From 5b96ffe188dedb6e72d6d6d26484722ef49ab5ae Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Mar 2021 17:39:59 +0000 Subject: [PATCH] update ls180.il 4ksram with correct sdram connections --- .../non_generated/full_core_4_4ksram_ls180.il | 215268 ++++++++------- 1 file changed, 109963 insertions(+), 105305 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il index 691400a..2bb27e0 100644 --- a/experiments9/non_generated/full_core_4_4ksram_ls180.il +++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il @@ -1,67 +1,67 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 14799 -attribute \src "libresoc.v:5.1-333.10" +autoidx 14913 +attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" attribute \generator "nMigen" module \ALU_dec19 - attribute \src "libresoc.v:282.3-291.6" + attribute \src "libresoc.v:284.3-293.6" wire width 3 $0\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:292.3-301.6" + attribute \src "libresoc.v:294.3-303.6" wire width 3 $0\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:322.3-331.6" + attribute \src "libresoc.v:324.3-333.6" wire width 2 $0\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:222.3-231.6" + attribute \src "libresoc.v:224.3-233.6" wire $0\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:192.3-201.6" - wire width 13 $0\ALU_dec19_function_unit[12:0] - attribute \src "libresoc.v:262.3-271.6" + attribute \src "libresoc.v:194.3-203.6" + wire width 14 $0\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:264.3-273.6" wire width 3 $0\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:272.3-281.6" + attribute \src "libresoc.v:274.3-283.6" wire width 4 $0\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:252.3-261.6" + attribute \src "libresoc.v:254.3-263.6" wire width 7 $0\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:202.3-211.6" + attribute \src "libresoc.v:204.3-213.6" wire $0\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:212.3-221.6" + attribute \src "libresoc.v:214.3-223.6" wire $0\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:232.3-241.6" + attribute \src "libresoc.v:234.3-243.6" wire $0\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:302.3-311.6" + attribute \src "libresoc.v:304.3-313.6" wire width 4 $0\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:312.3-321.6" + attribute \src "libresoc.v:314.3-323.6" wire width 2 $0\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:242.3-251.6" + attribute \src "libresoc.v:244.3-253.6" wire $0\ALU_dec19_sgn[0:0] attribute \src "libresoc.v:6.7-6.20" wire $0\initial[0:0] - attribute \src "libresoc.v:282.3-291.6" + attribute \src "libresoc.v:284.3-293.6" wire width 3 $1\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:292.3-301.6" + attribute \src "libresoc.v:294.3-303.6" wire width 3 $1\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:322.3-331.6" + attribute \src "libresoc.v:324.3-333.6" wire width 2 $1\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:222.3-231.6" + attribute \src "libresoc.v:224.3-233.6" wire $1\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:192.3-201.6" - wire width 13 $1\ALU_dec19_function_unit[12:0] - attribute \src "libresoc.v:262.3-271.6" + attribute \src "libresoc.v:194.3-203.6" + wire width 14 $1\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:264.3-273.6" wire width 3 $1\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:272.3-281.6" + attribute \src "libresoc.v:274.3-283.6" wire width 4 $1\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:252.3-261.6" + attribute \src "libresoc.v:254.3-263.6" wire width 7 $1\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:202.3-211.6" + attribute \src "libresoc.v:204.3-213.6" wire $1\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:212.3-221.6" + attribute \src "libresoc.v:214.3-223.6" wire $1\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:232.3-241.6" + attribute \src "libresoc.v:234.3-243.6" wire $1\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:302.3-311.6" + attribute \src "libresoc.v:304.3-313.6" wire width 4 $1\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:312.3-321.6" + attribute \src "libresoc.v:314.3-323.6" wire width 2 $1\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:242.3-251.6" + attribute \src "libresoc.v:244.3-253.6" wire $1\ALU_dec19_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -92,21 +92,22 @@ module \ALU_dec19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec19_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \ALU_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -206,6 +207,7 @@ module \ALU_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -236,14 +238,14 @@ module \ALU_dec19 wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:192.3-201.6" - process $proc$libresoc.v:192$1 + attribute \src "libresoc.v:194.3-203.6" + process $proc$libresoc.v:194$1 assign { } { } assign { } { } - assign $0\ALU_dec19_function_unit[12:0] $1\ALU_dec19_function_unit[12:0] - attribute \src "libresoc.v:193.5-193.29" + assign $0\ALU_dec19_function_unit[13:0] $1\ALU_dec19_function_unit[13:0] + attribute \src "libresoc.v:195.5-195.29" switch \initial - attribute \src "libresoc.v:193.9-193.17" + attribute \src "libresoc.v:195.9-195.17" case 1'1 case end @@ -252,21 +254,21 @@ module \ALU_dec19 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\ALU_dec19_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec19_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec19_function_unit[12:0] 13'0000000000000 + assign $1\ALU_dec19_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[12:0] + update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[13:0] end - attribute \src "libresoc.v:202.3-211.6" - process $proc$libresoc.v:202$2 + attribute \src "libresoc.v:204.3-213.6" + process $proc$libresoc.v:204$2 assign { } { } assign { } { } assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:203.5-203.29" + attribute \src "libresoc.v:205.5-205.29" switch \initial - attribute \src "libresoc.v:203.9-203.17" + attribute \src "libresoc.v:205.9-205.17" case 1'1 case end @@ -282,14 +284,14 @@ module \ALU_dec19 sync always update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] end - attribute \src "libresoc.v:212.3-221.6" - process $proc$libresoc.v:212$3 + attribute \src "libresoc.v:214.3-223.6" + process $proc$libresoc.v:214$3 assign { } { } assign { } { } assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:213.5-213.29" + attribute \src "libresoc.v:215.5-215.29" switch \initial - attribute \src "libresoc.v:213.9-213.17" + attribute \src "libresoc.v:215.9-215.17" case 1'1 case end @@ -305,14 +307,14 @@ module \ALU_dec19 sync always update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] end - attribute \src "libresoc.v:222.3-231.6" - process $proc$libresoc.v:222$4 + attribute \src "libresoc.v:224.3-233.6" + process $proc$libresoc.v:224$4 assign { } { } assign { } { } assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:223.5-223.29" + attribute \src "libresoc.v:225.5-225.29" switch \initial - attribute \src "libresoc.v:223.9-223.17" + attribute \src "libresoc.v:225.9-225.17" case 1'1 case end @@ -328,14 +330,14 @@ module \ALU_dec19 sync always update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] end - attribute \src "libresoc.v:232.3-241.6" - process $proc$libresoc.v:232$5 + attribute \src "libresoc.v:234.3-243.6" + process $proc$libresoc.v:234$5 assign { } { } assign { } { } assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:233.5-233.29" + attribute \src "libresoc.v:235.5-235.29" switch \initial - attribute \src "libresoc.v:233.9-233.17" + attribute \src "libresoc.v:235.9-235.17" case 1'1 case end @@ -351,14 +353,14 @@ module \ALU_dec19 sync always update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] end - attribute \src "libresoc.v:242.3-251.6" - process $proc$libresoc.v:242$6 + attribute \src "libresoc.v:244.3-253.6" + process $proc$libresoc.v:244$6 assign { } { } assign { } { } assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] - attribute \src "libresoc.v:243.5-243.29" + attribute \src "libresoc.v:245.5-245.29" switch \initial - attribute \src "libresoc.v:243.9-243.17" + attribute \src "libresoc.v:245.9-245.17" case 1'1 case end @@ -374,14 +376,14 @@ module \ALU_dec19 sync always update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] end - attribute \src "libresoc.v:252.3-261.6" - process $proc$libresoc.v:252$7 + attribute \src "libresoc.v:254.3-263.6" + process $proc$libresoc.v:254$7 assign { } { } assign { } { } assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:253.5-253.29" + attribute \src "libresoc.v:255.5-255.29" switch \initial - attribute \src "libresoc.v:253.9-253.17" + attribute \src "libresoc.v:255.9-255.17" case 1'1 case end @@ -397,14 +399,14 @@ module \ALU_dec19 sync always update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] end - attribute \src "libresoc.v:262.3-271.6" - process $proc$libresoc.v:262$8 + attribute \src "libresoc.v:264.3-273.6" + process $proc$libresoc.v:264$8 assign { } { } assign { } { } assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:263.5-263.29" + attribute \src "libresoc.v:265.5-265.29" switch \initial - attribute \src "libresoc.v:263.9-263.17" + attribute \src "libresoc.v:265.9-265.17" case 1'1 case end @@ -420,14 +422,14 @@ module \ALU_dec19 sync always update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] end - attribute \src "libresoc.v:272.3-281.6" - process $proc$libresoc.v:272$9 + attribute \src "libresoc.v:274.3-283.6" + process $proc$libresoc.v:274$9 assign { } { } assign { } { } assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:273.5-273.29" + attribute \src "libresoc.v:275.5-275.29" switch \initial - attribute \src "libresoc.v:273.9-273.17" + attribute \src "libresoc.v:275.9-275.17" case 1'1 case end @@ -443,14 +445,14 @@ module \ALU_dec19 sync always update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] end - attribute \src "libresoc.v:282.3-291.6" - process $proc$libresoc.v:282$10 + attribute \src "libresoc.v:284.3-293.6" + process $proc$libresoc.v:284$10 assign { } { } assign { } { } assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:283.5-283.29" + attribute \src "libresoc.v:285.5-285.29" switch \initial - attribute \src "libresoc.v:283.9-283.17" + attribute \src "libresoc.v:285.9-285.17" case 1'1 case end @@ -466,14 +468,14 @@ module \ALU_dec19 sync always update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] end - attribute \src "libresoc.v:292.3-301.6" - process $proc$libresoc.v:292$11 + attribute \src "libresoc.v:294.3-303.6" + process $proc$libresoc.v:294$11 assign { } { } assign { } { } assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:293.5-293.29" + attribute \src "libresoc.v:295.5-295.29" switch \initial - attribute \src "libresoc.v:293.9-293.17" + attribute \src "libresoc.v:295.9-295.17" case 1'1 case end @@ -489,14 +491,14 @@ module \ALU_dec19 sync always update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] end - attribute \src "libresoc.v:302.3-311.6" - process $proc$libresoc.v:302$12 + attribute \src "libresoc.v:304.3-313.6" + process $proc$libresoc.v:304$12 assign { } { } assign { } { } assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:303.5-303.29" + attribute \src "libresoc.v:305.5-305.29" switch \initial - attribute \src "libresoc.v:303.9-303.17" + attribute \src "libresoc.v:305.9-305.17" case 1'1 case end @@ -512,14 +514,14 @@ module \ALU_dec19 sync always update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] end - attribute \src "libresoc.v:312.3-321.6" - process $proc$libresoc.v:312$13 + attribute \src "libresoc.v:314.3-323.6" + process $proc$libresoc.v:314$13 assign { } { } assign { } { } assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:313.5-313.29" + attribute \src "libresoc.v:315.5-315.29" switch \initial - attribute \src "libresoc.v:313.9-313.17" + attribute \src "libresoc.v:315.9-315.17" case 1'1 case end @@ -535,14 +537,14 @@ module \ALU_dec19 sync always update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] end - attribute \src "libresoc.v:322.3-331.6" - process $proc$libresoc.v:322$14 + attribute \src "libresoc.v:324.3-333.6" + process $proc$libresoc.v:324$14 assign { } { } assign { } { } assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:323.5-323.29" + attribute \src "libresoc.v:325.5-325.29" switch \initial - attribute \src "libresoc.v:323.9-323.17" + attribute \src "libresoc.v:325.9-325.17" case 1'1 case end @@ -568,68 +570,68 @@ module \ALU_dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:337.1-1771.10" +attribute \src "libresoc.v:339.1-1785.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" attribute \generator "nMigen" module \ALU_dec31 - attribute \src "libresoc.v:1478.3-1499.6" + attribute \src "libresoc.v:1492.3-1513.6" wire width 3 $0\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1500.3-1521.6" + attribute \src "libresoc.v:1514.3-1535.6" wire width 3 $0\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1566.3-1587.6" + attribute \src "libresoc.v:1580.3-1601.6" wire width 2 $0\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1632.3-1653.6" + attribute \src "libresoc.v:1646.3-1667.6" wire $0\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1698.3-1719.6" - wire width 13 $0\ALU_dec31_function_unit[12:0] - attribute \src "libresoc.v:1742.3-1763.6" + attribute \src "libresoc.v:1712.3-1733.6" + wire width 14 $0\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1756.3-1777.6" wire width 3 $0\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1456.3-1477.6" + attribute \src "libresoc.v:1470.3-1491.6" wire width 4 $0\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1720.3-1741.6" + attribute \src "libresoc.v:1734.3-1755.6" wire width 7 $0\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1588.3-1609.6" + attribute \src "libresoc.v:1602.3-1623.6" wire $0\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1610.3-1631.6" + attribute \src "libresoc.v:1624.3-1645.6" wire $0\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1654.3-1675.6" + attribute \src "libresoc.v:1668.3-1689.6" wire $0\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1522.3-1543.6" + attribute \src "libresoc.v:1536.3-1557.6" wire width 4 $0\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1544.3-1565.6" + attribute \src "libresoc.v:1558.3-1579.6" wire width 2 $0\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1676.3-1697.6" + attribute \src "libresoc.v:1690.3-1711.6" wire $0\ALU_dec31_sgn[0:0] - attribute \src "libresoc.v:338.7-338.20" + attribute \src "libresoc.v:340.7-340.20" wire $0\initial[0:0] - attribute \src "libresoc.v:1478.3-1499.6" + attribute \src "libresoc.v:1492.3-1513.6" wire width 3 $1\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1500.3-1521.6" + attribute \src "libresoc.v:1514.3-1535.6" wire width 3 $1\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1566.3-1587.6" + attribute \src "libresoc.v:1580.3-1601.6" wire width 2 $1\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1632.3-1653.6" + attribute \src "libresoc.v:1646.3-1667.6" wire $1\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1698.3-1719.6" - wire width 13 $1\ALU_dec31_function_unit[12:0] - attribute \src "libresoc.v:1742.3-1763.6" + attribute \src "libresoc.v:1712.3-1733.6" + wire width 14 $1\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1756.3-1777.6" wire width 3 $1\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1456.3-1477.6" + attribute \src "libresoc.v:1470.3-1491.6" wire width 4 $1\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1720.3-1741.6" + attribute \src "libresoc.v:1734.3-1755.6" wire width 7 $1\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1588.3-1609.6" + attribute \src "libresoc.v:1602.3-1623.6" wire $1\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1610.3-1631.6" + attribute \src "libresoc.v:1624.3-1645.6" wire $1\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1654.3-1675.6" + attribute \src "libresoc.v:1668.3-1689.6" wire $1\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1522.3-1543.6" + attribute \src "libresoc.v:1536.3-1557.6" wire width 4 $1\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1544.3-1565.6" + attribute \src "libresoc.v:1558.3-1579.6" wire width 2 $1\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1676.3-1697.6" + attribute \src "libresoc.v:1690.3-1711.6" wire $1\ALU_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -688,21 +690,22 @@ module \ALU_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -802,6 +805,7 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -857,21 +861,22 @@ module \ALU_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -971,6 +976,7 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -1026,21 +1032,22 @@ module \ALU_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -1140,6 +1147,7 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -1195,21 +1203,22 @@ module \ALU_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -1309,6 +1318,7 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -1364,21 +1374,22 @@ module \ALU_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -1478,6 +1489,7 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -1505,21 +1517,22 @@ module \ALU_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec31_dec_sub8_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \ALU_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -1619,6 +1632,7 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -1643,7 +1657,7 @@ module \ALU_dec31 wire width 2 output 8 \ALU_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_sgn - attribute \src "libresoc.v:338.7-338.15" + attribute \src "libresoc.v:340.7-340.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -1652,7 +1666,7 @@ module \ALU_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:1371.22-1387.4" + attribute \src "libresoc.v:1385.22-1401.4" cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out @@ -1671,7 +1685,7 @@ module \ALU_dec31 connect \opcode_in \ALU_dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:1388.23-1404.4" + attribute \src "libresoc.v:1402.23-1418.4" cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out @@ -1690,7 +1704,7 @@ module \ALU_dec31 connect \opcode_in \ALU_dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:1405.23-1421.4" + attribute \src "libresoc.v:1419.23-1435.4" cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out @@ -1709,7 +1723,7 @@ module \ALU_dec31 connect \opcode_in \ALU_dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:1422.23-1438.4" + attribute \src "libresoc.v:1436.23-1452.4" cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out @@ -1728,7 +1742,7 @@ module \ALU_dec31 connect \opcode_in \ALU_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:1439.22-1455.4" + attribute \src "libresoc.v:1453.22-1469.4" cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out @@ -1746,14 +1760,14 @@ module \ALU_dec31 connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn connect \opcode_in \ALU_dec31_dec_sub8_opcode_in end - attribute \src "libresoc.v:1456.3-1477.6" - process $proc$libresoc.v:1456$16 + attribute \src "libresoc.v:1470.3-1491.6" + process $proc$libresoc.v:1470$16 assign { } { } assign { } { } assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1457.5-1457.29" + attribute \src "libresoc.v:1471.5-1471.29" switch \initial - attribute \src "libresoc.v:1457.9-1457.17" + attribute \src "libresoc.v:1471.9-1471.17" case 1'1 case end @@ -1785,14 +1799,14 @@ module \ALU_dec31 sync always update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:1478.3-1499.6" - process $proc$libresoc.v:1478$17 + attribute \src "libresoc.v:1492.3-1513.6" + process $proc$libresoc.v:1492$17 assign { } { } assign { } { } assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1479.5-1479.29" + attribute \src "libresoc.v:1493.5-1493.29" switch \initial - attribute \src "libresoc.v:1479.9-1479.17" + attribute \src "libresoc.v:1493.9-1493.17" case 1'1 case end @@ -1824,14 +1838,14 @@ module \ALU_dec31 sync always update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] end - attribute \src "libresoc.v:1500.3-1521.6" - process $proc$libresoc.v:1500$18 + attribute \src "libresoc.v:1514.3-1535.6" + process $proc$libresoc.v:1514$18 assign { } { } assign { } { } assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1501.5-1501.29" + attribute \src "libresoc.v:1515.5-1515.29" switch \initial - attribute \src "libresoc.v:1501.9-1501.17" + attribute \src "libresoc.v:1515.9-1515.17" case 1'1 case end @@ -1863,14 +1877,14 @@ module \ALU_dec31 sync always update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] end - attribute \src "libresoc.v:1522.3-1543.6" - process $proc$libresoc.v:1522$19 + attribute \src "libresoc.v:1536.3-1557.6" + process $proc$libresoc.v:1536$19 assign { } { } assign { } { } assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1523.5-1523.29" + attribute \src "libresoc.v:1537.5-1537.29" switch \initial - attribute \src "libresoc.v:1523.9-1523.17" + attribute \src "libresoc.v:1537.9-1537.17" case 1'1 case end @@ -1902,14 +1916,14 @@ module \ALU_dec31 sync always update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] end - attribute \src "libresoc.v:1544.3-1565.6" - process $proc$libresoc.v:1544$20 + attribute \src "libresoc.v:1558.3-1579.6" + process $proc$libresoc.v:1558$20 assign { } { } assign { } { } assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1545.5-1545.29" + attribute \src "libresoc.v:1559.5-1559.29" switch \initial - attribute \src "libresoc.v:1545.9-1545.17" + attribute \src "libresoc.v:1559.9-1559.17" case 1'1 case end @@ -1941,14 +1955,14 @@ module \ALU_dec31 sync always update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:1566.3-1587.6" - process $proc$libresoc.v:1566$21 + attribute \src "libresoc.v:1580.3-1601.6" + process $proc$libresoc.v:1580$21 assign { } { } assign { } { } assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1567.5-1567.29" + attribute \src "libresoc.v:1581.5-1581.29" switch \initial - attribute \src "libresoc.v:1567.9-1567.17" + attribute \src "libresoc.v:1581.9-1581.17" case 1'1 case end @@ -1980,14 +1994,14 @@ module \ALU_dec31 sync always update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] end - attribute \src "libresoc.v:1588.3-1609.6" - process $proc$libresoc.v:1588$22 + attribute \src "libresoc.v:1602.3-1623.6" + process $proc$libresoc.v:1602$22 assign { } { } assign { } { } assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1589.5-1589.29" + attribute \src "libresoc.v:1603.5-1603.29" switch \initial - attribute \src "libresoc.v:1589.9-1589.17" + attribute \src "libresoc.v:1603.9-1603.17" case 1'1 case end @@ -2019,14 +2033,14 @@ module \ALU_dec31 sync always update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] end - attribute \src "libresoc.v:1610.3-1631.6" - process $proc$libresoc.v:1610$23 + attribute \src "libresoc.v:1624.3-1645.6" + process $proc$libresoc.v:1624$23 assign { } { } assign { } { } assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1611.5-1611.29" + attribute \src "libresoc.v:1625.5-1625.29" switch \initial - attribute \src "libresoc.v:1611.9-1611.17" + attribute \src "libresoc.v:1625.9-1625.17" case 1'1 case end @@ -2058,14 +2072,14 @@ module \ALU_dec31 sync always update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] end - attribute \src "libresoc.v:1632.3-1653.6" - process $proc$libresoc.v:1632$24 + attribute \src "libresoc.v:1646.3-1667.6" + process $proc$libresoc.v:1646$24 assign { } { } assign { } { } assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1633.5-1633.29" + attribute \src "libresoc.v:1647.5-1647.29" switch \initial - attribute \src "libresoc.v:1633.9-1633.17" + attribute \src "libresoc.v:1647.9-1647.17" case 1'1 case end @@ -2097,14 +2111,14 @@ module \ALU_dec31 sync always update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] end - attribute \src "libresoc.v:1654.3-1675.6" - process $proc$libresoc.v:1654$25 + attribute \src "libresoc.v:1668.3-1689.6" + process $proc$libresoc.v:1668$25 assign { } { } assign { } { } assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1655.5-1655.29" + attribute \src "libresoc.v:1669.5-1669.29" switch \initial - attribute \src "libresoc.v:1655.9-1655.17" + attribute \src "libresoc.v:1669.9-1669.17" case 1'1 case end @@ -2136,14 +2150,14 @@ module \ALU_dec31 sync always update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] end - attribute \src "libresoc.v:1676.3-1697.6" - process $proc$libresoc.v:1676$26 + attribute \src "libresoc.v:1690.3-1711.6" + process $proc$libresoc.v:1690$26 assign { } { } assign { } { } assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] - attribute \src "libresoc.v:1677.5-1677.29" + attribute \src "libresoc.v:1691.5-1691.29" switch \initial - attribute \src "libresoc.v:1677.9-1677.17" + attribute \src "libresoc.v:1691.9-1691.17" case 1'1 case end @@ -2175,14 +2189,14 @@ module \ALU_dec31 sync always update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] end - attribute \src "libresoc.v:1698.3-1719.6" - process $proc$libresoc.v:1698$27 + attribute \src "libresoc.v:1712.3-1733.6" + process $proc$libresoc.v:1712$27 assign { } { } assign { } { } - assign $0\ALU_dec31_function_unit[12:0] $1\ALU_dec31_function_unit[12:0] - attribute \src "libresoc.v:1699.5-1699.29" + assign $0\ALU_dec31_function_unit[13:0] $1\ALU_dec31_function_unit[13:0] + attribute \src "libresoc.v:1713.5-1713.29" switch \initial - attribute \src "libresoc.v:1699.9-1699.17" + attribute \src "libresoc.v:1713.9-1713.17" case 1'1 case end @@ -2191,37 +2205,37 @@ module \ALU_dec31 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit case - assign $1\ALU_dec31_function_unit[12:0] 13'0000000000000 + assign $1\ALU_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[12:0] + update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[13:0] end - attribute \src "libresoc.v:1720.3-1741.6" - process $proc$libresoc.v:1720$28 + attribute \src "libresoc.v:1734.3-1755.6" + process $proc$libresoc.v:1734$28 assign { } { } assign { } { } assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1721.5-1721.29" + attribute \src "libresoc.v:1735.5-1735.29" switch \initial - attribute \src "libresoc.v:1721.9-1721.17" + attribute \src "libresoc.v:1735.9-1735.17" case 1'1 case end @@ -2253,14 +2267,14 @@ module \ALU_dec31 sync always update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] end - attribute \src "libresoc.v:1742.3-1763.6" - process $proc$libresoc.v:1742$29 + attribute \src "libresoc.v:1756.3-1777.6" + process $proc$libresoc.v:1756$29 assign { } { } assign { } { } assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1743.5-1743.29" + attribute \src "libresoc.v:1757.5-1757.29" switch \initial - attribute \src "libresoc.v:1743.9-1743.17" + attribute \src "libresoc.v:1757.9-1757.17" case 1'1 case end @@ -2292,8 +2306,8 @@ module \ALU_dec31 sync always update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] end - attribute \src "libresoc.v:338.7-338.20" - process $proc$libresoc.v:338$30 + attribute \src "libresoc.v:340.7-340.20" + process $proc$libresoc.v:340$30 assign { } { } assign $0\initial[0:0] 1'0 sync always @@ -2308,68 +2322,68 @@ module \ALU_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:1775.1-2187.10" +attribute \src "libresoc.v:1789.1-2203.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" attribute \generator "nMigen" module \ALU_dec31_dec_sub0 - attribute \src "libresoc.v:2106.3-2121.6" - wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:2122.3-2137.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2138.3-2153.6" wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2170.3-2185.6" + attribute \src "libresoc.v:2186.3-2201.6" wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:2010.3-2025.6" + attribute \src "libresoc.v:2026.3-2041.6" wire $0\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:1962.3-1977.6" - wire width 13 $0\ALU_dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:2074.3-2089.6" - wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:1978.3-1993.6" + wire width 14 $0\ALU_dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:2090.3-2105.6" + wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2106.3-2121.6" wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2058.3-2073.6" + attribute \src "libresoc.v:2074.3-2089.6" wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:1978.3-1993.6" - wire $0\ALU_dec31_dec_sub0_inv_a[0:0] attribute \src "libresoc.v:1994.3-2009.6" + wire $0\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:2010.3-2025.6" wire $0\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:2026.3-2041.6" + attribute \src "libresoc.v:2042.3-2057.6" wire $0\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2138.3-2153.6" - wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] attribute \src "libresoc.v:2154.3-2169.6" + wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2170.3-2185.6" wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2042.3-2057.6" + attribute \src "libresoc.v:2058.3-2073.6" wire $0\ALU_dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:1776.7-1776.20" + attribute \src "libresoc.v:1790.7-1790.20" wire $0\initial[0:0] - attribute \src "libresoc.v:2106.3-2121.6" - wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:2122.3-2137.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2138.3-2153.6" wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2170.3-2185.6" + attribute \src "libresoc.v:2186.3-2201.6" wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:2010.3-2025.6" + attribute \src "libresoc.v:2026.3-2041.6" wire $1\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:1962.3-1977.6" - wire width 13 $1\ALU_dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:2074.3-2089.6" - wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:1978.3-1993.6" + wire width 14 $1\ALU_dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:2090.3-2105.6" + wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2106.3-2121.6" wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2058.3-2073.6" + attribute \src "libresoc.v:2074.3-2089.6" wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:1978.3-1993.6" - wire $1\ALU_dec31_dec_sub0_inv_a[0:0] attribute \src "libresoc.v:1994.3-2009.6" + wire $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:2010.3-2025.6" wire $1\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:2026.3-2041.6" + attribute \src "libresoc.v:2042.3-2057.6" wire $1\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2138.3-2153.6" - wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] attribute \src "libresoc.v:2154.3-2169.6" + wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2170.3-2185.6" wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2042.3-2057.6" + attribute \src "libresoc.v:2058.3-2073.6" wire $1\ALU_dec31_dec_sub0_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -2400,21 +2414,22 @@ module \ALU_dec31_dec_sub0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \ALU_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -2514,6 +2529,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -2538,28 +2554,28 @@ module \ALU_dec31_dec_sub0 wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub0_sgn - attribute \src "libresoc.v:1776.7-1776.15" + attribute \src "libresoc.v:1790.7-1790.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:1776.7-1776.20" - process $proc$libresoc.v:1776$45 + attribute \src "libresoc.v:1790.7-1790.20" + process $proc$libresoc.v:1790$45 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:1962.3-1977.6" - process $proc$libresoc.v:1962$31 + attribute \src "libresoc.v:1978.3-1993.6" + process $proc$libresoc.v:1978$31 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_function_unit[12:0] $1\ALU_dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:1963.5-1963.29" + assign $0\ALU_dec31_dec_sub0_function_unit[13:0] $1\ALU_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:1979.5-1979.29" switch \initial - attribute \src "libresoc.v:1963.9-1963.17" + attribute \src "libresoc.v:1979.9-1979.17" case 1'1 case end @@ -2568,29 +2584,29 @@ module \ALU_dec31_dec_sub0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub0_function_unit[12:0] 13'0000000000000 + assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[12:0] + update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:1978.3-1993.6" - process $proc$libresoc.v:1978$32 + attribute \src "libresoc.v:1994.3-2009.6" + process $proc$libresoc.v:1994$32 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:1979.5-1979.29" + attribute \src "libresoc.v:1995.5-1995.29" switch \initial - attribute \src "libresoc.v:1979.9-1979.17" + attribute \src "libresoc.v:1995.9-1995.17" case 1'1 case end @@ -2614,14 +2630,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:1994.3-2009.6" - process $proc$libresoc.v:1994$33 + attribute \src "libresoc.v:2010.3-2025.6" + process $proc$libresoc.v:2010$33 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:1995.5-1995.29" + attribute \src "libresoc.v:2011.5-2011.29" switch \initial - attribute \src "libresoc.v:1995.9-1995.17" + attribute \src "libresoc.v:2011.9-2011.17" case 1'1 case end @@ -2645,14 +2661,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:2010.3-2025.6" - process $proc$libresoc.v:2010$34 + attribute \src "libresoc.v:2026.3-2041.6" + process $proc$libresoc.v:2026$34 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:2011.5-2011.29" + attribute \src "libresoc.v:2027.5-2027.29" switch \initial - attribute \src "libresoc.v:2011.9-2011.17" + attribute \src "libresoc.v:2027.9-2027.17" case 1'1 case end @@ -2676,14 +2692,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:2026.3-2041.6" - process $proc$libresoc.v:2026$35 + attribute \src "libresoc.v:2042.3-2057.6" + process $proc$libresoc.v:2042$35 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2027.5-2027.29" + attribute \src "libresoc.v:2043.5-2043.29" switch \initial - attribute \src "libresoc.v:2027.9-2027.17" + attribute \src "libresoc.v:2043.9-2043.17" case 1'1 case end @@ -2707,14 +2723,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:2042.3-2057.6" - process $proc$libresoc.v:2042$36 + attribute \src "libresoc.v:2058.3-2073.6" + process $proc$libresoc.v:2058$36 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:2043.5-2043.29" + attribute \src "libresoc.v:2059.5-2059.29" switch \initial - attribute \src "libresoc.v:2043.9-2043.17" + attribute \src "libresoc.v:2059.9-2059.17" case 1'1 case end @@ -2738,14 +2754,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:2058.3-2073.6" - process $proc$libresoc.v:2058$37 + attribute \src "libresoc.v:2074.3-2089.6" + process $proc$libresoc.v:2074$37 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:2059.5-2059.29" + attribute \src "libresoc.v:2075.5-2075.29" switch \initial - attribute \src "libresoc.v:2059.9-2059.17" + attribute \src "libresoc.v:2075.9-2075.17" case 1'1 case end @@ -2769,14 +2785,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:2074.3-2089.6" - process $proc$libresoc.v:2074$38 + attribute \src "libresoc.v:2090.3-2105.6" + process $proc$libresoc.v:2090$38 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:2075.5-2075.29" + attribute \src "libresoc.v:2091.5-2091.29" switch \initial - attribute \src "libresoc.v:2075.9-2075.17" + attribute \src "libresoc.v:2091.9-2091.17" case 1'1 case end @@ -2800,14 +2816,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:2090.3-2105.6" - process $proc$libresoc.v:2090$39 + attribute \src "libresoc.v:2106.3-2121.6" + process $proc$libresoc.v:2106$39 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2091.5-2091.29" + attribute \src "libresoc.v:2107.5-2107.29" switch \initial - attribute \src "libresoc.v:2091.9-2091.17" + attribute \src "libresoc.v:2107.9-2107.17" case 1'1 case end @@ -2831,14 +2847,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:2106.3-2121.6" - process $proc$libresoc.v:2106$40 + attribute \src "libresoc.v:2122.3-2137.6" + process $proc$libresoc.v:2122$40 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:2107.5-2107.29" + attribute \src "libresoc.v:2123.5-2123.29" switch \initial - attribute \src "libresoc.v:2107.9-2107.17" + attribute \src "libresoc.v:2123.9-2123.17" case 1'1 case end @@ -2862,14 +2878,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:2122.3-2137.6" - process $proc$libresoc.v:2122$41 + attribute \src "libresoc.v:2138.3-2153.6" + process $proc$libresoc.v:2138$41 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2123.5-2123.29" + attribute \src "libresoc.v:2139.5-2139.29" switch \initial - attribute \src "libresoc.v:2123.9-2123.17" + attribute \src "libresoc.v:2139.9-2139.17" case 1'1 case end @@ -2893,14 +2909,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:2138.3-2153.6" - process $proc$libresoc.v:2138$42 + attribute \src "libresoc.v:2154.3-2169.6" + process $proc$libresoc.v:2154$42 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:2139.5-2139.29" + attribute \src "libresoc.v:2155.5-2155.29" switch \initial - attribute \src "libresoc.v:2139.9-2139.17" + attribute \src "libresoc.v:2155.9-2155.17" case 1'1 case end @@ -2924,14 +2940,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:2154.3-2169.6" - process $proc$libresoc.v:2154$43 + attribute \src "libresoc.v:2170.3-2185.6" + process $proc$libresoc.v:2170$43 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2155.5-2155.29" + attribute \src "libresoc.v:2171.5-2171.29" switch \initial - attribute \src "libresoc.v:2155.9-2155.17" + attribute \src "libresoc.v:2171.9-2171.17" case 1'1 case end @@ -2955,14 +2971,14 @@ module \ALU_dec31_dec_sub0 sync always update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:2170.3-2185.6" - process $proc$libresoc.v:2170$44 + attribute \src "libresoc.v:2186.3-2201.6" + process $proc$libresoc.v:2186$44 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:2171.5-2171.29" + attribute \src "libresoc.v:2187.5-2187.29" switch \initial - attribute \src "libresoc.v:2171.9-2171.17" + attribute \src "libresoc.v:2187.9-2187.17" case 1'1 case end @@ -2988,68 +3004,68 @@ module \ALU_dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:2191.1-2897.10" +attribute \src "libresoc.v:2207.1-2915.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" attribute \generator "nMigen" module \ALU_dec31_dec_sub10 - attribute \src "libresoc.v:2711.3-2747.6" + attribute \src "libresoc.v:2729.3-2765.6" wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2748.3-2784.6" + attribute \src "libresoc.v:2766.3-2802.6" wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2859.3-2895.6" + attribute \src "libresoc.v:2877.3-2913.6" wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2489.3-2525.6" + attribute \src "libresoc.v:2507.3-2543.6" wire $0\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2378.3-2414.6" - wire width 13 $0\ALU_dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:2637.3-2673.6" + attribute \src "libresoc.v:2396.3-2432.6" + wire width 14 $0\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2655.3-2691.6" wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2674.3-2710.6" + attribute \src "libresoc.v:2692.3-2728.6" wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2600.3-2636.6" + attribute \src "libresoc.v:2618.3-2654.6" wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2415.3-2451.6" + attribute \src "libresoc.v:2433.3-2469.6" wire $0\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2452.3-2488.6" + attribute \src "libresoc.v:2470.3-2506.6" wire $0\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2526.3-2562.6" + attribute \src "libresoc.v:2544.3-2580.6" wire $0\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2785.3-2821.6" + attribute \src "libresoc.v:2803.3-2839.6" wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2822.3-2858.6" + attribute \src "libresoc.v:2840.3-2876.6" wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2563.3-2599.6" + attribute \src "libresoc.v:2581.3-2617.6" wire $0\ALU_dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:2192.7-2192.20" + attribute \src "libresoc.v:2208.7-2208.20" wire $0\initial[0:0] - attribute \src "libresoc.v:2711.3-2747.6" + attribute \src "libresoc.v:2729.3-2765.6" wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2748.3-2784.6" + attribute \src "libresoc.v:2766.3-2802.6" wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2859.3-2895.6" + attribute \src "libresoc.v:2877.3-2913.6" wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2489.3-2525.6" + attribute \src "libresoc.v:2507.3-2543.6" wire $1\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2378.3-2414.6" - wire width 13 $1\ALU_dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:2637.3-2673.6" + attribute \src "libresoc.v:2396.3-2432.6" + wire width 14 $1\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2655.3-2691.6" wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2674.3-2710.6" + attribute \src "libresoc.v:2692.3-2728.6" wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2600.3-2636.6" + attribute \src "libresoc.v:2618.3-2654.6" wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2415.3-2451.6" + attribute \src "libresoc.v:2433.3-2469.6" wire $1\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2452.3-2488.6" + attribute \src "libresoc.v:2470.3-2506.6" wire $1\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2526.3-2562.6" + attribute \src "libresoc.v:2544.3-2580.6" wire $1\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2785.3-2821.6" + attribute \src "libresoc.v:2803.3-2839.6" wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2822.3-2858.6" + attribute \src "libresoc.v:2840.3-2876.6" wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2563.3-2599.6" + attribute \src "libresoc.v:2581.3-2617.6" wire $1\ALU_dec31_dec_sub10_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -3080,21 +3096,22 @@ module \ALU_dec31_dec_sub10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \ALU_dec31_dec_sub10_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -3194,6 +3211,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -3218,28 +3236,28 @@ module \ALU_dec31_dec_sub10 wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub10_sgn - attribute \src "libresoc.v:2192.7-2192.15" + attribute \src "libresoc.v:2208.7-2208.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:2192.7-2192.20" - process $proc$libresoc.v:2192$60 + attribute \src "libresoc.v:2208.7-2208.20" + process $proc$libresoc.v:2208$60 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:2378.3-2414.6" - process $proc$libresoc.v:2378$46 + attribute \src "libresoc.v:2396.3-2432.6" + process $proc$libresoc.v:2396$46 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub10_function_unit[12:0] $1\ALU_dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:2379.5-2379.29" + assign $0\ALU_dec31_dec_sub10_function_unit[13:0] $1\ALU_dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:2397.5-2397.29" switch \initial - attribute \src "libresoc.v:2379.9-2379.17" + attribute \src "libresoc.v:2397.9-2397.17" case 1'1 case end @@ -3248,57 +3266,57 @@ module \ALU_dec31_dec_sub10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000000 + assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[12:0] + update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:2415.3-2451.6" - process $proc$libresoc.v:2415$47 + attribute \src "libresoc.v:2433.3-2469.6" + process $proc$libresoc.v:2433$47 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2416.5-2416.29" + attribute \src "libresoc.v:2434.5-2434.29" switch \initial - attribute \src "libresoc.v:2416.9-2416.17" + attribute \src "libresoc.v:2434.9-2434.17" case 1'1 case end @@ -3350,14 +3368,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:2452.3-2488.6" - process $proc$libresoc.v:2452$48 + attribute \src "libresoc.v:2470.3-2506.6" + process $proc$libresoc.v:2470$48 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2453.5-2453.29" + attribute \src "libresoc.v:2471.5-2471.29" switch \initial - attribute \src "libresoc.v:2453.9-2453.17" + attribute \src "libresoc.v:2471.9-2471.17" case 1'1 case end @@ -3409,14 +3427,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:2489.3-2525.6" - process $proc$libresoc.v:2489$49 + attribute \src "libresoc.v:2507.3-2543.6" + process $proc$libresoc.v:2507$49 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2490.5-2490.29" + attribute \src "libresoc.v:2508.5-2508.29" switch \initial - attribute \src "libresoc.v:2490.9-2490.17" + attribute \src "libresoc.v:2508.9-2508.17" case 1'1 case end @@ -3468,14 +3486,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:2526.3-2562.6" - process $proc$libresoc.v:2526$50 + attribute \src "libresoc.v:2544.3-2580.6" + process $proc$libresoc.v:2544$50 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2527.5-2527.29" + attribute \src "libresoc.v:2545.5-2545.29" switch \initial - attribute \src "libresoc.v:2527.9-2527.17" + attribute \src "libresoc.v:2545.9-2545.17" case 1'1 case end @@ -3527,14 +3545,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:2563.3-2599.6" - process $proc$libresoc.v:2563$51 + attribute \src "libresoc.v:2581.3-2617.6" + process $proc$libresoc.v:2581$51 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:2564.5-2564.29" + attribute \src "libresoc.v:2582.5-2582.29" switch \initial - attribute \src "libresoc.v:2564.9-2564.17" + attribute \src "libresoc.v:2582.9-2582.17" case 1'1 case end @@ -3586,14 +3604,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:2600.3-2636.6" - process $proc$libresoc.v:2600$52 + attribute \src "libresoc.v:2618.3-2654.6" + process $proc$libresoc.v:2618$52 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2601.5-2601.29" + attribute \src "libresoc.v:2619.5-2619.29" switch \initial - attribute \src "libresoc.v:2601.9-2601.17" + attribute \src "libresoc.v:2619.9-2619.17" case 1'1 case end @@ -3645,14 +3663,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:2637.3-2673.6" - process $proc$libresoc.v:2637$53 + attribute \src "libresoc.v:2655.3-2691.6" + process $proc$libresoc.v:2655$53 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2638.5-2638.29" + attribute \src "libresoc.v:2656.5-2656.29" switch \initial - attribute \src "libresoc.v:2638.9-2638.17" + attribute \src "libresoc.v:2656.9-2656.17" case 1'1 case end @@ -3704,14 +3722,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:2674.3-2710.6" - process $proc$libresoc.v:2674$54 + attribute \src "libresoc.v:2692.3-2728.6" + process $proc$libresoc.v:2692$54 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2675.5-2675.29" + attribute \src "libresoc.v:2693.5-2693.29" switch \initial - attribute \src "libresoc.v:2675.9-2675.17" + attribute \src "libresoc.v:2693.9-2693.17" case 1'1 case end @@ -3763,14 +3781,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:2711.3-2747.6" - process $proc$libresoc.v:2711$55 + attribute \src "libresoc.v:2729.3-2765.6" + process $proc$libresoc.v:2729$55 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2712.5-2712.29" + attribute \src "libresoc.v:2730.5-2730.29" switch \initial - attribute \src "libresoc.v:2712.9-2712.17" + attribute \src "libresoc.v:2730.9-2730.17" case 1'1 case end @@ -3822,14 +3840,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:2748.3-2784.6" - process $proc$libresoc.v:2748$56 + attribute \src "libresoc.v:2766.3-2802.6" + process $proc$libresoc.v:2766$56 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2749.5-2749.29" + attribute \src "libresoc.v:2767.5-2767.29" switch \initial - attribute \src "libresoc.v:2749.9-2749.17" + attribute \src "libresoc.v:2767.9-2767.17" case 1'1 case end @@ -3881,14 +3899,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:2785.3-2821.6" - process $proc$libresoc.v:2785$57 + attribute \src "libresoc.v:2803.3-2839.6" + process $proc$libresoc.v:2803$57 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2786.5-2786.29" + attribute \src "libresoc.v:2804.5-2804.29" switch \initial - attribute \src "libresoc.v:2786.9-2786.17" + attribute \src "libresoc.v:2804.9-2804.17" case 1'1 case end @@ -3940,14 +3958,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:2822.3-2858.6" - process $proc$libresoc.v:2822$58 + attribute \src "libresoc.v:2840.3-2876.6" + process $proc$libresoc.v:2840$58 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2823.5-2823.29" + attribute \src "libresoc.v:2841.5-2841.29" switch \initial - attribute \src "libresoc.v:2823.9-2823.17" + attribute \src "libresoc.v:2841.9-2841.17" case 1'1 case end @@ -3999,14 +4017,14 @@ module \ALU_dec31_dec_sub10 sync always update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:2859.3-2895.6" - process $proc$libresoc.v:2859$59 + attribute \src "libresoc.v:2877.3-2913.6" + process $proc$libresoc.v:2877$59 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2860.5-2860.29" + attribute \src "libresoc.v:2878.5-2878.29" switch \initial - attribute \src "libresoc.v:2860.9-2860.17" + attribute \src "libresoc.v:2878.9-2878.17" case 1'1 case end @@ -4060,68 +4078,68 @@ module \ALU_dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:2901.1-3481.10" +attribute \src "libresoc.v:2919.1-3501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" attribute \generator "nMigen" module \ALU_dec31_dec_sub22 - attribute \src "libresoc.v:3340.3-3367.6" + attribute \src "libresoc.v:3360.3-3387.6" wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3368.3-3395.6" + attribute \src "libresoc.v:3388.3-3415.6" wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3452.3-3479.6" + attribute \src "libresoc.v:3472.3-3499.6" wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3172.3-3199.6" + attribute \src "libresoc.v:3192.3-3219.6" wire $0\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3088.3-3115.6" - wire width 13 $0\ALU_dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:3284.3-3311.6" + attribute \src "libresoc.v:3108.3-3135.6" + wire width 14 $0\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3304.3-3331.6" wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3312.3-3339.6" + attribute \src "libresoc.v:3332.3-3359.6" wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3256.3-3283.6" + attribute \src "libresoc.v:3276.3-3303.6" wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3116.3-3143.6" + attribute \src "libresoc.v:3136.3-3163.6" wire $0\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3144.3-3171.6" + attribute \src "libresoc.v:3164.3-3191.6" wire $0\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3200.3-3227.6" + attribute \src "libresoc.v:3220.3-3247.6" wire $0\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3396.3-3423.6" + attribute \src "libresoc.v:3416.3-3443.6" wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3424.3-3451.6" + attribute \src "libresoc.v:3444.3-3471.6" wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3228.3-3255.6" + attribute \src "libresoc.v:3248.3-3275.6" wire $0\ALU_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:2902.7-2902.20" + attribute \src "libresoc.v:2920.7-2920.20" wire $0\initial[0:0] - attribute \src "libresoc.v:3340.3-3367.6" + attribute \src "libresoc.v:3360.3-3387.6" wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3368.3-3395.6" + attribute \src "libresoc.v:3388.3-3415.6" wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3452.3-3479.6" + attribute \src "libresoc.v:3472.3-3499.6" wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3172.3-3199.6" + attribute \src "libresoc.v:3192.3-3219.6" wire $1\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3088.3-3115.6" - wire width 13 $1\ALU_dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:3284.3-3311.6" + attribute \src "libresoc.v:3108.3-3135.6" + wire width 14 $1\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3304.3-3331.6" wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3312.3-3339.6" + attribute \src "libresoc.v:3332.3-3359.6" wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3256.3-3283.6" + attribute \src "libresoc.v:3276.3-3303.6" wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3116.3-3143.6" + attribute \src "libresoc.v:3136.3-3163.6" wire $1\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3144.3-3171.6" + attribute \src "libresoc.v:3164.3-3191.6" wire $1\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3200.3-3227.6" + attribute \src "libresoc.v:3220.3-3247.6" wire $1\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3396.3-3423.6" + attribute \src "libresoc.v:3416.3-3443.6" wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3424.3-3451.6" + attribute \src "libresoc.v:3444.3-3471.6" wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3228.3-3255.6" + attribute \src "libresoc.v:3248.3-3275.6" wire $1\ALU_dec31_dec_sub22_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -4152,21 +4170,22 @@ module \ALU_dec31_dec_sub22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \ALU_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -4266,6 +4285,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -4290,28 +4310,28 @@ module \ALU_dec31_dec_sub22 wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub22_sgn - attribute \src "libresoc.v:2902.7-2902.15" + attribute \src "libresoc.v:2920.7-2920.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:2902.7-2902.20" - process $proc$libresoc.v:2902$75 + attribute \src "libresoc.v:2920.7-2920.20" + process $proc$libresoc.v:2920$75 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:3088.3-3115.6" - process $proc$libresoc.v:3088$61 + attribute \src "libresoc.v:3108.3-3135.6" + process $proc$libresoc.v:3108$61 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub22_function_unit[12:0] $1\ALU_dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:3089.5-3089.29" + assign $0\ALU_dec31_dec_sub22_function_unit[13:0] $1\ALU_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:3109.5-3109.29" switch \initial - attribute \src "libresoc.v:3089.9-3089.17" + attribute \src "libresoc.v:3109.9-3109.17" case 1'1 case end @@ -4320,45 +4340,45 @@ module \ALU_dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000000 + assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[12:0] + update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:3116.3-3143.6" - process $proc$libresoc.v:3116$62 + attribute \src "libresoc.v:3136.3-3163.6" + process $proc$libresoc.v:3136$62 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3117.5-3117.29" + attribute \src "libresoc.v:3137.5-3137.29" switch \initial - attribute \src "libresoc.v:3117.9-3117.17" + attribute \src "libresoc.v:3137.9-3137.17" case 1'1 case end @@ -4398,14 +4418,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:3144.3-3171.6" - process $proc$libresoc.v:3144$63 + attribute \src "libresoc.v:3164.3-3191.6" + process $proc$libresoc.v:3164$63 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3145.5-3145.29" + attribute \src "libresoc.v:3165.5-3165.29" switch \initial - attribute \src "libresoc.v:3145.9-3145.17" + attribute \src "libresoc.v:3165.9-3165.17" case 1'1 case end @@ -4445,14 +4465,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:3172.3-3199.6" - process $proc$libresoc.v:3172$64 + attribute \src "libresoc.v:3192.3-3219.6" + process $proc$libresoc.v:3192$64 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3173.5-3173.29" + attribute \src "libresoc.v:3193.5-3193.29" switch \initial - attribute \src "libresoc.v:3173.9-3173.17" + attribute \src "libresoc.v:3193.9-3193.17" case 1'1 case end @@ -4492,14 +4512,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:3200.3-3227.6" - process $proc$libresoc.v:3200$65 + attribute \src "libresoc.v:3220.3-3247.6" + process $proc$libresoc.v:3220$65 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3201.5-3201.29" + attribute \src "libresoc.v:3221.5-3221.29" switch \initial - attribute \src "libresoc.v:3201.9-3201.17" + attribute \src "libresoc.v:3221.9-3221.17" case 1'1 case end @@ -4539,14 +4559,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:3228.3-3255.6" - process $proc$libresoc.v:3228$66 + attribute \src "libresoc.v:3248.3-3275.6" + process $proc$libresoc.v:3248$66 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:3229.5-3229.29" + attribute \src "libresoc.v:3249.5-3249.29" switch \initial - attribute \src "libresoc.v:3229.9-3229.17" + attribute \src "libresoc.v:3249.9-3249.17" case 1'1 case end @@ -4586,14 +4606,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:3256.3-3283.6" - process $proc$libresoc.v:3256$67 + attribute \src "libresoc.v:3276.3-3303.6" + process $proc$libresoc.v:3276$67 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3257.5-3257.29" + attribute \src "libresoc.v:3277.5-3277.29" switch \initial - attribute \src "libresoc.v:3257.9-3257.17" + attribute \src "libresoc.v:3277.9-3277.17" case 1'1 case end @@ -4633,14 +4653,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:3284.3-3311.6" - process $proc$libresoc.v:3284$68 + attribute \src "libresoc.v:3304.3-3331.6" + process $proc$libresoc.v:3304$68 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3285.5-3285.29" + attribute \src "libresoc.v:3305.5-3305.29" switch \initial - attribute \src "libresoc.v:3285.9-3285.17" + attribute \src "libresoc.v:3305.9-3305.17" case 1'1 case end @@ -4680,14 +4700,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:3312.3-3339.6" - process $proc$libresoc.v:3312$69 + attribute \src "libresoc.v:3332.3-3359.6" + process $proc$libresoc.v:3332$69 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3313.5-3313.29" + attribute \src "libresoc.v:3333.5-3333.29" switch \initial - attribute \src "libresoc.v:3313.9-3313.17" + attribute \src "libresoc.v:3333.9-3333.17" case 1'1 case end @@ -4727,14 +4747,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:3340.3-3367.6" - process $proc$libresoc.v:3340$70 + attribute \src "libresoc.v:3360.3-3387.6" + process $proc$libresoc.v:3360$70 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3341.5-3341.29" + attribute \src "libresoc.v:3361.5-3361.29" switch \initial - attribute \src "libresoc.v:3341.9-3341.17" + attribute \src "libresoc.v:3361.9-3361.17" case 1'1 case end @@ -4774,14 +4794,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:3368.3-3395.6" - process $proc$libresoc.v:3368$71 + attribute \src "libresoc.v:3388.3-3415.6" + process $proc$libresoc.v:3388$71 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3369.5-3369.29" + attribute \src "libresoc.v:3389.5-3389.29" switch \initial - attribute \src "libresoc.v:3369.9-3369.17" + attribute \src "libresoc.v:3389.9-3389.17" case 1'1 case end @@ -4821,14 +4841,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:3396.3-3423.6" - process $proc$libresoc.v:3396$72 + attribute \src "libresoc.v:3416.3-3443.6" + process $proc$libresoc.v:3416$72 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3397.5-3397.29" + attribute \src "libresoc.v:3417.5-3417.29" switch \initial - attribute \src "libresoc.v:3397.9-3397.17" + attribute \src "libresoc.v:3417.9-3417.17" case 1'1 case end @@ -4868,14 +4888,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:3424.3-3451.6" - process $proc$libresoc.v:3424$73 + attribute \src "libresoc.v:3444.3-3471.6" + process $proc$libresoc.v:3444$73 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3425.5-3425.29" + attribute \src "libresoc.v:3445.5-3445.29" switch \initial - attribute \src "libresoc.v:3425.9-3425.17" + attribute \src "libresoc.v:3445.9-3445.17" case 1'1 case end @@ -4915,14 +4935,14 @@ module \ALU_dec31_dec_sub22 sync always update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:3452.3-3479.6" - process $proc$libresoc.v:3452$74 + attribute \src "libresoc.v:3472.3-3499.6" + process $proc$libresoc.v:3472$74 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3453.5-3453.29" + attribute \src "libresoc.v:3473.5-3473.29" switch \initial - attribute \src "libresoc.v:3453.9-3453.17" + attribute \src "libresoc.v:3473.9-3473.17" case 1'1 case end @@ -4964,68 +4984,68 @@ module \ALU_dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:3485.1-3897.10" +attribute \src "libresoc.v:3505.1-3919.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" attribute \generator "nMigen" module \ALU_dec31_dec_sub26 - attribute \src "libresoc.v:3816.3-3831.6" + attribute \src "libresoc.v:3838.3-3853.6" wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3832.3-3847.6" + attribute \src "libresoc.v:3854.3-3869.6" wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3880.3-3895.6" + attribute \src "libresoc.v:3902.3-3917.6" wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3720.3-3735.6" + attribute \src "libresoc.v:3742.3-3757.6" wire $0\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3672.3-3687.6" - wire width 13 $0\ALU_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:3784.3-3799.6" + attribute \src "libresoc.v:3694.3-3709.6" + wire width 14 $0\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3806.3-3821.6" wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3800.3-3815.6" + attribute \src "libresoc.v:3822.3-3837.6" wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3768.3-3783.6" + attribute \src "libresoc.v:3790.3-3805.6" wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3688.3-3703.6" + attribute \src "libresoc.v:3710.3-3725.6" wire $0\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3704.3-3719.6" + attribute \src "libresoc.v:3726.3-3741.6" wire $0\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3736.3-3751.6" + attribute \src "libresoc.v:3758.3-3773.6" wire $0\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3848.3-3863.6" + attribute \src "libresoc.v:3870.3-3885.6" wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3864.3-3879.6" + attribute \src "libresoc.v:3886.3-3901.6" wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3752.3-3767.6" + attribute \src "libresoc.v:3774.3-3789.6" wire $0\ALU_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:3486.7-3486.20" + attribute \src "libresoc.v:3506.7-3506.20" wire $0\initial[0:0] - attribute \src "libresoc.v:3816.3-3831.6" + attribute \src "libresoc.v:3838.3-3853.6" wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3832.3-3847.6" + attribute \src "libresoc.v:3854.3-3869.6" wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3880.3-3895.6" + attribute \src "libresoc.v:3902.3-3917.6" wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3720.3-3735.6" + attribute \src "libresoc.v:3742.3-3757.6" wire $1\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3672.3-3687.6" - wire width 13 $1\ALU_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:3784.3-3799.6" + attribute \src "libresoc.v:3694.3-3709.6" + wire width 14 $1\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3806.3-3821.6" wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3800.3-3815.6" + attribute \src "libresoc.v:3822.3-3837.6" wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3768.3-3783.6" + attribute \src "libresoc.v:3790.3-3805.6" wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3688.3-3703.6" + attribute \src "libresoc.v:3710.3-3725.6" wire $1\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3704.3-3719.6" + attribute \src "libresoc.v:3726.3-3741.6" wire $1\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3736.3-3751.6" + attribute \src "libresoc.v:3758.3-3773.6" wire $1\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3848.3-3863.6" + attribute \src "libresoc.v:3870.3-3885.6" wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3864.3-3879.6" + attribute \src "libresoc.v:3886.3-3901.6" wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3752.3-3767.6" + attribute \src "libresoc.v:3774.3-3789.6" wire $1\ALU_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -5056,21 +5076,22 @@ module \ALU_dec31_dec_sub26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \ALU_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -5170,6 +5191,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -5194,28 +5216,28 @@ module \ALU_dec31_dec_sub26 wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub26_sgn - attribute \src "libresoc.v:3486.7-3486.15" + attribute \src "libresoc.v:3506.7-3506.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:3486.7-3486.20" - process $proc$libresoc.v:3486$90 + attribute \src "libresoc.v:3506.7-3506.20" + process $proc$libresoc.v:3506$90 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:3672.3-3687.6" - process $proc$libresoc.v:3672$76 + attribute \src "libresoc.v:3694.3-3709.6" + process $proc$libresoc.v:3694$76 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub26_function_unit[12:0] $1\ALU_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:3673.5-3673.29" + assign $0\ALU_dec31_dec_sub26_function_unit[13:0] $1\ALU_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:3695.5-3695.29" switch \initial - attribute \src "libresoc.v:3673.9-3673.17" + attribute \src "libresoc.v:3695.9-3695.17" case 1'1 case end @@ -5224,29 +5246,29 @@ module \ALU_dec31_dec_sub26 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub26_function_unit[12:0] 13'0000000000000 + assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[12:0] + update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:3688.3-3703.6" - process $proc$libresoc.v:3688$77 + attribute \src "libresoc.v:3710.3-3725.6" + process $proc$libresoc.v:3710$77 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3689.5-3689.29" + attribute \src "libresoc.v:3711.5-3711.29" switch \initial - attribute \src "libresoc.v:3689.9-3689.17" + attribute \src "libresoc.v:3711.9-3711.17" case 1'1 case end @@ -5270,14 +5292,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:3704.3-3719.6" - process $proc$libresoc.v:3704$78 + attribute \src "libresoc.v:3726.3-3741.6" + process $proc$libresoc.v:3726$78 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3705.5-3705.29" + attribute \src "libresoc.v:3727.5-3727.29" switch \initial - attribute \src "libresoc.v:3705.9-3705.17" + attribute \src "libresoc.v:3727.9-3727.17" case 1'1 case end @@ -5301,14 +5323,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:3720.3-3735.6" - process $proc$libresoc.v:3720$79 + attribute \src "libresoc.v:3742.3-3757.6" + process $proc$libresoc.v:3742$79 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3721.5-3721.29" + attribute \src "libresoc.v:3743.5-3743.29" switch \initial - attribute \src "libresoc.v:3721.9-3721.17" + attribute \src "libresoc.v:3743.9-3743.17" case 1'1 case end @@ -5332,14 +5354,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:3736.3-3751.6" - process $proc$libresoc.v:3736$80 + attribute \src "libresoc.v:3758.3-3773.6" + process $proc$libresoc.v:3758$80 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3737.5-3737.29" + attribute \src "libresoc.v:3759.5-3759.29" switch \initial - attribute \src "libresoc.v:3737.9-3737.17" + attribute \src "libresoc.v:3759.9-3759.17" case 1'1 case end @@ -5363,14 +5385,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:3752.3-3767.6" - process $proc$libresoc.v:3752$81 + attribute \src "libresoc.v:3774.3-3789.6" + process $proc$libresoc.v:3774$81 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:3753.5-3753.29" + attribute \src "libresoc.v:3775.5-3775.29" switch \initial - attribute \src "libresoc.v:3753.9-3753.17" + attribute \src "libresoc.v:3775.9-3775.17" case 1'1 case end @@ -5394,14 +5416,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:3768.3-3783.6" - process $proc$libresoc.v:3768$82 + attribute \src "libresoc.v:3790.3-3805.6" + process $proc$libresoc.v:3790$82 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3769.5-3769.29" + attribute \src "libresoc.v:3791.5-3791.29" switch \initial - attribute \src "libresoc.v:3769.9-3769.17" + attribute \src "libresoc.v:3791.9-3791.17" case 1'1 case end @@ -5425,14 +5447,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:3784.3-3799.6" - process $proc$libresoc.v:3784$83 + attribute \src "libresoc.v:3806.3-3821.6" + process $proc$libresoc.v:3806$83 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3785.5-3785.29" + attribute \src "libresoc.v:3807.5-3807.29" switch \initial - attribute \src "libresoc.v:3785.9-3785.17" + attribute \src "libresoc.v:3807.9-3807.17" case 1'1 case end @@ -5456,14 +5478,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:3800.3-3815.6" - process $proc$libresoc.v:3800$84 + attribute \src "libresoc.v:3822.3-3837.6" + process $proc$libresoc.v:3822$84 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3801.5-3801.29" + attribute \src "libresoc.v:3823.5-3823.29" switch \initial - attribute \src "libresoc.v:3801.9-3801.17" + attribute \src "libresoc.v:3823.9-3823.17" case 1'1 case end @@ -5487,14 +5509,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:3816.3-3831.6" - process $proc$libresoc.v:3816$85 + attribute \src "libresoc.v:3838.3-3853.6" + process $proc$libresoc.v:3838$85 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3817.5-3817.29" + attribute \src "libresoc.v:3839.5-3839.29" switch \initial - attribute \src "libresoc.v:3817.9-3817.17" + attribute \src "libresoc.v:3839.9-3839.17" case 1'1 case end @@ -5518,14 +5540,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:3832.3-3847.6" - process $proc$libresoc.v:3832$86 + attribute \src "libresoc.v:3854.3-3869.6" + process $proc$libresoc.v:3854$86 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3833.5-3833.29" + attribute \src "libresoc.v:3855.5-3855.29" switch \initial - attribute \src "libresoc.v:3833.9-3833.17" + attribute \src "libresoc.v:3855.9-3855.17" case 1'1 case end @@ -5549,14 +5571,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:3848.3-3863.6" - process $proc$libresoc.v:3848$87 + attribute \src "libresoc.v:3870.3-3885.6" + process $proc$libresoc.v:3870$87 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3849.5-3849.29" + attribute \src "libresoc.v:3871.5-3871.29" switch \initial - attribute \src "libresoc.v:3849.9-3849.17" + attribute \src "libresoc.v:3871.9-3871.17" case 1'1 case end @@ -5580,14 +5602,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:3864.3-3879.6" - process $proc$libresoc.v:3864$88 + attribute \src "libresoc.v:3886.3-3901.6" + process $proc$libresoc.v:3886$88 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3865.5-3865.29" + attribute \src "libresoc.v:3887.5-3887.29" switch \initial - attribute \src "libresoc.v:3865.9-3865.17" + attribute \src "libresoc.v:3887.9-3887.17" case 1'1 case end @@ -5611,14 +5633,14 @@ module \ALU_dec31_dec_sub26 sync always update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:3880.3-3895.6" - process $proc$libresoc.v:3880$89 + attribute \src "libresoc.v:3902.3-3917.6" + process $proc$libresoc.v:3902$89 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3881.5-3881.29" + attribute \src "libresoc.v:3903.5-3903.29" switch \initial - attribute \src "libresoc.v:3881.9-3881.17" + attribute \src "libresoc.v:3903.9-3903.17" case 1'1 case end @@ -5644,68 +5666,68 @@ module \ALU_dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:3901.1-4691.10" +attribute \src "libresoc.v:3923.1-4715.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" attribute \generator "nMigen" module \ALU_dec31_dec_sub8 - attribute \src "libresoc.v:4475.3-4517.6" + attribute \src "libresoc.v:4499.3-4541.6" wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4518.3-4560.6" + attribute \src "libresoc.v:4542.3-4584.6" wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4647.3-4689.6" + attribute \src "libresoc.v:4671.3-4713.6" wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4217.3-4259.6" + attribute \src "libresoc.v:4241.3-4283.6" wire $0\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4088.3-4130.6" - wire width 13 $0\ALU_dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:4389.3-4431.6" + attribute \src "libresoc.v:4112.3-4154.6" + wire width 14 $0\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4413.3-4455.6" wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4432.3-4474.6" + attribute \src "libresoc.v:4456.3-4498.6" wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4346.3-4388.6" + attribute \src "libresoc.v:4370.3-4412.6" wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4131.3-4173.6" + attribute \src "libresoc.v:4155.3-4197.6" wire $0\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4174.3-4216.6" + attribute \src "libresoc.v:4198.3-4240.6" wire $0\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4260.3-4302.6" + attribute \src "libresoc.v:4284.3-4326.6" wire $0\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4561.3-4603.6" + attribute \src "libresoc.v:4585.3-4627.6" wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4604.3-4646.6" + attribute \src "libresoc.v:4628.3-4670.6" wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4303.3-4345.6" + attribute \src "libresoc.v:4327.3-4369.6" wire $0\ALU_dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:3902.7-3902.20" + attribute \src "libresoc.v:3924.7-3924.20" wire $0\initial[0:0] - attribute \src "libresoc.v:4475.3-4517.6" + attribute \src "libresoc.v:4499.3-4541.6" wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4518.3-4560.6" + attribute \src "libresoc.v:4542.3-4584.6" wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4647.3-4689.6" + attribute \src "libresoc.v:4671.3-4713.6" wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4217.3-4259.6" + attribute \src "libresoc.v:4241.3-4283.6" wire $1\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4088.3-4130.6" - wire width 13 $1\ALU_dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:4389.3-4431.6" + attribute \src "libresoc.v:4112.3-4154.6" + wire width 14 $1\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4413.3-4455.6" wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4432.3-4474.6" + attribute \src "libresoc.v:4456.3-4498.6" wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4346.3-4388.6" + attribute \src "libresoc.v:4370.3-4412.6" wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4131.3-4173.6" + attribute \src "libresoc.v:4155.3-4197.6" wire $1\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4174.3-4216.6" + attribute \src "libresoc.v:4198.3-4240.6" wire $1\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4260.3-4302.6" + attribute \src "libresoc.v:4284.3-4326.6" wire $1\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4561.3-4603.6" + attribute \src "libresoc.v:4585.3-4627.6" wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4604.3-4646.6" + attribute \src "libresoc.v:4628.3-4670.6" wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4303.3-4345.6" + attribute \src "libresoc.v:4327.3-4369.6" wire $1\ALU_dec31_dec_sub8_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -5736,21 +5758,22 @@ module \ALU_dec31_dec_sub8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \ALU_dec31_dec_sub8_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -5850,6 +5873,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -5874,28 +5898,28 @@ module \ALU_dec31_dec_sub8 wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \ALU_dec31_dec_sub8_sgn - attribute \src "libresoc.v:3902.7-3902.15" + attribute \src "libresoc.v:3924.7-3924.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:3902.7-3902.20" - process $proc$libresoc.v:3902$105 + attribute \src "libresoc.v:3924.7-3924.20" + process $proc$libresoc.v:3924$105 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:4088.3-4130.6" - process $proc$libresoc.v:4088$91 + attribute \src "libresoc.v:4112.3-4154.6" + process $proc$libresoc.v:4112$91 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub8_function_unit[12:0] $1\ALU_dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:4089.5-4089.29" + assign $0\ALU_dec31_dec_sub8_function_unit[13:0] $1\ALU_dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:4113.5-4113.29" switch \initial - attribute \src "libresoc.v:4089.9-4089.17" + attribute \src "libresoc.v:4113.9-4113.17" case 1'1 case end @@ -5904,65 +5928,65 @@ module \ALU_dec31_dec_sub8 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000000 + assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[12:0] + update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:4131.3-4173.6" - process $proc$libresoc.v:4131$92 + attribute \src "libresoc.v:4155.3-4197.6" + process $proc$libresoc.v:4155$92 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4132.5-4132.29" + attribute \src "libresoc.v:4156.5-4156.29" switch \initial - attribute \src "libresoc.v:4132.9-4132.17" + attribute \src "libresoc.v:4156.9-4156.17" case 1'1 case end @@ -6022,14 +6046,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:4174.3-4216.6" - process $proc$libresoc.v:4174$93 + attribute \src "libresoc.v:4198.3-4240.6" + process $proc$libresoc.v:4198$93 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4175.5-4175.29" + attribute \src "libresoc.v:4199.5-4199.29" switch \initial - attribute \src "libresoc.v:4175.9-4175.17" + attribute \src "libresoc.v:4199.9-4199.17" case 1'1 case end @@ -6089,14 +6113,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:4217.3-4259.6" - process $proc$libresoc.v:4217$94 + attribute \src "libresoc.v:4241.3-4283.6" + process $proc$libresoc.v:4241$94 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4218.5-4218.29" + attribute \src "libresoc.v:4242.5-4242.29" switch \initial - attribute \src "libresoc.v:4218.9-4218.17" + attribute \src "libresoc.v:4242.9-4242.17" case 1'1 case end @@ -6156,14 +6180,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:4260.3-4302.6" - process $proc$libresoc.v:4260$95 + attribute \src "libresoc.v:4284.3-4326.6" + process $proc$libresoc.v:4284$95 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4261.5-4261.29" + attribute \src "libresoc.v:4285.5-4285.29" switch \initial - attribute \src "libresoc.v:4261.9-4261.17" + attribute \src "libresoc.v:4285.9-4285.17" case 1'1 case end @@ -6223,14 +6247,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:4303.3-4345.6" - process $proc$libresoc.v:4303$96 + attribute \src "libresoc.v:4327.3-4369.6" + process $proc$libresoc.v:4327$96 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:4304.5-4304.29" + attribute \src "libresoc.v:4328.5-4328.29" switch \initial - attribute \src "libresoc.v:4304.9-4304.17" + attribute \src "libresoc.v:4328.9-4328.17" case 1'1 case end @@ -6290,14 +6314,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:4346.3-4388.6" - process $proc$libresoc.v:4346$97 + attribute \src "libresoc.v:4370.3-4412.6" + process $proc$libresoc.v:4370$97 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4347.5-4347.29" + attribute \src "libresoc.v:4371.5-4371.29" switch \initial - attribute \src "libresoc.v:4347.9-4347.17" + attribute \src "libresoc.v:4371.9-4371.17" case 1'1 case end @@ -6357,14 +6381,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:4389.3-4431.6" - process $proc$libresoc.v:4389$98 + attribute \src "libresoc.v:4413.3-4455.6" + process $proc$libresoc.v:4413$98 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4390.5-4390.29" + attribute \src "libresoc.v:4414.5-4414.29" switch \initial - attribute \src "libresoc.v:4390.9-4390.17" + attribute \src "libresoc.v:4414.9-4414.17" case 1'1 case end @@ -6424,14 +6448,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:4432.3-4474.6" - process $proc$libresoc.v:4432$99 + attribute \src "libresoc.v:4456.3-4498.6" + process $proc$libresoc.v:4456$99 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4433.5-4433.29" + attribute \src "libresoc.v:4457.5-4457.29" switch \initial - attribute \src "libresoc.v:4433.9-4433.17" + attribute \src "libresoc.v:4457.9-4457.17" case 1'1 case end @@ -6491,14 +6515,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:4475.3-4517.6" - process $proc$libresoc.v:4475$100 + attribute \src "libresoc.v:4499.3-4541.6" + process $proc$libresoc.v:4499$100 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4476.5-4476.29" + attribute \src "libresoc.v:4500.5-4500.29" switch \initial - attribute \src "libresoc.v:4476.9-4476.17" + attribute \src "libresoc.v:4500.9-4500.17" case 1'1 case end @@ -6558,14 +6582,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:4518.3-4560.6" - process $proc$libresoc.v:4518$101 + attribute \src "libresoc.v:4542.3-4584.6" + process $proc$libresoc.v:4542$101 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4519.5-4519.29" + attribute \src "libresoc.v:4543.5-4543.29" switch \initial - attribute \src "libresoc.v:4519.9-4519.17" + attribute \src "libresoc.v:4543.9-4543.17" case 1'1 case end @@ -6625,14 +6649,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:4561.3-4603.6" - process $proc$libresoc.v:4561$102 + attribute \src "libresoc.v:4585.3-4627.6" + process $proc$libresoc.v:4585$102 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4562.5-4562.29" + attribute \src "libresoc.v:4586.5-4586.29" switch \initial - attribute \src "libresoc.v:4562.9-4562.17" + attribute \src "libresoc.v:4586.9-4586.17" case 1'1 case end @@ -6692,14 +6716,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:4604.3-4646.6" - process $proc$libresoc.v:4604$103 + attribute \src "libresoc.v:4628.3-4670.6" + process $proc$libresoc.v:4628$103 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4605.5-4605.29" + attribute \src "libresoc.v:4629.5-4629.29" switch \initial - attribute \src "libresoc.v:4605.9-4605.17" + attribute \src "libresoc.v:4629.9-4629.17" case 1'1 case end @@ -6759,14 +6783,14 @@ module \ALU_dec31_dec_sub8 sync always update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:4647.3-4689.6" - process $proc$libresoc.v:4647$104 + attribute \src "libresoc.v:4671.3-4713.6" + process $proc$libresoc.v:4671$104 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4648.5-4648.29" + attribute \src "libresoc.v:4672.5-4672.29" switch \initial - attribute \src "libresoc.v:4648.9-4648.17" + attribute \src "libresoc.v:4672.9-4672.17" case 1'1 case end @@ -6828,44 +6852,44 @@ module \ALU_dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:4695.1-4977.10" +attribute \src "libresoc.v:4719.1-5003.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" attribute \generator "nMigen" module \BRANCH_dec19 - attribute \src "libresoc.v:4896.3-4911.6" + attribute \src "libresoc.v:4922.3-4937.6" wire width 3 $0\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4912.3-4927.6" + attribute \src "libresoc.v:4938.3-4953.6" wire width 3 $0\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4848.3-4863.6" - wire width 13 $0\BRANCH_dec19_function_unit[12:0] - attribute \src "libresoc.v:4880.3-4895.6" + attribute \src "libresoc.v:4874.3-4889.6" + wire width 14 $0\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4906.3-4921.6" wire width 4 $0\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4864.3-4879.6" + attribute \src "libresoc.v:4890.3-4905.6" wire width 7 $0\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4944.3-4959.6" + attribute \src "libresoc.v:4970.3-4985.6" wire $0\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4960.3-4975.6" + attribute \src "libresoc.v:4986.3-5001.6" wire $0\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4928.3-4943.6" + attribute \src "libresoc.v:4954.3-4969.6" wire width 2 $0\BRANCH_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4696.7-4696.20" + attribute \src "libresoc.v:4720.7-4720.20" wire $0\initial[0:0] - attribute \src "libresoc.v:4896.3-4911.6" + attribute \src "libresoc.v:4922.3-4937.6" wire width 3 $1\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4912.3-4927.6" + attribute \src "libresoc.v:4938.3-4953.6" wire width 3 $1\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4848.3-4863.6" - wire width 13 $1\BRANCH_dec19_function_unit[12:0] - attribute \src "libresoc.v:4880.3-4895.6" + attribute \src "libresoc.v:4874.3-4889.6" + wire width 14 $1\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4906.3-4921.6" wire width 4 $1\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4864.3-4879.6" + attribute \src "libresoc.v:4890.3-4905.6" wire width 7 $1\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4944.3-4959.6" + attribute \src "libresoc.v:4970.3-4985.6" wire $1\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4960.3-4975.6" + attribute \src "libresoc.v:4986.3-5001.6" wire $1\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4928.3-4943.6" + attribute \src "libresoc.v:4954.3-4969.6" wire width 2 $1\BRANCH_dec19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -6888,21 +6912,22 @@ module \BRANCH_dec19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \BRANCH_dec19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \BRANCH_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -6994,6 +7019,7 @@ module \BRANCH_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \BRANCH_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -7006,28 +7032,28 @@ module \BRANCH_dec19 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 6 \BRANCH_dec19_rc_sel - attribute \src "libresoc.v:4696.7-4696.15" + attribute \src "libresoc.v:4720.7-4720.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 9 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:4696.7-4696.20" - process $proc$libresoc.v:4696$114 + attribute \src "libresoc.v:4720.7-4720.20" + process $proc$libresoc.v:4720$114 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:4848.3-4863.6" - process $proc$libresoc.v:4848$106 + attribute \src "libresoc.v:4874.3-4889.6" + process $proc$libresoc.v:4874$106 assign { } { } assign { } { } - assign $0\BRANCH_dec19_function_unit[12:0] $1\BRANCH_dec19_function_unit[12:0] - attribute \src "libresoc.v:4849.5-4849.29" + assign $0\BRANCH_dec19_function_unit[13:0] $1\BRANCH_dec19_function_unit[13:0] + attribute \src "libresoc.v:4875.5-4875.29" switch \initial - attribute \src "libresoc.v:4849.9-4849.17" + attribute \src "libresoc.v:4875.9-4875.17" case 1'1 case end @@ -7036,29 +7062,29 @@ module \BRANCH_dec19 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\BRANCH_dec19_function_unit[12:0] 13'0000000100000 + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\BRANCH_dec19_function_unit[12:0] 13'0000000100000 + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\BRANCH_dec19_function_unit[12:0] 13'0000000100000 + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 case - assign $1\BRANCH_dec19_function_unit[12:0] 13'0000000000000 + assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000000000 end sync always - update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[12:0] + update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[13:0] end - attribute \src "libresoc.v:4864.3-4879.6" - process $proc$libresoc.v:4864$107 + attribute \src "libresoc.v:4890.3-4905.6" + process $proc$libresoc.v:4890$107 assign { } { } assign { } { } assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4865.5-4865.29" + attribute \src "libresoc.v:4891.5-4891.29" switch \initial - attribute \src "libresoc.v:4865.9-4865.17" + attribute \src "libresoc.v:4891.9-4891.17" case 1'1 case end @@ -7082,14 +7108,14 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] end - attribute \src "libresoc.v:4880.3-4895.6" - process $proc$libresoc.v:4880$108 + attribute \src "libresoc.v:4906.3-4921.6" + process $proc$libresoc.v:4906$108 assign { } { } assign { } { } assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4881.5-4881.29" + attribute \src "libresoc.v:4907.5-4907.29" switch \initial - attribute \src "libresoc.v:4881.9-4881.17" + attribute \src "libresoc.v:4907.9-4907.17" case 1'1 case end @@ -7113,14 +7139,14 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] end - attribute \src "libresoc.v:4896.3-4911.6" - process $proc$libresoc.v:4896$109 + attribute \src "libresoc.v:4922.3-4937.6" + process $proc$libresoc.v:4922$109 assign { } { } assign { } { } assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4897.5-4897.29" + attribute \src "libresoc.v:4923.5-4923.29" switch \initial - attribute \src "libresoc.v:4897.9-4897.17" + attribute \src "libresoc.v:4923.9-4923.17" case 1'1 case end @@ -7144,14 +7170,14 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] end - attribute \src "libresoc.v:4912.3-4927.6" - process $proc$libresoc.v:4912$110 + attribute \src "libresoc.v:4938.3-4953.6" + process $proc$libresoc.v:4938$110 assign { } { } assign { } { } assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4913.5-4913.29" + attribute \src "libresoc.v:4939.5-4939.29" switch \initial - attribute \src "libresoc.v:4913.9-4913.17" + attribute \src "libresoc.v:4939.9-4939.17" case 1'1 case end @@ -7175,14 +7201,14 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] end - attribute \src "libresoc.v:4928.3-4943.6" - process $proc$libresoc.v:4928$111 + attribute \src "libresoc.v:4954.3-4969.6" + process $proc$libresoc.v:4954$111 assign { } { } assign { } { } assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4929.5-4929.29" + attribute \src "libresoc.v:4955.5-4955.29" switch \initial - attribute \src "libresoc.v:4929.9-4929.17" + attribute \src "libresoc.v:4955.9-4955.17" case 1'1 case end @@ -7206,14 +7232,14 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] end - attribute \src "libresoc.v:4944.3-4959.6" - process $proc$libresoc.v:4944$112 + attribute \src "libresoc.v:4970.3-4985.6" + process $proc$libresoc.v:4970$112 assign { } { } assign { } { } assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4945.5-4945.29" + attribute \src "libresoc.v:4971.5-4971.29" switch \initial - attribute \src "libresoc.v:4945.9-4945.17" + attribute \src "libresoc.v:4971.9-4971.17" case 1'1 case end @@ -7237,14 +7263,14 @@ module \BRANCH_dec19 sync always update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] end - attribute \src "libresoc.v:4960.3-4975.6" - process $proc$libresoc.v:4960$113 + attribute \src "libresoc.v:4986.3-5001.6" + process $proc$libresoc.v:4986$113 assign { } { } assign { } { } assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4961.5-4961.29" + attribute \src "libresoc.v:4987.5-4987.29" switch \initial - attribute \src "libresoc.v:4961.9-4961.17" + attribute \src "libresoc.v:4987.9-4987.17" case 1'1 case end @@ -7270,32 +7296,32 @@ module \BRANCH_dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:4981.1-5281.10" +attribute \src "libresoc.v:5007.1-5309.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec19" attribute \generator "nMigen" module \CR_dec19 - attribute \src "libresoc.v:5178.3-5211.6" + attribute \src "libresoc.v:5206.3-5239.6" wire width 3 $0\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5212.3-5245.6" + attribute \src "libresoc.v:5240.3-5273.6" wire width 3 $0\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5110.3-5143.6" - wire width 13 $0\CR_dec19_function_unit[12:0] - attribute \src "libresoc.v:5144.3-5177.6" + attribute \src "libresoc.v:5138.3-5171.6" + wire width 14 $0\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5172.3-5205.6" wire width 7 $0\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5246.3-5279.6" + attribute \src "libresoc.v:5274.3-5307.6" wire width 2 $0\CR_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4982.7-4982.20" + attribute \src "libresoc.v:5008.7-5008.20" wire $0\initial[0:0] - attribute \src "libresoc.v:5178.3-5211.6" + attribute \src "libresoc.v:5206.3-5239.6" wire width 3 $1\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5212.3-5245.6" + attribute \src "libresoc.v:5240.3-5273.6" wire width 3 $1\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5110.3-5143.6" - wire width 13 $1\CR_dec19_function_unit[12:0] - attribute \src "libresoc.v:5144.3-5177.6" + attribute \src "libresoc.v:5138.3-5171.6" + wire width 14 $1\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5172.3-5205.6" wire width 7 $1\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5246.3-5279.6" + attribute \src "libresoc.v:5274.3-5307.6" wire width 2 $1\CR_dec19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7318,21 +7344,22 @@ module \CR_dec19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \CR_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -7407,6 +7434,7 @@ module \CR_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec19_internal_op attribute \enum_base_type "RC" @@ -7415,28 +7443,28 @@ module \CR_dec19 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec19_rc_sel - attribute \src "libresoc.v:4982.7-4982.15" + attribute \src "libresoc.v:5008.7-5008.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:4982.7-4982.20" - process $proc$libresoc.v:4982$120 + attribute \src "libresoc.v:5008.7-5008.20" + process $proc$libresoc.v:5008$120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:5110.3-5143.6" - process $proc$libresoc.v:5110$115 + attribute \src "libresoc.v:5138.3-5171.6" + process $proc$libresoc.v:5138$115 assign { } { } assign { } { } - assign $0\CR_dec19_function_unit[12:0] $1\CR_dec19_function_unit[12:0] - attribute \src "libresoc.v:5111.5-5111.29" + assign $0\CR_dec19_function_unit[13:0] $1\CR_dec19_function_unit[13:0] + attribute \src "libresoc.v:5139.5-5139.29" switch \initial - attribute \src "libresoc.v:5111.9-5111.17" + attribute \src "libresoc.v:5139.9-5139.17" case 1'1 case end @@ -7445,53 +7473,53 @@ module \CR_dec19 attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec19_function_unit[12:0] 13'0000000000000 + assign $1\CR_dec19_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec19_function_unit $0\CR_dec19_function_unit[12:0] + update \CR_dec19_function_unit $0\CR_dec19_function_unit[13:0] end - attribute \src "libresoc.v:5144.3-5177.6" - process $proc$libresoc.v:5144$116 + attribute \src "libresoc.v:5172.3-5205.6" + process $proc$libresoc.v:5172$116 assign { } { } assign { } { } assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5145.5-5145.29" + attribute \src "libresoc.v:5173.5-5173.29" switch \initial - attribute \src "libresoc.v:5145.9-5145.17" + attribute \src "libresoc.v:5173.9-5173.17" case 1'1 case end @@ -7539,14 +7567,14 @@ module \CR_dec19 sync always update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] end - attribute \src "libresoc.v:5178.3-5211.6" - process $proc$libresoc.v:5178$117 + attribute \src "libresoc.v:5206.3-5239.6" + process $proc$libresoc.v:5206$117 assign { } { } assign { } { } assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5179.5-5179.29" + attribute \src "libresoc.v:5207.5-5207.29" switch \initial - attribute \src "libresoc.v:5179.9-5179.17" + attribute \src "libresoc.v:5207.9-5207.17" case 1'1 case end @@ -7594,14 +7622,14 @@ module \CR_dec19 sync always update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] end - attribute \src "libresoc.v:5212.3-5245.6" - process $proc$libresoc.v:5212$118 + attribute \src "libresoc.v:5240.3-5273.6" + process $proc$libresoc.v:5240$118 assign { } { } assign { } { } assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5213.5-5213.29" + attribute \src "libresoc.v:5241.5-5241.29" switch \initial - attribute \src "libresoc.v:5213.9-5213.17" + attribute \src "libresoc.v:5241.9-5241.17" case 1'1 case end @@ -7649,14 +7677,14 @@ module \CR_dec19 sync always update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] end - attribute \src "libresoc.v:5246.3-5279.6" - process $proc$libresoc.v:5246$119 + attribute \src "libresoc.v:5274.3-5307.6" + process $proc$libresoc.v:5274$119 assign { } { } assign { } { } assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] - attribute \src "libresoc.v:5247.5-5247.29" + attribute \src "libresoc.v:5275.5-5275.29" switch \initial - attribute \src "libresoc.v:5247.9-5247.17" + attribute \src "libresoc.v:5275.9-5275.17" case 1'1 case end @@ -7706,32 +7734,32 @@ module \CR_dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:5285.1-6029.10" +attribute \src "libresoc.v:5313.1-6067.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31" attribute \generator "nMigen" module \CR_dec31 - attribute \src "libresoc.v:5985.3-6003.6" + attribute \src "libresoc.v:6023.3-6041.6" wire width 3 $0\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:6004.3-6022.6" + attribute \src "libresoc.v:6042.3-6060.6" wire width 3 $0\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:5947.3-5965.6" - wire width 13 $0\CR_dec31_function_unit[12:0] - attribute \src "libresoc.v:5966.3-5984.6" + attribute \src "libresoc.v:5985.3-6003.6" + wire width 14 $0\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:6004.3-6022.6" wire width 7 $0\CR_dec31_internal_op[6:0] - attribute \src "libresoc.v:5928.3-5946.6" + attribute \src "libresoc.v:5966.3-5984.6" wire width 2 $0\CR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:5286.7-5286.20" + attribute \src "libresoc.v:5314.7-5314.20" wire $0\initial[0:0] - attribute \src "libresoc.v:5985.3-6003.6" + attribute \src "libresoc.v:6023.3-6041.6" wire width 3 $1\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:6004.3-6022.6" + attribute \src "libresoc.v:6042.3-6060.6" wire width 3 $1\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:5947.3-5965.6" - wire width 13 $1\CR_dec31_function_unit[12:0] - attribute \src "libresoc.v:5966.3-5984.6" + attribute \src "libresoc.v:5985.3-6003.6" + wire width 14 $1\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:6004.3-6022.6" wire width 7 $1\CR_dec31_internal_op[6:0] - attribute \src "libresoc.v:5928.3-5946.6" + attribute \src "libresoc.v:5966.3-5984.6" wire width 2 $1\CR_dec31_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7774,21 +7802,22 @@ module \CR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -7863,6 +7892,7 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" @@ -7894,21 +7924,22 @@ module \CR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -7983,6 +8014,7 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" @@ -8014,21 +8046,22 @@ module \CR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8103,6 +8136,7 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" @@ -8134,21 +8168,22 @@ module \CR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8223,6 +8258,7 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" @@ -8234,21 +8270,22 @@ module \CR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \CR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \CR_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8323,6 +8360,7 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_internal_op attribute \enum_base_type "RC" @@ -8331,7 +8369,7 @@ module \CR_dec31 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_rc_sel - attribute \src "libresoc.v:5286.7-5286.15" + attribute \src "libresoc.v:5314.7-5314.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -8340,7 +8378,7 @@ module \CR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:5896.21-5903.4" + attribute \src "libresoc.v:5934.21-5941.4" cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out @@ -8350,7 +8388,7 @@ module \CR_dec31 connect \opcode_in \CR_dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:5904.22-5911.4" + attribute \src "libresoc.v:5942.22-5949.4" cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out @@ -8360,7 +8398,7 @@ module \CR_dec31 connect \opcode_in \CR_dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:5912.22-5919.4" + attribute \src "libresoc.v:5950.22-5957.4" cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out @@ -8370,7 +8408,7 @@ module \CR_dec31 connect \opcode_in \CR_dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:5920.22-5927.4" + attribute \src "libresoc.v:5958.22-5965.4" cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out @@ -8379,22 +8417,22 @@ module \CR_dec31 connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel connect \opcode_in \CR_dec31_dec_sub19_opcode_in end - attribute \src "libresoc.v:5286.7-5286.20" - process $proc$libresoc.v:5286$126 + attribute \src "libresoc.v:5314.7-5314.20" + process $proc$libresoc.v:5314$126 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:5928.3-5946.6" - process $proc$libresoc.v:5928$121 + attribute \src "libresoc.v:5966.3-5984.6" + process $proc$libresoc.v:5966$121 assign { } { } assign { } { } assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:5929.5-5929.29" + attribute \src "libresoc.v:5967.5-5967.29" switch \initial - attribute \src "libresoc.v:5929.9-5929.17" + attribute \src "libresoc.v:5967.9-5967.17" case 1'1 case end @@ -8422,14 +8460,14 @@ module \CR_dec31 sync always update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:5947.3-5965.6" - process $proc$libresoc.v:5947$122 + attribute \src "libresoc.v:5985.3-6003.6" + process $proc$libresoc.v:5985$122 assign { } { } assign { } { } - assign $0\CR_dec31_function_unit[12:0] $1\CR_dec31_function_unit[12:0] - attribute \src "libresoc.v:5948.5-5948.29" + assign $0\CR_dec31_function_unit[13:0] $1\CR_dec31_function_unit[13:0] + attribute \src "libresoc.v:5986.5-5986.29" switch \initial - attribute \src "libresoc.v:5948.9-5948.17" + attribute \src "libresoc.v:5986.9-5986.17" case 1'1 case end @@ -8438,33 +8476,33 @@ module \CR_dec31 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\CR_dec31_function_unit[12:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\CR_dec31_function_unit[12:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\CR_dec31_function_unit[12:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\CR_dec31_function_unit[12:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit case - assign $1\CR_dec31_function_unit[12:0] 13'0000000000000 + assign $1\CR_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_function_unit $0\CR_dec31_function_unit[12:0] + update \CR_dec31_function_unit $0\CR_dec31_function_unit[13:0] end - attribute \src "libresoc.v:5966.3-5984.6" - process $proc$libresoc.v:5966$123 + attribute \src "libresoc.v:6004.3-6022.6" + process $proc$libresoc.v:6004$123 assign { } { } assign { } { } assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] - attribute \src "libresoc.v:5967.5-5967.29" + attribute \src "libresoc.v:6005.5-6005.29" switch \initial - attribute \src "libresoc.v:5967.9-5967.17" + attribute \src "libresoc.v:6005.9-6005.17" case 1'1 case end @@ -8492,14 +8530,14 @@ module \CR_dec31 sync always update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] end - attribute \src "libresoc.v:5985.3-6003.6" - process $proc$libresoc.v:5985$124 + attribute \src "libresoc.v:6023.3-6041.6" + process $proc$libresoc.v:6023$124 assign { } { } assign { } { } assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:5986.5-5986.29" + attribute \src "libresoc.v:6024.5-6024.29" switch \initial - attribute \src "libresoc.v:5986.9-5986.17" + attribute \src "libresoc.v:6024.9-6024.17" case 1'1 case end @@ -8527,14 +8565,14 @@ module \CR_dec31 sync always update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] end - attribute \src "libresoc.v:6004.3-6022.6" - process $proc$libresoc.v:6004$125 + attribute \src "libresoc.v:6042.3-6060.6" + process $proc$libresoc.v:6042$125 assign { } { } assign { } { } assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:6005.5-6005.29" + attribute \src "libresoc.v:6043.5-6043.29" switch \initial - attribute \src "libresoc.v:6005.9-6005.17" + attribute \src "libresoc.v:6043.9-6043.17" case 1'1 case end @@ -8569,32 +8607,32 @@ module \CR_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:6033.1-6213.10" +attribute \src "libresoc.v:6071.1-6253.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" attribute \generator "nMigen" module \CR_dec31_dec_sub0 - attribute \src "libresoc.v:6182.3-6191.6" + attribute \src "libresoc.v:6222.3-6231.6" wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6192.3-6201.6" + attribute \src "libresoc.v:6232.3-6241.6" wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6162.3-6171.6" - wire width 13 $0\CR_dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:6172.3-6181.6" - wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:6202.3-6211.6" + wire width 14 $0\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6212.3-6221.6" + wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6242.3-6251.6" wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:6034.7-6034.20" + attribute \src "libresoc.v:6072.7-6072.20" wire $0\initial[0:0] - attribute \src "libresoc.v:6182.3-6191.6" + attribute \src "libresoc.v:6222.3-6231.6" wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6192.3-6201.6" + attribute \src "libresoc.v:6232.3-6241.6" wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6162.3-6171.6" - wire width 13 $1\CR_dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:6172.3-6181.6" - wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:6202.3-6211.6" + wire width 14 $1\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6212.3-6221.6" + wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6242.3-6251.6" wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8617,21 +8655,22 @@ module \CR_dec31_dec_sub0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \CR_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8706,6 +8745,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" @@ -8714,28 +8754,28 @@ module \CR_dec31_dec_sub0 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel - attribute \src "libresoc.v:6034.7-6034.15" + attribute \src "libresoc.v:6072.7-6072.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:6034.7-6034.20" - process $proc$libresoc.v:6034$132 + attribute \src "libresoc.v:6072.7-6072.20" + process $proc$libresoc.v:6072$132 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:6162.3-6171.6" - process $proc$libresoc.v:6162$127 + attribute \src "libresoc.v:6202.3-6211.6" + process $proc$libresoc.v:6202$127 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub0_function_unit[12:0] $1\CR_dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:6163.5-6163.29" + assign $0\CR_dec31_dec_sub0_function_unit[13:0] $1\CR_dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:6203.5-6203.29" switch \initial - attribute \src "libresoc.v:6163.9-6163.17" + attribute \src "libresoc.v:6203.9-6203.17" case 1'1 case end @@ -8744,21 +8784,21 @@ module \CR_dec31_dec_sub0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\CR_dec31_dec_sub0_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub0_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec31_dec_sub0_function_unit[12:0] 13'0000000000000 + assign $1\CR_dec31_dec_sub0_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[12:0] + update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:6172.3-6181.6" - process $proc$libresoc.v:6172$128 + attribute \src "libresoc.v:6212.3-6221.6" + process $proc$libresoc.v:6212$128 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:6173.5-6173.29" + attribute \src "libresoc.v:6213.5-6213.29" switch \initial - attribute \src "libresoc.v:6173.9-6173.17" + attribute \src "libresoc.v:6213.9-6213.17" case 1'1 case end @@ -8774,14 +8814,14 @@ module \CR_dec31_dec_sub0 sync always update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:6182.3-6191.6" - process $proc$libresoc.v:6182$129 + attribute \src "libresoc.v:6222.3-6231.6" + process $proc$libresoc.v:6222$129 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6183.5-6183.29" + attribute \src "libresoc.v:6223.5-6223.29" switch \initial - attribute \src "libresoc.v:6183.9-6183.17" + attribute \src "libresoc.v:6223.9-6223.17" case 1'1 case end @@ -8797,14 +8837,14 @@ module \CR_dec31_dec_sub0 sync always update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:6192.3-6201.6" - process $proc$libresoc.v:6192$130 + attribute \src "libresoc.v:6232.3-6241.6" + process $proc$libresoc.v:6232$130 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6193.5-6193.29" + attribute \src "libresoc.v:6233.5-6233.29" switch \initial - attribute \src "libresoc.v:6193.9-6193.17" + attribute \src "libresoc.v:6233.9-6233.17" case 1'1 case end @@ -8820,14 +8860,14 @@ module \CR_dec31_dec_sub0 sync always update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:6202.3-6211.6" - process $proc$libresoc.v:6202$131 + attribute \src "libresoc.v:6242.3-6251.6" + process $proc$libresoc.v:6242$131 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:6203.5-6203.29" + attribute \src "libresoc.v:6243.5-6243.29" switch \initial - attribute \src "libresoc.v:6203.9-6203.17" + attribute \src "libresoc.v:6243.9-6243.17" case 1'1 case end @@ -8845,32 +8885,32 @@ module \CR_dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:6217.1-6862.10" +attribute \src "libresoc.v:6257.1-6904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" attribute \generator "nMigen" module \CR_dec31_dec_sub15 - attribute \src "libresoc.v:6552.3-6654.6" + attribute \src "libresoc.v:6594.3-6696.6" wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6655.3-6757.6" + attribute \src "libresoc.v:6697.3-6799.6" wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6346.3-6448.6" - wire width 13 $0\CR_dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:6449.3-6551.6" + attribute \src "libresoc.v:6388.3-6490.6" + wire width 14 $0\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6491.3-6593.6" wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6758.3-6860.6" + attribute \src "libresoc.v:6800.3-6902.6" wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:6218.7-6218.20" + attribute \src "libresoc.v:6258.7-6258.20" wire $0\initial[0:0] - attribute \src "libresoc.v:6552.3-6654.6" + attribute \src "libresoc.v:6594.3-6696.6" wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6655.3-6757.6" + attribute \src "libresoc.v:6697.3-6799.6" wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6346.3-6448.6" - wire width 13 $1\CR_dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:6449.3-6551.6" + attribute \src "libresoc.v:6388.3-6490.6" + wire width 14 $1\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6491.3-6593.6" wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6758.3-6860.6" + attribute \src "libresoc.v:6800.3-6902.6" wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8893,21 +8933,22 @@ module \CR_dec31_dec_sub15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \CR_dec31_dec_sub15_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -8982,6 +9023,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" @@ -8990,28 +9032,28 @@ module \CR_dec31_dec_sub15 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel - attribute \src "libresoc.v:6218.7-6218.15" + attribute \src "libresoc.v:6258.7-6258.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:6218.7-6218.20" - process $proc$libresoc.v:6218$138 + attribute \src "libresoc.v:6258.7-6258.20" + process $proc$libresoc.v:6258$138 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:6346.3-6448.6" - process $proc$libresoc.v:6346$133 + attribute \src "libresoc.v:6388.3-6490.6" + process $proc$libresoc.v:6388$133 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub15_function_unit[12:0] $1\CR_dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:6347.5-6347.29" + assign $0\CR_dec31_dec_sub15_function_unit[13:0] $1\CR_dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:6389.5-6389.29" switch \initial - attribute \src "libresoc.v:6347.9-6347.17" + attribute \src "libresoc.v:6389.9-6389.17" case 1'1 case end @@ -9020,145 +9062,145 @@ module \CR_dec31_dec_sub15 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000000000000 + assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[12:0] + update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:6449.3-6551.6" - process $proc$libresoc.v:6449$134 + attribute \src "libresoc.v:6491.3-6593.6" + process $proc$libresoc.v:6491$134 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6450.5-6450.29" + attribute \src "libresoc.v:6492.5-6492.29" switch \initial - attribute \src "libresoc.v:6450.9-6450.17" + attribute \src "libresoc.v:6492.9-6492.17" case 1'1 case end @@ -9298,14 +9340,14 @@ module \CR_dec31_dec_sub15 sync always update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:6552.3-6654.6" - process $proc$libresoc.v:6552$135 + attribute \src "libresoc.v:6594.3-6696.6" + process $proc$libresoc.v:6594$135 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6553.5-6553.29" + attribute \src "libresoc.v:6595.5-6595.29" switch \initial - attribute \src "libresoc.v:6553.9-6553.17" + attribute \src "libresoc.v:6595.9-6595.17" case 1'1 case end @@ -9445,14 +9487,14 @@ module \CR_dec31_dec_sub15 sync always update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:6655.3-6757.6" - process $proc$libresoc.v:6655$136 + attribute \src "libresoc.v:6697.3-6799.6" + process $proc$libresoc.v:6697$136 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6656.5-6656.29" + attribute \src "libresoc.v:6698.5-6698.29" switch \initial - attribute \src "libresoc.v:6656.9-6656.17" + attribute \src "libresoc.v:6698.9-6698.17" case 1'1 case end @@ -9592,14 +9634,14 @@ module \CR_dec31_dec_sub15 sync always update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:6758.3-6860.6" - process $proc$libresoc.v:6758$137 + attribute \src "libresoc.v:6800.3-6902.6" + process $proc$libresoc.v:6800$137 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:6759.5-6759.29" + attribute \src "libresoc.v:6801.5-6801.29" switch \initial - attribute \src "libresoc.v:6759.9-6759.17" + attribute \src "libresoc.v:6801.9-6801.17" case 1'1 case end @@ -9741,32 +9783,32 @@ module \CR_dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:6866.1-7046.10" +attribute \src "libresoc.v:6908.1-7090.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" attribute \generator "nMigen" module \CR_dec31_dec_sub16 - attribute \src "libresoc.v:7015.3-7024.6" + attribute \src "libresoc.v:7059.3-7068.6" wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:7025.3-7034.6" + attribute \src "libresoc.v:7069.3-7078.6" wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:6995.3-7004.6" - wire width 13 $0\CR_dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:7005.3-7014.6" + attribute \src "libresoc.v:7039.3-7048.6" + wire width 14 $0\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7049.3-7058.6" wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:7035.3-7044.6" + attribute \src "libresoc.v:7079.3-7088.6" wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:6867.7-6867.20" + attribute \src "libresoc.v:6909.7-6909.20" wire $0\initial[0:0] - attribute \src "libresoc.v:7015.3-7024.6" + attribute \src "libresoc.v:7059.3-7068.6" wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:7025.3-7034.6" + attribute \src "libresoc.v:7069.3-7078.6" wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:6995.3-7004.6" - wire width 13 $1\CR_dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:7005.3-7014.6" + attribute \src "libresoc.v:7039.3-7048.6" + wire width 14 $1\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7049.3-7058.6" wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:7035.3-7044.6" + attribute \src "libresoc.v:7079.3-7088.6" wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -9789,21 +9831,22 @@ module \CR_dec31_dec_sub16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \CR_dec31_dec_sub16_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -9878,6 +9921,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" @@ -9886,28 +9930,28 @@ module \CR_dec31_dec_sub16 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel - attribute \src "libresoc.v:6867.7-6867.15" + attribute \src "libresoc.v:6909.7-6909.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:6867.7-6867.20" - process $proc$libresoc.v:6867$144 + attribute \src "libresoc.v:6909.7-6909.20" + process $proc$libresoc.v:6909$144 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:6995.3-7004.6" - process $proc$libresoc.v:6995$139 + attribute \src "libresoc.v:7039.3-7048.6" + process $proc$libresoc.v:7039$139 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub16_function_unit[12:0] $1\CR_dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:6996.5-6996.29" + assign $0\CR_dec31_dec_sub16_function_unit[13:0] $1\CR_dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:7040.5-7040.29" switch \initial - attribute \src "libresoc.v:6996.9-6996.17" + attribute \src "libresoc.v:7040.9-7040.17" case 1'1 case end @@ -9916,21 +9960,21 @@ module \CR_dec31_dec_sub16 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\CR_dec31_dec_sub16_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub16_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec31_dec_sub16_function_unit[12:0] 13'0000000000000 + assign $1\CR_dec31_dec_sub16_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[12:0] + update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:7005.3-7014.6" - process $proc$libresoc.v:7005$140 + attribute \src "libresoc.v:7049.3-7058.6" + process $proc$libresoc.v:7049$140 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:7006.5-7006.29" + attribute \src "libresoc.v:7050.5-7050.29" switch \initial - attribute \src "libresoc.v:7006.9-7006.17" + attribute \src "libresoc.v:7050.9-7050.17" case 1'1 case end @@ -9946,14 +9990,14 @@ module \CR_dec31_dec_sub16 sync always update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:7015.3-7024.6" - process $proc$libresoc.v:7015$141 + attribute \src "libresoc.v:7059.3-7068.6" + process $proc$libresoc.v:7059$141 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:7016.5-7016.29" + attribute \src "libresoc.v:7060.5-7060.29" switch \initial - attribute \src "libresoc.v:7016.9-7016.17" + attribute \src "libresoc.v:7060.9-7060.17" case 1'1 case end @@ -9969,14 +10013,14 @@ module \CR_dec31_dec_sub16 sync always update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:7025.3-7034.6" - process $proc$libresoc.v:7025$142 + attribute \src "libresoc.v:7069.3-7078.6" + process $proc$libresoc.v:7069$142 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:7026.5-7026.29" + attribute \src "libresoc.v:7070.5-7070.29" switch \initial - attribute \src "libresoc.v:7026.9-7026.17" + attribute \src "libresoc.v:7070.9-7070.17" case 1'1 case end @@ -9992,14 +10036,14 @@ module \CR_dec31_dec_sub16 sync always update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:7035.3-7044.6" - process $proc$libresoc.v:7035$143 + attribute \src "libresoc.v:7079.3-7088.6" + process $proc$libresoc.v:7079$143 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:7036.5-7036.29" + attribute \src "libresoc.v:7080.5-7080.29" switch \initial - attribute \src "libresoc.v:7036.9-7036.17" + attribute \src "libresoc.v:7080.9-7080.17" case 1'1 case end @@ -10017,32 +10061,32 @@ module \CR_dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:7050.1-7230.10" +attribute \src "libresoc.v:7094.1-7276.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" attribute \generator "nMigen" module \CR_dec31_dec_sub19 - attribute \src "libresoc.v:7199.3-7208.6" + attribute \src "libresoc.v:7245.3-7254.6" wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7209.3-7218.6" + attribute \src "libresoc.v:7255.3-7264.6" wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7179.3-7188.6" - wire width 13 $0\CR_dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:7189.3-7198.6" + attribute \src "libresoc.v:7225.3-7234.6" + wire width 14 $0\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7235.3-7244.6" wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7219.3-7228.6" + attribute \src "libresoc.v:7265.3-7274.6" wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:7051.7-7051.20" + attribute \src "libresoc.v:7095.7-7095.20" wire $0\initial[0:0] - attribute \src "libresoc.v:7199.3-7208.6" + attribute \src "libresoc.v:7245.3-7254.6" wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7209.3-7218.6" + attribute \src "libresoc.v:7255.3-7264.6" wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7179.3-7188.6" - wire width 13 $1\CR_dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:7189.3-7198.6" + attribute \src "libresoc.v:7225.3-7234.6" + wire width 14 $1\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7235.3-7244.6" wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7219.3-7228.6" + attribute \src "libresoc.v:7265.3-7274.6" wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10065,21 +10109,22 @@ module \CR_dec31_dec_sub19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \CR_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -10154,6 +10199,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" @@ -10162,28 +10208,28 @@ module \CR_dec31_dec_sub19 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:7051.7-7051.15" + attribute \src "libresoc.v:7095.7-7095.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:7051.7-7051.20" - process $proc$libresoc.v:7051$150 + attribute \src "libresoc.v:7095.7-7095.20" + process $proc$libresoc.v:7095$150 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:7179.3-7188.6" - process $proc$libresoc.v:7179$145 + attribute \src "libresoc.v:7225.3-7234.6" + process $proc$libresoc.v:7225$145 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub19_function_unit[12:0] $1\CR_dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:7180.5-7180.29" + assign $0\CR_dec31_dec_sub19_function_unit[13:0] $1\CR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:7226.5-7226.29" switch \initial - attribute \src "libresoc.v:7180.9-7180.17" + attribute \src "libresoc.v:7226.9-7226.17" case 1'1 case end @@ -10192,21 +10238,21 @@ module \CR_dec31_dec_sub19 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\CR_dec31_dec_sub19_function_unit[12:0] 13'0000001000000 + assign $1\CR_dec31_dec_sub19_function_unit[13:0] 14'00000001000000 case - assign $1\CR_dec31_dec_sub19_function_unit[12:0] 13'0000000000000 + assign $1\CR_dec31_dec_sub19_function_unit[13:0] 14'00000000000000 end sync always - update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[12:0] + update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:7189.3-7198.6" - process $proc$libresoc.v:7189$146 + attribute \src "libresoc.v:7235.3-7244.6" + process $proc$libresoc.v:7235$146 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7190.5-7190.29" + attribute \src "libresoc.v:7236.5-7236.29" switch \initial - attribute \src "libresoc.v:7190.9-7190.17" + attribute \src "libresoc.v:7236.9-7236.17" case 1'1 case end @@ -10222,14 +10268,14 @@ module \CR_dec31_dec_sub19 sync always update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:7199.3-7208.6" - process $proc$libresoc.v:7199$147 + attribute \src "libresoc.v:7245.3-7254.6" + process $proc$libresoc.v:7245$147 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7200.5-7200.29" + attribute \src "libresoc.v:7246.5-7246.29" switch \initial - attribute \src "libresoc.v:7200.9-7200.17" + attribute \src "libresoc.v:7246.9-7246.17" case 1'1 case end @@ -10245,14 +10291,14 @@ module \CR_dec31_dec_sub19 sync always update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:7209.3-7218.6" - process $proc$libresoc.v:7209$148 + attribute \src "libresoc.v:7255.3-7264.6" + process $proc$libresoc.v:7255$148 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7210.5-7210.29" + attribute \src "libresoc.v:7256.5-7256.29" switch \initial - attribute \src "libresoc.v:7210.9-7210.17" + attribute \src "libresoc.v:7256.9-7256.17" case 1'1 case end @@ -10268,14 +10314,14 @@ module \CR_dec31_dec_sub19 sync always update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:7219.3-7228.6" - process $proc$libresoc.v:7219$149 + attribute \src "libresoc.v:7265.3-7274.6" + process $proc$libresoc.v:7265$149 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:7220.5-7220.29" + attribute \src "libresoc.v:7266.5-7266.29" switch \initial - attribute \src "libresoc.v:7220.9-7220.17" + attribute \src "libresoc.v:7266.9-7266.17" case 1'1 case end @@ -10293,68 +10339,68 @@ module \CR_dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:7234.1-7981.10" +attribute \src "libresoc.v:7280.1-8033.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" attribute \generator "nMigen" module \DIV_dec31 - attribute \src "libresoc.v:7951.3-7963.6" + attribute \src "libresoc.v:8003.3-8015.6" wire width 3 $0\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7964.3-7976.6" + attribute \src "libresoc.v:8016.3-8028.6" wire width 3 $0\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7821.3-7833.6" + attribute \src "libresoc.v:7873.3-7885.6" wire width 2 $0\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7860.3-7872.6" + attribute \src "libresoc.v:7912.3-7924.6" wire $0\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7899.3-7911.6" - wire width 13 $0\DIV_dec31_function_unit[12:0] - attribute \src "libresoc.v:7925.3-7937.6" + attribute \src "libresoc.v:7951.3-7963.6" + wire width 14 $0\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7977.3-7989.6" wire width 3 $0\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7938.3-7950.6" + attribute \src "libresoc.v:7990.3-8002.6" wire width 4 $0\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7912.3-7924.6" + attribute \src "libresoc.v:7964.3-7976.6" wire width 7 $0\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7834.3-7846.6" + attribute \src "libresoc.v:7886.3-7898.6" wire $0\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7847.3-7859.6" + attribute \src "libresoc.v:7899.3-7911.6" wire $0\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7873.3-7885.6" + attribute \src "libresoc.v:7925.3-7937.6" wire $0\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7795.3-7807.6" + attribute \src "libresoc.v:7847.3-7859.6" wire width 4 $0\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7808.3-7820.6" + attribute \src "libresoc.v:7860.3-7872.6" wire width 2 $0\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7886.3-7898.6" + attribute \src "libresoc.v:7938.3-7950.6" wire $0\DIV_dec31_sgn[0:0] - attribute \src "libresoc.v:7235.7-7235.20" + attribute \src "libresoc.v:7281.7-7281.20" wire $0\initial[0:0] - attribute \src "libresoc.v:7951.3-7963.6" + attribute \src "libresoc.v:8003.3-8015.6" wire width 3 $1\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7964.3-7976.6" + attribute \src "libresoc.v:8016.3-8028.6" wire width 3 $1\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7821.3-7833.6" + attribute \src "libresoc.v:7873.3-7885.6" wire width 2 $1\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7860.3-7872.6" + attribute \src "libresoc.v:7912.3-7924.6" wire $1\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7899.3-7911.6" - wire width 13 $1\DIV_dec31_function_unit[12:0] - attribute \src "libresoc.v:7925.3-7937.6" + attribute \src "libresoc.v:7951.3-7963.6" + wire width 14 $1\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7977.3-7989.6" wire width 3 $1\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7938.3-7950.6" + attribute \src "libresoc.v:7990.3-8002.6" wire width 4 $1\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7912.3-7924.6" + attribute \src "libresoc.v:7964.3-7976.6" wire width 7 $1\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7834.3-7846.6" + attribute \src "libresoc.v:7886.3-7898.6" wire $1\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7847.3-7859.6" + attribute \src "libresoc.v:7899.3-7911.6" wire $1\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7873.3-7885.6" + attribute \src "libresoc.v:7925.3-7937.6" wire $1\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7795.3-7807.6" + attribute \src "libresoc.v:7847.3-7859.6" wire width 4 $1\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7808.3-7820.6" + attribute \src "libresoc.v:7860.3-7872.6" wire width 2 $1\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7886.3-7898.6" + attribute \src "libresoc.v:7938.3-7950.6" wire $1\DIV_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10413,21 +10459,22 @@ module \DIV_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -10527,6 +10574,7 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -10582,21 +10630,22 @@ module \DIV_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -10696,6 +10745,7 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -10723,21 +10773,22 @@ module \DIV_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \DIV_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \DIV_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -10837,6 +10888,7 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \DIV_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -10861,7 +10913,7 @@ module \DIV_dec31 wire width 2 output 8 \DIV_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \DIV_dec31_sgn - attribute \src "libresoc.v:7235.7-7235.15" + attribute \src "libresoc.v:7281.7-7281.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -10870,7 +10922,7 @@ module \DIV_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:7761.23-7777.4" + attribute \src "libresoc.v:7813.23-7829.4" cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out @@ -10889,7 +10941,7 @@ module \DIV_dec31 connect \opcode_in \DIV_dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:7778.22-7794.4" + attribute \src "libresoc.v:7830.22-7846.4" cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out @@ -10907,22 +10959,22 @@ module \DIV_dec31 connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn connect \opcode_in \DIV_dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:7235.7-7235.20" - process $proc$libresoc.v:7235$165 + attribute \src "libresoc.v:7281.7-7281.20" + process $proc$libresoc.v:7281$165 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:7795.3-7807.6" - process $proc$libresoc.v:7795$151 + attribute \src "libresoc.v:7847.3-7859.6" + process $proc$libresoc.v:7847$151 assign { } { } assign { } { } assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7796.5-7796.29" + attribute \src "libresoc.v:7848.5-7848.29" switch \initial - attribute \src "libresoc.v:7796.9-7796.17" + attribute \src "libresoc.v:7848.9-7848.17" case 1'1 case end @@ -10942,14 +10994,14 @@ module \DIV_dec31 sync always update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] end - attribute \src "libresoc.v:7808.3-7820.6" - process $proc$libresoc.v:7808$152 + attribute \src "libresoc.v:7860.3-7872.6" + process $proc$libresoc.v:7860$152 assign { } { } assign { } { } assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7809.5-7809.29" + attribute \src "libresoc.v:7861.5-7861.29" switch \initial - attribute \src "libresoc.v:7809.9-7809.17" + attribute \src "libresoc.v:7861.9-7861.17" case 1'1 case end @@ -10969,14 +11021,14 @@ module \DIV_dec31 sync always update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:7821.3-7833.6" - process $proc$libresoc.v:7821$153 + attribute \src "libresoc.v:7873.3-7885.6" + process $proc$libresoc.v:7873$153 assign { } { } assign { } { } assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7822.5-7822.29" + attribute \src "libresoc.v:7874.5-7874.29" switch \initial - attribute \src "libresoc.v:7822.9-7822.17" + attribute \src "libresoc.v:7874.9-7874.17" case 1'1 case end @@ -10996,14 +11048,14 @@ module \DIV_dec31 sync always update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] end - attribute \src "libresoc.v:7834.3-7846.6" - process $proc$libresoc.v:7834$154 + attribute \src "libresoc.v:7886.3-7898.6" + process $proc$libresoc.v:7886$154 assign { } { } assign { } { } assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7835.5-7835.29" + attribute \src "libresoc.v:7887.5-7887.29" switch \initial - attribute \src "libresoc.v:7835.9-7835.17" + attribute \src "libresoc.v:7887.9-7887.17" case 1'1 case end @@ -11023,14 +11075,14 @@ module \DIV_dec31 sync always update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] end - attribute \src "libresoc.v:7847.3-7859.6" - process $proc$libresoc.v:7847$155 + attribute \src "libresoc.v:7899.3-7911.6" + process $proc$libresoc.v:7899$155 assign { } { } assign { } { } assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7848.5-7848.29" + attribute \src "libresoc.v:7900.5-7900.29" switch \initial - attribute \src "libresoc.v:7848.9-7848.17" + attribute \src "libresoc.v:7900.9-7900.17" case 1'1 case end @@ -11050,14 +11102,14 @@ module \DIV_dec31 sync always update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] end - attribute \src "libresoc.v:7860.3-7872.6" - process $proc$libresoc.v:7860$156 + attribute \src "libresoc.v:7912.3-7924.6" + process $proc$libresoc.v:7912$156 assign { } { } assign { } { } assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7861.5-7861.29" + attribute \src "libresoc.v:7913.5-7913.29" switch \initial - attribute \src "libresoc.v:7861.9-7861.17" + attribute \src "libresoc.v:7913.9-7913.17" case 1'1 case end @@ -11077,14 +11129,14 @@ module \DIV_dec31 sync always update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] end - attribute \src "libresoc.v:7873.3-7885.6" - process $proc$libresoc.v:7873$157 + attribute \src "libresoc.v:7925.3-7937.6" + process $proc$libresoc.v:7925$157 assign { } { } assign { } { } assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7874.5-7874.29" + attribute \src "libresoc.v:7926.5-7926.29" switch \initial - attribute \src "libresoc.v:7874.9-7874.17" + attribute \src "libresoc.v:7926.9-7926.17" case 1'1 case end @@ -11104,14 +11156,14 @@ module \DIV_dec31 sync always update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] end - attribute \src "libresoc.v:7886.3-7898.6" - process $proc$libresoc.v:7886$158 + attribute \src "libresoc.v:7938.3-7950.6" + process $proc$libresoc.v:7938$158 assign { } { } assign { } { } assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] - attribute \src "libresoc.v:7887.5-7887.29" + attribute \src "libresoc.v:7939.5-7939.29" switch \initial - attribute \src "libresoc.v:7887.9-7887.17" + attribute \src "libresoc.v:7939.9-7939.17" case 1'1 case end @@ -11131,14 +11183,14 @@ module \DIV_dec31 sync always update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] end - attribute \src "libresoc.v:7899.3-7911.6" - process $proc$libresoc.v:7899$159 + attribute \src "libresoc.v:7951.3-7963.6" + process $proc$libresoc.v:7951$159 assign { } { } assign { } { } - assign $0\DIV_dec31_function_unit[12:0] $1\DIV_dec31_function_unit[12:0] - attribute \src "libresoc.v:7900.5-7900.29" + assign $0\DIV_dec31_function_unit[13:0] $1\DIV_dec31_function_unit[13:0] + attribute \src "libresoc.v:7952.5-7952.29" switch \initial - attribute \src "libresoc.v:7900.9-7900.17" + attribute \src "libresoc.v:7952.9-7952.17" case 1'1 case end @@ -11147,25 +11199,25 @@ module \DIV_dec31 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\DIV_dec31_function_unit[12:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + assign $1\DIV_dec31_function_unit[13:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\DIV_dec31_function_unit[12:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + assign $1\DIV_dec31_function_unit[13:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit case - assign $1\DIV_dec31_function_unit[12:0] 13'0000000000000 + assign $1\DIV_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[12:0] + update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[13:0] end - attribute \src "libresoc.v:7912.3-7924.6" - process $proc$libresoc.v:7912$160 + attribute \src "libresoc.v:7964.3-7976.6" + process $proc$libresoc.v:7964$160 assign { } { } assign { } { } assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7913.5-7913.29" + attribute \src "libresoc.v:7965.5-7965.29" switch \initial - attribute \src "libresoc.v:7913.9-7913.17" + attribute \src "libresoc.v:7965.9-7965.17" case 1'1 case end @@ -11185,14 +11237,14 @@ module \DIV_dec31 sync always update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] end - attribute \src "libresoc.v:7925.3-7937.6" - process $proc$libresoc.v:7925$161 + attribute \src "libresoc.v:7977.3-7989.6" + process $proc$libresoc.v:7977$161 assign { } { } assign { } { } assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7926.5-7926.29" + attribute \src "libresoc.v:7978.5-7978.29" switch \initial - attribute \src "libresoc.v:7926.9-7926.17" + attribute \src "libresoc.v:7978.9-7978.17" case 1'1 case end @@ -11212,14 +11264,14 @@ module \DIV_dec31 sync always update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] end - attribute \src "libresoc.v:7938.3-7950.6" - process $proc$libresoc.v:7938$162 + attribute \src "libresoc.v:7990.3-8002.6" + process $proc$libresoc.v:7990$162 assign { } { } assign { } { } assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7939.5-7939.29" + attribute \src "libresoc.v:7991.5-7991.29" switch \initial - attribute \src "libresoc.v:7939.9-7939.17" + attribute \src "libresoc.v:7991.9-7991.17" case 1'1 case end @@ -11239,14 +11291,14 @@ module \DIV_dec31 sync always update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:7951.3-7963.6" - process $proc$libresoc.v:7951$163 + attribute \src "libresoc.v:8003.3-8015.6" + process $proc$libresoc.v:8003$163 assign { } { } assign { } { } assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7952.5-7952.29" + attribute \src "libresoc.v:8004.5-8004.29" switch \initial - attribute \src "libresoc.v:7952.9-7952.17" + attribute \src "libresoc.v:8004.9-8004.17" case 1'1 case end @@ -11266,14 +11318,14 @@ module \DIV_dec31 sync always update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] end - attribute \src "libresoc.v:7964.3-7976.6" - process $proc$libresoc.v:7964$164 + attribute \src "libresoc.v:8016.3-8028.6" + process $proc$libresoc.v:8016$164 assign { } { } assign { } { } assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7965.5-7965.29" + attribute \src "libresoc.v:8017.5-8017.29" switch \initial - attribute \src "libresoc.v:7965.9-7965.17" + attribute \src "libresoc.v:8017.9-8017.17" case 1'1 case end @@ -11298,68 +11350,68 @@ module \DIV_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:7985.1-8691.10" +attribute \src "libresoc.v:8037.1-8745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" attribute \generator "nMigen" module \DIV_dec31_dec_sub11 - attribute \src "libresoc.v:8505.3-8541.6" + attribute \src "libresoc.v:8559.3-8595.6" wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8542.3-8578.6" + attribute \src "libresoc.v:8596.3-8632.6" wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8653.3-8689.6" + attribute \src "libresoc.v:8707.3-8743.6" wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8283.3-8319.6" + attribute \src "libresoc.v:8337.3-8373.6" wire $0\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8172.3-8208.6" - wire width 13 $0\DIV_dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:8431.3-8467.6" + attribute \src "libresoc.v:8226.3-8262.6" + wire width 14 $0\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8485.3-8521.6" wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8468.3-8504.6" + attribute \src "libresoc.v:8522.3-8558.6" wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8394.3-8430.6" + attribute \src "libresoc.v:8448.3-8484.6" wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8209.3-8245.6" + attribute \src "libresoc.v:8263.3-8299.6" wire $0\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8246.3-8282.6" + attribute \src "libresoc.v:8300.3-8336.6" wire $0\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8320.3-8356.6" + attribute \src "libresoc.v:8374.3-8410.6" wire $0\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8579.3-8615.6" + attribute \src "libresoc.v:8633.3-8669.6" wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8616.3-8652.6" + attribute \src "libresoc.v:8670.3-8706.6" wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8357.3-8393.6" + attribute \src "libresoc.v:8411.3-8447.6" wire $0\DIV_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:7986.7-7986.20" + attribute \src "libresoc.v:8038.7-8038.20" wire $0\initial[0:0] - attribute \src "libresoc.v:8505.3-8541.6" + attribute \src "libresoc.v:8559.3-8595.6" wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8542.3-8578.6" + attribute \src "libresoc.v:8596.3-8632.6" wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8653.3-8689.6" + attribute \src "libresoc.v:8707.3-8743.6" wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8283.3-8319.6" + attribute \src "libresoc.v:8337.3-8373.6" wire $1\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8172.3-8208.6" - wire width 13 $1\DIV_dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:8431.3-8467.6" + attribute \src "libresoc.v:8226.3-8262.6" + wire width 14 $1\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8485.3-8521.6" wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8468.3-8504.6" + attribute \src "libresoc.v:8522.3-8558.6" wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8394.3-8430.6" + attribute \src "libresoc.v:8448.3-8484.6" wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8209.3-8245.6" + attribute \src "libresoc.v:8263.3-8299.6" wire $1\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8246.3-8282.6" + attribute \src "libresoc.v:8300.3-8336.6" wire $1\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8320.3-8356.6" + attribute \src "libresoc.v:8374.3-8410.6" wire $1\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8579.3-8615.6" + attribute \src "libresoc.v:8633.3-8669.6" wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8616.3-8652.6" + attribute \src "libresoc.v:8670.3-8706.6" wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8357.3-8393.6" + attribute \src "libresoc.v:8411.3-8447.6" wire $1\DIV_dec31_dec_sub11_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -11390,21 +11442,22 @@ module \DIV_dec31_dec_sub11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \DIV_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -11504,6 +11557,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -11528,28 +11582,28 @@ module \DIV_dec31_dec_sub11 wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \DIV_dec31_dec_sub11_sgn - attribute \src "libresoc.v:7986.7-7986.15" + attribute \src "libresoc.v:8038.7-8038.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:7986.7-7986.20" - process $proc$libresoc.v:7986$180 + attribute \src "libresoc.v:8038.7-8038.20" + process $proc$libresoc.v:8038$180 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:8172.3-8208.6" - process $proc$libresoc.v:8172$166 + attribute \src "libresoc.v:8226.3-8262.6" + process $proc$libresoc.v:8226$166 assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub11_function_unit[12:0] $1\DIV_dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:8173.5-8173.29" + assign $0\DIV_dec31_dec_sub11_function_unit[13:0] $1\DIV_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:8227.5-8227.29" switch \initial - attribute \src "libresoc.v:8173.9-8173.17" + attribute \src "libresoc.v:8227.9-8227.17" case 1'1 case end @@ -11558,57 +11612,57 @@ module \DIV_dec31_dec_sub11 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 case - assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0000000000000 + assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always - update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[12:0] + update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:8209.3-8245.6" - process $proc$libresoc.v:8209$167 + attribute \src "libresoc.v:8263.3-8299.6" + process $proc$libresoc.v:8263$167 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8210.5-8210.29" + attribute \src "libresoc.v:8264.5-8264.29" switch \initial - attribute \src "libresoc.v:8210.9-8210.17" + attribute \src "libresoc.v:8264.9-8264.17" case 1'1 case end @@ -11660,14 +11714,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:8246.3-8282.6" - process $proc$libresoc.v:8246$168 + attribute \src "libresoc.v:8300.3-8336.6" + process $proc$libresoc.v:8300$168 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8247.5-8247.29" + attribute \src "libresoc.v:8301.5-8301.29" switch \initial - attribute \src "libresoc.v:8247.9-8247.17" + attribute \src "libresoc.v:8301.9-8301.17" case 1'1 case end @@ -11719,14 +11773,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:8283.3-8319.6" - process $proc$libresoc.v:8283$169 + attribute \src "libresoc.v:8337.3-8373.6" + process $proc$libresoc.v:8337$169 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8284.5-8284.29" + attribute \src "libresoc.v:8338.5-8338.29" switch \initial - attribute \src "libresoc.v:8284.9-8284.17" + attribute \src "libresoc.v:8338.9-8338.17" case 1'1 case end @@ -11778,14 +11832,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:8320.3-8356.6" - process $proc$libresoc.v:8320$170 + attribute \src "libresoc.v:8374.3-8410.6" + process $proc$libresoc.v:8374$170 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8321.5-8321.29" + attribute \src "libresoc.v:8375.5-8375.29" switch \initial - attribute \src "libresoc.v:8321.9-8321.17" + attribute \src "libresoc.v:8375.9-8375.17" case 1'1 case end @@ -11837,14 +11891,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:8357.3-8393.6" - process $proc$libresoc.v:8357$171 + attribute \src "libresoc.v:8411.3-8447.6" + process $proc$libresoc.v:8411$171 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:8358.5-8358.29" + attribute \src "libresoc.v:8412.5-8412.29" switch \initial - attribute \src "libresoc.v:8358.9-8358.17" + attribute \src "libresoc.v:8412.9-8412.17" case 1'1 case end @@ -11896,14 +11950,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:8394.3-8430.6" - process $proc$libresoc.v:8394$172 + attribute \src "libresoc.v:8448.3-8484.6" + process $proc$libresoc.v:8448$172 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8395.5-8395.29" + attribute \src "libresoc.v:8449.5-8449.29" switch \initial - attribute \src "libresoc.v:8395.9-8395.17" + attribute \src "libresoc.v:8449.9-8449.17" case 1'1 case end @@ -11955,14 +12009,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:8431.3-8467.6" - process $proc$libresoc.v:8431$173 + attribute \src "libresoc.v:8485.3-8521.6" + process $proc$libresoc.v:8485$173 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8432.5-8432.29" + attribute \src "libresoc.v:8486.5-8486.29" switch \initial - attribute \src "libresoc.v:8432.9-8432.17" + attribute \src "libresoc.v:8486.9-8486.17" case 1'1 case end @@ -12014,14 +12068,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:8468.3-8504.6" - process $proc$libresoc.v:8468$174 + attribute \src "libresoc.v:8522.3-8558.6" + process $proc$libresoc.v:8522$174 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8469.5-8469.29" + attribute \src "libresoc.v:8523.5-8523.29" switch \initial - attribute \src "libresoc.v:8469.9-8469.17" + attribute \src "libresoc.v:8523.9-8523.17" case 1'1 case end @@ -12073,14 +12127,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:8505.3-8541.6" - process $proc$libresoc.v:8505$175 + attribute \src "libresoc.v:8559.3-8595.6" + process $proc$libresoc.v:8559$175 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8506.5-8506.29" + attribute \src "libresoc.v:8560.5-8560.29" switch \initial - attribute \src "libresoc.v:8506.9-8506.17" + attribute \src "libresoc.v:8560.9-8560.17" case 1'1 case end @@ -12132,14 +12186,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:8542.3-8578.6" - process $proc$libresoc.v:8542$176 + attribute \src "libresoc.v:8596.3-8632.6" + process $proc$libresoc.v:8596$176 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8543.5-8543.29" + attribute \src "libresoc.v:8597.5-8597.29" switch \initial - attribute \src "libresoc.v:8543.9-8543.17" + attribute \src "libresoc.v:8597.9-8597.17" case 1'1 case end @@ -12191,14 +12245,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:8579.3-8615.6" - process $proc$libresoc.v:8579$177 + attribute \src "libresoc.v:8633.3-8669.6" + process $proc$libresoc.v:8633$177 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8580.5-8580.29" + attribute \src "libresoc.v:8634.5-8634.29" switch \initial - attribute \src "libresoc.v:8580.9-8580.17" + attribute \src "libresoc.v:8634.9-8634.17" case 1'1 case end @@ -12250,14 +12304,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:8616.3-8652.6" - process $proc$libresoc.v:8616$178 + attribute \src "libresoc.v:8670.3-8706.6" + process $proc$libresoc.v:8670$178 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8617.5-8617.29" + attribute \src "libresoc.v:8671.5-8671.29" switch \initial - attribute \src "libresoc.v:8617.9-8617.17" + attribute \src "libresoc.v:8671.9-8671.17" case 1'1 case end @@ -12309,14 +12363,14 @@ module \DIV_dec31_dec_sub11 sync always update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:8653.3-8689.6" - process $proc$libresoc.v:8653$179 + attribute \src "libresoc.v:8707.3-8743.6" + process $proc$libresoc.v:8707$179 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8654.5-8654.29" + attribute \src "libresoc.v:8708.5-8708.29" switch \initial - attribute \src "libresoc.v:8654.9-8654.17" + attribute \src "libresoc.v:8708.9-8708.17" case 1'1 case end @@ -12370,68 +12424,68 @@ module \DIV_dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:8695.1-9401.10" +attribute \src "libresoc.v:8749.1-9457.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" attribute \generator "nMigen" module \DIV_dec31_dec_sub9 - attribute \src "libresoc.v:9215.3-9251.6" + attribute \src "libresoc.v:9271.3-9307.6" wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9252.3-9288.6" + attribute \src "libresoc.v:9308.3-9344.6" wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9363.3-9399.6" + attribute \src "libresoc.v:9419.3-9455.6" wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:8993.3-9029.6" + attribute \src "libresoc.v:9049.3-9085.6" wire $0\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8882.3-8918.6" - wire width 13 $0\DIV_dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:9141.3-9177.6" + attribute \src "libresoc.v:8938.3-8974.6" + wire width 14 $0\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:9197.3-9233.6" wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9178.3-9214.6" + attribute \src "libresoc.v:9234.3-9270.6" wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9104.3-9140.6" + attribute \src "libresoc.v:9160.3-9196.6" wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:8919.3-8955.6" + attribute \src "libresoc.v:8975.3-9011.6" wire $0\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8956.3-8992.6" + attribute \src "libresoc.v:9012.3-9048.6" wire $0\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:9030.3-9066.6" + attribute \src "libresoc.v:9086.3-9122.6" wire $0\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:9289.3-9325.6" + attribute \src "libresoc.v:9345.3-9381.6" wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9326.3-9362.6" + attribute \src "libresoc.v:9382.3-9418.6" wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:9067.3-9103.6" + attribute \src "libresoc.v:9123.3-9159.6" wire $0\DIV_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:8696.7-8696.20" + attribute \src "libresoc.v:8750.7-8750.20" wire $0\initial[0:0] - attribute \src "libresoc.v:9215.3-9251.6" + attribute \src "libresoc.v:9271.3-9307.6" wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9252.3-9288.6" + attribute \src "libresoc.v:9308.3-9344.6" wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9363.3-9399.6" + attribute \src "libresoc.v:9419.3-9455.6" wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:8993.3-9029.6" + attribute \src "libresoc.v:9049.3-9085.6" wire $1\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8882.3-8918.6" - wire width 13 $1\DIV_dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:9141.3-9177.6" + attribute \src "libresoc.v:8938.3-8974.6" + wire width 14 $1\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:9197.3-9233.6" wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9178.3-9214.6" + attribute \src "libresoc.v:9234.3-9270.6" wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9104.3-9140.6" + attribute \src "libresoc.v:9160.3-9196.6" wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:8919.3-8955.6" + attribute \src "libresoc.v:8975.3-9011.6" wire $1\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8956.3-8992.6" + attribute \src "libresoc.v:9012.3-9048.6" wire $1\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:9030.3-9066.6" + attribute \src "libresoc.v:9086.3-9122.6" wire $1\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:9289.3-9325.6" + attribute \src "libresoc.v:9345.3-9381.6" wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9326.3-9362.6" + attribute \src "libresoc.v:9382.3-9418.6" wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:9067.3-9103.6" + attribute \src "libresoc.v:9123.3-9159.6" wire $1\DIV_dec31_dec_sub9_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -12462,21 +12516,22 @@ module \DIV_dec31_dec_sub9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \DIV_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -12576,6 +12631,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -12600,28 +12656,28 @@ module \DIV_dec31_dec_sub9 wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \DIV_dec31_dec_sub9_sgn - attribute \src "libresoc.v:8696.7-8696.15" + attribute \src "libresoc.v:8750.7-8750.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:8696.7-8696.20" - process $proc$libresoc.v:8696$195 + attribute \src "libresoc.v:8750.7-8750.20" + process $proc$libresoc.v:8750$195 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:8882.3-8918.6" - process $proc$libresoc.v:8882$181 + attribute \src "libresoc.v:8938.3-8974.6" + process $proc$libresoc.v:8938$181 assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub9_function_unit[12:0] $1\DIV_dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:8883.5-8883.29" + assign $0\DIV_dec31_dec_sub9_function_unit[13:0] $1\DIV_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:8939.5-8939.29" switch \initial - attribute \src "libresoc.v:8883.9-8883.17" + attribute \src "libresoc.v:8939.9-8939.17" case 1'1 case end @@ -12630,57 +12686,57 @@ module \DIV_dec31_dec_sub9 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 case - assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0000000000000 + assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always - update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[12:0] + update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:8919.3-8955.6" - process $proc$libresoc.v:8919$182 + attribute \src "libresoc.v:8975.3-9011.6" + process $proc$libresoc.v:8975$182 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8920.5-8920.29" + attribute \src "libresoc.v:8976.5-8976.29" switch \initial - attribute \src "libresoc.v:8920.9-8920.17" + attribute \src "libresoc.v:8976.9-8976.17" case 1'1 case end @@ -12732,14 +12788,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:8956.3-8992.6" - process $proc$libresoc.v:8956$183 + attribute \src "libresoc.v:9012.3-9048.6" + process $proc$libresoc.v:9012$183 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:8957.5-8957.29" + attribute \src "libresoc.v:9013.5-9013.29" switch \initial - attribute \src "libresoc.v:8957.9-8957.17" + attribute \src "libresoc.v:9013.9-9013.17" case 1'1 case end @@ -12791,14 +12847,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:8993.3-9029.6" - process $proc$libresoc.v:8993$184 + attribute \src "libresoc.v:9049.3-9085.6" + process $proc$libresoc.v:9049$184 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8994.5-8994.29" + attribute \src "libresoc.v:9050.5-9050.29" switch \initial - attribute \src "libresoc.v:8994.9-8994.17" + attribute \src "libresoc.v:9050.9-9050.17" case 1'1 case end @@ -12850,14 +12906,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:9030.3-9066.6" - process $proc$libresoc.v:9030$185 + attribute \src "libresoc.v:9086.3-9122.6" + process $proc$libresoc.v:9086$185 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:9031.5-9031.29" + attribute \src "libresoc.v:9087.5-9087.29" switch \initial - attribute \src "libresoc.v:9031.9-9031.17" + attribute \src "libresoc.v:9087.9-9087.17" case 1'1 case end @@ -12909,14 +12965,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:9067.3-9103.6" - process $proc$libresoc.v:9067$186 + attribute \src "libresoc.v:9123.3-9159.6" + process $proc$libresoc.v:9123$186 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:9068.5-9068.29" + attribute \src "libresoc.v:9124.5-9124.29" switch \initial - attribute \src "libresoc.v:9068.9-9068.17" + attribute \src "libresoc.v:9124.9-9124.17" case 1'1 case end @@ -12968,14 +13024,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:9104.3-9140.6" - process $proc$libresoc.v:9104$187 + attribute \src "libresoc.v:9160.3-9196.6" + process $proc$libresoc.v:9160$187 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:9105.5-9105.29" + attribute \src "libresoc.v:9161.5-9161.29" switch \initial - attribute \src "libresoc.v:9105.9-9105.17" + attribute \src "libresoc.v:9161.9-9161.17" case 1'1 case end @@ -13027,14 +13083,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:9141.3-9177.6" - process $proc$libresoc.v:9141$188 + attribute \src "libresoc.v:9197.3-9233.6" + process $proc$libresoc.v:9197$188 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9142.5-9142.29" + attribute \src "libresoc.v:9198.5-9198.29" switch \initial - attribute \src "libresoc.v:9142.9-9142.17" + attribute \src "libresoc.v:9198.9-9198.17" case 1'1 case end @@ -13086,14 +13142,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:9178.3-9214.6" - process $proc$libresoc.v:9178$189 + attribute \src "libresoc.v:9234.3-9270.6" + process $proc$libresoc.v:9234$189 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9179.5-9179.29" + attribute \src "libresoc.v:9235.5-9235.29" switch \initial - attribute \src "libresoc.v:9179.9-9179.17" + attribute \src "libresoc.v:9235.9-9235.17" case 1'1 case end @@ -13145,14 +13201,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:9215.3-9251.6" - process $proc$libresoc.v:9215$190 + attribute \src "libresoc.v:9271.3-9307.6" + process $proc$libresoc.v:9271$190 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9216.5-9216.29" + attribute \src "libresoc.v:9272.5-9272.29" switch \initial - attribute \src "libresoc.v:9216.9-9216.17" + attribute \src "libresoc.v:9272.9-9272.17" case 1'1 case end @@ -13204,14 +13260,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:9252.3-9288.6" - process $proc$libresoc.v:9252$191 + attribute \src "libresoc.v:9308.3-9344.6" + process $proc$libresoc.v:9308$191 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9253.5-9253.29" + attribute \src "libresoc.v:9309.5-9309.29" switch \initial - attribute \src "libresoc.v:9253.9-9253.17" + attribute \src "libresoc.v:9309.9-9309.17" case 1'1 case end @@ -13263,14 +13319,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:9289.3-9325.6" - process $proc$libresoc.v:9289$192 + attribute \src "libresoc.v:9345.3-9381.6" + process $proc$libresoc.v:9345$192 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9290.5-9290.29" + attribute \src "libresoc.v:9346.5-9346.29" switch \initial - attribute \src "libresoc.v:9290.9-9290.17" + attribute \src "libresoc.v:9346.9-9346.17" case 1'1 case end @@ -13322,14 +13378,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:9326.3-9362.6" - process $proc$libresoc.v:9326$193 + attribute \src "libresoc.v:9382.3-9418.6" + process $proc$libresoc.v:9382$193 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:9327.5-9327.29" + attribute \src "libresoc.v:9383.5-9383.29" switch \initial - attribute \src "libresoc.v:9327.9-9327.17" + attribute \src "libresoc.v:9383.9-9383.17" case 1'1 case end @@ -13381,14 +13437,14 @@ module \DIV_dec31_dec_sub9 sync always update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:9363.3-9399.6" - process $proc$libresoc.v:9363$194 + attribute \src "libresoc.v:9419.3-9455.6" + process $proc$libresoc.v:9419$194 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:9364.5-9364.29" + attribute \src "libresoc.v:9420.5-9420.29" switch \initial - attribute \src "libresoc.v:9364.9-9364.17" + attribute \src "libresoc.v:9420.9-9420.17" case 1'1 case end @@ -13442,64 +13498,64 @@ module \DIV_dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:9405.1-10581.10" +attribute \src "libresoc.v:9461.1-10647.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" attribute \generator "nMigen" module \LDST_dec31 - attribute \src "libresoc.v:10423.3-10441.6" + attribute \src "libresoc.v:10489.3-10507.6" wire $0\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10328.3-10346.6" + attribute \src "libresoc.v:10394.3-10412.6" wire width 3 $0\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10347.3-10365.6" + attribute \src "libresoc.v:10413.3-10431.6" wire width 3 $0\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10499.3-10517.6" - wire width 13 $0\LDST_dec31_function_unit[12:0] - attribute \src "libresoc.v:10537.3-10555.6" + attribute \src "libresoc.v:10565.3-10583.6" + wire width 14 $0\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10603.3-10621.6" wire width 3 $0\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10556.3-10574.6" + attribute \src "libresoc.v:10622.3-10640.6" wire width 4 $0\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10518.3-10536.6" + attribute \src "libresoc.v:10584.3-10602.6" wire width 7 $0\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10461.3-10479.6" + attribute \src "libresoc.v:10527.3-10545.6" wire $0\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10366.3-10384.6" + attribute \src "libresoc.v:10432.3-10450.6" wire width 4 $0\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10404.3-10422.6" + attribute \src "libresoc.v:10470.3-10488.6" wire width 2 $0\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10480.3-10498.6" + attribute \src "libresoc.v:10546.3-10564.6" wire $0\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10442.3-10460.6" + attribute \src "libresoc.v:10508.3-10526.6" wire $0\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10385.3-10403.6" + attribute \src "libresoc.v:10451.3-10469.6" wire width 2 $0\LDST_dec31_upd[1:0] - attribute \src "libresoc.v:9406.7-9406.20" + attribute \src "libresoc.v:9462.7-9462.20" wire $0\initial[0:0] - attribute \src "libresoc.v:10423.3-10441.6" + attribute \src "libresoc.v:10489.3-10507.6" wire $1\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10328.3-10346.6" + attribute \src "libresoc.v:10394.3-10412.6" wire width 3 $1\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10347.3-10365.6" + attribute \src "libresoc.v:10413.3-10431.6" wire width 3 $1\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10499.3-10517.6" - wire width 13 $1\LDST_dec31_function_unit[12:0] - attribute \src "libresoc.v:10537.3-10555.6" + attribute \src "libresoc.v:10565.3-10583.6" + wire width 14 $1\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10603.3-10621.6" wire width 3 $1\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10556.3-10574.6" + attribute \src "libresoc.v:10622.3-10640.6" wire width 4 $1\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10518.3-10536.6" + attribute \src "libresoc.v:10584.3-10602.6" wire width 7 $1\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10461.3-10479.6" + attribute \src "libresoc.v:10527.3-10545.6" wire $1\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10366.3-10384.6" + attribute \src "libresoc.v:10432.3-10450.6" wire width 4 $1\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10404.3-10422.6" + attribute \src "libresoc.v:10470.3-10488.6" wire width 2 $1\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10480.3-10498.6" + attribute \src "libresoc.v:10546.3-10564.6" wire $1\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10442.3-10460.6" + attribute \src "libresoc.v:10508.3-10526.6" wire $1\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10385.3-10403.6" + attribute \src "libresoc.v:10451.3-10469.6" wire width 2 $1\LDST_dec31_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_br @@ -13546,21 +13602,22 @@ module \LDST_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -13660,6 +13717,7 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -13714,21 +13772,22 @@ module \LDST_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -13828,6 +13887,7 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -13882,21 +13942,22 @@ module \LDST_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -13996,6 +14057,7 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -14050,21 +14112,22 @@ module \LDST_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -14164,6 +14227,7 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -14196,21 +14260,22 @@ module \LDST_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec31_dec_sub23_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LDST_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -14310,6 +14375,7 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -14339,7 +14405,7 @@ module \LDST_dec31 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_upd - attribute \src "libresoc.v:9406.7-9406.15" + attribute \src "libresoc.v:9462.7-9462.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -14348,7 +14414,7 @@ module \LDST_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:10264.24-10279.4" + attribute \src "libresoc.v:10330.24-10345.4" cell \LDST_dec31_dec_sub20 \LDST_dec31_dec_sub20 connect \LDST_dec31_dec_sub20_br \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br connect \LDST_dec31_dec_sub20_cr_in \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in @@ -14366,7 +14432,7 @@ module \LDST_dec31 connect \opcode_in \LDST_dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:10280.24-10295.4" + attribute \src "libresoc.v:10346.24-10361.4" cell \LDST_dec31_dec_sub21 \LDST_dec31_dec_sub21 connect \LDST_dec31_dec_sub21_br \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br connect \LDST_dec31_dec_sub21_cr_in \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in @@ -14384,7 +14450,7 @@ module \LDST_dec31 connect \opcode_in \LDST_dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:10296.24-10311.4" + attribute \src "libresoc.v:10362.24-10377.4" cell \LDST_dec31_dec_sub22 \LDST_dec31_dec_sub22 connect \LDST_dec31_dec_sub22_br \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br connect \LDST_dec31_dec_sub22_cr_in \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in @@ -14402,7 +14468,7 @@ module \LDST_dec31 connect \opcode_in \LDST_dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:10312.24-10327.4" + attribute \src "libresoc.v:10378.24-10393.4" cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in @@ -14419,14 +14485,14 @@ module \LDST_dec31 connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd connect \opcode_in \LDST_dec31_dec_sub23_opcode_in end - attribute \src "libresoc.v:10328.3-10346.6" - process $proc$libresoc.v:10328$196 + attribute \src "libresoc.v:10394.3-10412.6" + process $proc$libresoc.v:10394$196 assign { } { } assign { } { } assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10329.5-10329.29" + attribute \src "libresoc.v:10395.5-10395.29" switch \initial - attribute \src "libresoc.v:10329.9-10329.17" + attribute \src "libresoc.v:10395.9-10395.17" case 1'1 case end @@ -14454,14 +14520,14 @@ module \LDST_dec31 sync always update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] end - attribute \src "libresoc.v:10347.3-10365.6" - process $proc$libresoc.v:10347$197 + attribute \src "libresoc.v:10413.3-10431.6" + process $proc$libresoc.v:10413$197 assign { } { } assign { } { } assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10348.5-10348.29" + attribute \src "libresoc.v:10414.5-10414.29" switch \initial - attribute \src "libresoc.v:10348.9-10348.17" + attribute \src "libresoc.v:10414.9-10414.17" case 1'1 case end @@ -14489,14 +14555,14 @@ module \LDST_dec31 sync always update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] end - attribute \src "libresoc.v:10366.3-10384.6" - process $proc$libresoc.v:10366$198 + attribute \src "libresoc.v:10432.3-10450.6" + process $proc$libresoc.v:10432$198 assign { } { } assign { } { } assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10367.5-10367.29" + attribute \src "libresoc.v:10433.5-10433.29" switch \initial - attribute \src "libresoc.v:10367.9-10367.17" + attribute \src "libresoc.v:10433.9-10433.17" case 1'1 case end @@ -14524,14 +14590,14 @@ module \LDST_dec31 sync always update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] end - attribute \src "libresoc.v:10385.3-10403.6" - process $proc$libresoc.v:10385$199 + attribute \src "libresoc.v:10451.3-10469.6" + process $proc$libresoc.v:10451$199 assign { } { } assign { } { } assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] - attribute \src "libresoc.v:10386.5-10386.29" + attribute \src "libresoc.v:10452.5-10452.29" switch \initial - attribute \src "libresoc.v:10386.9-10386.17" + attribute \src "libresoc.v:10452.9-10452.17" case 1'1 case end @@ -14559,14 +14625,14 @@ module \LDST_dec31 sync always update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] end - attribute \src "libresoc.v:10404.3-10422.6" - process $proc$libresoc.v:10404$200 + attribute \src "libresoc.v:10470.3-10488.6" + process $proc$libresoc.v:10470$200 assign { } { } assign { } { } assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10405.5-10405.29" + attribute \src "libresoc.v:10471.5-10471.29" switch \initial - attribute \src "libresoc.v:10405.9-10405.17" + attribute \src "libresoc.v:10471.9-10471.17" case 1'1 case end @@ -14594,14 +14660,14 @@ module \LDST_dec31 sync always update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:10423.3-10441.6" - process $proc$libresoc.v:10423$201 + attribute \src "libresoc.v:10489.3-10507.6" + process $proc$libresoc.v:10489$201 assign { } { } assign { } { } assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10424.5-10424.29" + attribute \src "libresoc.v:10490.5-10490.29" switch \initial - attribute \src "libresoc.v:10424.9-10424.17" + attribute \src "libresoc.v:10490.9-10490.17" case 1'1 case end @@ -14629,14 +14695,14 @@ module \LDST_dec31 sync always update \LDST_dec31_br $0\LDST_dec31_br[0:0] end - attribute \src "libresoc.v:10442.3-10460.6" - process $proc$libresoc.v:10442$202 + attribute \src "libresoc.v:10508.3-10526.6" + process $proc$libresoc.v:10508$202 assign { } { } assign { } { } assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10443.5-10443.29" + attribute \src "libresoc.v:10509.5-10509.29" switch \initial - attribute \src "libresoc.v:10443.9-10443.17" + attribute \src "libresoc.v:10509.9-10509.17" case 1'1 case end @@ -14664,14 +14730,14 @@ module \LDST_dec31 sync always update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:10461.3-10479.6" - process $proc$libresoc.v:10461$203 + attribute \src "libresoc.v:10527.3-10545.6" + process $proc$libresoc.v:10527$203 assign { } { } assign { } { } assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10462.5-10462.29" + attribute \src "libresoc.v:10528.5-10528.29" switch \initial - attribute \src "libresoc.v:10462.9-10462.17" + attribute \src "libresoc.v:10528.9-10528.17" case 1'1 case end @@ -14699,14 +14765,14 @@ module \LDST_dec31 sync always update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] end - attribute \src "libresoc.v:10480.3-10498.6" - process $proc$libresoc.v:10480$204 + attribute \src "libresoc.v:10546.3-10564.6" + process $proc$libresoc.v:10546$204 assign { } { } assign { } { } assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10481.5-10481.29" + attribute \src "libresoc.v:10547.5-10547.29" switch \initial - attribute \src "libresoc.v:10481.9-10481.17" + attribute \src "libresoc.v:10547.9-10547.17" case 1'1 case end @@ -14734,14 +14800,14 @@ module \LDST_dec31 sync always update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] end - attribute \src "libresoc.v:10499.3-10517.6" - process $proc$libresoc.v:10499$205 + attribute \src "libresoc.v:10565.3-10583.6" + process $proc$libresoc.v:10565$205 assign { } { } assign { } { } - assign $0\LDST_dec31_function_unit[12:0] $1\LDST_dec31_function_unit[12:0] - attribute \src "libresoc.v:10500.5-10500.29" + assign $0\LDST_dec31_function_unit[13:0] $1\LDST_dec31_function_unit[13:0] + attribute \src "libresoc.v:10566.5-10566.29" switch \initial - attribute \src "libresoc.v:10500.9-10500.17" + attribute \src "libresoc.v:10566.9-10566.17" case 1'1 case end @@ -14750,33 +14816,33 @@ module \LDST_dec31 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\LDST_dec31_function_unit[12:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\LDST_dec31_function_unit[12:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\LDST_dec31_function_unit[12:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\LDST_dec31_function_unit[12:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit case - assign $1\LDST_dec31_function_unit[12:0] 13'0000000000000 + assign $1\LDST_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[12:0] + update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[13:0] end - attribute \src "libresoc.v:10518.3-10536.6" - process $proc$libresoc.v:10518$206 + attribute \src "libresoc.v:10584.3-10602.6" + process $proc$libresoc.v:10584$206 assign { } { } assign { } { } assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10519.5-10519.29" + attribute \src "libresoc.v:10585.5-10585.29" switch \initial - attribute \src "libresoc.v:10519.9-10519.17" + attribute \src "libresoc.v:10585.9-10585.17" case 1'1 case end @@ -14804,14 +14870,14 @@ module \LDST_dec31 sync always update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] end - attribute \src "libresoc.v:10537.3-10555.6" - process $proc$libresoc.v:10537$207 + attribute \src "libresoc.v:10603.3-10621.6" + process $proc$libresoc.v:10603$207 assign { } { } assign { } { } assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10538.5-10538.29" + attribute \src "libresoc.v:10604.5-10604.29" switch \initial - attribute \src "libresoc.v:10538.9-10538.17" + attribute \src "libresoc.v:10604.9-10604.17" case 1'1 case end @@ -14839,14 +14905,14 @@ module \LDST_dec31 sync always update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] end - attribute \src "libresoc.v:10556.3-10574.6" - process $proc$libresoc.v:10556$208 + attribute \src "libresoc.v:10622.3-10640.6" + process $proc$libresoc.v:10622$208 assign { } { } assign { } { } assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10557.5-10557.29" + attribute \src "libresoc.v:10623.5-10623.29" switch \initial - attribute \src "libresoc.v:10557.9-10557.17" + attribute \src "libresoc.v:10623.9-10623.17" case 1'1 case end @@ -14874,8 +14940,8 @@ module \LDST_dec31 sync always update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:9406.7-9406.20" - process $proc$libresoc.v:9406$209 + attribute \src "libresoc.v:9462.7-9462.20" + process $proc$libresoc.v:9462$209 assign { } { } assign $0\initial[0:0] 1'0 sync always @@ -14889,64 +14955,64 @@ module \LDST_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:10585.1-11096.10" +attribute \src "libresoc.v:10651.1-11164.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" attribute \generator "nMigen" module \LDST_dec31_dec_sub20 - attribute \src "libresoc.v:10795.3-10819.6" + attribute \src "libresoc.v:10863.3-10887.6" wire $0\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10970.3-10994.6" + attribute \src "libresoc.v:11038.3-11062.6" wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10995.3-11019.6" + attribute \src "libresoc.v:11063.3-11087.6" wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10770.3-10794.6" - wire width 13 $0\LDST_dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:10920.3-10944.6" + attribute \src "libresoc.v:10838.3-10862.6" + wire width 14 $0\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10988.3-11012.6" wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10945.3-10969.6" + attribute \src "libresoc.v:11013.3-11037.6" wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10895.3-10919.6" + attribute \src "libresoc.v:10963.3-10987.6" wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10845.3-10869.6" + attribute \src "libresoc.v:10913.3-10937.6" wire $0\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:11020.3-11044.6" + attribute \src "libresoc.v:11088.3-11112.6" wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:11070.3-11094.6" + attribute \src "libresoc.v:11138.3-11162.6" wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:10870.3-10894.6" + attribute \src "libresoc.v:10938.3-10962.6" wire $0\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10820.3-10844.6" + attribute \src "libresoc.v:10888.3-10912.6" wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:11045.3-11069.6" + attribute \src "libresoc.v:11113.3-11137.6" wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:10586.7-10586.20" + attribute \src "libresoc.v:10652.7-10652.20" wire $0\initial[0:0] - attribute \src "libresoc.v:10795.3-10819.6" + attribute \src "libresoc.v:10863.3-10887.6" wire $1\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10970.3-10994.6" + attribute \src "libresoc.v:11038.3-11062.6" wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10995.3-11019.6" + attribute \src "libresoc.v:11063.3-11087.6" wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10770.3-10794.6" - wire width 13 $1\LDST_dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:10920.3-10944.6" + attribute \src "libresoc.v:10838.3-10862.6" + wire width 14 $1\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10988.3-11012.6" wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10945.3-10969.6" + attribute \src "libresoc.v:11013.3-11037.6" wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10895.3-10919.6" + attribute \src "libresoc.v:10963.3-10987.6" wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10845.3-10869.6" + attribute \src "libresoc.v:10913.3-10937.6" wire $1\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:11020.3-11044.6" + attribute \src "libresoc.v:11088.3-11112.6" wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:11070.3-11094.6" + attribute \src "libresoc.v:11138.3-11162.6" wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:10870.3-10894.6" + attribute \src "libresoc.v:10938.3-10962.6" wire $1\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10820.3-10844.6" + attribute \src "libresoc.v:10888.3-10912.6" wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:11045.3-11069.6" + attribute \src "libresoc.v:11113.3-11137.6" wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_dec_sub20_br @@ -14971,21 +15037,22 @@ module \LDST_dec31_dec_sub20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LDST_dec31_dec_sub20_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -15085,6 +15152,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -15114,28 +15182,28 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_dec_sub20_upd - attribute \src "libresoc.v:10586.7-10586.15" + attribute \src "libresoc.v:10652.7-10652.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:10586.7-10586.20" - process $proc$libresoc.v:10586$223 + attribute \src "libresoc.v:10652.7-10652.20" + process $proc$libresoc.v:10652$223 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:10770.3-10794.6" - process $proc$libresoc.v:10770$210 + attribute \src "libresoc.v:10838.3-10862.6" + process $proc$libresoc.v:10838$210 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_function_unit[12:0] $1\LDST_dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:10771.5-10771.29" + assign $0\LDST_dec31_dec_sub20_function_unit[13:0] $1\LDST_dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:10839.5-10839.29" switch \initial - attribute \src "libresoc.v:10771.9-10771.17" + attribute \src "libresoc.v:10839.9-10839.17" case 1'1 case end @@ -15144,41 +15212,41 @@ module \LDST_dec31_dec_sub20 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000000 + assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[12:0] + update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:10795.3-10819.6" - process $proc$libresoc.v:10795$211 + attribute \src "libresoc.v:10863.3-10887.6" + process $proc$libresoc.v:10863$211 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10796.5-10796.29" + attribute \src "libresoc.v:10864.5-10864.29" switch \initial - attribute \src "libresoc.v:10796.9-10796.17" + attribute \src "libresoc.v:10864.9-10864.17" case 1'1 case end @@ -15214,14 +15282,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:10820.3-10844.6" - process $proc$libresoc.v:10820$212 + attribute \src "libresoc.v:10888.3-10912.6" + process $proc$libresoc.v:10888$212 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:10821.5-10821.29" + attribute \src "libresoc.v:10889.5-10889.29" switch \initial - attribute \src "libresoc.v:10821.9-10821.17" + attribute \src "libresoc.v:10889.9-10889.17" case 1'1 case end @@ -15257,14 +15325,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:10845.3-10869.6" - process $proc$libresoc.v:10845$213 + attribute \src "libresoc.v:10913.3-10937.6" + process $proc$libresoc.v:10913$213 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:10846.5-10846.29" + attribute \src "libresoc.v:10914.5-10914.29" switch \initial - attribute \src "libresoc.v:10846.9-10846.17" + attribute \src "libresoc.v:10914.9-10914.17" case 1'1 case end @@ -15300,14 +15368,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:10870.3-10894.6" - process $proc$libresoc.v:10870$214 + attribute \src "libresoc.v:10938.3-10962.6" + process $proc$libresoc.v:10938$214 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10871.5-10871.29" + attribute \src "libresoc.v:10939.5-10939.29" switch \initial - attribute \src "libresoc.v:10871.9-10871.17" + attribute \src "libresoc.v:10939.9-10939.17" case 1'1 case end @@ -15343,14 +15411,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:10895.3-10919.6" - process $proc$libresoc.v:10895$215 + attribute \src "libresoc.v:10963.3-10987.6" + process $proc$libresoc.v:10963$215 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10896.5-10896.29" + attribute \src "libresoc.v:10964.5-10964.29" switch \initial - attribute \src "libresoc.v:10896.9-10896.17" + attribute \src "libresoc.v:10964.9-10964.17" case 1'1 case end @@ -15386,14 +15454,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:10920.3-10944.6" - process $proc$libresoc.v:10920$216 + attribute \src "libresoc.v:10988.3-11012.6" + process $proc$libresoc.v:10988$216 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10921.5-10921.29" + attribute \src "libresoc.v:10989.5-10989.29" switch \initial - attribute \src "libresoc.v:10921.9-10921.17" + attribute \src "libresoc.v:10989.9-10989.17" case 1'1 case end @@ -15429,14 +15497,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:10945.3-10969.6" - process $proc$libresoc.v:10945$217 + attribute \src "libresoc.v:11013.3-11037.6" + process $proc$libresoc.v:11013$217 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10946.5-10946.29" + attribute \src "libresoc.v:11014.5-11014.29" switch \initial - attribute \src "libresoc.v:10946.9-10946.17" + attribute \src "libresoc.v:11014.9-11014.17" case 1'1 case end @@ -15472,14 +15540,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:10970.3-10994.6" - process $proc$libresoc.v:10970$218 + attribute \src "libresoc.v:11038.3-11062.6" + process $proc$libresoc.v:11038$218 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10971.5-10971.29" + attribute \src "libresoc.v:11039.5-11039.29" switch \initial - attribute \src "libresoc.v:10971.9-10971.17" + attribute \src "libresoc.v:11039.9-11039.17" case 1'1 case end @@ -15515,14 +15583,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:10995.3-11019.6" - process $proc$libresoc.v:10995$219 + attribute \src "libresoc.v:11063.3-11087.6" + process $proc$libresoc.v:11063$219 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10996.5-10996.29" + attribute \src "libresoc.v:11064.5-11064.29" switch \initial - attribute \src "libresoc.v:10996.9-10996.17" + attribute \src "libresoc.v:11064.9-11064.17" case 1'1 case end @@ -15558,14 +15626,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:11020.3-11044.6" - process $proc$libresoc.v:11020$220 + attribute \src "libresoc.v:11088.3-11112.6" + process $proc$libresoc.v:11088$220 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:11021.5-11021.29" + attribute \src "libresoc.v:11089.5-11089.29" switch \initial - attribute \src "libresoc.v:11021.9-11021.17" + attribute \src "libresoc.v:11089.9-11089.17" case 1'1 case end @@ -15601,14 +15669,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:11045.3-11069.6" - process $proc$libresoc.v:11045$221 + attribute \src "libresoc.v:11113.3-11137.6" + process $proc$libresoc.v:11113$221 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:11046.5-11046.29" + attribute \src "libresoc.v:11114.5-11114.29" switch \initial - attribute \src "libresoc.v:11046.9-11046.17" + attribute \src "libresoc.v:11114.9-11114.17" case 1'1 case end @@ -15644,14 +15712,14 @@ module \LDST_dec31_dec_sub20 sync always update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:11070.3-11094.6" - process $proc$libresoc.v:11070$222 + attribute \src "libresoc.v:11138.3-11162.6" + process $proc$libresoc.v:11138$222 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:11071.5-11071.29" + attribute \src "libresoc.v:11139.5-11139.29" switch \initial - attribute \src "libresoc.v:11071.9-11071.17" + attribute \src "libresoc.v:11139.9-11139.17" case 1'1 case end @@ -15689,64 +15757,64 @@ module \LDST_dec31_dec_sub20 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:11100.1-11923.10" +attribute \src "libresoc.v:11168.1-11993.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" attribute \generator "nMigen" module \LDST_dec31_dec_sub21 - attribute \src "libresoc.v:11334.3-11382.6" + attribute \src "libresoc.v:11404.3-11452.6" wire $0\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11677.3-11725.6" + attribute \src "libresoc.v:11747.3-11795.6" wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11726.3-11774.6" + attribute \src "libresoc.v:11796.3-11844.6" wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11285.3-11333.6" - wire width 13 $0\LDST_dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:11579.3-11627.6" + attribute \src "libresoc.v:11355.3-11403.6" + wire width 14 $0\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11649.3-11697.6" wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11628.3-11676.6" + attribute \src "libresoc.v:11698.3-11746.6" wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11530.3-11578.6" + attribute \src "libresoc.v:11600.3-11648.6" wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11432.3-11480.6" + attribute \src "libresoc.v:11502.3-11550.6" wire $0\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11775.3-11823.6" + attribute \src "libresoc.v:11845.3-11893.6" wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11873.3-11921.6" + attribute \src "libresoc.v:11943.3-11991.6" wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11481.3-11529.6" + attribute \src "libresoc.v:11551.3-11599.6" wire $0\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11383.3-11431.6" + attribute \src "libresoc.v:11453.3-11501.6" wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11824.3-11872.6" + attribute \src "libresoc.v:11894.3-11942.6" wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:11101.7-11101.20" + attribute \src "libresoc.v:11169.7-11169.20" wire $0\initial[0:0] - attribute \src "libresoc.v:11334.3-11382.6" + attribute \src "libresoc.v:11404.3-11452.6" wire $1\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11677.3-11725.6" + attribute \src "libresoc.v:11747.3-11795.6" wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11726.3-11774.6" + attribute \src "libresoc.v:11796.3-11844.6" wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11285.3-11333.6" - wire width 13 $1\LDST_dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:11579.3-11627.6" + attribute \src "libresoc.v:11355.3-11403.6" + wire width 14 $1\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11649.3-11697.6" wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11628.3-11676.6" + attribute \src "libresoc.v:11698.3-11746.6" wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11530.3-11578.6" + attribute \src "libresoc.v:11600.3-11648.6" wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11432.3-11480.6" + attribute \src "libresoc.v:11502.3-11550.6" wire $1\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11775.3-11823.6" + attribute \src "libresoc.v:11845.3-11893.6" wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11873.3-11921.6" + attribute \src "libresoc.v:11943.3-11991.6" wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11481.3-11529.6" + attribute \src "libresoc.v:11551.3-11599.6" wire $1\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11383.3-11431.6" + attribute \src "libresoc.v:11453.3-11501.6" wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11824.3-11872.6" + attribute \src "libresoc.v:11894.3-11942.6" wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_dec_sub21_br @@ -15771,21 +15839,22 @@ module \LDST_dec31_dec_sub21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LDST_dec31_dec_sub21_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -15885,6 +15954,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -15914,28 +15984,28 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_dec_sub21_upd - attribute \src "libresoc.v:11101.7-11101.15" + attribute \src "libresoc.v:11169.7-11169.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:11101.7-11101.20" - process $proc$libresoc.v:11101$237 + attribute \src "libresoc.v:11169.7-11169.20" + process $proc$libresoc.v:11169$237 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:11285.3-11333.6" - process $proc$libresoc.v:11285$224 + attribute \src "libresoc.v:11355.3-11403.6" + process $proc$libresoc.v:11355$224 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_function_unit[12:0] $1\LDST_dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:11286.5-11286.29" + assign $0\LDST_dec31_dec_sub21_function_unit[13:0] $1\LDST_dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:11356.5-11356.29" switch \initial - attribute \src "libresoc.v:11286.9-11286.17" + attribute \src "libresoc.v:11356.9-11356.17" case 1'1 case end @@ -15944,73 +16014,73 @@ module \LDST_dec31_dec_sub21 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000000 + assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[12:0] + update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:11334.3-11382.6" - process $proc$libresoc.v:11334$225 + attribute \src "libresoc.v:11404.3-11452.6" + process $proc$libresoc.v:11404$225 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11335.5-11335.29" + attribute \src "libresoc.v:11405.5-11405.29" switch \initial - attribute \src "libresoc.v:11335.9-11335.17" + attribute \src "libresoc.v:11405.9-11405.17" case 1'1 case end @@ -16078,14 +16148,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:11383.3-11431.6" - process $proc$libresoc.v:11383$226 + attribute \src "libresoc.v:11453.3-11501.6" + process $proc$libresoc.v:11453$226 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11384.5-11384.29" + attribute \src "libresoc.v:11454.5-11454.29" switch \initial - attribute \src "libresoc.v:11384.9-11384.17" + attribute \src "libresoc.v:11454.9-11454.17" case 1'1 case end @@ -16153,14 +16223,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:11432.3-11480.6" - process $proc$libresoc.v:11432$227 + attribute \src "libresoc.v:11502.3-11550.6" + process $proc$libresoc.v:11502$227 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11433.5-11433.29" + attribute \src "libresoc.v:11503.5-11503.29" switch \initial - attribute \src "libresoc.v:11433.9-11433.17" + attribute \src "libresoc.v:11503.9-11503.17" case 1'1 case end @@ -16228,14 +16298,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:11481.3-11529.6" - process $proc$libresoc.v:11481$228 + attribute \src "libresoc.v:11551.3-11599.6" + process $proc$libresoc.v:11551$228 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11482.5-11482.29" + attribute \src "libresoc.v:11552.5-11552.29" switch \initial - attribute \src "libresoc.v:11482.9-11482.17" + attribute \src "libresoc.v:11552.9-11552.17" case 1'1 case end @@ -16303,14 +16373,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:11530.3-11578.6" - process $proc$libresoc.v:11530$229 + attribute \src "libresoc.v:11600.3-11648.6" + process $proc$libresoc.v:11600$229 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11531.5-11531.29" + attribute \src "libresoc.v:11601.5-11601.29" switch \initial - attribute \src "libresoc.v:11531.9-11531.17" + attribute \src "libresoc.v:11601.9-11601.17" case 1'1 case end @@ -16378,14 +16448,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:11579.3-11627.6" - process $proc$libresoc.v:11579$230 + attribute \src "libresoc.v:11649.3-11697.6" + process $proc$libresoc.v:11649$230 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11580.5-11580.29" + attribute \src "libresoc.v:11650.5-11650.29" switch \initial - attribute \src "libresoc.v:11580.9-11580.17" + attribute \src "libresoc.v:11650.9-11650.17" case 1'1 case end @@ -16453,14 +16523,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:11628.3-11676.6" - process $proc$libresoc.v:11628$231 + attribute \src "libresoc.v:11698.3-11746.6" + process $proc$libresoc.v:11698$231 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11629.5-11629.29" + attribute \src "libresoc.v:11699.5-11699.29" switch \initial - attribute \src "libresoc.v:11629.9-11629.17" + attribute \src "libresoc.v:11699.9-11699.17" case 1'1 case end @@ -16528,14 +16598,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:11677.3-11725.6" - process $proc$libresoc.v:11677$232 + attribute \src "libresoc.v:11747.3-11795.6" + process $proc$libresoc.v:11747$232 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11678.5-11678.29" + attribute \src "libresoc.v:11748.5-11748.29" switch \initial - attribute \src "libresoc.v:11678.9-11678.17" + attribute \src "libresoc.v:11748.9-11748.17" case 1'1 case end @@ -16603,14 +16673,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:11726.3-11774.6" - process $proc$libresoc.v:11726$233 + attribute \src "libresoc.v:11796.3-11844.6" + process $proc$libresoc.v:11796$233 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11727.5-11727.29" + attribute \src "libresoc.v:11797.5-11797.29" switch \initial - attribute \src "libresoc.v:11727.9-11727.17" + attribute \src "libresoc.v:11797.9-11797.17" case 1'1 case end @@ -16678,14 +16748,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:11775.3-11823.6" - process $proc$libresoc.v:11775$234 + attribute \src "libresoc.v:11845.3-11893.6" + process $proc$libresoc.v:11845$234 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11776.5-11776.29" + attribute \src "libresoc.v:11846.5-11846.29" switch \initial - attribute \src "libresoc.v:11776.9-11776.17" + attribute \src "libresoc.v:11846.9-11846.17" case 1'1 case end @@ -16753,14 +16823,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:11824.3-11872.6" - process $proc$libresoc.v:11824$235 + attribute \src "libresoc.v:11894.3-11942.6" + process $proc$libresoc.v:11894$235 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:11825.5-11825.29" + attribute \src "libresoc.v:11895.5-11895.29" switch \initial - attribute \src "libresoc.v:11825.9-11825.17" + attribute \src "libresoc.v:11895.9-11895.17" case 1'1 case end @@ -16828,14 +16898,14 @@ module \LDST_dec31_dec_sub21 sync always update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:11873.3-11921.6" - process $proc$libresoc.v:11873$236 + attribute \src "libresoc.v:11943.3-11991.6" + process $proc$libresoc.v:11943$236 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11874.5-11874.29" + attribute \src "libresoc.v:11944.5-11944.29" switch \initial - attribute \src "libresoc.v:11874.9-11874.17" + attribute \src "libresoc.v:11944.9-11944.17" case 1'1 case end @@ -16905,64 +16975,64 @@ module \LDST_dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:11927.1-12516.10" +attribute \src "libresoc.v:11997.1-12588.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" attribute \generator "nMigen" module \LDST_dec31_dec_sub22 - attribute \src "libresoc.v:12143.3-12173.6" + attribute \src "libresoc.v:12215.3-12245.6" wire $0\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12360.3-12390.6" + attribute \src "libresoc.v:12432.3-12462.6" wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12391.3-12421.6" + attribute \src "libresoc.v:12463.3-12493.6" wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12112.3-12142.6" - wire width 13 $0\LDST_dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:12298.3-12328.6" + attribute \src "libresoc.v:12184.3-12214.6" + wire width 14 $0\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12370.3-12400.6" wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12329.3-12359.6" + attribute \src "libresoc.v:12401.3-12431.6" wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12267.3-12297.6" + attribute \src "libresoc.v:12339.3-12369.6" wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12205.3-12235.6" + attribute \src "libresoc.v:12277.3-12307.6" wire $0\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12422.3-12452.6" + attribute \src "libresoc.v:12494.3-12524.6" wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12484.3-12514.6" + attribute \src "libresoc.v:12556.3-12586.6" wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12236.3-12266.6" + attribute \src "libresoc.v:12308.3-12338.6" wire $0\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12174.3-12204.6" + attribute \src "libresoc.v:12246.3-12276.6" wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12453.3-12483.6" + attribute \src "libresoc.v:12525.3-12555.6" wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:11928.7-11928.20" + attribute \src "libresoc.v:11998.7-11998.20" wire $0\initial[0:0] - attribute \src "libresoc.v:12143.3-12173.6" + attribute \src "libresoc.v:12215.3-12245.6" wire $1\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12360.3-12390.6" + attribute \src "libresoc.v:12432.3-12462.6" wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12391.3-12421.6" + attribute \src "libresoc.v:12463.3-12493.6" wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12112.3-12142.6" - wire width 13 $1\LDST_dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:12298.3-12328.6" + attribute \src "libresoc.v:12184.3-12214.6" + wire width 14 $1\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12370.3-12400.6" wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12329.3-12359.6" + attribute \src "libresoc.v:12401.3-12431.6" wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12267.3-12297.6" + attribute \src "libresoc.v:12339.3-12369.6" wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12205.3-12235.6" + attribute \src "libresoc.v:12277.3-12307.6" wire $1\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12422.3-12452.6" + attribute \src "libresoc.v:12494.3-12524.6" wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12484.3-12514.6" + attribute \src "libresoc.v:12556.3-12586.6" wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12236.3-12266.6" + attribute \src "libresoc.v:12308.3-12338.6" wire $1\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12174.3-12204.6" + attribute \src "libresoc.v:12246.3-12276.6" wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12453.3-12483.6" + attribute \src "libresoc.v:12525.3-12555.6" wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_dec_sub22_br @@ -16987,21 +17057,22 @@ module \LDST_dec31_dec_sub22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LDST_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -17101,6 +17172,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -17130,28 +17202,28 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_dec_sub22_upd - attribute \src "libresoc.v:11928.7-11928.15" + attribute \src "libresoc.v:11998.7-11998.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:11928.7-11928.20" - process $proc$libresoc.v:11928$251 + attribute \src "libresoc.v:11998.7-11998.20" + process $proc$libresoc.v:11998$251 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:12112.3-12142.6" - process $proc$libresoc.v:12112$238 + attribute \src "libresoc.v:12184.3-12214.6" + process $proc$libresoc.v:12184$238 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub22_function_unit[12:0] $1\LDST_dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:12113.5-12113.29" + assign $0\LDST_dec31_dec_sub22_function_unit[13:0] $1\LDST_dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:12185.5-12185.29" switch \initial - attribute \src "libresoc.v:12113.9-12113.17" + attribute \src "libresoc.v:12185.9-12185.17" case 1'1 case end @@ -17160,49 +17232,49 @@ module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000000 + assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[12:0] + update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:12143.3-12173.6" - process $proc$libresoc.v:12143$239 + attribute \src "libresoc.v:12215.3-12245.6" + process $proc$libresoc.v:12215$239 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12144.5-12144.29" + attribute \src "libresoc.v:12216.5-12216.29" switch \initial - attribute \src "libresoc.v:12144.9-12144.17" + attribute \src "libresoc.v:12216.9-12216.17" case 1'1 case end @@ -17246,14 +17318,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:12174.3-12204.6" - process $proc$libresoc.v:12174$240 + attribute \src "libresoc.v:12246.3-12276.6" + process $proc$libresoc.v:12246$240 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12175.5-12175.29" + attribute \src "libresoc.v:12247.5-12247.29" switch \initial - attribute \src "libresoc.v:12175.9-12175.17" + attribute \src "libresoc.v:12247.9-12247.17" case 1'1 case end @@ -17297,14 +17369,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:12205.3-12235.6" - process $proc$libresoc.v:12205$241 + attribute \src "libresoc.v:12277.3-12307.6" + process $proc$libresoc.v:12277$241 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12206.5-12206.29" + attribute \src "libresoc.v:12278.5-12278.29" switch \initial - attribute \src "libresoc.v:12206.9-12206.17" + attribute \src "libresoc.v:12278.9-12278.17" case 1'1 case end @@ -17348,14 +17420,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:12236.3-12266.6" - process $proc$libresoc.v:12236$242 + attribute \src "libresoc.v:12308.3-12338.6" + process $proc$libresoc.v:12308$242 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12237.5-12237.29" + attribute \src "libresoc.v:12309.5-12309.29" switch \initial - attribute \src "libresoc.v:12237.9-12237.17" + attribute \src "libresoc.v:12309.9-12309.17" case 1'1 case end @@ -17399,14 +17471,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:12267.3-12297.6" - process $proc$libresoc.v:12267$243 + attribute \src "libresoc.v:12339.3-12369.6" + process $proc$libresoc.v:12339$243 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12268.5-12268.29" + attribute \src "libresoc.v:12340.5-12340.29" switch \initial - attribute \src "libresoc.v:12268.9-12268.17" + attribute \src "libresoc.v:12340.9-12340.17" case 1'1 case end @@ -17450,14 +17522,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:12298.3-12328.6" - process $proc$libresoc.v:12298$244 + attribute \src "libresoc.v:12370.3-12400.6" + process $proc$libresoc.v:12370$244 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12299.5-12299.29" + attribute \src "libresoc.v:12371.5-12371.29" switch \initial - attribute \src "libresoc.v:12299.9-12299.17" + attribute \src "libresoc.v:12371.9-12371.17" case 1'1 case end @@ -17501,14 +17573,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:12329.3-12359.6" - process $proc$libresoc.v:12329$245 + attribute \src "libresoc.v:12401.3-12431.6" + process $proc$libresoc.v:12401$245 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12330.5-12330.29" + attribute \src "libresoc.v:12402.5-12402.29" switch \initial - attribute \src "libresoc.v:12330.9-12330.17" + attribute \src "libresoc.v:12402.9-12402.17" case 1'1 case end @@ -17552,14 +17624,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:12360.3-12390.6" - process $proc$libresoc.v:12360$246 + attribute \src "libresoc.v:12432.3-12462.6" + process $proc$libresoc.v:12432$246 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12361.5-12361.29" + attribute \src "libresoc.v:12433.5-12433.29" switch \initial - attribute \src "libresoc.v:12361.9-12361.17" + attribute \src "libresoc.v:12433.9-12433.17" case 1'1 case end @@ -17603,14 +17675,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:12391.3-12421.6" - process $proc$libresoc.v:12391$247 + attribute \src "libresoc.v:12463.3-12493.6" + process $proc$libresoc.v:12463$247 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12392.5-12392.29" + attribute \src "libresoc.v:12464.5-12464.29" switch \initial - attribute \src "libresoc.v:12392.9-12392.17" + attribute \src "libresoc.v:12464.9-12464.17" case 1'1 case end @@ -17654,14 +17726,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:12422.3-12452.6" - process $proc$libresoc.v:12422$248 + attribute \src "libresoc.v:12494.3-12524.6" + process $proc$libresoc.v:12494$248 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12423.5-12423.29" + attribute \src "libresoc.v:12495.5-12495.29" switch \initial - attribute \src "libresoc.v:12423.9-12423.17" + attribute \src "libresoc.v:12495.9-12495.17" case 1'1 case end @@ -17705,14 +17777,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:12453.3-12483.6" - process $proc$libresoc.v:12453$249 + attribute \src "libresoc.v:12525.3-12555.6" + process $proc$libresoc.v:12525$249 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:12454.5-12454.29" + attribute \src "libresoc.v:12526.5-12526.29" switch \initial - attribute \src "libresoc.v:12454.9-12454.17" + attribute \src "libresoc.v:12526.9-12526.17" case 1'1 case end @@ -17756,14 +17828,14 @@ module \LDST_dec31_dec_sub22 sync always update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:12484.3-12514.6" - process $proc$libresoc.v:12484$250 + attribute \src "libresoc.v:12556.3-12586.6" + process $proc$libresoc.v:12556$250 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12485.5-12485.29" + attribute \src "libresoc.v:12557.5-12557.29" switch \initial - attribute \src "libresoc.v:12485.9-12485.17" + attribute \src "libresoc.v:12557.9-12557.17" case 1'1 case end @@ -17809,64 +17881,64 @@ module \LDST_dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:12520.1-13343.10" +attribute \src "libresoc.v:12592.1-13417.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" attribute \generator "nMigen" module \LDST_dec31_dec_sub23 - attribute \src "libresoc.v:12754.3-12802.6" + attribute \src "libresoc.v:12828.3-12876.6" wire $0\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:13097.3-13145.6" + attribute \src "libresoc.v:13171.3-13219.6" wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:13146.3-13194.6" + attribute \src "libresoc.v:13220.3-13268.6" wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:12705.3-12753.6" - wire width 13 $0\LDST_dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:12999.3-13047.6" + attribute \src "libresoc.v:12779.3-12827.6" + wire width 14 $0\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:13073.3-13121.6" wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:13048.3-13096.6" + attribute \src "libresoc.v:13122.3-13170.6" wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:12950.3-12998.6" + attribute \src "libresoc.v:13024.3-13072.6" wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12852.3-12900.6" + attribute \src "libresoc.v:12926.3-12974.6" wire $0\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:13195.3-13243.6" + attribute \src "libresoc.v:13269.3-13317.6" wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13293.3-13341.6" + attribute \src "libresoc.v:13367.3-13415.6" wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:12901.3-12949.6" + attribute \src "libresoc.v:12975.3-13023.6" wire $0\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12803.3-12851.6" + attribute \src "libresoc.v:12877.3-12925.6" wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:13244.3-13292.6" + attribute \src "libresoc.v:13318.3-13366.6" wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:12521.7-12521.20" + attribute \src "libresoc.v:12593.7-12593.20" wire $0\initial[0:0] - attribute \src "libresoc.v:12754.3-12802.6" + attribute \src "libresoc.v:12828.3-12876.6" wire $1\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:13097.3-13145.6" + attribute \src "libresoc.v:13171.3-13219.6" wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:13146.3-13194.6" + attribute \src "libresoc.v:13220.3-13268.6" wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:12705.3-12753.6" - wire width 13 $1\LDST_dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:12999.3-13047.6" + attribute \src "libresoc.v:12779.3-12827.6" + wire width 14 $1\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:13073.3-13121.6" wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:13048.3-13096.6" + attribute \src "libresoc.v:13122.3-13170.6" wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:12950.3-12998.6" + attribute \src "libresoc.v:13024.3-13072.6" wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12852.3-12900.6" + attribute \src "libresoc.v:12926.3-12974.6" wire $1\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:13195.3-13243.6" + attribute \src "libresoc.v:13269.3-13317.6" wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13293.3-13341.6" + attribute \src "libresoc.v:13367.3-13415.6" wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:12901.3-12949.6" + attribute \src "libresoc.v:12975.3-13023.6" wire $1\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12803.3-12851.6" + attribute \src "libresoc.v:12877.3-12925.6" wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:13244.3-13292.6" + attribute \src "libresoc.v:13318.3-13366.6" wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec31_dec_sub23_br @@ -17891,21 +17963,22 @@ module \LDST_dec31_dec_sub23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LDST_dec31_dec_sub23_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -18005,6 +18078,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -18034,28 +18108,28 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec31_dec_sub23_upd - attribute \src "libresoc.v:12521.7-12521.15" + attribute \src "libresoc.v:12593.7-12593.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:12521.7-12521.20" - process $proc$libresoc.v:12521$265 + attribute \src "libresoc.v:12593.7-12593.20" + process $proc$libresoc.v:12593$265 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:12705.3-12753.6" - process $proc$libresoc.v:12705$252 + attribute \src "libresoc.v:12779.3-12827.6" + process $proc$libresoc.v:12779$252 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub23_function_unit[12:0] $1\LDST_dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:12706.5-12706.29" + assign $0\LDST_dec31_dec_sub23_function_unit[13:0] $1\LDST_dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:12780.5-12780.29" switch \initial - attribute \src "libresoc.v:12706.9-12706.17" + attribute \src "libresoc.v:12780.9-12780.17" case 1'1 case end @@ -18064,73 +18138,73 @@ module \LDST_dec31_dec_sub23 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000000 + assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[12:0] + update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:12754.3-12802.6" - process $proc$libresoc.v:12754$253 + attribute \src "libresoc.v:12828.3-12876.6" + process $proc$libresoc.v:12828$253 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:12755.5-12755.29" + attribute \src "libresoc.v:12829.5-12829.29" switch \initial - attribute \src "libresoc.v:12755.9-12755.17" + attribute \src "libresoc.v:12829.9-12829.17" case 1'1 case end @@ -18198,14 +18272,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:12803.3-12851.6" - process $proc$libresoc.v:12803$254 + attribute \src "libresoc.v:12877.3-12925.6" + process $proc$libresoc.v:12877$254 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:12804.5-12804.29" + attribute \src "libresoc.v:12878.5-12878.29" switch \initial - attribute \src "libresoc.v:12804.9-12804.17" + attribute \src "libresoc.v:12878.9-12878.17" case 1'1 case end @@ -18273,14 +18347,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:12852.3-12900.6" - process $proc$libresoc.v:12852$255 + attribute \src "libresoc.v:12926.3-12974.6" + process $proc$libresoc.v:12926$255 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:12853.5-12853.29" + attribute \src "libresoc.v:12927.5-12927.29" switch \initial - attribute \src "libresoc.v:12853.9-12853.17" + attribute \src "libresoc.v:12927.9-12927.17" case 1'1 case end @@ -18348,14 +18422,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:12901.3-12949.6" - process $proc$libresoc.v:12901$256 + attribute \src "libresoc.v:12975.3-13023.6" + process $proc$libresoc.v:12975$256 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12902.5-12902.29" + attribute \src "libresoc.v:12976.5-12976.29" switch \initial - attribute \src "libresoc.v:12902.9-12902.17" + attribute \src "libresoc.v:12976.9-12976.17" case 1'1 case end @@ -18423,14 +18497,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:12950.3-12998.6" - process $proc$libresoc.v:12950$257 + attribute \src "libresoc.v:13024.3-13072.6" + process $proc$libresoc.v:13024$257 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12951.5-12951.29" + attribute \src "libresoc.v:13025.5-13025.29" switch \initial - attribute \src "libresoc.v:12951.9-12951.17" + attribute \src "libresoc.v:13025.9-13025.17" case 1'1 case end @@ -18498,14 +18572,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:12999.3-13047.6" - process $proc$libresoc.v:12999$258 + attribute \src "libresoc.v:13073.3-13121.6" + process $proc$libresoc.v:13073$258 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:13000.5-13000.29" + attribute \src "libresoc.v:13074.5-13074.29" switch \initial - attribute \src "libresoc.v:13000.9-13000.17" + attribute \src "libresoc.v:13074.9-13074.17" case 1'1 case end @@ -18573,14 +18647,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:13048.3-13096.6" - process $proc$libresoc.v:13048$259 + attribute \src "libresoc.v:13122.3-13170.6" + process $proc$libresoc.v:13122$259 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:13049.5-13049.29" + attribute \src "libresoc.v:13123.5-13123.29" switch \initial - attribute \src "libresoc.v:13049.9-13049.17" + attribute \src "libresoc.v:13123.9-13123.17" case 1'1 case end @@ -18648,14 +18722,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:13097.3-13145.6" - process $proc$libresoc.v:13097$260 + attribute \src "libresoc.v:13171.3-13219.6" + process $proc$libresoc.v:13171$260 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:13098.5-13098.29" + attribute \src "libresoc.v:13172.5-13172.29" switch \initial - attribute \src "libresoc.v:13098.9-13098.17" + attribute \src "libresoc.v:13172.9-13172.17" case 1'1 case end @@ -18723,14 +18797,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:13146.3-13194.6" - process $proc$libresoc.v:13146$261 + attribute \src "libresoc.v:13220.3-13268.6" + process $proc$libresoc.v:13220$261 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:13147.5-13147.29" + attribute \src "libresoc.v:13221.5-13221.29" switch \initial - attribute \src "libresoc.v:13147.9-13147.17" + attribute \src "libresoc.v:13221.9-13221.17" case 1'1 case end @@ -18798,14 +18872,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:13195.3-13243.6" - process $proc$libresoc.v:13195$262 + attribute \src "libresoc.v:13269.3-13317.6" + process $proc$libresoc.v:13269$262 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13196.5-13196.29" + attribute \src "libresoc.v:13270.5-13270.29" switch \initial - attribute \src "libresoc.v:13196.9-13196.17" + attribute \src "libresoc.v:13270.9-13270.17" case 1'1 case end @@ -18873,14 +18947,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:13244.3-13292.6" - process $proc$libresoc.v:13244$263 + attribute \src "libresoc.v:13318.3-13366.6" + process $proc$libresoc.v:13318$263 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:13245.5-13245.29" + attribute \src "libresoc.v:13319.5-13319.29" switch \initial - attribute \src "libresoc.v:13245.9-13245.17" + attribute \src "libresoc.v:13319.9-13319.17" case 1'1 case end @@ -18948,14 +19022,14 @@ module \LDST_dec31_dec_sub23 sync always update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:13293.3-13341.6" - process $proc$libresoc.v:13293$264 + attribute \src "libresoc.v:13367.3-13415.6" + process $proc$libresoc.v:13367$264 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:13294.5-13294.29" + attribute \src "libresoc.v:13368.5-13368.29" switch \initial - attribute \src "libresoc.v:13294.9-13294.17" + attribute \src "libresoc.v:13368.9-13368.17" case 1'1 case end @@ -19025,64 +19099,64 @@ module \LDST_dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:13347.1-13741.10" +attribute \src "libresoc.v:13421.1-13817.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" attribute \generator "nMigen" module \LDST_dec58 - attribute \src "libresoc.v:13548.3-13563.6" + attribute \src "libresoc.v:13624.3-13639.6" wire $0\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13660.3-13675.6" + attribute \src "libresoc.v:13736.3-13751.6" wire width 3 $0\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13676.3-13691.6" + attribute \src "libresoc.v:13752.3-13767.6" wire width 3 $0\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13532.3-13547.6" - wire width 13 $0\LDST_dec58_function_unit[12:0] - attribute \src "libresoc.v:13628.3-13643.6" + attribute \src "libresoc.v:13608.3-13623.6" + wire width 14 $0\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13704.3-13719.6" wire width 3 $0\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13644.3-13659.6" + attribute \src "libresoc.v:13720.3-13735.6" wire width 4 $0\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13612.3-13627.6" + attribute \src "libresoc.v:13688.3-13703.6" wire width 7 $0\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13580.3-13595.6" + attribute \src "libresoc.v:13656.3-13671.6" wire $0\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13692.3-13707.6" + attribute \src "libresoc.v:13768.3-13783.6" wire width 4 $0\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13724.3-13739.6" + attribute \src "libresoc.v:13800.3-13815.6" wire width 2 $0\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13596.3-13611.6" + attribute \src "libresoc.v:13672.3-13687.6" wire $0\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13564.3-13579.6" + attribute \src "libresoc.v:13640.3-13655.6" wire $0\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13708.3-13723.6" + attribute \src "libresoc.v:13784.3-13799.6" wire width 2 $0\LDST_dec58_upd[1:0] - attribute \src "libresoc.v:13348.7-13348.20" + attribute \src "libresoc.v:13422.7-13422.20" wire $0\initial[0:0] - attribute \src "libresoc.v:13548.3-13563.6" + attribute \src "libresoc.v:13624.3-13639.6" wire $1\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13660.3-13675.6" + attribute \src "libresoc.v:13736.3-13751.6" wire width 3 $1\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13676.3-13691.6" + attribute \src "libresoc.v:13752.3-13767.6" wire width 3 $1\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13532.3-13547.6" - wire width 13 $1\LDST_dec58_function_unit[12:0] - attribute \src "libresoc.v:13628.3-13643.6" + attribute \src "libresoc.v:13608.3-13623.6" + wire width 14 $1\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13704.3-13719.6" wire width 3 $1\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13644.3-13659.6" + attribute \src "libresoc.v:13720.3-13735.6" wire width 4 $1\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13612.3-13627.6" + attribute \src "libresoc.v:13688.3-13703.6" wire width 7 $1\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13580.3-13595.6" + attribute \src "libresoc.v:13656.3-13671.6" wire $1\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13692.3-13707.6" + attribute \src "libresoc.v:13768.3-13783.6" wire width 4 $1\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13724.3-13739.6" + attribute \src "libresoc.v:13800.3-13815.6" wire width 2 $1\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13596.3-13611.6" + attribute \src "libresoc.v:13672.3-13687.6" wire $1\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13564.3-13579.6" + attribute \src "libresoc.v:13640.3-13655.6" wire $1\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13708.3-13723.6" + attribute \src "libresoc.v:13784.3-13799.6" wire width 2 $1\LDST_dec58_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec58_br @@ -19107,21 +19181,22 @@ module \LDST_dec58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec58_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LDST_dec58_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -19221,6 +19296,7 @@ module \LDST_dec58 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -19250,28 +19326,28 @@ module \LDST_dec58 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec58_upd - attribute \src "libresoc.v:13348.7-13348.15" + attribute \src "libresoc.v:13422.7-13422.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 2 \opcode_switch - attribute \src "libresoc.v:13348.7-13348.20" - process $proc$libresoc.v:13348$279 + attribute \src "libresoc.v:13422.7-13422.20" + process $proc$libresoc.v:13422$279 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:13532.3-13547.6" - process $proc$libresoc.v:13532$266 + attribute \src "libresoc.v:13608.3-13623.6" + process $proc$libresoc.v:13608$266 assign { } { } assign { } { } - assign $0\LDST_dec58_function_unit[12:0] $1\LDST_dec58_function_unit[12:0] - attribute \src "libresoc.v:13533.5-13533.29" + assign $0\LDST_dec58_function_unit[13:0] $1\LDST_dec58_function_unit[13:0] + attribute \src "libresoc.v:13609.5-13609.29" switch \initial - attribute \src "libresoc.v:13533.9-13533.17" + attribute \src "libresoc.v:13609.9-13609.17" case 1'1 case end @@ -19280,29 +19356,29 @@ module \LDST_dec58 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\LDST_dec58_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\LDST_dec58_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\LDST_dec58_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec58_function_unit[12:0] 13'0000000000000 + assign $1\LDST_dec58_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[12:0] + update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[13:0] end - attribute \src "libresoc.v:13548.3-13563.6" - process $proc$libresoc.v:13548$267 + attribute \src "libresoc.v:13624.3-13639.6" + process $proc$libresoc.v:13624$267 assign { } { } assign { } { } assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13549.5-13549.29" + attribute \src "libresoc.v:13625.5-13625.29" switch \initial - attribute \src "libresoc.v:13549.9-13549.17" + attribute \src "libresoc.v:13625.9-13625.17" case 1'1 case end @@ -19326,14 +19402,14 @@ module \LDST_dec58 sync always update \LDST_dec58_br $0\LDST_dec58_br[0:0] end - attribute \src "libresoc.v:13564.3-13579.6" - process $proc$libresoc.v:13564$268 + attribute \src "libresoc.v:13640.3-13655.6" + process $proc$libresoc.v:13640$268 assign { } { } assign { } { } assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13565.5-13565.29" + attribute \src "libresoc.v:13641.5-13641.29" switch \initial - attribute \src "libresoc.v:13565.9-13565.17" + attribute \src "libresoc.v:13641.9-13641.17" case 1'1 case end @@ -19357,14 +19433,14 @@ module \LDST_dec58 sync always update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:13580.3-13595.6" - process $proc$libresoc.v:13580$269 + attribute \src "libresoc.v:13656.3-13671.6" + process $proc$libresoc.v:13656$269 assign { } { } assign { } { } assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13581.5-13581.29" + attribute \src "libresoc.v:13657.5-13657.29" switch \initial - attribute \src "libresoc.v:13581.9-13581.17" + attribute \src "libresoc.v:13657.9-13657.17" case 1'1 case end @@ -19388,14 +19464,14 @@ module \LDST_dec58 sync always update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] end - attribute \src "libresoc.v:13596.3-13611.6" - process $proc$libresoc.v:13596$270 + attribute \src "libresoc.v:13672.3-13687.6" + process $proc$libresoc.v:13672$270 assign { } { } assign { } { } assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13597.5-13597.29" + attribute \src "libresoc.v:13673.5-13673.29" switch \initial - attribute \src "libresoc.v:13597.9-13597.17" + attribute \src "libresoc.v:13673.9-13673.17" case 1'1 case end @@ -19419,14 +19495,14 @@ module \LDST_dec58 sync always update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] end - attribute \src "libresoc.v:13612.3-13627.6" - process $proc$libresoc.v:13612$271 + attribute \src "libresoc.v:13688.3-13703.6" + process $proc$libresoc.v:13688$271 assign { } { } assign { } { } assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13613.5-13613.29" + attribute \src "libresoc.v:13689.5-13689.29" switch \initial - attribute \src "libresoc.v:13613.9-13613.17" + attribute \src "libresoc.v:13689.9-13689.17" case 1'1 case end @@ -19450,14 +19526,14 @@ module \LDST_dec58 sync always update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] end - attribute \src "libresoc.v:13628.3-13643.6" - process $proc$libresoc.v:13628$272 + attribute \src "libresoc.v:13704.3-13719.6" + process $proc$libresoc.v:13704$272 assign { } { } assign { } { } assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13629.5-13629.29" + attribute \src "libresoc.v:13705.5-13705.29" switch \initial - attribute \src "libresoc.v:13629.9-13629.17" + attribute \src "libresoc.v:13705.9-13705.17" case 1'1 case end @@ -19481,14 +19557,14 @@ module \LDST_dec58 sync always update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] end - attribute \src "libresoc.v:13644.3-13659.6" - process $proc$libresoc.v:13644$273 + attribute \src "libresoc.v:13720.3-13735.6" + process $proc$libresoc.v:13720$273 assign { } { } assign { } { } assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13645.5-13645.29" + attribute \src "libresoc.v:13721.5-13721.29" switch \initial - attribute \src "libresoc.v:13645.9-13645.17" + attribute \src "libresoc.v:13721.9-13721.17" case 1'1 case end @@ -19512,14 +19588,14 @@ module \LDST_dec58 sync always update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] end - attribute \src "libresoc.v:13660.3-13675.6" - process $proc$libresoc.v:13660$274 + attribute \src "libresoc.v:13736.3-13751.6" + process $proc$libresoc.v:13736$274 assign { } { } assign { } { } assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13661.5-13661.29" + attribute \src "libresoc.v:13737.5-13737.29" switch \initial - attribute \src "libresoc.v:13661.9-13661.17" + attribute \src "libresoc.v:13737.9-13737.17" case 1'1 case end @@ -19543,14 +19619,14 @@ module \LDST_dec58 sync always update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] end - attribute \src "libresoc.v:13676.3-13691.6" - process $proc$libresoc.v:13676$275 + attribute \src "libresoc.v:13752.3-13767.6" + process $proc$libresoc.v:13752$275 assign { } { } assign { } { } assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13677.5-13677.29" + attribute \src "libresoc.v:13753.5-13753.29" switch \initial - attribute \src "libresoc.v:13677.9-13677.17" + attribute \src "libresoc.v:13753.9-13753.17" case 1'1 case end @@ -19574,14 +19650,14 @@ module \LDST_dec58 sync always update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] end - attribute \src "libresoc.v:13692.3-13707.6" - process $proc$libresoc.v:13692$276 + attribute \src "libresoc.v:13768.3-13783.6" + process $proc$libresoc.v:13768$276 assign { } { } assign { } { } assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13693.5-13693.29" + attribute \src "libresoc.v:13769.5-13769.29" switch \initial - attribute \src "libresoc.v:13693.9-13693.17" + attribute \src "libresoc.v:13769.9-13769.17" case 1'1 case end @@ -19605,14 +19681,14 @@ module \LDST_dec58 sync always update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] end - attribute \src "libresoc.v:13708.3-13723.6" - process $proc$libresoc.v:13708$277 + attribute \src "libresoc.v:13784.3-13799.6" + process $proc$libresoc.v:13784$277 assign { } { } assign { } { } assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] - attribute \src "libresoc.v:13709.5-13709.29" + attribute \src "libresoc.v:13785.5-13785.29" switch \initial - attribute \src "libresoc.v:13709.9-13709.17" + attribute \src "libresoc.v:13785.9-13785.17" case 1'1 case end @@ -19636,14 +19712,14 @@ module \LDST_dec58 sync always update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] end - attribute \src "libresoc.v:13724.3-13739.6" - process $proc$libresoc.v:13724$278 + attribute \src "libresoc.v:13800.3-13815.6" + process $proc$libresoc.v:13800$278 assign { } { } assign { } { } assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13725.5-13725.29" + attribute \src "libresoc.v:13801.5-13801.29" switch \initial - attribute \src "libresoc.v:13725.9-13725.17" + attribute \src "libresoc.v:13801.9-13801.17" case 1'1 case end @@ -19669,64 +19745,64 @@ module \LDST_dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:13745.1-14100.10" +attribute \src "libresoc.v:13821.1-14178.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" attribute \generator "nMigen" module \LDST_dec62 - attribute \src "libresoc.v:13943.3-13955.6" + attribute \src "libresoc.v:14021.3-14033.6" wire $0\LDST_dec62_br[0:0] - attribute \src "libresoc.v:14034.3-14046.6" + attribute \src "libresoc.v:14112.3-14124.6" wire width 3 $0\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:14047.3-14059.6" + attribute \src "libresoc.v:14125.3-14137.6" wire width 3 $0\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:13930.3-13942.6" - wire width 13 $0\LDST_dec62_function_unit[12:0] attribute \src "libresoc.v:14008.3-14020.6" + wire width 14 $0\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14086.3-14098.6" wire width 3 $0\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:14021.3-14033.6" + attribute \src "libresoc.v:14099.3-14111.6" wire width 4 $0\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:13995.3-14007.6" + attribute \src "libresoc.v:14073.3-14085.6" wire width 7 $0\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13969.3-13981.6" + attribute \src "libresoc.v:14047.3-14059.6" wire $0\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:14060.3-14072.6" + attribute \src "libresoc.v:14138.3-14150.6" wire width 4 $0\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:14086.3-14098.6" + attribute \src "libresoc.v:14164.3-14176.6" wire width 2 $0\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:13982.3-13994.6" + attribute \src "libresoc.v:14060.3-14072.6" wire $0\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13956.3-13968.6" + attribute \src "libresoc.v:14034.3-14046.6" wire $0\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:14073.3-14085.6" + attribute \src "libresoc.v:14151.3-14163.6" wire width 2 $0\LDST_dec62_upd[1:0] - attribute \src "libresoc.v:13746.7-13746.20" + attribute \src "libresoc.v:13822.7-13822.20" wire $0\initial[0:0] - attribute \src "libresoc.v:13943.3-13955.6" + attribute \src "libresoc.v:14021.3-14033.6" wire $1\LDST_dec62_br[0:0] - attribute \src "libresoc.v:14034.3-14046.6" + attribute \src "libresoc.v:14112.3-14124.6" wire width 3 $1\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:14047.3-14059.6" + attribute \src "libresoc.v:14125.3-14137.6" wire width 3 $1\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:13930.3-13942.6" - wire width 13 $1\LDST_dec62_function_unit[12:0] attribute \src "libresoc.v:14008.3-14020.6" + wire width 14 $1\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14086.3-14098.6" wire width 3 $1\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:14021.3-14033.6" + attribute \src "libresoc.v:14099.3-14111.6" wire width 4 $1\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:13995.3-14007.6" + attribute \src "libresoc.v:14073.3-14085.6" wire width 7 $1\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13969.3-13981.6" + attribute \src "libresoc.v:14047.3-14059.6" wire $1\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:14060.3-14072.6" + attribute \src "libresoc.v:14138.3-14150.6" wire width 4 $1\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:14086.3-14098.6" + attribute \src "libresoc.v:14164.3-14176.6" wire width 2 $1\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:13982.3-13994.6" + attribute \src "libresoc.v:14060.3-14072.6" wire $1\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13956.3-13968.6" + attribute \src "libresoc.v:14034.3-14046.6" wire $1\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:14073.3-14085.6" + attribute \src "libresoc.v:14151.3-14163.6" wire width 2 $1\LDST_dec62_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \LDST_dec62_br @@ -19751,21 +19827,22 @@ module \LDST_dec62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 6 \LDST_dec62_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LDST_dec62_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -19865,6 +19942,7 @@ module \LDST_dec62 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LDST_dec62_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -19894,28 +19972,28 @@ module \LDST_dec62 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 8 \LDST_dec62_upd - attribute \src "libresoc.v:13746.7-13746.15" + attribute \src "libresoc.v:13822.7-13822.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 2 \opcode_switch - attribute \src "libresoc.v:13746.7-13746.20" - process $proc$libresoc.v:13746$293 + attribute \src "libresoc.v:13822.7-13822.20" + process $proc$libresoc.v:13822$293 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:13930.3-13942.6" - process $proc$libresoc.v:13930$280 + attribute \src "libresoc.v:14008.3-14020.6" + process $proc$libresoc.v:14008$280 assign { } { } assign { } { } - assign $0\LDST_dec62_function_unit[12:0] $1\LDST_dec62_function_unit[12:0] - attribute \src "libresoc.v:13931.5-13931.29" + assign $0\LDST_dec62_function_unit[13:0] $1\LDST_dec62_function_unit[13:0] + attribute \src "libresoc.v:14009.5-14009.29" switch \initial - attribute \src "libresoc.v:13931.9-13931.17" + attribute \src "libresoc.v:14009.9-14009.17" case 1'1 case end @@ -19924,25 +20002,25 @@ module \LDST_dec62 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\LDST_dec62_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\LDST_dec62_function_unit[12:0] 13'0000000000100 + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_dec62_function_unit[12:0] 13'0000000000000 + assign $1\LDST_dec62_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[12:0] + update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[13:0] end - attribute \src "libresoc.v:13943.3-13955.6" - process $proc$libresoc.v:13943$281 + attribute \src "libresoc.v:14021.3-14033.6" + process $proc$libresoc.v:14021$281 assign { } { } assign { } { } assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] - attribute \src "libresoc.v:13944.5-13944.29" + attribute \src "libresoc.v:14022.5-14022.29" switch \initial - attribute \src "libresoc.v:13944.9-13944.17" + attribute \src "libresoc.v:14022.9-14022.17" case 1'1 case end @@ -19962,14 +20040,14 @@ module \LDST_dec62 sync always update \LDST_dec62_br $0\LDST_dec62_br[0:0] end - attribute \src "libresoc.v:13956.3-13968.6" - process $proc$libresoc.v:13956$282 + attribute \src "libresoc.v:14034.3-14046.6" + process $proc$libresoc.v:14034$282 assign { } { } assign { } { } assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:13957.5-13957.29" + attribute \src "libresoc.v:14035.5-14035.29" switch \initial - attribute \src "libresoc.v:13957.9-13957.17" + attribute \src "libresoc.v:14035.9-14035.17" case 1'1 case end @@ -19989,14 +20067,14 @@ module \LDST_dec62 sync always update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:13969.3-13981.6" - process $proc$libresoc.v:13969$283 + attribute \src "libresoc.v:14047.3-14059.6" + process $proc$libresoc.v:14047$283 assign { } { } assign { } { } assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:13970.5-13970.29" + attribute \src "libresoc.v:14048.5-14048.29" switch \initial - attribute \src "libresoc.v:13970.9-13970.17" + attribute \src "libresoc.v:14048.9-14048.17" case 1'1 case end @@ -20016,14 +20094,14 @@ module \LDST_dec62 sync always update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] end - attribute \src "libresoc.v:13982.3-13994.6" - process $proc$libresoc.v:13982$284 + attribute \src "libresoc.v:14060.3-14072.6" + process $proc$libresoc.v:14060$284 assign { } { } assign { } { } assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13983.5-13983.29" + attribute \src "libresoc.v:14061.5-14061.29" switch \initial - attribute \src "libresoc.v:13983.9-13983.17" + attribute \src "libresoc.v:14061.9-14061.17" case 1'1 case end @@ -20043,14 +20121,14 @@ module \LDST_dec62 sync always update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] end - attribute \src "libresoc.v:13995.3-14007.6" - process $proc$libresoc.v:13995$285 + attribute \src "libresoc.v:14073.3-14085.6" + process $proc$libresoc.v:14073$285 assign { } { } assign { } { } assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13996.5-13996.29" + attribute \src "libresoc.v:14074.5-14074.29" switch \initial - attribute \src "libresoc.v:13996.9-13996.17" + attribute \src "libresoc.v:14074.9-14074.17" case 1'1 case end @@ -20070,14 +20148,14 @@ module \LDST_dec62 sync always update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] end - attribute \src "libresoc.v:14008.3-14020.6" - process $proc$libresoc.v:14008$286 + attribute \src "libresoc.v:14086.3-14098.6" + process $proc$libresoc.v:14086$286 assign { } { } assign { } { } assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:14009.5-14009.29" + attribute \src "libresoc.v:14087.5-14087.29" switch \initial - attribute \src "libresoc.v:14009.9-14009.17" + attribute \src "libresoc.v:14087.9-14087.17" case 1'1 case end @@ -20097,14 +20175,14 @@ module \LDST_dec62 sync always update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] end - attribute \src "libresoc.v:14021.3-14033.6" - process $proc$libresoc.v:14021$287 + attribute \src "libresoc.v:14099.3-14111.6" + process $proc$libresoc.v:14099$287 assign { } { } assign { } { } assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:14022.5-14022.29" + attribute \src "libresoc.v:14100.5-14100.29" switch \initial - attribute \src "libresoc.v:14022.9-14022.17" + attribute \src "libresoc.v:14100.9-14100.17" case 1'1 case end @@ -20124,14 +20202,14 @@ module \LDST_dec62 sync always update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] end - attribute \src "libresoc.v:14034.3-14046.6" - process $proc$libresoc.v:14034$288 + attribute \src "libresoc.v:14112.3-14124.6" + process $proc$libresoc.v:14112$288 assign { } { } assign { } { } assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:14035.5-14035.29" + attribute \src "libresoc.v:14113.5-14113.29" switch \initial - attribute \src "libresoc.v:14035.9-14035.17" + attribute \src "libresoc.v:14113.9-14113.17" case 1'1 case end @@ -20151,14 +20229,14 @@ module \LDST_dec62 sync always update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] end - attribute \src "libresoc.v:14047.3-14059.6" - process $proc$libresoc.v:14047$289 + attribute \src "libresoc.v:14125.3-14137.6" + process $proc$libresoc.v:14125$289 assign { } { } assign { } { } assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:14048.5-14048.29" + attribute \src "libresoc.v:14126.5-14126.29" switch \initial - attribute \src "libresoc.v:14048.9-14048.17" + attribute \src "libresoc.v:14126.9-14126.17" case 1'1 case end @@ -20178,14 +20256,14 @@ module \LDST_dec62 sync always update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] end - attribute \src "libresoc.v:14060.3-14072.6" - process $proc$libresoc.v:14060$290 + attribute \src "libresoc.v:14138.3-14150.6" + process $proc$libresoc.v:14138$290 assign { } { } assign { } { } assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:14061.5-14061.29" + attribute \src "libresoc.v:14139.5-14139.29" switch \initial - attribute \src "libresoc.v:14061.9-14061.17" + attribute \src "libresoc.v:14139.9-14139.17" case 1'1 case end @@ -20205,14 +20283,14 @@ module \LDST_dec62 sync always update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] end - attribute \src "libresoc.v:14073.3-14085.6" - process $proc$libresoc.v:14073$291 + attribute \src "libresoc.v:14151.3-14163.6" + process $proc$libresoc.v:14151$291 assign { } { } assign { } { } assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] - attribute \src "libresoc.v:14074.5-14074.29" + attribute \src "libresoc.v:14152.5-14152.29" switch \initial - attribute \src "libresoc.v:14074.9-14074.17" + attribute \src "libresoc.v:14152.9-14152.17" case 1'1 case end @@ -20232,14 +20310,14 @@ module \LDST_dec62 sync always update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] end - attribute \src "libresoc.v:14086.3-14098.6" - process $proc$libresoc.v:14086$292 + attribute \src "libresoc.v:14164.3-14176.6" + process $proc$libresoc.v:14164$292 assign { } { } assign { } { } assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:14087.5-14087.29" + attribute \src "libresoc.v:14165.5-14165.29" switch \initial - attribute \src "libresoc.v:14087.9-14087.17" + attribute \src "libresoc.v:14165.9-14165.17" case 1'1 case end @@ -20261,68 +20339,68 @@ module \LDST_dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:14104.1-14851.10" +attribute \src "libresoc.v:14182.1-14935.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" attribute \generator "nMigen" module \LOGICAL_dec31 - attribute \src "libresoc.v:14821.3-14833.6" + attribute \src "libresoc.v:14905.3-14917.6" wire width 3 $0\LOGICAL_dec31_cr_in[2:0] - attribute \src "libresoc.v:14834.3-14846.6" + attribute \src "libresoc.v:14918.3-14930.6" wire width 3 $0\LOGICAL_dec31_cr_out[2:0] - attribute \src "libresoc.v:14691.3-14703.6" + attribute \src "libresoc.v:14775.3-14787.6" wire width 2 $0\LOGICAL_dec31_cry_in[1:0] - attribute \src "libresoc.v:14730.3-14742.6" + attribute \src "libresoc.v:14814.3-14826.6" wire $0\LOGICAL_dec31_cry_out[0:0] - attribute \src "libresoc.v:14769.3-14781.6" - wire width 13 $0\LOGICAL_dec31_function_unit[12:0] - attribute \src "libresoc.v:14795.3-14807.6" + attribute \src "libresoc.v:14853.3-14865.6" + wire width 14 $0\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14879.3-14891.6" wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] - attribute \src "libresoc.v:14808.3-14820.6" + attribute \src "libresoc.v:14892.3-14904.6" wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:14782.3-14794.6" + attribute \src "libresoc.v:14866.3-14878.6" wire width 7 $0\LOGICAL_dec31_internal_op[6:0] - attribute \src "libresoc.v:14704.3-14716.6" + attribute \src "libresoc.v:14788.3-14800.6" wire $0\LOGICAL_dec31_inv_a[0:0] - attribute \src "libresoc.v:14717.3-14729.6" + attribute \src "libresoc.v:14801.3-14813.6" wire $0\LOGICAL_dec31_inv_out[0:0] - attribute \src "libresoc.v:14743.3-14755.6" + attribute \src "libresoc.v:14827.3-14839.6" wire $0\LOGICAL_dec31_is_32b[0:0] - attribute \src "libresoc.v:14665.3-14677.6" + attribute \src "libresoc.v:14749.3-14761.6" wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] - attribute \src "libresoc.v:14678.3-14690.6" + attribute \src "libresoc.v:14762.3-14774.6" wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:14756.3-14768.6" + attribute \src "libresoc.v:14840.3-14852.6" wire $0\LOGICAL_dec31_sgn[0:0] - attribute \src "libresoc.v:14105.7-14105.20" + attribute \src "libresoc.v:14183.7-14183.20" wire $0\initial[0:0] - attribute \src "libresoc.v:14821.3-14833.6" + attribute \src "libresoc.v:14905.3-14917.6" wire width 3 $1\LOGICAL_dec31_cr_in[2:0] - attribute \src "libresoc.v:14834.3-14846.6" + attribute \src "libresoc.v:14918.3-14930.6" wire width 3 $1\LOGICAL_dec31_cr_out[2:0] - attribute \src "libresoc.v:14691.3-14703.6" + attribute \src "libresoc.v:14775.3-14787.6" wire width 2 $1\LOGICAL_dec31_cry_in[1:0] - attribute \src "libresoc.v:14730.3-14742.6" + attribute \src "libresoc.v:14814.3-14826.6" wire $1\LOGICAL_dec31_cry_out[0:0] - attribute \src "libresoc.v:14769.3-14781.6" - wire width 13 $1\LOGICAL_dec31_function_unit[12:0] - attribute \src "libresoc.v:14795.3-14807.6" + attribute \src "libresoc.v:14853.3-14865.6" + wire width 14 $1\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14879.3-14891.6" wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] - attribute \src "libresoc.v:14808.3-14820.6" + attribute \src "libresoc.v:14892.3-14904.6" wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:14782.3-14794.6" + attribute \src "libresoc.v:14866.3-14878.6" wire width 7 $1\LOGICAL_dec31_internal_op[6:0] - attribute \src "libresoc.v:14704.3-14716.6" + attribute \src "libresoc.v:14788.3-14800.6" wire $1\LOGICAL_dec31_inv_a[0:0] - attribute \src "libresoc.v:14717.3-14729.6" + attribute \src "libresoc.v:14801.3-14813.6" wire $1\LOGICAL_dec31_inv_out[0:0] - attribute \src "libresoc.v:14743.3-14755.6" + attribute \src "libresoc.v:14827.3-14839.6" wire $1\LOGICAL_dec31_is_32b[0:0] - attribute \src "libresoc.v:14665.3-14677.6" + attribute \src "libresoc.v:14749.3-14761.6" wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] - attribute \src "libresoc.v:14678.3-14690.6" + attribute \src "libresoc.v:14762.3-14774.6" wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:14756.3-14768.6" + attribute \src "libresoc.v:14840.3-14852.6" wire $1\LOGICAL_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20381,21 +20459,22 @@ module \LOGICAL_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -20495,6 +20574,7 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -20550,21 +20630,22 @@ module \LOGICAL_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -20664,6 +20745,7 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -20691,21 +20773,22 @@ module \LOGICAL_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LOGICAL_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -20805,6 +20888,7 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LOGICAL_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -20829,7 +20913,7 @@ module \LOGICAL_dec31 wire width 2 output 8 \LOGICAL_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \LOGICAL_dec31_sgn - attribute \src "libresoc.v:14105.7-14105.15" + attribute \src "libresoc.v:14183.7-14183.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -20838,7 +20922,7 @@ module \LOGICAL_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:14631.27-14647.4" + attribute \src "libresoc.v:14715.27-14731.4" cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out @@ -20857,7 +20941,7 @@ module \LOGICAL_dec31 connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:14648.27-14664.4" + attribute \src "libresoc.v:14732.27-14748.4" cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out @@ -20875,22 +20959,22 @@ module \LOGICAL_dec31 connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in end - attribute \src "libresoc.v:14105.7-14105.20" - process $proc$libresoc.v:14105$308 + attribute \src "libresoc.v:14183.7-14183.20" + process $proc$libresoc.v:14183$308 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:14665.3-14677.6" - process $proc$libresoc.v:14665$294 + attribute \src "libresoc.v:14749.3-14761.6" + process $proc$libresoc.v:14749$294 assign { } { } assign { } { } assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] - attribute \src "libresoc.v:14666.5-14666.29" + attribute \src "libresoc.v:14750.5-14750.29" switch \initial - attribute \src "libresoc.v:14666.9-14666.17" + attribute \src "libresoc.v:14750.9-14750.17" case 1'1 case end @@ -20910,14 +20994,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] end - attribute \src "libresoc.v:14678.3-14690.6" - process $proc$libresoc.v:14678$295 + attribute \src "libresoc.v:14762.3-14774.6" + process $proc$libresoc.v:14762$295 assign { } { } assign { } { } assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:14679.5-14679.29" + attribute \src "libresoc.v:14763.5-14763.29" switch \initial - attribute \src "libresoc.v:14679.9-14679.17" + attribute \src "libresoc.v:14763.9-14763.17" case 1'1 case end @@ -20937,14 +21021,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:14691.3-14703.6" - process $proc$libresoc.v:14691$296 + attribute \src "libresoc.v:14775.3-14787.6" + process $proc$libresoc.v:14775$296 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] - attribute \src "libresoc.v:14692.5-14692.29" + attribute \src "libresoc.v:14776.5-14776.29" switch \initial - attribute \src "libresoc.v:14692.9-14692.17" + attribute \src "libresoc.v:14776.9-14776.17" case 1'1 case end @@ -20964,14 +21048,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] end - attribute \src "libresoc.v:14704.3-14716.6" - process $proc$libresoc.v:14704$297 + attribute \src "libresoc.v:14788.3-14800.6" + process $proc$libresoc.v:14788$297 assign { } { } assign { } { } assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] - attribute \src "libresoc.v:14705.5-14705.29" + attribute \src "libresoc.v:14789.5-14789.29" switch \initial - attribute \src "libresoc.v:14705.9-14705.17" + attribute \src "libresoc.v:14789.9-14789.17" case 1'1 case end @@ -20991,14 +21075,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] end - attribute \src "libresoc.v:14717.3-14729.6" - process $proc$libresoc.v:14717$298 + attribute \src "libresoc.v:14801.3-14813.6" + process $proc$libresoc.v:14801$298 assign { } { } assign { } { } assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] - attribute \src "libresoc.v:14718.5-14718.29" + attribute \src "libresoc.v:14802.5-14802.29" switch \initial - attribute \src "libresoc.v:14718.9-14718.17" + attribute \src "libresoc.v:14802.9-14802.17" case 1'1 case end @@ -21018,14 +21102,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] end - attribute \src "libresoc.v:14730.3-14742.6" - process $proc$libresoc.v:14730$299 + attribute \src "libresoc.v:14814.3-14826.6" + process $proc$libresoc.v:14814$299 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] - attribute \src "libresoc.v:14731.5-14731.29" + attribute \src "libresoc.v:14815.5-14815.29" switch \initial - attribute \src "libresoc.v:14731.9-14731.17" + attribute \src "libresoc.v:14815.9-14815.17" case 1'1 case end @@ -21045,14 +21129,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] end - attribute \src "libresoc.v:14743.3-14755.6" - process $proc$libresoc.v:14743$300 + attribute \src "libresoc.v:14827.3-14839.6" + process $proc$libresoc.v:14827$300 assign { } { } assign { } { } assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] - attribute \src "libresoc.v:14744.5-14744.29" + attribute \src "libresoc.v:14828.5-14828.29" switch \initial - attribute \src "libresoc.v:14744.9-14744.17" + attribute \src "libresoc.v:14828.9-14828.17" case 1'1 case end @@ -21072,14 +21156,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] end - attribute \src "libresoc.v:14756.3-14768.6" - process $proc$libresoc.v:14756$301 + attribute \src "libresoc.v:14840.3-14852.6" + process $proc$libresoc.v:14840$301 assign { } { } assign { } { } assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] - attribute \src "libresoc.v:14757.5-14757.29" + attribute \src "libresoc.v:14841.5-14841.29" switch \initial - attribute \src "libresoc.v:14757.9-14757.17" + attribute \src "libresoc.v:14841.9-14841.17" case 1'1 case end @@ -21099,14 +21183,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] end - attribute \src "libresoc.v:14769.3-14781.6" - process $proc$libresoc.v:14769$302 + attribute \src "libresoc.v:14853.3-14865.6" + process $proc$libresoc.v:14853$302 assign { } { } assign { } { } - assign $0\LOGICAL_dec31_function_unit[12:0] $1\LOGICAL_dec31_function_unit[12:0] - attribute \src "libresoc.v:14770.5-14770.29" + assign $0\LOGICAL_dec31_function_unit[13:0] $1\LOGICAL_dec31_function_unit[13:0] + attribute \src "libresoc.v:14854.5-14854.29" switch \initial - attribute \src "libresoc.v:14770.9-14770.17" + attribute \src "libresoc.v:14854.9-14854.17" case 1'1 case end @@ -21115,25 +21199,25 @@ module \LOGICAL_dec31 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\LOGICAL_dec31_function_unit[12:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + assign $1\LOGICAL_dec31_function_unit[13:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\LOGICAL_dec31_function_unit[12:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + assign $1\LOGICAL_dec31_function_unit[13:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit case - assign $1\LOGICAL_dec31_function_unit[12:0] 13'0000000000000 + assign $1\LOGICAL_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[12:0] + update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[13:0] end - attribute \src "libresoc.v:14782.3-14794.6" - process $proc$libresoc.v:14782$303 + attribute \src "libresoc.v:14866.3-14878.6" + process $proc$libresoc.v:14866$303 assign { } { } assign { } { } assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] - attribute \src "libresoc.v:14783.5-14783.29" + attribute \src "libresoc.v:14867.5-14867.29" switch \initial - attribute \src "libresoc.v:14783.9-14783.17" + attribute \src "libresoc.v:14867.9-14867.17" case 1'1 case end @@ -21153,14 +21237,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] end - attribute \src "libresoc.v:14795.3-14807.6" - process $proc$libresoc.v:14795$304 + attribute \src "libresoc.v:14879.3-14891.6" + process $proc$libresoc.v:14879$304 assign { } { } assign { } { } assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] - attribute \src "libresoc.v:14796.5-14796.29" + attribute \src "libresoc.v:14880.5-14880.29" switch \initial - attribute \src "libresoc.v:14796.9-14796.17" + attribute \src "libresoc.v:14880.9-14880.17" case 1'1 case end @@ -21180,14 +21264,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] end - attribute \src "libresoc.v:14808.3-14820.6" - process $proc$libresoc.v:14808$305 + attribute \src "libresoc.v:14892.3-14904.6" + process $proc$libresoc.v:14892$305 assign { } { } assign { } { } assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:14809.5-14809.29" + attribute \src "libresoc.v:14893.5-14893.29" switch \initial - attribute \src "libresoc.v:14809.9-14809.17" + attribute \src "libresoc.v:14893.9-14893.17" case 1'1 case end @@ -21207,14 +21291,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:14821.3-14833.6" - process $proc$libresoc.v:14821$306 + attribute \src "libresoc.v:14905.3-14917.6" + process $proc$libresoc.v:14905$306 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] - attribute \src "libresoc.v:14822.5-14822.29" + attribute \src "libresoc.v:14906.5-14906.29" switch \initial - attribute \src "libresoc.v:14822.9-14822.17" + attribute \src "libresoc.v:14906.9-14906.17" case 1'1 case end @@ -21234,14 +21318,14 @@ module \LOGICAL_dec31 sync always update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] end - attribute \src "libresoc.v:14834.3-14846.6" - process $proc$libresoc.v:14834$307 + attribute \src "libresoc.v:14918.3-14930.6" + process $proc$libresoc.v:14918$307 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] - attribute \src "libresoc.v:14835.5-14835.29" + attribute \src "libresoc.v:14919.5-14919.29" switch \initial - attribute \src "libresoc.v:14835.9-14835.17" + attribute \src "libresoc.v:14919.9-14919.17" case 1'1 case end @@ -21266,68 +21350,68 @@ module \LOGICAL_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:14855.1-15519.10" +attribute \src "libresoc.v:14939.1-15605.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" attribute \generator "nMigen" module \LOGICAL_dec31_dec_sub26 - attribute \src "libresoc.v:15348.3-15381.6" + attribute \src "libresoc.v:15434.3-15467.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15382.3-15415.6" + attribute \src "libresoc.v:15468.3-15501.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15484.3-15517.6" + attribute \src "libresoc.v:15570.3-15603.6" wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15144.3-15177.6" + attribute \src "libresoc.v:15230.3-15263.6" wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:15042.3-15075.6" - wire width 13 $0\LOGICAL_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:15280.3-15313.6" + attribute \src "libresoc.v:15128.3-15161.6" + wire width 14 $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15366.3-15399.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15314.3-15347.6" + attribute \src "libresoc.v:15400.3-15433.6" wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15246.3-15279.6" + attribute \src "libresoc.v:15332.3-15365.6" wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:15076.3-15109.6" + attribute \src "libresoc.v:15162.3-15195.6" wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:15110.3-15143.6" + attribute \src "libresoc.v:15196.3-15229.6" wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:15178.3-15211.6" + attribute \src "libresoc.v:15264.3-15297.6" wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15416.3-15449.6" + attribute \src "libresoc.v:15502.3-15535.6" wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15450.3-15483.6" + attribute \src "libresoc.v:15536.3-15569.6" wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15212.3-15245.6" + attribute \src "libresoc.v:15298.3-15331.6" wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:14856.7-14856.20" + attribute \src "libresoc.v:14940.7-14940.20" wire $0\initial[0:0] - attribute \src "libresoc.v:15348.3-15381.6" + attribute \src "libresoc.v:15434.3-15467.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15382.3-15415.6" + attribute \src "libresoc.v:15468.3-15501.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15484.3-15517.6" + attribute \src "libresoc.v:15570.3-15603.6" wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15144.3-15177.6" + attribute \src "libresoc.v:15230.3-15263.6" wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:15042.3-15075.6" - wire width 13 $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:15280.3-15313.6" + attribute \src "libresoc.v:15128.3-15161.6" + wire width 14 $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15366.3-15399.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15314.3-15347.6" + attribute \src "libresoc.v:15400.3-15433.6" wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15246.3-15279.6" + attribute \src "libresoc.v:15332.3-15365.6" wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:15076.3-15109.6" + attribute \src "libresoc.v:15162.3-15195.6" wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:15110.3-15143.6" + attribute \src "libresoc.v:15196.3-15229.6" wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:15178.3-15211.6" + attribute \src "libresoc.v:15264.3-15297.6" wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15416.3-15449.6" + attribute \src "libresoc.v:15502.3-15535.6" wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15450.3-15483.6" + attribute \src "libresoc.v:15536.3-15569.6" wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15212.3-15245.6" + attribute \src "libresoc.v:15298.3-15331.6" wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -21358,21 +21442,22 @@ module \LOGICAL_dec31_dec_sub26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -21472,6 +21557,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -21496,28 +21582,28 @@ module \LOGICAL_dec31_dec_sub26 wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \LOGICAL_dec31_dec_sub26_sgn - attribute \src "libresoc.v:14856.7-14856.15" + attribute \src "libresoc.v:14940.7-14940.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:14856.7-14856.20" - process $proc$libresoc.v:14856$323 + attribute \src "libresoc.v:14940.7-14940.20" + process $proc$libresoc.v:14940$323 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:15042.3-15075.6" - process $proc$libresoc.v:15042$309 + attribute \src "libresoc.v:15128.3-15161.6" + process $proc$libresoc.v:15128$309 assign { } { } assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_function_unit[12:0] $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:15043.5-15043.29" + assign $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:15129.5-15129.29" switch \initial - attribute \src "libresoc.v:15043.9-15043.17" + attribute \src "libresoc.v:15129.9-15129.17" case 1'1 case end @@ -21526,53 +21612,53 @@ module \LOGICAL_dec31_dec_sub26 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 case - assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000000000 + assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always - update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[12:0] + update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:15076.3-15109.6" - process $proc$libresoc.v:15076$310 + attribute \src "libresoc.v:15162.3-15195.6" + process $proc$libresoc.v:15162$310 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:15077.5-15077.29" + attribute \src "libresoc.v:15163.5-15163.29" switch \initial - attribute \src "libresoc.v:15077.9-15077.17" + attribute \src "libresoc.v:15163.9-15163.17" case 1'1 case end @@ -21620,14 +21706,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:15110.3-15143.6" - process $proc$libresoc.v:15110$311 + attribute \src "libresoc.v:15196.3-15229.6" + process $proc$libresoc.v:15196$311 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:15111.5-15111.29" + attribute \src "libresoc.v:15197.5-15197.29" switch \initial - attribute \src "libresoc.v:15111.9-15111.17" + attribute \src "libresoc.v:15197.9-15197.17" case 1'1 case end @@ -21675,14 +21761,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:15144.3-15177.6" - process $proc$libresoc.v:15144$312 + attribute \src "libresoc.v:15230.3-15263.6" + process $proc$libresoc.v:15230$312 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:15145.5-15145.29" + attribute \src "libresoc.v:15231.5-15231.29" switch \initial - attribute \src "libresoc.v:15145.9-15145.17" + attribute \src "libresoc.v:15231.9-15231.17" case 1'1 case end @@ -21730,14 +21816,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:15178.3-15211.6" - process $proc$libresoc.v:15178$313 + attribute \src "libresoc.v:15264.3-15297.6" + process $proc$libresoc.v:15264$313 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15179.5-15179.29" + attribute \src "libresoc.v:15265.5-15265.29" switch \initial - attribute \src "libresoc.v:15179.9-15179.17" + attribute \src "libresoc.v:15265.9-15265.17" case 1'1 case end @@ -21785,14 +21871,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:15212.3-15245.6" - process $proc$libresoc.v:15212$314 + attribute \src "libresoc.v:15298.3-15331.6" + process $proc$libresoc.v:15298$314 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:15213.5-15213.29" + attribute \src "libresoc.v:15299.5-15299.29" switch \initial - attribute \src "libresoc.v:15213.9-15213.17" + attribute \src "libresoc.v:15299.9-15299.17" case 1'1 case end @@ -21840,14 +21926,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:15246.3-15279.6" - process $proc$libresoc.v:15246$315 + attribute \src "libresoc.v:15332.3-15365.6" + process $proc$libresoc.v:15332$315 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:15247.5-15247.29" + attribute \src "libresoc.v:15333.5-15333.29" switch \initial - attribute \src "libresoc.v:15247.9-15247.17" + attribute \src "libresoc.v:15333.9-15333.17" case 1'1 case end @@ -21895,14 +21981,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:15280.3-15313.6" - process $proc$libresoc.v:15280$316 + attribute \src "libresoc.v:15366.3-15399.6" + process $proc$libresoc.v:15366$316 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15281.5-15281.29" + attribute \src "libresoc.v:15367.5-15367.29" switch \initial - attribute \src "libresoc.v:15281.9-15281.17" + attribute \src "libresoc.v:15367.9-15367.17" case 1'1 case end @@ -21950,14 +22036,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:15314.3-15347.6" - process $proc$libresoc.v:15314$317 + attribute \src "libresoc.v:15400.3-15433.6" + process $proc$libresoc.v:15400$317 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15315.5-15315.29" + attribute \src "libresoc.v:15401.5-15401.29" switch \initial - attribute \src "libresoc.v:15315.9-15315.17" + attribute \src "libresoc.v:15401.9-15401.17" case 1'1 case end @@ -22005,14 +22091,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:15348.3-15381.6" - process $proc$libresoc.v:15348$318 + attribute \src "libresoc.v:15434.3-15467.6" + process $proc$libresoc.v:15434$318 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15349.5-15349.29" + attribute \src "libresoc.v:15435.5-15435.29" switch \initial - attribute \src "libresoc.v:15349.9-15349.17" + attribute \src "libresoc.v:15435.9-15435.17" case 1'1 case end @@ -22060,14 +22146,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:15382.3-15415.6" - process $proc$libresoc.v:15382$319 + attribute \src "libresoc.v:15468.3-15501.6" + process $proc$libresoc.v:15468$319 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15383.5-15383.29" + attribute \src "libresoc.v:15469.5-15469.29" switch \initial - attribute \src "libresoc.v:15383.9-15383.17" + attribute \src "libresoc.v:15469.9-15469.17" case 1'1 case end @@ -22115,14 +22201,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:15416.3-15449.6" - process $proc$libresoc.v:15416$320 + attribute \src "libresoc.v:15502.3-15535.6" + process $proc$libresoc.v:15502$320 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15417.5-15417.29" + attribute \src "libresoc.v:15503.5-15503.29" switch \initial - attribute \src "libresoc.v:15417.9-15417.17" + attribute \src "libresoc.v:15503.9-15503.17" case 1'1 case end @@ -22170,14 +22256,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:15450.3-15483.6" - process $proc$libresoc.v:15450$321 + attribute \src "libresoc.v:15536.3-15569.6" + process $proc$libresoc.v:15536$321 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15451.5-15451.29" + attribute \src "libresoc.v:15537.5-15537.29" switch \initial - attribute \src "libresoc.v:15451.9-15451.17" + attribute \src "libresoc.v:15537.9-15537.17" case 1'1 case end @@ -22225,14 +22311,14 @@ module \LOGICAL_dec31_dec_sub26 sync always update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:15484.3-15517.6" - process $proc$libresoc.v:15484$322 + attribute \src "libresoc.v:15570.3-15603.6" + process $proc$libresoc.v:15570$322 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15485.5-15485.29" + attribute \src "libresoc.v:15571.5-15571.29" switch \initial - attribute \src "libresoc.v:15485.9-15485.17" + attribute \src "libresoc.v:15571.9-15571.17" case 1'1 case end @@ -22282,68 +22368,68 @@ module \LOGICAL_dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:15523.1-16229.10" +attribute \src "libresoc.v:15609.1-16317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" attribute \generator "nMigen" module \LOGICAL_dec31_dec_sub28 - attribute \src "libresoc.v:16043.3-16079.6" + attribute \src "libresoc.v:16131.3-16167.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:16080.3-16116.6" + attribute \src "libresoc.v:16168.3-16204.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:16191.3-16227.6" + attribute \src "libresoc.v:16279.3-16315.6" wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:15821.3-15857.6" + attribute \src "libresoc.v:15909.3-15945.6" wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15710.3-15746.6" - wire width 13 $0\LOGICAL_dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:15969.3-16005.6" + attribute \src "libresoc.v:15798.3-15834.6" + wire width 14 $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:16057.3-16093.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:16006.3-16042.6" + attribute \src "libresoc.v:16094.3-16130.6" wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:15932.3-15968.6" + attribute \src "libresoc.v:16020.3-16056.6" wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15747.3-15783.6" + attribute \src "libresoc.v:15835.3-15871.6" wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15784.3-15820.6" + attribute \src "libresoc.v:15872.3-15908.6" wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15858.3-15894.6" + attribute \src "libresoc.v:15946.3-15982.6" wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:16117.3-16153.6" + attribute \src "libresoc.v:16205.3-16241.6" wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:16154.3-16190.6" + attribute \src "libresoc.v:16242.3-16278.6" wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:15895.3-15931.6" + attribute \src "libresoc.v:15983.3-16019.6" wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:15524.7-15524.20" + attribute \src "libresoc.v:15610.7-15610.20" wire $0\initial[0:0] - attribute \src "libresoc.v:16043.3-16079.6" + attribute \src "libresoc.v:16131.3-16167.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:16080.3-16116.6" + attribute \src "libresoc.v:16168.3-16204.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:16191.3-16227.6" + attribute \src "libresoc.v:16279.3-16315.6" wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:15821.3-15857.6" + attribute \src "libresoc.v:15909.3-15945.6" wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15710.3-15746.6" - wire width 13 $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:15969.3-16005.6" + attribute \src "libresoc.v:15798.3-15834.6" + wire width 14 $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:16057.3-16093.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:16006.3-16042.6" + attribute \src "libresoc.v:16094.3-16130.6" wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:15932.3-15968.6" + attribute \src "libresoc.v:16020.3-16056.6" wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15747.3-15783.6" + attribute \src "libresoc.v:15835.3-15871.6" wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15784.3-15820.6" + attribute \src "libresoc.v:15872.3-15908.6" wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15858.3-15894.6" + attribute \src "libresoc.v:15946.3-15982.6" wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:16117.3-16153.6" + attribute \src "libresoc.v:16205.3-16241.6" wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:16154.3-16190.6" + attribute \src "libresoc.v:16242.3-16278.6" wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:15895.3-15931.6" + attribute \src "libresoc.v:15983.3-16019.6" wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -22374,21 +22460,22 @@ module \LOGICAL_dec31_dec_sub28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 12 \LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -22488,6 +22575,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -22512,28 +22600,28 @@ module \LOGICAL_dec31_dec_sub28 wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 14 \LOGICAL_dec31_dec_sub28_sgn - attribute \src "libresoc.v:15524.7-15524.15" + attribute \src "libresoc.v:15610.7-15610.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:15524.7-15524.20" - process $proc$libresoc.v:15524$338 + attribute \src "libresoc.v:15610.7-15610.20" + process $proc$libresoc.v:15610$338 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:15710.3-15746.6" - process $proc$libresoc.v:15710$324 + attribute \src "libresoc.v:15798.3-15834.6" + process $proc$libresoc.v:15798$324 assign { } { } assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_function_unit[12:0] $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:15711.5-15711.29" + assign $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:15799.5-15799.29" switch \initial - attribute \src "libresoc.v:15711.9-15711.17" + attribute \src "libresoc.v:15799.9-15799.17" case 1'1 case end @@ -22542,57 +22630,57 @@ module \LOGICAL_dec31_dec_sub28 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 case - assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000000000 + assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000000000 end sync always - update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[12:0] + update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:15747.3-15783.6" - process $proc$libresoc.v:15747$325 + attribute \src "libresoc.v:15835.3-15871.6" + process $proc$libresoc.v:15835$325 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15748.5-15748.29" + attribute \src "libresoc.v:15836.5-15836.29" switch \initial - attribute \src "libresoc.v:15748.9-15748.17" + attribute \src "libresoc.v:15836.9-15836.17" case 1'1 case end @@ -22644,14 +22732,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:15784.3-15820.6" - process $proc$libresoc.v:15784$326 + attribute \src "libresoc.v:15872.3-15908.6" + process $proc$libresoc.v:15872$326 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15785.5-15785.29" + attribute \src "libresoc.v:15873.5-15873.29" switch \initial - attribute \src "libresoc.v:15785.9-15785.17" + attribute \src "libresoc.v:15873.9-15873.17" case 1'1 case end @@ -22703,14 +22791,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:15821.3-15857.6" - process $proc$libresoc.v:15821$327 + attribute \src "libresoc.v:15909.3-15945.6" + process $proc$libresoc.v:15909$327 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15822.5-15822.29" + attribute \src "libresoc.v:15910.5-15910.29" switch \initial - attribute \src "libresoc.v:15822.9-15822.17" + attribute \src "libresoc.v:15910.9-15910.17" case 1'1 case end @@ -22762,14 +22850,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:15858.3-15894.6" - process $proc$libresoc.v:15858$328 + attribute \src "libresoc.v:15946.3-15982.6" + process $proc$libresoc.v:15946$328 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:15859.5-15859.29" + attribute \src "libresoc.v:15947.5-15947.29" switch \initial - attribute \src "libresoc.v:15859.9-15859.17" + attribute \src "libresoc.v:15947.9-15947.17" case 1'1 case end @@ -22821,14 +22909,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:15895.3-15931.6" - process $proc$libresoc.v:15895$329 + attribute \src "libresoc.v:15983.3-16019.6" + process $proc$libresoc.v:15983$329 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:15896.5-15896.29" + attribute \src "libresoc.v:15984.5-15984.29" switch \initial - attribute \src "libresoc.v:15896.9-15896.17" + attribute \src "libresoc.v:15984.9-15984.17" case 1'1 case end @@ -22880,14 +22968,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:15932.3-15968.6" - process $proc$libresoc.v:15932$330 + attribute \src "libresoc.v:16020.3-16056.6" + process $proc$libresoc.v:16020$330 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15933.5-15933.29" + attribute \src "libresoc.v:16021.5-16021.29" switch \initial - attribute \src "libresoc.v:15933.9-15933.17" + attribute \src "libresoc.v:16021.9-16021.17" case 1'1 case end @@ -22939,14 +23027,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:15969.3-16005.6" - process $proc$libresoc.v:15969$331 + attribute \src "libresoc.v:16057.3-16093.6" + process $proc$libresoc.v:16057$331 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:15970.5-15970.29" + attribute \src "libresoc.v:16058.5-16058.29" switch \initial - attribute \src "libresoc.v:15970.9-15970.17" + attribute \src "libresoc.v:16058.9-16058.17" case 1'1 case end @@ -22998,14 +23086,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:16006.3-16042.6" - process $proc$libresoc.v:16006$332 + attribute \src "libresoc.v:16094.3-16130.6" + process $proc$libresoc.v:16094$332 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:16007.5-16007.29" + attribute \src "libresoc.v:16095.5-16095.29" switch \initial - attribute \src "libresoc.v:16007.9-16007.17" + attribute \src "libresoc.v:16095.9-16095.17" case 1'1 case end @@ -23057,14 +23145,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:16043.3-16079.6" - process $proc$libresoc.v:16043$333 + attribute \src "libresoc.v:16131.3-16167.6" + process $proc$libresoc.v:16131$333 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:16044.5-16044.29" + attribute \src "libresoc.v:16132.5-16132.29" switch \initial - attribute \src "libresoc.v:16044.9-16044.17" + attribute \src "libresoc.v:16132.9-16132.17" case 1'1 case end @@ -23116,14 +23204,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:16080.3-16116.6" - process $proc$libresoc.v:16080$334 + attribute \src "libresoc.v:16168.3-16204.6" + process $proc$libresoc.v:16168$334 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:16081.5-16081.29" + attribute \src "libresoc.v:16169.5-16169.29" switch \initial - attribute \src "libresoc.v:16081.9-16081.17" + attribute \src "libresoc.v:16169.9-16169.17" case 1'1 case end @@ -23175,14 +23263,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:16117.3-16153.6" - process $proc$libresoc.v:16117$335 + attribute \src "libresoc.v:16205.3-16241.6" + process $proc$libresoc.v:16205$335 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:16118.5-16118.29" + attribute \src "libresoc.v:16206.5-16206.29" switch \initial - attribute \src "libresoc.v:16118.9-16118.17" + attribute \src "libresoc.v:16206.9-16206.17" case 1'1 case end @@ -23234,14 +23322,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:16154.3-16190.6" - process $proc$libresoc.v:16154$336 + attribute \src "libresoc.v:16242.3-16278.6" + process $proc$libresoc.v:16242$336 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:16155.5-16155.29" + attribute \src "libresoc.v:16243.5-16243.29" switch \initial - attribute \src "libresoc.v:16155.9-16155.17" + attribute \src "libresoc.v:16243.9-16243.17" case 1'1 case end @@ -23293,14 +23381,14 @@ module \LOGICAL_dec31_dec_sub28 sync always update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:16191.3-16227.6" - process $proc$libresoc.v:16191$337 + attribute \src "libresoc.v:16279.3-16315.6" + process $proc$libresoc.v:16279$337 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:16192.5-16192.29" + attribute \src "libresoc.v:16280.5-16280.29" switch \initial - attribute \src "libresoc.v:16192.9-16192.17" + attribute \src "libresoc.v:16280.9-16280.17" case 1'1 case end @@ -23354,44 +23442,44 @@ module \LOGICAL_dec31_dec_sub28 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:16233.1-16800.10" +attribute \src "libresoc.v:16321.1-16894.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" attribute \generator "nMigen" module \MUL_dec31 - attribute \src "libresoc.v:16757.3-16769.6" + attribute \src "libresoc.v:16851.3-16863.6" wire width 3 $0\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16770.3-16782.6" + attribute \src "libresoc.v:16864.3-16876.6" wire width 3 $0\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16718.3-16730.6" - wire width 13 $0\MUL_dec31_function_unit[12:0] - attribute \src "libresoc.v:16744.3-16756.6" + attribute \src "libresoc.v:16812.3-16824.6" + wire width 14 $0\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16838.3-16850.6" wire width 4 $0\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16731.3-16743.6" + attribute \src "libresoc.v:16825.3-16837.6" wire width 7 $0\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16692.3-16704.6" + attribute \src "libresoc.v:16786.3-16798.6" wire $0\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16783.3-16795.6" + attribute \src "libresoc.v:16877.3-16889.6" wire width 2 $0\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16705.3-16717.6" + attribute \src "libresoc.v:16799.3-16811.6" wire $0\MUL_dec31_sgn[0:0] - attribute \src "libresoc.v:16234.7-16234.20" + attribute \src "libresoc.v:16322.7-16322.20" wire $0\initial[0:0] - attribute \src "libresoc.v:16757.3-16769.6" + attribute \src "libresoc.v:16851.3-16863.6" wire width 3 $1\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16770.3-16782.6" + attribute \src "libresoc.v:16864.3-16876.6" wire width 3 $1\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16718.3-16730.6" - wire width 13 $1\MUL_dec31_function_unit[12:0] - attribute \src "libresoc.v:16744.3-16756.6" + attribute \src "libresoc.v:16812.3-16824.6" + wire width 14 $1\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16838.3-16850.6" wire width 4 $1\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16731.3-16743.6" + attribute \src "libresoc.v:16825.3-16837.6" wire width 7 $1\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16692.3-16704.6" + attribute \src "libresoc.v:16786.3-16798.6" wire $1\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16783.3-16795.6" + attribute \src "libresoc.v:16877.3-16889.6" wire width 2 $1\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16705.3-16717.6" + attribute \src "libresoc.v:16799.3-16811.6" wire $1\MUL_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23434,21 +23522,22 @@ module \MUL_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23540,6 +23629,7 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -23575,21 +23665,22 @@ module \MUL_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23681,6 +23772,7 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -23696,21 +23788,22 @@ module \MUL_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \MUL_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \MUL_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23802,6 +23895,7 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \MUL_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -23814,7 +23908,7 @@ module \MUL_dec31 wire width 2 output 6 \MUL_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \MUL_dec31_sgn - attribute \src "libresoc.v:16234.7-16234.15" + attribute \src "libresoc.v:16322.7-16322.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -23823,7 +23917,7 @@ module \MUL_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:16670.23-16680.4" + attribute \src "libresoc.v:16764.23-16774.4" cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out @@ -23836,7 +23930,7 @@ module \MUL_dec31 connect \opcode_in \MUL_dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:16681.22-16691.4" + attribute \src "libresoc.v:16775.22-16785.4" cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out @@ -23848,22 +23942,22 @@ module \MUL_dec31 connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn connect \opcode_in \MUL_dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:16234.7-16234.20" - process $proc$libresoc.v:16234$347 + attribute \src "libresoc.v:16322.7-16322.20" + process $proc$libresoc.v:16322$347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:16692.3-16704.6" - process $proc$libresoc.v:16692$339 + attribute \src "libresoc.v:16786.3-16798.6" + process $proc$libresoc.v:16786$339 assign { } { } assign { } { } assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16693.5-16693.29" + attribute \src "libresoc.v:16787.5-16787.29" switch \initial - attribute \src "libresoc.v:16693.9-16693.17" + attribute \src "libresoc.v:16787.9-16787.17" case 1'1 case end @@ -23883,14 +23977,14 @@ module \MUL_dec31 sync always update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] end - attribute \src "libresoc.v:16705.3-16717.6" - process $proc$libresoc.v:16705$340 + attribute \src "libresoc.v:16799.3-16811.6" + process $proc$libresoc.v:16799$340 assign { } { } assign { } { } assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] - attribute \src "libresoc.v:16706.5-16706.29" + attribute \src "libresoc.v:16800.5-16800.29" switch \initial - attribute \src "libresoc.v:16706.9-16706.17" + attribute \src "libresoc.v:16800.9-16800.17" case 1'1 case end @@ -23910,14 +24004,14 @@ module \MUL_dec31 sync always update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] end - attribute \src "libresoc.v:16718.3-16730.6" - process $proc$libresoc.v:16718$341 + attribute \src "libresoc.v:16812.3-16824.6" + process $proc$libresoc.v:16812$341 assign { } { } assign { } { } - assign $0\MUL_dec31_function_unit[12:0] $1\MUL_dec31_function_unit[12:0] - attribute \src "libresoc.v:16719.5-16719.29" + assign $0\MUL_dec31_function_unit[13:0] $1\MUL_dec31_function_unit[13:0] + attribute \src "libresoc.v:16813.5-16813.29" switch \initial - attribute \src "libresoc.v:16719.9-16719.17" + attribute \src "libresoc.v:16813.9-16813.17" case 1'1 case end @@ -23926,25 +24020,25 @@ module \MUL_dec31 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\MUL_dec31_function_unit[12:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + assign $1\MUL_dec31_function_unit[13:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\MUL_dec31_function_unit[12:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + assign $1\MUL_dec31_function_unit[13:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit case - assign $1\MUL_dec31_function_unit[12:0] 13'0000000000000 + assign $1\MUL_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[12:0] + update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[13:0] end - attribute \src "libresoc.v:16731.3-16743.6" - process $proc$libresoc.v:16731$342 + attribute \src "libresoc.v:16825.3-16837.6" + process $proc$libresoc.v:16825$342 assign { } { } assign { } { } assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16732.5-16732.29" + attribute \src "libresoc.v:16826.5-16826.29" switch \initial - attribute \src "libresoc.v:16732.9-16732.17" + attribute \src "libresoc.v:16826.9-16826.17" case 1'1 case end @@ -23964,14 +24058,14 @@ module \MUL_dec31 sync always update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] end - attribute \src "libresoc.v:16744.3-16756.6" - process $proc$libresoc.v:16744$343 + attribute \src "libresoc.v:16838.3-16850.6" + process $proc$libresoc.v:16838$343 assign { } { } assign { } { } assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16745.5-16745.29" + attribute \src "libresoc.v:16839.5-16839.29" switch \initial - attribute \src "libresoc.v:16745.9-16745.17" + attribute \src "libresoc.v:16839.9-16839.17" case 1'1 case end @@ -23991,14 +24085,14 @@ module \MUL_dec31 sync always update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:16757.3-16769.6" - process $proc$libresoc.v:16757$344 + attribute \src "libresoc.v:16851.3-16863.6" + process $proc$libresoc.v:16851$344 assign { } { } assign { } { } assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16758.5-16758.29" + attribute \src "libresoc.v:16852.5-16852.29" switch \initial - attribute \src "libresoc.v:16758.9-16758.17" + attribute \src "libresoc.v:16852.9-16852.17" case 1'1 case end @@ -24018,14 +24112,14 @@ module \MUL_dec31 sync always update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] end - attribute \src "libresoc.v:16770.3-16782.6" - process $proc$libresoc.v:16770$345 + attribute \src "libresoc.v:16864.3-16876.6" + process $proc$libresoc.v:16864$345 assign { } { } assign { } { } assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16771.5-16771.29" + attribute \src "libresoc.v:16865.5-16865.29" switch \initial - attribute \src "libresoc.v:16771.9-16771.17" + attribute \src "libresoc.v:16865.9-16865.17" case 1'1 case end @@ -24045,14 +24139,14 @@ module \MUL_dec31 sync always update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] end - attribute \src "libresoc.v:16783.3-16795.6" - process $proc$libresoc.v:16783$346 + attribute \src "libresoc.v:16877.3-16889.6" + process $proc$libresoc.v:16877$346 assign { } { } assign { } { } assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16784.5-16784.29" + attribute \src "libresoc.v:16878.5-16878.29" switch \initial - attribute \src "libresoc.v:16784.9-16784.17" + attribute \src "libresoc.v:16878.9-16878.17" case 1'1 case end @@ -24077,44 +24171,44 @@ module \MUL_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:16804.1-17158.10" +attribute \src "libresoc.v:16898.1-17254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" attribute \generator "nMigen" module \MUL_dec31_dec_sub11 - attribute \src "libresoc.v:17032.3-17056.6" + attribute \src "libresoc.v:17128.3-17152.6" wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:17057.3-17081.6" + attribute \src "libresoc.v:17153.3-17177.6" wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:16957.3-16981.6" - wire width 13 $0\MUL_dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:17007.3-17031.6" + attribute \src "libresoc.v:17053.3-17077.6" + wire width 14 $0\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17103.3-17127.6" wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:16982.3-17006.6" + attribute \src "libresoc.v:17078.3-17102.6" wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:17107.3-17131.6" + attribute \src "libresoc.v:17203.3-17227.6" wire $0\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:17082.3-17106.6" + attribute \src "libresoc.v:17178.3-17202.6" wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:17132.3-17156.6" + attribute \src "libresoc.v:17228.3-17252.6" wire $0\MUL_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:16805.7-16805.20" + attribute \src "libresoc.v:16899.7-16899.20" wire $0\initial[0:0] - attribute \src "libresoc.v:17032.3-17056.6" + attribute \src "libresoc.v:17128.3-17152.6" wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:17057.3-17081.6" + attribute \src "libresoc.v:17153.3-17177.6" wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:16957.3-16981.6" - wire width 13 $1\MUL_dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:17007.3-17031.6" + attribute \src "libresoc.v:17053.3-17077.6" + wire width 14 $1\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17103.3-17127.6" wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:16982.3-17006.6" + attribute \src "libresoc.v:17078.3-17102.6" wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:17107.3-17131.6" + attribute \src "libresoc.v:17203.3-17227.6" wire $1\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:17082.3-17106.6" + attribute \src "libresoc.v:17178.3-17202.6" wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:17132.3-17156.6" + attribute \src "libresoc.v:17228.3-17252.6" wire $1\MUL_dec31_dec_sub11_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -24137,21 +24231,22 @@ module \MUL_dec31_dec_sub11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \MUL_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -24243,6 +24338,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -24255,28 +24351,28 @@ module \MUL_dec31_dec_sub11 wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \MUL_dec31_dec_sub11_sgn - attribute \src "libresoc.v:16805.7-16805.15" + attribute \src "libresoc.v:16899.7-16899.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 9 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:16805.7-16805.20" - process $proc$libresoc.v:16805$356 + attribute \src "libresoc.v:16899.7-16899.20" + process $proc$libresoc.v:16899$356 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:16957.3-16981.6" - process $proc$libresoc.v:16957$348 + attribute \src "libresoc.v:17053.3-17077.6" + process $proc$libresoc.v:17053$348 assign { } { } assign { } { } - assign $0\MUL_dec31_dec_sub11_function_unit[12:0] $1\MUL_dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:16958.5-16958.29" + assign $0\MUL_dec31_dec_sub11_function_unit[13:0] $1\MUL_dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:17054.5-17054.29" switch \initial - attribute \src "libresoc.v:16958.9-16958.17" + attribute \src "libresoc.v:17054.9-17054.17" case 1'1 case end @@ -24285,41 +24381,41 @@ module \MUL_dec31_dec_sub11 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 case - assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000000000000 + assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always - update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[12:0] + update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:16982.3-17006.6" - process $proc$libresoc.v:16982$349 + attribute \src "libresoc.v:17078.3-17102.6" + process $proc$libresoc.v:17078$349 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:16983.5-16983.29" + attribute \src "libresoc.v:17079.5-17079.29" switch \initial - attribute \src "libresoc.v:16983.9-16983.17" + attribute \src "libresoc.v:17079.9-17079.17" case 1'1 case end @@ -24355,14 +24451,14 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:17007.3-17031.6" - process $proc$libresoc.v:17007$350 + attribute \src "libresoc.v:17103.3-17127.6" + process $proc$libresoc.v:17103$350 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:17008.5-17008.29" + attribute \src "libresoc.v:17104.5-17104.29" switch \initial - attribute \src "libresoc.v:17008.9-17008.17" + attribute \src "libresoc.v:17104.9-17104.17" case 1'1 case end @@ -24398,14 +24494,14 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:17032.3-17056.6" - process $proc$libresoc.v:17032$351 + attribute \src "libresoc.v:17128.3-17152.6" + process $proc$libresoc.v:17128$351 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:17033.5-17033.29" + attribute \src "libresoc.v:17129.5-17129.29" switch \initial - attribute \src "libresoc.v:17033.9-17033.17" + attribute \src "libresoc.v:17129.9-17129.17" case 1'1 case end @@ -24441,14 +24537,14 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:17057.3-17081.6" - process $proc$libresoc.v:17057$352 + attribute \src "libresoc.v:17153.3-17177.6" + process $proc$libresoc.v:17153$352 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:17058.5-17058.29" + attribute \src "libresoc.v:17154.5-17154.29" switch \initial - attribute \src "libresoc.v:17058.9-17058.17" + attribute \src "libresoc.v:17154.9-17154.17" case 1'1 case end @@ -24484,14 +24580,14 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:17082.3-17106.6" - process $proc$libresoc.v:17082$353 + attribute \src "libresoc.v:17178.3-17202.6" + process $proc$libresoc.v:17178$353 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:17083.5-17083.29" + attribute \src "libresoc.v:17179.5-17179.29" switch \initial - attribute \src "libresoc.v:17083.9-17083.17" + attribute \src "libresoc.v:17179.9-17179.17" case 1'1 case end @@ -24527,14 +24623,14 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:17107.3-17131.6" - process $proc$libresoc.v:17107$354 + attribute \src "libresoc.v:17203.3-17227.6" + process $proc$libresoc.v:17203$354 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:17108.5-17108.29" + attribute \src "libresoc.v:17204.5-17204.29" switch \initial - attribute \src "libresoc.v:17108.9-17108.17" + attribute \src "libresoc.v:17204.9-17204.17" case 1'1 case end @@ -24570,14 +24666,14 @@ module \MUL_dec31_dec_sub11 sync always update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:17132.3-17156.6" - process $proc$libresoc.v:17132$355 + attribute \src "libresoc.v:17228.3-17252.6" + process $proc$libresoc.v:17228$355 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:17133.5-17133.29" + attribute \src "libresoc.v:17229.5-17229.29" switch \initial - attribute \src "libresoc.v:17133.9-17133.17" + attribute \src "libresoc.v:17229.9-17229.17" case 1'1 case end @@ -24615,44 +24711,44 @@ module \MUL_dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:17162.1-17516.10" +attribute \src "libresoc.v:17258.1-17614.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" attribute \generator "nMigen" module \MUL_dec31_dec_sub9 - attribute \src "libresoc.v:17390.3-17414.6" + attribute \src "libresoc.v:17488.3-17512.6" wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17415.3-17439.6" + attribute \src "libresoc.v:17513.3-17537.6" wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17315.3-17339.6" - wire width 13 $0\MUL_dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:17365.3-17389.6" + attribute \src "libresoc.v:17413.3-17437.6" + wire width 14 $0\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17463.3-17487.6" wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17340.3-17364.6" + attribute \src "libresoc.v:17438.3-17462.6" wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17465.3-17489.6" + attribute \src "libresoc.v:17563.3-17587.6" wire $0\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17440.3-17464.6" + attribute \src "libresoc.v:17538.3-17562.6" wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17490.3-17514.6" + attribute \src "libresoc.v:17588.3-17612.6" wire $0\MUL_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:17163.7-17163.20" + attribute \src "libresoc.v:17259.7-17259.20" wire $0\initial[0:0] - attribute \src "libresoc.v:17390.3-17414.6" + attribute \src "libresoc.v:17488.3-17512.6" wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17415.3-17439.6" + attribute \src "libresoc.v:17513.3-17537.6" wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17315.3-17339.6" - wire width 13 $1\MUL_dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:17365.3-17389.6" + attribute \src "libresoc.v:17413.3-17437.6" + wire width 14 $1\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17463.3-17487.6" wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17340.3-17364.6" + attribute \src "libresoc.v:17438.3-17462.6" wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17465.3-17489.6" + attribute \src "libresoc.v:17563.3-17587.6" wire $1\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17440.3-17464.6" + attribute \src "libresoc.v:17538.3-17562.6" wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17490.3-17514.6" + attribute \src "libresoc.v:17588.3-17612.6" wire $1\MUL_dec31_dec_sub9_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -24675,21 +24771,22 @@ module \MUL_dec31_dec_sub9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \MUL_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -24781,6 +24878,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -24793,28 +24891,28 @@ module \MUL_dec31_dec_sub9 wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 8 \MUL_dec31_dec_sub9_sgn - attribute \src "libresoc.v:17163.7-17163.15" + attribute \src "libresoc.v:17259.7-17259.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 9 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:17163.7-17163.20" - process $proc$libresoc.v:17163$365 + attribute \src "libresoc.v:17259.7-17259.20" + process $proc$libresoc.v:17259$365 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:17315.3-17339.6" - process $proc$libresoc.v:17315$357 + attribute \src "libresoc.v:17413.3-17437.6" + process $proc$libresoc.v:17413$357 assign { } { } assign { } { } - assign $0\MUL_dec31_dec_sub9_function_unit[12:0] $1\MUL_dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:17316.5-17316.29" + assign $0\MUL_dec31_dec_sub9_function_unit[13:0] $1\MUL_dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:17414.5-17414.29" switch \initial - attribute \src "libresoc.v:17316.9-17316.17" + attribute \src "libresoc.v:17414.9-17414.17" case 1'1 case end @@ -24823,41 +24921,41 @@ module \MUL_dec31_dec_sub9 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 case - assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000000000000 + assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always - update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[12:0] + update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:17340.3-17364.6" - process $proc$libresoc.v:17340$358 + attribute \src "libresoc.v:17438.3-17462.6" + process $proc$libresoc.v:17438$358 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17341.5-17341.29" + attribute \src "libresoc.v:17439.5-17439.29" switch \initial - attribute \src "libresoc.v:17341.9-17341.17" + attribute \src "libresoc.v:17439.9-17439.17" case 1'1 case end @@ -24893,14 +24991,14 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:17365.3-17389.6" - process $proc$libresoc.v:17365$359 + attribute \src "libresoc.v:17463.3-17487.6" + process $proc$libresoc.v:17463$359 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17366.5-17366.29" + attribute \src "libresoc.v:17464.5-17464.29" switch \initial - attribute \src "libresoc.v:17366.9-17366.17" + attribute \src "libresoc.v:17464.9-17464.17" case 1'1 case end @@ -24936,14 +25034,14 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:17390.3-17414.6" - process $proc$libresoc.v:17390$360 + attribute \src "libresoc.v:17488.3-17512.6" + process $proc$libresoc.v:17488$360 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17391.5-17391.29" + attribute \src "libresoc.v:17489.5-17489.29" switch \initial - attribute \src "libresoc.v:17391.9-17391.17" + attribute \src "libresoc.v:17489.9-17489.17" case 1'1 case end @@ -24979,14 +25077,14 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:17415.3-17439.6" - process $proc$libresoc.v:17415$361 + attribute \src "libresoc.v:17513.3-17537.6" + process $proc$libresoc.v:17513$361 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17416.5-17416.29" + attribute \src "libresoc.v:17514.5-17514.29" switch \initial - attribute \src "libresoc.v:17416.9-17416.17" + attribute \src "libresoc.v:17514.9-17514.17" case 1'1 case end @@ -25022,14 +25120,14 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:17440.3-17464.6" - process $proc$libresoc.v:17440$362 + attribute \src "libresoc.v:17538.3-17562.6" + process $proc$libresoc.v:17538$362 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17441.5-17441.29" + attribute \src "libresoc.v:17539.5-17539.29" switch \initial - attribute \src "libresoc.v:17441.9-17441.17" + attribute \src "libresoc.v:17539.9-17539.17" case 1'1 case end @@ -25065,14 +25163,14 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:17465.3-17489.6" - process $proc$libresoc.v:17465$363 + attribute \src "libresoc.v:17563.3-17587.6" + process $proc$libresoc.v:17563$363 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17466.5-17466.29" + attribute \src "libresoc.v:17564.5-17564.29" switch \initial - attribute \src "libresoc.v:17466.9-17466.17" + attribute \src "libresoc.v:17564.9-17564.17" case 1'1 case end @@ -25108,14 +25206,14 @@ module \MUL_dec31_dec_sub9 sync always update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:17490.3-17514.6" - process $proc$libresoc.v:17490$364 + attribute \src "libresoc.v:17588.3-17612.6" + process $proc$libresoc.v:17588$364 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:17491.5-17491.29" + attribute \src "libresoc.v:17589.5-17589.29" switch \initial - attribute \src "libresoc.v:17491.9-17491.17" + attribute \src "libresoc.v:17589.9-17589.17" case 1'1 case end @@ -25153,56 +25251,56 @@ module \MUL_dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:17520.1-18094.10" +attribute \src "libresoc.v:17618.1-18194.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" attribute \generator "nMigen" module \SHIFT_ROT_dec30 - attribute \src "libresoc.v:17871.3-17907.6" + attribute \src "libresoc.v:17971.3-18007.6" wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17908.3-17944.6" + attribute \src "libresoc.v:18008.3-18044.6" wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17982.3-18018.6" + attribute \src "libresoc.v:18082.3-18118.6" wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:18056.3-18092.6" + attribute \src "libresoc.v:18156.3-18192.6" wire $0\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17686.3-17722.6" - wire width 13 $0\SHIFT_ROT_dec30_function_unit[12:0] - attribute \src "libresoc.v:17834.3-17870.6" + attribute \src "libresoc.v:17786.3-17822.6" + wire width 14 $0\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17934.3-17970.6" wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17797.3-17833.6" + attribute \src "libresoc.v:17897.3-17933.6" wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:18019.3-18055.6" + attribute \src "libresoc.v:18119.3-18155.6" wire $0\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:17723.3-17759.6" + attribute \src "libresoc.v:17823.3-17859.6" wire $0\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17945.3-17981.6" + attribute \src "libresoc.v:18045.3-18081.6" wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17760.3-17796.6" + attribute \src "libresoc.v:17860.3-17896.6" wire $0\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "libresoc.v:17521.7-17521.20" + attribute \src "libresoc.v:17619.7-17619.20" wire $0\initial[0:0] - attribute \src "libresoc.v:17871.3-17907.6" + attribute \src "libresoc.v:17971.3-18007.6" wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17908.3-17944.6" + attribute \src "libresoc.v:18008.3-18044.6" wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17982.3-18018.6" + attribute \src "libresoc.v:18082.3-18118.6" wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:18056.3-18092.6" + attribute \src "libresoc.v:18156.3-18192.6" wire $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17686.3-17722.6" - wire width 13 $1\SHIFT_ROT_dec30_function_unit[12:0] - attribute \src "libresoc.v:17834.3-17870.6" + attribute \src "libresoc.v:17786.3-17822.6" + wire width 14 $1\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17934.3-17970.6" wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17797.3-17833.6" + attribute \src "libresoc.v:17897.3-17933.6" wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:18019.3-18055.6" + attribute \src "libresoc.v:18119.3-18155.6" wire $1\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:17723.3-17759.6" + attribute \src "libresoc.v:17823.3-17859.6" wire $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17945.3-17981.6" + attribute \src "libresoc.v:18045.3-18081.6" wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17760.3-17796.6" + attribute \src "libresoc.v:17860.3-17896.6" wire $1\SHIFT_ROT_dec30_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -25233,21 +25331,22 @@ module \SHIFT_ROT_dec30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \SHIFT_ROT_dec30_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -25339,6 +25438,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec30_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -25353,28 +25453,28 @@ module \SHIFT_ROT_dec30 wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec30_sgn - attribute \src "libresoc.v:17521.7-17521.15" + attribute \src "libresoc.v:17619.7-17619.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 4 \opcode_switch - attribute \src "libresoc.v:17521.7-17521.20" - process $proc$libresoc.v:17521$377 + attribute \src "libresoc.v:17619.7-17619.20" + process $proc$libresoc.v:17619$377 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:17686.3-17722.6" - process $proc$libresoc.v:17686$366 + attribute \src "libresoc.v:17786.3-17822.6" + process $proc$libresoc.v:17786$366 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec30_function_unit[12:0] $1\SHIFT_ROT_dec30_function_unit[12:0] - attribute \src "libresoc.v:17687.5-17687.29" + assign $0\SHIFT_ROT_dec30_function_unit[13:0] $1\SHIFT_ROT_dec30_function_unit[13:0] + attribute \src "libresoc.v:17787.5-17787.29" switch \initial - attribute \src "libresoc.v:17687.9-17687.17" + attribute \src "libresoc.v:17787.9-17787.17" case 1'1 case end @@ -25383,57 +25483,57 @@ module \SHIFT_ROT_dec30 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000000000 + assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[12:0] + update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[13:0] end - attribute \src "libresoc.v:17723.3-17759.6" - process $proc$libresoc.v:17723$367 + attribute \src "libresoc.v:17823.3-17859.6" + process $proc$libresoc.v:17823$367 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17724.5-17724.29" + attribute \src "libresoc.v:17824.5-17824.29" switch \initial - attribute \src "libresoc.v:17724.9-17724.17" + attribute \src "libresoc.v:17824.9-17824.17" case 1'1 case end @@ -25485,14 +25585,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] end - attribute \src "libresoc.v:17760.3-17796.6" - process $proc$libresoc.v:17760$368 + attribute \src "libresoc.v:17860.3-17896.6" + process $proc$libresoc.v:17860$368 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "libresoc.v:17761.5-17761.29" + attribute \src "libresoc.v:17861.5-17861.29" switch \initial - attribute \src "libresoc.v:17761.9-17761.17" + attribute \src "libresoc.v:17861.9-17861.17" case 1'1 case end @@ -25544,14 +25644,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] end - attribute \src "libresoc.v:17797.3-17833.6" - process $proc$libresoc.v:17797$369 + attribute \src "libresoc.v:17897.3-17933.6" + process $proc$libresoc.v:17897$369 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17798.5-17798.29" + attribute \src "libresoc.v:17898.5-17898.29" switch \initial - attribute \src "libresoc.v:17798.9-17798.17" + attribute \src "libresoc.v:17898.9-17898.17" case 1'1 case end @@ -25603,14 +25703,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] end - attribute \src "libresoc.v:17834.3-17870.6" - process $proc$libresoc.v:17834$370 + attribute \src "libresoc.v:17934.3-17970.6" + process $proc$libresoc.v:17934$370 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17835.5-17835.29" + attribute \src "libresoc.v:17935.5-17935.29" switch \initial - attribute \src "libresoc.v:17835.9-17835.17" + attribute \src "libresoc.v:17935.9-17935.17" case 1'1 case end @@ -25662,14 +25762,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] end - attribute \src "libresoc.v:17871.3-17907.6" - process $proc$libresoc.v:17871$371 + attribute \src "libresoc.v:17971.3-18007.6" + process $proc$libresoc.v:17971$371 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17872.5-17872.29" + attribute \src "libresoc.v:17972.5-17972.29" switch \initial - attribute \src "libresoc.v:17872.9-17872.17" + attribute \src "libresoc.v:17972.9-17972.17" case 1'1 case end @@ -25721,14 +25821,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] end - attribute \src "libresoc.v:17908.3-17944.6" - process $proc$libresoc.v:17908$372 + attribute \src "libresoc.v:18008.3-18044.6" + process $proc$libresoc.v:18008$372 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17909.5-17909.29" + attribute \src "libresoc.v:18009.5-18009.29" switch \initial - attribute \src "libresoc.v:17909.9-17909.17" + attribute \src "libresoc.v:18009.9-18009.17" case 1'1 case end @@ -25780,14 +25880,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] end - attribute \src "libresoc.v:17945.3-17981.6" - process $proc$libresoc.v:17945$373 + attribute \src "libresoc.v:18045.3-18081.6" + process $proc$libresoc.v:18045$373 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17946.5-17946.29" + attribute \src "libresoc.v:18046.5-18046.29" switch \initial - attribute \src "libresoc.v:17946.9-17946.17" + attribute \src "libresoc.v:18046.9-18046.17" case 1'1 case end @@ -25839,14 +25939,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] end - attribute \src "libresoc.v:17982.3-18018.6" - process $proc$libresoc.v:17982$374 + attribute \src "libresoc.v:18082.3-18118.6" + process $proc$libresoc.v:18082$374 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17983.5-17983.29" + attribute \src "libresoc.v:18083.5-18083.29" switch \initial - attribute \src "libresoc.v:17983.9-17983.17" + attribute \src "libresoc.v:18083.9-18083.17" case 1'1 case end @@ -25898,14 +25998,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] end - attribute \src "libresoc.v:18019.3-18055.6" - process $proc$libresoc.v:18019$375 + attribute \src "libresoc.v:18119.3-18155.6" + process $proc$libresoc.v:18119$375 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_inv_a[0:0] $1\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:18020.5-18020.29" + attribute \src "libresoc.v:18120.5-18120.29" switch \initial - attribute \src "libresoc.v:18020.9-18020.17" + attribute \src "libresoc.v:18120.9-18120.17" case 1'1 case end @@ -25957,14 +26057,14 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_inv_a $0\SHIFT_ROT_dec30_inv_a[0:0] end - attribute \src "libresoc.v:18056.3-18092.6" - process $proc$libresoc.v:18056$376 + attribute \src "libresoc.v:18156.3-18192.6" + process $proc$libresoc.v:18156$376 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:18057.5-18057.29" + attribute \src "libresoc.v:18157.5-18157.29" switch \initial - attribute \src "libresoc.v:18057.9-18057.17" + attribute \src "libresoc.v:18157.9-18157.17" case 1'1 case end @@ -26018,56 +26118,56 @@ module \SHIFT_ROT_dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:18098.1-18942.10" +attribute \src "libresoc.v:18198.1-19050.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" attribute \generator "nMigen" module \SHIFT_ROT_dec31 - attribute \src "libresoc.v:18905.3-18920.6" + attribute \src "libresoc.v:19013.3-19028.6" wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18921.3-18936.6" + attribute \src "libresoc.v:19029.3-19044.6" wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18777.3-18792.6" + attribute \src "libresoc.v:18885.3-18900.6" wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18809.3-18824.6" + attribute \src "libresoc.v:18917.3-18932.6" wire $0\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18857.3-18872.6" - wire width 13 $0\SHIFT_ROT_dec31_function_unit[12:0] - attribute \src "libresoc.v:18889.3-18904.6" + attribute \src "libresoc.v:18965.3-18980.6" + wire width 14 $0\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18997.3-19012.6" wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18873.3-18888.6" + attribute \src "libresoc.v:18981.3-18996.6" wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18793.3-18808.6" + attribute \src "libresoc.v:18901.3-18916.6" wire $0\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18825.3-18840.6" + attribute \src "libresoc.v:18933.3-18948.6" wire $0\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18761.3-18776.6" + attribute \src "libresoc.v:18869.3-18884.6" wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18841.3-18856.6" + attribute \src "libresoc.v:18949.3-18964.6" wire $0\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "libresoc.v:18099.7-18099.20" + attribute \src "libresoc.v:18199.7-18199.20" wire $0\initial[0:0] - attribute \src "libresoc.v:18905.3-18920.6" + attribute \src "libresoc.v:19013.3-19028.6" wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18921.3-18936.6" + attribute \src "libresoc.v:19029.3-19044.6" wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18777.3-18792.6" + attribute \src "libresoc.v:18885.3-18900.6" wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18809.3-18824.6" + attribute \src "libresoc.v:18917.3-18932.6" wire $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18857.3-18872.6" - wire width 13 $1\SHIFT_ROT_dec31_function_unit[12:0] - attribute \src "libresoc.v:18889.3-18904.6" + attribute \src "libresoc.v:18965.3-18980.6" + wire width 14 $1\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18997.3-19012.6" wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18873.3-18888.6" + attribute \src "libresoc.v:18981.3-18996.6" wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18793.3-18808.6" + attribute \src "libresoc.v:18901.3-18916.6" wire $1\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18825.3-18840.6" + attribute \src "libresoc.v:18933.3-18948.6" wire $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18761.3-18776.6" + attribute \src "libresoc.v:18869.3-18884.6" wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18841.3-18856.6" + attribute \src "libresoc.v:18949.3-18964.6" wire $1\SHIFT_ROT_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26126,21 +26226,22 @@ module \SHIFT_ROT_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26232,6 +26333,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -26277,21 +26379,22 @@ module \SHIFT_ROT_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26383,6 +26486,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -26428,21 +26532,22 @@ module \SHIFT_ROT_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26534,6 +26639,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -26551,21 +26657,22 @@ module \SHIFT_ROT_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \SHIFT_ROT_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26657,6 +26764,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -26671,7 +26779,7 @@ module \SHIFT_ROT_dec31 wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec31_sgn - attribute \src "libresoc.v:18099.7-18099.15" + attribute \src "libresoc.v:18199.7-18199.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -26680,7 +26788,7 @@ module \SHIFT_ROT_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:18719.29-18732.4" + attribute \src "libresoc.v:18827.29-18840.4" cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out @@ -26696,7 +26804,7 @@ module \SHIFT_ROT_dec31 connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:18733.29-18746.4" + attribute \src "libresoc.v:18841.29-18854.4" cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out @@ -26712,7 +26820,7 @@ module \SHIFT_ROT_dec31 connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:18747.29-18760.4" + attribute \src "libresoc.v:18855.29-18868.4" cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out @@ -26727,22 +26835,22 @@ module \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in end - attribute \src "libresoc.v:18099.7-18099.20" - process $proc$libresoc.v:18099$389 + attribute \src "libresoc.v:18199.7-18199.20" + process $proc$libresoc.v:18199$389 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:18761.3-18776.6" - process $proc$libresoc.v:18761$378 + attribute \src "libresoc.v:18869.3-18884.6" + process $proc$libresoc.v:18869$378 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18762.5-18762.29" + attribute \src "libresoc.v:18870.5-18870.29" switch \initial - attribute \src "libresoc.v:18762.9-18762.17" + attribute \src "libresoc.v:18870.9-18870.17" case 1'1 case end @@ -26766,14 +26874,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:18777.3-18792.6" - process $proc$libresoc.v:18777$379 + attribute \src "libresoc.v:18885.3-18900.6" + process $proc$libresoc.v:18885$379 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18778.5-18778.29" + attribute \src "libresoc.v:18886.5-18886.29" switch \initial - attribute \src "libresoc.v:18778.9-18778.17" + attribute \src "libresoc.v:18886.9-18886.17" case 1'1 case end @@ -26797,14 +26905,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] end - attribute \src "libresoc.v:18793.3-18808.6" - process $proc$libresoc.v:18793$380 + attribute \src "libresoc.v:18901.3-18916.6" + process $proc$libresoc.v:18901$380 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_inv_a[0:0] $1\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18794.5-18794.29" + attribute \src "libresoc.v:18902.5-18902.29" switch \initial - attribute \src "libresoc.v:18794.9-18794.17" + attribute \src "libresoc.v:18902.9-18902.17" case 1'1 case end @@ -26828,14 +26936,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_inv_a $0\SHIFT_ROT_dec31_inv_a[0:0] end - attribute \src "libresoc.v:18809.3-18824.6" - process $proc$libresoc.v:18809$381 + attribute \src "libresoc.v:18917.3-18932.6" + process $proc$libresoc.v:18917$381 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18810.5-18810.29" + attribute \src "libresoc.v:18918.5-18918.29" switch \initial - attribute \src "libresoc.v:18810.9-18810.17" + attribute \src "libresoc.v:18918.9-18918.17" case 1'1 case end @@ -26859,14 +26967,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] end - attribute \src "libresoc.v:18825.3-18840.6" - process $proc$libresoc.v:18825$382 + attribute \src "libresoc.v:18933.3-18948.6" + process $proc$libresoc.v:18933$382 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18826.5-18826.29" + attribute \src "libresoc.v:18934.5-18934.29" switch \initial - attribute \src "libresoc.v:18826.9-18826.17" + attribute \src "libresoc.v:18934.9-18934.17" case 1'1 case end @@ -26890,14 +26998,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] end - attribute \src "libresoc.v:18841.3-18856.6" - process $proc$libresoc.v:18841$383 + attribute \src "libresoc.v:18949.3-18964.6" + process $proc$libresoc.v:18949$383 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "libresoc.v:18842.5-18842.29" + attribute \src "libresoc.v:18950.5-18950.29" switch \initial - attribute \src "libresoc.v:18842.9-18842.17" + attribute \src "libresoc.v:18950.9-18950.17" case 1'1 case end @@ -26921,14 +27029,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] end - attribute \src "libresoc.v:18857.3-18872.6" - process $proc$libresoc.v:18857$384 + attribute \src "libresoc.v:18965.3-18980.6" + process $proc$libresoc.v:18965$384 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_function_unit[12:0] $1\SHIFT_ROT_dec31_function_unit[12:0] - attribute \src "libresoc.v:18858.5-18858.29" + assign $0\SHIFT_ROT_dec31_function_unit[13:0] $1\SHIFT_ROT_dec31_function_unit[13:0] + attribute \src "libresoc.v:18966.5-18966.29" switch \initial - attribute \src "libresoc.v:18858.9-18858.17" + attribute \src "libresoc.v:18966.9-18966.17" case 1'1 case end @@ -26937,29 +27045,29 @@ module \SHIFT_ROT_dec31 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[12:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[12:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[12:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit case - assign $1\SHIFT_ROT_dec31_function_unit[12:0] 13'0000000000000 + assign $1\SHIFT_ROT_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[12:0] + update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[13:0] end - attribute \src "libresoc.v:18873.3-18888.6" - process $proc$libresoc.v:18873$385 + attribute \src "libresoc.v:18981.3-18996.6" + process $proc$libresoc.v:18981$385 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18874.5-18874.29" + attribute \src "libresoc.v:18982.5-18982.29" switch \initial - attribute \src "libresoc.v:18874.9-18874.17" + attribute \src "libresoc.v:18982.9-18982.17" case 1'1 case end @@ -26983,14 +27091,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] end - attribute \src "libresoc.v:18889.3-18904.6" - process $proc$libresoc.v:18889$386 + attribute \src "libresoc.v:18997.3-19012.6" + process $proc$libresoc.v:18997$386 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18890.5-18890.29" + attribute \src "libresoc.v:18998.5-18998.29" switch \initial - attribute \src "libresoc.v:18890.9-18890.17" + attribute \src "libresoc.v:18998.9-18998.17" case 1'1 case end @@ -27014,14 +27122,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:18905.3-18920.6" - process $proc$libresoc.v:18905$387 + attribute \src "libresoc.v:19013.3-19028.6" + process $proc$libresoc.v:19013$387 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18906.5-18906.29" + attribute \src "libresoc.v:19014.5-19014.29" switch \initial - attribute \src "libresoc.v:18906.9-18906.17" + attribute \src "libresoc.v:19014.9-19014.17" case 1'1 case end @@ -27045,14 +27153,14 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] end - attribute \src "libresoc.v:18921.3-18936.6" - process $proc$libresoc.v:18921$388 + attribute \src "libresoc.v:19029.3-19044.6" + process $proc$libresoc.v:19029$388 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18922.5-18922.29" + attribute \src "libresoc.v:19030.5-19030.29" switch \initial - attribute \src "libresoc.v:18922.9-18922.17" + attribute \src "libresoc.v:19030.9-19030.17" case 1'1 case end @@ -27082,56 +27190,56 @@ module \SHIFT_ROT_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:18946.1-19322.10" +attribute \src "libresoc.v:19054.1-19432.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub24 - attribute \src "libresoc.v:19207.3-19225.6" + attribute \src "libresoc.v:19317.3-19335.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19226.3-19244.6" + attribute \src "libresoc.v:19336.3-19354.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19264.3-19282.6" + attribute \src "libresoc.v:19374.3-19392.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19302.3-19320.6" + attribute \src "libresoc.v:19412.3-19430.6" wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:19112.3-19130.6" - wire width 13 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:19188.3-19206.6" + attribute \src "libresoc.v:19222.3-19240.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19298.3-19316.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19169.3-19187.6" + attribute \src "libresoc.v:19279.3-19297.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19283.3-19301.6" + attribute \src "libresoc.v:19393.3-19411.6" wire $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:19131.3-19149.6" + attribute \src "libresoc.v:19241.3-19259.6" wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:19245.3-19263.6" + attribute \src "libresoc.v:19355.3-19373.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:19150.3-19168.6" + attribute \src "libresoc.v:19260.3-19278.6" wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:18947.7-18947.20" + attribute \src "libresoc.v:19055.7-19055.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19207.3-19225.6" + attribute \src "libresoc.v:19317.3-19335.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19226.3-19244.6" + attribute \src "libresoc.v:19336.3-19354.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19264.3-19282.6" + attribute \src "libresoc.v:19374.3-19392.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19302.3-19320.6" + attribute \src "libresoc.v:19412.3-19430.6" wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:19112.3-19130.6" - wire width 13 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:19188.3-19206.6" + attribute \src "libresoc.v:19222.3-19240.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19298.3-19316.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19169.3-19187.6" + attribute \src "libresoc.v:19279.3-19297.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19283.3-19301.6" + attribute \src "libresoc.v:19393.3-19411.6" wire $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:19131.3-19149.6" + attribute \src "libresoc.v:19241.3-19259.6" wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:19245.3-19263.6" + attribute \src "libresoc.v:19355.3-19373.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:19150.3-19168.6" + attribute \src "libresoc.v:19260.3-19278.6" wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -27162,21 +27270,22 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -27268,6 +27377,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -27282,28 +27392,28 @@ module \SHIFT_ROT_dec31_dec_sub24 wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "libresoc.v:18947.7-18947.15" + attribute \src "libresoc.v:19055.7-19055.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:18947.7-18947.20" - process $proc$libresoc.v:18947$401 + attribute \src "libresoc.v:19055.7-19055.20" + process $proc$libresoc.v:19055$401 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:19112.3-19130.6" - process $proc$libresoc.v:19112$390 + attribute \src "libresoc.v:19222.3-19240.6" + process $proc$libresoc.v:19222$390 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:19113.5-19113.29" + assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:19223.5-19223.29" switch \initial - attribute \src "libresoc.v:19113.9-19113.17" + attribute \src "libresoc.v:19223.9-19223.17" case 1'1 case end @@ -27312,33 +27422,33 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000000000 + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] + update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:19131.3-19149.6" - process $proc$libresoc.v:19131$391 + attribute \src "libresoc.v:19241.3-19259.6" + process $proc$libresoc.v:19241$391 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:19132.5-19132.29" + attribute \src "libresoc.v:19242.5-19242.29" switch \initial - attribute \src "libresoc.v:19132.9-19132.17" + attribute \src "libresoc.v:19242.9-19242.17" case 1'1 case end @@ -27366,14 +27476,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:19150.3-19168.6" - process $proc$libresoc.v:19150$392 + attribute \src "libresoc.v:19260.3-19278.6" + process $proc$libresoc.v:19260$392 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:19151.5-19151.29" + attribute \src "libresoc.v:19261.5-19261.29" switch \initial - attribute \src "libresoc.v:19151.9-19151.17" + attribute \src "libresoc.v:19261.9-19261.17" case 1'1 case end @@ -27401,14 +27511,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:19169.3-19187.6" - process $proc$libresoc.v:19169$393 + attribute \src "libresoc.v:19279.3-19297.6" + process $proc$libresoc.v:19279$393 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19170.5-19170.29" + attribute \src "libresoc.v:19280.5-19280.29" switch \initial - attribute \src "libresoc.v:19170.9-19170.17" + attribute \src "libresoc.v:19280.9-19280.17" case 1'1 case end @@ -27436,14 +27546,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:19188.3-19206.6" - process $proc$libresoc.v:19188$394 + attribute \src "libresoc.v:19298.3-19316.6" + process $proc$libresoc.v:19298$394 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19189.5-19189.29" + attribute \src "libresoc.v:19299.5-19299.29" switch \initial - attribute \src "libresoc.v:19189.9-19189.17" + attribute \src "libresoc.v:19299.9-19299.17" case 1'1 case end @@ -27471,14 +27581,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:19207.3-19225.6" - process $proc$libresoc.v:19207$395 + attribute \src "libresoc.v:19317.3-19335.6" + process $proc$libresoc.v:19317$395 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19208.5-19208.29" + attribute \src "libresoc.v:19318.5-19318.29" switch \initial - attribute \src "libresoc.v:19208.9-19208.17" + attribute \src "libresoc.v:19318.9-19318.17" case 1'1 case end @@ -27506,14 +27616,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:19226.3-19244.6" - process $proc$libresoc.v:19226$396 + attribute \src "libresoc.v:19336.3-19354.6" + process $proc$libresoc.v:19336$396 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19227.5-19227.29" + attribute \src "libresoc.v:19337.5-19337.29" switch \initial - attribute \src "libresoc.v:19227.9-19227.17" + attribute \src "libresoc.v:19337.9-19337.17" case 1'1 case end @@ -27541,14 +27651,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:19245.3-19263.6" - process $proc$libresoc.v:19245$397 + attribute \src "libresoc.v:19355.3-19373.6" + process $proc$libresoc.v:19355$397 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:19246.5-19246.29" + attribute \src "libresoc.v:19356.5-19356.29" switch \initial - attribute \src "libresoc.v:19246.9-19246.17" + attribute \src "libresoc.v:19356.9-19356.17" case 1'1 case end @@ -27576,14 +27686,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:19264.3-19282.6" - process $proc$libresoc.v:19264$398 + attribute \src "libresoc.v:19374.3-19392.6" + process $proc$libresoc.v:19374$398 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19265.5-19265.29" + attribute \src "libresoc.v:19375.5-19375.29" switch \initial - attribute \src "libresoc.v:19265.9-19265.17" + attribute \src "libresoc.v:19375.9-19375.17" case 1'1 case end @@ -27611,14 +27721,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:19283.3-19301.6" - process $proc$libresoc.v:19283$399 + attribute \src "libresoc.v:19393.3-19411.6" + process $proc$libresoc.v:19393$399 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:19284.5-19284.29" + attribute \src "libresoc.v:19394.5-19394.29" switch \initial - attribute \src "libresoc.v:19284.9-19284.17" + attribute \src "libresoc.v:19394.9-19394.17" case 1'1 case end @@ -27646,14 +27756,14 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_inv_a $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:19302.3-19320.6" - process $proc$libresoc.v:19302$400 + attribute \src "libresoc.v:19412.3-19430.6" + process $proc$libresoc.v:19412$400 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:19303.5-19303.29" + attribute \src "libresoc.v:19413.5-19413.29" switch \initial - attribute \src "libresoc.v:19303.9-19303.17" + attribute \src "libresoc.v:19413.9-19413.17" case 1'1 case end @@ -27683,56 +27793,56 @@ module \SHIFT_ROT_dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:19326.1-19669.10" +attribute \src "libresoc.v:19436.1-19781.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub26 - attribute \src "libresoc.v:19572.3-19587.6" + attribute \src "libresoc.v:19684.3-19699.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19588.3-19603.6" + attribute \src "libresoc.v:19700.3-19715.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19620.3-19635.6" + attribute \src "libresoc.v:19732.3-19747.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19652.3-19667.6" + attribute \src "libresoc.v:19764.3-19779.6" wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19492.3-19507.6" - wire width 13 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:19556.3-19571.6" + attribute \src "libresoc.v:19604.3-19619.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19668.3-19683.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19540.3-19555.6" + attribute \src "libresoc.v:19652.3-19667.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19636.3-19651.6" + attribute \src "libresoc.v:19748.3-19763.6" wire $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19508.3-19523.6" + attribute \src "libresoc.v:19620.3-19635.6" wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19604.3-19619.6" + attribute \src "libresoc.v:19716.3-19731.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19524.3-19539.6" + attribute \src "libresoc.v:19636.3-19651.6" wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:19327.7-19327.20" + attribute \src "libresoc.v:19437.7-19437.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19572.3-19587.6" + attribute \src "libresoc.v:19684.3-19699.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19588.3-19603.6" + attribute \src "libresoc.v:19700.3-19715.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19620.3-19635.6" + attribute \src "libresoc.v:19732.3-19747.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19652.3-19667.6" + attribute \src "libresoc.v:19764.3-19779.6" wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19492.3-19507.6" - wire width 13 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:19556.3-19571.6" + attribute \src "libresoc.v:19604.3-19619.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19668.3-19683.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19540.3-19555.6" + attribute \src "libresoc.v:19652.3-19667.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19636.3-19651.6" + attribute \src "libresoc.v:19748.3-19763.6" wire $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19508.3-19523.6" + attribute \src "libresoc.v:19620.3-19635.6" wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19604.3-19619.6" + attribute \src "libresoc.v:19716.3-19731.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19524.3-19539.6" + attribute \src "libresoc.v:19636.3-19651.6" wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -27763,21 +27873,22 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -27869,6 +27980,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -27883,28 +27995,28 @@ module \SHIFT_ROT_dec31_dec_sub26 wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "libresoc.v:19327.7-19327.15" + attribute \src "libresoc.v:19437.7-19437.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:19327.7-19327.20" - process $proc$libresoc.v:19327$413 + attribute \src "libresoc.v:19437.7-19437.20" + process $proc$libresoc.v:19437$413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:19492.3-19507.6" - process $proc$libresoc.v:19492$402 + attribute \src "libresoc.v:19604.3-19619.6" + process $proc$libresoc.v:19604$402 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:19493.5-19493.29" + assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:19605.5-19605.29" switch \initial - attribute \src "libresoc.v:19493.9-19493.17" + attribute \src "libresoc.v:19605.9-19605.17" case 1'1 case end @@ -27913,29 +28025,29 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] 13'0000000000000 + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] + update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:19508.3-19523.6" - process $proc$libresoc.v:19508$403 + attribute \src "libresoc.v:19620.3-19635.6" + process $proc$libresoc.v:19620$403 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19509.5-19509.29" + attribute \src "libresoc.v:19621.5-19621.29" switch \initial - attribute \src "libresoc.v:19509.9-19509.17" + attribute \src "libresoc.v:19621.9-19621.17" case 1'1 case end @@ -27959,14 +28071,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:19524.3-19539.6" - process $proc$libresoc.v:19524$404 + attribute \src "libresoc.v:19636.3-19651.6" + process $proc$libresoc.v:19636$404 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:19525.5-19525.29" + attribute \src "libresoc.v:19637.5-19637.29" switch \initial - attribute \src "libresoc.v:19525.9-19525.17" + attribute \src "libresoc.v:19637.9-19637.17" case 1'1 case end @@ -27990,14 +28102,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:19540.3-19555.6" - process $proc$libresoc.v:19540$405 + attribute \src "libresoc.v:19652.3-19667.6" + process $proc$libresoc.v:19652$405 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19541.5-19541.29" + attribute \src "libresoc.v:19653.5-19653.29" switch \initial - attribute \src "libresoc.v:19541.9-19541.17" + attribute \src "libresoc.v:19653.9-19653.17" case 1'1 case end @@ -28021,14 +28133,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:19556.3-19571.6" - process $proc$libresoc.v:19556$406 + attribute \src "libresoc.v:19668.3-19683.6" + process $proc$libresoc.v:19668$406 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19557.5-19557.29" + attribute \src "libresoc.v:19669.5-19669.29" switch \initial - attribute \src "libresoc.v:19557.9-19557.17" + attribute \src "libresoc.v:19669.9-19669.17" case 1'1 case end @@ -28052,14 +28164,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:19572.3-19587.6" - process $proc$libresoc.v:19572$407 + attribute \src "libresoc.v:19684.3-19699.6" + process $proc$libresoc.v:19684$407 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19573.5-19573.29" + attribute \src "libresoc.v:19685.5-19685.29" switch \initial - attribute \src "libresoc.v:19573.9-19573.17" + attribute \src "libresoc.v:19685.9-19685.17" case 1'1 case end @@ -28083,14 +28195,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:19588.3-19603.6" - process $proc$libresoc.v:19588$408 + attribute \src "libresoc.v:19700.3-19715.6" + process $proc$libresoc.v:19700$408 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19589.5-19589.29" + attribute \src "libresoc.v:19701.5-19701.29" switch \initial - attribute \src "libresoc.v:19589.9-19589.17" + attribute \src "libresoc.v:19701.9-19701.17" case 1'1 case end @@ -28114,14 +28226,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:19604.3-19619.6" - process $proc$libresoc.v:19604$409 + attribute \src "libresoc.v:19716.3-19731.6" + process $proc$libresoc.v:19716$409 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19605.5-19605.29" + attribute \src "libresoc.v:19717.5-19717.29" switch \initial - attribute \src "libresoc.v:19605.9-19605.17" + attribute \src "libresoc.v:19717.9-19717.17" case 1'1 case end @@ -28145,14 +28257,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:19620.3-19635.6" - process $proc$libresoc.v:19620$410 + attribute \src "libresoc.v:19732.3-19747.6" + process $proc$libresoc.v:19732$410 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19621.5-19621.29" + attribute \src "libresoc.v:19733.5-19733.29" switch \initial - attribute \src "libresoc.v:19621.9-19621.17" + attribute \src "libresoc.v:19733.9-19733.17" case 1'1 case end @@ -28176,14 +28288,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:19636.3-19651.6" - process $proc$libresoc.v:19636$411 + attribute \src "libresoc.v:19748.3-19763.6" + process $proc$libresoc.v:19748$411 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19637.5-19637.29" + attribute \src "libresoc.v:19749.5-19749.29" switch \initial - attribute \src "libresoc.v:19637.9-19637.17" + attribute \src "libresoc.v:19749.9-19749.17" case 1'1 case end @@ -28207,14 +28319,14 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_inv_a $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:19652.3-19667.6" - process $proc$libresoc.v:19652$412 + attribute \src "libresoc.v:19764.3-19779.6" + process $proc$libresoc.v:19764$412 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19653.5-19653.29" + attribute \src "libresoc.v:19765.5-19765.29" switch \initial - attribute \src "libresoc.v:19653.9-19653.17" + attribute \src "libresoc.v:19765.9-19765.17" case 1'1 case end @@ -28240,56 +28352,56 @@ module \SHIFT_ROT_dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:19673.1-20049.10" +attribute \src "libresoc.v:19785.1-20163.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub27 - attribute \src "libresoc.v:19934.3-19952.6" + attribute \src "libresoc.v:20048.3-20066.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19953.3-19971.6" + attribute \src "libresoc.v:20067.3-20085.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19991.3-20009.6" + attribute \src "libresoc.v:20105.3-20123.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:20029.3-20047.6" + attribute \src "libresoc.v:20143.3-20161.6" wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19839.3-19857.6" - wire width 13 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:19915.3-19933.6" + attribute \src "libresoc.v:19953.3-19971.6" + wire width 14 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:20029.3-20047.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19896.3-19914.6" - wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] attribute \src "libresoc.v:20010.3-20028.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:20124.3-20142.6" wire $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:19858.3-19876.6" - wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] attribute \src "libresoc.v:19972.3-19990.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:20086.3-20104.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19877.3-19895.6" + attribute \src "libresoc.v:19991.3-20009.6" wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:19674.7-19674.20" + attribute \src "libresoc.v:19786.7-19786.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19934.3-19952.6" + attribute \src "libresoc.v:20048.3-20066.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19953.3-19971.6" + attribute \src "libresoc.v:20067.3-20085.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19991.3-20009.6" + attribute \src "libresoc.v:20105.3-20123.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:20029.3-20047.6" + attribute \src "libresoc.v:20143.3-20161.6" wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19839.3-19857.6" - wire width 13 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:19915.3-19933.6" + attribute \src "libresoc.v:19953.3-19971.6" + wire width 14 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:20029.3-20047.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19896.3-19914.6" - wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] attribute \src "libresoc.v:20010.3-20028.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:20124.3-20142.6" wire $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:19858.3-19876.6" - wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] attribute \src "libresoc.v:19972.3-19990.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:20086.3-20104.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19877.3-19895.6" + attribute \src "libresoc.v:19991.3-20009.6" wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -28320,21 +28432,22 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -28426,6 +28539,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -28440,28 +28554,28 @@ module \SHIFT_ROT_dec31_dec_sub27 wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "libresoc.v:19674.7-19674.15" + attribute \src "libresoc.v:19786.7-19786.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:19674.7-19674.20" - process $proc$libresoc.v:19674$425 + attribute \src "libresoc.v:19786.7-19786.20" + process $proc$libresoc.v:19786$425 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:19839.3-19857.6" - process $proc$libresoc.v:19839$414 + attribute \src "libresoc.v:19953.3-19971.6" + process $proc$libresoc.v:19953$414 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:19840.5-19840.29" + assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:19954.5-19954.29" switch \initial - attribute \src "libresoc.v:19840.9-19840.17" + attribute \src "libresoc.v:19954.9-19954.17" case 1'1 case end @@ -28470,33 +28584,33 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000000000 + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] + update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:19858.3-19876.6" - process $proc$libresoc.v:19858$415 + attribute \src "libresoc.v:19972.3-19990.6" + process $proc$libresoc.v:19972$415 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19859.5-19859.29" + attribute \src "libresoc.v:19973.5-19973.29" switch \initial - attribute \src "libresoc.v:19859.9-19859.17" + attribute \src "libresoc.v:19973.9-19973.17" case 1'1 case end @@ -28524,14 +28638,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:19877.3-19895.6" - process $proc$libresoc.v:19877$416 + attribute \src "libresoc.v:19991.3-20009.6" + process $proc$libresoc.v:19991$416 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:19878.5-19878.29" + attribute \src "libresoc.v:19992.5-19992.29" switch \initial - attribute \src "libresoc.v:19878.9-19878.17" + attribute \src "libresoc.v:19992.9-19992.17" case 1'1 case end @@ -28559,14 +28673,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:19896.3-19914.6" - process $proc$libresoc.v:19896$417 + attribute \src "libresoc.v:20010.3-20028.6" + process $proc$libresoc.v:20010$417 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19897.5-19897.29" + attribute \src "libresoc.v:20011.5-20011.29" switch \initial - attribute \src "libresoc.v:19897.9-19897.17" + attribute \src "libresoc.v:20011.9-20011.17" case 1'1 case end @@ -28594,14 +28708,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:19915.3-19933.6" - process $proc$libresoc.v:19915$418 + attribute \src "libresoc.v:20029.3-20047.6" + process $proc$libresoc.v:20029$418 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19916.5-19916.29" + attribute \src "libresoc.v:20030.5-20030.29" switch \initial - attribute \src "libresoc.v:19916.9-19916.17" + attribute \src "libresoc.v:20030.9-20030.17" case 1'1 case end @@ -28629,14 +28743,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:19934.3-19952.6" - process $proc$libresoc.v:19934$419 + attribute \src "libresoc.v:20048.3-20066.6" + process $proc$libresoc.v:20048$419 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19935.5-19935.29" + attribute \src "libresoc.v:20049.5-20049.29" switch \initial - attribute \src "libresoc.v:19935.9-19935.17" + attribute \src "libresoc.v:20049.9-20049.17" case 1'1 case end @@ -28664,14 +28778,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:19953.3-19971.6" - process $proc$libresoc.v:19953$420 + attribute \src "libresoc.v:20067.3-20085.6" + process $proc$libresoc.v:20067$420 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19954.5-19954.29" + attribute \src "libresoc.v:20068.5-20068.29" switch \initial - attribute \src "libresoc.v:19954.9-19954.17" + attribute \src "libresoc.v:20068.9-20068.17" case 1'1 case end @@ -28699,14 +28813,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:19972.3-19990.6" - process $proc$libresoc.v:19972$421 + attribute \src "libresoc.v:20086.3-20104.6" + process $proc$libresoc.v:20086$421 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19973.5-19973.29" + attribute \src "libresoc.v:20087.5-20087.29" switch \initial - attribute \src "libresoc.v:19973.9-19973.17" + attribute \src "libresoc.v:20087.9-20087.17" case 1'1 case end @@ -28734,14 +28848,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:19991.3-20009.6" - process $proc$libresoc.v:19991$422 + attribute \src "libresoc.v:20105.3-20123.6" + process $proc$libresoc.v:20105$422 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19992.5-19992.29" + attribute \src "libresoc.v:20106.5-20106.29" switch \initial - attribute \src "libresoc.v:19992.9-19992.17" + attribute \src "libresoc.v:20106.9-20106.17" case 1'1 case end @@ -28769,14 +28883,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:20010.3-20028.6" - process $proc$libresoc.v:20010$423 + attribute \src "libresoc.v:20124.3-20142.6" + process $proc$libresoc.v:20124$423 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:20011.5-20011.29" + attribute \src "libresoc.v:20125.5-20125.29" switch \initial - attribute \src "libresoc.v:20011.9-20011.17" + attribute \src "libresoc.v:20125.9-20125.17" case 1'1 case end @@ -28804,14 +28918,14 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_inv_a $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:20029.3-20047.6" - process $proc$libresoc.v:20029$424 + attribute \src "libresoc.v:20143.3-20161.6" + process $proc$libresoc.v:20143$424 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:20030.5-20030.29" + attribute \src "libresoc.v:20144.5-20144.29" switch \initial - attribute \src "libresoc.v:20030.9-20030.17" + attribute \src "libresoc.v:20144.9-20144.17" case 1'1 case end @@ -28856,36 +28970,36 @@ module \SPBlock_512W64B8W attribute \src "SPBlock_512W64B8W.v:5.17-5.19" wire width 8 input 4 \we end -attribute \src "libresoc.v:20053.1-20381.10" +attribute \src "libresoc.v:20167.1-20499.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" attribute \generator "nMigen" module \SPR_dec31 - attribute \src "libresoc.v:20338.3-20347.6" + attribute \src "libresoc.v:20456.3-20465.6" wire width 3 $0\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20348.3-20357.6" + attribute \src "libresoc.v:20466.3-20475.6" wire width 3 $0\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20318.3-20327.6" - wire width 13 $0\SPR_dec31_function_unit[12:0] - attribute \src "libresoc.v:20328.3-20337.6" + attribute \src "libresoc.v:20436.3-20445.6" + wire width 14 $0\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20446.3-20455.6" wire width 7 $0\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20368.3-20377.6" + attribute \src "libresoc.v:20486.3-20495.6" wire $0\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20358.3-20367.6" + attribute \src "libresoc.v:20476.3-20485.6" wire width 2 $0\SPR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:20054.7-20054.20" + attribute \src "libresoc.v:20168.7-20168.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20338.3-20347.6" + attribute \src "libresoc.v:20456.3-20465.6" wire width 3 $1\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20348.3-20357.6" + attribute \src "libresoc.v:20466.3-20475.6" wire width 3 $1\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20318.3-20327.6" - wire width 13 $1\SPR_dec31_function_unit[12:0] - attribute \src "libresoc.v:20328.3-20337.6" + attribute \src "libresoc.v:20436.3-20445.6" + wire width 14 $1\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20446.3-20455.6" wire width 7 $1\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20368.3-20377.6" + attribute \src "libresoc.v:20486.3-20495.6" wire $1\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20358.3-20367.6" + attribute \src "libresoc.v:20476.3-20485.6" wire width 2 $1\SPR_dec31_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -28928,21 +29042,22 @@ module \SPR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -29017,6 +29132,7 @@ module \SPR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -29030,21 +29146,22 @@ module \SPR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SPR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \SPR_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -29119,6 +29236,7 @@ module \SPR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SPR_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -29129,7 +29247,7 @@ module \SPR_dec31 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \SPR_dec31_rc_sel - attribute \src "libresoc.v:20054.7-20054.15" + attribute \src "libresoc.v:20168.7-20168.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -29138,7 +29256,7 @@ module \SPR_dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:20309.23-20317.4" + attribute \src "libresoc.v:20427.23-20435.4" cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out @@ -29148,22 +29266,22 @@ module \SPR_dec31 connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel connect \opcode_in \SPR_dec31_dec_sub19_opcode_in end - attribute \src "libresoc.v:20054.7-20054.20" - process $proc$libresoc.v:20054$432 + attribute \src "libresoc.v:20168.7-20168.20" + process $proc$libresoc.v:20168$432 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20318.3-20327.6" - process $proc$libresoc.v:20318$426 + attribute \src "libresoc.v:20436.3-20445.6" + process $proc$libresoc.v:20436$426 assign { } { } assign { } { } - assign $0\SPR_dec31_function_unit[12:0] $1\SPR_dec31_function_unit[12:0] - attribute \src "libresoc.v:20319.5-20319.29" + assign $0\SPR_dec31_function_unit[13:0] $1\SPR_dec31_function_unit[13:0] + attribute \src "libresoc.v:20437.5-20437.29" switch \initial - attribute \src "libresoc.v:20319.9-20319.17" + attribute \src "libresoc.v:20437.9-20437.17" case 1'1 case end @@ -29172,21 +29290,21 @@ module \SPR_dec31 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\SPR_dec31_function_unit[12:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + assign $1\SPR_dec31_function_unit[13:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit case - assign $1\SPR_dec31_function_unit[12:0] 13'0000000000000 + assign $1\SPR_dec31_function_unit[13:0] 14'00000000000000 end sync always - update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[12:0] + update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[13:0] end - attribute \src "libresoc.v:20328.3-20337.6" - process $proc$libresoc.v:20328$427 + attribute \src "libresoc.v:20446.3-20455.6" + process $proc$libresoc.v:20446$427 assign { } { } assign { } { } assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20329.5-20329.29" + attribute \src "libresoc.v:20447.5-20447.29" switch \initial - attribute \src "libresoc.v:20329.9-20329.17" + attribute \src "libresoc.v:20447.9-20447.17" case 1'1 case end @@ -29202,14 +29320,14 @@ module \SPR_dec31 sync always update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] end - attribute \src "libresoc.v:20338.3-20347.6" - process $proc$libresoc.v:20338$428 + attribute \src "libresoc.v:20456.3-20465.6" + process $proc$libresoc.v:20456$428 assign { } { } assign { } { } assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20339.5-20339.29" + attribute \src "libresoc.v:20457.5-20457.29" switch \initial - attribute \src "libresoc.v:20339.9-20339.17" + attribute \src "libresoc.v:20457.9-20457.17" case 1'1 case end @@ -29225,14 +29343,14 @@ module \SPR_dec31 sync always update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] end - attribute \src "libresoc.v:20348.3-20357.6" - process $proc$libresoc.v:20348$429 + attribute \src "libresoc.v:20466.3-20475.6" + process $proc$libresoc.v:20466$429 assign { } { } assign { } { } assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20349.5-20349.29" + attribute \src "libresoc.v:20467.5-20467.29" switch \initial - attribute \src "libresoc.v:20349.9-20349.17" + attribute \src "libresoc.v:20467.9-20467.17" case 1'1 case end @@ -29248,14 +29366,14 @@ module \SPR_dec31 sync always update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] end - attribute \src "libresoc.v:20358.3-20367.6" - process $proc$libresoc.v:20358$430 + attribute \src "libresoc.v:20476.3-20485.6" + process $proc$libresoc.v:20476$430 assign { } { } assign { } { } assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:20359.5-20359.29" + attribute \src "libresoc.v:20477.5-20477.29" switch \initial - attribute \src "libresoc.v:20359.9-20359.17" + attribute \src "libresoc.v:20477.9-20477.17" case 1'1 case end @@ -29271,14 +29389,14 @@ module \SPR_dec31 sync always update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:20368.3-20377.6" - process $proc$libresoc.v:20368$431 + attribute \src "libresoc.v:20486.3-20495.6" + process $proc$libresoc.v:20486$431 assign { } { } assign { } { } assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20369.5-20369.29" + attribute \src "libresoc.v:20487.5-20487.29" switch \initial - attribute \src "libresoc.v:20369.9-20369.17" + attribute \src "libresoc.v:20487.9-20487.17" case 1'1 case end @@ -29298,36 +29416,36 @@ module \SPR_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:20385.1-20596.10" +attribute \src "libresoc.v:20503.1-20716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" attribute \generator "nMigen" module \SPR_dec31_dec_sub19 - attribute \src "libresoc.v:20543.3-20555.6" + attribute \src "libresoc.v:20663.3-20675.6" wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20556.3-20568.6" + attribute \src "libresoc.v:20676.3-20688.6" wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20517.3-20529.6" - wire width 13 $0\SPR_dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:20530.3-20542.6" + attribute \src "libresoc.v:20637.3-20649.6" + wire width 14 $0\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20650.3-20662.6" wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20582.3-20594.6" + attribute \src "libresoc.v:20702.3-20714.6" wire $0\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20569.3-20581.6" + attribute \src "libresoc.v:20689.3-20701.6" wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:20386.7-20386.20" + attribute \src "libresoc.v:20504.7-20504.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20543.3-20555.6" + attribute \src "libresoc.v:20663.3-20675.6" wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20556.3-20568.6" + attribute \src "libresoc.v:20676.3-20688.6" wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20517.3-20529.6" - wire width 13 $1\SPR_dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:20530.3-20542.6" + attribute \src "libresoc.v:20637.3-20649.6" + wire width 14 $1\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20650.3-20662.6" wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20582.3-20594.6" + attribute \src "libresoc.v:20702.3-20714.6" wire $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20569.3-20581.6" + attribute \src "libresoc.v:20689.3-20701.6" wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -29350,21 +29468,22 @@ module \SPR_dec31_dec_sub19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \SPR_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -29439,6 +29558,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -29449,28 +29569,28 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:20386.7-20386.15" + attribute \src "libresoc.v:20504.7-20504.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 7 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:20386.7-20386.20" - process $proc$libresoc.v:20386$439 + attribute \src "libresoc.v:20504.7-20504.20" + process $proc$libresoc.v:20504$439 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20517.3-20529.6" - process $proc$libresoc.v:20517$433 + attribute \src "libresoc.v:20637.3-20649.6" + process $proc$libresoc.v:20637$433 assign { } { } assign { } { } - assign $0\SPR_dec31_dec_sub19_function_unit[12:0] $1\SPR_dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:20518.5-20518.29" + assign $0\SPR_dec31_dec_sub19_function_unit[13:0] $1\SPR_dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:20638.5-20638.29" switch \initial - attribute \src "libresoc.v:20518.9-20518.17" + attribute \src "libresoc.v:20638.9-20638.17" case 1'1 case end @@ -29479,25 +29599,25 @@ module \SPR_dec31_dec_sub19 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\SPR_dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00010000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\SPR_dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00010000000000 case - assign $1\SPR_dec31_dec_sub19_function_unit[12:0] 13'0000000000000 + assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00000000000000 end sync always - update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[12:0] + update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:20530.3-20542.6" - process $proc$libresoc.v:20530$434 + attribute \src "libresoc.v:20650.3-20662.6" + process $proc$libresoc.v:20650$434 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20531.5-20531.29" + attribute \src "libresoc.v:20651.5-20651.29" switch \initial - attribute \src "libresoc.v:20531.9-20531.17" + attribute \src "libresoc.v:20651.9-20651.17" case 1'1 case end @@ -29517,14 +29637,14 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:20543.3-20555.6" - process $proc$libresoc.v:20543$435 + attribute \src "libresoc.v:20663.3-20675.6" + process $proc$libresoc.v:20663$435 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20544.5-20544.29" + attribute \src "libresoc.v:20664.5-20664.29" switch \initial - attribute \src "libresoc.v:20544.9-20544.17" + attribute \src "libresoc.v:20664.9-20664.17" case 1'1 case end @@ -29544,14 +29664,14 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:20556.3-20568.6" - process $proc$libresoc.v:20556$436 + attribute \src "libresoc.v:20676.3-20688.6" + process $proc$libresoc.v:20676$436 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20557.5-20557.29" + attribute \src "libresoc.v:20677.5-20677.29" switch \initial - attribute \src "libresoc.v:20557.9-20557.17" + attribute \src "libresoc.v:20677.9-20677.17" case 1'1 case end @@ -29571,14 +29691,14 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:20569.3-20581.6" - process $proc$libresoc.v:20569$437 + attribute \src "libresoc.v:20689.3-20701.6" + process $proc$libresoc.v:20689$437 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:20570.5-20570.29" + attribute \src "libresoc.v:20690.5-20690.29" switch \initial - attribute \src "libresoc.v:20570.9-20570.17" + attribute \src "libresoc.v:20690.9-20690.17" case 1'1 case end @@ -29598,14 +29718,14 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:20582.3-20594.6" - process $proc$libresoc.v:20582$438 + attribute \src "libresoc.v:20702.3-20714.6" + process $proc$libresoc.v:20702$438 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20583.5-20583.29" + attribute \src "libresoc.v:20703.5-20703.29" switch \initial - attribute \src "libresoc.v:20583.9-20583.17" + attribute \src "libresoc.v:20703.9-20703.17" case 1'1 case end @@ -29627,93 +29747,93 @@ module \SPR_dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:20600.1-20872.10" +attribute \src "libresoc.v:20720.1-20992.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" attribute \generator "nMigen" module \_fsm - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $0\fsm_state$next[3:0]$464 - attribute \src "libresoc.v:20686.3-20687.35" + attribute \src "libresoc.v:20806.3-20807.35" wire width 4 $0\fsm_state[3:0] - attribute \src "libresoc.v:20601.7-20601.20" + attribute \src "libresoc.v:20721.7-20721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20692.3-20719.6" + attribute \src "libresoc.v:20812.3-20839.6" wire $0\isdr$next[0:0]$460 - attribute \src "libresoc.v:20688.3-20689.25" + attribute \src "libresoc.v:20808.3-20809.25" wire $0\isdr[0:0] - attribute \src "libresoc.v:20835.3-20862.6" + attribute \src "libresoc.v:20955.3-20982.6" wire $0\isir$next[0:0]$477 - attribute \src "libresoc.v:20690.3-20691.25" + attribute \src "libresoc.v:20810.3-20811.25" wire $0\isir[0:0] - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $10\fsm_state$next[3:0]$474 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $11\fsm_state$next[3:0]$475 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $1\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20641.13-20641.29" + attribute \src "libresoc.v:20761.13-20761.29" wire width 4 $1\fsm_state[3:0] - attribute \src "libresoc.v:20692.3-20719.6" + attribute \src "libresoc.v:20812.3-20839.6" wire $1\isdr$next[0:0]$461 - attribute \src "libresoc.v:20646.7-20646.18" + attribute \src "libresoc.v:20766.7-20766.18" wire $1\isdr[0:0] - attribute \src "libresoc.v:20835.3-20862.6" + attribute \src "libresoc.v:20955.3-20982.6" wire $1\isir$next[0:0]$478 - attribute \src "libresoc.v:20651.7-20651.18" + attribute \src "libresoc.v:20771.7-20771.18" wire $1\isir[0:0] - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $2\fsm_state$next[3:0]$466 - attribute \src "libresoc.v:20692.3-20719.6" + attribute \src "libresoc.v:20812.3-20839.6" wire $2\isdr$next[0:0]$462 - attribute \src "libresoc.v:20835.3-20862.6" + attribute \src "libresoc.v:20955.3-20982.6" wire $2\isir$next[0:0]$479 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $3\fsm_state$next[3:0]$467 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $4\fsm_state$next[3:0]$468 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $5\fsm_state$next[3:0]$469 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $6\fsm_state$next[3:0]$470 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $7\fsm_state$next[3:0]$471 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $8\fsm_state$next[3:0]$472 - attribute \src "libresoc.v:20720.3-20834.6" + attribute \src "libresoc.v:20840.3-20954.6" wire width 4 $9\fsm_state$next[3:0]$473 - attribute \src "libresoc.v:20670.17-20670.110" - wire $eq$libresoc.v:20670$440_Y - attribute \src "libresoc.v:20671.18-20671.111" - wire $eq$libresoc.v:20671$441_Y - attribute \src "libresoc.v:20672.18-20672.111" - wire $eq$libresoc.v:20672$442_Y - attribute \src "libresoc.v:20673.18-20673.111" - wire $eq$libresoc.v:20673$443_Y - attribute \src "libresoc.v:20674.18-20674.111" - wire $eq$libresoc.v:20674$444_Y - attribute \src "libresoc.v:20675.17-20675.108" - wire $eq$libresoc.v:20675$445_Y - attribute \src "libresoc.v:20676.18-20676.111" - wire $eq$libresoc.v:20676$446_Y - attribute \src "libresoc.v:20677.18-20677.111" - wire $eq$libresoc.v:20677$447_Y - attribute \src "libresoc.v:20678.18-20678.111" - wire $eq$libresoc.v:20678$448_Y - attribute \src "libresoc.v:20679.18-20679.111" - wire $eq$libresoc.v:20679$449_Y - attribute \src "libresoc.v:20680.18-20680.111" - wire $eq$libresoc.v:20680$450_Y - attribute \src "libresoc.v:20681.18-20681.111" - wire $eq$libresoc.v:20681$451_Y - attribute \src "libresoc.v:20682.18-20682.112" - wire $eq$libresoc.v:20682$452_Y - attribute \src "libresoc.v:20683.17-20683.108" - wire $eq$libresoc.v:20683$453_Y - attribute \src "libresoc.v:20684.17-20684.108" - wire $eq$libresoc.v:20684$454_Y - attribute \src "libresoc.v:20685.17-20685.108" - wire $eq$libresoc.v:20685$455_Y + attribute \src "libresoc.v:20790.17-20790.110" + wire $eq$libresoc.v:20790$440_Y + attribute \src "libresoc.v:20791.18-20791.111" + wire $eq$libresoc.v:20791$441_Y + attribute \src "libresoc.v:20792.18-20792.111" + wire $eq$libresoc.v:20792$442_Y + attribute \src "libresoc.v:20793.18-20793.111" + wire $eq$libresoc.v:20793$443_Y + attribute \src "libresoc.v:20794.18-20794.111" + wire $eq$libresoc.v:20794$444_Y + attribute \src "libresoc.v:20795.17-20795.108" + wire $eq$libresoc.v:20795$445_Y + attribute \src "libresoc.v:20796.18-20796.111" + wire $eq$libresoc.v:20796$446_Y + attribute \src "libresoc.v:20797.18-20797.111" + wire $eq$libresoc.v:20797$447_Y + attribute \src "libresoc.v:20798.18-20798.111" + wire $eq$libresoc.v:20798$448_Y + attribute \src "libresoc.v:20799.18-20799.111" + wire $eq$libresoc.v:20799$449_Y + attribute \src "libresoc.v:20800.18-20800.111" + wire $eq$libresoc.v:20800$450_Y + attribute \src "libresoc.v:20801.18-20801.111" + wire $eq$libresoc.v:20801$451_Y + attribute \src "libresoc.v:20802.18-20802.112" + wire $eq$libresoc.v:20802$452_Y + attribute \src "libresoc.v:20803.17-20803.108" + wire $eq$libresoc.v:20803$453_Y + attribute \src "libresoc.v:20804.17-20804.108" + wire $eq$libresoc.v:20804$454_Y + attribute \src "libresoc.v:20805.17-20805.108" + wire $eq$libresoc.v:20805$455_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" @@ -29756,7 +29876,7 @@ module \_fsm wire width 4 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" wire width 4 \fsm_state$next - attribute \src "libresoc.v:20601.7-20601.15" + attribute \src "libresoc.v:20721.7-20721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" wire output 11 \isdr @@ -29783,7 +29903,7 @@ module \_fsm attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire output 3 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - cell $eq $eq$libresoc.v:20670$440 + cell $eq $eq$libresoc.v:20790$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29791,10 +29911,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20670$440_Y + connect \Y $eq$libresoc.v:20790$440_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - cell $eq $eq$libresoc.v:20671$441 + cell $eq $eq$libresoc.v:20791$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29802,10 +29922,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20671$441_Y + connect \Y $eq$libresoc.v:20791$441_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" - cell $eq $eq$libresoc.v:20672$442 + cell $eq $eq$libresoc.v:20792$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29813,10 +29933,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20672$442_Y + connect \Y $eq$libresoc.v:20792$442_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" - cell $eq $eq$libresoc.v:20673$443 + cell $eq $eq$libresoc.v:20793$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29824,10 +29944,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20673$443_Y + connect \Y $eq$libresoc.v:20793$443_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - cell $eq $eq$libresoc.v:20674$444 + cell $eq $eq$libresoc.v:20794$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29835,10 +29955,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20674$444_Y + connect \Y $eq$libresoc.v:20794$444_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" - cell $eq $eq$libresoc.v:20675$445 + cell $eq $eq$libresoc.v:20795$445 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29846,10 +29966,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:20675$445_Y + connect \Y $eq$libresoc.v:20795$445_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - cell $eq $eq$libresoc.v:20676$446 + cell $eq $eq$libresoc.v:20796$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29857,10 +29977,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20676$446_Y + connect \Y $eq$libresoc.v:20796$446_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" - cell $eq $eq$libresoc.v:20677$447 + cell $eq $eq$libresoc.v:20797$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29868,10 +29988,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20677$447_Y + connect \Y $eq$libresoc.v:20797$447_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" - cell $eq $eq$libresoc.v:20678$448 + cell $eq $eq$libresoc.v:20798$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29879,10 +29999,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20678$448_Y + connect \Y $eq$libresoc.v:20798$448_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" - cell $eq $eq$libresoc.v:20679$449 + cell $eq $eq$libresoc.v:20799$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29890,10 +30010,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20679$449_Y + connect \Y $eq$libresoc.v:20799$449_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" - cell $eq $eq$libresoc.v:20680$450 + cell $eq $eq$libresoc.v:20800$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29901,10 +30021,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20680$450_Y + connect \Y $eq$libresoc.v:20800$450_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" - cell $eq $eq$libresoc.v:20681$451 + cell $eq $eq$libresoc.v:20801$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29912,10 +30032,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20681$451_Y + connect \Y $eq$libresoc.v:20801$451_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" - cell $eq $eq$libresoc.v:20682$452 + cell $eq $eq$libresoc.v:20802$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29923,10 +30043,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20682$452_Y + connect \Y $eq$libresoc.v:20802$452_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - cell $eq $eq$libresoc.v:20683$453 + cell $eq $eq$libresoc.v:20803$453 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29934,10 +30054,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'11 - connect \Y $eq$libresoc.v:20683$453_Y + connect \Y $eq$libresoc.v:20803$453_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - cell $eq $eq$libresoc.v:20684$454 + cell $eq $eq$libresoc.v:20804$454 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29945,10 +30065,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 3'101 - connect \Y $eq$libresoc.v:20684$454_Y + connect \Y $eq$libresoc.v:20804$454_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - cell $eq $eq$libresoc.v:20685$455 + cell $eq $eq$libresoc.v:20805$455 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29956,69 +30076,69 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 4'1000 - connect \Y $eq$libresoc.v:20685$455_Y + connect \Y $eq$libresoc.v:20805$455_Y end - attribute \src "libresoc.v:20601.7-20601.20" - process $proc$libresoc.v:20601$480 + attribute \src "libresoc.v:20721.7-20721.20" + process $proc$libresoc.v:20721$480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20641.13-20641.29" - process $proc$libresoc.v:20641$481 + attribute \src "libresoc.v:20761.13-20761.29" + process $proc$libresoc.v:20761$481 assign { } { } assign $1\fsm_state[3:0] 4'0000 sync always sync init update \fsm_state $1\fsm_state[3:0] end - attribute \src "libresoc.v:20646.7-20646.18" - process $proc$libresoc.v:20646$482 + attribute \src "libresoc.v:20766.7-20766.18" + process $proc$libresoc.v:20766$482 assign { } { } assign $1\isdr[0:0] 1'0 sync always sync init update \isdr $1\isdr[0:0] end - attribute \src "libresoc.v:20651.7-20651.18" - process $proc$libresoc.v:20651$483 + attribute \src "libresoc.v:20771.7-20771.18" + process $proc$libresoc.v:20771$483 assign { } { } assign $1\isir[0:0] 1'0 sync always sync init update \isir $1\isir[0:0] end - attribute \src "libresoc.v:20686.3-20687.35" - process $proc$libresoc.v:20686$456 + attribute \src "libresoc.v:20806.3-20807.35" + process $proc$libresoc.v:20806$456 assign { } { } assign $0\fsm_state[3:0] \fsm_state$next sync posedge \local_clk update \fsm_state $0\fsm_state[3:0] end - attribute \src "libresoc.v:20688.3-20689.25" - process $proc$libresoc.v:20688$457 + attribute \src "libresoc.v:20808.3-20809.25" + process $proc$libresoc.v:20808$457 assign { } { } assign $0\isdr[0:0] \isdr$next sync posedge \local_clk update \isdr $0\isdr[0:0] end - attribute \src "libresoc.v:20690.3-20691.25" - process $proc$libresoc.v:20690$458 + attribute \src "libresoc.v:20810.3-20811.25" + process $proc$libresoc.v:20810$458 assign { } { } assign $0\isir[0:0] \isir$next sync posedge \local_clk update \isir $0\isir[0:0] end - attribute \src "libresoc.v:20692.3-20719.6" - process $proc$libresoc.v:20692$459 + attribute \src "libresoc.v:20812.3-20839.6" + process $proc$libresoc.v:20812$459 assign { } { } assign { } { } assign $0\isdr$next[0:0]$460 $1\isdr$next[0:0]$461 - attribute \src "libresoc.v:20693.5-20693.29" + attribute \src "libresoc.v:20813.5-20813.29" switch \initial - attribute \src "libresoc.v:20693.9-20693.17" + attribute \src "libresoc.v:20813.9-20813.17" case 1'1 case end @@ -30055,14 +30175,14 @@ module \_fsm sync always update \isdr$next $0\isdr$next[0:0]$460 end - attribute \src "libresoc.v:20720.3-20834.6" - process $proc$libresoc.v:20720$463 + attribute \src "libresoc.v:20840.3-20954.6" + process $proc$libresoc.v:20840$463 assign { } { } assign { } { } assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20721.5-20721.29" + attribute \src "libresoc.v:20841.5-20841.29" switch \initial - attribute \src "libresoc.v:20721.9-20721.17" + attribute \src "libresoc.v:20841.9-20841.17" case 1'1 case end @@ -30216,14 +30336,14 @@ module \_fsm sync always update \fsm_state$next $0\fsm_state$next[3:0]$464 end - attribute \src "libresoc.v:20835.3-20862.6" - process $proc$libresoc.v:20835$476 + attribute \src "libresoc.v:20955.3-20982.6" + process $proc$libresoc.v:20955$476 assign { } { } assign { } { } assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 - attribute \src "libresoc.v:20836.5-20836.29" + attribute \src "libresoc.v:20956.5-20956.29" switch \initial - attribute \src "libresoc.v:20836.9-20836.17" + attribute \src "libresoc.v:20956.9-20956.17" case 1'1 case end @@ -30260,22 +30380,22 @@ module \_fsm sync always update \isir$next $0\isir$next[0:0]$477 end - connect \$9 $eq$libresoc.v:20670$440_Y - connect \$11 $eq$libresoc.v:20671$441_Y - connect \$13 $eq$libresoc.v:20672$442_Y - connect \$15 $eq$libresoc.v:20673$443_Y - connect \$17 $eq$libresoc.v:20674$444_Y - connect \$1 $eq$libresoc.v:20675$445_Y - connect \$19 $eq$libresoc.v:20676$446_Y - connect \$21 $eq$libresoc.v:20677$447_Y - connect \$23 $eq$libresoc.v:20678$448_Y - connect \$25 $eq$libresoc.v:20679$449_Y - connect \$27 $eq$libresoc.v:20680$450_Y - connect \$29 $eq$libresoc.v:20681$451_Y - connect \$31 $eq$libresoc.v:20682$452_Y - connect \$3 $eq$libresoc.v:20683$453_Y - connect \$5 $eq$libresoc.v:20684$454_Y - connect \$7 $eq$libresoc.v:20685$455_Y + connect \$9 $eq$libresoc.v:20790$440_Y + connect \$11 $eq$libresoc.v:20791$441_Y + connect \$13 $eq$libresoc.v:20792$442_Y + connect \$15 $eq$libresoc.v:20793$443_Y + connect \$17 $eq$libresoc.v:20794$444_Y + connect \$1 $eq$libresoc.v:20795$445_Y + connect \$19 $eq$libresoc.v:20796$446_Y + connect \$21 $eq$libresoc.v:20797$447_Y + connect \$23 $eq$libresoc.v:20798$448_Y + connect \$25 $eq$libresoc.v:20799$449_Y + connect \$27 $eq$libresoc.v:20800$450_Y + connect \$29 $eq$libresoc.v:20801$451_Y + connect \$31 $eq$libresoc.v:20802$452_Y + connect \$3 $eq$libresoc.v:20803$453_Y + connect \$5 $eq$libresoc.v:20804$454_Y + connect \$7 $eq$libresoc.v:20805$455_Y connect \update \$7 connect \shift \$5 connect \capture \$3 @@ -30286,29 +30406,29 @@ module \_fsm connect \posjtag_rst \rst connect \posjtag_clk \TAP_bus__tck end -attribute \src "libresoc.v:20876.1-20948.10" +attribute \src "libresoc.v:20996.1-21068.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" attribute \generator "nMigen" module \_idblock - attribute \src "libresoc.v:20921.3-20941.6" + attribute \src "libresoc.v:21041.3-21061.6" wire width 32 $0\TAP_id_sr$next[31:0]$489 - attribute \src "libresoc.v:20919.3-20920.35" + attribute \src "libresoc.v:21039.3-21040.35" wire width 32 $0\TAP_id_sr[31:0] - attribute \src "libresoc.v:20877.7-20877.20" + attribute \src "libresoc.v:20997.7-20997.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20921.3-20941.6" + attribute \src "libresoc.v:21041.3-21061.6" wire width 32 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:20887.14-20887.31" + attribute \src "libresoc.v:21007.14-21007.31" wire width 32 $1\TAP_id_sr[31:0] - attribute \src "libresoc.v:20921.3-20941.6" + attribute \src "libresoc.v:21041.3-21061.6" wire width 32 $2\TAP_id_sr$next[31:0]$491 - attribute \src "libresoc.v:20916.17-20916.110" - wire $and$libresoc.v:20916$484_Y - attribute \src "libresoc.v:20917.17-20917.108" - wire $and$libresoc.v:20917$485_Y - attribute \src "libresoc.v:20918.17-20918.109" - wire $and$libresoc.v:20918$486_Y + attribute \src "libresoc.v:21036.17-21036.110" + wire $and$libresoc.v:21036$484_Y + attribute \src "libresoc.v:21037.17-21037.108" + wire $and$libresoc.v:21037$485_Y + attribute \src "libresoc.v:21038.17-21038.109" + wire $and$libresoc.v:21038$486_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" @@ -30337,7 +30457,7 @@ module \_idblock wire input 2 \capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" wire input 1 \id_bypass - attribute \src "libresoc.v:20877.7-20877.15" + attribute \src "libresoc.v:20997.7-20997.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 8 \posjtag_clk @@ -30350,7 +30470,7 @@ module \_idblock attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 4 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - cell $and $and$libresoc.v:20916$484 + cell $and $and$libresoc.v:21036$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30358,10 +30478,10 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \capture - connect \Y $and$libresoc.v:20916$484_Y + connect \Y $and$libresoc.v:21036$484_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - cell $and $and$libresoc.v:20917$485 + cell $and $and$libresoc.v:21037$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30369,10 +30489,10 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \shift - connect \Y $and$libresoc.v:20917$485_Y + connect \Y $and$libresoc.v:21037$485_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - cell $and $and$libresoc.v:20918$486 + cell $and $and$libresoc.v:21038$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30380,39 +30500,39 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \update - connect \Y $and$libresoc.v:20918$486_Y + connect \Y $and$libresoc.v:21038$486_Y end - attribute \src "libresoc.v:20877.7-20877.20" - process $proc$libresoc.v:20877$492 + attribute \src "libresoc.v:20997.7-20997.20" + process $proc$libresoc.v:20997$492 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20887.14-20887.31" - process $proc$libresoc.v:20887$493 + attribute \src "libresoc.v:21007.14-21007.31" + process $proc$libresoc.v:21007$493 assign { } { } assign $1\TAP_id_sr[31:0] 0 sync always sync init update \TAP_id_sr $1\TAP_id_sr[31:0] end - attribute \src "libresoc.v:20919.3-20920.35" - process $proc$libresoc.v:20919$487 + attribute \src "libresoc.v:21039.3-21040.35" + process $proc$libresoc.v:21039$487 assign { } { } assign $0\TAP_id_sr[31:0] \TAP_id_sr$next sync posedge \posjtag_clk update \TAP_id_sr $0\TAP_id_sr[31:0] end - attribute \src "libresoc.v:20921.3-20941.6" - process $proc$libresoc.v:20921$488 + attribute \src "libresoc.v:21041.3-21061.6" + process $proc$libresoc.v:21041$488 assign { } { } assign { } { } assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:20922.5-20922.29" + attribute \src "libresoc.v:21042.5-21042.29" switch \initial - attribute \src "libresoc.v:20922.9-20922.17" + attribute \src "libresoc.v:21042.9-21042.17" case 1'1 case end @@ -30443,9 +30563,9 @@ module \_idblock sync always update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 end - connect \$1 $and$libresoc.v:20916$484_Y - connect \$3 $and$libresoc.v:20917$485_Y - connect \$5 $and$libresoc.v:20918$486_Y + connect \$1 $and$libresoc.v:21036$484_Y + connect \$3 $and$libresoc.v:21037$485_Y + connect \$5 $and$libresoc.v:21038$486_Y connect \TAP_id_tdo \TAP_id_sr [0] connect \_bypass \id_bypass connect \_update \$5 @@ -30453,43 +30573,43 @@ module \_idblock connect \_capture \$1 connect \_tdi \TAP_bus__tdi end -attribute \src "libresoc.v:20952.1-21036.10" +attribute \src "libresoc.v:21072.1-21156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" attribute \generator "nMigen" module \_irblock - attribute \src "libresoc.v:20953.7-20953.20" + attribute \src "libresoc.v:21073.7-21073.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21014.3-21034.6" + attribute \src "libresoc.v:21134.3-21154.6" wire width 4 $0\ir$next[3:0]$506 - attribute \src "libresoc.v:20997.3-20998.21" + attribute \src "libresoc.v:21117.3-21118.21" wire width 4 $0\ir[3:0] - attribute \src "libresoc.v:21001.3-21013.6" + attribute \src "libresoc.v:21121.3-21133.6" wire width 4 $0\shift_ir$next[3:0]$503 - attribute \src "libresoc.v:20999.3-21000.33" + attribute \src "libresoc.v:21119.3-21120.33" wire width 4 $0\shift_ir[3:0] - attribute \src "libresoc.v:21014.3-21034.6" + attribute \src "libresoc.v:21134.3-21154.6" wire width 4 $1\ir$next[3:0]$507 - attribute \src "libresoc.v:20972.13-20972.22" + attribute \src "libresoc.v:21092.13-21092.22" wire width 4 $1\ir[3:0] - attribute \src "libresoc.v:21001.3-21013.6" + attribute \src "libresoc.v:21121.3-21133.6" wire width 4 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:20984.13-20984.28" + attribute \src "libresoc.v:21104.13-21104.28" wire width 4 $1\shift_ir[3:0] - attribute \src "libresoc.v:21014.3-21034.6" + attribute \src "libresoc.v:21134.3-21154.6" wire width 4 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:20991.17-20991.103" - wire $and$libresoc.v:20991$494_Y - attribute \src "libresoc.v:20992.18-20992.105" - wire $and$libresoc.v:20992$495_Y - attribute \src "libresoc.v:20993.17-20993.105" - wire $and$libresoc.v:20993$496_Y - attribute \src "libresoc.v:20994.17-20994.103" - wire $and$libresoc.v:20994$497_Y - attribute \src "libresoc.v:20995.17-20995.104" - wire $and$libresoc.v:20995$498_Y - attribute \src "libresoc.v:20996.17-20996.105" - wire $and$libresoc.v:20996$499_Y + attribute \src "libresoc.v:21111.17-21111.103" + wire $and$libresoc.v:21111$494_Y + attribute \src "libresoc.v:21112.18-21112.105" + wire $and$libresoc.v:21112$495_Y + attribute \src "libresoc.v:21113.17-21113.105" + wire $and$libresoc.v:21113$496_Y + attribute \src "libresoc.v:21114.17-21114.103" + wire $and$libresoc.v:21114$497_Y + attribute \src "libresoc.v:21115.17-21115.104" + wire $and$libresoc.v:21115$498_Y + attribute \src "libresoc.v:21116.17-21116.105" + wire $and$libresoc.v:21116$499_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" @@ -30506,7 +30626,7 @@ module \_irblock wire input 4 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire input 1 \capture - attribute \src "libresoc.v:20953.7-20953.15" + attribute \src "libresoc.v:21073.7-21073.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 output 9 \ir @@ -30529,7 +30649,7 @@ module \_irblock attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 3 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:20991$494 + cell $and $and$libresoc.v:21111$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30537,10 +30657,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:20991$494_Y + connect \Y $and$libresoc.v:21111$494_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:20992$495 + cell $and $and$libresoc.v:21112$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30548,10 +30668,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:20992$495_Y + connect \Y $and$libresoc.v:21112$495_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:20993$496 + cell $and $and$libresoc.v:21113$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30559,10 +30679,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:20993$496_Y + connect \Y $and$libresoc.v:21113$496_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:20994$497 + cell $and $and$libresoc.v:21114$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30570,10 +30690,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:20994$497_Y + connect \Y $and$libresoc.v:21114$497_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:20995$498 + cell $and $and$libresoc.v:21115$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30581,10 +30701,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:20995$498_Y + connect \Y $and$libresoc.v:21115$498_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:20996$499 + cell $and $and$libresoc.v:21116$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30592,54 +30712,54 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:20996$499_Y + connect \Y $and$libresoc.v:21116$499_Y end - attribute \src "libresoc.v:20953.7-20953.20" - process $proc$libresoc.v:20953$509 + attribute \src "libresoc.v:21073.7-21073.20" + process $proc$libresoc.v:21073$509 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20972.13-20972.22" - process $proc$libresoc.v:20972$510 + attribute \src "libresoc.v:21092.13-21092.22" + process $proc$libresoc.v:21092$510 assign { } { } assign $1\ir[3:0] 4'0001 sync always sync init update \ir $1\ir[3:0] end - attribute \src "libresoc.v:20984.13-20984.28" - process $proc$libresoc.v:20984$511 + attribute \src "libresoc.v:21104.13-21104.28" + process $proc$libresoc.v:21104$511 assign { } { } assign $1\shift_ir[3:0] 4'0000 sync always sync init update \shift_ir $1\shift_ir[3:0] end - attribute \src "libresoc.v:20997.3-20998.21" - process $proc$libresoc.v:20997$500 + attribute \src "libresoc.v:21117.3-21118.21" + process $proc$libresoc.v:21117$500 assign { } { } assign $0\ir[3:0] \ir$next sync posedge \posjtag_clk update \ir $0\ir[3:0] end - attribute \src "libresoc.v:20999.3-21000.33" - process $proc$libresoc.v:20999$501 + attribute \src "libresoc.v:21119.3-21120.33" + process $proc$libresoc.v:21119$501 assign { } { } assign $0\shift_ir[3:0] \shift_ir$next sync posedge \posjtag_clk update \shift_ir $0\shift_ir[3:0] end - attribute \src "libresoc.v:21001.3-21013.6" - process $proc$libresoc.v:21001$502 + attribute \src "libresoc.v:21121.3-21133.6" + process $proc$libresoc.v:21121$502 assign { } { } assign { } { } assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:21002.5-21002.29" + attribute \src "libresoc.v:21122.5-21122.29" switch \initial - attribute \src "libresoc.v:21002.9-21002.17" + attribute \src "libresoc.v:21122.9-21122.17" case 1'1 case end @@ -30659,15 +30779,15 @@ module \_irblock sync always update \shift_ir$next $0\shift_ir$next[3:0]$503 end - attribute \src "libresoc.v:21014.3-21034.6" - process $proc$libresoc.v:21014$505 + attribute \src "libresoc.v:21134.3-21154.6" + process $proc$libresoc.v:21134$505 assign { } { } assign { } { } assign { } { } assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:21015.5-21015.29" + attribute \src "libresoc.v:21135.5-21135.29" switch \initial - attribute \src "libresoc.v:21015.9-21015.17" + attribute \src "libresoc.v:21135.9-21135.17" case 1'1 case end @@ -30698,45 +30818,45 @@ module \_irblock sync always update \ir$next $0\ir$next[3:0]$506 end - connect \$9 $and$libresoc.v:20991$494_Y - connect \$11 $and$libresoc.v:20992$495_Y - connect \$1 $and$libresoc.v:20993$496_Y - connect \$3 $and$libresoc.v:20994$497_Y - connect \$5 $and$libresoc.v:20995$498_Y - connect \$7 $and$libresoc.v:20996$499_Y + connect \$9 $and$libresoc.v:21111$494_Y + connect \$11 $and$libresoc.v:21112$495_Y + connect \$1 $and$libresoc.v:21113$496_Y + connect \$3 $and$libresoc.v:21114$497_Y + connect \$5 $and$libresoc.v:21115$498_Y + connect \$7 $and$libresoc.v:21116$499_Y connect \tdo \ir [0] end -attribute \src "libresoc.v:21040.1-21098.10" +attribute \src "libresoc.v:21160.1-21218.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" attribute \generator "nMigen" module \adr_l - attribute \src "libresoc.v:21041.7-21041.20" + attribute \src "libresoc.v:21161.7-21161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21086.3-21094.6" + attribute \src "libresoc.v:21206.3-21214.6" wire $0\q_int$next[0:0]$522 - attribute \src "libresoc.v:21084.3-21085.27" + attribute \src "libresoc.v:21204.3-21205.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:21086.3-21094.6" + attribute \src "libresoc.v:21206.3-21214.6" wire $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:21065.7-21065.19" + attribute \src "libresoc.v:21185.7-21185.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:21076.17-21076.96" - wire $and$libresoc.v:21076$512_Y - attribute \src "libresoc.v:21081.17-21081.96" - wire $and$libresoc.v:21081$517_Y - attribute \src "libresoc.v:21078.18-21078.93" - wire $not$libresoc.v:21078$514_Y - attribute \src "libresoc.v:21080.17-21080.92" - wire $not$libresoc.v:21080$516_Y - attribute \src "libresoc.v:21083.17-21083.92" - wire $not$libresoc.v:21083$519_Y - attribute \src "libresoc.v:21077.18-21077.98" - wire $or$libresoc.v:21077$513_Y - attribute \src "libresoc.v:21079.18-21079.99" - wire $or$libresoc.v:21079$515_Y - attribute \src "libresoc.v:21082.17-21082.97" - wire $or$libresoc.v:21082$518_Y + attribute \src "libresoc.v:21196.17-21196.96" + wire $and$libresoc.v:21196$512_Y + attribute \src "libresoc.v:21201.17-21201.96" + wire $and$libresoc.v:21201$517_Y + attribute \src "libresoc.v:21198.18-21198.93" + wire $not$libresoc.v:21198$514_Y + attribute \src "libresoc.v:21200.17-21200.92" + wire $not$libresoc.v:21200$516_Y + attribute \src "libresoc.v:21203.17-21203.92" + wire $not$libresoc.v:21203$519_Y + attribute \src "libresoc.v:21197.18-21197.98" + wire $or$libresoc.v:21197$513_Y + attribute \src "libresoc.v:21199.18-21199.99" + wire $or$libresoc.v:21199$515_Y + attribute \src "libresoc.v:21202.17-21202.97" + wire $or$libresoc.v:21202$518_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -30753,11 +30873,11 @@ module \adr_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:21041.7-21041.15" + attribute \src "libresoc.v:21161.7-21161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_adr @@ -30774,7 +30894,7 @@ module \adr_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:21076$512 + cell $and $and$libresoc.v:21196$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30782,10 +30902,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:21076$512_Y + connect \Y $and$libresoc.v:21196$512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:21081$517 + cell $and $and$libresoc.v:21201$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30793,34 +30913,34 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:21081$517_Y + connect \Y $and$libresoc.v:21201$517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:21078$514 + cell $not $not$libresoc.v:21198$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_adr - connect \Y $not$libresoc.v:21078$514_Y + connect \Y $not$libresoc.v:21198$514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:21080$516 + cell $not $not$libresoc.v:21200$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:21080$516_Y + connect \Y $not$libresoc.v:21200$516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:21083$519 + cell $not $not$libresoc.v:21203$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:21083$519_Y + connect \Y $not$libresoc.v:21203$519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:21077$513 + cell $or $or$libresoc.v:21197$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30828,10 +30948,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_adr - connect \Y $or$libresoc.v:21077$513_Y + connect \Y $or$libresoc.v:21197$513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:21079$515 + cell $or $or$libresoc.v:21199$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30839,10 +30959,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_adr connect \B \q_int - connect \Y $or$libresoc.v:21079$515_Y + connect \Y $or$libresoc.v:21199$515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:21082$518 + cell $or $or$libresoc.v:21202$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30850,39 +30970,39 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_adr - connect \Y $or$libresoc.v:21082$518_Y + connect \Y $or$libresoc.v:21202$518_Y end - attribute \src "libresoc.v:21041.7-21041.20" - process $proc$libresoc.v:21041$524 + attribute \src "libresoc.v:21161.7-21161.20" + process $proc$libresoc.v:21161$524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21065.7-21065.19" - process $proc$libresoc.v:21065$525 + attribute \src "libresoc.v:21185.7-21185.19" + process $proc$libresoc.v:21185$525 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:21084.3-21085.27" - process $proc$libresoc.v:21084$520 + attribute \src "libresoc.v:21204.3-21205.27" + process $proc$libresoc.v:21204$520 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:21086.3-21094.6" - process $proc$libresoc.v:21086$521 + attribute \src "libresoc.v:21206.3-21214.6" + process $proc$libresoc.v:21206$521 assign { } { } assign { } { } assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:21087.5-21087.29" + attribute \src "libresoc.v:21207.5-21207.29" switch \initial - attribute \src "libresoc.v:21087.9-21087.17" + attribute \src "libresoc.v:21207.9-21207.17" case 1'1 case end @@ -30898,49 +31018,49 @@ module \adr_l sync always update \q_int$next $0\q_int$next[0:0]$522 end - connect \$9 $and$libresoc.v:21076$512_Y - connect \$11 $or$libresoc.v:21077$513_Y - connect \$13 $not$libresoc.v:21078$514_Y - connect \$15 $or$libresoc.v:21079$515_Y - connect \$1 $not$libresoc.v:21080$516_Y - connect \$3 $and$libresoc.v:21081$517_Y - connect \$5 $or$libresoc.v:21082$518_Y - connect \$7 $not$libresoc.v:21083$519_Y + connect \$9 $and$libresoc.v:21196$512_Y + connect \$11 $or$libresoc.v:21197$513_Y + connect \$13 $not$libresoc.v:21198$514_Y + connect \$15 $or$libresoc.v:21199$515_Y + connect \$1 $not$libresoc.v:21200$516_Y + connect \$3 $and$libresoc.v:21201$517_Y + connect \$5 $or$libresoc.v:21202$518_Y + connect \$7 $not$libresoc.v:21203$519_Y connect \qlq_adr \$15 connect \qn_adr \$13 connect \q_adr \$11 end -attribute \src "libresoc.v:21102.1-21160.10" +attribute \src "libresoc.v:21222.1-21280.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" attribute \generator "nMigen" module \adrok_l - attribute \src "libresoc.v:21103.7-21103.20" + attribute \src "libresoc.v:21223.7-21223.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21148.3-21156.6" + attribute \src "libresoc.v:21268.3-21276.6" wire $0\q_int$next[0:0]$536 - attribute \src "libresoc.v:21146.3-21147.27" + attribute \src "libresoc.v:21266.3-21267.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:21148.3-21156.6" + attribute \src "libresoc.v:21268.3-21276.6" wire $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:21127.7-21127.19" + attribute \src "libresoc.v:21247.7-21247.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:21138.17-21138.96" - wire $and$libresoc.v:21138$526_Y - attribute \src "libresoc.v:21143.17-21143.96" - wire $and$libresoc.v:21143$531_Y - attribute \src "libresoc.v:21140.18-21140.100" - wire $not$libresoc.v:21140$528_Y - attribute \src "libresoc.v:21142.17-21142.99" - wire $not$libresoc.v:21142$530_Y - attribute \src "libresoc.v:21145.17-21145.99" - wire $not$libresoc.v:21145$533_Y - attribute \src "libresoc.v:21139.18-21139.105" - wire $or$libresoc.v:21139$527_Y - attribute \src "libresoc.v:21141.18-21141.106" - wire $or$libresoc.v:21141$529_Y - attribute \src "libresoc.v:21144.17-21144.104" - wire $or$libresoc.v:21144$532_Y + attribute \src "libresoc.v:21258.17-21258.96" + wire $and$libresoc.v:21258$526_Y + attribute \src "libresoc.v:21263.17-21263.96" + wire $and$libresoc.v:21263$531_Y + attribute \src "libresoc.v:21260.18-21260.100" + wire $not$libresoc.v:21260$528_Y + attribute \src "libresoc.v:21262.17-21262.99" + wire $not$libresoc.v:21262$530_Y + attribute \src "libresoc.v:21265.17-21265.99" + wire $not$libresoc.v:21265$533_Y + attribute \src "libresoc.v:21259.18-21259.105" + wire $or$libresoc.v:21259$527_Y + attribute \src "libresoc.v:21261.18-21261.106" + wire $or$libresoc.v:21261$529_Y + attribute \src "libresoc.v:21264.17-21264.104" + wire $or$libresoc.v:21264$532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -30957,11 +31077,11 @@ module \adrok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:21103.7-21103.15" + attribute \src "libresoc.v:21223.7-21223.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 5 \q_addr_acked @@ -30978,7 +31098,7 @@ module \adrok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:21138$526 + cell $and $and$libresoc.v:21258$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30986,10 +31106,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:21138$526_Y + connect \Y $and$libresoc.v:21258$526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:21143$531 + cell $and $and$libresoc.v:21263$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30997,34 +31117,34 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:21143$531_Y + connect \Y $and$libresoc.v:21263$531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:21140$528 + cell $not $not$libresoc.v:21260$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_addr_acked - connect \Y $not$libresoc.v:21140$528_Y + connect \Y $not$libresoc.v:21260$528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:21142$530 + cell $not $not$libresoc.v:21262$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:21142$530_Y + connect \Y $not$libresoc.v:21262$530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:21145$533 + cell $not $not$libresoc.v:21265$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:21145$533_Y + connect \Y $not$libresoc.v:21265$533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:21139$527 + cell $or $or$libresoc.v:21259$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31032,10 +31152,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_addr_acked - connect \Y $or$libresoc.v:21139$527_Y + connect \Y $or$libresoc.v:21259$527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:21141$529 + cell $or $or$libresoc.v:21261$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31043,10 +31163,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_addr_acked connect \B \q_int - connect \Y $or$libresoc.v:21141$529_Y + connect \Y $or$libresoc.v:21261$529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:21144$532 + cell $or $or$libresoc.v:21264$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31054,39 +31174,39 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_addr_acked - connect \Y $or$libresoc.v:21144$532_Y + connect \Y $or$libresoc.v:21264$532_Y end - attribute \src "libresoc.v:21103.7-21103.20" - process $proc$libresoc.v:21103$538 + attribute \src "libresoc.v:21223.7-21223.20" + process $proc$libresoc.v:21223$538 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21127.7-21127.19" - process $proc$libresoc.v:21127$539 + attribute \src "libresoc.v:21247.7-21247.19" + process $proc$libresoc.v:21247$539 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:21146.3-21147.27" - process $proc$libresoc.v:21146$534 + attribute \src "libresoc.v:21266.3-21267.27" + process $proc$libresoc.v:21266$534 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:21148.3-21156.6" - process $proc$libresoc.v:21148$535 + attribute \src "libresoc.v:21268.3-21276.6" + process $proc$libresoc.v:21268$535 assign { } { } assign { } { } assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:21149.5-21149.29" + attribute \src "libresoc.v:21269.5-21269.29" switch \initial - attribute \src "libresoc.v:21149.9-21149.17" + attribute \src "libresoc.v:21269.9-21269.17" case 1'1 case end @@ -31102,593 +31222,593 @@ module \adrok_l sync always update \q_int$next $0\q_int$next[0:0]$536 end - connect \$9 $and$libresoc.v:21138$526_Y - connect \$11 $or$libresoc.v:21139$527_Y - connect \$13 $not$libresoc.v:21140$528_Y - connect \$15 $or$libresoc.v:21141$529_Y - connect \$1 $not$libresoc.v:21142$530_Y - connect \$3 $and$libresoc.v:21143$531_Y - connect \$5 $or$libresoc.v:21144$532_Y - connect \$7 $not$libresoc.v:21145$533_Y + connect \$9 $and$libresoc.v:21258$526_Y + connect \$11 $or$libresoc.v:21259$527_Y + connect \$13 $not$libresoc.v:21260$528_Y + connect \$15 $or$libresoc.v:21261$529_Y + connect \$1 $not$libresoc.v:21262$530_Y + connect \$3 $and$libresoc.v:21263$531_Y + connect \$5 $or$libresoc.v:21264$532_Y + connect \$7 $not$libresoc.v:21265$533_Y connect \qlq_addr_acked \$15 connect \qn_addr_acked \$13 connect \q_addr_acked \$11 end -attribute \src "libresoc.v:21164.1-22491.10" +attribute \src "libresoc.v:21284.1-22615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" attribute \generator "nMigen" module \alu0 - attribute \src "libresoc.v:22002.3-22003.25" + attribute \src "libresoc.v:22126.3-22127.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 - attribute \src "libresoc.v:21974.3-21975.67" + attribute \src "libresoc.v:22098.3-22099.67" wire width 4 $0\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22192.3-22230.6" - wire width 13 $0\alu_alu0_alu_op__fn_unit$next[12:0]$687 - attribute \src "libresoc.v:21944.3-21945.65" - wire width 13 $0\alu_alu0_alu_op__fn_unit[12:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" + wire width 14 $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 + attribute \src "libresoc.v:22068.3-22069.65" + wire width 14 $0\alu_alu0_alu_op__fn_unit[13:0] + attribute \src "libresoc.v:22316.3-22354.6" wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 - attribute \src "libresoc.v:21946.3-21947.79" + attribute \src "libresoc.v:22070.3-22071.79" wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 - attribute \src "libresoc.v:21948.3-21949.75" + attribute \src "libresoc.v:22072.3-22073.75" wire $0\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 - attribute \src "libresoc.v:21966.3-21967.73" + attribute \src "libresoc.v:22090.3-22091.73" wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 - attribute \src "libresoc.v:21976.3-21977.59" + attribute \src "libresoc.v:22100.3-22101.59" wire width 32 $0\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 - attribute \src "libresoc.v:21942.3-21943.69" + attribute \src "libresoc.v:22066.3-22067.69" wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 - attribute \src "libresoc.v:21958.3-21959.69" + attribute \src "libresoc.v:22082.3-22083.69" wire $0\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 - attribute \src "libresoc.v:21962.3-21963.71" + attribute \src "libresoc.v:22086.3-22087.71" wire $0\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 - attribute \src "libresoc.v:21970.3-21971.67" + attribute \src "libresoc.v:22094.3-22095.67" wire $0\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 - attribute \src "libresoc.v:21972.3-21973.69" + attribute \src "libresoc.v:22096.3-22097.69" wire $0\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 - attribute \src "libresoc.v:21954.3-21955.63" + attribute \src "libresoc.v:22078.3-22079.63" wire $0\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 - attribute \src "libresoc.v:21956.3-21957.63" + attribute \src "libresoc.v:22080.3-22081.63" wire $0\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 - attribute \src "libresoc.v:21968.3-21969.75" + attribute \src "libresoc.v:22092.3-22093.75" wire $0\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 - attribute \src "libresoc.v:21952.3-21953.63" + attribute \src "libresoc.v:22076.3-22077.63" wire $0\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 - attribute \src "libresoc.v:21950.3-21951.63" + attribute \src "libresoc.v:22074.3-22075.63" wire $0\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 - attribute \src "libresoc.v:21964.3-21965.69" + attribute \src "libresoc.v:22088.3-22089.69" wire $0\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 - attribute \src "libresoc.v:21960.3-21961.63" + attribute \src "libresoc.v:22084.3-22085.63" wire $0\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:22000.3-22001.40" + attribute \src "libresoc.v:22124.3-22125.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:22390.3-22398.6" + attribute \src "libresoc.v:22514.3-22522.6" wire $0\alu_l_r_alu$next[0:0]$784 - attribute \src "libresoc.v:21910.3-21911.39" + attribute \src "libresoc.v:22034.3-22035.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22381.3-22389.6" + attribute \src "libresoc.v:22505.3-22513.6" wire $0\alui_l_r_alui$next[0:0]$781 - attribute \src "libresoc.v:21912.3-21913.43" + attribute \src "libresoc.v:22036.3-22037.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22231.3-22252.6" + attribute \src "libresoc.v:22355.3-22376.6" wire width 64 $0\data_r0__o$next[63:0]$729 - attribute \src "libresoc.v:21938.3-21939.37" + attribute \src "libresoc.v:22062.3-22063.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:22231.3-22252.6" + attribute \src "libresoc.v:22355.3-22376.6" wire $0\data_r0__o_ok$next[0:0]$730 - attribute \src "libresoc.v:21940.3-21941.43" + attribute \src "libresoc.v:22064.3-22065.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22253.3-22274.6" + attribute \src "libresoc.v:22377.3-22398.6" wire width 4 $0\data_r1__cr_a$next[3:0]$737 - attribute \src "libresoc.v:21934.3-21935.43" + attribute \src "libresoc.v:22058.3-22059.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22253.3-22274.6" + attribute \src "libresoc.v:22377.3-22398.6" wire $0\data_r1__cr_a_ok$next[0:0]$738 - attribute \src "libresoc.v:21936.3-21937.49" + attribute \src "libresoc.v:22060.3-22061.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22275.3-22296.6" + attribute \src "libresoc.v:22399.3-22420.6" wire width 2 $0\data_r2__xer_ca$next[1:0]$745 - attribute \src "libresoc.v:21930.3-21931.47" + attribute \src "libresoc.v:22054.3-22055.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22275.3-22296.6" + attribute \src "libresoc.v:22399.3-22420.6" wire $0\data_r2__xer_ca_ok$next[0:0]$746 - attribute \src "libresoc.v:21932.3-21933.53" + attribute \src "libresoc.v:22056.3-22057.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22297.3-22318.6" + attribute \src "libresoc.v:22421.3-22442.6" wire width 2 $0\data_r3__xer_ov$next[1:0]$753 - attribute \src "libresoc.v:21926.3-21927.47" + attribute \src "libresoc.v:22050.3-22051.47" wire width 2 $0\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22297.3-22318.6" + attribute \src "libresoc.v:22421.3-22442.6" wire $0\data_r3__xer_ov_ok$next[0:0]$754 - attribute \src "libresoc.v:21928.3-21929.53" + attribute \src "libresoc.v:22052.3-22053.53" wire $0\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22319.3-22340.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $0\data_r4__xer_so$next[0:0]$761 - attribute \src "libresoc.v:21922.3-21923.47" + attribute \src "libresoc.v:22046.3-22047.47" wire $0\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22319.3-22340.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $0\data_r4__xer_so_ok$next[0:0]$762 - attribute \src "libresoc.v:21924.3-21925.53" + attribute \src "libresoc.v:22048.3-22049.53" wire $0\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22399.3-22408.6" + attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:22409.3-22418.6" + attribute \src "libresoc.v:22533.3-22542.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:22419.3-22428.6" + attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:22429.3-22438.6" + attribute \src "libresoc.v:22553.3-22562.6" wire width 2 $0\dest4_o[1:0] - attribute \src "libresoc.v:22439.3-22448.6" + attribute \src "libresoc.v:22563.3-22572.6" wire $0\dest5_o[0:0] - attribute \src "libresoc.v:21165.7-21165.20" + attribute \src "libresoc.v:21285.7-21285.20" wire $0\initial[0:0] - attribute \src "libresoc.v:22147.3-22155.6" + attribute \src "libresoc.v:22271.3-22279.6" wire $0\opc_l_r_opc$next[0:0]$671 - attribute \src "libresoc.v:21986.3-21987.39" + attribute \src "libresoc.v:22110.3-22111.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:22138.3-22146.6" + attribute \src "libresoc.v:22262.3-22270.6" wire $0\opc_l_s_opc$next[0:0]$668 - attribute \src "libresoc.v:21988.3-21989.39" + attribute \src "libresoc.v:22112.3-22113.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22449.3-22457.6" + attribute \src "libresoc.v:22573.3-22581.6" wire width 5 $0\prev_wr_go$next[4:0]$792 - attribute \src "libresoc.v:21998.3-21999.37" + attribute \src "libresoc.v:22122.3-22123.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:22092.3-22101.6" + attribute \src "libresoc.v:22216.3-22225.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:22183.3-22191.6" + attribute \src "libresoc.v:22307.3-22315.6" wire width 5 $0\req_l_r_req$next[4:0]$683 - attribute \src "libresoc.v:21978.3-21979.39" + attribute \src "libresoc.v:22102.3-22103.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:22174.3-22182.6" + attribute \src "libresoc.v:22298.3-22306.6" wire width 5 $0\req_l_s_req$next[4:0]$680 - attribute \src "libresoc.v:21980.3-21981.39" + attribute \src "libresoc.v:22104.3-22105.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:22111.3-22119.6" + attribute \src "libresoc.v:22235.3-22243.6" wire $0\rok_l_r_rdok$next[0:0]$659 - attribute \src "libresoc.v:21994.3-21995.41" + attribute \src "libresoc.v:22118.3-22119.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:22102.3-22110.6" + attribute \src "libresoc.v:22226.3-22234.6" wire $0\rok_l_s_rdok$next[0:0]$656 - attribute \src "libresoc.v:21996.3-21997.41" + attribute \src "libresoc.v:22120.3-22121.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:22129.3-22137.6" + attribute \src "libresoc.v:22253.3-22261.6" wire $0\rst_l_r_rst$next[0:0]$665 - attribute \src "libresoc.v:21990.3-21991.39" + attribute \src "libresoc.v:22114.3-22115.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:22120.3-22128.6" + attribute \src "libresoc.v:22244.3-22252.6" wire $0\rst_l_s_rst$next[0:0]$662 - attribute \src "libresoc.v:21992.3-21993.39" + attribute \src "libresoc.v:22116.3-22117.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:22165.3-22173.6" + attribute \src "libresoc.v:22289.3-22297.6" wire width 4 $0\src_l_r_src$next[3:0]$677 - attribute \src "libresoc.v:21982.3-21983.39" + attribute \src "libresoc.v:22106.3-22107.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:22156.3-22164.6" + attribute \src "libresoc.v:22280.3-22288.6" wire width 4 $0\src_l_s_src$next[3:0]$674 - attribute \src "libresoc.v:21984.3-21985.39" + attribute \src "libresoc.v:22108.3-22109.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:22341.3-22350.6" + attribute \src "libresoc.v:22465.3-22474.6" wire width 64 $0\src_r0$next[63:0]$769 - attribute \src "libresoc.v:21920.3-21921.29" + attribute \src "libresoc.v:22044.3-22045.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:22351.3-22360.6" + attribute \src "libresoc.v:22475.3-22484.6" wire width 64 $0\src_r1$next[63:0]$772 - attribute \src "libresoc.v:21918.3-21919.29" + attribute \src "libresoc.v:22042.3-22043.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:22361.3-22370.6" + attribute \src "libresoc.v:22485.3-22494.6" wire $0\src_r2$next[0:0]$775 - attribute \src "libresoc.v:21916.3-21917.29" + attribute \src "libresoc.v:22040.3-22041.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:22371.3-22380.6" + attribute \src "libresoc.v:22495.3-22504.6" wire width 2 $0\src_r3$next[1:0]$778 - attribute \src "libresoc.v:21914.3-21915.29" + attribute \src "libresoc.v:22038.3-22039.29" wire width 2 $0\src_r3[1:0] - attribute \src "libresoc.v:21303.7-21303.24" + attribute \src "libresoc.v:21423.7-21423.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 - attribute \src "libresoc.v:21311.13-21311.45" + attribute \src "libresoc.v:21431.13-21431.45" wire width 4 $1\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22192.3-22230.6" - wire width 13 $1\alu_alu0_alu_op__fn_unit$next[12:0]$705 - attribute \src "libresoc.v:21329.14-21329.49" - wire width 13 $1\alu_alu0_alu_op__fn_unit[12:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" + wire width 14 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 + attribute \src "libresoc.v:21450.14-21450.49" + wire width 14 $1\alu_alu0_alu_op__fn_unit[13:0] + attribute \src "libresoc.v:22316.3-22354.6" wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 - attribute \src "libresoc.v:21333.14-21333.68" + attribute \src "libresoc.v:21454.14-21454.68" wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 - attribute \src "libresoc.v:21337.7-21337.43" + attribute \src "libresoc.v:21458.7-21458.43" wire $1\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 - attribute \src "libresoc.v:21345.13-21345.48" + attribute \src "libresoc.v:21466.13-21466.48" wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 - attribute \src "libresoc.v:21349.14-21349.43" + attribute \src "libresoc.v:21470.14-21470.43" wire width 32 $1\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 - attribute \src "libresoc.v:21427.13-21427.47" + attribute \src "libresoc.v:21549.13-21549.47" wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 - attribute \src "libresoc.v:21431.7-21431.40" + attribute \src "libresoc.v:21553.7-21553.40" wire $1\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 - attribute \src "libresoc.v:21435.7-21435.41" + attribute \src "libresoc.v:21557.7-21557.41" wire $1\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 - attribute \src "libresoc.v:21439.7-21439.39" + attribute \src "libresoc.v:21561.7-21561.39" wire $1\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 - attribute \src "libresoc.v:21443.7-21443.40" + attribute \src "libresoc.v:21565.7-21565.40" wire $1\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 - attribute \src "libresoc.v:21447.7-21447.37" + attribute \src "libresoc.v:21569.7-21569.37" wire $1\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 - attribute \src "libresoc.v:21451.7-21451.37" + attribute \src "libresoc.v:21573.7-21573.37" wire $1\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 - attribute \src "libresoc.v:21455.7-21455.43" + attribute \src "libresoc.v:21577.7-21577.43" wire $1\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 - attribute \src "libresoc.v:21459.7-21459.37" + attribute \src "libresoc.v:21581.7-21581.37" wire $1\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 - attribute \src "libresoc.v:21463.7-21463.37" + attribute \src "libresoc.v:21585.7-21585.37" wire $1\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 - attribute \src "libresoc.v:21467.7-21467.40" + attribute \src "libresoc.v:21589.7-21589.40" wire $1\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 - attribute \src "libresoc.v:21471.7-21471.37" + attribute \src "libresoc.v:21593.7-21593.37" wire $1\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21503.7-21503.26" + attribute \src "libresoc.v:21625.7-21625.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:22390.3-22398.6" + attribute \src "libresoc.v:22514.3-22522.6" wire $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:21511.7-21511.25" + attribute \src "libresoc.v:21633.7-21633.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22381.3-22389.6" + attribute \src "libresoc.v:22505.3-22513.6" wire $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:21523.7-21523.27" + attribute \src "libresoc.v:21645.7-21645.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22231.3-22252.6" + attribute \src "libresoc.v:22355.3-22376.6" wire width 64 $1\data_r0__o$next[63:0]$731 - attribute \src "libresoc.v:21557.14-21557.47" + attribute \src "libresoc.v:21679.14-21679.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:22231.3-22252.6" + attribute \src "libresoc.v:22355.3-22376.6" wire $1\data_r0__o_ok$next[0:0]$732 - attribute \src "libresoc.v:21561.7-21561.27" + attribute \src "libresoc.v:21683.7-21683.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22253.3-22274.6" + attribute \src "libresoc.v:22377.3-22398.6" wire width 4 $1\data_r1__cr_a$next[3:0]$739 - attribute \src "libresoc.v:21565.13-21565.33" + attribute \src "libresoc.v:21687.13-21687.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22253.3-22274.6" + attribute \src "libresoc.v:22377.3-22398.6" wire $1\data_r1__cr_a_ok$next[0:0]$740 - attribute \src "libresoc.v:21569.7-21569.30" + attribute \src "libresoc.v:21691.7-21691.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22275.3-22296.6" + attribute \src "libresoc.v:22399.3-22420.6" wire width 2 $1\data_r2__xer_ca$next[1:0]$747 - attribute \src "libresoc.v:21573.13-21573.35" + attribute \src "libresoc.v:21695.13-21695.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22275.3-22296.6" + attribute \src "libresoc.v:22399.3-22420.6" wire $1\data_r2__xer_ca_ok$next[0:0]$748 - attribute \src "libresoc.v:21577.7-21577.32" + attribute \src "libresoc.v:21699.7-21699.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22297.3-22318.6" + attribute \src "libresoc.v:22421.3-22442.6" wire width 2 $1\data_r3__xer_ov$next[1:0]$755 - attribute \src "libresoc.v:21581.13-21581.35" + attribute \src "libresoc.v:21703.13-21703.35" wire width 2 $1\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22297.3-22318.6" + attribute \src "libresoc.v:22421.3-22442.6" wire $1\data_r3__xer_ov_ok$next[0:0]$756 - attribute \src "libresoc.v:21585.7-21585.32" + attribute \src "libresoc.v:21707.7-21707.32" wire $1\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22319.3-22340.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $1\data_r4__xer_so$next[0:0]$763 - attribute \src "libresoc.v:21589.7-21589.29" + attribute \src "libresoc.v:21711.7-21711.29" wire $1\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22319.3-22340.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $1\data_r4__xer_so_ok$next[0:0]$764 - attribute \src "libresoc.v:21593.7-21593.32" + attribute \src "libresoc.v:21715.7-21715.32" wire $1\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22399.3-22408.6" + attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:22409.3-22418.6" + attribute \src "libresoc.v:22533.3-22542.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:22419.3-22428.6" + attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:22429.3-22438.6" + attribute \src "libresoc.v:22553.3-22562.6" wire width 2 $1\dest4_o[1:0] - attribute \src "libresoc.v:22439.3-22448.6" + attribute \src "libresoc.v:22563.3-22572.6" wire $1\dest5_o[0:0] - attribute \src "libresoc.v:22147.3-22155.6" + attribute \src "libresoc.v:22271.3-22279.6" wire $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:21616.7-21616.25" + attribute \src "libresoc.v:21738.7-21738.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:22138.3-22146.6" + attribute \src "libresoc.v:22262.3-22270.6" wire $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:21620.7-21620.25" + attribute \src "libresoc.v:21742.7-21742.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22449.3-22457.6" + attribute \src "libresoc.v:22573.3-22581.6" wire width 5 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:21752.13-21752.31" + attribute \src "libresoc.v:21876.13-21876.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:22092.3-22101.6" + attribute \src "libresoc.v:22216.3-22225.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:22183.3-22191.6" + attribute \src "libresoc.v:22307.3-22315.6" wire width 5 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:21760.13-21760.32" + attribute \src "libresoc.v:21884.13-21884.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:22174.3-22182.6" + attribute \src "libresoc.v:22298.3-22306.6" wire width 5 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:21764.13-21764.32" + attribute \src "libresoc.v:21888.13-21888.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:22111.3-22119.6" + attribute \src "libresoc.v:22235.3-22243.6" wire $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:21776.7-21776.26" + attribute \src "libresoc.v:21900.7-21900.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:22102.3-22110.6" + attribute \src "libresoc.v:22226.3-22234.6" wire $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:21780.7-21780.26" + attribute \src "libresoc.v:21904.7-21904.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:22129.3-22137.6" + attribute \src "libresoc.v:22253.3-22261.6" wire $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:21784.7-21784.25" + attribute \src "libresoc.v:21908.7-21908.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:22120.3-22128.6" + attribute \src "libresoc.v:22244.3-22252.6" wire $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:21788.7-21788.25" + attribute \src "libresoc.v:21912.7-21912.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:22165.3-22173.6" + attribute \src "libresoc.v:22289.3-22297.6" wire width 4 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:21804.13-21804.31" + attribute \src "libresoc.v:21928.13-21928.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:22156.3-22164.6" + attribute \src "libresoc.v:22280.3-22288.6" wire width 4 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:21808.13-21808.31" + attribute \src "libresoc.v:21932.13-21932.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:22341.3-22350.6" + attribute \src "libresoc.v:22465.3-22474.6" wire width 64 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:21816.14-21816.43" + attribute \src "libresoc.v:21940.14-21940.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:22351.3-22360.6" + attribute \src "libresoc.v:22475.3-22484.6" wire width 64 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:21820.14-21820.43" + attribute \src "libresoc.v:21944.14-21944.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:22361.3-22370.6" + attribute \src "libresoc.v:22485.3-22494.6" wire $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:21824.7-21824.20" + attribute \src "libresoc.v:21948.7-21948.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:22371.3-22380.6" + attribute \src "libresoc.v:22495.3-22504.6" wire width 2 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:21828.13-21828.26" + attribute \src "libresoc.v:21952.13-21952.26" wire width 2 $1\src_r3[1:0] - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 - attribute \src "libresoc.v:22192.3-22230.6" + attribute \src "libresoc.v:22316.3-22354.6" wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22231.3-22252.6" + attribute \src "libresoc.v:22355.3-22376.6" wire width 64 $2\data_r0__o$next[63:0]$733 - attribute \src "libresoc.v:22231.3-22252.6" + attribute \src "libresoc.v:22355.3-22376.6" wire $2\data_r0__o_ok$next[0:0]$734 - attribute \src "libresoc.v:22253.3-22274.6" + attribute \src "libresoc.v:22377.3-22398.6" wire width 4 $2\data_r1__cr_a$next[3:0]$741 - attribute \src "libresoc.v:22253.3-22274.6" + attribute \src "libresoc.v:22377.3-22398.6" wire $2\data_r1__cr_a_ok$next[0:0]$742 - attribute \src "libresoc.v:22275.3-22296.6" + attribute \src "libresoc.v:22399.3-22420.6" wire width 2 $2\data_r2__xer_ca$next[1:0]$749 - attribute \src "libresoc.v:22275.3-22296.6" + attribute \src "libresoc.v:22399.3-22420.6" wire $2\data_r2__xer_ca_ok$next[0:0]$750 - attribute \src "libresoc.v:22297.3-22318.6" + attribute \src "libresoc.v:22421.3-22442.6" wire width 2 $2\data_r3__xer_ov$next[1:0]$757 - attribute \src "libresoc.v:22297.3-22318.6" + attribute \src "libresoc.v:22421.3-22442.6" wire $2\data_r3__xer_ov_ok$next[0:0]$758 - attribute \src "libresoc.v:22319.3-22340.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $2\data_r4__xer_so$next[0:0]$765 - attribute \src "libresoc.v:22319.3-22340.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $2\data_r4__xer_so_ok$next[0:0]$766 - attribute \src "libresoc.v:22231.3-22252.6" + attribute \src "libresoc.v:22355.3-22376.6" wire $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22253.3-22274.6" + attribute \src "libresoc.v:22377.3-22398.6" wire $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22275.3-22296.6" + attribute \src "libresoc.v:22399.3-22420.6" wire $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22297.3-22318.6" + attribute \src "libresoc.v:22421.3-22442.6" wire $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22319.3-22340.6" + attribute \src "libresoc.v:22443.3-22464.6" wire $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:21844.18-21844.134" - wire $and$libresoc.v:21844$541_Y - attribute \src "libresoc.v:21845.19-21845.133" - wire $and$libresoc.v:21845$542_Y - attribute \src "libresoc.v:21846.19-21846.161" - wire width 4 $and$libresoc.v:21846$543_Y - attribute \src "libresoc.v:21849.19-21849.134" - wire width 4 $and$libresoc.v:21849$546_Y - attribute \src "libresoc.v:21851.19-21851.115" - wire width 4 $and$libresoc.v:21851$548_Y - attribute \src "libresoc.v:21852.19-21852.125" - wire $and$libresoc.v:21852$549_Y - attribute \src "libresoc.v:21853.19-21853.125" - wire $and$libresoc.v:21853$550_Y - attribute \src "libresoc.v:21854.18-21854.110" - wire $and$libresoc.v:21854$551_Y - attribute \src "libresoc.v:21855.19-21855.125" - wire $and$libresoc.v:21855$552_Y - attribute \src "libresoc.v:21856.19-21856.125" - wire $and$libresoc.v:21856$553_Y - attribute \src "libresoc.v:21857.19-21857.125" - wire $and$libresoc.v:21857$554_Y - attribute \src "libresoc.v:21858.19-21858.157" - wire width 5 $and$libresoc.v:21858$555_Y - attribute \src "libresoc.v:21859.19-21859.121" - wire width 5 $and$libresoc.v:21859$556_Y - attribute \src "libresoc.v:21860.19-21860.127" - wire $and$libresoc.v:21860$557_Y - attribute \src "libresoc.v:21861.19-21861.127" - wire $and$libresoc.v:21861$558_Y - attribute \src "libresoc.v:21862.19-21862.127" - wire $and$libresoc.v:21862$559_Y - attribute \src "libresoc.v:21863.19-21863.127" - wire $and$libresoc.v:21863$560_Y - attribute \src "libresoc.v:21864.19-21864.127" - wire $and$libresoc.v:21864$561_Y - attribute \src "libresoc.v:21866.18-21866.98" - wire $and$libresoc.v:21866$563_Y - attribute \src "libresoc.v:21868.18-21868.100" - wire $and$libresoc.v:21868$565_Y - attribute \src "libresoc.v:21869.18-21869.171" - wire width 5 $and$libresoc.v:21869$566_Y - attribute \src "libresoc.v:21871.18-21871.119" - wire width 5 $and$libresoc.v:21871$568_Y - attribute \src "libresoc.v:21874.18-21874.116" - wire $and$libresoc.v:21874$571_Y - attribute \src "libresoc.v:21878.17-21878.123" - wire $and$libresoc.v:21878$575_Y - attribute \src "libresoc.v:21880.18-21880.113" - wire $and$libresoc.v:21880$577_Y - attribute \src "libresoc.v:21881.18-21881.125" - wire width 5 $and$libresoc.v:21881$578_Y - attribute \src "libresoc.v:21883.18-21883.112" - wire $and$libresoc.v:21883$580_Y - attribute \src "libresoc.v:21885.18-21885.126" - wire $and$libresoc.v:21885$582_Y - attribute \src "libresoc.v:21886.18-21886.126" - wire $and$libresoc.v:21886$583_Y - attribute \src "libresoc.v:21887.18-21887.117" - wire $and$libresoc.v:21887$584_Y - attribute \src "libresoc.v:21892.18-21892.130" - wire $and$libresoc.v:21892$589_Y - attribute \src "libresoc.v:21893.18-21893.124" - wire width 5 $and$libresoc.v:21893$590_Y - attribute \src "libresoc.v:21896.18-21896.116" - wire $and$libresoc.v:21896$593_Y - attribute \src "libresoc.v:21897.18-21897.119" - wire $and$libresoc.v:21897$594_Y - attribute \src "libresoc.v:21898.18-21898.121" - wire $and$libresoc.v:21898$595_Y - attribute \src "libresoc.v:21899.18-21899.121" - wire $and$libresoc.v:21899$596_Y - attribute \src "libresoc.v:21900.18-21900.121" - wire $and$libresoc.v:21900$597_Y - attribute \src "libresoc.v:21882.18-21882.113" - wire $eq$libresoc.v:21882$579_Y - attribute \src "libresoc.v:21884.18-21884.119" - wire $eq$libresoc.v:21884$581_Y - attribute \src "libresoc.v:21847.19-21847.126" - wire $not$libresoc.v:21847$544_Y - attribute \src "libresoc.v:21848.19-21848.132" - wire $not$libresoc.v:21848$545_Y - attribute \src "libresoc.v:21850.19-21850.115" - wire width 4 $not$libresoc.v:21850$547_Y - attribute \src "libresoc.v:21865.18-21865.97" - wire $not$libresoc.v:21865$562_Y - attribute \src "libresoc.v:21867.18-21867.99" - wire $not$libresoc.v:21867$564_Y - attribute \src "libresoc.v:21870.18-21870.113" - wire width 5 $not$libresoc.v:21870$567_Y - attribute \src "libresoc.v:21873.18-21873.106" - wire $not$libresoc.v:21873$570_Y - attribute \src "libresoc.v:21879.18-21879.120" - wire $not$libresoc.v:21879$576_Y - attribute \src "libresoc.v:21894.17-21894.113" - wire width 4 $not$libresoc.v:21894$591_Y - attribute \src "libresoc.v:21877.18-21877.112" - wire $or$libresoc.v:21877$574_Y - attribute \src "libresoc.v:21888.18-21888.122" - wire $or$libresoc.v:21888$585_Y - attribute \src "libresoc.v:21889.18-21889.124" - wire $or$libresoc.v:21889$586_Y - attribute \src "libresoc.v:21890.18-21890.181" - wire width 5 $or$libresoc.v:21890$587_Y - attribute \src "libresoc.v:21891.18-21891.168" - wire width 4 $or$libresoc.v:21891$588_Y - attribute \src "libresoc.v:21895.18-21895.120" - wire width 5 $or$libresoc.v:21895$592_Y - attribute \src "libresoc.v:21904.17-21904.117" - wire width 4 $or$libresoc.v:21904$601_Y - attribute \src "libresoc.v:21843.17-21843.104" - wire $reduce_and$libresoc.v:21843$540_Y - attribute \src "libresoc.v:21872.18-21872.106" - wire $reduce_or$libresoc.v:21872$569_Y - attribute \src "libresoc.v:21875.18-21875.113" - wire $reduce_or$libresoc.v:21875$572_Y - attribute \src "libresoc.v:21876.18-21876.112" - wire $reduce_or$libresoc.v:21876$573_Y - attribute \src "libresoc.v:21901.18-21901.154" - wire $ternary$libresoc.v:21901$598_Y - attribute \src "libresoc.v:21902.18-21902.155" - wire width 64 $ternary$libresoc.v:21902$599_Y - attribute \src "libresoc.v:21903.18-21903.160" - wire $ternary$libresoc.v:21903$600_Y - attribute \src "libresoc.v:21905.18-21905.172" - wire width 64 $ternary$libresoc.v:21905$602_Y - attribute \src "libresoc.v:21906.18-21906.115" - wire width 64 $ternary$libresoc.v:21906$603_Y - attribute \src "libresoc.v:21907.18-21907.125" - wire width 64 $ternary$libresoc.v:21907$604_Y - attribute \src "libresoc.v:21908.18-21908.118" - wire $ternary$libresoc.v:21908$605_Y - attribute \src "libresoc.v:21909.18-21909.118" - wire width 2 $ternary$libresoc.v:21909$606_Y + attribute \src "libresoc.v:21968.18-21968.134" + wire $and$libresoc.v:21968$541_Y + attribute \src "libresoc.v:21969.19-21969.133" + wire $and$libresoc.v:21969$542_Y + attribute \src "libresoc.v:21970.19-21970.161" + wire width 4 $and$libresoc.v:21970$543_Y + attribute \src "libresoc.v:21973.19-21973.134" + wire width 4 $and$libresoc.v:21973$546_Y + attribute \src "libresoc.v:21975.19-21975.115" + wire width 4 $and$libresoc.v:21975$548_Y + attribute \src "libresoc.v:21976.19-21976.125" + wire $and$libresoc.v:21976$549_Y + attribute \src "libresoc.v:21977.19-21977.125" + wire $and$libresoc.v:21977$550_Y + attribute \src "libresoc.v:21978.18-21978.110" + wire $and$libresoc.v:21978$551_Y + attribute \src "libresoc.v:21979.19-21979.125" + wire $and$libresoc.v:21979$552_Y + attribute \src "libresoc.v:21980.19-21980.125" + wire $and$libresoc.v:21980$553_Y + attribute \src "libresoc.v:21981.19-21981.125" + wire $and$libresoc.v:21981$554_Y + attribute \src "libresoc.v:21982.19-21982.157" + wire width 5 $and$libresoc.v:21982$555_Y + attribute \src "libresoc.v:21983.19-21983.121" + wire width 5 $and$libresoc.v:21983$556_Y + attribute \src "libresoc.v:21984.19-21984.127" + wire $and$libresoc.v:21984$557_Y + attribute \src "libresoc.v:21985.19-21985.127" + wire $and$libresoc.v:21985$558_Y + attribute \src "libresoc.v:21986.19-21986.127" + wire $and$libresoc.v:21986$559_Y + attribute \src "libresoc.v:21987.19-21987.127" + wire $and$libresoc.v:21987$560_Y + attribute \src "libresoc.v:21988.19-21988.127" + wire $and$libresoc.v:21988$561_Y + attribute \src "libresoc.v:21990.18-21990.98" + wire $and$libresoc.v:21990$563_Y + attribute \src "libresoc.v:21992.18-21992.100" + wire $and$libresoc.v:21992$565_Y + attribute \src "libresoc.v:21993.18-21993.171" + wire width 5 $and$libresoc.v:21993$566_Y + attribute \src "libresoc.v:21995.18-21995.119" + wire width 5 $and$libresoc.v:21995$568_Y + attribute \src "libresoc.v:21998.18-21998.116" + wire $and$libresoc.v:21998$571_Y + attribute \src "libresoc.v:22002.17-22002.123" + wire $and$libresoc.v:22002$575_Y + attribute \src "libresoc.v:22004.18-22004.113" + wire $and$libresoc.v:22004$577_Y + attribute \src "libresoc.v:22005.18-22005.125" + wire width 5 $and$libresoc.v:22005$578_Y + attribute \src "libresoc.v:22007.18-22007.112" + wire $and$libresoc.v:22007$580_Y + attribute \src "libresoc.v:22009.18-22009.126" + wire $and$libresoc.v:22009$582_Y + attribute \src "libresoc.v:22010.18-22010.126" + wire $and$libresoc.v:22010$583_Y + attribute \src "libresoc.v:22011.18-22011.117" + wire $and$libresoc.v:22011$584_Y + attribute \src "libresoc.v:22016.18-22016.130" + wire $and$libresoc.v:22016$589_Y + attribute \src "libresoc.v:22017.18-22017.124" + wire width 5 $and$libresoc.v:22017$590_Y + attribute \src "libresoc.v:22020.18-22020.116" + wire $and$libresoc.v:22020$593_Y + attribute \src "libresoc.v:22021.18-22021.119" + wire $and$libresoc.v:22021$594_Y + attribute \src "libresoc.v:22022.18-22022.121" + wire $and$libresoc.v:22022$595_Y + attribute \src "libresoc.v:22023.18-22023.121" + wire $and$libresoc.v:22023$596_Y + attribute \src "libresoc.v:22024.18-22024.121" + wire $and$libresoc.v:22024$597_Y + attribute \src "libresoc.v:22006.18-22006.113" + wire $eq$libresoc.v:22006$579_Y + attribute \src "libresoc.v:22008.18-22008.119" + wire $eq$libresoc.v:22008$581_Y + attribute \src "libresoc.v:21971.19-21971.126" + wire $not$libresoc.v:21971$544_Y + attribute \src "libresoc.v:21972.19-21972.132" + wire $not$libresoc.v:21972$545_Y + attribute \src "libresoc.v:21974.19-21974.115" + wire width 4 $not$libresoc.v:21974$547_Y + attribute \src "libresoc.v:21989.18-21989.97" + wire $not$libresoc.v:21989$562_Y + attribute \src "libresoc.v:21991.18-21991.99" + wire $not$libresoc.v:21991$564_Y + attribute \src "libresoc.v:21994.18-21994.113" + wire width 5 $not$libresoc.v:21994$567_Y + attribute \src "libresoc.v:21997.18-21997.106" + wire $not$libresoc.v:21997$570_Y + attribute \src "libresoc.v:22003.18-22003.120" + wire $not$libresoc.v:22003$576_Y + attribute \src "libresoc.v:22018.17-22018.113" + wire width 4 $not$libresoc.v:22018$591_Y + attribute \src "libresoc.v:22001.18-22001.112" + wire $or$libresoc.v:22001$574_Y + attribute \src "libresoc.v:22012.18-22012.122" + wire $or$libresoc.v:22012$585_Y + attribute \src "libresoc.v:22013.18-22013.124" + wire $or$libresoc.v:22013$586_Y + attribute \src "libresoc.v:22014.18-22014.181" + wire width 5 $or$libresoc.v:22014$587_Y + attribute \src "libresoc.v:22015.18-22015.168" + wire width 4 $or$libresoc.v:22015$588_Y + attribute \src "libresoc.v:22019.18-22019.120" + wire width 5 $or$libresoc.v:22019$592_Y + attribute \src "libresoc.v:22028.17-22028.117" + wire width 4 $or$libresoc.v:22028$601_Y + attribute \src "libresoc.v:21967.17-21967.104" + wire $reduce_and$libresoc.v:21967$540_Y + attribute \src "libresoc.v:21996.18-21996.106" + wire $reduce_or$libresoc.v:21996$569_Y + attribute \src "libresoc.v:21999.18-21999.113" + wire $reduce_or$libresoc.v:21999$572_Y + attribute \src "libresoc.v:22000.18-22000.112" + wire $reduce_or$libresoc.v:22000$573_Y + attribute \src "libresoc.v:22025.18-22025.154" + wire $ternary$libresoc.v:22025$598_Y + attribute \src "libresoc.v:22026.18-22026.155" + wire width 64 $ternary$libresoc.v:22026$599_Y + attribute \src "libresoc.v:22027.18-22027.160" + wire $ternary$libresoc.v:22027$600_Y + attribute \src "libresoc.v:22029.18-22029.172" + wire width 64 $ternary$libresoc.v:22029$602_Y + attribute \src "libresoc.v:22030.18-22030.115" + wire width 64 $ternary$libresoc.v:22030$603_Y + attribute \src "libresoc.v:22031.18-22031.125" + wire width 64 $ternary$libresoc.v:22031$604_Y + attribute \src "libresoc.v:22032.18-22032.118" + wire $ternary$libresoc.v:22032$605_Y + attribute \src "libresoc.v:22033.18-22033.118" + wire width 2 $ternary$libresoc.v:22033$606_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -31838,23 +31958,24 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_alu0_alu_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_alu0_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_alu0_alu_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_alu0_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_alu0_alu_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_alu0_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -31949,6 +32070,7 @@ module \alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_alu0_alu_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -32051,9 +32173,9 @@ module \alu0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -32129,7 +32251,7 @@ module \alu0 wire width 2 output 38 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 40 \dest5_o - attribute \src "libresoc.v:21165.7-21165.15" + attribute \src "libresoc.v:21285.7-21285.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok @@ -32146,21 +32268,22 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_alu0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_alu0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -32247,6 +32370,7 @@ module \alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -32364,7 +32488,7 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 39 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:21844$541 + cell $and $and$libresoc.v:21968$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32372,10 +32496,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:21844$541_Y + connect \Y $and$libresoc.v:21968$541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:21845$542 + cell $and $and$libresoc.v:21969$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32383,10 +32507,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:21845$542_Y + connect \Y $and$libresoc.v:21969$542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21846$543 + cell $and $and$libresoc.v:21970$543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32394,10 +32518,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21846$543_Y + connect \Y $and$libresoc.v:21970$543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21849$546 + cell $and $and$libresoc.v:21973$546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32405,10 +32529,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$103 connect \B { 2'11 \$107 \$105 } - connect \Y $and$libresoc.v:21849$546_Y + connect \Y $and$libresoc.v:21973$546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21851$548 + cell $and $and$libresoc.v:21975$548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32416,10 +32540,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$109 connect \B \$111 - connect \Y $and$libresoc.v:21851$548_Y + connect \Y $and$libresoc.v:21975$548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21852$549 + cell $and $and$libresoc.v:21976$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32427,10 +32551,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21852$549_Y + connect \Y $and$libresoc.v:21976$549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21853$550 + cell $and $and$libresoc.v:21977$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32438,10 +32562,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21853$550_Y + connect \Y $and$libresoc.v:21977$550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:21854$551 + cell $and $and$libresoc.v:21978$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32449,10 +32573,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:21854$551_Y + connect \Y $and$libresoc.v:21978$551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21855$552 + cell $and $and$libresoc.v:21979$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32460,10 +32584,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21855$552_Y + connect \Y $and$libresoc.v:21979$552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21856$553 + cell $and $and$libresoc.v:21980$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32471,10 +32595,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21856$553_Y + connect \Y $and$libresoc.v:21980$553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21857$554 + cell $and $and$libresoc.v:21981$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32482,10 +32606,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21857$554_Y + connect \Y $and$libresoc.v:21981$554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21858$555 + cell $and $and$libresoc.v:21982$555 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32493,10 +32617,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$115 \$117 \$119 \$121 \$123 } - connect \Y $and$libresoc.v:21858$555_Y + connect \Y $and$libresoc.v:21982$555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21859$556 + cell $and $and$libresoc.v:21983$556 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32504,10 +32628,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \$125 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21859$556_Y + connect \Y $and$libresoc.v:21983$556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21860$557 + cell $and $and$libresoc.v:21984$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32515,10 +32639,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21860$557_Y + connect \Y $and$libresoc.v:21984$557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21861$558 + cell $and $and$libresoc.v:21985$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32526,10 +32650,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21861$558_Y + connect \Y $and$libresoc.v:21985$558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21862$559 + cell $and $and$libresoc.v:21986$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32537,10 +32661,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21862$559_Y + connect \Y $and$libresoc.v:21986$559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21863$560 + cell $and $and$libresoc.v:21987$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32548,10 +32672,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21863$560_Y + connect \Y $and$libresoc.v:21987$560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21864$561 + cell $and $and$libresoc.v:21988$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32559,10 +32683,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21864$561_Y + connect \Y $and$libresoc.v:21988$561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:21866$563 + cell $and $and$libresoc.v:21990$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32570,10 +32694,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:21866$563_Y + connect \Y $and$libresoc.v:21990$563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:21868$565 + cell $and $and$libresoc.v:21992$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32581,10 +32705,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:21868$565_Y + connect \Y $and$libresoc.v:21992$565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:21869$566 + cell $and $and$libresoc.v:21993$566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32592,10 +32716,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21869$566_Y + connect \Y $and$libresoc.v:21993$566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21871$568 + cell $and $and$libresoc.v:21995$568 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32603,10 +32727,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:21871$568_Y + connect \Y $and$libresoc.v:21995$568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21874$571 + cell $and $and$libresoc.v:21998$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32614,10 +32738,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:21874$571_Y + connect \Y $and$libresoc.v:21998$571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:21878$575 + cell $and $and$libresoc.v:22002$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32625,10 +32749,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:21878$575_Y + connect \Y $and$libresoc.v:22002$575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:21880$577 + cell $and $and$libresoc.v:22004$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32636,10 +32760,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:21880$577_Y + connect \Y $and$libresoc.v:22004$577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:21881$578 + cell $and $and$libresoc.v:22005$578 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32647,10 +32771,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21881$578_Y + connect \Y $and$libresoc.v:22005$578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:21883$580 + cell $and $and$libresoc.v:22007$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32658,10 +32782,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:21883$580_Y + connect \Y $and$libresoc.v:22007$580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21885$582 + cell $and $and$libresoc.v:22009$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32669,10 +32793,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_alu0_n_ready_i - connect \Y $and$libresoc.v:21885$582_Y + connect \Y $and$libresoc.v:22009$582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21886$583 + cell $and $and$libresoc.v:22010$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32680,10 +32804,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_alu0_n_valid_o - connect \Y $and$libresoc.v:21886$583_Y + connect \Y $and$libresoc.v:22010$583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21887$584 + cell $and $and$libresoc.v:22011$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32691,10 +32815,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:21887$584_Y + connect \Y $and$libresoc.v:22011$584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:21892$589 + cell $and $and$libresoc.v:22016$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32702,10 +32826,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:21892$589_Y + connect \Y $and$libresoc.v:22016$589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:21893$590 + cell $and $and$libresoc.v:22017$590 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32713,10 +32837,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21893$590_Y + connect \Y $and$libresoc.v:22017$590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21896$593 + cell $and $and$libresoc.v:22020$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32724,10 +32848,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21896$593_Y + connect \Y $and$libresoc.v:22020$593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21897$594 + cell $and $and$libresoc.v:22021$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32735,10 +32859,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21897$594_Y + connect \Y $and$libresoc.v:22021$594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21898$595 + cell $and $and$libresoc.v:22022$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32746,10 +32870,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21898$595_Y + connect \Y $and$libresoc.v:22022$595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21899$596 + cell $and $and$libresoc.v:22023$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32757,10 +32881,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21899$596_Y + connect \Y $and$libresoc.v:22023$596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21900$597 + cell $and $and$libresoc.v:22024$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32768,10 +32892,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21900$597_Y + connect \Y $and$libresoc.v:22024$597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:21882$579 + cell $eq $eq$libresoc.v:22006$579 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32779,10 +32903,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:21882$579_Y + connect \Y $eq$libresoc.v:22006$579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:21884$581 + cell $eq $eq$libresoc.v:22008$581 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32790,82 +32914,82 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:21884$581_Y + connect \Y $eq$libresoc.v:22008$581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21847$544 + cell $not $not$libresoc.v:21971$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__zero_a - connect \Y $not$libresoc.v:21847$544_Y + connect \Y $not$libresoc.v:21971$544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21848$545 + cell $not $not$libresoc.v:21972$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__imm_data__ok - connect \Y $not$libresoc.v:21848$545_Y + connect \Y $not$libresoc.v:21972$545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:21850$547 + cell $not $not$libresoc.v:21974$547 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:21850$547_Y + connect \Y $not$libresoc.v:21974$547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:21865$562 + cell $not $not$libresoc.v:21989$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:21865$562_Y + connect \Y $not$libresoc.v:21989$562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:21867$564 + cell $not $not$libresoc.v:21991$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:21867$564_Y + connect \Y $not$libresoc.v:21991$564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21870$567 + cell $not $not$libresoc.v:21994$567 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:21870$567_Y + connect \Y $not$libresoc.v:21994$567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21873$570 + cell $not $not$libresoc.v:21997$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:21873$570_Y + connect \Y $not$libresoc.v:21997$570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:21879$576 + cell $not $not$libresoc.v:22003$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_ready_i - connect \Y $not$libresoc.v:21879$576_Y + connect \Y $not$libresoc.v:22003$576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:21894$591 + cell $not $not$libresoc.v:22018$591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:21894$591_Y + connect \Y $not$libresoc.v:22018$591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:21877$574 + cell $or $or$libresoc.v:22001$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32873,10 +32997,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:21877$574_Y + connect \Y $or$libresoc.v:22001$574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:21888$585 + cell $or $or$libresoc.v:22012$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32884,10 +33008,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:21888$585_Y + connect \Y $or$libresoc.v:22012$585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:21889$586 + cell $or $or$libresoc.v:22013$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32895,10 +33019,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:21889$586_Y + connect \Y $or$libresoc.v:22013$586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:21890$587 + cell $or $or$libresoc.v:22014$587 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32906,10 +33030,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:21890$587_Y + connect \Y $or$libresoc.v:22014$587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:21891$588 + cell $or $or$libresoc.v:22015$588 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32917,10 +33041,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:21891$588_Y + connect \Y $or$libresoc.v:22015$588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:21895$592 + cell $or $or$libresoc.v:22019$592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32928,10 +33052,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:21895$592_Y + connect \Y $or$libresoc.v:22019$592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:21904$601 + cell $or $or$libresoc.v:22028$601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32939,106 +33063,106 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:21904$601_Y + connect \Y $or$libresoc.v:22028$601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:21843$540 + cell $reduce_and $reduce_and$libresoc.v:21967$540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:21843$540_Y + connect \Y $reduce_and$libresoc.v:21967$540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:21872$569 + cell $reduce_or $reduce_or$libresoc.v:21996$569 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:21872$569_Y + connect \Y $reduce_or$libresoc.v:21996$569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21875$572 + cell $reduce_or $reduce_or$libresoc.v:21999$572 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:21875$572_Y + connect \Y $reduce_or$libresoc.v:21999$572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21876$573 + cell $reduce_or $reduce_or$libresoc.v:22000$573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:21876$573_Y + connect \Y $reduce_or$libresoc.v:22000$573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:21901$598 + cell $mux $ternary$libresoc.v:22025$598 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:21901$598_Y + connect \Y $ternary$libresoc.v:22025$598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:21902$599 + cell $mux $ternary$libresoc.v:22026$599 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:21902$599_Y + connect \Y $ternary$libresoc.v:22026$599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:21903$600 + cell $mux $ternary$libresoc.v:22027$600 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:21903$600_Y + connect \Y $ternary$libresoc.v:22027$600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:21905$602 + cell $mux $ternary$libresoc.v:22029$602 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_alu0_alu_op__imm_data__data connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:21905$602_Y + connect \Y $ternary$libresoc.v:22029$602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:21906$603 + cell $mux $ternary$libresoc.v:22030$603 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:21906$603_Y + connect \Y $ternary$libresoc.v:22030$603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:21907$604 + cell $mux $ternary$libresoc.v:22031$604 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$88 connect \S \src_sel$85 - connect \Y $ternary$libresoc.v:21907$604_Y + connect \Y $ternary$libresoc.v:22031$604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:21908$605 + cell $mux $ternary$libresoc.v:22032$605 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:21908$605_Y + connect \Y $ternary$libresoc.v:22032$605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:21909$606 + cell $mux $ternary$libresoc.v:22033$606 parameter \WIDTH 2 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:21909$606_Y + connect \Y $ternary$libresoc.v:22033$606_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:22004.12-22043.4" + attribute \src "libresoc.v:22128.12-22167.4" cell \alu_alu0 \alu_alu0 connect \alu_op__data_len \alu_alu0_alu_op__data_len connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit @@ -33080,7 +33204,7 @@ module \alu0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:22044.9-22050.4" + attribute \src "libresoc.v:22168.9-22174.4" cell \alu_l \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33089,7 +33213,7 @@ module \alu0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:22051.10-22057.4" + attribute \src "libresoc.v:22175.10-22181.4" cell \alui_l \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33098,7 +33222,7 @@ module \alu0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:22058.9-22064.4" + attribute \src "libresoc.v:22182.9-22188.4" cell \opc_l \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33107,7 +33231,7 @@ module \alu0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:22065.9-22071.4" + attribute \src "libresoc.v:22189.9-22195.4" cell \req_l \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33116,7 +33240,7 @@ module \alu0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:22072.9-22078.4" + attribute \src "libresoc.v:22196.9-22202.4" cell \rok_l \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33125,7 +33249,7 @@ module \alu0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:22079.9-22084.4" + attribute \src "libresoc.v:22203.9-22208.4" cell \rst_l \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33133,7 +33257,7 @@ module \alu0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:22085.9-22091.4" + attribute \src "libresoc.v:22209.9-22215.4" cell \src_l \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33141,727 +33265,727 @@ module \alu0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:21165.7-21165.20" - process $proc$libresoc.v:21165$794 + attribute \src "libresoc.v:21285.7-21285.20" + process $proc$libresoc.v:21285$794 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21303.7-21303.24" - process $proc$libresoc.v:21303$795 + attribute \src "libresoc.v:21423.7-21423.24" + process $proc$libresoc.v:21423$795 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:21311.13-21311.45" - process $proc$libresoc.v:21311$796 + attribute \src "libresoc.v:21431.13-21431.45" + process $proc$libresoc.v:21431$796 assign { } { } assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:21329.14-21329.49" - process $proc$libresoc.v:21329$797 + attribute \src "libresoc.v:21450.14-21450.49" + process $proc$libresoc.v:21450$797 assign { } { } - assign $1\alu_alu0_alu_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_alu0_alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[12:0] + update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:21333.14-21333.68" - process $proc$libresoc.v:21333$798 + attribute \src "libresoc.v:21454.14-21454.68" + process $proc$libresoc.v:21454$798 assign { } { } assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:21337.7-21337.43" - process $proc$libresoc.v:21337$799 + attribute \src "libresoc.v:21458.7-21458.43" + process $proc$libresoc.v:21458$799 assign { } { } assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:21345.13-21345.48" - process $proc$libresoc.v:21345$800 + attribute \src "libresoc.v:21466.13-21466.48" + process $proc$libresoc.v:21466$800 assign { } { } assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:21349.14-21349.43" - process $proc$libresoc.v:21349$801 + attribute \src "libresoc.v:21470.14-21470.43" + process $proc$libresoc.v:21470$801 assign { } { } assign $1\alu_alu0_alu_op__insn[31:0] 0 sync always sync init update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:21427.13-21427.47" - process $proc$libresoc.v:21427$802 + attribute \src "libresoc.v:21549.13-21549.47" + process $proc$libresoc.v:21549$802 assign { } { } assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:21431.7-21431.40" - process $proc$libresoc.v:21431$803 + attribute \src "libresoc.v:21553.7-21553.40" + process $proc$libresoc.v:21553$803 assign { } { } assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:21435.7-21435.41" - process $proc$libresoc.v:21435$804 + attribute \src "libresoc.v:21557.7-21557.41" + process $proc$libresoc.v:21557$804 assign { } { } assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:21439.7-21439.39" - process $proc$libresoc.v:21439$805 + attribute \src "libresoc.v:21561.7-21561.39" + process $proc$libresoc.v:21561$805 assign { } { } assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:21443.7-21443.40" - process $proc$libresoc.v:21443$806 + attribute \src "libresoc.v:21565.7-21565.40" + process $proc$libresoc.v:21565$806 assign { } { } assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:21447.7-21447.37" - process $proc$libresoc.v:21447$807 + attribute \src "libresoc.v:21569.7-21569.37" + process $proc$libresoc.v:21569$807 assign { } { } assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:21451.7-21451.37" - process $proc$libresoc.v:21451$808 + attribute \src "libresoc.v:21573.7-21573.37" + process $proc$libresoc.v:21573$808 assign { } { } assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:21455.7-21455.43" - process $proc$libresoc.v:21455$809 + attribute \src "libresoc.v:21577.7-21577.43" + process $proc$libresoc.v:21577$809 assign { } { } assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:21459.7-21459.37" - process $proc$libresoc.v:21459$810 + attribute \src "libresoc.v:21581.7-21581.37" + process $proc$libresoc.v:21581$810 assign { } { } assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:21463.7-21463.37" - process $proc$libresoc.v:21463$811 + attribute \src "libresoc.v:21585.7-21585.37" + process $proc$libresoc.v:21585$811 assign { } { } assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:21467.7-21467.40" - process $proc$libresoc.v:21467$812 + attribute \src "libresoc.v:21589.7-21589.40" + process $proc$libresoc.v:21589$812 assign { } { } assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:21471.7-21471.37" - process $proc$libresoc.v:21471$813 + attribute \src "libresoc.v:21593.7-21593.37" + process $proc$libresoc.v:21593$813 assign { } { } assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:21503.7-21503.26" - process $proc$libresoc.v:21503$814 + attribute \src "libresoc.v:21625.7-21625.26" + process $proc$libresoc.v:21625$814 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:21511.7-21511.25" - process $proc$libresoc.v:21511$815 + attribute \src "libresoc.v:21633.7-21633.25" + process $proc$libresoc.v:21633$815 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:21523.7-21523.27" - process $proc$libresoc.v:21523$816 + attribute \src "libresoc.v:21645.7-21645.27" + process $proc$libresoc.v:21645$816 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:21557.14-21557.47" - process $proc$libresoc.v:21557$817 + attribute \src "libresoc.v:21679.14-21679.47" + process $proc$libresoc.v:21679$817 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:21561.7-21561.27" - process $proc$libresoc.v:21561$818 + attribute \src "libresoc.v:21683.7-21683.27" + process $proc$libresoc.v:21683$818 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:21565.13-21565.33" - process $proc$libresoc.v:21565$819 + attribute \src "libresoc.v:21687.13-21687.33" + process $proc$libresoc.v:21687$819 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:21569.7-21569.30" - process $proc$libresoc.v:21569$820 + attribute \src "libresoc.v:21691.7-21691.30" + process $proc$libresoc.v:21691$820 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:21573.13-21573.35" - process $proc$libresoc.v:21573$821 + attribute \src "libresoc.v:21695.13-21695.35" + process $proc$libresoc.v:21695$821 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:21577.7-21577.32" - process $proc$libresoc.v:21577$822 + attribute \src "libresoc.v:21699.7-21699.32" + process $proc$libresoc.v:21699$822 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:21581.13-21581.35" - process $proc$libresoc.v:21581$823 + attribute \src "libresoc.v:21703.13-21703.35" + process $proc$libresoc.v:21703$823 assign { } { } assign $1\data_r3__xer_ov[1:0] 2'00 sync always sync init update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:21585.7-21585.32" - process $proc$libresoc.v:21585$824 + attribute \src "libresoc.v:21707.7-21707.32" + process $proc$libresoc.v:21707$824 assign { } { } assign $1\data_r3__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:21589.7-21589.29" - process $proc$libresoc.v:21589$825 + attribute \src "libresoc.v:21711.7-21711.29" + process $proc$libresoc.v:21711$825 assign { } { } assign $1\data_r4__xer_so[0:0] 1'0 sync always sync init update \data_r4__xer_so $1\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:21593.7-21593.32" - process $proc$libresoc.v:21593$826 + attribute \src "libresoc.v:21715.7-21715.32" + process $proc$libresoc.v:21715$826 assign { } { } assign $1\data_r4__xer_so_ok[0:0] 1'0 sync always sync init update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:21616.7-21616.25" - process $proc$libresoc.v:21616$827 + attribute \src "libresoc.v:21738.7-21738.25" + process $proc$libresoc.v:21738$827 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:21620.7-21620.25" - process $proc$libresoc.v:21620$828 + attribute \src "libresoc.v:21742.7-21742.25" + process $proc$libresoc.v:21742$828 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:21752.13-21752.31" - process $proc$libresoc.v:21752$829 + attribute \src "libresoc.v:21876.13-21876.31" + process $proc$libresoc.v:21876$829 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:21760.13-21760.32" - process $proc$libresoc.v:21760$830 + attribute \src "libresoc.v:21884.13-21884.32" + process $proc$libresoc.v:21884$830 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:21764.13-21764.32" - process $proc$libresoc.v:21764$831 + attribute \src "libresoc.v:21888.13-21888.32" + process $proc$libresoc.v:21888$831 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:21776.7-21776.26" - process $proc$libresoc.v:21776$832 + attribute \src "libresoc.v:21900.7-21900.26" + process $proc$libresoc.v:21900$832 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:21780.7-21780.26" - process $proc$libresoc.v:21780$833 + attribute \src "libresoc.v:21904.7-21904.26" + process $proc$libresoc.v:21904$833 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:21784.7-21784.25" - process $proc$libresoc.v:21784$834 + attribute \src "libresoc.v:21908.7-21908.25" + process $proc$libresoc.v:21908$834 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:21788.7-21788.25" - process $proc$libresoc.v:21788$835 + attribute \src "libresoc.v:21912.7-21912.25" + process $proc$libresoc.v:21912$835 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:21804.13-21804.31" - process $proc$libresoc.v:21804$836 + attribute \src "libresoc.v:21928.13-21928.31" + process $proc$libresoc.v:21928$836 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:21808.13-21808.31" - process $proc$libresoc.v:21808$837 + attribute \src "libresoc.v:21932.13-21932.31" + process $proc$libresoc.v:21932$837 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:21816.14-21816.43" - process $proc$libresoc.v:21816$838 + attribute \src "libresoc.v:21940.14-21940.43" + process $proc$libresoc.v:21940$838 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:21820.14-21820.43" - process $proc$libresoc.v:21820$839 + attribute \src "libresoc.v:21944.14-21944.43" + process $proc$libresoc.v:21944$839 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:21824.7-21824.20" - process $proc$libresoc.v:21824$840 + attribute \src "libresoc.v:21948.7-21948.20" + process $proc$libresoc.v:21948$840 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:21828.13-21828.26" - process $proc$libresoc.v:21828$841 + attribute \src "libresoc.v:21952.13-21952.26" + process $proc$libresoc.v:21952$841 assign { } { } assign $1\src_r3[1:0] 2'00 sync always sync init update \src_r3 $1\src_r3[1:0] end - attribute \src "libresoc.v:21910.3-21911.39" - process $proc$libresoc.v:21910$607 + attribute \src "libresoc.v:22034.3-22035.39" + process $proc$libresoc.v:22034$607 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:21912.3-21913.43" - process $proc$libresoc.v:21912$608 + attribute \src "libresoc.v:22036.3-22037.43" + process $proc$libresoc.v:22036$608 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:21914.3-21915.29" - process $proc$libresoc.v:21914$609 + attribute \src "libresoc.v:22038.3-22039.29" + process $proc$libresoc.v:22038$609 assign { } { } assign $0\src_r3[1:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[1:0] end - attribute \src "libresoc.v:21916.3-21917.29" - process $proc$libresoc.v:21916$610 + attribute \src "libresoc.v:22040.3-22041.29" + process $proc$libresoc.v:22040$610 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:21918.3-21919.29" - process $proc$libresoc.v:21918$611 + attribute \src "libresoc.v:22042.3-22043.29" + process $proc$libresoc.v:22042$611 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:21920.3-21921.29" - process $proc$libresoc.v:21920$612 + attribute \src "libresoc.v:22044.3-22045.29" + process $proc$libresoc.v:22044$612 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:21922.3-21923.47" - process $proc$libresoc.v:21922$613 + attribute \src "libresoc.v:22046.3-22047.47" + process $proc$libresoc.v:22046$613 assign { } { } assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next sync posedge \coresync_clk update \data_r4__xer_so $0\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:21924.3-21925.53" - process $proc$libresoc.v:21924$614 + attribute \src "libresoc.v:22048.3-22049.53" + process $proc$libresoc.v:22048$614 assign { } { } assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next sync posedge \coresync_clk update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:21926.3-21927.47" - process $proc$libresoc.v:21926$615 + attribute \src "libresoc.v:22050.3-22051.47" + process $proc$libresoc.v:22050$615 assign { } { } assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next sync posedge \coresync_clk update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:21928.3-21929.53" - process $proc$libresoc.v:21928$616 + attribute \src "libresoc.v:22052.3-22053.53" + process $proc$libresoc.v:22052$616 assign { } { } assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next sync posedge \coresync_clk update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:21930.3-21931.47" - process $proc$libresoc.v:21930$617 + attribute \src "libresoc.v:22054.3-22055.47" + process $proc$libresoc.v:22054$617 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:21932.3-21933.53" - process $proc$libresoc.v:21932$618 + attribute \src "libresoc.v:22056.3-22057.53" + process $proc$libresoc.v:22056$618 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:21934.3-21935.43" - process $proc$libresoc.v:21934$619 + attribute \src "libresoc.v:22058.3-22059.43" + process $proc$libresoc.v:22058$619 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:21936.3-21937.49" - process $proc$libresoc.v:21936$620 + attribute \src "libresoc.v:22060.3-22061.49" + process $proc$libresoc.v:22060$620 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:21938.3-21939.37" - process $proc$libresoc.v:21938$621 + attribute \src "libresoc.v:22062.3-22063.37" + process $proc$libresoc.v:22062$621 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:21940.3-21941.43" - process $proc$libresoc.v:21940$622 + attribute \src "libresoc.v:22064.3-22065.43" + process $proc$libresoc.v:22064$622 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:21942.3-21943.69" - process $proc$libresoc.v:21942$623 + attribute \src "libresoc.v:22066.3-22067.69" + process $proc$libresoc.v:22066$623 assign { } { } assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:21944.3-21945.65" - process $proc$libresoc.v:21944$624 + attribute \src "libresoc.v:22068.3-22069.65" + process $proc$libresoc.v:22068$624 assign { } { } - assign $0\alu_alu0_alu_op__fn_unit[12:0] \alu_alu0_alu_op__fn_unit$next + assign $0\alu_alu0_alu_op__fn_unit[13:0] \alu_alu0_alu_op__fn_unit$next sync posedge \coresync_clk - update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[12:0] + update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:21946.3-21947.79" - process $proc$libresoc.v:21946$625 + attribute \src "libresoc.v:22070.3-22071.79" + process $proc$libresoc.v:22070$625 assign { } { } assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:21948.3-21949.75" - process $proc$libresoc.v:21948$626 + attribute \src "libresoc.v:22072.3-22073.75" + process $proc$libresoc.v:22072$626 assign { } { } assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:21950.3-21951.63" - process $proc$libresoc.v:21950$627 + attribute \src "libresoc.v:22074.3-22075.63" + process $proc$libresoc.v:22074$627 assign { } { } assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:21952.3-21953.63" - process $proc$libresoc.v:21952$628 + attribute \src "libresoc.v:22076.3-22077.63" + process $proc$libresoc.v:22076$628 assign { } { } assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:21954.3-21955.63" - process $proc$libresoc.v:21954$629 + attribute \src "libresoc.v:22078.3-22079.63" + process $proc$libresoc.v:22078$629 assign { } { } assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:21956.3-21957.63" - process $proc$libresoc.v:21956$630 + attribute \src "libresoc.v:22080.3-22081.63" + process $proc$libresoc.v:22080$630 assign { } { } assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:21958.3-21959.69" - process $proc$libresoc.v:21958$631 + attribute \src "libresoc.v:22082.3-22083.69" + process $proc$libresoc.v:22082$631 assign { } { } assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:21960.3-21961.63" - process $proc$libresoc.v:21960$632 + attribute \src "libresoc.v:22084.3-22085.63" + process $proc$libresoc.v:22084$632 assign { } { } assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next sync posedge \coresync_clk update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:21962.3-21963.71" - process $proc$libresoc.v:21962$633 + attribute \src "libresoc.v:22086.3-22087.71" + process $proc$libresoc.v:22086$633 assign { } { } assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:21964.3-21965.69" - process $proc$libresoc.v:21964$634 + attribute \src "libresoc.v:22088.3-22089.69" + process $proc$libresoc.v:22088$634 assign { } { } assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next sync posedge \coresync_clk update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:21966.3-21967.73" - process $proc$libresoc.v:21966$635 + attribute \src "libresoc.v:22090.3-22091.73" + process $proc$libresoc.v:22090$635 assign { } { } assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:21968.3-21969.75" - process $proc$libresoc.v:21968$636 + attribute \src "libresoc.v:22092.3-22093.75" + process $proc$libresoc.v:22092$636 assign { } { } assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:21970.3-21971.67" - process $proc$libresoc.v:21970$637 + attribute \src "libresoc.v:22094.3-22095.67" + process $proc$libresoc.v:22094$637 assign { } { } assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:21972.3-21973.69" - process $proc$libresoc.v:21972$638 + attribute \src "libresoc.v:22096.3-22097.69" + process $proc$libresoc.v:22096$638 assign { } { } assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:21974.3-21975.67" - process $proc$libresoc.v:21974$639 + attribute \src "libresoc.v:22098.3-22099.67" + process $proc$libresoc.v:22098$639 assign { } { } assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next sync posedge \coresync_clk update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:21976.3-21977.59" - process $proc$libresoc.v:21976$640 + attribute \src "libresoc.v:22100.3-22101.59" + process $proc$libresoc.v:22100$640 assign { } { } assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:21978.3-21979.39" - process $proc$libresoc.v:21978$641 + attribute \src "libresoc.v:22102.3-22103.39" + process $proc$libresoc.v:22102$641 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:21980.3-21981.39" - process $proc$libresoc.v:21980$642 + attribute \src "libresoc.v:22104.3-22105.39" + process $proc$libresoc.v:22104$642 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:21982.3-21983.39" - process $proc$libresoc.v:21982$643 + attribute \src "libresoc.v:22106.3-22107.39" + process $proc$libresoc.v:22106$643 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:21984.3-21985.39" - process $proc$libresoc.v:21984$644 + attribute \src "libresoc.v:22108.3-22109.39" + process $proc$libresoc.v:22108$644 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:21986.3-21987.39" - process $proc$libresoc.v:21986$645 + attribute \src "libresoc.v:22110.3-22111.39" + process $proc$libresoc.v:22110$645 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:21988.3-21989.39" - process $proc$libresoc.v:21988$646 + attribute \src "libresoc.v:22112.3-22113.39" + process $proc$libresoc.v:22112$646 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:21990.3-21991.39" - process $proc$libresoc.v:21990$647 + attribute \src "libresoc.v:22114.3-22115.39" + process $proc$libresoc.v:22114$647 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:21992.3-21993.39" - process $proc$libresoc.v:21992$648 + attribute \src "libresoc.v:22116.3-22117.39" + process $proc$libresoc.v:22116$648 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:21994.3-21995.41" - process $proc$libresoc.v:21994$649 + attribute \src "libresoc.v:22118.3-22119.41" + process $proc$libresoc.v:22118$649 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:21996.3-21997.41" - process $proc$libresoc.v:21996$650 + attribute \src "libresoc.v:22120.3-22121.41" + process $proc$libresoc.v:22120$650 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:21998.3-21999.37" - process $proc$libresoc.v:21998$651 + attribute \src "libresoc.v:22122.3-22123.37" + process $proc$libresoc.v:22122$651 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:22000.3-22001.40" - process $proc$libresoc.v:22000$652 + attribute \src "libresoc.v:22124.3-22125.40" + process $proc$libresoc.v:22124$652 assign { } { } assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:22002.3-22003.25" - process $proc$libresoc.v:22002$653 + attribute \src "libresoc.v:22126.3-22127.25" + process $proc$libresoc.v:22126$653 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:22092.3-22101.6" - process $proc$libresoc.v:22092$654 + attribute \src "libresoc.v:22216.3-22225.6" + process $proc$libresoc.v:22216$654 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:22093.5-22093.29" + attribute \src "libresoc.v:22217.5-22217.29" switch \initial - attribute \src "libresoc.v:22093.9-22093.17" + attribute \src "libresoc.v:22217.9-22217.17" case 1'1 case end @@ -33877,14 +34001,14 @@ module \alu0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:22102.3-22110.6" - process $proc$libresoc.v:22102$655 + attribute \src "libresoc.v:22226.3-22234.6" + process $proc$libresoc.v:22226$655 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:22103.5-22103.29" + attribute \src "libresoc.v:22227.5-22227.29" switch \initial - attribute \src "libresoc.v:22103.9-22103.17" + attribute \src "libresoc.v:22227.9-22227.17" case 1'1 case end @@ -33900,14 +34024,14 @@ module \alu0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 end - attribute \src "libresoc.v:22111.3-22119.6" - process $proc$libresoc.v:22111$658 + attribute \src "libresoc.v:22235.3-22243.6" + process $proc$libresoc.v:22235$658 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:22112.5-22112.29" + attribute \src "libresoc.v:22236.5-22236.29" switch \initial - attribute \src "libresoc.v:22112.9-22112.17" + attribute \src "libresoc.v:22236.9-22236.17" case 1'1 case end @@ -33923,14 +34047,14 @@ module \alu0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 end - attribute \src "libresoc.v:22120.3-22128.6" - process $proc$libresoc.v:22120$661 + attribute \src "libresoc.v:22244.3-22252.6" + process $proc$libresoc.v:22244$661 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:22121.5-22121.29" + attribute \src "libresoc.v:22245.5-22245.29" switch \initial - attribute \src "libresoc.v:22121.9-22121.17" + attribute \src "libresoc.v:22245.9-22245.17" case 1'1 case end @@ -33946,14 +34070,14 @@ module \alu0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 end - attribute \src "libresoc.v:22129.3-22137.6" - process $proc$libresoc.v:22129$664 + attribute \src "libresoc.v:22253.3-22261.6" + process $proc$libresoc.v:22253$664 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:22130.5-22130.29" + attribute \src "libresoc.v:22254.5-22254.29" switch \initial - attribute \src "libresoc.v:22130.9-22130.17" + attribute \src "libresoc.v:22254.9-22254.17" case 1'1 case end @@ -33969,14 +34093,14 @@ module \alu0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 end - attribute \src "libresoc.v:22138.3-22146.6" - process $proc$libresoc.v:22138$667 + attribute \src "libresoc.v:22262.3-22270.6" + process $proc$libresoc.v:22262$667 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:22139.5-22139.29" + attribute \src "libresoc.v:22263.5-22263.29" switch \initial - attribute \src "libresoc.v:22139.9-22139.17" + attribute \src "libresoc.v:22263.9-22263.17" case 1'1 case end @@ -33992,14 +34116,14 @@ module \alu0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 end - attribute \src "libresoc.v:22147.3-22155.6" - process $proc$libresoc.v:22147$670 + attribute \src "libresoc.v:22271.3-22279.6" + process $proc$libresoc.v:22271$670 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:22148.5-22148.29" + attribute \src "libresoc.v:22272.5-22272.29" switch \initial - attribute \src "libresoc.v:22148.9-22148.17" + attribute \src "libresoc.v:22272.9-22272.17" case 1'1 case end @@ -34015,14 +34139,14 @@ module \alu0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 end - attribute \src "libresoc.v:22156.3-22164.6" - process $proc$libresoc.v:22156$673 + attribute \src "libresoc.v:22280.3-22288.6" + process $proc$libresoc.v:22280$673 assign { } { } assign { } { } assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:22157.5-22157.29" + attribute \src "libresoc.v:22281.5-22281.29" switch \initial - attribute \src "libresoc.v:22157.9-22157.17" + attribute \src "libresoc.v:22281.9-22281.17" case 1'1 case end @@ -34038,14 +34162,14 @@ module \alu0 sync always update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 end - attribute \src "libresoc.v:22165.3-22173.6" - process $proc$libresoc.v:22165$676 + attribute \src "libresoc.v:22289.3-22297.6" + process $proc$libresoc.v:22289$676 assign { } { } assign { } { } assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:22166.5-22166.29" + attribute \src "libresoc.v:22290.5-22290.29" switch \initial - attribute \src "libresoc.v:22166.9-22166.17" + attribute \src "libresoc.v:22290.9-22290.17" case 1'1 case end @@ -34061,14 +34185,14 @@ module \alu0 sync always update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 end - attribute \src "libresoc.v:22174.3-22182.6" - process $proc$libresoc.v:22174$679 + attribute \src "libresoc.v:22298.3-22306.6" + process $proc$libresoc.v:22298$679 assign { } { } assign { } { } assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:22175.5-22175.29" + attribute \src "libresoc.v:22299.5-22299.29" switch \initial - attribute \src "libresoc.v:22175.9-22175.17" + attribute \src "libresoc.v:22299.9-22299.17" case 1'1 case end @@ -34084,14 +34208,14 @@ module \alu0 sync always update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 end - attribute \src "libresoc.v:22183.3-22191.6" - process $proc$libresoc.v:22183$682 + attribute \src "libresoc.v:22307.3-22315.6" + process $proc$libresoc.v:22307$682 assign { } { } assign { } { } assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:22184.5-22184.29" + attribute \src "libresoc.v:22308.5-22308.29" switch \initial - attribute \src "libresoc.v:22184.9-22184.17" + attribute \src "libresoc.v:22308.9-22308.17" case 1'1 case end @@ -34107,8 +34231,8 @@ module \alu0 sync always update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 end - attribute \src "libresoc.v:22192.3-22230.6" - process $proc$libresoc.v:22192$685 + attribute \src "libresoc.v:22316.3-22354.6" + process $proc$libresoc.v:22316$685 assign { } { } assign { } { } assign { } { } @@ -34146,7 +34270,7 @@ module \alu0 assign { } { } assign { } { } assign $0\alu_alu0_alu_op__data_len$next[3:0]$686 $1\alu_alu0_alu_op__data_len$next[3:0]$704 - assign $0\alu_alu0_alu_op__fn_unit$next[12:0]$687 $1\alu_alu0_alu_op__fn_unit$next[12:0]$705 + assign $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 assign { } { } assign { } { } assign $0\alu_alu0_alu_op__input_carry$next[1:0]$690 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 @@ -34169,9 +34293,9 @@ module \alu0 assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22193.5-22193.29" + attribute \src "libresoc.v:22317.5-22317.29" switch \initial - attribute \src "libresoc.v:22193.9-22193.17" + attribute \src "libresoc.v:22317.9-22317.17" case 1'1 case end @@ -34197,10 +34321,10 @@ module \alu0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[12:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } case assign $1\alu_alu0_alu_op__data_len$next[3:0]$704 \alu_alu0_alu_op__data_len - assign $1\alu_alu0_alu_op__fn_unit$next[12:0]$705 \alu_alu0_alu_op__fn_unit + assign $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 \alu_alu0_alu_op__fn_unit assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 \alu_alu0_alu_op__imm_data__data assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 \alu_alu0_alu_op__imm_data__ok assign $1\alu_alu0_alu_op__input_carry$next[1:0]$708 \alu_alu0_alu_op__input_carry @@ -34244,7 +34368,7 @@ module \alu0 end sync always update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$686 - update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[12:0]$687 + update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$690 @@ -34262,8 +34386,8 @@ module \alu0 update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 end - attribute \src "libresoc.v:22231.3-22252.6" - process $proc$libresoc.v:22231$728 + attribute \src "libresoc.v:22355.3-22376.6" + process $proc$libresoc.v:22355$728 assign { } { } assign { } { } assign { } { } @@ -34273,9 +34397,9 @@ module \alu0 assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 assign { } { } assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22232.5-22232.29" + attribute \src "libresoc.v:22356.5-22356.29" switch \initial - attribute \src "libresoc.v:22232.9-22232.17" + attribute \src "libresoc.v:22356.9-22356.17" case 1'1 case end @@ -34314,8 +34438,8 @@ module \alu0 update \data_r0__o$next $0\data_r0__o$next[63:0]$729 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 end - attribute \src "libresoc.v:22253.3-22274.6" - process $proc$libresoc.v:22253$736 + attribute \src "libresoc.v:22377.3-22398.6" + process $proc$libresoc.v:22377$736 assign { } { } assign { } { } assign { } { } @@ -34325,9 +34449,9 @@ module \alu0 assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22254.5-22254.29" + attribute \src "libresoc.v:22378.5-22378.29" switch \initial - attribute \src "libresoc.v:22254.9-22254.17" + attribute \src "libresoc.v:22378.9-22378.17" case 1'1 case end @@ -34366,8 +34490,8 @@ module \alu0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 end - attribute \src "libresoc.v:22275.3-22296.6" - process $proc$libresoc.v:22275$744 + attribute \src "libresoc.v:22399.3-22420.6" + process $proc$libresoc.v:22399$744 assign { } { } assign { } { } assign { } { } @@ -34377,9 +34501,9 @@ module \alu0 assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 assign { } { } assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22276.5-22276.29" + attribute \src "libresoc.v:22400.5-22400.29" switch \initial - attribute \src "libresoc.v:22276.9-22276.17" + attribute \src "libresoc.v:22400.9-22400.17" case 1'1 case end @@ -34418,8 +34542,8 @@ module \alu0 update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 end - attribute \src "libresoc.v:22297.3-22318.6" - process $proc$libresoc.v:22297$752 + attribute \src "libresoc.v:22421.3-22442.6" + process $proc$libresoc.v:22421$752 assign { } { } assign { } { } assign { } { } @@ -34429,9 +34553,9 @@ module \alu0 assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 assign { } { } assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22298.5-22298.29" + attribute \src "libresoc.v:22422.5-22422.29" switch \initial - attribute \src "libresoc.v:22298.9-22298.17" + attribute \src "libresoc.v:22422.9-22422.17" case 1'1 case end @@ -34470,8 +34594,8 @@ module \alu0 update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 end - attribute \src "libresoc.v:22319.3-22340.6" - process $proc$libresoc.v:22319$760 + attribute \src "libresoc.v:22443.3-22464.6" + process $proc$libresoc.v:22443$760 assign { } { } assign { } { } assign { } { } @@ -34481,9 +34605,9 @@ module \alu0 assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 assign { } { } assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:22320.5-22320.29" + attribute \src "libresoc.v:22444.5-22444.29" switch \initial - attribute \src "libresoc.v:22320.9-22320.17" + attribute \src "libresoc.v:22444.9-22444.17" case 1'1 case end @@ -34522,14 +34646,14 @@ module \alu0 update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 end - attribute \src "libresoc.v:22341.3-22350.6" - process $proc$libresoc.v:22341$768 + attribute \src "libresoc.v:22465.3-22474.6" + process $proc$libresoc.v:22465$768 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:22342.5-22342.29" + attribute \src "libresoc.v:22466.5-22466.29" switch \initial - attribute \src "libresoc.v:22342.9-22342.17" + attribute \src "libresoc.v:22466.9-22466.17" case 1'1 case end @@ -34545,14 +34669,14 @@ module \alu0 sync always update \src_r0$next $0\src_r0$next[63:0]$769 end - attribute \src "libresoc.v:22351.3-22360.6" - process $proc$libresoc.v:22351$771 + attribute \src "libresoc.v:22475.3-22484.6" + process $proc$libresoc.v:22475$771 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:22352.5-22352.29" + attribute \src "libresoc.v:22476.5-22476.29" switch \initial - attribute \src "libresoc.v:22352.9-22352.17" + attribute \src "libresoc.v:22476.9-22476.17" case 1'1 case end @@ -34568,14 +34692,14 @@ module \alu0 sync always update \src_r1$next $0\src_r1$next[63:0]$772 end - attribute \src "libresoc.v:22361.3-22370.6" - process $proc$libresoc.v:22361$774 + attribute \src "libresoc.v:22485.3-22494.6" + process $proc$libresoc.v:22485$774 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:22362.5-22362.29" + attribute \src "libresoc.v:22486.5-22486.29" switch \initial - attribute \src "libresoc.v:22362.9-22362.17" + attribute \src "libresoc.v:22486.9-22486.17" case 1'1 case end @@ -34591,14 +34715,14 @@ module \alu0 sync always update \src_r2$next $0\src_r2$next[0:0]$775 end - attribute \src "libresoc.v:22371.3-22380.6" - process $proc$libresoc.v:22371$777 + attribute \src "libresoc.v:22495.3-22504.6" + process $proc$libresoc.v:22495$777 assign { } { } assign { } { } assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:22372.5-22372.29" + attribute \src "libresoc.v:22496.5-22496.29" switch \initial - attribute \src "libresoc.v:22372.9-22372.17" + attribute \src "libresoc.v:22496.9-22496.17" case 1'1 case end @@ -34614,14 +34738,14 @@ module \alu0 sync always update \src_r3$next $0\src_r3$next[1:0]$778 end - attribute \src "libresoc.v:22381.3-22389.6" - process $proc$libresoc.v:22381$780 + attribute \src "libresoc.v:22505.3-22513.6" + process $proc$libresoc.v:22505$780 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:22382.5-22382.29" + attribute \src "libresoc.v:22506.5-22506.29" switch \initial - attribute \src "libresoc.v:22382.9-22382.17" + attribute \src "libresoc.v:22506.9-22506.17" case 1'1 case end @@ -34637,14 +34761,14 @@ module \alu0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$781 end - attribute \src "libresoc.v:22390.3-22398.6" - process $proc$libresoc.v:22390$783 + attribute \src "libresoc.v:22514.3-22522.6" + process $proc$libresoc.v:22514$783 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$784 $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:22391.5-22391.29" + attribute \src "libresoc.v:22515.5-22515.29" switch \initial - attribute \src "libresoc.v:22391.9-22391.17" + attribute \src "libresoc.v:22515.9-22515.17" case 1'1 case end @@ -34660,14 +34784,14 @@ module \alu0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$784 end - attribute \src "libresoc.v:22399.3-22408.6" - process $proc$libresoc.v:22399$786 + attribute \src "libresoc.v:22523.3-22532.6" + process $proc$libresoc.v:22523$786 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:22400.5-22400.29" + attribute \src "libresoc.v:22524.5-22524.29" switch \initial - attribute \src "libresoc.v:22400.9-22400.17" + attribute \src "libresoc.v:22524.9-22524.17" case 1'1 case end @@ -34683,14 +34807,14 @@ module \alu0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:22409.3-22418.6" - process $proc$libresoc.v:22409$787 + attribute \src "libresoc.v:22533.3-22542.6" + process $proc$libresoc.v:22533$787 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:22410.5-22410.29" + attribute \src "libresoc.v:22534.5-22534.29" switch \initial - attribute \src "libresoc.v:22410.9-22410.17" + attribute \src "libresoc.v:22534.9-22534.17" case 1'1 case end @@ -34706,14 +34830,14 @@ module \alu0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:22419.3-22428.6" - process $proc$libresoc.v:22419$788 + attribute \src "libresoc.v:22543.3-22552.6" + process $proc$libresoc.v:22543$788 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:22420.5-22420.29" + attribute \src "libresoc.v:22544.5-22544.29" switch \initial - attribute \src "libresoc.v:22420.9-22420.17" + attribute \src "libresoc.v:22544.9-22544.17" case 1'1 case end @@ -34729,14 +34853,14 @@ module \alu0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:22429.3-22438.6" - process $proc$libresoc.v:22429$789 + attribute \src "libresoc.v:22553.3-22562.6" + process $proc$libresoc.v:22553$789 assign { } { } assign { } { } assign $0\dest4_o[1:0] $1\dest4_o[1:0] - attribute \src "libresoc.v:22430.5-22430.29" + attribute \src "libresoc.v:22554.5-22554.29" switch \initial - attribute \src "libresoc.v:22430.9-22430.17" + attribute \src "libresoc.v:22554.9-22554.17" case 1'1 case end @@ -34752,14 +34876,14 @@ module \alu0 sync always update \dest4_o $0\dest4_o[1:0] end - attribute \src "libresoc.v:22439.3-22448.6" - process $proc$libresoc.v:22439$790 + attribute \src "libresoc.v:22563.3-22572.6" + process $proc$libresoc.v:22563$790 assign { } { } assign { } { } assign $0\dest5_o[0:0] $1\dest5_o[0:0] - attribute \src "libresoc.v:22440.5-22440.29" + attribute \src "libresoc.v:22564.5-22564.29" switch \initial - attribute \src "libresoc.v:22440.9-22440.17" + attribute \src "libresoc.v:22564.9-22564.17" case 1'1 case end @@ -34775,14 +34899,14 @@ module \alu0 sync always update \dest5_o $0\dest5_o[0:0] end - attribute \src "libresoc.v:22449.3-22457.6" - process $proc$libresoc.v:22449$791 + attribute \src "libresoc.v:22573.3-22581.6" + process $proc$libresoc.v:22573$791 assign { } { } assign { } { } assign $0\prev_wr_go$next[4:0]$792 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:22450.5-22450.29" + attribute \src "libresoc.v:22574.5-22574.29" switch \initial - attribute \src "libresoc.v:22450.9-22450.17" + attribute \src "libresoc.v:22574.9-22574.17" case 1'1 case end @@ -34798,73 +34922,73 @@ module \alu0 sync always update \prev_wr_go$next $0\prev_wr_go$next[4:0]$792 end - connect \$5 $reduce_and$libresoc.v:21843$540_Y - connect \$99 $and$libresoc.v:21844$541_Y - connect \$101 $and$libresoc.v:21845$542_Y - connect \$103 $and$libresoc.v:21846$543_Y - connect \$105 $not$libresoc.v:21847$544_Y - connect \$107 $not$libresoc.v:21848$545_Y - connect \$109 $and$libresoc.v:21849$546_Y - connect \$111 $not$libresoc.v:21850$547_Y - connect \$113 $and$libresoc.v:21851$548_Y - connect \$115 $and$libresoc.v:21852$549_Y - connect \$117 $and$libresoc.v:21853$550_Y - connect \$11 $and$libresoc.v:21854$551_Y - connect \$119 $and$libresoc.v:21855$552_Y - connect \$121 $and$libresoc.v:21856$553_Y - connect \$123 $and$libresoc.v:21857$554_Y - connect \$125 $and$libresoc.v:21858$555_Y - connect \$127 $and$libresoc.v:21859$556_Y - connect \$129 $and$libresoc.v:21860$557_Y - connect \$131 $and$libresoc.v:21861$558_Y - connect \$133 $and$libresoc.v:21862$559_Y - connect \$135 $and$libresoc.v:21863$560_Y - connect \$137 $and$libresoc.v:21864$561_Y - connect \$13 $not$libresoc.v:21865$562_Y - connect \$15 $and$libresoc.v:21866$563_Y - connect \$17 $not$libresoc.v:21867$564_Y - connect \$19 $and$libresoc.v:21868$565_Y - connect \$21 $and$libresoc.v:21869$566_Y - connect \$25 $not$libresoc.v:21870$567_Y - connect \$27 $and$libresoc.v:21871$568_Y - connect \$24 $reduce_or$libresoc.v:21872$569_Y - connect \$23 $not$libresoc.v:21873$570_Y - connect \$31 $and$libresoc.v:21874$571_Y - connect \$33 $reduce_or$libresoc.v:21875$572_Y - connect \$35 $reduce_or$libresoc.v:21876$573_Y - connect \$37 $or$libresoc.v:21877$574_Y - connect \$3 $and$libresoc.v:21878$575_Y - connect \$39 $not$libresoc.v:21879$576_Y - connect \$41 $and$libresoc.v:21880$577_Y - connect \$43 $and$libresoc.v:21881$578_Y - connect \$45 $eq$libresoc.v:21882$579_Y - connect \$47 $and$libresoc.v:21883$580_Y - connect \$49 $eq$libresoc.v:21884$581_Y - connect \$51 $and$libresoc.v:21885$582_Y - connect \$53 $and$libresoc.v:21886$583_Y - connect \$55 $and$libresoc.v:21887$584_Y - connect \$57 $or$libresoc.v:21888$585_Y - connect \$59 $or$libresoc.v:21889$586_Y - connect \$61 $or$libresoc.v:21890$587_Y - connect \$63 $or$libresoc.v:21891$588_Y - connect \$65 $and$libresoc.v:21892$589_Y - connect \$67 $and$libresoc.v:21893$590_Y - connect \$6 $not$libresoc.v:21894$591_Y - connect \$69 $or$libresoc.v:21895$592_Y - connect \$71 $and$libresoc.v:21896$593_Y - connect \$73 $and$libresoc.v:21897$594_Y - connect \$75 $and$libresoc.v:21898$595_Y - connect \$77 $and$libresoc.v:21899$596_Y - connect \$79 $and$libresoc.v:21900$597_Y - connect \$81 $ternary$libresoc.v:21901$598_Y - connect \$83 $ternary$libresoc.v:21902$599_Y - connect \$86 $ternary$libresoc.v:21903$600_Y - connect \$8 $or$libresoc.v:21904$601_Y - connect \$89 $ternary$libresoc.v:21905$602_Y - connect \$91 $ternary$libresoc.v:21906$603_Y - connect \$93 $ternary$libresoc.v:21907$604_Y - connect \$95 $ternary$libresoc.v:21908$605_Y - connect \$97 $ternary$libresoc.v:21909$606_Y + connect \$5 $reduce_and$libresoc.v:21967$540_Y + connect \$99 $and$libresoc.v:21968$541_Y + connect \$101 $and$libresoc.v:21969$542_Y + connect \$103 $and$libresoc.v:21970$543_Y + connect \$105 $not$libresoc.v:21971$544_Y + connect \$107 $not$libresoc.v:21972$545_Y + connect \$109 $and$libresoc.v:21973$546_Y + connect \$111 $not$libresoc.v:21974$547_Y + connect \$113 $and$libresoc.v:21975$548_Y + connect \$115 $and$libresoc.v:21976$549_Y + connect \$117 $and$libresoc.v:21977$550_Y + connect \$11 $and$libresoc.v:21978$551_Y + connect \$119 $and$libresoc.v:21979$552_Y + connect \$121 $and$libresoc.v:21980$553_Y + connect \$123 $and$libresoc.v:21981$554_Y + connect \$125 $and$libresoc.v:21982$555_Y + connect \$127 $and$libresoc.v:21983$556_Y + connect \$129 $and$libresoc.v:21984$557_Y + connect \$131 $and$libresoc.v:21985$558_Y + connect \$133 $and$libresoc.v:21986$559_Y + connect \$135 $and$libresoc.v:21987$560_Y + connect \$137 $and$libresoc.v:21988$561_Y + connect \$13 $not$libresoc.v:21989$562_Y + connect \$15 $and$libresoc.v:21990$563_Y + connect \$17 $not$libresoc.v:21991$564_Y + connect \$19 $and$libresoc.v:21992$565_Y + connect \$21 $and$libresoc.v:21993$566_Y + connect \$25 $not$libresoc.v:21994$567_Y + connect \$27 $and$libresoc.v:21995$568_Y + connect \$24 $reduce_or$libresoc.v:21996$569_Y + connect \$23 $not$libresoc.v:21997$570_Y + connect \$31 $and$libresoc.v:21998$571_Y + connect \$33 $reduce_or$libresoc.v:21999$572_Y + connect \$35 $reduce_or$libresoc.v:22000$573_Y + connect \$37 $or$libresoc.v:22001$574_Y + connect \$3 $and$libresoc.v:22002$575_Y + connect \$39 $not$libresoc.v:22003$576_Y + connect \$41 $and$libresoc.v:22004$577_Y + connect \$43 $and$libresoc.v:22005$578_Y + connect \$45 $eq$libresoc.v:22006$579_Y + connect \$47 $and$libresoc.v:22007$580_Y + connect \$49 $eq$libresoc.v:22008$581_Y + connect \$51 $and$libresoc.v:22009$582_Y + connect \$53 $and$libresoc.v:22010$583_Y + connect \$55 $and$libresoc.v:22011$584_Y + connect \$57 $or$libresoc.v:22012$585_Y + connect \$59 $or$libresoc.v:22013$586_Y + connect \$61 $or$libresoc.v:22014$587_Y + connect \$63 $or$libresoc.v:22015$588_Y + connect \$65 $and$libresoc.v:22016$589_Y + connect \$67 $and$libresoc.v:22017$590_Y + connect \$6 $not$libresoc.v:22018$591_Y + connect \$69 $or$libresoc.v:22019$592_Y + connect \$71 $and$libresoc.v:22020$593_Y + connect \$73 $and$libresoc.v:22021$594_Y + connect \$75 $and$libresoc.v:22022$595_Y + connect \$77 $and$libresoc.v:22023$596_Y + connect \$79 $and$libresoc.v:22024$597_Y + connect \$81 $ternary$libresoc.v:22025$598_Y + connect \$83 $ternary$libresoc.v:22026$599_Y + connect \$86 $ternary$libresoc.v:22027$600_Y + connect \$8 $or$libresoc.v:22028$601_Y + connect \$89 $ternary$libresoc.v:22029$602_Y + connect \$91 $ternary$libresoc.v:22030$603_Y + connect \$93 $ternary$libresoc.v:22031$604_Y + connect \$95 $ternary$libresoc.v:22032$605_Y + connect \$97 $ternary$libresoc.v:22033$606_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$127 @@ -34899,7 +35023,7 @@ module \alu0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:22495.1-23561.10" +attribute \src "libresoc.v:22619.1-23697.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0" attribute \generator "nMigen" @@ -34909,37 +35033,39 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$70 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 10 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 10 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$55 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 11 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35038,6 +35164,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 9 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -35114,6 +35241,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35160,9 +35288,9 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 28 \cr_a @@ -35189,37 +35317,39 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe1_alu_op__data_len$20 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe1_alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe1_alu_op__fn_unit$5 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_alu_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35318,6 +35448,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -35394,6 +35525,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_alu_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35485,37 +35617,39 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe2_alu_op__data_len$41 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe2_alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe2_alu_op__fn_unit$26 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_alu_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35614,6 +35748,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -35690,6 +35825,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_alu_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35809,19 +35945,19 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 6 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:23400.5-23403.4" + attribute \src "libresoc.v:23536.5-23539.4" cell \n \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:23404.5-23407.4" + attribute \src "libresoc.v:23540.5-23543.4" cell \p \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:23408.9-23467.4" + attribute \src "libresoc.v:23544.9-23603.4" cell \pipe1 \pipe1 connect \alu_op__data_len \pipe1_alu_op__data_len connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 @@ -35883,7 +36019,7 @@ module \alu_alu0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:23468.9-23533.4" + attribute \src "libresoc.v:23604.9-23669.4" cell \pipe2 \pipe2 connect \alu_op__data_len \pipe2_alu_op__data_len connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 @@ -35978,7 +36114,7 @@ module \alu_alu0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:23565.1-24104.10" +attribute \src "libresoc.v:23701.1-24248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" attribute \generator "nMigen" @@ -35988,37 +36124,39 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__cia$15 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 9 \br_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \br_op__fn_unit$17 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 11 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36105,6 +36243,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \br_op__insn_type attribute \enum_base_type "MicrOp" @@ -36181,6 +36320,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \br_op__insn_type$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36191,9 +36331,9 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a @@ -36230,37 +36370,39 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__cia$4 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_br_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_br_op__fn_unit$6 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_br_op__fn_unit$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36347,6 +36489,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_br_op__insn_type attribute \enum_base_type "MicrOp" @@ -36423,6 +36566,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_br_op__insn_type$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36464,19 +36608,19 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \module_not_derived 1 - attribute \src "libresoc.v:24046.10-24049.4" + attribute \src "libresoc.v:24190.10-24193.4" cell \n$18 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:24050.10-24053.4" + attribute \src "libresoc.v:24194.10-24197.4" cell \p$17 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:24054.13-24088.4" + attribute \src "libresoc.v:24198.13-24232.4" cell \pipe$19 \pipe connect \br_op__cia \pipe_br_op__cia connect \br_op__cia$2 \pipe_br_op__cia$4 @@ -36528,14 +36672,14 @@ module \alu_branch0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:24108.1-24615.10" +attribute \src "libresoc.v:24252.1-24767.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 12 \cr_a @@ -36548,37 +36692,39 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 18 \cr_c attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \cr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 8 \cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \cr_op__fn_unit$11 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \cr_op__fn_unit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 9 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36657,6 +36803,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 7 \cr_op__insn_type attribute \enum_base_type "MicrOp" @@ -36733,6 +36880,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -36768,37 +36916,39 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_c attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_cr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_cr_op__fn_unit$5 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_cr_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36877,6 +37027,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_cr_op__insn_type attribute \enum_base_type "MicrOp" @@ -36953,6 +37104,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_cr_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -36986,19 +37138,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \module_not_derived 1 - attribute \src "libresoc.v:24561.9-24564.4" + attribute \src "libresoc.v:24713.9-24716.4" cell \n$6 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:24565.9-24568.4" + attribute \src "libresoc.v:24717.9-24720.4" cell \p$5 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:24569.8-24596.4" + attribute \src "libresoc.v:24721.8-24748.4" cell \pipe \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -37046,14 +37198,14 @@ module \alu_cr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:24619.1-26068.10" +attribute \src "libresoc.v:24771.1-26236.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 27 \cr_a @@ -37064,37 +37216,39 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$88 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 9 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$73 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 10 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37193,6 +37347,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -37269,6 +37424,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37350,37 +37506,39 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_end_logical_op__data_len$68 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_end_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_end_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_end_logical_op__fn_unit$53 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_end_logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_end_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37479,6 +37637,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_end_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -37555,6 +37714,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_end_logical_op__insn_type$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37664,37 +37824,39 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_middle_0_logical_op__data_len$41 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_middle_0_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_middle_0_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_middle_0_logical_op__fn_unit$26 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_middle_0_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_middle_0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37793,6 +37955,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_middle_0_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -37869,6 +38032,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_middle_0_logical_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37964,37 +38128,39 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_start_logical_op__data_len$19 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_start_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_start_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_start_logical_op__fn_unit$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_start_logical_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_start_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -38093,6 +38259,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_start_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -38169,6 +38336,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_start_logical_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -38256,19 +38424,19 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:25824.10-25827.4" + attribute \src "libresoc.v:25992.10-25995.4" cell \n$75 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:25828.10-25831.4" + attribute \src "libresoc.v:25996.10-25999.4" cell \p$74 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:25832.12-25895.4" + attribute \src "libresoc.v:26000.12-26063.4" cell \pipe_end \pipe_end connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38334,7 +38502,7 @@ module \alu_div0 connect \xer_so_ok \pipe_end_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:25896.17-25962.4" + attribute \src "libresoc.v:26064.17-26130.4" cell \pipe_middle_0 \pipe_middle_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38403,7 +38571,7 @@ module \alu_div0 connect \xer_so$22 \pipe_middle_0_xer_so$45 end attribute \module_not_derived 1 - attribute \src "libresoc.v:25963.14-26022.4" + attribute \src "libresoc.v:26131.14-26190.4" cell \pipe_start \pipe_start connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38510,37 +38678,37 @@ module \alu_div0 connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o end -attribute \src "libresoc.v:26072.1-26130.10" +attribute \src "libresoc.v:26240.1-26298.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" attribute \generator "nMigen" module \alu_l - attribute \src "libresoc.v:26073.7-26073.20" + attribute \src "libresoc.v:26241.7-26241.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26118.3-26126.6" + attribute \src "libresoc.v:26286.3-26294.6" wire $0\q_int$next[0:0]$852 - attribute \src "libresoc.v:26116.3-26117.27" + attribute \src "libresoc.v:26284.3-26285.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26118.3-26126.6" + attribute \src "libresoc.v:26286.3-26294.6" wire $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:26097.7-26097.19" + attribute \src "libresoc.v:26265.7-26265.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26108.17-26108.96" - wire $and$libresoc.v:26108$842_Y - attribute \src "libresoc.v:26113.17-26113.96" - wire $and$libresoc.v:26113$847_Y - attribute \src "libresoc.v:26110.18-26110.93" - wire $not$libresoc.v:26110$844_Y - attribute \src "libresoc.v:26112.17-26112.92" - wire $not$libresoc.v:26112$846_Y - attribute \src "libresoc.v:26115.17-26115.92" - wire $not$libresoc.v:26115$849_Y - attribute \src "libresoc.v:26109.18-26109.98" - wire $or$libresoc.v:26109$843_Y - attribute \src "libresoc.v:26111.18-26111.99" - wire $or$libresoc.v:26111$845_Y - attribute \src "libresoc.v:26114.17-26114.97" - wire $or$libresoc.v:26114$848_Y + attribute \src "libresoc.v:26276.17-26276.96" + wire $and$libresoc.v:26276$842_Y + attribute \src "libresoc.v:26281.17-26281.96" + wire $and$libresoc.v:26281$847_Y + attribute \src "libresoc.v:26278.18-26278.93" + wire $not$libresoc.v:26278$844_Y + attribute \src "libresoc.v:26280.17-26280.92" + wire $not$libresoc.v:26280$846_Y + attribute \src "libresoc.v:26283.17-26283.92" + wire $not$libresoc.v:26283$849_Y + attribute \src "libresoc.v:26277.18-26277.98" + wire $or$libresoc.v:26277$843_Y + attribute \src "libresoc.v:26279.18-26279.99" + wire $or$libresoc.v:26279$845_Y + attribute \src "libresoc.v:26282.17-26282.97" + wire $or$libresoc.v:26282$848_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -38557,11 +38725,11 @@ module \alu_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26073.7-26073.15" + attribute \src "libresoc.v:26241.7-26241.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -38578,7 +38746,7 @@ module \alu_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26108$842 + cell $and $and$libresoc.v:26276$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38586,10 +38754,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26108$842_Y + connect \Y $and$libresoc.v:26276$842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26113$847 + cell $and $and$libresoc.v:26281$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38597,34 +38765,34 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26113$847_Y + connect \Y $and$libresoc.v:26281$847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26110$844 + cell $not $not$libresoc.v:26278$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26110$844_Y + connect \Y $not$libresoc.v:26278$844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26112$846 + cell $not $not$libresoc.v:26280$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26112$846_Y + connect \Y $not$libresoc.v:26280$846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26115$849 + cell $not $not$libresoc.v:26283$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26115$849_Y + connect \Y $not$libresoc.v:26283$849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26109$843 + cell $or $or$libresoc.v:26277$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38632,10 +38800,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26109$843_Y + connect \Y $or$libresoc.v:26277$843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26111$845 + cell $or $or$libresoc.v:26279$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38643,10 +38811,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26111$845_Y + connect \Y $or$libresoc.v:26279$845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26114$848 + cell $or $or$libresoc.v:26282$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38654,39 +38822,39 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26114$848_Y + connect \Y $or$libresoc.v:26282$848_Y end - attribute \src "libresoc.v:26073.7-26073.20" - process $proc$libresoc.v:26073$854 + attribute \src "libresoc.v:26241.7-26241.20" + process $proc$libresoc.v:26241$854 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26097.7-26097.19" - process $proc$libresoc.v:26097$855 + attribute \src "libresoc.v:26265.7-26265.19" + process $proc$libresoc.v:26265$855 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26116.3-26117.27" - process $proc$libresoc.v:26116$850 + attribute \src "libresoc.v:26284.3-26285.27" + process $proc$libresoc.v:26284$850 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26118.3-26126.6" - process $proc$libresoc.v:26118$851 + attribute \src "libresoc.v:26286.3-26294.6" + process $proc$libresoc.v:26286$851 assign { } { } assign { } { } assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:26119.5-26119.29" + attribute \src "libresoc.v:26287.5-26287.29" switch \initial - attribute \src "libresoc.v:26119.9-26119.17" + attribute \src "libresoc.v:26287.9-26287.17" case 1'1 case end @@ -38702,49 +38870,49 @@ module \alu_l sync always update \q_int$next $0\q_int$next[0:0]$852 end - connect \$9 $and$libresoc.v:26108$842_Y - connect \$11 $or$libresoc.v:26109$843_Y - connect \$13 $not$libresoc.v:26110$844_Y - connect \$15 $or$libresoc.v:26111$845_Y - connect \$1 $not$libresoc.v:26112$846_Y - connect \$3 $and$libresoc.v:26113$847_Y - connect \$5 $or$libresoc.v:26114$848_Y - connect \$7 $not$libresoc.v:26115$849_Y + connect \$9 $and$libresoc.v:26276$842_Y + connect \$11 $or$libresoc.v:26277$843_Y + connect \$13 $not$libresoc.v:26278$844_Y + connect \$15 $or$libresoc.v:26279$845_Y + connect \$1 $not$libresoc.v:26280$846_Y + connect \$3 $and$libresoc.v:26281$847_Y + connect \$5 $or$libresoc.v:26282$848_Y + connect \$7 $not$libresoc.v:26283$849_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26134.1-26192.10" +attribute \src "libresoc.v:26302.1-26360.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" attribute \generator "nMigen" module \alu_l$107 - attribute \src "libresoc.v:26135.7-26135.20" + attribute \src "libresoc.v:26303.7-26303.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26180.3-26188.6" + attribute \src "libresoc.v:26348.3-26356.6" wire $0\q_int$next[0:0]$866 - attribute \src "libresoc.v:26178.3-26179.27" + attribute \src "libresoc.v:26346.3-26347.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26180.3-26188.6" + attribute \src "libresoc.v:26348.3-26356.6" wire $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:26159.7-26159.19" + attribute \src "libresoc.v:26327.7-26327.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26170.17-26170.96" - wire $and$libresoc.v:26170$856_Y - attribute \src "libresoc.v:26175.17-26175.96" - wire $and$libresoc.v:26175$861_Y - attribute \src "libresoc.v:26172.18-26172.93" - wire $not$libresoc.v:26172$858_Y - attribute \src "libresoc.v:26174.17-26174.92" - wire $not$libresoc.v:26174$860_Y - attribute \src "libresoc.v:26177.17-26177.92" - wire $not$libresoc.v:26177$863_Y - attribute \src "libresoc.v:26171.18-26171.98" - wire $or$libresoc.v:26171$857_Y - attribute \src "libresoc.v:26173.18-26173.99" - wire $or$libresoc.v:26173$859_Y - attribute \src "libresoc.v:26176.17-26176.97" - wire $or$libresoc.v:26176$862_Y + attribute \src "libresoc.v:26338.17-26338.96" + wire $and$libresoc.v:26338$856_Y + attribute \src "libresoc.v:26343.17-26343.96" + wire $and$libresoc.v:26343$861_Y + attribute \src "libresoc.v:26340.18-26340.93" + wire $not$libresoc.v:26340$858_Y + attribute \src "libresoc.v:26342.17-26342.92" + wire $not$libresoc.v:26342$860_Y + attribute \src "libresoc.v:26345.17-26345.92" + wire $not$libresoc.v:26345$863_Y + attribute \src "libresoc.v:26339.18-26339.98" + wire $or$libresoc.v:26339$857_Y + attribute \src "libresoc.v:26341.18-26341.99" + wire $or$libresoc.v:26341$859_Y + attribute \src "libresoc.v:26344.17-26344.97" + wire $or$libresoc.v:26344$862_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -38761,11 +38929,11 @@ module \alu_l$107 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26135.7-26135.15" + attribute \src "libresoc.v:26303.7-26303.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -38782,7 +38950,7 @@ module \alu_l$107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26170$856 + cell $and $and$libresoc.v:26338$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38790,10 +38958,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26170$856_Y + connect \Y $and$libresoc.v:26338$856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26175$861 + cell $and $and$libresoc.v:26343$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38801,34 +38969,34 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26175$861_Y + connect \Y $and$libresoc.v:26343$861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26172$858 + cell $not $not$libresoc.v:26340$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26172$858_Y + connect \Y $not$libresoc.v:26340$858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26174$860 + cell $not $not$libresoc.v:26342$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26174$860_Y + connect \Y $not$libresoc.v:26342$860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26177$863 + cell $not $not$libresoc.v:26345$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26177$863_Y + connect \Y $not$libresoc.v:26345$863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26171$857 + cell $or $or$libresoc.v:26339$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38836,10 +39004,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26171$857_Y + connect \Y $or$libresoc.v:26339$857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26173$859 + cell $or $or$libresoc.v:26341$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38847,10 +39015,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26173$859_Y + connect \Y $or$libresoc.v:26341$859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26176$862 + cell $or $or$libresoc.v:26344$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38858,39 +39026,39 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26176$862_Y + connect \Y $or$libresoc.v:26344$862_Y end - attribute \src "libresoc.v:26135.7-26135.20" - process $proc$libresoc.v:26135$868 + attribute \src "libresoc.v:26303.7-26303.20" + process $proc$libresoc.v:26303$868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26159.7-26159.19" - process $proc$libresoc.v:26159$869 + attribute \src "libresoc.v:26327.7-26327.19" + process $proc$libresoc.v:26327$869 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26178.3-26179.27" - process $proc$libresoc.v:26178$864 + attribute \src "libresoc.v:26346.3-26347.27" + process $proc$libresoc.v:26346$864 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26180.3-26188.6" - process $proc$libresoc.v:26180$865 + attribute \src "libresoc.v:26348.3-26356.6" + process $proc$libresoc.v:26348$865 assign { } { } assign { } { } assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:26181.5-26181.29" + attribute \src "libresoc.v:26349.5-26349.29" switch \initial - attribute \src "libresoc.v:26181.9-26181.17" + attribute \src "libresoc.v:26349.9-26349.17" case 1'1 case end @@ -38906,49 +39074,49 @@ module \alu_l$107 sync always update \q_int$next $0\q_int$next[0:0]$866 end - connect \$9 $and$libresoc.v:26170$856_Y - connect \$11 $or$libresoc.v:26171$857_Y - connect \$13 $not$libresoc.v:26172$858_Y - connect \$15 $or$libresoc.v:26173$859_Y - connect \$1 $not$libresoc.v:26174$860_Y - connect \$3 $and$libresoc.v:26175$861_Y - connect \$5 $or$libresoc.v:26176$862_Y - connect \$7 $not$libresoc.v:26177$863_Y + connect \$9 $and$libresoc.v:26338$856_Y + connect \$11 $or$libresoc.v:26339$857_Y + connect \$13 $not$libresoc.v:26340$858_Y + connect \$15 $or$libresoc.v:26341$859_Y + connect \$1 $not$libresoc.v:26342$860_Y + connect \$3 $and$libresoc.v:26343$861_Y + connect \$5 $or$libresoc.v:26344$862_Y + connect \$7 $not$libresoc.v:26345$863_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26196.1-26254.10" +attribute \src "libresoc.v:26364.1-26422.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" attribute \generator "nMigen" module \alu_l$125 - attribute \src "libresoc.v:26197.7-26197.20" + attribute \src "libresoc.v:26365.7-26365.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26242.3-26250.6" + attribute \src "libresoc.v:26410.3-26418.6" wire $0\q_int$next[0:0]$880 - attribute \src "libresoc.v:26240.3-26241.27" + attribute \src "libresoc.v:26408.3-26409.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26242.3-26250.6" + attribute \src "libresoc.v:26410.3-26418.6" wire $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26221.7-26221.19" + attribute \src "libresoc.v:26389.7-26389.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26232.17-26232.96" - wire $and$libresoc.v:26232$870_Y - attribute \src "libresoc.v:26237.17-26237.96" - wire $and$libresoc.v:26237$875_Y - attribute \src "libresoc.v:26234.18-26234.93" - wire $not$libresoc.v:26234$872_Y - attribute \src "libresoc.v:26236.17-26236.92" - wire $not$libresoc.v:26236$874_Y - attribute \src "libresoc.v:26239.17-26239.92" - wire $not$libresoc.v:26239$877_Y - attribute \src "libresoc.v:26233.18-26233.98" - wire $or$libresoc.v:26233$871_Y - attribute \src "libresoc.v:26235.18-26235.99" - wire $or$libresoc.v:26235$873_Y - attribute \src "libresoc.v:26238.17-26238.97" - wire $or$libresoc.v:26238$876_Y + attribute \src "libresoc.v:26400.17-26400.96" + wire $and$libresoc.v:26400$870_Y + attribute \src "libresoc.v:26405.17-26405.96" + wire $and$libresoc.v:26405$875_Y + attribute \src "libresoc.v:26402.18-26402.93" + wire $not$libresoc.v:26402$872_Y + attribute \src "libresoc.v:26404.17-26404.92" + wire $not$libresoc.v:26404$874_Y + attribute \src "libresoc.v:26407.17-26407.92" + wire $not$libresoc.v:26407$877_Y + attribute \src "libresoc.v:26401.18-26401.98" + wire $or$libresoc.v:26401$871_Y + attribute \src "libresoc.v:26403.18-26403.99" + wire $or$libresoc.v:26403$873_Y + attribute \src "libresoc.v:26406.17-26406.97" + wire $or$libresoc.v:26406$876_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -38965,11 +39133,11 @@ module \alu_l$125 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26197.7-26197.15" + attribute \src "libresoc.v:26365.7-26365.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -38986,7 +39154,7 @@ module \alu_l$125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26232$870 + cell $and $and$libresoc.v:26400$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38994,10 +39162,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26232$870_Y + connect \Y $and$libresoc.v:26400$870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26237$875 + cell $and $and$libresoc.v:26405$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39005,34 +39173,34 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26237$875_Y + connect \Y $and$libresoc.v:26405$875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26234$872 + cell $not $not$libresoc.v:26402$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26234$872_Y + connect \Y $not$libresoc.v:26402$872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26236$874 + cell $not $not$libresoc.v:26404$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26236$874_Y + connect \Y $not$libresoc.v:26404$874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26239$877 + cell $not $not$libresoc.v:26407$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26239$877_Y + connect \Y $not$libresoc.v:26407$877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26233$871 + cell $or $or$libresoc.v:26401$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39040,10 +39208,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26233$871_Y + connect \Y $or$libresoc.v:26401$871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26235$873 + cell $or $or$libresoc.v:26403$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39051,10 +39219,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26235$873_Y + connect \Y $or$libresoc.v:26403$873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26238$876 + cell $or $or$libresoc.v:26406$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39062,39 +39230,39 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26238$876_Y + connect \Y $or$libresoc.v:26406$876_Y end - attribute \src "libresoc.v:26197.7-26197.20" - process $proc$libresoc.v:26197$882 + attribute \src "libresoc.v:26365.7-26365.20" + process $proc$libresoc.v:26365$882 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26221.7-26221.19" - process $proc$libresoc.v:26221$883 + attribute \src "libresoc.v:26389.7-26389.19" + process $proc$libresoc.v:26389$883 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26240.3-26241.27" - process $proc$libresoc.v:26240$878 + attribute \src "libresoc.v:26408.3-26409.27" + process $proc$libresoc.v:26408$878 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26242.3-26250.6" - process $proc$libresoc.v:26242$879 + attribute \src "libresoc.v:26410.3-26418.6" + process $proc$libresoc.v:26410$879 assign { } { } assign { } { } assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26243.5-26243.29" + attribute \src "libresoc.v:26411.5-26411.29" switch \initial - attribute \src "libresoc.v:26243.9-26243.17" + attribute \src "libresoc.v:26411.9-26411.17" case 1'1 case end @@ -39110,49 +39278,49 @@ module \alu_l$125 sync always update \q_int$next $0\q_int$next[0:0]$880 end - connect \$9 $and$libresoc.v:26232$870_Y - connect \$11 $or$libresoc.v:26233$871_Y - connect \$13 $not$libresoc.v:26234$872_Y - connect \$15 $or$libresoc.v:26235$873_Y - connect \$1 $not$libresoc.v:26236$874_Y - connect \$3 $and$libresoc.v:26237$875_Y - connect \$5 $or$libresoc.v:26238$876_Y - connect \$7 $not$libresoc.v:26239$877_Y + connect \$9 $and$libresoc.v:26400$870_Y + connect \$11 $or$libresoc.v:26401$871_Y + connect \$13 $not$libresoc.v:26402$872_Y + connect \$15 $or$libresoc.v:26403$873_Y + connect \$1 $not$libresoc.v:26404$874_Y + connect \$3 $and$libresoc.v:26405$875_Y + connect \$5 $or$libresoc.v:26406$876_Y + connect \$7 $not$libresoc.v:26407$877_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26258.1-26316.10" +attribute \src "libresoc.v:26426.1-26484.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" attribute \generator "nMigen" module \alu_l$128 - attribute \src "libresoc.v:26259.7-26259.20" + attribute \src "libresoc.v:26427.7-26427.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26304.3-26312.6" + attribute \src "libresoc.v:26472.3-26480.6" wire $0\q_int$next[0:0]$894 - attribute \src "libresoc.v:26302.3-26303.27" + attribute \src "libresoc.v:26470.3-26471.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26304.3-26312.6" + attribute \src "libresoc.v:26472.3-26480.6" wire $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26283.7-26283.19" + attribute \src "libresoc.v:26451.7-26451.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26294.17-26294.96" - wire $and$libresoc.v:26294$884_Y - attribute \src "libresoc.v:26299.17-26299.96" - wire $and$libresoc.v:26299$889_Y - attribute \src "libresoc.v:26296.18-26296.93" - wire $not$libresoc.v:26296$886_Y - attribute \src "libresoc.v:26298.17-26298.92" - wire $not$libresoc.v:26298$888_Y - attribute \src "libresoc.v:26301.17-26301.92" - wire $not$libresoc.v:26301$891_Y - attribute \src "libresoc.v:26295.18-26295.98" - wire $or$libresoc.v:26295$885_Y - attribute \src "libresoc.v:26297.18-26297.99" - wire $or$libresoc.v:26297$887_Y - attribute \src "libresoc.v:26300.17-26300.97" - wire $or$libresoc.v:26300$890_Y + attribute \src "libresoc.v:26462.17-26462.96" + wire $and$libresoc.v:26462$884_Y + attribute \src "libresoc.v:26467.17-26467.96" + wire $and$libresoc.v:26467$889_Y + attribute \src "libresoc.v:26464.18-26464.93" + wire $not$libresoc.v:26464$886_Y + attribute \src "libresoc.v:26466.17-26466.92" + wire $not$libresoc.v:26466$888_Y + attribute \src "libresoc.v:26469.17-26469.92" + wire $not$libresoc.v:26469$891_Y + attribute \src "libresoc.v:26463.18-26463.98" + wire $or$libresoc.v:26463$885_Y + attribute \src "libresoc.v:26465.18-26465.99" + wire $or$libresoc.v:26465$887_Y + attribute \src "libresoc.v:26468.17-26468.97" + wire $or$libresoc.v:26468$890_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39169,11 +39337,11 @@ module \alu_l$128 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26259.7-26259.15" + attribute \src "libresoc.v:26427.7-26427.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_alu @@ -39190,7 +39358,7 @@ module \alu_l$128 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26294$884 + cell $and $and$libresoc.v:26462$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39198,10 +39366,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26294$884_Y + connect \Y $and$libresoc.v:26462$884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26299$889 + cell $and $and$libresoc.v:26467$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39209,34 +39377,34 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26299$889_Y + connect \Y $and$libresoc.v:26467$889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26296$886 + cell $not $not$libresoc.v:26464$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26296$886_Y + connect \Y $not$libresoc.v:26464$886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26298$888 + cell $not $not$libresoc.v:26466$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26298$888_Y + connect \Y $not$libresoc.v:26466$888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26301$891 + cell $not $not$libresoc.v:26469$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26301$891_Y + connect \Y $not$libresoc.v:26469$891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26295$885 + cell $or $or$libresoc.v:26463$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39244,10 +39412,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26295$885_Y + connect \Y $or$libresoc.v:26463$885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26297$887 + cell $or $or$libresoc.v:26465$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39255,10 +39423,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26297$887_Y + connect \Y $or$libresoc.v:26465$887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26300$890 + cell $or $or$libresoc.v:26468$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39266,39 +39434,39 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26300$890_Y + connect \Y $or$libresoc.v:26468$890_Y end - attribute \src "libresoc.v:26259.7-26259.20" - process $proc$libresoc.v:26259$896 + attribute \src "libresoc.v:26427.7-26427.20" + process $proc$libresoc.v:26427$896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26283.7-26283.19" - process $proc$libresoc.v:26283$897 + attribute \src "libresoc.v:26451.7-26451.19" + process $proc$libresoc.v:26451$897 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26302.3-26303.27" - process $proc$libresoc.v:26302$892 + attribute \src "libresoc.v:26470.3-26471.27" + process $proc$libresoc.v:26470$892 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26304.3-26312.6" - process $proc$libresoc.v:26304$893 + attribute \src "libresoc.v:26472.3-26480.6" + process $proc$libresoc.v:26472$893 assign { } { } assign { } { } assign $0\q_int$next[0:0]$894 $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26305.5-26305.29" + attribute \src "libresoc.v:26473.5-26473.29" switch \initial - attribute \src "libresoc.v:26305.9-26305.17" + attribute \src "libresoc.v:26473.9-26473.17" case 1'1 case end @@ -39314,49 +39482,49 @@ module \alu_l$128 sync always update \q_int$next $0\q_int$next[0:0]$894 end - connect \$9 $and$libresoc.v:26294$884_Y - connect \$11 $or$libresoc.v:26295$885_Y - connect \$13 $not$libresoc.v:26296$886_Y - connect \$15 $or$libresoc.v:26297$887_Y - connect \$1 $not$libresoc.v:26298$888_Y - connect \$3 $and$libresoc.v:26299$889_Y - connect \$5 $or$libresoc.v:26300$890_Y - connect \$7 $not$libresoc.v:26301$891_Y + connect \$9 $and$libresoc.v:26462$884_Y + connect \$11 $or$libresoc.v:26463$885_Y + connect \$13 $not$libresoc.v:26464$886_Y + connect \$15 $or$libresoc.v:26465$887_Y + connect \$1 $not$libresoc.v:26466$888_Y + connect \$3 $and$libresoc.v:26467$889_Y + connect \$5 $or$libresoc.v:26468$890_Y + connect \$7 $not$libresoc.v:26469$891_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26320.1-26378.10" +attribute \src "libresoc.v:26488.1-26546.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" attribute \generator "nMigen" module \alu_l$16 - attribute \src "libresoc.v:26321.7-26321.20" + attribute \src "libresoc.v:26489.7-26489.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26366.3-26374.6" + attribute \src "libresoc.v:26534.3-26542.6" wire $0\q_int$next[0:0]$908 - attribute \src "libresoc.v:26364.3-26365.27" + attribute \src "libresoc.v:26532.3-26533.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26366.3-26374.6" + attribute \src "libresoc.v:26534.3-26542.6" wire $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26345.7-26345.19" + attribute \src "libresoc.v:26513.7-26513.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26356.17-26356.96" - wire $and$libresoc.v:26356$898_Y - attribute \src "libresoc.v:26361.17-26361.96" - wire $and$libresoc.v:26361$903_Y - attribute \src "libresoc.v:26358.18-26358.93" - wire $not$libresoc.v:26358$900_Y - attribute \src "libresoc.v:26360.17-26360.92" - wire $not$libresoc.v:26360$902_Y - attribute \src "libresoc.v:26363.17-26363.92" - wire $not$libresoc.v:26363$905_Y - attribute \src "libresoc.v:26357.18-26357.98" - wire $or$libresoc.v:26357$899_Y - attribute \src "libresoc.v:26359.18-26359.99" - wire $or$libresoc.v:26359$901_Y - attribute \src "libresoc.v:26362.17-26362.97" - wire $or$libresoc.v:26362$904_Y + attribute \src "libresoc.v:26524.17-26524.96" + wire $and$libresoc.v:26524$898_Y + attribute \src "libresoc.v:26529.17-26529.96" + wire $and$libresoc.v:26529$903_Y + attribute \src "libresoc.v:26526.18-26526.93" + wire $not$libresoc.v:26526$900_Y + attribute \src "libresoc.v:26528.17-26528.92" + wire $not$libresoc.v:26528$902_Y + attribute \src "libresoc.v:26531.17-26531.92" + wire $not$libresoc.v:26531$905_Y + attribute \src "libresoc.v:26525.18-26525.98" + wire $or$libresoc.v:26525$899_Y + attribute \src "libresoc.v:26527.18-26527.99" + wire $or$libresoc.v:26527$901_Y + attribute \src "libresoc.v:26530.17-26530.97" + wire $or$libresoc.v:26530$904_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39373,11 +39541,11 @@ module \alu_l$16 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26321.7-26321.15" + attribute \src "libresoc.v:26489.7-26489.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39394,7 +39562,7 @@ module \alu_l$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26356$898 + cell $and $and$libresoc.v:26524$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39402,10 +39570,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26356$898_Y + connect \Y $and$libresoc.v:26524$898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26361$903 + cell $and $and$libresoc.v:26529$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39413,34 +39581,34 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26361$903_Y + connect \Y $and$libresoc.v:26529$903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26358$900 + cell $not $not$libresoc.v:26526$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26358$900_Y + connect \Y $not$libresoc.v:26526$900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26360$902 + cell $not $not$libresoc.v:26528$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26360$902_Y + connect \Y $not$libresoc.v:26528$902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26363$905 + cell $not $not$libresoc.v:26531$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26363$905_Y + connect \Y $not$libresoc.v:26531$905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26357$899 + cell $or $or$libresoc.v:26525$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39448,10 +39616,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26357$899_Y + connect \Y $or$libresoc.v:26525$899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26359$901 + cell $or $or$libresoc.v:26527$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39459,10 +39627,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26359$901_Y + connect \Y $or$libresoc.v:26527$901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26362$904 + cell $or $or$libresoc.v:26530$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39470,39 +39638,39 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26362$904_Y + connect \Y $or$libresoc.v:26530$904_Y end - attribute \src "libresoc.v:26321.7-26321.20" - process $proc$libresoc.v:26321$910 + attribute \src "libresoc.v:26489.7-26489.20" + process $proc$libresoc.v:26489$910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26345.7-26345.19" - process $proc$libresoc.v:26345$911 + attribute \src "libresoc.v:26513.7-26513.19" + process $proc$libresoc.v:26513$911 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26364.3-26365.27" - process $proc$libresoc.v:26364$906 + attribute \src "libresoc.v:26532.3-26533.27" + process $proc$libresoc.v:26532$906 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26366.3-26374.6" - process $proc$libresoc.v:26366$907 + attribute \src "libresoc.v:26534.3-26542.6" + process $proc$libresoc.v:26534$907 assign { } { } assign { } { } assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26367.5-26367.29" + attribute \src "libresoc.v:26535.5-26535.29" switch \initial - attribute \src "libresoc.v:26367.9-26367.17" + attribute \src "libresoc.v:26535.9-26535.17" case 1'1 case end @@ -39518,49 +39686,49 @@ module \alu_l$16 sync always update \q_int$next $0\q_int$next[0:0]$908 end - connect \$9 $and$libresoc.v:26356$898_Y - connect \$11 $or$libresoc.v:26357$899_Y - connect \$13 $not$libresoc.v:26358$900_Y - connect \$15 $or$libresoc.v:26359$901_Y - connect \$1 $not$libresoc.v:26360$902_Y - connect \$3 $and$libresoc.v:26361$903_Y - connect \$5 $or$libresoc.v:26362$904_Y - connect \$7 $not$libresoc.v:26363$905_Y + connect \$9 $and$libresoc.v:26524$898_Y + connect \$11 $or$libresoc.v:26525$899_Y + connect \$13 $not$libresoc.v:26526$900_Y + connect \$15 $or$libresoc.v:26527$901_Y + connect \$1 $not$libresoc.v:26528$902_Y + connect \$3 $and$libresoc.v:26529$903_Y + connect \$5 $or$libresoc.v:26530$904_Y + connect \$7 $not$libresoc.v:26531$905_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26382.1-26440.10" +attribute \src "libresoc.v:26550.1-26608.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" attribute \generator "nMigen" module \alu_l$29 - attribute \src "libresoc.v:26383.7-26383.20" + attribute \src "libresoc.v:26551.7-26551.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26428.3-26436.6" + attribute \src "libresoc.v:26596.3-26604.6" wire $0\q_int$next[0:0]$922 - attribute \src "libresoc.v:26426.3-26427.27" + attribute \src "libresoc.v:26594.3-26595.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26428.3-26436.6" + attribute \src "libresoc.v:26596.3-26604.6" wire $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26407.7-26407.19" + attribute \src "libresoc.v:26575.7-26575.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26418.17-26418.96" - wire $and$libresoc.v:26418$912_Y - attribute \src "libresoc.v:26423.17-26423.96" - wire $and$libresoc.v:26423$917_Y - attribute \src "libresoc.v:26420.18-26420.93" - wire $not$libresoc.v:26420$914_Y - attribute \src "libresoc.v:26422.17-26422.92" - wire $not$libresoc.v:26422$916_Y - attribute \src "libresoc.v:26425.17-26425.92" - wire $not$libresoc.v:26425$919_Y - attribute \src "libresoc.v:26419.18-26419.98" - wire $or$libresoc.v:26419$913_Y - attribute \src "libresoc.v:26421.18-26421.99" - wire $or$libresoc.v:26421$915_Y - attribute \src "libresoc.v:26424.17-26424.97" - wire $or$libresoc.v:26424$918_Y + attribute \src "libresoc.v:26586.17-26586.96" + wire $and$libresoc.v:26586$912_Y + attribute \src "libresoc.v:26591.17-26591.96" + wire $and$libresoc.v:26591$917_Y + attribute \src "libresoc.v:26588.18-26588.93" + wire $not$libresoc.v:26588$914_Y + attribute \src "libresoc.v:26590.17-26590.92" + wire $not$libresoc.v:26590$916_Y + attribute \src "libresoc.v:26593.17-26593.92" + wire $not$libresoc.v:26593$919_Y + attribute \src "libresoc.v:26587.18-26587.98" + wire $or$libresoc.v:26587$913_Y + attribute \src "libresoc.v:26589.18-26589.99" + wire $or$libresoc.v:26589$915_Y + attribute \src "libresoc.v:26592.17-26592.97" + wire $or$libresoc.v:26592$918_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39577,11 +39745,11 @@ module \alu_l$29 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26383.7-26383.15" + attribute \src "libresoc.v:26551.7-26551.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39598,7 +39766,7 @@ module \alu_l$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26418$912 + cell $and $and$libresoc.v:26586$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39606,10 +39774,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26418$912_Y + connect \Y $and$libresoc.v:26586$912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26423$917 + cell $and $and$libresoc.v:26591$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39617,34 +39785,34 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26423$917_Y + connect \Y $and$libresoc.v:26591$917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26420$914 + cell $not $not$libresoc.v:26588$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26420$914_Y + connect \Y $not$libresoc.v:26588$914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26422$916 + cell $not $not$libresoc.v:26590$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26422$916_Y + connect \Y $not$libresoc.v:26590$916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26425$919 + cell $not $not$libresoc.v:26593$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26425$919_Y + connect \Y $not$libresoc.v:26593$919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26419$913 + cell $or $or$libresoc.v:26587$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39652,10 +39820,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26419$913_Y + connect \Y $or$libresoc.v:26587$913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26421$915 + cell $or $or$libresoc.v:26589$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39663,10 +39831,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26421$915_Y + connect \Y $or$libresoc.v:26589$915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26424$918 + cell $or $or$libresoc.v:26592$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39674,39 +39842,39 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26424$918_Y + connect \Y $or$libresoc.v:26592$918_Y end - attribute \src "libresoc.v:26383.7-26383.20" - process $proc$libresoc.v:26383$924 + attribute \src "libresoc.v:26551.7-26551.20" + process $proc$libresoc.v:26551$924 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26407.7-26407.19" - process $proc$libresoc.v:26407$925 + attribute \src "libresoc.v:26575.7-26575.19" + process $proc$libresoc.v:26575$925 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26426.3-26427.27" - process $proc$libresoc.v:26426$920 + attribute \src "libresoc.v:26594.3-26595.27" + process $proc$libresoc.v:26594$920 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26428.3-26436.6" - process $proc$libresoc.v:26428$921 + attribute \src "libresoc.v:26596.3-26604.6" + process $proc$libresoc.v:26596$921 assign { } { } assign { } { } assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26429.5-26429.29" + attribute \src "libresoc.v:26597.5-26597.29" switch \initial - attribute \src "libresoc.v:26429.9-26429.17" + attribute \src "libresoc.v:26597.9-26597.17" case 1'1 case end @@ -39722,49 +39890,49 @@ module \alu_l$29 sync always update \q_int$next $0\q_int$next[0:0]$922 end - connect \$9 $and$libresoc.v:26418$912_Y - connect \$11 $or$libresoc.v:26419$913_Y - connect \$13 $not$libresoc.v:26420$914_Y - connect \$15 $or$libresoc.v:26421$915_Y - connect \$1 $not$libresoc.v:26422$916_Y - connect \$3 $and$libresoc.v:26423$917_Y - connect \$5 $or$libresoc.v:26424$918_Y - connect \$7 $not$libresoc.v:26425$919_Y + connect \$9 $and$libresoc.v:26586$912_Y + connect \$11 $or$libresoc.v:26587$913_Y + connect \$13 $not$libresoc.v:26588$914_Y + connect \$15 $or$libresoc.v:26589$915_Y + connect \$1 $not$libresoc.v:26590$916_Y + connect \$3 $and$libresoc.v:26591$917_Y + connect \$5 $or$libresoc.v:26592$918_Y + connect \$7 $not$libresoc.v:26593$919_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26444.1-26502.10" +attribute \src "libresoc.v:26612.1-26670.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" attribute \generator "nMigen" module \alu_l$45 - attribute \src "libresoc.v:26445.7-26445.20" + attribute \src "libresoc.v:26613.7-26613.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26490.3-26498.6" + attribute \src "libresoc.v:26658.3-26666.6" wire $0\q_int$next[0:0]$936 - attribute \src "libresoc.v:26488.3-26489.27" + attribute \src "libresoc.v:26656.3-26657.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26490.3-26498.6" + attribute \src "libresoc.v:26658.3-26666.6" wire $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26469.7-26469.19" + attribute \src "libresoc.v:26637.7-26637.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26480.17-26480.96" - wire $and$libresoc.v:26480$926_Y - attribute \src "libresoc.v:26485.17-26485.96" - wire $and$libresoc.v:26485$931_Y - attribute \src "libresoc.v:26482.18-26482.93" - wire $not$libresoc.v:26482$928_Y - attribute \src "libresoc.v:26484.17-26484.92" - wire $not$libresoc.v:26484$930_Y - attribute \src "libresoc.v:26487.17-26487.92" - wire $not$libresoc.v:26487$933_Y - attribute \src "libresoc.v:26481.18-26481.98" - wire $or$libresoc.v:26481$927_Y - attribute \src "libresoc.v:26483.18-26483.99" - wire $or$libresoc.v:26483$929_Y - attribute \src "libresoc.v:26486.17-26486.97" - wire $or$libresoc.v:26486$932_Y + attribute \src "libresoc.v:26648.17-26648.96" + wire $and$libresoc.v:26648$926_Y + attribute \src "libresoc.v:26653.17-26653.96" + wire $and$libresoc.v:26653$931_Y + attribute \src "libresoc.v:26650.18-26650.93" + wire $not$libresoc.v:26650$928_Y + attribute \src "libresoc.v:26652.17-26652.92" + wire $not$libresoc.v:26652$930_Y + attribute \src "libresoc.v:26655.17-26655.92" + wire $not$libresoc.v:26655$933_Y + attribute \src "libresoc.v:26649.18-26649.98" + wire $or$libresoc.v:26649$927_Y + attribute \src "libresoc.v:26651.18-26651.99" + wire $or$libresoc.v:26651$929_Y + attribute \src "libresoc.v:26654.17-26654.97" + wire $or$libresoc.v:26654$932_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39781,11 +39949,11 @@ module \alu_l$45 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26445.7-26445.15" + attribute \src "libresoc.v:26613.7-26613.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39802,7 +39970,7 @@ module \alu_l$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26480$926 + cell $and $and$libresoc.v:26648$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39810,10 +39978,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26480$926_Y + connect \Y $and$libresoc.v:26648$926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26485$931 + cell $and $and$libresoc.v:26653$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39821,34 +39989,34 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26485$931_Y + connect \Y $and$libresoc.v:26653$931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26482$928 + cell $not $not$libresoc.v:26650$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26482$928_Y + connect \Y $not$libresoc.v:26650$928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26484$930 + cell $not $not$libresoc.v:26652$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26484$930_Y + connect \Y $not$libresoc.v:26652$930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26487$933 + cell $not $not$libresoc.v:26655$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26487$933_Y + connect \Y $not$libresoc.v:26655$933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26481$927 + cell $or $or$libresoc.v:26649$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39856,10 +40024,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26481$927_Y + connect \Y $or$libresoc.v:26649$927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26483$929 + cell $or $or$libresoc.v:26651$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39867,10 +40035,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26483$929_Y + connect \Y $or$libresoc.v:26651$929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26486$932 + cell $or $or$libresoc.v:26654$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39878,39 +40046,39 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26486$932_Y + connect \Y $or$libresoc.v:26654$932_Y end - attribute \src "libresoc.v:26445.7-26445.20" - process $proc$libresoc.v:26445$938 + attribute \src "libresoc.v:26613.7-26613.20" + process $proc$libresoc.v:26613$938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26469.7-26469.19" - process $proc$libresoc.v:26469$939 + attribute \src "libresoc.v:26637.7-26637.19" + process $proc$libresoc.v:26637$939 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26488.3-26489.27" - process $proc$libresoc.v:26488$934 + attribute \src "libresoc.v:26656.3-26657.27" + process $proc$libresoc.v:26656$934 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26490.3-26498.6" - process $proc$libresoc.v:26490$935 + attribute \src "libresoc.v:26658.3-26666.6" + process $proc$libresoc.v:26658$935 assign { } { } assign { } { } assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26491.5-26491.29" + attribute \src "libresoc.v:26659.5-26659.29" switch \initial - attribute \src "libresoc.v:26491.9-26491.17" + attribute \src "libresoc.v:26659.9-26659.17" case 1'1 case end @@ -39926,49 +40094,49 @@ module \alu_l$45 sync always update \q_int$next $0\q_int$next[0:0]$936 end - connect \$9 $and$libresoc.v:26480$926_Y - connect \$11 $or$libresoc.v:26481$927_Y - connect \$13 $not$libresoc.v:26482$928_Y - connect \$15 $or$libresoc.v:26483$929_Y - connect \$1 $not$libresoc.v:26484$930_Y - connect \$3 $and$libresoc.v:26485$931_Y - connect \$5 $or$libresoc.v:26486$932_Y - connect \$7 $not$libresoc.v:26487$933_Y + connect \$9 $and$libresoc.v:26648$926_Y + connect \$11 $or$libresoc.v:26649$927_Y + connect \$13 $not$libresoc.v:26650$928_Y + connect \$15 $or$libresoc.v:26651$929_Y + connect \$1 $not$libresoc.v:26652$930_Y + connect \$3 $and$libresoc.v:26653$931_Y + connect \$5 $or$libresoc.v:26654$932_Y + connect \$7 $not$libresoc.v:26655$933_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26506.1-26564.10" +attribute \src "libresoc.v:26674.1-26732.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" attribute \generator "nMigen" module \alu_l$61 - attribute \src "libresoc.v:26507.7-26507.20" + attribute \src "libresoc.v:26675.7-26675.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26552.3-26560.6" + attribute \src "libresoc.v:26720.3-26728.6" wire $0\q_int$next[0:0]$950 - attribute \src "libresoc.v:26550.3-26551.27" + attribute \src "libresoc.v:26718.3-26719.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26552.3-26560.6" + attribute \src "libresoc.v:26720.3-26728.6" wire $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26531.7-26531.19" + attribute \src "libresoc.v:26699.7-26699.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26542.17-26542.96" - wire $and$libresoc.v:26542$940_Y - attribute \src "libresoc.v:26547.17-26547.96" - wire $and$libresoc.v:26547$945_Y - attribute \src "libresoc.v:26544.18-26544.93" - wire $not$libresoc.v:26544$942_Y - attribute \src "libresoc.v:26546.17-26546.92" - wire $not$libresoc.v:26546$944_Y - attribute \src "libresoc.v:26549.17-26549.92" - wire $not$libresoc.v:26549$947_Y - attribute \src "libresoc.v:26543.18-26543.98" - wire $or$libresoc.v:26543$941_Y - attribute \src "libresoc.v:26545.18-26545.99" - wire $or$libresoc.v:26545$943_Y - attribute \src "libresoc.v:26548.17-26548.97" - wire $or$libresoc.v:26548$946_Y + attribute \src "libresoc.v:26710.17-26710.96" + wire $and$libresoc.v:26710$940_Y + attribute \src "libresoc.v:26715.17-26715.96" + wire $and$libresoc.v:26715$945_Y + attribute \src "libresoc.v:26712.18-26712.93" + wire $not$libresoc.v:26712$942_Y + attribute \src "libresoc.v:26714.17-26714.92" + wire $not$libresoc.v:26714$944_Y + attribute \src "libresoc.v:26717.17-26717.92" + wire $not$libresoc.v:26717$947_Y + attribute \src "libresoc.v:26711.18-26711.98" + wire $or$libresoc.v:26711$941_Y + attribute \src "libresoc.v:26713.18-26713.99" + wire $or$libresoc.v:26713$943_Y + attribute \src "libresoc.v:26716.17-26716.97" + wire $or$libresoc.v:26716$946_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39985,11 +40153,11 @@ module \alu_l$61 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26507.7-26507.15" + attribute \src "libresoc.v:26675.7-26675.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40006,7 +40174,7 @@ module \alu_l$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26542$940 + cell $and $and$libresoc.v:26710$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40014,10 +40182,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26542$940_Y + connect \Y $and$libresoc.v:26710$940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26547$945 + cell $and $and$libresoc.v:26715$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40025,34 +40193,34 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26547$945_Y + connect \Y $and$libresoc.v:26715$945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26544$942 + cell $not $not$libresoc.v:26712$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26544$942_Y + connect \Y $not$libresoc.v:26712$942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26546$944 + cell $not $not$libresoc.v:26714$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26546$944_Y + connect \Y $not$libresoc.v:26714$944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26549$947 + cell $not $not$libresoc.v:26717$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26549$947_Y + connect \Y $not$libresoc.v:26717$947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26543$941 + cell $or $or$libresoc.v:26711$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40060,10 +40228,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26543$941_Y + connect \Y $or$libresoc.v:26711$941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26545$943 + cell $or $or$libresoc.v:26713$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40071,10 +40239,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26545$943_Y + connect \Y $or$libresoc.v:26713$943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26548$946 + cell $or $or$libresoc.v:26716$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40082,39 +40250,39 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26548$946_Y + connect \Y $or$libresoc.v:26716$946_Y end - attribute \src "libresoc.v:26507.7-26507.20" - process $proc$libresoc.v:26507$952 + attribute \src "libresoc.v:26675.7-26675.20" + process $proc$libresoc.v:26675$952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26531.7-26531.19" - process $proc$libresoc.v:26531$953 + attribute \src "libresoc.v:26699.7-26699.19" + process $proc$libresoc.v:26699$953 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26550.3-26551.27" - process $proc$libresoc.v:26550$948 + attribute \src "libresoc.v:26718.3-26719.27" + process $proc$libresoc.v:26718$948 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26552.3-26560.6" - process $proc$libresoc.v:26552$949 + attribute \src "libresoc.v:26720.3-26728.6" + process $proc$libresoc.v:26720$949 assign { } { } assign { } { } assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26553.5-26553.29" + attribute \src "libresoc.v:26721.5-26721.29" switch \initial - attribute \src "libresoc.v:26553.9-26553.17" + attribute \src "libresoc.v:26721.9-26721.17" case 1'1 case end @@ -40130,49 +40298,49 @@ module \alu_l$61 sync always update \q_int$next $0\q_int$next[0:0]$950 end - connect \$9 $and$libresoc.v:26542$940_Y - connect \$11 $or$libresoc.v:26543$941_Y - connect \$13 $not$libresoc.v:26544$942_Y - connect \$15 $or$libresoc.v:26545$943_Y - connect \$1 $not$libresoc.v:26546$944_Y - connect \$3 $and$libresoc.v:26547$945_Y - connect \$5 $or$libresoc.v:26548$946_Y - connect \$7 $not$libresoc.v:26549$947_Y + connect \$9 $and$libresoc.v:26710$940_Y + connect \$11 $or$libresoc.v:26711$941_Y + connect \$13 $not$libresoc.v:26712$942_Y + connect \$15 $or$libresoc.v:26713$943_Y + connect \$1 $not$libresoc.v:26714$944_Y + connect \$3 $and$libresoc.v:26715$945_Y + connect \$5 $or$libresoc.v:26716$946_Y + connect \$7 $not$libresoc.v:26717$947_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26568.1-26626.10" +attribute \src "libresoc.v:26736.1-26794.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_l" attribute \generator "nMigen" module \alu_l$73 - attribute \src "libresoc.v:26569.7-26569.20" + attribute \src "libresoc.v:26737.7-26737.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26614.3-26622.6" + attribute \src "libresoc.v:26782.3-26790.6" wire $0\q_int$next[0:0]$964 - attribute \src "libresoc.v:26612.3-26613.27" + attribute \src "libresoc.v:26780.3-26781.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26614.3-26622.6" + attribute \src "libresoc.v:26782.3-26790.6" wire $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26593.7-26593.19" + attribute \src "libresoc.v:26761.7-26761.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26604.17-26604.96" - wire $and$libresoc.v:26604$954_Y - attribute \src "libresoc.v:26609.17-26609.96" - wire $and$libresoc.v:26609$959_Y - attribute \src "libresoc.v:26606.18-26606.93" - wire $not$libresoc.v:26606$956_Y - attribute \src "libresoc.v:26608.17-26608.92" - wire $not$libresoc.v:26608$958_Y - attribute \src "libresoc.v:26611.17-26611.92" - wire $not$libresoc.v:26611$961_Y - attribute \src "libresoc.v:26605.18-26605.98" - wire $or$libresoc.v:26605$955_Y - attribute \src "libresoc.v:26607.18-26607.99" - wire $or$libresoc.v:26607$957_Y - attribute \src "libresoc.v:26610.17-26610.97" - wire $or$libresoc.v:26610$960_Y + attribute \src "libresoc.v:26772.17-26772.96" + wire $and$libresoc.v:26772$954_Y + attribute \src "libresoc.v:26777.17-26777.96" + wire $and$libresoc.v:26777$959_Y + attribute \src "libresoc.v:26774.18-26774.93" + wire $not$libresoc.v:26774$956_Y + attribute \src "libresoc.v:26776.17-26776.92" + wire $not$libresoc.v:26776$958_Y + attribute \src "libresoc.v:26779.17-26779.92" + wire $not$libresoc.v:26779$961_Y + attribute \src "libresoc.v:26773.18-26773.98" + wire $or$libresoc.v:26773$955_Y + attribute \src "libresoc.v:26775.18-26775.99" + wire $or$libresoc.v:26775$957_Y + attribute \src "libresoc.v:26778.17-26778.97" + wire $or$libresoc.v:26778$960_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -40189,11 +40357,11 @@ module \alu_l$73 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26569.7-26569.15" + attribute \src "libresoc.v:26737.7-26737.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40210,7 +40378,7 @@ module \alu_l$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26604$954 + cell $and $and$libresoc.v:26772$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40218,10 +40386,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26604$954_Y + connect \Y $and$libresoc.v:26772$954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26609$959 + cell $and $and$libresoc.v:26777$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40229,34 +40397,34 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26609$959_Y + connect \Y $and$libresoc.v:26777$959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26606$956 + cell $not $not$libresoc.v:26774$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26606$956_Y + connect \Y $not$libresoc.v:26774$956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26608$958 + cell $not $not$libresoc.v:26776$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26608$958_Y + connect \Y $not$libresoc.v:26776$958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26611$961 + cell $not $not$libresoc.v:26779$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26611$961_Y + connect \Y $not$libresoc.v:26779$961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26605$955 + cell $or $or$libresoc.v:26773$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40264,10 +40432,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26605$955_Y + connect \Y $or$libresoc.v:26773$955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26607$957 + cell $or $or$libresoc.v:26775$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40275,10 +40443,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26607$957_Y + connect \Y $or$libresoc.v:26775$957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26610$960 + cell $or $or$libresoc.v:26778$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40286,39 +40454,39 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26610$960_Y + connect \Y $or$libresoc.v:26778$960_Y end - attribute \src "libresoc.v:26569.7-26569.20" - process $proc$libresoc.v:26569$966 + attribute \src "libresoc.v:26737.7-26737.20" + process $proc$libresoc.v:26737$966 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26593.7-26593.19" - process $proc$libresoc.v:26593$967 + attribute \src "libresoc.v:26761.7-26761.19" + process $proc$libresoc.v:26761$967 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26612.3-26613.27" - process $proc$libresoc.v:26612$962 + attribute \src "libresoc.v:26780.3-26781.27" + process $proc$libresoc.v:26780$962 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26614.3-26622.6" - process $proc$libresoc.v:26614$963 + attribute \src "libresoc.v:26782.3-26790.6" + process $proc$libresoc.v:26782$963 assign { } { } assign { } { } assign $0\q_int$next[0:0]$964 $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26615.5-26615.29" + attribute \src "libresoc.v:26783.5-26783.29" switch \initial - attribute \src "libresoc.v:26615.9-26615.17" + attribute \src "libresoc.v:26783.9-26783.17" case 1'1 case end @@ -40334,49 +40502,49 @@ module \alu_l$73 sync always update \q_int$next $0\q_int$next[0:0]$964 end - connect \$9 $and$libresoc.v:26604$954_Y - connect \$11 $or$libresoc.v:26605$955_Y - connect \$13 $not$libresoc.v:26606$956_Y - connect \$15 $or$libresoc.v:26607$957_Y - connect \$1 $not$libresoc.v:26608$958_Y - connect \$3 $and$libresoc.v:26609$959_Y - connect \$5 $or$libresoc.v:26610$960_Y - connect \$7 $not$libresoc.v:26611$961_Y + connect \$9 $and$libresoc.v:26772$954_Y + connect \$11 $or$libresoc.v:26773$955_Y + connect \$13 $not$libresoc.v:26774$956_Y + connect \$15 $or$libresoc.v:26775$957_Y + connect \$1 $not$libresoc.v:26776$958_Y + connect \$3 $and$libresoc.v:26777$959_Y + connect \$5 $or$libresoc.v:26778$960_Y + connect \$7 $not$libresoc.v:26779$961_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26630.1-26688.10" +attribute \src "libresoc.v:26798.1-26856.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_l" attribute \generator "nMigen" module \alu_l$90 - attribute \src "libresoc.v:26631.7-26631.20" + attribute \src "libresoc.v:26799.7-26799.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26676.3-26684.6" + attribute \src "libresoc.v:26844.3-26852.6" wire $0\q_int$next[0:0]$978 - attribute \src "libresoc.v:26674.3-26675.27" + attribute \src "libresoc.v:26842.3-26843.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26676.3-26684.6" + attribute \src "libresoc.v:26844.3-26852.6" wire $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26655.7-26655.19" + attribute \src "libresoc.v:26823.7-26823.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26666.17-26666.96" - wire $and$libresoc.v:26666$968_Y - attribute \src "libresoc.v:26671.17-26671.96" - wire $and$libresoc.v:26671$973_Y - attribute \src "libresoc.v:26668.18-26668.93" - wire $not$libresoc.v:26668$970_Y - attribute \src "libresoc.v:26670.17-26670.92" - wire $not$libresoc.v:26670$972_Y - attribute \src "libresoc.v:26673.17-26673.92" - wire $not$libresoc.v:26673$975_Y - attribute \src "libresoc.v:26667.18-26667.98" - wire $or$libresoc.v:26667$969_Y - attribute \src "libresoc.v:26669.18-26669.99" - wire $or$libresoc.v:26669$971_Y - attribute \src "libresoc.v:26672.17-26672.97" - wire $or$libresoc.v:26672$974_Y + attribute \src "libresoc.v:26834.17-26834.96" + wire $and$libresoc.v:26834$968_Y + attribute \src "libresoc.v:26839.17-26839.96" + wire $and$libresoc.v:26839$973_Y + attribute \src "libresoc.v:26836.18-26836.93" + wire $not$libresoc.v:26836$970_Y + attribute \src "libresoc.v:26838.17-26838.92" + wire $not$libresoc.v:26838$972_Y + attribute \src "libresoc.v:26841.17-26841.92" + wire $not$libresoc.v:26841$975_Y + attribute \src "libresoc.v:26835.18-26835.98" + wire $or$libresoc.v:26835$969_Y + attribute \src "libresoc.v:26837.18-26837.99" + wire $or$libresoc.v:26837$971_Y + attribute \src "libresoc.v:26840.17-26840.97" + wire $or$libresoc.v:26840$974_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -40393,11 +40561,11 @@ module \alu_l$90 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:26631.7-26631.15" + attribute \src "libresoc.v:26799.7-26799.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40414,7 +40582,7 @@ module \alu_l$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26666$968 + cell $and $and$libresoc.v:26834$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40422,10 +40590,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26666$968_Y + connect \Y $and$libresoc.v:26834$968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26671$973 + cell $and $and$libresoc.v:26839$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40433,34 +40601,34 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26671$973_Y + connect \Y $and$libresoc.v:26839$973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26668$970 + cell $not $not$libresoc.v:26836$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26668$970_Y + connect \Y $not$libresoc.v:26836$970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26670$972 + cell $not $not$libresoc.v:26838$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26670$972_Y + connect \Y $not$libresoc.v:26838$972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26673$975 + cell $not $not$libresoc.v:26841$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26673$975_Y + connect \Y $not$libresoc.v:26841$975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26667$969 + cell $or $or$libresoc.v:26835$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40468,10 +40636,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26667$969_Y + connect \Y $or$libresoc.v:26835$969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26669$971 + cell $or $or$libresoc.v:26837$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40479,10 +40647,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26669$971_Y + connect \Y $or$libresoc.v:26837$971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26672$974 + cell $or $or$libresoc.v:26840$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40490,39 +40658,39 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26672$974_Y + connect \Y $or$libresoc.v:26840$974_Y end - attribute \src "libresoc.v:26631.7-26631.20" - process $proc$libresoc.v:26631$980 + attribute \src "libresoc.v:26799.7-26799.20" + process $proc$libresoc.v:26799$980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26655.7-26655.19" - process $proc$libresoc.v:26655$981 + attribute \src "libresoc.v:26823.7-26823.19" + process $proc$libresoc.v:26823$981 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26674.3-26675.27" - process $proc$libresoc.v:26674$976 + attribute \src "libresoc.v:26842.3-26843.27" + process $proc$libresoc.v:26842$976 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26676.3-26684.6" - process $proc$libresoc.v:26676$977 + attribute \src "libresoc.v:26844.3-26852.6" + process $proc$libresoc.v:26844$977 assign { } { } assign { } { } assign $0\q_int$next[0:0]$978 $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26677.5-26677.29" + attribute \src "libresoc.v:26845.5-26845.29" switch \initial - attribute \src "libresoc.v:26677.9-26677.17" + attribute \src "libresoc.v:26845.9-26845.17" case 1'1 case end @@ -40538,26 +40706,26 @@ module \alu_l$90 sync always update \q_int$next $0\q_int$next[0:0]$978 end - connect \$9 $and$libresoc.v:26666$968_Y - connect \$11 $or$libresoc.v:26667$969_Y - connect \$13 $not$libresoc.v:26668$970_Y - connect \$15 $or$libresoc.v:26669$971_Y - connect \$1 $not$libresoc.v:26670$972_Y - connect \$3 $and$libresoc.v:26671$973_Y - connect \$5 $or$libresoc.v:26672$974_Y - connect \$7 $not$libresoc.v:26673$975_Y + connect \$9 $and$libresoc.v:26834$968_Y + connect \$11 $or$libresoc.v:26835$969_Y + connect \$13 $not$libresoc.v:26836$970_Y + connect \$15 $or$libresoc.v:26837$971_Y + connect \$1 $not$libresoc.v:26838$972_Y + connect \$3 $and$libresoc.v:26839$973_Y + connect \$5 $or$libresoc.v:26840$974_Y + connect \$7 $not$libresoc.v:26841$975_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26692.1-27693.10" +attribute \src "libresoc.v:26860.1-27873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -40568,37 +40736,39 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$61 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 7 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$46 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -40697,6 +40867,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -40773,6 +40944,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -40828,37 +41000,39 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe1_logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_pipe1_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe1_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_pipe1_logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe1_logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_pipe1_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -40957,6 +41131,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe1_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -41033,6 +41208,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe1_logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41118,37 +41294,39 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe2_logical_op__data_len$38 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_pipe2_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe2_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_pipe2_logical_op__fn_unit$23 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_pipe2_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_pipe2_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41247,6 +41425,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe2_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -41323,6 +41502,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe2_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41416,7 +41596,7 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 28 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:27553.17-27607.4" + attribute \src "libresoc.v:27733.17-27787.4" cell \logical_pipe1 \logical_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41473,7 +41653,7 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27608.17-27663.4" + attribute \src "libresoc.v:27788.17-27843.4" cell \logical_pipe2 \logical_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41531,13 +41711,13 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe2_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27664.10-27667.4" + attribute \src "libresoc.v:27844.10-27847.4" cell \n$47 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:27668.10-27671.4" + attribute \src "libresoc.v:27848.10-27851.4" cell \p$46 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i @@ -41564,51 +41744,53 @@ module \alu_logical0 connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o end -attribute \src "libresoc.v:27697.1-28898.10" +attribute \src "libresoc.v:27877.1-29094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \cr_a_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 9 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 9 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$51 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 10 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41695,6 +41877,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -41771,6 +41954,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41802,37 +41986,39 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$58 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_pipe1_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe1_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_pipe1_mul_op__fn_unit$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe1_mul_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe1_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -41919,6 +42105,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe1_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -41995,6 +42182,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe1_mul_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42054,37 +42242,39 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe1_xer_so$17 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_pipe2_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe2_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_pipe2_mul_op__fn_unit$20 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe2_mul_op__fn_unit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe2_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42171,6 +42361,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe2_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -42247,6 +42438,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe2_mul_op__insn_type$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42312,37 +42504,39 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_cr_a_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_pipe3_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe3_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_pipe3_mul_op__fn_unit$36 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_pipe3_mul_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42429,6 +42623,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe3_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -42505,6 +42700,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe3_mul_op__insn_type$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42598,7 +42794,7 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:28726.13-28767.4" + attribute \src "libresoc.v:28922.13-28963.4" cell \mul_pipe1 \mul_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42642,7 +42838,7 @@ module \alu_mul0 connect \xer_so$16 \mul_pipe1_xer_so$17 end attribute \module_not_derived 1 - attribute \src "libresoc.v:28768.13-28810.4" + attribute \src "libresoc.v:28964.13-29006.4" cell \mul_pipe2 \mul_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42687,7 +42883,7 @@ module \alu_mul0 connect \xer_so$14 \mul_pipe2_xer_so$31 end attribute \module_not_derived 1 - attribute \src "libresoc.v:28811.13-28856.4" + attribute \src "libresoc.v:29007.13-29052.4" cell \mul_pipe3 \mul_pipe3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42735,13 +42931,13 @@ module \alu_mul0 connect \xer_so_ok \mul_pipe3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:28857.10-28860.4" + attribute \src "libresoc.v:29053.10-29056.4" cell \n$92 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:28861.10-28864.4" + attribute \src "libresoc.v:29057.10-29060.4" cell \p$91 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i @@ -42780,14 +42976,14 @@ module \alu_mul0 connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o end -attribute \src "libresoc.v:28902.1-29923.10" +attribute \src "libresoc.v:29098.1-30131.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -42836,37 +43032,39 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rc attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe1_sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe1_sr_op__fn_unit$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_sr_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42969,6 +43167,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -43045,6 +43244,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_sr_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43128,37 +43328,39 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe2_p_valid_i attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe2_sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe2_sr_op__fn_unit$24 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_sr_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43261,6 +43463,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -43337,6 +43540,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_sr_op__insn_type$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43398,37 +43602,39 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 29 \rc attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 8 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$48 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 9 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43531,6 +43737,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 7 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -43607,6 +43814,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43658,19 +43866,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 30 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:29775.11-29778.4" + attribute \src "libresoc.v:29983.11-29986.4" cell \n$109 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:29779.11-29782.4" + attribute \src "libresoc.v:29987.11-29990.4" cell \p$108 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:29783.15-29839.4" + attribute \src "libresoc.v:29991.15-30047.4" cell \pipe1$110 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -43729,7 +43937,7 @@ module \alu_shift_rot0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:29840.15-29897.4" + attribute \src "libresoc.v:30048.15-30105.4" cell \pipe2$115 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -43814,14 +44022,14 @@ module \alu_shift_rot0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:29927.1-30477.10" +attribute \src "libresoc.v:30135.1-30693.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \fast1 @@ -43876,37 +44084,39 @@ module \alu_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_spr1_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_spr_op__fn_unit$8 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe_spr_op__fn_unit$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -43985,6 +44195,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_spr_op__insn_type attribute \enum_base_type "MicrOp" @@ -44061,6 +44272,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_spr_op__insn_type$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44094,37 +44306,39 @@ module \alu_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 7 \spr1_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 11 \spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 11 \spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_op__fn_unit$18 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 12 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44203,6 +44417,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 10 \spr_op__insn_type attribute \enum_base_type "MicrOp" @@ -44279,6 +44494,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_op__insn_type$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44304,19 +44520,19 @@ module \alu_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:30412.10-30415.4" + attribute \src "libresoc.v:30628.10-30631.4" cell \n$63 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:30416.10-30419.4" + attribute \src "libresoc.v:30632.10-30635.4" cell \p$62 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:30420.13-30455.4" + attribute \src "libresoc.v:30636.13-30671.4" cell \pipe$64 \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -44375,14 +44591,14 @@ module \alu_spr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:30481.1-31342.10" +attribute \src "libresoc.v:30697.1-31570.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 19 \fast1 @@ -44453,37 +44669,39 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_trap_op__cia$8 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe1_trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe1_trap_op__fn_unit$5 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe1_trap_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44562,6 +44780,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -44638,6 +44857,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_trap_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44705,37 +44925,39 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_trap_op__cia$22 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe2_trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe2_trap_op__fn_unit$19 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \pipe2_trap_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe2_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44814,6 +45036,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -44890,6 +45113,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_trap_op__insn_type$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -44921,37 +45145,39 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__cia$34 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 10 \trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 10 \trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$31 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 11 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -45030,6 +45256,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 9 \trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -45106,6 +45333,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -45129,19 +45357,19 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$36 attribute \module_not_derived 1 - attribute \src "libresoc.v:31230.10-31233.4" + attribute \src "libresoc.v:31458.10-31461.4" cell \n$31 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:31234.10-31237.4" + attribute \src "libresoc.v:31462.10-31465.4" cell \p$30 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:31238.14-31273.4" + attribute \src "libresoc.v:31466.14-31501.4" cell \pipe1$32 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -45179,7 +45407,7 @@ module \alu_trap0 connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 end attribute \module_not_derived 1 - attribute \src "libresoc.v:31274.14-31315.4" + attribute \src "libresoc.v:31502.14-31543.4" cell \pipe2$35 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -45249,37 +45477,37 @@ module \alu_trap0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:31346.1-31404.10" +attribute \src "libresoc.v:31574.1-31632.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" attribute \generator "nMigen" module \alui_l - attribute \src "libresoc.v:31347.7-31347.20" + attribute \src "libresoc.v:31575.7-31575.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31392.3-31400.6" + attribute \src "libresoc.v:31620.3-31628.6" wire $0\q_int$next[0:0]$992 - attribute \src "libresoc.v:31390.3-31391.27" + attribute \src "libresoc.v:31618.3-31619.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31392.3-31400.6" + attribute \src "libresoc.v:31620.3-31628.6" wire $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31371.7-31371.19" + attribute \src "libresoc.v:31599.7-31599.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31382.17-31382.96" - wire $and$libresoc.v:31382$982_Y - attribute \src "libresoc.v:31387.17-31387.96" - wire $and$libresoc.v:31387$987_Y - attribute \src "libresoc.v:31384.18-31384.94" - wire $not$libresoc.v:31384$984_Y - attribute \src "libresoc.v:31386.17-31386.93" - wire $not$libresoc.v:31386$986_Y - attribute \src "libresoc.v:31389.17-31389.93" - wire $not$libresoc.v:31389$989_Y - attribute \src "libresoc.v:31383.18-31383.99" - wire $or$libresoc.v:31383$983_Y - attribute \src "libresoc.v:31385.18-31385.100" - wire $or$libresoc.v:31385$985_Y - attribute \src "libresoc.v:31388.17-31388.98" - wire $or$libresoc.v:31388$988_Y + attribute \src "libresoc.v:31610.17-31610.96" + wire $and$libresoc.v:31610$982_Y + attribute \src "libresoc.v:31615.17-31615.96" + wire $and$libresoc.v:31615$987_Y + attribute \src "libresoc.v:31612.18-31612.94" + wire $not$libresoc.v:31612$984_Y + attribute \src "libresoc.v:31614.17-31614.93" + wire $not$libresoc.v:31614$986_Y + attribute \src "libresoc.v:31617.17-31617.93" + wire $not$libresoc.v:31617$989_Y + attribute \src "libresoc.v:31611.18-31611.99" + wire $or$libresoc.v:31611$983_Y + attribute \src "libresoc.v:31613.18-31613.100" + wire $or$libresoc.v:31613$985_Y + attribute \src "libresoc.v:31616.17-31616.98" + wire $or$libresoc.v:31616$988_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45296,11 +45524,11 @@ module \alui_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31347.7-31347.15" + attribute \src "libresoc.v:31575.7-31575.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45317,7 +45545,7 @@ module \alui_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31382$982 + cell $and $and$libresoc.v:31610$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45325,10 +45553,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31382$982_Y + connect \Y $and$libresoc.v:31610$982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31387$987 + cell $and $and$libresoc.v:31615$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45336,34 +45564,34 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31387$987_Y + connect \Y $and$libresoc.v:31615$987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31384$984 + cell $not $not$libresoc.v:31612$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31384$984_Y + connect \Y $not$libresoc.v:31612$984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31386$986 + cell $not $not$libresoc.v:31614$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31386$986_Y + connect \Y $not$libresoc.v:31614$986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31389$989 + cell $not $not$libresoc.v:31617$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31389$989_Y + connect \Y $not$libresoc.v:31617$989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31383$983 + cell $or $or$libresoc.v:31611$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45371,10 +45599,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31383$983_Y + connect \Y $or$libresoc.v:31611$983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31385$985 + cell $or $or$libresoc.v:31613$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45382,10 +45610,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31385$985_Y + connect \Y $or$libresoc.v:31613$985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31388$988 + cell $or $or$libresoc.v:31616$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45393,39 +45621,39 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31388$988_Y + connect \Y $or$libresoc.v:31616$988_Y end - attribute \src "libresoc.v:31347.7-31347.20" - process $proc$libresoc.v:31347$994 + attribute \src "libresoc.v:31575.7-31575.20" + process $proc$libresoc.v:31575$994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31371.7-31371.19" - process $proc$libresoc.v:31371$995 + attribute \src "libresoc.v:31599.7-31599.19" + process $proc$libresoc.v:31599$995 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31390.3-31391.27" - process $proc$libresoc.v:31390$990 + attribute \src "libresoc.v:31618.3-31619.27" + process $proc$libresoc.v:31618$990 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31392.3-31400.6" - process $proc$libresoc.v:31392$991 + attribute \src "libresoc.v:31620.3-31628.6" + process $proc$libresoc.v:31620$991 assign { } { } assign { } { } assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31393.5-31393.29" + attribute \src "libresoc.v:31621.5-31621.29" switch \initial - attribute \src "libresoc.v:31393.9-31393.17" + attribute \src "libresoc.v:31621.9-31621.17" case 1'1 case end @@ -45441,49 +45669,49 @@ module \alui_l sync always update \q_int$next $0\q_int$next[0:0]$992 end - connect \$9 $and$libresoc.v:31382$982_Y - connect \$11 $or$libresoc.v:31383$983_Y - connect \$13 $not$libresoc.v:31384$984_Y - connect \$15 $or$libresoc.v:31385$985_Y - connect \$1 $not$libresoc.v:31386$986_Y - connect \$3 $and$libresoc.v:31387$987_Y - connect \$5 $or$libresoc.v:31388$988_Y - connect \$7 $not$libresoc.v:31389$989_Y + connect \$9 $and$libresoc.v:31610$982_Y + connect \$11 $or$libresoc.v:31611$983_Y + connect \$13 $not$libresoc.v:31612$984_Y + connect \$15 $or$libresoc.v:31613$985_Y + connect \$1 $not$libresoc.v:31614$986_Y + connect \$3 $and$libresoc.v:31615$987_Y + connect \$5 $or$libresoc.v:31616$988_Y + connect \$7 $not$libresoc.v:31617$989_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31408.1-31466.10" +attribute \src "libresoc.v:31636.1-31694.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" attribute \generator "nMigen" module \alui_l$106 - attribute \src "libresoc.v:31409.7-31409.20" + attribute \src "libresoc.v:31637.7-31637.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31454.3-31462.6" + attribute \src "libresoc.v:31682.3-31690.6" wire $0\q_int$next[0:0]$1006 - attribute \src "libresoc.v:31452.3-31453.27" + attribute \src "libresoc.v:31680.3-31681.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31454.3-31462.6" + attribute \src "libresoc.v:31682.3-31690.6" wire $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31433.7-31433.19" + attribute \src "libresoc.v:31661.7-31661.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31444.17-31444.96" - wire $and$libresoc.v:31444$996_Y - attribute \src "libresoc.v:31449.17-31449.96" - wire $and$libresoc.v:31449$1001_Y - attribute \src "libresoc.v:31446.18-31446.94" - wire $not$libresoc.v:31446$998_Y - attribute \src "libresoc.v:31448.17-31448.93" - wire $not$libresoc.v:31448$1000_Y - attribute \src "libresoc.v:31451.17-31451.93" - wire $not$libresoc.v:31451$1003_Y - attribute \src "libresoc.v:31445.18-31445.99" - wire $or$libresoc.v:31445$997_Y - attribute \src "libresoc.v:31447.18-31447.100" - wire $or$libresoc.v:31447$999_Y - attribute \src "libresoc.v:31450.17-31450.98" - wire $or$libresoc.v:31450$1002_Y + attribute \src "libresoc.v:31672.17-31672.96" + wire $and$libresoc.v:31672$996_Y + attribute \src "libresoc.v:31677.17-31677.96" + wire $and$libresoc.v:31677$1001_Y + attribute \src "libresoc.v:31674.18-31674.94" + wire $not$libresoc.v:31674$998_Y + attribute \src "libresoc.v:31676.17-31676.93" + wire $not$libresoc.v:31676$1000_Y + attribute \src "libresoc.v:31679.17-31679.93" + wire $not$libresoc.v:31679$1003_Y + attribute \src "libresoc.v:31673.18-31673.99" + wire $or$libresoc.v:31673$997_Y + attribute \src "libresoc.v:31675.18-31675.100" + wire $or$libresoc.v:31675$999_Y + attribute \src "libresoc.v:31678.17-31678.98" + wire $or$libresoc.v:31678$1002_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45500,11 +45728,11 @@ module \alui_l$106 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31409.7-31409.15" + attribute \src "libresoc.v:31637.7-31637.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45521,7 +45749,7 @@ module \alui_l$106 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31444$996 + cell $and $and$libresoc.v:31672$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45529,10 +45757,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31444$996_Y + connect \Y $and$libresoc.v:31672$996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31449$1001 + cell $and $and$libresoc.v:31677$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45540,34 +45768,34 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31449$1001_Y + connect \Y $and$libresoc.v:31677$1001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31446$998 + cell $not $not$libresoc.v:31674$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31446$998_Y + connect \Y $not$libresoc.v:31674$998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31448$1000 + cell $not $not$libresoc.v:31676$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31448$1000_Y + connect \Y $not$libresoc.v:31676$1000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31451$1003 + cell $not $not$libresoc.v:31679$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31451$1003_Y + connect \Y $not$libresoc.v:31679$1003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31445$997 + cell $or $or$libresoc.v:31673$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45575,10 +45803,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31445$997_Y + connect \Y $or$libresoc.v:31673$997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31447$999 + cell $or $or$libresoc.v:31675$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45586,10 +45814,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31447$999_Y + connect \Y $or$libresoc.v:31675$999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31450$1002 + cell $or $or$libresoc.v:31678$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45597,39 +45825,39 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31450$1002_Y + connect \Y $or$libresoc.v:31678$1002_Y end - attribute \src "libresoc.v:31409.7-31409.20" - process $proc$libresoc.v:31409$1008 + attribute \src "libresoc.v:31637.7-31637.20" + process $proc$libresoc.v:31637$1008 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31433.7-31433.19" - process $proc$libresoc.v:31433$1009 + attribute \src "libresoc.v:31661.7-31661.19" + process $proc$libresoc.v:31661$1009 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31452.3-31453.27" - process $proc$libresoc.v:31452$1004 + attribute \src "libresoc.v:31680.3-31681.27" + process $proc$libresoc.v:31680$1004 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31454.3-31462.6" - process $proc$libresoc.v:31454$1005 + attribute \src "libresoc.v:31682.3-31690.6" + process $proc$libresoc.v:31682$1005 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31455.5-31455.29" + attribute \src "libresoc.v:31683.5-31683.29" switch \initial - attribute \src "libresoc.v:31455.9-31455.17" + attribute \src "libresoc.v:31683.9-31683.17" case 1'1 case end @@ -45645,49 +45873,49 @@ module \alui_l$106 sync always update \q_int$next $0\q_int$next[0:0]$1006 end - connect \$9 $and$libresoc.v:31444$996_Y - connect \$11 $or$libresoc.v:31445$997_Y - connect \$13 $not$libresoc.v:31446$998_Y - connect \$15 $or$libresoc.v:31447$999_Y - connect \$1 $not$libresoc.v:31448$1000_Y - connect \$3 $and$libresoc.v:31449$1001_Y - connect \$5 $or$libresoc.v:31450$1002_Y - connect \$7 $not$libresoc.v:31451$1003_Y + connect \$9 $and$libresoc.v:31672$996_Y + connect \$11 $or$libresoc.v:31673$997_Y + connect \$13 $not$libresoc.v:31674$998_Y + connect \$15 $or$libresoc.v:31675$999_Y + connect \$1 $not$libresoc.v:31676$1000_Y + connect \$3 $and$libresoc.v:31677$1001_Y + connect \$5 $or$libresoc.v:31678$1002_Y + connect \$7 $not$libresoc.v:31679$1003_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31470.1-31528.10" +attribute \src "libresoc.v:31698.1-31756.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" attribute \generator "nMigen" module \alui_l$124 - attribute \src "libresoc.v:31471.7-31471.20" + attribute \src "libresoc.v:31699.7-31699.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31516.3-31524.6" + attribute \src "libresoc.v:31744.3-31752.6" wire $0\q_int$next[0:0]$1020 - attribute \src "libresoc.v:31514.3-31515.27" + attribute \src "libresoc.v:31742.3-31743.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31516.3-31524.6" + attribute \src "libresoc.v:31744.3-31752.6" wire $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31495.7-31495.19" + attribute \src "libresoc.v:31723.7-31723.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31506.17-31506.96" - wire $and$libresoc.v:31506$1010_Y - attribute \src "libresoc.v:31511.17-31511.96" - wire $and$libresoc.v:31511$1015_Y - attribute \src "libresoc.v:31508.18-31508.94" - wire $not$libresoc.v:31508$1012_Y - attribute \src "libresoc.v:31510.17-31510.93" - wire $not$libresoc.v:31510$1014_Y - attribute \src "libresoc.v:31513.17-31513.93" - wire $not$libresoc.v:31513$1017_Y - attribute \src "libresoc.v:31507.18-31507.99" - wire $or$libresoc.v:31507$1011_Y - attribute \src "libresoc.v:31509.18-31509.100" - wire $or$libresoc.v:31509$1013_Y - attribute \src "libresoc.v:31512.17-31512.98" - wire $or$libresoc.v:31512$1016_Y + attribute \src "libresoc.v:31734.17-31734.96" + wire $and$libresoc.v:31734$1010_Y + attribute \src "libresoc.v:31739.17-31739.96" + wire $and$libresoc.v:31739$1015_Y + attribute \src "libresoc.v:31736.18-31736.94" + wire $not$libresoc.v:31736$1012_Y + attribute \src "libresoc.v:31738.17-31738.93" + wire $not$libresoc.v:31738$1014_Y + attribute \src "libresoc.v:31741.17-31741.93" + wire $not$libresoc.v:31741$1017_Y + attribute \src "libresoc.v:31735.18-31735.99" + wire $or$libresoc.v:31735$1011_Y + attribute \src "libresoc.v:31737.18-31737.100" + wire $or$libresoc.v:31737$1013_Y + attribute \src "libresoc.v:31740.17-31740.98" + wire $or$libresoc.v:31740$1016_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45704,11 +45932,11 @@ module \alui_l$124 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31471.7-31471.15" + attribute \src "libresoc.v:31699.7-31699.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45725,7 +45953,7 @@ module \alui_l$124 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31506$1010 + cell $and $and$libresoc.v:31734$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45733,10 +45961,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31506$1010_Y + connect \Y $and$libresoc.v:31734$1010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31511$1015 + cell $and $and$libresoc.v:31739$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45744,34 +45972,34 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31511$1015_Y + connect \Y $and$libresoc.v:31739$1015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31508$1012 + cell $not $not$libresoc.v:31736$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31508$1012_Y + connect \Y $not$libresoc.v:31736$1012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31510$1014 + cell $not $not$libresoc.v:31738$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31510$1014_Y + connect \Y $not$libresoc.v:31738$1014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31513$1017 + cell $not $not$libresoc.v:31741$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31513$1017_Y + connect \Y $not$libresoc.v:31741$1017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31507$1011 + cell $or $or$libresoc.v:31735$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45779,10 +46007,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31507$1011_Y + connect \Y $or$libresoc.v:31735$1011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31509$1013 + cell $or $or$libresoc.v:31737$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45790,10 +46018,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31509$1013_Y + connect \Y $or$libresoc.v:31737$1013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31512$1016 + cell $or $or$libresoc.v:31740$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45801,39 +46029,39 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31512$1016_Y + connect \Y $or$libresoc.v:31740$1016_Y end - attribute \src "libresoc.v:31471.7-31471.20" - process $proc$libresoc.v:31471$1022 + attribute \src "libresoc.v:31699.7-31699.20" + process $proc$libresoc.v:31699$1022 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31495.7-31495.19" - process $proc$libresoc.v:31495$1023 + attribute \src "libresoc.v:31723.7-31723.19" + process $proc$libresoc.v:31723$1023 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31514.3-31515.27" - process $proc$libresoc.v:31514$1018 + attribute \src "libresoc.v:31742.3-31743.27" + process $proc$libresoc.v:31742$1018 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31516.3-31524.6" - process $proc$libresoc.v:31516$1019 + attribute \src "libresoc.v:31744.3-31752.6" + process $proc$libresoc.v:31744$1019 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31517.5-31517.29" + attribute \src "libresoc.v:31745.5-31745.29" switch \initial - attribute \src "libresoc.v:31517.9-31517.17" + attribute \src "libresoc.v:31745.9-31745.17" case 1'1 case end @@ -45849,49 +46077,49 @@ module \alui_l$124 sync always update \q_int$next $0\q_int$next[0:0]$1020 end - connect \$9 $and$libresoc.v:31506$1010_Y - connect \$11 $or$libresoc.v:31507$1011_Y - connect \$13 $not$libresoc.v:31508$1012_Y - connect \$15 $or$libresoc.v:31509$1013_Y - connect \$1 $not$libresoc.v:31510$1014_Y - connect \$3 $and$libresoc.v:31511$1015_Y - connect \$5 $or$libresoc.v:31512$1016_Y - connect \$7 $not$libresoc.v:31513$1017_Y + connect \$9 $and$libresoc.v:31734$1010_Y + connect \$11 $or$libresoc.v:31735$1011_Y + connect \$13 $not$libresoc.v:31736$1012_Y + connect \$15 $or$libresoc.v:31737$1013_Y + connect \$1 $not$libresoc.v:31738$1014_Y + connect \$3 $and$libresoc.v:31739$1015_Y + connect \$5 $or$libresoc.v:31740$1016_Y + connect \$7 $not$libresoc.v:31741$1017_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31532.1-31590.10" +attribute \src "libresoc.v:31760.1-31818.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" attribute \generator "nMigen" module \alui_l$15 - attribute \src "libresoc.v:31533.7-31533.20" + attribute \src "libresoc.v:31761.7-31761.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31578.3-31586.6" + attribute \src "libresoc.v:31806.3-31814.6" wire $0\q_int$next[0:0]$1034 - attribute \src "libresoc.v:31576.3-31577.27" + attribute \src "libresoc.v:31804.3-31805.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31578.3-31586.6" + attribute \src "libresoc.v:31806.3-31814.6" wire $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31557.7-31557.19" + attribute \src "libresoc.v:31785.7-31785.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31568.17-31568.96" - wire $and$libresoc.v:31568$1024_Y - attribute \src "libresoc.v:31573.17-31573.96" - wire $and$libresoc.v:31573$1029_Y - attribute \src "libresoc.v:31570.18-31570.94" - wire $not$libresoc.v:31570$1026_Y - attribute \src "libresoc.v:31572.17-31572.93" - wire $not$libresoc.v:31572$1028_Y - attribute \src "libresoc.v:31575.17-31575.93" - wire $not$libresoc.v:31575$1031_Y - attribute \src "libresoc.v:31569.18-31569.99" - wire $or$libresoc.v:31569$1025_Y - attribute \src "libresoc.v:31571.18-31571.100" - wire $or$libresoc.v:31571$1027_Y - attribute \src "libresoc.v:31574.17-31574.98" - wire $or$libresoc.v:31574$1030_Y + attribute \src "libresoc.v:31796.17-31796.96" + wire $and$libresoc.v:31796$1024_Y + attribute \src "libresoc.v:31801.17-31801.96" + wire $and$libresoc.v:31801$1029_Y + attribute \src "libresoc.v:31798.18-31798.94" + wire $not$libresoc.v:31798$1026_Y + attribute \src "libresoc.v:31800.17-31800.93" + wire $not$libresoc.v:31800$1028_Y + attribute \src "libresoc.v:31803.17-31803.93" + wire $not$libresoc.v:31803$1031_Y + attribute \src "libresoc.v:31797.18-31797.99" + wire $or$libresoc.v:31797$1025_Y + attribute \src "libresoc.v:31799.18-31799.100" + wire $or$libresoc.v:31799$1027_Y + attribute \src "libresoc.v:31802.17-31802.98" + wire $or$libresoc.v:31802$1030_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45908,11 +46136,11 @@ module \alui_l$15 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31533.7-31533.15" + attribute \src "libresoc.v:31761.7-31761.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45929,7 +46157,7 @@ module \alui_l$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31568$1024 + cell $and $and$libresoc.v:31796$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45937,10 +46165,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31568$1024_Y + connect \Y $and$libresoc.v:31796$1024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31573$1029 + cell $and $and$libresoc.v:31801$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45948,34 +46176,34 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31573$1029_Y + connect \Y $and$libresoc.v:31801$1029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31570$1026 + cell $not $not$libresoc.v:31798$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31570$1026_Y + connect \Y $not$libresoc.v:31798$1026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31572$1028 + cell $not $not$libresoc.v:31800$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31572$1028_Y + connect \Y $not$libresoc.v:31800$1028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31575$1031 + cell $not $not$libresoc.v:31803$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31575$1031_Y + connect \Y $not$libresoc.v:31803$1031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31569$1025 + cell $or $or$libresoc.v:31797$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45983,10 +46211,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31569$1025_Y + connect \Y $or$libresoc.v:31797$1025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31571$1027 + cell $or $or$libresoc.v:31799$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45994,10 +46222,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31571$1027_Y + connect \Y $or$libresoc.v:31799$1027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31574$1030 + cell $or $or$libresoc.v:31802$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46005,39 +46233,39 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31574$1030_Y + connect \Y $or$libresoc.v:31802$1030_Y end - attribute \src "libresoc.v:31533.7-31533.20" - process $proc$libresoc.v:31533$1036 + attribute \src "libresoc.v:31761.7-31761.20" + process $proc$libresoc.v:31761$1036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31557.7-31557.19" - process $proc$libresoc.v:31557$1037 + attribute \src "libresoc.v:31785.7-31785.19" + process $proc$libresoc.v:31785$1037 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31576.3-31577.27" - process $proc$libresoc.v:31576$1032 + attribute \src "libresoc.v:31804.3-31805.27" + process $proc$libresoc.v:31804$1032 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31578.3-31586.6" - process $proc$libresoc.v:31578$1033 + attribute \src "libresoc.v:31806.3-31814.6" + process $proc$libresoc.v:31806$1033 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31579.5-31579.29" + attribute \src "libresoc.v:31807.5-31807.29" switch \initial - attribute \src "libresoc.v:31579.9-31579.17" + attribute \src "libresoc.v:31807.9-31807.17" case 1'1 case end @@ -46053,49 +46281,49 @@ module \alui_l$15 sync always update \q_int$next $0\q_int$next[0:0]$1034 end - connect \$9 $and$libresoc.v:31568$1024_Y - connect \$11 $or$libresoc.v:31569$1025_Y - connect \$13 $not$libresoc.v:31570$1026_Y - connect \$15 $or$libresoc.v:31571$1027_Y - connect \$1 $not$libresoc.v:31572$1028_Y - connect \$3 $and$libresoc.v:31573$1029_Y - connect \$5 $or$libresoc.v:31574$1030_Y - connect \$7 $not$libresoc.v:31575$1031_Y + connect \$9 $and$libresoc.v:31796$1024_Y + connect \$11 $or$libresoc.v:31797$1025_Y + connect \$13 $not$libresoc.v:31798$1026_Y + connect \$15 $or$libresoc.v:31799$1027_Y + connect \$1 $not$libresoc.v:31800$1028_Y + connect \$3 $and$libresoc.v:31801$1029_Y + connect \$5 $or$libresoc.v:31802$1030_Y + connect \$7 $not$libresoc.v:31803$1031_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31594.1-31652.10" +attribute \src "libresoc.v:31822.1-31880.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" attribute \generator "nMigen" module \alui_l$28 - attribute \src "libresoc.v:31595.7-31595.20" + attribute \src "libresoc.v:31823.7-31823.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31640.3-31648.6" + attribute \src "libresoc.v:31868.3-31876.6" wire $0\q_int$next[0:0]$1048 - attribute \src "libresoc.v:31638.3-31639.27" + attribute \src "libresoc.v:31866.3-31867.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31640.3-31648.6" + attribute \src "libresoc.v:31868.3-31876.6" wire $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31619.7-31619.19" + attribute \src "libresoc.v:31847.7-31847.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31630.17-31630.96" - wire $and$libresoc.v:31630$1038_Y - attribute \src "libresoc.v:31635.17-31635.96" - wire $and$libresoc.v:31635$1043_Y - attribute \src "libresoc.v:31632.18-31632.94" - wire $not$libresoc.v:31632$1040_Y - attribute \src "libresoc.v:31634.17-31634.93" - wire $not$libresoc.v:31634$1042_Y - attribute \src "libresoc.v:31637.17-31637.93" - wire $not$libresoc.v:31637$1045_Y - attribute \src "libresoc.v:31631.18-31631.99" - wire $or$libresoc.v:31631$1039_Y - attribute \src "libresoc.v:31633.18-31633.100" - wire $or$libresoc.v:31633$1041_Y - attribute \src "libresoc.v:31636.17-31636.98" - wire $or$libresoc.v:31636$1044_Y + attribute \src "libresoc.v:31858.17-31858.96" + wire $and$libresoc.v:31858$1038_Y + attribute \src "libresoc.v:31863.17-31863.96" + wire $and$libresoc.v:31863$1043_Y + attribute \src "libresoc.v:31860.18-31860.94" + wire $not$libresoc.v:31860$1040_Y + attribute \src "libresoc.v:31862.17-31862.93" + wire $not$libresoc.v:31862$1042_Y + attribute \src "libresoc.v:31865.17-31865.93" + wire $not$libresoc.v:31865$1045_Y + attribute \src "libresoc.v:31859.18-31859.99" + wire $or$libresoc.v:31859$1039_Y + attribute \src "libresoc.v:31861.18-31861.100" + wire $or$libresoc.v:31861$1041_Y + attribute \src "libresoc.v:31864.17-31864.98" + wire $or$libresoc.v:31864$1044_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46112,11 +46340,11 @@ module \alui_l$28 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31595.7-31595.15" + attribute \src "libresoc.v:31823.7-31823.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46133,7 +46361,7 @@ module \alui_l$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31630$1038 + cell $and $and$libresoc.v:31858$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46141,10 +46369,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31630$1038_Y + connect \Y $and$libresoc.v:31858$1038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31635$1043 + cell $and $and$libresoc.v:31863$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46152,34 +46380,34 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31635$1043_Y + connect \Y $and$libresoc.v:31863$1043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31632$1040 + cell $not $not$libresoc.v:31860$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31632$1040_Y + connect \Y $not$libresoc.v:31860$1040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31634$1042 + cell $not $not$libresoc.v:31862$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31634$1042_Y + connect \Y $not$libresoc.v:31862$1042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31637$1045 + cell $not $not$libresoc.v:31865$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31637$1045_Y + connect \Y $not$libresoc.v:31865$1045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31631$1039 + cell $or $or$libresoc.v:31859$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46187,10 +46415,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31631$1039_Y + connect \Y $or$libresoc.v:31859$1039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31633$1041 + cell $or $or$libresoc.v:31861$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46198,10 +46426,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31633$1041_Y + connect \Y $or$libresoc.v:31861$1041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31636$1044 + cell $or $or$libresoc.v:31864$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46209,39 +46437,39 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31636$1044_Y + connect \Y $or$libresoc.v:31864$1044_Y end - attribute \src "libresoc.v:31595.7-31595.20" - process $proc$libresoc.v:31595$1050 + attribute \src "libresoc.v:31823.7-31823.20" + process $proc$libresoc.v:31823$1050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31619.7-31619.19" - process $proc$libresoc.v:31619$1051 + attribute \src "libresoc.v:31847.7-31847.19" + process $proc$libresoc.v:31847$1051 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31638.3-31639.27" - process $proc$libresoc.v:31638$1046 + attribute \src "libresoc.v:31866.3-31867.27" + process $proc$libresoc.v:31866$1046 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31640.3-31648.6" - process $proc$libresoc.v:31640$1047 + attribute \src "libresoc.v:31868.3-31876.6" + process $proc$libresoc.v:31868$1047 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31641.5-31641.29" + attribute \src "libresoc.v:31869.5-31869.29" switch \initial - attribute \src "libresoc.v:31641.9-31641.17" + attribute \src "libresoc.v:31869.9-31869.17" case 1'1 case end @@ -46257,49 +46485,49 @@ module \alui_l$28 sync always update \q_int$next $0\q_int$next[0:0]$1048 end - connect \$9 $and$libresoc.v:31630$1038_Y - connect \$11 $or$libresoc.v:31631$1039_Y - connect \$13 $not$libresoc.v:31632$1040_Y - connect \$15 $or$libresoc.v:31633$1041_Y - connect \$1 $not$libresoc.v:31634$1042_Y - connect \$3 $and$libresoc.v:31635$1043_Y - connect \$5 $or$libresoc.v:31636$1044_Y - connect \$7 $not$libresoc.v:31637$1045_Y + connect \$9 $and$libresoc.v:31858$1038_Y + connect \$11 $or$libresoc.v:31859$1039_Y + connect \$13 $not$libresoc.v:31860$1040_Y + connect \$15 $or$libresoc.v:31861$1041_Y + connect \$1 $not$libresoc.v:31862$1042_Y + connect \$3 $and$libresoc.v:31863$1043_Y + connect \$5 $or$libresoc.v:31864$1044_Y + connect \$7 $not$libresoc.v:31865$1045_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31656.1-31714.10" +attribute \src "libresoc.v:31884.1-31942.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" attribute \generator "nMigen" module \alui_l$44 - attribute \src "libresoc.v:31657.7-31657.20" + attribute \src "libresoc.v:31885.7-31885.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31702.3-31710.6" + attribute \src "libresoc.v:31930.3-31938.6" wire $0\q_int$next[0:0]$1062 - attribute \src "libresoc.v:31700.3-31701.27" + attribute \src "libresoc.v:31928.3-31929.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31702.3-31710.6" + attribute \src "libresoc.v:31930.3-31938.6" wire $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31681.7-31681.19" + attribute \src "libresoc.v:31909.7-31909.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31692.17-31692.96" - wire $and$libresoc.v:31692$1052_Y - attribute \src "libresoc.v:31697.17-31697.96" - wire $and$libresoc.v:31697$1057_Y - attribute \src "libresoc.v:31694.18-31694.94" - wire $not$libresoc.v:31694$1054_Y - attribute \src "libresoc.v:31696.17-31696.93" - wire $not$libresoc.v:31696$1056_Y - attribute \src "libresoc.v:31699.17-31699.93" - wire $not$libresoc.v:31699$1059_Y - attribute \src "libresoc.v:31693.18-31693.99" - wire $or$libresoc.v:31693$1053_Y - attribute \src "libresoc.v:31695.18-31695.100" - wire $or$libresoc.v:31695$1055_Y - attribute \src "libresoc.v:31698.17-31698.98" - wire $or$libresoc.v:31698$1058_Y + attribute \src "libresoc.v:31920.17-31920.96" + wire $and$libresoc.v:31920$1052_Y + attribute \src "libresoc.v:31925.17-31925.96" + wire $and$libresoc.v:31925$1057_Y + attribute \src "libresoc.v:31922.18-31922.94" + wire $not$libresoc.v:31922$1054_Y + attribute \src "libresoc.v:31924.17-31924.93" + wire $not$libresoc.v:31924$1056_Y + attribute \src "libresoc.v:31927.17-31927.93" + wire $not$libresoc.v:31927$1059_Y + attribute \src "libresoc.v:31921.18-31921.99" + wire $or$libresoc.v:31921$1053_Y + attribute \src "libresoc.v:31923.18-31923.100" + wire $or$libresoc.v:31923$1055_Y + attribute \src "libresoc.v:31926.17-31926.98" + wire $or$libresoc.v:31926$1058_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46316,11 +46544,11 @@ module \alui_l$44 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31657.7-31657.15" + attribute \src "libresoc.v:31885.7-31885.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46337,7 +46565,7 @@ module \alui_l$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31692$1052 + cell $and $and$libresoc.v:31920$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46345,10 +46573,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31692$1052_Y + connect \Y $and$libresoc.v:31920$1052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31697$1057 + cell $and $and$libresoc.v:31925$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46356,34 +46584,34 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31697$1057_Y + connect \Y $and$libresoc.v:31925$1057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31694$1054 + cell $not $not$libresoc.v:31922$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31694$1054_Y + connect \Y $not$libresoc.v:31922$1054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31696$1056 + cell $not $not$libresoc.v:31924$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31696$1056_Y + connect \Y $not$libresoc.v:31924$1056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31699$1059 + cell $not $not$libresoc.v:31927$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31699$1059_Y + connect \Y $not$libresoc.v:31927$1059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31693$1053 + cell $or $or$libresoc.v:31921$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46391,10 +46619,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31693$1053_Y + connect \Y $or$libresoc.v:31921$1053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31695$1055 + cell $or $or$libresoc.v:31923$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46402,10 +46630,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31695$1055_Y + connect \Y $or$libresoc.v:31923$1055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31698$1058 + cell $or $or$libresoc.v:31926$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46413,39 +46641,39 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31698$1058_Y + connect \Y $or$libresoc.v:31926$1058_Y end - attribute \src "libresoc.v:31657.7-31657.20" - process $proc$libresoc.v:31657$1064 + attribute \src "libresoc.v:31885.7-31885.20" + process $proc$libresoc.v:31885$1064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31681.7-31681.19" - process $proc$libresoc.v:31681$1065 + attribute \src "libresoc.v:31909.7-31909.19" + process $proc$libresoc.v:31909$1065 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31700.3-31701.27" - process $proc$libresoc.v:31700$1060 + attribute \src "libresoc.v:31928.3-31929.27" + process $proc$libresoc.v:31928$1060 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31702.3-31710.6" - process $proc$libresoc.v:31702$1061 + attribute \src "libresoc.v:31930.3-31938.6" + process $proc$libresoc.v:31930$1061 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31703.5-31703.29" + attribute \src "libresoc.v:31931.5-31931.29" switch \initial - attribute \src "libresoc.v:31703.9-31703.17" + attribute \src "libresoc.v:31931.9-31931.17" case 1'1 case end @@ -46461,49 +46689,49 @@ module \alui_l$44 sync always update \q_int$next $0\q_int$next[0:0]$1062 end - connect \$9 $and$libresoc.v:31692$1052_Y - connect \$11 $or$libresoc.v:31693$1053_Y - connect \$13 $not$libresoc.v:31694$1054_Y - connect \$15 $or$libresoc.v:31695$1055_Y - connect \$1 $not$libresoc.v:31696$1056_Y - connect \$3 $and$libresoc.v:31697$1057_Y - connect \$5 $or$libresoc.v:31698$1058_Y - connect \$7 $not$libresoc.v:31699$1059_Y + connect \$9 $and$libresoc.v:31920$1052_Y + connect \$11 $or$libresoc.v:31921$1053_Y + connect \$13 $not$libresoc.v:31922$1054_Y + connect \$15 $or$libresoc.v:31923$1055_Y + connect \$1 $not$libresoc.v:31924$1056_Y + connect \$3 $and$libresoc.v:31925$1057_Y + connect \$5 $or$libresoc.v:31926$1058_Y + connect \$7 $not$libresoc.v:31927$1059_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31718.1-31776.10" +attribute \src "libresoc.v:31946.1-32004.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" attribute \generator "nMigen" module \alui_l$60 - attribute \src "libresoc.v:31719.7-31719.20" + attribute \src "libresoc.v:31947.7-31947.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31764.3-31772.6" + attribute \src "libresoc.v:31992.3-32000.6" wire $0\q_int$next[0:0]$1076 - attribute \src "libresoc.v:31762.3-31763.27" + attribute \src "libresoc.v:31990.3-31991.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31764.3-31772.6" + attribute \src "libresoc.v:31992.3-32000.6" wire $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31743.7-31743.19" + attribute \src "libresoc.v:31971.7-31971.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31754.17-31754.96" - wire $and$libresoc.v:31754$1066_Y - attribute \src "libresoc.v:31759.17-31759.96" - wire $and$libresoc.v:31759$1071_Y - attribute \src "libresoc.v:31756.18-31756.94" - wire $not$libresoc.v:31756$1068_Y - attribute \src "libresoc.v:31758.17-31758.93" - wire $not$libresoc.v:31758$1070_Y - attribute \src "libresoc.v:31761.17-31761.93" - wire $not$libresoc.v:31761$1073_Y - attribute \src "libresoc.v:31755.18-31755.99" - wire $or$libresoc.v:31755$1067_Y - attribute \src "libresoc.v:31757.18-31757.100" - wire $or$libresoc.v:31757$1069_Y - attribute \src "libresoc.v:31760.17-31760.98" - wire $or$libresoc.v:31760$1072_Y + attribute \src "libresoc.v:31982.17-31982.96" + wire $and$libresoc.v:31982$1066_Y + attribute \src "libresoc.v:31987.17-31987.96" + wire $and$libresoc.v:31987$1071_Y + attribute \src "libresoc.v:31984.18-31984.94" + wire $not$libresoc.v:31984$1068_Y + attribute \src "libresoc.v:31986.17-31986.93" + wire $not$libresoc.v:31986$1070_Y + attribute \src "libresoc.v:31989.17-31989.93" + wire $not$libresoc.v:31989$1073_Y + attribute \src "libresoc.v:31983.18-31983.99" + wire $or$libresoc.v:31983$1067_Y + attribute \src "libresoc.v:31985.18-31985.100" + wire $or$libresoc.v:31985$1069_Y + attribute \src "libresoc.v:31988.17-31988.98" + wire $or$libresoc.v:31988$1072_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46520,11 +46748,11 @@ module \alui_l$60 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31719.7-31719.15" + attribute \src "libresoc.v:31947.7-31947.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46541,7 +46769,7 @@ module \alui_l$60 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31754$1066 + cell $and $and$libresoc.v:31982$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46549,10 +46777,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31754$1066_Y + connect \Y $and$libresoc.v:31982$1066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31759$1071 + cell $and $and$libresoc.v:31987$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46560,34 +46788,34 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31759$1071_Y + connect \Y $and$libresoc.v:31987$1071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31756$1068 + cell $not $not$libresoc.v:31984$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31756$1068_Y + connect \Y $not$libresoc.v:31984$1068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31758$1070 + cell $not $not$libresoc.v:31986$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31758$1070_Y + connect \Y $not$libresoc.v:31986$1070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31761$1073 + cell $not $not$libresoc.v:31989$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31761$1073_Y + connect \Y $not$libresoc.v:31989$1073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31755$1067 + cell $or $or$libresoc.v:31983$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46595,10 +46823,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31755$1067_Y + connect \Y $or$libresoc.v:31983$1067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31757$1069 + cell $or $or$libresoc.v:31985$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46606,10 +46834,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31757$1069_Y + connect \Y $or$libresoc.v:31985$1069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31760$1072 + cell $or $or$libresoc.v:31988$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46617,39 +46845,39 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31760$1072_Y + connect \Y $or$libresoc.v:31988$1072_Y end - attribute \src "libresoc.v:31719.7-31719.20" - process $proc$libresoc.v:31719$1078 + attribute \src "libresoc.v:31947.7-31947.20" + process $proc$libresoc.v:31947$1078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31743.7-31743.19" - process $proc$libresoc.v:31743$1079 + attribute \src "libresoc.v:31971.7-31971.19" + process $proc$libresoc.v:31971$1079 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31762.3-31763.27" - process $proc$libresoc.v:31762$1074 + attribute \src "libresoc.v:31990.3-31991.27" + process $proc$libresoc.v:31990$1074 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31764.3-31772.6" - process $proc$libresoc.v:31764$1075 + attribute \src "libresoc.v:31992.3-32000.6" + process $proc$libresoc.v:31992$1075 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31765.5-31765.29" + attribute \src "libresoc.v:31993.5-31993.29" switch \initial - attribute \src "libresoc.v:31765.9-31765.17" + attribute \src "libresoc.v:31993.9-31993.17" case 1'1 case end @@ -46665,49 +46893,49 @@ module \alui_l$60 sync always update \q_int$next $0\q_int$next[0:0]$1076 end - connect \$9 $and$libresoc.v:31754$1066_Y - connect \$11 $or$libresoc.v:31755$1067_Y - connect \$13 $not$libresoc.v:31756$1068_Y - connect \$15 $or$libresoc.v:31757$1069_Y - connect \$1 $not$libresoc.v:31758$1070_Y - connect \$3 $and$libresoc.v:31759$1071_Y - connect \$5 $or$libresoc.v:31760$1072_Y - connect \$7 $not$libresoc.v:31761$1073_Y + connect \$9 $and$libresoc.v:31982$1066_Y + connect \$11 $or$libresoc.v:31983$1067_Y + connect \$13 $not$libresoc.v:31984$1068_Y + connect \$15 $or$libresoc.v:31985$1069_Y + connect \$1 $not$libresoc.v:31986$1070_Y + connect \$3 $and$libresoc.v:31987$1071_Y + connect \$5 $or$libresoc.v:31988$1072_Y + connect \$7 $not$libresoc.v:31989$1073_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31780.1-31838.10" +attribute \src "libresoc.v:32008.1-32066.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" attribute \generator "nMigen" module \alui_l$72 - attribute \src "libresoc.v:31781.7-31781.20" + attribute \src "libresoc.v:32009.7-32009.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31826.3-31834.6" + attribute \src "libresoc.v:32054.3-32062.6" wire $0\q_int$next[0:0]$1090 - attribute \src "libresoc.v:31824.3-31825.27" + attribute \src "libresoc.v:32052.3-32053.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31826.3-31834.6" + attribute \src "libresoc.v:32054.3-32062.6" wire $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:31805.7-31805.19" + attribute \src "libresoc.v:32033.7-32033.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31816.17-31816.96" - wire $and$libresoc.v:31816$1080_Y - attribute \src "libresoc.v:31821.17-31821.96" - wire $and$libresoc.v:31821$1085_Y - attribute \src "libresoc.v:31818.18-31818.94" - wire $not$libresoc.v:31818$1082_Y - attribute \src "libresoc.v:31820.17-31820.93" - wire $not$libresoc.v:31820$1084_Y - attribute \src "libresoc.v:31823.17-31823.93" - wire $not$libresoc.v:31823$1087_Y - attribute \src "libresoc.v:31817.18-31817.99" - wire $or$libresoc.v:31817$1081_Y - attribute \src "libresoc.v:31819.18-31819.100" - wire $or$libresoc.v:31819$1083_Y - attribute \src "libresoc.v:31822.17-31822.98" - wire $or$libresoc.v:31822$1086_Y + attribute \src "libresoc.v:32044.17-32044.96" + wire $and$libresoc.v:32044$1080_Y + attribute \src "libresoc.v:32049.17-32049.96" + wire $and$libresoc.v:32049$1085_Y + attribute \src "libresoc.v:32046.18-32046.94" + wire $not$libresoc.v:32046$1082_Y + attribute \src "libresoc.v:32048.17-32048.93" + wire $not$libresoc.v:32048$1084_Y + attribute \src "libresoc.v:32051.17-32051.93" + wire $not$libresoc.v:32051$1087_Y + attribute \src "libresoc.v:32045.18-32045.99" + wire $or$libresoc.v:32045$1081_Y + attribute \src "libresoc.v:32047.18-32047.100" + wire $or$libresoc.v:32047$1083_Y + attribute \src "libresoc.v:32050.17-32050.98" + wire $or$libresoc.v:32050$1086_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46724,11 +46952,11 @@ module \alui_l$72 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31781.7-31781.15" + attribute \src "libresoc.v:32009.7-32009.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46745,7 +46973,7 @@ module \alui_l$72 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31816$1080 + cell $and $and$libresoc.v:32044$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46753,10 +46981,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31816$1080_Y + connect \Y $and$libresoc.v:32044$1080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31821$1085 + cell $and $and$libresoc.v:32049$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46764,34 +46992,34 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31821$1085_Y + connect \Y $and$libresoc.v:32049$1085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31818$1082 + cell $not $not$libresoc.v:32046$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31818$1082_Y + connect \Y $not$libresoc.v:32046$1082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31820$1084 + cell $not $not$libresoc.v:32048$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31820$1084_Y + connect \Y $not$libresoc.v:32048$1084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31823$1087 + cell $not $not$libresoc.v:32051$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31823$1087_Y + connect \Y $not$libresoc.v:32051$1087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31817$1081 + cell $or $or$libresoc.v:32045$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46799,10 +47027,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31817$1081_Y + connect \Y $or$libresoc.v:32045$1081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31819$1083 + cell $or $or$libresoc.v:32047$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46810,10 +47038,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31819$1083_Y + connect \Y $or$libresoc.v:32047$1083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31822$1086 + cell $or $or$libresoc.v:32050$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46821,39 +47049,39 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31822$1086_Y + connect \Y $or$libresoc.v:32050$1086_Y end - attribute \src "libresoc.v:31781.7-31781.20" - process $proc$libresoc.v:31781$1092 + attribute \src "libresoc.v:32009.7-32009.20" + process $proc$libresoc.v:32009$1092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31805.7-31805.19" - process $proc$libresoc.v:31805$1093 + attribute \src "libresoc.v:32033.7-32033.19" + process $proc$libresoc.v:32033$1093 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31824.3-31825.27" - process $proc$libresoc.v:31824$1088 + attribute \src "libresoc.v:32052.3-32053.27" + process $proc$libresoc.v:32052$1088 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31826.3-31834.6" - process $proc$libresoc.v:31826$1089 + attribute \src "libresoc.v:32054.3-32062.6" + process $proc$libresoc.v:32054$1089 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:31827.5-31827.29" + attribute \src "libresoc.v:32055.5-32055.29" switch \initial - attribute \src "libresoc.v:31827.9-31827.17" + attribute \src "libresoc.v:32055.9-32055.17" case 1'1 case end @@ -46869,49 +47097,49 @@ module \alui_l$72 sync always update \q_int$next $0\q_int$next[0:0]$1090 end - connect \$9 $and$libresoc.v:31816$1080_Y - connect \$11 $or$libresoc.v:31817$1081_Y - connect \$13 $not$libresoc.v:31818$1082_Y - connect \$15 $or$libresoc.v:31819$1083_Y - connect \$1 $not$libresoc.v:31820$1084_Y - connect \$3 $and$libresoc.v:31821$1085_Y - connect \$5 $or$libresoc.v:31822$1086_Y - connect \$7 $not$libresoc.v:31823$1087_Y + connect \$9 $and$libresoc.v:32044$1080_Y + connect \$11 $or$libresoc.v:32045$1081_Y + connect \$13 $not$libresoc.v:32046$1082_Y + connect \$15 $or$libresoc.v:32047$1083_Y + connect \$1 $not$libresoc.v:32048$1084_Y + connect \$3 $and$libresoc.v:32049$1085_Y + connect \$5 $or$libresoc.v:32050$1086_Y + connect \$7 $not$libresoc.v:32051$1087_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31842.1-31900.10" +attribute \src "libresoc.v:32070.1-32128.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alui_l" attribute \generator "nMigen" module \alui_l$89 - attribute \src "libresoc.v:31843.7-31843.20" + attribute \src "libresoc.v:32071.7-32071.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31888.3-31896.6" + attribute \src "libresoc.v:32116.3-32124.6" wire $0\q_int$next[0:0]$1104 - attribute \src "libresoc.v:31886.3-31887.27" + attribute \src "libresoc.v:32114.3-32115.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31888.3-31896.6" + attribute \src "libresoc.v:32116.3-32124.6" wire $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:31867.7-31867.19" + attribute \src "libresoc.v:32095.7-32095.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31878.17-31878.96" - wire $and$libresoc.v:31878$1094_Y - attribute \src "libresoc.v:31883.17-31883.96" - wire $and$libresoc.v:31883$1099_Y - attribute \src "libresoc.v:31880.18-31880.94" - wire $not$libresoc.v:31880$1096_Y - attribute \src "libresoc.v:31882.17-31882.93" - wire $not$libresoc.v:31882$1098_Y - attribute \src "libresoc.v:31885.17-31885.93" - wire $not$libresoc.v:31885$1101_Y - attribute \src "libresoc.v:31879.18-31879.99" - wire $or$libresoc.v:31879$1095_Y - attribute \src "libresoc.v:31881.18-31881.100" - wire $or$libresoc.v:31881$1097_Y - attribute \src "libresoc.v:31884.17-31884.98" - wire $or$libresoc.v:31884$1100_Y + attribute \src "libresoc.v:32106.17-32106.96" + wire $and$libresoc.v:32106$1094_Y + attribute \src "libresoc.v:32111.17-32111.96" + wire $and$libresoc.v:32111$1099_Y + attribute \src "libresoc.v:32108.18-32108.94" + wire $not$libresoc.v:32108$1096_Y + attribute \src "libresoc.v:32110.17-32110.93" + wire $not$libresoc.v:32110$1098_Y + attribute \src "libresoc.v:32113.17-32113.93" + wire $not$libresoc.v:32113$1101_Y + attribute \src "libresoc.v:32107.18-32107.99" + wire $or$libresoc.v:32107$1095_Y + attribute \src "libresoc.v:32109.18-32109.100" + wire $or$libresoc.v:32109$1097_Y + attribute \src "libresoc.v:32112.17-32112.98" + wire $or$libresoc.v:32112$1100_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46928,11 +47156,11 @@ module \alui_l$89 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:31843.7-31843.15" + attribute \src "libresoc.v:32071.7-32071.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46949,7 +47177,7 @@ module \alui_l$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31878$1094 + cell $and $and$libresoc.v:32106$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46957,10 +47185,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31878$1094_Y + connect \Y $and$libresoc.v:32106$1094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31883$1099 + cell $and $and$libresoc.v:32111$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46968,34 +47196,34 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31883$1099_Y + connect \Y $and$libresoc.v:32111$1099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31880$1096 + cell $not $not$libresoc.v:32108$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31880$1096_Y + connect \Y $not$libresoc.v:32108$1096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31882$1098 + cell $not $not$libresoc.v:32110$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31882$1098_Y + connect \Y $not$libresoc.v:32110$1098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31885$1101 + cell $not $not$libresoc.v:32113$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31885$1101_Y + connect \Y $not$libresoc.v:32113$1101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31879$1095 + cell $or $or$libresoc.v:32107$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47003,10 +47231,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31879$1095_Y + connect \Y $or$libresoc.v:32107$1095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31881$1097 + cell $or $or$libresoc.v:32109$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47014,10 +47242,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31881$1097_Y + connect \Y $or$libresoc.v:32109$1097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31884$1100 + cell $or $or$libresoc.v:32112$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47025,39 +47253,39 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31884$1100_Y + connect \Y $or$libresoc.v:32112$1100_Y end - attribute \src "libresoc.v:31843.7-31843.20" - process $proc$libresoc.v:31843$1106 + attribute \src "libresoc.v:32071.7-32071.20" + process $proc$libresoc.v:32071$1106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31867.7-31867.19" - process $proc$libresoc.v:31867$1107 + attribute \src "libresoc.v:32095.7-32095.19" + process $proc$libresoc.v:32095$1107 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31886.3-31887.27" - process $proc$libresoc.v:31886$1102 + attribute \src "libresoc.v:32114.3-32115.27" + process $proc$libresoc.v:32114$1102 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31888.3-31896.6" - process $proc$libresoc.v:31888$1103 + attribute \src "libresoc.v:32116.3-32124.6" + process $proc$libresoc.v:32116$1103 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1104 $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:31889.5-31889.29" + attribute \src "libresoc.v:32117.5-32117.29" switch \initial - attribute \src "libresoc.v:31889.9-31889.17" + attribute \src "libresoc.v:32117.9-32117.17" case 1'1 case end @@ -47073,75 +47301,75 @@ module \alui_l$89 sync always update \q_int$next $0\q_int$next[0:0]$1104 end - connect \$9 $and$libresoc.v:31878$1094_Y - connect \$11 $or$libresoc.v:31879$1095_Y - connect \$13 $not$libresoc.v:31880$1096_Y - connect \$15 $or$libresoc.v:31881$1097_Y - connect \$1 $not$libresoc.v:31882$1098_Y - connect \$3 $and$libresoc.v:31883$1099_Y - connect \$5 $or$libresoc.v:31884$1100_Y - connect \$7 $not$libresoc.v:31885$1101_Y + connect \$9 $and$libresoc.v:32106$1094_Y + connect \$11 $or$libresoc.v:32107$1095_Y + connect \$13 $not$libresoc.v:32108$1096_Y + connect \$15 $or$libresoc.v:32109$1097_Y + connect \$1 $not$libresoc.v:32110$1098_Y + connect \$3 $and$libresoc.v:32111$1099_Y + connect \$5 $or$libresoc.v:32112$1100_Y + connect \$7 $not$libresoc.v:32113$1101_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31904.1-33248.10" +attribute \src "libresoc.v:32132.1-33476.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" attribute \generator "nMigen" module \bpermd - attribute \src "libresoc.v:31905.7-31905.20" + attribute \src "libresoc.v:32133.7-32133.20" wire $0\initial[0:0] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire width 64 $0\perm[63:0] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $10\perm[4:4] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $11\perm[5:5] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $12\perm[5:5] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $13\perm[6:6] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $14\perm[6:6] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $15\perm[7:7] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $16\perm[7:7] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $1\perm[0:0] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $2\perm[0:0] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $3\perm[1:1] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $4\perm[1:1] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $5\perm[2:2] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $6\perm[2:2] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $7\perm[3:3] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $8\perm[3:3] - attribute \src "libresoc.v:32082.3-33173.6" + attribute \src "libresoc.v:32310.3-33401.6" wire $9\perm[4:4] - attribute \src "libresoc.v:32074.17-32074.104" - wire $lt$libresoc.v:32074$1108_Y - attribute \src "libresoc.v:32075.18-32075.105" - wire $lt$libresoc.v:32075$1109_Y - attribute \src "libresoc.v:32076.18-32076.105" - wire $lt$libresoc.v:32076$1110_Y - attribute \src "libresoc.v:32077.18-32077.105" - wire $lt$libresoc.v:32077$1111_Y - attribute \src "libresoc.v:32078.17-32078.104" - wire $lt$libresoc.v:32078$1112_Y - attribute \src "libresoc.v:32079.17-32079.104" - wire $lt$libresoc.v:32079$1113_Y - attribute \src "libresoc.v:32080.17-32080.104" - wire $lt$libresoc.v:32080$1114_Y - attribute \src "libresoc.v:32081.17-32081.104" - wire $lt$libresoc.v:32081$1115_Y + attribute \src "libresoc.v:32302.17-32302.104" + wire $lt$libresoc.v:32302$1108_Y + attribute \src "libresoc.v:32303.18-32303.105" + wire $lt$libresoc.v:32303$1109_Y + attribute \src "libresoc.v:32304.18-32304.105" + wire $lt$libresoc.v:32304$1110_Y + attribute \src "libresoc.v:32305.18-32305.105" + wire $lt$libresoc.v:32305$1111_Y + attribute \src "libresoc.v:32306.17-32306.104" + wire $lt$libresoc.v:32306$1112_Y + attribute \src "libresoc.v:32307.17-32307.104" + wire $lt$libresoc.v:32307$1113_Y + attribute \src "libresoc.v:32308.17-32308.104" + wire $lt$libresoc.v:32308$1114_Y + attribute \src "libresoc.v:32309.17-32309.104" + wire $lt$libresoc.v:32309$1115_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" @@ -47174,7 +47402,7 @@ module \bpermd wire width 8 \idx_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_7 - attribute \src "libresoc.v:31905.7-31905.15" + attribute \src "libresoc.v:32133.7-32133.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" wire width 64 \perm @@ -47313,7 +47541,7 @@ module \bpermd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 input 3 \rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32074$1108 + cell $lt $lt$libresoc.v:32302$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47321,10 +47549,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_4 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32074$1108_Y + connect \Y $lt$libresoc.v:32302$1108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32075$1109 + cell $lt $lt$libresoc.v:32303$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47332,10 +47560,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_5 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32075$1109_Y + connect \Y $lt$libresoc.v:32303$1109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32076$1110 + cell $lt $lt$libresoc.v:32304$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47343,10 +47571,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_6 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32076$1110_Y + connect \Y $lt$libresoc.v:32304$1110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32077$1111 + cell $lt $lt$libresoc.v:32305$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47354,10 +47582,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_7 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32077$1111_Y + connect \Y $lt$libresoc.v:32305$1111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32078$1112 + cell $lt $lt$libresoc.v:32306$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47365,10 +47593,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_0 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32078$1112_Y + connect \Y $lt$libresoc.v:32306$1112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32079$1113 + cell $lt $lt$libresoc.v:32307$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47376,10 +47604,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_1 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32079$1113_Y + connect \Y $lt$libresoc.v:32307$1113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32080$1114 + cell $lt $lt$libresoc.v:32308$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47387,10 +47615,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_2 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32080$1114_Y + connect \Y $lt$libresoc.v:32308$1114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32081$1115 + cell $lt $lt$libresoc.v:32309$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47398,18 +47626,18 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_3 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32081$1115_Y + connect \Y $lt$libresoc.v:32309$1115_Y end - attribute \src "libresoc.v:31905.7-31905.20" - process $proc$libresoc.v:31905$1117 + attribute \src "libresoc.v:32133.7-32133.20" + process $proc$libresoc.v:32133$1117 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:32082.3-33173.6" - process $proc$libresoc.v:32082$1116 + attribute \src "libresoc.v:32310.3-33401.6" + process $proc$libresoc.v:32310$1116 assign { } { } assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 assign $0\perm[63:0] [0] $1\perm[0:0] @@ -47420,9 +47648,9 @@ module \bpermd assign $0\perm[63:0] [5] $11\perm[5:5] assign $0\perm[63:0] [6] $13\perm[6:6] assign $0\perm[63:0] [7] $15\perm[7:7] - attribute \src "libresoc.v:32083.5-32083.29" + attribute \src "libresoc.v:32311.5-32311.29" switch \initial - attribute \src "libresoc.v:32083.9-32083.17" + attribute \src "libresoc.v:32311.9-32311.17" case 1'1 case end @@ -49589,14 +49817,14 @@ module \bpermd sync always update \perm $0\perm[63:0] end - connect \$9 $lt$libresoc.v:32074$1108_Y - connect \$11 $lt$libresoc.v:32075$1109_Y - connect \$13 $lt$libresoc.v:32076$1110_Y - connect \$15 $lt$libresoc.v:32077$1111_Y - connect \$1 $lt$libresoc.v:32078$1112_Y - connect \$3 $lt$libresoc.v:32079$1113_Y - connect \$5 $lt$libresoc.v:32080$1114_Y - connect \$7 $lt$libresoc.v:32081$1115_Y + connect \$9 $lt$libresoc.v:32302$1108_Y + connect \$11 $lt$libresoc.v:32303$1109_Y + connect \$13 $lt$libresoc.v:32304$1110_Y + connect \$15 $lt$libresoc.v:32305$1111_Y + connect \$1 $lt$libresoc.v:32306$1112_Y + connect \$3 $lt$libresoc.v:32307$1113_Y + connect \$5 $lt$libresoc.v:32308$1114_Y + connect \$7 $lt$libresoc.v:32309$1115_Y connect \ra [7:0] \perm [7:0] connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 connect \idx_7 \rs [63:56] @@ -49672,413 +49900,413 @@ module \bpermd connect \rb64_1 \rb [62] connect \rb64_0 \rb [63] end -attribute \src "libresoc.v:33252.1-34303.10" +attribute \src "libresoc.v:33480.1-34535.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" attribute \generator "nMigen" module \branch0 - attribute \src "libresoc.v:33920.3-33921.25" + attribute \src "libresoc.v:34152.3-34153.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 - attribute \src "libresoc.v:33880.3-33881.61" + attribute \src "libresoc.v:34112.3-34113.61" wire width 64 $0\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:34095.3-34119.6" - wire width 13 $0\alu_branch0_br_op__fn_unit$next[12:0]$1240 - attribute \src "libresoc.v:33884.3-33885.69" - wire width 13 $0\alu_branch0_br_op__fn_unit[12:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" + wire width 14 $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 + attribute \src "libresoc.v:34116.3-34117.69" + wire width 14 $0\alu_branch0_br_op__fn_unit[13:0] + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 - attribute \src "libresoc.v:33888.3-33889.83" + attribute \src "libresoc.v:34120.3-34121.83" wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 - attribute \src "libresoc.v:33890.3-33891.79" + attribute \src "libresoc.v:34122.3-34123.79" wire $0\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 - attribute \src "libresoc.v:33886.3-33887.63" + attribute \src "libresoc.v:34118.3-34119.63" wire width 32 $0\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 - attribute \src "libresoc.v:33882.3-33883.73" + attribute \src "libresoc.v:34114.3-34115.73" wire width 7 $0\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 - attribute \src "libresoc.v:33894.3-33895.71" + attribute \src "libresoc.v:34126.3-34127.71" wire $0\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $0\alu_branch0_br_op__lk$next[0:0]$1246 - attribute \src "libresoc.v:33892.3-33893.59" + attribute \src "libresoc.v:34124.3-34125.59" wire $0\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33918.3-33919.43" + attribute \src "libresoc.v:34150.3-34151.43" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:34225.3-34233.6" + attribute \src "libresoc.v:34457.3-34465.6" wire $0\alu_l_r_alu$next[0:0]$1294 - attribute \src "libresoc.v:33858.3-33859.39" + attribute \src "libresoc.v:34090.3-34091.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:34216.3-34224.6" + attribute \src "libresoc.v:34448.3-34456.6" wire $0\alui_l_r_alui$next[0:0]$1291 - attribute \src "libresoc.v:33860.3-33861.43" + attribute \src "libresoc.v:34092.3-34093.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:34120.3-34141.6" + attribute \src "libresoc.v:34352.3-34373.6" wire width 64 $0\data_r0__fast1$next[63:0]$1258 - attribute \src "libresoc.v:33876.3-33877.45" + attribute \src "libresoc.v:34108.3-34109.45" wire width 64 $0\data_r0__fast1[63:0] - attribute \src "libresoc.v:34120.3-34141.6" + attribute \src "libresoc.v:34352.3-34373.6" wire $0\data_r0__fast1_ok$next[0:0]$1259 - attribute \src "libresoc.v:33878.3-33879.51" + attribute \src "libresoc.v:34110.3-34111.51" wire $0\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:34142.3-34163.6" + attribute \src "libresoc.v:34374.3-34395.6" wire width 64 $0\data_r1__fast2$next[63:0]$1266 - attribute \src "libresoc.v:33872.3-33873.45" + attribute \src "libresoc.v:34104.3-34105.45" wire width 64 $0\data_r1__fast2[63:0] - attribute \src "libresoc.v:34142.3-34163.6" + attribute \src "libresoc.v:34374.3-34395.6" wire $0\data_r1__fast2_ok$next[0:0]$1267 - attribute \src "libresoc.v:33874.3-33875.51" + attribute \src "libresoc.v:34106.3-34107.51" wire $0\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:34164.3-34185.6" + attribute \src "libresoc.v:34396.3-34417.6" wire width 64 $0\data_r2__nia$next[63:0]$1274 - attribute \src "libresoc.v:33868.3-33869.41" + attribute \src "libresoc.v:34100.3-34101.41" wire width 64 $0\data_r2__nia[63:0] - attribute \src "libresoc.v:34164.3-34185.6" + attribute \src "libresoc.v:34396.3-34417.6" wire $0\data_r2__nia_ok$next[0:0]$1275 - attribute \src "libresoc.v:33870.3-33871.47" + attribute \src "libresoc.v:34102.3-34103.47" wire $0\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:34234.3-34243.6" + attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:34244.3-34253.6" + attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:34254.3-34263.6" + attribute \src "libresoc.v:34486.3-34495.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:33253.7-33253.20" + attribute \src "libresoc.v:33481.7-33481.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34050.3-34058.6" + attribute \src "libresoc.v:34282.3-34290.6" wire $0\opc_l_r_opc$next[0:0]$1224 - attribute \src "libresoc.v:33904.3-33905.39" + attribute \src "libresoc.v:34136.3-34137.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:34041.3-34049.6" + attribute \src "libresoc.v:34273.3-34281.6" wire $0\opc_l_s_opc$next[0:0]$1221 - attribute \src "libresoc.v:33906.3-33907.39" + attribute \src "libresoc.v:34138.3-34139.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34264.3-34272.6" + attribute \src "libresoc.v:34496.3-34504.6" wire width 3 $0\prev_wr_go$next[2:0]$1300 - attribute \src "libresoc.v:33916.3-33917.37" + attribute \src "libresoc.v:34148.3-34149.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:33995.3-34004.6" + attribute \src "libresoc.v:34227.3-34236.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:34086.3-34094.6" + attribute \src "libresoc.v:34318.3-34326.6" wire width 3 $0\req_l_r_req$next[2:0]$1236 - attribute \src "libresoc.v:33896.3-33897.39" + attribute \src "libresoc.v:34128.3-34129.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:34077.3-34085.6" + attribute \src "libresoc.v:34309.3-34317.6" wire width 3 $0\req_l_s_req$next[2:0]$1233 - attribute \src "libresoc.v:33898.3-33899.39" + attribute \src "libresoc.v:34130.3-34131.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:34014.3-34022.6" + attribute \src "libresoc.v:34246.3-34254.6" wire $0\rok_l_r_rdok$next[0:0]$1212 - attribute \src "libresoc.v:33912.3-33913.41" + attribute \src "libresoc.v:34144.3-34145.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:34005.3-34013.6" + attribute \src "libresoc.v:34237.3-34245.6" wire $0\rok_l_s_rdok$next[0:0]$1209 - attribute \src "libresoc.v:33914.3-33915.41" + attribute \src "libresoc.v:34146.3-34147.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:34032.3-34040.6" + attribute \src "libresoc.v:34264.3-34272.6" wire $0\rst_l_r_rst$next[0:0]$1218 - attribute \src "libresoc.v:33908.3-33909.39" + attribute \src "libresoc.v:34140.3-34141.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:34023.3-34031.6" + attribute \src "libresoc.v:34255.3-34263.6" wire $0\rst_l_s_rst$next[0:0]$1215 - attribute \src "libresoc.v:33910.3-33911.39" + attribute \src "libresoc.v:34142.3-34143.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:34068.3-34076.6" + attribute \src "libresoc.v:34300.3-34308.6" wire width 3 $0\src_l_r_src$next[2:0]$1230 - attribute \src "libresoc.v:33900.3-33901.39" + attribute \src "libresoc.v:34132.3-34133.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:34059.3-34067.6" + attribute \src "libresoc.v:34291.3-34299.6" wire width 3 $0\src_l_s_src$next[2:0]$1227 - attribute \src "libresoc.v:33902.3-33903.39" + attribute \src "libresoc.v:34134.3-34135.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:34186.3-34195.6" + attribute \src "libresoc.v:34418.3-34427.6" wire width 64 $0\src_r0$next[63:0]$1282 - attribute \src "libresoc.v:33866.3-33867.29" + attribute \src "libresoc.v:34098.3-34099.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:34196.3-34205.6" + attribute \src "libresoc.v:34428.3-34437.6" wire width 64 $0\src_r1$next[63:0]$1285 - attribute \src "libresoc.v:33864.3-33865.29" + attribute \src "libresoc.v:34096.3-34097.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:34206.3-34215.6" + attribute \src "libresoc.v:34438.3-34447.6" wire width 4 $0\src_r2$next[3:0]$1288 - attribute \src "libresoc.v:33862.3-33863.29" + attribute \src "libresoc.v:34094.3-34095.29" wire width 4 $0\src_r2[3:0] - attribute \src "libresoc.v:33371.7-33371.24" + attribute \src "libresoc.v:33599.7-33599.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 - attribute \src "libresoc.v:33379.14-33379.59" + attribute \src "libresoc.v:33607.14-33607.59" wire width 64 $1\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:34095.3-34119.6" - wire width 13 $1\alu_branch0_br_op__fn_unit$next[12:0]$1248 - attribute \src "libresoc.v:33397.14-33397.51" - wire width 13 $1\alu_branch0_br_op__fn_unit[12:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" + wire width 14 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 + attribute \src "libresoc.v:33626.14-33626.51" + wire width 14 $1\alu_branch0_br_op__fn_unit[13:0] + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 - attribute \src "libresoc.v:33401.14-33401.70" + attribute \src "libresoc.v:33630.14-33630.70" wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 - attribute \src "libresoc.v:33405.7-33405.45" + attribute \src "libresoc.v:33634.7-33634.45" wire $1\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1251 - attribute \src "libresoc.v:33409.14-33409.45" + attribute \src "libresoc.v:33638.14-33638.45" wire width 32 $1\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 - attribute \src "libresoc.v:33487.13-33487.49" + attribute \src "libresoc.v:33717.13-33717.49" wire width 7 $1\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 - attribute \src "libresoc.v:33491.7-33491.41" + attribute \src "libresoc.v:33721.7-33721.41" wire $1\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $1\alu_branch0_br_op__lk$next[0:0]$1254 - attribute \src "libresoc.v:33495.7-33495.35" + attribute \src "libresoc.v:33725.7-33725.35" wire $1\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33521.7-33521.26" + attribute \src "libresoc.v:33751.7-33751.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:34225.3-34233.6" + attribute \src "libresoc.v:34457.3-34465.6" wire $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:33529.7-33529.25" + attribute \src "libresoc.v:33759.7-33759.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:34216.3-34224.6" + attribute \src "libresoc.v:34448.3-34456.6" wire $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:33541.7-33541.27" + attribute \src "libresoc.v:33771.7-33771.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:34120.3-34141.6" + attribute \src "libresoc.v:34352.3-34373.6" wire width 64 $1\data_r0__fast1$next[63:0]$1260 - attribute \src "libresoc.v:33573.14-33573.51" + attribute \src "libresoc.v:33803.14-33803.51" wire width 64 $1\data_r0__fast1[63:0] - attribute \src "libresoc.v:34120.3-34141.6" + attribute \src "libresoc.v:34352.3-34373.6" wire $1\data_r0__fast1_ok$next[0:0]$1261 - attribute \src "libresoc.v:33577.7-33577.31" + attribute \src "libresoc.v:33807.7-33807.31" wire $1\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:34142.3-34163.6" + attribute \src "libresoc.v:34374.3-34395.6" wire width 64 $1\data_r1__fast2$next[63:0]$1268 - attribute \src "libresoc.v:33581.14-33581.51" + attribute \src "libresoc.v:33811.14-33811.51" wire width 64 $1\data_r1__fast2[63:0] - attribute \src "libresoc.v:34142.3-34163.6" + attribute \src "libresoc.v:34374.3-34395.6" wire $1\data_r1__fast2_ok$next[0:0]$1269 - attribute \src "libresoc.v:33585.7-33585.31" + attribute \src "libresoc.v:33815.7-33815.31" wire $1\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:34164.3-34185.6" + attribute \src "libresoc.v:34396.3-34417.6" wire width 64 $1\data_r2__nia$next[63:0]$1276 - attribute \src "libresoc.v:33589.14-33589.49" + attribute \src "libresoc.v:33819.14-33819.49" wire width 64 $1\data_r2__nia[63:0] - attribute \src "libresoc.v:34164.3-34185.6" + attribute \src "libresoc.v:34396.3-34417.6" wire $1\data_r2__nia_ok$next[0:0]$1277 - attribute \src "libresoc.v:33593.7-33593.29" + attribute \src "libresoc.v:33823.7-33823.29" wire $1\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:34234.3-34243.6" + attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:34244.3-34253.6" + attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:34254.3-34263.6" + attribute \src "libresoc.v:34486.3-34495.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:34050.3-34058.6" + attribute \src "libresoc.v:34282.3-34290.6" wire $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:33614.7-33614.25" + attribute \src "libresoc.v:33844.7-33844.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:34041.3-34049.6" + attribute \src "libresoc.v:34273.3-34281.6" wire $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:33618.7-33618.25" + attribute \src "libresoc.v:33848.7-33848.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34264.3-34272.6" + attribute \src "libresoc.v:34496.3-34504.6" wire width 3 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:33726.13-33726.30" + attribute \src "libresoc.v:33958.13-33958.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:33995.3-34004.6" + attribute \src "libresoc.v:34227.3-34236.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:34086.3-34094.6" + attribute \src "libresoc.v:34318.3-34326.6" wire width 3 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:33734.13-33734.31" + attribute \src "libresoc.v:33966.13-33966.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:34077.3-34085.6" + attribute \src "libresoc.v:34309.3-34317.6" wire width 3 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:33738.13-33738.31" + attribute \src "libresoc.v:33970.13-33970.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:34014.3-34022.6" + attribute \src "libresoc.v:34246.3-34254.6" wire $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:33750.7-33750.26" + attribute \src "libresoc.v:33982.7-33982.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:34005.3-34013.6" + attribute \src "libresoc.v:34237.3-34245.6" wire $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:33754.7-33754.26" + attribute \src "libresoc.v:33986.7-33986.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:34032.3-34040.6" + attribute \src "libresoc.v:34264.3-34272.6" wire $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:33758.7-33758.25" + attribute \src "libresoc.v:33990.7-33990.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:34023.3-34031.6" + attribute \src "libresoc.v:34255.3-34263.6" wire $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:33762.7-33762.25" + attribute \src "libresoc.v:33994.7-33994.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:34068.3-34076.6" + attribute \src "libresoc.v:34300.3-34308.6" wire width 3 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:33776.13-33776.31" + attribute \src "libresoc.v:34008.13-34008.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:34059.3-34067.6" + attribute \src "libresoc.v:34291.3-34299.6" wire width 3 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:33780.13-33780.31" + attribute \src "libresoc.v:34012.13-34012.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:34186.3-34195.6" + attribute \src "libresoc.v:34418.3-34427.6" wire width 64 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:33786.14-33786.43" + attribute \src "libresoc.v:34018.14-34018.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:34196.3-34205.6" + attribute \src "libresoc.v:34428.3-34437.6" wire width 64 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:33790.14-33790.43" + attribute \src "libresoc.v:34022.14-34022.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:34206.3-34215.6" + attribute \src "libresoc.v:34438.3-34447.6" wire width 4 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:33794.13-33794.26" + attribute \src "libresoc.v:34026.13-34026.26" wire width 4 $1\src_r2[3:0] - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 - attribute \src "libresoc.v:34095.3-34119.6" + attribute \src "libresoc.v:34327.3-34351.6" wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:34120.3-34141.6" + attribute \src "libresoc.v:34352.3-34373.6" wire width 64 $2\data_r0__fast1$next[63:0]$1262 - attribute \src "libresoc.v:34120.3-34141.6" + attribute \src "libresoc.v:34352.3-34373.6" wire $2\data_r0__fast1_ok$next[0:0]$1263 - attribute \src "libresoc.v:34142.3-34163.6" + attribute \src "libresoc.v:34374.3-34395.6" wire width 64 $2\data_r1__fast2$next[63:0]$1270 - attribute \src "libresoc.v:34142.3-34163.6" + attribute \src "libresoc.v:34374.3-34395.6" wire $2\data_r1__fast2_ok$next[0:0]$1271 - attribute \src "libresoc.v:34164.3-34185.6" + attribute \src "libresoc.v:34396.3-34417.6" wire width 64 $2\data_r2__nia$next[63:0]$1278 - attribute \src "libresoc.v:34164.3-34185.6" + attribute \src "libresoc.v:34396.3-34417.6" wire $2\data_r2__nia_ok$next[0:0]$1279 - attribute \src "libresoc.v:34120.3-34141.6" + attribute \src "libresoc.v:34352.3-34373.6" wire $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:34142.3-34163.6" + attribute \src "libresoc.v:34374.3-34395.6" wire $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:34164.3-34185.6" + attribute \src "libresoc.v:34396.3-34417.6" wire $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:33802.18-33802.112" - wire width 3 $and$libresoc.v:33802$1119_Y - attribute \src "libresoc.v:33803.19-33803.125" - wire $and$libresoc.v:33803$1120_Y - attribute \src "libresoc.v:33804.19-33804.125" - wire $and$libresoc.v:33804$1121_Y - attribute \src "libresoc.v:33805.19-33805.125" - wire $and$libresoc.v:33805$1122_Y - attribute \src "libresoc.v:33806.19-33806.141" - wire width 3 $and$libresoc.v:33806$1123_Y - attribute \src "libresoc.v:33807.19-33807.121" - wire width 3 $and$libresoc.v:33807$1124_Y - attribute \src "libresoc.v:33808.19-33808.127" - wire $and$libresoc.v:33808$1125_Y - attribute \src "libresoc.v:33809.19-33809.127" - wire $and$libresoc.v:33809$1126_Y - attribute \src "libresoc.v:33810.19-33810.127" - wire $and$libresoc.v:33810$1127_Y - attribute \src "libresoc.v:33811.18-33811.110" - wire $and$libresoc.v:33811$1128_Y - attribute \src "libresoc.v:33813.18-33813.98" - wire $and$libresoc.v:33813$1130_Y - attribute \src "libresoc.v:33815.18-33815.100" - wire $and$libresoc.v:33815$1132_Y - attribute \src "libresoc.v:33816.18-33816.149" - wire width 3 $and$libresoc.v:33816$1133_Y - attribute \src "libresoc.v:33818.18-33818.119" - wire width 3 $and$libresoc.v:33818$1135_Y - attribute \src "libresoc.v:33821.18-33821.116" - wire $and$libresoc.v:33821$1138_Y - attribute \src "libresoc.v:33825.17-33825.123" - wire $and$libresoc.v:33825$1142_Y - attribute \src "libresoc.v:33827.18-33827.113" - wire $and$libresoc.v:33827$1144_Y - attribute \src "libresoc.v:33828.18-33828.125" - wire width 3 $and$libresoc.v:33828$1145_Y - attribute \src "libresoc.v:33830.18-33830.112" - wire $and$libresoc.v:33830$1147_Y - attribute \src "libresoc.v:33832.18-33832.129" - wire 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\src "libresoc.v:34064.18-34064.129" + wire $and$libresoc.v:34064$1149_Y + attribute \src "libresoc.v:34065.18-34065.129" + wire $and$libresoc.v:34065$1150_Y + attribute \src "libresoc.v:34066.18-34066.117" + wire $and$libresoc.v:34066$1151_Y + attribute \src "libresoc.v:34071.18-34071.133" + wire $and$libresoc.v:34071$1156_Y + attribute \src "libresoc.v:34072.18-34072.124" + wire width 3 $and$libresoc.v:34072$1157_Y + attribute \src "libresoc.v:34075.18-34075.120" + wire $and$libresoc.v:34075$1160_Y + attribute \src "libresoc.v:34076.18-34076.120" + wire $and$libresoc.v:34076$1161_Y + attribute \src "libresoc.v:34077.18-34077.118" + wire $and$libresoc.v:34077$1162_Y + attribute \src "libresoc.v:34083.18-34083.137" + wire $and$libresoc.v:34083$1168_Y + attribute \src "libresoc.v:34085.18-34085.135" + wire $and$libresoc.v:34085$1170_Y + attribute \src "libresoc.v:34086.18-34086.149" + wire width 3 $and$libresoc.v:34086$1171_Y + attribute \src "libresoc.v:34088.18-34088.129" + wire width 3 $and$libresoc.v:34088$1173_Y + attribute \src "libresoc.v:34061.18-34061.113" + wire $eq$libresoc.v:34061$1146_Y + attribute \src "libresoc.v:34063.18-34063.119" + wire $eq$libresoc.v:34063$1148_Y + attribute \src "libresoc.v:34044.18-34044.97" + wire $not$libresoc.v:34044$1129_Y + attribute \src "libresoc.v:34046.18-34046.99" + wire $not$libresoc.v:34046$1131_Y + attribute \src "libresoc.v:34049.18-34049.113" + wire width 3 $not$libresoc.v:34049$1134_Y + attribute \src "libresoc.v:34052.18-34052.106" + wire $not$libresoc.v:34052$1137_Y + attribute \src "libresoc.v:34058.18-34058.123" + wire $not$libresoc.v:34058$1143_Y + attribute \src "libresoc.v:34073.17-34073.113" + wire width 3 $not$libresoc.v:34073$1158_Y + attribute \src "libresoc.v:34087.18-34087.133" + wire $not$libresoc.v:34087$1172_Y + attribute \src "libresoc.v:34089.18-34089.114" + wire width 3 $not$libresoc.v:34089$1174_Y + attribute \src "libresoc.v:34056.18-34056.112" + wire $or$libresoc.v:34056$1141_Y + attribute \src "libresoc.v:34067.18-34067.122" + wire $or$libresoc.v:34067$1152_Y + attribute \src "libresoc.v:34068.18-34068.124" + wire $or$libresoc.v:34068$1153_Y + attribute \src "libresoc.v:34069.18-34069.155" + wire width 3 $or$libresoc.v:34069$1154_Y + attribute \src "libresoc.v:34070.18-34070.155" + wire width 3 $or$libresoc.v:34070$1155_Y + attribute \src "libresoc.v:34074.18-34074.120" + wire width 3 $or$libresoc.v:34074$1159_Y + attribute \src "libresoc.v:34084.17-34084.117" + wire width 3 $or$libresoc.v:34084$1169_Y + attribute \src "libresoc.v:34033.17-34033.104" + wire $reduce_and$libresoc.v:34033$1118_Y + attribute \src "libresoc.v:34051.18-34051.106" + wire $reduce_or$libresoc.v:34051$1136_Y + attribute \src "libresoc.v:34054.18-34054.113" + wire $reduce_or$libresoc.v:34054$1139_Y + attribute \src "libresoc.v:34055.18-34055.112" + wire $reduce_or$libresoc.v:34055$1140_Y + attribute \src "libresoc.v:34078.18-34078.162" + wire $ternary$libresoc.v:34078$1163_Y + attribute \src "libresoc.v:34079.18-34079.176" + wire width 64 $ternary$libresoc.v:34079$1164_Y + attribute \src "libresoc.v:34080.18-34080.118" + wire width 64 $ternary$libresoc.v:34080$1165_Y + attribute \src "libresoc.v:34081.18-34081.115" + wire width 64 $ternary$libresoc.v:34081$1166_Y + attribute \src "libresoc.v:34082.18-34082.118" + wire width 4 $ternary$libresoc.v:34082$1167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -50208,23 +50436,24 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__cia$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_branch0_br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_branch0_br_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_branch0_br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_branch0_br_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50311,6 +50540,7 @@ module \branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_branch0_br_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50371,9 +50601,9 @@ module \branch0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o @@ -50431,7 +50661,7 @@ module \branch0 wire output 18 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast2_ok - attribute \src "libresoc.v:33253.7-33253.15" + attribute \src "libresoc.v:33481.7-33481.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \nia_ok @@ -50448,21 +50678,22 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 2 \oper_i_alu_branch0__cia attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 4 \oper_i_alu_branch0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 4 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 6 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50543,6 +50774,7 @@ module \branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 3 \oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50626,7 +50858,7 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33802$1119 + cell $and $and$libresoc.v:34034$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50634,10 +50866,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:33802$1119_Y + connect \Y $and$libresoc.v:34034$1119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33803$1120 + cell $and $and$libresoc.v:34035$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50645,10 +50877,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33803$1120_Y + connect \Y $and$libresoc.v:34035$1120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33804$1121 + cell $and $and$libresoc.v:34036$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50656,10 +50888,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33804$1121_Y + connect \Y $and$libresoc.v:34036$1121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33805$1122 + cell $and $and$libresoc.v:34037$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50667,10 +50899,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33805$1122_Y + connect \Y $and$libresoc.v:34037$1122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:33806$1123 + cell $and $and$libresoc.v:34038$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50678,10 +50910,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:33806$1123_Y + connect \Y $and$libresoc.v:34038$1123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:33807$1124 + cell $and $and$libresoc.v:34039$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50689,10 +50921,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33807$1124_Y + connect \Y $and$libresoc.v:34039$1124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33808$1125 + cell $and $and$libresoc.v:34040$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50700,10 +50932,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33808$1125_Y + connect \Y $and$libresoc.v:34040$1125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33809$1126 + cell $and $and$libresoc.v:34041$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50711,10 +50943,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33809$1126_Y + connect \Y $and$libresoc.v:34041$1126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33810$1127 + cell $and $and$libresoc.v:34042$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50722,10 +50954,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33810$1127_Y + connect \Y $and$libresoc.v:34042$1127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:33811$1128 + cell $and $and$libresoc.v:34043$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50733,10 +50965,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:33811$1128_Y + connect \Y $and$libresoc.v:34043$1128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:33813$1130 + cell $and $and$libresoc.v:34045$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50744,10 +50976,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:33813$1130_Y + connect \Y $and$libresoc.v:34045$1130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:33815$1132 + cell $and $and$libresoc.v:34047$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50755,10 +50987,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:33815$1132_Y + connect \Y $and$libresoc.v:34047$1132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:33816$1133 + cell $and $and$libresoc.v:34048$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50766,10 +50998,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:33816$1133_Y + connect \Y $and$libresoc.v:34048$1133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:33818$1135 + cell $and $and$libresoc.v:34050$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50777,10 +51009,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:33818$1135_Y + connect \Y $and$libresoc.v:34050$1135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:33821$1138 + cell $and $and$libresoc.v:34053$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50788,10 +51020,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:33821$1138_Y + connect \Y $and$libresoc.v:34053$1138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:33825$1142 + cell $and $and$libresoc.v:34057$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50799,10 +51031,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:33825$1142_Y + connect \Y $and$libresoc.v:34057$1142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:33827$1144 + cell $and $and$libresoc.v:34059$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50810,10 +51042,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:33827$1144_Y + connect \Y $and$libresoc.v:34059$1144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:33828$1145 + cell $and $and$libresoc.v:34060$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50821,10 +51053,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33828$1145_Y + connect \Y $and$libresoc.v:34060$1145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:33830$1147 + cell $and $and$libresoc.v:34062$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50832,10 +51064,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:33830$1147_Y + connect \Y $and$libresoc.v:34062$1147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33832$1149 + cell $and $and$libresoc.v:34064$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50843,10 +51075,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_branch0_n_ready_i - connect \Y $and$libresoc.v:33832$1149_Y + connect \Y $and$libresoc.v:34064$1149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33833$1150 + cell $and $and$libresoc.v:34065$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50854,10 +51086,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_branch0_n_valid_o - connect \Y $and$libresoc.v:33833$1150_Y + connect \Y $and$libresoc.v:34065$1150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33834$1151 + cell $and $and$libresoc.v:34066$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50865,10 +51097,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:33834$1151_Y + connect \Y $and$libresoc.v:34066$1151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:33839$1156 + cell $and $and$libresoc.v:34071$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50876,10 +51108,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:33839$1156_Y + connect \Y $and$libresoc.v:34071$1156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:33840$1157 + cell $and $and$libresoc.v:34072$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50887,10 +51119,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33840$1157_Y + connect \Y $and$libresoc.v:34072$1157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33843$1160 + cell $and $and$libresoc.v:34075$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50898,10 +51130,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33843$1160_Y + connect \Y $and$libresoc.v:34075$1160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33844$1161 + cell $and $and$libresoc.v:34076$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50909,10 +51141,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33844$1161_Y + connect \Y $and$libresoc.v:34076$1161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33845$1162 + cell $and $and$libresoc.v:34077$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50920,10 +51152,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33845$1162_Y + connect \Y $and$libresoc.v:34077$1162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:33851$1168 + cell $and $and$libresoc.v:34083$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50931,10 +51163,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:33851$1168_Y + connect \Y $and$libresoc.v:34083$1168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:33853$1170 + cell $and $and$libresoc.v:34085$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50942,10 +51174,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:33853$1170_Y + connect \Y $and$libresoc.v:34085$1170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33854$1171 + cell $and $and$libresoc.v:34086$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50953,10 +51185,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:33854$1171_Y + connect \Y $and$libresoc.v:34086$1171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33856$1173 + cell $and $and$libresoc.v:34088$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50964,10 +51196,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$91 connect \B { 1'1 \$93 1'1 } - connect \Y $and$libresoc.v:33856$1173_Y + connect \Y $and$libresoc.v:34088$1173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:33829$1146 + cell $eq $eq$libresoc.v:34061$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50975,10 +51207,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:33829$1146_Y + connect \Y $eq$libresoc.v:34061$1146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:33831$1148 + cell $eq $eq$libresoc.v:34063$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50986,74 +51218,74 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:33831$1148_Y + connect \Y $eq$libresoc.v:34063$1148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:33812$1129 + cell $not $not$libresoc.v:34044$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:33812$1129_Y + connect \Y $not$libresoc.v:34044$1129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:33814$1131 + cell $not $not$libresoc.v:34046$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:33814$1131_Y + connect \Y $not$libresoc.v:34046$1131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:33817$1134 + cell $not $not$libresoc.v:34049$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:33817$1134_Y + connect \Y $not$libresoc.v:34049$1134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:33820$1137 + cell $not $not$libresoc.v:34052$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:33820$1137_Y + connect \Y $not$libresoc.v:34052$1137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:33826$1143 + cell $not $not$libresoc.v:34058$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_ready_i - connect \Y $not$libresoc.v:33826$1143_Y + connect \Y $not$libresoc.v:34058$1143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:33841$1158 + cell $not $not$libresoc.v:34073$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:33841$1158_Y + connect \Y $not$libresoc.v:34073$1158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:33855$1172 + cell $not $not$libresoc.v:34087$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_br_op__imm_data__ok - connect \Y $not$libresoc.v:33855$1172_Y + connect \Y $not$libresoc.v:34087$1172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:33857$1174 + cell $not $not$libresoc.v:34089$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:33857$1174_Y + connect \Y $not$libresoc.v:34089$1174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:33824$1141 + cell $or $or$libresoc.v:34056$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51061,10 +51293,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:33824$1141_Y + connect \Y $or$libresoc.v:34056$1141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:33835$1152 + cell $or $or$libresoc.v:34067$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51072,10 +51304,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:33835$1152_Y + connect \Y $or$libresoc.v:34067$1152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:33836$1153 + cell $or $or$libresoc.v:34068$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51083,10 +51315,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:33836$1153_Y + connect \Y $or$libresoc.v:34068$1153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:33837$1154 + cell $or $or$libresoc.v:34069$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51094,10 +51326,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:33837$1154_Y + connect \Y $or$libresoc.v:34069$1154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:33838$1155 + cell $or $or$libresoc.v:34070$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51105,10 +51337,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:33838$1155_Y + connect \Y $or$libresoc.v:34070$1155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:33842$1159 + cell $or $or$libresoc.v:34074$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51116,10 +51348,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:33842$1159_Y + connect \Y $or$libresoc.v:34074$1159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:33852$1169 + cell $or $or$libresoc.v:34084$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51127,82 +51359,82 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:33852$1169_Y + connect \Y $or$libresoc.v:34084$1169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:33801$1118 + cell $reduce_and $reduce_and$libresoc.v:34033$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:33801$1118_Y + connect \Y $reduce_and$libresoc.v:34033$1118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:33819$1136 + cell $reduce_or $reduce_or$libresoc.v:34051$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:33819$1136_Y + connect \Y $reduce_or$libresoc.v:34051$1136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:33822$1139 + cell $reduce_or $reduce_or$libresoc.v:34054$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:33822$1139_Y + connect \Y $reduce_or$libresoc.v:34054$1139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:33823$1140 + cell $reduce_or $reduce_or$libresoc.v:34055$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:33823$1140_Y + connect \Y $reduce_or$libresoc.v:34055$1140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:33846$1163 + cell $mux $ternary$libresoc.v:34078$1163 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:33846$1163_Y + connect \Y $ternary$libresoc.v:34078$1163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:33847$1164 + cell $mux $ternary$libresoc.v:34079$1164 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_branch0_br_op__imm_data__data connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:33847$1164_Y + connect \Y $ternary$libresoc.v:34079$1164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:33848$1165 + cell $mux $ternary$libresoc.v:34080$1165 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:33848$1165_Y + connect \Y $ternary$libresoc.v:34080$1165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:33849$1166 + cell $mux $ternary$libresoc.v:34081$1166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:33849$1166_Y + connect \Y $ternary$libresoc.v:34081$1166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:33850$1167 + cell $mux $ternary$libresoc.v:34082$1167 parameter \WIDTH 4 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:33850$1167_Y + connect \Y $ternary$libresoc.v:34082$1167_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:33922.15-33946.4" + attribute \src "libresoc.v:34154.15-34178.4" cell \alu_branch0 \alu_branch0 connect \br_op__cia \alu_branch0_br_op__cia connect \br_op__fn_unit \alu_branch0_br_op__fn_unit @@ -51229,7 +51461,7 @@ module \branch0 connect \p_valid_i \alu_branch0_p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:33947.14-33953.4" + attribute \src "libresoc.v:34179.14-34185.4" cell \alu_l$29 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51238,7 +51470,7 @@ module \branch0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:33954.15-33960.4" + attribute \src "libresoc.v:34186.15-34192.4" cell \alui_l$28 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51247,7 +51479,7 @@ module \branch0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:33961.14-33967.4" + attribute \src "libresoc.v:34193.14-34199.4" cell \opc_l$24 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51256,7 +51488,7 @@ module \branch0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:33968.14-33974.4" + attribute \src "libresoc.v:34200.14-34206.4" cell \req_l$25 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51265,7 +51497,7 @@ module \branch0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:33975.14-33981.4" + attribute \src "libresoc.v:34207.14-34213.4" cell \rok_l$27 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51274,7 +51506,7 @@ module \branch0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:33982.14-33987.4" + attribute \src "libresoc.v:34214.14-34219.4" cell \rst_l$26 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51282,7 +51514,7 @@ module \branch0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:33988.14-33994.4" + attribute \src "libresoc.v:34220.14-34226.4" cell \src_l$23 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51290,502 +51522,502 @@ module \branch0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:33253.7-33253.20" - process $proc$libresoc.v:33253$1302 + attribute \src "libresoc.v:33481.7-33481.20" + process $proc$libresoc.v:33481$1302 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:33371.7-33371.24" - process $proc$libresoc.v:33371$1303 + attribute \src "libresoc.v:33599.7-33599.24" + process $proc$libresoc.v:33599$1303 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:33379.14-33379.59" - process $proc$libresoc.v:33379$1304 + attribute \src "libresoc.v:33607.14-33607.59" + process $proc$libresoc.v:33607$1304 assign { } { } assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:33397.14-33397.51" - process $proc$libresoc.v:33397$1305 + attribute \src "libresoc.v:33626.14-33626.51" + process $proc$libresoc.v:33626$1305 assign { } { } - assign $1\alu_branch0_br_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_branch0_br_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[12:0] + update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[13:0] end - attribute \src "libresoc.v:33401.14-33401.70" - process $proc$libresoc.v:33401$1306 + attribute \src "libresoc.v:33630.14-33630.70" + process $proc$libresoc.v:33630$1306 assign { } { } assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:33405.7-33405.45" - process $proc$libresoc.v:33405$1307 + attribute \src "libresoc.v:33634.7-33634.45" + process $proc$libresoc.v:33634$1307 assign { } { } assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:33409.14-33409.45" - process $proc$libresoc.v:33409$1308 + attribute \src "libresoc.v:33638.14-33638.45" + process $proc$libresoc.v:33638$1308 assign { } { } assign $1\alu_branch0_br_op__insn[31:0] 0 sync always sync init update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:33487.13-33487.49" - process $proc$libresoc.v:33487$1309 + attribute \src "libresoc.v:33717.13-33717.49" + process $proc$libresoc.v:33717$1309 assign { } { } assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:33491.7-33491.41" - process $proc$libresoc.v:33491$1310 + attribute \src "libresoc.v:33721.7-33721.41" + process $proc$libresoc.v:33721$1310 assign { } { } assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 sync always sync init update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:33495.7-33495.35" - process $proc$libresoc.v:33495$1311 + attribute \src "libresoc.v:33725.7-33725.35" + process $proc$libresoc.v:33725$1311 assign { } { } assign $1\alu_branch0_br_op__lk[0:0] 1'0 sync always sync init update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:33521.7-33521.26" - process $proc$libresoc.v:33521$1312 + attribute \src "libresoc.v:33751.7-33751.26" + process $proc$libresoc.v:33751$1312 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:33529.7-33529.25" - process $proc$libresoc.v:33529$1313 + attribute \src "libresoc.v:33759.7-33759.25" + process $proc$libresoc.v:33759$1313 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:33541.7-33541.27" - process $proc$libresoc.v:33541$1314 + attribute \src "libresoc.v:33771.7-33771.27" + process $proc$libresoc.v:33771$1314 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:33573.14-33573.51" - process $proc$libresoc.v:33573$1315 + attribute \src "libresoc.v:33803.14-33803.51" + process $proc$libresoc.v:33803$1315 assign { } { } assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__fast1 $1\data_r0__fast1[63:0] end - attribute \src "libresoc.v:33577.7-33577.31" - process $proc$libresoc.v:33577$1316 + attribute \src "libresoc.v:33807.7-33807.31" + process $proc$libresoc.v:33807$1316 assign { } { } assign $1\data_r0__fast1_ok[0:0] 1'0 sync always sync init update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:33581.14-33581.51" - process $proc$libresoc.v:33581$1317 + attribute \src "libresoc.v:33811.14-33811.51" + process $proc$libresoc.v:33811$1317 assign { } { } assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast2 $1\data_r1__fast2[63:0] end - attribute \src "libresoc.v:33585.7-33585.31" - process $proc$libresoc.v:33585$1318 + attribute \src "libresoc.v:33815.7-33815.31" + process $proc$libresoc.v:33815$1318 assign { } { } assign $1\data_r1__fast2_ok[0:0] 1'0 sync always sync init update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:33589.14-33589.49" - process $proc$libresoc.v:33589$1319 + attribute \src "libresoc.v:33819.14-33819.49" + process $proc$libresoc.v:33819$1319 assign { } { } assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__nia $1\data_r2__nia[63:0] end - attribute \src "libresoc.v:33593.7-33593.29" - process $proc$libresoc.v:33593$1320 + attribute \src "libresoc.v:33823.7-33823.29" + process $proc$libresoc.v:33823$1320 assign { } { } assign $1\data_r2__nia_ok[0:0] 1'0 sync always sync init update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:33614.7-33614.25" - process $proc$libresoc.v:33614$1321 + attribute \src "libresoc.v:33844.7-33844.25" + process $proc$libresoc.v:33844$1321 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:33618.7-33618.25" - process $proc$libresoc.v:33618$1322 + attribute \src "libresoc.v:33848.7-33848.25" + process $proc$libresoc.v:33848$1322 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:33726.13-33726.30" - process $proc$libresoc.v:33726$1323 + attribute \src "libresoc.v:33958.13-33958.30" + process $proc$libresoc.v:33958$1323 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:33734.13-33734.31" - process $proc$libresoc.v:33734$1324 + attribute \src "libresoc.v:33966.13-33966.31" + process $proc$libresoc.v:33966$1324 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:33738.13-33738.31" - process $proc$libresoc.v:33738$1325 + attribute \src "libresoc.v:33970.13-33970.31" + process $proc$libresoc.v:33970$1325 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:33750.7-33750.26" - process $proc$libresoc.v:33750$1326 + attribute \src "libresoc.v:33982.7-33982.26" + process $proc$libresoc.v:33982$1326 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:33754.7-33754.26" - process $proc$libresoc.v:33754$1327 + attribute \src "libresoc.v:33986.7-33986.26" + process $proc$libresoc.v:33986$1327 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:33758.7-33758.25" - process $proc$libresoc.v:33758$1328 + attribute \src "libresoc.v:33990.7-33990.25" + process $proc$libresoc.v:33990$1328 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:33762.7-33762.25" - process $proc$libresoc.v:33762$1329 + attribute \src "libresoc.v:33994.7-33994.25" + process $proc$libresoc.v:33994$1329 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:33776.13-33776.31" - process $proc$libresoc.v:33776$1330 + attribute \src "libresoc.v:34008.13-34008.31" + process $proc$libresoc.v:34008$1330 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:33780.13-33780.31" - process $proc$libresoc.v:33780$1331 + attribute \src "libresoc.v:34012.13-34012.31" + process $proc$libresoc.v:34012$1331 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:33786.14-33786.43" - process $proc$libresoc.v:33786$1332 + attribute \src "libresoc.v:34018.14-34018.43" + process $proc$libresoc.v:34018$1332 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:33790.14-33790.43" - process $proc$libresoc.v:33790$1333 + attribute \src "libresoc.v:34022.14-34022.43" + process $proc$libresoc.v:34022$1333 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:33794.13-33794.26" - process $proc$libresoc.v:33794$1334 + attribute \src "libresoc.v:34026.13-34026.26" + process $proc$libresoc.v:34026$1334 assign { } { } assign $1\src_r2[3:0] 4'0000 sync always sync init update \src_r2 $1\src_r2[3:0] end - attribute \src "libresoc.v:33858.3-33859.39" - process $proc$libresoc.v:33858$1175 + attribute \src "libresoc.v:34090.3-34091.39" + process $proc$libresoc.v:34090$1175 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:33860.3-33861.43" - process $proc$libresoc.v:33860$1176 + attribute \src "libresoc.v:34092.3-34093.43" + process $proc$libresoc.v:34092$1176 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:33862.3-33863.29" - process $proc$libresoc.v:33862$1177 + attribute \src "libresoc.v:34094.3-34095.29" + process $proc$libresoc.v:34094$1177 assign { } { } assign $0\src_r2[3:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[3:0] end - attribute \src "libresoc.v:33864.3-33865.29" - process $proc$libresoc.v:33864$1178 + attribute \src "libresoc.v:34096.3-34097.29" + process $proc$libresoc.v:34096$1178 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:33866.3-33867.29" - process $proc$libresoc.v:33866$1179 + attribute \src "libresoc.v:34098.3-34099.29" + process $proc$libresoc.v:34098$1179 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:33868.3-33869.41" - process $proc$libresoc.v:33868$1180 + attribute \src "libresoc.v:34100.3-34101.41" + process $proc$libresoc.v:34100$1180 assign { } { } assign $0\data_r2__nia[63:0] \data_r2__nia$next sync posedge \coresync_clk update \data_r2__nia $0\data_r2__nia[63:0] end - attribute \src "libresoc.v:33870.3-33871.47" - process $proc$libresoc.v:33870$1181 + attribute \src "libresoc.v:34102.3-34103.47" + process $proc$libresoc.v:34102$1181 assign { } { } assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next sync posedge \coresync_clk update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:33872.3-33873.45" - process $proc$libresoc.v:33872$1182 + attribute \src "libresoc.v:34104.3-34105.45" + process $proc$libresoc.v:34104$1182 assign { } { } assign $0\data_r1__fast2[63:0] \data_r1__fast2$next sync posedge \coresync_clk update \data_r1__fast2 $0\data_r1__fast2[63:0] end - attribute \src "libresoc.v:33874.3-33875.51" - process $proc$libresoc.v:33874$1183 + attribute \src "libresoc.v:34106.3-34107.51" + process $proc$libresoc.v:34106$1183 assign { } { } assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next sync posedge \coresync_clk update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:33876.3-33877.45" - process $proc$libresoc.v:33876$1184 + attribute \src "libresoc.v:34108.3-34109.45" + process $proc$libresoc.v:34108$1184 assign { } { } assign $0\data_r0__fast1[63:0] \data_r0__fast1$next sync posedge \coresync_clk update \data_r0__fast1 $0\data_r0__fast1[63:0] end - attribute \src "libresoc.v:33878.3-33879.51" - process $proc$libresoc.v:33878$1185 + attribute \src "libresoc.v:34110.3-34111.51" + process $proc$libresoc.v:34110$1185 assign { } { } assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next sync posedge \coresync_clk update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:33880.3-33881.61" - process $proc$libresoc.v:33880$1186 + attribute \src "libresoc.v:34112.3-34113.61" + process $proc$libresoc.v:34112$1186 assign { } { } assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next sync posedge \coresync_clk update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:33882.3-33883.73" - process $proc$libresoc.v:33882$1187 + attribute \src "libresoc.v:34114.3-34115.73" + process $proc$libresoc.v:34114$1187 assign { } { } assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next sync posedge \coresync_clk update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:33884.3-33885.69" - process $proc$libresoc.v:33884$1188 + attribute \src "libresoc.v:34116.3-34117.69" + process $proc$libresoc.v:34116$1188 assign { } { } - assign $0\alu_branch0_br_op__fn_unit[12:0] \alu_branch0_br_op__fn_unit$next + assign $0\alu_branch0_br_op__fn_unit[13:0] \alu_branch0_br_op__fn_unit$next sync posedge \coresync_clk - update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[12:0] + update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[13:0] end - attribute \src "libresoc.v:33886.3-33887.63" - process $proc$libresoc.v:33886$1189 + attribute \src "libresoc.v:34118.3-34119.63" + process $proc$libresoc.v:34118$1189 assign { } { } assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next sync posedge \coresync_clk update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:33888.3-33889.83" - process $proc$libresoc.v:33888$1190 + attribute \src "libresoc.v:34120.3-34121.83" + process $proc$libresoc.v:34120$1190 assign { } { } assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:33890.3-33891.79" - process $proc$libresoc.v:33890$1191 + attribute \src "libresoc.v:34122.3-34123.79" + process $proc$libresoc.v:34122$1191 assign { } { } assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:33892.3-33893.59" - process $proc$libresoc.v:33892$1192 + attribute \src "libresoc.v:34124.3-34125.59" + process $proc$libresoc.v:34124$1192 assign { } { } assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next sync posedge \coresync_clk update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:33894.3-33895.71" - process $proc$libresoc.v:33894$1193 + attribute \src "libresoc.v:34126.3-34127.71" + process $proc$libresoc.v:34126$1193 assign { } { } assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next sync posedge \coresync_clk update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:33896.3-33897.39" - process $proc$libresoc.v:33896$1194 + attribute \src "libresoc.v:34128.3-34129.39" + process $proc$libresoc.v:34128$1194 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:33898.3-33899.39" - process $proc$libresoc.v:33898$1195 + attribute \src "libresoc.v:34130.3-34131.39" + process $proc$libresoc.v:34130$1195 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:33900.3-33901.39" - process $proc$libresoc.v:33900$1196 + attribute \src "libresoc.v:34132.3-34133.39" + process $proc$libresoc.v:34132$1196 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:33902.3-33903.39" - process $proc$libresoc.v:33902$1197 + attribute \src "libresoc.v:34134.3-34135.39" + process $proc$libresoc.v:34134$1197 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:33904.3-33905.39" - process $proc$libresoc.v:33904$1198 + attribute \src "libresoc.v:34136.3-34137.39" + process $proc$libresoc.v:34136$1198 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:33906.3-33907.39" - process $proc$libresoc.v:33906$1199 + attribute \src "libresoc.v:34138.3-34139.39" + process $proc$libresoc.v:34138$1199 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:33908.3-33909.39" - process $proc$libresoc.v:33908$1200 + attribute \src "libresoc.v:34140.3-34141.39" + process $proc$libresoc.v:34140$1200 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:33910.3-33911.39" - process $proc$libresoc.v:33910$1201 + attribute \src "libresoc.v:34142.3-34143.39" + process $proc$libresoc.v:34142$1201 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:33912.3-33913.41" - process $proc$libresoc.v:33912$1202 + attribute \src "libresoc.v:34144.3-34145.41" + process $proc$libresoc.v:34144$1202 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:33914.3-33915.41" - process $proc$libresoc.v:33914$1203 + attribute \src "libresoc.v:34146.3-34147.41" + process $proc$libresoc.v:34146$1203 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:33916.3-33917.37" - process $proc$libresoc.v:33916$1204 + attribute \src "libresoc.v:34148.3-34149.37" + process $proc$libresoc.v:34148$1204 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:33918.3-33919.43" - process $proc$libresoc.v:33918$1205 + attribute \src "libresoc.v:34150.3-34151.43" + process $proc$libresoc.v:34150$1205 assign { } { } assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:33920.3-33921.25" - process $proc$libresoc.v:33920$1206 + attribute \src "libresoc.v:34152.3-34153.25" + process $proc$libresoc.v:34152$1206 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:33995.3-34004.6" - process $proc$libresoc.v:33995$1207 + attribute \src "libresoc.v:34227.3-34236.6" + process $proc$libresoc.v:34227$1207 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:33996.5-33996.29" + attribute \src "libresoc.v:34228.5-34228.29" switch \initial - attribute \src "libresoc.v:33996.9-33996.17" + attribute \src "libresoc.v:34228.9-34228.17" case 1'1 case end @@ -51801,14 +52033,14 @@ module \branch0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:34005.3-34013.6" - process $proc$libresoc.v:34005$1208 + attribute \src "libresoc.v:34237.3-34245.6" + process $proc$libresoc.v:34237$1208 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:34006.5-34006.29" + attribute \src "libresoc.v:34238.5-34238.29" switch \initial - attribute \src "libresoc.v:34006.9-34006.17" + attribute \src "libresoc.v:34238.9-34238.17" case 1'1 case end @@ -51824,14 +52056,14 @@ module \branch0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 end - attribute \src "libresoc.v:34014.3-34022.6" - process $proc$libresoc.v:34014$1211 + attribute \src "libresoc.v:34246.3-34254.6" + process $proc$libresoc.v:34246$1211 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:34015.5-34015.29" + attribute \src "libresoc.v:34247.5-34247.29" switch \initial - attribute \src "libresoc.v:34015.9-34015.17" + attribute \src "libresoc.v:34247.9-34247.17" case 1'1 case end @@ -51847,14 +52079,14 @@ module \branch0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 end - attribute \src "libresoc.v:34023.3-34031.6" - process $proc$libresoc.v:34023$1214 + attribute \src "libresoc.v:34255.3-34263.6" + process $proc$libresoc.v:34255$1214 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:34024.5-34024.29" + attribute \src "libresoc.v:34256.5-34256.29" switch \initial - attribute \src "libresoc.v:34024.9-34024.17" + attribute \src "libresoc.v:34256.9-34256.17" case 1'1 case end @@ -51870,14 +52102,14 @@ module \branch0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 end - attribute \src "libresoc.v:34032.3-34040.6" - process $proc$libresoc.v:34032$1217 + attribute \src "libresoc.v:34264.3-34272.6" + process $proc$libresoc.v:34264$1217 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:34033.5-34033.29" + attribute \src "libresoc.v:34265.5-34265.29" switch \initial - attribute \src "libresoc.v:34033.9-34033.17" + attribute \src "libresoc.v:34265.9-34265.17" case 1'1 case end @@ -51893,14 +52125,14 @@ module \branch0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 end - attribute \src "libresoc.v:34041.3-34049.6" - process $proc$libresoc.v:34041$1220 + attribute \src "libresoc.v:34273.3-34281.6" + process $proc$libresoc.v:34273$1220 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:34042.5-34042.29" + attribute \src "libresoc.v:34274.5-34274.29" switch \initial - attribute \src "libresoc.v:34042.9-34042.17" + attribute \src "libresoc.v:34274.9-34274.17" case 1'1 case end @@ -51916,14 +52148,14 @@ module \branch0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 end - attribute \src "libresoc.v:34050.3-34058.6" - process $proc$libresoc.v:34050$1223 + attribute \src "libresoc.v:34282.3-34290.6" + process $proc$libresoc.v:34282$1223 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:34051.5-34051.29" + attribute \src "libresoc.v:34283.5-34283.29" switch \initial - attribute \src "libresoc.v:34051.9-34051.17" + attribute \src "libresoc.v:34283.9-34283.17" case 1'1 case end @@ -51939,14 +52171,14 @@ module \branch0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 end - attribute \src "libresoc.v:34059.3-34067.6" - process $proc$libresoc.v:34059$1226 + attribute \src "libresoc.v:34291.3-34299.6" + process $proc$libresoc.v:34291$1226 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:34060.5-34060.29" + attribute \src "libresoc.v:34292.5-34292.29" switch \initial - attribute \src "libresoc.v:34060.9-34060.17" + attribute \src "libresoc.v:34292.9-34292.17" case 1'1 case end @@ -51962,14 +52194,14 @@ module \branch0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 end - attribute \src "libresoc.v:34068.3-34076.6" - process $proc$libresoc.v:34068$1229 + attribute \src "libresoc.v:34300.3-34308.6" + process $proc$libresoc.v:34300$1229 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:34069.5-34069.29" + attribute \src "libresoc.v:34301.5-34301.29" switch \initial - attribute \src "libresoc.v:34069.9-34069.17" + attribute \src "libresoc.v:34301.9-34301.17" case 1'1 case end @@ -51985,14 +52217,14 @@ module \branch0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 end - attribute \src "libresoc.v:34077.3-34085.6" - process $proc$libresoc.v:34077$1232 + attribute \src "libresoc.v:34309.3-34317.6" + process $proc$libresoc.v:34309$1232 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:34078.5-34078.29" + attribute \src "libresoc.v:34310.5-34310.29" switch \initial - attribute \src "libresoc.v:34078.9-34078.17" + attribute \src "libresoc.v:34310.9-34310.17" case 1'1 case end @@ -52008,14 +52240,14 @@ module \branch0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 end - attribute \src "libresoc.v:34086.3-34094.6" - process $proc$libresoc.v:34086$1235 + attribute \src "libresoc.v:34318.3-34326.6" + process $proc$libresoc.v:34318$1235 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:34087.5-34087.29" + attribute \src "libresoc.v:34319.5-34319.29" switch \initial - attribute \src "libresoc.v:34087.9-34087.17" + attribute \src "libresoc.v:34319.9-34319.17" case 1'1 case end @@ -52031,8 +52263,8 @@ module \branch0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 end - attribute \src "libresoc.v:34095.3-34119.6" - process $proc$libresoc.v:34095$1238 + attribute \src "libresoc.v:34327.3-34351.6" + process $proc$libresoc.v:34327$1238 assign { } { } assign { } { } assign { } { } @@ -52050,7 +52282,7 @@ module \branch0 assign { } { } assign { } { } assign $0\alu_branch0_br_op__cia$next[63:0]$1239 $1\alu_branch0_br_op__cia$next[63:0]$1247 - assign $0\alu_branch0_br_op__fn_unit$next[12:0]$1240 $1\alu_branch0_br_op__fn_unit$next[12:0]$1248 + assign $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 assign { } { } assign { } { } assign $0\alu_branch0_br_op__insn$next[31:0]$1243 $1\alu_branch0_br_op__insn$next[31:0]$1251 @@ -52059,9 +52291,9 @@ module \branch0 assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:34096.5-34096.29" + attribute \src "libresoc.v:34328.5-34328.29" switch \initial - attribute \src "libresoc.v:34096.9-34096.17" + attribute \src "libresoc.v:34328.9-34328.17" case 1'1 case end @@ -52077,10 +52309,10 @@ module \branch0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[12:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } case assign $1\alu_branch0_br_op__cia$next[63:0]$1247 \alu_branch0_br_op__cia - assign $1\alu_branch0_br_op__fn_unit$next[12:0]$1248 \alu_branch0_br_op__fn_unit + assign $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 \alu_branch0_br_op__fn_unit assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 \alu_branch0_br_op__imm_data__data assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 \alu_branch0_br_op__imm_data__ok assign $1\alu_branch0_br_op__insn$next[31:0]$1251 \alu_branch0_br_op__insn @@ -52102,7 +52334,7 @@ module \branch0 end sync always update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1239 - update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[12:0]$1240 + update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1243 @@ -52110,8 +52342,8 @@ module \branch0 update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 end - attribute \src "libresoc.v:34120.3-34141.6" - process $proc$libresoc.v:34120$1257 + attribute \src "libresoc.v:34352.3-34373.6" + process $proc$libresoc.v:34352$1257 assign { } { } assign { } { } assign { } { } @@ -52121,9 +52353,9 @@ module \branch0 assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 assign { } { } assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:34121.5-34121.29" + attribute \src "libresoc.v:34353.5-34353.29" switch \initial - attribute \src "libresoc.v:34121.9-34121.17" + attribute \src "libresoc.v:34353.9-34353.17" case 1'1 case end @@ -52162,8 +52394,8 @@ module \branch0 update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 end - attribute \src "libresoc.v:34142.3-34163.6" - process $proc$libresoc.v:34142$1265 + attribute \src "libresoc.v:34374.3-34395.6" + process $proc$libresoc.v:34374$1265 assign { } { } assign { } { } assign { } { } @@ -52173,9 +52405,9 @@ module \branch0 assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 assign { } { } assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:34143.5-34143.29" + attribute \src "libresoc.v:34375.5-34375.29" switch \initial - attribute \src "libresoc.v:34143.9-34143.17" + attribute \src "libresoc.v:34375.9-34375.17" case 1'1 case end @@ -52214,8 +52446,8 @@ module \branch0 update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 end - attribute \src "libresoc.v:34164.3-34185.6" - process $proc$libresoc.v:34164$1273 + attribute \src "libresoc.v:34396.3-34417.6" + process $proc$libresoc.v:34396$1273 assign { } { } assign { } { } assign { } { } @@ -52225,9 +52457,9 @@ module \branch0 assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 assign { } { } assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:34165.5-34165.29" + attribute \src "libresoc.v:34397.5-34397.29" switch \initial - attribute \src "libresoc.v:34165.9-34165.17" + attribute \src "libresoc.v:34397.9-34397.17" case 1'1 case end @@ -52266,14 +52498,14 @@ module \branch0 update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 end - attribute \src "libresoc.v:34186.3-34195.6" - process $proc$libresoc.v:34186$1281 + attribute \src "libresoc.v:34418.3-34427.6" + process $proc$libresoc.v:34418$1281 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:34187.5-34187.29" + attribute \src "libresoc.v:34419.5-34419.29" switch \initial - attribute \src "libresoc.v:34187.9-34187.17" + attribute \src "libresoc.v:34419.9-34419.17" case 1'1 case end @@ -52289,14 +52521,14 @@ module \branch0 sync always update \src_r0$next $0\src_r0$next[63:0]$1282 end - attribute \src "libresoc.v:34196.3-34205.6" - process $proc$libresoc.v:34196$1284 + attribute \src "libresoc.v:34428.3-34437.6" + process $proc$libresoc.v:34428$1284 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:34197.5-34197.29" + attribute \src "libresoc.v:34429.5-34429.29" switch \initial - attribute \src "libresoc.v:34197.9-34197.17" + attribute \src "libresoc.v:34429.9-34429.17" case 1'1 case end @@ -52312,14 +52544,14 @@ module \branch0 sync always update \src_r1$next $0\src_r1$next[63:0]$1285 end - attribute \src "libresoc.v:34206.3-34215.6" - process $proc$libresoc.v:34206$1287 + attribute \src "libresoc.v:34438.3-34447.6" + process $proc$libresoc.v:34438$1287 assign { } { } assign { } { } assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:34207.5-34207.29" + attribute \src "libresoc.v:34439.5-34439.29" switch \initial - attribute \src "libresoc.v:34207.9-34207.17" + attribute \src "libresoc.v:34439.9-34439.17" case 1'1 case end @@ -52335,14 +52567,14 @@ module \branch0 sync always update \src_r2$next $0\src_r2$next[3:0]$1288 end - attribute \src "libresoc.v:34216.3-34224.6" - process $proc$libresoc.v:34216$1290 + attribute \src "libresoc.v:34448.3-34456.6" + process $proc$libresoc.v:34448$1290 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:34217.5-34217.29" + attribute \src "libresoc.v:34449.5-34449.29" switch \initial - attribute \src "libresoc.v:34217.9-34217.17" + attribute \src "libresoc.v:34449.9-34449.17" case 1'1 case end @@ -52358,14 +52590,14 @@ module \branch0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 end - attribute \src "libresoc.v:34225.3-34233.6" - process $proc$libresoc.v:34225$1293 + attribute \src "libresoc.v:34457.3-34465.6" + process $proc$libresoc.v:34457$1293 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:34226.5-34226.29" + attribute \src "libresoc.v:34458.5-34458.29" switch \initial - attribute \src "libresoc.v:34226.9-34226.17" + attribute \src "libresoc.v:34458.9-34458.17" case 1'1 case end @@ -52381,14 +52613,14 @@ module \branch0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 end - attribute \src "libresoc.v:34234.3-34243.6" - process $proc$libresoc.v:34234$1296 + attribute \src "libresoc.v:34466.3-34475.6" + process $proc$libresoc.v:34466$1296 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:34235.5-34235.29" + attribute \src "libresoc.v:34467.5-34467.29" switch \initial - attribute \src "libresoc.v:34235.9-34235.17" + attribute \src "libresoc.v:34467.9-34467.17" case 1'1 case end @@ -52404,14 +52636,14 @@ module \branch0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:34244.3-34253.6" - process $proc$libresoc.v:34244$1297 + attribute \src "libresoc.v:34476.3-34485.6" + process $proc$libresoc.v:34476$1297 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:34245.5-34245.29" + attribute \src "libresoc.v:34477.5-34477.29" switch \initial - attribute \src "libresoc.v:34245.9-34245.17" + attribute \src "libresoc.v:34477.9-34477.17" case 1'1 case end @@ -52427,14 +52659,14 @@ module \branch0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:34254.3-34263.6" - process $proc$libresoc.v:34254$1298 + attribute \src "libresoc.v:34486.3-34495.6" + process $proc$libresoc.v:34486$1298 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:34255.5-34255.29" + attribute \src "libresoc.v:34487.5-34487.29" switch \initial - attribute \src "libresoc.v:34255.9-34255.17" + attribute \src "libresoc.v:34487.9-34487.17" case 1'1 case end @@ -52450,14 +52682,14 @@ module \branch0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:34264.3-34272.6" - process $proc$libresoc.v:34264$1299 + attribute \src "libresoc.v:34496.3-34504.6" + process $proc$libresoc.v:34496$1299 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:34265.5-34265.29" + attribute \src "libresoc.v:34497.5-34497.29" switch \initial - attribute \src "libresoc.v:34265.9-34265.17" + attribute \src "libresoc.v:34497.9-34497.17" case 1'1 case end @@ -52473,63 +52705,63 @@ module \branch0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1300 end - connect \$5 $reduce_and$libresoc.v:33801$1118_Y - connect \$99 $and$libresoc.v:33802$1119_Y - connect \$101 $and$libresoc.v:33803$1120_Y - connect \$103 $and$libresoc.v:33804$1121_Y - connect \$105 $and$libresoc.v:33805$1122_Y - connect \$107 $and$libresoc.v:33806$1123_Y - connect \$109 $and$libresoc.v:33807$1124_Y - connect \$111 $and$libresoc.v:33808$1125_Y - connect \$113 $and$libresoc.v:33809$1126_Y - connect \$115 $and$libresoc.v:33810$1127_Y - connect \$11 $and$libresoc.v:33811$1128_Y - connect \$13 $not$libresoc.v:33812$1129_Y - connect \$15 $and$libresoc.v:33813$1130_Y - connect \$17 $not$libresoc.v:33814$1131_Y - connect \$19 $and$libresoc.v:33815$1132_Y - connect \$21 $and$libresoc.v:33816$1133_Y - connect \$25 $not$libresoc.v:33817$1134_Y - connect \$27 $and$libresoc.v:33818$1135_Y - connect \$24 $reduce_or$libresoc.v:33819$1136_Y - connect \$23 $not$libresoc.v:33820$1137_Y - connect \$31 $and$libresoc.v:33821$1138_Y - connect \$33 $reduce_or$libresoc.v:33822$1139_Y - connect \$35 $reduce_or$libresoc.v:33823$1140_Y - connect \$37 $or$libresoc.v:33824$1141_Y - connect \$3 $and$libresoc.v:33825$1142_Y - connect \$39 $not$libresoc.v:33826$1143_Y - connect \$41 $and$libresoc.v:33827$1144_Y - connect \$43 $and$libresoc.v:33828$1145_Y - connect \$45 $eq$libresoc.v:33829$1146_Y - connect \$47 $and$libresoc.v:33830$1147_Y - connect \$49 $eq$libresoc.v:33831$1148_Y - connect \$51 $and$libresoc.v:33832$1149_Y - connect \$53 $and$libresoc.v:33833$1150_Y - connect \$55 $and$libresoc.v:33834$1151_Y - connect \$57 $or$libresoc.v:33835$1152_Y - connect \$59 $or$libresoc.v:33836$1153_Y - connect \$61 $or$libresoc.v:33837$1154_Y - connect \$63 $or$libresoc.v:33838$1155_Y - connect \$65 $and$libresoc.v:33839$1156_Y - connect \$67 $and$libresoc.v:33840$1157_Y - connect \$6 $not$libresoc.v:33841$1158_Y - connect \$69 $or$libresoc.v:33842$1159_Y - connect \$71 $and$libresoc.v:33843$1160_Y - connect \$73 $and$libresoc.v:33844$1161_Y - connect \$75 $and$libresoc.v:33845$1162_Y - connect \$77 $ternary$libresoc.v:33846$1163_Y - connect \$79 $ternary$libresoc.v:33847$1164_Y - connect \$81 $ternary$libresoc.v:33848$1165_Y - connect \$83 $ternary$libresoc.v:33849$1166_Y - connect \$85 $ternary$libresoc.v:33850$1167_Y - connect \$87 $and$libresoc.v:33851$1168_Y - connect \$8 $or$libresoc.v:33852$1169_Y - connect \$89 $and$libresoc.v:33853$1170_Y - connect \$91 $and$libresoc.v:33854$1171_Y - connect \$93 $not$libresoc.v:33855$1172_Y - connect \$95 $and$libresoc.v:33856$1173_Y - connect \$97 $not$libresoc.v:33857$1174_Y + connect \$5 $reduce_and$libresoc.v:34033$1118_Y + connect \$99 $and$libresoc.v:34034$1119_Y + connect \$101 $and$libresoc.v:34035$1120_Y + connect \$103 $and$libresoc.v:34036$1121_Y + connect \$105 $and$libresoc.v:34037$1122_Y + connect \$107 $and$libresoc.v:34038$1123_Y + connect \$109 $and$libresoc.v:34039$1124_Y + connect \$111 $and$libresoc.v:34040$1125_Y + connect \$113 $and$libresoc.v:34041$1126_Y + connect \$115 $and$libresoc.v:34042$1127_Y + connect \$11 $and$libresoc.v:34043$1128_Y + connect \$13 $not$libresoc.v:34044$1129_Y + connect \$15 $and$libresoc.v:34045$1130_Y + connect \$17 $not$libresoc.v:34046$1131_Y + connect \$19 $and$libresoc.v:34047$1132_Y + connect \$21 $and$libresoc.v:34048$1133_Y + connect \$25 $not$libresoc.v:34049$1134_Y + connect \$27 $and$libresoc.v:34050$1135_Y + connect \$24 $reduce_or$libresoc.v:34051$1136_Y + connect \$23 $not$libresoc.v:34052$1137_Y + connect \$31 $and$libresoc.v:34053$1138_Y + connect \$33 $reduce_or$libresoc.v:34054$1139_Y + connect \$35 $reduce_or$libresoc.v:34055$1140_Y + connect \$37 $or$libresoc.v:34056$1141_Y + connect \$3 $and$libresoc.v:34057$1142_Y + connect \$39 $not$libresoc.v:34058$1143_Y + connect \$41 $and$libresoc.v:34059$1144_Y + connect \$43 $and$libresoc.v:34060$1145_Y + connect \$45 $eq$libresoc.v:34061$1146_Y + connect \$47 $and$libresoc.v:34062$1147_Y + connect \$49 $eq$libresoc.v:34063$1148_Y + connect \$51 $and$libresoc.v:34064$1149_Y + connect \$53 $and$libresoc.v:34065$1150_Y + connect \$55 $and$libresoc.v:34066$1151_Y + connect \$57 $or$libresoc.v:34067$1152_Y + connect \$59 $or$libresoc.v:34068$1153_Y + connect \$61 $or$libresoc.v:34069$1154_Y + connect \$63 $or$libresoc.v:34070$1155_Y + connect \$65 $and$libresoc.v:34071$1156_Y + connect \$67 $and$libresoc.v:34072$1157_Y + connect \$6 $not$libresoc.v:34073$1158_Y + connect \$69 $or$libresoc.v:34074$1159_Y + connect \$71 $and$libresoc.v:34075$1160_Y + connect \$73 $and$libresoc.v:34076$1161_Y + connect \$75 $and$libresoc.v:34077$1162_Y + connect \$77 $ternary$libresoc.v:34078$1163_Y + connect \$79 $ternary$libresoc.v:34079$1164_Y + connect \$81 $ternary$libresoc.v:34080$1165_Y + connect \$83 $ternary$libresoc.v:34081$1166_Y + connect \$85 $ternary$libresoc.v:34082$1167_Y + connect \$87 $and$libresoc.v:34083$1168_Y + connect \$8 $or$libresoc.v:34084$1169_Y + connect \$89 $and$libresoc.v:34085$1170_Y + connect \$91 $and$libresoc.v:34086$1171_Y + connect \$93 $not$libresoc.v:34087$1172_Y + connect \$95 $and$libresoc.v:34088$1173_Y + connect \$97 $not$libresoc.v:34089$1174_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -52561,37 +52793,37 @@ module \branch0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:34307.1-34365.10" +attribute \src "libresoc.v:34539.1-34597.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" attribute \generator "nMigen" module \busy_l - attribute \src "libresoc.v:34308.7-34308.20" + attribute \src "libresoc.v:34540.7-34540.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34353.3-34361.6" + attribute \src "libresoc.v:34585.3-34593.6" wire $0\q_int$next[0:0]$1345 - attribute \src "libresoc.v:34351.3-34352.27" + attribute \src "libresoc.v:34583.3-34584.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:34353.3-34361.6" + attribute \src "libresoc.v:34585.3-34593.6" wire $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34332.7-34332.19" + attribute \src "libresoc.v:34564.7-34564.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:34343.17-34343.96" - wire $and$libresoc.v:34343$1335_Y - attribute \src "libresoc.v:34348.17-34348.96" - wire $and$libresoc.v:34348$1340_Y - attribute \src "libresoc.v:34345.18-34345.94" - wire $not$libresoc.v:34345$1337_Y - attribute \src "libresoc.v:34347.17-34347.93" - wire $not$libresoc.v:34347$1339_Y - attribute \src "libresoc.v:34350.17-34350.93" - wire $not$libresoc.v:34350$1342_Y - attribute \src "libresoc.v:34344.18-34344.99" - wire $or$libresoc.v:34344$1336_Y - attribute \src "libresoc.v:34346.18-34346.100" - wire $or$libresoc.v:34346$1338_Y - attribute \src "libresoc.v:34349.17-34349.98" - wire $or$libresoc.v:34349$1341_Y + attribute \src "libresoc.v:34575.17-34575.96" + wire $and$libresoc.v:34575$1335_Y + attribute \src "libresoc.v:34580.17-34580.96" + wire $and$libresoc.v:34580$1340_Y + attribute \src "libresoc.v:34577.18-34577.94" + wire $not$libresoc.v:34577$1337_Y + attribute \src "libresoc.v:34579.17-34579.93" + wire $not$libresoc.v:34579$1339_Y + attribute \src "libresoc.v:34582.17-34582.93" + wire $not$libresoc.v:34582$1342_Y + attribute \src "libresoc.v:34576.18-34576.99" + wire $or$libresoc.v:34576$1336_Y + attribute \src "libresoc.v:34578.18-34578.100" + wire $or$libresoc.v:34578$1338_Y + attribute \src "libresoc.v:34581.17-34581.98" + wire $or$libresoc.v:34581$1341_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -52608,11 +52840,11 @@ module \busy_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:34308.7-34308.15" + attribute \src "libresoc.v:34540.7-34540.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_busy @@ -52629,7 +52861,7 @@ module \busy_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:34343$1335 + cell $and $and$libresoc.v:34575$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52637,10 +52869,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:34343$1335_Y + connect \Y $and$libresoc.v:34575$1335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:34348$1340 + cell $and $and$libresoc.v:34580$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52648,34 +52880,34 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:34348$1340_Y + connect \Y $and$libresoc.v:34580$1340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:34345$1337 + cell $not $not$libresoc.v:34577$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_busy - connect \Y $not$libresoc.v:34345$1337_Y + connect \Y $not$libresoc.v:34577$1337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:34347$1339 + cell $not $not$libresoc.v:34579$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:34347$1339_Y + connect \Y $not$libresoc.v:34579$1339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:34350$1342 + cell $not $not$libresoc.v:34582$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:34350$1342_Y + connect \Y $not$libresoc.v:34582$1342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:34344$1336 + cell $or $or$libresoc.v:34576$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52683,10 +52915,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_busy - connect \Y $or$libresoc.v:34344$1336_Y + connect \Y $or$libresoc.v:34576$1336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:34346$1338 + cell $or $or$libresoc.v:34578$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52694,10 +52926,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_busy connect \B \q_int - connect \Y $or$libresoc.v:34346$1338_Y + connect \Y $or$libresoc.v:34578$1338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:34349$1341 + cell $or $or$libresoc.v:34581$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52705,39 +52937,39 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_busy - connect \Y $or$libresoc.v:34349$1341_Y + connect \Y $or$libresoc.v:34581$1341_Y end - attribute \src "libresoc.v:34308.7-34308.20" - process $proc$libresoc.v:34308$1347 + attribute \src "libresoc.v:34540.7-34540.20" + process $proc$libresoc.v:34540$1347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:34332.7-34332.19" - process $proc$libresoc.v:34332$1348 + attribute \src "libresoc.v:34564.7-34564.19" + process $proc$libresoc.v:34564$1348 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:34351.3-34352.27" - process $proc$libresoc.v:34351$1343 + attribute \src "libresoc.v:34583.3-34584.27" + process $proc$libresoc.v:34583$1343 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:34353.3-34361.6" - process $proc$libresoc.v:34353$1344 + attribute \src "libresoc.v:34585.3-34593.6" + process $proc$libresoc.v:34585$1344 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34354.5-34354.29" + attribute \src "libresoc.v:34586.5-34586.29" switch \initial - attribute \src "libresoc.v:34354.9-34354.17" + attribute \src "libresoc.v:34586.9-34586.17" case 1'1 case end @@ -52753,525 +52985,525 @@ module \busy_l sync always update \q_int$next $0\q_int$next[0:0]$1345 end - connect \$9 $and$libresoc.v:34343$1335_Y - connect \$11 $or$libresoc.v:34344$1336_Y - connect \$13 $not$libresoc.v:34345$1337_Y - connect \$15 $or$libresoc.v:34346$1338_Y - connect \$1 $not$libresoc.v:34347$1339_Y - connect \$3 $and$libresoc.v:34348$1340_Y - connect \$5 $or$libresoc.v:34349$1341_Y - connect \$7 $not$libresoc.v:34350$1342_Y + connect \$9 $and$libresoc.v:34575$1335_Y + connect \$11 $or$libresoc.v:34576$1336_Y + connect \$13 $not$libresoc.v:34577$1337_Y + connect \$15 $or$libresoc.v:34578$1338_Y + connect \$1 $not$libresoc.v:34579$1339_Y + connect \$3 $and$libresoc.v:34580$1340_Y + connect \$5 $or$libresoc.v:34581$1341_Y + connect \$7 $not$libresoc.v:34582$1342_Y connect \qlq_busy \$15 connect \qn_busy \$13 connect \q_busy \$11 end -attribute \src "libresoc.v:34369.1-35977.10" +attribute \src "libresoc.v:34601.1-36209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" attribute \generator "nMigen" module \clz - attribute \src "libresoc.v:34844.3-34858.6" + attribute \src "libresoc.v:35076.3-35090.6" wire width 2 $0\cnt_1_0[1:0] - attribute \src "libresoc.v:34934.3-34948.6" + attribute \src "libresoc.v:35166.3-35180.6" wire width 2 $0\cnt_1_10[1:0] - attribute \src "libresoc.v:34949.3-34963.6" + attribute \src "libresoc.v:35181.3-35195.6" wire width 2 $0\cnt_1_11[1:0] - attribute \src "libresoc.v:34964.3-34978.6" + attribute \src "libresoc.v:35196.3-35210.6" wire width 2 $0\cnt_1_12[1:0] - attribute \src "libresoc.v:34979.3-34993.6" + attribute \src "libresoc.v:35211.3-35225.6" wire width 2 $0\cnt_1_13[1:0] - attribute \src "libresoc.v:34994.3-35008.6" + attribute \src "libresoc.v:35226.3-35240.6" wire width 2 $0\cnt_1_14[1:0] - attribute \src "libresoc.v:35024.3-35038.6" + attribute \src "libresoc.v:35256.3-35270.6" wire width 2 $0\cnt_1_15[1:0] - attribute \src "libresoc.v:35039.3-35053.6" + attribute \src "libresoc.v:35271.3-35285.6" wire width 2 $0\cnt_1_16[1:0] - attribute \src "libresoc.v:35054.3-35068.6" + attribute \src "libresoc.v:35286.3-35300.6" wire width 2 $0\cnt_1_17[1:0] - attribute \src "libresoc.v:35069.3-35083.6" + attribute \src "libresoc.v:35301.3-35315.6" wire width 2 $0\cnt_1_18[1:0] - attribute \src "libresoc.v:35084.3-35098.6" + attribute \src "libresoc.v:35316.3-35330.6" wire width 2 $0\cnt_1_19[1:0] - attribute \src "libresoc.v:35009.3-35023.6" + attribute \src "libresoc.v:35241.3-35255.6" wire width 2 $0\cnt_1_1[1:0] - attribute \src "libresoc.v:35099.3-35113.6" + attribute \src "libresoc.v:35331.3-35345.6" wire width 2 $0\cnt_1_20[1:0] - attribute \src "libresoc.v:35114.3-35128.6" + attribute \src "libresoc.v:35346.3-35360.6" wire width 2 $0\cnt_1_21[1:0] - attribute \src "libresoc.v:35129.3-35143.6" + attribute \src "libresoc.v:35361.3-35375.6" wire width 2 $0\cnt_1_22[1:0] - attribute \src "libresoc.v:35144.3-35158.6" + attribute \src "libresoc.v:35376.3-35390.6" wire width 2 $0\cnt_1_23[1:0] - attribute \src "libresoc.v:35159.3-35173.6" + attribute \src "libresoc.v:35391.3-35405.6" wire width 2 $0\cnt_1_24[1:0] - attribute \src "libresoc.v:35189.3-35203.6" + attribute \src "libresoc.v:35421.3-35435.6" wire width 2 $0\cnt_1_25[1:0] - attribute \src "libresoc.v:35204.3-35218.6" + attribute \src "libresoc.v:35436.3-35450.6" wire width 2 $0\cnt_1_26[1:0] - attribute \src "libresoc.v:35219.3-35233.6" + attribute \src "libresoc.v:35451.3-35465.6" wire width 2 $0\cnt_1_27[1:0] - attribute \src "libresoc.v:35234.3-35248.6" + attribute \src "libresoc.v:35466.3-35480.6" wire width 2 $0\cnt_1_28[1:0] - attribute \src "libresoc.v:35249.3-35263.6" + attribute \src "libresoc.v:35481.3-35495.6" wire width 2 $0\cnt_1_29[1:0] - attribute \src "libresoc.v:35174.3-35188.6" + attribute \src "libresoc.v:35406.3-35420.6" wire width 2 $0\cnt_1_2[1:0] - attribute \src "libresoc.v:35264.3-35278.6" + attribute \src "libresoc.v:35496.3-35510.6" wire width 2 $0\cnt_1_30[1:0] - attribute \src "libresoc.v:35279.3-35293.6" + attribute \src "libresoc.v:35511.3-35525.6" wire width 2 $0\cnt_1_31[1:0] - attribute \src "libresoc.v:35414.3-35428.6" + attribute \src "libresoc.v:35646.3-35660.6" wire width 2 $0\cnt_1_3[1:0] - attribute \src "libresoc.v:35829.3-35843.6" + attribute \src "libresoc.v:36061.3-36075.6" wire width 2 $0\cnt_1_4[1:0] - attribute \src "libresoc.v:34859.3-34873.6" + attribute \src "libresoc.v:35091.3-35105.6" wire width 2 $0\cnt_1_5[1:0] - attribute \src "libresoc.v:34874.3-34888.6" + attribute \src "libresoc.v:35106.3-35120.6" wire width 2 $0\cnt_1_6[1:0] - attribute \src "libresoc.v:34889.3-34903.6" + attribute \src "libresoc.v:35121.3-35135.6" wire width 2 $0\cnt_1_7[1:0] - attribute \src "libresoc.v:34904.3-34918.6" + attribute \src "libresoc.v:35136.3-35150.6" wire width 2 $0\cnt_1_8[1:0] - attribute \src "libresoc.v:34919.3-34933.6" + attribute \src "libresoc.v:35151.3-35165.6" wire width 2 $0\cnt_1_9[1:0] - attribute \src "libresoc.v:35294.3-35313.6" + attribute \src "libresoc.v:35526.3-35545.6" wire width 3 $0\cnt_2_0[2:0] - attribute \src "libresoc.v:35394.3-35413.6" + attribute \src "libresoc.v:35626.3-35645.6" wire width 3 $0\cnt_2_10[2:0] - attribute \src "libresoc.v:35429.3-35448.6" + attribute \src "libresoc.v:35661.3-35680.6" wire width 3 $0\cnt_2_12[2:0] - attribute \src "libresoc.v:35449.3-35468.6" + attribute \src "libresoc.v:35681.3-35700.6" wire width 3 $0\cnt_2_14[2:0] - attribute \src "libresoc.v:35469.3-35488.6" + attribute \src "libresoc.v:35701.3-35720.6" wire width 3 $0\cnt_2_16[2:0] - attribute \src "libresoc.v:35489.3-35508.6" + attribute \src "libresoc.v:35721.3-35740.6" wire width 3 $0\cnt_2_18[2:0] - attribute \src "libresoc.v:35509.3-35528.6" + attribute \src "libresoc.v:35741.3-35760.6" wire width 3 $0\cnt_2_20[2:0] - attribute \src "libresoc.v:35529.3-35548.6" + attribute \src "libresoc.v:35761.3-35780.6" wire width 3 $0\cnt_2_22[2:0] - attribute \src "libresoc.v:35549.3-35568.6" + attribute \src "libresoc.v:35781.3-35800.6" wire width 3 $0\cnt_2_24[2:0] - attribute \src "libresoc.v:35569.3-35588.6" + attribute \src "libresoc.v:35801.3-35820.6" wire width 3 $0\cnt_2_26[2:0] - attribute \src "libresoc.v:35589.3-35608.6" + attribute \src "libresoc.v:35821.3-35840.6" wire width 3 $0\cnt_2_28[2:0] - attribute \src "libresoc.v:35314.3-35333.6" + attribute \src "libresoc.v:35546.3-35565.6" wire width 3 $0\cnt_2_2[2:0] - attribute \src "libresoc.v:35609.3-35628.6" + attribute \src "libresoc.v:35841.3-35860.6" wire width 3 $0\cnt_2_30[2:0] - attribute \src "libresoc.v:35334.3-35353.6" + attribute \src "libresoc.v:35566.3-35585.6" wire width 3 $0\cnt_2_4[2:0] - attribute \src "libresoc.v:35354.3-35373.6" + attribute \src "libresoc.v:35586.3-35605.6" wire width 3 $0\cnt_2_6[2:0] - attribute \src "libresoc.v:35374.3-35393.6" + attribute \src "libresoc.v:35606.3-35625.6" wire width 3 $0\cnt_2_8[2:0] - attribute \src "libresoc.v:35629.3-35648.6" + attribute \src "libresoc.v:35861.3-35880.6" wire width 4 $0\cnt_3_0[3:0] - attribute \src "libresoc.v:35729.3-35748.6" + attribute \src "libresoc.v:35961.3-35980.6" wire width 4 $0\cnt_3_10[3:0] - attribute \src "libresoc.v:35749.3-35768.6" + attribute \src "libresoc.v:35981.3-36000.6" wire width 4 $0\cnt_3_12[3:0] - attribute \src "libresoc.v:35769.3-35788.6" + attribute \src "libresoc.v:36001.3-36020.6" wire width 4 $0\cnt_3_14[3:0] - attribute \src "libresoc.v:35649.3-35668.6" + attribute \src "libresoc.v:35881.3-35900.6" wire width 4 $0\cnt_3_2[3:0] - attribute \src "libresoc.v:35669.3-35688.6" + attribute \src "libresoc.v:35901.3-35920.6" wire width 4 $0\cnt_3_4[3:0] - attribute \src "libresoc.v:35689.3-35708.6" + attribute \src "libresoc.v:35921.3-35940.6" wire width 4 $0\cnt_3_6[3:0] - attribute \src "libresoc.v:35709.3-35728.6" + attribute \src "libresoc.v:35941.3-35960.6" wire width 4 $0\cnt_3_8[3:0] - attribute \src "libresoc.v:35789.3-35808.6" + attribute \src "libresoc.v:36021.3-36040.6" wire width 5 $0\cnt_4_0[4:0] - attribute \src "libresoc.v:35809.3-35828.6" + attribute \src "libresoc.v:36041.3-36060.6" wire width 5 $0\cnt_4_2[4:0] - attribute \src "libresoc.v:35844.3-35863.6" + attribute \src "libresoc.v:36076.3-36095.6" wire width 5 $0\cnt_4_4[4:0] - attribute \src "libresoc.v:35864.3-35883.6" + attribute \src "libresoc.v:36096.3-36115.6" wire width 5 $0\cnt_4_6[4:0] - attribute \src "libresoc.v:35884.3-35903.6" + attribute \src "libresoc.v:36116.3-36135.6" wire width 6 $0\cnt_5_0[5:0] - attribute \src "libresoc.v:35904.3-35923.6" + attribute \src "libresoc.v:36136.3-36155.6" wire width 6 $0\cnt_5_2[5:0] - attribute \src "libresoc.v:35924.3-35943.6" + attribute \src "libresoc.v:36156.3-36175.6" wire width 7 $0\cnt_6_0[6:0] - attribute \src "libresoc.v:34370.7-34370.20" + attribute \src "libresoc.v:34602.7-34602.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34844.3-34858.6" + attribute \src "libresoc.v:35076.3-35090.6" wire width 2 $1\cnt_1_0[1:0] - attribute \src "libresoc.v:34934.3-34948.6" + attribute \src "libresoc.v:35166.3-35180.6" wire width 2 $1\cnt_1_10[1:0] - attribute \src "libresoc.v:34949.3-34963.6" + attribute \src "libresoc.v:35181.3-35195.6" wire width 2 $1\cnt_1_11[1:0] - attribute \src "libresoc.v:34964.3-34978.6" + attribute \src "libresoc.v:35196.3-35210.6" wire width 2 $1\cnt_1_12[1:0] - attribute \src "libresoc.v:34979.3-34993.6" + attribute \src "libresoc.v:35211.3-35225.6" wire width 2 $1\cnt_1_13[1:0] - attribute \src "libresoc.v:34994.3-35008.6" + attribute \src "libresoc.v:35226.3-35240.6" wire width 2 $1\cnt_1_14[1:0] - attribute \src "libresoc.v:35024.3-35038.6" + attribute \src "libresoc.v:35256.3-35270.6" wire width 2 $1\cnt_1_15[1:0] - attribute \src "libresoc.v:35039.3-35053.6" + attribute \src "libresoc.v:35271.3-35285.6" wire width 2 $1\cnt_1_16[1:0] - attribute \src "libresoc.v:35054.3-35068.6" + attribute \src "libresoc.v:35286.3-35300.6" wire width 2 $1\cnt_1_17[1:0] - attribute \src "libresoc.v:35069.3-35083.6" + attribute \src "libresoc.v:35301.3-35315.6" wire width 2 $1\cnt_1_18[1:0] - attribute \src "libresoc.v:35084.3-35098.6" + attribute \src "libresoc.v:35316.3-35330.6" wire width 2 $1\cnt_1_19[1:0] - attribute \src "libresoc.v:35009.3-35023.6" + attribute \src "libresoc.v:35241.3-35255.6" wire width 2 $1\cnt_1_1[1:0] - attribute \src "libresoc.v:35099.3-35113.6" + attribute \src "libresoc.v:35331.3-35345.6" wire width 2 $1\cnt_1_20[1:0] - attribute \src "libresoc.v:35114.3-35128.6" + attribute \src "libresoc.v:35346.3-35360.6" wire width 2 $1\cnt_1_21[1:0] - attribute \src "libresoc.v:35129.3-35143.6" + attribute \src "libresoc.v:35361.3-35375.6" wire width 2 $1\cnt_1_22[1:0] - attribute \src "libresoc.v:35144.3-35158.6" + attribute \src "libresoc.v:35376.3-35390.6" wire width 2 $1\cnt_1_23[1:0] - attribute \src "libresoc.v:35159.3-35173.6" + attribute \src "libresoc.v:35391.3-35405.6" wire width 2 $1\cnt_1_24[1:0] - attribute \src "libresoc.v:35189.3-35203.6" + attribute \src "libresoc.v:35421.3-35435.6" wire width 2 $1\cnt_1_25[1:0] - attribute \src "libresoc.v:35204.3-35218.6" + attribute \src "libresoc.v:35436.3-35450.6" wire width 2 $1\cnt_1_26[1:0] - attribute \src "libresoc.v:35219.3-35233.6" + attribute \src "libresoc.v:35451.3-35465.6" wire width 2 $1\cnt_1_27[1:0] - attribute \src "libresoc.v:35234.3-35248.6" + attribute \src "libresoc.v:35466.3-35480.6" wire width 2 $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35249.3-35263.6" + attribute \src "libresoc.v:35481.3-35495.6" wire width 2 $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35174.3-35188.6" + attribute \src "libresoc.v:35406.3-35420.6" wire width 2 $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35264.3-35278.6" + attribute \src "libresoc.v:35496.3-35510.6" wire width 2 $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35279.3-35293.6" + attribute \src "libresoc.v:35511.3-35525.6" wire width 2 $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35414.3-35428.6" + attribute \src "libresoc.v:35646.3-35660.6" wire width 2 $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35829.3-35843.6" + attribute \src "libresoc.v:36061.3-36075.6" wire width 2 $1\cnt_1_4[1:0] - attribute \src "libresoc.v:34859.3-34873.6" + attribute \src "libresoc.v:35091.3-35105.6" wire width 2 $1\cnt_1_5[1:0] - attribute \src "libresoc.v:34874.3-34888.6" + attribute \src "libresoc.v:35106.3-35120.6" wire width 2 $1\cnt_1_6[1:0] - attribute \src "libresoc.v:34889.3-34903.6" + attribute \src "libresoc.v:35121.3-35135.6" wire width 2 $1\cnt_1_7[1:0] - attribute \src "libresoc.v:34904.3-34918.6" + attribute \src "libresoc.v:35136.3-35150.6" wire width 2 $1\cnt_1_8[1:0] - attribute \src "libresoc.v:34919.3-34933.6" + attribute \src "libresoc.v:35151.3-35165.6" wire width 2 $1\cnt_1_9[1:0] - attribute \src "libresoc.v:35294.3-35313.6" + attribute \src "libresoc.v:35526.3-35545.6" wire width 3 $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35394.3-35413.6" + attribute \src "libresoc.v:35626.3-35645.6" wire width 3 $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35429.3-35448.6" + attribute \src "libresoc.v:35661.3-35680.6" wire width 3 $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35449.3-35468.6" + attribute \src "libresoc.v:35681.3-35700.6" wire width 3 $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35469.3-35488.6" + attribute \src "libresoc.v:35701.3-35720.6" wire width 3 $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35489.3-35508.6" + attribute \src "libresoc.v:35721.3-35740.6" wire width 3 $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35509.3-35528.6" + attribute \src "libresoc.v:35741.3-35760.6" wire width 3 $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35529.3-35548.6" + attribute \src "libresoc.v:35761.3-35780.6" wire width 3 $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35549.3-35568.6" + attribute \src "libresoc.v:35781.3-35800.6" wire width 3 $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35569.3-35588.6" + attribute \src "libresoc.v:35801.3-35820.6" wire width 3 $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35589.3-35608.6" + attribute \src "libresoc.v:35821.3-35840.6" wire width 3 $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35314.3-35333.6" + attribute \src "libresoc.v:35546.3-35565.6" wire width 3 $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35609.3-35628.6" + attribute \src "libresoc.v:35841.3-35860.6" wire width 3 $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35334.3-35353.6" + attribute \src "libresoc.v:35566.3-35585.6" wire width 3 $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35354.3-35373.6" + attribute \src "libresoc.v:35586.3-35605.6" wire width 3 $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35374.3-35393.6" + attribute \src "libresoc.v:35606.3-35625.6" wire width 3 $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35629.3-35648.6" + attribute \src "libresoc.v:35861.3-35880.6" wire width 4 $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35729.3-35748.6" + attribute \src "libresoc.v:35961.3-35980.6" wire width 4 $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35749.3-35768.6" + attribute \src "libresoc.v:35981.3-36000.6" wire width 4 $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35769.3-35788.6" + attribute \src "libresoc.v:36001.3-36020.6" wire width 4 $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35649.3-35668.6" + attribute \src "libresoc.v:35881.3-35900.6" wire width 4 $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35669.3-35688.6" + attribute \src "libresoc.v:35901.3-35920.6" wire width 4 $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35689.3-35708.6" + attribute \src "libresoc.v:35921.3-35940.6" wire width 4 $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35709.3-35728.6" + attribute \src "libresoc.v:35941.3-35960.6" wire width 4 $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35789.3-35808.6" + attribute \src "libresoc.v:36021.3-36040.6" wire width 5 $1\cnt_4_0[4:0] - attribute \src "libresoc.v:35809.3-35828.6" + attribute \src "libresoc.v:36041.3-36060.6" wire width 5 $1\cnt_4_2[4:0] - attribute \src "libresoc.v:35844.3-35863.6" + attribute \src "libresoc.v:36076.3-36095.6" wire width 5 $1\cnt_4_4[4:0] - attribute \src "libresoc.v:35864.3-35883.6" + attribute \src "libresoc.v:36096.3-36115.6" wire width 5 $1\cnt_4_6[4:0] - attribute \src "libresoc.v:35884.3-35903.6" + attribute \src "libresoc.v:36116.3-36135.6" wire width 6 $1\cnt_5_0[5:0] - attribute \src "libresoc.v:35904.3-35923.6" + attribute \src "libresoc.v:36136.3-36155.6" wire width 6 $1\cnt_5_2[5:0] - attribute \src "libresoc.v:35924.3-35943.6" + attribute \src "libresoc.v:36156.3-36175.6" wire width 7 $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35294.3-35313.6" + attribute \src "libresoc.v:35526.3-35545.6" wire width 3 $2\cnt_2_0[2:0] - attribute \src "libresoc.v:35394.3-35413.6" + attribute \src "libresoc.v:35626.3-35645.6" wire width 3 $2\cnt_2_10[2:0] - attribute \src "libresoc.v:35429.3-35448.6" + attribute \src "libresoc.v:35661.3-35680.6" wire width 3 $2\cnt_2_12[2:0] - attribute \src "libresoc.v:35449.3-35468.6" + attribute \src "libresoc.v:35681.3-35700.6" wire width 3 $2\cnt_2_14[2:0] - attribute \src "libresoc.v:35469.3-35488.6" + attribute \src "libresoc.v:35701.3-35720.6" wire width 3 $2\cnt_2_16[2:0] - attribute \src "libresoc.v:35489.3-35508.6" + attribute \src "libresoc.v:35721.3-35740.6" wire width 3 $2\cnt_2_18[2:0] - attribute \src "libresoc.v:35509.3-35528.6" + attribute \src "libresoc.v:35741.3-35760.6" wire width 3 $2\cnt_2_20[2:0] - attribute \src "libresoc.v:35529.3-35548.6" + attribute \src "libresoc.v:35761.3-35780.6" wire width 3 $2\cnt_2_22[2:0] - attribute \src "libresoc.v:35549.3-35568.6" + attribute \src "libresoc.v:35781.3-35800.6" wire width 3 $2\cnt_2_24[2:0] - attribute \src "libresoc.v:35569.3-35588.6" + attribute \src "libresoc.v:35801.3-35820.6" wire width 3 $2\cnt_2_26[2:0] - attribute \src "libresoc.v:35589.3-35608.6" + attribute \src "libresoc.v:35821.3-35840.6" wire width 3 $2\cnt_2_28[2:0] - attribute \src "libresoc.v:35314.3-35333.6" + attribute \src "libresoc.v:35546.3-35565.6" wire width 3 $2\cnt_2_2[2:0] - attribute \src "libresoc.v:35609.3-35628.6" + attribute \src "libresoc.v:35841.3-35860.6" wire width 3 $2\cnt_2_30[2:0] - attribute \src "libresoc.v:35334.3-35353.6" + attribute \src "libresoc.v:35566.3-35585.6" wire width 3 $2\cnt_2_4[2:0] - attribute \src "libresoc.v:35354.3-35373.6" + attribute \src "libresoc.v:35586.3-35605.6" wire width 3 $2\cnt_2_6[2:0] - attribute \src "libresoc.v:35374.3-35393.6" + attribute \src "libresoc.v:35606.3-35625.6" wire width 3 $2\cnt_2_8[2:0] - attribute \src "libresoc.v:35629.3-35648.6" + attribute \src "libresoc.v:35861.3-35880.6" wire width 4 $2\cnt_3_0[3:0] - attribute \src "libresoc.v:35729.3-35748.6" + attribute \src "libresoc.v:35961.3-35980.6" wire width 4 $2\cnt_3_10[3:0] - attribute \src "libresoc.v:35749.3-35768.6" + attribute \src "libresoc.v:35981.3-36000.6" wire width 4 $2\cnt_3_12[3:0] - attribute \src "libresoc.v:35769.3-35788.6" + attribute \src "libresoc.v:36001.3-36020.6" wire width 4 $2\cnt_3_14[3:0] - attribute \src "libresoc.v:35649.3-35668.6" + attribute \src "libresoc.v:35881.3-35900.6" wire width 4 $2\cnt_3_2[3:0] - attribute \src "libresoc.v:35669.3-35688.6" + attribute \src "libresoc.v:35901.3-35920.6" wire width 4 $2\cnt_3_4[3:0] - attribute \src "libresoc.v:35689.3-35708.6" + attribute \src "libresoc.v:35921.3-35940.6" wire width 4 $2\cnt_3_6[3:0] - attribute \src "libresoc.v:35709.3-35728.6" + attribute \src "libresoc.v:35941.3-35960.6" wire width 4 $2\cnt_3_8[3:0] - attribute \src "libresoc.v:35789.3-35808.6" + attribute \src "libresoc.v:36021.3-36040.6" wire width 5 $2\cnt_4_0[4:0] - attribute \src "libresoc.v:35809.3-35828.6" + attribute \src "libresoc.v:36041.3-36060.6" wire width 5 $2\cnt_4_2[4:0] - attribute \src "libresoc.v:35844.3-35863.6" + attribute \src "libresoc.v:36076.3-36095.6" wire width 5 $2\cnt_4_4[4:0] - attribute \src "libresoc.v:35864.3-35883.6" + attribute \src "libresoc.v:36096.3-36115.6" wire width 5 $2\cnt_4_6[4:0] - attribute \src "libresoc.v:35884.3-35903.6" + attribute \src "libresoc.v:36116.3-36135.6" wire width 6 $2\cnt_5_0[5:0] - attribute \src "libresoc.v:35904.3-35923.6" + attribute \src "libresoc.v:36136.3-36155.6" wire width 6 $2\cnt_5_2[5:0] - attribute \src "libresoc.v:35924.3-35943.6" + attribute \src "libresoc.v:36156.3-36175.6" wire width 7 $2\cnt_6_0[6:0] - attribute \src "libresoc.v:34751.17-34751.101" - wire $eq$libresoc.v:34751$1349_Y - attribute \src "libresoc.v:34752.18-34752.102" - wire $eq$libresoc.v:34752$1350_Y - attribute \src "libresoc.v:34754.19-34754.103" - wire $eq$libresoc.v:34754$1352_Y - attribute \src "libresoc.v:34755.19-34755.103" - wire $eq$libresoc.v:34755$1353_Y - attribute \src "libresoc.v:34757.19-34757.104" - wire $eq$libresoc.v:34757$1355_Y - attribute \src "libresoc.v:34758.19-34758.103" - wire $eq$libresoc.v:34758$1356_Y - attribute \src "libresoc.v:34760.19-34760.104" - wire $eq$libresoc.v:34760$1358_Y - attribute \src "libresoc.v:34761.19-34761.104" - wire $eq$libresoc.v:34761$1359_Y - attribute \src "libresoc.v:34764.19-34764.104" - wire $eq$libresoc.v:34764$1362_Y - attribute \src "libresoc.v:34765.19-34765.104" - wire $eq$libresoc.v:34765$1363_Y - attribute \src "libresoc.v:34767.19-34767.104" - wire $eq$libresoc.v:34767$1365_Y - attribute \src "libresoc.v:34768.19-34768.104" - wire $eq$libresoc.v:34768$1366_Y - attribute \src "libresoc.v:34770.19-34770.104" - wire $eq$libresoc.v:34770$1368_Y - attribute \src "libresoc.v:34771.19-34771.104" - wire $eq$libresoc.v:34771$1369_Y - attribute \src "libresoc.v:34773.18-34773.102" - wire $eq$libresoc.v:34773$1371_Y - attribute \src "libresoc.v:34774.19-34774.104" - wire $eq$libresoc.v:34774$1372_Y - attribute \src "libresoc.v:34775.19-34775.104" - wire $eq$libresoc.v:34775$1373_Y - attribute \src "libresoc.v:34777.19-34777.103" - wire $eq$libresoc.v:34777$1375_Y - attribute \src "libresoc.v:34778.19-34778.103" - wire $eq$libresoc.v:34778$1376_Y - attribute \src "libresoc.v:34780.19-34780.103" - wire $eq$libresoc.v:34780$1378_Y - attribute \src "libresoc.v:34781.19-34781.103" - wire $eq$libresoc.v:34781$1379_Y - attribute \src "libresoc.v:34783.19-34783.104" - wire $eq$libresoc.v:34783$1381_Y - attribute \src "libresoc.v:34784.18-34784.102" - wire $eq$libresoc.v:34784$1382_Y - attribute \src "libresoc.v:34785.19-34785.103" - wire $eq$libresoc.v:34785$1383_Y - attribute \src "libresoc.v:34787.19-34787.104" - wire $eq$libresoc.v:34787$1385_Y - attribute \src "libresoc.v:34788.19-34788.104" - wire $eq$libresoc.v:34788$1386_Y - attribute \src "libresoc.v:34790.19-34790.103" - wire $eq$libresoc.v:34790$1388_Y - attribute \src "libresoc.v:34791.19-34791.103" - wire $eq$libresoc.v:34791$1389_Y - attribute \src "libresoc.v:34793.19-34793.103" - wire $eq$libresoc.v:34793$1391_Y - attribute \src "libresoc.v:34794.19-34794.103" - wire $eq$libresoc.v:34794$1392_Y - attribute \src "libresoc.v:34797.19-34797.103" - wire $eq$libresoc.v:34797$1395_Y - attribute \src "libresoc.v:34798.19-34798.103" - wire $eq$libresoc.v:34798$1396_Y - attribute \src "libresoc.v:34800.17-34800.101" - wire $eq$libresoc.v:34800$1398_Y - attribute \src "libresoc.v:34801.18-34801.102" - wire $eq$libresoc.v:34801$1399_Y - attribute \src "libresoc.v:34802.18-34802.102" - wire $eq$libresoc.v:34802$1400_Y - attribute \src "libresoc.v:34804.18-34804.102" - wire $eq$libresoc.v:34804$1402_Y - attribute \src "libresoc.v:34805.18-34805.102" - wire $eq$libresoc.v:34805$1403_Y - attribute \src "libresoc.v:34807.18-34807.103" - wire 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"libresoc.v:34843.18-34843.102" - wire $eq$libresoc.v:34843$1441_Y - attribute \src "libresoc.v:34753.19-34753.109" - wire width 4 $pos$libresoc.v:34753$1351_Y - attribute \src "libresoc.v:34756.19-34756.109" - wire width 4 $pos$libresoc.v:34756$1354_Y - attribute \src "libresoc.v:34759.19-34759.109" - wire width 4 $pos$libresoc.v:34759$1357_Y - attribute \src "libresoc.v:34762.18-34762.106" - wire width 3 $pos$libresoc.v:34762$1360_Y - attribute \src "libresoc.v:34763.19-34763.110" - wire width 4 $pos$libresoc.v:34763$1361_Y - attribute \src "libresoc.v:34766.19-34766.110" - wire width 4 $pos$libresoc.v:34766$1364_Y - attribute \src "libresoc.v:34769.19-34769.110" - wire width 4 $pos$libresoc.v:34769$1367_Y - attribute \src "libresoc.v:34772.19-34772.110" - wire width 4 $pos$libresoc.v:34772$1370_Y - attribute \src "libresoc.v:34776.19-34776.110" - wire width 4 $pos$libresoc.v:34776$1374_Y - attribute \src "libresoc.v:34779.19-34779.109" - wire width 5 $pos$libresoc.v:34779$1377_Y - attribute \src "libresoc.v:34782.19-34782.109" - wire width 5 $pos$libresoc.v:34782$1380_Y - attribute \src "libresoc.v:34786.19-34786.109" - wire width 5 $pos$libresoc.v:34786$1384_Y - attribute \src "libresoc.v:34789.19-34789.110" - wire width 5 $pos$libresoc.v:34789$1387_Y - attribute \src "libresoc.v:34792.19-34792.109" - wire width 6 $pos$libresoc.v:34792$1390_Y - attribute \src "libresoc.v:34795.18-34795.106" - wire width 3 $pos$libresoc.v:34795$1393_Y - attribute \src "libresoc.v:34796.19-34796.109" - wire width 6 $pos$libresoc.v:34796$1394_Y - attribute \src "libresoc.v:34799.19-34799.109" - wire width 7 $pos$libresoc.v:34799$1397_Y - attribute \src "libresoc.v:34803.18-34803.106" - wire width 3 $pos$libresoc.v:34803$1401_Y - attribute \src "libresoc.v:34806.18-34806.106" - wire width 3 $pos$libresoc.v:34806$1404_Y - attribute \src "libresoc.v:34809.18-34809.107" - wire width 3 $pos$libresoc.v:34809$1407_Y - attribute \src "libresoc.v:34813.18-34813.107" - wire width 3 $pos$libresoc.v:34813$1411_Y - attribute \src "libresoc.v:34816.18-34816.107" - wire width 3 $pos$libresoc.v:34816$1414_Y - attribute \src "libresoc.v:34819.18-34819.107" - wire width 3 $pos$libresoc.v:34819$1417_Y - attribute \src "libresoc.v:34822.17-34822.105" - wire width 3 $pos$libresoc.v:34822$1420_Y - attribute \src "libresoc.v:34823.18-34823.107" - wire width 3 $pos$libresoc.v:34823$1421_Y - attribute \src "libresoc.v:34826.18-34826.107" - wire width 3 $pos$libresoc.v:34826$1424_Y - attribute \src "libresoc.v:34829.18-34829.107" - wire width 3 $pos$libresoc.v:34829$1427_Y - attribute \src "libresoc.v:34832.18-34832.107" - wire width 3 $pos$libresoc.v:34832$1430_Y - attribute \src "libresoc.v:34836.18-34836.107" - wire width 3 $pos$libresoc.v:34836$1434_Y - attribute \src "libresoc.v:34839.18-34839.107" - wire width 3 $pos$libresoc.v:34839$1437_Y - attribute \src "libresoc.v:34842.18-34842.107" - wire width 3 $pos$libresoc.v:34842$1440_Y + attribute \src "libresoc.v:34983.17-34983.101" + wire $eq$libresoc.v:34983$1349_Y + attribute \src "libresoc.v:34984.18-34984.102" + wire $eq$libresoc.v:34984$1350_Y + attribute \src "libresoc.v:34986.19-34986.103" + wire $eq$libresoc.v:34986$1352_Y + attribute \src "libresoc.v:34987.19-34987.103" + wire $eq$libresoc.v:34987$1353_Y + attribute \src "libresoc.v:34989.19-34989.104" + wire $eq$libresoc.v:34989$1355_Y + attribute \src "libresoc.v:34990.19-34990.103" + wire $eq$libresoc.v:34990$1356_Y + attribute \src "libresoc.v:34992.19-34992.104" + wire $eq$libresoc.v:34992$1358_Y + attribute \src "libresoc.v:34993.19-34993.104" + wire $eq$libresoc.v:34993$1359_Y + attribute \src "libresoc.v:34996.19-34996.104" + wire $eq$libresoc.v:34996$1362_Y + attribute \src "libresoc.v:34997.19-34997.104" + wire $eq$libresoc.v:34997$1363_Y + attribute \src "libresoc.v:34999.19-34999.104" + wire $eq$libresoc.v:34999$1365_Y + attribute \src "libresoc.v:35000.19-35000.104" + wire $eq$libresoc.v:35000$1366_Y + attribute \src "libresoc.v:35002.19-35002.104" + wire $eq$libresoc.v:35002$1368_Y + attribute \src "libresoc.v:35003.19-35003.104" + wire $eq$libresoc.v:35003$1369_Y + attribute \src "libresoc.v:35005.18-35005.102" + wire $eq$libresoc.v:35005$1371_Y + attribute \src "libresoc.v:35006.19-35006.104" + wire $eq$libresoc.v:35006$1372_Y + attribute \src "libresoc.v:35007.19-35007.104" + wire $eq$libresoc.v:35007$1373_Y + attribute \src "libresoc.v:35009.19-35009.103" + wire $eq$libresoc.v:35009$1375_Y + attribute \src "libresoc.v:35010.19-35010.103" + wire $eq$libresoc.v:35010$1376_Y + attribute \src "libresoc.v:35012.19-35012.103" + wire $eq$libresoc.v:35012$1378_Y + attribute \src "libresoc.v:35013.19-35013.103" + wire $eq$libresoc.v:35013$1379_Y + attribute \src "libresoc.v:35015.19-35015.104" + wire $eq$libresoc.v:35015$1381_Y + attribute \src "libresoc.v:35016.18-35016.102" + wire $eq$libresoc.v:35016$1382_Y + attribute \src "libresoc.v:35017.19-35017.103" + wire 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"libresoc.v:35053.18-35053.103" + wire $eq$libresoc.v:35053$1419_Y + attribute \src "libresoc.v:35056.18-35056.103" + wire $eq$libresoc.v:35056$1422_Y + attribute \src "libresoc.v:35057.18-35057.103" + wire $eq$libresoc.v:35057$1423_Y + attribute \src "libresoc.v:35059.18-35059.103" + wire $eq$libresoc.v:35059$1425_Y + attribute \src "libresoc.v:35060.18-35060.103" + wire $eq$libresoc.v:35060$1426_Y + attribute \src "libresoc.v:35062.18-35062.103" + wire $eq$libresoc.v:35062$1428_Y + attribute \src "libresoc.v:35063.18-35063.103" + wire $eq$libresoc.v:35063$1429_Y + attribute \src "libresoc.v:35065.17-35065.101" + wire $eq$libresoc.v:35065$1431_Y + attribute \src "libresoc.v:35066.18-35066.103" + wire $eq$libresoc.v:35066$1432_Y + attribute \src "libresoc.v:35067.18-35067.103" + wire $eq$libresoc.v:35067$1433_Y + attribute \src "libresoc.v:35069.18-35069.103" + wire $eq$libresoc.v:35069$1435_Y + attribute \src "libresoc.v:35070.18-35070.103" + wire $eq$libresoc.v:35070$1436_Y + attribute \src "libresoc.v:35072.18-35072.103" + wire $eq$libresoc.v:35072$1438_Y + attribute \src "libresoc.v:35073.18-35073.103" + wire $eq$libresoc.v:35073$1439_Y + attribute \src "libresoc.v:35075.18-35075.102" + wire $eq$libresoc.v:35075$1441_Y + attribute \src "libresoc.v:34985.19-34985.109" + wire width 4 $pos$libresoc.v:34985$1351_Y + attribute \src "libresoc.v:34988.19-34988.109" + wire width 4 $pos$libresoc.v:34988$1354_Y + attribute \src "libresoc.v:34991.19-34991.109" + wire width 4 $pos$libresoc.v:34991$1357_Y + attribute \src "libresoc.v:34994.18-34994.106" + wire width 3 $pos$libresoc.v:34994$1360_Y + attribute \src "libresoc.v:34995.19-34995.110" + wire width 4 $pos$libresoc.v:34995$1361_Y + attribute \src "libresoc.v:34998.19-34998.110" + wire width 4 $pos$libresoc.v:34998$1364_Y + attribute \src "libresoc.v:35001.19-35001.110" + wire width 4 $pos$libresoc.v:35001$1367_Y + attribute \src "libresoc.v:35004.19-35004.110" + wire width 4 $pos$libresoc.v:35004$1370_Y + attribute \src "libresoc.v:35008.19-35008.110" + wire width 4 $pos$libresoc.v:35008$1374_Y + attribute \src "libresoc.v:35011.19-35011.109" + wire width 5 $pos$libresoc.v:35011$1377_Y + attribute \src "libresoc.v:35014.19-35014.109" + wire width 5 $pos$libresoc.v:35014$1380_Y + attribute \src "libresoc.v:35018.19-35018.109" + wire width 5 $pos$libresoc.v:35018$1384_Y + attribute \src "libresoc.v:35021.19-35021.110" + wire width 5 $pos$libresoc.v:35021$1387_Y + attribute \src "libresoc.v:35024.19-35024.109" + wire width 6 $pos$libresoc.v:35024$1390_Y + attribute \src "libresoc.v:35027.18-35027.106" + wire width 3 $pos$libresoc.v:35027$1393_Y + attribute \src "libresoc.v:35028.19-35028.109" + wire width 6 $pos$libresoc.v:35028$1394_Y + attribute \src "libresoc.v:35031.19-35031.109" + wire width 7 $pos$libresoc.v:35031$1397_Y + attribute \src "libresoc.v:35035.18-35035.106" + wire width 3 $pos$libresoc.v:35035$1401_Y + attribute \src "libresoc.v:35038.18-35038.106" + wire width 3 $pos$libresoc.v:35038$1404_Y + attribute \src "libresoc.v:35041.18-35041.107" + wire width 3 $pos$libresoc.v:35041$1407_Y + attribute \src "libresoc.v:35045.18-35045.107" + wire width 3 $pos$libresoc.v:35045$1411_Y + attribute \src "libresoc.v:35048.18-35048.107" + wire width 3 $pos$libresoc.v:35048$1414_Y + attribute \src "libresoc.v:35051.18-35051.107" + wire width 3 $pos$libresoc.v:35051$1417_Y + attribute \src "libresoc.v:35054.17-35054.105" + wire width 3 $pos$libresoc.v:35054$1420_Y + attribute \src "libresoc.v:35055.18-35055.107" + wire width 3 $pos$libresoc.v:35055$1421_Y + attribute \src "libresoc.v:35058.18-35058.107" + wire width 3 $pos$libresoc.v:35058$1424_Y + attribute \src "libresoc.v:35061.18-35061.107" + wire width 3 $pos$libresoc.v:35061$1427_Y + attribute \src "libresoc.v:35064.18-35064.107" + wire width 3 $pos$libresoc.v:35064$1430_Y + attribute \src "libresoc.v:35068.18-35068.107" + wire width 3 $pos$libresoc.v:35068$1434_Y + attribute \src "libresoc.v:35071.18-35071.107" + wire width 3 $pos$libresoc.v:35071$1437_Y + attribute \src "libresoc.v:35074.18-35074.107" + wire width 3 $pos$libresoc.v:35074$1440_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" @@ -53584,7 +53816,7 @@ module \clz wire width 6 \cnt_5_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 7 \cnt_6_0 - attribute \src "libresoc.v:34370.7-34370.15" + attribute \src "libresoc.v:34602.7-34602.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 7 output 1 \lz @@ -53655,7 +53887,7 @@ module \clz attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" wire width 64 input 2 \sig_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34751$1349 + cell $eq $eq$libresoc.v:34983$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53663,10 +53895,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_2 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34751$1349_Y + connect \Y $eq$libresoc.v:34983$1349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34752$1350 + cell $eq $eq$libresoc.v:34984$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53674,10 +53906,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_0 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34752$1350_Y + connect \Y $eq$libresoc.v:34984$1350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34754$1352 + cell $eq $eq$libresoc.v:34986$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53685,10 +53917,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_6 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34754$1352_Y + connect \Y $eq$libresoc.v:34986$1352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34755$1353 + cell $eq $eq$libresoc.v:34987$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53696,10 +53928,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_4 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34755$1353_Y + connect \Y $eq$libresoc.v:34987$1353_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34757$1355 + cell $eq $eq$libresoc.v:34989$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53707,10 +53939,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_10 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34757$1355_Y + connect \Y $eq$libresoc.v:34989$1355_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34758$1356 + cell $eq $eq$libresoc.v:34990$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53718,10 +53950,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_8 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34758$1356_Y + connect \Y $eq$libresoc.v:34990$1356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34760$1358 + cell $eq $eq$libresoc.v:34992$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53729,10 +53961,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_14 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34760$1358_Y + connect \Y $eq$libresoc.v:34992$1358_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34761$1359 + cell $eq $eq$libresoc.v:34993$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53740,10 +53972,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_12 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34761$1359_Y + connect \Y $eq$libresoc.v:34993$1359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34764$1362 + cell $eq $eq$libresoc.v:34996$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53751,10 +53983,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_18 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34764$1362_Y + connect \Y $eq$libresoc.v:34996$1362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34765$1363 + cell $eq $eq$libresoc.v:34997$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53762,10 +53994,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_16 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34765$1363_Y + connect \Y $eq$libresoc.v:34997$1363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34767$1365 + cell $eq $eq$libresoc.v:34999$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53773,10 +54005,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_22 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34767$1365_Y + connect \Y $eq$libresoc.v:34999$1365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34768$1366 + cell $eq $eq$libresoc.v:35000$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53784,10 +54016,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_20 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34768$1366_Y + connect \Y $eq$libresoc.v:35000$1366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34770$1368 + cell $eq $eq$libresoc.v:35002$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53795,10 +54027,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_26 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34770$1368_Y + connect \Y $eq$libresoc.v:35002$1368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34771$1369 + cell $eq $eq$libresoc.v:35003$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53806,10 +54038,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_24 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34771$1369_Y + connect \Y $eq$libresoc.v:35003$1369_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34773$1371 + cell $eq $eq$libresoc.v:35005$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53817,10 +54049,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_5 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34773$1371_Y + connect \Y $eq$libresoc.v:35005$1371_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34774$1372 + cell $eq $eq$libresoc.v:35006$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53828,10 +54060,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_30 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34774$1372_Y + connect \Y $eq$libresoc.v:35006$1372_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34775$1373 + cell $eq $eq$libresoc.v:35007$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53839,10 +54071,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_28 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34775$1373_Y + connect \Y $eq$libresoc.v:35007$1373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34777$1375 + cell $eq $eq$libresoc.v:35009$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53850,10 +54082,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_2 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34777$1375_Y + connect \Y $eq$libresoc.v:35009$1375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34778$1376 + cell $eq $eq$libresoc.v:35010$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53861,10 +54093,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_0 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34778$1376_Y + connect \Y $eq$libresoc.v:35010$1376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34780$1378 + cell $eq $eq$libresoc.v:35012$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53872,10 +54104,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_6 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34780$1378_Y + connect \Y $eq$libresoc.v:35012$1378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34781$1379 + cell $eq $eq$libresoc.v:35013$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53883,10 +54115,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_4 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34781$1379_Y + connect \Y $eq$libresoc.v:35013$1379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34783$1381 + cell $eq $eq$libresoc.v:35015$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53894,10 +54126,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_10 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34783$1381_Y + connect \Y $eq$libresoc.v:35015$1381_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34784$1382 + cell $eq $eq$libresoc.v:35016$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53905,10 +54137,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_4 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34784$1382_Y + connect \Y $eq$libresoc.v:35016$1382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34785$1383 + cell $eq $eq$libresoc.v:35017$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53916,10 +54148,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_8 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34785$1383_Y + connect \Y $eq$libresoc.v:35017$1383_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34787$1385 + cell $eq $eq$libresoc.v:35019$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53927,10 +54159,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_14 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34787$1385_Y + connect \Y $eq$libresoc.v:35019$1385_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34788$1386 + cell $eq $eq$libresoc.v:35020$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53938,10 +54170,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_12 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34788$1386_Y + connect \Y $eq$libresoc.v:35020$1386_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34790$1388 + cell $eq $eq$libresoc.v:35022$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53949,10 +54181,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_2 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34790$1388_Y + connect \Y $eq$libresoc.v:35022$1388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34791$1389 + cell $eq $eq$libresoc.v:35023$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53960,10 +54192,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_0 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34791$1389_Y + connect \Y $eq$libresoc.v:35023$1389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34793$1391 + cell $eq $eq$libresoc.v:35025$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53971,10 +54203,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_6 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34793$1391_Y + connect \Y $eq$libresoc.v:35025$1391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34794$1392 + cell $eq $eq$libresoc.v:35026$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53982,10 +54214,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_4 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34794$1392_Y + connect \Y $eq$libresoc.v:35026$1392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34797$1395 + cell $eq $eq$libresoc.v:35029$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53993,10 +54225,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_2 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:34797$1395_Y + connect \Y $eq$libresoc.v:35029$1395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34798$1396 + cell $eq $eq$libresoc.v:35030$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54004,10 +54236,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_0 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:34798$1396_Y + connect \Y $eq$libresoc.v:35030$1396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34800$1398 + cell $eq $eq$libresoc.v:35032$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54015,10 +54247,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_1 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34800$1398_Y + connect \Y $eq$libresoc.v:35032$1398_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34801$1399 + cell $eq $eq$libresoc.v:35033$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54026,10 +54258,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_7 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34801$1399_Y + connect \Y $eq$libresoc.v:35033$1399_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34802$1400 + cell $eq $eq$libresoc.v:35034$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54037,10 +54269,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_6 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34802$1400_Y + connect \Y $eq$libresoc.v:35034$1400_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34804$1402 + cell $eq $eq$libresoc.v:35036$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54048,10 +54280,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_9 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34804$1402_Y + connect \Y $eq$libresoc.v:35036$1402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34805$1403 + cell $eq $eq$libresoc.v:35037$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54059,10 +54291,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_8 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34805$1403_Y + connect \Y $eq$libresoc.v:35037$1403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34807$1405 + cell $eq $eq$libresoc.v:35039$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54070,10 +54302,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_11 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34807$1405_Y + connect \Y $eq$libresoc.v:35039$1405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34808$1406 + cell $eq $eq$libresoc.v:35040$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54081,10 +54313,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_10 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34808$1406_Y + connect \Y $eq$libresoc.v:35040$1406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34810$1408 + cell $eq $eq$libresoc.v:35042$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54092,10 +54324,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_13 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34810$1408_Y + connect \Y $eq$libresoc.v:35042$1408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34811$1409 + cell $eq $eq$libresoc.v:35043$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54103,10 +54335,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_0 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34811$1409_Y + connect \Y $eq$libresoc.v:35043$1409_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34812$1410 + cell $eq $eq$libresoc.v:35044$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54114,10 +54346,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_12 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34812$1410_Y + connect \Y $eq$libresoc.v:35044$1410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34814$1412 + cell $eq $eq$libresoc.v:35046$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54125,10 +54357,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_15 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34814$1412_Y + connect \Y $eq$libresoc.v:35046$1412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34815$1413 + cell $eq $eq$libresoc.v:35047$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54136,10 +54368,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_14 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34815$1413_Y + connect \Y $eq$libresoc.v:35047$1413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34817$1415 + cell $eq $eq$libresoc.v:35049$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54147,10 +54379,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_17 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34817$1415_Y + connect \Y $eq$libresoc.v:35049$1415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34818$1416 + cell $eq $eq$libresoc.v:35050$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54158,10 +54390,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_16 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34818$1416_Y + connect \Y $eq$libresoc.v:35050$1416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34820$1418 + cell $eq $eq$libresoc.v:35052$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54169,10 +54401,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_19 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34820$1418_Y + connect \Y $eq$libresoc.v:35052$1418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34821$1419 + cell $eq $eq$libresoc.v:35053$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54180,10 +54412,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_18 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34821$1419_Y + connect \Y $eq$libresoc.v:35053$1419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34824$1422 + cell $eq $eq$libresoc.v:35056$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54191,10 +54423,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_21 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34824$1422_Y + connect \Y $eq$libresoc.v:35056$1422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34825$1423 + cell $eq $eq$libresoc.v:35057$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54202,10 +54434,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_20 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34825$1423_Y + connect \Y $eq$libresoc.v:35057$1423_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34827$1425 + cell $eq $eq$libresoc.v:35059$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54213,10 +54445,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_23 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34827$1425_Y + connect \Y $eq$libresoc.v:35059$1425_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34828$1426 + cell $eq $eq$libresoc.v:35060$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54224,10 +54456,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_22 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34828$1426_Y + connect \Y $eq$libresoc.v:35060$1426_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34830$1428 + cell $eq $eq$libresoc.v:35062$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54235,10 +54467,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_25 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34830$1428_Y + connect \Y $eq$libresoc.v:35062$1428_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34831$1429 + cell $eq $eq$libresoc.v:35063$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54246,10 +54478,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_24 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34831$1429_Y + connect \Y $eq$libresoc.v:35063$1429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34833$1431 + cell $eq $eq$libresoc.v:35065$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54257,10 +54489,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_3 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34833$1431_Y + connect \Y $eq$libresoc.v:35065$1431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34834$1432 + cell $eq $eq$libresoc.v:35066$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54268,10 +54500,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_27 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34834$1432_Y + connect \Y $eq$libresoc.v:35066$1432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34835$1433 + cell $eq $eq$libresoc.v:35067$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54279,10 +54511,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_26 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34835$1433_Y + connect \Y $eq$libresoc.v:35067$1433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34837$1435 + cell $eq $eq$libresoc.v:35069$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54290,10 +54522,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_29 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34837$1435_Y + connect \Y $eq$libresoc.v:35069$1435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34838$1436 + cell $eq $eq$libresoc.v:35070$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54301,10 +54533,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_28 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34838$1436_Y + connect \Y $eq$libresoc.v:35070$1436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34840$1438 + cell $eq $eq$libresoc.v:35072$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54312,10 +54544,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_31 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34840$1438_Y + connect \Y $eq$libresoc.v:35072$1438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34841$1439 + cell $eq $eq$libresoc.v:35073$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54323,10 +54555,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_30 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34841$1439_Y + connect \Y $eq$libresoc.v:35073$1439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34843$1441 + cell $eq $eq$libresoc.v:35075$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54334,271 +54566,271 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_2 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34843$1441_Y + connect \Y $eq$libresoc.v:35075$1441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34753$1351 + cell $pos $pos$libresoc.v:34985$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_0 [1:0] } - connect \Y $pos$libresoc.v:34753$1351_Y + connect \Y $pos$libresoc.v:34985$1351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34756$1354 + cell $pos $pos$libresoc.v:34988$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_4 [1:0] } - connect \Y $pos$libresoc.v:34756$1354_Y + connect \Y $pos$libresoc.v:34988$1354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34759$1357 + cell $pos $pos$libresoc.v:34991$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_8 [1:0] } - connect \Y $pos$libresoc.v:34759$1357_Y + connect \Y $pos$libresoc.v:34991$1357_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34762$1360 + cell $pos $pos$libresoc.v:34994$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_2 [0] } - connect \Y $pos$libresoc.v:34762$1360_Y + connect \Y $pos$libresoc.v:34994$1360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34763$1361 + cell $pos $pos$libresoc.v:34995$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_12 [1:0] } - connect \Y $pos$libresoc.v:34763$1361_Y + connect \Y $pos$libresoc.v:34995$1361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34766$1364 + cell $pos $pos$libresoc.v:34998$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_16 [1:0] } - connect \Y $pos$libresoc.v:34766$1364_Y + connect \Y $pos$libresoc.v:34998$1364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34769$1367 + cell $pos $pos$libresoc.v:35001$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_20 [1:0] } - connect \Y $pos$libresoc.v:34769$1367_Y + connect \Y $pos$libresoc.v:35001$1367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34772$1370 + cell $pos $pos$libresoc.v:35004$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_24 [1:0] } - connect \Y $pos$libresoc.v:34772$1370_Y + connect \Y $pos$libresoc.v:35004$1370_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34776$1374 + cell $pos $pos$libresoc.v:35008$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_28 [1:0] } - connect \Y $pos$libresoc.v:34776$1374_Y + connect \Y $pos$libresoc.v:35008$1374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34779$1377 + cell $pos $pos$libresoc.v:35011$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_0 [2:0] } - connect \Y $pos$libresoc.v:34779$1377_Y + connect \Y $pos$libresoc.v:35011$1377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34782$1380 + cell $pos $pos$libresoc.v:35014$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_4 [2:0] } - connect \Y $pos$libresoc.v:34782$1380_Y + connect \Y $pos$libresoc.v:35014$1380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34786$1384 + cell $pos $pos$libresoc.v:35018$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_8 [2:0] } - connect \Y $pos$libresoc.v:34786$1384_Y + connect \Y $pos$libresoc.v:35018$1384_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34789$1387 + cell $pos $pos$libresoc.v:35021$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_12 [2:0] } - connect \Y $pos$libresoc.v:34789$1387_Y + connect \Y $pos$libresoc.v:35021$1387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34792$1390 + cell $pos $pos$libresoc.v:35024$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_0 [3:0] } - connect \Y $pos$libresoc.v:34792$1390_Y + connect \Y $pos$libresoc.v:35024$1390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34795$1393 + cell $pos $pos$libresoc.v:35027$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_4 [0] } - connect \Y $pos$libresoc.v:34795$1393_Y + connect \Y $pos$libresoc.v:35027$1393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34796$1394 + cell $pos $pos$libresoc.v:35028$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_4 [3:0] } - connect \Y $pos$libresoc.v:34796$1394_Y + connect \Y $pos$libresoc.v:35028$1394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34799$1397 + cell $pos $pos$libresoc.v:35031$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { 2'01 \cnt_5_0 [4:0] } - connect \Y $pos$libresoc.v:34799$1397_Y + connect \Y $pos$libresoc.v:35031$1397_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34803$1401 + cell $pos $pos$libresoc.v:35035$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_6 [0] } - connect \Y $pos$libresoc.v:34803$1401_Y + connect \Y $pos$libresoc.v:35035$1401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34806$1404 + cell $pos $pos$libresoc.v:35038$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_8 [0] } - connect \Y $pos$libresoc.v:34806$1404_Y + connect \Y $pos$libresoc.v:35038$1404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34809$1407 + cell $pos $pos$libresoc.v:35041$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_10 [0] } - connect \Y $pos$libresoc.v:34809$1407_Y + connect \Y $pos$libresoc.v:35041$1407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34813$1411 + cell $pos $pos$libresoc.v:35045$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_12 [0] } - connect \Y $pos$libresoc.v:34813$1411_Y + connect \Y $pos$libresoc.v:35045$1411_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34816$1414 + cell $pos $pos$libresoc.v:35048$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_14 [0] } - connect \Y $pos$libresoc.v:34816$1414_Y + connect \Y $pos$libresoc.v:35048$1414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34819$1417 + cell $pos $pos$libresoc.v:35051$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_16 [0] } - connect \Y $pos$libresoc.v:34819$1417_Y + connect \Y $pos$libresoc.v:35051$1417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34822$1420 + cell $pos $pos$libresoc.v:35054$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_0 [0] } - connect \Y $pos$libresoc.v:34822$1420_Y + connect \Y $pos$libresoc.v:35054$1420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34823$1421 + cell $pos $pos$libresoc.v:35055$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_18 [0] } - connect \Y $pos$libresoc.v:34823$1421_Y + connect \Y $pos$libresoc.v:35055$1421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34826$1424 + cell $pos $pos$libresoc.v:35058$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_20 [0] } - connect \Y $pos$libresoc.v:34826$1424_Y + connect \Y $pos$libresoc.v:35058$1424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34829$1427 + cell $pos $pos$libresoc.v:35061$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_22 [0] } - connect \Y $pos$libresoc.v:34829$1427_Y + connect \Y $pos$libresoc.v:35061$1427_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34832$1430 + cell $pos $pos$libresoc.v:35064$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_24 [0] } - connect \Y $pos$libresoc.v:34832$1430_Y + connect \Y $pos$libresoc.v:35064$1430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34836$1434 + cell $pos $pos$libresoc.v:35068$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_26 [0] } - connect \Y $pos$libresoc.v:34836$1434_Y + connect \Y $pos$libresoc.v:35068$1434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34839$1437 + cell $pos $pos$libresoc.v:35071$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_28 [0] } - connect \Y $pos$libresoc.v:34839$1437_Y + connect \Y $pos$libresoc.v:35071$1437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34842$1440 + cell $pos $pos$libresoc.v:35074$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_30 [0] } - connect \Y $pos$libresoc.v:34842$1440_Y + connect \Y $pos$libresoc.v:35074$1440_Y end - attribute \src "libresoc.v:34370.7-34370.20" - process $proc$libresoc.v:34370$1505 + attribute \src "libresoc.v:34602.7-34602.20" + process $proc$libresoc.v:34602$1505 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:34844.3-34858.6" - process $proc$libresoc.v:34844$1442 + attribute \src "libresoc.v:35076.3-35090.6" + process $proc$libresoc.v:35076$1442 assign { } { } assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] - attribute \src "libresoc.v:34845.5-34845.29" + attribute \src "libresoc.v:35077.5-35077.29" switch \initial - attribute \src "libresoc.v:34845.9-34845.17" + attribute \src "libresoc.v:35077.9-35077.17" case 1'1 case end @@ -54620,13 +54852,13 @@ module \clz sync always update \cnt_1_0 $0\cnt_1_0[1:0] end - attribute \src "libresoc.v:34859.3-34873.6" - process $proc$libresoc.v:34859$1443 + attribute \src "libresoc.v:35091.3-35105.6" + process $proc$libresoc.v:35091$1443 assign { } { } assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] - attribute \src "libresoc.v:34860.5-34860.29" + attribute \src "libresoc.v:35092.5-35092.29" switch \initial - attribute \src "libresoc.v:34860.9-34860.17" + attribute \src "libresoc.v:35092.9-35092.17" case 1'1 case end @@ -54648,13 +54880,13 @@ module \clz sync always update \cnt_1_5 $0\cnt_1_5[1:0] end - attribute \src "libresoc.v:34874.3-34888.6" - process $proc$libresoc.v:34874$1444 + attribute \src "libresoc.v:35106.3-35120.6" + process $proc$libresoc.v:35106$1444 assign { } { } assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] - attribute \src "libresoc.v:34875.5-34875.29" + attribute \src "libresoc.v:35107.5-35107.29" switch \initial - attribute \src "libresoc.v:34875.9-34875.17" + attribute \src "libresoc.v:35107.9-35107.17" case 1'1 case end @@ -54676,13 +54908,13 @@ module \clz sync always update \cnt_1_6 $0\cnt_1_6[1:0] end - attribute \src "libresoc.v:34889.3-34903.6" - process $proc$libresoc.v:34889$1445 + attribute \src "libresoc.v:35121.3-35135.6" + process $proc$libresoc.v:35121$1445 assign { } { } assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] - attribute \src "libresoc.v:34890.5-34890.29" + attribute \src "libresoc.v:35122.5-35122.29" switch \initial - attribute \src "libresoc.v:34890.9-34890.17" + attribute \src "libresoc.v:35122.9-35122.17" case 1'1 case end @@ -54704,13 +54936,13 @@ module \clz sync always update \cnt_1_7 $0\cnt_1_7[1:0] end - attribute \src "libresoc.v:34904.3-34918.6" - process $proc$libresoc.v:34904$1446 + attribute \src "libresoc.v:35136.3-35150.6" + process $proc$libresoc.v:35136$1446 assign { } { } assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] - attribute \src "libresoc.v:34905.5-34905.29" + attribute \src "libresoc.v:35137.5-35137.29" switch \initial - attribute \src "libresoc.v:34905.9-34905.17" + attribute \src "libresoc.v:35137.9-35137.17" case 1'1 case end @@ -54732,13 +54964,13 @@ module \clz sync always update \cnt_1_8 $0\cnt_1_8[1:0] end - attribute \src "libresoc.v:34919.3-34933.6" - process $proc$libresoc.v:34919$1447 + attribute \src "libresoc.v:35151.3-35165.6" + process $proc$libresoc.v:35151$1447 assign { } { } assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] - attribute \src "libresoc.v:34920.5-34920.29" + attribute \src "libresoc.v:35152.5-35152.29" switch \initial - attribute \src "libresoc.v:34920.9-34920.17" + attribute \src "libresoc.v:35152.9-35152.17" case 1'1 case end @@ -54760,13 +54992,13 @@ module \clz sync always update \cnt_1_9 $0\cnt_1_9[1:0] end - attribute \src "libresoc.v:34934.3-34948.6" - process $proc$libresoc.v:34934$1448 + attribute \src "libresoc.v:35166.3-35180.6" + process $proc$libresoc.v:35166$1448 assign { } { } assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] - attribute \src "libresoc.v:34935.5-34935.29" + attribute \src "libresoc.v:35167.5-35167.29" switch \initial - attribute \src "libresoc.v:34935.9-34935.17" + attribute \src "libresoc.v:35167.9-35167.17" case 1'1 case end @@ -54788,13 +55020,13 @@ module \clz sync always update \cnt_1_10 $0\cnt_1_10[1:0] end - attribute \src "libresoc.v:34949.3-34963.6" - process $proc$libresoc.v:34949$1449 + attribute \src "libresoc.v:35181.3-35195.6" + process $proc$libresoc.v:35181$1449 assign { } { } assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] - attribute \src "libresoc.v:34950.5-34950.29" + attribute \src "libresoc.v:35182.5-35182.29" switch \initial - attribute \src "libresoc.v:34950.9-34950.17" + attribute \src "libresoc.v:35182.9-35182.17" case 1'1 case end @@ -54816,13 +55048,13 @@ module \clz sync always update \cnt_1_11 $0\cnt_1_11[1:0] end - attribute \src "libresoc.v:34964.3-34978.6" - process $proc$libresoc.v:34964$1450 + attribute \src "libresoc.v:35196.3-35210.6" + process $proc$libresoc.v:35196$1450 assign { } { } assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] - attribute \src "libresoc.v:34965.5-34965.29" + attribute \src "libresoc.v:35197.5-35197.29" switch \initial - attribute \src "libresoc.v:34965.9-34965.17" + attribute \src "libresoc.v:35197.9-35197.17" case 1'1 case end @@ -54844,13 +55076,13 @@ module \clz sync always update \cnt_1_12 $0\cnt_1_12[1:0] end - attribute \src "libresoc.v:34979.3-34993.6" - process $proc$libresoc.v:34979$1451 + attribute \src "libresoc.v:35211.3-35225.6" + process $proc$libresoc.v:35211$1451 assign { } { } assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] - attribute \src "libresoc.v:34980.5-34980.29" + attribute \src "libresoc.v:35212.5-35212.29" switch \initial - attribute \src "libresoc.v:34980.9-34980.17" + attribute \src "libresoc.v:35212.9-35212.17" case 1'1 case end @@ -54872,13 +55104,13 @@ module \clz sync always update \cnt_1_13 $0\cnt_1_13[1:0] end - attribute \src "libresoc.v:34994.3-35008.6" - process $proc$libresoc.v:34994$1452 + attribute \src "libresoc.v:35226.3-35240.6" + process $proc$libresoc.v:35226$1452 assign { } { } assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] - attribute \src "libresoc.v:34995.5-34995.29" + attribute \src "libresoc.v:35227.5-35227.29" switch \initial - attribute \src "libresoc.v:34995.9-34995.17" + attribute \src "libresoc.v:35227.9-35227.17" case 1'1 case end @@ -54900,13 +55132,13 @@ module \clz sync always update \cnt_1_14 $0\cnt_1_14[1:0] end - attribute \src "libresoc.v:35009.3-35023.6" - process $proc$libresoc.v:35009$1453 + attribute \src "libresoc.v:35241.3-35255.6" + process $proc$libresoc.v:35241$1453 assign { } { } assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] - attribute \src "libresoc.v:35010.5-35010.29" + attribute \src "libresoc.v:35242.5-35242.29" switch \initial - attribute \src "libresoc.v:35010.9-35010.17" + attribute \src "libresoc.v:35242.9-35242.17" case 1'1 case end @@ -54928,13 +55160,13 @@ module \clz sync always update \cnt_1_1 $0\cnt_1_1[1:0] end - attribute \src "libresoc.v:35024.3-35038.6" - process $proc$libresoc.v:35024$1454 + attribute \src "libresoc.v:35256.3-35270.6" + process $proc$libresoc.v:35256$1454 assign { } { } assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] - attribute \src "libresoc.v:35025.5-35025.29" + attribute \src "libresoc.v:35257.5-35257.29" switch \initial - attribute \src "libresoc.v:35025.9-35025.17" + attribute \src "libresoc.v:35257.9-35257.17" case 1'1 case end @@ -54956,13 +55188,13 @@ module \clz sync always update \cnt_1_15 $0\cnt_1_15[1:0] end - attribute \src "libresoc.v:35039.3-35053.6" - process $proc$libresoc.v:35039$1455 + attribute \src "libresoc.v:35271.3-35285.6" + process $proc$libresoc.v:35271$1455 assign { } { } assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] - attribute \src "libresoc.v:35040.5-35040.29" + attribute \src "libresoc.v:35272.5-35272.29" switch \initial - attribute \src "libresoc.v:35040.9-35040.17" + attribute \src "libresoc.v:35272.9-35272.17" case 1'1 case end @@ -54984,13 +55216,13 @@ module \clz sync always update \cnt_1_16 $0\cnt_1_16[1:0] end - attribute \src "libresoc.v:35054.3-35068.6" - process $proc$libresoc.v:35054$1456 + attribute \src "libresoc.v:35286.3-35300.6" + process $proc$libresoc.v:35286$1456 assign { } { } assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] - attribute \src "libresoc.v:35055.5-35055.29" + attribute \src "libresoc.v:35287.5-35287.29" switch \initial - attribute \src "libresoc.v:35055.9-35055.17" + attribute \src "libresoc.v:35287.9-35287.17" case 1'1 case end @@ -55012,13 +55244,13 @@ module \clz sync always update \cnt_1_17 $0\cnt_1_17[1:0] end - attribute \src "libresoc.v:35069.3-35083.6" - process $proc$libresoc.v:35069$1457 + attribute \src "libresoc.v:35301.3-35315.6" + process $proc$libresoc.v:35301$1457 assign { } { } assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] - attribute \src "libresoc.v:35070.5-35070.29" + attribute \src "libresoc.v:35302.5-35302.29" switch \initial - attribute \src "libresoc.v:35070.9-35070.17" + attribute \src "libresoc.v:35302.9-35302.17" case 1'1 case end @@ -55040,13 +55272,13 @@ module \clz sync always update \cnt_1_18 $0\cnt_1_18[1:0] end - attribute \src "libresoc.v:35084.3-35098.6" - process $proc$libresoc.v:35084$1458 + attribute \src "libresoc.v:35316.3-35330.6" + process $proc$libresoc.v:35316$1458 assign { } { } assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] - attribute \src "libresoc.v:35085.5-35085.29" + attribute \src "libresoc.v:35317.5-35317.29" switch \initial - attribute \src "libresoc.v:35085.9-35085.17" + attribute \src "libresoc.v:35317.9-35317.17" case 1'1 case end @@ -55068,13 +55300,13 @@ module \clz sync always update \cnt_1_19 $0\cnt_1_19[1:0] end - attribute \src "libresoc.v:35099.3-35113.6" - process $proc$libresoc.v:35099$1459 + attribute \src "libresoc.v:35331.3-35345.6" + process $proc$libresoc.v:35331$1459 assign { } { } assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] - attribute \src "libresoc.v:35100.5-35100.29" + attribute \src "libresoc.v:35332.5-35332.29" switch \initial - attribute \src "libresoc.v:35100.9-35100.17" + attribute \src "libresoc.v:35332.9-35332.17" case 1'1 case end @@ -55096,13 +55328,13 @@ module \clz sync always update \cnt_1_20 $0\cnt_1_20[1:0] end - attribute \src "libresoc.v:35114.3-35128.6" - process $proc$libresoc.v:35114$1460 + attribute \src "libresoc.v:35346.3-35360.6" + process $proc$libresoc.v:35346$1460 assign { } { } assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] - attribute \src "libresoc.v:35115.5-35115.29" + attribute \src "libresoc.v:35347.5-35347.29" switch \initial - attribute \src "libresoc.v:35115.9-35115.17" + attribute \src "libresoc.v:35347.9-35347.17" case 1'1 case end @@ -55124,13 +55356,13 @@ module \clz sync always update \cnt_1_21 $0\cnt_1_21[1:0] end - attribute \src "libresoc.v:35129.3-35143.6" - process $proc$libresoc.v:35129$1461 + attribute \src "libresoc.v:35361.3-35375.6" + process $proc$libresoc.v:35361$1461 assign { } { } assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] - attribute \src "libresoc.v:35130.5-35130.29" + attribute \src "libresoc.v:35362.5-35362.29" switch \initial - attribute \src "libresoc.v:35130.9-35130.17" + attribute \src "libresoc.v:35362.9-35362.17" case 1'1 case end @@ -55152,13 +55384,13 @@ module \clz sync always update \cnt_1_22 $0\cnt_1_22[1:0] end - attribute \src "libresoc.v:35144.3-35158.6" - process $proc$libresoc.v:35144$1462 + attribute \src "libresoc.v:35376.3-35390.6" + process $proc$libresoc.v:35376$1462 assign { } { } assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] - attribute \src "libresoc.v:35145.5-35145.29" + attribute \src "libresoc.v:35377.5-35377.29" switch \initial - attribute \src "libresoc.v:35145.9-35145.17" + attribute \src "libresoc.v:35377.9-35377.17" case 1'1 case end @@ -55180,13 +55412,13 @@ module \clz sync always update \cnt_1_23 $0\cnt_1_23[1:0] end - attribute \src "libresoc.v:35159.3-35173.6" - process $proc$libresoc.v:35159$1463 + attribute \src "libresoc.v:35391.3-35405.6" + process $proc$libresoc.v:35391$1463 assign { } { } assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] - attribute \src "libresoc.v:35160.5-35160.29" + attribute \src "libresoc.v:35392.5-35392.29" switch \initial - attribute \src "libresoc.v:35160.9-35160.17" + attribute \src "libresoc.v:35392.9-35392.17" case 1'1 case end @@ -55208,13 +55440,13 @@ module \clz sync always update \cnt_1_24 $0\cnt_1_24[1:0] end - attribute \src "libresoc.v:35174.3-35188.6" - process $proc$libresoc.v:35174$1464 + attribute \src "libresoc.v:35406.3-35420.6" + process $proc$libresoc.v:35406$1464 assign { } { } assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35175.5-35175.29" + attribute \src "libresoc.v:35407.5-35407.29" switch \initial - attribute \src "libresoc.v:35175.9-35175.17" + attribute \src "libresoc.v:35407.9-35407.17" case 1'1 case end @@ -55236,13 +55468,13 @@ module \clz sync always update \cnt_1_2 $0\cnt_1_2[1:0] end - attribute \src "libresoc.v:35189.3-35203.6" - process $proc$libresoc.v:35189$1465 + attribute \src "libresoc.v:35421.3-35435.6" + process $proc$libresoc.v:35421$1465 assign { } { } assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] - attribute \src "libresoc.v:35190.5-35190.29" + attribute \src "libresoc.v:35422.5-35422.29" switch \initial - attribute \src "libresoc.v:35190.9-35190.17" + attribute \src "libresoc.v:35422.9-35422.17" case 1'1 case end @@ -55264,13 +55496,13 @@ module \clz sync always update \cnt_1_25 $0\cnt_1_25[1:0] end - attribute \src "libresoc.v:35204.3-35218.6" - process $proc$libresoc.v:35204$1466 + attribute \src "libresoc.v:35436.3-35450.6" + process $proc$libresoc.v:35436$1466 assign { } { } assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] - attribute \src "libresoc.v:35205.5-35205.29" + attribute \src "libresoc.v:35437.5-35437.29" switch \initial - attribute \src "libresoc.v:35205.9-35205.17" + attribute \src "libresoc.v:35437.9-35437.17" case 1'1 case end @@ -55292,13 +55524,13 @@ module \clz sync always update \cnt_1_26 $0\cnt_1_26[1:0] end - attribute \src "libresoc.v:35219.3-35233.6" - process $proc$libresoc.v:35219$1467 + attribute \src "libresoc.v:35451.3-35465.6" + process $proc$libresoc.v:35451$1467 assign { } { } assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] - attribute \src "libresoc.v:35220.5-35220.29" + attribute \src "libresoc.v:35452.5-35452.29" switch \initial - attribute \src "libresoc.v:35220.9-35220.17" + attribute \src "libresoc.v:35452.9-35452.17" case 1'1 case end @@ -55320,13 +55552,13 @@ module \clz sync always update \cnt_1_27 $0\cnt_1_27[1:0] end - attribute \src "libresoc.v:35234.3-35248.6" - process $proc$libresoc.v:35234$1468 + attribute \src "libresoc.v:35466.3-35480.6" + process $proc$libresoc.v:35466$1468 assign { } { } assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35235.5-35235.29" + attribute \src "libresoc.v:35467.5-35467.29" switch \initial - attribute \src "libresoc.v:35235.9-35235.17" + attribute \src "libresoc.v:35467.9-35467.17" case 1'1 case end @@ -55348,13 +55580,13 @@ module \clz sync always update \cnt_1_28 $0\cnt_1_28[1:0] end - attribute \src "libresoc.v:35249.3-35263.6" - process $proc$libresoc.v:35249$1469 + attribute \src "libresoc.v:35481.3-35495.6" + process $proc$libresoc.v:35481$1469 assign { } { } assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35250.5-35250.29" + attribute \src "libresoc.v:35482.5-35482.29" switch \initial - attribute \src "libresoc.v:35250.9-35250.17" + attribute \src "libresoc.v:35482.9-35482.17" case 1'1 case end @@ -55376,13 +55608,13 @@ module \clz sync always update \cnt_1_29 $0\cnt_1_29[1:0] end - attribute \src "libresoc.v:35264.3-35278.6" - process $proc$libresoc.v:35264$1470 + attribute \src "libresoc.v:35496.3-35510.6" + process $proc$libresoc.v:35496$1470 assign { } { } assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35265.5-35265.29" + attribute \src "libresoc.v:35497.5-35497.29" switch \initial - attribute \src "libresoc.v:35265.9-35265.17" + attribute \src "libresoc.v:35497.9-35497.17" case 1'1 case end @@ -55404,13 +55636,13 @@ module \clz sync always update \cnt_1_30 $0\cnt_1_30[1:0] end - attribute \src "libresoc.v:35279.3-35293.6" - process $proc$libresoc.v:35279$1471 + attribute \src "libresoc.v:35511.3-35525.6" + process $proc$libresoc.v:35511$1471 assign { } { } assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35280.5-35280.29" + attribute \src "libresoc.v:35512.5-35512.29" switch \initial - attribute \src "libresoc.v:35280.9-35280.17" + attribute \src "libresoc.v:35512.9-35512.17" case 1'1 case end @@ -55432,13 +55664,13 @@ module \clz sync always update \cnt_1_31 $0\cnt_1_31[1:0] end - attribute \src "libresoc.v:35294.3-35313.6" - process $proc$libresoc.v:35294$1472 + attribute \src "libresoc.v:35526.3-35545.6" + process $proc$libresoc.v:35526$1472 assign { } { } assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35295.5-35295.29" + attribute \src "libresoc.v:35527.5-35527.29" switch \initial - attribute \src "libresoc.v:35295.9-35295.17" + attribute \src "libresoc.v:35527.9-35527.17" case 1'1 case end @@ -55467,13 +55699,13 @@ module \clz sync always update \cnt_2_0 $0\cnt_2_0[2:0] end - attribute \src "libresoc.v:35314.3-35333.6" - process $proc$libresoc.v:35314$1473 + attribute \src "libresoc.v:35546.3-35565.6" + process $proc$libresoc.v:35546$1473 assign { } { } assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35315.5-35315.29" + attribute \src "libresoc.v:35547.5-35547.29" switch \initial - attribute \src "libresoc.v:35315.9-35315.17" + attribute \src "libresoc.v:35547.9-35547.17" case 1'1 case end @@ -55502,13 +55734,13 @@ module \clz sync always update \cnt_2_2 $0\cnt_2_2[2:0] end - attribute \src "libresoc.v:35334.3-35353.6" - process $proc$libresoc.v:35334$1474 + attribute \src "libresoc.v:35566.3-35585.6" + process $proc$libresoc.v:35566$1474 assign { } { } assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35335.5-35335.29" + attribute \src "libresoc.v:35567.5-35567.29" switch \initial - attribute \src "libresoc.v:35335.9-35335.17" + attribute \src "libresoc.v:35567.9-35567.17" case 1'1 case end @@ -55537,13 +55769,13 @@ module \clz sync always update \cnt_2_4 $0\cnt_2_4[2:0] end - attribute \src "libresoc.v:35354.3-35373.6" - process $proc$libresoc.v:35354$1475 + attribute \src "libresoc.v:35586.3-35605.6" + process $proc$libresoc.v:35586$1475 assign { } { } assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35355.5-35355.29" + attribute \src "libresoc.v:35587.5-35587.29" switch \initial - attribute \src "libresoc.v:35355.9-35355.17" + attribute \src "libresoc.v:35587.9-35587.17" case 1'1 case end @@ -55572,13 +55804,13 @@ module \clz sync always update \cnt_2_6 $0\cnt_2_6[2:0] end - attribute \src "libresoc.v:35374.3-35393.6" - process $proc$libresoc.v:35374$1476 + attribute \src "libresoc.v:35606.3-35625.6" + process $proc$libresoc.v:35606$1476 assign { } { } assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35375.5-35375.29" + attribute \src "libresoc.v:35607.5-35607.29" switch \initial - attribute \src "libresoc.v:35375.9-35375.17" + attribute \src "libresoc.v:35607.9-35607.17" case 1'1 case end @@ -55607,13 +55839,13 @@ module \clz sync always update \cnt_2_8 $0\cnt_2_8[2:0] end - attribute \src "libresoc.v:35394.3-35413.6" - process $proc$libresoc.v:35394$1477 + attribute \src "libresoc.v:35626.3-35645.6" + process $proc$libresoc.v:35626$1477 assign { } { } assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35395.5-35395.29" + attribute \src "libresoc.v:35627.5-35627.29" switch \initial - attribute \src "libresoc.v:35395.9-35395.17" + attribute \src "libresoc.v:35627.9-35627.17" case 1'1 case end @@ -55642,13 +55874,13 @@ module \clz sync always update \cnt_2_10 $0\cnt_2_10[2:0] end - attribute \src "libresoc.v:35414.3-35428.6" - process $proc$libresoc.v:35414$1478 + attribute \src "libresoc.v:35646.3-35660.6" + process $proc$libresoc.v:35646$1478 assign { } { } assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35415.5-35415.29" + attribute \src "libresoc.v:35647.5-35647.29" switch \initial - attribute \src "libresoc.v:35415.9-35415.17" + attribute \src "libresoc.v:35647.9-35647.17" case 1'1 case end @@ -55670,13 +55902,13 @@ module \clz sync always update \cnt_1_3 $0\cnt_1_3[1:0] end - attribute \src "libresoc.v:35429.3-35448.6" - process $proc$libresoc.v:35429$1479 + attribute \src "libresoc.v:35661.3-35680.6" + process $proc$libresoc.v:35661$1479 assign { } { } assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35430.5-35430.29" + attribute \src "libresoc.v:35662.5-35662.29" switch \initial - attribute \src "libresoc.v:35430.9-35430.17" + attribute \src "libresoc.v:35662.9-35662.17" case 1'1 case end @@ -55705,13 +55937,13 @@ module \clz sync always update \cnt_2_12 $0\cnt_2_12[2:0] end - attribute \src "libresoc.v:35449.3-35468.6" - process $proc$libresoc.v:35449$1480 + attribute \src "libresoc.v:35681.3-35700.6" + process $proc$libresoc.v:35681$1480 assign { } { } assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35450.5-35450.29" + attribute \src "libresoc.v:35682.5-35682.29" switch \initial - attribute \src "libresoc.v:35450.9-35450.17" + attribute \src "libresoc.v:35682.9-35682.17" case 1'1 case end @@ -55740,13 +55972,13 @@ module \clz sync always update \cnt_2_14 $0\cnt_2_14[2:0] end - attribute \src "libresoc.v:35469.3-35488.6" - process $proc$libresoc.v:35469$1481 + attribute \src "libresoc.v:35701.3-35720.6" + process $proc$libresoc.v:35701$1481 assign { } { } assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35470.5-35470.29" + attribute \src "libresoc.v:35702.5-35702.29" switch \initial - attribute \src "libresoc.v:35470.9-35470.17" + attribute \src "libresoc.v:35702.9-35702.17" case 1'1 case end @@ -55775,13 +56007,13 @@ module \clz sync always update \cnt_2_16 $0\cnt_2_16[2:0] end - attribute \src "libresoc.v:35489.3-35508.6" - process $proc$libresoc.v:35489$1482 + attribute \src "libresoc.v:35721.3-35740.6" + process $proc$libresoc.v:35721$1482 assign { } { } assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35490.5-35490.29" + attribute \src "libresoc.v:35722.5-35722.29" switch \initial - attribute \src "libresoc.v:35490.9-35490.17" + attribute \src "libresoc.v:35722.9-35722.17" case 1'1 case end @@ -55810,13 +56042,13 @@ module \clz sync always update \cnt_2_18 $0\cnt_2_18[2:0] end - attribute \src "libresoc.v:35509.3-35528.6" - process $proc$libresoc.v:35509$1483 + attribute \src "libresoc.v:35741.3-35760.6" + process $proc$libresoc.v:35741$1483 assign { } { } assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35510.5-35510.29" + attribute \src "libresoc.v:35742.5-35742.29" switch \initial - attribute \src "libresoc.v:35510.9-35510.17" + attribute \src "libresoc.v:35742.9-35742.17" case 1'1 case end @@ -55845,13 +56077,13 @@ module \clz sync always update \cnt_2_20 $0\cnt_2_20[2:0] end - attribute \src "libresoc.v:35529.3-35548.6" - process $proc$libresoc.v:35529$1484 + attribute \src "libresoc.v:35761.3-35780.6" + process $proc$libresoc.v:35761$1484 assign { } { } assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35530.5-35530.29" + attribute \src "libresoc.v:35762.5-35762.29" switch \initial - attribute \src "libresoc.v:35530.9-35530.17" + attribute \src "libresoc.v:35762.9-35762.17" case 1'1 case end @@ -55880,13 +56112,13 @@ module \clz sync always update \cnt_2_22 $0\cnt_2_22[2:0] end - attribute \src "libresoc.v:35549.3-35568.6" - process $proc$libresoc.v:35549$1485 + attribute \src "libresoc.v:35781.3-35800.6" + process $proc$libresoc.v:35781$1485 assign { } { } assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35550.5-35550.29" + attribute \src "libresoc.v:35782.5-35782.29" switch \initial - attribute \src "libresoc.v:35550.9-35550.17" + attribute \src "libresoc.v:35782.9-35782.17" case 1'1 case end @@ -55915,13 +56147,13 @@ module \clz sync always update \cnt_2_24 $0\cnt_2_24[2:0] end - attribute \src "libresoc.v:35569.3-35588.6" - process $proc$libresoc.v:35569$1486 + attribute \src "libresoc.v:35801.3-35820.6" + process $proc$libresoc.v:35801$1486 assign { } { } assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35570.5-35570.29" + attribute \src "libresoc.v:35802.5-35802.29" switch \initial - attribute \src "libresoc.v:35570.9-35570.17" + attribute \src "libresoc.v:35802.9-35802.17" case 1'1 case end @@ -55950,13 +56182,13 @@ module \clz sync always update \cnt_2_26 $0\cnt_2_26[2:0] end - attribute \src "libresoc.v:35589.3-35608.6" - process $proc$libresoc.v:35589$1487 + attribute \src "libresoc.v:35821.3-35840.6" + process $proc$libresoc.v:35821$1487 assign { } { } assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35590.5-35590.29" + attribute \src "libresoc.v:35822.5-35822.29" switch \initial - attribute \src "libresoc.v:35590.9-35590.17" + attribute \src "libresoc.v:35822.9-35822.17" case 1'1 case end @@ -55985,13 +56217,13 @@ module \clz sync always update \cnt_2_28 $0\cnt_2_28[2:0] end - attribute \src "libresoc.v:35609.3-35628.6" - process $proc$libresoc.v:35609$1488 + attribute \src "libresoc.v:35841.3-35860.6" + process $proc$libresoc.v:35841$1488 assign { } { } assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35610.5-35610.29" + attribute \src "libresoc.v:35842.5-35842.29" switch \initial - attribute \src "libresoc.v:35610.9-35610.17" + attribute \src "libresoc.v:35842.9-35842.17" case 1'1 case end @@ -56020,13 +56252,13 @@ module \clz sync always update \cnt_2_30 $0\cnt_2_30[2:0] end - attribute \src "libresoc.v:35629.3-35648.6" - process $proc$libresoc.v:35629$1489 + attribute \src "libresoc.v:35861.3-35880.6" + process $proc$libresoc.v:35861$1489 assign { } { } assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35630.5-35630.29" + attribute \src "libresoc.v:35862.5-35862.29" switch \initial - attribute \src "libresoc.v:35630.9-35630.17" + attribute \src "libresoc.v:35862.9-35862.17" case 1'1 case end @@ -56055,13 +56287,13 @@ module \clz sync always update \cnt_3_0 $0\cnt_3_0[3:0] end - attribute \src "libresoc.v:35649.3-35668.6" - process $proc$libresoc.v:35649$1490 + attribute \src "libresoc.v:35881.3-35900.6" + process $proc$libresoc.v:35881$1490 assign { } { } assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35650.5-35650.29" + attribute \src "libresoc.v:35882.5-35882.29" switch \initial - attribute \src "libresoc.v:35650.9-35650.17" + attribute \src "libresoc.v:35882.9-35882.17" case 1'1 case end @@ -56090,13 +56322,13 @@ module \clz sync always update \cnt_3_2 $0\cnt_3_2[3:0] end - attribute \src "libresoc.v:35669.3-35688.6" - process $proc$libresoc.v:35669$1491 + attribute \src "libresoc.v:35901.3-35920.6" + process $proc$libresoc.v:35901$1491 assign { } { } assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35670.5-35670.29" + attribute \src "libresoc.v:35902.5-35902.29" switch \initial - attribute \src "libresoc.v:35670.9-35670.17" + attribute \src "libresoc.v:35902.9-35902.17" case 1'1 case end @@ -56125,13 +56357,13 @@ module \clz sync always update \cnt_3_4 $0\cnt_3_4[3:0] end - attribute \src "libresoc.v:35689.3-35708.6" - process $proc$libresoc.v:35689$1492 + attribute \src "libresoc.v:35921.3-35940.6" + process $proc$libresoc.v:35921$1492 assign { } { } assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35690.5-35690.29" + attribute \src "libresoc.v:35922.5-35922.29" switch \initial - attribute \src "libresoc.v:35690.9-35690.17" + attribute \src "libresoc.v:35922.9-35922.17" case 1'1 case end @@ -56160,13 +56392,13 @@ module \clz sync always update \cnt_3_6 $0\cnt_3_6[3:0] end - attribute \src "libresoc.v:35709.3-35728.6" - process $proc$libresoc.v:35709$1493 + attribute \src "libresoc.v:35941.3-35960.6" + process $proc$libresoc.v:35941$1493 assign { } { } assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35710.5-35710.29" + attribute \src "libresoc.v:35942.5-35942.29" switch \initial - attribute \src "libresoc.v:35710.9-35710.17" + attribute \src "libresoc.v:35942.9-35942.17" case 1'1 case end @@ -56195,13 +56427,13 @@ module \clz sync always update \cnt_3_8 $0\cnt_3_8[3:0] end - attribute \src "libresoc.v:35729.3-35748.6" - process $proc$libresoc.v:35729$1494 + attribute \src "libresoc.v:35961.3-35980.6" + process $proc$libresoc.v:35961$1494 assign { } { } assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35730.5-35730.29" + attribute \src "libresoc.v:35962.5-35962.29" switch \initial - attribute \src "libresoc.v:35730.9-35730.17" + attribute \src "libresoc.v:35962.9-35962.17" case 1'1 case end @@ -56230,13 +56462,13 @@ module \clz sync always update \cnt_3_10 $0\cnt_3_10[3:0] end - attribute \src "libresoc.v:35749.3-35768.6" - process $proc$libresoc.v:35749$1495 + attribute \src "libresoc.v:35981.3-36000.6" + process $proc$libresoc.v:35981$1495 assign { } { } assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35750.5-35750.29" + attribute \src "libresoc.v:35982.5-35982.29" switch \initial - attribute \src "libresoc.v:35750.9-35750.17" + attribute \src "libresoc.v:35982.9-35982.17" case 1'1 case end @@ -56265,13 +56497,13 @@ module \clz sync always update \cnt_3_12 $0\cnt_3_12[3:0] end - attribute \src "libresoc.v:35769.3-35788.6" - process $proc$libresoc.v:35769$1496 + attribute \src "libresoc.v:36001.3-36020.6" + process $proc$libresoc.v:36001$1496 assign { } { } assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35770.5-35770.29" + attribute \src "libresoc.v:36002.5-36002.29" switch \initial - attribute \src "libresoc.v:35770.9-35770.17" + attribute \src "libresoc.v:36002.9-36002.17" case 1'1 case end @@ -56300,13 +56532,13 @@ module \clz sync always update \cnt_3_14 $0\cnt_3_14[3:0] end - attribute \src "libresoc.v:35789.3-35808.6" - process $proc$libresoc.v:35789$1497 + attribute \src "libresoc.v:36021.3-36040.6" + process $proc$libresoc.v:36021$1497 assign { } { } assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] - attribute \src "libresoc.v:35790.5-35790.29" + attribute \src "libresoc.v:36022.5-36022.29" switch \initial - attribute \src "libresoc.v:35790.9-35790.17" + attribute \src "libresoc.v:36022.9-36022.17" case 1'1 case end @@ -56335,13 +56567,13 @@ module \clz sync always update \cnt_4_0 $0\cnt_4_0[4:0] end - attribute \src "libresoc.v:35809.3-35828.6" - process $proc$libresoc.v:35809$1498 + attribute \src "libresoc.v:36041.3-36060.6" + process $proc$libresoc.v:36041$1498 assign { } { } assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] - attribute \src "libresoc.v:35810.5-35810.29" + attribute \src "libresoc.v:36042.5-36042.29" switch \initial - attribute \src "libresoc.v:35810.9-35810.17" + attribute \src "libresoc.v:36042.9-36042.17" case 1'1 case end @@ -56370,13 +56602,13 @@ module \clz sync always update \cnt_4_2 $0\cnt_4_2[4:0] end - attribute \src "libresoc.v:35829.3-35843.6" - process $proc$libresoc.v:35829$1499 + attribute \src "libresoc.v:36061.3-36075.6" + process $proc$libresoc.v:36061$1499 assign { } { } assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] - attribute \src "libresoc.v:35830.5-35830.29" + attribute \src "libresoc.v:36062.5-36062.29" switch \initial - attribute \src "libresoc.v:35830.9-35830.17" + attribute \src "libresoc.v:36062.9-36062.17" case 1'1 case end @@ -56398,13 +56630,13 @@ module \clz sync always update \cnt_1_4 $0\cnt_1_4[1:0] end - attribute \src "libresoc.v:35844.3-35863.6" - process $proc$libresoc.v:35844$1500 + attribute \src "libresoc.v:36076.3-36095.6" + process $proc$libresoc.v:36076$1500 assign { } { } assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] - attribute \src "libresoc.v:35845.5-35845.29" + attribute \src "libresoc.v:36077.5-36077.29" switch \initial - attribute \src "libresoc.v:35845.9-35845.17" + attribute \src "libresoc.v:36077.9-36077.17" case 1'1 case end @@ -56433,13 +56665,13 @@ module \clz sync always update \cnt_4_4 $0\cnt_4_4[4:0] end - attribute \src "libresoc.v:35864.3-35883.6" - process $proc$libresoc.v:35864$1501 + attribute \src "libresoc.v:36096.3-36115.6" + process $proc$libresoc.v:36096$1501 assign { } { } assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] - attribute \src "libresoc.v:35865.5-35865.29" + attribute \src "libresoc.v:36097.5-36097.29" switch \initial - attribute \src "libresoc.v:35865.9-35865.17" + attribute \src "libresoc.v:36097.9-36097.17" case 1'1 case end @@ -56468,13 +56700,13 @@ module \clz sync always update \cnt_4_6 $0\cnt_4_6[4:0] end - attribute \src "libresoc.v:35884.3-35903.6" - process $proc$libresoc.v:35884$1502 + attribute \src "libresoc.v:36116.3-36135.6" + process $proc$libresoc.v:36116$1502 assign { } { } assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] - attribute \src "libresoc.v:35885.5-35885.29" + attribute \src "libresoc.v:36117.5-36117.29" switch \initial - attribute \src "libresoc.v:35885.9-35885.17" + attribute \src "libresoc.v:36117.9-36117.17" case 1'1 case end @@ -56503,13 +56735,13 @@ module \clz sync always update \cnt_5_0 $0\cnt_5_0[5:0] end - attribute \src "libresoc.v:35904.3-35923.6" - process $proc$libresoc.v:35904$1503 + attribute \src "libresoc.v:36136.3-36155.6" + process $proc$libresoc.v:36136$1503 assign { } { } assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] - attribute \src "libresoc.v:35905.5-35905.29" + attribute \src "libresoc.v:36137.5-36137.29" switch \initial - attribute \src "libresoc.v:35905.9-35905.17" + attribute \src "libresoc.v:36137.9-36137.17" case 1'1 case end @@ -56538,13 +56770,13 @@ module \clz sync always update \cnt_5_2 $0\cnt_5_2[5:0] end - attribute \src "libresoc.v:35924.3-35943.6" - process $proc$libresoc.v:35924$1504 + attribute \src "libresoc.v:36156.3-36175.6" + process $proc$libresoc.v:36156$1504 assign { } { } assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35925.5-35925.29" + attribute \src "libresoc.v:36157.5-36157.29" switch \initial - attribute \src "libresoc.v:35925.9-35925.17" + attribute \src "libresoc.v:36157.9-36157.17" case 1'1 case end @@ -56573,99 +56805,99 @@ module \clz sync always update \cnt_6_0 $0\cnt_6_0[6:0] end - connect \$9 $eq$libresoc.v:34751$1349_Y - connect \$99 $eq$libresoc.v:34752$1350_Y - connect \$101 $pos$libresoc.v:34753$1351_Y - connect \$103 $eq$libresoc.v:34754$1352_Y - connect \$105 $eq$libresoc.v:34755$1353_Y - connect \$107 $pos$libresoc.v:34756$1354_Y - connect \$109 $eq$libresoc.v:34757$1355_Y - connect \$111 $eq$libresoc.v:34758$1356_Y - connect \$113 $pos$libresoc.v:34759$1357_Y - connect \$115 $eq$libresoc.v:34760$1358_Y - connect \$117 $eq$libresoc.v:34761$1359_Y - connect \$11 $pos$libresoc.v:34762$1360_Y - connect \$119 $pos$libresoc.v:34763$1361_Y - connect \$121 $eq$libresoc.v:34764$1362_Y - connect \$123 $eq$libresoc.v:34765$1363_Y - connect \$125 $pos$libresoc.v:34766$1364_Y - connect \$127 $eq$libresoc.v:34767$1365_Y - connect \$129 $eq$libresoc.v:34768$1366_Y - connect \$131 $pos$libresoc.v:34769$1367_Y - connect \$133 $eq$libresoc.v:34770$1368_Y - connect \$135 $eq$libresoc.v:34771$1369_Y - connect \$137 $pos$libresoc.v:34772$1370_Y - connect \$13 $eq$libresoc.v:34773$1371_Y - connect \$139 $eq$libresoc.v:34774$1372_Y - connect \$141 $eq$libresoc.v:34775$1373_Y - connect \$143 $pos$libresoc.v:34776$1374_Y - connect \$145 $eq$libresoc.v:34777$1375_Y - connect \$147 $eq$libresoc.v:34778$1376_Y - connect \$149 $pos$libresoc.v:34779$1377_Y - connect \$151 $eq$libresoc.v:34780$1378_Y - connect \$153 $eq$libresoc.v:34781$1379_Y - connect \$155 $pos$libresoc.v:34782$1380_Y - connect \$157 $eq$libresoc.v:34783$1381_Y - connect \$15 $eq$libresoc.v:34784$1382_Y - connect \$159 $eq$libresoc.v:34785$1383_Y - connect \$161 $pos$libresoc.v:34786$1384_Y - connect \$163 $eq$libresoc.v:34787$1385_Y - connect \$165 $eq$libresoc.v:34788$1386_Y - connect \$167 $pos$libresoc.v:34789$1387_Y - connect \$169 $eq$libresoc.v:34790$1388_Y - connect \$171 $eq$libresoc.v:34791$1389_Y - connect \$173 $pos$libresoc.v:34792$1390_Y - connect \$175 $eq$libresoc.v:34793$1391_Y - connect \$177 $eq$libresoc.v:34794$1392_Y - connect \$17 $pos$libresoc.v:34795$1393_Y - connect \$179 $pos$libresoc.v:34796$1394_Y - connect \$181 $eq$libresoc.v:34797$1395_Y - connect \$183 $eq$libresoc.v:34798$1396_Y - connect \$185 $pos$libresoc.v:34799$1397_Y - connect \$1 $eq$libresoc.v:34800$1398_Y - connect \$19 $eq$libresoc.v:34801$1399_Y - connect \$21 $eq$libresoc.v:34802$1400_Y - connect \$23 $pos$libresoc.v:34803$1401_Y - connect \$25 $eq$libresoc.v:34804$1402_Y - connect \$27 $eq$libresoc.v:34805$1403_Y - connect \$29 $pos$libresoc.v:34806$1404_Y - connect \$31 $eq$libresoc.v:34807$1405_Y - connect \$33 $eq$libresoc.v:34808$1406_Y - connect \$35 $pos$libresoc.v:34809$1407_Y - connect \$37 $eq$libresoc.v:34810$1408_Y - connect \$3 $eq$libresoc.v:34811$1409_Y - connect \$39 $eq$libresoc.v:34812$1410_Y - connect \$41 $pos$libresoc.v:34813$1411_Y - connect \$43 $eq$libresoc.v:34814$1412_Y - connect \$45 $eq$libresoc.v:34815$1413_Y - connect \$47 $pos$libresoc.v:34816$1414_Y - connect \$49 $eq$libresoc.v:34817$1415_Y - connect \$51 $eq$libresoc.v:34818$1416_Y - connect \$53 $pos$libresoc.v:34819$1417_Y - connect \$55 $eq$libresoc.v:34820$1418_Y - connect \$57 $eq$libresoc.v:34821$1419_Y - connect \$5 $pos$libresoc.v:34822$1420_Y - connect \$59 $pos$libresoc.v:34823$1421_Y - connect \$61 $eq$libresoc.v:34824$1422_Y - connect \$63 $eq$libresoc.v:34825$1423_Y - connect \$65 $pos$libresoc.v:34826$1424_Y - connect \$67 $eq$libresoc.v:34827$1425_Y - connect \$69 $eq$libresoc.v:34828$1426_Y - connect \$71 $pos$libresoc.v:34829$1427_Y - connect \$73 $eq$libresoc.v:34830$1428_Y - connect \$75 $eq$libresoc.v:34831$1429_Y - connect \$77 $pos$libresoc.v:34832$1430_Y - connect \$7 $eq$libresoc.v:34833$1431_Y - connect \$79 $eq$libresoc.v:34834$1432_Y - connect \$81 $eq$libresoc.v:34835$1433_Y - connect \$83 $pos$libresoc.v:34836$1434_Y - connect \$85 $eq$libresoc.v:34837$1435_Y - connect \$87 $eq$libresoc.v:34838$1436_Y - connect \$89 $pos$libresoc.v:34839$1437_Y - connect \$91 $eq$libresoc.v:34840$1438_Y - connect \$93 $eq$libresoc.v:34841$1439_Y - connect \$95 $pos$libresoc.v:34842$1440_Y - connect \$97 $eq$libresoc.v:34843$1441_Y + connect \$9 $eq$libresoc.v:34983$1349_Y + connect \$99 $eq$libresoc.v:34984$1350_Y + connect \$101 $pos$libresoc.v:34985$1351_Y + connect \$103 $eq$libresoc.v:34986$1352_Y + connect \$105 $eq$libresoc.v:34987$1353_Y + connect \$107 $pos$libresoc.v:34988$1354_Y + connect \$109 $eq$libresoc.v:34989$1355_Y + connect \$111 $eq$libresoc.v:34990$1356_Y + connect \$113 $pos$libresoc.v:34991$1357_Y + connect \$115 $eq$libresoc.v:34992$1358_Y + connect \$117 $eq$libresoc.v:34993$1359_Y + connect \$11 $pos$libresoc.v:34994$1360_Y + connect \$119 $pos$libresoc.v:34995$1361_Y + connect \$121 $eq$libresoc.v:34996$1362_Y + connect \$123 $eq$libresoc.v:34997$1363_Y + connect \$125 $pos$libresoc.v:34998$1364_Y + connect \$127 $eq$libresoc.v:34999$1365_Y + connect \$129 $eq$libresoc.v:35000$1366_Y + connect \$131 $pos$libresoc.v:35001$1367_Y + connect \$133 $eq$libresoc.v:35002$1368_Y + connect \$135 $eq$libresoc.v:35003$1369_Y + connect \$137 $pos$libresoc.v:35004$1370_Y + connect \$13 $eq$libresoc.v:35005$1371_Y + connect \$139 $eq$libresoc.v:35006$1372_Y + connect \$141 $eq$libresoc.v:35007$1373_Y + connect \$143 $pos$libresoc.v:35008$1374_Y + connect \$145 $eq$libresoc.v:35009$1375_Y + connect \$147 $eq$libresoc.v:35010$1376_Y + connect \$149 $pos$libresoc.v:35011$1377_Y + connect \$151 $eq$libresoc.v:35012$1378_Y + connect \$153 $eq$libresoc.v:35013$1379_Y + connect \$155 $pos$libresoc.v:35014$1380_Y + connect \$157 $eq$libresoc.v:35015$1381_Y + connect \$15 $eq$libresoc.v:35016$1382_Y + connect \$159 $eq$libresoc.v:35017$1383_Y + connect \$161 $pos$libresoc.v:35018$1384_Y + connect \$163 $eq$libresoc.v:35019$1385_Y + connect \$165 $eq$libresoc.v:35020$1386_Y + connect \$167 $pos$libresoc.v:35021$1387_Y + connect \$169 $eq$libresoc.v:35022$1388_Y + connect \$171 $eq$libresoc.v:35023$1389_Y + connect \$173 $pos$libresoc.v:35024$1390_Y + connect \$175 $eq$libresoc.v:35025$1391_Y + connect \$177 $eq$libresoc.v:35026$1392_Y + connect \$17 $pos$libresoc.v:35027$1393_Y + connect \$179 $pos$libresoc.v:35028$1394_Y + connect \$181 $eq$libresoc.v:35029$1395_Y + connect \$183 $eq$libresoc.v:35030$1396_Y + connect \$185 $pos$libresoc.v:35031$1397_Y + connect \$1 $eq$libresoc.v:35032$1398_Y + connect \$19 $eq$libresoc.v:35033$1399_Y + connect \$21 $eq$libresoc.v:35034$1400_Y + connect \$23 $pos$libresoc.v:35035$1401_Y + connect \$25 $eq$libresoc.v:35036$1402_Y + connect \$27 $eq$libresoc.v:35037$1403_Y + connect \$29 $pos$libresoc.v:35038$1404_Y + connect \$31 $eq$libresoc.v:35039$1405_Y + connect \$33 $eq$libresoc.v:35040$1406_Y + connect \$35 $pos$libresoc.v:35041$1407_Y + connect \$37 $eq$libresoc.v:35042$1408_Y + connect \$3 $eq$libresoc.v:35043$1409_Y + connect \$39 $eq$libresoc.v:35044$1410_Y + connect \$41 $pos$libresoc.v:35045$1411_Y + connect \$43 $eq$libresoc.v:35046$1412_Y + connect \$45 $eq$libresoc.v:35047$1413_Y + connect \$47 $pos$libresoc.v:35048$1414_Y + connect \$49 $eq$libresoc.v:35049$1415_Y + connect \$51 $eq$libresoc.v:35050$1416_Y + connect \$53 $pos$libresoc.v:35051$1417_Y + connect \$55 $eq$libresoc.v:35052$1418_Y + connect \$57 $eq$libresoc.v:35053$1419_Y + connect \$5 $pos$libresoc.v:35054$1420_Y + connect \$59 $pos$libresoc.v:35055$1421_Y + connect \$61 $eq$libresoc.v:35056$1422_Y + connect \$63 $eq$libresoc.v:35057$1423_Y + connect \$65 $pos$libresoc.v:35058$1424_Y + connect \$67 $eq$libresoc.v:35059$1425_Y + connect \$69 $eq$libresoc.v:35060$1426_Y + connect \$71 $pos$libresoc.v:35061$1427_Y + connect \$73 $eq$libresoc.v:35062$1428_Y + connect \$75 $eq$libresoc.v:35063$1429_Y + connect \$77 $pos$libresoc.v:35064$1430_Y + connect \$7 $eq$libresoc.v:35065$1431_Y + connect \$79 $eq$libresoc.v:35066$1432_Y + connect \$81 $eq$libresoc.v:35067$1433_Y + connect \$83 $pos$libresoc.v:35068$1434_Y + connect \$85 $eq$libresoc.v:35069$1435_Y + connect \$87 $eq$libresoc.v:35070$1436_Y + connect \$89 $pos$libresoc.v:35071$1437_Y + connect \$91 $eq$libresoc.v:35072$1438_Y + connect \$93 $eq$libresoc.v:35073$1439_Y + connect \$95 $pos$libresoc.v:35074$1440_Y + connect \$97 $eq$libresoc.v:35075$1441_Y connect \lz \cnt_6_0 connect \pair62 \sig_in [63:62] connect \pair60 \sig_in [61:60] @@ -56700,5072 +56932,5072 @@ module \clz connect \pair2 \sig_in [3:2] connect \pair0 \sig_in [1:0] end -attribute \src "libresoc.v:35981.1-48836.10" +attribute \src "libresoc.v:36213.1-49141.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core" attribute \generator "nMigen" module \core - attribute \src "libresoc.v:45802.3-45822.6" - wire $0\core_terminate_o$next[0:0]$2588 - attribute \src "libresoc.v:42690.3-42691.49" + attribute \src "libresoc.v:46587.3-46607.6" + wire $0\core_terminate_o$next[0:0]$2673 + attribute \src "libresoc.v:42982.3-42983.49" wire $0\core_terminate_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $0\corebusy_o[0:0] - attribute \src "libresoc.v:45627.3-45653.6" - wire width 2 $0\counter$next[1:0]$2565 - attribute \src "libresoc.v:42692.3-42693.31" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $0\counter$next[1:0]$2654 + attribute \src "libresoc.v:42984.3-42985.31" wire width 2 $0\counter[1:0] - attribute \src "libresoc.v:46112.3-46120.6" - wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 - attribute \src "libresoc.v:42626.3-42627.57" + attribute \src "libresoc.v:46412.3-46420.6" + wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 + attribute \src "libresoc.v:42918.3-42919.57" wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46093.3-46101.6" - wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 - attribute \src "libresoc.v:42628.3-42629.49" + attribute \src "libresoc.v:46393.3-46401.6" + wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 + attribute \src "libresoc.v:42920.3-42921.49" wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46131.3-46139.6" - wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 - attribute \src "libresoc.v:42624.3-42625.49" + attribute \src "libresoc.v:46458.3-46466.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 + attribute \src "libresoc.v:42916.3-42917.49" wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46180.3-46188.6" - wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 - attribute \src "libresoc.v:42622.3-42623.49" + attribute \src "libresoc.v:46568.3-46576.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 + attribute \src "libresoc.v:42914.3-42915.49" wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46044.3-46052.6" - wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 - attribute \src "libresoc.v:42630.3-42631.55" + attribute \src "libresoc.v:46374.3-46382.6" + wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 + attribute \src "libresoc.v:42922.3-42923.55" wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46199.3-46207.6" - wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 - attribute \src "libresoc.v:42620.3-42621.63" + attribute \src "libresoc.v:46608.3-46616.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 + attribute \src "libresoc.v:42912.3-42913.63" wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46266.3-46274.6" - wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 - attribute \src "libresoc.v:42616.3-42617.57" + attribute \src "libresoc.v:46675.3-46683.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 + attribute \src "libresoc.v:42908.3-42909.57" wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46218.3-46226.6" - wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 - attribute \src "libresoc.v:42618.3-42619.59" + attribute \src "libresoc.v:46627.3-46635.6" + wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 + attribute \src "libresoc.v:42910.3-42911.59" wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46314.3-46322.6" - wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 - attribute \src "libresoc.v:42614.3-42615.63" + attribute \src "libresoc.v:46723.3-46731.6" + wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 + attribute \src "libresoc.v:42906.3-42907.63" wire $0\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46333.3-46341.6" - wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 - attribute \src "libresoc.v:42612.3-42613.59" + attribute \src "libresoc.v:46742.3-46750.6" + wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 + attribute \src "libresoc.v:42904.3-42905.59" wire $0\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45266.3-45274.6" - wire $0\dp_INT_ra_alu0_0$next[0:0]$2457 - attribute \src "libresoc.v:42688.3-42689.49" + attribute \src "libresoc.v:45823.3-45831.6" + wire $0\dp_INT_ra_alu0_0$next[0:0]$2474 + attribute \src "libresoc.v:42980.3-42981.49" wire $0\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45285.3-45293.6" - wire $0\dp_INT_ra_cr0_1$next[0:0]$2461 - attribute \src "libresoc.v:42686.3-42687.47" + attribute \src "libresoc.v:45842.3-45850.6" + wire $0\dp_INT_ra_cr0_1$next[0:0]$2478 + attribute \src "libresoc.v:42978.3-42979.47" wire $0\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45361.3-45369.6" - wire $0\dp_INT_ra_div0_5$next[0:0]$2485 - attribute \src "libresoc.v:42678.3-42679.49" + attribute \src "libresoc.v:45918.3-45926.6" + wire $0\dp_INT_ra_div0_5$next[0:0]$2502 + attribute \src "libresoc.v:42970.3-42971.49" wire $0\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45418.3-45426.6" - wire $0\dp_INT_ra_ldst0_8$next[0:0]$2503 - attribute \src "libresoc.v:42672.3-42673.51" + attribute \src "libresoc.v:45975.3-45983.6" + wire $0\dp_INT_ra_ldst0_8$next[0:0]$2520 + attribute \src "libresoc.v:42964.3-42965.51" wire $0\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45323.3-45331.6" - wire $0\dp_INT_ra_logical0_3$next[0:0]$2473 - attribute \src "libresoc.v:42682.3-42683.57" + attribute \src "libresoc.v:45880.3-45888.6" + wire $0\dp_INT_ra_logical0_3$next[0:0]$2490 + attribute \src "libresoc.v:42974.3-42975.57" wire $0\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45380.3-45388.6" - wire $0\dp_INT_ra_mul0_6$next[0:0]$2491 - attribute \src "libresoc.v:42676.3-42677.49" + attribute \src "libresoc.v:45937.3-45945.6" + wire $0\dp_INT_ra_mul0_6$next[0:0]$2508 + attribute \src "libresoc.v:42968.3-42969.49" wire $0\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45399.3-45407.6" - wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 - attribute \src "libresoc.v:42674.3-42675.59" + attribute \src "libresoc.v:45956.3-45964.6" + wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 + attribute \src "libresoc.v:42966.3-42967.59" wire $0\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45342.3-45350.6" - wire $0\dp_INT_ra_spr0_4$next[0:0]$2479 - attribute \src "libresoc.v:42680.3-42681.49" + attribute \src "libresoc.v:45899.3-45907.6" + wire $0\dp_INT_ra_spr0_4$next[0:0]$2496 + attribute \src "libresoc.v:42972.3-42973.49" wire $0\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45304.3-45312.6" - wire $0\dp_INT_ra_trap0_2$next[0:0]$2467 - attribute \src "libresoc.v:42684.3-42685.51" + attribute \src "libresoc.v:45861.3-45869.6" + wire $0\dp_INT_ra_trap0_2$next[0:0]$2484 + attribute \src "libresoc.v:42976.3-42977.51" wire $0\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45437.3-45445.6" - wire $0\dp_INT_rb_alu0_0$next[0:0]$2509 - attribute \src "libresoc.v:42670.3-42671.49" + attribute \src "libresoc.v:45994.3-46002.6" + wire $0\dp_INT_rb_alu0_0$next[0:0]$2526 + attribute \src "libresoc.v:42962.3-42963.49" wire $0\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:45456.3-45464.6" - wire $0\dp_INT_rb_cr0_1$next[0:0]$2513 - attribute \src "libresoc.v:42668.3-42669.47" + attribute \src "libresoc.v:46013.3-46021.6" + wire $0\dp_INT_rb_cr0_1$next[0:0]$2530 + attribute \src "libresoc.v:42960.3-42961.47" wire $0\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:45513.3-45521.6" - wire $0\dp_INT_rb_div0_4$next[0:0]$2531 - attribute \src "libresoc.v:42662.3-42663.49" + attribute \src "libresoc.v:46070.3-46078.6" + wire $0\dp_INT_rb_div0_4$next[0:0]$2548 + attribute \src "libresoc.v:42954.3-42955.49" wire $0\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:45570.3-45578.6" - wire $0\dp_INT_rb_ldst0_7$next[0:0]$2549 - attribute \src "libresoc.v:42656.3-42657.51" + attribute \src "libresoc.v:46127.3-46135.6" + wire $0\dp_INT_rb_ldst0_7$next[0:0]$2566 + attribute \src "libresoc.v:42948.3-42949.51" wire $0\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:45494.3-45502.6" - wire $0\dp_INT_rb_logical0_3$next[0:0]$2525 - attribute \src "libresoc.v:42664.3-42665.57" + attribute \src "libresoc.v:46051.3-46059.6" + wire $0\dp_INT_rb_logical0_3$next[0:0]$2542 + attribute \src "libresoc.v:42956.3-42957.57" wire $0\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:45532.3-45540.6" - wire $0\dp_INT_rb_mul0_5$next[0:0]$2537 - attribute \src "libresoc.v:42660.3-42661.49" + attribute \src "libresoc.v:46089.3-46097.6" + wire $0\dp_INT_rb_mul0_5$next[0:0]$2554 + attribute \src "libresoc.v:42952.3-42953.49" wire $0\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:45551.3-45559.6" - wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 - attribute \src "libresoc.v:42658.3-42659.59" + attribute \src "libresoc.v:46108.3-46116.6" + wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 + attribute \src "libresoc.v:42950.3-42951.59" wire $0\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:45475.3-45483.6" - wire $0\dp_INT_rb_trap0_2$next[0:0]$2519 - attribute \src "libresoc.v:42666.3-42667.51" + attribute \src "libresoc.v:46032.3-46040.6" + wire $0\dp_INT_rb_trap0_2$next[0:0]$2536 + attribute \src "libresoc.v:42958.3-42959.51" wire $0\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:45608.3-45616.6" - wire $0\dp_INT_rc_ldst0_1$next[0:0]$2559 - attribute \src "libresoc.v:42652.3-42653.51" + attribute \src "libresoc.v:46165.3-46173.6" + wire $0\dp_INT_rc_ldst0_1$next[0:0]$2576 + attribute \src "libresoc.v:42944.3-42945.51" wire $0\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:45589.3-45597.6" - wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 - attribute \src "libresoc.v:42654.3-42655.59" + attribute \src "libresoc.v:46146.3-46154.6" + wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 + attribute \src "libresoc.v:42946.3-42947.59" wire $0\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46381.3-46389.6" - wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 - attribute \src "libresoc.v:42610.3-42611.53" + attribute \src "libresoc.v:46791.3-46799.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 + attribute \src "libresoc.v:42902.3-42903.53" wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45909.3-45917.6" - wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 - attribute \src "libresoc.v:42638.3-42639.57" + attribute \src "libresoc.v:46298.3-46306.6" + wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 + attribute \src "libresoc.v:42930.3-42931.57" wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45976.3-45984.6" - wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 - attribute \src "libresoc.v:42634.3-42635.67" + attribute \src "libresoc.v:46336.3-46344.6" + wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 + attribute \src "libresoc.v:42926.3-42927.67" wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45957.3-45965.6" - wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 - attribute \src "libresoc.v:42636.3-42637.57" + attribute \src "libresoc.v:46317.3-46325.6" + wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 + attribute \src "libresoc.v:42928.3-42929.57" wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46025.3-46033.6" - wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 - attribute \src "libresoc.v:42632.3-42633.57" + attribute \src "libresoc.v:46355.3-46363.6" + wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 + attribute \src "libresoc.v:42924.3-42925.57" wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:45654.3-45662.6" - wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 - attribute \src "libresoc.v:42650.3-42651.57" + attribute \src "libresoc.v:46184.3-46192.6" + wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 + attribute \src "libresoc.v:42942.3-42943.57" wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45823.3-45831.6" - wire $0\dp_XER_xer_so_div0_3$next[0:0]$2593 - attribute \src "libresoc.v:42644.3-42645.57" + attribute \src "libresoc.v:46241.3-46249.6" + wire $0\dp_XER_xer_so_div0_3$next[0:0]$2598 + attribute \src "libresoc.v:42936.3-42937.57" wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:45764.3-45772.6" - wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 - attribute \src "libresoc.v:42648.3-42649.65" + attribute \src "libresoc.v:46203.3-46211.6" + wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 + attribute \src "libresoc.v:42940.3-42941.65" wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45842.3-45850.6" - wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 - attribute \src "libresoc.v:42642.3-42643.57" + attribute \src "libresoc.v:46260.3-46268.6" + wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 + attribute \src "libresoc.v:42934.3-42935.57" wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45890.3-45898.6" - wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 - attribute \src "libresoc.v:42640.3-42641.67" + attribute \src "libresoc.v:46279.3-46287.6" + wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 + attribute \src "libresoc.v:42932.3-42933.67" wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:45783.3-45791.6" - wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 - attribute \src "libresoc.v:42646.3-42647.57" + attribute \src "libresoc.v:46222.3-46230.6" + wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 + attribute \src "libresoc.v:42938.3-42939.57" wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46901.3-46929.6" - wire $0\fus_cu_issue_i$13[0:0]$2768 - attribute \src "libresoc.v:47298.3-47326.6" - wire $0\fus_cu_issue_i$16[0:0]$2830 - attribute \src "libresoc.v:47662.3-47690.6" - wire $0\fus_cu_issue_i$19[0:0]$2864 - attribute \src "libresoc.v:48158.3-48186.6" - wire $0\fus_cu_issue_i$22[0:0]$2889 - attribute \src "libresoc.v:43485.3-43513.6" - wire $0\fus_cu_issue_i$25[0:0]$2356 - attribute \src "libresoc.v:43981.3-44009.6" - wire $0\fus_cu_issue_i$28[0:0]$2381 - attribute \src "libresoc.v:44303.3-44331.6" - wire $0\fus_cu_issue_i$31[0:0]$2400 - attribute \src "libresoc.v:44770.3-44798.6" - wire $0\fus_cu_issue_i$34[0:0]$2424 - attribute \src "libresoc.v:45208.3-45236.6" - wire $0\fus_cu_issue_i$37[0:0]$2447 - attribute \src "libresoc.v:46693.3-46721.6" + attribute \src "libresoc.v:47566.3-47594.6" + wire $0\fus_cu_issue_i$13[0:0]$2821 + attribute \src "libresoc.v:47900.3-47928.6" + wire $0\fus_cu_issue_i$16[0:0]$2862 + attribute \src "libresoc.v:48219.3-48247.6" + wire $0\fus_cu_issue_i$19[0:0]$2881 + attribute \src "libresoc.v:43868.3-43896.6" + wire $0\fus_cu_issue_i$22[0:0]$2359 + attribute \src "libresoc.v:44042.3-44070.6" + wire $0\fus_cu_issue_i$25[0:0]$2373 + attribute \src "libresoc.v:44538.3-44566.6" + wire $0\fus_cu_issue_i$28[0:0]$2398 + attribute \src "libresoc.v:44860.3-44888.6" + wire $0\fus_cu_issue_i$31[0:0]$2417 + attribute \src "libresoc.v:45327.3-45355.6" + wire $0\fus_cu_issue_i$34[0:0]$2441 + attribute \src "libresoc.v:45765.3-45793.6" + wire $0\fus_cu_issue_i$37[0:0]$2464 + attribute \src "libresoc.v:47349.3-47377.6" wire $0\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46939.3-46967.6" - wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2776 - attribute \src "libresoc.v:47336.3-47364.6" - wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2838 - attribute \src "libresoc.v:47691.3-47719.6" - wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2869 - attribute \src "libresoc.v:48187.3-48215.6" - wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2894 - attribute \src "libresoc.v:43514.3-43542.6" - wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2361 - attribute \src "libresoc.v:44010.3-44038.6" - wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2386 - attribute \src "libresoc.v:44332.3-44360.6" - wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2405 - attribute \src "libresoc.v:44799.3-44827.6" - wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2429 - attribute \src "libresoc.v:45237.3-45265.6" - wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2452 - attribute \src "libresoc.v:46731.3-46759.6" + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2829 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2867 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2886 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2364 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2378 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2403 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2422 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2446 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2469 + attribute \src "libresoc.v:47396.3-47424.6" wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46608.3-46636.6" + attribute \src "libresoc.v:47273.3-47301.6" wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45918.3-45946.6" - wire width 13 $0\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45985.3-46014.6" + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $0\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45985.3-46014.6" + attribute \src "libresoc.v:46761.3-46790.6" wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46438.3-46466.6" + attribute \src "libresoc.v:47094.3-47122.6" wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46655.3-46683.6" + attribute \src "libresoc.v:47311.3-47339.6" wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45861.3-45889.6" + attribute \src "libresoc.v:46646.3-46674.6" wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46237.3-46265.6" + attribute \src "libresoc.v:46933.3-46961.6" wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46352.3-46380.6" + attribute \src "libresoc.v:47018.3-47046.6" wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46523.3-46551.6" + attribute \src "libresoc.v:47188.3-47216.6" wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46570.3-46598.6" + attribute \src "libresoc.v:47226.3-47254.6" wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46150.3-46179.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46150.3-46179.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46485.3-46513.6" + attribute \src "libresoc.v:47141.3-47169.6" wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46063.3-46092.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46063.3-46092.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46400.3-46428.6" + attribute \src "libresoc.v:47056.3-47084.6" wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46285.3-46313.6" + attribute \src "libresoc.v:46980.3-47008.6" wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46986.3-47014.6" + attribute \src "libresoc.v:47651.3-47679.6" wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47071.3-47099.6" - wire width 13 $0\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47156.3-47185.6" + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $0\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47156.3-47185.6" + attribute \src "libresoc.v:47812.3-47841.6" wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47109.3-47137.6" + attribute \src "libresoc.v:47774.3-47802.6" wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47024.3-47052.6" + attribute \src "libresoc.v:47689.3-47717.6" wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47251.3-47279.6" + attribute \src "libresoc.v:47871.3-47899.6" wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47213.3-47241.6" + attribute \src "libresoc.v:47842.3-47870.6" wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46816.3-46844.6" - wire width 13 $0\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46863.3-46891.6" + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $0\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46769.3-46797.6" + attribute \src "libresoc.v:47434.3-47462.6" wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43923.3-43951.6" + attribute \src "libresoc.v:44480.3-44508.6" wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43572.3-43600.6" - wire width 13 $0\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43601.3-43630.6" + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $0\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43601.3-43630.6" + attribute \src "libresoc.v:44158.3-44187.6" wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43749.3-43777.6" + attribute \src "libresoc.v:44306.3-44334.6" wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43952.3-43980.6" + attribute \src "libresoc.v:44509.3-44537.6" wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43543.3-43571.6" + attribute \src "libresoc.v:44100.3-44128.6" wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43691.3-43719.6" + attribute \src "libresoc.v:44248.3-44276.6" wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43778.3-43806.6" + attribute \src "libresoc.v:44335.3-44363.6" wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43865.3-43893.6" + attribute \src "libresoc.v:44422.3-44450.6" wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43894.3-43922.6" + attribute \src "libresoc.v:44451.3-44479.6" wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43661.3-43690.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43661.3-43690.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43836.3-43864.6" + attribute \src "libresoc.v:44393.3-44421.6" wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43631.3-43660.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43631.3-43660.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43807.3-43835.6" + attribute \src "libresoc.v:44364.3-44392.6" wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43720.3-43748.6" + attribute \src "libresoc.v:44277.3-44305.6" wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48100.3-48128.6" + attribute \src "libresoc.v:43810.3-43838.6" wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47749.3-47777.6" - wire width 13 $0\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47778.3-47807.6" + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $0\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47778.3-47807.6" + attribute \src "libresoc.v:48335.3-48364.6" wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47926.3-47954.6" + attribute \src "libresoc.v:48483.3-48511.6" wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48129.3-48157.6" + attribute \src "libresoc.v:43839.3-43867.6" wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47720.3-47748.6" + attribute \src "libresoc.v:48277.3-48305.6" wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47868.3-47896.6" + attribute \src "libresoc.v:48425.3-48453.6" wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47955.3-47983.6" + attribute \src "libresoc.v:48512.3-48540.6" wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48042.3-48070.6" + attribute \src "libresoc.v:43752.3-43780.6" wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48071.3-48099.6" + attribute \src "libresoc.v:43781.3-43809.6" wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47838.3-47867.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47838.3-47867.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48013.3-48041.6" + attribute \src "libresoc.v:43723.3-43751.6" wire $0\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47808.3-47837.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47808.3-47837.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47984.3-48012.6" + attribute \src "libresoc.v:48541.3-48569.6" wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47897.3-47925.6" + attribute \src "libresoc.v:48454.3-48482.6" wire $0\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44068.3-44096.6" - wire width 13 $0\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44097.3-44126.6" + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $0\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44097.3-44126.6" + attribute \src "libresoc.v:44654.3-44683.6" wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44274.3-44302.6" + attribute \src "libresoc.v:44831.3-44859.6" wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44039.3-44067.6" + attribute \src "libresoc.v:44596.3-44624.6" wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44216.3-44244.6" + attribute \src "libresoc.v:44773.3-44801.6" wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44245.3-44273.6" + attribute \src "libresoc.v:44802.3-44830.6" wire $0\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44157.3-44186.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44157.3-44186.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44127.3-44156.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44127.3-44156.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44187.3-44215.6" + attribute \src "libresoc.v:44744.3-44772.6" wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44390.3-44418.6" - wire width 13 $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44419.3-44448.6" + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44419.3-44448.6" + attribute \src "libresoc.v:44976.3-45005.6" wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:45124.3-45152.6" wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:45182.3-45210.6" wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44741.3-44769.6" + attribute \src "libresoc.v:45298.3-45326.6" wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44361.3-44389.6" + attribute \src "libresoc.v:44918.3-44946.6" wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:45095.3-45123.6" wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44683.3-44711.6" + attribute \src "libresoc.v:45240.3-45268.6" wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44712.3-44740.6" + attribute \src "libresoc.v:45269.3-45297.6" wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44479.3-44508.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44479.3-44508.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:45153.3-45181.6" wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44654.3-44682.6" + attribute \src "libresoc.v:45211.3-45239.6" wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44449.3-44478.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44449.3-44478.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:45066.3-45094.6" wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48245.3-48273.6" - wire width 13 $0\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:43427.3-43455.6" + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $0\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48216.3-48244.6" + attribute \src "libresoc.v:43926.3-43954.6" wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43456.3-43484.6" + attribute \src "libresoc.v:44013.3-44041.6" wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47517.3-47545.6" + attribute \src "libresoc.v:48074.3-48102.6" wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47421.3-47449.6" - wire width 13 $0\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47459.3-47487.6" + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $0\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47374.3-47402.6" + attribute \src "libresoc.v:47958.3-47986.6" wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47546.3-47574.6" + attribute \src "libresoc.v:48103.3-48131.6" wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47633.3-47661.6" + attribute \src "libresoc.v:48190.3-48218.6" wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47488.3-47516.6" + attribute \src "libresoc.v:48045.3-48073.6" wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47604.3-47632.6" + attribute \src "libresoc.v:48161.3-48189.6" wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47575.3-47603.6" + attribute \src "libresoc.v:48132.3-48160.6" wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45092.3-45120.6" + attribute \src "libresoc.v:45649.3-45677.6" wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45063.3-45091.6" + attribute \src "libresoc.v:45620.3-45648.6" wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44857.3-44885.6" - wire width 13 $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44886.3-44915.6" + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44886.3-44915.6" + attribute \src "libresoc.v:45443.3-45472.6" wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45179.3-45207.6" + attribute \src "libresoc.v:45736.3-45764.6" wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44828.3-44856.6" + attribute \src "libresoc.v:45385.3-45413.6" wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45005.3-45033.6" + attribute \src "libresoc.v:45562.3-45590.6" wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45034.3-45062.6" + attribute \src "libresoc.v:45591.3-45619.6" wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45150.3-45178.6" + attribute \src "libresoc.v:45707.3-45735.6" wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44975.3-45004.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44975.3-45004.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44945.3-44974.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44945.3-44974.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45121.3-45149.6" + attribute \src "libresoc.v:45678.3-45706.6" wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44916.3-44944.6" + attribute \src "libresoc.v:45473.3-45501.6" wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45294.3-45303.6" - wire width 64 $0\fus_src1_i$42[63:0]$2464 - attribute \src "libresoc.v:45313.3-45322.6" - wire width 64 $0\fus_src1_i$45[63:0]$2470 - attribute \src "libresoc.v:45332.3-45341.6" - wire width 64 $0\fus_src1_i$48[63:0]$2476 - attribute \src "libresoc.v:45351.3-45360.6" - wire width 64 $0\fus_src1_i$51[63:0]$2482 - attribute \src "libresoc.v:45370.3-45379.6" - wire width 64 $0\fus_src1_i$54[63:0]$2488 - attribute \src "libresoc.v:45389.3-45398.6" - wire width 64 $0\fus_src1_i$57[63:0]$2494 - attribute \src "libresoc.v:45408.3-45417.6" - wire width 64 $0\fus_src1_i$60[63:0]$2500 - attribute \src "libresoc.v:45427.3-45436.6" - wire width 64 $0\fus_src1_i$63[63:0]$2506 - attribute \src "libresoc.v:46208.3-46217.6" - wire width 64 $0\fus_src1_i$86[63:0]$2669 - attribute \src "libresoc.v:45275.3-45284.6" + attribute \src "libresoc.v:45851.3-45860.6" + wire width 64 $0\fus_src1_i$42[63:0]$2481 + attribute \src "libresoc.v:45870.3-45879.6" + wire width 64 $0\fus_src1_i$45[63:0]$2487 + attribute \src "libresoc.v:45889.3-45898.6" + wire width 64 $0\fus_src1_i$48[63:0]$2493 + attribute \src "libresoc.v:45908.3-45917.6" + wire width 64 $0\fus_src1_i$51[63:0]$2499 + attribute \src "libresoc.v:45927.3-45936.6" + wire width 64 $0\fus_src1_i$54[63:0]$2505 + attribute \src "libresoc.v:45946.3-45955.6" + wire width 64 $0\fus_src1_i$57[63:0]$2511 + attribute \src "libresoc.v:45965.3-45974.6" + wire width 64 $0\fus_src1_i$60[63:0]$2517 + attribute \src "libresoc.v:45984.3-45993.6" + wire width 64 $0\fus_src1_i$63[63:0]$2523 + attribute \src "libresoc.v:46617.3-46626.6" + wire width 64 $0\fus_src1_i$86[63:0]$2681 + attribute \src "libresoc.v:45832.3-45841.6" wire width 64 $0\fus_src1_i[63:0] - attribute \src "libresoc.v:45465.3-45474.6" - wire width 64 $0\fus_src2_i$64[63:0]$2516 - attribute \src "libresoc.v:45484.3-45493.6" - wire width 64 $0\fus_src2_i$65[63:0]$2522 - attribute \src "libresoc.v:45503.3-45512.6" - wire width 64 $0\fus_src2_i$66[63:0]$2528 - attribute \src "libresoc.v:45522.3-45531.6" - wire width 64 $0\fus_src2_i$67[63:0]$2534 - attribute \src "libresoc.v:45541.3-45550.6" - wire width 64 $0\fus_src2_i$68[63:0]$2540 - attribute \src "libresoc.v:45560.3-45569.6" - wire width 64 $0\fus_src2_i$69[63:0]$2546 - attribute \src "libresoc.v:45579.3-45588.6" - wire width 64 $0\fus_src2_i$70[63:0]$2552 - attribute \src "libresoc.v:46323.3-46332.6" - wire width 64 $0\fus_src2_i$89[63:0]$2689 - attribute \src "libresoc.v:46390.3-46399.6" - wire width 64 $0\fus_src2_i$91[63:0]$2702 - attribute \src "libresoc.v:45446.3-45455.6" + attribute \src "libresoc.v:46022.3-46031.6" + wire width 64 $0\fus_src2_i$64[63:0]$2533 + attribute \src "libresoc.v:46041.3-46050.6" + wire width 64 $0\fus_src2_i$65[63:0]$2539 + attribute \src "libresoc.v:46060.3-46069.6" + wire width 64 $0\fus_src2_i$66[63:0]$2545 + attribute \src "libresoc.v:46079.3-46088.6" + wire width 64 $0\fus_src2_i$67[63:0]$2551 + attribute \src "libresoc.v:46098.3-46107.6" + wire width 64 $0\fus_src2_i$68[63:0]$2557 + attribute \src "libresoc.v:46117.3-46126.6" + wire width 64 $0\fus_src2_i$69[63:0]$2563 + attribute \src "libresoc.v:46136.3-46145.6" + wire width 64 $0\fus_src2_i$70[63:0]$2569 + attribute \src "libresoc.v:46732.3-46741.6" + wire width 64 $0\fus_src2_i$89[63:0]$2701 + attribute \src "libresoc.v:46800.3-46809.6" + wire width 64 $0\fus_src2_i$91[63:0]$2714 + attribute \src "libresoc.v:46003.3-46012.6" wire width 64 $0\fus_src2_i[63:0] - attribute \src "libresoc.v:45617.3-45626.6" - wire width 64 $0\fus_src3_i$71[63:0]$2562 - attribute \src "libresoc.v:45663.3-45672.6" - wire $0\fus_src3_i$72[0:0]$2574 - attribute \src "libresoc.v:45773.3-45782.6" - wire $0\fus_src3_i$73[0:0]$2581 - attribute \src "libresoc.v:45832.3-45841.6" - wire $0\fus_src3_i$74[0:0]$2596 - attribute \src "libresoc.v:45851.3-45860.6" - wire $0\fus_src3_i$75[0:0]$2602 - attribute \src "libresoc.v:46053.3-46062.6" - wire width 32 $0\fus_src3_i$79[31:0]$2637 - attribute \src "libresoc.v:46121.3-46130.6" - wire width 4 $0\fus_src3_i$83[3:0]$2650 - attribute \src "libresoc.v:46227.3-46236.6" - wire width 64 $0\fus_src3_i$87[63:0]$2675 - attribute \src "libresoc.v:46275.3-46284.6" - wire width 64 $0\fus_src3_i$88[63:0]$2682 - attribute \src "libresoc.v:45598.3-45607.6" + attribute \src "libresoc.v:46174.3-46183.6" + wire width 64 $0\fus_src3_i$71[63:0]$2579 + attribute \src "libresoc.v:46193.3-46202.6" + wire $0\fus_src3_i$72[0:0]$2585 + attribute \src "libresoc.v:46212.3-46221.6" + wire $0\fus_src3_i$73[0:0]$2591 + attribute \src "libresoc.v:46250.3-46259.6" + wire $0\fus_src3_i$74[0:0]$2601 + attribute \src "libresoc.v:46269.3-46278.6" + wire $0\fus_src3_i$75[0:0]$2607 + attribute \src "libresoc.v:46383.3-46392.6" + wire width 32 $0\fus_src3_i$79[31:0]$2639 + attribute \src "libresoc.v:46421.3-46430.6" + wire width 4 $0\fus_src3_i$83[3:0]$2651 + attribute \src "libresoc.v:46636.3-46645.6" + wire width 64 $0\fus_src3_i$87[63:0]$2687 + attribute \src "libresoc.v:46684.3-46693.6" + wire width 64 $0\fus_src3_i$88[63:0]$2694 + attribute \src "libresoc.v:46155.3-46164.6" wire width 64 $0\fus_src3_i[63:0] - attribute \src "libresoc.v:45899.3-45908.6" - wire $0\fus_src4_i$76[0:0]$2609 - attribute \src "libresoc.v:45947.3-45956.6" - wire width 2 $0\fus_src4_i$77[1:0]$2616 - attribute \src "libresoc.v:46102.3-46111.6" - wire width 4 $0\fus_src4_i$80[3:0]$2644 - attribute \src "libresoc.v:46342.3-46351.6" - wire width 64 $0\fus_src4_i$90[63:0]$2695 - attribute \src "libresoc.v:45792.3-45801.6" + attribute \src "libresoc.v:46288.3-46297.6" + wire $0\fus_src4_i$76[0:0]$2613 + attribute \src "libresoc.v:46307.3-46316.6" + wire width 2 $0\fus_src4_i$77[1:0]$2619 + attribute \src "libresoc.v:46402.3-46411.6" + wire width 4 $0\fus_src4_i$80[3:0]$2645 + attribute \src "libresoc.v:46751.3-46760.6" + wire width 64 $0\fus_src4_i$90[63:0]$2707 + attribute \src "libresoc.v:46231.3-46240.6" wire $0\fus_src4_i[0:0] - attribute \src "libresoc.v:46034.3-46043.6" - wire width 2 $0\fus_src5_i$78[1:0]$2631 - attribute \src "libresoc.v:46140.3-46149.6" - wire width 4 $0\fus_src5_i$84[3:0]$2656 - attribute \src "libresoc.v:46015.3-46024.6" + attribute \src "libresoc.v:46364.3-46373.6" + wire width 2 $0\fus_src5_i$78[1:0]$2633 + attribute \src "libresoc.v:46467.3-46476.6" + wire width 4 $0\fus_src5_i$84[3:0]$2663 + attribute \src "libresoc.v:46345.3-46354.6" wire width 2 $0\fus_src5_i[1:0] - attribute \src "libresoc.v:46189.3-46198.6" - wire width 4 $0\fus_src6_i$85[3:0]$2663 - attribute \src "libresoc.v:45966.3-45975.6" + attribute \src "libresoc.v:46577.3-46586.6" + wire width 4 $0\fus_src6_i$85[3:0]$2670 + attribute \src "libresoc.v:46326.3-46335.6" wire width 2 $0\fus_src6_i[1:0] - attribute \src "libresoc.v:35982.7-35982.20" + attribute \src "libresoc.v:36214.7-36214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:46476.3-46484.6" - wire $0\wr_pick_dly$1005$next[0:0]$2713 - attribute \src "libresoc.v:42604.3-42605.51" - wire $0\wr_pick_dly$1005[0:0]$2307 - attribute \src "libresoc.v:41434.7-41434.32" - wire $0\wr_pick_dly$1005[0:0]$2945 - attribute \src "libresoc.v:46514.3-46522.6" - wire $0\wr_pick_dly$1026$next[0:0]$2717 - attribute \src "libresoc.v:42602.3-42603.51" - wire $0\wr_pick_dly$1026[0:0]$2305 - attribute \src "libresoc.v:41438.7-41438.32" - wire $0\wr_pick_dly$1026[0:0]$2947 - attribute \src "libresoc.v:46552.3-46560.6" - wire $0\wr_pick_dly$1044$next[0:0]$2721 - attribute \src "libresoc.v:42600.3-42601.51" - wire $0\wr_pick_dly$1044[0:0]$2303 - attribute \src "libresoc.v:41442.7-41442.32" - wire $0\wr_pick_dly$1044[0:0]$2949 - attribute \src "libresoc.v:46561.3-46569.6" - wire $0\wr_pick_dly$1066$next[0:0]$2724 - attribute \src "libresoc.v:42598.3-42599.51" - wire $0\wr_pick_dly$1066[0:0]$2301 - attribute \src "libresoc.v:41446.7-41446.32" - wire $0\wr_pick_dly$1066[0:0]$2951 - attribute \src "libresoc.v:46599.3-46607.6" - wire $0\wr_pick_dly$1086$next[0:0]$2728 - attribute \src "libresoc.v:42596.3-42597.51" - wire $0\wr_pick_dly$1086[0:0]$2299 - attribute \src "libresoc.v:41450.7-41450.32" - wire $0\wr_pick_dly$1086[0:0]$2953 - attribute \src "libresoc.v:46637.3-46645.6" - wire $0\wr_pick_dly$1106$next[0:0]$2732 - attribute \src "libresoc.v:42594.3-42595.51" - wire $0\wr_pick_dly$1106[0:0]$2297 - attribute \src "libresoc.v:41454.7-41454.32" - wire $0\wr_pick_dly$1106[0:0]$2955 - attribute \src "libresoc.v:46646.3-46654.6" - wire $0\wr_pick_dly$1125$next[0:0]$2735 - attribute \src "libresoc.v:42592.3-42593.51" - wire $0\wr_pick_dly$1125[0:0]$2295 - attribute \src "libresoc.v:41458.7-41458.32" - wire $0\wr_pick_dly$1125[0:0]$2957 - attribute \src "libresoc.v:46684.3-46692.6" - wire $0\wr_pick_dly$1143$next[0:0]$2739 - attribute \src "libresoc.v:42590.3-42591.51" - wire $0\wr_pick_dly$1143[0:0]$2293 - attribute \src "libresoc.v:41462.7-41462.32" - wire $0\wr_pick_dly$1143[0:0]$2959 - attribute \src "libresoc.v:46722.3-46730.6" - wire $0\wr_pick_dly$1217$next[0:0]$2743 - attribute \src "libresoc.v:42588.3-42589.51" - wire $0\wr_pick_dly$1217[0:0]$2291 - attribute \src "libresoc.v:41466.7-41466.32" - wire $0\wr_pick_dly$1217[0:0]$2961 - attribute \src "libresoc.v:46760.3-46768.6" - wire $0\wr_pick_dly$1245$next[0:0]$2747 - attribute \src "libresoc.v:42586.3-42587.51" - wire $0\wr_pick_dly$1245[0:0]$2289 - attribute \src "libresoc.v:41470.7-41470.32" - wire $0\wr_pick_dly$1245[0:0]$2963 - attribute \src "libresoc.v:46798.3-46806.6" - wire $0\wr_pick_dly$1265$next[0:0]$2751 - attribute \src "libresoc.v:42584.3-42585.51" - wire $0\wr_pick_dly$1265[0:0]$2287 - attribute \src "libresoc.v:41474.7-41474.32" - wire $0\wr_pick_dly$1265[0:0]$2965 - attribute \src "libresoc.v:46807.3-46815.6" - wire $0\wr_pick_dly$1285$next[0:0]$2754 - attribute \src "libresoc.v:42582.3-42583.51" - wire $0\wr_pick_dly$1285[0:0]$2285 - attribute \src "libresoc.v:41478.7-41478.32" - wire $0\wr_pick_dly$1285[0:0]$2967 - attribute \src "libresoc.v:46845.3-46853.6" - wire $0\wr_pick_dly$1305$next[0:0]$2758 - attribute \src "libresoc.v:42580.3-42581.51" - wire $0\wr_pick_dly$1305[0:0]$2283 - attribute \src "libresoc.v:41482.7-41482.32" - wire $0\wr_pick_dly$1305[0:0]$2969 - attribute \src "libresoc.v:46854.3-46862.6" - wire $0\wr_pick_dly$1325$next[0:0]$2761 - attribute \src "libresoc.v:42578.3-42579.51" - wire $0\wr_pick_dly$1325[0:0]$2281 - attribute \src "libresoc.v:41486.7-41486.32" - wire $0\wr_pick_dly$1325[0:0]$2971 - attribute \src "libresoc.v:46892.3-46900.6" - wire $0\wr_pick_dly$1345$next[0:0]$2765 - attribute \src "libresoc.v:42576.3-42577.51" - wire $0\wr_pick_dly$1345[0:0]$2279 - attribute \src "libresoc.v:41490.7-41490.32" - wire $0\wr_pick_dly$1345[0:0]$2973 - attribute \src "libresoc.v:46930.3-46938.6" - wire $0\wr_pick_dly$1392$next[0:0]$2773 - attribute \src "libresoc.v:42574.3-42575.51" - wire $0\wr_pick_dly$1392[0:0]$2277 - attribute \src "libresoc.v:41494.7-41494.32" - wire $0\wr_pick_dly$1392[0:0]$2975 - attribute \src "libresoc.v:46968.3-46976.6" - wire $0\wr_pick_dly$1408$next[0:0]$2781 - attribute \src "libresoc.v:42572.3-42573.51" - wire $0\wr_pick_dly$1408[0:0]$2275 - attribute \src "libresoc.v:41498.7-41498.32" - wire $0\wr_pick_dly$1408[0:0]$2977 - attribute \src "libresoc.v:46977.3-46985.6" - wire $0\wr_pick_dly$1424$next[0:0]$2784 - attribute \src "libresoc.v:42570.3-42571.51" - wire $0\wr_pick_dly$1424[0:0]$2273 - attribute \src "libresoc.v:41502.7-41502.32" - wire $0\wr_pick_dly$1424[0:0]$2979 - attribute \src "libresoc.v:47015.3-47023.6" - wire $0\wr_pick_dly$1458$next[0:0]$2788 - attribute \src "libresoc.v:42568.3-42569.51" - wire $0\wr_pick_dly$1458[0:0]$2271 - attribute \src "libresoc.v:41506.7-41506.32" - wire $0\wr_pick_dly$1458[0:0]$2981 - attribute \src "libresoc.v:47053.3-47061.6" - wire $0\wr_pick_dly$1474$next[0:0]$2792 - attribute \src "libresoc.v:42566.3-42567.51" - wire $0\wr_pick_dly$1474[0:0]$2269 - attribute \src "libresoc.v:41510.7-41510.32" - wire $0\wr_pick_dly$1474[0:0]$2983 - attribute \src "libresoc.v:47062.3-47070.6" - wire $0\wr_pick_dly$1490$next[0:0]$2795 - attribute \src "libresoc.v:42564.3-42565.51" - wire $0\wr_pick_dly$1490[0:0]$2267 - attribute \src "libresoc.v:41514.7-41514.32" - wire $0\wr_pick_dly$1490[0:0]$2985 - attribute \src "libresoc.v:47100.3-47108.6" - wire $0\wr_pick_dly$1506$next[0:0]$2799 - attribute \src "libresoc.v:42562.3-42563.51" - wire $0\wr_pick_dly$1506[0:0]$2265 - attribute \src "libresoc.v:41518.7-41518.32" - wire $0\wr_pick_dly$1506[0:0]$2987 - attribute \src "libresoc.v:47138.3-47146.6" - wire $0\wr_pick_dly$1542$next[0:0]$2803 - attribute \src "libresoc.v:42560.3-42561.51" - wire $0\wr_pick_dly$1542[0:0]$2263 - attribute \src "libresoc.v:41522.7-41522.32" - wire $0\wr_pick_dly$1542[0:0]$2989 - attribute \src "libresoc.v:47147.3-47155.6" - wire $0\wr_pick_dly$1558$next[0:0]$2806 - attribute \src "libresoc.v:42558.3-42559.51" - wire $0\wr_pick_dly$1558[0:0]$2261 - attribute \src "libresoc.v:41526.7-41526.32" - wire $0\wr_pick_dly$1558[0:0]$2991 - attribute \src "libresoc.v:47186.3-47194.6" - wire $0\wr_pick_dly$1574$next[0:0]$2810 - attribute \src "libresoc.v:42556.3-42557.51" - wire $0\wr_pick_dly$1574[0:0]$2259 - attribute \src "libresoc.v:41530.7-41530.32" - wire $0\wr_pick_dly$1574[0:0]$2993 - attribute \src "libresoc.v:47195.3-47203.6" - wire $0\wr_pick_dly$1590$next[0:0]$2813 - attribute \src "libresoc.v:42554.3-42555.51" - wire $0\wr_pick_dly$1590[0:0]$2257 - attribute \src "libresoc.v:41534.7-41534.32" - wire $0\wr_pick_dly$1590[0:0]$2995 - attribute \src "libresoc.v:47204.3-47212.6" - wire $0\wr_pick_dly$1632$next[0:0]$2816 - attribute \src "libresoc.v:42552.3-42553.51" - wire $0\wr_pick_dly$1632[0:0]$2255 - attribute \src "libresoc.v:41538.7-41538.32" - wire $0\wr_pick_dly$1632[0:0]$2997 - attribute \src "libresoc.v:47242.3-47250.6" - wire $0\wr_pick_dly$1651$next[0:0]$2820 - attribute \src "libresoc.v:42550.3-42551.51" - wire $0\wr_pick_dly$1651[0:0]$2253 - attribute \src "libresoc.v:41542.7-41542.32" - wire $0\wr_pick_dly$1651[0:0]$2999 - attribute \src "libresoc.v:47280.3-47288.6" - wire $0\wr_pick_dly$1667$next[0:0]$2824 - attribute \src "libresoc.v:42548.3-42549.51" - wire $0\wr_pick_dly$1667[0:0]$2251 - attribute \src "libresoc.v:41546.7-41546.32" - wire $0\wr_pick_dly$1667[0:0]$3001 - attribute \src "libresoc.v:47289.3-47297.6" - wire $0\wr_pick_dly$1683$next[0:0]$2827 - attribute \src "libresoc.v:42546.3-42547.51" - wire $0\wr_pick_dly$1683[0:0]$2249 - attribute \src "libresoc.v:41550.7-41550.32" - wire $0\wr_pick_dly$1683[0:0]$3003 - attribute \src "libresoc.v:47327.3-47335.6" - wire $0\wr_pick_dly$1699$next[0:0]$2835 - attribute \src "libresoc.v:42544.3-42545.51" - wire $0\wr_pick_dly$1699[0:0]$2247 - attribute \src "libresoc.v:41554.7-41554.32" - wire $0\wr_pick_dly$1699[0:0]$3005 - attribute \src "libresoc.v:47365.3-47373.6" - wire $0\wr_pick_dly$1743$next[0:0]$2843 - attribute \src "libresoc.v:42542.3-42543.51" - wire $0\wr_pick_dly$1743[0:0]$2245 - attribute \src "libresoc.v:41558.7-41558.32" - wire $0\wr_pick_dly$1743[0:0]$3007 - attribute \src "libresoc.v:47403.3-47411.6" - wire $0\wr_pick_dly$1759$next[0:0]$2847 - attribute \src "libresoc.v:42540.3-42541.51" - wire $0\wr_pick_dly$1759[0:0]$2243 - attribute \src "libresoc.v:41562.7-41562.32" - wire $0\wr_pick_dly$1759[0:0]$3009 - attribute \src "libresoc.v:47412.3-47420.6" - wire $0\wr_pick_dly$1783$next[0:0]$2850 - attribute \src "libresoc.v:42538.3-42539.51" - wire $0\wr_pick_dly$1783[0:0]$2241 - attribute \src "libresoc.v:41566.7-41566.32" - wire $0\wr_pick_dly$1783[0:0]$3011 - attribute \src "libresoc.v:47450.3-47458.6" - wire $0\wr_pick_dly$1803$next[0:0]$2854 - attribute \src "libresoc.v:42536.3-42537.51" - wire $0\wr_pick_dly$1803[0:0]$2239 - attribute \src "libresoc.v:41570.7-41570.32" - wire $0\wr_pick_dly$1803[0:0]$3013 - attribute \src "libresoc.v:46467.3-46475.6" - wire $0\wr_pick_dly$986$next[0:0]$2710 - attribute \src "libresoc.v:42606.3-42607.49" - wire $0\wr_pick_dly$986[0:0]$2309 - attribute \src "libresoc.v:41574.7-41574.31" - wire $0\wr_pick_dly$986[0:0]$3015 - attribute \src "libresoc.v:46429.3-46437.6" - wire $0\wr_pick_dly$next[0:0]$2706 - attribute \src "libresoc.v:42608.3-42609.39" + attribute \src "libresoc.v:46858.3-46866.6" + wire $0\wr_pick_dly$1010$next[0:0]$2724 + attribute \src "libresoc.v:42896.3-42897.51" + wire $0\wr_pick_dly$1010[0:0]$2307 + attribute \src "libresoc.v:41726.7-41726.32" + wire $0\wr_pick_dly$1010[0:0]$2945 + attribute \src "libresoc.v:46867.3-46875.6" + wire $0\wr_pick_dly$1031$next[0:0]$2727 + attribute \src "libresoc.v:42894.3-42895.51" + wire $0\wr_pick_dly$1031[0:0]$2305 + attribute \src "libresoc.v:41730.7-41730.32" + wire $0\wr_pick_dly$1031[0:0]$2947 + attribute \src "libresoc.v:46906.3-46914.6" + wire $0\wr_pick_dly$1049$next[0:0]$2731 + attribute \src "libresoc.v:42892.3-42893.51" + wire $0\wr_pick_dly$1049[0:0]$2303 + attribute \src "libresoc.v:41734.7-41734.32" + wire $0\wr_pick_dly$1049[0:0]$2949 + attribute \src "libresoc.v:46915.3-46923.6" + wire $0\wr_pick_dly$1071$next[0:0]$2734 + attribute \src "libresoc.v:42890.3-42891.51" + wire $0\wr_pick_dly$1071[0:0]$2301 + attribute \src "libresoc.v:41738.7-41738.32" + wire $0\wr_pick_dly$1071[0:0]$2951 + attribute \src "libresoc.v:46924.3-46932.6" + wire $0\wr_pick_dly$1091$next[0:0]$2737 + attribute \src "libresoc.v:42888.3-42889.51" + wire $0\wr_pick_dly$1091[0:0]$2299 + attribute \src "libresoc.v:41742.7-41742.32" + wire $0\wr_pick_dly$1091[0:0]$2953 + attribute \src "libresoc.v:46962.3-46970.6" + wire $0\wr_pick_dly$1111$next[0:0]$2741 + attribute \src "libresoc.v:42886.3-42887.51" + wire $0\wr_pick_dly$1111[0:0]$2297 + attribute \src "libresoc.v:41746.7-41746.32" + wire $0\wr_pick_dly$1111[0:0]$2955 + attribute \src "libresoc.v:46971.3-46979.6" + wire $0\wr_pick_dly$1130$next[0:0]$2744 + attribute \src "libresoc.v:42884.3-42885.51" + wire $0\wr_pick_dly$1130[0:0]$2295 + attribute \src "libresoc.v:41750.7-41750.32" + wire $0\wr_pick_dly$1130[0:0]$2957 + attribute \src "libresoc.v:47009.3-47017.6" + wire $0\wr_pick_dly$1148$next[0:0]$2748 + attribute \src "libresoc.v:42882.3-42883.51" + wire $0\wr_pick_dly$1148[0:0]$2293 + attribute \src "libresoc.v:41754.7-41754.32" + wire $0\wr_pick_dly$1148[0:0]$2959 + attribute \src "libresoc.v:47047.3-47055.6" + wire $0\wr_pick_dly$1222$next[0:0]$2752 + attribute \src "libresoc.v:42880.3-42881.51" + wire $0\wr_pick_dly$1222[0:0]$2291 + attribute \src "libresoc.v:41758.7-41758.32" + wire $0\wr_pick_dly$1222[0:0]$2961 + attribute \src "libresoc.v:47085.3-47093.6" + wire $0\wr_pick_dly$1250$next[0:0]$2756 + attribute \src "libresoc.v:42878.3-42879.51" + wire $0\wr_pick_dly$1250[0:0]$2289 + attribute \src "libresoc.v:41762.7-41762.32" + wire $0\wr_pick_dly$1250[0:0]$2963 + attribute \src "libresoc.v:47123.3-47131.6" + wire $0\wr_pick_dly$1270$next[0:0]$2760 + attribute \src "libresoc.v:42876.3-42877.51" + wire $0\wr_pick_dly$1270[0:0]$2287 + attribute \src "libresoc.v:41766.7-41766.32" + wire $0\wr_pick_dly$1270[0:0]$2965 + attribute \src "libresoc.v:47132.3-47140.6" + wire $0\wr_pick_dly$1290$next[0:0]$2763 + attribute \src "libresoc.v:42874.3-42875.51" + wire $0\wr_pick_dly$1290[0:0]$2285 + attribute \src "libresoc.v:41770.7-41770.32" + wire $0\wr_pick_dly$1290[0:0]$2967 + attribute \src "libresoc.v:47170.3-47178.6" + wire $0\wr_pick_dly$1310$next[0:0]$2767 + attribute \src "libresoc.v:42872.3-42873.51" + wire $0\wr_pick_dly$1310[0:0]$2283 + attribute \src "libresoc.v:41774.7-41774.32" + wire $0\wr_pick_dly$1310[0:0]$2969 + attribute \src "libresoc.v:47179.3-47187.6" + wire $0\wr_pick_dly$1330$next[0:0]$2770 + attribute \src "libresoc.v:42870.3-42871.51" + wire $0\wr_pick_dly$1330[0:0]$2281 + attribute \src "libresoc.v:41778.7-41778.32" + wire $0\wr_pick_dly$1330[0:0]$2971 + attribute \src "libresoc.v:47217.3-47225.6" + wire $0\wr_pick_dly$1350$next[0:0]$2774 + attribute \src "libresoc.v:42868.3-42869.51" + wire $0\wr_pick_dly$1350[0:0]$2279 + attribute \src "libresoc.v:41782.7-41782.32" + wire $0\wr_pick_dly$1350[0:0]$2973 + attribute \src "libresoc.v:47255.3-47263.6" + wire $0\wr_pick_dly$1397$next[0:0]$2778 + attribute \src "libresoc.v:42866.3-42867.51" + wire $0\wr_pick_dly$1397[0:0]$2277 + attribute \src "libresoc.v:41786.7-41786.32" + wire $0\wr_pick_dly$1397[0:0]$2975 + attribute \src "libresoc.v:47264.3-47272.6" + wire $0\wr_pick_dly$1413$next[0:0]$2781 + attribute \src "libresoc.v:42864.3-42865.51" + wire $0\wr_pick_dly$1413[0:0]$2275 + attribute \src "libresoc.v:41790.7-41790.32" + wire $0\wr_pick_dly$1413[0:0]$2977 + attribute \src "libresoc.v:47302.3-47310.6" + wire $0\wr_pick_dly$1429$next[0:0]$2785 + attribute \src "libresoc.v:42862.3-42863.51" + wire $0\wr_pick_dly$1429[0:0]$2273 + attribute \src "libresoc.v:41794.7-41794.32" + wire $0\wr_pick_dly$1429[0:0]$2979 + attribute \src "libresoc.v:47340.3-47348.6" + wire $0\wr_pick_dly$1463$next[0:0]$2789 + attribute \src "libresoc.v:42860.3-42861.51" + wire $0\wr_pick_dly$1463[0:0]$2271 + attribute \src "libresoc.v:41798.7-41798.32" + wire $0\wr_pick_dly$1463[0:0]$2981 + attribute \src "libresoc.v:47378.3-47386.6" + wire $0\wr_pick_dly$1479$next[0:0]$2793 + attribute \src "libresoc.v:42858.3-42859.51" + wire $0\wr_pick_dly$1479[0:0]$2269 + attribute \src "libresoc.v:41802.7-41802.32" + wire $0\wr_pick_dly$1479[0:0]$2983 + attribute \src "libresoc.v:47387.3-47395.6" + wire $0\wr_pick_dly$1495$next[0:0]$2796 + attribute \src "libresoc.v:42856.3-42857.51" + wire $0\wr_pick_dly$1495[0:0]$2267 + attribute \src "libresoc.v:41806.7-41806.32" + wire $0\wr_pick_dly$1495[0:0]$2985 + attribute \src "libresoc.v:47425.3-47433.6" + wire $0\wr_pick_dly$1511$next[0:0]$2800 + attribute \src "libresoc.v:42854.3-42855.51" + wire $0\wr_pick_dly$1511[0:0]$2265 + attribute \src "libresoc.v:41810.7-41810.32" + wire $0\wr_pick_dly$1511[0:0]$2987 + attribute \src "libresoc.v:47463.3-47471.6" + wire $0\wr_pick_dly$1547$next[0:0]$2804 + attribute \src "libresoc.v:42852.3-42853.51" + wire $0\wr_pick_dly$1547[0:0]$2263 + attribute \src "libresoc.v:41814.7-41814.32" + wire $0\wr_pick_dly$1547[0:0]$2989 + attribute \src "libresoc.v:47472.3-47480.6" + wire $0\wr_pick_dly$1563$next[0:0]$2807 + attribute \src "libresoc.v:42850.3-42851.51" + wire $0\wr_pick_dly$1563[0:0]$2261 + attribute \src "libresoc.v:41818.7-41818.32" + wire $0\wr_pick_dly$1563[0:0]$2991 + attribute \src "libresoc.v:47510.3-47518.6" + wire $0\wr_pick_dly$1579$next[0:0]$2811 + attribute \src "libresoc.v:42848.3-42849.51" + wire $0\wr_pick_dly$1579[0:0]$2259 + attribute \src "libresoc.v:41822.7-41822.32" + wire $0\wr_pick_dly$1579[0:0]$2993 + attribute \src "libresoc.v:47519.3-47527.6" + wire $0\wr_pick_dly$1595$next[0:0]$2814 + attribute \src "libresoc.v:42846.3-42847.51" + wire $0\wr_pick_dly$1595[0:0]$2257 + attribute \src "libresoc.v:41826.7-41826.32" + wire $0\wr_pick_dly$1595[0:0]$2995 + attribute \src "libresoc.v:47557.3-47565.6" + wire $0\wr_pick_dly$1637$next[0:0]$2818 + attribute \src "libresoc.v:42844.3-42845.51" + wire $0\wr_pick_dly$1637[0:0]$2255 + attribute \src "libresoc.v:41830.7-41830.32" + wire $0\wr_pick_dly$1637[0:0]$2997 + attribute \src "libresoc.v:47595.3-47603.6" + wire $0\wr_pick_dly$1656$next[0:0]$2826 + attribute \src "libresoc.v:42842.3-42843.51" + wire $0\wr_pick_dly$1656[0:0]$2253 + attribute \src "libresoc.v:41834.7-41834.32" + wire $0\wr_pick_dly$1656[0:0]$2999 + attribute \src "libresoc.v:47633.3-47641.6" + wire $0\wr_pick_dly$1672$next[0:0]$2834 + attribute \src "libresoc.v:42840.3-42841.51" + wire $0\wr_pick_dly$1672[0:0]$2251 + attribute \src "libresoc.v:41838.7-41838.32" + wire $0\wr_pick_dly$1672[0:0]$3001 + attribute \src "libresoc.v:47642.3-47650.6" + wire $0\wr_pick_dly$1688$next[0:0]$2837 + attribute \src "libresoc.v:42838.3-42839.51" + wire $0\wr_pick_dly$1688[0:0]$2249 + attribute \src "libresoc.v:41842.7-41842.32" + wire $0\wr_pick_dly$1688[0:0]$3003 + attribute \src "libresoc.v:47680.3-47688.6" + wire $0\wr_pick_dly$1704$next[0:0]$2841 + attribute \src "libresoc.v:42836.3-42837.51" + wire $0\wr_pick_dly$1704[0:0]$2247 + attribute \src "libresoc.v:41846.7-41846.32" + wire $0\wr_pick_dly$1704[0:0]$3005 + attribute \src "libresoc.v:47718.3-47726.6" + wire $0\wr_pick_dly$1748$next[0:0]$2845 + attribute \src "libresoc.v:42834.3-42835.51" + wire $0\wr_pick_dly$1748[0:0]$2245 + attribute \src "libresoc.v:41850.7-41850.32" + wire $0\wr_pick_dly$1748[0:0]$3007 + attribute \src "libresoc.v:47727.3-47735.6" + wire $0\wr_pick_dly$1764$next[0:0]$2848 + attribute \src "libresoc.v:42832.3-42833.51" + wire $0\wr_pick_dly$1764[0:0]$2243 + attribute \src "libresoc.v:41854.7-41854.32" + wire $0\wr_pick_dly$1764[0:0]$3009 + attribute \src "libresoc.v:47765.3-47773.6" + wire $0\wr_pick_dly$1788$next[0:0]$2852 + attribute \src "libresoc.v:42830.3-42831.51" + wire $0\wr_pick_dly$1788[0:0]$2241 + attribute \src "libresoc.v:41858.7-41858.32" + wire $0\wr_pick_dly$1788[0:0]$3011 + attribute \src "libresoc.v:47803.3-47811.6" + wire $0\wr_pick_dly$1808$next[0:0]$2856 + attribute \src "libresoc.v:42828.3-42829.51" + wire $0\wr_pick_dly$1808[0:0]$2239 + attribute \src "libresoc.v:41862.7-41862.32" + wire $0\wr_pick_dly$1808[0:0]$3013 + attribute \src "libresoc.v:46819.3-46827.6" + wire $0\wr_pick_dly$991$next[0:0]$2720 + attribute \src "libresoc.v:42898.3-42899.49" + wire $0\wr_pick_dly$991[0:0]$2309 + attribute \src "libresoc.v:41866.7-41866.31" + wire $0\wr_pick_dly$991[0:0]$3015 + attribute \src "libresoc.v:46810.3-46818.6" + wire $0\wr_pick_dly$next[0:0]$2717 + attribute \src "libresoc.v:42900.3-42901.39" wire $0\wr_pick_dly[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $10\corebusy_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $11\corebusy_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $12\corebusy_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $13\corebusy_o[0:0] - attribute \src "libresoc.v:45802.3-45822.6" - wire $1\core_terminate_o$next[0:0]$2589 - attribute \src "libresoc.v:38029.7-38029.30" + attribute \src "libresoc.v:46587.3-46607.6" + wire $1\core_terminate_o$next[0:0]$2674 + attribute \src "libresoc.v:38263.7-38263.30" wire $1\core_terminate_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $1\corebusy_o[0:0] - attribute \src "libresoc.v:45627.3-45653.6" - wire width 2 $1\counter$next[1:0]$2566 - attribute \src "libresoc.v:38042.13-38042.27" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $1\counter$next[1:0]$2655 + attribute \src "libresoc.v:38276.13-38276.27" wire width 2 $1\counter[1:0] - attribute \src "libresoc.v:46112.3-46120.6" - wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:39183.7-39183.34" + attribute \src "libresoc.v:46412.3-46420.6" + wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 + attribute \src "libresoc.v:39443.7-39443.34" wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46093.3-46101.6" - wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:39187.7-39187.30" + attribute \src "libresoc.v:46393.3-46401.6" + wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 + attribute \src "libresoc.v:39447.7-39447.30" wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46131.3-46139.6" - wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 - attribute \src "libresoc.v:39191.7-39191.30" + attribute \src "libresoc.v:46458.3-46466.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:39451.7-39451.30" wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46180.3-46188.6" - wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:39195.7-39195.30" + attribute \src "libresoc.v:46568.3-46576.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 + attribute \src "libresoc.v:39455.7-39455.30" wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46044.3-46052.6" - wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 - attribute \src "libresoc.v:39199.7-39199.33" + attribute \src "libresoc.v:46374.3-46382.6" + wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 + attribute \src "libresoc.v:39459.7-39459.33" wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46199.3-46207.6" - wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 - attribute \src "libresoc.v:39203.7-39203.37" + attribute \src "libresoc.v:46608.3-46616.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 + attribute \src "libresoc.v:39463.7-39463.37" wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46266.3-46274.6" - wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 - attribute \src "libresoc.v:39207.7-39207.34" + attribute \src "libresoc.v:46675.3-46683.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 + attribute \src "libresoc.v:39467.7-39467.34" wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46218.3-46226.6" - wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 - attribute \src "libresoc.v:39211.7-39211.35" + attribute \src "libresoc.v:46627.3-46635.6" + wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 + attribute \src "libresoc.v:39471.7-39471.35" wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46314.3-46322.6" - wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 - attribute \src "libresoc.v:39215.7-39215.37" + attribute \src "libresoc.v:46723.3-46731.6" + wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 + attribute \src "libresoc.v:39475.7-39475.37" wire $1\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46333.3-46341.6" - wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 - attribute \src "libresoc.v:39219.7-39219.35" + attribute \src "libresoc.v:46742.3-46750.6" + wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 + attribute \src "libresoc.v:39479.7-39479.35" wire $1\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45266.3-45274.6" - wire $1\dp_INT_ra_alu0_0$next[0:0]$2458 - attribute \src "libresoc.v:39223.7-39223.30" + attribute \src "libresoc.v:45823.3-45831.6" + wire $1\dp_INT_ra_alu0_0$next[0:0]$2475 + attribute \src "libresoc.v:39483.7-39483.30" wire $1\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45285.3-45293.6" - wire $1\dp_INT_ra_cr0_1$next[0:0]$2462 - attribute \src "libresoc.v:39227.7-39227.29" + attribute \src "libresoc.v:45842.3-45850.6" + wire $1\dp_INT_ra_cr0_1$next[0:0]$2479 + attribute \src "libresoc.v:39487.7-39487.29" wire $1\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45361.3-45369.6" - wire $1\dp_INT_ra_div0_5$next[0:0]$2486 - attribute \src "libresoc.v:39231.7-39231.30" + attribute \src "libresoc.v:45918.3-45926.6" + wire $1\dp_INT_ra_div0_5$next[0:0]$2503 + attribute \src "libresoc.v:39491.7-39491.30" wire $1\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45418.3-45426.6" - wire $1\dp_INT_ra_ldst0_8$next[0:0]$2504 - attribute \src "libresoc.v:39235.7-39235.31" + attribute \src "libresoc.v:45975.3-45983.6" + wire $1\dp_INT_ra_ldst0_8$next[0:0]$2521 + attribute \src "libresoc.v:39495.7-39495.31" wire $1\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45323.3-45331.6" - wire $1\dp_INT_ra_logical0_3$next[0:0]$2474 - attribute \src "libresoc.v:39239.7-39239.34" + attribute \src "libresoc.v:45880.3-45888.6" + wire $1\dp_INT_ra_logical0_3$next[0:0]$2491 + attribute \src "libresoc.v:39499.7-39499.34" wire $1\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45380.3-45388.6" - wire $1\dp_INT_ra_mul0_6$next[0:0]$2492 - attribute \src "libresoc.v:39243.7-39243.30" + attribute \src "libresoc.v:45937.3-45945.6" + wire $1\dp_INT_ra_mul0_6$next[0:0]$2509 + attribute \src "libresoc.v:39503.7-39503.30" wire $1\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45399.3-45407.6" - wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 - attribute \src "libresoc.v:39247.7-39247.35" + attribute \src "libresoc.v:45956.3-45964.6" + wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 + attribute \src "libresoc.v:39507.7-39507.35" wire $1\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45342.3-45350.6" - wire $1\dp_INT_ra_spr0_4$next[0:0]$2480 - attribute \src "libresoc.v:39251.7-39251.30" + attribute \src "libresoc.v:45899.3-45907.6" + wire $1\dp_INT_ra_spr0_4$next[0:0]$2497 + attribute \src "libresoc.v:39511.7-39511.30" wire $1\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45304.3-45312.6" - wire $1\dp_INT_ra_trap0_2$next[0:0]$2468 - attribute \src "libresoc.v:39255.7-39255.31" + attribute \src "libresoc.v:45861.3-45869.6" + wire $1\dp_INT_ra_trap0_2$next[0:0]$2485 + attribute \src "libresoc.v:39515.7-39515.31" wire $1\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45437.3-45445.6" - wire $1\dp_INT_rb_alu0_0$next[0:0]$2510 - attribute \src "libresoc.v:39259.7-39259.30" + attribute \src "libresoc.v:45994.3-46002.6" + wire $1\dp_INT_rb_alu0_0$next[0:0]$2527 + attribute \src "libresoc.v:39519.7-39519.30" wire $1\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:45456.3-45464.6" - wire $1\dp_INT_rb_cr0_1$next[0:0]$2514 - attribute \src "libresoc.v:39263.7-39263.29" + attribute \src "libresoc.v:46013.3-46021.6" + wire $1\dp_INT_rb_cr0_1$next[0:0]$2531 + attribute \src "libresoc.v:39523.7-39523.29" wire $1\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:45513.3-45521.6" - wire $1\dp_INT_rb_div0_4$next[0:0]$2532 - attribute \src "libresoc.v:39267.7-39267.30" + attribute \src "libresoc.v:46070.3-46078.6" + wire $1\dp_INT_rb_div0_4$next[0:0]$2549 + attribute \src "libresoc.v:39527.7-39527.30" wire $1\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:45570.3-45578.6" - wire $1\dp_INT_rb_ldst0_7$next[0:0]$2550 - attribute \src "libresoc.v:39271.7-39271.31" + attribute \src "libresoc.v:46127.3-46135.6" + wire $1\dp_INT_rb_ldst0_7$next[0:0]$2567 + attribute \src "libresoc.v:39531.7-39531.31" wire $1\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:45494.3-45502.6" - wire $1\dp_INT_rb_logical0_3$next[0:0]$2526 - attribute \src "libresoc.v:39275.7-39275.34" + attribute \src "libresoc.v:46051.3-46059.6" + wire $1\dp_INT_rb_logical0_3$next[0:0]$2543 + attribute \src "libresoc.v:39535.7-39535.34" wire $1\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:45532.3-45540.6" - wire $1\dp_INT_rb_mul0_5$next[0:0]$2538 - attribute \src "libresoc.v:39279.7-39279.30" + attribute \src "libresoc.v:46089.3-46097.6" + wire $1\dp_INT_rb_mul0_5$next[0:0]$2555 + attribute \src "libresoc.v:39539.7-39539.30" wire $1\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:45551.3-45559.6" - wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 - attribute \src "libresoc.v:39283.7-39283.35" + attribute \src "libresoc.v:46108.3-46116.6" + wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 + attribute \src "libresoc.v:39543.7-39543.35" wire $1\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:45475.3-45483.6" - wire $1\dp_INT_rb_trap0_2$next[0:0]$2520 - attribute \src "libresoc.v:39287.7-39287.31" + attribute \src "libresoc.v:46032.3-46040.6" + wire $1\dp_INT_rb_trap0_2$next[0:0]$2537 + attribute \src "libresoc.v:39547.7-39547.31" wire $1\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:45608.3-45616.6" - wire $1\dp_INT_rc_ldst0_1$next[0:0]$2560 - attribute \src "libresoc.v:39291.7-39291.31" + attribute \src "libresoc.v:46165.3-46173.6" + wire $1\dp_INT_rc_ldst0_1$next[0:0]$2577 + attribute \src "libresoc.v:39551.7-39551.31" wire $1\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:45589.3-45597.6" - wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 - attribute \src "libresoc.v:39295.7-39295.35" + attribute \src "libresoc.v:46146.3-46154.6" + wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 + attribute \src "libresoc.v:39555.7-39555.35" wire $1\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46381.3-46389.6" - wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 - attribute \src "libresoc.v:39299.7-39299.32" + attribute \src "libresoc.v:46791.3-46799.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 + attribute \src "libresoc.v:39559.7-39559.32" wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45909.3-45917.6" - wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 - attribute \src "libresoc.v:39303.7-39303.34" + attribute \src "libresoc.v:46298.3-46306.6" + wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 + attribute \src "libresoc.v:39563.7-39563.34" wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45976.3-45984.6" - wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 - attribute \src "libresoc.v:39307.7-39307.39" + attribute \src "libresoc.v:46336.3-46344.6" + wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 + attribute \src "libresoc.v:39567.7-39567.39" wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45957.3-45965.6" - wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 - attribute \src "libresoc.v:39311.7-39311.34" + attribute \src "libresoc.v:46317.3-46325.6" + wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 + attribute \src "libresoc.v:39571.7-39571.34" wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46025.3-46033.6" - wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 - attribute \src "libresoc.v:39315.7-39315.34" + attribute \src "libresoc.v:46355.3-46363.6" + wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 + attribute \src "libresoc.v:39575.7-39575.34" wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:45654.3-45662.6" - wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 - attribute \src "libresoc.v:39319.7-39319.34" + attribute \src "libresoc.v:46184.3-46192.6" + wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 + attribute \src "libresoc.v:39579.7-39579.34" wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45823.3-45831.6" - wire $1\dp_XER_xer_so_div0_3$next[0:0]$2594 - attribute \src "libresoc.v:39323.7-39323.34" + attribute \src "libresoc.v:46241.3-46249.6" + wire $1\dp_XER_xer_so_div0_3$next[0:0]$2599 + attribute \src "libresoc.v:39583.7-39583.34" wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:45764.3-45772.6" - wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 - attribute \src "libresoc.v:39327.7-39327.38" + attribute \src "libresoc.v:46203.3-46211.6" + wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 + attribute \src "libresoc.v:39587.7-39587.38" wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45842.3-45850.6" - wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 - attribute \src "libresoc.v:39331.7-39331.34" + attribute \src "libresoc.v:46260.3-46268.6" + wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 + attribute \src "libresoc.v:39591.7-39591.34" wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45890.3-45898.6" - wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 - attribute \src "libresoc.v:39335.7-39335.39" + attribute \src "libresoc.v:46279.3-46287.6" + wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + attribute \src "libresoc.v:39595.7-39595.39" wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:45783.3-45791.6" - wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 - attribute \src "libresoc.v:39339.7-39339.34" + attribute \src "libresoc.v:46222.3-46230.6" + wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 + attribute \src "libresoc.v:39599.7-39599.34" wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46901.3-46929.6" - wire $1\fus_cu_issue_i$13[0:0]$2769 - attribute \src "libresoc.v:47298.3-47326.6" - wire $1\fus_cu_issue_i$16[0:0]$2831 - attribute \src "libresoc.v:47662.3-47690.6" - wire $1\fus_cu_issue_i$19[0:0]$2865 - attribute \src "libresoc.v:48158.3-48186.6" - wire $1\fus_cu_issue_i$22[0:0]$2890 - attribute \src "libresoc.v:43485.3-43513.6" - wire $1\fus_cu_issue_i$25[0:0]$2357 - attribute \src "libresoc.v:43981.3-44009.6" - wire $1\fus_cu_issue_i$28[0:0]$2382 - attribute \src "libresoc.v:44303.3-44331.6" - wire $1\fus_cu_issue_i$31[0:0]$2401 - attribute \src "libresoc.v:44770.3-44798.6" - wire $1\fus_cu_issue_i$34[0:0]$2425 - attribute \src "libresoc.v:45208.3-45236.6" - wire $1\fus_cu_issue_i$37[0:0]$2448 - attribute \src "libresoc.v:46693.3-46721.6" + attribute \src "libresoc.v:47566.3-47594.6" + wire $1\fus_cu_issue_i$13[0:0]$2822 + attribute \src "libresoc.v:47900.3-47928.6" + wire $1\fus_cu_issue_i$16[0:0]$2863 + attribute \src "libresoc.v:48219.3-48247.6" + wire $1\fus_cu_issue_i$19[0:0]$2882 + attribute \src "libresoc.v:43868.3-43896.6" + wire $1\fus_cu_issue_i$22[0:0]$2360 + attribute \src "libresoc.v:44042.3-44070.6" + wire $1\fus_cu_issue_i$25[0:0]$2374 + attribute \src "libresoc.v:44538.3-44566.6" + wire $1\fus_cu_issue_i$28[0:0]$2399 + attribute \src "libresoc.v:44860.3-44888.6" + wire $1\fus_cu_issue_i$31[0:0]$2418 + attribute \src "libresoc.v:45327.3-45355.6" + wire $1\fus_cu_issue_i$34[0:0]$2442 + attribute \src "libresoc.v:45765.3-45793.6" + wire $1\fus_cu_issue_i$37[0:0]$2465 + attribute \src "libresoc.v:47349.3-47377.6" wire $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46939.3-46967.6" - wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2777 - attribute \src "libresoc.v:47336.3-47364.6" - wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2839 - attribute \src "libresoc.v:47691.3-47719.6" - wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2870 - attribute \src "libresoc.v:48187.3-48215.6" - wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2895 - attribute \src "libresoc.v:43514.3-43542.6" - wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2362 - attribute \src "libresoc.v:44010.3-44038.6" - wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2387 - attribute \src "libresoc.v:44332.3-44360.6" - wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2406 - attribute \src "libresoc.v:44799.3-44827.6" - wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2430 - attribute \src "libresoc.v:45237.3-45265.6" - wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2453 - attribute \src "libresoc.v:46731.3-46759.6" + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2830 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2868 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2887 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2365 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2379 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2404 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2423 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2447 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2470 + attribute \src "libresoc.v:47396.3-47424.6" wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46608.3-46636.6" + attribute \src "libresoc.v:47273.3-47301.6" wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45918.3-45946.6" - wire width 13 $1\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45985.3-46014.6" + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $1\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45985.3-46014.6" + attribute \src "libresoc.v:46761.3-46790.6" wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46438.3-46466.6" + attribute \src "libresoc.v:47094.3-47122.6" wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46655.3-46683.6" + attribute \src "libresoc.v:47311.3-47339.6" wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45861.3-45889.6" + attribute \src "libresoc.v:46646.3-46674.6" wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46237.3-46265.6" + attribute \src "libresoc.v:46933.3-46961.6" wire $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46352.3-46380.6" + attribute \src "libresoc.v:47018.3-47046.6" wire $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46523.3-46551.6" + attribute \src "libresoc.v:47188.3-47216.6" wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46570.3-46598.6" + attribute \src "libresoc.v:47226.3-47254.6" wire $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46150.3-46179.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46150.3-46179.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46485.3-46513.6" + attribute \src "libresoc.v:47141.3-47169.6" wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46063.3-46092.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46063.3-46092.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46400.3-46428.6" + attribute \src "libresoc.v:47056.3-47084.6" wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46285.3-46313.6" + attribute \src "libresoc.v:46980.3-47008.6" wire $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46986.3-47014.6" + attribute \src "libresoc.v:47651.3-47679.6" wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47071.3-47099.6" - wire width 13 $1\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47156.3-47185.6" + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $1\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47156.3-47185.6" + attribute \src "libresoc.v:47812.3-47841.6" wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47109.3-47137.6" + attribute \src "libresoc.v:47774.3-47802.6" wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47024.3-47052.6" + attribute \src "libresoc.v:47689.3-47717.6" wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47251.3-47279.6" + attribute \src "libresoc.v:47871.3-47899.6" wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47213.3-47241.6" + attribute \src "libresoc.v:47842.3-47870.6" wire $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46816.3-46844.6" - wire width 13 $1\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46863.3-46891.6" + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $1\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46769.3-46797.6" + attribute \src "libresoc.v:47434.3-47462.6" wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43923.3-43951.6" + attribute \src "libresoc.v:44480.3-44508.6" wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43572.3-43600.6" - wire width 13 $1\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43601.3-43630.6" + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $1\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43601.3-43630.6" + attribute \src "libresoc.v:44158.3-44187.6" wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43749.3-43777.6" + attribute \src "libresoc.v:44306.3-44334.6" wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43952.3-43980.6" + attribute \src "libresoc.v:44509.3-44537.6" wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43543.3-43571.6" + attribute \src "libresoc.v:44100.3-44128.6" wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43691.3-43719.6" + attribute \src "libresoc.v:44248.3-44276.6" wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43778.3-43806.6" + attribute \src "libresoc.v:44335.3-44363.6" wire $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43865.3-43893.6" + attribute \src "libresoc.v:44422.3-44450.6" wire $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43894.3-43922.6" + attribute \src "libresoc.v:44451.3-44479.6" wire $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43661.3-43690.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $1\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43661.3-43690.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43836.3-43864.6" + attribute \src "libresoc.v:44393.3-44421.6" wire $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43631.3-43660.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $1\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43631.3-43660.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43807.3-43835.6" + attribute \src "libresoc.v:44364.3-44392.6" wire $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43720.3-43748.6" + attribute \src "libresoc.v:44277.3-44305.6" wire $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48100.3-48128.6" + attribute \src "libresoc.v:43810.3-43838.6" wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47749.3-47777.6" - wire width 13 $1\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47778.3-47807.6" + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $1\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47778.3-47807.6" + attribute \src "libresoc.v:48335.3-48364.6" wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47926.3-47954.6" + attribute \src "libresoc.v:48483.3-48511.6" wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48129.3-48157.6" + attribute \src "libresoc.v:43839.3-43867.6" wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47720.3-47748.6" + attribute \src "libresoc.v:48277.3-48305.6" wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47868.3-47896.6" + attribute \src "libresoc.v:48425.3-48453.6" wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47955.3-47983.6" + attribute \src "libresoc.v:48512.3-48540.6" wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48042.3-48070.6" + attribute \src "libresoc.v:43752.3-43780.6" wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48071.3-48099.6" + attribute \src "libresoc.v:43781.3-43809.6" wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47838.3-47867.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47838.3-47867.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48013.3-48041.6" + attribute \src "libresoc.v:43723.3-43751.6" wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47808.3-47837.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47808.3-47837.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47984.3-48012.6" + attribute \src "libresoc.v:48541.3-48569.6" wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47897.3-47925.6" + attribute \src "libresoc.v:48454.3-48482.6" wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44068.3-44096.6" - wire width 13 $1\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44097.3-44126.6" + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $1\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44097.3-44126.6" + attribute \src "libresoc.v:44654.3-44683.6" wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44274.3-44302.6" + attribute \src "libresoc.v:44831.3-44859.6" wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44039.3-44067.6" + attribute \src "libresoc.v:44596.3-44624.6" wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44216.3-44244.6" + attribute \src "libresoc.v:44773.3-44801.6" wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44245.3-44273.6" + attribute \src "libresoc.v:44802.3-44830.6" wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44157.3-44186.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44157.3-44186.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44127.3-44156.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44127.3-44156.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44187.3-44215.6" + attribute \src "libresoc.v:44744.3-44772.6" wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44390.3-44418.6" - wire width 13 $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44419.3-44448.6" + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44419.3-44448.6" + attribute \src "libresoc.v:44976.3-45005.6" wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:45124.3-45152.6" wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:45182.3-45210.6" wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44741.3-44769.6" + attribute \src "libresoc.v:45298.3-45326.6" wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44361.3-44389.6" + attribute \src "libresoc.v:44918.3-44946.6" wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:45095.3-45123.6" wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44683.3-44711.6" + attribute \src "libresoc.v:45240.3-45268.6" wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44712.3-44740.6" + attribute \src "libresoc.v:45269.3-45297.6" wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44479.3-44508.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44479.3-44508.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:45153.3-45181.6" wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44654.3-44682.6" + attribute \src "libresoc.v:45211.3-45239.6" wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44449.3-44478.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44449.3-44478.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:45066.3-45094.6" wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48245.3-48273.6" - wire width 13 $1\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:43427.3-43455.6" + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $1\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48216.3-48244.6" + attribute \src "libresoc.v:43926.3-43954.6" wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43456.3-43484.6" + attribute \src "libresoc.v:44013.3-44041.6" wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47517.3-47545.6" + attribute \src "libresoc.v:48074.3-48102.6" wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47421.3-47449.6" - wire width 13 $1\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47459.3-47487.6" + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $1\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47374.3-47402.6" + attribute \src "libresoc.v:47958.3-47986.6" wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47546.3-47574.6" + attribute \src "libresoc.v:48103.3-48131.6" wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47633.3-47661.6" + attribute \src "libresoc.v:48190.3-48218.6" wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47488.3-47516.6" + attribute \src "libresoc.v:48045.3-48073.6" wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47604.3-47632.6" + attribute \src "libresoc.v:48161.3-48189.6" wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47575.3-47603.6" + attribute \src "libresoc.v:48132.3-48160.6" wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45092.3-45120.6" + attribute \src "libresoc.v:45649.3-45677.6" wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45063.3-45091.6" + attribute \src "libresoc.v:45620.3-45648.6" wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44857.3-44885.6" - wire width 13 $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44886.3-44915.6" + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44886.3-44915.6" + attribute \src "libresoc.v:45443.3-45472.6" wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45179.3-45207.6" + attribute \src "libresoc.v:45736.3-45764.6" wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44828.3-44856.6" + attribute \src "libresoc.v:45385.3-45413.6" wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45005.3-45033.6" + attribute \src "libresoc.v:45562.3-45590.6" wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45034.3-45062.6" + attribute \src "libresoc.v:45591.3-45619.6" wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45150.3-45178.6" + attribute \src "libresoc.v:45707.3-45735.6" wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44975.3-45004.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44975.3-45004.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44945.3-44974.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44945.3-44974.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45121.3-45149.6" + attribute \src "libresoc.v:45678.3-45706.6" wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44916.3-44944.6" + attribute \src "libresoc.v:45473.3-45501.6" wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45294.3-45303.6" - wire width 64 $1\fus_src1_i$42[63:0]$2465 - attribute \src "libresoc.v:45313.3-45322.6" - wire width 64 $1\fus_src1_i$45[63:0]$2471 - attribute \src "libresoc.v:45332.3-45341.6" - wire width 64 $1\fus_src1_i$48[63:0]$2477 - attribute \src "libresoc.v:45351.3-45360.6" - wire width 64 $1\fus_src1_i$51[63:0]$2483 - attribute \src "libresoc.v:45370.3-45379.6" - wire width 64 $1\fus_src1_i$54[63:0]$2489 - attribute \src "libresoc.v:45389.3-45398.6" - wire width 64 $1\fus_src1_i$57[63:0]$2495 - attribute \src "libresoc.v:45408.3-45417.6" - wire width 64 $1\fus_src1_i$60[63:0]$2501 - attribute \src "libresoc.v:45427.3-45436.6" - wire width 64 $1\fus_src1_i$63[63:0]$2507 - attribute \src "libresoc.v:46208.3-46217.6" - wire width 64 $1\fus_src1_i$86[63:0]$2670 - attribute \src "libresoc.v:45275.3-45284.6" + attribute \src "libresoc.v:45851.3-45860.6" + wire width 64 $1\fus_src1_i$42[63:0]$2482 + attribute \src "libresoc.v:45870.3-45879.6" + wire width 64 $1\fus_src1_i$45[63:0]$2488 + attribute \src "libresoc.v:45889.3-45898.6" + wire width 64 $1\fus_src1_i$48[63:0]$2494 + attribute \src "libresoc.v:45908.3-45917.6" + wire width 64 $1\fus_src1_i$51[63:0]$2500 + attribute \src "libresoc.v:45927.3-45936.6" + wire width 64 $1\fus_src1_i$54[63:0]$2506 + attribute \src "libresoc.v:45946.3-45955.6" + wire width 64 $1\fus_src1_i$57[63:0]$2512 + attribute \src "libresoc.v:45965.3-45974.6" + wire width 64 $1\fus_src1_i$60[63:0]$2518 + attribute \src "libresoc.v:45984.3-45993.6" + wire width 64 $1\fus_src1_i$63[63:0]$2524 + attribute \src "libresoc.v:46617.3-46626.6" + wire width 64 $1\fus_src1_i$86[63:0]$2682 + attribute \src "libresoc.v:45832.3-45841.6" wire width 64 $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45465.3-45474.6" - wire width 64 $1\fus_src2_i$64[63:0]$2517 - attribute \src "libresoc.v:45484.3-45493.6" - wire width 64 $1\fus_src2_i$65[63:0]$2523 - attribute \src "libresoc.v:45503.3-45512.6" - wire width 64 $1\fus_src2_i$66[63:0]$2529 - attribute \src "libresoc.v:45522.3-45531.6" - wire width 64 $1\fus_src2_i$67[63:0]$2535 - attribute \src "libresoc.v:45541.3-45550.6" - wire width 64 $1\fus_src2_i$68[63:0]$2541 - attribute \src "libresoc.v:45560.3-45569.6" - wire width 64 $1\fus_src2_i$69[63:0]$2547 - attribute \src "libresoc.v:45579.3-45588.6" - wire width 64 $1\fus_src2_i$70[63:0]$2553 - attribute \src "libresoc.v:46323.3-46332.6" - wire width 64 $1\fus_src2_i$89[63:0]$2690 - attribute \src "libresoc.v:46390.3-46399.6" - wire width 64 $1\fus_src2_i$91[63:0]$2703 - attribute \src "libresoc.v:45446.3-45455.6" + attribute \src "libresoc.v:46022.3-46031.6" + wire width 64 $1\fus_src2_i$64[63:0]$2534 + attribute \src "libresoc.v:46041.3-46050.6" + wire width 64 $1\fus_src2_i$65[63:0]$2540 + attribute \src "libresoc.v:46060.3-46069.6" + wire width 64 $1\fus_src2_i$66[63:0]$2546 + attribute \src "libresoc.v:46079.3-46088.6" + wire width 64 $1\fus_src2_i$67[63:0]$2552 + attribute \src "libresoc.v:46098.3-46107.6" + wire width 64 $1\fus_src2_i$68[63:0]$2558 + attribute \src "libresoc.v:46117.3-46126.6" + wire width 64 $1\fus_src2_i$69[63:0]$2564 + attribute \src "libresoc.v:46136.3-46145.6" + wire width 64 $1\fus_src2_i$70[63:0]$2570 + attribute \src "libresoc.v:46732.3-46741.6" + wire width 64 $1\fus_src2_i$89[63:0]$2702 + attribute \src "libresoc.v:46800.3-46809.6" + wire width 64 $1\fus_src2_i$91[63:0]$2715 + attribute \src "libresoc.v:46003.3-46012.6" wire width 64 $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45617.3-45626.6" - wire width 64 $1\fus_src3_i$71[63:0]$2563 - attribute \src "libresoc.v:45663.3-45672.6" - wire $1\fus_src3_i$72[0:0]$2575 - attribute \src "libresoc.v:45773.3-45782.6" - wire $1\fus_src3_i$73[0:0]$2582 - attribute \src "libresoc.v:45832.3-45841.6" - wire $1\fus_src3_i$74[0:0]$2597 - attribute \src "libresoc.v:45851.3-45860.6" - wire $1\fus_src3_i$75[0:0]$2603 - attribute \src "libresoc.v:46053.3-46062.6" - wire width 32 $1\fus_src3_i$79[31:0]$2638 - attribute \src "libresoc.v:46121.3-46130.6" - wire width 4 $1\fus_src3_i$83[3:0]$2651 - attribute \src "libresoc.v:46227.3-46236.6" - wire width 64 $1\fus_src3_i$87[63:0]$2676 - attribute \src "libresoc.v:46275.3-46284.6" - wire width 64 $1\fus_src3_i$88[63:0]$2683 - attribute \src "libresoc.v:45598.3-45607.6" + attribute \src "libresoc.v:46174.3-46183.6" + wire width 64 $1\fus_src3_i$71[63:0]$2580 + attribute \src "libresoc.v:46193.3-46202.6" + wire $1\fus_src3_i$72[0:0]$2586 + attribute \src "libresoc.v:46212.3-46221.6" + wire $1\fus_src3_i$73[0:0]$2592 + attribute \src "libresoc.v:46250.3-46259.6" + wire $1\fus_src3_i$74[0:0]$2602 + attribute \src "libresoc.v:46269.3-46278.6" + wire $1\fus_src3_i$75[0:0]$2608 + attribute \src "libresoc.v:46383.3-46392.6" + wire width 32 $1\fus_src3_i$79[31:0]$2640 + attribute \src "libresoc.v:46421.3-46430.6" + wire width 4 $1\fus_src3_i$83[3:0]$2652 + attribute \src "libresoc.v:46636.3-46645.6" + wire width 64 $1\fus_src3_i$87[63:0]$2688 + attribute \src "libresoc.v:46684.3-46693.6" + wire width 64 $1\fus_src3_i$88[63:0]$2695 + attribute \src "libresoc.v:46155.3-46164.6" wire width 64 $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45899.3-45908.6" - wire $1\fus_src4_i$76[0:0]$2610 - attribute \src "libresoc.v:45947.3-45956.6" - wire width 2 $1\fus_src4_i$77[1:0]$2617 - attribute \src "libresoc.v:46102.3-46111.6" - wire width 4 $1\fus_src4_i$80[3:0]$2645 - attribute \src "libresoc.v:46342.3-46351.6" - wire width 64 $1\fus_src4_i$90[63:0]$2696 - attribute \src "libresoc.v:45792.3-45801.6" + attribute \src "libresoc.v:46288.3-46297.6" + wire $1\fus_src4_i$76[0:0]$2614 + attribute \src "libresoc.v:46307.3-46316.6" + wire width 2 $1\fus_src4_i$77[1:0]$2620 + attribute \src "libresoc.v:46402.3-46411.6" + wire width 4 $1\fus_src4_i$80[3:0]$2646 + attribute \src "libresoc.v:46751.3-46760.6" + wire width 64 $1\fus_src4_i$90[63:0]$2708 + attribute \src "libresoc.v:46231.3-46240.6" wire $1\fus_src4_i[0:0] - attribute \src "libresoc.v:46034.3-46043.6" - wire width 2 $1\fus_src5_i$78[1:0]$2632 - attribute \src "libresoc.v:46140.3-46149.6" - wire width 4 $1\fus_src5_i$84[3:0]$2657 - attribute \src "libresoc.v:46015.3-46024.6" + attribute \src "libresoc.v:46364.3-46373.6" + wire width 2 $1\fus_src5_i$78[1:0]$2634 + attribute \src "libresoc.v:46467.3-46476.6" + wire width 4 $1\fus_src5_i$84[3:0]$2664 + attribute \src "libresoc.v:46345.3-46354.6" wire width 2 $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46189.3-46198.6" - wire width 4 $1\fus_src6_i$85[3:0]$2664 - attribute \src "libresoc.v:45966.3-45975.6" + attribute \src "libresoc.v:46577.3-46586.6" + wire width 4 $1\fus_src6_i$85[3:0]$2671 + attribute \src "libresoc.v:46326.3-46335.6" wire width 2 $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46476.3-46484.6" - wire $1\wr_pick_dly$1005$next[0:0]$2714 - attribute \src "libresoc.v:46514.3-46522.6" - wire $1\wr_pick_dly$1026$next[0:0]$2718 - attribute \src "libresoc.v:46552.3-46560.6" - wire $1\wr_pick_dly$1044$next[0:0]$2722 - attribute \src "libresoc.v:46561.3-46569.6" - wire $1\wr_pick_dly$1066$next[0:0]$2725 - attribute \src "libresoc.v:46599.3-46607.6" - wire $1\wr_pick_dly$1086$next[0:0]$2729 - attribute \src "libresoc.v:46637.3-46645.6" - wire $1\wr_pick_dly$1106$next[0:0]$2733 - attribute \src "libresoc.v:46646.3-46654.6" - wire $1\wr_pick_dly$1125$next[0:0]$2736 - attribute \src "libresoc.v:46684.3-46692.6" - wire $1\wr_pick_dly$1143$next[0:0]$2740 - attribute \src "libresoc.v:46722.3-46730.6" - wire $1\wr_pick_dly$1217$next[0:0]$2744 - attribute \src "libresoc.v:46760.3-46768.6" - wire $1\wr_pick_dly$1245$next[0:0]$2748 - attribute \src "libresoc.v:46798.3-46806.6" - wire $1\wr_pick_dly$1265$next[0:0]$2752 - attribute \src "libresoc.v:46807.3-46815.6" - wire $1\wr_pick_dly$1285$next[0:0]$2755 - attribute \src "libresoc.v:46845.3-46853.6" - wire $1\wr_pick_dly$1305$next[0:0]$2759 - attribute \src "libresoc.v:46854.3-46862.6" - wire $1\wr_pick_dly$1325$next[0:0]$2762 - attribute \src "libresoc.v:46892.3-46900.6" - wire $1\wr_pick_dly$1345$next[0:0]$2766 - attribute \src "libresoc.v:46930.3-46938.6" - wire $1\wr_pick_dly$1392$next[0:0]$2774 - attribute \src "libresoc.v:46968.3-46976.6" - wire $1\wr_pick_dly$1408$next[0:0]$2782 - attribute \src "libresoc.v:46977.3-46985.6" - wire $1\wr_pick_dly$1424$next[0:0]$2785 - attribute \src "libresoc.v:47015.3-47023.6" - wire $1\wr_pick_dly$1458$next[0:0]$2789 - attribute \src "libresoc.v:47053.3-47061.6" - wire $1\wr_pick_dly$1474$next[0:0]$2793 - attribute \src "libresoc.v:47062.3-47070.6" - wire $1\wr_pick_dly$1490$next[0:0]$2796 - attribute \src "libresoc.v:47100.3-47108.6" - wire $1\wr_pick_dly$1506$next[0:0]$2800 - attribute \src "libresoc.v:47138.3-47146.6" - wire $1\wr_pick_dly$1542$next[0:0]$2804 - attribute \src "libresoc.v:47147.3-47155.6" - wire $1\wr_pick_dly$1558$next[0:0]$2807 - attribute \src "libresoc.v:47186.3-47194.6" - wire $1\wr_pick_dly$1574$next[0:0]$2811 - attribute \src "libresoc.v:47195.3-47203.6" - wire $1\wr_pick_dly$1590$next[0:0]$2814 - attribute \src "libresoc.v:47204.3-47212.6" - wire $1\wr_pick_dly$1632$next[0:0]$2817 - attribute \src "libresoc.v:47242.3-47250.6" - wire $1\wr_pick_dly$1651$next[0:0]$2821 - attribute \src "libresoc.v:47280.3-47288.6" - wire $1\wr_pick_dly$1667$next[0:0]$2825 - attribute \src "libresoc.v:47289.3-47297.6" - wire $1\wr_pick_dly$1683$next[0:0]$2828 - attribute \src "libresoc.v:47327.3-47335.6" - wire $1\wr_pick_dly$1699$next[0:0]$2836 - attribute \src "libresoc.v:47365.3-47373.6" - wire $1\wr_pick_dly$1743$next[0:0]$2844 - attribute \src "libresoc.v:47403.3-47411.6" - wire $1\wr_pick_dly$1759$next[0:0]$2848 - attribute \src "libresoc.v:47412.3-47420.6" - wire $1\wr_pick_dly$1783$next[0:0]$2851 - attribute \src "libresoc.v:47450.3-47458.6" - wire $1\wr_pick_dly$1803$next[0:0]$2855 - attribute \src "libresoc.v:46467.3-46475.6" - wire $1\wr_pick_dly$986$next[0:0]$2711 - attribute \src "libresoc.v:46429.3-46437.6" - wire $1\wr_pick_dly$next[0:0]$2707 - attribute \src "libresoc.v:41432.7-41432.25" + attribute \src "libresoc.v:46858.3-46866.6" + wire $1\wr_pick_dly$1010$next[0:0]$2725 + attribute \src "libresoc.v:46867.3-46875.6" + wire $1\wr_pick_dly$1031$next[0:0]$2728 + attribute \src "libresoc.v:46906.3-46914.6" + wire $1\wr_pick_dly$1049$next[0:0]$2732 + attribute \src "libresoc.v:46915.3-46923.6" + wire $1\wr_pick_dly$1071$next[0:0]$2735 + attribute \src "libresoc.v:46924.3-46932.6" + wire $1\wr_pick_dly$1091$next[0:0]$2738 + attribute \src "libresoc.v:46962.3-46970.6" + wire $1\wr_pick_dly$1111$next[0:0]$2742 + attribute \src "libresoc.v:46971.3-46979.6" + wire $1\wr_pick_dly$1130$next[0:0]$2745 + attribute \src "libresoc.v:47009.3-47017.6" + wire $1\wr_pick_dly$1148$next[0:0]$2749 + attribute \src "libresoc.v:47047.3-47055.6" + wire $1\wr_pick_dly$1222$next[0:0]$2753 + attribute \src "libresoc.v:47085.3-47093.6" + wire $1\wr_pick_dly$1250$next[0:0]$2757 + attribute \src "libresoc.v:47123.3-47131.6" + wire $1\wr_pick_dly$1270$next[0:0]$2761 + attribute \src "libresoc.v:47132.3-47140.6" + wire $1\wr_pick_dly$1290$next[0:0]$2764 + attribute \src "libresoc.v:47170.3-47178.6" + wire $1\wr_pick_dly$1310$next[0:0]$2768 + attribute \src "libresoc.v:47179.3-47187.6" + wire $1\wr_pick_dly$1330$next[0:0]$2771 + attribute \src "libresoc.v:47217.3-47225.6" + wire $1\wr_pick_dly$1350$next[0:0]$2775 + attribute \src "libresoc.v:47255.3-47263.6" + wire $1\wr_pick_dly$1397$next[0:0]$2779 + attribute \src "libresoc.v:47264.3-47272.6" + wire $1\wr_pick_dly$1413$next[0:0]$2782 + attribute \src "libresoc.v:47302.3-47310.6" + wire $1\wr_pick_dly$1429$next[0:0]$2786 + attribute \src "libresoc.v:47340.3-47348.6" + wire $1\wr_pick_dly$1463$next[0:0]$2790 + attribute \src "libresoc.v:47378.3-47386.6" + wire $1\wr_pick_dly$1479$next[0:0]$2794 + attribute \src "libresoc.v:47387.3-47395.6" + wire $1\wr_pick_dly$1495$next[0:0]$2797 + attribute \src "libresoc.v:47425.3-47433.6" + wire $1\wr_pick_dly$1511$next[0:0]$2801 + attribute \src "libresoc.v:47463.3-47471.6" + wire $1\wr_pick_dly$1547$next[0:0]$2805 + attribute \src "libresoc.v:47472.3-47480.6" + wire $1\wr_pick_dly$1563$next[0:0]$2808 + attribute \src "libresoc.v:47510.3-47518.6" + wire $1\wr_pick_dly$1579$next[0:0]$2812 + attribute \src "libresoc.v:47519.3-47527.6" + wire $1\wr_pick_dly$1595$next[0:0]$2815 + attribute \src "libresoc.v:47557.3-47565.6" + wire $1\wr_pick_dly$1637$next[0:0]$2819 + attribute \src "libresoc.v:47595.3-47603.6" + wire $1\wr_pick_dly$1656$next[0:0]$2827 + attribute \src "libresoc.v:47633.3-47641.6" + wire $1\wr_pick_dly$1672$next[0:0]$2835 + attribute \src "libresoc.v:47642.3-47650.6" + wire $1\wr_pick_dly$1688$next[0:0]$2838 + attribute \src "libresoc.v:47680.3-47688.6" + wire $1\wr_pick_dly$1704$next[0:0]$2842 + attribute \src "libresoc.v:47718.3-47726.6" + wire $1\wr_pick_dly$1748$next[0:0]$2846 + attribute \src "libresoc.v:47727.3-47735.6" + wire $1\wr_pick_dly$1764$next[0:0]$2849 + attribute \src "libresoc.v:47765.3-47773.6" + wire $1\wr_pick_dly$1788$next[0:0]$2853 + attribute \src "libresoc.v:47803.3-47811.6" + wire $1\wr_pick_dly$1808$next[0:0]$2857 + attribute \src "libresoc.v:46819.3-46827.6" + wire $1\wr_pick_dly$991$next[0:0]$2721 + attribute \src "libresoc.v:46810.3-46818.6" + wire $1\wr_pick_dly$next[0:0]$2718 + attribute \src "libresoc.v:41724.7-41724.25" wire $1\wr_pick_dly[0:0] - attribute \src "libresoc.v:45802.3-45822.6" - wire $2\core_terminate_o$next[0:0]$2590 - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46587.3-46607.6" + wire $2\core_terminate_o$next[0:0]$2675 + attribute \src "libresoc.v:46477.3-46567.6" wire $2\corebusy_o[0:0] - attribute \src "libresoc.v:45627.3-45653.6" - wire width 2 $2\counter$next[1:0]$2567 - attribute \src "libresoc.v:46901.3-46929.6" - wire $2\fus_cu_issue_i$13[0:0]$2770 - attribute \src "libresoc.v:47298.3-47326.6" - wire $2\fus_cu_issue_i$16[0:0]$2832 - attribute \src "libresoc.v:47662.3-47690.6" - wire $2\fus_cu_issue_i$19[0:0]$2866 - attribute \src "libresoc.v:48158.3-48186.6" - wire $2\fus_cu_issue_i$22[0:0]$2891 - attribute \src "libresoc.v:43485.3-43513.6" - wire $2\fus_cu_issue_i$25[0:0]$2358 - attribute \src "libresoc.v:43981.3-44009.6" - wire $2\fus_cu_issue_i$28[0:0]$2383 - attribute \src "libresoc.v:44303.3-44331.6" - wire $2\fus_cu_issue_i$31[0:0]$2402 - attribute \src "libresoc.v:44770.3-44798.6" - wire $2\fus_cu_issue_i$34[0:0]$2426 - attribute \src "libresoc.v:45208.3-45236.6" - wire $2\fus_cu_issue_i$37[0:0]$2449 - attribute \src "libresoc.v:46693.3-46721.6" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $2\counter$next[1:0]$2656 + attribute \src "libresoc.v:47566.3-47594.6" + wire $2\fus_cu_issue_i$13[0:0]$2823 + attribute \src "libresoc.v:47900.3-47928.6" + wire $2\fus_cu_issue_i$16[0:0]$2864 + attribute \src "libresoc.v:48219.3-48247.6" + wire $2\fus_cu_issue_i$19[0:0]$2883 + attribute \src "libresoc.v:43868.3-43896.6" + wire $2\fus_cu_issue_i$22[0:0]$2361 + attribute \src "libresoc.v:44042.3-44070.6" + wire $2\fus_cu_issue_i$25[0:0]$2375 + attribute \src "libresoc.v:44538.3-44566.6" + wire $2\fus_cu_issue_i$28[0:0]$2400 + attribute \src "libresoc.v:44860.3-44888.6" + wire $2\fus_cu_issue_i$31[0:0]$2419 + attribute \src "libresoc.v:45327.3-45355.6" + wire $2\fus_cu_issue_i$34[0:0]$2443 + attribute \src "libresoc.v:45765.3-45793.6" + wire $2\fus_cu_issue_i$37[0:0]$2466 + attribute \src "libresoc.v:47349.3-47377.6" wire $2\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46939.3-46967.6" - wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2778 - attribute \src "libresoc.v:47336.3-47364.6" - wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2840 - attribute \src "libresoc.v:47691.3-47719.6" - wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2871 - attribute \src "libresoc.v:48187.3-48215.6" - wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2896 - attribute \src "libresoc.v:43514.3-43542.6" - wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2363 - attribute \src "libresoc.v:44010.3-44038.6" - wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2388 - attribute \src "libresoc.v:44332.3-44360.6" - wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2407 - attribute \src "libresoc.v:44799.3-44827.6" - wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2431 - attribute \src "libresoc.v:45237.3-45265.6" - wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2454 - attribute \src "libresoc.v:46731.3-46759.6" + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2831 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2869 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2888 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2366 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2380 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2405 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2424 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2448 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2471 + attribute \src "libresoc.v:47396.3-47424.6" wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46608.3-46636.6" + attribute \src "libresoc.v:47273.3-47301.6" wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45918.3-45946.6" - wire width 13 $2\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45985.3-46014.6" + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $2\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45985.3-46014.6" + attribute \src "libresoc.v:46761.3-46790.6" wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46438.3-46466.6" + attribute \src "libresoc.v:47094.3-47122.6" wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46655.3-46683.6" + attribute \src "libresoc.v:47311.3-47339.6" wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45861.3-45889.6" + attribute \src "libresoc.v:46646.3-46674.6" wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46237.3-46265.6" + attribute \src "libresoc.v:46933.3-46961.6" wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46352.3-46380.6" + attribute \src "libresoc.v:47018.3-47046.6" wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46523.3-46551.6" + attribute \src "libresoc.v:47188.3-47216.6" wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46570.3-46598.6" + attribute \src "libresoc.v:47226.3-47254.6" wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46150.3-46179.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46150.3-46179.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46485.3-46513.6" + attribute \src "libresoc.v:47141.3-47169.6" wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46063.3-46092.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46063.3-46092.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46400.3-46428.6" + attribute \src "libresoc.v:47056.3-47084.6" wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46285.3-46313.6" + attribute \src "libresoc.v:46980.3-47008.6" wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46986.3-47014.6" + attribute \src "libresoc.v:47651.3-47679.6" wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47071.3-47099.6" - wire width 13 $2\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47156.3-47185.6" + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $2\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47156.3-47185.6" + attribute \src "libresoc.v:47812.3-47841.6" wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47109.3-47137.6" + attribute \src "libresoc.v:47774.3-47802.6" wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47024.3-47052.6" + attribute \src "libresoc.v:47689.3-47717.6" wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47251.3-47279.6" + attribute \src "libresoc.v:47871.3-47899.6" wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47213.3-47241.6" + attribute \src "libresoc.v:47842.3-47870.6" wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46816.3-46844.6" - wire width 13 $2\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46863.3-46891.6" + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $2\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46769.3-46797.6" + attribute \src "libresoc.v:47434.3-47462.6" wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43923.3-43951.6" + attribute \src "libresoc.v:44480.3-44508.6" wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43572.3-43600.6" - wire width 13 $2\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43601.3-43630.6" + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $2\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43601.3-43630.6" + attribute \src "libresoc.v:44158.3-44187.6" wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43749.3-43777.6" + attribute \src "libresoc.v:44306.3-44334.6" wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43952.3-43980.6" + attribute \src "libresoc.v:44509.3-44537.6" wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43543.3-43571.6" + attribute \src "libresoc.v:44100.3-44128.6" wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43691.3-43719.6" + attribute \src "libresoc.v:44248.3-44276.6" wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43778.3-43806.6" + attribute \src "libresoc.v:44335.3-44363.6" wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43865.3-43893.6" + attribute \src "libresoc.v:44422.3-44450.6" wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43894.3-43922.6" + attribute \src "libresoc.v:44451.3-44479.6" wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43661.3-43690.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43661.3-43690.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43836.3-43864.6" + attribute \src "libresoc.v:44393.3-44421.6" wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43631.3-43660.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $2\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43631.3-43660.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43807.3-43835.6" + attribute \src "libresoc.v:44364.3-44392.6" wire $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43720.3-43748.6" + attribute \src "libresoc.v:44277.3-44305.6" wire $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48100.3-48128.6" + attribute \src "libresoc.v:43810.3-43838.6" wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47749.3-47777.6" - wire width 13 $2\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47778.3-47807.6" + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $2\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47778.3-47807.6" + attribute \src "libresoc.v:48335.3-48364.6" wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47926.3-47954.6" + attribute \src "libresoc.v:48483.3-48511.6" wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48129.3-48157.6" + attribute \src "libresoc.v:43839.3-43867.6" wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47720.3-47748.6" + attribute \src "libresoc.v:48277.3-48305.6" wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47868.3-47896.6" + attribute \src "libresoc.v:48425.3-48453.6" wire $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47955.3-47983.6" + attribute \src "libresoc.v:48512.3-48540.6" wire $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48042.3-48070.6" + attribute \src "libresoc.v:43752.3-43780.6" wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48071.3-48099.6" + attribute \src "libresoc.v:43781.3-43809.6" wire $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47838.3-47867.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47838.3-47867.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48013.3-48041.6" + attribute \src "libresoc.v:43723.3-43751.6" wire $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47808.3-47837.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47808.3-47837.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47984.3-48012.6" + attribute \src "libresoc.v:48541.3-48569.6" wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47897.3-47925.6" + attribute \src "libresoc.v:48454.3-48482.6" wire $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44068.3-44096.6" - wire width 13 $2\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44097.3-44126.6" + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $2\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44097.3-44126.6" + attribute \src "libresoc.v:44654.3-44683.6" wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44274.3-44302.6" + attribute \src "libresoc.v:44831.3-44859.6" wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44039.3-44067.6" + attribute \src "libresoc.v:44596.3-44624.6" wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44216.3-44244.6" + attribute \src "libresoc.v:44773.3-44801.6" wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44245.3-44273.6" + attribute \src "libresoc.v:44802.3-44830.6" wire $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44157.3-44186.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44157.3-44186.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44127.3-44156.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44127.3-44156.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44187.3-44215.6" + attribute \src "libresoc.v:44744.3-44772.6" wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44390.3-44418.6" - wire width 13 $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44419.3-44448.6" + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44419.3-44448.6" + attribute \src "libresoc.v:44976.3-45005.6" wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:45124.3-45152.6" wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:45182.3-45210.6" wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44741.3-44769.6" + attribute \src "libresoc.v:45298.3-45326.6" wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44361.3-44389.6" + attribute \src "libresoc.v:44918.3-44946.6" wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:45095.3-45123.6" wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44683.3-44711.6" + attribute \src "libresoc.v:45240.3-45268.6" wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44712.3-44740.6" + attribute \src "libresoc.v:45269.3-45297.6" wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44479.3-44508.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44479.3-44508.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:45153.3-45181.6" wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44654.3-44682.6" + attribute \src "libresoc.v:45211.3-45239.6" wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44449.3-44478.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44449.3-44478.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:45066.3-45094.6" wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48245.3-48273.6" - wire width 13 $2\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:43427.3-43455.6" + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $2\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48216.3-48244.6" + attribute \src "libresoc.v:43926.3-43954.6" wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43456.3-43484.6" + attribute \src "libresoc.v:44013.3-44041.6" wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47517.3-47545.6" + attribute \src "libresoc.v:48074.3-48102.6" wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47421.3-47449.6" - wire width 13 $2\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47459.3-47487.6" + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $2\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47374.3-47402.6" + attribute \src "libresoc.v:47958.3-47986.6" wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47546.3-47574.6" + attribute \src "libresoc.v:48103.3-48131.6" wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47633.3-47661.6" + attribute \src "libresoc.v:48190.3-48218.6" wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47488.3-47516.6" + attribute \src "libresoc.v:48045.3-48073.6" wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47604.3-47632.6" + attribute \src "libresoc.v:48161.3-48189.6" wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47575.3-47603.6" + attribute \src "libresoc.v:48132.3-48160.6" wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45092.3-45120.6" + attribute \src "libresoc.v:45649.3-45677.6" wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45063.3-45091.6" + attribute \src "libresoc.v:45620.3-45648.6" wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44857.3-44885.6" - wire width 13 $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44886.3-44915.6" + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44886.3-44915.6" + attribute \src "libresoc.v:45443.3-45472.6" wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45179.3-45207.6" + attribute \src "libresoc.v:45736.3-45764.6" wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44828.3-44856.6" + attribute \src "libresoc.v:45385.3-45413.6" wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45005.3-45033.6" + attribute \src "libresoc.v:45562.3-45590.6" wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45034.3-45062.6" + attribute \src "libresoc.v:45591.3-45619.6" wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45150.3-45178.6" + attribute \src "libresoc.v:45707.3-45735.6" wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44975.3-45004.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44975.3-45004.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44945.3-44974.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44945.3-44974.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45121.3-45149.6" + attribute \src "libresoc.v:45678.3-45706.6" wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44916.3-44944.6" + attribute \src "libresoc.v:45473.3-45501.6" wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45802.3-45822.6" - wire $3\core_terminate_o$next[0:0]$2591 - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46587.3-46607.6" + wire $3\core_terminate_o$next[0:0]$2676 + attribute \src "libresoc.v:46477.3-46567.6" wire $3\corebusy_o[0:0] - attribute \src "libresoc.v:45627.3-45653.6" - wire width 2 $3\counter$next[1:0]$2568 - attribute \src "libresoc.v:46901.3-46929.6" - wire $3\fus_cu_issue_i$13[0:0]$2771 - attribute \src "libresoc.v:47298.3-47326.6" - wire $3\fus_cu_issue_i$16[0:0]$2833 - attribute \src "libresoc.v:47662.3-47690.6" - wire $3\fus_cu_issue_i$19[0:0]$2867 - attribute \src "libresoc.v:48158.3-48186.6" - wire $3\fus_cu_issue_i$22[0:0]$2892 - attribute \src "libresoc.v:43485.3-43513.6" - wire $3\fus_cu_issue_i$25[0:0]$2359 - attribute \src "libresoc.v:43981.3-44009.6" - wire $3\fus_cu_issue_i$28[0:0]$2384 - attribute \src "libresoc.v:44303.3-44331.6" - wire $3\fus_cu_issue_i$31[0:0]$2403 - attribute \src "libresoc.v:44770.3-44798.6" - wire $3\fus_cu_issue_i$34[0:0]$2427 - attribute \src "libresoc.v:45208.3-45236.6" - wire $3\fus_cu_issue_i$37[0:0]$2450 - attribute \src "libresoc.v:46693.3-46721.6" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $3\counter$next[1:0]$2657 + attribute \src "libresoc.v:47566.3-47594.6" + wire $3\fus_cu_issue_i$13[0:0]$2824 + attribute \src "libresoc.v:47900.3-47928.6" + wire $3\fus_cu_issue_i$16[0:0]$2865 + attribute \src "libresoc.v:48219.3-48247.6" + wire $3\fus_cu_issue_i$19[0:0]$2884 + attribute \src "libresoc.v:43868.3-43896.6" + wire $3\fus_cu_issue_i$22[0:0]$2362 + attribute \src "libresoc.v:44042.3-44070.6" + wire $3\fus_cu_issue_i$25[0:0]$2376 + attribute \src "libresoc.v:44538.3-44566.6" + wire $3\fus_cu_issue_i$28[0:0]$2401 + attribute \src "libresoc.v:44860.3-44888.6" + wire $3\fus_cu_issue_i$31[0:0]$2420 + attribute \src "libresoc.v:45327.3-45355.6" + wire $3\fus_cu_issue_i$34[0:0]$2444 + attribute \src "libresoc.v:45765.3-45793.6" + wire $3\fus_cu_issue_i$37[0:0]$2467 + attribute \src "libresoc.v:47349.3-47377.6" wire $3\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46939.3-46967.6" - wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2779 - attribute \src "libresoc.v:47336.3-47364.6" - wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2841 - attribute \src "libresoc.v:47691.3-47719.6" - wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2872 - attribute \src "libresoc.v:48187.3-48215.6" - wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2897 - attribute \src "libresoc.v:43514.3-43542.6" - wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2364 - attribute \src "libresoc.v:44010.3-44038.6" - wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2389 - attribute \src "libresoc.v:44332.3-44360.6" - wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2408 - attribute \src "libresoc.v:44799.3-44827.6" - wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2432 - attribute \src "libresoc.v:45237.3-45265.6" - wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2455 - attribute \src "libresoc.v:46731.3-46759.6" + attribute \src "libresoc.v:47604.3-47632.6" + wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2832 + attribute \src "libresoc.v:47929.3-47957.6" + wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2870 + attribute \src "libresoc.v:48248.3-48276.6" + wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2889 + attribute \src "libresoc.v:43897.3-43925.6" + wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2367 + attribute \src "libresoc.v:44071.3-44099.6" + wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2381 + attribute \src "libresoc.v:44567.3-44595.6" + wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2406 + attribute \src "libresoc.v:44889.3-44917.6" + wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2425 + attribute \src "libresoc.v:45356.3-45384.6" + wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2449 + attribute \src "libresoc.v:45794.3-45822.6" + wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2472 + attribute \src "libresoc.v:47396.3-47424.6" wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46608.3-46636.6" + attribute \src "libresoc.v:47273.3-47301.6" wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45918.3-45946.6" - wire width 13 $3\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45985.3-46014.6" + attribute \src "libresoc.v:46694.3-46722.6" + wire width 14 $3\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46761.3-46790.6" wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45985.3-46014.6" + attribute \src "libresoc.v:46761.3-46790.6" wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46438.3-46466.6" + attribute \src "libresoc.v:47094.3-47122.6" wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46655.3-46683.6" + attribute \src "libresoc.v:47311.3-47339.6" wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45861.3-45889.6" + attribute \src "libresoc.v:46646.3-46674.6" wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46237.3-46265.6" + attribute \src "libresoc.v:46933.3-46961.6" wire $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46352.3-46380.6" + attribute \src "libresoc.v:47018.3-47046.6" wire $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46523.3-46551.6" + attribute \src "libresoc.v:47188.3-47216.6" wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46570.3-46598.6" + attribute \src "libresoc.v:47226.3-47254.6" wire $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46150.3-46179.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46150.3-46179.6" + attribute \src "libresoc.v:46876.3-46905.6" wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46485.3-46513.6" + attribute \src "libresoc.v:47141.3-47169.6" wire $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46063.3-46092.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46063.3-46092.6" + attribute \src "libresoc.v:46828.3-46857.6" wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46400.3-46428.6" + attribute \src "libresoc.v:47056.3-47084.6" wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46285.3-46313.6" + attribute \src "libresoc.v:46980.3-47008.6" wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46986.3-47014.6" + attribute \src "libresoc.v:47651.3-47679.6" wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47071.3-47099.6" - wire width 13 $3\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47156.3-47185.6" + attribute \src "libresoc.v:47736.3-47764.6" + wire width 14 $3\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47812.3-47841.6" wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47156.3-47185.6" + attribute \src "libresoc.v:47812.3-47841.6" wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47109.3-47137.6" + attribute \src "libresoc.v:47774.3-47802.6" wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47024.3-47052.6" + attribute \src "libresoc.v:47689.3-47717.6" wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47251.3-47279.6" + attribute \src "libresoc.v:47871.3-47899.6" wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47213.3-47241.6" + attribute \src "libresoc.v:47842.3-47870.6" wire $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46816.3-46844.6" - wire width 13 $3\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46863.3-46891.6" + attribute \src "libresoc.v:47481.3-47509.6" + wire width 14 $3\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47528.3-47556.6" wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46769.3-46797.6" + attribute \src "libresoc.v:47434.3-47462.6" wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43923.3-43951.6" + attribute \src "libresoc.v:44480.3-44508.6" wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43572.3-43600.6" - wire width 13 $3\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43601.3-43630.6" + attribute \src "libresoc.v:44129.3-44157.6" + wire width 14 $3\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44158.3-44187.6" wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43601.3-43630.6" + attribute \src "libresoc.v:44158.3-44187.6" wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43749.3-43777.6" + attribute \src "libresoc.v:44306.3-44334.6" wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43952.3-43980.6" + attribute \src "libresoc.v:44509.3-44537.6" wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43543.3-43571.6" + attribute \src "libresoc.v:44100.3-44128.6" wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43691.3-43719.6" + attribute \src "libresoc.v:44248.3-44276.6" wire $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43778.3-43806.6" + attribute \src "libresoc.v:44335.3-44363.6" wire $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43865.3-43893.6" + attribute \src "libresoc.v:44422.3-44450.6" wire $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43894.3-43922.6" + attribute \src "libresoc.v:44451.3-44479.6" wire $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43661.3-43690.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $3\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43661.3-43690.6" + attribute \src "libresoc.v:44218.3-44247.6" wire $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43836.3-43864.6" + attribute \src "libresoc.v:44393.3-44421.6" wire $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43631.3-43660.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $3\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43631.3-43660.6" + attribute \src "libresoc.v:44188.3-44217.6" wire $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43807.3-43835.6" + attribute \src "libresoc.v:44364.3-44392.6" wire $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43720.3-43748.6" + attribute \src "libresoc.v:44277.3-44305.6" wire $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48100.3-48128.6" + attribute \src "libresoc.v:43810.3-43838.6" wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47749.3-47777.6" - wire width 13 $3\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47778.3-47807.6" + attribute \src "libresoc.v:48306.3-48334.6" + wire width 14 $3\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48335.3-48364.6" wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47778.3-47807.6" + attribute \src "libresoc.v:48335.3-48364.6" wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47926.3-47954.6" + attribute \src "libresoc.v:48483.3-48511.6" wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48129.3-48157.6" + attribute \src "libresoc.v:43839.3-43867.6" wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47720.3-47748.6" + attribute \src "libresoc.v:48277.3-48305.6" wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47868.3-47896.6" + attribute \src "libresoc.v:48425.3-48453.6" wire $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47955.3-47983.6" + attribute \src "libresoc.v:48512.3-48540.6" wire $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48042.3-48070.6" + attribute \src "libresoc.v:43752.3-43780.6" wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48071.3-48099.6" + attribute \src "libresoc.v:43781.3-43809.6" wire $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47838.3-47867.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47838.3-47867.6" + attribute \src "libresoc.v:48395.3-48424.6" wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48013.3-48041.6" + attribute \src "libresoc.v:43723.3-43751.6" wire $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47808.3-47837.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47808.3-47837.6" + attribute \src "libresoc.v:48365.3-48394.6" wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47984.3-48012.6" + attribute \src "libresoc.v:48541.3-48569.6" wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47897.3-47925.6" + attribute \src "libresoc.v:48454.3-48482.6" wire $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44068.3-44096.6" - wire width 13 $3\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44097.3-44126.6" + attribute \src "libresoc.v:44625.3-44653.6" + wire width 14 $3\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44654.3-44683.6" wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44097.3-44126.6" + attribute \src "libresoc.v:44654.3-44683.6" wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44274.3-44302.6" + attribute \src "libresoc.v:44831.3-44859.6" wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44039.3-44067.6" + attribute \src "libresoc.v:44596.3-44624.6" wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44216.3-44244.6" + attribute \src "libresoc.v:44773.3-44801.6" wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44245.3-44273.6" + attribute \src "libresoc.v:44802.3-44830.6" wire $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44157.3-44186.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44157.3-44186.6" + attribute \src "libresoc.v:44714.3-44743.6" wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44127.3-44156.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44127.3-44156.6" + attribute \src "libresoc.v:44684.3-44713.6" wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44187.3-44215.6" + attribute \src "libresoc.v:44744.3-44772.6" wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44390.3-44418.6" - wire width 13 $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44419.3-44448.6" + attribute \src "libresoc.v:44947.3-44975.6" + wire width 14 $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44976.3-45005.6" wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44419.3-44448.6" + attribute \src "libresoc.v:44976.3-45005.6" wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:45124.3-45152.6" wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:45182.3-45210.6" wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44741.3-44769.6" + attribute \src "libresoc.v:45298.3-45326.6" wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44361.3-44389.6" + attribute \src "libresoc.v:44918.3-44946.6" wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:45095.3-45123.6" wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44683.3-44711.6" + attribute \src "libresoc.v:45240.3-45268.6" wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44712.3-44740.6" + attribute \src "libresoc.v:45269.3-45297.6" wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44479.3-44508.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44479.3-44508.6" + attribute \src "libresoc.v:45036.3-45065.6" wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:45153.3-45181.6" wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44654.3-44682.6" + attribute \src "libresoc.v:45211.3-45239.6" wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44449.3-44478.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44449.3-44478.6" + attribute \src "libresoc.v:45006.3-45035.6" wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:45066.3-45094.6" wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48245.3-48273.6" - wire width 13 $3\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:43427.3-43455.6" + attribute \src "libresoc.v:43955.3-43983.6" + wire width 14 $3\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43984.3-44012.6" wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48216.3-48244.6" + attribute \src "libresoc.v:43926.3-43954.6" wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43456.3-43484.6" + attribute \src "libresoc.v:44013.3-44041.6" wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47517.3-47545.6" + attribute \src "libresoc.v:48074.3-48102.6" wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47421.3-47449.6" - wire width 13 $3\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47459.3-47487.6" + attribute \src "libresoc.v:47987.3-48015.6" + wire width 14 $3\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:48016.3-48044.6" wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47374.3-47402.6" + attribute \src "libresoc.v:47958.3-47986.6" wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47546.3-47574.6" + attribute \src "libresoc.v:48103.3-48131.6" wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47633.3-47661.6" + attribute \src "libresoc.v:48190.3-48218.6" wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47488.3-47516.6" + attribute \src "libresoc.v:48045.3-48073.6" wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47604.3-47632.6" + attribute \src "libresoc.v:48161.3-48189.6" wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47575.3-47603.6" + attribute \src "libresoc.v:48132.3-48160.6" wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45092.3-45120.6" + attribute \src "libresoc.v:45649.3-45677.6" wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45063.3-45091.6" + attribute \src "libresoc.v:45620.3-45648.6" wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44857.3-44885.6" - wire width 13 $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44886.3-44915.6" + attribute \src "libresoc.v:45414.3-45442.6" + wire width 14 $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45443.3-45472.6" wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44886.3-44915.6" + attribute \src "libresoc.v:45443.3-45472.6" wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45179.3-45207.6" + attribute \src "libresoc.v:45736.3-45764.6" wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44828.3-44856.6" + attribute \src "libresoc.v:45385.3-45413.6" wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45005.3-45033.6" + attribute \src "libresoc.v:45562.3-45590.6" wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45034.3-45062.6" + attribute \src "libresoc.v:45591.3-45619.6" wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45150.3-45178.6" + attribute \src "libresoc.v:45707.3-45735.6" wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44975.3-45004.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44975.3-45004.6" + attribute \src "libresoc.v:45532.3-45561.6" wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44945.3-44974.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44945.3-44974.6" + attribute \src "libresoc.v:45502.3-45531.6" wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45121.3-45149.6" + attribute \src "libresoc.v:45678.3-45706.6" wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44916.3-44944.6" + attribute \src "libresoc.v:45473.3-45501.6" wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $4\corebusy_o[0:0] - attribute \src "libresoc.v:45627.3-45653.6" - wire width 2 $4\counter$next[1:0]$2569 - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46431.3-46457.6" + wire width 2 $4\counter$next[1:0]$2658 + attribute \src "libresoc.v:46477.3-46567.6" wire $5\corebusy_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $6\corebusy_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $7\corebusy_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $8\corebusy_o[0:0] - attribute \src "libresoc.v:45673.3-45763.6" + attribute \src "libresoc.v:46477.3-46567.6" wire $9\corebusy_o[0:0] - attribute \src "libresoc.v:41811.20-41811.122" - wire $and$libresoc.v:41811$1506_Y - attribute \src "libresoc.v:41812.20-41812.126" - wire $and$libresoc.v:41812$1507_Y - attribute \src "libresoc.v:41814.20-41814.110" - wire $and$libresoc.v:41814$1509_Y - attribute \src "libresoc.v:41815.20-41815.123" - wire $and$libresoc.v:41815$1510_Y - attribute \src "libresoc.v:41817.20-41817.122" - wire $and$libresoc.v:41817$1512_Y - attribute \src "libresoc.v:41818.20-41818.126" - wire $and$libresoc.v:41818$1513_Y - attribute \src "libresoc.v:41820.20-41820.110" - wire $and$libresoc.v:41820$1515_Y - attribute \src "libresoc.v:41821.20-41821.123" - wire $and$libresoc.v:41821$1516_Y - attribute \src "libresoc.v:41823.20-41823.123" - wire $and$libresoc.v:41823$1518_Y - attribute \src "libresoc.v:41824.20-41824.126" - wire $and$libresoc.v:41824$1519_Y - attribute \src "libresoc.v:41826.20-41826.110" - wire $and$libresoc.v:41826$1521_Y - attribute \src "libresoc.v:41827.20-41827.123" - wire $and$libresoc.v:41827$1522_Y - attribute \src "libresoc.v:41829.20-41829.123" - wire $and$libresoc.v:41829$1524_Y - attribute \src "libresoc.v:41830.20-41830.126" - wire $and$libresoc.v:41830$1525_Y - attribute \src "libresoc.v:41832.20-41832.110" - wire $and$libresoc.v:41832$1527_Y - attribute \src "libresoc.v:41833.20-41833.123" - wire $and$libresoc.v:41833$1528_Y - attribute \src "libresoc.v:41835.20-41835.123" - wire $and$libresoc.v:41835$1530_Y - attribute \src "libresoc.v:41836.20-41836.126" - wire $and$libresoc.v:41836$1531_Y - attribute \src "libresoc.v:41838.20-41838.110" - wire $and$libresoc.v:41838$1533_Y - attribute \src "libresoc.v:41839.20-41839.123" - wire $and$libresoc.v:41839$1534_Y - attribute \src "libresoc.v:41841.20-41841.123" - wire $and$libresoc.v:41841$1536_Y - attribute \src "libresoc.v:41842.20-41842.126" - wire $and$libresoc.v:41842$1537_Y - attribute \src "libresoc.v:41844.20-41844.110" - wire $and$libresoc.v:41844$1539_Y - attribute \src "libresoc.v:41845.20-41845.123" - wire $and$libresoc.v:41845$1540_Y - attribute \src "libresoc.v:41847.20-41847.113" - wire $and$libresoc.v:41847$1542_Y - attribute \src "libresoc.v:41848.20-41848.126" - wire $and$libresoc.v:41848$1543_Y - attribute \src "libresoc.v:41850.20-41850.110" - wire $and$libresoc.v:41850$1545_Y - attribute \src "libresoc.v:41851.20-41851.123" - wire $and$libresoc.v:41851$1546_Y - attribute \src "libresoc.v:41853.20-41853.114" - wire $and$libresoc.v:41853$1548_Y - attribute \src "libresoc.v:41854.20-41854.126" - wire $and$libresoc.v:41854$1549_Y - attribute \src "libresoc.v:41856.20-41856.110" - wire $and$libresoc.v:41856$1551_Y - attribute \src "libresoc.v:41857.20-41857.123" - wire $and$libresoc.v:41857$1552_Y - attribute \src "libresoc.v:41886.20-41886.123" - wire $and$libresoc.v:41886$1581_Y - attribute \src "libresoc.v:41887.20-41887.128" - wire $and$libresoc.v:41887$1582_Y - attribute \src "libresoc.v:41888.20-41888.133" - wire $and$libresoc.v:41888$1583_Y - attribute \src "libresoc.v:41890.20-41890.110" - wire $and$libresoc.v:41890$1585_Y - attribute \src "libresoc.v:41891.20-41891.128" - wire $and$libresoc.v:41891$1586_Y - attribute \src "libresoc.v:41893.20-41893.116" - wire $and$libresoc.v:41893$1588_Y - attribute \src "libresoc.v:41894.20-41894.123" - wire $and$libresoc.v:41894$1589_Y - attribute \src "libresoc.v:41895.20-41895.128" - wire $and$libresoc.v:41895$1590_Y - attribute \src "libresoc.v:41896.20-41896.128" - wire $and$libresoc.v:41896$1591_Y - attribute \src "libresoc.v:41897.20-41897.129" - wire $and$libresoc.v:41897$1592_Y - attribute \src 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+ wire width 3 $extend$libresoc.v:42418$1825_Y + attribute \src "libresoc.v:42691.19-42691.93" + wire width 3 $extend$libresoc.v:42691$2099_Y + attribute \src "libresoc.v:42716.19-42716.93" + wire width 3 $extend$libresoc.v:42716$2125_Y + attribute \src "libresoc.v:42446.19-42446.103" + wire $ne$libresoc.v:42446$1854_Y + attribute \src "libresoc.v:42448.19-42448.103" + wire $ne$libresoc.v:42448$1856_Y + attribute \src "libresoc.v:42107.20-42107.106" + wire $not$libresoc.v:42107$1510_Y + attribute \src "libresoc.v:42113.20-42113.106" + wire $not$libresoc.v:42113$1516_Y + attribute \src "libresoc.v:42119.20-42119.106" + wire $not$libresoc.v:42119$1522_Y + attribute \src "libresoc.v:42125.20-42125.106" + wire $not$libresoc.v:42125$1528_Y + attribute \src "libresoc.v:42131.20-42131.106" + wire $not$libresoc.v:42131$1534_Y + attribute \src "libresoc.v:42137.20-42137.106" + wire $not$libresoc.v:42137$1540_Y + attribute \src "libresoc.v:42143.20-42143.106" + wire $not$libresoc.v:42143$1546_Y + attribute \src "libresoc.v:42149.20-42149.106" + wire $not$libresoc.v:42149$1552_Y + attribute \src "libresoc.v:42183.20-42183.106" + wire $not$libresoc.v:42183$1586_Y + attribute \src "libresoc.v:42195.20-42195.106" + wire $not$libresoc.v:42195$1598_Y + attribute \src "libresoc.v:42203.20-42203.106" + wire $not$libresoc.v:42203$1606_Y + attribute \src "libresoc.v:42211.20-42211.106" + wire $not$libresoc.v:42211$1614_Y + attribute \src "libresoc.v:42219.20-42219.106" + wire $not$libresoc.v:42219$1622_Y + attribute \src "libresoc.v:42227.20-42227.106" + wire $not$libresoc.v:42227$1630_Y + attribute \src "libresoc.v:42235.20-42235.106" + wire $not$libresoc.v:42235$1638_Y + attribute \src "libresoc.v:42256.20-42256.106" + wire $not$libresoc.v:42256$1659_Y + attribute \src "libresoc.v:42262.20-42262.106" + wire $not$libresoc.v:42262$1665_Y + attribute \src "libresoc.v:42268.20-42268.106" + wire $not$libresoc.v:42268$1671_Y + attribute \src "libresoc.v:42283.20-42283.106" + wire $not$libresoc.v:42283$1687_Y + attribute \src "libresoc.v:42289.20-42289.106" + wire $not$libresoc.v:42289$1693_Y + attribute \src "libresoc.v:42295.20-42295.106" + wire $not$libresoc.v:42295$1699_Y + attribute \src "libresoc.v:42301.20-42301.106" + wire $not$libresoc.v:42301$1705_Y + attribute \src "libresoc.v:42317.20-42317.106" + wire $not$libresoc.v:42317$1721_Y + attribute \src "libresoc.v:42323.20-42323.106" + wire $not$libresoc.v:42323$1727_Y + attribute \src "libresoc.v:42329.20-42329.106" + wire $not$libresoc.v:42329$1733_Y + attribute \src "libresoc.v:42335.20-42335.106" + wire $not$libresoc.v:42335$1739_Y + attribute \src "libresoc.v:42354.20-42354.106" + wire $not$libresoc.v:42354$1760_Y + attribute \src "libresoc.v:42360.20-42360.106" + wire $not$libresoc.v:42360$1766_Y + attribute \src "libresoc.v:42366.20-42366.106" + wire $not$libresoc.v:42366$1772_Y + attribute \src "libresoc.v:42372.20-42372.106" + wire $not$libresoc.v:42372$1778_Y + attribute \src "libresoc.v:42378.20-42378.106" + wire $not$libresoc.v:42378$1784_Y + attribute \src "libresoc.v:42398.20-42398.106" + wire $not$libresoc.v:42398$1804_Y + attribute \src "libresoc.v:42404.20-42404.106" + wire $not$libresoc.v:42404$1810_Y + attribute \src "libresoc.v:42414.20-42414.106" + wire $not$libresoc.v:42414$1821_Y + attribute \src "libresoc.v:42422.20-42422.106" + wire $not$libresoc.v:42422$1830_Y + attribute \src "libresoc.v:42459.19-42459.136" + wire width 4 $not$libresoc.v:42459$1867_Y + attribute \src "libresoc.v:42460.19-42460.192" + wire width 6 $not$libresoc.v:42460$1868_Y + attribute \src "libresoc.v:42461.19-42461.138" + wire width 3 $not$libresoc.v:42461$1869_Y + attribute \src "libresoc.v:42462.19-42462.150" + wire width 4 $not$libresoc.v:42462$1870_Y + attribute \src "libresoc.v:42469.19-42469.128" + wire width 3 $not$libresoc.v:42469$1877_Y + attribute \src "libresoc.v:42484.19-42484.159" + wire width 6 $not$libresoc.v:42484$1892_Y + attribute \src "libresoc.v:42491.19-42491.128" + wire width 3 $not$libresoc.v:42491$1899_Y + attribute \src "libresoc.v:42498.19-42498.128" + wire width 3 $not$libresoc.v:42498$1906_Y + attribute \src "libresoc.v:42509.19-42509.150" + wire width 5 $not$libresoc.v:42509$1917_Y + attribute \src "libresoc.v:42510.19-42510.134" + wire width 3 $not$libresoc.v:42510$1918_Y + attribute \src "libresoc.v:42513.19-42513.106" + wire $not$libresoc.v:42513$1921_Y + attribute \src "libresoc.v:42519.19-42519.105" + wire $not$libresoc.v:42519$1927_Y + attribute \src "libresoc.v:42525.19-42525.107" + wire $not$libresoc.v:42525$1933_Y + attribute \src "libresoc.v:42531.19-42531.110" + wire $not$libresoc.v:42531$1939_Y + attribute \src "libresoc.v:42537.19-42537.106" + wire $not$libresoc.v:42537$1945_Y + attribute \src "libresoc.v:42543.19-42543.106" + wire $not$libresoc.v:42543$1951_Y + attribute \src "libresoc.v:42549.19-42549.106" + wire $not$libresoc.v:42549$1957_Y + attribute \src "libresoc.v:42555.19-42555.111" + wire $not$libresoc.v:42555$1963_Y + attribute \src "libresoc.v:42561.19-42561.107" + wire $not$libresoc.v:42561$1969_Y + attribute \src "libresoc.v:42576.19-42576.106" + wire $not$libresoc.v:42576$1984_Y + attribute \src "libresoc.v:42582.19-42582.105" + wire $not$libresoc.v:42582$1990_Y + attribute \src "libresoc.v:42588.19-42588.107" + wire $not$libresoc.v:42588$1996_Y + attribute \src "libresoc.v:42594.19-42594.110" + wire $not$libresoc.v:42594$2002_Y + attribute \src "libresoc.v:42600.19-42600.106" + wire $not$libresoc.v:42600$2008_Y + attribute \src "libresoc.v:42606.19-42606.106" + wire $not$libresoc.v:42606$2014_Y + attribute \src "libresoc.v:42612.19-42612.111" + wire $not$libresoc.v:42612$2020_Y + attribute \src "libresoc.v:42618.19-42618.107" + wire $not$libresoc.v:42618$2026_Y + attribute \src "libresoc.v:42632.19-42632.111" + wire $not$libresoc.v:42632$2040_Y + attribute \src "libresoc.v:42638.19-42638.107" + wire $not$libresoc.v:42638$2046_Y + attribute \src "libresoc.v:42652.19-42652.110" + wire $not$libresoc.v:42652$2060_Y + attribute \src "libresoc.v:42658.19-42658.114" + wire $not$libresoc.v:42658$2066_Y + attribute \src "libresoc.v:42664.19-42664.110" + wire $not$libresoc.v:42664$2072_Y + attribute \src "libresoc.v:42670.19-42670.110" + wire $not$libresoc.v:42670$2078_Y + attribute \src "libresoc.v:42676.19-42676.110" + wire $not$libresoc.v:42676$2084_Y + attribute \src "libresoc.v:42682.19-42682.115" + wire $not$libresoc.v:42682$2090_Y + attribute \src "libresoc.v:42698.19-42698.110" + wire $not$libresoc.v:42698$2107_Y + attribute \src "libresoc.v:42704.19-42704.110" + wire $not$libresoc.v:42704$2113_Y + attribute \src "libresoc.v:42710.19-42710.115" + wire $not$libresoc.v:42710$2119_Y + attribute \src "libresoc.v:42723.19-42723.110" + wire $not$libresoc.v:42723$2133_Y + attribute \src "libresoc.v:42729.19-42729.109" + wire $not$libresoc.v:42729$2139_Y + attribute \src "libresoc.v:42735.19-42735.106" + wire $not$libresoc.v:42735$2145_Y + attribute \src "libresoc.v:42743.19-42743.110" + wire $not$libresoc.v:42743$2153_Y + attribute \src "libresoc.v:42752.19-42752.106" + wire $not$libresoc.v:42752$2162_Y + attribute \src "libresoc.v:42760.19-42760.106" + wire $not$libresoc.v:42760$2170_Y + attribute \src "libresoc.v:42768.19-42768.113" + wire $not$libresoc.v:42768$2178_Y + attribute \src "libresoc.v:42774.19-42774.111" + wire $not$libresoc.v:42774$2184_Y + attribute \src "libresoc.v:42780.19-42780.110" + wire $not$libresoc.v:42780$2190_Y + attribute \src "libresoc.v:42789.19-42789.113" + wire $not$libresoc.v:42789$2199_Y + attribute \src "libresoc.v:42795.19-42795.111" + wire $not$libresoc.v:42795$2205_Y + attribute \src "libresoc.v:42803.19-42803.108" + wire $not$libresoc.v:42803$2213_Y + attribute \src "libresoc.v:42820.19-42820.99" + wire $not$libresoc.v:42820$2230_Y + attribute \src "libresoc.v:42826.19-42826.104" + wire $not$libresoc.v:42826$2236_Y + attribute \src "libresoc.v:42153.20-42153.117" + wire width 64 $or$libresoc.v:42153$1556_Y + attribute \src "libresoc.v:42154.20-42154.123" + wire width 64 $or$libresoc.v:42154$1557_Y + attribute \src "libresoc.v:42155.20-42155.113" + wire width 64 $or$libresoc.v:42155$1558_Y + attribute \src "libresoc.v:42156.20-42156.103" + wire width 64 $or$libresoc.v:42156$1559_Y + attribute \src "libresoc.v:42157.20-42157.123" + wire width 64 $or$libresoc.v:42157$1560_Y + attribute \src "libresoc.v:42158.20-42158.122" + wire width 65 $or$libresoc.v:42158$1561_Y + attribute \src "libresoc.v:42159.20-42159.113" + wire width 65 $or$libresoc.v:42159$1562_Y + attribute \src "libresoc.v:42160.20-42160.103" + wire width 65 $or$libresoc.v:42160$1563_Y + attribute \src "libresoc.v:42161.20-42161.103" + wire width 65 $or$libresoc.v:42161$1564_Y + attribute \src "libresoc.v:42162.20-42162.110" + wire width 7 $or$libresoc.v:42162$1565_Y + attribute \src "libresoc.v:42163.20-42163.117" + wire width 7 $or$libresoc.v:42163$1566_Y + attribute \src "libresoc.v:42164.20-42164.110" + wire width 7 $or$libresoc.v:42164$1567_Y + attribute \src "libresoc.v:42165.20-42165.103" + wire width 7 $or$libresoc.v:42165$1568_Y + attribute \src "libresoc.v:42166.20-42166.117" + wire width 7 $or$libresoc.v:42166$1569_Y + attribute \src "libresoc.v:42167.20-42167.117" + wire width 7 $or$libresoc.v:42167$1570_Y + attribute \src "libresoc.v:42168.20-42168.110" + wire width 7 $or$libresoc.v:42168$1571_Y + attribute \src "libresoc.v:42169.20-42169.103" + wire width 7 $or$libresoc.v:42169$1572_Y + attribute \src "libresoc.v:42170.20-42170.103" + wire width 7 $or$libresoc.v:42170$1573_Y + attribute \src "libresoc.v:42171.20-42171.99" + wire $or$libresoc.v:42171$1574_Y + attribute \src "libresoc.v:42172.20-42172.107" + wire $or$libresoc.v:42172$1575_Y + attribute \src "libresoc.v:42173.20-42173.105" + wire $or$libresoc.v:42173$1576_Y + attribute \src "libresoc.v:42174.20-42174.103" + wire $or$libresoc.v:42174$1577_Y + attribute \src "libresoc.v:42175.20-42175.107" + wire $or$libresoc.v:42175$1578_Y + attribute \src "libresoc.v:42176.20-42176.107" + wire $or$libresoc.v:42176$1579_Y + attribute \src "libresoc.v:42177.20-42177.105" + wire $or$libresoc.v:42177$1580_Y + attribute \src "libresoc.v:42178.20-42178.103" + wire $or$libresoc.v:42178$1581_Y + attribute \src "libresoc.v:42179.20-42179.103" + wire $or$libresoc.v:42179$1582_Y + attribute \src "libresoc.v:42241.20-42241.117" + wire width 4 $or$libresoc.v:42241$1644_Y + attribute \src "libresoc.v:42242.20-42242.113" + wire width 4 $or$libresoc.v:42242$1645_Y + attribute \src "libresoc.v:42243.20-42243.123" + wire width 4 $or$libresoc.v:42243$1646_Y + attribute \src "libresoc.v:42244.20-42244.113" + wire width 4 $or$libresoc.v:42244$1647_Y + attribute \src "libresoc.v:42245.20-42245.103" + wire width 4 $or$libresoc.v:42245$1648_Y + attribute \src "libresoc.v:42246.20-42246.117" + wire width 256 $or$libresoc.v:42246$1649_Y + attribute \src "libresoc.v:42247.20-42247.110" + wire width 256 $or$libresoc.v:42247$1650_Y + attribute \src "libresoc.v:42248.20-42248.117" + wire width 256 $or$libresoc.v:42248$1651_Y + attribute \src "libresoc.v:42249.20-42249.110" + wire width 256 $or$libresoc.v:42249$1652_Y + attribute \src "libresoc.v:42250.20-42250.103" + wire width 256 $or$libresoc.v:42250$1653_Y + attribute \src "libresoc.v:42272.20-42272.117" + wire width 2 $or$libresoc.v:42272$1675_Y + attribute \src "libresoc.v:42273.20-42273.113" + wire width 2 $or$libresoc.v:42273$1676_Y + attribute \src "libresoc.v:42274.20-42274.117" + wire width 2 $or$libresoc.v:42274$1677_Y + attribute \src "libresoc.v:42275.20-42275.110" + wire width 2 $or$libresoc.v:42275$1678_Y + attribute \src "libresoc.v:42305.20-42305.112" + wire width 2 $or$libresoc.v:42305$1709_Y + attribute \src "libresoc.v:42306.20-42306.123" + wire width 2 $or$libresoc.v:42306$1710_Y + attribute \src "libresoc.v:42307.20-42307.103" + wire width 2 $or$libresoc.v:42307$1711_Y + attribute \src "libresoc.v:42308.20-42308.117" + wire width 3 $or$libresoc.v:42308$1712_Y + attribute \src "libresoc.v:42309.20-42309.117" + wire width 3 $or$libresoc.v:42309$1713_Y + attribute \src "libresoc.v:42310.20-42310.103" + wire width 3 $or$libresoc.v:42310$1714_Y + attribute \src "libresoc.v:42339.20-42339.123" + wire $or$libresoc.v:42339$1743_Y + attribute \src "libresoc.v:42340.20-42340.123" + wire $or$libresoc.v:42340$1744_Y + attribute \src "libresoc.v:42341.20-42341.103" + wire $or$libresoc.v:42341$1745_Y + attribute \src "libresoc.v:42343.20-42343.117" + wire $or$libresoc.v:42343$1748_Y + attribute \src "libresoc.v:42344.20-42344.117" + wire $or$libresoc.v:42344$1749_Y + attribute \src "libresoc.v:42345.20-42345.103" + wire $or$libresoc.v:42345$1750_Y + attribute \src "libresoc.v:42382.20-42382.123" + wire width 64 $or$libresoc.v:42382$1788_Y + attribute \src "libresoc.v:42383.20-42383.123" + wire width 64 $or$libresoc.v:42383$1789_Y + attribute \src "libresoc.v:42384.20-42384.113" + wire width 64 $or$libresoc.v:42384$1790_Y + attribute \src "libresoc.v:42385.20-42385.103" + wire width 64 $or$libresoc.v:42385$1791_Y + attribute \src "libresoc.v:42386.20-42386.117" + wire width 3 $or$libresoc.v:42386$1792_Y + attribute \src "libresoc.v:42387.20-42387.117" + wire width 3 $or$libresoc.v:42387$1793_Y + attribute \src "libresoc.v:42388.20-42388.110" + wire width 3 $or$libresoc.v:42388$1794_Y + attribute \src "libresoc.v:42389.20-42389.103" + wire width 3 $or$libresoc.v:42389$1795_Y + attribute \src "libresoc.v:42390.20-42390.107" + wire $or$libresoc.v:42390$1796_Y + attribute \src "libresoc.v:42391.20-42391.107" + wire $or$libresoc.v:42391$1797_Y + attribute \src "libresoc.v:42392.20-42392.105" + wire $or$libresoc.v:42392$1798_Y + attribute \src "libresoc.v:42393.20-42393.103" + wire $or$libresoc.v:42393$1799_Y + attribute \src "libresoc.v:42408.20-42408.123" + wire width 64 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\addr_en$1083 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 7 \addr_en$1103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 7 \addr_en$1122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 7 \addr_en$1140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 7 \addr_en$1156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 8 \addr_en$1230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 256 \addr_en$1258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 256 \addr_en$1278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 256 \addr_en$1298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 256 \addr_en$1318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 256 \addr_en$1338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 256 \addr_en$1358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 2 \addr_en$1405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 2 \addr_en$1421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 2 \addr_en$1437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1487 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \addr_en$1555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \addr_en$1571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \addr_en$1587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \addr_en$1603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \addr_en$1712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \addr_en$1756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \addr_en$1772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 2 \addr_en$1796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 10 \addr_en$1816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 256 \addr_en_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 256 \addr_en_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 256 \addr_en_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 256 \addr_en_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 8 \addr_en_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 3 \addr_en_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 3 \addr_en_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 3 \addr_en_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 3 \addr_en_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 3 \addr_en_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 7 \addr_en_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 10 \addr_en_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 2 \addr_en_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 2 \addr_en_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire width 3 \addr_en_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" wire \addr_en_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire input 67 \bigendian_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 8 \cia__data_o @@ -61796,21 +62028,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 59 \core_core_exc_$signal$9 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 13 input 45 \core_core_fn_unit + wire width 14 input 45 \core_core_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -61893,6 +62126,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 input 44 \core_core_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" @@ -62189,21 +62423,21 @@ module \core attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 input 24 \core_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire output 14 \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire \core_terminate_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 input 27 \core_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:95" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" - wire input 96 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 97 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" wire width 2 \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" wire width 2 \counter$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_data_i @@ -62240,43 +62474,44 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 12 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 69 \data_i$11 + wire width 64 input 70 \data_i$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 88 \dbus__ack + wire input 89 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 93 \dbus__adr + wire width 45 output 94 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 87 \dbus__cyc + wire output 88 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 92 \dbus__dat_r + wire width 64 input 93 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 95 \dbus__dat_w + wire width 64 output 96 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 89 \dbus__err + wire input 90 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 91 \dbus__sel + wire width 8 output 92 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 90 \dbus__stb + wire output 91 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 94 \dbus__we + wire output 95 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_ALU_ALU__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_ALU_ALU__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_ALU_ALU__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_ALU_ALU__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62363,6 +62598,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_ALU_ALU__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62391,24 +62627,27 @@ module \core wire \dec_ALU_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_ALU_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec_ALU_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__cia attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_BRANCH_BRANCH__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_BRANCH_BRANCH__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62489,6 +62728,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_BRANCH_BRANCH__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62500,21 +62740,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_BRANCH_raw_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_CR_CR__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_CR_CR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_CR_CR__insn attribute \enum_base_type "MicrOp" @@ -62591,6 +62832,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_CR_CR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" @@ -62600,21 +62842,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_DIV_DIV__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_DIV_DIV__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_DIV_DIV__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_DIV_DIV__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62701,6 +62944,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_DIV_DIV__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62729,26 +62973,29 @@ module \core wire \dec_DIV_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_DIV_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec_DIV_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LDST_LDST__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_LDST_LDST__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_LDST_LDST__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_LDST_LDST__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62829,6 +63076,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_LDST_LDST__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62858,24 +63106,27 @@ module \core wire \dec_LDST_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_LDST_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec_LDST_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LOGICAL_LOGICAL__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_LOGICAL_LOGICAL__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_LOGICAL_LOGICAL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_LOGICAL_LOGICAL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62962,6 +63213,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_LOGICAL_LOGICAL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62990,22 +63242,25 @@ module \core wire \dec_LOGICAL_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_LOGICAL_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec_LOGICAL_sv_a_nz attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_MUL_MUL__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_MUL_MUL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_MUL_MUL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63086,6 +63341,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_MUL_MUL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63107,21 +63363,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_MUL_raw_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63210,6 +63467,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_SHIFT_ROT_SHIFT_ROT__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63237,21 +63495,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_SHIFT_ROT_raw_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dec_SPR_SPR__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dec_SPR_SPR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_SPR_SPR__insn attribute \enum_base_type "MicrOp" @@ -63328,6 +63587,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_SPR_SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63337,192 +63597,192 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec_SPR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 73 \dmi__addr + wire width 5 input 74 \dmi__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 75 \dmi__data_o + wire width 64 output 76 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 74 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire input 75 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_cr_c_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast2_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_FAST_fast2_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_div0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_ldst0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_mul0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_shiftrot0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_spr0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_ra_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rb_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rc_ldst0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_INT_rc_shiftrot0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_SPR_spr1_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_shiftrot0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_div0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_logical0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_mul0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_shiftrot0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" wire \dp_XER_xer_so_spr0_2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_ldst0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire \en_trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \fast_dest1__addr @@ -63542,16 +63802,16 @@ module \core wire width 64 \fast_src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \fast_src2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" wire width 10 \fu_enable attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 32 output 77 \full_rd2__data_o + wire width 32 output 78 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 8 input 76 \full_rd2__ren + wire width 8 input 77 \full_rd2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 6 output 79 \full_rd__data_o + wire width 6 output 80 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 78 \full_rd__ren + wire width 3 input 79 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -63853,21 +64113,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_alu0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_alu0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63954,6 +64215,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63981,21 +64243,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_branch0__cia attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_branch0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64076,6 +64339,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64083,21 +64347,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_branch0__lk attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_cr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" @@ -64174,26 +64439,28 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_div0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_div0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64280,6 +64547,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64307,21 +64575,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_logical0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_logical0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64408,6 +64677,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64433,21 +64703,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__zero_a attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_mul0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64528,6 +64799,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64545,21 +64817,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__write_cr0 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_shift_rot0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64648,6 +64921,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64671,21 +64945,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_spr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" @@ -64762,6 +65037,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64769,21 +65045,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_trap0__cia attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_trap0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" @@ -64860,6 +65137,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64877,21 +65155,22 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_ldst_ldst0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \fus_oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64972,6 +65251,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -65101,7 +65381,7 @@ module \core wire \fus_xer_so_ok$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_xer_so_ok$143 - attribute \src "libresoc.v:35982.7-35982.15" + attribute \src "libresoc.v:36214.7-36214.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_dest1__addr @@ -65128,134 +65408,134 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 80 \issue__addr + wire width 3 input 81 \issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 83 \issue__addr$12 + wire width 3 input 84 \issue__addr$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 85 \issue__data_i + wire width 64 input 86 \issue__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 82 \issue__data_o + wire width 64 output 83 \issue__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 81 \issue__ren + wire input 82 \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 84 \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire input 71 \issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire input 70 \ivalid_i + wire input 85 \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + wire input 72 \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + wire input 71 \ivalid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 15 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 13 \msr__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \pick_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 32 input 66 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_CR_cr_a_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_CR_cr_b_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_CR_cr_c_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_CR_full_cr_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_FAST_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_FAST_fast2_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_INT_ra_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_INT_rb_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_INT_rc_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_SPR_spr1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:252" wire \rdflag_XER_xer_so_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_a_en_o @@ -65335,85 +65615,85 @@ module \core wire width 6 \rdpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \rp_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 7 \spr_spr1__addr @@ -65432,462 +65712,474 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \state_data_i$174 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 output 72 \state_nia_wen + wire width 3 output 73 \state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \state_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 10 \sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 9 \sv__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire input 68 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \sv_a_nz$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" - wire input 86 \wb_dcache_en + wire input 87 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 11 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 68 \wen$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + wire width 3 input 69 \wen$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1015 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1033 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1055 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1075 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1095 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1350 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1413 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1463 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1479 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1495 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1511 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1547 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1563 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1579 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1595 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1640 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1656 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1672 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1688 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1704 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1748 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1764 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1788 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$1808 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" - wire \wp$994 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$1813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" + wire \wp$999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" wire \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1002 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1023 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1041 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1063 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1083 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1302 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1322 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1342 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1421 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1471 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1487 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1503 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1539 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1555 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1571 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1587 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1629 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1648 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1664 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1680 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1696 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1740 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1756 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1780 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$1800 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \wr_pick$983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1028 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1068 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$1805 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:410" + wire \wr_pick$988 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1005 + wire \wr_pick_dly$1010 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1005$next + wire \wr_pick_dly$1010$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1026 + wire \wr_pick_dly$1031 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1026$next + wire \wr_pick_dly$1031$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1044 + wire \wr_pick_dly$1049 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1044$next + wire \wr_pick_dly$1049$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1066 + wire \wr_pick_dly$1071 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1066$next + wire \wr_pick_dly$1071$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1086 + wire \wr_pick_dly$1091 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1086$next + wire \wr_pick_dly$1091$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1106 + wire \wr_pick_dly$1111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1106$next + wire \wr_pick_dly$1111$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1125 + wire \wr_pick_dly$1130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1125$next + wire \wr_pick_dly$1130$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1143 + wire \wr_pick_dly$1148 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1143$next + wire \wr_pick_dly$1148$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1217 + wire \wr_pick_dly$1222 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1217$next + wire \wr_pick_dly$1222$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1245 + wire \wr_pick_dly$1250 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1245$next + wire \wr_pick_dly$1250$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1265 + wire \wr_pick_dly$1270 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1265$next + wire \wr_pick_dly$1270$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1285 + wire \wr_pick_dly$1290 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1285$next + wire \wr_pick_dly$1290$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1305 + wire \wr_pick_dly$1310 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1305$next + wire \wr_pick_dly$1310$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1325 + wire \wr_pick_dly$1330 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1325$next + wire \wr_pick_dly$1330$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1345 + wire \wr_pick_dly$1350 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1345$next + wire \wr_pick_dly$1350$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1392 + wire \wr_pick_dly$1397 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1392$next + wire \wr_pick_dly$1397$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1408 + wire \wr_pick_dly$1413 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1408$next + wire \wr_pick_dly$1413$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1424 + wire \wr_pick_dly$1429 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1424$next + wire \wr_pick_dly$1429$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1458 + wire \wr_pick_dly$1463 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1458$next + wire \wr_pick_dly$1463$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1474 + wire \wr_pick_dly$1479 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1474$next + wire \wr_pick_dly$1479$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1490 + wire \wr_pick_dly$1495 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1490$next + wire \wr_pick_dly$1495$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1506 + wire \wr_pick_dly$1511 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1506$next + wire \wr_pick_dly$1511$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1542 + wire \wr_pick_dly$1547 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1542$next + wire \wr_pick_dly$1547$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1558 + wire \wr_pick_dly$1563 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1558$next + wire \wr_pick_dly$1563$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1574 + wire \wr_pick_dly$1579 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1574$next + wire \wr_pick_dly$1579$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1590 + wire \wr_pick_dly$1595 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1590$next + wire \wr_pick_dly$1595$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1632 + wire \wr_pick_dly$1637 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1632$next + wire \wr_pick_dly$1637$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1651 + wire \wr_pick_dly$1656 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1651$next + wire \wr_pick_dly$1656$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1667 + wire \wr_pick_dly$1672 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1667$next + wire \wr_pick_dly$1672$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1683 + wire \wr_pick_dly$1688 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1683$next + wire \wr_pick_dly$1688$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1699 + wire \wr_pick_dly$1704 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1699$next + wire \wr_pick_dly$1704$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1743 + wire \wr_pick_dly$1748 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1743$next + wire \wr_pick_dly$1748$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1759 + wire \wr_pick_dly$1764 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1759$next + wire \wr_pick_dly$1764$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1783 + wire \wr_pick_dly$1788 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1783$next + wire \wr_pick_dly$1788$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1803 + wire \wr_pick_dly$1808 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$1803$next + wire \wr_pick_dly$1808$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$986 + wire \wr_pick_dly$991 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \wr_pick_dly$986$next + wire \wr_pick_dly$991$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1006 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1011 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1012 + wire \wr_pick_rise$1016 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1013 + wire \wr_pick_rise$1017 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1014 + wire \wr_pick_rise$1018 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1027 + wire \wr_pick_rise$1019 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1032 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1045 + wire \wr_pick_rise$1037 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1050 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1051 + wire \wr_pick_rise$1055 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1052 + wire \wr_pick_rise$1056 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1053 + wire \wr_pick_rise$1057 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1054 + wire \wr_pick_rise$1058 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1067 + wire \wr_pick_rise$1059 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1072 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1073 + wire \wr_pick_rise$1077 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1074 + wire \wr_pick_rise$1078 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1087 + wire \wr_pick_rise$1079 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1092 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1093 + wire \wr_pick_rise$1097 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1094 + wire \wr_pick_rise$1098 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1107 + wire \wr_pick_rise$1099 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1113 + wire \wr_pick_rise$1117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1126 + wire \wr_pick_rise$1118 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1633 + wire \wr_pick_rise$1136 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1638 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$1639 + wire \wr_pick_rise$1643 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$973 + wire \wr_pick_rise$1644 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$974 + wire \wr_pick_rise$978 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$975 + wire \wr_pick_rise$979 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$976 + wire \wr_pick_rise$980 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$987 + wire \wr_pick_rise$981 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$992 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \wr_pick_rise$993 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + wire \wr_pick_rise$997 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \wr_pick_rise$998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:396" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" wire \wrflag_trap0_o_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_CR_cr_a_en_o @@ -65973,8 +66265,19 @@ module \core wire width 3 \xer_wen$171 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41811$1506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42103$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$988 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:42103$1506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42105$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65982,10 +66285,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$95 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:41811$1506_Y + connect \Y $and$libresoc.v:42105$1508_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41812$1507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42106$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65993,32 +66296,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41812$1507_Y + connect \Y $and$libresoc.v:42106$1509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41814$1509 + cell $and $and$libresoc.v:42108$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1002 - connect \B \$1007 - connect \Y $and$libresoc.v:41814$1509_Y + connect \A \wr_pick$1007 + connect \B \$1012 + connect \Y $and$libresoc.v:42108$1511_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41815$1510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42109$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1002 + connect \A \wr_pick$1007 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41815$1510_Y + connect \Y $and$libresoc.v:42109$1512_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41817$1512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42111$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66026,10 +66329,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$98 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:41817$1512_Y + connect \Y $and$libresoc.v:42111$1514_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41818$1513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42112$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66037,32 +66340,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41818$1513_Y + connect \Y $and$libresoc.v:42112$1515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41820$1515 + cell $and $and$libresoc.v:42114$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1023 - connect \B \$1028 - connect \Y $and$libresoc.v:41820$1515_Y + connect \A \wr_pick$1028 + connect \B \$1033 + connect \Y $and$libresoc.v:42114$1517_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41821$1516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42115$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1023 + connect \A \wr_pick$1028 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41821$1516_Y + connect \Y $and$libresoc.v:42115$1518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41823$1518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42117$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66070,10 +66373,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$101 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41823$1518_Y + connect \Y $and$libresoc.v:42117$1520_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41824$1519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42118$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66081,32 +66384,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41824$1519_Y + connect \Y $and$libresoc.v:42118$1521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41826$1521 + cell $and $and$libresoc.v:42120$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1041 - connect \B \$1046 - connect \Y $and$libresoc.v:41826$1521_Y + connect \A \wr_pick$1046 + connect \B \$1051 + connect \Y $and$libresoc.v:42120$1523_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41827$1522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42121$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1041 + connect \A \wr_pick$1046 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41827$1522_Y + connect \Y $and$libresoc.v:42121$1524_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41829$1524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42123$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66114,10 +66417,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$104 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:41829$1524_Y + connect \Y $and$libresoc.v:42123$1526_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41830$1525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42124$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66125,32 +66428,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41830$1525_Y + connect \Y $and$libresoc.v:42124$1527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41832$1527 + cell $and $and$libresoc.v:42126$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1063 - connect \B \$1068 - connect \Y $and$libresoc.v:41832$1527_Y + connect \A \wr_pick$1068 + connect \B \$1073 + connect \Y $and$libresoc.v:42126$1529_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41833$1528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42127$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1063 + connect \A \wr_pick$1068 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41833$1528_Y + connect \Y $and$libresoc.v:42127$1530_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41835$1530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42129$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66158,10 +66461,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$107 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:41835$1530_Y + connect \Y $and$libresoc.v:42129$1532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41836$1531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42130$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66169,32 +66472,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41836$1531_Y + connect \Y $and$libresoc.v:42130$1533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41838$1533 + cell $and $and$libresoc.v:42132$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1083 - connect \B \$1088 - connect \Y $and$libresoc.v:41838$1533_Y + connect \A \wr_pick$1088 + connect \B \$1093 + connect \Y $and$libresoc.v:42132$1535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41839$1534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42133$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1083 + connect \A \wr_pick$1088 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41839$1534_Y + connect \Y $and$libresoc.v:42133$1536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41841$1536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42135$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66202,10 +66505,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$110 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:41841$1536_Y + connect \Y $and$libresoc.v:42135$1538_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41842$1537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42136$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66213,32 +66516,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41842$1537_Y + connect \Y $and$libresoc.v:42136$1539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41844$1539 + cell $and $and$libresoc.v:42138$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1103 - connect \B \$1108 - connect \Y $and$libresoc.v:41844$1539_Y + connect \A \wr_pick$1108 + connect \B \$1113 + connect \Y $and$libresoc.v:42138$1541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41845$1540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42139$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1103 + connect \A \wr_pick$1108 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41845$1540_Y + connect \Y $and$libresoc.v:42139$1542_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41847$1542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42141$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66246,10 +66549,10 @@ module \core parameter \Y_WIDTH 1 connect \A \o_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:41847$1542_Y + connect \Y $and$libresoc.v:42141$1544_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41848$1543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42142$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66257,32 +66560,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41848$1543_Y + connect \Y $and$libresoc.v:42142$1545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41850$1545 + cell $and $and$libresoc.v:42144$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1122 - connect \B \$1127 - connect \Y $and$libresoc.v:41850$1545_Y + connect \A \wr_pick$1127 + connect \B \$1132 + connect \Y $and$libresoc.v:42144$1547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41851$1546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42145$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1122 + connect \A \wr_pick$1127 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41851$1546_Y + connect \Y $and$libresoc.v:42145$1548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41853$1548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42147$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66290,10 +66593,10 @@ module \core parameter \Y_WIDTH 1 connect \A \ea_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:41853$1548_Y + connect \Y $and$libresoc.v:42147$1550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41854$1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42148$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66301,32 +66604,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41854$1549_Y + connect \Y $and$libresoc.v:42148$1551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41856$1551 + cell $and $and$libresoc.v:42150$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1140 - connect \B \$1144 - connect \Y $and$libresoc.v:41856$1551_Y + connect \A \wr_pick$1145 + connect \B \$1149 + connect \Y $and$libresoc.v:42150$1553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41857$1552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42151$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1140 + connect \A \wr_pick$1145 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41857$1552_Y + connect \Y $and$libresoc.v:42151$1554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41886$1581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42180$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66334,10 +66637,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:41886$1581_Y + connect \Y $and$libresoc.v:42180$1583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41887$1582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42181$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66345,10 +66648,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41887$1582_Y + connect \Y $and$libresoc.v:42181$1584_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41888$1583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42182$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66356,32 +66659,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41888$1583_Y + connect \Y $and$libresoc.v:42182$1585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41890$1585 + cell $and $and$libresoc.v:42184$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1214 - connect \B \$1218 - connect \Y $and$libresoc.v:41890$1585_Y + connect \A \wr_pick$1219 + connect \B \$1223 + connect \Y $and$libresoc.v:42184$1587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41891$1586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42185$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1214 + connect \A \wr_pick$1219 connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41891$1586_Y + connect \Y $and$libresoc.v:42185$1588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41893$1588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42187$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66389,10 +66692,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41893$1588_Y + connect \Y $and$libresoc.v:42187$1590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41894$1589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42188$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66400,10 +66703,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41894$1589_Y + connect \Y $and$libresoc.v:42188$1591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41895$1590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42189$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66411,10 +66714,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41895$1590_Y + connect \Y $and$libresoc.v:42189$1592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41896$1591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42190$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66422,10 +66725,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41896$1591_Y + connect \Y $and$libresoc.v:42190$1593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41897$1592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42191$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66433,10 +66736,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41897$1592_Y + connect \Y $and$libresoc.v:42191$1594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41898$1593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42192$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66444,10 +66747,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41898$1593_Y + connect \Y $and$libresoc.v:42192$1595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41899$1594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42193$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66455,10 +66758,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41899$1594_Y + connect \Y $and$libresoc.v:42193$1596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41900$1595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42194$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66466,32 +66769,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41900$1595_Y + connect \Y $and$libresoc.v:42194$1597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41902$1597 + cell $and $and$libresoc.v:42196$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1242 - connect \B \$1246 - connect \Y $and$libresoc.v:41902$1597_Y + connect \A \wr_pick$1247 + connect \B \$1251 + connect \Y $and$libresoc.v:42196$1599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41903$1598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42197$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1242 + connect \A \wr_pick$1247 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41903$1598_Y + connect \Y $and$libresoc.v:42197$1600_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41907$1602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42201$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66499,10 +66802,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$122 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:41907$1602_Y + connect \Y $and$libresoc.v:42201$1604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41908$1603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42202$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66510,32 +66813,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41908$1603_Y + connect \Y $and$libresoc.v:42202$1605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41910$1605 + cell $and $and$libresoc.v:42204$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1262 - connect \B \$1266 - connect \Y $and$libresoc.v:41910$1605_Y + connect \A \wr_pick$1267 + connect \B \$1271 + connect \Y $and$libresoc.v:42204$1607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41911$1606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42205$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1262 + connect \A \wr_pick$1267 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41911$1606_Y + connect \Y $and$libresoc.v:42205$1608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41915$1610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42209$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66543,10 +66846,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$123 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:41915$1610_Y + connect \Y $and$libresoc.v:42209$1612_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41916$1611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42210$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66554,32 +66857,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41916$1611_Y + connect \Y $and$libresoc.v:42210$1613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41918$1613 + cell $and $and$libresoc.v:42212$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1282 - connect \B \$1286 - connect \Y $and$libresoc.v:41918$1613_Y + connect \A \wr_pick$1287 + connect \B \$1291 + connect \Y $and$libresoc.v:42212$1615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41919$1614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42213$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1282 + connect \A \wr_pick$1287 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41919$1614_Y + connect \Y $and$libresoc.v:42213$1616_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41923$1618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42217$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66587,10 +66890,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$124 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:41923$1618_Y + connect \Y $and$libresoc.v:42217$1620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41924$1619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42218$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66598,32 +66901,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41924$1619_Y + connect \Y $and$libresoc.v:42218$1621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41926$1621 + cell $and $and$libresoc.v:42220$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1302 - connect \B \$1306 - connect \Y $and$libresoc.v:41926$1621_Y + connect \A \wr_pick$1307 + connect \B \$1311 + connect \Y $and$libresoc.v:42220$1623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41927$1622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42221$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1302 + connect \A \wr_pick$1307 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41927$1622_Y + connect \Y $and$libresoc.v:42221$1624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41931$1626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42225$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66631,10 +66934,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$125 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:41931$1626_Y + connect \Y $and$libresoc.v:42225$1628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41932$1627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42226$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66642,32 +66945,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41932$1627_Y + connect \Y $and$libresoc.v:42226$1629_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41934$1629 + cell $and $and$libresoc.v:42228$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1322 - connect \B \$1326 - connect \Y $and$libresoc.v:41934$1629_Y + connect \A \wr_pick$1327 + connect \B \$1331 + connect \Y $and$libresoc.v:42228$1631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41935$1630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42229$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1322 + connect \A \wr_pick$1327 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41935$1630_Y + connect \Y $and$libresoc.v:42229$1632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41939$1634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42233$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66675,10 +66978,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$126 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:41939$1634_Y + connect \Y $and$libresoc.v:42233$1636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41940$1635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42234$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66686,32 +66989,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41940$1635_Y + connect \Y $and$libresoc.v:42234$1637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41942$1637 + cell $and $and$libresoc.v:42236$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1342 - connect \B \$1346 - connect \Y $and$libresoc.v:41942$1637_Y + connect \A \wr_pick$1347 + connect \B \$1351 + connect \Y $and$libresoc.v:42236$1639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41943$1638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42237$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1342 + connect \A \wr_pick$1347 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41943$1638_Y + connect \Y $and$libresoc.v:42237$1640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41957$1652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42251$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66719,10 +67022,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41957$1652_Y + connect \Y $and$libresoc.v:42251$1654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41958$1653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42252$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66730,10 +67033,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41958$1653_Y + connect \Y $and$libresoc.v:42252$1655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41959$1654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42253$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66741,10 +67044,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41959$1654_Y + connect \Y $and$libresoc.v:42253$1656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41960$1655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42254$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66752,10 +67055,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41960$1655_Y + connect \Y $and$libresoc.v:42254$1657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41961$1656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42255$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66763,32 +67066,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41961$1656_Y + connect \Y $and$libresoc.v:42255$1658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41963$1658 + cell $and $and$libresoc.v:42257$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1389 - connect \B \$1393 - connect \Y $and$libresoc.v:41963$1658_Y + connect \A \wr_pick$1394 + connect \B \$1398 + connect \Y $and$libresoc.v:42257$1660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41964$1659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42258$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1389 + connect \A \wr_pick$1394 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41964$1659_Y + connect \Y $and$libresoc.v:42258$1661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41966$1661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42260$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66796,10 +67099,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$132 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41966$1661_Y + connect \Y $and$libresoc.v:42260$1663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41967$1662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42261$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66807,32 +67110,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41967$1662_Y + connect \Y $and$libresoc.v:42261$1664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41969$1664 + cell $and $and$libresoc.v:42263$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1405 - connect \B \$1409 - connect \Y $and$libresoc.v:41969$1664_Y + connect \A \wr_pick$1410 + connect \B \$1414 + connect \Y $and$libresoc.v:42263$1666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41970$1665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42264$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1405 + connect \A \wr_pick$1410 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41970$1665_Y + connect \Y $and$libresoc.v:42264$1667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41972$1667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42266$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66840,10 +67143,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$133 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:41972$1667_Y + connect \Y $and$libresoc.v:42266$1669_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41973$1668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42267$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66851,32 +67154,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41973$1668_Y + connect \Y $and$libresoc.v:42267$1670_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41975$1670 + cell $and $and$libresoc.v:42269$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1421 - connect \B \$1425 - connect \Y $and$libresoc.v:41975$1670_Y + connect \A \wr_pick$1426 + connect \B \$1430 + connect \Y $and$libresoc.v:42269$1672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41976$1671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42270$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1421 + connect \A \wr_pick$1426 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41976$1671_Y + connect \Y $and$libresoc.v:42270$1673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41983$1679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42277$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66884,10 +67187,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41983$1679_Y + connect \Y $and$libresoc.v:42277$1681_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41984$1680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42278$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66895,10 +67198,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41984$1680_Y + connect \Y $and$libresoc.v:42278$1682_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41985$1681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42279$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66906,10 +67209,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41985$1681_Y + connect \Y $and$libresoc.v:42279$1683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41986$1682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42280$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66917,10 +67220,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41986$1682_Y + connect \Y $and$libresoc.v:42280$1684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41987$1683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42281$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66928,10 +67231,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41987$1683_Y + connect \Y $and$libresoc.v:42281$1685_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41988$1684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42282$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66939,32 +67242,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41988$1684_Y + connect \Y $and$libresoc.v:42282$1686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41990$1686 + cell $and $and$libresoc.v:42284$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1455 - connect \B \$1459 - connect \Y $and$libresoc.v:41990$1686_Y + connect \A \wr_pick$1460 + connect \B \$1464 + connect \Y $and$libresoc.v:42284$1688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41991$1687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42285$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1455 + connect \A \wr_pick$1460 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41991$1687_Y + connect \Y $and$libresoc.v:42285$1689_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41993$1689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42287$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66972,10 +67275,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$136 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41993$1689_Y + connect \Y $and$libresoc.v:42287$1691_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41994$1690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42288$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66983,32 +67286,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41994$1690_Y + connect \Y $and$libresoc.v:42288$1692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41996$1692 + cell $and $and$libresoc.v:42290$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1471 - connect \B \$1475 - connect \Y $and$libresoc.v:41996$1692_Y + connect \A \wr_pick$1476 + connect \B \$1480 + connect \Y $and$libresoc.v:42290$1694_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41997$1693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42291$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1471 + connect \A \wr_pick$1476 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41997$1693_Y + connect \Y $and$libresoc.v:42291$1695_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41999$1695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42293$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67016,10 +67319,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$137 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:41999$1695_Y + connect \Y $and$libresoc.v:42293$1697_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42000$1696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42294$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67027,32 +67330,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42000$1696_Y + connect \Y $and$libresoc.v:42294$1698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42002$1698 + cell $and $and$libresoc.v:42296$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1487 - connect \B \$1491 - connect \Y $and$libresoc.v:42002$1698_Y + connect \A \wr_pick$1492 + connect \B \$1496 + connect \Y $and$libresoc.v:42296$1700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42003$1699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42297$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1487 + connect \A \wr_pick$1492 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42003$1699_Y + connect \Y $and$libresoc.v:42297$1701_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42005$1701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42299$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67060,10 +67363,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$138 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42005$1701_Y + connect \Y $and$libresoc.v:42299$1703_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42006$1702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42300$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67071,32 +67374,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42006$1702_Y + connect \Y $and$libresoc.v:42300$1704_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42008$1704 + cell $and $and$libresoc.v:42302$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1503 - connect \B \$1507 - connect \Y $and$libresoc.v:42008$1704_Y + connect \A \wr_pick$1508 + connect \B \$1512 + connect \Y $and$libresoc.v:42302$1706_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42009$1705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42303$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1503 + connect \A \wr_pick$1508 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42009$1705_Y + connect \Y $and$libresoc.v:42303$1707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42017$1713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42311$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67104,10 +67407,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42017$1713_Y + connect \Y $and$libresoc.v:42311$1715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42018$1714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42312$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67115,10 +67418,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42018$1714_Y + connect \Y $and$libresoc.v:42312$1716_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42019$1715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42313$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67126,10 +67429,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42019$1715_Y + connect \Y $and$libresoc.v:42313$1717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42020$1716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42314$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67137,10 +67440,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [3] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42020$1716_Y + connect \Y $and$libresoc.v:42314$1718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42021$1717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42315$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67148,10 +67451,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [3] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42021$1717_Y + connect \Y $and$libresoc.v:42315$1719_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42022$1718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42316$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67159,32 +67462,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42022$1718_Y + connect \Y $and$libresoc.v:42316$1720_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42024$1720 + cell $and $and$libresoc.v:42318$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1539 - connect \B \$1543 - connect \Y $and$libresoc.v:42024$1720_Y + connect \A \wr_pick$1544 + connect \B \$1548 + connect \Y $and$libresoc.v:42318$1722_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42025$1721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42319$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1539 + connect \A \wr_pick$1544 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42025$1721_Y + connect \Y $and$libresoc.v:42319$1723_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42027$1723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42321$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67192,10 +67495,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$141 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42027$1723_Y + connect \Y $and$libresoc.v:42321$1725_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42028$1724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42322$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67203,32 +67506,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42028$1724_Y + connect \Y $and$libresoc.v:42322$1726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42030$1726 + cell $and $and$libresoc.v:42324$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1555 - connect \B \$1559 - connect \Y $and$libresoc.v:42030$1726_Y + connect \A \wr_pick$1560 + connect \B \$1564 + connect \Y $and$libresoc.v:42324$1728_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42031$1727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42325$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1555 + connect \A \wr_pick$1560 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42031$1727_Y + connect \Y $and$libresoc.v:42325$1729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42033$1729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42327$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67236,10 +67539,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$142 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42033$1729_Y + connect \Y $and$libresoc.v:42327$1731_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42034$1730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42328$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67247,32 +67550,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42034$1730_Y + connect \Y $and$libresoc.v:42328$1732_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42036$1732 + cell $and $and$libresoc.v:42330$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1571 - connect \B \$1575 - connect \Y $and$libresoc.v:42036$1732_Y + connect \A \wr_pick$1576 + connect \B \$1580 + connect \Y $and$libresoc.v:42330$1734_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42037$1733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42331$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1571 + connect \A \wr_pick$1576 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42037$1733_Y + connect \Y $and$libresoc.v:42331$1735_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42039$1735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42333$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67280,10 +67583,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$143 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42039$1735_Y + connect \Y $and$libresoc.v:42333$1737_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42040$1736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42334$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67291,32 +67594,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42040$1736_Y + connect \Y $and$libresoc.v:42334$1738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42042$1738 + cell $and $and$libresoc.v:42336$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1587 - connect \B \$1591 - connect \Y $and$libresoc.v:42042$1738_Y + connect \A \wr_pick$1592 + connect \B \$1596 + connect \Y $and$libresoc.v:42336$1740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42043$1739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42337$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1587 + connect \A \wr_pick$1592 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42043$1739_Y + connect \Y $and$libresoc.v:42337$1741_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42053$1751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42347$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67324,10 +67627,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42053$1751_Y + connect \Y $and$libresoc.v:42347$1753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42054$1752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42348$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67335,10 +67638,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42054$1752_Y + connect \Y $and$libresoc.v:42348$1754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42055$1753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42349$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67346,10 +67649,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42055$1753_Y + connect \Y $and$libresoc.v:42349$1755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42056$1754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42350$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67357,10 +67660,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42056$1754_Y + connect \Y $and$libresoc.v:42350$1756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42057$1755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42351$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67368,10 +67671,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42057$1755_Y + connect \Y $and$libresoc.v:42351$1757_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42058$1756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42352$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67379,10 +67682,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42058$1756_Y + connect \Y $and$libresoc.v:42352$1758_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42059$1757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42353$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67390,32 +67693,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42059$1757_Y + connect \Y $and$libresoc.v:42353$1759_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42061$1759 + cell $and $and$libresoc.v:42355$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1629 - connect \B \$1634 - connect \Y $and$libresoc.v:42061$1759_Y + connect \A \wr_pick$1634 + connect \B \$1639 + connect \Y $and$libresoc.v:42355$1761_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42062$1760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42356$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1629 + connect \A \wr_pick$1634 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42062$1760_Y + connect \Y $and$libresoc.v:42356$1762_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42064$1762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42358$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67423,10 +67726,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$150 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42064$1762_Y + connect \Y $and$libresoc.v:42358$1764_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42065$1763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42359$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67434,32 +67737,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42065$1763_Y + connect \Y $and$libresoc.v:42359$1765_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42067$1765 + cell $and $and$libresoc.v:42361$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1648 - connect \B \$1652 - connect \Y $and$libresoc.v:42067$1765_Y + connect \A \wr_pick$1653 + connect \B \$1657 + connect \Y $and$libresoc.v:42361$1767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42068$1766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42362$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1648 + connect \A \wr_pick$1653 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42068$1766_Y + connect \Y $and$libresoc.v:42362$1768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42070$1768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42364$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67467,10 +67770,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$151 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42070$1768_Y + connect \Y $and$libresoc.v:42364$1770_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42071$1769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42365$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67478,32 +67781,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42071$1769_Y + connect \Y $and$libresoc.v:42365$1771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42073$1771 + cell $and $and$libresoc.v:42367$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1664 - connect \B \$1668 - connect \Y $and$libresoc.v:42073$1771_Y + connect \A \wr_pick$1669 + connect \B \$1673 + connect \Y $and$libresoc.v:42367$1773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42074$1772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42368$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1664 + connect \A \wr_pick$1669 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42074$1772_Y + connect \Y $and$libresoc.v:42368$1774_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42076$1774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42370$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67511,10 +67814,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42076$1774_Y + connect \Y $and$libresoc.v:42370$1776_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42077$1775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42371$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67522,32 +67825,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42077$1775_Y + connect \Y $and$libresoc.v:42371$1777_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42079$1777 + cell $and $and$libresoc.v:42373$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1680 - connect \B \$1684 - connect \Y $and$libresoc.v:42079$1777_Y + connect \A \wr_pick$1685 + connect \B \$1689 + connect \Y $and$libresoc.v:42373$1779_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42080$1778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42374$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1680 + connect \A \wr_pick$1685 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42080$1778_Y + connect \Y $and$libresoc.v:42374$1780_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42082$1780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42376$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67555,10 +67858,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok$152 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42082$1780_Y + connect \Y $and$libresoc.v:42376$1782_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42083$1781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42377$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67566,32 +67869,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42083$1781_Y + connect \Y $and$libresoc.v:42377$1783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42085$1783 + cell $and $and$libresoc.v:42379$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1696 - connect \B \$1700 - connect \Y $and$libresoc.v:42085$1783_Y + connect \A \wr_pick$1701 + connect \B \$1705 + connect \Y $and$libresoc.v:42379$1785_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42086$1784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42380$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1696 + connect \A \wr_pick$1701 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42086$1784_Y + connect \Y $and$libresoc.v:42380$1786_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42100$1798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42394$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67599,10 +67902,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42100$1798_Y + connect \Y $and$libresoc.v:42394$1800_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42101$1799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42395$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67610,10 +67913,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42101$1799_Y + connect \Y $and$libresoc.v:42395$1801_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42102$1800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42396$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67621,10 +67924,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42102$1800_Y + connect \Y $and$libresoc.v:42396$1802_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42103$1801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42397$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67632,32 +67935,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42103$1801_Y + connect \Y $and$libresoc.v:42397$1803_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42105$1803 + cell $and $and$libresoc.v:42399$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1740 - connect \B \$1744 - connect \Y $and$libresoc.v:42105$1803_Y + connect \A \wr_pick$1745 + connect \B \$1749 + connect \Y $and$libresoc.v:42399$1805_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42106$1804 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42400$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1740 + connect \A \wr_pick$1745 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42106$1804_Y + connect \Y $and$libresoc.v:42400$1806_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42108$1806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42402$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67665,10 +67968,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok$158 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42108$1806_Y + connect \Y $and$libresoc.v:42402$1808_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42109$1807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42403$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67676,32 +67979,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42109$1807_Y + connect \Y $and$libresoc.v:42403$1809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42111$1809 + cell $and $and$libresoc.v:42405$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1756 - connect \B \$1760 - connect \Y $and$libresoc.v:42111$1809_Y + connect \A \wr_pick$1761 + connect \B \$1765 + connect \Y $and$libresoc.v:42405$1811_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42112$1810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42406$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1756 + connect \A \wr_pick$1761 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42112$1810_Y + connect \Y $and$libresoc.v:42406$1812_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42117$1816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42411$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67709,10 +68012,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_msr_ok connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42117$1816_Y + connect \Y $and$libresoc.v:42411$1818_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42118$1817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42412$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67720,21 +68023,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [4] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42118$1817_Y + connect \Y $and$libresoc.v:42412$1819_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42119$1818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 13 - connect \A \core_core_fn_unit - connect \B 2'10 - connect \Y $and$libresoc.v:42119$1818_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42120$1819 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42413$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67742,32 +68034,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42120$1819_Y + connect \Y $and$libresoc.v:42413$1820_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42122$1821 + cell $and $and$libresoc.v:42415$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1780 - connect \B \$1784 - connect \Y $and$libresoc.v:42122$1821_Y + connect \A \wr_pick$1785 + connect \B \$1789 + connect \Y $and$libresoc.v:42415$1822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42124$1823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42416$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1780 + connect \A \wr_pick$1785 connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42124$1823_Y + connect \Y $and$libresoc.v:42416$1823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42127$1827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42419$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67775,10 +68067,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_spr1_ok connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42127$1827_Y + connect \Y $and$libresoc.v:42419$1827_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42128$1828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42420$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67786,10 +68078,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42128$1828_Y + connect \Y $and$libresoc.v:42420$1828_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42129$1829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42421$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67797,131 +68089,142 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42129$1829_Y + connect \Y $and$libresoc.v:42421$1829_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42131$1831 + cell $and $and$libresoc.v:42423$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1800 - connect \B \$1804 - connect \Y $and$libresoc.v:42131$1831_Y + connect \A \wr_pick$1805 + connect \B \$1809 + connect \Y $and$libresoc.v:42423$1831_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42132$1832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42424$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1800 + connect \A \wr_pick$1805 connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42132$1832_Y + connect \Y $and$libresoc.v:42424$1832_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42134$1834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42426$1834 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 14 + connect \A \core_core_fn_unit + connect \B 2'10 + connect \Y $and$libresoc.v:42426$1834_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42428$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 7'1000000 - connect \Y $and$libresoc.v:42134$1834_Y + connect \Y $and$libresoc.v:42428$1836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42136$1836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42430$1838 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 6 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 6'100000 - connect \Y $and$libresoc.v:42136$1836_Y + connect \Y $and$libresoc.v:42430$1838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42138$1838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42432$1840 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 8 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 8'10000000 - connect \Y $and$libresoc.v:42138$1838_Y + connect \Y $and$libresoc.v:42432$1840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42140$1840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42434$1842 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 5 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 5'10000 - connect \Y $and$libresoc.v:42140$1840_Y + connect \Y $and$libresoc.v:42434$1842_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42142$1842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42436$1844 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 11 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 11'10000000000 - connect \Y $and$libresoc.v:42142$1842_Y + connect \Y $and$libresoc.v:42436$1844_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42144$1844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42438$1846 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 10 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 10'1000000000 - connect \Y $and$libresoc.v:42144$1844_Y + connect \Y $and$libresoc.v:42438$1846_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42146$1846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42440$1848 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 9 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 9'100000000 - connect \Y $and$libresoc.v:42146$1846_Y + connect \Y $and$libresoc.v:42440$1848_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42148$1848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42442$1850 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 4'1000 - connect \Y $and$libresoc.v:42148$1848_Y + connect \Y $and$libresoc.v:42442$1850_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42150$1850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $and $and$libresoc.v:42444$1852 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 3 - parameter \Y_WIDTH 13 + parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 3'100 - connect \Y $and$libresoc.v:42150$1850_Y + connect \Y $and$libresoc.v:42444$1852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42155$1855 + cell $and $and$libresoc.v:42449$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67929,10 +68232,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42155$1855_Y + connect \Y $and$libresoc.v:42449$1857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42156$1856 + cell $and $and$libresoc.v:42450$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67940,10 +68243,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42156$1856_Y + connect \Y $and$libresoc.v:42450$1858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42159$1859 + cell $and $and$libresoc.v:42453$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67951,10 +68254,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42159$1859_Y + connect \Y $and$libresoc.v:42453$1861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42162$1862 + cell $and $and$libresoc.v:42456$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67962,10 +68265,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42162$1862_Y + connect \Y $and$libresoc.v:42456$1864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42169$1869 + cell $and $and$libresoc.v:42463$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67973,10 +68276,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42169$1869_Y + connect \Y $and$libresoc.v:42463$1871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42170$1870 + cell $and $and$libresoc.v:42464$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67984,10 +68287,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42170$1870_Y + connect \Y $and$libresoc.v:42464$1872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42173$1873 + cell $and $and$libresoc.v:42467$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67995,10 +68298,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42173$1873_Y + connect \Y $and$libresoc.v:42467$1875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42176$1876 + cell $and $and$libresoc.v:42470$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68006,10 +68309,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42176$1876_Y + connect \Y $and$libresoc.v:42470$1878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42177$1877 + cell $and $and$libresoc.v:42471$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68017,10 +68320,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42177$1877_Y + connect \Y $and$libresoc.v:42471$1879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42180$1880 + cell $and $and$libresoc.v:42474$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68028,10 +68331,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42180$1880_Y + connect \Y $and$libresoc.v:42474$1882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42182$1882 + cell $and $and$libresoc.v:42476$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68039,10 +68342,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42182$1882_Y + connect \Y $and$libresoc.v:42476$1884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42183$1883 + cell $and $and$libresoc.v:42477$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68050,10 +68353,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42183$1883_Y + connect \Y $and$libresoc.v:42477$1885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42187$1887 + cell $and $and$libresoc.v:42481$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68061,10 +68364,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42187$1887_Y + connect \Y $and$libresoc.v:42481$1889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42191$1891 + cell $and $and$libresoc.v:42485$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68072,10 +68375,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42191$1891_Y + connect \Y $and$libresoc.v:42485$1893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42192$1892 + cell $and $and$libresoc.v:42486$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68083,10 +68386,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42192$1892_Y + connect \Y $and$libresoc.v:42486$1894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42195$1895 + cell $and $and$libresoc.v:42489$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68094,10 +68397,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42195$1895_Y + connect \Y $and$libresoc.v:42489$1897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42198$1898 + cell $and $and$libresoc.v:42492$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68105,10 +68408,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42198$1898_Y + connect \Y $and$libresoc.v:42492$1900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42199$1899 + cell $and $and$libresoc.v:42493$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68116,10 +68419,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42199$1899_Y + connect \Y $and$libresoc.v:42493$1901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42202$1902 + cell $and $and$libresoc.v:42496$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68127,10 +68430,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42202$1902_Y + connect \Y $and$libresoc.v:42496$1904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42205$1905 + cell $and $and$libresoc.v:42499$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68138,10 +68441,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42205$1905_Y + connect \Y $and$libresoc.v:42499$1907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42206$1906 + cell $and $and$libresoc.v:42500$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68149,10 +68452,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42206$1906_Y + connect \Y $and$libresoc.v:42500$1908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42209$1909 + cell $and $and$libresoc.v:42503$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68160,10 +68463,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42209$1909_Y + connect \Y $and$libresoc.v:42503$1911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42212$1912 + cell $and $and$libresoc.v:42506$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68171,10 +68474,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42212$1912_Y + connect \Y $and$libresoc.v:42506$1914_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42217$1917 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42511$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68182,32 +68485,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42217$1917_Y + connect \Y $and$libresoc.v:42511$1919_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42218$1918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42512$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$347 + connect \A \$352 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42218$1918_Y + connect \Y $and$libresoc.v:42512$1920_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42220$1920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42514$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$349 - connect \B \$351 - connect \Y $and$libresoc.v:42220$1920_Y + connect \A \$354 + connect \B \$356 + connect \Y $and$libresoc.v:42514$1922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42221$1921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42515$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68215,10 +68518,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [0] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42221$1921_Y + connect \Y $and$libresoc.v:42515$1923_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42223$1923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42517$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68226,32 +68529,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42223$1923_Y + connect \Y $and$libresoc.v:42517$1925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42224$1924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42518$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$359 + connect \A \$364 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42224$1924_Y + connect \Y $and$libresoc.v:42518$1926_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42226$1926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42520$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$361 - connect \B \$363 - connect \Y $and$libresoc.v:42226$1926_Y + connect \A \$366 + connect \B \$368 + connect \Y $and$libresoc.v:42520$1928_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42227$1927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42521$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68259,10 +68562,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [1] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42227$1927_Y + connect \Y $and$libresoc.v:42521$1929_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42229$1929 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42523$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68270,32 +68573,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42229$1929_Y + connect \Y $and$libresoc.v:42523$1931_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42230$1930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42524$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$371 + connect \A \$376 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42230$1930_Y + connect \Y $and$libresoc.v:42524$1932_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42232$1932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42526$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$373 - connect \B \$375 - connect \Y $and$libresoc.v:42232$1932_Y + connect \A \$378 + connect \B \$380 + connect \Y $and$libresoc.v:42526$1934_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42233$1933 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42527$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68303,10 +68606,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [2] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42233$1933_Y + connect \Y $and$libresoc.v:42527$1935_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42235$1935 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42529$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68314,32 +68617,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42235$1935_Y + connect \Y $and$libresoc.v:42529$1937_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42236$1936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42530$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$383 + connect \A \$388 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42236$1936_Y + connect \Y $and$libresoc.v:42530$1938_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42238$1938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42532$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$385 - connect \B \$387 - connect \Y $and$libresoc.v:42238$1938_Y + connect \A \$390 + connect \B \$392 + connect \Y $and$libresoc.v:42532$1940_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42239$1939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42533$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68347,10 +68650,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [3] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42239$1939_Y + connect \Y $and$libresoc.v:42533$1941_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42241$1941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42535$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68358,32 +68661,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42241$1941_Y + connect \Y $and$libresoc.v:42535$1943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42242$1942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42536$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$395 + connect \A \$400 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42242$1942_Y + connect \Y $and$libresoc.v:42536$1944_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42244$1944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42538$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$397 - connect \B \$399 - connect \Y $and$libresoc.v:42244$1944_Y + connect \A \$402 + connect \B \$404 + connect \Y $and$libresoc.v:42538$1946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42245$1945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42539$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68391,10 +68694,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [4] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42245$1945_Y + connect \Y $and$libresoc.v:42539$1947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42247$1947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42541$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68402,32 +68705,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42247$1947_Y + connect \Y $and$libresoc.v:42541$1949_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42248$1948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42542$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$407 + connect \A \$412 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42248$1948_Y + connect \Y $and$libresoc.v:42542$1950_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42250$1950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42544$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$409 - connect \B \$411 - connect \Y $and$libresoc.v:42250$1950_Y + connect \A \$414 + connect \B \$416 + connect \Y $and$libresoc.v:42544$1952_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42251$1951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42545$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68435,10 +68738,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [5] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42251$1951_Y + connect \Y $and$libresoc.v:42545$1953_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42253$1953 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42547$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68446,32 +68749,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42253$1953_Y + connect \Y $and$libresoc.v:42547$1955_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42254$1954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42548$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$419 + connect \A \$424 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42254$1954_Y + connect \Y $and$libresoc.v:42548$1956_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42256$1956 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42550$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$421 - connect \B \$423 - connect \Y $and$libresoc.v:42256$1956_Y + connect \A \$426 + connect \B \$428 + connect \Y $and$libresoc.v:42550$1958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42257$1957 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42551$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68479,10 +68782,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [6] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42257$1957_Y + connect \Y $and$libresoc.v:42551$1959_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42259$1959 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42553$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68490,32 +68793,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42259$1959_Y + connect \Y $and$libresoc.v:42553$1961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42260$1960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42554$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$431 + connect \A \$436 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42260$1960_Y + connect \Y $and$libresoc.v:42554$1962_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42262$1962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42556$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$433 - connect \B \$435 - connect \Y $and$libresoc.v:42262$1962_Y + connect \A \$438 + connect \B \$440 + connect \Y $and$libresoc.v:42556$1964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42263$1963 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42557$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68523,10 +68826,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [7] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42263$1963_Y + connect \Y $and$libresoc.v:42557$1965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42265$1965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42559$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68534,32 +68837,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42265$1965_Y + connect \Y $and$libresoc.v:42559$1967_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42266$1966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42560$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$443 + connect \A \$448 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42266$1966_Y + connect \Y $and$libresoc.v:42560$1968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42268$1968 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42562$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$445 - connect \B \$447 - connect \Y $and$libresoc.v:42268$1968_Y + connect \A \$450 + connect \B \$452 + connect \Y $and$libresoc.v:42562$1970_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42269$1969 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42563$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68567,10 +68870,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [8] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42269$1969_Y + connect \Y $and$libresoc.v:42563$1971_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42280$1980 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42574$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68578,32 +68881,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42280$1980_Y + connect \Y $and$libresoc.v:42574$1982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42281$1981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42575$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$474 + connect \A \$479 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42281$1981_Y + connect \Y $and$libresoc.v:42575$1983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42283$1983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42577$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$476 - connect \B \$478 - connect \Y $and$libresoc.v:42283$1983_Y + connect \A \$481 + connect \B \$483 + connect \Y $and$libresoc.v:42577$1985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42284$1984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42578$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68611,10 +68914,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [0] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42284$1984_Y + connect \Y $and$libresoc.v:42578$1986_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42286$1986 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42580$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68622,32 +68925,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42286$1986_Y + connect \Y $and$libresoc.v:42580$1988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42287$1987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42581$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$486 + connect \A \$491 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42287$1987_Y + connect \Y $and$libresoc.v:42581$1989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42289$1989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42583$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$488 - connect \B \$490 - connect \Y $and$libresoc.v:42289$1989_Y + connect \A \$493 + connect \B \$495 + connect \Y $and$libresoc.v:42583$1991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42290$1990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42584$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68655,10 +68958,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [1] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42290$1990_Y + connect \Y $and$libresoc.v:42584$1992_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42292$1992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42586$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68666,32 +68969,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42292$1992_Y + connect \Y $and$libresoc.v:42586$1994_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42293$1993 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42587$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$498 + connect \A \$503 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42293$1993_Y + connect \Y $and$libresoc.v:42587$1995_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42295$1995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42589$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$500 - connect \B \$502 - connect \Y $and$libresoc.v:42295$1995_Y + connect \A \$505 + connect \B \$507 + connect \Y $and$libresoc.v:42589$1997_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42296$1996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42590$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68699,10 +69002,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [2] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42296$1996_Y + connect \Y $and$libresoc.v:42590$1998_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42298$1998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42592$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68710,32 +69013,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42298$1998_Y + connect \Y $and$libresoc.v:42592$2000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42299$1999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42593$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$510 + connect \A \$515 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42299$1999_Y + connect \Y $and$libresoc.v:42593$2001_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42301$2001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42595$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$512 - connect \B \$514 - connect \Y $and$libresoc.v:42301$2001_Y + connect \A \$517 + connect \B \$519 + connect \Y $and$libresoc.v:42595$2003_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42302$2002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42596$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68743,10 +69046,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [3] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42302$2002_Y + connect \Y $and$libresoc.v:42596$2004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42304$2004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42598$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68754,32 +69057,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42304$2004_Y + connect \Y $and$libresoc.v:42598$2006_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42305$2005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42599$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$522 + connect \A \$527 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42305$2005_Y + connect \Y $and$libresoc.v:42599$2007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42307$2007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42601$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$524 - connect \B \$526 - connect \Y $and$libresoc.v:42307$2007_Y + connect \A \$529 + connect \B \$531 + connect \Y $and$libresoc.v:42601$2009_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42308$2008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42602$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68787,10 +69090,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [4] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42308$2008_Y + connect \Y $and$libresoc.v:42602$2010_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42310$2010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42604$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68798,32 +69101,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42310$2010_Y + connect \Y $and$libresoc.v:42604$2012_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42311$2011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42605$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$534 + connect \A \$539 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42311$2011_Y + connect \Y $and$libresoc.v:42605$2013_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42313$2013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42607$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$536 - connect \B \$538 - connect \Y $and$libresoc.v:42313$2013_Y + connect \A \$541 + connect \B \$543 + connect \Y $and$libresoc.v:42607$2015_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42314$2014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42608$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68831,10 +69134,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [5] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42314$2014_Y + connect \Y $and$libresoc.v:42608$2016_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42316$2016 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42610$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68842,32 +69145,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42316$2016_Y + connect \Y $and$libresoc.v:42610$2018_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42317$2017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42611$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$546 + connect \A \$551 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42317$2017_Y + connect \Y $and$libresoc.v:42611$2019_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42319$2019 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42613$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$548 - connect \B \$550 - connect \Y $and$libresoc.v:42319$2019_Y + connect \A \$553 + connect \B \$555 + connect \Y $and$libresoc.v:42613$2021_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42320$2020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42614$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68875,10 +69178,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [6] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42320$2020_Y + connect \Y $and$libresoc.v:42614$2022_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42322$2022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42616$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68886,32 +69189,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42322$2022_Y + connect \Y $and$libresoc.v:42616$2024_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42323$2023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42617$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$558 + connect \A \$563 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42323$2023_Y + connect \Y $and$libresoc.v:42617$2025_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42325$2025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42619$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$560 - connect \B \$562 - connect \Y $and$libresoc.v:42325$2025_Y + connect \A \$565 + connect \B \$567 + connect \Y $and$libresoc.v:42619$2027_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42326$2026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42620$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68919,10 +69222,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [7] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42326$2026_Y + connect \Y $and$libresoc.v:42620$2028_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42336$2036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42630$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68930,32 +69233,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42336$2036_Y + connect \Y $and$libresoc.v:42630$2038_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42337$2037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42631$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$587 + connect \A \$592 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42337$2037_Y + connect \Y $and$libresoc.v:42631$2039_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42339$2039 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42633$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$589 - connect \B \$591 - connect \Y $and$libresoc.v:42339$2039_Y + connect \A \$594 + connect \B \$596 + connect \Y $and$libresoc.v:42633$2041_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42340$2040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42634$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68963,10 +69266,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [0] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42340$2040_Y + connect \Y $and$libresoc.v:42634$2042_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42342$2042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42636$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68974,32 +69277,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [2] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42342$2042_Y + connect \Y $and$libresoc.v:42636$2044_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42343$2043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42637$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$599 + connect \A \$604 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42343$2043_Y + connect \Y $and$libresoc.v:42637$2045_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42345$2045 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42639$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$601 - connect \B \$603 - connect \Y $and$libresoc.v:42345$2045_Y + connect \A \$606 + connect \B \$608 + connect \Y $and$libresoc.v:42639$2047_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42346$2046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42640$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69007,10 +69310,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [1] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42346$2046_Y + connect \Y $and$libresoc.v:42640$2048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42350$2050 + cell $and $and$libresoc.v:42644$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69018,10 +69321,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42350$2050_Y + connect \Y $and$libresoc.v:42644$2052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42351$2051 + cell $and $and$libresoc.v:42645$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69029,10 +69332,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42351$2051_Y + connect \Y $and$libresoc.v:42645$2053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42354$2054 + cell $and $and$libresoc.v:42648$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69040,10 +69343,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42354$2054_Y + connect \Y $and$libresoc.v:42648$2056_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42356$2056 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42650$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69051,32 +69354,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42356$2056_Y + connect \Y $and$libresoc.v:42650$2058_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42357$2057 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42651$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$628 + connect \A \$633 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42357$2057_Y + connect \Y $and$libresoc.v:42651$2059_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42359$2059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42653$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$630 - connect \B \$632 - connect \Y $and$libresoc.v:42359$2059_Y + connect \A \$635 + connect \B \$637 + connect \Y $and$libresoc.v:42653$2061_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42360$2060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42654$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69084,10 +69387,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42360$2060_Y + connect \Y $and$libresoc.v:42654$2062_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42362$2062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42656$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69095,32 +69398,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [2] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42362$2062_Y + connect \Y $and$libresoc.v:42656$2064_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42363$2063 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42657$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$640 + connect \A \$645 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42363$2063_Y + connect \Y $and$libresoc.v:42657$2065_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42365$2065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42659$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$642 - connect \B \$644 - connect \Y $and$libresoc.v:42365$2065_Y + connect \A \$647 + connect \B \$649 + connect \Y $and$libresoc.v:42659$2067_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42366$2066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42660$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69128,10 +69431,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42366$2066_Y + connect \Y $and$libresoc.v:42660$2068_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42368$2068 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42662$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69139,32 +69442,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42368$2068_Y + connect \Y $and$libresoc.v:42662$2070_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42369$2069 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42663$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$652 + connect \A \$657 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42369$2069_Y + connect \Y $and$libresoc.v:42663$2071_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42371$2071 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42665$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$654 - connect \B \$656 - connect \Y $and$libresoc.v:42371$2071_Y + connect \A \$659 + connect \B \$661 + connect \Y $and$libresoc.v:42665$2073_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42372$2072 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42666$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69172,10 +69475,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42372$2072_Y + connect \Y $and$libresoc.v:42666$2074_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42374$2074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42668$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69183,32 +69486,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42374$2074_Y + connect \Y $and$libresoc.v:42668$2076_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42375$2075 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42669$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$664 + connect \A \$669 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42375$2075_Y + connect \Y $and$libresoc.v:42669$2077_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42377$2077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42671$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$666 - connect \B \$668 - connect \Y $and$libresoc.v:42377$2077_Y + connect \A \$671 + connect \B \$673 + connect \Y $and$libresoc.v:42671$2079_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42378$2078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42672$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69216,10 +69519,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42378$2078_Y + connect \Y $and$libresoc.v:42672$2080_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42380$2080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42674$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69227,32 +69530,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42380$2080_Y + connect \Y $and$libresoc.v:42674$2082_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42381$2081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42675$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$676 + connect \A \$681 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42381$2081_Y + connect \Y $and$libresoc.v:42675$2083_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42383$2083 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42677$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$678 - connect \B \$680 - connect \Y $and$libresoc.v:42383$2083_Y + connect \A \$683 + connect \B \$685 + connect \Y $and$libresoc.v:42677$2085_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42384$2084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42678$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69260,10 +69563,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42384$2084_Y + connect \Y $and$libresoc.v:42678$2086_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42386$2086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42680$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69271,32 +69574,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [3] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42386$2086_Y + connect \Y $and$libresoc.v:42680$2088_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42387$2087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42681$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$688 + connect \A \$693 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42387$2087_Y + connect \Y $and$libresoc.v:42681$2089_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42389$2089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42683$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$690 - connect \B \$692 - connect \Y $and$libresoc.v:42389$2089_Y + connect \A \$695 + connect \B \$697 + connect \Y $and$libresoc.v:42683$2091_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42390$2090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42684$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69304,10 +69607,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [5] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42390$2090_Y + connect \Y $and$libresoc.v:42684$2092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42399$2100 + cell $and $and$libresoc.v:42693$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69315,10 +69618,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42399$2100_Y + connect \Y $and$libresoc.v:42693$2102_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42402$2103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42696$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69326,32 +69629,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42402$2103_Y + connect \Y $and$libresoc.v:42696$2105_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42403$2104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42697$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$720 + connect \A \$725 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42403$2104_Y + connect \Y $and$libresoc.v:42697$2106_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42405$2106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42699$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$722 - connect \B \$724 - connect \Y $and$libresoc.v:42405$2106_Y + connect \A \$727 + connect \B \$729 + connect \Y $and$libresoc.v:42699$2108_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42406$2107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42700$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69359,10 +69662,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42406$2107_Y + connect \Y $and$libresoc.v:42700$2109_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42408$2109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42702$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69370,32 +69673,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42408$2109_Y + connect \Y $and$libresoc.v:42702$2111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42409$2110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42703$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$732 + connect \A \$737 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42409$2110_Y + connect \Y $and$libresoc.v:42703$2112_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42411$2112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42705$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$734 - connect \B \$736 - connect \Y $and$libresoc.v:42411$2112_Y + connect \A \$739 + connect \B \$741 + connect \Y $and$libresoc.v:42705$2114_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42412$2113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42706$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69403,10 +69706,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42412$2113_Y + connect \Y $and$libresoc.v:42706$2115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42414$2115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42708$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69414,32 +69717,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [4] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42414$2115_Y + connect \Y $and$libresoc.v:42708$2117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42415$2116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42709$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$744 + connect \A \$749 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42415$2116_Y + connect \Y $and$libresoc.v:42709$2118_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42417$2118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42711$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$746 - connect \B \$748 - connect \Y $and$libresoc.v:42417$2118_Y + connect \A \$751 + connect \B \$753 + connect \Y $and$libresoc.v:42711$2120_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42418$2119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42712$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69447,10 +69750,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42418$2119_Y + connect \Y $and$libresoc.v:42712$2121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42423$2125 + cell $and $and$libresoc.v:42717$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69458,10 +69761,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42423$2125_Y + connect \Y $and$libresoc.v:42717$2127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42424$2126 + cell $and $and$libresoc.v:42718$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69469,10 +69772,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42424$2126_Y + connect \Y $and$libresoc.v:42718$2128_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42427$2129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42721$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69480,32 +69783,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42427$2129_Y + connect \Y $and$libresoc.v:42721$2131_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42428$2130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42722$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$770 + connect \A \$775 connect \B \rdflag_XER_xer_ov_0 - connect \Y $and$libresoc.v:42428$2130_Y + connect \Y $and$libresoc.v:42722$2132_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42430$2132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42724$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$772 - connect \B \$774 - connect \Y $and$libresoc.v:42430$2132_Y + connect \A \$777 + connect \B \$779 + connect \Y $and$libresoc.v:42724$2134_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42431$2133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42725$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69513,10 +69816,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42431$2133_Y + connect \Y $and$libresoc.v:42725$2135_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42433$2135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42727$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69524,32 +69827,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42433$2135_Y + connect \Y $and$libresoc.v:42727$2137_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42434$2136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42728$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$782 + connect \A \$787 connect \B \rdflag_CR_full_cr_0 - connect \Y $and$libresoc.v:42434$2136_Y + connect \Y $and$libresoc.v:42728$2138_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42436$2138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42730$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$784 - connect \B \$786 - connect \Y $and$libresoc.v:42436$2138_Y + connect \A \$789 + connect \B \$791 + connect \Y $and$libresoc.v:42730$2140_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42437$2139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42731$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69557,10 +69860,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42437$2139_Y + connect \Y $and$libresoc.v:42731$2141_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42439$2141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42733$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69568,32 +69871,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [3] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42439$2141_Y + connect \Y $and$libresoc.v:42733$2143_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42440$2142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42734$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$794 + connect \A \$799 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42440$2142_Y + connect \Y $and$libresoc.v:42734$2144_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42442$2144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42736$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$796 - connect \B \$798 - connect \Y $and$libresoc.v:42442$2144_Y + connect \A \$801 + connect \B \$803 + connect \Y $and$libresoc.v:42736$2146_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42443$2145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42737$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69601,10 +69904,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42443$2145_Y + connect \Y $and$libresoc.v:42737$2147_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42447$2149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42741$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69612,32 +69915,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42447$2149_Y + connect \Y $and$libresoc.v:42741$2151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42448$2150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42742$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$810 + connect \A \$815 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42448$2150_Y + connect \Y $and$libresoc.v:42742$2152_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42450$2152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42744$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$812 - connect \B \$814 - connect \Y $and$libresoc.v:42450$2152_Y + connect \A \$817 + connect \B \$819 + connect \Y $and$libresoc.v:42744$2154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42451$2153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42745$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69645,10 +69948,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42451$2153_Y + connect \Y $and$libresoc.v:42745$2155_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42456$2158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42750$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69656,32 +69959,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [4] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42456$2158_Y + connect \Y $and$libresoc.v:42750$2160_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42457$2159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42751$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$829 + connect \A \$834 connect \B \rdflag_CR_cr_b_0 - connect \Y $and$libresoc.v:42457$2159_Y + connect \Y $and$libresoc.v:42751$2161_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42459$2161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42753$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$831 - connect \B \$833 - connect \Y $and$libresoc.v:42459$2161_Y + connect \A \$836 + connect \B \$838 + connect \Y $and$libresoc.v:42753$2163_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42460$2162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42754$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69689,10 +69992,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $and$libresoc.v:42460$2162_Y + connect \Y $and$libresoc.v:42754$2164_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42464$2166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42758$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69700,32 +70003,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [5] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42464$2166_Y + connect \Y $and$libresoc.v:42758$2168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42465$2167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42759$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$845 + connect \A \$850 connect \B \rdflag_CR_cr_c_0 - connect \Y $and$libresoc.v:42465$2167_Y + connect \Y $and$libresoc.v:42759$2169_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42467$2169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42761$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$847 - connect \B \$849 - connect \Y $and$libresoc.v:42467$2169_Y + connect \A \$852 + connect \B \$854 + connect \Y $and$libresoc.v:42761$2171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42468$2170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42762$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69733,10 +70036,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $and$libresoc.v:42468$2170_Y + connect \Y $and$libresoc.v:42762$2172_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42472$2174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42766$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69744,32 +70047,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42472$2174_Y + connect \Y $and$libresoc.v:42766$2176_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42473$2175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42767$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$861 + connect \A \$866 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42473$2175_Y + connect \Y $and$libresoc.v:42767$2177_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42475$2177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42769$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$863 - connect \B \$865 - connect \Y $and$libresoc.v:42475$2177_Y + connect \A \$868 + connect \B \$870 + connect \Y $and$libresoc.v:42769$2179_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42476$2178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42770$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69777,10 +70080,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42476$2178_Y + connect \Y $and$libresoc.v:42770$2180_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42478$2180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42772$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69788,32 +70091,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42478$2180_Y + connect \Y $and$libresoc.v:42772$2182_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42479$2181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42773$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$873 + connect \A \$878 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42479$2181_Y + connect \Y $and$libresoc.v:42773$2183_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42481$2183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42775$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$875 - connect \B \$877 - connect \Y $and$libresoc.v:42481$2183_Y + connect \A \$880 + connect \B \$882 + connect \Y $and$libresoc.v:42775$2185_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42482$2184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42776$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69821,10 +70124,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42482$2184_Y + connect \Y $and$libresoc.v:42776$2186_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42484$2186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42778$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69832,32 +70135,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42484$2186_Y + connect \Y $and$libresoc.v:42778$2188_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42485$2187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42779$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$885 + connect \A \$890 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42485$2187_Y + connect \Y $and$libresoc.v:42779$2189_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42487$2189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42781$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$887 - connect \B \$889 - connect \Y $and$libresoc.v:42487$2189_Y + connect \A \$892 + connect \B \$894 + connect \Y $and$libresoc.v:42781$2191_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42488$2190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42782$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69865,10 +70168,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42488$2190_Y + connect \Y $and$libresoc.v:42782$2192_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42493$2195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42787$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69876,32 +70179,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42493$2195_Y + connect \Y $and$libresoc.v:42787$2197_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42494$2196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42788$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$903 + connect \A \$908 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42494$2196_Y + connect \Y $and$libresoc.v:42788$2198_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42496$2198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42790$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$905 - connect \B \$907 - connect \Y $and$libresoc.v:42496$2198_Y + connect \A \$910 + connect \B \$912 + connect \Y $and$libresoc.v:42790$2200_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42497$2199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42791$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69909,10 +70212,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [0] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42497$2199_Y + connect \Y $and$libresoc.v:42791$2201_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42499$2201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42793$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69920,32 +70223,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42499$2201_Y + connect \Y $and$libresoc.v:42793$2203_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42500$2202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42794$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$915 + connect \A \$920 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42500$2202_Y + connect \Y $and$libresoc.v:42794$2204_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42502$2204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42796$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$917 - connect \B \$919 - connect \Y $and$libresoc.v:42502$2204_Y + connect \A \$922 + connect \B \$924 + connect \Y $and$libresoc.v:42796$2206_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42503$2205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42797$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69953,10 +70256,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [1] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42503$2205_Y + connect \Y $and$libresoc.v:42797$2207_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42507$2209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42801$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69964,32 +70267,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42507$2209_Y + connect \Y $and$libresoc.v:42801$2211_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42508$2210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" + cell $and $and$libresoc.v:42802$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$931 + connect \A \$936 connect \B \rdflag_SPR_spr1_0 - connect \Y $and$libresoc.v:42508$2210_Y + connect \Y $and$libresoc.v:42802$2212_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42510$2212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42804$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$933 - connect \B \$935 - connect \Y $and$libresoc.v:42510$2212_Y + connect \A \$938 + connect \B \$940 + connect \Y $and$libresoc.v:42804$2214_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42511$2213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" + cell $and $and$libresoc.v:42805$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69997,10 +70300,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42511$2213_Y + connect \Y $and$libresoc.v:42805$2215_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42514$2216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42808$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70008,10 +70311,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42514$2216_Y + connect \Y $and$libresoc.v:42808$2218_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42515$2217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42809$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70019,10 +70322,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42515$2217_Y + connect \Y $and$libresoc.v:42809$2219_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42516$2218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42810$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70030,10 +70333,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42516$2218_Y + connect \Y $and$libresoc.v:42810$2220_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42517$2219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42811$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70041,10 +70344,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42517$2219_Y + connect \Y $and$libresoc.v:42811$2221_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42518$2220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42812$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70052,10 +70355,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42518$2220_Y + connect \Y $and$libresoc.v:42812$2222_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42519$2221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42813$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70063,10 +70366,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42519$2221_Y + connect \Y $and$libresoc.v:42813$2223_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42520$2222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42814$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70074,10 +70377,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42520$2222_Y + connect \Y $and$libresoc.v:42814$2224_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42521$2223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42815$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70085,10 +70388,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42521$2223_Y + connect \Y $and$libresoc.v:42815$2225_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42522$2224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42816$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70096,10 +70399,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42522$2224_Y + connect \Y $and$libresoc.v:42816$2226_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42523$2225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42817$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70107,10 +70410,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42523$2225_Y + connect \Y $and$libresoc.v:42817$2227_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42524$2226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $and$libresoc.v:42818$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70118,10 +70421,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42524$2226_Y + connect \Y $and$libresoc.v:42818$2228_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42525$2227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42819$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70129,21 +70432,21 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42525$2227_Y + connect \Y $and$libresoc.v:42819$2229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42527$2229 + cell $and $and$libresoc.v:42821$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick - connect \B \$969 - connect \Y $and$libresoc.v:42527$2229_Y + connect \B \$974 + connect \Y $and$libresoc.v:42821$2231_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42528$2230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" + cell $and $and$libresoc.v:42822$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70151,10 +70454,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42528$2230_Y + connect \Y $and$libresoc.v:42822$2232_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42530$2232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" + cell $and $and$libresoc.v:42824$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70162,10 +70465,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$92 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42530$2232_Y + connect \Y $and$libresoc.v:42824$2234_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42531$2233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" + cell $and $and$libresoc.v:42825$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70173,43 +70476,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42531$2233_Y + connect \Y $and$libresoc.v:42825$2235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42533$2235 + cell $and $and$libresoc.v:42827$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$983 - connect \B \$988 - connect \Y $and$libresoc.v:42533$2235_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42534$2236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$983 - connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42534$2236_Y + connect \A \wr_pick$988 + connect \B \$993 + connect \Y $and$libresoc.v:42827$2237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42157$1857 + cell $eq $eq$libresoc.v:42451$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$226 + connect \A \$231 connect \B 1'1 - connect \Y $eq$libresoc.v:42157$1857_Y + connect \Y $eq$libresoc.v:42451$1859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42161$1861 + cell $eq $eq$libresoc.v:42455$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70217,54 +70509,54 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42161$1861_Y + connect \Y $eq$libresoc.v:42455$1863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42163$1863 + cell $eq $eq$libresoc.v:42457$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$238 + connect \A \$243 connect \B 3'100 - connect \Y $eq$libresoc.v:42163$1863_Y + connect \Y $eq$libresoc.v:42457$1865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42171$1871 + cell $eq $eq$libresoc.v:42465$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$254 + connect \A \$259 connect \B 1'1 - connect \Y $eq$libresoc.v:42171$1871_Y + connect \Y $eq$libresoc.v:42465$1873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42178$1878 + cell $eq $eq$libresoc.v:42472$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$268 + connect \A \$273 connect \B 1'1 - connect \Y $eq$libresoc.v:42178$1878_Y + connect \Y $eq$libresoc.v:42472$1880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42184$1884 + cell $eq $eq$libresoc.v:42478$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$280 + connect \A \$285 connect \B 2'10 - connect \Y $eq$libresoc.v:42184$1884_Y + connect \Y $eq$libresoc.v:42478$1886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42186$1886 + cell $eq $eq$libresoc.v:42480$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70272,54 +70564,54 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42186$1886_Y + connect \Y $eq$libresoc.v:42480$1888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42188$1888 + cell $eq $eq$libresoc.v:42482$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$288 + connect \A \$293 connect \B 3'100 - connect \Y $eq$libresoc.v:42188$1888_Y + connect \Y $eq$libresoc.v:42482$1890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42193$1893 + cell $eq $eq$libresoc.v:42487$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$298 + connect \A \$303 connect \B 1'1 - connect \Y $eq$libresoc.v:42193$1893_Y + connect \Y $eq$libresoc.v:42487$1895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42200$1900 + cell $eq $eq$libresoc.v:42494$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$312 + connect \A \$317 connect \B 1'1 - connect \Y $eq$libresoc.v:42200$1900_Y + connect \Y $eq$libresoc.v:42494$1902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42207$1907 + cell $eq $eq$libresoc.v:42501$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$326 + connect \A \$331 connect \B 1'1 - connect \Y $eq$libresoc.v:42207$1907_Y + connect \Y $eq$libresoc.v:42501$1909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42211$1911 + cell $eq $eq$libresoc.v:42505$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70327,32 +70619,32 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42211$1911_Y + connect \Y $eq$libresoc.v:42505$1913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42213$1913 + cell $eq $eq$libresoc.v:42507$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$338 + connect \A \$343 connect \B 3'100 - connect \Y $eq$libresoc.v:42213$1913_Y + connect \Y $eq$libresoc.v:42507$1915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42352$2052 + cell $eq $eq$libresoc.v:42646$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$618 + connect \A \$623 connect \B 1'1 - connect \Y $eq$libresoc.v:42352$2052_Y + connect \Y $eq$libresoc.v:42646$2054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42398$2099 + cell $eq $eq$libresoc.v:42692$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70360,88 +70652,88 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42398$2099_Y + connect \Y $eq$libresoc.v:42692$2101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42400$2101 + cell $eq $eq$libresoc.v:42694$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$714 + connect \A \$719 connect \B 3'100 - connect \Y $eq$libresoc.v:42400$2101_Y + connect \Y $eq$libresoc.v:42694$2103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42425$2127 + cell $eq $eq$libresoc.v:42719$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$764 + connect \A \$769 connect \B 2'10 - connect \Y $eq$libresoc.v:42425$2127_Y + connect \Y $eq$libresoc.v:42719$2129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:41982$1677 + cell $pos $extend$libresoc.v:42276$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$1442 - connect \Y $extend$libresoc.v:41982$1677_Y + connect \A \$1447 + connect \Y $extend$libresoc.v:42276$1679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42048$1744 + cell $pos $extend$libresoc.v:42342$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 - connect \A \$1606 - connect \Y $extend$libresoc.v:42048$1744_Y + connect \A \$1611 + connect \Y $extend$libresoc.v:42342$1746_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42052$1749 + cell $pos $extend$libresoc.v:42346$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$1614 - connect \Y $extend$libresoc.v:42052$1749_Y + connect \A \$1619 + connect \Y $extend$libresoc.v:42346$1751_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $extend$libresoc.v:42116$1814 + cell $pos $extend$libresoc.v:42410$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$1773 - connect \Y $extend$libresoc.v:42116$1814_Y + connect \A \$1778 + connect \Y $extend$libresoc.v:42410$1816_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $pos $extend$libresoc.v:42126$1825 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $pos $extend$libresoc.v:42418$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \addr_en$1791 - connect \Y $extend$libresoc.v:42126$1825_Y + connect \A \addr_en$1796 + connect \Y $extend$libresoc.v:42418$1825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42397$2097 + cell $pos $extend$libresoc.v:42691$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$709 - connect \Y $extend$libresoc.v:42397$2097_Y + connect \A \$714 + connect \Y $extend$libresoc.v:42691$2099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42422$2123 + cell $pos $extend$libresoc.v:42716$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$759 - connect \Y $extend$libresoc.v:42422$2123_Y + connect \A \$764 + connect \Y $extend$libresoc.v:42716$2125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" - cell $ne $ne$libresoc.v:42152$1852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + cell $ne $ne$libresoc.v:42446$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70449,10 +70741,10 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42152$1852_Y + connect \Y $ne$libresoc.v:42446$1854_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" - cell $ne $ne$libresoc.v:42154$1854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + cell $ne $ne$libresoc.v:42448$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70460,706 +70752,706 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42154$1854_Y + connect \Y $ne$libresoc.v:42448$1856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41813$1508 + cell $not $not$libresoc.v:42107$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1005 - connect \Y $not$libresoc.v:41813$1508_Y + connect \A \wr_pick_dly$1010 + connect \Y $not$libresoc.v:42107$1510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41819$1514 + cell $not $not$libresoc.v:42113$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1026 - connect \Y $not$libresoc.v:41819$1514_Y + connect \A \wr_pick_dly$1031 + connect \Y $not$libresoc.v:42113$1516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41825$1520 + cell $not $not$libresoc.v:42119$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1044 - connect \Y $not$libresoc.v:41825$1520_Y + connect \A \wr_pick_dly$1049 + connect \Y $not$libresoc.v:42119$1522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41831$1526 + cell $not $not$libresoc.v:42125$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1066 - connect \Y $not$libresoc.v:41831$1526_Y + connect \A \wr_pick_dly$1071 + connect \Y $not$libresoc.v:42125$1528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41837$1532 + cell $not $not$libresoc.v:42131$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1086 - connect \Y $not$libresoc.v:41837$1532_Y + connect \A \wr_pick_dly$1091 + connect \Y $not$libresoc.v:42131$1534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41843$1538 + cell $not $not$libresoc.v:42137$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1106 - connect \Y $not$libresoc.v:41843$1538_Y + connect \A \wr_pick_dly$1111 + connect \Y $not$libresoc.v:42137$1540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41849$1544 + cell $not $not$libresoc.v:42143$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1125 - connect \Y $not$libresoc.v:41849$1544_Y + connect \A \wr_pick_dly$1130 + connect \Y $not$libresoc.v:42143$1546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41855$1550 + cell $not $not$libresoc.v:42149$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1143 - connect \Y $not$libresoc.v:41855$1550_Y + connect \A \wr_pick_dly$1148 + connect \Y $not$libresoc.v:42149$1552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41889$1584 + cell $not $not$libresoc.v:42183$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1217 - connect \Y $not$libresoc.v:41889$1584_Y + connect \A \wr_pick_dly$1222 + connect \Y $not$libresoc.v:42183$1586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41901$1596 + cell $not $not$libresoc.v:42195$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1245 - connect \Y $not$libresoc.v:41901$1596_Y + connect \A \wr_pick_dly$1250 + connect \Y $not$libresoc.v:42195$1598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41909$1604 + cell $not $not$libresoc.v:42203$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1265 - connect \Y $not$libresoc.v:41909$1604_Y + connect \A \wr_pick_dly$1270 + connect \Y $not$libresoc.v:42203$1606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41917$1612 + cell $not $not$libresoc.v:42211$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1285 - connect \Y $not$libresoc.v:41917$1612_Y + connect \A \wr_pick_dly$1290 + connect \Y $not$libresoc.v:42211$1614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41925$1620 + cell $not $not$libresoc.v:42219$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1305 - connect \Y $not$libresoc.v:41925$1620_Y + connect \A \wr_pick_dly$1310 + connect \Y $not$libresoc.v:42219$1622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41933$1628 + cell $not $not$libresoc.v:42227$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1325 - connect \Y $not$libresoc.v:41933$1628_Y + connect \A \wr_pick_dly$1330 + connect \Y $not$libresoc.v:42227$1630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41941$1636 + cell $not $not$libresoc.v:42235$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1345 - connect \Y $not$libresoc.v:41941$1636_Y + connect \A \wr_pick_dly$1350 + connect \Y $not$libresoc.v:42235$1638_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41962$1657 + cell $not $not$libresoc.v:42256$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1392 - connect \Y $not$libresoc.v:41962$1657_Y + connect \A \wr_pick_dly$1397 + connect \Y $not$libresoc.v:42256$1659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41968$1663 + cell $not $not$libresoc.v:42262$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1408 - connect \Y $not$libresoc.v:41968$1663_Y + connect \A \wr_pick_dly$1413 + connect \Y $not$libresoc.v:42262$1665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41974$1669 + cell $not $not$libresoc.v:42268$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1424 - connect \Y $not$libresoc.v:41974$1669_Y + connect \A \wr_pick_dly$1429 + connect \Y $not$libresoc.v:42268$1671_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41989$1685 + cell $not $not$libresoc.v:42283$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1458 - connect \Y $not$libresoc.v:41989$1685_Y + connect \A \wr_pick_dly$1463 + connect \Y $not$libresoc.v:42283$1687_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41995$1691 + cell $not $not$libresoc.v:42289$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1474 - connect \Y $not$libresoc.v:41995$1691_Y + connect \A \wr_pick_dly$1479 + connect \Y $not$libresoc.v:42289$1693_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42001$1697 + cell $not $not$libresoc.v:42295$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1490 - connect \Y $not$libresoc.v:42001$1697_Y + connect \A \wr_pick_dly$1495 + connect \Y $not$libresoc.v:42295$1699_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42007$1703 + cell $not $not$libresoc.v:42301$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1506 - connect \Y $not$libresoc.v:42007$1703_Y + connect \A \wr_pick_dly$1511 + connect \Y $not$libresoc.v:42301$1705_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42023$1719 + cell $not $not$libresoc.v:42317$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1542 - connect \Y $not$libresoc.v:42023$1719_Y + connect \A \wr_pick_dly$1547 + connect \Y $not$libresoc.v:42317$1721_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42029$1725 + cell $not $not$libresoc.v:42323$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1558 - connect \Y $not$libresoc.v:42029$1725_Y + connect \A \wr_pick_dly$1563 + connect \Y $not$libresoc.v:42323$1727_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42035$1731 + cell $not $not$libresoc.v:42329$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1574 - connect \Y $not$libresoc.v:42035$1731_Y + connect \A \wr_pick_dly$1579 + connect \Y $not$libresoc.v:42329$1733_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42041$1737 + cell $not $not$libresoc.v:42335$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1590 - connect \Y $not$libresoc.v:42041$1737_Y + connect \A \wr_pick_dly$1595 + connect \Y $not$libresoc.v:42335$1739_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42060$1758 + cell $not $not$libresoc.v:42354$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1632 - connect \Y $not$libresoc.v:42060$1758_Y + connect \A \wr_pick_dly$1637 + connect \Y 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- connect \Y $not$libresoc.v:42078$1776_Y + connect \A \wr_pick_dly$1688 + connect \Y $not$libresoc.v:42372$1778_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42084$1782 + cell $not $not$libresoc.v:42378$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1699 - connect \Y $not$libresoc.v:42084$1782_Y + connect \A \wr_pick_dly$1704 + connect \Y $not$libresoc.v:42378$1784_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42104$1802 + cell $not $not$libresoc.v:42398$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1743 - connect \Y $not$libresoc.v:42104$1802_Y + connect \A \wr_pick_dly$1748 + connect \Y $not$libresoc.v:42398$1804_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42110$1808 + cell $not $not$libresoc.v:42404$1810 parameter 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connect \Y $not$libresoc.v:42704$2113_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42416$2117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42710$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_shiftrot0_2 - connect \Y $not$libresoc.v:42416$2117_Y + connect \Y $not$libresoc.v:42710$2119_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42429$2131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42723$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ov_spr0_0 - connect \Y $not$libresoc.v:42429$2131_Y + connect \Y $not$libresoc.v:42723$2133_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42435$2137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42729$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_full_cr_cr0_0 - connect \Y $not$libresoc.v:42435$2137_Y + connect \Y $not$libresoc.v:42729$2139_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42441$2143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42735$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_cr0_0 - connect \Y $not$libresoc.v:42441$2143_Y + connect \Y $not$libresoc.v:42735$2145_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42449$2151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42743$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_branch0_1 - connect \Y $not$libresoc.v:42449$2151_Y + connect \Y $not$libresoc.v:42743$2153_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42458$2160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42752$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 - connect \Y $not$libresoc.v:42458$2160_Y + connect \Y $not$libresoc.v:42752$2162_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42466$2168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42760$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 - connect \Y $not$libresoc.v:42466$2168_Y + connect \Y $not$libresoc.v:42760$2170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42474$2176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42768$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 - connect \Y $not$libresoc.v:42474$2176_Y + connect \Y $not$libresoc.v:42768$2178_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42480$2182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42774$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_1 - connect \Y $not$libresoc.v:42480$2182_Y + connect \Y $not$libresoc.v:42774$2184_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42486$2188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42780$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_spr0_2 - connect \Y $not$libresoc.v:42486$2188_Y + connect \Y $not$libresoc.v:42780$2190_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42495$2197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42789$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_branch0_0 - connect \Y $not$libresoc.v:42495$2197_Y + connect \Y $not$libresoc.v:42789$2199_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42501$2203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42795$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_trap0_1 - connect \Y $not$libresoc.v:42501$2203_Y + connect \Y $not$libresoc.v:42795$2205_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42509$2211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $not $not$libresoc.v:42803$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_SPR_spr1_spr0_0 - connect \Y $not$libresoc.v:42509$2211_Y + connect \Y $not$libresoc.v:42803$2213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42526$2228 + cell $not $not$libresoc.v:42820$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly - connect \Y $not$libresoc.v:42526$2228_Y + connect \Y $not$libresoc.v:42820$2230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42532$2234 + cell $not $not$libresoc.v:42826$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$986 - connect \Y $not$libresoc.v:42532$2234_Y + connect \A \wr_pick_dly$991 + connect \Y $not$libresoc.v:42826$2236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41859$1554 + cell $or $or$libresoc.v:42153$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71167,10 +71459,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o connect \B \fus_dest1_o$115 - connect \Y $or$libresoc.v:41859$1554_Y + connect \Y $or$libresoc.v:42153$1556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41860$1555 + cell $or $or$libresoc.v:42154$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71178,32 +71470,32 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$117 connect \B \fus_dest1_o$118 - connect \Y $or$libresoc.v:41860$1555_Y + connect \Y $or$libresoc.v:42154$1557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41861$1556 + cell $or $or$libresoc.v:42155$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o$116 - connect \B \$1157 - connect \Y $or$libresoc.v:41861$1556_Y + connect \B \$1162 + connect \Y $or$libresoc.v:42155$1558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41862$1557 + cell $or $or$libresoc.v:42156$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$1155 - connect \B \$1159 - connect \Y $or$libresoc.v:41862$1557_Y + connect \A \$1160 + connect \B \$1164 + connect \Y $or$libresoc.v:42156$1559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41863$1558 + cell $or $or$libresoc.v:42157$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71211,10 +71503,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$119 connect \B \fus_dest1_o$120 - connect \Y $or$libresoc.v:41863$1558_Y + connect \Y $or$libresoc.v:42157$1560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41864$1559 + cell $or $or$libresoc.v:42158$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 @@ -71222,241 +71514,241 @@ module \core parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } - connect \Y $or$libresoc.v:41864$1559_Y + connect \Y $or$libresoc.v:42158$1561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41865$1560 + cell $or $or$libresoc.v:42159$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 connect \A \fus_dest1_o$121 - connect \B \$1165 - connect \Y $or$libresoc.v:41865$1560_Y + connect \B \$1170 + connect \Y $or$libresoc.v:42159$1562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41866$1561 + cell $or $or$libresoc.v:42160$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A \$1163 - connect \B \$1167 - connect \Y $or$libresoc.v:41866$1561_Y + connect \A \$1168 + connect \B \$1172 + connect \Y $or$libresoc.v:42160$1563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41867$1562 + cell $or $or$libresoc.v:42161$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A \$1161 - connect \B \$1169 - connect \Y $or$libresoc.v:41867$1562_Y + connect \A \$1166 + connect \B \$1174 + connect \Y $or$libresoc.v:42161$1564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41868$1563 + cell $or $or$libresoc.v:42162$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en - connect \B \addr_en$997 - connect \Y $or$libresoc.v:41868$1563_Y + connect \B \addr_en$1002 + connect \Y $or$libresoc.v:42162$1565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41869$1564 + cell $or $or$libresoc.v:42163$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1036 - connect \B \addr_en$1058 - connect \Y $or$libresoc.v:41869$1564_Y + connect \A \addr_en$1041 + connect \B \addr_en$1063 + connect \Y $or$libresoc.v:42163$1566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41870$1565 + cell $or $or$libresoc.v:42164$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1018 - connect \B \$1176 - connect \Y $or$libresoc.v:41870$1565_Y + connect \A \addr_en$1023 + connect \B \$1181 + connect \Y $or$libresoc.v:42164$1567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41871$1566 + cell $or $or$libresoc.v:42165$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$1174 - connect \B \$1178 - connect \Y $or$libresoc.v:41871$1566_Y + connect \A \$1179 + connect \B \$1183 + connect \Y $or$libresoc.v:42165$1568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41872$1567 + cell $or $or$libresoc.v:42166$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1078 - connect \B \addr_en$1098 - connect \Y $or$libresoc.v:41872$1567_Y + connect \A \addr_en$1083 + connect \B \addr_en$1103 + connect \Y $or$libresoc.v:42166$1569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41873$1568 + cell $or $or$libresoc.v:42167$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1135 - connect \B \addr_en$1151 - connect \Y $or$libresoc.v:41873$1568_Y + connect \A \addr_en$1140 + connect \B \addr_en$1156 + connect \Y $or$libresoc.v:42167$1570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41874$1569 + cell $or $or$libresoc.v:42168$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \addr_en$1117 - connect \B \$1184 - connect \Y $or$libresoc.v:41874$1569_Y + connect \A \addr_en$1122 + connect \B \$1189 + connect \Y $or$libresoc.v:42168$1571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41875$1570 + cell $or $or$libresoc.v:42169$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$1182 - connect \B \$1186 - connect \Y $or$libresoc.v:41875$1570_Y + connect \A \$1187 + connect \B \$1191 + connect \Y $or$libresoc.v:42169$1572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41876$1571 + cell $or $or$libresoc.v:42170$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$1180 - connect \B \$1188 - connect \Y $or$libresoc.v:41876$1571_Y + connect \A \$1185 + connect \B \$1193 + connect \Y $or$libresoc.v:42170$1573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41877$1572 + cell $or $or$libresoc.v:42171$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp - connect \B \wp$994 - connect \Y $or$libresoc.v:41877$1572_Y + connect \B \wp$999 + connect \Y $or$libresoc.v:42171$1574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41878$1573 + cell $or $or$libresoc.v:42172$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1033 - connect \B \wp$1055 - connect \Y $or$libresoc.v:41878$1573_Y + connect \A \wp$1038 + connect \B \wp$1060 + connect \Y $or$libresoc.v:42172$1575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41879$1574 + cell $or $or$libresoc.v:42173$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1015 - connect \B \$1194 - connect \Y $or$libresoc.v:41879$1574_Y + connect \A \wp$1020 + connect \B \$1199 + connect \Y $or$libresoc.v:42173$1576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41880$1575 + cell $or $or$libresoc.v:42174$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1192 - connect \B \$1196 - connect \Y $or$libresoc.v:41880$1575_Y + connect \A \$1197 + connect \B \$1201 + connect \Y $or$libresoc.v:42174$1577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41881$1576 + cell $or $or$libresoc.v:42175$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1075 - connect \B \wp$1095 - connect \Y $or$libresoc.v:41881$1576_Y + connect \A \wp$1080 + connect \B \wp$1100 + connect \Y $or$libresoc.v:42175$1578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41882$1577 + cell $or $or$libresoc.v:42176$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1132 - connect \B \wp$1148 - connect \Y $or$libresoc.v:41882$1577_Y + connect \A \wp$1137 + connect \B \wp$1153 + connect \Y $or$libresoc.v:42176$1579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41883$1578 + cell $or $or$libresoc.v:42177$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1114 - connect \B \$1202 - connect \Y $or$libresoc.v:41883$1578_Y + connect \A \wp$1119 + connect \B \$1207 + connect \Y $or$libresoc.v:42177$1580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41884$1579 + cell $or $or$libresoc.v:42178$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1200 - connect \B \$1204 - connect \Y $or$libresoc.v:41884$1579_Y + connect \A \$1205 + connect \B \$1209 + connect \Y $or$libresoc.v:42178$1581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41885$1580 + cell $or $or$libresoc.v:42179$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1198 - connect \B \$1206 - connect \Y $or$libresoc.v:41885$1580_Y + connect \A \$1203 + connect \B \$1211 + connect \Y $or$libresoc.v:42179$1582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41947$1642 + cell $or $or$libresoc.v:42241$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71464,21 +71756,21 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest3_o connect \B \fus_dest2_o$128 - connect \Y $or$libresoc.v:41947$1642_Y + connect \Y $or$libresoc.v:42241$1644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41948$1643 + cell $or $or$libresoc.v:42242$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$127 - connect \B \$1360 - connect \Y $or$libresoc.v:41948$1643_Y + connect \B \$1365 + connect \Y $or$libresoc.v:42242$1645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41949$1644 + cell $or $or$libresoc.v:42243$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71486,87 +71778,87 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$130 connect \B \fus_dest2_o$131 - connect \Y $or$libresoc.v:41949$1644_Y + connect \Y $or$libresoc.v:42243$1646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41950$1645 + cell $or $or$libresoc.v:42244$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$129 - connect \B \$1364 - connect \Y $or$libresoc.v:41950$1645_Y + connect \B \$1369 + connect \Y $or$libresoc.v:42244$1647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41951$1646 + cell $or $or$libresoc.v:42245$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \$1362 - connect \B \$1366 - connect \Y $or$libresoc.v:41951$1646_Y + connect \A \$1367 + connect \B \$1371 + connect \Y $or$libresoc.v:42245$1648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41952$1647 + cell $or $or$libresoc.v:42246$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \addr_en$1273 - connect \B \addr_en$1293 - connect \Y $or$libresoc.v:41952$1647_Y + connect \A \addr_en$1278 + connect \B \addr_en$1298 + connect \Y $or$libresoc.v:42246$1649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41953$1648 + cell $or $or$libresoc.v:42247$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \addr_en$1253 - connect \B \$1371 - connect \Y $or$libresoc.v:41953$1648_Y + connect \A \addr_en$1258 + connect \B \$1376 + connect \Y $or$libresoc.v:42247$1650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41954$1649 + cell $or $or$libresoc.v:42248$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \addr_en$1333 - connect \B \addr_en$1353 - connect \Y $or$libresoc.v:41954$1649_Y + connect \A \addr_en$1338 + connect \B \addr_en$1358 + connect \Y $or$libresoc.v:42248$1651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41955$1650 + cell $or $or$libresoc.v:42249$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \addr_en$1313 - connect \B \$1375 - connect \Y $or$libresoc.v:41955$1650_Y + connect \A \addr_en$1318 + connect \B \$1380 + connect \Y $or$libresoc.v:42249$1652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41956$1651 + cell $or $or$libresoc.v:42250$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 - connect \A \$1373 - connect \B \$1377 - connect \Y $or$libresoc.v:41956$1651_Y + connect \A \$1378 + connect \B \$1382 + connect \Y $or$libresoc.v:42250$1653_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41978$1673 + cell $or $or$libresoc.v:42272$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71574,43 +71866,43 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest6_o connect \B \fus_dest3_o$135 - connect \Y $or$libresoc.v:41978$1673_Y + connect \Y $or$libresoc.v:42272$1675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41979$1674 + cell $or $or$libresoc.v:42273$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest3_o$134 - connect \B \$1435 - connect \Y $or$libresoc.v:41979$1674_Y + connect \B \$1440 + connect \Y $or$libresoc.v:42273$1676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41980$1675 + cell $or $or$libresoc.v:42274$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1416 - connect \B \addr_en$1432 - connect \Y $or$libresoc.v:41980$1675_Y + connect \A \addr_en$1421 + connect \B \addr_en$1437 + connect \Y $or$libresoc.v:42274$1677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41981$1676 + cell $or $or$libresoc.v:42275$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1400 - connect \B \$1440 - connect \Y $or$libresoc.v:41981$1676_Y + connect \A \addr_en$1405 + connect \B \$1445 + connect \Y $or$libresoc.v:42275$1678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42011$1707 + cell $or $or$libresoc.v:42305$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71618,10 +71910,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $or$libresoc.v:42011$1707_Y + connect \Y $or$libresoc.v:42305$1709_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42012$1708 + cell $or $or$libresoc.v:42306$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71629,54 +71921,54 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$139 connect \B \fus_dest3_o$140 - connect \Y $or$libresoc.v:42012$1708_Y + connect \Y $or$libresoc.v:42306$1710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42013$1709 + cell $or $or$libresoc.v:42307$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \$1517 - connect \B \$1519 - connect \Y $or$libresoc.v:42013$1709_Y + connect \A \$1522 + connect \B \$1524 + connect \Y $or$libresoc.v:42307$1711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42014$1710 + cell $or $or$libresoc.v:42308$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1466 - connect \B \addr_en$1482 - connect \Y $or$libresoc.v:42014$1710_Y + connect \A \addr_en$1471 + connect \B \addr_en$1487 + connect \Y $or$libresoc.v:42308$1712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42015$1711 + cell $or $or$libresoc.v:42309$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1498 - connect \B \addr_en$1514 - connect \Y $or$libresoc.v:42015$1711_Y + connect \A \addr_en$1503 + connect \B \addr_en$1519 + connect \Y $or$libresoc.v:42309$1713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42016$1712 + cell $or $or$libresoc.v:42310$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \$1523 - connect \B \$1525 - connect \Y $or$libresoc.v:42016$1712_Y + connect \A \$1528 + connect \B \$1530 + connect \Y $or$libresoc.v:42310$1714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42045$1741 + cell $or $or$libresoc.v:42339$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71684,10 +71976,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest5_o$144 connect \B \fus_dest4_o$145 - connect \Y $or$libresoc.v:42045$1741_Y + connect \Y $or$libresoc.v:42339$1743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42046$1742 + cell $or $or$libresoc.v:42340$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71695,54 +71987,54 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest4_o$146 connect \B \fus_dest4_o$147 - connect \Y $or$libresoc.v:42046$1742_Y + connect \Y $or$libresoc.v:42340$1744_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42047$1743 + cell $or $or$libresoc.v:42341$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1602 - connect \B \$1604 - connect \Y $or$libresoc.v:42047$1743_Y + connect \A \$1607 + connect \B \$1609 + connect \Y $or$libresoc.v:42341$1745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42049$1746 + cell $or $or$libresoc.v:42343$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1550 - connect \B \addr_en$1566 - connect \Y $or$libresoc.v:42049$1746_Y + connect \A \addr_en$1555 + connect \B \addr_en$1571 + connect \Y $or$libresoc.v:42343$1748_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42050$1747 + cell $or $or$libresoc.v:42344$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1582 - connect \B \addr_en$1598 - connect \Y $or$libresoc.v:42050$1747_Y + connect \A \addr_en$1587 + connect \B \addr_en$1603 + connect \Y $or$libresoc.v:42344$1749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42051$1748 + cell $or $or$libresoc.v:42345$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1610 - connect \B \$1612 - connect \Y $or$libresoc.v:42051$1748_Y + connect \A \$1615 + connect \B \$1617 + connect \Y $or$libresoc.v:42345$1750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42088$1786 + cell $or $or$libresoc.v:42382$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71750,10 +72042,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$153 connect \B \fus_dest2_o$154 - connect \Y $or$libresoc.v:42088$1786_Y + connect \Y $or$libresoc.v:42382$1788_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42089$1787 + cell $or $or$libresoc.v:42383$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71761,120 +72053,120 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest2_o$156 connect \B \fus_dest3_o$157 - connect \Y $or$libresoc.v:42089$1787_Y + connect \Y $or$libresoc.v:42383$1789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42090$1788 + cell $or $or$libresoc.v:42384$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest3_o$155 - connect \B \$1712 - connect \Y $or$libresoc.v:42090$1788_Y + connect \B \$1717 + connect \Y $or$libresoc.v:42384$1790_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42091$1789 + cell $or $or$libresoc.v:42385$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$1710 - connect \B \$1714 - connect \Y $or$libresoc.v:42091$1789_Y + connect \A \$1715 + connect \B \$1719 + connect \Y $or$libresoc.v:42385$1791_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42092$1790 + cell $or $or$libresoc.v:42386$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1643 - connect \B \addr_en$1659 - connect \Y $or$libresoc.v:42092$1790_Y + connect \A \addr_en$1648 + connect \B \addr_en$1664 + connect \Y $or$libresoc.v:42386$1792_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42093$1791 + cell $or $or$libresoc.v:42387$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1691 - connect \B \addr_en$1707 - connect \Y $or$libresoc.v:42093$1791_Y + connect \A \addr_en$1696 + connect \B \addr_en$1712 + connect \Y $or$libresoc.v:42387$1793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42094$1792 + cell $or $or$libresoc.v:42388$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1675 - connect \B \$1720 - connect \Y $or$libresoc.v:42094$1792_Y + connect \A \addr_en$1680 + connect \B \$1725 + connect \Y $or$libresoc.v:42388$1794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42095$1793 + cell $or $or$libresoc.v:42389$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \$1718 - connect \B \$1722 - connect \Y $or$libresoc.v:42095$1793_Y + connect \A \$1723 + connect \B \$1727 + connect \Y $or$libresoc.v:42389$1795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42096$1794 + cell $or $or$libresoc.v:42390$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1640 - connect \B \wp$1656 - connect \Y $or$libresoc.v:42096$1794_Y + connect \A \wp$1645 + connect \B \wp$1661 + connect \Y $or$libresoc.v:42390$1796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42097$1795 + cell $or $or$libresoc.v:42391$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1688 - connect \B \wp$1704 - connect \Y $or$libresoc.v:42097$1795_Y + connect \A \wp$1693 + connect \B \wp$1709 + connect \Y $or$libresoc.v:42391$1797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42098$1796 + cell $or $or$libresoc.v:42392$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1672 - connect \B \$1728 - connect \Y $or$libresoc.v:42098$1796_Y + connect \A \wp$1677 + connect \B \$1733 + connect \Y $or$libresoc.v:42392$1798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42099$1797 + cell $or $or$libresoc.v:42393$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1726 - connect \B \$1730 - connect \Y $or$libresoc.v:42099$1797_Y + connect \A \$1731 + connect \B \$1735 + connect \Y $or$libresoc.v:42393$1799_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42114$1812 + cell $or $or$libresoc.v:42408$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71882,197 +72174,197 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$159 connect \B \fus_dest4_o$160 - connect \Y $or$libresoc.v:42114$1812_Y + connect \Y $or$libresoc.v:42408$1814_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42115$1813 + cell $or $or$libresoc.v:42409$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1751 - connect \B \addr_en$1767 - connect \Y $or$libresoc.v:42115$1813_Y + connect \A \addr_en$1756 + connect \B \addr_en$1772 + connect \Y $or$libresoc.v:42409$1815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42158$1858 + cell $or $or$libresoc.v:42452$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$224 - connect \B \$228 - connect \Y $or$libresoc.v:42158$1858_Y + connect \A \$229 + connect \B \$233 + connect \Y $or$libresoc.v:42452$1860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42160$1860 + cell $or $or$libresoc.v:42454$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$230 - connect \B \$232 - connect \Y $or$libresoc.v:42160$1860_Y + connect \A \$235 + connect \B \$237 + connect \Y $or$libresoc.v:42454$1862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42164$1864 + cell $or $or$libresoc.v:42458$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$236 - connect \B \$240 - connect \Y $or$libresoc.v:42164$1864_Y + connect \A \$241 + connect \B \$245 + connect \Y $or$libresoc.v:42458$1866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42172$1872 + cell $or $or$libresoc.v:42466$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$252 - connect \B \$256 - connect \Y $or$libresoc.v:42172$1872_Y + connect \A \$257 + connect \B \$261 + connect \Y $or$libresoc.v:42466$1874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42174$1874 + cell $or $or$libresoc.v:42468$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$258 - connect \B \$260 - connect \Y $or$libresoc.v:42174$1874_Y + connect \A \$263 + connect \B \$265 + connect \Y $or$libresoc.v:42468$1876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42179$1879 + cell $or $or$libresoc.v:42473$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$266 - connect \B \$270 - connect \Y $or$libresoc.v:42179$1879_Y + connect \A \$271 + connect \B \$275 + connect \Y $or$libresoc.v:42473$1881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42181$1881 + cell $or $or$libresoc.v:42475$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$272 - connect \B \$274 - connect \Y $or$libresoc.v:42181$1881_Y + connect \A \$277 + connect \B \$279 + connect \Y $or$libresoc.v:42475$1883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42185$1885 + cell $or $or$libresoc.v:42479$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$278 - connect \B \$282 - connect \Y $or$libresoc.v:42185$1885_Y + connect \A \$283 + connect \B \$287 + connect \Y $or$libresoc.v:42479$1887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42189$1889 + cell $or $or$libresoc.v:42483$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$286 - connect \B \$290 - connect \Y $or$libresoc.v:42189$1889_Y + connect \A \$291 + connect \B \$295 + connect \Y $or$libresoc.v:42483$1891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42194$1894 + cell $or $or$libresoc.v:42488$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$296 - connect \B \$300 - connect \Y $or$libresoc.v:42194$1894_Y + connect \A \$301 + connect \B \$305 + connect \Y $or$libresoc.v:42488$1896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42196$1896 + cell $or $or$libresoc.v:42490$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$302 - connect \B \$304 - connect \Y $or$libresoc.v:42196$1896_Y + connect \A \$307 + connect \B \$309 + connect \Y $or$libresoc.v:42490$1898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42201$1901 + cell $or $or$libresoc.v:42495$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$310 - connect \B \$314 - connect \Y $or$libresoc.v:42201$1901_Y + connect \A \$315 + connect \B \$319 + connect \Y $or$libresoc.v:42495$1903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42203$1903 + cell $or $or$libresoc.v:42497$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$316 - connect \B \$318 - connect \Y $or$libresoc.v:42203$1903_Y + connect \A \$321 + connect \B \$323 + connect \Y $or$libresoc.v:42497$1905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42208$1908 + cell $or $or$libresoc.v:42502$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$324 - connect \B \$328 - connect \Y $or$libresoc.v:42208$1908_Y + connect \A \$329 + connect \B \$333 + connect \Y $or$libresoc.v:42502$1910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42210$1910 + cell $or $or$libresoc.v:42504$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$330 - connect \B \$332 - connect \Y $or$libresoc.v:42210$1910_Y + connect \A \$335 + connect \B \$337 + connect \Y $or$libresoc.v:42504$1912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42214$1914 + cell $or $or$libresoc.v:42508$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$336 - connect \B \$340 - connect \Y $or$libresoc.v:42214$1914_Y + connect \A \$341 + connect \B \$345 + connect \Y $or$libresoc.v:42508$1916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42271$1971 + cell $or $or$libresoc.v:42565$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72080,10 +72372,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_alu0_0 connect \B \addr_en_INT_ra_cr0_1 - connect \Y $or$libresoc.v:42271$1971_Y + connect \Y $or$libresoc.v:42565$1973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42272$1972 + cell $or $or$libresoc.v:42566$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72091,21 +72383,21 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_trap0_2 connect \B \addr_en_INT_ra_logical0_3 - connect \Y $or$libresoc.v:42272$1972_Y + connect \Y $or$libresoc.v:42566$1974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42273$1973 + cell $or $or$libresoc.v:42567$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$456 - connect \B \$458 - connect \Y $or$libresoc.v:42273$1973_Y + connect \A \$461 + connect \B \$463 + connect \Y $or$libresoc.v:42567$1975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42274$1974 + cell $or $or$libresoc.v:42568$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72113,10 +72405,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_spr0_4 connect \B \addr_en_INT_ra_div0_5 - connect \Y $or$libresoc.v:42274$1974_Y + connect \Y $or$libresoc.v:42568$1976_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42275$1975 + cell $or $or$libresoc.v:42569$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72124,43 +72416,43 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_shiftrot0_7 connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $or$libresoc.v:42275$1975_Y + connect \Y $or$libresoc.v:42569$1977_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42276$1976 + cell $or $or$libresoc.v:42570$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_mul0_6 - connect \B \$464 - connect \Y $or$libresoc.v:42276$1976_Y + connect \B \$469 + connect \Y $or$libresoc.v:42570$1978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42277$1977 + cell $or $or$libresoc.v:42571$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$462 - connect \B \$466 - connect \Y $or$libresoc.v:42277$1977_Y + connect \A \$467 + connect \B \$471 + connect \Y $or$libresoc.v:42571$1979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42278$1978 + cell $or $or$libresoc.v:42572$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$460 - connect \B \$468 - connect \Y $or$libresoc.v:42278$1978_Y + connect \A \$465 + connect \B \$473 + connect \Y $or$libresoc.v:42572$1980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42328$2028 + cell $or $or$libresoc.v:42622$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72168,10 +72460,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_alu0_0 connect \B \addr_en_INT_rb_cr0_1 - connect \Y $or$libresoc.v:42328$2028_Y + connect \Y $or$libresoc.v:42622$2030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42329$2029 + cell $or $or$libresoc.v:42623$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72179,21 +72471,21 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_trap0_2 connect \B \addr_en_INT_rb_logical0_3 - connect \Y $or$libresoc.v:42329$2029_Y + connect \Y $or$libresoc.v:42623$2031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42330$2030 + cell $or $or$libresoc.v:42624$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$571 - connect \B \$573 - connect \Y $or$libresoc.v:42330$2030_Y + connect \A \$576 + connect \B \$578 + connect \Y $or$libresoc.v:42624$2032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42331$2031 + cell $or $or$libresoc.v:42625$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72201,10 +72493,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_div0_4 connect \B \addr_en_INT_rb_mul0_5 - connect \Y $or$libresoc.v:42331$2031_Y + connect \Y $or$libresoc.v:42625$2033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42332$2032 + cell $or $or$libresoc.v:42626$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72212,32 +72504,32 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_shiftrot0_6 connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $or$libresoc.v:42332$2032_Y + connect \Y $or$libresoc.v:42626$2034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42333$2033 + cell $or $or$libresoc.v:42627$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$577 - connect \B \$579 - connect \Y $or$libresoc.v:42333$2033_Y + connect \A \$582 + connect \B \$584 + connect \Y $or$libresoc.v:42627$2035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42334$2034 + cell $or $or$libresoc.v:42628$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 - connect \A \$575 - connect \B \$581 - connect \Y $or$libresoc.v:42334$2034_Y + connect \A \$580 + connect \B \$586 + connect \Y $or$libresoc.v:42628$2036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42348$2048 + cell $or $or$libresoc.v:42642$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72245,32 +72537,32 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rc_shiftrot0_0 connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $or$libresoc.v:42348$2048_Y + connect \Y $or$libresoc.v:42642$2050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42353$2053 + cell $or $or$libresoc.v:42647$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$616 - connect \B \$620 - connect \Y $or$libresoc.v:42353$2053_Y + connect \A \$621 + connect \B \$625 + connect \Y $or$libresoc.v:42647$2055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42355$2055 + cell $or $or$libresoc.v:42649$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$622 - connect \B \$624 - connect \Y $or$libresoc.v:42355$2055_Y + connect \A \$627 + connect \B \$629 + connect \Y $or$libresoc.v:42649$2057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42392$2092 + cell $or $or$libresoc.v:42686$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72278,21 +72570,21 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_logical0_1 connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $or$libresoc.v:42392$2092_Y + connect \Y $or$libresoc.v:42686$2094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42393$2093 + cell $or $or$libresoc.v:42687$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 - connect \B \$701 - connect \Y $or$libresoc.v:42393$2093_Y + connect \B \$706 + connect \Y $or$libresoc.v:42687$2095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42394$2094 + cell $or $or$libresoc.v:42688$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72300,43 +72592,43 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_mul0_4 connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $or$libresoc.v:42394$2094_Y + connect \Y $or$libresoc.v:42688$2096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42395$2095 + cell $or $or$libresoc.v:42689$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_div0_3 - connect \B \$705 - connect \Y $or$libresoc.v:42395$2095_Y + connect \B \$710 + connect \Y $or$libresoc.v:42689$2097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42396$2096 + cell $or $or$libresoc.v:42690$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$703 - connect \B \$707 - connect \Y $or$libresoc.v:42396$2096_Y + connect \A \$708 + connect \B \$712 + connect \Y $or$libresoc.v:42690$2098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42401$2102 + cell $or $or$libresoc.v:42695$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$712 - connect \B \$716 - connect \Y $or$libresoc.v:42401$2102_Y + connect \A \$717 + connect \B \$721 + connect \Y $or$libresoc.v:42695$2104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42420$2121 + cell $or $or$libresoc.v:42714$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72344,32 +72636,32 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $or$libresoc.v:42420$2121_Y + connect \Y $or$libresoc.v:42714$2123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42421$2122 + cell $or $or$libresoc.v:42715$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 - connect \B \$757 - connect \Y $or$libresoc.v:42421$2122_Y + connect \B \$762 + connect \Y $or$libresoc.v:42715$2124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42426$2128 + cell $or $or$libresoc.v:42720$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$762 - connect \B \$766 - connect \Y $or$libresoc.v:42426$2128_Y + connect \A \$767 + connect \B \$771 + connect \Y $or$libresoc.v:42720$2130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42455$2157 + cell $or $or$libresoc.v:42749$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -72377,10 +72669,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $or$libresoc.v:42455$2157_Y + connect \Y $or$libresoc.v:42749$2159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42490$2192 + cell $or $or$libresoc.v:42784$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72388,21 +72680,21 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_trap0_1 connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $or$libresoc.v:42490$2192_Y + connect \Y $or$libresoc.v:42784$2194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42491$2193 + cell $or $or$libresoc.v:42785$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_0 - connect \B \$897 - connect \Y $or$libresoc.v:42491$2193_Y + connect \B \$902 + connect \Y $or$libresoc.v:42785$2195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42505$2207 + cell $or $or$libresoc.v:42799$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72410,304 +72702,304 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast2_branch0_0 connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $or$libresoc.v:42505$2207_Y + connect \Y $or$libresoc.v:42799$2209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:41982$1678 + cell $pos $pos$libresoc.v:42276$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:41982$1677_Y - connect \Y $pos$libresoc.v:41982$1678_Y + connect \A $extend$libresoc.v:42276$1679_Y + connect \Y $pos$libresoc.v:42276$1680_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42048$1745 + cell $pos $pos$libresoc.v:42342$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:42048$1744_Y - connect \Y $pos$libresoc.v:42048$1745_Y + connect \A $extend$libresoc.v:42342$1746_Y + connect \Y $pos$libresoc.v:42342$1747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42052$1750 + cell $pos $pos$libresoc.v:42346$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42052$1749_Y - connect \Y $pos$libresoc.v:42052$1750_Y + connect \A $extend$libresoc.v:42346$1751_Y + connect \Y $pos$libresoc.v:42346$1752_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $pos$libresoc.v:42116$1815 + cell $pos $pos$libresoc.v:42410$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42116$1814_Y - connect \Y $pos$libresoc.v:42116$1815_Y + connect \A $extend$libresoc.v:42410$1816_Y + connect \Y $pos$libresoc.v:42410$1817_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $pos $pos$libresoc.v:42126$1826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $pos $pos$libresoc.v:42418$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42126$1825_Y - connect \Y $pos$libresoc.v:42126$1826_Y + connect \A $extend$libresoc.v:42418$1825_Y + connect \Y $pos$libresoc.v:42418$1826_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42397$2098 + cell $pos $pos$libresoc.v:42691$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42397$2097_Y - connect \Y $pos$libresoc.v:42397$2098_Y + connect \A $extend$libresoc.v:42691$2099_Y + connect \Y $pos$libresoc.v:42691$2100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42422$2124 + cell $pos $pos$libresoc.v:42716$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42422$2123_Y - connect \Y $pos$libresoc.v:42422$2124_Y + connect \A $extend$libresoc.v:42716$2125_Y + connect \Y $pos$libresoc.v:42716$2126_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42123$1822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42427$1835 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$177 - connect \Y $reduce_or$libresoc.v:42123$1822_Y + connect \A \$182 + connect \Y $reduce_or$libresoc.v:42427$1835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42135$1835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42429$1837 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$181 - connect \Y $reduce_or$libresoc.v:42135$1835_Y + connect \A \$186 + connect \Y $reduce_or$libresoc.v:42429$1837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42137$1837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42431$1839 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$185 - connect \Y $reduce_or$libresoc.v:42137$1837_Y + connect \A \$190 + connect \Y $reduce_or$libresoc.v:42431$1839_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42139$1839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42433$1841 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$189 - connect \Y $reduce_or$libresoc.v:42139$1839_Y + connect \A \$194 + connect \Y $reduce_or$libresoc.v:42433$1841_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42141$1841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42435$1843 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$193 - connect \Y $reduce_or$libresoc.v:42141$1841_Y + connect \A \$198 + connect \Y $reduce_or$libresoc.v:42435$1843_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42143$1843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42437$1845 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$197 - connect \Y $reduce_or$libresoc.v:42143$1843_Y + connect \A \$202 + connect \Y $reduce_or$libresoc.v:42437$1845_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42145$1845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42439$1847 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$201 - connect \Y $reduce_or$libresoc.v:42145$1845_Y + connect \A \$206 + connect \Y $reduce_or$libresoc.v:42439$1847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42147$1847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42441$1849 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$205 - connect \Y $reduce_or$libresoc.v:42147$1847_Y + connect \A \$210 + connect \Y $reduce_or$libresoc.v:42441$1849_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42149$1849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42443$1851 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$209 - connect \Y $reduce_or$libresoc.v:42149$1849_Y + connect \A \$214 + connect \Y $reduce_or$libresoc.v:42443$1851_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42151$1851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $reduce_or $reduce_or$libresoc.v:42445$1853 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \Y_WIDTH 1 - connect \A \$213 - connect \Y $reduce_or$libresoc.v:42151$1851_Y + connect \A \$218 + connect \Y $reduce_or$libresoc.v:42445$1853_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42279$1979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42573$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $reduce_or$libresoc.v:42279$1979_Y + connect \Y $reduce_or$libresoc.v:42573$1981_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42335$2035 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42629$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $reduce_or$libresoc.v:42335$2035_Y + connect \Y $reduce_or$libresoc.v:42629$2037_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42349$2049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42643$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $reduce_or$libresoc.v:42349$2049_Y + connect \Y $reduce_or$libresoc.v:42643$2051_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42492$2194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42786$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $reduce_or$libresoc.v:42492$2194_Y + connect \Y $reduce_or$libresoc.v:42786$2196_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42506$2208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42800$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $reduce_or$libresoc.v:42506$2208_Y + connect \Y $reduce_or$libresoc.v:42800$2210_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42513$2215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" + cell $reduce_or $reduce_or$libresoc.v:42807$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rp_SPR_spr1_spr0_0 - connect \Y $reduce_or$libresoc.v:42513$2215_Y + connect \Y $reduce_or$libresoc.v:42807$2217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41905$1600 + cell $sshl $sshl$libresoc.v:42199$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1254 - connect \Y $sshl$libresoc.v:41905$1600_Y + connect \B \$1259 + connect \Y $sshl$libresoc.v:42199$1602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41913$1608 + cell $sshl $sshl$libresoc.v:42207$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1274 - connect \Y $sshl$libresoc.v:41913$1608_Y + connect \B \$1279 + connect \Y $sshl$libresoc.v:42207$1610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41921$1616 + cell $sshl $sshl$libresoc.v:42215$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1294 - connect \Y $sshl$libresoc.v:41921$1616_Y + connect \B \$1299 + connect \Y $sshl$libresoc.v:42215$1618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41929$1624 + cell $sshl $sshl$libresoc.v:42223$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1314 - connect \Y $sshl$libresoc.v:41929$1624_Y + connect \B \$1319 + connect \Y $sshl$libresoc.v:42223$1626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41937$1632 + cell $sshl $sshl$libresoc.v:42231$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1334 - connect \Y $sshl$libresoc.v:41937$1632_Y + connect \B \$1339 + connect \Y $sshl$libresoc.v:42231$1634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41945$1640 + cell $sshl $sshl$libresoc.v:42239$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$1354 - connect \Y $sshl$libresoc.v:41945$1640_Y + connect \B \$1359 + connect \Y $sshl$libresoc.v:42239$1642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42445$2147 + cell $sshl $sshl$libresoc.v:42739$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$804 - connect \Y $sshl$libresoc.v:42445$2147_Y + connect \B \$809 + connect \Y $sshl$libresoc.v:42739$2149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42453$2155 + cell $sshl $sshl$libresoc.v:42747$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$820 - connect \Y $sshl$libresoc.v:42453$2155_Y + connect \B \$825 + connect \Y $sshl$libresoc.v:42747$2157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $sshl$libresoc.v:42462$2164 + cell $sshl $sshl$libresoc.v:42756$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$839 - connect \Y $sshl$libresoc.v:42462$2164_Y + connect \B \$844 + connect \Y $sshl$libresoc.v:42756$2166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $sshl$libresoc.v:42470$2172 + cell $sshl $sshl$libresoc.v:42764$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 - connect \B \$855 - connect \Y $sshl$libresoc.v:42470$2172_Y + connect \B \$860 + connect \Y $sshl$libresoc.v:42764$2174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41904$1599 + cell $sub $sub$libresoc.v:42198$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72715,10 +73007,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41904$1599_Y + connect \Y $sub$libresoc.v:42198$1601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41912$1607 + cell $sub $sub$libresoc.v:42206$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72726,10 +73018,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41912$1607_Y + connect \Y $sub$libresoc.v:42206$1609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41920$1615 + cell $sub $sub$libresoc.v:42214$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72737,10 +73029,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41920$1615_Y + connect \Y $sub$libresoc.v:42214$1617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41928$1623 + cell $sub $sub$libresoc.v:42222$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72748,10 +73040,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41928$1623_Y + connect \Y $sub$libresoc.v:42222$1625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41936$1631 + cell $sub $sub$libresoc.v:42230$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72759,10 +73051,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41936$1631_Y + connect \Y $sub$libresoc.v:42230$1633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41944$1639 + cell $sub $sub$libresoc.v:42238$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72770,10 +73062,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41944$1639_Y + connect \Y $sub$libresoc.v:42238$1641_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $sub $sub$libresoc.v:42153$1853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + cell $sub $sub$libresoc.v:42447$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72781,10 +73073,10 @@ module \core parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 - connect \Y $sub$libresoc.v:42153$1853_Y + connect \Y $sub$libresoc.v:42447$1855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42444$2146 + cell $sub $sub$libresoc.v:42738$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72792,10 +73084,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42444$2146_Y + connect \Y $sub$libresoc.v:42738$2148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42452$2154 + cell $sub $sub$libresoc.v:42746$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72803,10 +73095,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42452$2154_Y + connect \Y $sub$libresoc.v:42746$2156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $sub$libresoc.v:42461$2163 + cell $sub $sub$libresoc.v:42755$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72814,10 +73106,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2 - connect \Y $sub$libresoc.v:42461$2163_Y + connect \Y $sub$libresoc.v:42755$2165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $sub$libresoc.v:42469$2171 + cell $sub $sub$libresoc.v:42763$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72825,626 +73117,626 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2$1 - connect \Y $sub$libresoc.v:42469$2171_Y + connect \Y $sub$libresoc.v:42763$2173_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41816$1511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42104$1507 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1015 - connect \Y $ternary$libresoc.v:41816$1511_Y + connect \S \wp$999 + connect \Y $ternary$libresoc.v:42104$1507_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41822$1517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42110$1513 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1033 - connect \Y $ternary$libresoc.v:41822$1517_Y + connect \S \wp$1020 + connect \Y $ternary$libresoc.v:42110$1513_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41828$1523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42116$1519 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1055 - connect \Y $ternary$libresoc.v:41828$1523_Y + connect \S \wp$1038 + connect \Y $ternary$libresoc.v:42116$1519_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41834$1529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42122$1525 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1075 - connect \Y $ternary$libresoc.v:41834$1529_Y + connect \S \wp$1060 + connect \Y $ternary$libresoc.v:42122$1525_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41840$1535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42128$1531 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1095 - connect \Y $ternary$libresoc.v:41840$1535_Y + connect \S \wp$1080 + connect \Y $ternary$libresoc.v:42128$1531_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41846$1541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42134$1537 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1114 - connect \Y $ternary$libresoc.v:41846$1541_Y + connect \S \wp$1100 + connect \Y $ternary$libresoc.v:42134$1537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41852$1547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42140$1543 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego - connect \S \wp$1132 - connect \Y $ternary$libresoc.v:41852$1547_Y + connect \S \wp$1119 + connect \Y $ternary$libresoc.v:42140$1543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41858$1553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42146$1549 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_rego + connect \S \wp$1137 + connect \Y $ternary$libresoc.v:42146$1549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42152$1555 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_ea - connect \S \wp$1148 - connect \Y $ternary$libresoc.v:41858$1553_Y + connect \S \wp$1153 + connect \Y $ternary$libresoc.v:42152$1555_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41892$1587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42186$1589 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_wr - connect \S \wp$1222 - connect \Y $ternary$libresoc.v:41892$1587_Y + connect \S \wp$1227 + connect \Y $ternary$libresoc.v:42186$1589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41906$1601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42200$1603 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1256 - connect \S \wp$1250 - connect \Y $ternary$libresoc.v:41906$1601_Y + connect \B \$1261 + connect \S \wp$1255 + connect \Y $ternary$libresoc.v:42200$1603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41914$1609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42208$1611 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1276 - connect \S \wp$1270 - connect \Y $ternary$libresoc.v:41914$1609_Y + connect \B \$1281 + connect \S \wp$1275 + connect \Y $ternary$libresoc.v:42208$1611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41922$1617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42216$1619 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1296 - connect \S \wp$1290 - connect \Y $ternary$libresoc.v:41922$1617_Y + connect \B \$1301 + connect \S \wp$1295 + connect \Y $ternary$libresoc.v:42216$1619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41930$1625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42224$1627 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1316 - connect \S \wp$1310 - connect \Y $ternary$libresoc.v:41930$1625_Y + connect \B \$1321 + connect \S \wp$1315 + connect \Y $ternary$libresoc.v:42224$1627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41938$1633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42232$1635 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1336 - connect \S \wp$1330 - connect \Y $ternary$libresoc.v:41938$1633_Y + connect \B \$1341 + connect \S \wp$1335 + connect \Y $ternary$libresoc.v:42232$1635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41946$1641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42240$1643 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$1356 - connect \S \wp$1350 - connect \Y $ternary$libresoc.v:41946$1641_Y + connect \B \$1361 + connect \S \wp$1355 + connect \Y $ternary$libresoc.v:42240$1643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41965$1660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42259$1662 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1397 - connect \Y $ternary$libresoc.v:41965$1660_Y + connect \S \wp$1402 + connect \Y $ternary$libresoc.v:42259$1662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41971$1666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42265$1668 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1413 - connect \Y $ternary$libresoc.v:41971$1666_Y + connect \S \wp$1418 + connect \Y $ternary$libresoc.v:42265$1668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41977$1672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42271$1674 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1429 - connect \Y $ternary$libresoc.v:41977$1672_Y + connect \S \wp$1434 + connect \Y $ternary$libresoc.v:42271$1674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41992$1688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42286$1690 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1463 - connect \Y $ternary$libresoc.v:41992$1688_Y + connect \S \wp$1468 + connect \Y $ternary$libresoc.v:42286$1690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41998$1694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42292$1696 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1479 - connect \Y $ternary$libresoc.v:41998$1694_Y + connect \S \wp$1484 + connect \Y $ternary$libresoc.v:42292$1696_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42004$1700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42298$1702 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1495 - connect \Y $ternary$libresoc.v:42004$1700_Y + connect \S \wp$1500 + connect \Y $ternary$libresoc.v:42298$1702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42010$1706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42304$1708 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1511 - connect \Y $ternary$libresoc.v:42010$1706_Y + connect \S \wp$1516 + connect \Y $ternary$libresoc.v:42304$1708_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42026$1722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42320$1724 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1547 - connect \Y $ternary$libresoc.v:42026$1722_Y + connect \S \wp$1552 + connect \Y $ternary$libresoc.v:42320$1724_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42032$1728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42326$1730 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1563 - connect \Y $ternary$libresoc.v:42032$1728_Y + connect \S \wp$1568 + connect \Y $ternary$libresoc.v:42326$1730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42038$1734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42332$1736 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1579 - connect \Y $ternary$libresoc.v:42038$1734_Y + connect \S \wp$1584 + connect \Y $ternary$libresoc.v:42332$1736_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42044$1740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42338$1742 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1595 - connect \Y $ternary$libresoc.v:42044$1740_Y + connect \S \wp$1600 + connect \Y $ternary$libresoc.v:42338$1742_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42063$1761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42357$1763 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1640 - connect \Y $ternary$libresoc.v:42063$1761_Y + connect \S \wp$1645 + connect \Y $ternary$libresoc.v:42357$1763_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42069$1767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42363$1769 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1656 - connect \Y $ternary$libresoc.v:42069$1767_Y + connect \S \wp$1661 + connect \Y $ternary$libresoc.v:42363$1769_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42075$1773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42369$1775 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1672 - connect \Y $ternary$libresoc.v:42075$1773_Y + connect \S \wp$1677 + connect \Y $ternary$libresoc.v:42369$1775_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42081$1779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42375$1781 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 - connect \S \wp$1688 - connect \Y $ternary$libresoc.v:42081$1779_Y + connect \S \wp$1693 + connect \Y $ternary$libresoc.v:42375$1781_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42087$1785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42381$1787 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 - connect \S \wp$1704 - connect \Y $ternary$libresoc.v:42087$1785_Y + connect \S \wp$1709 + connect \Y $ternary$libresoc.v:42381$1787_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42107$1805 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42401$1807 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1748 - connect \Y $ternary$libresoc.v:42107$1805_Y + connect \S \wp$1753 + connect \Y $ternary$libresoc.v:42401$1807_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42113$1811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42407$1813 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1764 - connect \Y $ternary$libresoc.v:42113$1811_Y + connect \S \wp$1769 + connect \Y $ternary$libresoc.v:42407$1813_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42125$1824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42417$1824 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1788 - connect \Y $ternary$libresoc.v:42125$1824_Y + connect \S \wp$1793 + connect \Y $ternary$libresoc.v:42417$1824_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42133$1833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42425$1833 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spro - connect \S \wp$1808 - connect \Y $ternary$libresoc.v:42133$1833_Y + connect \S \wp$1813 + connect \Y $ternary$libresoc.v:42425$1833_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42222$1922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42516$1924 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_alu0_0 - connect \Y $ternary$libresoc.v:42222$1922_Y + connect \Y $ternary$libresoc.v:42516$1924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42228$1928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42522$1930 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_cr0_1 - connect \Y $ternary$libresoc.v:42228$1928_Y + connect \Y $ternary$libresoc.v:42522$1930_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42234$1934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42528$1936 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_trap0_2 - connect \Y $ternary$libresoc.v:42234$1934_Y + connect \Y $ternary$libresoc.v:42528$1936_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42240$1940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42534$1942 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_logical0_3 - connect \Y $ternary$libresoc.v:42240$1940_Y + connect \Y $ternary$libresoc.v:42534$1942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42246$1946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42540$1948 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_spr0_4 - connect \Y $ternary$libresoc.v:42246$1946_Y + connect \Y $ternary$libresoc.v:42540$1948_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42252$1952 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42546$1954 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_div0_5 - connect \Y $ternary$libresoc.v:42252$1952_Y + connect \Y $ternary$libresoc.v:42546$1954_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42258$1958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42552$1960 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_mul0_6 - connect \Y $ternary$libresoc.v:42258$1958_Y + connect \Y $ternary$libresoc.v:42552$1960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42264$1964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42558$1966 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $ternary$libresoc.v:42264$1964_Y + connect \Y $ternary$libresoc.v:42558$1966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42270$1970 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42564$1972 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_ldst0_8 - connect \Y $ternary$libresoc.v:42270$1970_Y + connect \Y $ternary$libresoc.v:42564$1972_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42285$1985 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42579$1987 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_alu0_0 - connect \Y $ternary$libresoc.v:42285$1985_Y + connect \Y $ternary$libresoc.v:42579$1987_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42291$1991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42585$1993 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_cr0_1 - connect \Y $ternary$libresoc.v:42291$1991_Y + connect \Y $ternary$libresoc.v:42585$1993_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42297$1997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42591$1999 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_trap0_2 - connect \Y $ternary$libresoc.v:42297$1997_Y + connect \Y $ternary$libresoc.v:42591$1999_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42303$2003 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42597$2005 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_logical0_3 - connect \Y $ternary$libresoc.v:42303$2003_Y + connect \Y $ternary$libresoc.v:42597$2005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42309$2009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42603$2011 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_div0_4 - connect \Y $ternary$libresoc.v:42309$2009_Y + connect \Y $ternary$libresoc.v:42603$2011_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42315$2015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42609$2017 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_mul0_5 - connect \Y $ternary$libresoc.v:42315$2015_Y + connect \Y $ternary$libresoc.v:42609$2017_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42321$2021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42615$2023 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $ternary$libresoc.v:42321$2021_Y + connect \Y $ternary$libresoc.v:42615$2023_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42327$2027 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42621$2029 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_ldst0_7 - connect \Y $ternary$libresoc.v:42327$2027_Y + connect \Y $ternary$libresoc.v:42621$2029_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42341$2041 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42635$2043 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $ternary$libresoc.v:42341$2041_Y + connect \Y $ternary$libresoc.v:42635$2043_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42347$2047 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42641$2049 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rc_ldst0_1 - connect \Y $ternary$libresoc.v:42347$2047_Y + connect \Y $ternary$libresoc.v:42641$2049_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42361$2061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42655$2063 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$libresoc.v:42361$2061_Y + connect \Y $ternary$libresoc.v:42655$2063_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42367$2067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42661$2069 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$libresoc.v:42367$2067_Y + connect \Y $ternary$libresoc.v:42661$2069_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42373$2073 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42667$2075 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$libresoc.v:42373$2073_Y + connect \Y $ternary$libresoc.v:42667$2075_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42379$2079 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42673$2081 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$libresoc.v:42379$2079_Y + connect \Y $ternary$libresoc.v:42673$2081_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42385$2085 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42679$2087 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$libresoc.v:42385$2085_Y + connect \Y $ternary$libresoc.v:42679$2087_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42391$2091 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42685$2093 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$libresoc.v:42391$2091_Y + connect \Y $ternary$libresoc.v:42685$2093_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42407$2108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42701$2110 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$libresoc.v:42407$2108_Y + connect \Y $ternary$libresoc.v:42701$2110_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42413$2114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42707$2116 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$libresoc.v:42413$2114_Y + connect \Y $ternary$libresoc.v:42707$2116_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42419$2120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42713$2122 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$libresoc.v:42419$2120_Y + connect \Y $ternary$libresoc.v:42713$2122_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42432$2134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42726$2136 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$libresoc.v:42432$2134_Y + connect \Y $ternary$libresoc.v:42726$2136_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42438$2140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42732$2142 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$libresoc.v:42438$2140_Y + connect \Y $ternary$libresoc.v:42732$2142_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42446$2148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42740$2150 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$806 + connect \B \$811 connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$libresoc.v:42446$2148_Y + connect \Y $ternary$libresoc.v:42740$2150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42454$2156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42748$2158 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$822 + connect \B \$827 connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$libresoc.v:42454$2156_Y + connect \Y $ternary$libresoc.v:42748$2158_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42463$2165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42757$2167 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$841 + connect \B \$846 connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$libresoc.v:42463$2165_Y + connect \Y $ternary$libresoc.v:42757$2167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42471$2173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42765$2175 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - connect \B \$857 + connect \B \$862 connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$libresoc.v:42471$2173_Y + connect \Y $ternary$libresoc.v:42765$2175_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42477$2179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42771$2181 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$libresoc.v:42477$2179_Y + connect \Y $ternary$libresoc.v:42771$2181_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42483$2185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42777$2187 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$libresoc.v:42483$2185_Y + connect \Y $ternary$libresoc.v:42777$2187_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42489$2191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42783$2193 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$libresoc.v:42489$2191_Y + connect \Y $ternary$libresoc.v:42783$2193_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42498$2200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42792$2202 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_branch0_0 - connect \Y $ternary$libresoc.v:42498$2200_Y + connect \Y $ternary$libresoc.v:42792$2202_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42504$2206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42798$2208 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_trap0_1 - connect \Y $ternary$libresoc.v:42504$2206_Y + connect \Y $ternary$libresoc.v:42798$2208_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42512$2214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" + cell $mux $ternary$libresoc.v:42806$2216 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$libresoc.v:42512$2214_Y + connect \Y $ternary$libresoc.v:42806$2216_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42529$2231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" + cell $mux $ternary$libresoc.v:42823$2233 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp - connect \Y $ternary$libresoc.v:42529$2231_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42535$2237 - parameter \WIDTH 7 - connect \A 7'0000000 - connect \B \core_rego - connect \S \wp$994 - connect \Y $ternary$libresoc.v:42535$2237_Y + connect \Y $ternary$libresoc.v:42823$2233_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:42694.6-42711.4" + attribute \src "libresoc.v:42986.6-43003.4" cell \cr \cr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73464,7 +73756,7 @@ module \core connect \wen \cr_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:42712.11-42733.4" + attribute \src "libresoc.v:43004.11-43026.4" cell \dec_ALU \dec_ALU connect \ALU__data_len \dec_ALU_ALU__data_len connect \ALU__fn_unit \dec_ALU_ALU__fn_unit @@ -73486,9 +73778,10 @@ module \core connect \ALU__zero_a \dec_ALU_ALU__zero_a connect \bigendian \dec_ALU_bigendian connect \raw_opcode_in \dec_ALU_raw_opcode_in + connect \sv_a_nz \dec_ALU_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:42734.14-42746.4" + attribute \src "libresoc.v:43027.14-43039.4" cell \dec_BRANCH \dec_BRANCH connect \BRANCH__cia \dec_BRANCH_BRANCH__cia connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit @@ -73503,7 +73796,7 @@ module \core connect \raw_opcode_in \dec_BRANCH_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42747.10-42753.4" + attribute \src "libresoc.v:43040.10-43046.4" cell \dec_CR \dec_CR connect \CR__fn_unit \dec_CR_CR__fn_unit connect \CR__insn \dec_CR_CR__insn @@ -73512,7 +73805,7 @@ module \core connect \raw_opcode_in \dec_CR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42754.11-42775.4" + attribute \src "libresoc.v:43047.11-43069.4" cell \dec_DIV \dec_DIV connect \DIV__data_len \dec_DIV_DIV__data_len connect \DIV__fn_unit \dec_DIV_DIV__fn_unit @@ -73534,9 +73827,10 @@ module \core connect \DIV__zero_a \dec_DIV_DIV__zero_a connect \bigendian \dec_DIV_bigendian connect \raw_opcode_in \dec_DIV_raw_opcode_in + connect \sv_a_nz \dec_DIV_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:42776.12-42795.4" + attribute \src "libresoc.v:43070.12-43090.4" cell \dec_LDST \dec_LDST connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse connect \LDST__data_len \dec_LDST_LDST__data_len @@ -73556,9 +73850,10 @@ module \core connect \LDST__zero_a \dec_LDST_LDST__zero_a connect \bigendian \dec_LDST_bigendian connect \raw_opcode_in \dec_LDST_raw_opcode_in + connect \sv_a_nz \dec_LDST_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:42796.15-42817.4" + attribute \src "libresoc.v:43091.15-43113.4" cell \dec_LOGICAL \dec_LOGICAL connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit @@ -73580,9 +73875,10 @@ module \core connect \LOGICAL__zero_a \dec_LOGICAL_LOGICAL__zero_a connect \bigendian \dec_LOGICAL_bigendian connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + connect \sv_a_nz \dec_LOGICAL_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:42818.11-42833.4" + attribute \src "libresoc.v:43114.11-43129.4" cell \dec_MUL \dec_MUL connect \MUL__fn_unit \dec_MUL_MUL__fn_unit connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data @@ -73600,7 +73896,7 @@ module \core connect \raw_opcode_in \dec_MUL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42834.17-42854.4" + attribute \src "libresoc.v:43130.17-43150.4" cell \dec_SHIFT_ROT \dec_SHIFT_ROT connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data @@ -73623,7 +73919,7 @@ module \core connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42855.11-42862.4" + attribute \src "libresoc.v:43151.11-43158.4" cell \dec_SPR \dec_SPR connect \SPR__fn_unit \dec_SPR_SPR__fn_unit connect \SPR__insn \dec_SPR_SPR__insn @@ -73633,7 +73929,7 @@ module \core connect \raw_opcode_in \dec_SPR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42863.8-42881.4" + attribute \src "libresoc.v:43159.8-43177.4" cell \fast \fast connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73654,7 +73950,7 @@ module \core connect \src2__ren \fast_src2__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:42882.7-43213.4" + attribute \src "libresoc.v:43178.7-43509.4" cell \fus \fus connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73988,7 +74284,7 @@ module \core connect \xer_so_ok$131 \fus_xer_so_ok$143 end attribute \module_not_derived 1 - attribute \src "libresoc.v:43214.9-43232.4" + attribute \src "libresoc.v:43510.9-43528.4" cell \int \int connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74009,7 +74305,7 @@ module \core connect \src3__ren \int_src3__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:43233.6-43265.4" + attribute \src "libresoc.v:43529.6-43561.4" cell \l0 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74044,98 +74340,98 @@ module \core connect \wb_dcache_en \wb_dcache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:43266.18-43270.4" + attribute \src "libresoc.v:43562.18-43566.4" cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \en_o \rdpick_CR_cr_a_en_o connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43271.18-43275.4" + attribute \src "libresoc.v:43567.18-43571.4" cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \en_o \rdpick_CR_cr_b_en_o connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43276.18-43280.4" + attribute \src "libresoc.v:43572.18-43576.4" cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \en_o \rdpick_CR_cr_c_en_o connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43281.21-43285.4" + attribute \src "libresoc.v:43577.21-43581.4" cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \en_o \rdpick_CR_full_cr_en_o connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43286.21-43290.4" + attribute \src "libresoc.v:43582.21-43586.4" cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \en_o \rdpick_FAST_fast1_en_o connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43291.21-43295.4" + attribute \src "libresoc.v:43587.21-43591.4" cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 connect \en_o \rdpick_FAST_fast2_en_o connect \i \rdpick_FAST_fast2_i connect \o \rdpick_FAST_fast2_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43296.17-43300.4" + attribute \src "libresoc.v:43592.17-43596.4" cell \rdpick_INT_ra \rdpick_INT_ra connect \en_o \rdpick_INT_ra_en_o connect \i \rdpick_INT_ra_i connect \o \rdpick_INT_ra_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43301.17-43305.4" + attribute \src "libresoc.v:43597.17-43601.4" cell \rdpick_INT_rb \rdpick_INT_rb connect \en_o \rdpick_INT_rb_en_o connect \i \rdpick_INT_rb_i connect \o \rdpick_INT_rb_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43306.17-43310.4" + attribute \src "libresoc.v:43602.17-43606.4" cell \rdpick_INT_rc \rdpick_INT_rc connect \en_o \rdpick_INT_rc_en_o connect \i \rdpick_INT_rc_i connect \o \rdpick_INT_rc_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43311.19-43315.4" + attribute \src "libresoc.v:43607.19-43611.4" cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \en_o \rdpick_SPR_spr1_en_o connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43316.21-43320.4" + attribute \src "libresoc.v:43612.21-43616.4" cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43321.21-43325.4" + attribute \src "libresoc.v:43617.21-43621.4" cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \en_o \rdpick_XER_xer_ov_en_o connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43326.21-43330.4" + attribute \src "libresoc.v:43622.21-43626.4" cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43331.7-43340.4" + attribute \src "libresoc.v:43627.7-43636.4" cell \spr \spr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74147,7 +74443,7 @@ module \core connect \spr1__wen \spr_spr1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43341.9-43358.4" + attribute \src "libresoc.v:43637.9-43654.4" cell \state \state connect \cia__data_o \cia__data_o connect \cia__ren \cia__ren @@ -74167,77 +74463,77 @@ module \core connect \wen$5 \state_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43359.18-43363.4" + attribute \src "libresoc.v:43655.18-43659.4" cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43364.21-43368.4" + attribute \src "libresoc.v:43660.21-43664.4" cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \en_o \wrpick_CR_full_cr_en_o connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43369.21-43373.4" + attribute \src "libresoc.v:43665.21-43669.4" cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \en_o \wrpick_FAST_fast1_en_o connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43374.16-43378.4" + attribute \src "libresoc.v:43670.16-43674.4" cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43379.19-43383.4" + attribute \src "libresoc.v:43675.19-43679.4" cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \en_o \wrpick_SPR_spr1_en_o connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43384.20-43388.4" + attribute \src "libresoc.v:43680.20-43684.4" cell \wrpick_STATE_msr \wrpick_STATE_msr connect \en_o \wrpick_STATE_msr_en_o connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43389.20-43393.4" + attribute \src "libresoc.v:43685.20-43689.4" cell \wrpick_STATE_nia \wrpick_STATE_nia connect \en_o \wrpick_STATE_nia_en_o connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43394.21-43398.4" + attribute \src "libresoc.v:43690.21-43694.4" cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43399.21-43403.4" + attribute \src "libresoc.v:43695.21-43699.4" cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43404.21-43408.4" + attribute \src "libresoc.v:43700.21-43704.4" cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43409.7-43426.4" + attribute \src "libresoc.v:43705.7-43722.4" cell \xer \xer connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74256,1397 +74552,1802 @@ module \core connect \wen$2 \xer_wen$171 connect \wen$4 \xer_wen$173 end - attribute \src "libresoc.v:35982.7-35982.20" - process $proc$libresoc.v:35982$2900 + attribute \src "libresoc.v:36214.7-36214.20" + process $proc$libresoc.v:36214$2900 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:38029.7-38029.30" - process $proc$libresoc.v:38029$2901 + attribute \src "libresoc.v:38263.7-38263.30" + process $proc$libresoc.v:38263$2901 assign { } { } assign $1\core_terminate_o[0:0] 1'0 sync always sync init update \core_terminate_o $1\core_terminate_o[0:0] end - attribute \src "libresoc.v:38042.13-38042.27" - process $proc$libresoc.v:38042$2902 + attribute \src "libresoc.v:38276.13-38276.27" + process $proc$libresoc.v:38276$2902 assign { } { } assign $1\counter[1:0] 2'00 sync always sync init update \counter $1\counter[1:0] end - attribute \src "libresoc.v:39183.7-39183.34" - process $proc$libresoc.v:39183$2903 + attribute \src "libresoc.v:39443.7-39443.34" + process $proc$libresoc.v:39443$2903 assign { } { } assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 sync always sync init update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:39187.7-39187.30" - process $proc$libresoc.v:39187$2904 + attribute \src "libresoc.v:39447.7-39447.30" + process $proc$libresoc.v:39447$2904 assign { } { } assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:39191.7-39191.30" - process $proc$libresoc.v:39191$2905 + attribute \src "libresoc.v:39451.7-39451.30" + process $proc$libresoc.v:39451$2905 assign { } { } assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:39195.7-39195.30" - process $proc$libresoc.v:39195$2906 + attribute \src "libresoc.v:39455.7-39455.30" + process $proc$libresoc.v:39455$2906 assign { } { } assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:39199.7-39199.33" - process $proc$libresoc.v:39199$2907 + attribute \src "libresoc.v:39459.7-39459.33" + process $proc$libresoc.v:39459$2907 assign { } { } assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:39203.7-39203.37" - process $proc$libresoc.v:39203$2908 + attribute \src "libresoc.v:39463.7-39463.37" + process $proc$libresoc.v:39463$2908 assign { } { } assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:39207.7-39207.34" - process $proc$libresoc.v:39207$2909 + attribute \src "libresoc.v:39467.7-39467.34" + process $proc$libresoc.v:39467$2909 assign { } { } assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 sync always sync init update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:39211.7-39211.35" - process $proc$libresoc.v:39211$2910 + attribute \src "libresoc.v:39471.7-39471.35" + process $proc$libresoc.v:39471$2910 assign { } { } assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:39215.7-39215.37" - process $proc$libresoc.v:39215$2911 + attribute \src "libresoc.v:39475.7-39475.37" + process $proc$libresoc.v:39475$2911 assign { } { } assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:39219.7-39219.35" - process $proc$libresoc.v:39219$2912 + attribute \src "libresoc.v:39479.7-39479.35" + process $proc$libresoc.v:39479$2912 assign { } { } assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:39223.7-39223.30" - process $proc$libresoc.v:39223$2913 + attribute \src "libresoc.v:39483.7-39483.30" + process $proc$libresoc.v:39483$2913 assign { } { } assign $1\dp_INT_ra_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:39227.7-39227.29" - process $proc$libresoc.v:39227$2914 + attribute \src "libresoc.v:39487.7-39487.29" + process $proc$libresoc.v:39487$2914 assign { } { } assign $1\dp_INT_ra_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:39231.7-39231.30" - process $proc$libresoc.v:39231$2915 + attribute \src "libresoc.v:39491.7-39491.30" + process $proc$libresoc.v:39491$2915 assign { } { } assign $1\dp_INT_ra_div0_5[0:0] 1'0 sync always sync init update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:39235.7-39235.31" - process $proc$libresoc.v:39235$2916 + attribute \src "libresoc.v:39495.7-39495.31" + process $proc$libresoc.v:39495$2916 assign { } { } assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 sync always sync init update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:39239.7-39239.34" - process $proc$libresoc.v:39239$2917 + attribute \src "libresoc.v:39499.7-39499.34" + process $proc$libresoc.v:39499$2917 assign { } { } assign $1\dp_INT_ra_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:39243.7-39243.30" - process $proc$libresoc.v:39243$2918 + attribute \src "libresoc.v:39503.7-39503.30" + process $proc$libresoc.v:39503$2918 assign { } { } assign $1\dp_INT_ra_mul0_6[0:0] 1'0 sync always sync init update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:39247.7-39247.35" - process $proc$libresoc.v:39247$2919 + attribute \src "libresoc.v:39507.7-39507.35" + process $proc$libresoc.v:39507$2919 assign { } { } assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 sync always sync init update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:39251.7-39251.30" - process $proc$libresoc.v:39251$2920 + attribute \src "libresoc.v:39511.7-39511.30" + process $proc$libresoc.v:39511$2920 assign { } { } assign $1\dp_INT_ra_spr0_4[0:0] 1'0 sync always sync init update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:39255.7-39255.31" - process $proc$libresoc.v:39255$2921 + attribute \src "libresoc.v:39515.7-39515.31" + process $proc$libresoc.v:39515$2921 assign { } { } assign $1\dp_INT_ra_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:39259.7-39259.30" - process $proc$libresoc.v:39259$2922 + attribute \src "libresoc.v:39519.7-39519.30" + process $proc$libresoc.v:39519$2922 assign { } { } assign $1\dp_INT_rb_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:39263.7-39263.29" - process $proc$libresoc.v:39263$2923 + attribute \src "libresoc.v:39523.7-39523.29" + process $proc$libresoc.v:39523$2923 assign { } { } assign $1\dp_INT_rb_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:39267.7-39267.30" - process $proc$libresoc.v:39267$2924 + attribute \src "libresoc.v:39527.7-39527.30" + process $proc$libresoc.v:39527$2924 assign { } { } assign $1\dp_INT_rb_div0_4[0:0] 1'0 sync always sync init update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:39271.7-39271.31" - process $proc$libresoc.v:39271$2925 + attribute \src "libresoc.v:39531.7-39531.31" + process $proc$libresoc.v:39531$2925 assign { } { } assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 sync always sync init update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:39275.7-39275.34" - process $proc$libresoc.v:39275$2926 + attribute \src "libresoc.v:39535.7-39535.34" + process $proc$libresoc.v:39535$2926 assign { } { } assign $1\dp_INT_rb_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:39279.7-39279.30" - process $proc$libresoc.v:39279$2927 + attribute \src "libresoc.v:39539.7-39539.30" + process $proc$libresoc.v:39539$2927 assign { } { } assign $1\dp_INT_rb_mul0_5[0:0] 1'0 sync always sync init update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:39283.7-39283.35" - process $proc$libresoc.v:39283$2928 + attribute \src "libresoc.v:39543.7-39543.35" + process $proc$libresoc.v:39543$2928 assign { } { } assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 sync always sync init update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:39287.7-39287.31" - process $proc$libresoc.v:39287$2929 + attribute \src "libresoc.v:39547.7-39547.31" + process $proc$libresoc.v:39547$2929 assign { } { } assign $1\dp_INT_rb_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:39291.7-39291.31" - process $proc$libresoc.v:39291$2930 + attribute \src "libresoc.v:39551.7-39551.31" + process $proc$libresoc.v:39551$2930 assign { } { } assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 sync always sync init update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:39295.7-39295.35" - process $proc$libresoc.v:39295$2931 + attribute \src "libresoc.v:39555.7-39555.35" + process $proc$libresoc.v:39555$2931 assign { } { } assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 sync always sync init update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:39299.7-39299.32" - process $proc$libresoc.v:39299$2932 + attribute \src "libresoc.v:39559.7-39559.32" + process $proc$libresoc.v:39559$2932 assign { } { } assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 sync always sync init update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:39303.7-39303.34" - process $proc$libresoc.v:39303$2933 + attribute \src "libresoc.v:39563.7-39563.34" + process $proc$libresoc.v:39563$2933 assign { } { } assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:39307.7-39307.39" - process $proc$libresoc.v:39307$2934 + attribute \src "libresoc.v:39567.7-39567.39" + process $proc$libresoc.v:39567$2934 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:39311.7-39311.34" - process $proc$libresoc.v:39311$2935 + attribute \src "libresoc.v:39571.7-39571.34" + process $proc$libresoc.v:39571$2935 assign { } { } assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:39315.7-39315.34" - process $proc$libresoc.v:39315$2936 + attribute \src "libresoc.v:39575.7-39575.34" + process $proc$libresoc.v:39575$2936 assign { } { } assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:39319.7-39319.34" - process $proc$libresoc.v:39319$2937 + attribute \src "libresoc.v:39579.7-39579.34" + process $proc$libresoc.v:39579$2937 assign { } { } assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:39323.7-39323.34" - process $proc$libresoc.v:39323$2938 + attribute \src "libresoc.v:39583.7-39583.34" + process $proc$libresoc.v:39583$2938 assign { } { } assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 sync always sync init update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:39327.7-39327.38" - process $proc$libresoc.v:39327$2939 + attribute \src "libresoc.v:39587.7-39587.38" + process $proc$libresoc.v:39587$2939 assign { } { } assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:39331.7-39331.34" - process $proc$libresoc.v:39331$2940 + attribute \src "libresoc.v:39591.7-39591.34" + process $proc$libresoc.v:39591$2940 assign { } { } assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 sync always sync init update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:39335.7-39335.39" - process $proc$libresoc.v:39335$2941 + attribute \src "libresoc.v:39595.7-39595.39" + process $proc$libresoc.v:39595$2941 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 sync always sync init update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:39339.7-39339.34" - process $proc$libresoc.v:39339$2942 + attribute \src "libresoc.v:39599.7-39599.34" + process $proc$libresoc.v:39599$2942 assign { } { } assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:41432.7-41432.25" - process $proc$libresoc.v:41432$2943 + attribute \src "libresoc.v:41724.7-41724.25" + process $proc$libresoc.v:41724$2943 assign { } { } assign $1\wr_pick_dly[0:0] 1'0 sync always sync init update \wr_pick_dly $1\wr_pick_dly[0:0] end - attribute \src "libresoc.v:41434.7-41434.32" - process $proc$libresoc.v:41434$2944 + attribute \src "libresoc.v:41726.7-41726.32" + process $proc$libresoc.v:41726$2944 assign { } { } - assign $0\wr_pick_dly$1005[0:0]$2945 1'0 + assign $0\wr_pick_dly$1010[0:0]$2945 1'0 sync always sync init - update \wr_pick_dly$1005 $0\wr_pick_dly$1005[0:0]$2945 + update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2945 end - attribute \src "libresoc.v:41438.7-41438.32" - process $proc$libresoc.v:41438$2946 + attribute \src "libresoc.v:41730.7-41730.32" + process $proc$libresoc.v:41730$2946 assign { } { } - assign $0\wr_pick_dly$1026[0:0]$2947 1'0 + assign $0\wr_pick_dly$1031[0:0]$2947 1'0 sync always sync init - update \wr_pick_dly$1026 $0\wr_pick_dly$1026[0:0]$2947 + update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2947 end - attribute \src "libresoc.v:41442.7-41442.32" - process $proc$libresoc.v:41442$2948 + attribute \src "libresoc.v:41734.7-41734.32" + process $proc$libresoc.v:41734$2948 assign { } { } - assign $0\wr_pick_dly$1044[0:0]$2949 1'0 + assign $0\wr_pick_dly$1049[0:0]$2949 1'0 sync always sync init - update \wr_pick_dly$1044 $0\wr_pick_dly$1044[0:0]$2949 + update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2949 end - attribute \src "libresoc.v:41446.7-41446.32" - process $proc$libresoc.v:41446$2950 + attribute \src "libresoc.v:41738.7-41738.32" + process $proc$libresoc.v:41738$2950 assign { } { } - assign $0\wr_pick_dly$1066[0:0]$2951 1'0 + assign $0\wr_pick_dly$1071[0:0]$2951 1'0 sync always sync init - update \wr_pick_dly$1066 $0\wr_pick_dly$1066[0:0]$2951 + update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2951 end - attribute \src "libresoc.v:41450.7-41450.32" - process $proc$libresoc.v:41450$2952 + attribute \src "libresoc.v:41742.7-41742.32" + process $proc$libresoc.v:41742$2952 assign { } { } - assign $0\wr_pick_dly$1086[0:0]$2953 1'0 + assign $0\wr_pick_dly$1091[0:0]$2953 1'0 sync always sync init - update \wr_pick_dly$1086 $0\wr_pick_dly$1086[0:0]$2953 + update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2953 end - attribute \src "libresoc.v:41454.7-41454.32" - process $proc$libresoc.v:41454$2954 + attribute \src "libresoc.v:41746.7-41746.32" + process $proc$libresoc.v:41746$2954 assign { } { } - assign $0\wr_pick_dly$1106[0:0]$2955 1'0 + assign $0\wr_pick_dly$1111[0:0]$2955 1'0 sync always sync init - update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2955 + update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2955 end - attribute \src "libresoc.v:41458.7-41458.32" - process $proc$libresoc.v:41458$2956 + attribute \src "libresoc.v:41750.7-41750.32" + process $proc$libresoc.v:41750$2956 assign { } { } - assign $0\wr_pick_dly$1125[0:0]$2957 1'0 + assign $0\wr_pick_dly$1130[0:0]$2957 1'0 sync always sync init - update \wr_pick_dly$1125 $0\wr_pick_dly$1125[0:0]$2957 + update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2957 end - attribute \src "libresoc.v:41462.7-41462.32" - process $proc$libresoc.v:41462$2958 + attribute \src "libresoc.v:41754.7-41754.32" + process $proc$libresoc.v:41754$2958 assign { } { } - assign $0\wr_pick_dly$1143[0:0]$2959 1'0 + assign $0\wr_pick_dly$1148[0:0]$2959 1'0 sync always sync init - update \wr_pick_dly$1143 $0\wr_pick_dly$1143[0:0]$2959 + update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2959 end - attribute \src "libresoc.v:41466.7-41466.32" - process $proc$libresoc.v:41466$2960 + attribute \src "libresoc.v:41758.7-41758.32" + process $proc$libresoc.v:41758$2960 assign { } { } - assign $0\wr_pick_dly$1217[0:0]$2961 1'0 + assign $0\wr_pick_dly$1222[0:0]$2961 1'0 sync always sync init - update \wr_pick_dly$1217 $0\wr_pick_dly$1217[0:0]$2961 + update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2961 end - attribute \src "libresoc.v:41470.7-41470.32" - process $proc$libresoc.v:41470$2962 + attribute \src "libresoc.v:41762.7-41762.32" + process $proc$libresoc.v:41762$2962 assign { } { } - assign $0\wr_pick_dly$1245[0:0]$2963 1'0 + assign $0\wr_pick_dly$1250[0:0]$2963 1'0 sync always sync init - update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2963 + update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2963 end - attribute \src "libresoc.v:41474.7-41474.32" - process $proc$libresoc.v:41474$2964 + attribute \src "libresoc.v:41766.7-41766.32" + process $proc$libresoc.v:41766$2964 assign { } { } - assign $0\wr_pick_dly$1265[0:0]$2965 1'0 + assign $0\wr_pick_dly$1270[0:0]$2965 1'0 sync always sync init - update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2965 + update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2965 end - attribute \src "libresoc.v:41478.7-41478.32" - process $proc$libresoc.v:41478$2966 + attribute \src "libresoc.v:41770.7-41770.32" + process $proc$libresoc.v:41770$2966 assign { } { } - assign $0\wr_pick_dly$1285[0:0]$2967 1'0 + assign $0\wr_pick_dly$1290[0:0]$2967 1'0 sync always sync init - update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2967 + update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2967 end - attribute \src "libresoc.v:41482.7-41482.32" - process $proc$libresoc.v:41482$2968 + attribute \src "libresoc.v:41774.7-41774.32" + process $proc$libresoc.v:41774$2968 assign { } { } - assign $0\wr_pick_dly$1305[0:0]$2969 1'0 + assign $0\wr_pick_dly$1310[0:0]$2969 1'0 sync always sync init - update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2969 + update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2969 end - attribute \src "libresoc.v:41486.7-41486.32" - process $proc$libresoc.v:41486$2970 + attribute \src "libresoc.v:41778.7-41778.32" + process $proc$libresoc.v:41778$2970 assign { } { } - assign $0\wr_pick_dly$1325[0:0]$2971 1'0 + assign $0\wr_pick_dly$1330[0:0]$2971 1'0 sync always sync init - update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2971 + update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2971 end - attribute \src "libresoc.v:41490.7-41490.32" - process $proc$libresoc.v:41490$2972 + attribute \src "libresoc.v:41782.7-41782.32" + process $proc$libresoc.v:41782$2972 assign { } { } - assign $0\wr_pick_dly$1345[0:0]$2973 1'0 + assign $0\wr_pick_dly$1350[0:0]$2973 1'0 sync always sync init - update \wr_pick_dly$1345 $0\wr_pick_dly$1345[0:0]$2973 + update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2973 end - attribute \src "libresoc.v:41494.7-41494.32" - process $proc$libresoc.v:41494$2974 + attribute \src "libresoc.v:41786.7-41786.32" + process $proc$libresoc.v:41786$2974 assign { } { } - assign $0\wr_pick_dly$1392[0:0]$2975 1'0 + assign $0\wr_pick_dly$1397[0:0]$2975 1'0 sync always sync init - update \wr_pick_dly$1392 $0\wr_pick_dly$1392[0:0]$2975 + update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2975 end - attribute \src "libresoc.v:41498.7-41498.32" - process $proc$libresoc.v:41498$2976 + attribute \src "libresoc.v:41790.7-41790.32" + process $proc$libresoc.v:41790$2976 assign { } { } - assign $0\wr_pick_dly$1408[0:0]$2977 1'0 + assign $0\wr_pick_dly$1413[0:0]$2977 1'0 sync always sync init - update \wr_pick_dly$1408 $0\wr_pick_dly$1408[0:0]$2977 + update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2977 end - attribute \src "libresoc.v:41502.7-41502.32" - process $proc$libresoc.v:41502$2978 + attribute \src "libresoc.v:41794.7-41794.32" + process $proc$libresoc.v:41794$2978 assign { } { } - assign $0\wr_pick_dly$1424[0:0]$2979 1'0 + assign $0\wr_pick_dly$1429[0:0]$2979 1'0 sync always sync init - update \wr_pick_dly$1424 $0\wr_pick_dly$1424[0:0]$2979 + update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2979 end - attribute \src "libresoc.v:41506.7-41506.32" - process $proc$libresoc.v:41506$2980 + attribute \src "libresoc.v:41798.7-41798.32" + process $proc$libresoc.v:41798$2980 assign { } { } - assign $0\wr_pick_dly$1458[0:0]$2981 1'0 + assign $0\wr_pick_dly$1463[0:0]$2981 1'0 sync always sync init - update \wr_pick_dly$1458 $0\wr_pick_dly$1458[0:0]$2981 + update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2981 end - attribute \src "libresoc.v:41510.7-41510.32" - process $proc$libresoc.v:41510$2982 + attribute \src "libresoc.v:41802.7-41802.32" + process $proc$libresoc.v:41802$2982 assign { } { } - assign $0\wr_pick_dly$1474[0:0]$2983 1'0 + assign $0\wr_pick_dly$1479[0:0]$2983 1'0 sync always sync init - update \wr_pick_dly$1474 $0\wr_pick_dly$1474[0:0]$2983 + update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2983 end - attribute \src "libresoc.v:41514.7-41514.32" - process $proc$libresoc.v:41514$2984 + attribute \src "libresoc.v:41806.7-41806.32" + process $proc$libresoc.v:41806$2984 assign { } { } - assign $0\wr_pick_dly$1490[0:0]$2985 1'0 + assign $0\wr_pick_dly$1495[0:0]$2985 1'0 sync always sync init - update \wr_pick_dly$1490 $0\wr_pick_dly$1490[0:0]$2985 + update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2985 end - attribute \src "libresoc.v:41518.7-41518.32" - process $proc$libresoc.v:41518$2986 + attribute \src "libresoc.v:41810.7-41810.32" + process $proc$libresoc.v:41810$2986 assign { } { } - assign $0\wr_pick_dly$1506[0:0]$2987 1'0 + assign $0\wr_pick_dly$1511[0:0]$2987 1'0 sync always sync init - update \wr_pick_dly$1506 $0\wr_pick_dly$1506[0:0]$2987 + update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2987 end - attribute \src "libresoc.v:41522.7-41522.32" - process $proc$libresoc.v:41522$2988 + attribute \src "libresoc.v:41814.7-41814.32" + process $proc$libresoc.v:41814$2988 assign { } { } - assign $0\wr_pick_dly$1542[0:0]$2989 1'0 + assign $0\wr_pick_dly$1547[0:0]$2989 1'0 sync always sync init - update \wr_pick_dly$1542 $0\wr_pick_dly$1542[0:0]$2989 + update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2989 end - attribute \src "libresoc.v:41526.7-41526.32" - process $proc$libresoc.v:41526$2990 + attribute \src "libresoc.v:41818.7-41818.32" + process $proc$libresoc.v:41818$2990 assign { } { } - assign $0\wr_pick_dly$1558[0:0]$2991 1'0 + assign $0\wr_pick_dly$1563[0:0]$2991 1'0 sync always sync init - update \wr_pick_dly$1558 $0\wr_pick_dly$1558[0:0]$2991 + update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2991 end - attribute \src "libresoc.v:41530.7-41530.32" - process $proc$libresoc.v:41530$2992 + attribute \src "libresoc.v:41822.7-41822.32" + process $proc$libresoc.v:41822$2992 assign { } { } - assign $0\wr_pick_dly$1574[0:0]$2993 1'0 + assign $0\wr_pick_dly$1579[0:0]$2993 1'0 sync always sync init - update \wr_pick_dly$1574 $0\wr_pick_dly$1574[0:0]$2993 + update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2993 end - attribute \src "libresoc.v:41534.7-41534.32" - process $proc$libresoc.v:41534$2994 + attribute \src "libresoc.v:41826.7-41826.32" + process $proc$libresoc.v:41826$2994 assign { } { } - assign $0\wr_pick_dly$1590[0:0]$2995 1'0 + assign $0\wr_pick_dly$1595[0:0]$2995 1'0 sync always sync init - update \wr_pick_dly$1590 $0\wr_pick_dly$1590[0:0]$2995 + update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2995 end - attribute \src "libresoc.v:41538.7-41538.32" - process $proc$libresoc.v:41538$2996 + attribute \src "libresoc.v:41830.7-41830.32" + process $proc$libresoc.v:41830$2996 assign { } { } - assign $0\wr_pick_dly$1632[0:0]$2997 1'0 + assign $0\wr_pick_dly$1637[0:0]$2997 1'0 sync always sync init - update \wr_pick_dly$1632 $0\wr_pick_dly$1632[0:0]$2997 + update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2997 end - attribute \src "libresoc.v:41542.7-41542.32" - process $proc$libresoc.v:41542$2998 + attribute \src "libresoc.v:41834.7-41834.32" + process $proc$libresoc.v:41834$2998 assign { } { } - assign $0\wr_pick_dly$1651[0:0]$2999 1'0 + assign $0\wr_pick_dly$1656[0:0]$2999 1'0 sync always sync init - update \wr_pick_dly$1651 $0\wr_pick_dly$1651[0:0]$2999 + update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2999 end - attribute \src "libresoc.v:41546.7-41546.32" - process $proc$libresoc.v:41546$3000 + attribute \src "libresoc.v:41838.7-41838.32" + process $proc$libresoc.v:41838$3000 assign { } { } - assign $0\wr_pick_dly$1667[0:0]$3001 1'0 + assign $0\wr_pick_dly$1672[0:0]$3001 1'0 sync always sync init - update \wr_pick_dly$1667 $0\wr_pick_dly$1667[0:0]$3001 + update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$3001 end - attribute \src "libresoc.v:41550.7-41550.32" - process $proc$libresoc.v:41550$3002 + attribute \src "libresoc.v:41842.7-41842.32" + process $proc$libresoc.v:41842$3002 assign { } { } - assign $0\wr_pick_dly$1683[0:0]$3003 1'0 + assign $0\wr_pick_dly$1688[0:0]$3003 1'0 sync always sync init - update \wr_pick_dly$1683 $0\wr_pick_dly$1683[0:0]$3003 + update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$3003 end - attribute \src "libresoc.v:41554.7-41554.32" - process $proc$libresoc.v:41554$3004 + attribute \src "libresoc.v:41846.7-41846.32" + process $proc$libresoc.v:41846$3004 assign { } { } - assign $0\wr_pick_dly$1699[0:0]$3005 1'0 + assign $0\wr_pick_dly$1704[0:0]$3005 1'0 sync always sync init - update \wr_pick_dly$1699 $0\wr_pick_dly$1699[0:0]$3005 + update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$3005 end - attribute \src "libresoc.v:41558.7-41558.32" - process $proc$libresoc.v:41558$3006 + attribute \src "libresoc.v:41850.7-41850.32" + process $proc$libresoc.v:41850$3006 assign { } { } - assign $0\wr_pick_dly$1743[0:0]$3007 1'0 + assign $0\wr_pick_dly$1748[0:0]$3007 1'0 sync always sync init - update \wr_pick_dly$1743 $0\wr_pick_dly$1743[0:0]$3007 + update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$3007 end - attribute \src "libresoc.v:41562.7-41562.32" - process $proc$libresoc.v:41562$3008 + attribute \src "libresoc.v:41854.7-41854.32" + process $proc$libresoc.v:41854$3008 assign { } { } - assign $0\wr_pick_dly$1759[0:0]$3009 1'0 + assign $0\wr_pick_dly$1764[0:0]$3009 1'0 sync always sync init - update \wr_pick_dly$1759 $0\wr_pick_dly$1759[0:0]$3009 + update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$3009 end - attribute \src "libresoc.v:41566.7-41566.32" - process $proc$libresoc.v:41566$3010 + attribute \src "libresoc.v:41858.7-41858.32" + process $proc$libresoc.v:41858$3010 assign { } { } - assign $0\wr_pick_dly$1783[0:0]$3011 1'0 + assign $0\wr_pick_dly$1788[0:0]$3011 1'0 sync always sync init - update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$3011 + update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$3011 end - attribute \src "libresoc.v:41570.7-41570.32" - process $proc$libresoc.v:41570$3012 + attribute \src "libresoc.v:41862.7-41862.32" + process $proc$libresoc.v:41862$3012 assign { } { } - assign $0\wr_pick_dly$1803[0:0]$3013 1'0 + assign $0\wr_pick_dly$1808[0:0]$3013 1'0 sync always sync init - update \wr_pick_dly$1803 $0\wr_pick_dly$1803[0:0]$3013 + update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$3013 end - attribute \src "libresoc.v:41574.7-41574.31" - process $proc$libresoc.v:41574$3014 + attribute \src "libresoc.v:41866.7-41866.31" + process $proc$libresoc.v:41866$3014 assign { } { } - assign $0\wr_pick_dly$986[0:0]$3015 1'0 + assign $0\wr_pick_dly$991[0:0]$3015 1'0 sync always sync init - update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$3015 + update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$3015 end - attribute \src "libresoc.v:42536.3-42537.51" - process $proc$libresoc.v:42536$2238 + attribute \src "libresoc.v:42828.3-42829.51" + process $proc$libresoc.v:42828$2238 assign { } { } - assign $0\wr_pick_dly$1803[0:0]$2239 \wr_pick_dly$1803$next + assign $0\wr_pick_dly$1808[0:0]$2239 \wr_pick_dly$1808$next sync posedge \coresync_clk - update \wr_pick_dly$1803 $0\wr_pick_dly$1803[0:0]$2239 + update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$2239 end - attribute \src "libresoc.v:42538.3-42539.51" - process $proc$libresoc.v:42538$2240 + attribute \src "libresoc.v:42830.3-42831.51" + process $proc$libresoc.v:42830$2240 assign { } { } - assign $0\wr_pick_dly$1783[0:0]$2241 \wr_pick_dly$1783$next + assign $0\wr_pick_dly$1788[0:0]$2241 \wr_pick_dly$1788$next sync posedge \coresync_clk - update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2241 + update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$2241 end - attribute \src "libresoc.v:42540.3-42541.51" - process $proc$libresoc.v:42540$2242 + attribute \src "libresoc.v:42832.3-42833.51" + process $proc$libresoc.v:42832$2242 assign { } { } - assign $0\wr_pick_dly$1759[0:0]$2243 \wr_pick_dly$1759$next + assign $0\wr_pick_dly$1764[0:0]$2243 \wr_pick_dly$1764$next sync posedge \coresync_clk - update \wr_pick_dly$1759 $0\wr_pick_dly$1759[0:0]$2243 + update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$2243 end - attribute \src "libresoc.v:42542.3-42543.51" - process $proc$libresoc.v:42542$2244 + attribute \src "libresoc.v:42834.3-42835.51" + process $proc$libresoc.v:42834$2244 assign { } { } - assign $0\wr_pick_dly$1743[0:0]$2245 \wr_pick_dly$1743$next + assign $0\wr_pick_dly$1748[0:0]$2245 \wr_pick_dly$1748$next sync posedge \coresync_clk - update \wr_pick_dly$1743 $0\wr_pick_dly$1743[0:0]$2245 + update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$2245 end - attribute \src "libresoc.v:42544.3-42545.51" - process $proc$libresoc.v:42544$2246 + attribute \src "libresoc.v:42836.3-42837.51" + process $proc$libresoc.v:42836$2246 assign { } { } - assign $0\wr_pick_dly$1699[0:0]$2247 \wr_pick_dly$1699$next + assign $0\wr_pick_dly$1704[0:0]$2247 \wr_pick_dly$1704$next sync posedge \coresync_clk - update \wr_pick_dly$1699 $0\wr_pick_dly$1699[0:0]$2247 + update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$2247 end - attribute \src "libresoc.v:42546.3-42547.51" - process $proc$libresoc.v:42546$2248 + attribute \src "libresoc.v:42838.3-42839.51" + process $proc$libresoc.v:42838$2248 assign { } { } - assign $0\wr_pick_dly$1683[0:0]$2249 \wr_pick_dly$1683$next + assign $0\wr_pick_dly$1688[0:0]$2249 \wr_pick_dly$1688$next sync posedge \coresync_clk - update \wr_pick_dly$1683 $0\wr_pick_dly$1683[0:0]$2249 + update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$2249 end - attribute \src "libresoc.v:42548.3-42549.51" - process $proc$libresoc.v:42548$2250 + attribute \src "libresoc.v:42840.3-42841.51" + process $proc$libresoc.v:42840$2250 assign { } { } - assign $0\wr_pick_dly$1667[0:0]$2251 \wr_pick_dly$1667$next + assign $0\wr_pick_dly$1672[0:0]$2251 \wr_pick_dly$1672$next sync posedge \coresync_clk - update \wr_pick_dly$1667 $0\wr_pick_dly$1667[0:0]$2251 + update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$2251 end - attribute \src "libresoc.v:42550.3-42551.51" - process $proc$libresoc.v:42550$2252 + attribute \src "libresoc.v:42842.3-42843.51" + process $proc$libresoc.v:42842$2252 assign { } { } - assign $0\wr_pick_dly$1651[0:0]$2253 \wr_pick_dly$1651$next + assign $0\wr_pick_dly$1656[0:0]$2253 \wr_pick_dly$1656$next sync posedge \coresync_clk - update \wr_pick_dly$1651 $0\wr_pick_dly$1651[0:0]$2253 + update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2253 end - attribute \src "libresoc.v:42552.3-42553.51" - process $proc$libresoc.v:42552$2254 + attribute \src "libresoc.v:42844.3-42845.51" + process $proc$libresoc.v:42844$2254 assign { } { } - assign $0\wr_pick_dly$1632[0:0]$2255 \wr_pick_dly$1632$next + assign $0\wr_pick_dly$1637[0:0]$2255 \wr_pick_dly$1637$next sync posedge \coresync_clk - update \wr_pick_dly$1632 $0\wr_pick_dly$1632[0:0]$2255 + update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2255 end - attribute \src "libresoc.v:42554.3-42555.51" - process $proc$libresoc.v:42554$2256 + attribute \src "libresoc.v:42846.3-42847.51" + process $proc$libresoc.v:42846$2256 assign { } { } - assign $0\wr_pick_dly$1590[0:0]$2257 \wr_pick_dly$1590$next + assign $0\wr_pick_dly$1595[0:0]$2257 \wr_pick_dly$1595$next sync posedge \coresync_clk - update \wr_pick_dly$1590 $0\wr_pick_dly$1590[0:0]$2257 + update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2257 end - attribute \src "libresoc.v:42556.3-42557.51" - process $proc$libresoc.v:42556$2258 + attribute \src "libresoc.v:42848.3-42849.51" + process $proc$libresoc.v:42848$2258 assign { } { } - assign $0\wr_pick_dly$1574[0:0]$2259 \wr_pick_dly$1574$next + assign $0\wr_pick_dly$1579[0:0]$2259 \wr_pick_dly$1579$next sync posedge \coresync_clk - update \wr_pick_dly$1574 $0\wr_pick_dly$1574[0:0]$2259 + update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2259 end - attribute \src "libresoc.v:42558.3-42559.51" - process $proc$libresoc.v:42558$2260 + attribute \src "libresoc.v:42850.3-42851.51" + process $proc$libresoc.v:42850$2260 assign { } { } - assign $0\wr_pick_dly$1558[0:0]$2261 \wr_pick_dly$1558$next + assign $0\wr_pick_dly$1563[0:0]$2261 \wr_pick_dly$1563$next sync posedge \coresync_clk - update \wr_pick_dly$1558 $0\wr_pick_dly$1558[0:0]$2261 + update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2261 end - attribute \src "libresoc.v:42560.3-42561.51" - process $proc$libresoc.v:42560$2262 + attribute \src "libresoc.v:42852.3-42853.51" + process $proc$libresoc.v:42852$2262 assign { } { } - assign $0\wr_pick_dly$1542[0:0]$2263 \wr_pick_dly$1542$next + assign $0\wr_pick_dly$1547[0:0]$2263 \wr_pick_dly$1547$next sync posedge \coresync_clk - update \wr_pick_dly$1542 $0\wr_pick_dly$1542[0:0]$2263 + update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2263 end - attribute \src "libresoc.v:42562.3-42563.51" - process $proc$libresoc.v:42562$2264 + attribute \src "libresoc.v:42854.3-42855.51" + process $proc$libresoc.v:42854$2264 assign { } { } - assign $0\wr_pick_dly$1506[0:0]$2265 \wr_pick_dly$1506$next + assign $0\wr_pick_dly$1511[0:0]$2265 \wr_pick_dly$1511$next sync posedge \coresync_clk - update \wr_pick_dly$1506 $0\wr_pick_dly$1506[0:0]$2265 + update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2265 end - attribute \src "libresoc.v:42564.3-42565.51" - process $proc$libresoc.v:42564$2266 + attribute \src "libresoc.v:42856.3-42857.51" + process $proc$libresoc.v:42856$2266 assign { } { } - assign $0\wr_pick_dly$1490[0:0]$2267 \wr_pick_dly$1490$next + assign $0\wr_pick_dly$1495[0:0]$2267 \wr_pick_dly$1495$next sync posedge \coresync_clk - update \wr_pick_dly$1490 $0\wr_pick_dly$1490[0:0]$2267 + update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2267 end - attribute \src "libresoc.v:42566.3-42567.51" - process $proc$libresoc.v:42566$2268 + attribute \src "libresoc.v:42858.3-42859.51" + process $proc$libresoc.v:42858$2268 assign { } { } - assign $0\wr_pick_dly$1474[0:0]$2269 \wr_pick_dly$1474$next + assign $0\wr_pick_dly$1479[0:0]$2269 \wr_pick_dly$1479$next sync posedge \coresync_clk - update \wr_pick_dly$1474 $0\wr_pick_dly$1474[0:0]$2269 + update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2269 end - attribute \src "libresoc.v:42568.3-42569.51" - process $proc$libresoc.v:42568$2270 + attribute \src "libresoc.v:42860.3-42861.51" + process $proc$libresoc.v:42860$2270 assign { } { } - assign $0\wr_pick_dly$1458[0:0]$2271 \wr_pick_dly$1458$next + assign $0\wr_pick_dly$1463[0:0]$2271 \wr_pick_dly$1463$next sync posedge \coresync_clk - update \wr_pick_dly$1458 $0\wr_pick_dly$1458[0:0]$2271 + update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2271 end - attribute \src "libresoc.v:42570.3-42571.51" - process $proc$libresoc.v:42570$2272 + attribute \src "libresoc.v:42862.3-42863.51" + process $proc$libresoc.v:42862$2272 assign { } { } - assign $0\wr_pick_dly$1424[0:0]$2273 \wr_pick_dly$1424$next + assign $0\wr_pick_dly$1429[0:0]$2273 \wr_pick_dly$1429$next sync posedge \coresync_clk - update \wr_pick_dly$1424 $0\wr_pick_dly$1424[0:0]$2273 + update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2273 end - attribute \src "libresoc.v:42572.3-42573.51" - process $proc$libresoc.v:42572$2274 + attribute \src "libresoc.v:42864.3-42865.51" + process $proc$libresoc.v:42864$2274 assign { } { } - assign $0\wr_pick_dly$1408[0:0]$2275 \wr_pick_dly$1408$next + assign $0\wr_pick_dly$1413[0:0]$2275 \wr_pick_dly$1413$next sync posedge \coresync_clk - update \wr_pick_dly$1408 $0\wr_pick_dly$1408[0:0]$2275 + update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2275 end - attribute \src "libresoc.v:42574.3-42575.51" - process $proc$libresoc.v:42574$2276 + attribute \src "libresoc.v:42866.3-42867.51" + process $proc$libresoc.v:42866$2276 assign { } { } - assign $0\wr_pick_dly$1392[0:0]$2277 \wr_pick_dly$1392$next + assign $0\wr_pick_dly$1397[0:0]$2277 \wr_pick_dly$1397$next sync posedge \coresync_clk - update \wr_pick_dly$1392 $0\wr_pick_dly$1392[0:0]$2277 + update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2277 end - attribute \src "libresoc.v:42576.3-42577.51" - process $proc$libresoc.v:42576$2278 + attribute \src "libresoc.v:42868.3-42869.51" + process $proc$libresoc.v:42868$2278 assign { } { } - assign $0\wr_pick_dly$1345[0:0]$2279 \wr_pick_dly$1345$next + assign $0\wr_pick_dly$1350[0:0]$2279 \wr_pick_dly$1350$next sync posedge \coresync_clk - update \wr_pick_dly$1345 $0\wr_pick_dly$1345[0:0]$2279 + update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2279 end - attribute \src "libresoc.v:42578.3-42579.51" - process $proc$libresoc.v:42578$2280 + attribute \src "libresoc.v:42870.3-42871.51" + process $proc$libresoc.v:42870$2280 assign { } { } - assign $0\wr_pick_dly$1325[0:0]$2281 \wr_pick_dly$1325$next + assign $0\wr_pick_dly$1330[0:0]$2281 \wr_pick_dly$1330$next sync posedge \coresync_clk - update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2281 + update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2281 end - attribute \src "libresoc.v:42580.3-42581.51" - process $proc$libresoc.v:42580$2282 + attribute \src "libresoc.v:42872.3-42873.51" + process $proc$libresoc.v:42872$2282 assign { } { } - assign $0\wr_pick_dly$1305[0:0]$2283 \wr_pick_dly$1305$next + assign $0\wr_pick_dly$1310[0:0]$2283 \wr_pick_dly$1310$next sync posedge \coresync_clk - update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2283 + update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2283 end - attribute \src "libresoc.v:42582.3-42583.51" - process $proc$libresoc.v:42582$2284 + attribute \src "libresoc.v:42874.3-42875.51" + process $proc$libresoc.v:42874$2284 assign { } { } - assign $0\wr_pick_dly$1285[0:0]$2285 \wr_pick_dly$1285$next + assign $0\wr_pick_dly$1290[0:0]$2285 \wr_pick_dly$1290$next sync posedge \coresync_clk - update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2285 + update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2285 end - attribute \src "libresoc.v:42584.3-42585.51" - process $proc$libresoc.v:42584$2286 + attribute \src "libresoc.v:42876.3-42877.51" + process $proc$libresoc.v:42876$2286 assign { } { } - assign $0\wr_pick_dly$1265[0:0]$2287 \wr_pick_dly$1265$next + assign $0\wr_pick_dly$1270[0:0]$2287 \wr_pick_dly$1270$next sync posedge \coresync_clk - update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2287 + update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2287 end - attribute \src "libresoc.v:42586.3-42587.51" - process $proc$libresoc.v:42586$2288 + attribute \src "libresoc.v:42878.3-42879.51" + process $proc$libresoc.v:42878$2288 assign { } { } - assign $0\wr_pick_dly$1245[0:0]$2289 \wr_pick_dly$1245$next + assign $0\wr_pick_dly$1250[0:0]$2289 \wr_pick_dly$1250$next sync posedge \coresync_clk - update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2289 + update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2289 end - attribute \src "libresoc.v:42588.3-42589.51" - process $proc$libresoc.v:42588$2290 + attribute \src "libresoc.v:42880.3-42881.51" + process $proc$libresoc.v:42880$2290 assign { } { } - assign $0\wr_pick_dly$1217[0:0]$2291 \wr_pick_dly$1217$next + assign $0\wr_pick_dly$1222[0:0]$2291 \wr_pick_dly$1222$next sync posedge \coresync_clk - update \wr_pick_dly$1217 $0\wr_pick_dly$1217[0:0]$2291 + update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2291 end - attribute \src "libresoc.v:42590.3-42591.51" - process $proc$libresoc.v:42590$2292 + attribute \src "libresoc.v:42882.3-42883.51" + process $proc$libresoc.v:42882$2292 assign { } { } - assign $0\wr_pick_dly$1143[0:0]$2293 \wr_pick_dly$1143$next + assign $0\wr_pick_dly$1148[0:0]$2293 \wr_pick_dly$1148$next sync posedge \coresync_clk - update \wr_pick_dly$1143 $0\wr_pick_dly$1143[0:0]$2293 + update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2293 end - attribute \src "libresoc.v:42592.3-42593.51" - process $proc$libresoc.v:42592$2294 + attribute \src "libresoc.v:42884.3-42885.51" + process $proc$libresoc.v:42884$2294 assign { } { } - assign $0\wr_pick_dly$1125[0:0]$2295 \wr_pick_dly$1125$next + assign $0\wr_pick_dly$1130[0:0]$2295 \wr_pick_dly$1130$next sync posedge \coresync_clk - update \wr_pick_dly$1125 $0\wr_pick_dly$1125[0:0]$2295 + update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2295 end - attribute \src "libresoc.v:42594.3-42595.51" - process $proc$libresoc.v:42594$2296 + attribute \src "libresoc.v:42886.3-42887.51" + process $proc$libresoc.v:42886$2296 assign { } { } - assign $0\wr_pick_dly$1106[0:0]$2297 \wr_pick_dly$1106$next + assign $0\wr_pick_dly$1111[0:0]$2297 \wr_pick_dly$1111$next sync posedge \coresync_clk - update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2297 + update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2297 end - attribute \src "libresoc.v:42596.3-42597.51" - process $proc$libresoc.v:42596$2298 + attribute \src "libresoc.v:42888.3-42889.51" + process $proc$libresoc.v:42888$2298 assign { } { } - assign $0\wr_pick_dly$1086[0:0]$2299 \wr_pick_dly$1086$next + assign $0\wr_pick_dly$1091[0:0]$2299 \wr_pick_dly$1091$next sync posedge \coresync_clk - update \wr_pick_dly$1086 $0\wr_pick_dly$1086[0:0]$2299 + update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2299 end - attribute \src "libresoc.v:42598.3-42599.51" - process $proc$libresoc.v:42598$2300 + attribute \src "libresoc.v:42890.3-42891.51" + process $proc$libresoc.v:42890$2300 assign { } { } - assign $0\wr_pick_dly$1066[0:0]$2301 \wr_pick_dly$1066$next + assign $0\wr_pick_dly$1071[0:0]$2301 \wr_pick_dly$1071$next sync posedge \coresync_clk - update \wr_pick_dly$1066 $0\wr_pick_dly$1066[0:0]$2301 + update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2301 end - attribute \src "libresoc.v:42600.3-42601.51" - process $proc$libresoc.v:42600$2302 + attribute \src "libresoc.v:42892.3-42893.51" + process $proc$libresoc.v:42892$2302 assign { } { } - assign $0\wr_pick_dly$1044[0:0]$2303 \wr_pick_dly$1044$next + assign $0\wr_pick_dly$1049[0:0]$2303 \wr_pick_dly$1049$next sync posedge \coresync_clk - update \wr_pick_dly$1044 $0\wr_pick_dly$1044[0:0]$2303 + update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2303 end - attribute \src "libresoc.v:42602.3-42603.51" - process $proc$libresoc.v:42602$2304 + attribute \src "libresoc.v:42894.3-42895.51" + process $proc$libresoc.v:42894$2304 assign { } { } - assign $0\wr_pick_dly$1026[0:0]$2305 \wr_pick_dly$1026$next + assign $0\wr_pick_dly$1031[0:0]$2305 \wr_pick_dly$1031$next sync posedge \coresync_clk - update \wr_pick_dly$1026 $0\wr_pick_dly$1026[0:0]$2305 + update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2305 end - attribute \src "libresoc.v:42604.3-42605.51" - process $proc$libresoc.v:42604$2306 + attribute \src "libresoc.v:42896.3-42897.51" + process $proc$libresoc.v:42896$2306 assign { } { } - assign $0\wr_pick_dly$1005[0:0]$2307 \wr_pick_dly$1005$next + assign $0\wr_pick_dly$1010[0:0]$2307 \wr_pick_dly$1010$next sync posedge \coresync_clk - update \wr_pick_dly$1005 $0\wr_pick_dly$1005[0:0]$2307 + update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2307 end - attribute \src "libresoc.v:42606.3-42607.49" - process $proc$libresoc.v:42606$2308 + attribute \src "libresoc.v:42898.3-42899.49" + process $proc$libresoc.v:42898$2308 assign { } { } - assign $0\wr_pick_dly$986[0:0]$2309 \wr_pick_dly$986$next + assign $0\wr_pick_dly$991[0:0]$2309 \wr_pick_dly$991$next sync posedge \coresync_clk - update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2309 + update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$2309 end - attribute \src "libresoc.v:42608.3-42609.39" - process $proc$libresoc.v:42608$2310 + attribute \src "libresoc.v:42900.3-42901.39" + process $proc$libresoc.v:42900$2310 assign { } { } assign $0\wr_pick_dly[0:0] \wr_pick_dly$next sync posedge \coresync_clk update \wr_pick_dly $0\wr_pick_dly[0:0] end - attribute \src "libresoc.v:42610.3-42611.53" - process $proc$libresoc.v:42610$2311 + attribute \src "libresoc.v:42902.3-42903.53" + process $proc$libresoc.v:42902$2311 assign { } { } assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:42612.3-42613.59" - process $proc$libresoc.v:42612$2312 + attribute \src "libresoc.v:42904.3-42905.59" + process $proc$libresoc.v:42904$2312 assign { } { } assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:42614.3-42615.63" - process $proc$libresoc.v:42614$2313 + attribute \src "libresoc.v:42906.3-42907.63" + process $proc$libresoc.v:42906$2313 assign { } { } assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:42616.3-42617.57" - process $proc$libresoc.v:42616$2314 + attribute \src "libresoc.v:42908.3-42909.57" + process $proc$libresoc.v:42908$2314 assign { } { } assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:42618.3-42619.59" - process $proc$libresoc.v:42618$2315 + attribute \src "libresoc.v:42910.3-42911.59" + process $proc$libresoc.v:42910$2315 assign { } { } assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:42620.3-42621.63" - process $proc$libresoc.v:42620$2316 + attribute \src "libresoc.v:42912.3-42913.63" + process $proc$libresoc.v:42912$2316 assign { } { } assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:42622.3-42623.49" - process $proc$libresoc.v:42622$2317 + attribute \src "libresoc.v:42914.3-42915.49" + process $proc$libresoc.v:42914$2317 assign { } { } assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:42624.3-42625.49" - process $proc$libresoc.v:42624$2318 + attribute \src "libresoc.v:42916.3-42917.49" + process $proc$libresoc.v:42916$2318 assign { } { } assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:42626.3-42627.57" - process $proc$libresoc.v:42626$2319 + attribute \src "libresoc.v:42918.3-42919.57" + process $proc$libresoc.v:42918$2319 assign { } { } assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:42628.3-42629.49" - process $proc$libresoc.v:42628$2320 + attribute \src "libresoc.v:42920.3-42921.49" + process $proc$libresoc.v:42920$2320 assign { } { } assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:42630.3-42631.55" - process $proc$libresoc.v:42630$2321 + attribute \src "libresoc.v:42922.3-42923.55" + process $proc$libresoc.v:42922$2321 assign { } { } assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:42632.3-42633.57" - process $proc$libresoc.v:42632$2322 + attribute \src "libresoc.v:42924.3-42925.57" + process $proc$libresoc.v:42924$2322 assign { } { } assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:42634.3-42635.67" - process $proc$libresoc.v:42634$2323 + attribute \src "libresoc.v:42926.3-42927.67" + process $proc$libresoc.v:42926$2323 assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:42636.3-42637.57" - process $proc$libresoc.v:42636$2324 + attribute \src "libresoc.v:42928.3-42929.57" + process $proc$libresoc.v:42928$2324 assign { } { } assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:42638.3-42639.57" - process $proc$libresoc.v:42638$2325 + attribute \src "libresoc.v:42930.3-42931.57" + process $proc$libresoc.v:42930$2325 assign { } { } assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:42640.3-42641.67" - process $proc$libresoc.v:42640$2326 + attribute \src "libresoc.v:42932.3-42933.67" + process $proc$libresoc.v:42932$2326 assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next sync posedge \coresync_clk update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:42642.3-42643.57" - process $proc$libresoc.v:42642$2327 + attribute \src "libresoc.v:42934.3-42935.57" + process $proc$libresoc.v:42934$2327 assign { } { } assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next sync posedge \coresync_clk update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:42644.3-42645.57" - process $proc$libresoc.v:42644$2328 + attribute \src "libresoc.v:42936.3-42937.57" + process $proc$libresoc.v:42936$2328 assign { } { } assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next sync posedge \coresync_clk update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:42646.3-42647.57" - process $proc$libresoc.v:42646$2329 + attribute \src "libresoc.v:42938.3-42939.57" + process $proc$libresoc.v:42938$2329 assign { } { } assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next sync posedge \coresync_clk update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:42648.3-42649.65" - process $proc$libresoc.v:42648$2330 + attribute \src "libresoc.v:42940.3-42941.65" + process $proc$libresoc.v:42940$2330 assign { } { } assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next sync posedge \coresync_clk update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:42650.3-42651.57" - process $proc$libresoc.v:42650$2331 + attribute \src "libresoc.v:42942.3-42943.57" + process $proc$libresoc.v:42942$2331 assign { } { } assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:42652.3-42653.51" - process $proc$libresoc.v:42652$2332 + attribute \src "libresoc.v:42944.3-42945.51" + process $proc$libresoc.v:42944$2332 assign { } { } assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next sync posedge \coresync_clk update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:42654.3-42655.59" - process $proc$libresoc.v:42654$2333 + attribute \src "libresoc.v:42946.3-42947.59" + process $proc$libresoc.v:42946$2333 assign { } { } assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next sync posedge \coresync_clk update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:42656.3-42657.51" - process $proc$libresoc.v:42656$2334 + attribute \src "libresoc.v:42948.3-42949.51" + process $proc$libresoc.v:42948$2334 assign { } { } assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next sync posedge \coresync_clk update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:42658.3-42659.59" - process $proc$libresoc.v:42658$2335 + attribute \src "libresoc.v:42950.3-42951.59" + process $proc$libresoc.v:42950$2335 assign { } { } assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next sync posedge \coresync_clk update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:42660.3-42661.49" - process $proc$libresoc.v:42660$2336 + attribute \src "libresoc.v:42952.3-42953.49" + process $proc$libresoc.v:42952$2336 assign { } { } assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next sync posedge \coresync_clk update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:42662.3-42663.49" - process $proc$libresoc.v:42662$2337 + attribute \src "libresoc.v:42954.3-42955.49" + process $proc$libresoc.v:42954$2337 assign { } { } assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next sync posedge \coresync_clk update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:42664.3-42665.57" - process $proc$libresoc.v:42664$2338 + attribute \src "libresoc.v:42956.3-42957.57" + process $proc$libresoc.v:42956$2338 assign { } { } assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next sync posedge \coresync_clk update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:42666.3-42667.51" - process $proc$libresoc.v:42666$2339 + attribute \src "libresoc.v:42958.3-42959.51" + process $proc$libresoc.v:42958$2339 assign { } { } assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next sync posedge \coresync_clk update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:42668.3-42669.47" - process $proc$libresoc.v:42668$2340 + attribute \src "libresoc.v:42960.3-42961.47" + process $proc$libresoc.v:42960$2340 assign { } { } assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next sync posedge \coresync_clk update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:42670.3-42671.49" - process $proc$libresoc.v:42670$2341 + attribute \src "libresoc.v:42962.3-42963.49" + process $proc$libresoc.v:42962$2341 assign { } { } assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next sync posedge \coresync_clk update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:42672.3-42673.51" - process $proc$libresoc.v:42672$2342 + attribute \src "libresoc.v:42964.3-42965.51" + process $proc$libresoc.v:42964$2342 assign { } { } assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next sync posedge \coresync_clk update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:42674.3-42675.59" - process $proc$libresoc.v:42674$2343 + attribute \src "libresoc.v:42966.3-42967.59" + process $proc$libresoc.v:42966$2343 assign { } { } assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next sync posedge \coresync_clk update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:42676.3-42677.49" - process $proc$libresoc.v:42676$2344 + attribute \src "libresoc.v:42968.3-42969.49" + process $proc$libresoc.v:42968$2344 assign { } { } assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next sync posedge \coresync_clk update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:42678.3-42679.49" - process $proc$libresoc.v:42678$2345 + attribute \src "libresoc.v:42970.3-42971.49" + process $proc$libresoc.v:42970$2345 assign { } { } assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next sync posedge \coresync_clk update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:42680.3-42681.49" - process $proc$libresoc.v:42680$2346 + attribute \src "libresoc.v:42972.3-42973.49" + process $proc$libresoc.v:42972$2346 assign { } { } assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next sync posedge \coresync_clk update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:42682.3-42683.57" - process $proc$libresoc.v:42682$2347 + attribute \src "libresoc.v:42974.3-42975.57" + process $proc$libresoc.v:42974$2347 assign { } { } assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next sync posedge \coresync_clk update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:42684.3-42685.51" - process $proc$libresoc.v:42684$2348 + attribute \src "libresoc.v:42976.3-42977.51" + process $proc$libresoc.v:42976$2348 assign { } { } assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next sync posedge \coresync_clk update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:42686.3-42687.47" - process $proc$libresoc.v:42686$2349 + attribute \src "libresoc.v:42978.3-42979.47" + process $proc$libresoc.v:42978$2349 assign { } { } assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next sync posedge \coresync_clk update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:42688.3-42689.49" - process $proc$libresoc.v:42688$2350 + attribute \src "libresoc.v:42980.3-42981.49" + process $proc$libresoc.v:42980$2350 assign { } { } assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next sync posedge \coresync_clk update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:42690.3-42691.49" - process $proc$libresoc.v:42690$2351 + attribute \src "libresoc.v:42982.3-42983.49" + process $proc$libresoc.v:42982$2351 assign { } { } assign $0\core_terminate_o[0:0] \core_terminate_o$next sync posedge \coresync_clk update \core_terminate_o $0\core_terminate_o[0:0] end - attribute \src "libresoc.v:42692.3-42693.31" - process $proc$libresoc.v:42692$2352 + attribute \src "libresoc.v:42984.3-42985.31" + process $proc$libresoc.v:42984$2352 assign { } { } assign $0\counter[1:0] \counter$next sync posedge \coresync_clk update \counter $0\counter[1:0] end - attribute \src "libresoc.v:43427.3-43455.6" - process $proc$libresoc.v:43427$2353 + attribute \src "libresoc.v:43723.3-43751.6" + process $proc$libresoc.v:43723$2353 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43428.5-43428.29" + assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:43724.5-43724.29" switch \initial - attribute \src "libresoc.v:43428.9-43428.17" + attribute \src "libresoc.v:43724.9-43724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [5] + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry case - assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 end sync always - update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] end - attribute \src "libresoc.v:43456.3-43484.6" - process $proc$libresoc.v:43456$2354 + attribute \src "libresoc.v:43752.3-43780.6" + process $proc$libresoc.v:43752$2354 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:43457.5-43457.29" + assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:43753.5-43753.29" switch \initial - attribute \src "libresoc.v:43457.9-43457.17" + attribute \src "libresoc.v:43753.9-43753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [5] + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit case - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 end sync always - update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] + end + attribute \src "libresoc.v:43781.3-43809.6" + process $proc$libresoc.v:43781$2355 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:43782.5-43782.29" + switch \initial + attribute \src "libresoc.v:43782.9-43782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed + case + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] end - attribute \src "libresoc.v:43485.3-43513.6" - process $proc$libresoc.v:43485$2355 + attribute \src "libresoc.v:43810.3-43838.6" + process $proc$libresoc.v:43810$2356 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$25[0:0]$2356 $1\fus_cu_issue_i$25[0:0]$2357 - attribute \src "libresoc.v:43486.5-43486.29" + assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:43811.5-43811.29" switch \initial - attribute \src "libresoc.v:43486.9-43486.17" + attribute \src "libresoc.v:43811.9-43811.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$25[0:0]$2357 $2\fus_cu_issue_i$25[0:0]$2358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$25[0:0]$2358 1'0 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$25[0:0]$2358 1'0 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$25[0:0]$2358 $3\fus_cu_issue_i$25[0:0]$2359 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len + case + assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] + end + attribute \src "libresoc.v:43839.3-43867.6" + process $proc$libresoc.v:43839$2357 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:43840.5-43840.29" + switch \initial + attribute \src "libresoc.v:43840.9-43840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn + case + assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] + end + attribute \src "libresoc.v:43868.3-43896.6" + process $proc$libresoc.v:43868$2358 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$22[0:0]$2359 $1\fus_cu_issue_i$22[0:0]$2360 + attribute \src "libresoc.v:43869.5-43869.29" + switch \initial + attribute \src "libresoc.v:43869.9-43869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$22[0:0]$2360 $2\fus_cu_issue_i$22[0:0]$2361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$22[0:0]$2361 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$22[0:0]$2361 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$22[0:0]$2361 $3\fus_cu_issue_i$22[0:0]$2362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$22[0:0]$2362 \issue_i + case + assign $3\fus_cu_issue_i$22[0:0]$2362 1'0 + end + end + case + assign $1\fus_cu_issue_i$22[0:0]$2360 1'0 + end + sync always + update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2359 + end + attribute \src "libresoc.v:43897.3-43925.6" + process $proc$libresoc.v:43897$2363 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$24[2:0]$2364 $1\fus_cu_rdmaskn_i$24[2:0]$2365 + attribute \src "libresoc.v:43898.5-43898.29" + switch \initial + attribute \src "libresoc.v:43898.9-43898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 $2\fus_cu_rdmaskn_i$24[2:0]$2366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 $3\fus_cu_rdmaskn_i$24[2:0]$2367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$24[2:0]$2367 \$256 + case + assign $3\fus_cu_rdmaskn_i$24[2:0]$2367 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 3'000 + end + sync always + update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2364 + end + attribute \src "libresoc.v:43926.3-43954.6" + process $proc$libresoc.v:43926$2368 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43927.5-43927.29" + switch \initial + attribute \src "libresoc.v:43927.9-43927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$25[0:0]$2359 \issue_i + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type case - assign $3\fus_cu_issue_i$25[0:0]$2359 1'0 + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 end end case - assign $1\fus_cu_issue_i$25[0:0]$2357 1'0 + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 end sync always - update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2356 + update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] end - attribute \src "libresoc.v:43514.3-43542.6" - process $proc$libresoc.v:43514$2360 + attribute \src "libresoc.v:43955.3-43983.6" + process $proc$libresoc.v:43955$2369 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$27[5:0]$2361 $1\fus_cu_rdmaskn_i$27[5:0]$2362 - attribute \src "libresoc.v:43515.5-43515.29" + assign $0\fus_oper_i_alu_spr0__fn_unit[13:0] $1\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "libresoc.v:43956.5-43956.29" switch \initial - attribute \src "libresoc.v:43515.9-43515.17" + attribute \src "libresoc.v:43956.9-43956.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$27[5:0]$2362 $2\fus_cu_rdmaskn_i$27[5:0]$2363 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] $2\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$27[5:0]$2363 6'000000 + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$27[5:0]$2363 6'000000 + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$27[5:0]$2363 $3\fus_cu_rdmaskn_i$27[5:0]$2364 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] $3\fus_oper_i_alu_spr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$27[5:0]$2364 \$265 + assign $3\fus_oper_i_alu_spr0__fn_unit[13:0] \dec_SPR_SPR__fn_unit case - assign $3\fus_cu_rdmaskn_i$27[5:0]$2364 6'000000 + assign $3\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_cu_rdmaskn_i$27[5:0]$2362 6'000000 + assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2361 + update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[13:0] end - attribute \src "libresoc.v:43543.3-43571.6" - process $proc$libresoc.v:43543$2365 + attribute \src "libresoc.v:43984.3-44012.6" + process $proc$libresoc.v:43984$2370 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43985.5-43985.29" + switch \initial + attribute \src "libresoc.v:43985.9-43985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn + case + assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + end + attribute \src "libresoc.v:44013.3-44041.6" + process $proc$libresoc.v:44013$2371 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:44014.5-44014.29" + switch \initial + attribute \src "libresoc.v:44014.9-44014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit + case + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + end + attribute \src "libresoc.v:44042.3-44070.6" + process $proc$libresoc.v:44042$2372 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$25[0:0]$2373 $1\fus_cu_issue_i$25[0:0]$2374 + attribute \src "libresoc.v:44043.5-44043.29" + switch \initial + attribute \src "libresoc.v:44043.9-44043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$25[0:0]$2374 $2\fus_cu_issue_i$25[0:0]$2375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$25[0:0]$2375 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$25[0:0]$2375 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$25[0:0]$2375 $3\fus_cu_issue_i$25[0:0]$2376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$25[0:0]$2376 \issue_i + case + assign $3\fus_cu_issue_i$25[0:0]$2376 1'0 + end + end + case + assign $1\fus_cu_issue_i$25[0:0]$2374 1'0 + end + sync always + update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2373 + end + attribute \src "libresoc.v:44071.3-44099.6" + process $proc$libresoc.v:44071$2377 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$27[5:0]$2378 $1\fus_cu_rdmaskn_i$27[5:0]$2379 + attribute \src "libresoc.v:44072.5-44072.29" + switch \initial + attribute \src "libresoc.v:44072.9-44072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 $2\fus_cu_rdmaskn_i$27[5:0]$2380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 $3\fus_cu_rdmaskn_i$27[5:0]$2381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$27[5:0]$2381 \$270 + case + assign $3\fus_cu_rdmaskn_i$27[5:0]$2381 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2378 + end + attribute \src "libresoc.v:44100.3-44128.6" + process $proc$libresoc.v:44100$2382 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43544.5-43544.29" + attribute \src "libresoc.v:44101.5-44101.29" switch \initial - attribute \src "libresoc.v:43544.9-43544.17" + attribute \src "libresoc.v:44101.9-44101.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75658,7 +76359,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75674,66 +76375,66 @@ module \core sync always update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] end - attribute \src "libresoc.v:43572.3-43600.6" - process $proc$libresoc.v:43572$2366 + attribute \src "libresoc.v:44129.3-44157.6" + process $proc$libresoc.v:44129$2383 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__fn_unit[12:0] $1\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43573.5-43573.29" + assign $0\fus_oper_i_alu_div0__fn_unit[13:0] $1\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "libresoc.v:44130.5-44130.29" switch \initial - attribute \src "libresoc.v:43573.9-43573.17" + attribute \src "libresoc.v:44130.9-44130.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_div0__fn_unit[12:0] $2\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_div0__fn_unit[13:0] $2\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_div0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_div0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_div0__fn_unit[12:0] $3\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_div0__fn_unit[13:0] $3\fus_oper_i_alu_div0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__fn_unit[12:0] \dec_DIV_DIV__fn_unit + assign $3\fus_oper_i_alu_div0__fn_unit[13:0] \dec_DIV_DIV__fn_unit case - assign $3\fus_oper_i_alu_div0__fn_unit[12:0] 13'0000000000000 + assign $3\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_div0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[12:0] + update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[13:0] end - attribute \src "libresoc.v:43601.3-43630.6" - process $proc$libresoc.v:43601$2367 + attribute \src "libresoc.v:44158.3-44187.6" + process $proc$libresoc.v:44158$2384 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43602.5-43602.29" + attribute \src "libresoc.v:44159.5-44159.29" switch \initial - attribute \src "libresoc.v:43602.9-43602.17" + attribute \src "libresoc.v:44159.9-44159.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75741,7 +76442,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75757,7 +76458,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75777,21 +76478,21 @@ module \core update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] end - attribute \src "libresoc.v:43631.3-43660.6" - process $proc$libresoc.v:43631$2368 + attribute \src "libresoc.v:44188.3-44217.6" + process $proc$libresoc.v:44188$2385 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43632.5-43632.29" + attribute \src "libresoc.v:44189.5-44189.29" switch \initial - attribute \src "libresoc.v:43632.9-43632.17" + attribute \src "libresoc.v:44189.9-44189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75799,7 +76500,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75815,7 +76516,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75835,21 +76536,21 @@ module \core update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] end - attribute \src "libresoc.v:43661.3-43690.6" - process $proc$libresoc.v:43661$2369 + attribute \src "libresoc.v:44218.3-44247.6" + process $proc$libresoc.v:44218$2386 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43662.5-43662.29" + attribute \src "libresoc.v:44219.5-44219.29" switch \initial - attribute \src "libresoc.v:43662.9-43662.17" + attribute \src "libresoc.v:44219.9-44219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75857,7 +76558,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75873,7 +76574,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75893,24 +76594,24 @@ module \core update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] end - attribute \src "libresoc.v:43691.3-43719.6" - process $proc$libresoc.v:43691$2370 + attribute \src "libresoc.v:44248.3-44276.6" + process $proc$libresoc.v:44248$2387 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43692.5-43692.29" + attribute \src "libresoc.v:44249.5-44249.29" switch \initial - attribute \src "libresoc.v:43692.9-43692.17" + attribute \src "libresoc.v:44249.9-44249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75922,7 +76623,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75938,24 +76639,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] end - attribute \src "libresoc.v:43720.3-43748.6" - process $proc$libresoc.v:43720$2371 + attribute \src "libresoc.v:44277.3-44305.6" + process $proc$libresoc.v:44277$2388 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43721.5-43721.29" + attribute \src "libresoc.v:44278.5-44278.29" switch \initial - attribute \src "libresoc.v:43721.9-43721.17" + attribute \src "libresoc.v:44278.9-44278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75967,7 +76668,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75983,24 +76684,24 @@ module \core sync always update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] end - attribute \src "libresoc.v:43749.3-43777.6" - process $proc$libresoc.v:43749$2372 + attribute \src "libresoc.v:44306.3-44334.6" + process $proc$libresoc.v:44306$2389 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43750.5-43750.29" + attribute \src "libresoc.v:44307.5-44307.29" switch \initial - attribute \src "libresoc.v:43750.9-43750.17" + attribute \src "libresoc.v:44307.9-44307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76012,7 +76713,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76028,24 +76729,24 @@ module \core sync always update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] end - attribute \src "libresoc.v:43778.3-43806.6" - process $proc$libresoc.v:43778$2373 + attribute \src "libresoc.v:44335.3-44363.6" + process $proc$libresoc.v:44335$2390 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43779.5-43779.29" + attribute \src "libresoc.v:44336.5-44336.29" switch \initial - attribute \src "libresoc.v:43779.9-43779.17" + attribute \src "libresoc.v:44336.9-44336.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76057,7 +76758,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76073,24 +76774,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] end - attribute \src "libresoc.v:43807.3-43835.6" - process $proc$libresoc.v:43807$2374 + attribute \src "libresoc.v:44364.3-44392.6" + process $proc$libresoc.v:44364$2391 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43808.5-43808.29" + attribute \src "libresoc.v:44365.5-44365.29" switch \initial - attribute \src "libresoc.v:43808.9-43808.17" + attribute \src "libresoc.v:44365.9-44365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76102,7 +76803,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76118,24 +76819,24 @@ module \core sync always update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] end - attribute \src "libresoc.v:43836.3-43864.6" - process $proc$libresoc.v:43836$2375 + attribute \src "libresoc.v:44393.3-44421.6" + process $proc$libresoc.v:44393$2392 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43837.5-43837.29" + attribute \src "libresoc.v:44394.5-44394.29" switch \initial - attribute \src "libresoc.v:43837.9-43837.17" + attribute \src "libresoc.v:44394.9-44394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76147,7 +76848,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76163,24 +76864,24 @@ module \core sync always update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] end - attribute \src "libresoc.v:43865.3-43893.6" - process $proc$libresoc.v:43865$2376 + attribute \src "libresoc.v:44422.3-44450.6" + process $proc$libresoc.v:44422$2393 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43866.5-43866.29" + attribute \src "libresoc.v:44423.5-44423.29" switch \initial - attribute \src "libresoc.v:43866.9-43866.17" + attribute \src "libresoc.v:44423.9-44423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76192,7 +76893,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76208,24 +76909,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] end - attribute \src "libresoc.v:43894.3-43922.6" - process $proc$libresoc.v:43894$2377 + attribute \src "libresoc.v:44451.3-44479.6" + process $proc$libresoc.v:44451$2394 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43895.5-43895.29" + attribute \src "libresoc.v:44452.5-44452.29" switch \initial - attribute \src "libresoc.v:43895.9-43895.17" + attribute \src "libresoc.v:44452.9-44452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76237,7 +76938,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76253,24 +76954,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] end - attribute \src "libresoc.v:43923.3-43951.6" - process $proc$libresoc.v:43923$2378 + attribute \src "libresoc.v:44480.3-44508.6" + process $proc$libresoc.v:44480$2395 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43924.5-43924.29" + attribute \src "libresoc.v:44481.5-44481.29" switch \initial - attribute \src "libresoc.v:43924.9-43924.17" + attribute \src "libresoc.v:44481.9-44481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76282,7 +76983,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76298,24 +76999,24 @@ module \core sync always update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] end - attribute \src "libresoc.v:43952.3-43980.6" - process $proc$libresoc.v:43952$2379 + attribute \src "libresoc.v:44509.3-44537.6" + process $proc$libresoc.v:44509$2396 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43953.5-43953.29" + attribute \src "libresoc.v:44510.5-44510.29" switch \initial - attribute \src "libresoc.v:43953.9-43953.17" + attribute \src "libresoc.v:44510.9-44510.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76327,7 +77028,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76343,114 +77044,114 @@ module \core sync always update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] end - attribute \src "libresoc.v:43981.3-44009.6" - process $proc$libresoc.v:43981$2380 + attribute \src "libresoc.v:44538.3-44566.6" + process $proc$libresoc.v:44538$2397 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$28[0:0]$2381 $1\fus_cu_issue_i$28[0:0]$2382 - attribute \src "libresoc.v:43982.5-43982.29" + assign $0\fus_cu_issue_i$28[0:0]$2398 $1\fus_cu_issue_i$28[0:0]$2399 + attribute \src "libresoc.v:44539.5-44539.29" switch \initial - attribute \src "libresoc.v:43982.9-43982.17" + attribute \src "libresoc.v:44539.9-44539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$28[0:0]$2382 $2\fus_cu_issue_i$28[0:0]$2383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_issue_i$28[0:0]$2399 $2\fus_cu_issue_i$28[0:0]$2400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$28[0:0]$2383 1'0 + assign $2\fus_cu_issue_i$28[0:0]$2400 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$28[0:0]$2383 1'0 + assign $2\fus_cu_issue_i$28[0:0]$2400 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$28[0:0]$2383 $3\fus_cu_issue_i$28[0:0]$2384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_issue_i$28[0:0]$2400 $3\fus_cu_issue_i$28[0:0]$2401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$28[0:0]$2384 \issue_i + assign $3\fus_cu_issue_i$28[0:0]$2401 \issue_i case - assign $3\fus_cu_issue_i$28[0:0]$2384 1'0 + assign $3\fus_cu_issue_i$28[0:0]$2401 1'0 end end case - assign $1\fus_cu_issue_i$28[0:0]$2382 1'0 + assign $1\fus_cu_issue_i$28[0:0]$2399 1'0 end sync always - update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2381 + update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2398 end - attribute \src "libresoc.v:44010.3-44038.6" - process $proc$libresoc.v:44010$2385 + attribute \src "libresoc.v:44567.3-44595.6" + process $proc$libresoc.v:44567$2402 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$30[2:0]$2386 $1\fus_cu_rdmaskn_i$30[2:0]$2387 - attribute \src "libresoc.v:44011.5-44011.29" + assign $0\fus_cu_rdmaskn_i$30[2:0]$2403 $1\fus_cu_rdmaskn_i$30[2:0]$2404 + attribute \src "libresoc.v:44568.5-44568.29" switch \initial - attribute \src "libresoc.v:44011.9-44011.17" + attribute \src "libresoc.v:44568.9-44568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$30[2:0]$2387 $2\fus_cu_rdmaskn_i$30[2:0]$2388 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 $2\fus_cu_rdmaskn_i$30[2:0]$2405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$30[2:0]$2388 3'000 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$30[2:0]$2388 3'000 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$30[2:0]$2388 $3\fus_cu_rdmaskn_i$30[2:0]$2389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 $3\fus_cu_rdmaskn_i$30[2:0]$2406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$30[2:0]$2389 \$295 + assign $3\fus_cu_rdmaskn_i$30[2:0]$2406 \$300 case - assign $3\fus_cu_rdmaskn_i$30[2:0]$2389 3'000 + assign $3\fus_cu_rdmaskn_i$30[2:0]$2406 3'000 end end case - assign $1\fus_cu_rdmaskn_i$30[2:0]$2387 3'000 + assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 3'000 end sync always - update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2386 + update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2403 end - attribute \src "libresoc.v:44039.3-44067.6" - process $proc$libresoc.v:44039$2390 + attribute \src "libresoc.v:44596.3-44624.6" + process $proc$libresoc.v:44596$2407 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44040.5-44040.29" + attribute \src "libresoc.v:44597.5-44597.29" switch \initial - attribute \src "libresoc.v:44040.9-44040.17" + attribute \src "libresoc.v:44597.9-44597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76462,7 +77163,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76478,66 +77179,66 @@ module \core sync always update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] end - attribute \src "libresoc.v:44068.3-44096.6" - process $proc$libresoc.v:44068$2391 + attribute \src "libresoc.v:44625.3-44653.6" + process $proc$libresoc.v:44625$2408 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_mul0__fn_unit[12:0] $1\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44069.5-44069.29" + assign $0\fus_oper_i_alu_mul0__fn_unit[13:0] $1\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "libresoc.v:44626.5-44626.29" switch \initial - attribute \src "libresoc.v:44069.9-44069.17" + attribute \src "libresoc.v:44626.9-44626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_mul0__fn_unit[12:0] $2\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] $2\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_mul0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_mul0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_mul0__fn_unit[12:0] $3\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] $3\fus_oper_i_alu_mul0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_mul0__fn_unit[12:0] \dec_MUL_MUL__fn_unit + assign $3\fus_oper_i_alu_mul0__fn_unit[13:0] \dec_MUL_MUL__fn_unit case - assign $3\fus_oper_i_alu_mul0__fn_unit[12:0] 13'0000000000000 + assign $3\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_mul0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[12:0] + update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[13:0] end - attribute \src "libresoc.v:44097.3-44126.6" - process $proc$libresoc.v:44097$2392 + attribute \src "libresoc.v:44654.3-44683.6" + process $proc$libresoc.v:44654$2409 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44098.5-44098.29" + attribute \src "libresoc.v:44655.5-44655.29" switch \initial - attribute \src "libresoc.v:44098.9-44098.17" + attribute \src "libresoc.v:44655.9-44655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76545,7 +77246,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76561,7 +77262,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76581,21 +77282,21 @@ module \core update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44127.3-44156.6" - process $proc$libresoc.v:44127$2393 + attribute \src "libresoc.v:44684.3-44713.6" + process $proc$libresoc.v:44684$2410 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44128.5-44128.29" + attribute \src "libresoc.v:44685.5-44685.29" switch \initial - attribute \src "libresoc.v:44128.9-44128.17" + attribute \src "libresoc.v:44685.9-44685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76603,7 +77304,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76619,7 +77320,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76639,21 +77340,21 @@ module \core update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] end - attribute \src "libresoc.v:44157.3-44186.6" - process $proc$libresoc.v:44157$2394 + attribute \src "libresoc.v:44714.3-44743.6" + process $proc$libresoc.v:44714$2411 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44158.5-44158.29" + attribute \src "libresoc.v:44715.5-44715.29" switch \initial - attribute \src "libresoc.v:44158.9-44158.17" + attribute \src "libresoc.v:44715.9-44715.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76661,7 +77362,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76677,7 +77378,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76697,24 +77398,24 @@ module \core update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] end - attribute \src "libresoc.v:44187.3-44215.6" - process $proc$libresoc.v:44187$2395 + attribute \src "libresoc.v:44744.3-44772.6" + process $proc$libresoc.v:44744$2412 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44188.5-44188.29" + attribute \src "libresoc.v:44745.5-44745.29" switch \initial - attribute \src "libresoc.v:44188.9-44188.17" + attribute \src "libresoc.v:44745.9-44745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76726,7 +77427,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76742,24 +77443,24 @@ module \core sync always update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] end - attribute \src "libresoc.v:44216.3-44244.6" - process $proc$libresoc.v:44216$2396 + attribute \src "libresoc.v:44773.3-44801.6" + process $proc$libresoc.v:44773$2413 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44217.5-44217.29" + attribute \src "libresoc.v:44774.5-44774.29" switch \initial - attribute \src "libresoc.v:44217.9-44217.17" + attribute \src "libresoc.v:44774.9-44774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76771,7 +77472,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76787,24 +77488,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] end - attribute \src "libresoc.v:44245.3-44273.6" - process $proc$libresoc.v:44245$2397 + attribute \src "libresoc.v:44802.3-44830.6" + process $proc$libresoc.v:44802$2414 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44246.5-44246.29" + attribute \src "libresoc.v:44803.5-44803.29" switch \initial - attribute \src "libresoc.v:44246.9-44246.17" + attribute \src "libresoc.v:44803.9-44803.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76816,7 +77517,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76832,24 +77533,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] end - attribute \src "libresoc.v:44274.3-44302.6" - process $proc$libresoc.v:44274$2398 + attribute \src "libresoc.v:44831.3-44859.6" + process $proc$libresoc.v:44831$2415 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44275.5-44275.29" + attribute \src "libresoc.v:44832.5-44832.29" switch \initial - attribute \src "libresoc.v:44275.9-44275.17" + attribute \src "libresoc.v:44832.9-44832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76861,7 +77562,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76877,114 +77578,114 @@ module \core sync always update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] end - attribute \src "libresoc.v:44303.3-44331.6" - process $proc$libresoc.v:44303$2399 + attribute \src "libresoc.v:44860.3-44888.6" + process $proc$libresoc.v:44860$2416 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$31[0:0]$2400 $1\fus_cu_issue_i$31[0:0]$2401 - attribute \src "libresoc.v:44304.5-44304.29" + assign $0\fus_cu_issue_i$31[0:0]$2417 $1\fus_cu_issue_i$31[0:0]$2418 + attribute \src "libresoc.v:44861.5-44861.29" switch \initial - attribute \src "libresoc.v:44304.9-44304.17" + attribute \src "libresoc.v:44861.9-44861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$31[0:0]$2401 $2\fus_cu_issue_i$31[0:0]$2402 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_issue_i$31[0:0]$2418 $2\fus_cu_issue_i$31[0:0]$2419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$31[0:0]$2402 1'0 + assign $2\fus_cu_issue_i$31[0:0]$2419 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$31[0:0]$2402 1'0 + assign $2\fus_cu_issue_i$31[0:0]$2419 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$31[0:0]$2402 $3\fus_cu_issue_i$31[0:0]$2403 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_issue_i$31[0:0]$2419 $3\fus_cu_issue_i$31[0:0]$2420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$31[0:0]$2403 \issue_i + assign $3\fus_cu_issue_i$31[0:0]$2420 \issue_i case - assign $3\fus_cu_issue_i$31[0:0]$2403 1'0 + assign $3\fus_cu_issue_i$31[0:0]$2420 1'0 end end case - assign $1\fus_cu_issue_i$31[0:0]$2401 1'0 + assign $1\fus_cu_issue_i$31[0:0]$2418 1'0 end sync always - update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2400 + update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2417 end - attribute \src "libresoc.v:44332.3-44360.6" - process $proc$libresoc.v:44332$2404 + attribute \src "libresoc.v:44889.3-44917.6" + process $proc$libresoc.v:44889$2421 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$33[2:0]$2405 $1\fus_cu_rdmaskn_i$33[2:0]$2406 - attribute \src "libresoc.v:44333.5-44333.29" + assign $0\fus_cu_rdmaskn_i$33[2:0]$2422 $1\fus_cu_rdmaskn_i$33[2:0]$2423 + attribute \src "libresoc.v:44890.5-44890.29" switch \initial - attribute \src "libresoc.v:44333.9-44333.17" + attribute \src "libresoc.v:44890.9-44890.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$33[2:0]$2406 $2\fus_cu_rdmaskn_i$33[2:0]$2407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 $2\fus_cu_rdmaskn_i$33[2:0]$2424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$33[2:0]$2407 3'000 + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$33[2:0]$2407 3'000 + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$33[2:0]$2407 $3\fus_cu_rdmaskn_i$33[2:0]$2408 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 $3\fus_cu_rdmaskn_i$33[2:0]$2425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$33[2:0]$2408 \$309 + assign $3\fus_cu_rdmaskn_i$33[2:0]$2425 \$314 case - assign $3\fus_cu_rdmaskn_i$33[2:0]$2408 3'000 + assign $3\fus_cu_rdmaskn_i$33[2:0]$2425 3'000 end end case - assign $1\fus_cu_rdmaskn_i$33[2:0]$2406 3'000 + assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 3'000 end sync always - update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2405 + update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2422 end - attribute \src "libresoc.v:44361.3-44389.6" - process $proc$libresoc.v:44361$2409 + attribute \src "libresoc.v:44918.3-44946.6" + process $proc$libresoc.v:44918$2426 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44362.5-44362.29" + attribute \src "libresoc.v:44919.5-44919.29" switch \initial - attribute \src "libresoc.v:44362.9-44362.17" + attribute \src "libresoc.v:44919.9-44919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76996,7 +77697,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77012,66 +77713,66 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] end - attribute \src "libresoc.v:44390.3-44418.6" - process $proc$libresoc.v:44390$2410 + attribute \src "libresoc.v:44947.3-44975.6" + process $proc$libresoc.v:44947$2427 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44391.5-44391.29" + assign $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "libresoc.v:44948.5-44948.29" switch \initial - attribute \src "libresoc.v:44391.9-44391.17" + attribute \src "libresoc.v:44948.9-44948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit case - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] 13'0000000000000 + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] end - attribute \src "libresoc.v:44419.3-44448.6" - process $proc$libresoc.v:44419$2411 + attribute \src "libresoc.v:44976.3-45005.6" + process $proc$libresoc.v:44976$2428 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44420.5-44420.29" + attribute \src "libresoc.v:44977.5-44977.29" switch \initial - attribute \src "libresoc.v:44420.9-44420.17" + attribute \src "libresoc.v:44977.9-44977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77079,7 +77780,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77095,7 +77796,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77115,21 +77816,21 @@ module \core update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44449.3-44478.6" - process $proc$libresoc.v:44449$2412 + attribute \src "libresoc.v:45006.3-45035.6" + process $proc$libresoc.v:45006$2429 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44450.5-44450.29" + attribute \src "libresoc.v:45007.5-45007.29" switch \initial - attribute \src "libresoc.v:44450.9-44450.17" + attribute \src "libresoc.v:45007.9-45007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77137,7 +77838,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77153,7 +77854,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77173,21 +77874,21 @@ module \core update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] end - attribute \src "libresoc.v:44479.3-44508.6" - process $proc$libresoc.v:44479$2413 + attribute \src "libresoc.v:45036.3-45065.6" + process $proc$libresoc.v:45036$2430 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44480.5-44480.29" + attribute \src "libresoc.v:45037.5-45037.29" switch \initial - attribute \src "libresoc.v:44480.9-44480.17" + attribute \src "libresoc.v:45037.9-45037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77195,7 +77896,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77211,7 +77912,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77231,24 +77932,24 @@ module \core update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] end - attribute \src "libresoc.v:44509.3-44537.6" - process $proc$libresoc.v:44509$2414 + attribute \src "libresoc.v:45066.3-45094.6" + process $proc$libresoc.v:45066$2431 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:44510.5-44510.29" + attribute \src "libresoc.v:45067.5-45067.29" switch \initial - attribute \src "libresoc.v:44510.9-44510.17" + attribute \src "libresoc.v:45067.9-45067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77260,7 +77961,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77276,24 +77977,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] end - attribute \src "libresoc.v:44538.3-44566.6" - process $proc$libresoc.v:44538$2415 + attribute \src "libresoc.v:45095.3-45123.6" + process $proc$libresoc.v:45095$2432 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44539.5-44539.29" + attribute \src "libresoc.v:45096.5-45096.29" switch \initial - attribute \src "libresoc.v:44539.9-44539.17" + attribute \src "libresoc.v:45096.9-45096.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77305,7 +78006,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77321,24 +78022,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] end - attribute \src "libresoc.v:44567.3-44595.6" - process $proc$libresoc.v:44567$2416 + attribute \src "libresoc.v:45124.3-45152.6" + process $proc$libresoc.v:45124$2433 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44568.5-44568.29" + attribute \src "libresoc.v:45125.5-45125.29" switch \initial - attribute \src "libresoc.v:44568.9-44568.17" + attribute \src "libresoc.v:45125.9-45125.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77350,7 +78051,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77366,24 +78067,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] end - attribute \src "libresoc.v:44596.3-44624.6" - process $proc$libresoc.v:44596$2417 + attribute \src "libresoc.v:45153.3-45181.6" + process $proc$libresoc.v:45153$2434 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44597.5-44597.29" + attribute \src "libresoc.v:45154.5-45154.29" switch \initial - attribute \src "libresoc.v:44597.9-44597.17" + attribute \src "libresoc.v:45154.9-45154.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77395,7 +78096,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77411,24 +78112,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] end - attribute \src "libresoc.v:44625.3-44653.6" - process $proc$libresoc.v:44625$2418 + attribute \src "libresoc.v:45182.3-45210.6" + process $proc$libresoc.v:45182$2435 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44626.5-44626.29" + attribute \src "libresoc.v:45183.5-45183.29" switch \initial - attribute \src "libresoc.v:44626.9-44626.17" + attribute \src "libresoc.v:45183.9-45183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77440,7 +78141,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77456,24 +78157,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] end - attribute \src "libresoc.v:44654.3-44682.6" - process $proc$libresoc.v:44654$2419 + attribute \src "libresoc.v:45211.3-45239.6" + process $proc$libresoc.v:45211$2436 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44655.5-44655.29" + attribute \src "libresoc.v:45212.5-45212.29" switch \initial - attribute \src "libresoc.v:44655.9-44655.17" + attribute \src "libresoc.v:45212.9-45212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77485,7 +78186,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77501,24 +78202,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] end - attribute \src "libresoc.v:44683.3-44711.6" - process $proc$libresoc.v:44683$2420 + attribute \src "libresoc.v:45240.3-45268.6" + process $proc$libresoc.v:45240$2437 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44684.5-44684.29" + attribute \src "libresoc.v:45241.5-45241.29" switch \initial - attribute \src "libresoc.v:44684.9-44684.17" + attribute \src "libresoc.v:45241.9-45241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77530,7 +78231,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77546,24 +78247,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] end - attribute \src "libresoc.v:44712.3-44740.6" - process $proc$libresoc.v:44712$2421 + attribute \src "libresoc.v:45269.3-45297.6" + process $proc$libresoc.v:45269$2438 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44713.5-44713.29" + attribute \src "libresoc.v:45270.5-45270.29" switch \initial - attribute \src "libresoc.v:44713.9-44713.17" + attribute \src "libresoc.v:45270.9-45270.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77575,7 +78276,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77591,24 +78292,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] end - attribute \src "libresoc.v:44741.3-44769.6" - process $proc$libresoc.v:44741$2422 + attribute \src "libresoc.v:45298.3-45326.6" + process $proc$libresoc.v:45298$2439 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44742.5-44742.29" + attribute \src "libresoc.v:45299.5-45299.29" switch \initial - attribute \src "libresoc.v:44742.9-44742.17" + attribute \src "libresoc.v:45299.9-45299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77620,7 +78321,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77636,114 +78337,114 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] end - attribute \src "libresoc.v:44770.3-44798.6" - process $proc$libresoc.v:44770$2423 + attribute \src "libresoc.v:45327.3-45355.6" + process $proc$libresoc.v:45327$2440 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$34[0:0]$2424 $1\fus_cu_issue_i$34[0:0]$2425 - attribute \src "libresoc.v:44771.5-44771.29" + assign $0\fus_cu_issue_i$34[0:0]$2441 $1\fus_cu_issue_i$34[0:0]$2442 + attribute \src "libresoc.v:45328.5-45328.29" switch \initial - attribute \src "libresoc.v:44771.9-44771.17" + attribute \src "libresoc.v:45328.9-45328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$34[0:0]$2425 $2\fus_cu_issue_i$34[0:0]$2426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_issue_i$34[0:0]$2442 $2\fus_cu_issue_i$34[0:0]$2443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$34[0:0]$2426 1'0 + assign $2\fus_cu_issue_i$34[0:0]$2443 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$34[0:0]$2426 1'0 + assign $2\fus_cu_issue_i$34[0:0]$2443 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$34[0:0]$2426 $3\fus_cu_issue_i$34[0:0]$2427 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_issue_i$34[0:0]$2443 $3\fus_cu_issue_i$34[0:0]$2444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$34[0:0]$2427 \issue_i + assign $3\fus_cu_issue_i$34[0:0]$2444 \issue_i case - assign $3\fus_cu_issue_i$34[0:0]$2427 1'0 + assign $3\fus_cu_issue_i$34[0:0]$2444 1'0 end end case - assign $1\fus_cu_issue_i$34[0:0]$2425 1'0 + assign $1\fus_cu_issue_i$34[0:0]$2442 1'0 end sync always - update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2424 + update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2441 end - attribute \src "libresoc.v:44799.3-44827.6" - process $proc$libresoc.v:44799$2428 + attribute \src "libresoc.v:45356.3-45384.6" + process $proc$libresoc.v:45356$2445 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$36[4:0]$2429 $1\fus_cu_rdmaskn_i$36[4:0]$2430 - attribute \src "libresoc.v:44800.5-44800.29" + assign $0\fus_cu_rdmaskn_i$36[4:0]$2446 $1\fus_cu_rdmaskn_i$36[4:0]$2447 + attribute \src "libresoc.v:45357.5-45357.29" switch \initial - attribute \src "libresoc.v:44800.9-44800.17" + attribute \src "libresoc.v:45357.9-45357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$36[4:0]$2430 $2\fus_cu_rdmaskn_i$36[4:0]$2431 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 $2\fus_cu_rdmaskn_i$36[4:0]$2448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$36[4:0]$2431 5'00000 + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 5'00000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$36[4:0]$2431 5'00000 + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 5'00000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$36[4:0]$2431 $3\fus_cu_rdmaskn_i$36[4:0]$2432 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 $3\fus_cu_rdmaskn_i$36[4:0]$2449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$36[4:0]$2432 \$323 + assign $3\fus_cu_rdmaskn_i$36[4:0]$2449 \$328 case - assign $3\fus_cu_rdmaskn_i$36[4:0]$2432 5'00000 + assign $3\fus_cu_rdmaskn_i$36[4:0]$2449 5'00000 end end case - assign $1\fus_cu_rdmaskn_i$36[4:0]$2430 5'00000 + assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 5'00000 end sync always - update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2429 + update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2446 end - attribute \src "libresoc.v:44828.3-44856.6" - process $proc$libresoc.v:44828$2433 + attribute \src "libresoc.v:45385.3-45413.6" + process $proc$libresoc.v:45385$2450 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44829.5-44829.29" + attribute \src "libresoc.v:45386.5-45386.29" switch \initial - attribute \src "libresoc.v:44829.9-44829.17" + attribute \src "libresoc.v:45386.9-45386.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77755,7 +78456,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77771,66 +78472,66 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] end - attribute \src "libresoc.v:44857.3-44885.6" - process $proc$libresoc.v:44857$2434 + attribute \src "libresoc.v:45414.3-45442.6" + process $proc$libresoc.v:45414$2451 assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44858.5-44858.29" + assign $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "libresoc.v:45415.5-45415.29" switch \initial - attribute \src "libresoc.v:44858.9-44858.17" + attribute \src "libresoc.v:45415.9-45415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] \dec_LDST_LDST__fn_unit + assign $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] \dec_LDST_LDST__fn_unit case - assign $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] 13'0000000000000 + assign $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] + update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] end - attribute \src "libresoc.v:44886.3-44915.6" - process $proc$libresoc.v:44886$2435 + attribute \src "libresoc.v:45443.3-45472.6" + process $proc$libresoc.v:45443$2452 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44887.5-44887.29" + attribute \src "libresoc.v:45444.5-45444.29" switch \initial - attribute \src "libresoc.v:44887.9-44887.17" + attribute \src "libresoc.v:45444.9-45444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77838,7 +78539,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77854,7 +78555,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77874,24 +78575,24 @@ module \core update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44916.3-44944.6" - process $proc$libresoc.v:44916$2436 + attribute \src "libresoc.v:45473.3-45501.6" + process $proc$libresoc.v:45473$2453 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:44917.5-44917.29" + attribute \src "libresoc.v:45474.5-45474.29" switch \initial - attribute \src "libresoc.v:44917.9-44917.17" + attribute \src "libresoc.v:45474.9-45474.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77903,7 +78604,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77919,21 +78620,21 @@ module \core sync always update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] end - attribute \src "libresoc.v:44945.3-44974.6" - process $proc$libresoc.v:44945$2437 + attribute \src "libresoc.v:45502.3-45531.6" + process $proc$libresoc.v:45502$2454 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44946.5-44946.29" + attribute \src "libresoc.v:45503.5-45503.29" switch \initial - attribute \src "libresoc.v:44946.9-44946.17" + attribute \src "libresoc.v:45503.9-45503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77941,7 +78642,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77957,7 +78658,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77977,21 +78678,21 @@ module \core update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] end - attribute \src "libresoc.v:44975.3-45004.6" - process $proc$libresoc.v:44975$2438 + attribute \src "libresoc.v:45532.3-45561.6" + process $proc$libresoc.v:45532$2455 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44976.5-44976.29" + attribute \src "libresoc.v:45533.5-45533.29" switch \initial - attribute \src "libresoc.v:44976.9-44976.17" + attribute \src "libresoc.v:45533.9-45533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77999,7 +78700,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78015,7 +78716,7 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78035,24 +78736,24 @@ module \core update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] end - attribute \src "libresoc.v:45005.3-45033.6" - process $proc$libresoc.v:45005$2439 + attribute \src "libresoc.v:45562.3-45590.6" + process $proc$libresoc.v:45562$2456 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45006.5-45006.29" + attribute \src "libresoc.v:45563.5-45563.29" switch \initial - attribute \src "libresoc.v:45006.9-45006.17" + attribute \src "libresoc.v:45563.9-45563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78064,7 +78765,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78080,24 +78781,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] end - attribute \src "libresoc.v:45034.3-45062.6" - process $proc$libresoc.v:45034$2440 + attribute \src "libresoc.v:45591.3-45619.6" + process $proc$libresoc.v:45591$2457 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45035.5-45035.29" + attribute \src "libresoc.v:45592.5-45592.29" switch \initial - attribute \src "libresoc.v:45035.9-45035.17" + attribute \src "libresoc.v:45592.9-45592.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78109,7 +78810,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78125,24 +78826,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] end - attribute \src "libresoc.v:45063.3-45091.6" - process $proc$libresoc.v:45063$2441 + attribute \src "libresoc.v:45620.3-45648.6" + process $proc$libresoc.v:45620$2458 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45064.5-45064.29" + attribute \src "libresoc.v:45621.5-45621.29" switch \initial - attribute \src "libresoc.v:45064.9-45064.17" + attribute \src "libresoc.v:45621.9-45621.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78154,7 +78855,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78170,24 +78871,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] end - attribute \src "libresoc.v:45092.3-45120.6" - process $proc$libresoc.v:45092$2442 + attribute \src "libresoc.v:45649.3-45677.6" + process $proc$libresoc.v:45649$2459 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45093.5-45093.29" + attribute \src "libresoc.v:45650.5-45650.29" switch \initial - attribute \src "libresoc.v:45093.9-45093.17" + attribute \src "libresoc.v:45650.9-45650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78199,7 +78900,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78215,24 +78916,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] end - attribute \src "libresoc.v:45121.3-45149.6" - process $proc$libresoc.v:45121$2443 + attribute \src "libresoc.v:45678.3-45706.6" + process $proc$libresoc.v:45678$2460 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45122.5-45122.29" + attribute \src "libresoc.v:45679.5-45679.29" switch \initial - attribute \src "libresoc.v:45122.9-45122.17" + attribute \src "libresoc.v:45679.9-45679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78244,7 +78945,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78260,24 +78961,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] end - attribute \src "libresoc.v:45150.3-45178.6" - process $proc$libresoc.v:45150$2444 + attribute \src "libresoc.v:45707.3-45735.6" + process $proc$libresoc.v:45707$2461 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45151.5-45151.29" + attribute \src "libresoc.v:45708.5-45708.29" switch \initial - attribute \src "libresoc.v:45151.9-45151.17" + attribute \src "libresoc.v:45708.9-45708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78289,7 +78990,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78305,24 +79006,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] end - attribute \src "libresoc.v:45179.3-45207.6" - process $proc$libresoc.v:45179$2445 + attribute \src "libresoc.v:45736.3-45764.6" + process $proc$libresoc.v:45736$2462 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45180.5-45180.29" + attribute \src "libresoc.v:45737.5-45737.29" switch \initial - attribute \src "libresoc.v:45180.9-45180.17" + attribute \src "libresoc.v:45737.9-45737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78334,7 +79035,7 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78350,104 +79051,104 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] end - attribute \src "libresoc.v:45208.3-45236.6" - process $proc$libresoc.v:45208$2446 + attribute \src "libresoc.v:45765.3-45793.6" + process $proc$libresoc.v:45765$2463 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$37[0:0]$2447 $1\fus_cu_issue_i$37[0:0]$2448 - attribute \src "libresoc.v:45209.5-45209.29" + assign $0\fus_cu_issue_i$37[0:0]$2464 $1\fus_cu_issue_i$37[0:0]$2465 + attribute \src "libresoc.v:45766.5-45766.29" switch \initial - attribute \src "libresoc.v:45209.9-45209.17" + attribute \src "libresoc.v:45766.9-45766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$37[0:0]$2448 $2\fus_cu_issue_i$37[0:0]$2449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_issue_i$37[0:0]$2465 $2\fus_cu_issue_i$37[0:0]$2466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$37[0:0]$2449 1'0 + assign $2\fus_cu_issue_i$37[0:0]$2466 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$37[0:0]$2449 1'0 + assign $2\fus_cu_issue_i$37[0:0]$2466 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$37[0:0]$2449 $3\fus_cu_issue_i$37[0:0]$2450 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_issue_i$37[0:0]$2466 $3\fus_cu_issue_i$37[0:0]$2467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$37[0:0]$2450 \issue_i + assign $3\fus_cu_issue_i$37[0:0]$2467 \issue_i case - assign $3\fus_cu_issue_i$37[0:0]$2450 1'0 + assign $3\fus_cu_issue_i$37[0:0]$2467 1'0 end end case - assign $1\fus_cu_issue_i$37[0:0]$2448 1'0 + assign $1\fus_cu_issue_i$37[0:0]$2465 1'0 end sync always - update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2447 + update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2464 end - attribute \src "libresoc.v:45237.3-45265.6" - process $proc$libresoc.v:45237$2451 + attribute \src "libresoc.v:45794.3-45822.6" + process $proc$libresoc.v:45794$2468 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$39[2:0]$2452 $1\fus_cu_rdmaskn_i$39[2:0]$2453 - attribute \src "libresoc.v:45238.5-45238.29" + assign $0\fus_cu_rdmaskn_i$39[2:0]$2469 $1\fus_cu_rdmaskn_i$39[2:0]$2470 + attribute \src "libresoc.v:45795.5-45795.29" switch \initial - attribute \src "libresoc.v:45238.9-45238.17" + attribute \src "libresoc.v:45795.9-45795.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$39[2:0]$2453 $2\fus_cu_rdmaskn_i$39[2:0]$2454 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 $2\fus_cu_rdmaskn_i$39[2:0]$2471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$39[2:0]$2454 3'000 + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$39[2:0]$2454 3'000 + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$39[2:0]$2454 $3\fus_cu_rdmaskn_i$39[2:0]$2455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 $3\fus_cu_rdmaskn_i$39[2:0]$2472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$39[2:0]$2455 \$345 + assign $3\fus_cu_rdmaskn_i$39[2:0]$2472 \$350 case - assign $3\fus_cu_rdmaskn_i$39[2:0]$2455 3'000 + assign $3\fus_cu_rdmaskn_i$39[2:0]$2472 3'000 end end case - assign $1\fus_cu_rdmaskn_i$39[2:0]$2453 3'000 + assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 3'000 end sync always - update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2452 + update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2469 end - attribute \src "libresoc.v:45266.3-45274.6" - process $proc$libresoc.v:45266$2456 + attribute \src "libresoc.v:45823.3-45831.6" + process $proc$libresoc.v:45823$2473 assign { } { } assign { } { } - assign $0\dp_INT_ra_alu0_0$next[0:0]$2457 $1\dp_INT_ra_alu0_0$next[0:0]$2458 - attribute \src "libresoc.v:45267.5-45267.29" + assign $0\dp_INT_ra_alu0_0$next[0:0]$2474 $1\dp_INT_ra_alu0_0$next[0:0]$2475 + attribute \src "libresoc.v:45824.5-45824.29" switch \initial - attribute \src "libresoc.v:45267.9-45267.17" + attribute \src "libresoc.v:45824.9-45824.17" case 1'1 case end @@ -78456,25 +79157,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_alu0_0$next[0:0]$2458 1'0 + assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 1'0 case - assign $1\dp_INT_ra_alu0_0$next[0:0]$2458 \rp_INT_ra_alu0_0 + assign $1\dp_INT_ra_alu0_0$next[0:0]$2475 \rp_INT_ra_alu0_0 end sync always - update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2457 + update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2474 end - attribute \src "libresoc.v:45275.3-45284.6" - process $proc$libresoc.v:45275$2459 + attribute \src "libresoc.v:45832.3-45841.6" + process $proc$libresoc.v:45832$2476 assign { } { } assign { } { } assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45276.5-45276.29" + attribute \src "libresoc.v:45833.5-45833.29" switch \initial - attribute \src "libresoc.v:45276.9-45276.17" + attribute \src "libresoc.v:45833.9-45833.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78486,14 +79187,14 @@ module \core sync always update \fus_src1_i $0\fus_src1_i[63:0] end - attribute \src "libresoc.v:45285.3-45293.6" - process $proc$libresoc.v:45285$2460 + attribute \src "libresoc.v:45842.3-45850.6" + process $proc$libresoc.v:45842$2477 assign { } { } assign { } { } - assign $0\dp_INT_ra_cr0_1$next[0:0]$2461 $1\dp_INT_ra_cr0_1$next[0:0]$2462 - attribute \src "libresoc.v:45286.5-45286.29" + assign $0\dp_INT_ra_cr0_1$next[0:0]$2478 $1\dp_INT_ra_cr0_1$next[0:0]$2479 + attribute \src "libresoc.v:45843.5-45843.29" switch \initial - attribute \src "libresoc.v:45286.9-45286.17" + attribute \src "libresoc.v:45843.9-45843.17" case 1'1 case end @@ -78502,44 +79203,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_cr0_1$next[0:0]$2462 1'0 + assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 1'0 case - assign $1\dp_INT_ra_cr0_1$next[0:0]$2462 \rp_INT_ra_cr0_1 + assign $1\dp_INT_ra_cr0_1$next[0:0]$2479 \rp_INT_ra_cr0_1 end sync always - update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2461 + update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2478 end - attribute \src "libresoc.v:45294.3-45303.6" - process $proc$libresoc.v:45294$2463 + attribute \src "libresoc.v:45851.3-45860.6" + process $proc$libresoc.v:45851$2480 assign { } { } assign { } { } - assign $0\fus_src1_i$42[63:0]$2464 $1\fus_src1_i$42[63:0]$2465 - attribute \src "libresoc.v:45295.5-45295.29" + assign $0\fus_src1_i$42[63:0]$2481 $1\fus_src1_i$42[63:0]$2482 + attribute \src "libresoc.v:45852.5-45852.29" switch \initial - attribute \src "libresoc.v:45295.9-45295.17" + attribute \src "libresoc.v:45852.9-45852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$42[63:0]$2465 \int_src1__data_o + assign $1\fus_src1_i$42[63:0]$2482 \int_src1__data_o case - assign $1\fus_src1_i$42[63:0]$2465 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2464 + update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2481 end - attribute \src "libresoc.v:45304.3-45312.6" - process $proc$libresoc.v:45304$2466 + attribute \src "libresoc.v:45861.3-45869.6" + process $proc$libresoc.v:45861$2483 assign { } { } assign { } { } - assign $0\dp_INT_ra_trap0_2$next[0:0]$2467 $1\dp_INT_ra_trap0_2$next[0:0]$2468 - attribute \src "libresoc.v:45305.5-45305.29" + assign $0\dp_INT_ra_trap0_2$next[0:0]$2484 $1\dp_INT_ra_trap0_2$next[0:0]$2485 + attribute \src "libresoc.v:45862.5-45862.29" switch \initial - attribute \src "libresoc.v:45305.9-45305.17" + attribute \src "libresoc.v:45862.9-45862.17" case 1'1 case end @@ -78548,44 +79249,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_trap0_2$next[0:0]$2468 1'0 + assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 1'0 case - assign $1\dp_INT_ra_trap0_2$next[0:0]$2468 \rp_INT_ra_trap0_2 + assign $1\dp_INT_ra_trap0_2$next[0:0]$2485 \rp_INT_ra_trap0_2 end sync always - update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2467 + update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2484 end - attribute \src "libresoc.v:45313.3-45322.6" - process $proc$libresoc.v:45313$2469 + attribute \src "libresoc.v:45870.3-45879.6" + process $proc$libresoc.v:45870$2486 assign { } { } assign { } { } - assign $0\fus_src1_i$45[63:0]$2470 $1\fus_src1_i$45[63:0]$2471 - attribute \src "libresoc.v:45314.5-45314.29" + assign $0\fus_src1_i$45[63:0]$2487 $1\fus_src1_i$45[63:0]$2488 + attribute \src "libresoc.v:45871.5-45871.29" switch \initial - attribute \src "libresoc.v:45314.9-45314.17" + attribute \src "libresoc.v:45871.9-45871.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$45[63:0]$2471 \int_src1__data_o + assign $1\fus_src1_i$45[63:0]$2488 \int_src1__data_o case - assign $1\fus_src1_i$45[63:0]$2471 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2470 + update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2487 end - attribute \src "libresoc.v:45323.3-45331.6" - process $proc$libresoc.v:45323$2472 + attribute \src "libresoc.v:45880.3-45888.6" + process $proc$libresoc.v:45880$2489 assign { } { } assign { } { } - assign $0\dp_INT_ra_logical0_3$next[0:0]$2473 $1\dp_INT_ra_logical0_3$next[0:0]$2474 - attribute \src "libresoc.v:45324.5-45324.29" + assign $0\dp_INT_ra_logical0_3$next[0:0]$2490 $1\dp_INT_ra_logical0_3$next[0:0]$2491 + attribute \src "libresoc.v:45881.5-45881.29" switch \initial - attribute \src "libresoc.v:45324.9-45324.17" + attribute \src "libresoc.v:45881.9-45881.17" case 1'1 case end @@ -78594,44 +79295,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_logical0_3$next[0:0]$2474 1'0 + assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 1'0 case - assign $1\dp_INT_ra_logical0_3$next[0:0]$2474 \rp_INT_ra_logical0_3 + assign $1\dp_INT_ra_logical0_3$next[0:0]$2491 \rp_INT_ra_logical0_3 end sync always - update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2473 + update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2490 end - attribute \src "libresoc.v:45332.3-45341.6" - process $proc$libresoc.v:45332$2475 + attribute \src "libresoc.v:45889.3-45898.6" + process $proc$libresoc.v:45889$2492 assign { } { } assign { } { } - assign $0\fus_src1_i$48[63:0]$2476 $1\fus_src1_i$48[63:0]$2477 - attribute \src "libresoc.v:45333.5-45333.29" + assign $0\fus_src1_i$48[63:0]$2493 $1\fus_src1_i$48[63:0]$2494 + attribute \src "libresoc.v:45890.5-45890.29" switch \initial - attribute \src "libresoc.v:45333.9-45333.17" + attribute \src "libresoc.v:45890.9-45890.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$48[63:0]$2477 \int_src1__data_o + assign $1\fus_src1_i$48[63:0]$2494 \int_src1__data_o case - assign $1\fus_src1_i$48[63:0]$2477 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2476 + update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2493 end - attribute \src "libresoc.v:45342.3-45350.6" - process $proc$libresoc.v:45342$2478 + attribute \src "libresoc.v:45899.3-45907.6" + process $proc$libresoc.v:45899$2495 assign { } { } assign { } { } - assign $0\dp_INT_ra_spr0_4$next[0:0]$2479 $1\dp_INT_ra_spr0_4$next[0:0]$2480 - attribute \src "libresoc.v:45343.5-45343.29" + assign $0\dp_INT_ra_spr0_4$next[0:0]$2496 $1\dp_INT_ra_spr0_4$next[0:0]$2497 + attribute \src "libresoc.v:45900.5-45900.29" switch \initial - attribute \src "libresoc.v:45343.9-45343.17" + attribute \src "libresoc.v:45900.9-45900.17" case 1'1 case end @@ -78640,44 +79341,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_spr0_4$next[0:0]$2480 1'0 + assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 1'0 case - assign $1\dp_INT_ra_spr0_4$next[0:0]$2480 \rp_INT_ra_spr0_4 + assign $1\dp_INT_ra_spr0_4$next[0:0]$2497 \rp_INT_ra_spr0_4 end sync always - update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2479 + update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2496 end - attribute \src "libresoc.v:45351.3-45360.6" - process $proc$libresoc.v:45351$2481 + attribute \src "libresoc.v:45908.3-45917.6" + process $proc$libresoc.v:45908$2498 assign { } { } assign { } { } - assign $0\fus_src1_i$51[63:0]$2482 $1\fus_src1_i$51[63:0]$2483 - attribute \src "libresoc.v:45352.5-45352.29" + assign $0\fus_src1_i$51[63:0]$2499 $1\fus_src1_i$51[63:0]$2500 + attribute \src "libresoc.v:45909.5-45909.29" switch \initial - attribute \src "libresoc.v:45352.9-45352.17" + attribute \src "libresoc.v:45909.9-45909.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_spr0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$51[63:0]$2483 \int_src1__data_o + assign $1\fus_src1_i$51[63:0]$2500 \int_src1__data_o case - assign $1\fus_src1_i$51[63:0]$2483 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2482 + update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2499 end - attribute \src "libresoc.v:45361.3-45369.6" - process $proc$libresoc.v:45361$2484 + attribute \src "libresoc.v:45918.3-45926.6" + process $proc$libresoc.v:45918$2501 assign { } { } assign { } { } - assign $0\dp_INT_ra_div0_5$next[0:0]$2485 $1\dp_INT_ra_div0_5$next[0:0]$2486 - attribute \src "libresoc.v:45362.5-45362.29" + assign $0\dp_INT_ra_div0_5$next[0:0]$2502 $1\dp_INT_ra_div0_5$next[0:0]$2503 + attribute \src "libresoc.v:45919.5-45919.29" switch \initial - attribute \src "libresoc.v:45362.9-45362.17" + attribute \src "libresoc.v:45919.9-45919.17" case 1'1 case end @@ -78686,44 +79387,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_div0_5$next[0:0]$2486 1'0 + assign $1\dp_INT_ra_div0_5$next[0:0]$2503 1'0 case - assign $1\dp_INT_ra_div0_5$next[0:0]$2486 \rp_INT_ra_div0_5 + assign $1\dp_INT_ra_div0_5$next[0:0]$2503 \rp_INT_ra_div0_5 end sync always - update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2485 + update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2502 end - attribute \src "libresoc.v:45370.3-45379.6" - process $proc$libresoc.v:45370$2487 + attribute \src "libresoc.v:45927.3-45936.6" + process $proc$libresoc.v:45927$2504 assign { } { } assign { } { } - assign $0\fus_src1_i$54[63:0]$2488 $1\fus_src1_i$54[63:0]$2489 - attribute \src "libresoc.v:45371.5-45371.29" + assign $0\fus_src1_i$54[63:0]$2505 $1\fus_src1_i$54[63:0]$2506 + attribute \src "libresoc.v:45928.5-45928.29" switch \initial - attribute \src "libresoc.v:45371.9-45371.17" + attribute \src "libresoc.v:45928.9-45928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_div0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$54[63:0]$2489 \int_src1__data_o + assign $1\fus_src1_i$54[63:0]$2506 \int_src1__data_o case - assign $1\fus_src1_i$54[63:0]$2489 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2488 + update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2505 end - attribute \src "libresoc.v:45380.3-45388.6" - process $proc$libresoc.v:45380$2490 + attribute \src "libresoc.v:45937.3-45945.6" + process $proc$libresoc.v:45937$2507 assign { } { } assign { } { } - assign $0\dp_INT_ra_mul0_6$next[0:0]$2491 $1\dp_INT_ra_mul0_6$next[0:0]$2492 - attribute \src "libresoc.v:45381.5-45381.29" + assign $0\dp_INT_ra_mul0_6$next[0:0]$2508 $1\dp_INT_ra_mul0_6$next[0:0]$2509 + attribute \src "libresoc.v:45938.5-45938.29" switch \initial - attribute \src "libresoc.v:45381.9-45381.17" + attribute \src "libresoc.v:45938.9-45938.17" case 1'1 case end @@ -78732,44 +79433,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_mul0_6$next[0:0]$2492 1'0 + assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 1'0 case - assign $1\dp_INT_ra_mul0_6$next[0:0]$2492 \rp_INT_ra_mul0_6 + assign $1\dp_INT_ra_mul0_6$next[0:0]$2509 \rp_INT_ra_mul0_6 end sync always - update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2491 + update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2508 end - attribute \src "libresoc.v:45389.3-45398.6" - process $proc$libresoc.v:45389$2493 + attribute \src "libresoc.v:45946.3-45955.6" + process $proc$libresoc.v:45946$2510 assign { } { } assign { } { } - assign $0\fus_src1_i$57[63:0]$2494 $1\fus_src1_i$57[63:0]$2495 - attribute \src "libresoc.v:45390.5-45390.29" + assign $0\fus_src1_i$57[63:0]$2511 $1\fus_src1_i$57[63:0]$2512 + attribute \src "libresoc.v:45947.5-45947.29" switch \initial - attribute \src "libresoc.v:45390.9-45390.17" + attribute \src "libresoc.v:45947.9-45947.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_mul0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$57[63:0]$2495 \int_src1__data_o + assign $1\fus_src1_i$57[63:0]$2512 \int_src1__data_o case - assign $1\fus_src1_i$57[63:0]$2495 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2494 + update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2511 end - attribute \src "libresoc.v:45399.3-45407.6" - process $proc$libresoc.v:45399$2496 + attribute \src "libresoc.v:45956.3-45964.6" + process $proc$libresoc.v:45956$2513 assign { } { } assign { } { } - assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 - attribute \src "libresoc.v:45400.5-45400.29" + assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 + attribute \src "libresoc.v:45957.5-45957.29" switch \initial - attribute \src "libresoc.v:45400.9-45400.17" + attribute \src "libresoc.v:45957.9-45957.17" case 1'1 case end @@ -78778,44 +79479,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 1'0 + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 1'0 case - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 \rp_INT_ra_shiftrot0_7 + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 \rp_INT_ra_shiftrot0_7 end sync always - update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 + update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 end - attribute \src "libresoc.v:45408.3-45417.6" - process $proc$libresoc.v:45408$2499 + attribute \src "libresoc.v:45965.3-45974.6" + process $proc$libresoc.v:45965$2516 assign { } { } assign { } { } - assign $0\fus_src1_i$60[63:0]$2500 $1\fus_src1_i$60[63:0]$2501 - attribute \src "libresoc.v:45409.5-45409.29" + assign $0\fus_src1_i$60[63:0]$2517 $1\fus_src1_i$60[63:0]$2518 + attribute \src "libresoc.v:45966.5-45966.29" switch \initial - attribute \src "libresoc.v:45409.9-45409.17" + attribute \src "libresoc.v:45966.9-45966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_shiftrot0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$60[63:0]$2501 \int_src1__data_o + assign $1\fus_src1_i$60[63:0]$2518 \int_src1__data_o case - assign $1\fus_src1_i$60[63:0]$2501 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2500 + update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2517 end - attribute \src "libresoc.v:45418.3-45426.6" - process $proc$libresoc.v:45418$2502 + attribute \src "libresoc.v:45975.3-45983.6" + process $proc$libresoc.v:45975$2519 assign { } { } assign { } { } - assign $0\dp_INT_ra_ldst0_8$next[0:0]$2503 $1\dp_INT_ra_ldst0_8$next[0:0]$2504 - attribute \src "libresoc.v:45419.5-45419.29" + assign $0\dp_INT_ra_ldst0_8$next[0:0]$2520 $1\dp_INT_ra_ldst0_8$next[0:0]$2521 + attribute \src "libresoc.v:45976.5-45976.29" switch \initial - attribute \src "libresoc.v:45419.9-45419.17" + attribute \src "libresoc.v:45976.9-45976.17" case 1'1 case end @@ -78824,44 +79525,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2504 1'0 + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 1'0 case - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2504 \rp_INT_ra_ldst0_8 + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2521 \rp_INT_ra_ldst0_8 end sync always - update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2503 + update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2520 end - attribute \src "libresoc.v:45427.3-45436.6" - process $proc$libresoc.v:45427$2505 + attribute \src "libresoc.v:45984.3-45993.6" + process $proc$libresoc.v:45984$2522 assign { } { } assign { } { } - assign $0\fus_src1_i$63[63:0]$2506 $1\fus_src1_i$63[63:0]$2507 - attribute \src "libresoc.v:45428.5-45428.29" + assign $0\fus_src1_i$63[63:0]$2523 $1\fus_src1_i$63[63:0]$2524 + attribute \src "libresoc.v:45985.5-45985.29" switch \initial - attribute \src "libresoc.v:45428.9-45428.17" + attribute \src "libresoc.v:45985.9-45985.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_ra_ldst0_8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$63[63:0]$2507 \int_src1__data_o + assign $1\fus_src1_i$63[63:0]$2524 \int_src1__data_o case - assign $1\fus_src1_i$63[63:0]$2507 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$63[63:0]$2524 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2506 + update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2523 end - attribute \src "libresoc.v:45437.3-45445.6" - process $proc$libresoc.v:45437$2508 + attribute \src "libresoc.v:45994.3-46002.6" + process $proc$libresoc.v:45994$2525 assign { } { } assign { } { } - assign $0\dp_INT_rb_alu0_0$next[0:0]$2509 $1\dp_INT_rb_alu0_0$next[0:0]$2510 - attribute \src "libresoc.v:45438.5-45438.29" + assign $0\dp_INT_rb_alu0_0$next[0:0]$2526 $1\dp_INT_rb_alu0_0$next[0:0]$2527 + attribute \src "libresoc.v:45995.5-45995.29" switch \initial - attribute \src "libresoc.v:45438.9-45438.17" + attribute \src "libresoc.v:45995.9-45995.17" case 1'1 case end @@ -78870,25 +79571,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_alu0_0$next[0:0]$2510 1'0 + assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 1'0 case - assign $1\dp_INT_rb_alu0_0$next[0:0]$2510 \rp_INT_rb_alu0_0 + assign $1\dp_INT_rb_alu0_0$next[0:0]$2527 \rp_INT_rb_alu0_0 end sync always - update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2509 + update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2526 end - attribute \src "libresoc.v:45446.3-45455.6" - process $proc$libresoc.v:45446$2511 + attribute \src "libresoc.v:46003.3-46012.6" + process $proc$libresoc.v:46003$2528 assign { } { } assign { } { } assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45447.5-45447.29" + attribute \src "libresoc.v:46004.5-46004.29" switch \initial - attribute \src "libresoc.v:45447.9-45447.17" + attribute \src "libresoc.v:46004.9-46004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78900,14 +79601,14 @@ module \core sync always update \fus_src2_i $0\fus_src2_i[63:0] end - attribute \src "libresoc.v:45456.3-45464.6" - process $proc$libresoc.v:45456$2512 + attribute \src "libresoc.v:46013.3-46021.6" + process $proc$libresoc.v:46013$2529 assign { } { } assign { } { } - assign $0\dp_INT_rb_cr0_1$next[0:0]$2513 $1\dp_INT_rb_cr0_1$next[0:0]$2514 - attribute \src "libresoc.v:45457.5-45457.29" + assign $0\dp_INT_rb_cr0_1$next[0:0]$2530 $1\dp_INT_rb_cr0_1$next[0:0]$2531 + attribute \src "libresoc.v:46014.5-46014.29" switch \initial - attribute \src "libresoc.v:45457.9-45457.17" + attribute \src "libresoc.v:46014.9-46014.17" case 1'1 case end @@ -78916,44 +79617,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_cr0_1$next[0:0]$2514 1'0 + assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 1'0 case - assign $1\dp_INT_rb_cr0_1$next[0:0]$2514 \rp_INT_rb_cr0_1 + assign $1\dp_INT_rb_cr0_1$next[0:0]$2531 \rp_INT_rb_cr0_1 end sync always - update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2513 + update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2530 end - attribute \src "libresoc.v:45465.3-45474.6" - process $proc$libresoc.v:45465$2515 + attribute \src "libresoc.v:46022.3-46031.6" + process $proc$libresoc.v:46022$2532 assign { } { } assign { } { } - assign $0\fus_src2_i$64[63:0]$2516 $1\fus_src2_i$64[63:0]$2517 - attribute \src "libresoc.v:45466.5-45466.29" + assign $0\fus_src2_i$64[63:0]$2533 $1\fus_src2_i$64[63:0]$2534 + attribute \src "libresoc.v:46023.5-46023.29" switch \initial - attribute \src "libresoc.v:45466.9-45466.17" + attribute \src "libresoc.v:46023.9-46023.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$64[63:0]$2517 \int_src2__data_o + assign $1\fus_src2_i$64[63:0]$2534 \int_src2__data_o case - assign $1\fus_src2_i$64[63:0]$2517 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$64[63:0]$2534 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2516 + update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2533 end - attribute \src "libresoc.v:45475.3-45483.6" - process $proc$libresoc.v:45475$2518 + attribute \src "libresoc.v:46032.3-46040.6" + process $proc$libresoc.v:46032$2535 assign { } { } assign { } { } - assign $0\dp_INT_rb_trap0_2$next[0:0]$2519 $1\dp_INT_rb_trap0_2$next[0:0]$2520 - attribute \src "libresoc.v:45476.5-45476.29" + assign $0\dp_INT_rb_trap0_2$next[0:0]$2536 $1\dp_INT_rb_trap0_2$next[0:0]$2537 + attribute \src "libresoc.v:46033.5-46033.29" switch \initial - attribute \src "libresoc.v:45476.9-45476.17" + attribute \src "libresoc.v:46033.9-46033.17" case 1'1 case end @@ -78962,44 +79663,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_trap0_2$next[0:0]$2520 1'0 + assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 1'0 case - assign $1\dp_INT_rb_trap0_2$next[0:0]$2520 \rp_INT_rb_trap0_2 + assign $1\dp_INT_rb_trap0_2$next[0:0]$2537 \rp_INT_rb_trap0_2 end sync always - update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2519 + update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2536 end - attribute \src "libresoc.v:45484.3-45493.6" - process $proc$libresoc.v:45484$2521 + attribute \src "libresoc.v:46041.3-46050.6" + process $proc$libresoc.v:46041$2538 assign { } { } assign { } { } - assign $0\fus_src2_i$65[63:0]$2522 $1\fus_src2_i$65[63:0]$2523 - attribute \src "libresoc.v:45485.5-45485.29" + assign $0\fus_src2_i$65[63:0]$2539 $1\fus_src2_i$65[63:0]$2540 + attribute \src "libresoc.v:46042.5-46042.29" switch \initial - attribute \src "libresoc.v:45485.9-45485.17" + attribute \src "libresoc.v:46042.9-46042.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$65[63:0]$2523 \int_src2__data_o + assign $1\fus_src2_i$65[63:0]$2540 \int_src2__data_o case - assign $1\fus_src2_i$65[63:0]$2523 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$65[63:0]$2540 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2522 + update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2539 end - attribute \src "libresoc.v:45494.3-45502.6" - process $proc$libresoc.v:45494$2524 + attribute \src "libresoc.v:46051.3-46059.6" + process $proc$libresoc.v:46051$2541 assign { } { } assign { } { } - assign $0\dp_INT_rb_logical0_3$next[0:0]$2525 $1\dp_INT_rb_logical0_3$next[0:0]$2526 - attribute \src "libresoc.v:45495.5-45495.29" + assign $0\dp_INT_rb_logical0_3$next[0:0]$2542 $1\dp_INT_rb_logical0_3$next[0:0]$2543 + attribute \src "libresoc.v:46052.5-46052.29" switch \initial - attribute \src "libresoc.v:45495.9-45495.17" + attribute \src "libresoc.v:46052.9-46052.17" case 1'1 case end @@ -79008,44 +79709,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_logical0_3$next[0:0]$2526 1'0 + assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 1'0 case - assign $1\dp_INT_rb_logical0_3$next[0:0]$2526 \rp_INT_rb_logical0_3 + assign $1\dp_INT_rb_logical0_3$next[0:0]$2543 \rp_INT_rb_logical0_3 end sync always - update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2525 + update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2542 end - attribute \src "libresoc.v:45503.3-45512.6" - process $proc$libresoc.v:45503$2527 + attribute \src "libresoc.v:46060.3-46069.6" + process $proc$libresoc.v:46060$2544 assign { } { } assign { } { } - assign $0\fus_src2_i$66[63:0]$2528 $1\fus_src2_i$66[63:0]$2529 - attribute \src "libresoc.v:45504.5-45504.29" + assign $0\fus_src2_i$66[63:0]$2545 $1\fus_src2_i$66[63:0]$2546 + attribute \src "libresoc.v:46061.5-46061.29" switch \initial - attribute \src "libresoc.v:45504.9-45504.17" + attribute \src "libresoc.v:46061.9-46061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$66[63:0]$2529 \int_src2__data_o + assign $1\fus_src2_i$66[63:0]$2546 \int_src2__data_o case - assign $1\fus_src2_i$66[63:0]$2529 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$66[63:0]$2546 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2528 + update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2545 end - attribute \src "libresoc.v:45513.3-45521.6" - process $proc$libresoc.v:45513$2530 + attribute \src "libresoc.v:46070.3-46078.6" + process $proc$libresoc.v:46070$2547 assign { } { } assign { } { } - assign $0\dp_INT_rb_div0_4$next[0:0]$2531 $1\dp_INT_rb_div0_4$next[0:0]$2532 - attribute \src "libresoc.v:45514.5-45514.29" + assign $0\dp_INT_rb_div0_4$next[0:0]$2548 $1\dp_INT_rb_div0_4$next[0:0]$2549 + attribute \src "libresoc.v:46071.5-46071.29" switch \initial - attribute \src "libresoc.v:45514.9-45514.17" + attribute \src "libresoc.v:46071.9-46071.17" case 1'1 case end @@ -79054,44 +79755,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_div0_4$next[0:0]$2532 1'0 + assign $1\dp_INT_rb_div0_4$next[0:0]$2549 1'0 case - assign $1\dp_INT_rb_div0_4$next[0:0]$2532 \rp_INT_rb_div0_4 + assign $1\dp_INT_rb_div0_4$next[0:0]$2549 \rp_INT_rb_div0_4 end sync always - update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2531 + update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2548 end - attribute \src "libresoc.v:45522.3-45531.6" - process $proc$libresoc.v:45522$2533 + attribute \src "libresoc.v:46079.3-46088.6" + process $proc$libresoc.v:46079$2550 assign { } { } assign { } { } - assign $0\fus_src2_i$67[63:0]$2534 $1\fus_src2_i$67[63:0]$2535 - attribute \src "libresoc.v:45523.5-45523.29" + assign $0\fus_src2_i$67[63:0]$2551 $1\fus_src2_i$67[63:0]$2552 + attribute \src "libresoc.v:46080.5-46080.29" switch \initial - attribute \src "libresoc.v:45523.9-45523.17" + attribute \src "libresoc.v:46080.9-46080.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_div0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$67[63:0]$2535 \int_src2__data_o + assign $1\fus_src2_i$67[63:0]$2552 \int_src2__data_o case - assign $1\fus_src2_i$67[63:0]$2535 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$67[63:0]$2552 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2534 + update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2551 end - attribute \src "libresoc.v:45532.3-45540.6" - process $proc$libresoc.v:45532$2536 + attribute \src "libresoc.v:46089.3-46097.6" + process $proc$libresoc.v:46089$2553 assign { } { } assign { } { } - assign $0\dp_INT_rb_mul0_5$next[0:0]$2537 $1\dp_INT_rb_mul0_5$next[0:0]$2538 - attribute \src "libresoc.v:45533.5-45533.29" + assign $0\dp_INT_rb_mul0_5$next[0:0]$2554 $1\dp_INT_rb_mul0_5$next[0:0]$2555 + attribute \src "libresoc.v:46090.5-46090.29" switch \initial - attribute \src "libresoc.v:45533.9-45533.17" + attribute \src "libresoc.v:46090.9-46090.17" case 1'1 case end @@ -79100,44 +79801,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_mul0_5$next[0:0]$2538 1'0 + assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 1'0 case - assign $1\dp_INT_rb_mul0_5$next[0:0]$2538 \rp_INT_rb_mul0_5 + assign $1\dp_INT_rb_mul0_5$next[0:0]$2555 \rp_INT_rb_mul0_5 end sync always - update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2537 + update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2554 end - attribute \src "libresoc.v:45541.3-45550.6" - process $proc$libresoc.v:45541$2539 + attribute \src "libresoc.v:46098.3-46107.6" + process $proc$libresoc.v:46098$2556 assign { } { } assign { } { } - assign $0\fus_src2_i$68[63:0]$2540 $1\fus_src2_i$68[63:0]$2541 - attribute \src "libresoc.v:45542.5-45542.29" + assign $0\fus_src2_i$68[63:0]$2557 $1\fus_src2_i$68[63:0]$2558 + attribute \src "libresoc.v:46099.5-46099.29" switch \initial - attribute \src "libresoc.v:45542.9-45542.17" + attribute \src "libresoc.v:46099.9-46099.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_mul0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$68[63:0]$2541 \int_src2__data_o + assign $1\fus_src2_i$68[63:0]$2558 \int_src2__data_o case - assign $1\fus_src2_i$68[63:0]$2541 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$68[63:0]$2558 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2540 + update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2557 end - attribute \src "libresoc.v:45551.3-45559.6" - process $proc$libresoc.v:45551$2542 + attribute \src "libresoc.v:46108.3-46116.6" + process $proc$libresoc.v:46108$2559 assign { } { } assign { } { } - assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 - attribute \src "libresoc.v:45552.5-45552.29" + assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 + attribute \src "libresoc.v:46109.5-46109.29" switch \initial - attribute \src "libresoc.v:45552.9-45552.17" + attribute \src "libresoc.v:46109.9-46109.17" case 1'1 case end @@ -79146,44 +79847,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 1'0 + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 1'0 case - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 \rp_INT_rb_shiftrot0_6 + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 \rp_INT_rb_shiftrot0_6 end sync always - update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 + update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 end - attribute \src "libresoc.v:45560.3-45569.6" - process $proc$libresoc.v:45560$2545 + attribute \src "libresoc.v:46117.3-46126.6" + process $proc$libresoc.v:46117$2562 assign { } { } assign { } { } - assign $0\fus_src2_i$69[63:0]$2546 $1\fus_src2_i$69[63:0]$2547 - attribute \src "libresoc.v:45561.5-45561.29" + assign $0\fus_src2_i$69[63:0]$2563 $1\fus_src2_i$69[63:0]$2564 + attribute \src "libresoc.v:46118.5-46118.29" switch \initial - attribute \src "libresoc.v:45561.9-45561.17" + attribute \src "libresoc.v:46118.9-46118.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_shiftrot0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$69[63:0]$2547 \int_src2__data_o + assign $1\fus_src2_i$69[63:0]$2564 \int_src2__data_o case - assign $1\fus_src2_i$69[63:0]$2547 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$69[63:0]$2564 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2546 + update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2563 end - attribute \src "libresoc.v:45570.3-45578.6" - process $proc$libresoc.v:45570$2548 + attribute \src "libresoc.v:46127.3-46135.6" + process $proc$libresoc.v:46127$2565 assign { } { } assign { } { } - assign $0\dp_INT_rb_ldst0_7$next[0:0]$2549 $1\dp_INT_rb_ldst0_7$next[0:0]$2550 - attribute \src "libresoc.v:45571.5-45571.29" + assign $0\dp_INT_rb_ldst0_7$next[0:0]$2566 $1\dp_INT_rb_ldst0_7$next[0:0]$2567 + attribute \src "libresoc.v:46128.5-46128.29" switch \initial - attribute \src "libresoc.v:45571.9-45571.17" + attribute \src "libresoc.v:46128.9-46128.17" case 1'1 case end @@ -79192,44 +79893,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2550 1'0 + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 1'0 case - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2550 \rp_INT_rb_ldst0_7 + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2567 \rp_INT_rb_ldst0_7 end sync always - update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2549 + update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2566 end - attribute \src "libresoc.v:45579.3-45588.6" - process $proc$libresoc.v:45579$2551 + attribute \src "libresoc.v:46136.3-46145.6" + process $proc$libresoc.v:46136$2568 assign { } { } assign { } { } - assign $0\fus_src2_i$70[63:0]$2552 $1\fus_src2_i$70[63:0]$2553 - attribute \src "libresoc.v:45580.5-45580.29" + assign $0\fus_src2_i$70[63:0]$2569 $1\fus_src2_i$70[63:0]$2570 + attribute \src "libresoc.v:46137.5-46137.29" switch \initial - attribute \src "libresoc.v:45580.9-45580.17" + attribute \src "libresoc.v:46137.9-46137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rb_ldst0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$70[63:0]$2553 \int_src2__data_o + assign $1\fus_src2_i$70[63:0]$2570 \int_src2__data_o case - assign $1\fus_src2_i$70[63:0]$2553 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$70[63:0]$2570 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2552 + update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2569 end - attribute \src "libresoc.v:45589.3-45597.6" - process $proc$libresoc.v:45589$2554 + attribute \src "libresoc.v:46146.3-46154.6" + process $proc$libresoc.v:46146$2571 assign { } { } assign { } { } - assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 - attribute \src "libresoc.v:45590.5-45590.29" + assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 + attribute \src "libresoc.v:46147.5-46147.29" switch \initial - attribute \src "libresoc.v:45590.9-45590.17" + attribute \src "libresoc.v:46147.9-46147.17" case 1'1 case end @@ -79238,25 +79939,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 1'0 + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 1'0 case - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 \rp_INT_rc_shiftrot0_0 + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 \rp_INT_rc_shiftrot0_0 end sync always - update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 + update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 end - attribute \src "libresoc.v:45598.3-45607.6" - process $proc$libresoc.v:45598$2557 + attribute \src "libresoc.v:46155.3-46164.6" + process $proc$libresoc.v:46155$2574 assign { } { } assign { } { } assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45599.5-45599.29" + attribute \src "libresoc.v:46156.5-46156.29" switch \initial - attribute \src "libresoc.v:45599.9-45599.17" + attribute \src "libresoc.v:46156.9-46156.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rc_shiftrot0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79268,14 +79969,14 @@ module \core sync always update \fus_src3_i $0\fus_src3_i[63:0] end - attribute \src "libresoc.v:45608.3-45616.6" - process $proc$libresoc.v:45608$2558 + attribute \src "libresoc.v:46165.3-46173.6" + process $proc$libresoc.v:46165$2575 assign { } { } assign { } { } - assign $0\dp_INT_rc_ldst0_1$next[0:0]$2559 $1\dp_INT_rc_ldst0_1$next[0:0]$2560 - attribute \src "libresoc.v:45609.5-45609.29" + assign $0\dp_INT_rc_ldst0_1$next[0:0]$2576 $1\dp_INT_rc_ldst0_1$next[0:0]$2577 + attribute \src "libresoc.v:46166.5-46166.29" switch \initial - attribute \src "libresoc.v:45609.9-45609.17" + attribute \src "libresoc.v:46166.9-46166.17" case 1'1 case end @@ -79284,96 +79985,90 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2560 1'0 + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 1'0 case - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2560 \rp_INT_rc_ldst0_1 + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2577 \rp_INT_rc_ldst0_1 end sync always - update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2559 + update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2576 end - attribute \src "libresoc.v:45617.3-45626.6" - process $proc$libresoc.v:45617$2561 + attribute \src "libresoc.v:46174.3-46183.6" + process $proc$libresoc.v:46174$2578 assign { } { } assign { } { } - assign $0\fus_src3_i$71[63:0]$2562 $1\fus_src3_i$71[63:0]$2563 - attribute \src "libresoc.v:45618.5-45618.29" + assign $0\fus_src3_i$71[63:0]$2579 $1\fus_src3_i$71[63:0]$2580 + attribute \src "libresoc.v:46175.5-46175.29" switch \initial - attribute \src "libresoc.v:45618.9-45618.17" + attribute \src "libresoc.v:46175.9-46175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" switch \dp_INT_rc_ldst0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$71[63:0]$2563 \int_src3__data_o + assign $1\fus_src3_i$71[63:0]$2580 \int_src3__data_o case - assign $1\fus_src3_i$71[63:0]$2563 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src3_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2562 + update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2579 end - attribute \src "libresoc.v:45627.3-45653.6" - process $proc$libresoc.v:45627$2564 - assign { } { } - assign { } { } + attribute \src "libresoc.v:46184.3-46192.6" + process $proc$libresoc.v:46184$2581 assign { } { } assign { } { } - assign $0\counter$next[1:0]$2565 $4\counter$next[1:0]$2569 - attribute \src "libresoc.v:45628.5-45628.29" + assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 + attribute \src "libresoc.v:46185.5-46185.29" switch \initial - attribute \src "libresoc.v:45628.9-45628.17" + attribute \src "libresoc.v:46185.9-46185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" - switch \$216 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\counter$next[1:0]$2566 \$218 [1:0] + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 1'0 case - assign $1\counter$next[1:0]$2566 \counter + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 \rp_XER_xer_so_alu0_0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 + end + attribute \src "libresoc.v:46193.3-46202.6" + process $proc$libresoc.v:46193$2584 + assign { } { } + assign { } { } + assign $0\fus_src3_i$72[0:0]$2585 $1\fus_src3_i$72[0:0]$2586 + attribute \src "libresoc.v:46194.5-46194.29" + switch \initial + attribute \src "libresoc.v:46194.9-46194.17" case 1'1 - assign { } { } - assign $2\counter$next[1:0]$2567 $3\counter$next[1:0]$2568 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign { } { } - assign $3\counter$next[1:0]$2568 2'10 - case - assign $3\counter$next[1:0]$2568 $1\counter$next[1:0]$2566 - end case - assign $2\counter$next[1:0]$2567 $1\counter$next[1:0]$2566 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\counter$next[1:0]$2569 2'00 + assign $1\fus_src3_i$72[0:0]$2586 \xer_src1__data_o [0] case - assign $4\counter$next[1:0]$2569 $2\counter$next[1:0]$2567 + assign $1\fus_src3_i$72[0:0]$2586 1'0 end sync always - update \counter$next $0\counter$next[1:0]$2565 + update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2585 end - attribute \src "libresoc.v:45654.3-45662.6" - process $proc$libresoc.v:45654$2570 + attribute \src "libresoc.v:46203.3-46211.6" + process $proc$libresoc.v:46203$2587 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 - attribute \src "libresoc.v:45655.5-45655.29" + assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 + attribute \src "libresoc.v:46204.5-46204.29" switch \initial - attribute \src "libresoc.v:45655.9-45655.17" + attribute \src "libresoc.v:46204.9-46204.17" case 1'1 case end @@ -79382,190 +80077,90 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 1'0 + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 1'0 case - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 \rp_XER_xer_so_alu0_0 + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 \rp_XER_xer_so_logical0_1 end sync always - update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 + update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 end - attribute \src "libresoc.v:45663.3-45672.6" - process $proc$libresoc.v:45663$2573 + attribute \src "libresoc.v:46212.3-46221.6" + process $proc$libresoc.v:46212$2590 assign { } { } assign { } { } - assign $0\fus_src3_i$72[0:0]$2574 $1\fus_src3_i$72[0:0]$2575 - attribute \src "libresoc.v:45664.5-45664.29" + assign $0\fus_src3_i$73[0:0]$2591 $1\fus_src3_i$73[0:0]$2592 + attribute \src "libresoc.v:46213.5-46213.29" switch \initial - attribute \src "libresoc.v:45664.9-45664.17" + attribute \src "libresoc.v:46213.9-46213.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_logical0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$72[0:0]$2575 \xer_src1__data_o [0] + assign $1\fus_src3_i$73[0:0]$2592 \xer_src1__data_o [0] case - assign $1\fus_src3_i$72[0:0]$2575 1'0 + assign $1\fus_src3_i$73[0:0]$2592 1'0 end sync always - update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2574 + update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2591 end - attribute \src "libresoc.v:45673.3-45763.6" - process $proc$libresoc.v:45673$2576 + attribute \src "libresoc.v:46222.3-46230.6" + process $proc$libresoc.v:46222$2593 assign { } { } assign { } { } - assign { } { } - assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "libresoc.v:45674.5-45674.29" + assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 + attribute \src "libresoc.v:46223.5-46223.29" switch \initial - attribute \src "libresoc.v:45674.9-45674.17" + attribute \src "libresoc.v:46223.9-46223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" - switch \$221 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\corebusy_o[0:0] 1'1 + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 1'0 case - assign $1\corebusy_o[0:0] 1'0 + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 \rp_XER_xer_so_spr0_2 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i + sync always + update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 + end + attribute \src "libresoc.v:46231.3-46240.6" + process $proc$libresoc.v:46231$2596 + assign { } { } + assign { } { } + assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] + attribute \src "libresoc.v:46232.5-46232.29" + switch \initial + attribute \src "libresoc.v:46232.9-46232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign { } { } - assign $3\corebusy_o[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\corebusy_o[0:0] \fus_cu_busy_o - case - assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\corebusy_o[0:0] \fus_cu_busy_o$14 - case - assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\corebusy_o[0:0] \fus_cu_busy_o$17 - case - assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\corebusy_o[0:0] \fus_cu_busy_o$20 - case - assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\corebusy_o[0:0] \fus_cu_busy_o$23 - case - assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\corebusy_o[0:0] \fus_cu_busy_o$26 - case - assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\corebusy_o[0:0] \fus_cu_busy_o$29 - case - assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\corebusy_o[0:0] \fus_cu_busy_o$32 - case - assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $12\corebusy_o[0:0] \fus_cu_busy_o$35 - case - assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\corebusy_o[0:0] \fus_cu_busy_o$38 - case - assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] - end - end + assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] case - assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] + assign $1\fus_src4_i[0:0] 1'0 end sync always - update \corebusy_o $0\corebusy_o[0:0] + update \fus_src4_i $0\fus_src4_i[0:0] end - attribute \src "libresoc.v:45764.3-45772.6" - process $proc$libresoc.v:45764$2577 + attribute \src "libresoc.v:46241.3-46249.6" + process $proc$libresoc.v:46241$2597 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 - attribute \src "libresoc.v:45765.5-45765.29" + assign $0\dp_XER_xer_so_div0_3$next[0:0]$2598 $1\dp_XER_xer_so_div0_3$next[0:0]$2599 + attribute \src "libresoc.v:46242.5-46242.29" switch \initial - attribute \src "libresoc.v:45765.9-45765.17" + attribute \src "libresoc.v:46242.9-46242.17" case 1'1 case end @@ -79574,44 +80169,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 1'0 + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2599 1'0 case - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 \rp_XER_xer_so_logical0_1 + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2599 \rp_XER_xer_so_div0_3 end sync always - update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 + update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2598 end - attribute \src "libresoc.v:45773.3-45782.6" - process $proc$libresoc.v:45773$2580 + attribute \src "libresoc.v:46250.3-46259.6" + process $proc$libresoc.v:46250$2600 assign { } { } assign { } { } - assign $0\fus_src3_i$73[0:0]$2581 $1\fus_src3_i$73[0:0]$2582 - attribute \src "libresoc.v:45774.5-45774.29" + assign $0\fus_src3_i$74[0:0]$2601 $1\fus_src3_i$74[0:0]$2602 + attribute \src "libresoc.v:46251.5-46251.29" switch \initial - attribute \src "libresoc.v:45774.9-45774.17" + attribute \src "libresoc.v:46251.9-46251.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_div0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$73[0:0]$2582 \xer_src1__data_o [0] + assign $1\fus_src3_i$74[0:0]$2602 \xer_src1__data_o [0] case - assign $1\fus_src3_i$73[0:0]$2582 1'0 + assign $1\fus_src3_i$74[0:0]$2602 1'0 end sync always - update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2581 + update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2601 end - attribute \src "libresoc.v:45783.3-45791.6" - process $proc$libresoc.v:45783$2583 + attribute \src "libresoc.v:46260.3-46268.6" + process $proc$libresoc.v:46260$2603 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 - attribute \src "libresoc.v:45784.5-45784.29" + assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 + attribute \src "libresoc.v:46261.5-46261.29" switch \initial - attribute \src "libresoc.v:45784.9-45784.17" + attribute \src "libresoc.v:46261.9-46261.17" case 1'1 case end @@ -79620,86 +80215,136 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 1'0 + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 1'0 case - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 \rp_XER_xer_so_spr0_2 + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 \rp_XER_xer_so_mul0_4 end sync always - update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 + update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 end - attribute \src "libresoc.v:45792.3-45801.6" - process $proc$libresoc.v:45792$2586 + attribute \src "libresoc.v:46269.3-46278.6" + process $proc$libresoc.v:46269$2606 assign { } { } assign { } { } - assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "libresoc.v:45793.5-45793.29" + assign $0\fus_src3_i$75[0:0]$2607 $1\fus_src3_i$75[0:0]$2608 + attribute \src "libresoc.v:46270.5-46270.29" switch \initial - attribute \src "libresoc.v:45793.9-45793.17" + attribute \src "libresoc.v:46270.9-46270.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_mul0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] + assign $1\fus_src3_i$75[0:0]$2608 \xer_src1__data_o [0] case - assign $1\fus_src4_i[0:0] 1'0 + assign $1\fus_src3_i$75[0:0]$2608 1'0 end sync always - update \fus_src4_i $0\fus_src4_i[0:0] + update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2607 end - attribute \src "libresoc.v:45802.3-45822.6" - process $proc$libresoc.v:45802$2587 + attribute \src "libresoc.v:46279.3-46287.6" + process $proc$libresoc.v:46279$2609 + assign { } { } assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + attribute \src "libresoc.v:46280.5-46280.29" + switch \initial + attribute \src "libresoc.v:46280.9-46280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 1'0 + case + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 \rp_XER_xer_so_shiftrot0_5 + end + sync always + update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 + end + attribute \src "libresoc.v:46288.3-46297.6" + process $proc$libresoc.v:46288$2612 assign { } { } assign { } { } - assign $0\core_terminate_o$next[0:0]$2588 $3\core_terminate_o$next[0:0]$2591 - attribute \src "libresoc.v:45803.5-45803.29" + assign $0\fus_src4_i$76[0:0]$2613 $1\fus_src4_i$76[0:0]$2614 + attribute \src "libresoc.v:46289.5-46289.29" switch \initial - attribute \src "libresoc.v:45803.9-45803.17" + attribute \src "libresoc.v:46289.9-46289.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_so_shiftrot0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_terminate_o$next[0:0]$2589 $2\core_terminate_o$next[0:0]$2590 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign { } { } - assign $2\core_terminate_o$next[0:0]$2590 1'1 - case - assign $2\core_terminate_o$next[0:0]$2590 \core_terminate_o - end + assign $1\fus_src4_i$76[0:0]$2614 \xer_src1__data_o [0] + case + assign $1\fus_src4_i$76[0:0]$2614 1'0 + end + sync always + update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2613 + end + attribute \src "libresoc.v:46298.3-46306.6" + process $proc$libresoc.v:46298$2615 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 + attribute \src "libresoc.v:46299.5-46299.29" + switch \initial + attribute \src "libresoc.v:46299.9-46299.17" + case 1'1 case - assign $1\core_terminate_o$next[0:0]$2589 \core_terminate_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_terminate_o$next[0:0]$2591 1'0 + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 1'0 case - assign $3\core_terminate_o$next[0:0]$2591 $1\core_terminate_o$next[0:0]$2589 + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 \rp_XER_xer_ca_alu0_0 end sync always - update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2588 + update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 end - attribute \src "libresoc.v:45823.3-45831.6" - process $proc$libresoc.v:45823$2592 + attribute \src "libresoc.v:46307.3-46316.6" + process $proc$libresoc.v:46307$2618 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_div0_3$next[0:0]$2593 $1\dp_XER_xer_so_div0_3$next[0:0]$2594 - attribute \src "libresoc.v:45824.5-45824.29" + assign $0\fus_src4_i$77[1:0]$2619 $1\fus_src4_i$77[1:0]$2620 + attribute \src "libresoc.v:46308.5-46308.29" switch \initial - attribute \src "libresoc.v:45824.9-45824.17" + attribute \src "libresoc.v:46308.9-46308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$77[1:0]$2620 \xer_src2__data_o + case + assign $1\fus_src4_i$77[1:0]$2620 2'00 + end + sync always + update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2619 + end + attribute \src "libresoc.v:46317.3-46325.6" + process $proc$libresoc.v:46317$2621 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 + attribute \src "libresoc.v:46318.5-46318.29" + switch \initial + attribute \src "libresoc.v:46318.9-46318.17" case 1'1 case end @@ -79708,44 +80353,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2594 1'0 + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 1'0 case - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2594 \rp_XER_xer_so_div0_3 + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 \rp_XER_xer_ca_spr0_1 end sync always - update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2593 + update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 end - attribute \src "libresoc.v:45832.3-45841.6" - process $proc$libresoc.v:45832$2595 + attribute \src "libresoc.v:46326.3-46335.6" + process $proc$libresoc.v:46326$2624 assign { } { } assign { } { } - assign $0\fus_src3_i$74[0:0]$2596 $1\fus_src3_i$74[0:0]$2597 - attribute \src "libresoc.v:45833.5-45833.29" + assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] + attribute \src "libresoc.v:46327.5-46327.29" switch \initial - attribute \src "libresoc.v:45833.9-45833.17" + attribute \src "libresoc.v:46327.9-46327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_spr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$74[0:0]$2597 \xer_src1__data_o [0] + assign $1\fus_src6_i[1:0] \xer_src2__data_o case - assign $1\fus_src3_i$74[0:0]$2597 1'0 + assign $1\fus_src6_i[1:0] 2'00 end sync always - update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2596 + update \fus_src6_i $0\fus_src6_i[1:0] end - attribute \src "libresoc.v:45842.3-45850.6" - process $proc$libresoc.v:45842$2598 + attribute \src "libresoc.v:46336.3-46344.6" + process $proc$libresoc.v:46336$2625 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 - attribute \src "libresoc.v:45843.5-45843.29" + assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 + attribute \src "libresoc.v:46337.5-46337.29" switch \initial - attribute \src "libresoc.v:45843.9-45843.17" + attribute \src "libresoc.v:46337.9-46337.17" case 1'1 case end @@ -79754,89 +80399,90 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 1'0 + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 1'0 case - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 \rp_XER_xer_so_mul0_4 + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 \rp_XER_xer_ca_shiftrot0_2 end sync always - update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 + update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 end - attribute \src "libresoc.v:45851.3-45860.6" - process $proc$libresoc.v:45851$2601 + attribute \src "libresoc.v:46345.3-46354.6" + process $proc$libresoc.v:46345$2628 assign { } { } assign { } { } - assign $0\fus_src3_i$75[0:0]$2602 $1\fus_src3_i$75[0:0]$2603 - attribute \src "libresoc.v:45852.5-45852.29" + assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] + attribute \src "libresoc.v:46346.5-46346.29" switch \initial - attribute \src "libresoc.v:45852.9-45852.17" + attribute \src "libresoc.v:46346.9-46346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ca_shiftrot0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$75[0:0]$2603 \xer_src1__data_o [0] + assign $1\fus_src5_i[1:0] \xer_src2__data_o case - assign $1\fus_src3_i$75[0:0]$2603 1'0 + assign $1\fus_src5_i[1:0] 2'00 end sync always - update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2602 + update \fus_src5_i $0\fus_src5_i[1:0] end - attribute \src "libresoc.v:45861.3-45889.6" - process $proc$libresoc.v:45861$2604 + attribute \src "libresoc.v:46355.3-46363.6" + process $proc$libresoc.v:46355$2629 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45862.5-45862.29" + assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 + attribute \src "libresoc.v:46356.5-46356.29" switch \initial - attribute \src "libresoc.v:45862.9-45862.17" + attribute \src "libresoc.v:46356.9-46356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type - case - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - end - end + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 1'0 case - assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 \rp_XER_xer_ov_spr0_0 end sync always - update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] + update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 + end + attribute \src "libresoc.v:46364.3-46373.6" + process $proc$libresoc.v:46364$2632 + assign { } { } + assign { } { } + assign $0\fus_src5_i$78[1:0]$2633 $1\fus_src5_i$78[1:0]$2634 + attribute \src "libresoc.v:46365.5-46365.29" + switch \initial + attribute \src "libresoc.v:46365.9-46365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_XER_xer_ov_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$78[1:0]$2634 \xer_src3__data_o + case + assign $1\fus_src5_i$78[1:0]$2634 2'00 + end + sync always + update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2633 end - attribute \src "libresoc.v:45890.3-45898.6" - process $proc$libresoc.v:45890$2605 + attribute \src "libresoc.v:46374.3-46382.6" + process $proc$libresoc.v:46374$2635 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 - attribute \src "libresoc.v:45891.5-45891.29" + assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 + attribute \src "libresoc.v:46375.5-46375.29" switch \initial - attribute \src "libresoc.v:45891.9-45891.17" + attribute \src "libresoc.v:46375.9-46375.17" case 1'1 case end @@ -79845,44 +80491,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 1'0 + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 1'0 case - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 \rp_XER_xer_so_shiftrot0_5 + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 \rp_CR_full_cr_cr0_0 end sync always - update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 + update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 end - attribute \src "libresoc.v:45899.3-45908.6" - process $proc$libresoc.v:45899$2608 + attribute \src "libresoc.v:46383.3-46392.6" + process $proc$libresoc.v:46383$2638 assign { } { } assign { } { } - assign $0\fus_src4_i$76[0:0]$2609 $1\fus_src4_i$76[0:0]$2610 - attribute \src "libresoc.v:45900.5-45900.29" + assign $0\fus_src3_i$79[31:0]$2639 $1\fus_src3_i$79[31:0]$2640 + attribute \src "libresoc.v:46384.5-46384.29" switch \initial - attribute \src "libresoc.v:45900.9-45900.17" + attribute \src "libresoc.v:46384.9-46384.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_full_cr_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$76[0:0]$2610 \xer_src1__data_o [0] + assign $1\fus_src3_i$79[31:0]$2640 \cr_full_rd__data_o case - assign $1\fus_src4_i$76[0:0]$2610 1'0 + assign $1\fus_src3_i$79[31:0]$2640 0 end sync always - update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2609 + update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2639 end - attribute \src "libresoc.v:45909.3-45917.6" - process $proc$libresoc.v:45909$2611 + attribute \src "libresoc.v:46393.3-46401.6" + process $proc$libresoc.v:46393$2641 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 - attribute \src "libresoc.v:45910.5-45910.29" + assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 + attribute \src "libresoc.v:46394.5-46394.29" switch \initial - attribute \src "libresoc.v:45910.9-45910.17" + attribute \src "libresoc.v:46394.9-46394.17" case 1'1 case end @@ -79891,135 +80537,142 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 1'0 + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 1'0 case - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 \rp_XER_xer_ca_alu0_0 + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 \rp_CR_cr_a_cr0_0 end sync always - update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 + update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 end - attribute \src "libresoc.v:45918.3-45946.6" - process $proc$libresoc.v:45918$2614 + attribute \src "libresoc.v:46402.3-46411.6" + process $proc$libresoc.v:46402$2644 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__fn_unit[12:0] $1\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45919.5-45919.29" + assign $0\fus_src4_i$80[3:0]$2645 $1\fus_src4_i$80[3:0]$2646 + attribute \src "libresoc.v:46403.5-46403.29" switch \initial - attribute \src "libresoc.v:45919.9-45919.17" + attribute \src "libresoc.v:46403.9-46403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_a_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__fn_unit[12:0] $2\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__fn_unit[12:0] $3\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__fn_unit[12:0] \dec_ALU_ALU__fn_unit - case - assign $3\fus_oper_i_alu_alu0__fn_unit[12:0] 13'0000000000000 - end - end + assign $1\fus_src4_i$80[3:0]$2646 \cr_src1__data_o case - assign $1\fus_oper_i_alu_alu0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_src4_i$80[3:0]$2646 4'0000 end sync always - update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[12:0] + update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2645 end - attribute \src "libresoc.v:45947.3-45956.6" - process $proc$libresoc.v:45947$2615 + attribute \src "libresoc.v:46412.3-46420.6" + process $proc$libresoc.v:46412$2647 assign { } { } assign { } { } - assign $0\fus_src4_i$77[1:0]$2616 $1\fus_src4_i$77[1:0]$2617 - attribute \src "libresoc.v:45948.5-45948.29" + assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 + attribute \src "libresoc.v:46413.5-46413.29" switch \initial - attribute \src "libresoc.v:45948.9-45948.17" + attribute \src "libresoc.v:46413.9-46413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$77[1:0]$2617 \xer_src2__data_o + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 1'0 case - assign $1\fus_src4_i$77[1:0]$2617 2'00 + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 \rp_CR_cr_a_branch0_1 end sync always - update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2616 + update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 end - attribute \src "libresoc.v:45957.3-45965.6" - process $proc$libresoc.v:45957$2618 + attribute \src "libresoc.v:46421.3-46430.6" + process $proc$libresoc.v:46421$2650 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 - attribute \src "libresoc.v:45958.5-45958.29" + assign $0\fus_src3_i$83[3:0]$2651 $1\fus_src3_i$83[3:0]$2652 + attribute \src "libresoc.v:46422.5-46422.29" switch \initial - attribute \src "libresoc.v:45958.9-45958.17" + attribute \src "libresoc.v:46422.9-46422.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_a_branch0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 1'0 + assign $1\fus_src3_i$83[3:0]$2652 \cr_src1__data_o case - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 \rp_XER_xer_ca_spr0_1 + assign $1\fus_src3_i$83[3:0]$2652 4'0000 end sync always - update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 + update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2651 end - attribute \src "libresoc.v:45966.3-45975.6" - process $proc$libresoc.v:45966$2621 + attribute \src "libresoc.v:46431.3-46457.6" + process $proc$libresoc.v:46431$2653 assign { } { } assign { } { } - assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "libresoc.v:45967.5-45967.29" + assign { } { } + assign { } { } + assign $0\counter$next[1:0]$2654 $4\counter$next[1:0]$2658 + attribute \src "libresoc.v:46432.5-46432.29" switch \initial - attribute \src "libresoc.v:45967.9-45967.17" + attribute \src "libresoc.v:46432.9-46432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \$221 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src6_i[1:0] \xer_src2__data_o + assign $1\counter$next[1:0]$2655 \$223 [1:0] case - assign $1\fus_src6_i[1:0] 2'00 + assign $1\counter$next[1:0]$2655 \counter + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter$next[1:0]$2656 $3\counter$next[1:0]$2657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\counter$next[1:0]$2657 2'10 + case + assign $3\counter$next[1:0]$2657 $1\counter$next[1:0]$2655 + end + case + assign $2\counter$next[1:0]$2656 $1\counter$next[1:0]$2655 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\counter$next[1:0]$2658 2'00 + case + assign $4\counter$next[1:0]$2658 $2\counter$next[1:0]$2656 end sync always - update \fus_src6_i $0\fus_src6_i[1:0] + update \counter$next $0\counter$next[1:0]$2654 end - attribute \src "libresoc.v:45976.3-45984.6" - process $proc$libresoc.v:45976$2622 + attribute \src "libresoc.v:46458.3-46466.6" + process $proc$libresoc.v:46458$2659 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 - attribute \src "libresoc.v:45977.5-45977.29" + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:46459.5-46459.29" switch \initial - attribute \src "libresoc.v:45977.9-45977.17" + attribute \src "libresoc.v:46459.9-46459.17" case 1'1 case end @@ -80028,148 +80681,278 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 1'0 + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 1'0 case - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 \rp_XER_xer_ca_shiftrot0_2 + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 \rp_CR_cr_b_cr0_0 end sync always - update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 end - attribute \src "libresoc.v:45985.3-46014.6" - process $proc$libresoc.v:45985$2625 + attribute \src "libresoc.v:46467.3-46476.6" + process $proc$libresoc.v:46467$2662 + assign { } { } assign { } { } + assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664 + attribute \src "libresoc.v:46468.5-46468.29" + switch \initial + attribute \src "libresoc.v:46468.9-46468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_b_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$84[3:0]$2664 \cr_src2__data_o + case + assign $1\fus_src5_i$84[3:0]$2664 4'0000 + end + sync always + update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663 + end + attribute \src "libresoc.v:46477.3-46567.6" + process $proc$libresoc.v:46477$2665 assign { } { } assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45986.5-45986.29" + assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] + attribute \src "libresoc.v:46478.5-46478.29" switch \initial - attribute \src "libresoc.v:45986.9-45986.17" + attribute \src "libresoc.v:46478.9-46478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $1\corebusy_o[0:0] 1'1 + case + assign $1\corebusy_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + assign { } { } + assign $3\corebusy_o[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $4\corebusy_o[0:0] \fus_cu_busy_o + case + assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } + assign $5\corebusy_o[0:0] \fus_cu_busy_o$14 case - assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\corebusy_o[0:0] \fus_cu_busy_o$17 + case + assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\corebusy_o[0:0] \fus_cu_busy_o$20 + case + assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\corebusy_o[0:0] \fus_cu_busy_o$23 + case + assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\corebusy_o[0:0] \fus_cu_busy_o$26 + case + assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\corebusy_o[0:0] \fus_cu_busy_o$29 + case + assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\corebusy_o[0:0] \fus_cu_busy_o$32 + case + assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\corebusy_o[0:0] \fus_cu_busy_o$35 + case + assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\corebusy_o[0:0] \fus_cu_busy_o$38 + case + assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] end end case - assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] end sync always - update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + update \corebusy_o $0\corebusy_o[0:0] end - attribute \src "libresoc.v:46015.3-46024.6" - process $proc$libresoc.v:46015$2626 + attribute \src "libresoc.v:46568.3-46576.6" + process $proc$libresoc.v:46568$2666 assign { } { } assign { } { } - assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46016.5-46016.29" + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 + attribute \src "libresoc.v:46569.5-46569.29" switch \initial - attribute \src "libresoc.v:46016.9-46016.17" + attribute \src "libresoc.v:46569.9-46569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i[1:0] \xer_src2__data_o + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 1'0 case - assign $1\fus_src5_i[1:0] 2'00 + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 \rp_CR_cr_c_cr0_0 end sync always - update \fus_src5_i $0\fus_src5_i[1:0] + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 end - attribute \src "libresoc.v:46025.3-46033.6" - process $proc$libresoc.v:46025$2627 + attribute \src "libresoc.v:46577.3-46586.6" + process $proc$libresoc.v:46577$2669 assign { } { } assign { } { } - assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 - attribute \src "libresoc.v:46026.5-46026.29" + assign $0\fus_src6_i$85[3:0]$2670 $1\fus_src6_i$85[3:0]$2671 + attribute \src "libresoc.v:46578.5-46578.29" switch \initial - attribute \src "libresoc.v:46026.9-46026.17" + attribute \src "libresoc.v:46578.9-46578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_CR_cr_c_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 1'0 + assign $1\fus_src6_i$85[3:0]$2671 \cr_src3__data_o case - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 \rp_XER_xer_ov_spr0_0 + assign $1\fus_src6_i$85[3:0]$2671 4'0000 end sync always - update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 + update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2670 end - attribute \src "libresoc.v:46034.3-46043.6" - process $proc$libresoc.v:46034$2630 + attribute \src "libresoc.v:46587.3-46607.6" + process $proc$libresoc.v:46587$2672 assign { } { } assign { } { } - assign $0\fus_src5_i$78[1:0]$2631 $1\fus_src5_i$78[1:0]$2632 - attribute \src "libresoc.v:46035.5-46035.29" + assign { } { } + assign $0\core_terminate_o$next[0:0]$2673 $3\core_terminate_o$next[0:0]$2676 + attribute \src "libresoc.v:46588.5-46588.29" switch \initial - attribute \src "libresoc.v:46035.9-46035.17" + attribute \src "libresoc.v:46588.9-46588.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_terminate_o$next[0:0]$2674 $2\core_terminate_o$next[0:0]$2675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign { } { } + assign $2\core_terminate_o$next[0:0]$2675 1'1 + case + assign $2\core_terminate_o$next[0:0]$2675 \core_terminate_o + end + case + assign $1\core_terminate_o$next[0:0]$2674 \core_terminate_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i$78[1:0]$2632 \xer_src3__data_o + assign $3\core_terminate_o$next[0:0]$2676 1'0 case - assign $1\fus_src5_i$78[1:0]$2632 2'00 + assign $3\core_terminate_o$next[0:0]$2676 $1\core_terminate_o$next[0:0]$2674 end sync always - update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2631 + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2673 end - attribute \src "libresoc.v:46044.3-46052.6" - process $proc$libresoc.v:46044$2633 + attribute \src "libresoc.v:46608.3-46616.6" + process $proc$libresoc.v:46608$2677 assign { } { } assign { } { } - assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 - attribute \src "libresoc.v:46045.5-46045.29" + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 + attribute \src "libresoc.v:46609.5-46609.29" switch \initial - attribute \src "libresoc.v:46045.9-46045.17" + attribute \src "libresoc.v:46609.9-46609.17" case 1'1 case end @@ -80178,102 +80961,135 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 1'0 + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 1'0 case - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 \rp_CR_full_cr_cr0_0 + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 \rp_FAST_fast1_branch0_0 end sync always - update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 end - attribute \src "libresoc.v:46053.3-46062.6" - process $proc$libresoc.v:46053$2636 + attribute \src "libresoc.v:46617.3-46626.6" + process $proc$libresoc.v:46617$2680 assign { } { } assign { } { } - assign $0\fus_src3_i$79[31:0]$2637 $1\fus_src3_i$79[31:0]$2638 - attribute \src "libresoc.v:46054.5-46054.29" + assign $0\fus_src1_i$86[63:0]$2681 $1\fus_src1_i$86[63:0]$2682 + attribute \src "libresoc.v:46618.5-46618.29" switch \initial - attribute \src "libresoc.v:46054.9-46054.17" + attribute \src "libresoc.v:46618.9-46618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_branch0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$79[31:0]$2638 \cr_full_rd__data_o + assign $1\fus_src1_i$86[63:0]$2682 \fast_src1__data_o case - assign $1\fus_src3_i$79[31:0]$2638 0 + assign $1\fus_src1_i$86[63:0]$2682 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2637 + update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2681 end - attribute \src "libresoc.v:46063.3-46092.6" - process $proc$libresoc.v:46063$2639 + attribute \src "libresoc.v:46627.3-46635.6" + process $proc$libresoc.v:46627$2683 assign { } { } assign { } { } + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 + attribute \src "libresoc.v:46628.5-46628.29" + switch \initial + attribute \src "libresoc.v:46628.9-46628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 1'0 + case + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 \rp_FAST_fast1_trap0_1 + end + sync always + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 + end + attribute \src "libresoc.v:46636.3-46645.6" + process $proc$libresoc.v:46636$2686 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46064.5-46064.29" + assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688 + attribute \src "libresoc.v:46637.5-46637.29" switch \initial - attribute \src "libresoc.v:46064.9-46064.17" + attribute \src "libresoc.v:46637.9-46637.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_trap0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $1\fus_src3_i$87[63:0]$2688 \fast_src1__data_o + case + assign $1\fus_src3_i$87[63:0]$2688 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687 + end + attribute \src "libresoc.v:46646.3-46674.6" + process $proc$libresoc.v:46646$2689 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46647.5-46647.29" + switch \initial + attribute \src "libresoc.v:46647.9-46647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type case - assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 end end case - assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 end sync always - update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] - update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] + update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] end - attribute \src "libresoc.v:46093.3-46101.6" - process $proc$libresoc.v:46093$2640 + attribute \src "libresoc.v:46675.3-46683.6" + process $proc$libresoc.v:46675$2690 assign { } { } assign { } { } - assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:46094.5-46094.29" + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 + attribute \src "libresoc.v:46676.5-46676.29" switch \initial - attribute \src "libresoc.v:46094.9-46094.17" + attribute \src "libresoc.v:46676.9-46676.17" case 1'1 case end @@ -80282,44 +81098,89 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 1'0 + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 1'0 case - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 \rp_CR_cr_a_cr0_0 + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 \rp_FAST_fast1_spr0_2 end sync always - update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 end - attribute \src "libresoc.v:46102.3-46111.6" - process $proc$libresoc.v:46102$2643 + attribute \src "libresoc.v:46684.3-46693.6" + process $proc$libresoc.v:46684$2693 assign { } { } assign { } { } - assign $0\fus_src4_i$80[3:0]$2644 $1\fus_src4_i$80[3:0]$2645 - attribute \src "libresoc.v:46103.5-46103.29" + assign $0\fus_src3_i$88[63:0]$2694 $1\fus_src3_i$88[63:0]$2695 + attribute \src "libresoc.v:46685.5-46685.29" switch \initial - attribute \src "libresoc.v:46103.9-46103.17" + attribute \src "libresoc.v:46685.9-46685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast1_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$80[3:0]$2645 \cr_src1__data_o + assign $1\fus_src3_i$88[63:0]$2695 \fast_src1__data_o case - assign $1\fus_src4_i$80[3:0]$2645 4'0000 + assign $1\fus_src3_i$88[63:0]$2695 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2644 + update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2694 end - attribute \src "libresoc.v:46112.3-46120.6" - process $proc$libresoc.v:46112$2646 + attribute \src "libresoc.v:46694.3-46722.6" + process $proc$libresoc.v:46694$2696 assign { } { } assign { } { } - assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:46113.5-46113.29" + assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "libresoc.v:46695.5-46695.29" switch \initial - attribute \src "libresoc.v:46113.9-46113.17" + attribute \src "libresoc.v:46695.9-46695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] \dec_ALU_ALU__fn_unit + case + assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 + end + sync always + update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0] + end + attribute \src "libresoc.v:46723.3-46731.6" + process $proc$libresoc.v:46723$2697 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 + attribute \src "libresoc.v:46724.5-46724.29" + switch \initial + attribute \src "libresoc.v:46724.9-46724.17" case 1'1 case end @@ -80328,44 +81189,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 1'0 + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 1'0 case - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 \rp_CR_cr_a_branch0_1 + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 \rp_FAST_fast2_branch0_0 end sync always - update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 + update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 end - attribute \src "libresoc.v:46121.3-46130.6" - process $proc$libresoc.v:46121$2649 + attribute \src "libresoc.v:46732.3-46741.6" + process $proc$libresoc.v:46732$2700 assign { } { } assign { } { } - assign $0\fus_src3_i$83[3:0]$2650 $1\fus_src3_i$83[3:0]$2651 - attribute \src "libresoc.v:46122.5-46122.29" + assign $0\fus_src2_i$89[63:0]$2701 $1\fus_src2_i$89[63:0]$2702 + attribute \src "libresoc.v:46733.5-46733.29" switch \initial - attribute \src "libresoc.v:46122.9-46122.17" + attribute \src "libresoc.v:46733.9-46733.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast2_branch0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$83[3:0]$2651 \cr_src1__data_o + assign $1\fus_src2_i$89[63:0]$2702 \fast_src2__data_o case - assign $1\fus_src3_i$83[3:0]$2651 4'0000 + assign $1\fus_src2_i$89[63:0]$2702 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2650 + update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2701 end - attribute \src "libresoc.v:46131.3-46139.6" - process $proc$libresoc.v:46131$2652 + attribute \src "libresoc.v:46742.3-46750.6" + process $proc$libresoc.v:46742$2703 assign { } { } assign { } { } - assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 - attribute \src "libresoc.v:46132.5-46132.29" + assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 + attribute \src "libresoc.v:46743.5-46743.29" switch \initial - attribute \src "libresoc.v:46132.9-46132.17" + attribute \src "libresoc.v:46743.9-46743.17" case 1'1 case end @@ -80374,102 +81235,102 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 1'0 + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 1'0 case - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 \rp_CR_cr_b_cr0_0 + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 \rp_FAST_fast2_trap0_1 end sync always - update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 + update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 end - attribute \src "libresoc.v:46140.3-46149.6" - process $proc$libresoc.v:46140$2655 + attribute \src "libresoc.v:46751.3-46760.6" + process $proc$libresoc.v:46751$2706 assign { } { } assign { } { } - assign $0\fus_src5_i$84[3:0]$2656 $1\fus_src5_i$84[3:0]$2657 - attribute \src "libresoc.v:46141.5-46141.29" + assign $0\fus_src4_i$90[63:0]$2707 $1\fus_src4_i$90[63:0]$2708 + attribute \src "libresoc.v:46752.5-46752.29" switch \initial - attribute \src "libresoc.v:46141.9-46141.17" + attribute \src "libresoc.v:46752.9-46752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_FAST_fast2_trap0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i$84[3:0]$2657 \cr_src2__data_o + assign $1\fus_src4_i$90[63:0]$2708 \fast_src2__data_o case - assign $1\fus_src5_i$84[3:0]$2657 4'0000 + assign $1\fus_src4_i$90[63:0]$2708 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2656 + update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2707 end - attribute \src "libresoc.v:46150.3-46179.6" - process $proc$libresoc.v:46150$2658 + attribute \src "libresoc.v:46761.3-46790.6" + process $proc$libresoc.v:46761$2709 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46151.5-46151.29" + assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46762.5-46762.29" switch \initial - attribute \src "libresoc.v:46151.9-46151.17" + attribute \src "libresoc.v:46762.9-46762.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } + assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } case - assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 end sync always - update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] - update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] + update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] end - attribute \src "libresoc.v:46180.3-46188.6" - process $proc$libresoc.v:46180$2659 + attribute \src "libresoc.v:46791.3-46799.6" + process $proc$libresoc.v:46791$2710 assign { } { } assign { } { } - assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:46181.5-46181.29" + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 + attribute \src "libresoc.v:46792.5-46792.29" switch \initial - attribute \src "libresoc.v:46181.9-46181.17" + attribute \src "libresoc.v:46792.9-46792.17" case 1'1 case end @@ -80478,44 +81339,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 1'0 + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 1'0 case - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 \rp_CR_cr_c_cr0_0 + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 \rp_SPR_spr1_spr0_0 end sync always - update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 end - attribute \src "libresoc.v:46189.3-46198.6" - process $proc$libresoc.v:46189$2662 + attribute \src "libresoc.v:46800.3-46809.6" + process $proc$libresoc.v:46800$2713 assign { } { } assign { } { } - assign $0\fus_src6_i$85[3:0]$2663 $1\fus_src6_i$85[3:0]$2664 - attribute \src "libresoc.v:46190.5-46190.29" + assign $0\fus_src2_i$91[63:0]$2714 $1\fus_src2_i$91[63:0]$2715 + attribute \src "libresoc.v:46801.5-46801.29" switch \initial - attribute \src "libresoc.v:46190.9-46190.17" + attribute \src "libresoc.v:46801.9-46801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:300" + switch \dp_SPR_spr1_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src6_i$85[3:0]$2664 \cr_src3__data_o + assign $1\fus_src2_i$91[63:0]$2715 \spr_spr1__data_o case - assign $1\fus_src6_i$85[3:0]$2664 4'0000 + assign $1\fus_src2_i$91[63:0]$2715 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2663 + update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2714 end - attribute \src "libresoc.v:46199.3-46207.6" - process $proc$libresoc.v:46199$2665 + attribute \src "libresoc.v:46810.3-46818.6" + process $proc$libresoc.v:46810$2716 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 - attribute \src "libresoc.v:46200.5-46200.29" + assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718 + attribute \src "libresoc.v:46811.5-46811.29" switch \initial - attribute \src "libresoc.v:46200.9-46200.17" + attribute \src "libresoc.v:46811.9-46811.17" case 1'1 case end @@ -80524,44 +81385,102 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 1'0 + assign $1\wr_pick_dly$next[0:0]$2718 1'0 case - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 \rp_FAST_fast1_branch0_0 + assign $1\wr_pick_dly$next[0:0]$2718 \wr_pick end sync always - update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717 end - attribute \src "libresoc.v:46208.3-46217.6" - process $proc$libresoc.v:46208$2668 + attribute \src "libresoc.v:46819.3-46827.6" + process $proc$libresoc.v:46819$2719 assign { } { } assign { } { } - assign $0\fus_src1_i$86[63:0]$2669 $1\fus_src1_i$86[63:0]$2670 - attribute \src "libresoc.v:46209.5-46209.29" + assign $0\wr_pick_dly$991$next[0:0]$2720 $1\wr_pick_dly$991$next[0:0]$2721 + attribute \src "libresoc.v:46820.5-46820.29" switch \initial - attribute \src "libresoc.v:46209.9-46209.17" + attribute \src "libresoc.v:46820.9-46820.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$991$next[0:0]$2721 1'0 + case + assign $1\wr_pick_dly$991$next[0:0]$2721 \wr_pick$988 + end + sync always + update \wr_pick_dly$991$next $0\wr_pick_dly$991$next[0:0]$2720 + end + attribute \src "libresoc.v:46828.3-46857.6" + process $proc$libresoc.v:46828$2722 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46829.5-46829.29" + switch \initial + attribute \src "libresoc.v:46829.9-46829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$86[63:0]$2670 \fast_src1__data_o + assign { } { } + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } + case + assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + end case - assign $1\fus_src1_i$86[63:0]$2670 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 end sync always - update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2669 + update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] + update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] end - attribute \src "libresoc.v:46218.3-46226.6" - process $proc$libresoc.v:46218$2671 + attribute \src "libresoc.v:46858.3-46866.6" + process $proc$libresoc.v:46858$2723 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 - attribute \src "libresoc.v:46219.5-46219.29" + assign $0\wr_pick_dly$1010$next[0:0]$2724 $1\wr_pick_dly$1010$next[0:0]$2725 + attribute \src "libresoc.v:46859.5-46859.29" switch \initial - attribute \src "libresoc.v:46219.9-46219.17" + attribute \src "libresoc.v:46859.9-46859.17" case 1'1 case end @@ -80570,89 +81489,102 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 1'0 + assign $1\wr_pick_dly$1010$next[0:0]$2725 1'0 case - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 \rp_FAST_fast1_trap0_1 + assign $1\wr_pick_dly$1010$next[0:0]$2725 \wr_pick$1007 end sync always - update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 + update \wr_pick_dly$1010$next $0\wr_pick_dly$1010$next[0:0]$2724 end - attribute \src "libresoc.v:46227.3-46236.6" - process $proc$libresoc.v:46227$2674 + attribute \src "libresoc.v:46867.3-46875.6" + process $proc$libresoc.v:46867$2726 assign { } { } assign { } { } - assign $0\fus_src3_i$87[63:0]$2675 $1\fus_src3_i$87[63:0]$2676 - attribute \src "libresoc.v:46228.5-46228.29" + assign $0\wr_pick_dly$1031$next[0:0]$2727 $1\wr_pick_dly$1031$next[0:0]$2728 + attribute \src "libresoc.v:46868.5-46868.29" switch \initial - attribute \src "libresoc.v:46228.9-46228.17" + attribute \src "libresoc.v:46868.9-46868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$87[63:0]$2676 \fast_src1__data_o + assign $1\wr_pick_dly$1031$next[0:0]$2728 1'0 case - assign $1\fus_src3_i$87[63:0]$2676 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1031$next[0:0]$2728 \wr_pick$1028 end sync always - update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2675 + update \wr_pick_dly$1031$next $0\wr_pick_dly$1031$next[0:0]$2727 end - attribute \src "libresoc.v:46237.3-46265.6" - process $proc$libresoc.v:46237$2677 + attribute \src "libresoc.v:46876.3-46905.6" + process $proc$libresoc.v:46876$2729 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46238.5-46238.29" + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46877.5-46877.29" switch \initial - attribute \src "libresoc.v:46238.9-46238.17" + attribute \src "libresoc.v:46877.9-46877.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign { } { } + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign { } { } + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in + assign { } { } + assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } case - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 end sync always - update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] + update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] + update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] end - attribute \src "libresoc.v:46266.3-46274.6" - process $proc$libresoc.v:46266$2678 + attribute \src "libresoc.v:46906.3-46914.6" + process $proc$libresoc.v:46906$2730 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 - attribute \src "libresoc.v:46267.5-46267.29" + assign $0\wr_pick_dly$1049$next[0:0]$2731 $1\wr_pick_dly$1049$next[0:0]$2732 + attribute \src "libresoc.v:46907.5-46907.29" switch \initial - attribute \src "libresoc.v:46267.9-46267.17" + attribute \src "libresoc.v:46907.9-46907.17" case 1'1 case end @@ -80661,89 +81593,112 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 1'0 + assign $1\wr_pick_dly$1049$next[0:0]$2732 1'0 case - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 \rp_FAST_fast1_spr0_2 + assign $1\wr_pick_dly$1049$next[0:0]$2732 \wr_pick$1046 end sync always - update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 + update \wr_pick_dly$1049$next $0\wr_pick_dly$1049$next[0:0]$2731 end - attribute \src "libresoc.v:46275.3-46284.6" - process $proc$libresoc.v:46275$2681 + attribute \src "libresoc.v:46915.3-46923.6" + process $proc$libresoc.v:46915$2733 assign { } { } assign { } { } - assign $0\fus_src3_i$88[63:0]$2682 $1\fus_src3_i$88[63:0]$2683 - attribute \src "libresoc.v:46276.5-46276.29" + assign $0\wr_pick_dly$1071$next[0:0]$2734 $1\wr_pick_dly$1071$next[0:0]$2735 + attribute \src "libresoc.v:46916.5-46916.29" switch \initial - attribute \src "libresoc.v:46276.9-46276.17" + attribute \src "libresoc.v:46916.9-46916.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$88[63:0]$2683 \fast_src1__data_o + assign $1\wr_pick_dly$1071$next[0:0]$2735 1'0 case - assign $1\fus_src3_i$88[63:0]$2683 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1071$next[0:0]$2735 \wr_pick$1068 end sync always - update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2682 + update \wr_pick_dly$1071$next $0\wr_pick_dly$1071$next[0:0]$2734 end - attribute \src "libresoc.v:46285.3-46313.6" - process $proc$libresoc.v:46285$2684 + attribute \src "libresoc.v:46924.3-46932.6" + process $proc$libresoc.v:46924$2736 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46286.5-46286.29" + assign $0\wr_pick_dly$1091$next[0:0]$2737 $1\wr_pick_dly$1091$next[0:0]$2738 + attribute \src "libresoc.v:46925.5-46925.29" + switch \initial + attribute \src "libresoc.v:46925.9-46925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1091$next[0:0]$2738 1'0 + case + assign $1\wr_pick_dly$1091$next[0:0]$2738 \wr_pick$1088 + end + sync always + update \wr_pick_dly$1091$next $0\wr_pick_dly$1091$next[0:0]$2737 + end + attribute \src "libresoc.v:46933.3-46961.6" + process $proc$libresoc.v:46933$2739 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46934.5-46934.29" switch \initial - attribute \src "libresoc.v:46286.9-46286.17" + attribute \src "libresoc.v:46934.9-46934.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in case - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 end sync always - update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] + update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] end - attribute \src "libresoc.v:46314.3-46322.6" - process $proc$libresoc.v:46314$2685 + attribute \src "libresoc.v:46962.3-46970.6" + process $proc$libresoc.v:46962$2740 assign { } { } assign { } { } - assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 - attribute \src "libresoc.v:46315.5-46315.29" + assign $0\wr_pick_dly$1111$next[0:0]$2741 $1\wr_pick_dly$1111$next[0:0]$2742 + attribute \src "libresoc.v:46963.5-46963.29" switch \initial - attribute \src "libresoc.v:46315.9-46315.17" + attribute \src "libresoc.v:46963.9-46963.17" case 1'1 case end @@ -80752,100 +81707,122 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 1'0 + assign $1\wr_pick_dly$1111$next[0:0]$2742 1'0 case - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 \rp_FAST_fast2_branch0_0 + assign $1\wr_pick_dly$1111$next[0:0]$2742 \wr_pick$1108 end sync always - update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 + update \wr_pick_dly$1111$next $0\wr_pick_dly$1111$next[0:0]$2741 end - attribute \src "libresoc.v:46323.3-46332.6" - process $proc$libresoc.v:46323$2688 + attribute \src "libresoc.v:46971.3-46979.6" + process $proc$libresoc.v:46971$2743 assign { } { } assign { } { } - assign $0\fus_src2_i$89[63:0]$2689 $1\fus_src2_i$89[63:0]$2690 - attribute \src "libresoc.v:46324.5-46324.29" + assign $0\wr_pick_dly$1130$next[0:0]$2744 $1\wr_pick_dly$1130$next[0:0]$2745 + attribute \src "libresoc.v:46972.5-46972.29" switch \initial - attribute \src "libresoc.v:46324.9-46324.17" + attribute \src "libresoc.v:46972.9-46972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$89[63:0]$2690 \fast_src2__data_o + assign $1\wr_pick_dly$1130$next[0:0]$2745 1'0 case - assign $1\fus_src2_i$89[63:0]$2690 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1130$next[0:0]$2745 \wr_pick$1127 end sync always - update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2689 + update \wr_pick_dly$1130$next $0\wr_pick_dly$1130$next[0:0]$2744 end - attribute \src "libresoc.v:46333.3-46341.6" - process $proc$libresoc.v:46333$2691 + attribute \src "libresoc.v:46980.3-47008.6" + process $proc$libresoc.v:46980$2746 assign { } { } assign { } { } - assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 - attribute \src "libresoc.v:46334.5-46334.29" + assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46981.5-46981.29" switch \initial - attribute \src "libresoc.v:46334.9-46334.17" + attribute \src "libresoc.v:46981.9-46981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 1'0 + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a + case + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + end case - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 \rp_FAST_fast2_trap0_1 + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 end sync always - update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 + update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] end - attribute \src "libresoc.v:46342.3-46351.6" - process $proc$libresoc.v:46342$2694 + attribute \src "libresoc.v:47009.3-47017.6" + process $proc$libresoc.v:47009$2747 assign { } { } assign { } { } - assign $0\fus_src4_i$90[63:0]$2695 $1\fus_src4_i$90[63:0]$2696 - attribute \src "libresoc.v:46343.5-46343.29" + assign $0\wr_pick_dly$1148$next[0:0]$2748 $1\wr_pick_dly$1148$next[0:0]$2749 + attribute \src "libresoc.v:47010.5-47010.29" switch \initial - attribute \src "libresoc.v:46343.9-46343.17" + attribute \src "libresoc.v:47010.9-47010.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$90[63:0]$2696 \fast_src2__data_o + assign $1\wr_pick_dly$1148$next[0:0]$2749 1'0 case - assign $1\fus_src4_i$90[63:0]$2696 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1148$next[0:0]$2749 \wr_pick$1145 end sync always - update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2695 + update \wr_pick_dly$1148$next $0\wr_pick_dly$1148$next[0:0]$2748 end - attribute \src "libresoc.v:46352.3-46380.6" - process $proc$libresoc.v:46352$2697 + attribute \src "libresoc.v:47018.3-47046.6" + process $proc$libresoc.v:47018$2750 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46353.5-46353.29" + attribute \src "libresoc.v:47019.5-47019.29" switch \initial - attribute \src "libresoc.v:46353.9-46353.17" + attribute \src "libresoc.v:47019.9-47019.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80857,7 +81834,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80873,14 +81850,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] end - attribute \src "libresoc.v:46381.3-46389.6" - process $proc$libresoc.v:46381$2698 + attribute \src "libresoc.v:47047.3-47055.6" + process $proc$libresoc.v:47047$2751 assign { } { } assign { } { } - assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 - attribute \src "libresoc.v:46382.5-46382.29" + assign $0\wr_pick_dly$1222$next[0:0]$2752 $1\wr_pick_dly$1222$next[0:0]$2753 + attribute \src "libresoc.v:47048.5-47048.29" switch \initial - attribute \src "libresoc.v:46382.9-46382.17" + attribute \src "libresoc.v:47048.9-47048.17" case 1'1 case end @@ -80889,54 +81866,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 1'0 - case - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 \rp_SPR_spr1_spr0_0 - end - sync always - update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 - end - attribute \src "libresoc.v:46390.3-46399.6" - process $proc$libresoc.v:46390$2701 - assign { } { } - assign { } { } - assign $0\fus_src2_i$91[63:0]$2702 $1\fus_src2_i$91[63:0]$2703 - attribute \src "libresoc.v:46391.5-46391.29" - switch \initial - attribute \src "libresoc.v:46391.9-46391.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" - switch \dp_SPR_spr1_spr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$91[63:0]$2703 \spr_spr1__data_o + assign $1\wr_pick_dly$1222$next[0:0]$2753 1'0 case - assign $1\fus_src2_i$91[63:0]$2703 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\wr_pick_dly$1222$next[0:0]$2753 \wr_pick$1219 end sync always - update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2702 + update \wr_pick_dly$1222$next $0\wr_pick_dly$1222$next[0:0]$2752 end - attribute \src "libresoc.v:46400.3-46428.6" - process $proc$libresoc.v:46400$2704 + attribute \src "libresoc.v:47056.3-47084.6" + process $proc$libresoc.v:47056$2754 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46401.5-46401.29" + attribute \src "libresoc.v:47057.5-47057.29" switch \initial - attribute \src "libresoc.v:46401.9-46401.17" + attribute \src "libresoc.v:47057.9-47057.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80948,7 +81902,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80964,14 +81918,14 @@ module \core sync always update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] end - attribute \src "libresoc.v:46429.3-46437.6" - process $proc$libresoc.v:46429$2705 + attribute \src "libresoc.v:47085.3-47093.6" + process $proc$libresoc.v:47085$2755 assign { } { } assign { } { } - assign $0\wr_pick_dly$next[0:0]$2706 $1\wr_pick_dly$next[0:0]$2707 - attribute \src "libresoc.v:46430.5-46430.29" + assign $0\wr_pick_dly$1250$next[0:0]$2756 $1\wr_pick_dly$1250$next[0:0]$2757 + attribute \src "libresoc.v:47086.5-47086.29" switch \initial - attribute \src "libresoc.v:46430.9-46430.17" + attribute \src "libresoc.v:47086.9-47086.17" case 1'1 case end @@ -80980,31 +81934,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$next[0:0]$2707 1'0 + assign $1\wr_pick_dly$1250$next[0:0]$2757 1'0 case - assign $1\wr_pick_dly$next[0:0]$2707 \wr_pick + assign $1\wr_pick_dly$1250$next[0:0]$2757 \wr_pick$1247 end sync always - update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2706 + update \wr_pick_dly$1250$next $0\wr_pick_dly$1250$next[0:0]$2756 end - attribute \src "libresoc.v:46438.3-46466.6" - process $proc$libresoc.v:46438$2708 + attribute \src "libresoc.v:47094.3-47122.6" + process $proc$libresoc.v:47094$2758 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46439.5-46439.29" + attribute \src "libresoc.v:47095.5-47095.29" switch \initial - attribute \src "libresoc.v:46439.9-46439.17" + attribute \src "libresoc.v:47095.9-47095.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81016,7 +81970,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81032,14 +81986,14 @@ module \core sync always update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] end - attribute \src "libresoc.v:46467.3-46475.6" - process $proc$libresoc.v:46467$2709 + attribute \src "libresoc.v:47123.3-47131.6" + process $proc$libresoc.v:47123$2759 assign { } { } assign { } { } - assign $0\wr_pick_dly$986$next[0:0]$2710 $1\wr_pick_dly$986$next[0:0]$2711 - attribute \src "libresoc.v:46468.5-46468.29" + assign $0\wr_pick_dly$1270$next[0:0]$2760 $1\wr_pick_dly$1270$next[0:0]$2761 + attribute \src "libresoc.v:47124.5-47124.29" switch \initial - attribute \src "libresoc.v:46468.9-46468.17" + attribute \src "libresoc.v:47124.9-47124.17" case 1'1 case end @@ -81048,21 +82002,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$986$next[0:0]$2711 1'0 + assign $1\wr_pick_dly$1270$next[0:0]$2761 1'0 case - assign $1\wr_pick_dly$986$next[0:0]$2711 \wr_pick$983 + assign $1\wr_pick_dly$1270$next[0:0]$2761 \wr_pick$1267 end sync always - update \wr_pick_dly$986$next $0\wr_pick_dly$986$next[0:0]$2710 + update \wr_pick_dly$1270$next $0\wr_pick_dly$1270$next[0:0]$2760 end - attribute \src "libresoc.v:46476.3-46484.6" - process $proc$libresoc.v:46476$2712 + attribute \src "libresoc.v:47132.3-47140.6" + process $proc$libresoc.v:47132$2762 assign { } { } assign { } { } - assign $0\wr_pick_dly$1005$next[0:0]$2713 $1\wr_pick_dly$1005$next[0:0]$2714 - attribute \src "libresoc.v:46477.5-46477.29" + assign $0\wr_pick_dly$1290$next[0:0]$2763 $1\wr_pick_dly$1290$next[0:0]$2764 + attribute \src "libresoc.v:47133.5-47133.29" switch \initial - attribute \src "libresoc.v:46477.9-46477.17" + attribute \src "libresoc.v:47133.9-47133.17" case 1'1 case end @@ -81071,31 +82025,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1005$next[0:0]$2714 1'0 + assign $1\wr_pick_dly$1290$next[0:0]$2764 1'0 case - assign $1\wr_pick_dly$1005$next[0:0]$2714 \wr_pick$1002 + assign $1\wr_pick_dly$1290$next[0:0]$2764 \wr_pick$1287 end sync always - update \wr_pick_dly$1005$next $0\wr_pick_dly$1005$next[0:0]$2713 + update \wr_pick_dly$1290$next $0\wr_pick_dly$1290$next[0:0]$2763 end - attribute \src "libresoc.v:46485.3-46513.6" - process $proc$libresoc.v:46485$2715 + attribute \src "libresoc.v:47141.3-47169.6" + process $proc$libresoc.v:47141$2765 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46486.5-46486.29" + attribute \src "libresoc.v:47142.5-47142.29" switch \initial - attribute \src "libresoc.v:46486.9-46486.17" + attribute \src "libresoc.v:47142.9-47142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81107,7 +82061,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81123,14 +82077,14 @@ module \core sync always update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] end - attribute \src "libresoc.v:46514.3-46522.6" - process $proc$libresoc.v:46514$2716 + attribute \src "libresoc.v:47170.3-47178.6" + process $proc$libresoc.v:47170$2766 assign { } { } assign { } { } - assign $0\wr_pick_dly$1026$next[0:0]$2717 $1\wr_pick_dly$1026$next[0:0]$2718 - attribute \src "libresoc.v:46515.5-46515.29" + assign $0\wr_pick_dly$1310$next[0:0]$2767 $1\wr_pick_dly$1310$next[0:0]$2768 + attribute \src "libresoc.v:47171.5-47171.29" switch \initial - attribute \src "libresoc.v:46515.9-46515.17" + attribute \src "libresoc.v:47171.9-47171.17" case 1'1 case end @@ -81139,31 +82093,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1026$next[0:0]$2718 1'0 + assign $1\wr_pick_dly$1310$next[0:0]$2768 1'0 case - assign $1\wr_pick_dly$1026$next[0:0]$2718 \wr_pick$1023 + assign $1\wr_pick_dly$1310$next[0:0]$2768 \wr_pick$1307 end sync always - update \wr_pick_dly$1026$next $0\wr_pick_dly$1026$next[0:0]$2717 + update \wr_pick_dly$1310$next $0\wr_pick_dly$1310$next[0:0]$2767 end - attribute \src "libresoc.v:46523.3-46551.6" - process $proc$libresoc.v:46523$2719 + attribute \src "libresoc.v:47179.3-47187.6" + process $proc$libresoc.v:47179$2769 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1330$next[0:0]$2770 $1\wr_pick_dly$1330$next[0:0]$2771 + attribute \src "libresoc.v:47180.5-47180.29" + switch \initial + attribute \src "libresoc.v:47180.9-47180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1330$next[0:0]$2771 1'0 + case + assign $1\wr_pick_dly$1330$next[0:0]$2771 \wr_pick$1327 + end + sync always + update \wr_pick_dly$1330$next $0\wr_pick_dly$1330$next[0:0]$2770 + end + attribute \src "libresoc.v:47188.3-47216.6" + process $proc$libresoc.v:47188$2772 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46524.5-46524.29" + attribute \src "libresoc.v:47189.5-47189.29" switch \initial - attribute \src "libresoc.v:46524.9-46524.17" + attribute \src "libresoc.v:47189.9-47189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81175,7 +82152,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81191,37 +82168,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] end - attribute \src "libresoc.v:46552.3-46560.6" - process $proc$libresoc.v:46552$2720 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1044$next[0:0]$2721 $1\wr_pick_dly$1044$next[0:0]$2722 - attribute \src "libresoc.v:46553.5-46553.29" - switch \initial - attribute \src "libresoc.v:46553.9-46553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1044$next[0:0]$2722 1'0 - case - assign $1\wr_pick_dly$1044$next[0:0]$2722 \wr_pick$1041 - end - sync always - update \wr_pick_dly$1044$next $0\wr_pick_dly$1044$next[0:0]$2721 - end - attribute \src "libresoc.v:46561.3-46569.6" - process $proc$libresoc.v:46561$2723 + attribute \src "libresoc.v:47217.3-47225.6" + process $proc$libresoc.v:47217$2773 assign { } { } assign { } { } - assign $0\wr_pick_dly$1066$next[0:0]$2724 $1\wr_pick_dly$1066$next[0:0]$2725 - attribute \src "libresoc.v:46562.5-46562.29" + assign $0\wr_pick_dly$1350$next[0:0]$2774 $1\wr_pick_dly$1350$next[0:0]$2775 + attribute \src "libresoc.v:47218.5-47218.29" switch \initial - attribute \src "libresoc.v:46562.9-46562.17" + attribute \src "libresoc.v:47218.9-47218.17" case 1'1 case end @@ -81230,31 +82184,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1066$next[0:0]$2725 1'0 + assign $1\wr_pick_dly$1350$next[0:0]$2775 1'0 case - assign $1\wr_pick_dly$1066$next[0:0]$2725 \wr_pick$1063 + assign $1\wr_pick_dly$1350$next[0:0]$2775 \wr_pick$1347 end sync always - update \wr_pick_dly$1066$next $0\wr_pick_dly$1066$next[0:0]$2724 + update \wr_pick_dly$1350$next $0\wr_pick_dly$1350$next[0:0]$2774 end - attribute \src "libresoc.v:46570.3-46598.6" - process $proc$libresoc.v:46570$2726 + attribute \src "libresoc.v:47226.3-47254.6" + process $proc$libresoc.v:47226$2776 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46571.5-46571.29" + attribute \src "libresoc.v:47227.5-47227.29" switch \initial - attribute \src "libresoc.v:46571.9-46571.17" + attribute \src "libresoc.v:47227.9-47227.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81266,7 +82220,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81282,14 +82236,37 @@ module \core sync always update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] end - attribute \src "libresoc.v:46599.3-46607.6" - process $proc$libresoc.v:46599$2727 + attribute \src "libresoc.v:47255.3-47263.6" + process $proc$libresoc.v:47255$2777 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1397$next[0:0]$2778 $1\wr_pick_dly$1397$next[0:0]$2779 + attribute \src "libresoc.v:47256.5-47256.29" + switch \initial + attribute \src "libresoc.v:47256.9-47256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1397$next[0:0]$2779 1'0 + case + assign $1\wr_pick_dly$1397$next[0:0]$2779 \wr_pick$1394 + end + sync always + update \wr_pick_dly$1397$next $0\wr_pick_dly$1397$next[0:0]$2778 + end + attribute \src "libresoc.v:47264.3-47272.6" + process $proc$libresoc.v:47264$2780 assign { } { } assign { } { } - assign $0\wr_pick_dly$1086$next[0:0]$2728 $1\wr_pick_dly$1086$next[0:0]$2729 - attribute \src "libresoc.v:46600.5-46600.29" + assign $0\wr_pick_dly$1413$next[0:0]$2781 $1\wr_pick_dly$1413$next[0:0]$2782 + attribute \src "libresoc.v:47265.5-47265.29" switch \initial - attribute \src "libresoc.v:46600.9-46600.17" + attribute \src "libresoc.v:47265.9-47265.17" case 1'1 case end @@ -81298,31 +82275,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1086$next[0:0]$2729 1'0 + assign $1\wr_pick_dly$1413$next[0:0]$2782 1'0 case - assign $1\wr_pick_dly$1086$next[0:0]$2729 \wr_pick$1083 + assign $1\wr_pick_dly$1413$next[0:0]$2782 \wr_pick$1410 end sync always - update \wr_pick_dly$1086$next $0\wr_pick_dly$1086$next[0:0]$2728 + update \wr_pick_dly$1413$next $0\wr_pick_dly$1413$next[0:0]$2781 end - attribute \src "libresoc.v:46608.3-46636.6" - process $proc$libresoc.v:46608$2730 + attribute \src "libresoc.v:47273.3-47301.6" + process $proc$libresoc.v:47273$2783 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46609.5-46609.29" + attribute \src "libresoc.v:47274.5-47274.29" switch \initial - attribute \src "libresoc.v:46609.9-46609.17" + attribute \src "libresoc.v:47274.9-47274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81334,7 +82311,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81350,37 +82327,14 @@ module \core sync always update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] end - attribute \src "libresoc.v:46637.3-46645.6" - process $proc$libresoc.v:46637$2731 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1106$next[0:0]$2732 $1\wr_pick_dly$1106$next[0:0]$2733 - attribute \src "libresoc.v:46638.5-46638.29" - switch \initial - attribute \src "libresoc.v:46638.9-46638.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1106$next[0:0]$2733 1'0 - case - assign $1\wr_pick_dly$1106$next[0:0]$2733 \wr_pick$1103 - end - sync always - update \wr_pick_dly$1106$next $0\wr_pick_dly$1106$next[0:0]$2732 - end - attribute \src "libresoc.v:46646.3-46654.6" - process $proc$libresoc.v:46646$2734 + attribute \src "libresoc.v:47302.3-47310.6" + process $proc$libresoc.v:47302$2784 assign { } { } assign { } { } - assign $0\wr_pick_dly$1125$next[0:0]$2735 $1\wr_pick_dly$1125$next[0:0]$2736 - attribute \src "libresoc.v:46647.5-46647.29" + assign $0\wr_pick_dly$1429$next[0:0]$2785 $1\wr_pick_dly$1429$next[0:0]$2786 + attribute \src "libresoc.v:47303.5-47303.29" switch \initial - attribute \src "libresoc.v:46647.9-46647.17" + attribute \src "libresoc.v:47303.9-47303.17" case 1'1 case end @@ -81389,31 +82343,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1125$next[0:0]$2736 1'0 + assign $1\wr_pick_dly$1429$next[0:0]$2786 1'0 case - assign $1\wr_pick_dly$1125$next[0:0]$2736 \wr_pick$1122 + assign $1\wr_pick_dly$1429$next[0:0]$2786 \wr_pick$1426 end sync always - update \wr_pick_dly$1125$next $0\wr_pick_dly$1125$next[0:0]$2735 + update \wr_pick_dly$1429$next $0\wr_pick_dly$1429$next[0:0]$2785 end - attribute \src "libresoc.v:46655.3-46683.6" - process $proc$libresoc.v:46655$2737 + attribute \src "libresoc.v:47311.3-47339.6" + process $proc$libresoc.v:47311$2787 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46656.5-46656.29" + attribute \src "libresoc.v:47312.5-47312.29" switch \initial - attribute \src "libresoc.v:46656.9-46656.17" + attribute \src "libresoc.v:47312.9-47312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81425,7 +82379,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81441,14 +82395,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] end - attribute \src "libresoc.v:46684.3-46692.6" - process $proc$libresoc.v:46684$2738 + attribute \src "libresoc.v:47340.3-47348.6" + process $proc$libresoc.v:47340$2788 assign { } { } assign { } { } - assign $0\wr_pick_dly$1143$next[0:0]$2739 $1\wr_pick_dly$1143$next[0:0]$2740 - attribute \src "libresoc.v:46685.5-46685.29" + assign $0\wr_pick_dly$1463$next[0:0]$2789 $1\wr_pick_dly$1463$next[0:0]$2790 + attribute \src "libresoc.v:47341.5-47341.29" switch \initial - attribute \src "libresoc.v:46685.9-46685.17" + attribute \src "libresoc.v:47341.9-47341.17" case 1'1 case end @@ -81457,31 +82411,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1143$next[0:0]$2740 1'0 + assign $1\wr_pick_dly$1463$next[0:0]$2790 1'0 case - assign $1\wr_pick_dly$1143$next[0:0]$2740 \wr_pick$1140 + assign $1\wr_pick_dly$1463$next[0:0]$2790 \wr_pick$1460 end sync always - update \wr_pick_dly$1143$next $0\wr_pick_dly$1143$next[0:0]$2739 + update \wr_pick_dly$1463$next $0\wr_pick_dly$1463$next[0:0]$2789 end - attribute \src "libresoc.v:46693.3-46721.6" - process $proc$libresoc.v:46693$2741 + attribute \src "libresoc.v:47349.3-47377.6" + process $proc$libresoc.v:47349$2791 assign { } { } assign { } { } assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46694.5-46694.29" + attribute \src "libresoc.v:47350.5-47350.29" switch \initial - attribute \src "libresoc.v:46694.9-46694.17" + attribute \src "libresoc.v:47350.9-47350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81493,7 +82447,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81509,14 +82463,14 @@ module \core sync always update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] end - attribute \src "libresoc.v:46722.3-46730.6" - process $proc$libresoc.v:46722$2742 + attribute \src "libresoc.v:47378.3-47386.6" + process $proc$libresoc.v:47378$2792 assign { } { } assign { } { } - assign $0\wr_pick_dly$1217$next[0:0]$2743 $1\wr_pick_dly$1217$next[0:0]$2744 - attribute \src "libresoc.v:46723.5-46723.29" + assign $0\wr_pick_dly$1479$next[0:0]$2793 $1\wr_pick_dly$1479$next[0:0]$2794 + attribute \src "libresoc.v:47379.5-47379.29" switch \initial - attribute \src "libresoc.v:46723.9-46723.17" + attribute \src "libresoc.v:47379.9-47379.17" case 1'1 case end @@ -81525,31 +82479,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1217$next[0:0]$2744 1'0 + assign $1\wr_pick_dly$1479$next[0:0]$2794 1'0 case - assign $1\wr_pick_dly$1217$next[0:0]$2744 \wr_pick$1214 + assign $1\wr_pick_dly$1479$next[0:0]$2794 \wr_pick$1476 end sync always - update \wr_pick_dly$1217$next $0\wr_pick_dly$1217$next[0:0]$2743 + update \wr_pick_dly$1479$next $0\wr_pick_dly$1479$next[0:0]$2793 end - attribute \src "libresoc.v:46731.3-46759.6" - process $proc$libresoc.v:46731$2745 + attribute \src "libresoc.v:47387.3-47395.6" + process $proc$libresoc.v:47387$2795 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1495$next[0:0]$2796 $1\wr_pick_dly$1495$next[0:0]$2797 + attribute \src "libresoc.v:47388.5-47388.29" + switch \initial + attribute \src "libresoc.v:47388.9-47388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1495$next[0:0]$2797 1'0 + case + assign $1\wr_pick_dly$1495$next[0:0]$2797 \wr_pick$1492 + end + sync always + update \wr_pick_dly$1495$next $0\wr_pick_dly$1495$next[0:0]$2796 + end + attribute \src "libresoc.v:47396.3-47424.6" + process $proc$libresoc.v:47396$2798 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46732.5-46732.29" + attribute \src "libresoc.v:47397.5-47397.29" switch \initial - attribute \src "libresoc.v:46732.9-46732.17" + attribute \src "libresoc.v:47397.9-47397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81561,12 +82538,12 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i[3:0] \$223 + assign $3\fus_cu_rdmaskn_i[3:0] \$228 case assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 end @@ -81577,14 +82554,14 @@ module \core sync always update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] end - attribute \src "libresoc.v:46760.3-46768.6" - process $proc$libresoc.v:46760$2746 + attribute \src "libresoc.v:47425.3-47433.6" + process $proc$libresoc.v:47425$2799 assign { } { } assign { } { } - assign $0\wr_pick_dly$1245$next[0:0]$2747 $1\wr_pick_dly$1245$next[0:0]$2748 - attribute \src "libresoc.v:46761.5-46761.29" + assign $0\wr_pick_dly$1511$next[0:0]$2800 $1\wr_pick_dly$1511$next[0:0]$2801 + attribute \src "libresoc.v:47426.5-47426.29" switch \initial - attribute \src "libresoc.v:46761.9-46761.17" + attribute \src "libresoc.v:47426.9-47426.17" case 1'1 case end @@ -81593,31 +82570,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1245$next[0:0]$2748 1'0 + assign $1\wr_pick_dly$1511$next[0:0]$2801 1'0 case - assign $1\wr_pick_dly$1245$next[0:0]$2748 \wr_pick$1242 + assign $1\wr_pick_dly$1511$next[0:0]$2801 \wr_pick$1508 end sync always - update \wr_pick_dly$1245$next $0\wr_pick_dly$1245$next[0:0]$2747 + update \wr_pick_dly$1511$next $0\wr_pick_dly$1511$next[0:0]$2800 end - attribute \src "libresoc.v:46769.3-46797.6" - process $proc$libresoc.v:46769$2749 + attribute \src "libresoc.v:47434.3-47462.6" + process $proc$libresoc.v:47434$2802 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:46770.5-46770.29" + attribute \src "libresoc.v:47435.5-47435.29" switch \initial - attribute \src "libresoc.v:46770.9-46770.17" + attribute \src "libresoc.v:47435.9-47435.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81629,7 +82606,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81645,14 +82622,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] end - attribute \src "libresoc.v:46798.3-46806.6" - process $proc$libresoc.v:46798$2750 + attribute \src "libresoc.v:47463.3-47471.6" + process $proc$libresoc.v:47463$2803 assign { } { } assign { } { } - assign $0\wr_pick_dly$1265$next[0:0]$2751 $1\wr_pick_dly$1265$next[0:0]$2752 - attribute \src "libresoc.v:46799.5-46799.29" + assign $0\wr_pick_dly$1547$next[0:0]$2804 $1\wr_pick_dly$1547$next[0:0]$2805 + attribute \src "libresoc.v:47464.5-47464.29" switch \initial - attribute \src "libresoc.v:46799.9-46799.17" + attribute \src "libresoc.v:47464.9-47464.17" case 1'1 case end @@ -81661,21 +82638,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1265$next[0:0]$2752 1'0 + assign $1\wr_pick_dly$1547$next[0:0]$2805 1'0 case - assign $1\wr_pick_dly$1265$next[0:0]$2752 \wr_pick$1262 + assign $1\wr_pick_dly$1547$next[0:0]$2805 \wr_pick$1544 end sync always - update \wr_pick_dly$1265$next $0\wr_pick_dly$1265$next[0:0]$2751 + update \wr_pick_dly$1547$next $0\wr_pick_dly$1547$next[0:0]$2804 end - attribute \src "libresoc.v:46807.3-46815.6" - process $proc$libresoc.v:46807$2753 + attribute \src "libresoc.v:47472.3-47480.6" + process $proc$libresoc.v:47472$2806 assign { } { } assign { } { } - assign $0\wr_pick_dly$1285$next[0:0]$2754 $1\wr_pick_dly$1285$next[0:0]$2755 - attribute \src "libresoc.v:46808.5-46808.29" + assign $0\wr_pick_dly$1563$next[0:0]$2807 $1\wr_pick_dly$1563$next[0:0]$2808 + attribute \src "libresoc.v:47473.5-47473.29" switch \initial - attribute \src "libresoc.v:46808.9-46808.17" + attribute \src "libresoc.v:47473.9-47473.17" case 1'1 case end @@ -81684,66 +82661,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1285$next[0:0]$2755 1'0 + assign $1\wr_pick_dly$1563$next[0:0]$2808 1'0 case - assign $1\wr_pick_dly$1285$next[0:0]$2755 \wr_pick$1282 + assign $1\wr_pick_dly$1563$next[0:0]$2808 \wr_pick$1560 end sync always - update \wr_pick_dly$1285$next $0\wr_pick_dly$1285$next[0:0]$2754 + update \wr_pick_dly$1563$next $0\wr_pick_dly$1563$next[0:0]$2807 end - attribute \src "libresoc.v:46816.3-46844.6" - process $proc$libresoc.v:46816$2756 + attribute \src "libresoc.v:47481.3-47509.6" + process $proc$libresoc.v:47481$2809 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_cr0__fn_unit[12:0] $1\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46817.5-46817.29" + assign $0\fus_oper_i_alu_cr0__fn_unit[13:0] $1\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "libresoc.v:47482.5-47482.29" switch \initial - attribute \src "libresoc.v:46817.9-46817.17" + attribute \src "libresoc.v:47482.9-47482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_cr0__fn_unit[12:0] $2\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] $2\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_cr0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_cr0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_cr0__fn_unit[12:0] $3\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] $3\fus_oper_i_alu_cr0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_cr0__fn_unit[12:0] \dec_CR_CR__fn_unit + assign $3\fus_oper_i_alu_cr0__fn_unit[13:0] \dec_CR_CR__fn_unit case - assign $3\fus_oper_i_alu_cr0__fn_unit[12:0] 13'0000000000000 + assign $3\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_cr0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[12:0] + update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[13:0] end - attribute \src "libresoc.v:46845.3-46853.6" - process $proc$libresoc.v:46845$2757 + attribute \src "libresoc.v:47510.3-47518.6" + process $proc$libresoc.v:47510$2810 assign { } { } assign { } { } - assign $0\wr_pick_dly$1305$next[0:0]$2758 $1\wr_pick_dly$1305$next[0:0]$2759 - attribute \src "libresoc.v:46846.5-46846.29" + assign $0\wr_pick_dly$1579$next[0:0]$2811 $1\wr_pick_dly$1579$next[0:0]$2812 + attribute \src "libresoc.v:47511.5-47511.29" switch \initial - attribute \src "libresoc.v:46846.9-46846.17" + attribute \src "libresoc.v:47511.9-47511.17" case 1'1 case end @@ -81752,21 +82729,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1305$next[0:0]$2759 1'0 + assign $1\wr_pick_dly$1579$next[0:0]$2812 1'0 case - assign $1\wr_pick_dly$1305$next[0:0]$2759 \wr_pick$1302 + assign $1\wr_pick_dly$1579$next[0:0]$2812 \wr_pick$1576 end sync always - update \wr_pick_dly$1305$next $0\wr_pick_dly$1305$next[0:0]$2758 + update \wr_pick_dly$1579$next $0\wr_pick_dly$1579$next[0:0]$2811 end - attribute \src "libresoc.v:46854.3-46862.6" - process $proc$libresoc.v:46854$2760 + attribute \src "libresoc.v:47519.3-47527.6" + process $proc$libresoc.v:47519$2813 assign { } { } assign { } { } - assign $0\wr_pick_dly$1325$next[0:0]$2761 $1\wr_pick_dly$1325$next[0:0]$2762 - attribute \src "libresoc.v:46855.5-46855.29" + assign $0\wr_pick_dly$1595$next[0:0]$2814 $1\wr_pick_dly$1595$next[0:0]$2815 + attribute \src "libresoc.v:47520.5-47520.29" switch \initial - attribute \src "libresoc.v:46855.9-46855.17" + attribute \src "libresoc.v:47520.9-47520.17" case 1'1 case end @@ -81775,31 +82752,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1325$next[0:0]$2762 1'0 + assign $1\wr_pick_dly$1595$next[0:0]$2815 1'0 case - assign $1\wr_pick_dly$1325$next[0:0]$2762 \wr_pick$1322 + assign $1\wr_pick_dly$1595$next[0:0]$2815 \wr_pick$1592 end sync always - update \wr_pick_dly$1325$next $0\wr_pick_dly$1325$next[0:0]$2761 + update \wr_pick_dly$1595$next $0\wr_pick_dly$1595$next[0:0]$2814 end - attribute \src "libresoc.v:46863.3-46891.6" - process $proc$libresoc.v:46863$2763 + attribute \src "libresoc.v:47528.3-47556.6" + process $proc$libresoc.v:47528$2816 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46864.5-46864.29" + attribute \src "libresoc.v:47529.5-47529.29" switch \initial - attribute \src "libresoc.v:46864.9-46864.17" + attribute \src "libresoc.v:47529.9-47529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81811,7 +82788,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81827,14 +82804,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] end - attribute \src "libresoc.v:46892.3-46900.6" - process $proc$libresoc.v:46892$2764 + attribute \src "libresoc.v:47557.3-47565.6" + process $proc$libresoc.v:47557$2817 assign { } { } assign { } { } - assign $0\wr_pick_dly$1345$next[0:0]$2765 $1\wr_pick_dly$1345$next[0:0]$2766 - attribute \src "libresoc.v:46893.5-46893.29" + assign $0\wr_pick_dly$1637$next[0:0]$2818 $1\wr_pick_dly$1637$next[0:0]$2819 + attribute \src "libresoc.v:47558.5-47558.29" switch \initial - attribute \src "libresoc.v:46893.9-46893.17" + attribute \src "libresoc.v:47558.9-47558.17" case 1'1 case end @@ -81843,66 +82820,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1345$next[0:0]$2766 1'0 + assign $1\wr_pick_dly$1637$next[0:0]$2819 1'0 case - assign $1\wr_pick_dly$1345$next[0:0]$2766 \wr_pick$1342 + assign $1\wr_pick_dly$1637$next[0:0]$2819 \wr_pick$1634 end sync always - update \wr_pick_dly$1345$next $0\wr_pick_dly$1345$next[0:0]$2765 + update \wr_pick_dly$1637$next $0\wr_pick_dly$1637$next[0:0]$2818 end - attribute \src "libresoc.v:46901.3-46929.6" - process $proc$libresoc.v:46901$2767 + attribute \src "libresoc.v:47566.3-47594.6" + process $proc$libresoc.v:47566$2820 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$13[0:0]$2768 $1\fus_cu_issue_i$13[0:0]$2769 - attribute \src "libresoc.v:46902.5-46902.29" + assign $0\fus_cu_issue_i$13[0:0]$2821 $1\fus_cu_issue_i$13[0:0]$2822 + attribute \src "libresoc.v:47567.5-47567.29" switch \initial - attribute \src "libresoc.v:46902.9-46902.17" + attribute \src "libresoc.v:47567.9-47567.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$13[0:0]$2769 $2\fus_cu_issue_i$13[0:0]$2770 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_issue_i$13[0:0]$2822 $2\fus_cu_issue_i$13[0:0]$2823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$13[0:0]$2770 1'0 + assign $2\fus_cu_issue_i$13[0:0]$2823 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$13[0:0]$2770 1'0 + assign $2\fus_cu_issue_i$13[0:0]$2823 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$13[0:0]$2770 $3\fus_cu_issue_i$13[0:0]$2771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_issue_i$13[0:0]$2823 $3\fus_cu_issue_i$13[0:0]$2824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$13[0:0]$2771 \issue_i + assign $3\fus_cu_issue_i$13[0:0]$2824 \issue_i case - assign $3\fus_cu_issue_i$13[0:0]$2771 1'0 + assign $3\fus_cu_issue_i$13[0:0]$2824 1'0 end end case - assign $1\fus_cu_issue_i$13[0:0]$2769 1'0 + assign $1\fus_cu_issue_i$13[0:0]$2822 1'0 end sync always - update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2768 + update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2821 end - attribute \src "libresoc.v:46930.3-46938.6" - process $proc$libresoc.v:46930$2772 + attribute \src "libresoc.v:47595.3-47603.6" + process $proc$libresoc.v:47595$2825 assign { } { } assign { } { } - assign $0\wr_pick_dly$1392$next[0:0]$2773 $1\wr_pick_dly$1392$next[0:0]$2774 - attribute \src "libresoc.v:46931.5-46931.29" + assign $0\wr_pick_dly$1656$next[0:0]$2826 $1\wr_pick_dly$1656$next[0:0]$2827 + attribute \src "libresoc.v:47596.5-47596.29" switch \initial - attribute \src "libresoc.v:46931.9-46931.17" + attribute \src "libresoc.v:47596.9-47596.17" case 1'1 case end @@ -81911,66 +82888,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1392$next[0:0]$2774 1'0 + assign $1\wr_pick_dly$1656$next[0:0]$2827 1'0 case - assign $1\wr_pick_dly$1392$next[0:0]$2774 \wr_pick$1389 + assign $1\wr_pick_dly$1656$next[0:0]$2827 \wr_pick$1653 end sync always - update \wr_pick_dly$1392$next $0\wr_pick_dly$1392$next[0:0]$2773 + update \wr_pick_dly$1656$next $0\wr_pick_dly$1656$next[0:0]$2826 end - attribute \src "libresoc.v:46939.3-46967.6" - process $proc$libresoc.v:46939$2775 + attribute \src "libresoc.v:47604.3-47632.6" + process $proc$libresoc.v:47604$2828 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$15[5:0]$2776 $1\fus_cu_rdmaskn_i$15[5:0]$2777 - attribute \src "libresoc.v:46940.5-46940.29" + assign $0\fus_cu_rdmaskn_i$15[5:0]$2829 $1\fus_cu_rdmaskn_i$15[5:0]$2830 + attribute \src "libresoc.v:47605.5-47605.29" switch \initial - attribute \src "libresoc.v:46940.9-46940.17" + attribute \src "libresoc.v:47605.9-47605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$15[5:0]$2777 $2\fus_cu_rdmaskn_i$15[5:0]$2778 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 $2\fus_cu_rdmaskn_i$15[5:0]$2831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$15[5:0]$2778 6'000000 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$15[5:0]$2778 6'000000 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 6'000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$15[5:0]$2778 $3\fus_cu_rdmaskn_i$15[5:0]$2779 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_rdmaskn_i$15[5:0]$2831 $3\fus_cu_rdmaskn_i$15[5:0]$2832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$15[5:0]$2779 \$245 + assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 \$250 case - assign $3\fus_cu_rdmaskn_i$15[5:0]$2779 6'000000 + assign $3\fus_cu_rdmaskn_i$15[5:0]$2832 6'000000 end end case - assign $1\fus_cu_rdmaskn_i$15[5:0]$2777 6'000000 + assign $1\fus_cu_rdmaskn_i$15[5:0]$2830 6'000000 end sync always - update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2776 + update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2829 end - attribute \src "libresoc.v:46968.3-46976.6" - process $proc$libresoc.v:46968$2780 + attribute \src "libresoc.v:47633.3-47641.6" + process $proc$libresoc.v:47633$2833 assign { } { } assign { } { } - assign $0\wr_pick_dly$1408$next[0:0]$2781 $1\wr_pick_dly$1408$next[0:0]$2782 - attribute \src "libresoc.v:46969.5-46969.29" + assign $0\wr_pick_dly$1672$next[0:0]$2834 $1\wr_pick_dly$1672$next[0:0]$2835 + attribute \src "libresoc.v:47634.5-47634.29" switch \initial - attribute \src "libresoc.v:46969.9-46969.17" + attribute \src "libresoc.v:47634.9-47634.17" case 1'1 case end @@ -81979,21 +82956,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1408$next[0:0]$2782 1'0 + assign $1\wr_pick_dly$1672$next[0:0]$2835 1'0 case - assign $1\wr_pick_dly$1408$next[0:0]$2782 \wr_pick$1405 + assign $1\wr_pick_dly$1672$next[0:0]$2835 \wr_pick$1669 end sync always - update \wr_pick_dly$1408$next $0\wr_pick_dly$1408$next[0:0]$2781 + update \wr_pick_dly$1672$next $0\wr_pick_dly$1672$next[0:0]$2834 end - attribute \src "libresoc.v:46977.3-46985.6" - process $proc$libresoc.v:46977$2783 + attribute \src "libresoc.v:47642.3-47650.6" + process $proc$libresoc.v:47642$2836 assign { } { } assign { } { } - assign $0\wr_pick_dly$1424$next[0:0]$2784 $1\wr_pick_dly$1424$next[0:0]$2785 - attribute \src "libresoc.v:46978.5-46978.29" + assign $0\wr_pick_dly$1688$next[0:0]$2837 $1\wr_pick_dly$1688$next[0:0]$2838 + attribute \src "libresoc.v:47643.5-47643.29" switch \initial - attribute \src "libresoc.v:46978.9-46978.17" + attribute \src "libresoc.v:47643.9-47643.17" case 1'1 case end @@ -82002,31 +82979,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1424$next[0:0]$2785 1'0 + assign $1\wr_pick_dly$1688$next[0:0]$2838 1'0 case - assign $1\wr_pick_dly$1424$next[0:0]$2785 \wr_pick$1421 + assign $1\wr_pick_dly$1688$next[0:0]$2838 \wr_pick$1685 end sync always - update \wr_pick_dly$1424$next $0\wr_pick_dly$1424$next[0:0]$2784 + update \wr_pick_dly$1688$next $0\wr_pick_dly$1688$next[0:0]$2837 end - attribute \src "libresoc.v:46986.3-47014.6" - process $proc$libresoc.v:46986$2786 + attribute \src "libresoc.v:47651.3-47679.6" + process $proc$libresoc.v:47651$2839 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46987.5-46987.29" + attribute \src "libresoc.v:47652.5-47652.29" switch \initial - attribute \src "libresoc.v:46987.9-46987.17" + attribute \src "libresoc.v:47652.9-47652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82038,7 +83015,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82054,14 +83031,14 @@ module \core sync always update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] end - attribute \src "libresoc.v:47015.3-47023.6" - process $proc$libresoc.v:47015$2787 + attribute \src "libresoc.v:47680.3-47688.6" + process $proc$libresoc.v:47680$2840 assign { } { } assign { } { } - assign $0\wr_pick_dly$1458$next[0:0]$2788 $1\wr_pick_dly$1458$next[0:0]$2789 - attribute \src "libresoc.v:47016.5-47016.29" + assign $0\wr_pick_dly$1704$next[0:0]$2841 $1\wr_pick_dly$1704$next[0:0]$2842 + attribute \src "libresoc.v:47681.5-47681.29" switch \initial - attribute \src "libresoc.v:47016.9-47016.17" + attribute \src "libresoc.v:47681.9-47681.17" case 1'1 case end @@ -82070,31 +83047,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1458$next[0:0]$2789 1'0 + assign $1\wr_pick_dly$1704$next[0:0]$2842 1'0 case - assign $1\wr_pick_dly$1458$next[0:0]$2789 \wr_pick$1455 + assign $1\wr_pick_dly$1704$next[0:0]$2842 \wr_pick$1701 end sync always - update \wr_pick_dly$1458$next $0\wr_pick_dly$1458$next[0:0]$2788 + update \wr_pick_dly$1704$next $0\wr_pick_dly$1704$next[0:0]$2841 end - attribute \src "libresoc.v:47024.3-47052.6" - process $proc$libresoc.v:47024$2790 + attribute \src "libresoc.v:47689.3-47717.6" + process $proc$libresoc.v:47689$2843 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47025.5-47025.29" + attribute \src "libresoc.v:47690.5-47690.29" switch \initial - attribute \src "libresoc.v:47025.9-47025.17" + attribute \src "libresoc.v:47690.9-47690.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82106,7 +83083,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82122,14 +83099,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] end - attribute \src "libresoc.v:47053.3-47061.6" - process $proc$libresoc.v:47053$2791 + attribute \src "libresoc.v:47718.3-47726.6" + process $proc$libresoc.v:47718$2844 assign { } { } assign { } { } - assign $0\wr_pick_dly$1474$next[0:0]$2792 $1\wr_pick_dly$1474$next[0:0]$2793 - attribute \src "libresoc.v:47054.5-47054.29" + assign $0\wr_pick_dly$1748$next[0:0]$2845 $1\wr_pick_dly$1748$next[0:0]$2846 + attribute \src "libresoc.v:47719.5-47719.29" switch \initial - attribute \src "libresoc.v:47054.9-47054.17" + attribute \src "libresoc.v:47719.9-47719.17" case 1'1 case end @@ -82138,21 +83115,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1474$next[0:0]$2793 1'0 + assign $1\wr_pick_dly$1748$next[0:0]$2846 1'0 case - assign $1\wr_pick_dly$1474$next[0:0]$2793 \wr_pick$1471 + assign $1\wr_pick_dly$1748$next[0:0]$2846 \wr_pick$1745 end sync always - update \wr_pick_dly$1474$next $0\wr_pick_dly$1474$next[0:0]$2792 + update \wr_pick_dly$1748$next $0\wr_pick_dly$1748$next[0:0]$2845 end - attribute \src "libresoc.v:47062.3-47070.6" - process $proc$libresoc.v:47062$2794 + attribute \src "libresoc.v:47727.3-47735.6" + process $proc$libresoc.v:47727$2847 assign { } { } assign { } { } - assign $0\wr_pick_dly$1490$next[0:0]$2795 $1\wr_pick_dly$1490$next[0:0]$2796 - attribute \src "libresoc.v:47063.5-47063.29" + assign $0\wr_pick_dly$1764$next[0:0]$2848 $1\wr_pick_dly$1764$next[0:0]$2849 + attribute \src "libresoc.v:47728.5-47728.29" switch \initial - attribute \src "libresoc.v:47063.9-47063.17" + attribute \src "libresoc.v:47728.9-47728.17" case 1'1 case end @@ -82161,66 +83138,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1490$next[0:0]$2796 1'0 + assign $1\wr_pick_dly$1764$next[0:0]$2849 1'0 case - assign $1\wr_pick_dly$1490$next[0:0]$2796 \wr_pick$1487 + assign $1\wr_pick_dly$1764$next[0:0]$2849 \wr_pick$1761 end sync always - update \wr_pick_dly$1490$next $0\wr_pick_dly$1490$next[0:0]$2795 + update \wr_pick_dly$1764$next $0\wr_pick_dly$1764$next[0:0]$2848 end - attribute \src "libresoc.v:47071.3-47099.6" - process $proc$libresoc.v:47071$2797 + attribute \src "libresoc.v:47736.3-47764.6" + process $proc$libresoc.v:47736$2850 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_branch0__fn_unit[12:0] $1\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47072.5-47072.29" + assign $0\fus_oper_i_alu_branch0__fn_unit[13:0] $1\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "libresoc.v:47737.5-47737.29" switch \initial - attribute \src "libresoc.v:47072.9-47072.17" + attribute \src "libresoc.v:47737.9-47737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_branch0__fn_unit[12:0] $2\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] $2\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_branch0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_branch0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_branch0__fn_unit[12:0] $3\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] $3\fus_oper_i_alu_branch0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__fn_unit[12:0] \dec_BRANCH_BRANCH__fn_unit + assign $3\fus_oper_i_alu_branch0__fn_unit[13:0] \dec_BRANCH_BRANCH__fn_unit case - assign $3\fus_oper_i_alu_branch0__fn_unit[12:0] 13'0000000000000 + assign $3\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_branch0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[12:0] + update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[13:0] end - attribute \src "libresoc.v:47100.3-47108.6" - process $proc$libresoc.v:47100$2798 + attribute \src "libresoc.v:47765.3-47773.6" + process $proc$libresoc.v:47765$2851 assign { } { } assign { } { } - assign $0\wr_pick_dly$1506$next[0:0]$2799 $1\wr_pick_dly$1506$next[0:0]$2800 - attribute \src "libresoc.v:47101.5-47101.29" + assign $0\wr_pick_dly$1788$next[0:0]$2852 $1\wr_pick_dly$1788$next[0:0]$2853 + attribute \src "libresoc.v:47766.5-47766.29" switch \initial - attribute \src "libresoc.v:47101.9-47101.17" + attribute \src "libresoc.v:47766.9-47766.17" case 1'1 case end @@ -82229,31 +83206,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1506$next[0:0]$2800 1'0 + assign $1\wr_pick_dly$1788$next[0:0]$2853 1'0 case - assign $1\wr_pick_dly$1506$next[0:0]$2800 \wr_pick$1503 + assign $1\wr_pick_dly$1788$next[0:0]$2853 \wr_pick$1785 end sync always - update \wr_pick_dly$1506$next $0\wr_pick_dly$1506$next[0:0]$2799 + update \wr_pick_dly$1788$next $0\wr_pick_dly$1788$next[0:0]$2852 end - attribute \src "libresoc.v:47109.3-47137.6" - process $proc$libresoc.v:47109$2801 + attribute \src "libresoc.v:47774.3-47802.6" + process $proc$libresoc.v:47774$2854 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47110.5-47110.29" + attribute \src "libresoc.v:47775.5-47775.29" switch \initial - attribute \src "libresoc.v:47110.9-47110.17" + attribute \src "libresoc.v:47775.9-47775.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82265,7 +83242,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82281,37 +83258,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] end - attribute \src "libresoc.v:47138.3-47146.6" - process $proc$libresoc.v:47138$2802 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1542$next[0:0]$2803 $1\wr_pick_dly$1542$next[0:0]$2804 - attribute \src "libresoc.v:47139.5-47139.29" - switch \initial - attribute \src "libresoc.v:47139.9-47139.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1542$next[0:0]$2804 1'0 - case - assign $1\wr_pick_dly$1542$next[0:0]$2804 \wr_pick$1539 - end - sync always - update \wr_pick_dly$1542$next $0\wr_pick_dly$1542$next[0:0]$2803 - end - attribute \src "libresoc.v:47147.3-47155.6" - process $proc$libresoc.v:47147$2805 + attribute \src "libresoc.v:47803.3-47811.6" + process $proc$libresoc.v:47803$2855 assign { } { } assign { } { } - assign $0\wr_pick_dly$1558$next[0:0]$2806 $1\wr_pick_dly$1558$next[0:0]$2807 - attribute \src "libresoc.v:47148.5-47148.29" + assign $0\wr_pick_dly$1808$next[0:0]$2856 $1\wr_pick_dly$1808$next[0:0]$2857 + attribute \src "libresoc.v:47804.5-47804.29" switch \initial - attribute \src "libresoc.v:47148.9-47148.17" + attribute \src "libresoc.v:47804.9-47804.17" case 1'1 case end @@ -82320,28 +83274,28 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1558$next[0:0]$2807 1'0 + assign $1\wr_pick_dly$1808$next[0:0]$2857 1'0 case - assign $1\wr_pick_dly$1558$next[0:0]$2807 \wr_pick$1555 + assign $1\wr_pick_dly$1808$next[0:0]$2857 \wr_pick$1805 end sync always - update \wr_pick_dly$1558$next $0\wr_pick_dly$1558$next[0:0]$2806 + update \wr_pick_dly$1808$next $0\wr_pick_dly$1808$next[0:0]$2856 end - attribute \src "libresoc.v:47156.3-47185.6" - process $proc$libresoc.v:47156$2808 + attribute \src "libresoc.v:47812.3-47841.6" + process $proc$libresoc.v:47812$2858 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47157.5-47157.29" + attribute \src "libresoc.v:47813.5-47813.29" switch \initial - attribute \src "libresoc.v:47157.9-47157.17" + attribute \src "libresoc.v:47813.9-47813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82349,7 +83303,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82365,7 +83319,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82385,952 +83339,699 @@ module \core update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] end - attribute \src "libresoc.v:47186.3-47194.6" - process $proc$libresoc.v:47186$2809 + attribute \src "libresoc.v:47842.3-47870.6" + process $proc$libresoc.v:47842$2859 assign { } { } assign { } { } - assign $0\wr_pick_dly$1574$next[0:0]$2810 $1\wr_pick_dly$1574$next[0:0]$2811 - attribute \src "libresoc.v:47187.5-47187.29" - switch \initial - attribute \src "libresoc.v:47187.9-47187.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1574$next[0:0]$2811 1'0 - case - assign $1\wr_pick_dly$1574$next[0:0]$2811 \wr_pick$1571 - end - sync always - update \wr_pick_dly$1574$next $0\wr_pick_dly$1574$next[0:0]$2810 - end - attribute \src "libresoc.v:47195.3-47203.6" - process $proc$libresoc.v:47195$2812 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1590$next[0:0]$2813 $1\wr_pick_dly$1590$next[0:0]$2814 - attribute \src "libresoc.v:47196.5-47196.29" - switch \initial - attribute \src "libresoc.v:47196.9-47196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1590$next[0:0]$2814 1'0 - case - assign $1\wr_pick_dly$1590$next[0:0]$2814 \wr_pick$1587 - end - sync always - update \wr_pick_dly$1590$next $0\wr_pick_dly$1590$next[0:0]$2813 - end - attribute \src "libresoc.v:47204.3-47212.6" - process $proc$libresoc.v:47204$2815 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1632$next[0:0]$2816 $1\wr_pick_dly$1632$next[0:0]$2817 - attribute \src "libresoc.v:47205.5-47205.29" + assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:47843.5-47843.29" switch \initial - attribute \src "libresoc.v:47205.9-47205.17" + attribute \src "libresoc.v:47843.9-47843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1632$next[0:0]$2817 1'0 + assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH__lk + case + assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + end case - assign $1\wr_pick_dly$1632$next[0:0]$2817 \wr_pick$1629 + assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 end sync always - update \wr_pick_dly$1632$next $0\wr_pick_dly$1632$next[0:0]$2816 + update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] end - attribute \src "libresoc.v:47213.3-47241.6" - process $proc$libresoc.v:47213$2818 + attribute \src "libresoc.v:47871.3-47899.6" + process $proc$libresoc.v:47871$2860 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47214.5-47214.29" + assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47872.5-47872.29" switch \initial - attribute \src "libresoc.v:47214.9-47214.17" + attribute \src "libresoc.v:47872.9-47872.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH__lk + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH__is_32bit case - assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 end end case - assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 end sync always - update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] + update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] end - attribute \src "libresoc.v:47242.3-47250.6" - process $proc$libresoc.v:47242$2819 + attribute \src "libresoc.v:47900.3-47928.6" + process $proc$libresoc.v:47900$2861 assign { } { } assign { } { } - assign $0\wr_pick_dly$1651$next[0:0]$2820 $1\wr_pick_dly$1651$next[0:0]$2821 - attribute \src "libresoc.v:47243.5-47243.29" + assign $0\fus_cu_issue_i$16[0:0]$2862 $1\fus_cu_issue_i$16[0:0]$2863 + attribute \src "libresoc.v:47901.5-47901.29" switch \initial - attribute \src "libresoc.v:47243.9-47243.17" + attribute \src "libresoc.v:47901.9-47901.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1651$next[0:0]$2821 1'0 + assign $1\fus_cu_issue_i$16[0:0]$2863 $2\fus_cu_issue_i$16[0:0]$2864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$16[0:0]$2864 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$16[0:0]$2864 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$16[0:0]$2864 $3\fus_cu_issue_i$16[0:0]$2865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$16[0:0]$2865 \issue_i + case + assign $3\fus_cu_issue_i$16[0:0]$2865 1'0 + end + end case - assign $1\wr_pick_dly$1651$next[0:0]$2821 \wr_pick$1648 + assign $1\fus_cu_issue_i$16[0:0]$2863 1'0 end sync always - update \wr_pick_dly$1651$next $0\wr_pick_dly$1651$next[0:0]$2820 + update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2862 end - attribute \src "libresoc.v:47251.3-47279.6" - process $proc$libresoc.v:47251$2822 + attribute \src "libresoc.v:47929.3-47957.6" + process $proc$libresoc.v:47929$2866 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47252.5-47252.29" + assign $0\fus_cu_rdmaskn_i$18[2:0]$2867 $1\fus_cu_rdmaskn_i$18[2:0]$2868 + attribute \src "libresoc.v:47930.5-47930.29" switch \initial - attribute \src "libresoc.v:47252.9-47252.17" + attribute \src "libresoc.v:47930.9-47930.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 $2\fus_cu_rdmaskn_i$18[2:0]$2869 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 $3\fus_cu_rdmaskn_i$18[2:0]$2870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH__is_32bit + assign $3\fus_cu_rdmaskn_i$18[2:0]$2870 \$252 case - assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + assign $3\fus_cu_rdmaskn_i$18[2:0]$2870 3'000 end end case - assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 3'000 end sync always - update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] + update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2867 end - attribute \src "libresoc.v:47280.3-47288.6" - process $proc$libresoc.v:47280$2823 + attribute \src "libresoc.v:47958.3-47986.6" + process $proc$libresoc.v:47958$2871 assign { } { } assign { } { } - assign $0\wr_pick_dly$1667$next[0:0]$2824 $1\wr_pick_dly$1667$next[0:0]$2825 - attribute \src "libresoc.v:47281.5-47281.29" + assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47959.5-47959.29" switch \initial - attribute \src "libresoc.v:47281.9-47281.17" + attribute \src "libresoc.v:47959.9-47959.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1667$next[0:0]$2825 1'0 + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type + case + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + end case - assign $1\wr_pick_dly$1667$next[0:0]$2825 \wr_pick$1664 + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 end sync always - update \wr_pick_dly$1667$next $0\wr_pick_dly$1667$next[0:0]$2824 + update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] end - attribute \src "libresoc.v:47289.3-47297.6" - process $proc$libresoc.v:47289$2826 + attribute \src "libresoc.v:47987.3-48015.6" + process $proc$libresoc.v:47987$2872 assign { } { } assign { } { } - assign $0\wr_pick_dly$1683$next[0:0]$2827 $1\wr_pick_dly$1683$next[0:0]$2828 - attribute \src "libresoc.v:47290.5-47290.29" + assign $0\fus_oper_i_alu_trap0__fn_unit[13:0] $1\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "libresoc.v:47988.5-47988.29" switch \initial - attribute \src "libresoc.v:47290.9-47290.17" + attribute \src "libresoc.v:47988.9-47988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1683$next[0:0]$2828 1'0 + assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] $2\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] $3\fus_oper_i_alu_trap0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__fn_unit[13:0] \core_core_fn_unit + case + assign $3\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 + end + end case - assign $1\wr_pick_dly$1683$next[0:0]$2828 \wr_pick$1680 + assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 end sync always - update \wr_pick_dly$1683$next $0\wr_pick_dly$1683$next[0:0]$2827 + update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[13:0] end - attribute \src "libresoc.v:47298.3-47326.6" - process $proc$libresoc.v:47298$2829 + attribute \src "libresoc.v:48016.3-48044.6" + process $proc$libresoc.v:48016$2873 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$16[0:0]$2830 $1\fus_cu_issue_i$16[0:0]$2831 - attribute \src "libresoc.v:47299.5-47299.29" + assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:48017.5-48017.29" switch \initial - attribute \src "libresoc.v:47299.9-47299.17" + attribute \src "libresoc.v:48017.9-48017.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$16[0:0]$2831 $2\fus_cu_issue_i$16[0:0]$2832 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$16[0:0]$2832 1'0 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$16[0:0]$2832 1'0 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$16[0:0]$2832 $3\fus_cu_issue_i$16[0:0]$2833 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [2] + assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$16[0:0]$2833 \issue_i + assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn case - assign $3\fus_cu_issue_i$16[0:0]$2833 1'0 + assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 end end case - assign $1\fus_cu_issue_i$16[0:0]$2831 1'0 + assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 end sync always - update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2830 + update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] end - attribute \src "libresoc.v:47327.3-47335.6" - process $proc$libresoc.v:47327$2834 + attribute \src "libresoc.v:48045.3-48073.6" + process $proc$libresoc.v:48045$2874 assign { } { } assign { } { } - assign $0\wr_pick_dly$1699$next[0:0]$2835 $1\wr_pick_dly$1699$next[0:0]$2836 - attribute \src "libresoc.v:47328.5-47328.29" + assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:48046.5-48046.29" switch \initial - attribute \src "libresoc.v:47328.9-47328.17" + attribute \src "libresoc.v:48046.9-48046.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1699$next[0:0]$2836 1'0 + assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr + case + assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end case - assign $1\wr_pick_dly$1699$next[0:0]$2836 \wr_pick$1696 + assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \wr_pick_dly$1699$next $0\wr_pick_dly$1699$next[0:0]$2835 + update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] end - attribute \src "libresoc.v:47336.3-47364.6" - process $proc$libresoc.v:47336$2837 + attribute \src "libresoc.v:48074.3-48102.6" + process $proc$libresoc.v:48074$2875 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$18[2:0]$2838 $1\fus_cu_rdmaskn_i$18[2:0]$2839 - attribute \src "libresoc.v:47337.5-47337.29" + assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:48075.5-48075.29" switch \initial - attribute \src "libresoc.v:47337.9-47337.17" + attribute \src "libresoc.v:48075.9-48075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$18[2:0]$2839 $2\fus_cu_rdmaskn_i$18[2:0]$2840 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$18[2:0]$2840 3'000 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$18[2:0]$2840 3'000 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$18[2:0]$2840 $3\fus_cu_rdmaskn_i$18[2:0]$2841 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [2] + assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$18[2:0]$2841 \$247 + assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia case - assign $3\fus_cu_rdmaskn_i$18[2:0]$2841 3'000 + assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end end case - assign $1\fus_cu_rdmaskn_i$18[2:0]$2839 3'000 + assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2838 + update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] end - attribute \src "libresoc.v:47365.3-47373.6" - process $proc$libresoc.v:47365$2842 + attribute \src "libresoc.v:48103.3-48131.6" + process $proc$libresoc.v:48103$2876 assign { } { } assign { } { } - assign $0\wr_pick_dly$1743$next[0:0]$2843 $1\wr_pick_dly$1743$next[0:0]$2844 - attribute \src "libresoc.v:47366.5-47366.29" + assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:48104.5-48104.29" switch \initial - attribute \src "libresoc.v:47366.9-47366.17" + attribute \src "libresoc.v:48104.9-48104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1743$next[0:0]$2844 1'0 + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit + case + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + end case - assign $1\wr_pick_dly$1743$next[0:0]$2844 \wr_pick$1740 + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 end sync always - update \wr_pick_dly$1743$next $0\wr_pick_dly$1743$next[0:0]$2843 + update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] end - attribute \src "libresoc.v:47374.3-47402.6" - process $proc$libresoc.v:47374$2845 + attribute \src "libresoc.v:48132.3-48160.6" + process $proc$libresoc.v:48132$2877 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47375.5-47375.29" + assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:48133.5-48133.29" switch \initial - attribute \src "libresoc.v:47375.9-47375.17" + attribute \src "libresoc.v:48133.9-48133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type + assign $3\fus_oper_i_alu_trap0__traptype[7:0] \core_core_traptype case - assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + assign $3\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 end end case - assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + assign $1\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 end sync always - update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] + update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] end - attribute \src "libresoc.v:47403.3-47411.6" - process $proc$libresoc.v:47403$2846 + attribute \src "libresoc.v:48161.3-48189.6" + process $proc$libresoc.v:48161$2878 assign { } { } assign { } { } - assign $0\wr_pick_dly$1759$next[0:0]$2847 $1\wr_pick_dly$1759$next[0:0]$2848 - attribute \src "libresoc.v:47404.5-47404.29" + assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:48162.5-48162.29" switch \initial - attribute \src "libresoc.v:47404.9-47404.17" + attribute \src "libresoc.v:48162.9-48162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1759$next[0:0]$2848 1'0 + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr + case + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + end case - assign $1\wr_pick_dly$1759$next[0:0]$2848 \wr_pick$1756 + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 end sync always - update \wr_pick_dly$1759$next $0\wr_pick_dly$1759$next[0:0]$2847 + update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] end - attribute \src "libresoc.v:47412.3-47420.6" - process $proc$libresoc.v:47412$2849 + attribute \src "libresoc.v:48190.3-48218.6" + process $proc$libresoc.v:48190$2879 assign { } { } assign { } { } - assign $0\wr_pick_dly$1783$next[0:0]$2850 $1\wr_pick_dly$1783$next[0:0]$2851 - attribute \src "libresoc.v:47413.5-47413.29" + assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:48191.5-48191.29" switch \initial - attribute \src "libresoc.v:47413.9-47413.17" + attribute \src "libresoc.v:48191.9-48191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" + switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1783$next[0:0]$2851 1'0 + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] { \core_core_exc_$signal$9 \core_core_exc_$signal$8 \core_core_exc_$signal$7 \core_core_exc_$signal$6 \core_core_exc_$signal$5 \core_core_exc_$signal$4 \core_core_exc_$signal$3 \core_core_exc_$signal } + case + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + end + end case - assign $1\wr_pick_dly$1783$next[0:0]$2851 \wr_pick$1780 + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 end sync always - update \wr_pick_dly$1783$next $0\wr_pick_dly$1783$next[0:0]$2850 + update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] end - attribute \src "libresoc.v:47421.3-47449.6" - process $proc$libresoc.v:47421$2852 + attribute \src "libresoc.v:48219.3-48247.6" + process $proc$libresoc.v:48219$2880 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_trap0__fn_unit[12:0] $1\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47422.5-47422.29" + assign $0\fus_cu_issue_i$19[0:0]$2881 $1\fus_cu_issue_i$19[0:0]$2882 + attribute \src "libresoc.v:48220.5-48220.29" switch \initial - attribute \src "libresoc.v:47422.9-47422.17" + attribute \src "libresoc.v:48220.9-48220.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_trap0__fn_unit[12:0] $2\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_issue_i$19[0:0]$2882 $2\fus_cu_issue_i$19[0:0]$2883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_trap0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_cu_issue_i$19[0:0]$2883 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_trap0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_cu_issue_i$19[0:0]$2883 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_trap0__fn_unit[12:0] $3\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_issue_i$19[0:0]$2883 $3\fus_cu_issue_i$19[0:0]$2884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_trap0__fn_unit[12:0] \core_core_fn_unit + assign $3\fus_cu_issue_i$19[0:0]$2884 \issue_i case - assign $3\fus_oper_i_alu_trap0__fn_unit[12:0] 13'0000000000000 + assign $3\fus_cu_issue_i$19[0:0]$2884 1'0 end end case - assign $1\fus_oper_i_alu_trap0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_cu_issue_i$19[0:0]$2882 1'0 end sync always - update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[12:0] + update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2881 end - attribute \src "libresoc.v:47450.3-47458.6" - process $proc$libresoc.v:47450$2853 + attribute \src "libresoc.v:48248.3-48276.6" + process $proc$libresoc.v:48248$2885 assign { } { } assign { } { } - assign $0\wr_pick_dly$1803$next[0:0]$2854 $1\wr_pick_dly$1803$next[0:0]$2855 - attribute \src "libresoc.v:47451.5-47451.29" + assign $0\fus_cu_rdmaskn_i$21[3:0]$2886 $1\fus_cu_rdmaskn_i$21[3:0]$2887 + attribute \src "libresoc.v:48249.5-48249.29" switch \initial - attribute \src "libresoc.v:47451.9-47451.17" + attribute \src "libresoc.v:48249.9-48249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1803$next[0:0]$2855 1'0 - case - assign $1\wr_pick_dly$1803$next[0:0]$2855 \wr_pick$1800 - end - sync always - update \wr_pick_dly$1803$next $0\wr_pick_dly$1803$next[0:0]$2854 - end - attribute \src "libresoc.v:47459.3-47487.6" - process $proc$libresoc.v:47459$2856 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47460.5-47460.29" - switch \initial - attribute \src "libresoc.v:47460.9-47460.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn - case - assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] - end - attribute \src "libresoc.v:47488.3-47516.6" - process $proc$libresoc.v:47488$2857 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47489.5-47489.29" - switch \initial - attribute \src "libresoc.v:47489.9-47489.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr - case - assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] - end - attribute \src "libresoc.v:47517.3-47545.6" - process $proc$libresoc.v:47517$2858 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47518.5-47518.29" - switch \initial - attribute \src "libresoc.v:47518.9-47518.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia - case - assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] - end - attribute \src "libresoc.v:47546.3-47574.6" - process $proc$libresoc.v:47546$2859 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47547.5-47547.29" - switch \initial - attribute \src "libresoc.v:47547.9-47547.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit - case - assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] - end - attribute \src "libresoc.v:47575.3-47603.6" - process $proc$libresoc.v:47575$2860 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:47576.5-47576.29" - switch \initial - attribute \src "libresoc.v:47576.9-47576.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__traptype[7:0] \core_core_traptype - case - assign $3\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 - end - sync always - update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] - end - attribute \src "libresoc.v:47604.3-47632.6" - process $proc$libresoc.v:47604$2861 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47605.5-47605.29" - switch \initial - attribute \src "libresoc.v:47605.9-47605.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr - case - assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - end - sync always - update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] - end - attribute \src "libresoc.v:47633.3-47661.6" - process $proc$libresoc.v:47633$2862 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47634.5-47634.29" - switch \initial - attribute \src "libresoc.v:47634.9-47634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] { \core_core_exc_$signal$9 \core_core_exc_$signal$8 \core_core_exc_$signal$7 \core_core_exc_$signal$6 \core_core_exc_$signal$5 \core_core_exc_$signal$4 \core_core_exc_$signal$3 \core_core_exc_$signal } - case - assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 - end - sync always - update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - end - attribute \src "libresoc.v:47662.3-47690.6" - process $proc$libresoc.v:47662$2863 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$19[0:0]$2864 $1\fus_cu_issue_i$19[0:0]$2865 - attribute \src "libresoc.v:47663.5-47663.29" - switch \initial - attribute \src "libresoc.v:47663.9-47663.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$19[0:0]$2865 $2\fus_cu_issue_i$19[0:0]$2866 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$19[0:0]$2866 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$19[0:0]$2866 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$19[0:0]$2866 $3\fus_cu_issue_i$19[0:0]$2867 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$19[0:0]$2867 \issue_i - case - assign $3\fus_cu_issue_i$19[0:0]$2867 1'0 - end - end - case - assign $1\fus_cu_issue_i$19[0:0]$2865 1'0 - end - sync always - update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2864 - end - attribute \src "libresoc.v:47691.3-47719.6" - process $proc$libresoc.v:47691$2868 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$21[3:0]$2869 $1\fus_cu_rdmaskn_i$21[3:0]$2870 - attribute \src "libresoc.v:47692.5-47692.29" - switch \initial - attribute \src "libresoc.v:47692.9-47692.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$21[3:0]$2870 $2\fus_cu_rdmaskn_i$21[3:0]$2871 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 $2\fus_cu_rdmaskn_i$21[3:0]$2888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$21[3:0]$2871 4'0000 + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$21[3:0]$2871 4'0000 + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$21[3:0]$2871 $3\fus_cu_rdmaskn_i$21[3:0]$2872 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 $3\fus_cu_rdmaskn_i$21[3:0]$2889 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$21[3:0]$2872 \$249 + assign $3\fus_cu_rdmaskn_i$21[3:0]$2889 \$254 case - assign $3\fus_cu_rdmaskn_i$21[3:0]$2872 4'0000 + assign $3\fus_cu_rdmaskn_i$21[3:0]$2889 4'0000 end end case - assign $1\fus_cu_rdmaskn_i$21[3:0]$2870 4'0000 + assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 4'0000 end sync always - update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2869 + update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2886 end - attribute \src "libresoc.v:47720.3-47748.6" - process $proc$libresoc.v:47720$2873 + attribute \src "libresoc.v:48277.3-48305.6" + process $proc$libresoc.v:48277$2890 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47721.5-47721.29" + attribute \src "libresoc.v:48278.5-48278.29" switch \initial - attribute \src "libresoc.v:47721.9-47721.17" + attribute \src "libresoc.v:48278.9-48278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83342,7 +84043,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83358,66 +84059,66 @@ module \core sync always update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] end - attribute \src "libresoc.v:47749.3-47777.6" - process $proc$libresoc.v:47749$2874 + attribute \src "libresoc.v:48306.3-48334.6" + process $proc$libresoc.v:48306$2891 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_logical0__fn_unit[12:0] $1\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47750.5-47750.29" + assign $0\fus_oper_i_alu_logical0__fn_unit[13:0] $1\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "libresoc.v:48307.5-48307.29" switch \initial - attribute \src "libresoc.v:47750.9-47750.17" + attribute \src "libresoc.v:48307.9-48307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_logical0__fn_unit[12:0] $2\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] $2\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_logical0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_logical0__fn_unit[12:0] 13'0000000000000 + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_logical0__fn_unit[12:0] $3\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] $3\fus_oper_i_alu_logical0__fn_unit[13:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__fn_unit[12:0] \dec_LOGICAL_LOGICAL__fn_unit + assign $3\fus_oper_i_alu_logical0__fn_unit[13:0] \dec_LOGICAL_LOGICAL__fn_unit case - assign $3\fus_oper_i_alu_logical0__fn_unit[12:0] 13'0000000000000 + assign $3\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 end end case - assign $1\fus_oper_i_alu_logical0__fn_unit[12:0] 13'0000000000000 + assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 end sync always - update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[12:0] + update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[13:0] end - attribute \src "libresoc.v:47778.3-47807.6" - process $proc$libresoc.v:47778$2875 + attribute \src "libresoc.v:48335.3-48364.6" + process $proc$libresoc.v:48335$2892 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47779.5-47779.29" + attribute \src "libresoc.v:48336.5-48336.29" switch \initial - attribute \src "libresoc.v:47779.9-47779.17" + attribute \src "libresoc.v:48336.9-48336.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83425,7 +84126,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83441,7 +84142,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83461,21 +84162,21 @@ module \core update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] end - attribute \src "libresoc.v:47808.3-47837.6" - process $proc$libresoc.v:47808$2876 + attribute \src "libresoc.v:48365.3-48394.6" + process $proc$libresoc.v:48365$2893 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47809.5-47809.29" + attribute \src "libresoc.v:48366.5-48366.29" switch \initial - attribute \src "libresoc.v:47809.9-47809.17" + attribute \src "libresoc.v:48366.9-48366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83483,7 +84184,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83499,7 +84200,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83519,21 +84220,21 @@ module \core update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] end - attribute \src "libresoc.v:47838.3-47867.6" - process $proc$libresoc.v:47838$2877 + attribute \src "libresoc.v:48395.3-48424.6" + process $proc$libresoc.v:48395$2894 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47839.5-47839.29" + attribute \src "libresoc.v:48396.5-48396.29" switch \initial - attribute \src "libresoc.v:47839.9-47839.17" + attribute \src "libresoc.v:48396.9-48396.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83541,7 +84242,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83557,7 +84258,7 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83577,24 +84278,24 @@ module \core update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] end - attribute \src "libresoc.v:47868.3-47896.6" - process $proc$libresoc.v:47868$2878 + attribute \src "libresoc.v:48425.3-48453.6" + process $proc$libresoc.v:48425$2895 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47869.5-47869.29" + attribute \src "libresoc.v:48426.5-48426.29" switch \initial - attribute \src "libresoc.v:47869.9-47869.17" + attribute \src "libresoc.v:48426.9-48426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83606,7 +84307,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83622,24 +84323,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] end - attribute \src "libresoc.v:47897.3-47925.6" - process $proc$libresoc.v:47897$2879 + attribute \src "libresoc.v:48454.3-48482.6" + process $proc$libresoc.v:48454$2896 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:47898.5-47898.29" + attribute \src "libresoc.v:48455.5-48455.29" switch \initial - attribute \src "libresoc.v:47898.9-47898.17" + attribute \src "libresoc.v:48455.9-48455.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83651,7 +84352,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83667,24 +84368,24 @@ module \core sync always update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] end - attribute \src "libresoc.v:47926.3-47954.6" - process $proc$libresoc.v:47926$2880 + attribute \src "libresoc.v:48483.3-48511.6" + process $proc$libresoc.v:48483$2897 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47927.5-47927.29" + attribute \src "libresoc.v:48484.5-48484.29" switch \initial - attribute \src "libresoc.v:47927.9-47927.17" + attribute \src "libresoc.v:48484.9-48484.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83696,7 +84397,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83712,24 +84413,24 @@ module \core sync always update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] end - attribute \src "libresoc.v:47955.3-47983.6" - process $proc$libresoc.v:47955$2881 + attribute \src "libresoc.v:48512.3-48540.6" + process $proc$libresoc.v:48512$2898 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47956.5-47956.29" + attribute \src "libresoc.v:48513.5-48513.29" switch \initial - attribute \src "libresoc.v:47956.9-47956.17" + attribute \src "libresoc.v:48513.9-48513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83741,7 +84442,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83757,24 +84458,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] end - attribute \src "libresoc.v:47984.3-48012.6" - process $proc$libresoc.v:47984$2882 + attribute \src "libresoc.v:48541.3-48569.6" + process $proc$libresoc.v:48541$2899 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47985.5-47985.29" + attribute \src "libresoc.v:48542.5-48542.29" switch \initial - attribute \src "libresoc.v:47985.9-47985.17" + attribute \src "libresoc.v:48542.9-48542.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83786,7 +84487,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -83802,1574 +84503,1169 @@ module \core sync always update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] end - attribute \src "libresoc.v:48013.3-48041.6" - process $proc$libresoc.v:48013$2883 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48014.5-48014.29" - switch \initial - attribute \src "libresoc.v:48014.9-48014.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry - case - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] - end - attribute \src "libresoc.v:48042.3-48070.6" - process $proc$libresoc.v:48042$2884 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48043.5-48043.29" - switch \initial - attribute \src "libresoc.v:48043.9-48043.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit - case - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] - end - attribute \src "libresoc.v:48071.3-48099.6" - process $proc$libresoc.v:48071$2885 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48072.5-48072.29" - switch \initial - attribute \src "libresoc.v:48072.9-48072.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed - case - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] - end - attribute \src "libresoc.v:48100.3-48128.6" - process $proc$libresoc.v:48100$2886 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48101.5-48101.29" - switch \initial - attribute \src "libresoc.v:48101.9-48101.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len - case - assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] - end - attribute \src "libresoc.v:48129.3-48157.6" - process $proc$libresoc.v:48129$2887 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48130.5-48130.29" - switch \initial - attribute \src "libresoc.v:48130.9-48130.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn - case - assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] - end - attribute \src "libresoc.v:48158.3-48186.6" - process $proc$libresoc.v:48158$2888 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$22[0:0]$2889 $1\fus_cu_issue_i$22[0:0]$2890 - attribute \src "libresoc.v:48159.5-48159.29" - switch \initial - attribute \src "libresoc.v:48159.9-48159.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$22[0:0]$2890 $2\fus_cu_issue_i$22[0:0]$2891 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$22[0:0]$2891 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$22[0:0]$2891 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$22[0:0]$2891 $3\fus_cu_issue_i$22[0:0]$2892 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$22[0:0]$2892 \issue_i - case - assign $3\fus_cu_issue_i$22[0:0]$2892 1'0 - end - end - case - assign $1\fus_cu_issue_i$22[0:0]$2890 1'0 - end - sync always - update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2889 - end - attribute \src "libresoc.v:48187.3-48215.6" - process $proc$libresoc.v:48187$2893 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$24[2:0]$2894 $1\fus_cu_rdmaskn_i$24[2:0]$2895 - attribute \src "libresoc.v:48188.5-48188.29" - switch \initial - attribute \src "libresoc.v:48188.9-48188.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$24[2:0]$2895 $2\fus_cu_rdmaskn_i$24[2:0]$2896 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$24[2:0]$2896 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$24[2:0]$2896 3'000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$24[2:0]$2896 $3\fus_cu_rdmaskn_i$24[2:0]$2897 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$24[2:0]$2897 \$251 - case - assign $3\fus_cu_rdmaskn_i$24[2:0]$2897 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$24[2:0]$2895 3'000 - end - sync always - update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2894 - end - attribute \src "libresoc.v:48216.3-48244.6" - process $proc$libresoc.v:48216$2898 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:48217.5-48217.29" - switch \initial - attribute \src "libresoc.v:48217.9-48217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type - case - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] - end - attribute \src "libresoc.v:48245.3-48273.6" - process $proc$libresoc.v:48245$2899 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__fn_unit[12:0] $1\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:48246.5-48246.29" - switch \initial - attribute \src "libresoc.v:48246.9-48246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__fn_unit[12:0] $2\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__fn_unit[12:0] $3\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__fn_unit[12:0] \dec_SPR_SPR__fn_unit - case - assign $3\fus_oper_i_alu_spr0__fn_unit[12:0] 13'0000000000000 - end - end - case - assign $1\fus_oper_i_alu_spr0__fn_unit[12:0] 13'0000000000000 - end - sync always - update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[12:0] - end - connect \$1000 $and$libresoc.v:41811$1506_Y - connect \$1003 $and$libresoc.v:41812$1507_Y - connect \$1007 $not$libresoc.v:41813$1508_Y - connect \$1009 $and$libresoc.v:41814$1509_Y - connect \$1016 $and$libresoc.v:41815$1510_Y - connect \$1019 $ternary$libresoc.v:41816$1511_Y - connect \$1021 $and$libresoc.v:41817$1512_Y - connect \$1024 $and$libresoc.v:41818$1513_Y - connect \$1028 $not$libresoc.v:41819$1514_Y - connect \$1030 $and$libresoc.v:41820$1515_Y - connect \$1034 $and$libresoc.v:41821$1516_Y - connect \$1037 $ternary$libresoc.v:41822$1517_Y - connect \$1039 $and$libresoc.v:41823$1518_Y - connect \$1042 $and$libresoc.v:41824$1519_Y - connect \$1046 $not$libresoc.v:41825$1520_Y - connect \$1048 $and$libresoc.v:41826$1521_Y - connect \$1056 $and$libresoc.v:41827$1522_Y - connect \$1059 $ternary$libresoc.v:41828$1523_Y - connect \$1061 $and$libresoc.v:41829$1524_Y - connect \$1064 $and$libresoc.v:41830$1525_Y - connect \$1068 $not$libresoc.v:41831$1526_Y - connect \$1070 $and$libresoc.v:41832$1527_Y - connect \$1076 $and$libresoc.v:41833$1528_Y - connect \$1079 $ternary$libresoc.v:41834$1529_Y - connect \$1081 $and$libresoc.v:41835$1530_Y - connect \$1084 $and$libresoc.v:41836$1531_Y - connect \$1088 $not$libresoc.v:41837$1532_Y - connect \$1090 $and$libresoc.v:41838$1533_Y - connect \$1096 $and$libresoc.v:41839$1534_Y - connect \$1099 $ternary$libresoc.v:41840$1535_Y - connect \$1101 $and$libresoc.v:41841$1536_Y - connect \$1104 $and$libresoc.v:41842$1537_Y - connect \$1108 $not$libresoc.v:41843$1538_Y - connect \$1110 $and$libresoc.v:41844$1539_Y - connect \$1115 $and$libresoc.v:41845$1540_Y - connect \$1118 $ternary$libresoc.v:41846$1541_Y - connect \$1120 $and$libresoc.v:41847$1542_Y - connect \$1123 $and$libresoc.v:41848$1543_Y - connect \$1127 $not$libresoc.v:41849$1544_Y - connect \$1129 $and$libresoc.v:41850$1545_Y - connect \$1133 $and$libresoc.v:41851$1546_Y - connect \$1136 $ternary$libresoc.v:41852$1547_Y - connect \$1138 $and$libresoc.v:41853$1548_Y - connect \$1141 $and$libresoc.v:41854$1549_Y - connect \$1144 $not$libresoc.v:41855$1550_Y - connect \$1146 $and$libresoc.v:41856$1551_Y - connect \$1149 $and$libresoc.v:41857$1552_Y - connect \$1152 $ternary$libresoc.v:41858$1553_Y - connect \$1155 $or$libresoc.v:41859$1554_Y - connect \$1157 $or$libresoc.v:41860$1555_Y - connect \$1159 $or$libresoc.v:41861$1556_Y - connect \$1161 $or$libresoc.v:41862$1557_Y - connect \$1163 $or$libresoc.v:41863$1558_Y - connect \$1165 $or$libresoc.v:41864$1559_Y - connect \$1167 $or$libresoc.v:41865$1560_Y - connect \$1169 $or$libresoc.v:41866$1561_Y - connect \$1171 $or$libresoc.v:41867$1562_Y - connect \$1174 $or$libresoc.v:41868$1563_Y - connect \$1176 $or$libresoc.v:41869$1564_Y - connect \$1178 $or$libresoc.v:41870$1565_Y - connect \$1180 $or$libresoc.v:41871$1566_Y - connect \$1182 $or$libresoc.v:41872$1567_Y - connect \$1184 $or$libresoc.v:41873$1568_Y - connect \$1186 $or$libresoc.v:41874$1569_Y - connect \$1188 $or$libresoc.v:41875$1570_Y - connect \$1190 $or$libresoc.v:41876$1571_Y - connect \$1192 $or$libresoc.v:41877$1572_Y - connect \$1194 $or$libresoc.v:41878$1573_Y - connect \$1196 $or$libresoc.v:41879$1574_Y - connect \$1198 $or$libresoc.v:41880$1575_Y - connect \$1200 $or$libresoc.v:41881$1576_Y - connect \$1202 $or$libresoc.v:41882$1577_Y - connect \$1204 $or$libresoc.v:41883$1578_Y - connect \$1206 $or$libresoc.v:41884$1579_Y - connect \$1208 $or$libresoc.v:41885$1580_Y - connect \$1210 $and$libresoc.v:41886$1581_Y - connect \$1212 $and$libresoc.v:41887$1582_Y - connect \$1215 $and$libresoc.v:41888$1583_Y - connect \$1218 $not$libresoc.v:41889$1584_Y - connect \$1220 $and$libresoc.v:41890$1585_Y - connect \$1223 $and$libresoc.v:41891$1586_Y - connect \$1226 $ternary$libresoc.v:41892$1587_Y - connect \$1228 $and$libresoc.v:41893$1588_Y - connect \$1230 $and$libresoc.v:41894$1589_Y - connect \$1232 $and$libresoc.v:41895$1590_Y - connect \$1234 $and$libresoc.v:41896$1591_Y - connect \$1236 $and$libresoc.v:41897$1592_Y - connect \$1238 $and$libresoc.v:41898$1593_Y - connect \$1240 $and$libresoc.v:41899$1594_Y - connect \$1243 $and$libresoc.v:41900$1595_Y - connect \$1246 $not$libresoc.v:41901$1596_Y - connect \$1248 $and$libresoc.v:41902$1597_Y - connect \$1251 $and$libresoc.v:41903$1598_Y - connect \$1254 $sub$libresoc.v:41904$1599_Y - connect \$1256 $sshl$libresoc.v:41905$1600_Y - connect \$1258 $ternary$libresoc.v:41906$1601_Y - connect \$1260 $and$libresoc.v:41907$1602_Y - connect \$1263 $and$libresoc.v:41908$1603_Y - connect \$1266 $not$libresoc.v:41909$1604_Y - connect \$1268 $and$libresoc.v:41910$1605_Y - connect \$1271 $and$libresoc.v:41911$1606_Y - connect \$1274 $sub$libresoc.v:41912$1607_Y - connect \$1276 $sshl$libresoc.v:41913$1608_Y - connect \$1278 $ternary$libresoc.v:41914$1609_Y - connect \$1280 $and$libresoc.v:41915$1610_Y - connect \$1283 $and$libresoc.v:41916$1611_Y - connect \$1286 $not$libresoc.v:41917$1612_Y - connect \$1288 $and$libresoc.v:41918$1613_Y - connect \$1291 $and$libresoc.v:41919$1614_Y - connect \$1294 $sub$libresoc.v:41920$1615_Y - connect \$1296 $sshl$libresoc.v:41921$1616_Y - connect \$1298 $ternary$libresoc.v:41922$1617_Y - connect \$1300 $and$libresoc.v:41923$1618_Y - connect \$1303 $and$libresoc.v:41924$1619_Y - connect \$1306 $not$libresoc.v:41925$1620_Y - connect \$1308 $and$libresoc.v:41926$1621_Y - connect \$1311 $and$libresoc.v:41927$1622_Y - connect \$1314 $sub$libresoc.v:41928$1623_Y - connect \$1316 $sshl$libresoc.v:41929$1624_Y - connect \$1318 $ternary$libresoc.v:41930$1625_Y - connect \$1320 $and$libresoc.v:41931$1626_Y - connect \$1323 $and$libresoc.v:41932$1627_Y - connect \$1326 $not$libresoc.v:41933$1628_Y - connect \$1328 $and$libresoc.v:41934$1629_Y - connect \$1331 $and$libresoc.v:41935$1630_Y - connect \$1334 $sub$libresoc.v:41936$1631_Y - connect \$1336 $sshl$libresoc.v:41937$1632_Y - connect \$1338 $ternary$libresoc.v:41938$1633_Y - connect \$1340 $and$libresoc.v:41939$1634_Y - connect \$1343 $and$libresoc.v:41940$1635_Y - connect \$1346 $not$libresoc.v:41941$1636_Y - connect \$1348 $and$libresoc.v:41942$1637_Y - connect \$1351 $and$libresoc.v:41943$1638_Y - connect \$1354 $sub$libresoc.v:41944$1639_Y - connect \$1356 $sshl$libresoc.v:41945$1640_Y - connect \$1358 $ternary$libresoc.v:41946$1641_Y - connect \$1360 $or$libresoc.v:41947$1642_Y - connect \$1362 $or$libresoc.v:41948$1643_Y - connect \$1364 $or$libresoc.v:41949$1644_Y - connect \$1366 $or$libresoc.v:41950$1645_Y - connect \$1368 $or$libresoc.v:41951$1646_Y - connect \$1371 $or$libresoc.v:41952$1647_Y - connect \$1373 $or$libresoc.v:41953$1648_Y - connect \$1375 $or$libresoc.v:41954$1649_Y - connect \$1377 $or$libresoc.v:41955$1650_Y - connect \$1379 $or$libresoc.v:41956$1651_Y - connect \$1381 $and$libresoc.v:41957$1652_Y - connect \$1383 $and$libresoc.v:41958$1653_Y - connect \$1385 $and$libresoc.v:41959$1654_Y - connect \$1387 $and$libresoc.v:41960$1655_Y - connect \$1390 $and$libresoc.v:41961$1656_Y - connect \$1393 $not$libresoc.v:41962$1657_Y - connect \$1395 $and$libresoc.v:41963$1658_Y - connect \$1398 $and$libresoc.v:41964$1659_Y - connect \$1401 $ternary$libresoc.v:41965$1660_Y - connect \$1403 $and$libresoc.v:41966$1661_Y - connect \$1406 $and$libresoc.v:41967$1662_Y - connect \$1409 $not$libresoc.v:41968$1663_Y - connect \$1411 $and$libresoc.v:41969$1664_Y - connect \$1414 $and$libresoc.v:41970$1665_Y - connect \$1417 $ternary$libresoc.v:41971$1666_Y - connect \$1419 $and$libresoc.v:41972$1667_Y - connect \$1422 $and$libresoc.v:41973$1668_Y - connect \$1425 $not$libresoc.v:41974$1669_Y - connect \$1427 $and$libresoc.v:41975$1670_Y - connect \$1430 $and$libresoc.v:41976$1671_Y - connect \$1433 $ternary$libresoc.v:41977$1672_Y - connect \$1435 $or$libresoc.v:41978$1673_Y - connect \$1437 $or$libresoc.v:41979$1674_Y - connect \$1440 $or$libresoc.v:41980$1675_Y - connect \$1442 $or$libresoc.v:41981$1676_Y - connect \$1439 $pos$libresoc.v:41982$1678_Y - connect \$1445 $and$libresoc.v:41983$1679_Y - connect \$1447 $and$libresoc.v:41984$1680_Y - connect \$1449 $and$libresoc.v:41985$1681_Y - connect \$1451 $and$libresoc.v:41986$1682_Y - connect \$1453 $and$libresoc.v:41987$1683_Y - connect \$1456 $and$libresoc.v:41988$1684_Y - connect \$1459 $not$libresoc.v:41989$1685_Y - connect \$1461 $and$libresoc.v:41990$1686_Y - connect \$1464 $and$libresoc.v:41991$1687_Y - connect \$1467 $ternary$libresoc.v:41992$1688_Y - connect \$1469 $and$libresoc.v:41993$1689_Y - connect \$1472 $and$libresoc.v:41994$1690_Y - connect \$1475 $not$libresoc.v:41995$1691_Y - connect \$1477 $and$libresoc.v:41996$1692_Y - connect \$1480 $and$libresoc.v:41997$1693_Y - connect \$1483 $ternary$libresoc.v:41998$1694_Y - connect \$1485 $and$libresoc.v:41999$1695_Y - connect \$1488 $and$libresoc.v:42000$1696_Y - connect \$1491 $not$libresoc.v:42001$1697_Y - connect \$1493 $and$libresoc.v:42002$1698_Y - connect \$1496 $and$libresoc.v:42003$1699_Y - connect \$1499 $ternary$libresoc.v:42004$1700_Y - connect \$1501 $and$libresoc.v:42005$1701_Y - connect \$1504 $and$libresoc.v:42006$1702_Y - connect \$1507 $not$libresoc.v:42007$1703_Y - connect \$1509 $and$libresoc.v:42008$1704_Y - connect \$1512 $and$libresoc.v:42009$1705_Y - connect \$1515 $ternary$libresoc.v:42010$1706_Y - connect \$1517 $or$libresoc.v:42011$1707_Y - connect \$1519 $or$libresoc.v:42012$1708_Y - connect \$1521 $or$libresoc.v:42013$1709_Y - connect \$1523 $or$libresoc.v:42014$1710_Y - connect \$1525 $or$libresoc.v:42015$1711_Y - connect \$1527 $or$libresoc.v:42016$1712_Y - connect \$1529 $and$libresoc.v:42017$1713_Y - connect \$1531 $and$libresoc.v:42018$1714_Y - connect \$1533 $and$libresoc.v:42019$1715_Y - connect \$1535 $and$libresoc.v:42020$1716_Y - connect \$1537 $and$libresoc.v:42021$1717_Y - connect \$1540 $and$libresoc.v:42022$1718_Y - connect \$1543 $not$libresoc.v:42023$1719_Y - connect \$1545 $and$libresoc.v:42024$1720_Y - connect \$1548 $and$libresoc.v:42025$1721_Y - connect \$1551 $ternary$libresoc.v:42026$1722_Y - connect \$1553 $and$libresoc.v:42027$1723_Y - connect \$1556 $and$libresoc.v:42028$1724_Y - connect \$1559 $not$libresoc.v:42029$1725_Y - connect \$1561 $and$libresoc.v:42030$1726_Y - connect \$1564 $and$libresoc.v:42031$1727_Y - connect \$1567 $ternary$libresoc.v:42032$1728_Y - connect \$1569 $and$libresoc.v:42033$1729_Y - connect \$1572 $and$libresoc.v:42034$1730_Y - connect \$1575 $not$libresoc.v:42035$1731_Y - connect \$1577 $and$libresoc.v:42036$1732_Y - connect \$1580 $and$libresoc.v:42037$1733_Y - connect \$1583 $ternary$libresoc.v:42038$1734_Y - connect \$1585 $and$libresoc.v:42039$1735_Y - connect \$1588 $and$libresoc.v:42040$1736_Y - connect \$1591 $not$libresoc.v:42041$1737_Y - connect \$1593 $and$libresoc.v:42042$1738_Y - connect \$1596 $and$libresoc.v:42043$1739_Y - connect \$1599 $ternary$libresoc.v:42044$1740_Y - connect \$1602 $or$libresoc.v:42045$1741_Y - connect \$1604 $or$libresoc.v:42046$1742_Y - connect \$1606 $or$libresoc.v:42047$1743_Y - connect \$1601 $pos$libresoc.v:42048$1745_Y - connect \$1610 $or$libresoc.v:42049$1746_Y - connect \$1612 $or$libresoc.v:42050$1747_Y - connect \$1614 $or$libresoc.v:42051$1748_Y - connect \$1609 $pos$libresoc.v:42052$1750_Y - connect \$1617 $and$libresoc.v:42053$1751_Y - connect \$1619 $and$libresoc.v:42054$1752_Y - connect \$1621 $and$libresoc.v:42055$1753_Y - connect \$1623 $and$libresoc.v:42056$1754_Y - connect \$1625 $and$libresoc.v:42057$1755_Y - connect \$1627 $and$libresoc.v:42058$1756_Y - connect \$1630 $and$libresoc.v:42059$1757_Y - connect \$1634 $not$libresoc.v:42060$1758_Y - connect \$1636 $and$libresoc.v:42061$1759_Y - connect \$1641 $and$libresoc.v:42062$1760_Y - connect \$1644 $ternary$libresoc.v:42063$1761_Y - connect \$1646 $and$libresoc.v:42064$1762_Y - connect \$1649 $and$libresoc.v:42065$1763_Y - connect \$1652 $not$libresoc.v:42066$1764_Y - connect \$1654 $and$libresoc.v:42067$1765_Y - connect \$1657 $and$libresoc.v:42068$1766_Y - connect \$1660 $ternary$libresoc.v:42069$1767_Y - connect \$1662 $and$libresoc.v:42070$1768_Y - connect \$1665 $and$libresoc.v:42071$1769_Y - connect \$1668 $not$libresoc.v:42072$1770_Y - connect \$1670 $and$libresoc.v:42073$1771_Y - connect \$1673 $and$libresoc.v:42074$1772_Y - connect \$1676 $ternary$libresoc.v:42075$1773_Y - connect \$1678 $and$libresoc.v:42076$1774_Y - connect \$1681 $and$libresoc.v:42077$1775_Y - connect \$1684 $not$libresoc.v:42078$1776_Y - connect \$1686 $and$libresoc.v:42079$1777_Y - connect \$1689 $and$libresoc.v:42080$1778_Y - connect \$1692 $ternary$libresoc.v:42081$1779_Y - connect \$1694 $and$libresoc.v:42082$1780_Y - connect \$1697 $and$libresoc.v:42083$1781_Y - connect \$1700 $not$libresoc.v:42084$1782_Y - connect \$1702 $and$libresoc.v:42085$1783_Y - connect \$1705 $and$libresoc.v:42086$1784_Y - connect \$1708 $ternary$libresoc.v:42087$1785_Y - connect \$1710 $or$libresoc.v:42088$1786_Y - connect \$1712 $or$libresoc.v:42089$1787_Y - connect \$1714 $or$libresoc.v:42090$1788_Y - connect \$1716 $or$libresoc.v:42091$1789_Y - connect \$1718 $or$libresoc.v:42092$1790_Y - connect \$1720 $or$libresoc.v:42093$1791_Y - connect \$1722 $or$libresoc.v:42094$1792_Y - connect \$1724 $or$libresoc.v:42095$1793_Y - connect \$1726 $or$libresoc.v:42096$1794_Y - connect \$1728 $or$libresoc.v:42097$1795_Y - connect \$1730 $or$libresoc.v:42098$1796_Y - connect \$1732 $or$libresoc.v:42099$1797_Y - connect \$1734 $and$libresoc.v:42100$1798_Y - connect \$1736 $and$libresoc.v:42101$1799_Y - connect \$1738 $and$libresoc.v:42102$1800_Y - connect \$1741 $and$libresoc.v:42103$1801_Y - connect \$1744 $not$libresoc.v:42104$1802_Y - connect \$1746 $and$libresoc.v:42105$1803_Y - connect \$1749 $and$libresoc.v:42106$1804_Y - connect \$1752 $ternary$libresoc.v:42107$1805_Y - connect \$1754 $and$libresoc.v:42108$1806_Y - connect \$1757 $and$libresoc.v:42109$1807_Y - connect \$1760 $not$libresoc.v:42110$1808_Y - connect \$1762 $and$libresoc.v:42111$1809_Y - connect \$1765 $and$libresoc.v:42112$1810_Y - connect \$1768 $ternary$libresoc.v:42113$1811_Y - connect \$1770 $or$libresoc.v:42114$1812_Y - connect \$1773 $or$libresoc.v:42115$1813_Y - connect \$1772 $pos$libresoc.v:42116$1815_Y - connect \$1776 $and$libresoc.v:42117$1816_Y - connect \$1778 $and$libresoc.v:42118$1817_Y - connect \$177 $and$libresoc.v:42119$1818_Y - connect \$1781 $and$libresoc.v:42120$1819_Y - connect \$1784 $not$libresoc.v:42121$1820_Y - connect \$1786 $and$libresoc.v:42122$1821_Y - connect \$176 $reduce_or$libresoc.v:42123$1822_Y - connect \$1789 $and$libresoc.v:42124$1823_Y - connect \$1792 $ternary$libresoc.v:42125$1824_Y - connect \$1794 $pos$libresoc.v:42126$1826_Y - connect \$1796 $and$libresoc.v:42127$1827_Y - connect \$1798 $and$libresoc.v:42128$1828_Y - connect \$1801 $and$libresoc.v:42129$1829_Y - connect \$1804 $not$libresoc.v:42130$1830_Y - connect \$1806 $and$libresoc.v:42131$1831_Y - connect \$1809 $and$libresoc.v:42132$1832_Y - connect \$1812 $ternary$libresoc.v:42133$1833_Y - connect \$181 $and$libresoc.v:42134$1834_Y - connect \$180 $reduce_or$libresoc.v:42135$1835_Y - connect \$185 $and$libresoc.v:42136$1836_Y - connect \$184 $reduce_or$libresoc.v:42137$1837_Y - connect \$189 $and$libresoc.v:42138$1838_Y - connect \$188 $reduce_or$libresoc.v:42139$1839_Y - connect \$193 $and$libresoc.v:42140$1840_Y - connect \$192 $reduce_or$libresoc.v:42141$1841_Y - connect \$197 $and$libresoc.v:42142$1842_Y - connect \$196 $reduce_or$libresoc.v:42143$1843_Y - connect \$201 $and$libresoc.v:42144$1844_Y - connect \$200 $reduce_or$libresoc.v:42145$1845_Y - connect \$205 $and$libresoc.v:42146$1846_Y - connect \$204 $reduce_or$libresoc.v:42147$1847_Y - connect \$209 $and$libresoc.v:42148$1848_Y - connect \$208 $reduce_or$libresoc.v:42149$1849_Y - connect \$213 $and$libresoc.v:42150$1850_Y - connect \$212 $reduce_or$libresoc.v:42151$1851_Y - connect \$216 $ne$libresoc.v:42152$1852_Y - connect \$219 $sub$libresoc.v:42153$1853_Y - connect \$221 $ne$libresoc.v:42154$1854_Y - connect \$224 $and$libresoc.v:42155$1855_Y - connect \$226 $and$libresoc.v:42156$1856_Y - connect \$228 $eq$libresoc.v:42157$1857_Y - connect \$230 $or$libresoc.v:42158$1858_Y - connect \$232 $and$libresoc.v:42159$1859_Y - connect \$234 $or$libresoc.v:42160$1860_Y - connect \$236 $eq$libresoc.v:42161$1861_Y - connect \$238 $and$libresoc.v:42162$1862_Y - connect \$240 $eq$libresoc.v:42163$1863_Y - connect \$242 $or$libresoc.v:42164$1864_Y - connect \$223 $not$libresoc.v:42165$1865_Y - connect \$245 $not$libresoc.v:42166$1866_Y - connect \$247 $not$libresoc.v:42167$1867_Y - connect \$249 $not$libresoc.v:42168$1868_Y - connect \$252 $and$libresoc.v:42169$1869_Y - connect \$254 $and$libresoc.v:42170$1870_Y - connect \$256 $eq$libresoc.v:42171$1871_Y - connect \$258 $or$libresoc.v:42172$1872_Y - connect \$260 $and$libresoc.v:42173$1873_Y - connect \$262 $or$libresoc.v:42174$1874_Y - connect \$251 $not$libresoc.v:42175$1875_Y - connect \$266 $and$libresoc.v:42176$1876_Y - connect \$268 $and$libresoc.v:42177$1877_Y - connect \$270 $eq$libresoc.v:42178$1878_Y - connect \$272 $or$libresoc.v:42179$1879_Y - connect \$274 $and$libresoc.v:42180$1880_Y - connect \$276 $or$libresoc.v:42181$1881_Y - connect \$278 $and$libresoc.v:42182$1882_Y - connect \$280 $and$libresoc.v:42183$1883_Y - connect \$282 $eq$libresoc.v:42184$1884_Y - connect \$284 $or$libresoc.v:42185$1885_Y - connect \$286 $eq$libresoc.v:42186$1886_Y - connect \$288 $and$libresoc.v:42187$1887_Y - connect \$290 $eq$libresoc.v:42188$1888_Y - connect \$292 $or$libresoc.v:42189$1889_Y - connect \$265 $not$libresoc.v:42190$1890_Y - connect \$296 $and$libresoc.v:42191$1891_Y - connect \$298 $and$libresoc.v:42192$1892_Y - connect \$300 $eq$libresoc.v:42193$1893_Y - connect \$302 $or$libresoc.v:42194$1894_Y - connect \$304 $and$libresoc.v:42195$1895_Y - connect \$306 $or$libresoc.v:42196$1896_Y - connect \$295 $not$libresoc.v:42197$1897_Y - connect \$310 $and$libresoc.v:42198$1898_Y - connect \$312 $and$libresoc.v:42199$1899_Y - connect \$314 $eq$libresoc.v:42200$1900_Y - connect \$316 $or$libresoc.v:42201$1901_Y - connect \$318 $and$libresoc.v:42202$1902_Y - connect \$320 $or$libresoc.v:42203$1903_Y - connect \$309 $not$libresoc.v:42204$1904_Y - connect \$324 $and$libresoc.v:42205$1905_Y - connect \$326 $and$libresoc.v:42206$1906_Y - connect \$328 $eq$libresoc.v:42207$1907_Y - connect \$330 $or$libresoc.v:42208$1908_Y - connect \$332 $and$libresoc.v:42209$1909_Y - connect \$334 $or$libresoc.v:42210$1910_Y - connect \$336 $eq$libresoc.v:42211$1911_Y - connect \$338 $and$libresoc.v:42212$1912_Y - connect \$340 $eq$libresoc.v:42213$1913_Y - connect \$342 $or$libresoc.v:42214$1914_Y - connect \$323 $not$libresoc.v:42215$1915_Y - connect \$345 $not$libresoc.v:42216$1916_Y - connect \$347 $and$libresoc.v:42217$1917_Y - connect \$349 $and$libresoc.v:42218$1918_Y - connect \$351 $not$libresoc.v:42219$1919_Y - connect \$353 $and$libresoc.v:42220$1920_Y - connect \$355 $and$libresoc.v:42221$1921_Y - connect \$357 $ternary$libresoc.v:42222$1922_Y - connect \$359 $and$libresoc.v:42223$1923_Y - connect \$361 $and$libresoc.v:42224$1924_Y - connect \$363 $not$libresoc.v:42225$1925_Y - connect \$365 $and$libresoc.v:42226$1926_Y - connect \$367 $and$libresoc.v:42227$1927_Y - connect \$369 $ternary$libresoc.v:42228$1928_Y - connect \$371 $and$libresoc.v:42229$1929_Y - connect \$373 $and$libresoc.v:42230$1930_Y - connect \$375 $not$libresoc.v:42231$1931_Y - connect \$377 $and$libresoc.v:42232$1932_Y - connect \$379 $and$libresoc.v:42233$1933_Y - connect \$381 $ternary$libresoc.v:42234$1934_Y - connect \$383 $and$libresoc.v:42235$1935_Y - connect \$385 $and$libresoc.v:42236$1936_Y - connect \$387 $not$libresoc.v:42237$1937_Y - connect \$389 $and$libresoc.v:42238$1938_Y - connect \$391 $and$libresoc.v:42239$1939_Y - connect \$393 $ternary$libresoc.v:42240$1940_Y - connect \$395 $and$libresoc.v:42241$1941_Y - connect \$397 $and$libresoc.v:42242$1942_Y - connect \$399 $not$libresoc.v:42243$1943_Y - connect \$401 $and$libresoc.v:42244$1944_Y - connect \$403 $and$libresoc.v:42245$1945_Y - connect \$405 $ternary$libresoc.v:42246$1946_Y - connect \$407 $and$libresoc.v:42247$1947_Y - connect \$409 $and$libresoc.v:42248$1948_Y - connect \$411 $not$libresoc.v:42249$1949_Y - connect \$413 $and$libresoc.v:42250$1950_Y - connect \$415 $and$libresoc.v:42251$1951_Y - connect \$417 $ternary$libresoc.v:42252$1952_Y - connect \$419 $and$libresoc.v:42253$1953_Y - connect \$421 $and$libresoc.v:42254$1954_Y - connect \$423 $not$libresoc.v:42255$1955_Y - connect \$425 $and$libresoc.v:42256$1956_Y - connect \$427 $and$libresoc.v:42257$1957_Y - connect \$429 $ternary$libresoc.v:42258$1958_Y - connect \$431 $and$libresoc.v:42259$1959_Y - connect \$433 $and$libresoc.v:42260$1960_Y - connect \$435 $not$libresoc.v:42261$1961_Y - connect \$437 $and$libresoc.v:42262$1962_Y - connect \$439 $and$libresoc.v:42263$1963_Y - connect \$441 $ternary$libresoc.v:42264$1964_Y - connect \$443 $and$libresoc.v:42265$1965_Y - connect \$445 $and$libresoc.v:42266$1966_Y - connect \$447 $not$libresoc.v:42267$1967_Y - connect \$449 $and$libresoc.v:42268$1968_Y - connect \$451 $and$libresoc.v:42269$1969_Y - connect \$453 $ternary$libresoc.v:42270$1970_Y - connect \$456 $or$libresoc.v:42271$1971_Y - connect \$458 $or$libresoc.v:42272$1972_Y - connect \$460 $or$libresoc.v:42273$1973_Y - connect \$462 $or$libresoc.v:42274$1974_Y - connect \$464 $or$libresoc.v:42275$1975_Y - connect \$466 $or$libresoc.v:42276$1976_Y - connect \$468 $or$libresoc.v:42277$1977_Y - connect \$470 $or$libresoc.v:42278$1978_Y - connect \$472 $reduce_or$libresoc.v:42279$1979_Y - connect \$474 $and$libresoc.v:42280$1980_Y - connect \$476 $and$libresoc.v:42281$1981_Y - connect \$478 $not$libresoc.v:42282$1982_Y - connect \$480 $and$libresoc.v:42283$1983_Y - connect \$482 $and$libresoc.v:42284$1984_Y - connect \$484 $ternary$libresoc.v:42285$1985_Y - connect \$486 $and$libresoc.v:42286$1986_Y - connect \$488 $and$libresoc.v:42287$1987_Y - connect \$490 $not$libresoc.v:42288$1988_Y - connect \$492 $and$libresoc.v:42289$1989_Y - connect \$494 $and$libresoc.v:42290$1990_Y - connect \$496 $ternary$libresoc.v:42291$1991_Y - connect \$498 $and$libresoc.v:42292$1992_Y - connect \$500 $and$libresoc.v:42293$1993_Y - connect \$502 $not$libresoc.v:42294$1994_Y - connect \$504 $and$libresoc.v:42295$1995_Y - connect \$506 $and$libresoc.v:42296$1996_Y - connect \$508 $ternary$libresoc.v:42297$1997_Y - connect \$510 $and$libresoc.v:42298$1998_Y - connect \$512 $and$libresoc.v:42299$1999_Y - connect \$514 $not$libresoc.v:42300$2000_Y - connect \$516 $and$libresoc.v:42301$2001_Y - connect \$518 $and$libresoc.v:42302$2002_Y - connect \$520 $ternary$libresoc.v:42303$2003_Y - connect \$522 $and$libresoc.v:42304$2004_Y - connect \$524 $and$libresoc.v:42305$2005_Y - connect \$526 $not$libresoc.v:42306$2006_Y - connect \$528 $and$libresoc.v:42307$2007_Y - connect \$530 $and$libresoc.v:42308$2008_Y - connect \$532 $ternary$libresoc.v:42309$2009_Y - connect \$534 $and$libresoc.v:42310$2010_Y - connect \$536 $and$libresoc.v:42311$2011_Y - connect \$538 $not$libresoc.v:42312$2012_Y - connect \$540 $and$libresoc.v:42313$2013_Y - connect \$542 $and$libresoc.v:42314$2014_Y - connect \$544 $ternary$libresoc.v:42315$2015_Y - connect \$546 $and$libresoc.v:42316$2016_Y - connect \$548 $and$libresoc.v:42317$2017_Y - connect \$550 $not$libresoc.v:42318$2018_Y - connect \$552 $and$libresoc.v:42319$2019_Y - connect \$554 $and$libresoc.v:42320$2020_Y - connect \$556 $ternary$libresoc.v:42321$2021_Y - connect \$558 $and$libresoc.v:42322$2022_Y - connect \$560 $and$libresoc.v:42323$2023_Y - connect \$562 $not$libresoc.v:42324$2024_Y - connect \$564 $and$libresoc.v:42325$2025_Y - connect \$566 $and$libresoc.v:42326$2026_Y - connect \$568 $ternary$libresoc.v:42327$2027_Y - connect \$571 $or$libresoc.v:42328$2028_Y - connect \$573 $or$libresoc.v:42329$2029_Y - connect \$575 $or$libresoc.v:42330$2030_Y - connect \$577 $or$libresoc.v:42331$2031_Y - connect \$579 $or$libresoc.v:42332$2032_Y - connect \$581 $or$libresoc.v:42333$2033_Y - connect \$583 $or$libresoc.v:42334$2034_Y - connect \$585 $reduce_or$libresoc.v:42335$2035_Y - connect \$587 $and$libresoc.v:42336$2036_Y - connect \$589 $and$libresoc.v:42337$2037_Y - connect \$591 $not$libresoc.v:42338$2038_Y - connect \$593 $and$libresoc.v:42339$2039_Y - connect \$595 $and$libresoc.v:42340$2040_Y - connect \$597 $ternary$libresoc.v:42341$2041_Y - connect \$599 $and$libresoc.v:42342$2042_Y - connect \$601 $and$libresoc.v:42343$2043_Y - connect \$603 $not$libresoc.v:42344$2044_Y - connect \$605 $and$libresoc.v:42345$2045_Y - connect \$607 $and$libresoc.v:42346$2046_Y - connect \$609 $ternary$libresoc.v:42347$2047_Y - connect \$612 $or$libresoc.v:42348$2048_Y - connect \$614 $reduce_or$libresoc.v:42349$2049_Y - connect \$616 $and$libresoc.v:42350$2050_Y - connect \$618 $and$libresoc.v:42351$2051_Y - connect \$620 $eq$libresoc.v:42352$2052_Y - connect \$622 $or$libresoc.v:42353$2053_Y - connect \$624 $and$libresoc.v:42354$2054_Y - connect \$626 $or$libresoc.v:42355$2055_Y - connect \$628 $and$libresoc.v:42356$2056_Y - connect \$630 $and$libresoc.v:42357$2057_Y - connect \$632 $not$libresoc.v:42358$2058_Y - connect \$634 $and$libresoc.v:42359$2059_Y - connect \$636 $and$libresoc.v:42360$2060_Y - connect \$638 $ternary$libresoc.v:42361$2061_Y - connect \$640 $and$libresoc.v:42362$2062_Y - connect \$642 $and$libresoc.v:42363$2063_Y - connect \$644 $not$libresoc.v:42364$2064_Y - connect \$646 $and$libresoc.v:42365$2065_Y - connect \$648 $and$libresoc.v:42366$2066_Y - connect \$650 $ternary$libresoc.v:42367$2067_Y - connect \$652 $and$libresoc.v:42368$2068_Y - connect \$654 $and$libresoc.v:42369$2069_Y - connect \$656 $not$libresoc.v:42370$2070_Y - connect \$658 $and$libresoc.v:42371$2071_Y - connect \$660 $and$libresoc.v:42372$2072_Y - connect \$662 $ternary$libresoc.v:42373$2073_Y - connect \$664 $and$libresoc.v:42374$2074_Y - connect \$666 $and$libresoc.v:42375$2075_Y - connect \$668 $not$libresoc.v:42376$2076_Y - connect \$670 $and$libresoc.v:42377$2077_Y - connect \$672 $and$libresoc.v:42378$2078_Y - connect \$674 $ternary$libresoc.v:42379$2079_Y - connect \$676 $and$libresoc.v:42380$2080_Y - connect \$678 $and$libresoc.v:42381$2081_Y - connect \$680 $not$libresoc.v:42382$2082_Y - connect \$682 $and$libresoc.v:42383$2083_Y - connect \$684 $and$libresoc.v:42384$2084_Y - connect \$686 $ternary$libresoc.v:42385$2085_Y - connect \$688 $and$libresoc.v:42386$2086_Y - connect \$690 $and$libresoc.v:42387$2087_Y - connect \$692 $not$libresoc.v:42388$2088_Y - connect \$694 $and$libresoc.v:42389$2089_Y - connect \$696 $and$libresoc.v:42390$2090_Y - connect \$698 $ternary$libresoc.v:42391$2091_Y - connect \$701 $or$libresoc.v:42392$2092_Y - connect \$703 $or$libresoc.v:42393$2093_Y - connect \$705 $or$libresoc.v:42394$2094_Y - connect \$707 $or$libresoc.v:42395$2095_Y - connect \$709 $or$libresoc.v:42396$2096_Y - connect \$700 $pos$libresoc.v:42397$2098_Y - connect \$712 $eq$libresoc.v:42398$2099_Y - connect \$714 $and$libresoc.v:42399$2100_Y - connect \$716 $eq$libresoc.v:42400$2101_Y - connect \$718 $or$libresoc.v:42401$2102_Y - connect \$720 $and$libresoc.v:42402$2103_Y - connect \$722 $and$libresoc.v:42403$2104_Y - connect \$724 $not$libresoc.v:42404$2105_Y - connect \$726 $and$libresoc.v:42405$2106_Y - connect \$728 $and$libresoc.v:42406$2107_Y - connect \$730 $ternary$libresoc.v:42407$2108_Y - connect \$732 $and$libresoc.v:42408$2109_Y - connect \$734 $and$libresoc.v:42409$2110_Y - connect \$736 $not$libresoc.v:42410$2111_Y - connect \$738 $and$libresoc.v:42411$2112_Y - connect \$740 $and$libresoc.v:42412$2113_Y - connect \$742 $ternary$libresoc.v:42413$2114_Y - connect \$744 $and$libresoc.v:42414$2115_Y - connect \$746 $and$libresoc.v:42415$2116_Y - connect \$748 $not$libresoc.v:42416$2117_Y - connect \$750 $and$libresoc.v:42417$2118_Y - connect \$752 $and$libresoc.v:42418$2119_Y - connect \$754 $ternary$libresoc.v:42419$2120_Y - connect \$757 $or$libresoc.v:42420$2121_Y - connect \$759 $or$libresoc.v:42421$2122_Y - connect \$756 $pos$libresoc.v:42422$2124_Y - connect \$762 $and$libresoc.v:42423$2125_Y - connect \$764 $and$libresoc.v:42424$2126_Y - connect \$766 $eq$libresoc.v:42425$2127_Y - connect \$768 $or$libresoc.v:42426$2128_Y - connect \$770 $and$libresoc.v:42427$2129_Y - connect \$772 $and$libresoc.v:42428$2130_Y - connect \$774 $not$libresoc.v:42429$2131_Y - connect \$776 $and$libresoc.v:42430$2132_Y - connect \$778 $and$libresoc.v:42431$2133_Y - connect \$780 $ternary$libresoc.v:42432$2134_Y - connect \$782 $and$libresoc.v:42433$2135_Y - connect \$784 $and$libresoc.v:42434$2136_Y - connect \$786 $not$libresoc.v:42435$2137_Y - connect \$788 $and$libresoc.v:42436$2138_Y - connect \$790 $and$libresoc.v:42437$2139_Y - connect \$792 $ternary$libresoc.v:42438$2140_Y - connect \$794 $and$libresoc.v:42439$2141_Y - connect \$796 $and$libresoc.v:42440$2142_Y - connect \$798 $not$libresoc.v:42441$2143_Y - connect \$800 $and$libresoc.v:42442$2144_Y - connect \$802 $and$libresoc.v:42443$2145_Y - connect \$804 $sub$libresoc.v:42444$2146_Y - connect \$806 $sshl$libresoc.v:42445$2147_Y - connect \$808 $ternary$libresoc.v:42446$2148_Y - connect \$810 $and$libresoc.v:42447$2149_Y - connect \$812 $and$libresoc.v:42448$2150_Y - connect \$814 $not$libresoc.v:42449$2151_Y - connect \$816 $and$libresoc.v:42450$2152_Y - connect \$818 $and$libresoc.v:42451$2153_Y - connect \$820 $sub$libresoc.v:42452$2154_Y - connect \$822 $sshl$libresoc.v:42453$2155_Y - connect \$824 $ternary$libresoc.v:42454$2156_Y - connect \$827 $or$libresoc.v:42455$2157_Y - connect \$829 $and$libresoc.v:42456$2158_Y - connect \$831 $and$libresoc.v:42457$2159_Y - connect \$833 $not$libresoc.v:42458$2160_Y - connect \$835 $and$libresoc.v:42459$2161_Y - connect \$837 $and$libresoc.v:42460$2162_Y - connect \$839 $sub$libresoc.v:42461$2163_Y - connect \$841 $sshl$libresoc.v:42462$2164_Y - connect \$843 $ternary$libresoc.v:42463$2165_Y - connect \$845 $and$libresoc.v:42464$2166_Y - connect \$847 $and$libresoc.v:42465$2167_Y - connect \$849 $not$libresoc.v:42466$2168_Y - connect \$851 $and$libresoc.v:42467$2169_Y - connect \$853 $and$libresoc.v:42468$2170_Y - connect \$855 $sub$libresoc.v:42469$2171_Y - connect \$857 $sshl$libresoc.v:42470$2172_Y - connect \$859 $ternary$libresoc.v:42471$2173_Y - connect \$861 $and$libresoc.v:42472$2174_Y - connect \$863 $and$libresoc.v:42473$2175_Y - connect \$865 $not$libresoc.v:42474$2176_Y - connect \$867 $and$libresoc.v:42475$2177_Y - connect \$869 $and$libresoc.v:42476$2178_Y - connect \$871 $ternary$libresoc.v:42477$2179_Y - connect \$873 $and$libresoc.v:42478$2180_Y - connect \$875 $and$libresoc.v:42479$2181_Y - connect \$877 $not$libresoc.v:42480$2182_Y - connect \$879 $and$libresoc.v:42481$2183_Y - connect \$881 $and$libresoc.v:42482$2184_Y - connect \$883 $ternary$libresoc.v:42483$2185_Y - connect \$885 $and$libresoc.v:42484$2186_Y - connect \$887 $and$libresoc.v:42485$2187_Y - connect \$889 $not$libresoc.v:42486$2188_Y - connect \$891 $and$libresoc.v:42487$2189_Y - connect \$893 $and$libresoc.v:42488$2190_Y - connect \$895 $ternary$libresoc.v:42489$2191_Y - connect \$897 $or$libresoc.v:42490$2192_Y - connect \$899 $or$libresoc.v:42491$2193_Y - connect \$901 $reduce_or$libresoc.v:42492$2194_Y - connect \$903 $and$libresoc.v:42493$2195_Y - connect \$905 $and$libresoc.v:42494$2196_Y - connect \$907 $not$libresoc.v:42495$2197_Y - connect \$909 $and$libresoc.v:42496$2198_Y - connect \$911 $and$libresoc.v:42497$2199_Y - connect \$913 $ternary$libresoc.v:42498$2200_Y - connect \$915 $and$libresoc.v:42499$2201_Y - connect \$917 $and$libresoc.v:42500$2202_Y - connect \$919 $not$libresoc.v:42501$2203_Y - connect \$921 $and$libresoc.v:42502$2204_Y - connect \$923 $and$libresoc.v:42503$2205_Y - connect \$925 $ternary$libresoc.v:42504$2206_Y - connect \$927 $or$libresoc.v:42505$2207_Y - connect \$929 $reduce_or$libresoc.v:42506$2208_Y - connect \$931 $and$libresoc.v:42507$2209_Y - connect \$933 $and$libresoc.v:42508$2210_Y - connect \$935 $not$libresoc.v:42509$2211_Y - connect \$937 $and$libresoc.v:42510$2212_Y - connect \$939 $and$libresoc.v:42511$2213_Y - connect \$941 $ternary$libresoc.v:42512$2214_Y - connect \$943 $reduce_or$libresoc.v:42513$2215_Y - connect \$945 $and$libresoc.v:42514$2216_Y - connect \$947 $and$libresoc.v:42515$2217_Y - connect \$949 $and$libresoc.v:42516$2218_Y - connect \$951 $and$libresoc.v:42517$2219_Y - connect \$953 $and$libresoc.v:42518$2220_Y - connect \$955 $and$libresoc.v:42519$2221_Y - connect \$957 $and$libresoc.v:42520$2222_Y - connect \$959 $and$libresoc.v:42521$2223_Y - connect \$961 $and$libresoc.v:42522$2224_Y - connect \$963 $and$libresoc.v:42523$2225_Y - connect \$965 $and$libresoc.v:42524$2226_Y - connect \$967 $and$libresoc.v:42525$2227_Y - connect \$969 $not$libresoc.v:42526$2228_Y - connect \$971 $and$libresoc.v:42527$2229_Y - connect \$977 $and$libresoc.v:42528$2230_Y - connect \$979 $ternary$libresoc.v:42529$2231_Y - connect \$981 $and$libresoc.v:42530$2232_Y - connect \$984 $and$libresoc.v:42531$2233_Y - connect \$988 $not$libresoc.v:42532$2234_Y - connect \$990 $and$libresoc.v:42533$2235_Y - connect \$995 $and$libresoc.v:42534$2236_Y - connect \$998 $ternary$libresoc.v:42535$2237_Y - connect \$218 \$219 - connect \$455 \$470 - connect \$570 \$583 - connect \$611 \$612 - connect \$826 \$827 - connect \$1154 \$1171 - connect \$1173 \$1190 - connect \$1370 \$1379 + connect \$1000 $and$libresoc.v:42103$1506_Y + connect \$1003 $ternary$libresoc.v:42104$1507_Y + connect \$1005 $and$libresoc.v:42105$1508_Y + connect \$1008 $and$libresoc.v:42106$1509_Y + connect \$1012 $not$libresoc.v:42107$1510_Y + connect \$1014 $and$libresoc.v:42108$1511_Y + connect \$1021 $and$libresoc.v:42109$1512_Y + connect \$1024 $ternary$libresoc.v:42110$1513_Y + connect \$1026 $and$libresoc.v:42111$1514_Y + connect \$1029 $and$libresoc.v:42112$1515_Y + connect \$1033 $not$libresoc.v:42113$1516_Y + connect \$1035 $and$libresoc.v:42114$1517_Y + connect \$1039 $and$libresoc.v:42115$1518_Y + connect \$1042 $ternary$libresoc.v:42116$1519_Y + connect \$1044 $and$libresoc.v:42117$1520_Y + connect \$1047 $and$libresoc.v:42118$1521_Y + connect \$1051 $not$libresoc.v:42119$1522_Y + connect \$1053 $and$libresoc.v:42120$1523_Y + connect \$1061 $and$libresoc.v:42121$1524_Y + connect \$1064 $ternary$libresoc.v:42122$1525_Y + connect \$1066 $and$libresoc.v:42123$1526_Y + connect \$1069 $and$libresoc.v:42124$1527_Y + connect \$1073 $not$libresoc.v:42125$1528_Y + connect \$1075 $and$libresoc.v:42126$1529_Y + connect \$1081 $and$libresoc.v:42127$1530_Y + connect \$1084 $ternary$libresoc.v:42128$1531_Y + connect \$1086 $and$libresoc.v:42129$1532_Y + connect \$1089 $and$libresoc.v:42130$1533_Y + connect \$1093 $not$libresoc.v:42131$1534_Y + connect \$1095 $and$libresoc.v:42132$1535_Y + connect \$1101 $and$libresoc.v:42133$1536_Y + connect \$1104 $ternary$libresoc.v:42134$1537_Y + connect \$1106 $and$libresoc.v:42135$1538_Y + connect \$1109 $and$libresoc.v:42136$1539_Y + connect \$1113 $not$libresoc.v:42137$1540_Y + connect \$1115 $and$libresoc.v:42138$1541_Y + connect \$1120 $and$libresoc.v:42139$1542_Y + connect \$1123 $ternary$libresoc.v:42140$1543_Y + connect \$1125 $and$libresoc.v:42141$1544_Y + connect \$1128 $and$libresoc.v:42142$1545_Y + connect \$1132 $not$libresoc.v:42143$1546_Y + connect \$1134 $and$libresoc.v:42144$1547_Y + connect \$1138 $and$libresoc.v:42145$1548_Y + connect \$1141 $ternary$libresoc.v:42146$1549_Y + connect \$1143 $and$libresoc.v:42147$1550_Y + connect \$1146 $and$libresoc.v:42148$1551_Y + connect \$1149 $not$libresoc.v:42149$1552_Y + connect \$1151 $and$libresoc.v:42150$1553_Y + connect \$1154 $and$libresoc.v:42151$1554_Y + connect \$1157 $ternary$libresoc.v:42152$1555_Y + connect \$1160 $or$libresoc.v:42153$1556_Y + connect \$1162 $or$libresoc.v:42154$1557_Y + connect \$1164 $or$libresoc.v:42155$1558_Y + connect \$1166 $or$libresoc.v:42156$1559_Y + connect \$1168 $or$libresoc.v:42157$1560_Y + connect \$1170 $or$libresoc.v:42158$1561_Y + connect \$1172 $or$libresoc.v:42159$1562_Y + connect \$1174 $or$libresoc.v:42160$1563_Y + connect \$1176 $or$libresoc.v:42161$1564_Y + connect \$1179 $or$libresoc.v:42162$1565_Y + connect \$1181 $or$libresoc.v:42163$1566_Y + connect \$1183 $or$libresoc.v:42164$1567_Y + connect \$1185 $or$libresoc.v:42165$1568_Y + connect \$1187 $or$libresoc.v:42166$1569_Y + connect \$1189 $or$libresoc.v:42167$1570_Y + connect \$1191 $or$libresoc.v:42168$1571_Y + connect \$1193 $or$libresoc.v:42169$1572_Y + connect \$1195 $or$libresoc.v:42170$1573_Y + connect \$1197 $or$libresoc.v:42171$1574_Y + connect \$1199 $or$libresoc.v:42172$1575_Y + connect \$1201 $or$libresoc.v:42173$1576_Y + connect \$1203 $or$libresoc.v:42174$1577_Y + connect \$1205 $or$libresoc.v:42175$1578_Y + connect \$1207 $or$libresoc.v:42176$1579_Y + connect \$1209 $or$libresoc.v:42177$1580_Y + connect \$1211 $or$libresoc.v:42178$1581_Y + connect \$1213 $or$libresoc.v:42179$1582_Y + connect \$1215 $and$libresoc.v:42180$1583_Y + connect \$1217 $and$libresoc.v:42181$1584_Y + connect \$1220 $and$libresoc.v:42182$1585_Y + connect \$1223 $not$libresoc.v:42183$1586_Y + connect \$1225 $and$libresoc.v:42184$1587_Y + connect \$1228 $and$libresoc.v:42185$1588_Y + connect \$1231 $ternary$libresoc.v:42186$1589_Y + connect \$1233 $and$libresoc.v:42187$1590_Y + connect \$1235 $and$libresoc.v:42188$1591_Y + connect \$1237 $and$libresoc.v:42189$1592_Y + connect \$1239 $and$libresoc.v:42190$1593_Y + connect \$1241 $and$libresoc.v:42191$1594_Y + connect \$1243 $and$libresoc.v:42192$1595_Y + connect \$1245 $and$libresoc.v:42193$1596_Y + connect \$1248 $and$libresoc.v:42194$1597_Y + connect \$1251 $not$libresoc.v:42195$1598_Y + connect \$1253 $and$libresoc.v:42196$1599_Y + connect \$1256 $and$libresoc.v:42197$1600_Y + connect \$1259 $sub$libresoc.v:42198$1601_Y + connect \$1261 $sshl$libresoc.v:42199$1602_Y + connect \$1263 $ternary$libresoc.v:42200$1603_Y + connect \$1265 $and$libresoc.v:42201$1604_Y + connect \$1268 $and$libresoc.v:42202$1605_Y + connect \$1271 $not$libresoc.v:42203$1606_Y + connect \$1273 $and$libresoc.v:42204$1607_Y + connect \$1276 $and$libresoc.v:42205$1608_Y + connect \$1279 $sub$libresoc.v:42206$1609_Y + connect \$1281 $sshl$libresoc.v:42207$1610_Y + connect \$1283 $ternary$libresoc.v:42208$1611_Y + connect \$1285 $and$libresoc.v:42209$1612_Y + connect \$1288 $and$libresoc.v:42210$1613_Y + connect \$1291 $not$libresoc.v:42211$1614_Y + connect \$1293 $and$libresoc.v:42212$1615_Y + connect \$1296 $and$libresoc.v:42213$1616_Y + connect \$1299 $sub$libresoc.v:42214$1617_Y + connect \$1301 $sshl$libresoc.v:42215$1618_Y + connect \$1303 $ternary$libresoc.v:42216$1619_Y + connect \$1305 $and$libresoc.v:42217$1620_Y + connect \$1308 $and$libresoc.v:42218$1621_Y + connect \$1311 $not$libresoc.v:42219$1622_Y + connect \$1313 $and$libresoc.v:42220$1623_Y + connect \$1316 $and$libresoc.v:42221$1624_Y + connect \$1319 $sub$libresoc.v:42222$1625_Y + connect \$1321 $sshl$libresoc.v:42223$1626_Y + connect \$1323 $ternary$libresoc.v:42224$1627_Y + connect \$1325 $and$libresoc.v:42225$1628_Y + connect \$1328 $and$libresoc.v:42226$1629_Y + connect \$1331 $not$libresoc.v:42227$1630_Y + connect \$1333 $and$libresoc.v:42228$1631_Y + connect \$1336 $and$libresoc.v:42229$1632_Y + connect \$1339 $sub$libresoc.v:42230$1633_Y + connect \$1341 $sshl$libresoc.v:42231$1634_Y + connect \$1343 $ternary$libresoc.v:42232$1635_Y + connect \$1345 $and$libresoc.v:42233$1636_Y + connect \$1348 $and$libresoc.v:42234$1637_Y + connect \$1351 $not$libresoc.v:42235$1638_Y + connect \$1353 $and$libresoc.v:42236$1639_Y + connect \$1356 $and$libresoc.v:42237$1640_Y + connect \$1359 $sub$libresoc.v:42238$1641_Y + connect \$1361 $sshl$libresoc.v:42239$1642_Y + connect \$1363 $ternary$libresoc.v:42240$1643_Y + connect \$1365 $or$libresoc.v:42241$1644_Y + connect \$1367 $or$libresoc.v:42242$1645_Y + connect \$1369 $or$libresoc.v:42243$1646_Y + connect \$1371 $or$libresoc.v:42244$1647_Y + connect \$1373 $or$libresoc.v:42245$1648_Y + connect \$1376 $or$libresoc.v:42246$1649_Y + connect \$1378 $or$libresoc.v:42247$1650_Y + connect \$1380 $or$libresoc.v:42248$1651_Y + connect \$1382 $or$libresoc.v:42249$1652_Y + connect \$1384 $or$libresoc.v:42250$1653_Y + connect \$1386 $and$libresoc.v:42251$1654_Y + connect \$1388 $and$libresoc.v:42252$1655_Y + connect \$1390 $and$libresoc.v:42253$1656_Y + connect \$1392 $and$libresoc.v:42254$1657_Y + connect \$1395 $and$libresoc.v:42255$1658_Y + connect \$1398 $not$libresoc.v:42256$1659_Y + connect \$1400 $and$libresoc.v:42257$1660_Y + connect \$1403 $and$libresoc.v:42258$1661_Y + connect \$1406 $ternary$libresoc.v:42259$1662_Y + connect \$1408 $and$libresoc.v:42260$1663_Y + connect \$1411 $and$libresoc.v:42261$1664_Y + connect \$1414 $not$libresoc.v:42262$1665_Y + connect \$1416 $and$libresoc.v:42263$1666_Y + connect \$1419 $and$libresoc.v:42264$1667_Y + connect \$1422 $ternary$libresoc.v:42265$1668_Y + connect \$1424 $and$libresoc.v:42266$1669_Y + connect \$1427 $and$libresoc.v:42267$1670_Y + connect \$1430 $not$libresoc.v:42268$1671_Y + connect \$1432 $and$libresoc.v:42269$1672_Y + connect \$1435 $and$libresoc.v:42270$1673_Y + connect \$1438 $ternary$libresoc.v:42271$1674_Y + connect \$1440 $or$libresoc.v:42272$1675_Y + connect \$1442 $or$libresoc.v:42273$1676_Y + connect \$1445 $or$libresoc.v:42274$1677_Y + connect \$1447 $or$libresoc.v:42275$1678_Y + connect \$1444 $pos$libresoc.v:42276$1680_Y + connect \$1450 $and$libresoc.v:42277$1681_Y + connect \$1452 $and$libresoc.v:42278$1682_Y + connect \$1454 $and$libresoc.v:42279$1683_Y + connect \$1456 $and$libresoc.v:42280$1684_Y + connect \$1458 $and$libresoc.v:42281$1685_Y + connect \$1461 $and$libresoc.v:42282$1686_Y + connect \$1464 $not$libresoc.v:42283$1687_Y + connect \$1466 $and$libresoc.v:42284$1688_Y + connect \$1469 $and$libresoc.v:42285$1689_Y + connect \$1472 $ternary$libresoc.v:42286$1690_Y + connect \$1474 $and$libresoc.v:42287$1691_Y + connect \$1477 $and$libresoc.v:42288$1692_Y + connect \$1480 $not$libresoc.v:42289$1693_Y + connect \$1482 $and$libresoc.v:42290$1694_Y + connect \$1485 $and$libresoc.v:42291$1695_Y + connect \$1488 $ternary$libresoc.v:42292$1696_Y + connect \$1490 $and$libresoc.v:42293$1697_Y + connect \$1493 $and$libresoc.v:42294$1698_Y + connect \$1496 $not$libresoc.v:42295$1699_Y + connect \$1498 $and$libresoc.v:42296$1700_Y + connect \$1501 $and$libresoc.v:42297$1701_Y + connect \$1504 $ternary$libresoc.v:42298$1702_Y + connect \$1506 $and$libresoc.v:42299$1703_Y + connect \$1509 $and$libresoc.v:42300$1704_Y + connect \$1512 $not$libresoc.v:42301$1705_Y + connect \$1514 $and$libresoc.v:42302$1706_Y + connect \$1517 $and$libresoc.v:42303$1707_Y + connect \$1520 $ternary$libresoc.v:42304$1708_Y + connect \$1522 $or$libresoc.v:42305$1709_Y + connect \$1524 $or$libresoc.v:42306$1710_Y + connect \$1526 $or$libresoc.v:42307$1711_Y + connect \$1528 $or$libresoc.v:42308$1712_Y + connect \$1530 $or$libresoc.v:42309$1713_Y + connect \$1532 $or$libresoc.v:42310$1714_Y + connect \$1534 $and$libresoc.v:42311$1715_Y + connect \$1536 $and$libresoc.v:42312$1716_Y + connect \$1538 $and$libresoc.v:42313$1717_Y + connect \$1540 $and$libresoc.v:42314$1718_Y + connect \$1542 $and$libresoc.v:42315$1719_Y + connect \$1545 $and$libresoc.v:42316$1720_Y + connect \$1548 $not$libresoc.v:42317$1721_Y + connect \$1550 $and$libresoc.v:42318$1722_Y + connect \$1553 $and$libresoc.v:42319$1723_Y + connect \$1556 $ternary$libresoc.v:42320$1724_Y + connect \$1558 $and$libresoc.v:42321$1725_Y + connect \$1561 $and$libresoc.v:42322$1726_Y + connect \$1564 $not$libresoc.v:42323$1727_Y + connect \$1566 $and$libresoc.v:42324$1728_Y + connect \$1569 $and$libresoc.v:42325$1729_Y + connect \$1572 $ternary$libresoc.v:42326$1730_Y + connect \$1574 $and$libresoc.v:42327$1731_Y + connect \$1577 $and$libresoc.v:42328$1732_Y + connect \$1580 $not$libresoc.v:42329$1733_Y + connect \$1582 $and$libresoc.v:42330$1734_Y + connect \$1585 $and$libresoc.v:42331$1735_Y + connect \$1588 $ternary$libresoc.v:42332$1736_Y + connect \$1590 $and$libresoc.v:42333$1737_Y + connect \$1593 $and$libresoc.v:42334$1738_Y + connect \$1596 $not$libresoc.v:42335$1739_Y + connect \$1598 $and$libresoc.v:42336$1740_Y + connect \$1601 $and$libresoc.v:42337$1741_Y + connect \$1604 $ternary$libresoc.v:42338$1742_Y + connect \$1607 $or$libresoc.v:42339$1743_Y + connect \$1609 $or$libresoc.v:42340$1744_Y + connect \$1611 $or$libresoc.v:42341$1745_Y + connect \$1606 $pos$libresoc.v:42342$1747_Y + connect \$1615 $or$libresoc.v:42343$1748_Y + connect \$1617 $or$libresoc.v:42344$1749_Y + connect \$1619 $or$libresoc.v:42345$1750_Y + connect \$1614 $pos$libresoc.v:42346$1752_Y + connect \$1622 $and$libresoc.v:42347$1753_Y + connect \$1624 $and$libresoc.v:42348$1754_Y + connect \$1626 $and$libresoc.v:42349$1755_Y + connect \$1628 $and$libresoc.v:42350$1756_Y + connect \$1630 $and$libresoc.v:42351$1757_Y + connect \$1632 $and$libresoc.v:42352$1758_Y + connect \$1635 $and$libresoc.v:42353$1759_Y + connect \$1639 $not$libresoc.v:42354$1760_Y + connect \$1641 $and$libresoc.v:42355$1761_Y + connect \$1646 $and$libresoc.v:42356$1762_Y + connect \$1649 $ternary$libresoc.v:42357$1763_Y + connect \$1651 $and$libresoc.v:42358$1764_Y + connect \$1654 $and$libresoc.v:42359$1765_Y + connect \$1657 $not$libresoc.v:42360$1766_Y + connect \$1659 $and$libresoc.v:42361$1767_Y + connect \$1662 $and$libresoc.v:42362$1768_Y + connect \$1665 $ternary$libresoc.v:42363$1769_Y + connect \$1667 $and$libresoc.v:42364$1770_Y + connect \$1670 $and$libresoc.v:42365$1771_Y + connect \$1673 $not$libresoc.v:42366$1772_Y + connect \$1675 $and$libresoc.v:42367$1773_Y + connect \$1678 $and$libresoc.v:42368$1774_Y + connect \$1681 $ternary$libresoc.v:42369$1775_Y + connect \$1683 $and$libresoc.v:42370$1776_Y + connect \$1686 $and$libresoc.v:42371$1777_Y + connect \$1689 $not$libresoc.v:42372$1778_Y + connect \$1691 $and$libresoc.v:42373$1779_Y + connect \$1694 $and$libresoc.v:42374$1780_Y + connect \$1697 $ternary$libresoc.v:42375$1781_Y + connect \$1699 $and$libresoc.v:42376$1782_Y + connect \$1702 $and$libresoc.v:42377$1783_Y + connect \$1705 $not$libresoc.v:42378$1784_Y + connect \$1707 $and$libresoc.v:42379$1785_Y + connect \$1710 $and$libresoc.v:42380$1786_Y + connect \$1713 $ternary$libresoc.v:42381$1787_Y + connect \$1715 $or$libresoc.v:42382$1788_Y + connect \$1717 $or$libresoc.v:42383$1789_Y + connect \$1719 $or$libresoc.v:42384$1790_Y + connect \$1721 $or$libresoc.v:42385$1791_Y + connect \$1723 $or$libresoc.v:42386$1792_Y + connect \$1725 $or$libresoc.v:42387$1793_Y + connect \$1727 $or$libresoc.v:42388$1794_Y + connect \$1729 $or$libresoc.v:42389$1795_Y + connect \$1731 $or$libresoc.v:42390$1796_Y + connect \$1733 $or$libresoc.v:42391$1797_Y + connect \$1735 $or$libresoc.v:42392$1798_Y + connect \$1737 $or$libresoc.v:42393$1799_Y + connect \$1739 $and$libresoc.v:42394$1800_Y + connect \$1741 $and$libresoc.v:42395$1801_Y + connect \$1743 $and$libresoc.v:42396$1802_Y + connect \$1746 $and$libresoc.v:42397$1803_Y + connect \$1749 $not$libresoc.v:42398$1804_Y + connect \$1751 $and$libresoc.v:42399$1805_Y + connect \$1754 $and$libresoc.v:42400$1806_Y + connect \$1757 $ternary$libresoc.v:42401$1807_Y + connect \$1759 $and$libresoc.v:42402$1808_Y + connect \$1762 $and$libresoc.v:42403$1809_Y + connect \$1765 $not$libresoc.v:42404$1810_Y + connect \$1767 $and$libresoc.v:42405$1811_Y + connect \$1770 $and$libresoc.v:42406$1812_Y + connect \$1773 $ternary$libresoc.v:42407$1813_Y + connect \$1775 $or$libresoc.v:42408$1814_Y + connect \$1778 $or$libresoc.v:42409$1815_Y + connect \$1777 $pos$libresoc.v:42410$1817_Y + connect \$1781 $and$libresoc.v:42411$1818_Y + connect \$1783 $and$libresoc.v:42412$1819_Y + connect \$1786 $and$libresoc.v:42413$1820_Y + connect \$1789 $not$libresoc.v:42414$1821_Y + connect \$1791 $and$libresoc.v:42415$1822_Y + connect \$1794 $and$libresoc.v:42416$1823_Y + connect \$1797 $ternary$libresoc.v:42417$1824_Y + connect \$1799 $pos$libresoc.v:42418$1826_Y + connect \$1801 $and$libresoc.v:42419$1827_Y + connect \$1803 $and$libresoc.v:42420$1828_Y + connect \$1806 $and$libresoc.v:42421$1829_Y + connect \$1809 $not$libresoc.v:42422$1830_Y + connect \$1811 $and$libresoc.v:42423$1831_Y + connect \$1814 $and$libresoc.v:42424$1832_Y + connect \$1817 $ternary$libresoc.v:42425$1833_Y + connect \$182 $and$libresoc.v:42426$1834_Y + connect \$181 $reduce_or$libresoc.v:42427$1835_Y + connect \$186 $and$libresoc.v:42428$1836_Y + connect \$185 $reduce_or$libresoc.v:42429$1837_Y + connect \$190 $and$libresoc.v:42430$1838_Y + connect \$189 $reduce_or$libresoc.v:42431$1839_Y + connect \$194 $and$libresoc.v:42432$1840_Y + connect \$193 $reduce_or$libresoc.v:42433$1841_Y + connect \$198 $and$libresoc.v:42434$1842_Y + connect \$197 $reduce_or$libresoc.v:42435$1843_Y + connect \$202 $and$libresoc.v:42436$1844_Y + connect \$201 $reduce_or$libresoc.v:42437$1845_Y + connect \$206 $and$libresoc.v:42438$1846_Y + connect \$205 $reduce_or$libresoc.v:42439$1847_Y + connect \$210 $and$libresoc.v:42440$1848_Y + connect \$209 $reduce_or$libresoc.v:42441$1849_Y + connect \$214 $and$libresoc.v:42442$1850_Y + connect \$213 $reduce_or$libresoc.v:42443$1851_Y + connect \$218 $and$libresoc.v:42444$1852_Y + connect \$217 $reduce_or$libresoc.v:42445$1853_Y + connect \$221 $ne$libresoc.v:42446$1854_Y + connect \$224 $sub$libresoc.v:42447$1855_Y + connect \$226 $ne$libresoc.v:42448$1856_Y + connect \$229 $and$libresoc.v:42449$1857_Y + connect \$231 $and$libresoc.v:42450$1858_Y + connect \$233 $eq$libresoc.v:42451$1859_Y + connect \$235 $or$libresoc.v:42452$1860_Y + connect \$237 $and$libresoc.v:42453$1861_Y + connect \$239 $or$libresoc.v:42454$1862_Y + connect \$241 $eq$libresoc.v:42455$1863_Y + connect \$243 $and$libresoc.v:42456$1864_Y + connect \$245 $eq$libresoc.v:42457$1865_Y + connect \$247 $or$libresoc.v:42458$1866_Y + connect \$228 $not$libresoc.v:42459$1867_Y + connect \$250 $not$libresoc.v:42460$1868_Y + connect \$252 $not$libresoc.v:42461$1869_Y + connect \$254 $not$libresoc.v:42462$1870_Y + connect \$257 $and$libresoc.v:42463$1871_Y + connect \$259 $and$libresoc.v:42464$1872_Y + connect \$261 $eq$libresoc.v:42465$1873_Y + connect \$263 $or$libresoc.v:42466$1874_Y + connect \$265 $and$libresoc.v:42467$1875_Y + connect \$267 $or$libresoc.v:42468$1876_Y + connect \$256 $not$libresoc.v:42469$1877_Y + connect \$271 $and$libresoc.v:42470$1878_Y + connect \$273 $and$libresoc.v:42471$1879_Y + connect \$275 $eq$libresoc.v:42472$1880_Y + connect \$277 $or$libresoc.v:42473$1881_Y + connect \$279 $and$libresoc.v:42474$1882_Y + connect \$281 $or$libresoc.v:42475$1883_Y + connect \$283 $and$libresoc.v:42476$1884_Y + connect \$285 $and$libresoc.v:42477$1885_Y + connect \$287 $eq$libresoc.v:42478$1886_Y + connect \$289 $or$libresoc.v:42479$1887_Y + connect \$291 $eq$libresoc.v:42480$1888_Y + connect \$293 $and$libresoc.v:42481$1889_Y + connect \$295 $eq$libresoc.v:42482$1890_Y + connect \$297 $or$libresoc.v:42483$1891_Y + connect \$270 $not$libresoc.v:42484$1892_Y + connect \$301 $and$libresoc.v:42485$1893_Y + connect \$303 $and$libresoc.v:42486$1894_Y + connect \$305 $eq$libresoc.v:42487$1895_Y + connect \$307 $or$libresoc.v:42488$1896_Y + connect \$309 $and$libresoc.v:42489$1897_Y + connect \$311 $or$libresoc.v:42490$1898_Y + connect \$300 $not$libresoc.v:42491$1899_Y + connect \$315 $and$libresoc.v:42492$1900_Y + connect \$317 $and$libresoc.v:42493$1901_Y + connect \$319 $eq$libresoc.v:42494$1902_Y + connect \$321 $or$libresoc.v:42495$1903_Y + connect \$323 $and$libresoc.v:42496$1904_Y + connect \$325 $or$libresoc.v:42497$1905_Y + connect \$314 $not$libresoc.v:42498$1906_Y + connect \$329 $and$libresoc.v:42499$1907_Y + connect \$331 $and$libresoc.v:42500$1908_Y + connect \$333 $eq$libresoc.v:42501$1909_Y + connect \$335 $or$libresoc.v:42502$1910_Y + connect \$337 $and$libresoc.v:42503$1911_Y + connect \$339 $or$libresoc.v:42504$1912_Y + connect \$341 $eq$libresoc.v:42505$1913_Y + connect \$343 $and$libresoc.v:42506$1914_Y + connect \$345 $eq$libresoc.v:42507$1915_Y + connect \$347 $or$libresoc.v:42508$1916_Y + connect \$328 $not$libresoc.v:42509$1917_Y + connect \$350 $not$libresoc.v:42510$1918_Y + connect \$352 $and$libresoc.v:42511$1919_Y + connect \$354 $and$libresoc.v:42512$1920_Y + connect \$356 $not$libresoc.v:42513$1921_Y + connect \$358 $and$libresoc.v:42514$1922_Y + connect \$360 $and$libresoc.v:42515$1923_Y + connect \$362 $ternary$libresoc.v:42516$1924_Y + connect \$364 $and$libresoc.v:42517$1925_Y + connect \$366 $and$libresoc.v:42518$1926_Y + connect \$368 $not$libresoc.v:42519$1927_Y + connect \$370 $and$libresoc.v:42520$1928_Y + connect \$372 $and$libresoc.v:42521$1929_Y + connect \$374 $ternary$libresoc.v:42522$1930_Y + connect \$376 $and$libresoc.v:42523$1931_Y + connect \$378 $and$libresoc.v:42524$1932_Y + connect \$380 $not$libresoc.v:42525$1933_Y + connect \$382 $and$libresoc.v:42526$1934_Y + connect \$384 $and$libresoc.v:42527$1935_Y + connect \$386 $ternary$libresoc.v:42528$1936_Y + connect \$388 $and$libresoc.v:42529$1937_Y + connect \$390 $and$libresoc.v:42530$1938_Y + connect \$392 $not$libresoc.v:42531$1939_Y + connect \$394 $and$libresoc.v:42532$1940_Y + connect \$396 $and$libresoc.v:42533$1941_Y + connect \$398 $ternary$libresoc.v:42534$1942_Y + connect \$400 $and$libresoc.v:42535$1943_Y + connect \$402 $and$libresoc.v:42536$1944_Y + connect \$404 $not$libresoc.v:42537$1945_Y + connect \$406 $and$libresoc.v:42538$1946_Y + connect \$408 $and$libresoc.v:42539$1947_Y + connect \$410 $ternary$libresoc.v:42540$1948_Y + connect \$412 $and$libresoc.v:42541$1949_Y + connect \$414 $and$libresoc.v:42542$1950_Y + connect \$416 $not$libresoc.v:42543$1951_Y + connect \$418 $and$libresoc.v:42544$1952_Y + connect \$420 $and$libresoc.v:42545$1953_Y + connect \$422 $ternary$libresoc.v:42546$1954_Y + connect \$424 $and$libresoc.v:42547$1955_Y + connect \$426 $and$libresoc.v:42548$1956_Y + connect \$428 $not$libresoc.v:42549$1957_Y + connect \$430 $and$libresoc.v:42550$1958_Y + connect \$432 $and$libresoc.v:42551$1959_Y + connect \$434 $ternary$libresoc.v:42552$1960_Y + connect \$436 $and$libresoc.v:42553$1961_Y + connect \$438 $and$libresoc.v:42554$1962_Y + connect \$440 $not$libresoc.v:42555$1963_Y + connect \$442 $and$libresoc.v:42556$1964_Y + connect \$444 $and$libresoc.v:42557$1965_Y + connect \$446 $ternary$libresoc.v:42558$1966_Y + connect \$448 $and$libresoc.v:42559$1967_Y + connect \$450 $and$libresoc.v:42560$1968_Y + connect \$452 $not$libresoc.v:42561$1969_Y + connect \$454 $and$libresoc.v:42562$1970_Y + connect \$456 $and$libresoc.v:42563$1971_Y + connect \$458 $ternary$libresoc.v:42564$1972_Y + connect \$461 $or$libresoc.v:42565$1973_Y + connect \$463 $or$libresoc.v:42566$1974_Y + connect \$465 $or$libresoc.v:42567$1975_Y + connect \$467 $or$libresoc.v:42568$1976_Y + connect \$469 $or$libresoc.v:42569$1977_Y + connect \$471 $or$libresoc.v:42570$1978_Y + connect \$473 $or$libresoc.v:42571$1979_Y + connect \$475 $or$libresoc.v:42572$1980_Y + connect \$477 $reduce_or$libresoc.v:42573$1981_Y + connect \$479 $and$libresoc.v:42574$1982_Y + connect \$481 $and$libresoc.v:42575$1983_Y + connect \$483 $not$libresoc.v:42576$1984_Y + connect \$485 $and$libresoc.v:42577$1985_Y + connect \$487 $and$libresoc.v:42578$1986_Y + connect \$489 $ternary$libresoc.v:42579$1987_Y + connect \$491 $and$libresoc.v:42580$1988_Y + connect \$493 $and$libresoc.v:42581$1989_Y + connect \$495 $not$libresoc.v:42582$1990_Y + connect \$497 $and$libresoc.v:42583$1991_Y + connect \$499 $and$libresoc.v:42584$1992_Y + connect \$501 $ternary$libresoc.v:42585$1993_Y + connect \$503 $and$libresoc.v:42586$1994_Y + connect \$505 $and$libresoc.v:42587$1995_Y + connect \$507 $not$libresoc.v:42588$1996_Y + connect \$509 $and$libresoc.v:42589$1997_Y + connect \$511 $and$libresoc.v:42590$1998_Y + connect \$513 $ternary$libresoc.v:42591$1999_Y + connect \$515 $and$libresoc.v:42592$2000_Y + connect \$517 $and$libresoc.v:42593$2001_Y + connect \$519 $not$libresoc.v:42594$2002_Y + connect \$521 $and$libresoc.v:42595$2003_Y + connect \$523 $and$libresoc.v:42596$2004_Y + connect \$525 $ternary$libresoc.v:42597$2005_Y + connect \$527 $and$libresoc.v:42598$2006_Y + connect \$529 $and$libresoc.v:42599$2007_Y + connect \$531 $not$libresoc.v:42600$2008_Y + connect \$533 $and$libresoc.v:42601$2009_Y + connect \$535 $and$libresoc.v:42602$2010_Y + connect \$537 $ternary$libresoc.v:42603$2011_Y + connect \$539 $and$libresoc.v:42604$2012_Y + connect \$541 $and$libresoc.v:42605$2013_Y + connect \$543 $not$libresoc.v:42606$2014_Y + connect \$545 $and$libresoc.v:42607$2015_Y + connect \$547 $and$libresoc.v:42608$2016_Y + connect \$549 $ternary$libresoc.v:42609$2017_Y + connect \$551 $and$libresoc.v:42610$2018_Y + connect \$553 $and$libresoc.v:42611$2019_Y + connect \$555 $not$libresoc.v:42612$2020_Y + connect \$557 $and$libresoc.v:42613$2021_Y + connect \$559 $and$libresoc.v:42614$2022_Y + connect \$561 $ternary$libresoc.v:42615$2023_Y + connect \$563 $and$libresoc.v:42616$2024_Y + connect \$565 $and$libresoc.v:42617$2025_Y + connect \$567 $not$libresoc.v:42618$2026_Y + connect \$569 $and$libresoc.v:42619$2027_Y + connect \$571 $and$libresoc.v:42620$2028_Y + connect \$573 $ternary$libresoc.v:42621$2029_Y + connect \$576 $or$libresoc.v:42622$2030_Y + connect \$578 $or$libresoc.v:42623$2031_Y + connect \$580 $or$libresoc.v:42624$2032_Y + connect \$582 $or$libresoc.v:42625$2033_Y + connect \$584 $or$libresoc.v:42626$2034_Y + connect \$586 $or$libresoc.v:42627$2035_Y + connect \$588 $or$libresoc.v:42628$2036_Y + connect \$590 $reduce_or$libresoc.v:42629$2037_Y + connect \$592 $and$libresoc.v:42630$2038_Y + connect \$594 $and$libresoc.v:42631$2039_Y + connect \$596 $not$libresoc.v:42632$2040_Y + connect \$598 $and$libresoc.v:42633$2041_Y + connect \$600 $and$libresoc.v:42634$2042_Y + connect \$602 $ternary$libresoc.v:42635$2043_Y + connect \$604 $and$libresoc.v:42636$2044_Y + connect \$606 $and$libresoc.v:42637$2045_Y + connect \$608 $not$libresoc.v:42638$2046_Y + connect \$610 $and$libresoc.v:42639$2047_Y + connect \$612 $and$libresoc.v:42640$2048_Y + connect \$614 $ternary$libresoc.v:42641$2049_Y + connect \$617 $or$libresoc.v:42642$2050_Y + connect \$619 $reduce_or$libresoc.v:42643$2051_Y + connect \$621 $and$libresoc.v:42644$2052_Y + connect \$623 $and$libresoc.v:42645$2053_Y + connect \$625 $eq$libresoc.v:42646$2054_Y + connect \$627 $or$libresoc.v:42647$2055_Y + connect \$629 $and$libresoc.v:42648$2056_Y + connect \$631 $or$libresoc.v:42649$2057_Y + connect \$633 $and$libresoc.v:42650$2058_Y + connect \$635 $and$libresoc.v:42651$2059_Y + connect \$637 $not$libresoc.v:42652$2060_Y + connect \$639 $and$libresoc.v:42653$2061_Y + connect \$641 $and$libresoc.v:42654$2062_Y + connect \$643 $ternary$libresoc.v:42655$2063_Y + connect \$645 $and$libresoc.v:42656$2064_Y + connect \$647 $and$libresoc.v:42657$2065_Y + connect \$649 $not$libresoc.v:42658$2066_Y + connect \$651 $and$libresoc.v:42659$2067_Y + connect \$653 $and$libresoc.v:42660$2068_Y + connect \$655 $ternary$libresoc.v:42661$2069_Y + connect \$657 $and$libresoc.v:42662$2070_Y + connect \$659 $and$libresoc.v:42663$2071_Y + connect \$661 $not$libresoc.v:42664$2072_Y + connect \$663 $and$libresoc.v:42665$2073_Y + connect \$665 $and$libresoc.v:42666$2074_Y + connect \$667 $ternary$libresoc.v:42667$2075_Y + connect \$669 $and$libresoc.v:42668$2076_Y + connect \$671 $and$libresoc.v:42669$2077_Y + connect \$673 $not$libresoc.v:42670$2078_Y + connect \$675 $and$libresoc.v:42671$2079_Y + connect \$677 $and$libresoc.v:42672$2080_Y + connect \$679 $ternary$libresoc.v:42673$2081_Y + connect \$681 $and$libresoc.v:42674$2082_Y + connect \$683 $and$libresoc.v:42675$2083_Y + connect \$685 $not$libresoc.v:42676$2084_Y + connect \$687 $and$libresoc.v:42677$2085_Y + connect \$689 $and$libresoc.v:42678$2086_Y + connect \$691 $ternary$libresoc.v:42679$2087_Y + connect \$693 $and$libresoc.v:42680$2088_Y + connect \$695 $and$libresoc.v:42681$2089_Y + connect \$697 $not$libresoc.v:42682$2090_Y + connect \$699 $and$libresoc.v:42683$2091_Y + connect \$701 $and$libresoc.v:42684$2092_Y + connect \$703 $ternary$libresoc.v:42685$2093_Y + connect \$706 $or$libresoc.v:42686$2094_Y + connect \$708 $or$libresoc.v:42687$2095_Y + connect \$710 $or$libresoc.v:42688$2096_Y + connect \$712 $or$libresoc.v:42689$2097_Y + connect \$714 $or$libresoc.v:42690$2098_Y + connect \$705 $pos$libresoc.v:42691$2100_Y + connect \$717 $eq$libresoc.v:42692$2101_Y + connect \$719 $and$libresoc.v:42693$2102_Y + connect \$721 $eq$libresoc.v:42694$2103_Y + connect \$723 $or$libresoc.v:42695$2104_Y + connect \$725 $and$libresoc.v:42696$2105_Y + connect \$727 $and$libresoc.v:42697$2106_Y + connect \$729 $not$libresoc.v:42698$2107_Y + connect \$731 $and$libresoc.v:42699$2108_Y + connect \$733 $and$libresoc.v:42700$2109_Y + connect \$735 $ternary$libresoc.v:42701$2110_Y + connect \$737 $and$libresoc.v:42702$2111_Y + connect \$739 $and$libresoc.v:42703$2112_Y + connect \$741 $not$libresoc.v:42704$2113_Y + connect \$743 $and$libresoc.v:42705$2114_Y + connect \$745 $and$libresoc.v:42706$2115_Y + connect \$747 $ternary$libresoc.v:42707$2116_Y + connect \$749 $and$libresoc.v:42708$2117_Y + connect \$751 $and$libresoc.v:42709$2118_Y + connect \$753 $not$libresoc.v:42710$2119_Y + connect \$755 $and$libresoc.v:42711$2120_Y + connect \$757 $and$libresoc.v:42712$2121_Y + connect \$759 $ternary$libresoc.v:42713$2122_Y + connect \$762 $or$libresoc.v:42714$2123_Y + connect \$764 $or$libresoc.v:42715$2124_Y + connect \$761 $pos$libresoc.v:42716$2126_Y + connect \$767 $and$libresoc.v:42717$2127_Y + connect \$769 $and$libresoc.v:42718$2128_Y + connect \$771 $eq$libresoc.v:42719$2129_Y + connect \$773 $or$libresoc.v:42720$2130_Y + connect \$775 $and$libresoc.v:42721$2131_Y + connect \$777 $and$libresoc.v:42722$2132_Y + connect \$779 $not$libresoc.v:42723$2133_Y + connect \$781 $and$libresoc.v:42724$2134_Y + connect \$783 $and$libresoc.v:42725$2135_Y + connect \$785 $ternary$libresoc.v:42726$2136_Y + connect \$787 $and$libresoc.v:42727$2137_Y + connect \$789 $and$libresoc.v:42728$2138_Y + connect \$791 $not$libresoc.v:42729$2139_Y + connect \$793 $and$libresoc.v:42730$2140_Y + connect \$795 $and$libresoc.v:42731$2141_Y + connect \$797 $ternary$libresoc.v:42732$2142_Y + connect \$799 $and$libresoc.v:42733$2143_Y + connect \$801 $and$libresoc.v:42734$2144_Y + connect \$803 $not$libresoc.v:42735$2145_Y + connect \$805 $and$libresoc.v:42736$2146_Y + connect \$807 $and$libresoc.v:42737$2147_Y + connect \$809 $sub$libresoc.v:42738$2148_Y + connect \$811 $sshl$libresoc.v:42739$2149_Y + connect \$813 $ternary$libresoc.v:42740$2150_Y + connect \$815 $and$libresoc.v:42741$2151_Y + connect \$817 $and$libresoc.v:42742$2152_Y + connect \$819 $not$libresoc.v:42743$2153_Y + connect \$821 $and$libresoc.v:42744$2154_Y + connect \$823 $and$libresoc.v:42745$2155_Y + connect \$825 $sub$libresoc.v:42746$2156_Y + connect \$827 $sshl$libresoc.v:42747$2157_Y + connect \$829 $ternary$libresoc.v:42748$2158_Y + connect \$832 $or$libresoc.v:42749$2159_Y + connect \$834 $and$libresoc.v:42750$2160_Y + connect \$836 $and$libresoc.v:42751$2161_Y + connect \$838 $not$libresoc.v:42752$2162_Y + connect \$840 $and$libresoc.v:42753$2163_Y + connect \$842 $and$libresoc.v:42754$2164_Y + connect \$844 $sub$libresoc.v:42755$2165_Y + connect \$846 $sshl$libresoc.v:42756$2166_Y + connect \$848 $ternary$libresoc.v:42757$2167_Y + connect \$850 $and$libresoc.v:42758$2168_Y + connect \$852 $and$libresoc.v:42759$2169_Y + connect \$854 $not$libresoc.v:42760$2170_Y + connect \$856 $and$libresoc.v:42761$2171_Y + connect \$858 $and$libresoc.v:42762$2172_Y + connect \$860 $sub$libresoc.v:42763$2173_Y + connect \$862 $sshl$libresoc.v:42764$2174_Y + connect \$864 $ternary$libresoc.v:42765$2175_Y + connect \$866 $and$libresoc.v:42766$2176_Y + connect \$868 $and$libresoc.v:42767$2177_Y + connect \$870 $not$libresoc.v:42768$2178_Y + connect \$872 $and$libresoc.v:42769$2179_Y + connect \$874 $and$libresoc.v:42770$2180_Y + connect \$876 $ternary$libresoc.v:42771$2181_Y + connect \$878 $and$libresoc.v:42772$2182_Y + connect \$880 $and$libresoc.v:42773$2183_Y + connect \$882 $not$libresoc.v:42774$2184_Y + connect \$884 $and$libresoc.v:42775$2185_Y + connect \$886 $and$libresoc.v:42776$2186_Y + connect \$888 $ternary$libresoc.v:42777$2187_Y + connect \$890 $and$libresoc.v:42778$2188_Y + connect \$892 $and$libresoc.v:42779$2189_Y + connect \$894 $not$libresoc.v:42780$2190_Y + connect \$896 $and$libresoc.v:42781$2191_Y + connect \$898 $and$libresoc.v:42782$2192_Y + connect \$900 $ternary$libresoc.v:42783$2193_Y + connect \$902 $or$libresoc.v:42784$2194_Y + connect \$904 $or$libresoc.v:42785$2195_Y + connect \$906 $reduce_or$libresoc.v:42786$2196_Y + connect \$908 $and$libresoc.v:42787$2197_Y + connect \$910 $and$libresoc.v:42788$2198_Y + connect \$912 $not$libresoc.v:42789$2199_Y + connect \$914 $and$libresoc.v:42790$2200_Y + connect \$916 $and$libresoc.v:42791$2201_Y + connect \$918 $ternary$libresoc.v:42792$2202_Y + connect \$920 $and$libresoc.v:42793$2203_Y + connect \$922 $and$libresoc.v:42794$2204_Y + connect \$924 $not$libresoc.v:42795$2205_Y + connect \$926 $and$libresoc.v:42796$2206_Y + connect \$928 $and$libresoc.v:42797$2207_Y + connect \$930 $ternary$libresoc.v:42798$2208_Y + connect \$932 $or$libresoc.v:42799$2209_Y + connect \$934 $reduce_or$libresoc.v:42800$2210_Y + connect \$936 $and$libresoc.v:42801$2211_Y + connect \$938 $and$libresoc.v:42802$2212_Y + connect \$940 $not$libresoc.v:42803$2213_Y + connect \$942 $and$libresoc.v:42804$2214_Y + connect \$944 $and$libresoc.v:42805$2215_Y + connect \$946 $ternary$libresoc.v:42806$2216_Y + connect \$948 $reduce_or$libresoc.v:42807$2217_Y + connect \$950 $and$libresoc.v:42808$2218_Y + connect \$952 $and$libresoc.v:42809$2219_Y + connect \$954 $and$libresoc.v:42810$2220_Y + connect \$956 $and$libresoc.v:42811$2221_Y + connect \$958 $and$libresoc.v:42812$2222_Y + connect \$960 $and$libresoc.v:42813$2223_Y + connect \$962 $and$libresoc.v:42814$2224_Y + connect \$964 $and$libresoc.v:42815$2225_Y + connect \$966 $and$libresoc.v:42816$2226_Y + connect \$968 $and$libresoc.v:42817$2227_Y + connect \$970 $and$libresoc.v:42818$2228_Y + connect \$972 $and$libresoc.v:42819$2229_Y + connect \$974 $not$libresoc.v:42820$2230_Y + connect \$976 $and$libresoc.v:42821$2231_Y + connect \$982 $and$libresoc.v:42822$2232_Y + connect \$984 $ternary$libresoc.v:42823$2233_Y + connect \$986 $and$libresoc.v:42824$2234_Y + connect \$989 $and$libresoc.v:42825$2235_Y + connect \$993 $not$libresoc.v:42826$2236_Y + connect \$995 $and$libresoc.v:42827$2237_Y + connect \$223 \$224 + connect \$460 \$475 + connect \$575 \$588 + connect \$616 \$617 + connect \$831 \$832 + connect \$1159 \$1176 + connect \$1178 \$1195 + connect \$1375 \$1384 connect \o_ok 1'0 connect \ea_ok 1'0 - connect \spr_spr1__wen \wp$1808 - connect \spr_spr1__addr$175 \addr_en$1811 [6:0] + connect \spr_spr1__wen \wp$1813 + connect \spr_spr1__addr$175 \addr_en$1816 [6:0] connect \spr_spr1__data_i \fus_dest2_o$162 - connect \addr_en$1811 \$1812 - connect \wp$1808 \$1809 - connect \wr_pick_rise$1054 \$1806 - connect \wr_pick$1800 \$1801 - connect \wrpick_SPR_spr1_i \$1798 - connect \wrflag_spr0_spr1_1 \$1796 - connect \state_wen \$1794 + connect \addr_en$1816 \$1817 + connect \wp$1813 \$1814 + connect \wr_pick_rise$1059 \$1811 + connect \wr_pick$1805 \$1806 + connect \wrpick_SPR_spr1_i \$1803 + connect \wrflag_spr0_spr1_1 \$1801 + connect \state_wen \$1799 connect \state_data_i$174 \fus_dest5_o$161 - connect \addr_en$1791 \$1792 - connect \wp$1788 \$1789 - connect \wr_pick_rise$1014 \$1786 - connect \wr_pick$1780 \$1781 - connect \wrpick_STATE_msr_i \$1778 - connect \wrflag_trap0_msr_4 \$1776 - connect \state_nia_wen \$1772 - connect \state_data_i \$1770 - connect \addr_en$1767 \$1768 - connect \wp$1764 \$1765 - connect \wr_pick_rise$1013 \$1762 - connect \wr_pick$1756 \$1757 - connect \wrflag_trap0_nia_3 \$1754 - connect \addr_en$1751 \$1752 - connect \wp$1748 \$1749 - connect \wr_pick_rise$1639 \$1746 - connect \wr_pick$1740 \$1741 - connect \wrpick_STATE_nia_i [1] \$1738 - connect \wrpick_STATE_nia_i [0] \$1736 - connect \wrflag_branch0_nia_2 \$1734 - connect \fast_dest1__wen \$1732 - connect \fast_dest1__addr \$1724 - connect \fast_dest1__data_i \$1716 - connect \addr_en$1707 \$1708 - connect \wp$1704 \$1705 - connect \wr_pick_rise$1012 \$1702 - connect \wr_pick$1696 \$1697 - connect \wrflag_trap0_fast1_2 \$1694 - connect \addr_en$1691 \$1692 - connect \wp$1688 \$1689 - connect \wr_pick_rise$1638 \$1686 - connect \wr_pick$1680 \$1681 - connect \wrflag_branch0_fast1_1 \$1678 - connect \addr_en$1675 \$1676 - connect \wp$1672 \$1673 - connect \wr_pick_rise$1053 \$1670 - connect \wr_pick$1664 \$1665 - connect \wrflag_spr0_fast1_2 \$1662 - connect \addr_en$1659 \$1660 - connect \wp$1656 \$1657 - connect \wr_pick_rise$1011 \$1654 - connect \wr_pick$1648 \$1649 - connect \wrflag_trap0_fast1_1 \$1646 - connect \addr_en$1643 \$1644 - connect \wp$1640 \$1641 - connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1639 - connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1638 - connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1633 - connect \wr_pick_rise$1633 \$1636 - connect \wr_pick$1629 \$1630 - connect \wrpick_FAST_fast1_i [4] \$1627 - connect \wrpick_FAST_fast1_i [3] \$1625 - connect \wrpick_FAST_fast1_i [2] \$1623 - connect \wrpick_FAST_fast1_i [1] \$1621 - connect \wrpick_FAST_fast1_i [0] \$1619 - connect \wrflag_branch0_fast1_0 \$1617 - connect \xer_wen$173 \$1609 - connect \xer_data_i$172 \$1601 - connect \addr_en$1598 \$1599 - connect \wp$1595 \$1596 - connect \wr_pick_rise$1094 \$1593 - connect \wr_pick$1587 \$1588 - connect \wrflag_mul0_xer_so_3 \$1585 - connect \addr_en$1582 \$1583 - connect \wp$1579 \$1580 - connect \wr_pick_rise$1074 \$1577 - connect \wr_pick$1571 \$1572 - connect \wrflag_div0_xer_so_3 \$1569 - connect \addr_en$1566 \$1567 - connect \wp$1563 \$1564 - connect \wr_pick_rise$1052 \$1561 - connect \wr_pick$1555 \$1556 - connect \wrflag_spr0_xer_so_3 \$1553 - connect \addr_en$1550 \$1551 - connect \wp$1547 \$1548 - connect \wr_pick_rise$976 \$1545 - connect \wr_pick$1539 \$1540 - connect \wrpick_XER_xer_so_i [3] \$1537 - connect \wrpick_XER_xer_so_i [2] \$1535 - connect \wrpick_XER_xer_so_i [1] \$1533 - connect \wrpick_XER_xer_so_i [0] \$1531 - connect \wrflag_alu0_xer_so_4 \$1529 - connect \xer_wen$171 \$1527 - connect \xer_data_i$170 \$1521 - connect \addr_en$1514 \$1515 - connect \wp$1511 \$1512 - connect \wr_pick_rise$1093 \$1509 - connect \wr_pick$1503 \$1504 - connect \wrflag_mul0_xer_ov_2 \$1501 - connect \addr_en$1498 \$1499 - connect \wp$1495 \$1496 - connect \wr_pick_rise$1073 \$1493 - connect \wr_pick$1487 \$1488 - connect \wrflag_div0_xer_ov_2 \$1485 - connect \addr_en$1482 \$1483 - connect \wp$1479 \$1480 - connect \wr_pick_rise$1051 \$1477 - connect \wr_pick$1471 \$1472 - connect \wrflag_spr0_xer_ov_4 \$1469 - connect \addr_en$1466 \$1467 - connect \wp$1463 \$1464 - connect \wr_pick_rise$975 \$1461 - connect \wr_pick$1455 \$1456 - connect \wrpick_XER_xer_ov_i [3] \$1453 - connect \wrpick_XER_xer_ov_i [2] \$1451 - connect \wrpick_XER_xer_ov_i [1] \$1449 - connect \wrpick_XER_xer_ov_i [0] \$1447 - connect \wrflag_alu0_xer_ov_3 \$1445 - connect \xer_wen \$1439 - connect \xer_data_i \$1437 - connect \addr_en$1432 \$1433 - connect \wp$1429 \$1430 - connect \wr_pick_rise$1113 \$1427 - connect \wr_pick$1421 \$1422 - connect \wrflag_shiftrot0_xer_ca_2 \$1419 - connect \addr_en$1416 \$1417 - connect \wp$1413 \$1414 - connect \wr_pick_rise$1050 \$1411 - connect \wr_pick$1405 \$1406 - connect \wrflag_spr0_xer_ca_5 \$1403 - connect \addr_en$1400 \$1401 - connect \wp$1397 \$1398 - connect \wr_pick_rise$974 \$1395 - connect \wr_pick$1389 \$1390 - connect \wrpick_XER_xer_ca_i [2] \$1387 - connect \wrpick_XER_xer_ca_i [1] \$1385 - connect \wrpick_XER_xer_ca_i [0] \$1383 - connect \wrflag_alu0_xer_ca_2 \$1381 - connect \cr_wen \$1379 [7:0] - connect \cr_data_i \$1368 - connect \addr_en$1353 \$1358 - connect \wp$1350 \$1351 - connect \wr_pick_rise$1112 \$1348 - connect \wr_pick$1342 \$1343 - connect \wrflag_shiftrot0_cr_a_1 \$1340 - connect \addr_en$1333 \$1338 - connect \wp$1330 \$1331 - connect \wr_pick_rise$1092 \$1328 - connect \wr_pick$1322 \$1323 - connect \wrflag_mul0_cr_a_1 \$1320 - connect \addr_en$1313 \$1318 - connect \wp$1310 \$1311 - connect \wr_pick_rise$1072 \$1308 - connect \wr_pick$1302 \$1303 - connect \wrflag_div0_cr_a_1 \$1300 - connect \addr_en$1293 \$1298 - connect \wp$1290 \$1291 - connect \wr_pick_rise$1032 \$1288 - connect \wr_pick$1282 \$1283 - connect \wrflag_logical0_cr_a_1 \$1280 - connect \addr_en$1273 \$1278 - connect \wp$1270 \$1271 - connect \wr_pick_rise$993 \$1268 - connect \wr_pick$1262 \$1263 - connect \wrflag_cr0_cr_a_2 \$1260 - connect \addr_en$1253 \$1258 - connect \wp$1250 \$1251 - connect \wr_pick_rise$973 \$1248 - connect \wr_pick$1242 \$1243 - connect \wrpick_CR_cr_a_i [5] \$1240 - connect \wrpick_CR_cr_a_i [4] \$1238 - connect \wrpick_CR_cr_a_i [3] \$1236 - connect \wrpick_CR_cr_a_i [2] \$1234 - connect \wrpick_CR_cr_a_i [1] \$1232 - connect \wrpick_CR_cr_a_i [0] \$1230 - connect \wrflag_alu0_cr_a_1 \$1228 - connect \cr_full_wr__wen \addr_en$1225 + connect \addr_en$1796 \$1797 + connect \wp$1793 \$1794 + connect \wr_pick_rise$1019 \$1791 + connect \wr_pick$1785 \$1786 + connect \wrpick_STATE_msr_i \$1783 + connect \wrflag_trap0_msr_4 \$1781 + connect \state_nia_wen \$1777 + connect \state_data_i \$1775 + connect \addr_en$1772 \$1773 + connect \wp$1769 \$1770 + connect \wr_pick_rise$1018 \$1767 + connect \wr_pick$1761 \$1762 + connect \wrflag_trap0_nia_3 \$1759 + connect \addr_en$1756 \$1757 + connect \wp$1753 \$1754 + connect \wr_pick_rise$1644 \$1751 + connect \wr_pick$1745 \$1746 + connect \wrpick_STATE_nia_i [1] \$1743 + connect \wrpick_STATE_nia_i [0] \$1741 + connect \wrflag_branch0_nia_2 \$1739 + connect \fast_dest1__wen \$1737 + connect \fast_dest1__addr \$1729 + connect \fast_dest1__data_i \$1721 + connect \addr_en$1712 \$1713 + connect \wp$1709 \$1710 + connect \wr_pick_rise$1017 \$1707 + connect \wr_pick$1701 \$1702 + connect \wrflag_trap0_fast1_2 \$1699 + connect \addr_en$1696 \$1697 + connect \wp$1693 \$1694 + connect \wr_pick_rise$1643 \$1691 + connect \wr_pick$1685 \$1686 + connect \wrflag_branch0_fast1_1 \$1683 + connect \addr_en$1680 \$1681 + connect \wp$1677 \$1678 + connect \wr_pick_rise$1058 \$1675 + connect \wr_pick$1669 \$1670 + connect \wrflag_spr0_fast1_2 \$1667 + connect \addr_en$1664 \$1665 + connect \wp$1661 \$1662 + connect \wr_pick_rise$1016 \$1659 + connect \wr_pick$1653 \$1654 + connect \wrflag_trap0_fast1_1 \$1651 + connect \addr_en$1648 \$1649 + connect \wp$1645 \$1646 + connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1644 + connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1643 + connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1638 + connect \wr_pick_rise$1638 \$1641 + connect \wr_pick$1634 \$1635 + connect \wrpick_FAST_fast1_i [4] \$1632 + connect \wrpick_FAST_fast1_i [3] \$1630 + connect \wrpick_FAST_fast1_i [2] \$1628 + connect \wrpick_FAST_fast1_i [1] \$1626 + connect \wrpick_FAST_fast1_i [0] \$1624 + connect \wrflag_branch0_fast1_0 \$1622 + connect \xer_wen$173 \$1614 + connect \xer_data_i$172 \$1606 + connect \addr_en$1603 \$1604 + connect \wp$1600 \$1601 + connect \wr_pick_rise$1099 \$1598 + connect \wr_pick$1592 \$1593 + connect \wrflag_mul0_xer_so_3 \$1590 + connect \addr_en$1587 \$1588 + connect \wp$1584 \$1585 + connect \wr_pick_rise$1079 \$1582 + connect \wr_pick$1576 \$1577 + connect \wrflag_div0_xer_so_3 \$1574 + connect \addr_en$1571 \$1572 + connect \wp$1568 \$1569 + connect \wr_pick_rise$1057 \$1566 + connect \wr_pick$1560 \$1561 + connect \wrflag_spr0_xer_so_3 \$1558 + connect \addr_en$1555 \$1556 + connect \wp$1552 \$1553 + connect \wr_pick_rise$981 \$1550 + connect \wr_pick$1544 \$1545 + connect \wrpick_XER_xer_so_i [3] \$1542 + connect \wrpick_XER_xer_so_i [2] \$1540 + connect \wrpick_XER_xer_so_i [1] \$1538 + connect \wrpick_XER_xer_so_i [0] \$1536 + connect \wrflag_alu0_xer_so_4 \$1534 + connect \xer_wen$171 \$1532 + connect \xer_data_i$170 \$1526 + connect \addr_en$1519 \$1520 + connect \wp$1516 \$1517 + connect \wr_pick_rise$1098 \$1514 + connect \wr_pick$1508 \$1509 + connect \wrflag_mul0_xer_ov_2 \$1506 + connect \addr_en$1503 \$1504 + connect \wp$1500 \$1501 + connect \wr_pick_rise$1078 \$1498 + connect \wr_pick$1492 \$1493 + connect \wrflag_div0_xer_ov_2 \$1490 + connect \addr_en$1487 \$1488 + connect \wp$1484 \$1485 + connect \wr_pick_rise$1056 \$1482 + connect \wr_pick$1476 \$1477 + connect \wrflag_spr0_xer_ov_4 \$1474 + connect \addr_en$1471 \$1472 + connect \wp$1468 \$1469 + connect \wr_pick_rise$980 \$1466 + connect \wr_pick$1460 \$1461 + connect \wrpick_XER_xer_ov_i [3] \$1458 + connect \wrpick_XER_xer_ov_i [2] \$1456 + connect \wrpick_XER_xer_ov_i [1] \$1454 + connect \wrpick_XER_xer_ov_i [0] \$1452 + connect \wrflag_alu0_xer_ov_3 \$1450 + connect \xer_wen \$1444 + connect \xer_data_i \$1442 + connect \addr_en$1437 \$1438 + connect \wp$1434 \$1435 + connect \wr_pick_rise$1118 \$1432 + connect \wr_pick$1426 \$1427 + connect \wrflag_shiftrot0_xer_ca_2 \$1424 + connect \addr_en$1421 \$1422 + connect \wp$1418 \$1419 + connect \wr_pick_rise$1055 \$1416 + connect \wr_pick$1410 \$1411 + connect \wrflag_spr0_xer_ca_5 \$1408 + connect \addr_en$1405 \$1406 + connect \wp$1402 \$1403 + connect \wr_pick_rise$979 \$1400 + connect \wr_pick$1394 \$1395 + connect \wrpick_XER_xer_ca_i [2] \$1392 + connect \wrpick_XER_xer_ca_i [1] \$1390 + connect \wrpick_XER_xer_ca_i [0] \$1388 + connect \wrflag_alu0_xer_ca_2 \$1386 + connect \cr_wen \$1384 [7:0] + connect \cr_data_i \$1373 + connect \addr_en$1358 \$1363 + connect \wp$1355 \$1356 + connect \wr_pick_rise$1117 \$1353 + connect \wr_pick$1347 \$1348 + connect \wrflag_shiftrot0_cr_a_1 \$1345 + connect \addr_en$1338 \$1343 + connect \wp$1335 \$1336 + connect \wr_pick_rise$1097 \$1333 + connect \wr_pick$1327 \$1328 + connect \wrflag_mul0_cr_a_1 \$1325 + connect \addr_en$1318 \$1323 + connect \wp$1315 \$1316 + connect \wr_pick_rise$1077 \$1313 + connect \wr_pick$1307 \$1308 + connect \wrflag_div0_cr_a_1 \$1305 + connect \addr_en$1298 \$1303 + connect \wp$1295 \$1296 + connect \wr_pick_rise$1037 \$1293 + connect \wr_pick$1287 \$1288 + connect \wrflag_logical0_cr_a_1 \$1285 + connect \addr_en$1278 \$1283 + connect \wp$1275 \$1276 + connect \wr_pick_rise$998 \$1273 + connect \wr_pick$1267 \$1268 + connect \wrflag_cr0_cr_a_2 \$1265 + connect \addr_en$1258 \$1263 + connect \wp$1255 \$1256 + connect \wr_pick_rise$978 \$1253 + connect \wr_pick$1247 \$1248 + connect \wrpick_CR_cr_a_i [5] \$1245 + connect \wrpick_CR_cr_a_i [4] \$1243 + connect \wrpick_CR_cr_a_i [3] \$1241 + connect \wrpick_CR_cr_a_i [2] \$1239 + connect \wrpick_CR_cr_a_i [1] \$1237 + connect \wrpick_CR_cr_a_i [0] \$1235 + connect \wrflag_alu0_cr_a_1 \$1233 + connect \cr_full_wr__wen \addr_en$1230 connect \cr_full_wr__data_i \fus_dest2_o - connect \addr_en$1225 \$1226 - connect \wp$1222 \$1223 - connect \wr_pick_rise$992 \$1220 - connect \wr_pick$1214 \$1215 - connect \wrpick_CR_full_cr_i \$1212 - connect \wrflag_cr0_full_cr_1 \$1210 - connect \int_dest1__wen \$1208 - connect \int_dest1__addr \$1190 [4:0] - connect \int_dest1__data_i \$1171 [63:0] - connect \addr_en$1151 \$1152 - connect \wp$1148 \$1149 - connect \wr_pick_rise$1131 \$1146 - connect \wr_pick$1140 \$1141 - connect \wrflag_ldst0_o_1 \$1138 - connect \addr_en$1135 \$1136 - connect \wp$1132 \$1133 - connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1131 - connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1126 - connect \wr_pick_rise$1126 \$1129 - connect \wr_pick$1122 \$1123 - connect \wrflag_ldst0_o_0 \$1120 - connect \addr_en$1117 \$1118 - connect \wp$1114 \$1115 - connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1113 - connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1112 - connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1107 - connect \wr_pick_rise$1107 \$1110 - connect \wr_pick$1103 \$1104 - connect \wrflag_shiftrot0_o_0 \$1101 - connect \addr_en$1098 \$1099 - connect \wp$1095 \$1096 - connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1094 - connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1093 - connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1092 - connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1087 - connect \wr_pick_rise$1087 \$1090 - connect \wr_pick$1083 \$1084 - connect \wrflag_mul0_o_0 \$1081 - connect \addr_en$1078 \$1079 - connect \wp$1075 \$1076 - connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1074 - connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1073 - connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1072 - connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1067 - connect \wr_pick_rise$1067 \$1070 - connect \wr_pick$1063 \$1064 - connect \wrflag_div0_o_0 \$1061 - connect \addr_en$1058 \$1059 - connect \wp$1055 \$1056 - connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1054 - connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1053 - connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1052 - connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1051 - connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1050 - connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1045 - connect \wr_pick_rise$1045 \$1048 - connect \wr_pick$1041 \$1042 - connect \wrflag_spr0_o_0 \$1039 - connect \addr_en$1036 \$1037 - connect \wp$1033 \$1034 - connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1032 - connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1027 - connect \wr_pick_rise$1027 \$1030 - connect \wr_pick$1023 \$1024 - connect \wrflag_logical0_o_0 \$1021 - connect \addr_en$1018 \$1019 - connect \wp$1015 \$1016 - connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1014 - connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1013 - connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1012 - connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1011 - connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1006 - connect \wr_pick_rise$1006 \$1009 - connect \wr_pick$1002 \$1003 - connect \wrflag_trap0_o_0 \$1000 - connect \addr_en$997 \$998 - connect \wp$994 \$995 - connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$993 - connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$992 - connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$987 - connect \wr_pick_rise$987 \$990 - connect \wr_pick$983 \$984 - connect \wrflag_cr0_o_0 \$981 - connect \addr_en \$979 - connect \wp \$977 - connect \fus_cu_wr__go_i [4] \wr_pick_rise$976 - connect \fus_cu_wr__go_i [3] \wr_pick_rise$975 - connect \fus_cu_wr__go_i [2] \wr_pick_rise$974 - connect \fus_cu_wr__go_i [1] \wr_pick_rise$973 + connect \addr_en$1230 \$1231 + connect \wp$1227 \$1228 + connect \wr_pick_rise$997 \$1225 + connect \wr_pick$1219 \$1220 + connect \wrpick_CR_full_cr_i \$1217 + connect \wrflag_cr0_full_cr_1 \$1215 + connect \int_dest1__wen \$1213 + connect \int_dest1__addr \$1195 [4:0] + connect \int_dest1__data_i \$1176 [63:0] + connect \addr_en$1156 \$1157 + connect \wp$1153 \$1154 + connect \wr_pick_rise$1136 \$1151 + connect \wr_pick$1145 \$1146 + connect \wrflag_ldst0_o_1 \$1143 + connect \addr_en$1140 \$1141 + connect \wp$1137 \$1138 + connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1136 + connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1131 + connect \wr_pick_rise$1131 \$1134 + connect \wr_pick$1127 \$1128 + connect \wrflag_ldst0_o_0 \$1125 + connect \addr_en$1122 \$1123 + connect \wp$1119 \$1120 + connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1118 + connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1117 + connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1112 + connect \wr_pick_rise$1112 \$1115 + connect \wr_pick$1108 \$1109 + connect \wrflag_shiftrot0_o_0 \$1106 + connect \addr_en$1103 \$1104 + connect \wp$1100 \$1101 + connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1099 + connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1098 + connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1097 + connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1092 + connect \wr_pick_rise$1092 \$1095 + connect \wr_pick$1088 \$1089 + connect \wrflag_mul0_o_0 \$1086 + connect \addr_en$1083 \$1084 + connect \wp$1080 \$1081 + connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1079 + connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1078 + connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1077 + connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1072 + connect \wr_pick_rise$1072 \$1075 + connect \wr_pick$1068 \$1069 + connect \wrflag_div0_o_0 \$1066 + connect \addr_en$1063 \$1064 + connect \wp$1060 \$1061 + connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1059 + connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1058 + connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1057 + connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1056 + connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1055 + connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1050 + connect \wr_pick_rise$1050 \$1053 + connect \wr_pick$1046 \$1047 + connect \wrflag_spr0_o_0 \$1044 + connect \addr_en$1041 \$1042 + connect \wp$1038 \$1039 + connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1037 + connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1032 + connect \wr_pick_rise$1032 \$1035 + connect \wr_pick$1028 \$1029 + connect \wrflag_logical0_o_0 \$1026 + connect \addr_en$1023 \$1024 + connect \wp$1020 \$1021 + connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1019 + connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1018 + connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1017 + connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1016 + connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1011 + connect \wr_pick_rise$1011 \$1014 + connect \wr_pick$1007 \$1008 + connect \wrflag_trap0_o_0 \$1005 + connect \addr_en$1002 \$1003 + connect \wp$999 \$1000 + connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$998 + connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$997 + connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$992 + connect \wr_pick_rise$992 \$995 + connect \wr_pick$988 \$989 + connect \wrflag_cr0_o_0 \$986 + connect \addr_en \$984 + connect \wp \$982 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$981 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$980 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$979 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$978 connect \fus_cu_wr__go_i [0] \wr_pick_rise - connect \wr_pick_rise \$971 - connect \wr_pick \$967 - connect \wrpick_INT_o_i [9] \$965 - connect \wrpick_INT_o_i [8] \$963 - connect \wrpick_INT_o_i [7] \$961 - connect \wrpick_INT_o_i [6] \$959 - connect \wrpick_INT_o_i [5] \$957 - connect \wrpick_INT_o_i [4] \$955 - connect \wrpick_INT_o_i [3] \$953 - connect \wrpick_INT_o_i [2] \$951 - connect \wrpick_INT_o_i [1] \$949 - connect \wrpick_INT_o_i [0] \$947 - connect \wrflag_alu0_o_0 \$945 - connect \spr_spr1__ren \$943 + connect \wr_pick_rise \$976 + connect \wr_pick \$972 + connect \wrpick_INT_o_i [9] \$970 + connect \wrpick_INT_o_i [8] \$968 + connect \wrpick_INT_o_i [7] \$966 + connect \wrpick_INT_o_i [6] \$964 + connect \wrpick_INT_o_i [5] \$962 + connect \wrpick_INT_o_i [4] \$960 + connect \wrpick_INT_o_i [3] \$958 + connect \wrpick_INT_o_i [2] \$956 + connect \wrpick_INT_o_i [1] \$954 + connect \wrpick_INT_o_i [0] \$952 + connect \wrflag_alu0_o_0 \$950 + connect \spr_spr1__ren \$948 connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] - connect \addr_en_SPR_spr1_spr0_0 \$941 - connect \rp_SPR_spr1_spr0_0 \$939 + connect \addr_en_SPR_spr1_spr0_0 \$946 + connect \rp_SPR_spr1_spr0_0 \$944 connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 - connect \pick_SPR_spr1_spr0_0 \$937 + connect \pick_SPR_spr1_spr0_0 \$942 connect \rdflag_SPR_spr1_0 \core_spr1_ok - connect \fast_src2__ren \$929 - connect \fast_src2__addr \$927 - connect \addr_en_FAST_fast2_trap0_1 \$925 - connect \rp_FAST_fast2_trap0_1 \$923 - connect \pick_FAST_fast2_trap0_1 \$921 - connect \addr_en_FAST_fast2_branch0_0 \$913 - connect \rp_FAST_fast2_branch0_0 \$911 + connect \fast_src2__ren \$934 + connect \fast_src2__addr \$932 + connect \addr_en_FAST_fast2_trap0_1 \$930 + connect \rp_FAST_fast2_trap0_1 \$928 + connect \pick_FAST_fast2_trap0_1 \$926 + connect \addr_en_FAST_fast2_branch0_0 \$918 + connect \rp_FAST_fast2_branch0_0 \$916 connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 - connect \pick_FAST_fast2_branch0_0 \$909 + connect \pick_FAST_fast2_branch0_0 \$914 connect \rdflag_FAST_fast2_0 \core_fast2_ok - connect \fast_src1__ren \$901 - connect \fast_src1__addr \$899 - connect \addr_en_FAST_fast1_spr0_2 \$895 - connect \rp_FAST_fast1_spr0_2 \$893 - connect \pick_FAST_fast1_spr0_2 \$891 - connect \addr_en_FAST_fast1_trap0_1 \$883 - connect \rp_FAST_fast1_trap0_1 \$881 - connect \pick_FAST_fast1_trap0_1 \$879 - connect \addr_en_FAST_fast1_branch0_0 \$871 - connect \rp_FAST_fast1_branch0_0 \$869 + connect \fast_src1__ren \$906 + connect \fast_src1__addr \$904 + connect \addr_en_FAST_fast1_spr0_2 \$900 + connect \rp_FAST_fast1_spr0_2 \$898 + connect \pick_FAST_fast1_spr0_2 \$896 + connect \addr_en_FAST_fast1_trap0_1 \$888 + connect \rp_FAST_fast1_trap0_1 \$886 + connect \pick_FAST_fast1_trap0_1 \$884 + connect \addr_en_FAST_fast1_branch0_0 \$876 + connect \rp_FAST_fast1_branch0_0 \$874 connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 - connect \pick_FAST_fast1_branch0_0 \$867 + connect \pick_FAST_fast1_branch0_0 \$872 connect \rdflag_FAST_fast1_0 \core_fast1_ok connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] - connect \addr_en_CR_cr_c_cr0_0 \$859 - connect \rp_CR_cr_c_cr0_0 \$853 + connect \addr_en_CR_cr_c_cr0_0 \$864 + connect \rp_CR_cr_c_cr0_0 \$858 connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 - connect \pick_CR_cr_c_cr0_0 \$851 + connect \pick_CR_cr_c_cr0_0 \$856 connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] - connect \addr_en_CR_cr_b_cr0_0 \$843 - connect \rp_CR_cr_b_cr0_0 \$837 + connect \addr_en_CR_cr_b_cr0_0 \$848 + connect \rp_CR_cr_b_cr0_0 \$842 connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 - connect \pick_CR_cr_b_cr0_0 \$835 + connect \pick_CR_cr_b_cr0_0 \$840 connect \rdflag_CR_cr_b_0 \core_cr_in2_ok - connect \cr_src1__ren \$827 [7:0] - connect \addr_en_CR_cr_a_branch0_1 \$824 - connect \rp_CR_cr_a_branch0_1 \$818 + connect \cr_src1__ren \$832 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$829 + connect \rp_CR_cr_a_branch0_1 \$823 connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast2_branch0_0 connect \fus_cu_rd__go_i$82 [0] \dp_FAST_fast1_branch0_0 connect \fus_cu_rd__go_i$82 [2] \dp_CR_cr_a_branch0_1 - connect \pick_CR_cr_a_branch0_1 \$816 - connect \addr_en_CR_cr_a_cr0_0 \$808 - connect \rp_CR_cr_a_cr0_0 \$802 + connect \pick_CR_cr_a_branch0_1 \$821 + connect \addr_en_CR_cr_a_cr0_0 \$813 + connect \rp_CR_cr_a_cr0_0 \$807 connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 - connect \pick_CR_cr_a_cr0_0 \$800 + connect \pick_CR_cr_a_cr0_0 \$805 connect \rdflag_CR_cr_a_0 \core_cr_in1_ok connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 - connect \addr_en_CR_full_cr_cr0_0 \$792 - connect \rp_CR_full_cr_cr0_0 \$790 + connect \addr_en_CR_full_cr_cr0_0 \$797 + connect \rp_CR_full_cr_cr0_0 \$795 connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 - connect \pick_CR_full_cr_cr0_0 \$788 + connect \pick_CR_full_cr_cr0_0 \$793 connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 - connect \addr_en_XER_xer_ov_spr0_0 \$780 - connect \rp_XER_xer_ov_spr0_0 \$778 + connect \addr_en_XER_xer_ov_spr0_0 \$785 + connect \rp_XER_xer_ov_spr0_0 \$783 connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 - connect \pick_XER_xer_ov_spr0_0 \$776 - connect \rdflag_XER_xer_ov_0 \$768 - connect \xer_src2__ren \$756 - connect \addr_en_XER_xer_ca_shiftrot0_2 \$754 - connect \rp_XER_xer_ca_shiftrot0_2 \$752 - connect \pick_XER_xer_ca_shiftrot0_2 \$750 - connect \addr_en_XER_xer_ca_spr0_1 \$742 - connect \rp_XER_xer_ca_spr0_1 \$740 - connect \pick_XER_xer_ca_spr0_1 \$738 - connect \addr_en_XER_xer_ca_alu0_0 \$730 - connect \rp_XER_xer_ca_alu0_0 \$728 + connect \pick_XER_xer_ov_spr0_0 \$781 + connect \rdflag_XER_xer_ov_0 \$773 + connect \xer_src2__ren \$761 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$759 + connect \rp_XER_xer_ca_shiftrot0_2 \$757 + connect \pick_XER_xer_ca_shiftrot0_2 \$755 + connect \addr_en_XER_xer_ca_spr0_1 \$747 + connect \rp_XER_xer_ca_spr0_1 \$745 + connect \pick_XER_xer_ca_spr0_1 \$743 + connect \addr_en_XER_xer_ca_alu0_0 \$735 + connect \rp_XER_xer_ca_alu0_0 \$733 connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 - connect \pick_XER_xer_ca_alu0_0 \$726 - connect \rdflag_XER_xer_ca_0 \$718 - connect \xer_src1__ren \$700 - connect \addr_en_XER_xer_so_shiftrot0_5 \$698 - connect \rp_XER_xer_so_shiftrot0_5 \$696 - connect \pick_XER_xer_so_shiftrot0_5 \$694 - connect \addr_en_XER_xer_so_mul0_4 \$686 - connect \rp_XER_xer_so_mul0_4 \$684 - connect \pick_XER_xer_so_mul0_4 \$682 - connect \addr_en_XER_xer_so_div0_3 \$674 - connect \rp_XER_xer_so_div0_3 \$672 - connect \pick_XER_xer_so_div0_3 \$670 - connect \addr_en_XER_xer_so_spr0_2 \$662 - connect \rp_XER_xer_so_spr0_2 \$660 - connect \pick_XER_xer_so_spr0_2 \$658 - connect \addr_en_XER_xer_so_logical0_1 \$650 - connect \rp_XER_xer_so_logical0_1 \$648 - connect \pick_XER_xer_so_logical0_1 \$646 - connect \addr_en_XER_xer_so_alu0_0 \$638 - connect \rp_XER_xer_so_alu0_0 \$636 + connect \pick_XER_xer_ca_alu0_0 \$731 + connect \rdflag_XER_xer_ca_0 \$723 + connect \xer_src1__ren \$705 + connect \addr_en_XER_xer_so_shiftrot0_5 \$703 + connect \rp_XER_xer_so_shiftrot0_5 \$701 + connect \pick_XER_xer_so_shiftrot0_5 \$699 + connect \addr_en_XER_xer_so_mul0_4 \$691 + connect \rp_XER_xer_so_mul0_4 \$689 + connect \pick_XER_xer_so_mul0_4 \$687 + connect \addr_en_XER_xer_so_div0_3 \$679 + connect \rp_XER_xer_so_div0_3 \$677 + connect \pick_XER_xer_so_div0_3 \$675 + connect \addr_en_XER_xer_so_spr0_2 \$667 + connect \rp_XER_xer_so_spr0_2 \$665 + connect \pick_XER_xer_so_spr0_2 \$663 + connect \addr_en_XER_xer_so_logical0_1 \$655 + connect \rp_XER_xer_so_logical0_1 \$653 + connect \pick_XER_xer_so_logical0_1 \$651 + connect \addr_en_XER_xer_so_alu0_0 \$643 + connect \rp_XER_xer_so_alu0_0 \$641 connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 - connect \pick_XER_xer_so_alu0_0 \$634 - connect \rdflag_XER_xer_so_0 \$626 - connect \int_src3__ren \$614 - connect \int_src3__addr \$612 [4:0] - connect \addr_en_INT_rc_ldst0_1 \$609 - connect \rp_INT_rc_ldst0_1 \$607 - connect \pick_INT_rc_ldst0_1 \$605 - connect \addr_en_INT_rc_shiftrot0_0 \$597 - connect \rp_INT_rc_shiftrot0_0 \$595 + connect \pick_XER_xer_so_alu0_0 \$639 + connect \rdflag_XER_xer_so_0 \$631 + connect \int_src3__ren \$619 + connect \int_src3__addr \$617 [4:0] + connect \addr_en_INT_rc_ldst0_1 \$614 + connect \rp_INT_rc_ldst0_1 \$612 + connect \pick_INT_rc_ldst0_1 \$610 + connect \addr_en_INT_rc_shiftrot0_0 \$602 + connect \rp_INT_rc_shiftrot0_0 \$600 connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 - connect \pick_INT_rc_shiftrot0_0 \$593 + connect \pick_INT_rc_shiftrot0_0 \$598 connect \rdflag_INT_rc_0 \core_reg3_ok - connect \int_src2__ren \$585 - connect \int_src2__addr \$583 [4:0] - connect \addr_en_INT_rb_ldst0_7 \$568 - connect \rp_INT_rb_ldst0_7 \$566 - connect \pick_INT_rb_ldst0_7 \$564 - connect \addr_en_INT_rb_shiftrot0_6 \$556 - connect \rp_INT_rb_shiftrot0_6 \$554 - connect \pick_INT_rb_shiftrot0_6 \$552 - connect \addr_en_INT_rb_mul0_5 \$544 - connect \rp_INT_rb_mul0_5 \$542 - connect \pick_INT_rb_mul0_5 \$540 - connect \addr_en_INT_rb_div0_4 \$532 - connect \rp_INT_rb_div0_4 \$530 - connect \pick_INT_rb_div0_4 \$528 - connect \addr_en_INT_rb_logical0_3 \$520 - connect \rp_INT_rb_logical0_3 \$518 - connect \pick_INT_rb_logical0_3 \$516 - connect \addr_en_INT_rb_trap0_2 \$508 - connect \rp_INT_rb_trap0_2 \$506 - connect \pick_INT_rb_trap0_2 \$504 - connect \addr_en_INT_rb_cr0_1 \$496 - connect \rp_INT_rb_cr0_1 \$494 - connect \pick_INT_rb_cr0_1 \$492 - connect \addr_en_INT_rb_alu0_0 \$484 - connect \rp_INT_rb_alu0_0 \$482 + connect \int_src2__ren \$590 + connect \int_src2__addr \$588 [4:0] + connect \addr_en_INT_rb_ldst0_7 \$573 + connect \rp_INT_rb_ldst0_7 \$571 + connect \pick_INT_rb_ldst0_7 \$569 + connect \addr_en_INT_rb_shiftrot0_6 \$561 + connect \rp_INT_rb_shiftrot0_6 \$559 + connect \pick_INT_rb_shiftrot0_6 \$557 + connect \addr_en_INT_rb_mul0_5 \$549 + connect \rp_INT_rb_mul0_5 \$547 + connect \pick_INT_rb_mul0_5 \$545 + connect \addr_en_INT_rb_div0_4 \$537 + connect \rp_INT_rb_div0_4 \$535 + connect \pick_INT_rb_div0_4 \$533 + connect \addr_en_INT_rb_logical0_3 \$525 + connect \rp_INT_rb_logical0_3 \$523 + connect \pick_INT_rb_logical0_3 \$521 + connect \addr_en_INT_rb_trap0_2 \$513 + connect \rp_INT_rb_trap0_2 \$511 + connect \pick_INT_rb_trap0_2 \$509 + connect \addr_en_INT_rb_cr0_1 \$501 + connect \rp_INT_rb_cr0_1 \$499 + connect \pick_INT_rb_cr0_1 \$497 + connect \addr_en_INT_rb_alu0_0 \$489 + connect \rp_INT_rb_alu0_0 \$487 connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 @@ -85378,69 +85674,69 @@ module \core connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 - connect \pick_INT_rb_alu0_0 \$480 + connect \pick_INT_rb_alu0_0 \$485 connect \rdflag_INT_rb_0 \core_reg2_ok - connect \int_src1__ren \$472 - connect \int_src1__addr \$470 [4:0] - connect \addr_en_INT_ra_ldst0_8 \$453 - connect \rp_INT_ra_ldst0_8 \$451 + connect \int_src1__ren \$477 + connect \int_src1__addr \$475 [4:0] + connect \addr_en_INT_ra_ldst0_8 \$458 + connect \rp_INT_ra_ldst0_8 \$456 connect \fus_cu_rd__go_i$62 [2] \dp_INT_rc_ldst0_1 connect \fus_cu_rd__go_i$62 [1] \dp_INT_rb_ldst0_7 connect \fus_cu_rd__go_i$62 [0] \dp_INT_ra_ldst0_8 - connect \pick_INT_ra_ldst0_8 \$449 - connect \addr_en_INT_ra_shiftrot0_7 \$441 - connect \rp_INT_ra_shiftrot0_7 \$439 + connect \pick_INT_ra_ldst0_8 \$454 + connect \addr_en_INT_ra_shiftrot0_7 \$446 + connect \rp_INT_ra_shiftrot0_7 \$444 connect \fus_cu_rd__go_i$59 [4] \dp_XER_xer_ca_shiftrot0_2 connect \fus_cu_rd__go_i$59 [3] \dp_XER_xer_so_shiftrot0_5 connect \fus_cu_rd__go_i$59 [2] \dp_INT_rc_shiftrot0_0 connect \fus_cu_rd__go_i$59 [1] \dp_INT_rb_shiftrot0_6 connect \fus_cu_rd__go_i$59 [0] \dp_INT_ra_shiftrot0_7 - connect \pick_INT_ra_shiftrot0_7 \$437 - connect \addr_en_INT_ra_mul0_6 \$429 - connect \rp_INT_ra_mul0_6 \$427 + connect \pick_INT_ra_shiftrot0_7 \$442 + connect \addr_en_INT_ra_mul0_6 \$434 + connect \rp_INT_ra_mul0_6 \$432 connect \fus_cu_rd__go_i$56 [2] \dp_XER_xer_so_mul0_4 connect \fus_cu_rd__go_i$56 [1] \dp_INT_rb_mul0_5 connect \fus_cu_rd__go_i$56 [0] \dp_INT_ra_mul0_6 - connect \pick_INT_ra_mul0_6 \$425 - connect \addr_en_INT_ra_div0_5 \$417 - connect \rp_INT_ra_div0_5 \$415 + connect \pick_INT_ra_mul0_6 \$430 + connect \addr_en_INT_ra_div0_5 \$422 + connect \rp_INT_ra_div0_5 \$420 connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_div0_3 connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_div0_4 connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_div0_5 - connect \pick_INT_ra_div0_5 \$413 - connect \addr_en_INT_ra_spr0_4 \$405 - connect \rp_INT_ra_spr0_4 \$403 + connect \pick_INT_ra_div0_5 \$418 + connect \addr_en_INT_ra_spr0_4 \$410 + connect \rp_INT_ra_spr0_4 \$408 connect \fus_cu_rd__go_i$50 [1] \dp_SPR_spr1_spr0_0 connect \fus_cu_rd__go_i$50 [2] \dp_FAST_fast1_spr0_2 connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ov_spr0_0 connect \fus_cu_rd__go_i$50 [5] \dp_XER_xer_ca_spr0_1 connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_spr0_2 connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_spr0_4 - connect \pick_INT_ra_spr0_4 \$401 - connect \addr_en_INT_ra_logical0_3 \$393 - connect \rp_INT_ra_logical0_3 \$391 + connect \pick_INT_ra_spr0_4 \$406 + connect \addr_en_INT_ra_logical0_3 \$398 + connect \rp_INT_ra_logical0_3 \$396 connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_logical0_1 connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_logical0_3 connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_logical0_3 - connect \pick_INT_ra_logical0_3 \$389 - connect \addr_en_INT_ra_trap0_2 \$381 - connect \rp_INT_ra_trap0_2 \$379 + connect \pick_INT_ra_logical0_3 \$394 + connect \addr_en_INT_ra_trap0_2 \$386 + connect \rp_INT_ra_trap0_2 \$384 connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast2_trap0_1 connect \fus_cu_rd__go_i$44 [2] \dp_FAST_fast1_trap0_1 connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_trap0_2 connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_trap0_2 - connect \pick_INT_ra_trap0_2 \$377 - connect \addr_en_INT_ra_cr0_1 \$369 - connect \rp_INT_ra_cr0_1 \$367 + connect \pick_INT_ra_trap0_2 \$382 + connect \addr_en_INT_ra_cr0_1 \$374 + connect \rp_INT_ra_cr0_1 \$372 connect \fus_cu_rd__go_i$41 [5] \dp_CR_cr_c_cr0_0 connect \fus_cu_rd__go_i$41 [4] \dp_CR_cr_b_cr0_0 connect \fus_cu_rd__go_i$41 [3] \dp_CR_cr_a_cr0_0 connect \fus_cu_rd__go_i$41 [2] \dp_CR_full_cr_cr0_0 connect \fus_cu_rd__go_i$41 [1] \dp_INT_rb_cr0_1 connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_cr0_1 - connect \pick_INT_ra_cr0_1 \$365 - connect \addr_en_INT_ra_alu0_0 \$357 - connect \rp_INT_ra_alu0_0 \$355 + connect \pick_INT_ra_cr0_1 \$370 + connect \addr_en_INT_ra_alu0_0 \$362 + connect \rp_INT_ra_alu0_0 \$360 connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 @@ -85454,17 +85750,17 @@ module \core connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 - connect \pick_INT_ra_alu0_0 \$353 + connect \pick_INT_ra_alu0_0 \$358 connect \rdflag_INT_ra_0 \core_reg1_ok - connect \en_ldst0 \$212 - connect \en_shiftrot0 \$208 - connect \en_mul0 \$204 - connect \en_div0 \$200 - connect \en_spr0 \$196 - connect \en_logical0 \$192 - connect \en_trap0 \$188 - connect \en_branch0 \$184 - connect \en_cr0 \$180 + connect \en_ldst0 \$217 + connect \en_shiftrot0 \$213 + connect \en_mul0 \$209 + connect \en_div0 \$205 + connect \en_spr0 \$201 + connect \en_logical0 \$197 + connect \en_trap0 \$193 + connect \en_branch0 \$189 + connect \en_cr0 \$185 connect \fu_enable [9] \en_ldst0 connect \fu_enable [8] \en_shiftrot0 connect \fu_enable [7] \en_mul0 @@ -85475,117 +85771,126 @@ module \core connect \fu_enable [2] \en_branch0 connect \fu_enable [1] \en_cr0 connect \fu_enable [0] \en_alu0 - connect \en_alu0 \$176 + connect \en_alu0 \$181 + connect \dec_LDST_sv_a_nz \sv_a_nz connect \dec_LDST_bigendian \bigendian_i connect \dec_LDST_raw_opcode_in \raw_insn_i + connect \sv_a_nz$180 \sv_a_nz connect \dec_SHIFT_ROT_bigendian \bigendian_i connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i + connect \sv_a_nz$179 \sv_a_nz connect \dec_MUL_bigendian \bigendian_i connect \dec_MUL_raw_opcode_in \raw_insn_i + connect \dec_DIV_sv_a_nz \sv_a_nz connect \dec_DIV_bigendian \bigendian_i connect \dec_DIV_raw_opcode_in \raw_insn_i + connect \sv_a_nz$178 \sv_a_nz connect \dec_SPR_bigendian \bigendian_i connect \dec_SPR_raw_opcode_in \raw_insn_i + connect \dec_LOGICAL_sv_a_nz \sv_a_nz connect \dec_LOGICAL_bigendian \bigendian_i connect \dec_LOGICAL_raw_opcode_in \raw_insn_i + connect \sv_a_nz$177 \sv_a_nz connect \dec_BRANCH_bigendian \bigendian_i connect \dec_BRANCH_raw_opcode_in \raw_insn_i + connect \sv_a_nz$176 \sv_a_nz connect \dec_CR_bigendian \bigendian_i connect \dec_CR_raw_opcode_in \raw_insn_i + connect \dec_ALU_sv_a_nz \sv_a_nz connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:48840.1-49473.10" +attribute \src "libresoc.v:49145.1-49778.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr - attribute \src "libresoc.v:48841.7-48841.20" + attribute \src "libresoc.v:49146.7-49146.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49387.3-49395.6" + attribute \src "libresoc.v:49692.3-49700.6" wire width 8 $0\ren_delay$17$next[7:0]$3046 - attribute \src "libresoc.v:49223.3-49224.43" + attribute \src "libresoc.v:49528.3-49529.43" wire width 8 $0\ren_delay$17[7:0]$3043 - attribute \src "libresoc.v:49169.13-49169.35" + attribute \src "libresoc.v:49474.13-49474.35" wire width 8 $0\ren_delay$17[7:0]$3060 - attribute \src "libresoc.v:49406.3-49414.6" + attribute \src "libresoc.v:49711.3-49719.6" wire width 8 $0\ren_delay$34$next[7:0]$3050 - attribute \src "libresoc.v:49221.3-49222.43" + attribute \src "libresoc.v:49526.3-49527.43" wire width 8 $0\ren_delay$34[7:0]$3041 - attribute \src "libresoc.v:49173.13-49173.35" + attribute \src "libresoc.v:49478.13-49478.35" wire width 8 $0\ren_delay$34[7:0]$3062 - attribute \src "libresoc.v:49425.3-49433.6" + attribute \src "libresoc.v:49730.3-49738.6" wire width 8 $0\ren_delay$next[7:0]$3054 - attribute \src "libresoc.v:49225.3-49226.35" + attribute \src "libresoc.v:49530.3-49531.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:49434.3-49443.6" + attribute \src "libresoc.v:49739.3-49748.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:49396.3-49405.6" + attribute \src "libresoc.v:49701.3-49710.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:49415.3-49424.6" + attribute \src "libresoc.v:49720.3-49729.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:49387.3-49395.6" + attribute \src "libresoc.v:49692.3-49700.6" wire width 8 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49406.3-49414.6" + attribute \src "libresoc.v:49711.3-49719.6" wire width 8 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49425.3-49433.6" + attribute \src "libresoc.v:49730.3-49738.6" wire width 8 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49167.13-49167.30" + attribute \src "libresoc.v:49472.13-49472.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:49434.3-49443.6" + attribute \src "libresoc.v:49739.3-49748.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:49396.3-49405.6" + attribute \src "libresoc.v:49701.3-49710.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:49415.3-49424.6" + attribute \src "libresoc.v:49720.3-49729.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:49197.17-49197.125" - wire width 4 $or$libresoc.v:49197$3016_Y - attribute \src "libresoc.v:49198.18-49198.126" - wire width 4 $or$libresoc.v:49198$3017_Y - attribute \src "libresoc.v:49199.18-49199.96" - wire width 4 $or$libresoc.v:49199$3018_Y - attribute \src "libresoc.v:49200.18-49200.96" - wire width 4 $or$libresoc.v:49200$3019_Y - attribute \src "libresoc.v:49203.18-49203.126" - wire width 4 $or$libresoc.v:49203$3022_Y - attribute \src "libresoc.v:49204.18-49204.126" - wire width 4 $or$libresoc.v:49204$3023_Y - attribute \src "libresoc.v:49205.18-49205.97" - wire width 4 $or$libresoc.v:49205$3024_Y - attribute \src "libresoc.v:49206.18-49206.126" - wire width 4 $or$libresoc.v:49206$3025_Y - attribute \src "libresoc.v:49207.18-49207.126" - wire width 4 $or$libresoc.v:49207$3026_Y - attribute \src "libresoc.v:49208.18-49208.97" - wire width 4 $or$libresoc.v:49208$3027_Y - attribute \src "libresoc.v:49209.18-49209.97" - wire width 4 $or$libresoc.v:49209$3028_Y - attribute \src "libresoc.v:49211.18-49211.126" - wire width 4 $or$libresoc.v:49211$3030_Y - attribute \src "libresoc.v:49212.17-49212.125" - wire width 4 $or$libresoc.v:49212$3031_Y - attribute \src "libresoc.v:49213.18-49213.126" - wire width 4 $or$libresoc.v:49213$3032_Y - attribute \src "libresoc.v:49214.18-49214.97" - wire width 4 $or$libresoc.v:49214$3033_Y - attribute \src "libresoc.v:49215.18-49215.126" - wire width 4 $or$libresoc.v:49215$3034_Y - attribute \src "libresoc.v:49216.18-49216.126" - wire width 4 $or$libresoc.v:49216$3035_Y - attribute \src "libresoc.v:49217.18-49217.97" - wire width 4 $or$libresoc.v:49217$3036_Y - attribute \src "libresoc.v:49218.18-49218.97" - wire width 4 $or$libresoc.v:49218$3037_Y - attribute \src "libresoc.v:49219.17-49219.125" - wire width 4 $or$libresoc.v:49219$3038_Y - attribute \src "libresoc.v:49220.17-49220.94" - wire width 4 $or$libresoc.v:49220$3039_Y - attribute \src "libresoc.v:49201.18-49201.100" - wire $reduce_or$libresoc.v:49201$3020_Y - attribute \src "libresoc.v:49202.17-49202.95" - wire $reduce_or$libresoc.v:49202$3021_Y - attribute \src "libresoc.v:49210.18-49210.100" - wire $reduce_or$libresoc.v:49210$3029_Y + attribute \src "libresoc.v:49502.17-49502.125" + wire width 4 $or$libresoc.v:49502$3016_Y + attribute \src "libresoc.v:49503.18-49503.126" + wire width 4 $or$libresoc.v:49503$3017_Y + attribute \src "libresoc.v:49504.18-49504.96" + wire width 4 $or$libresoc.v:49504$3018_Y + attribute \src "libresoc.v:49505.18-49505.96" + wire width 4 $or$libresoc.v:49505$3019_Y + attribute \src "libresoc.v:49508.18-49508.126" + wire width 4 $or$libresoc.v:49508$3022_Y + attribute \src "libresoc.v:49509.18-49509.126" + wire width 4 $or$libresoc.v:49509$3023_Y + attribute \src "libresoc.v:49510.18-49510.97" + wire width 4 $or$libresoc.v:49510$3024_Y + attribute \src "libresoc.v:49511.18-49511.126" + wire width 4 $or$libresoc.v:49511$3025_Y + attribute \src "libresoc.v:49512.18-49512.126" + wire width 4 $or$libresoc.v:49512$3026_Y + attribute \src "libresoc.v:49513.18-49513.97" + wire width 4 $or$libresoc.v:49513$3027_Y + attribute \src "libresoc.v:49514.18-49514.97" + wire width 4 $or$libresoc.v:49514$3028_Y + attribute \src "libresoc.v:49516.18-49516.126" + wire width 4 $or$libresoc.v:49516$3030_Y + attribute \src "libresoc.v:49517.17-49517.125" + wire width 4 $or$libresoc.v:49517$3031_Y + attribute \src "libresoc.v:49518.18-49518.126" + wire width 4 $or$libresoc.v:49518$3032_Y + attribute \src "libresoc.v:49519.18-49519.97" + wire width 4 $or$libresoc.v:49519$3033_Y + attribute \src "libresoc.v:49520.18-49520.126" + wire width 4 $or$libresoc.v:49520$3034_Y + attribute \src "libresoc.v:49521.18-49521.126" + wire width 4 $or$libresoc.v:49521$3035_Y + attribute \src "libresoc.v:49522.18-49522.97" + wire width 4 $or$libresoc.v:49522$3036_Y + attribute \src "libresoc.v:49523.18-49523.97" + wire width 4 $or$libresoc.v:49523$3037_Y + attribute \src "libresoc.v:49524.17-49524.125" + wire width 4 $or$libresoc.v:49524$3038_Y + attribute \src "libresoc.v:49525.17-49525.94" + wire width 4 $or$libresoc.v:49525$3039_Y + attribute \src "libresoc.v:49506.18-49506.100" + wire $reduce_or$libresoc.v:49506$3020_Y + attribute \src "libresoc.v:49507.17-49507.95" + wire $reduce_or$libresoc.v:49507$3021_Y + attribute \src "libresoc.v:49515.18-49515.100" + wire $reduce_or$libresoc.v:49515$3029_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -85634,9 +85939,9 @@ module \cr wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 14 \data_i @@ -85654,7 +85959,7 @@ module \cr wire width 32 input 12 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 13 \full_wr__wen - attribute \src "libresoc.v:48841.7-48841.15" + attribute \src "libresoc.v:49146.7-49146.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest10__data_i @@ -85941,7 +86246,7 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \wen$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49197$3016 + cell $or $or$libresoc.v:49502$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85949,10 +86254,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src14__data_o connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:49197$3016_Y + connect \Y $or$libresoc.v:49502$3016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49198$3017 + cell $or $or$libresoc.v:49503$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85960,10 +86265,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src16__data_o connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:49198$3017_Y + connect \Y $or$libresoc.v:49503$3017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49199$3018 + cell $or $or$libresoc.v:49504$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85971,10 +86276,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:49199$3018_Y + connect \Y $or$libresoc.v:49504$3018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49200$3019 + cell $or $or$libresoc.v:49505$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85982,10 +86287,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:49200$3019_Y + connect \Y $or$libresoc.v:49505$3019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49203$3022 + cell $or $or$libresoc.v:49508$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85993,10 +86298,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src20__data_o connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:49203$3022_Y + connect \Y $or$libresoc.v:49508$3022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49204$3023 + cell $or $or$libresoc.v:49509$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86004,10 +86309,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src22__data_o connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:49204$3023_Y + connect \Y $or$libresoc.v:49509$3023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49205$3024 + cell $or $or$libresoc.v:49510$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86015,10 +86320,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:49205$3024_Y + connect \Y $or$libresoc.v:49510$3024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49206$3025 + cell $or $or$libresoc.v:49511$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86026,10 +86331,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src24__data_o connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:49206$3025_Y + connect \Y $or$libresoc.v:49511$3025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49207$3026 + cell $or $or$libresoc.v:49512$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86037,10 +86342,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src26__data_o connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:49207$3026_Y + connect \Y $or$libresoc.v:49512$3026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49208$3027 + cell $or $or$libresoc.v:49513$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86048,10 +86353,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:49208$3027_Y + connect \Y $or$libresoc.v:49513$3027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49209$3028 + cell $or $or$libresoc.v:49514$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86059,10 +86364,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:49209$3028_Y + connect \Y $or$libresoc.v:49514$3028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49211$3030 + cell $or $or$libresoc.v:49516$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86070,10 +86375,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src30__data_o connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:49211$3030_Y + connect \Y $or$libresoc.v:49516$3030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49212$3031 + cell $or $or$libresoc.v:49517$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86081,10 +86386,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src10__data_o connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:49212$3031_Y + connect \Y $or$libresoc.v:49517$3031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49213$3032 + cell $or $or$libresoc.v:49518$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86092,10 +86397,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src32__data_o connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:49213$3032_Y + connect \Y $or$libresoc.v:49518$3032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49214$3033 + cell $or $or$libresoc.v:49519$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86103,10 +86408,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:49214$3033_Y + connect \Y $or$libresoc.v:49519$3033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49215$3034 + cell $or $or$libresoc.v:49520$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86114,10 +86419,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src34__data_o connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:49215$3034_Y + connect \Y $or$libresoc.v:49520$3034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49216$3035 + cell $or $or$libresoc.v:49521$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86125,10 +86430,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src36__data_o connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:49216$3035_Y + connect \Y $or$libresoc.v:49521$3035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49217$3036 + cell $or $or$libresoc.v:49522$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86136,10 +86441,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:49217$3036_Y + connect \Y $or$libresoc.v:49522$3036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49218$3037 + cell $or $or$libresoc.v:49523$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86147,10 +86452,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:49218$3037_Y + connect \Y $or$libresoc.v:49523$3037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49219$3038 + cell $or $or$libresoc.v:49524$3038 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86158,10 +86463,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src12__data_o connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:49219$3038_Y + connect \Y $or$libresoc.v:49524$3038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49220$3039 + cell $or $or$libresoc.v:49525$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86169,34 +86474,34 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:49220$3039_Y + connect \Y $or$libresoc.v:49525$3039_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49201$3020 + cell $reduce_or $reduce_or$libresoc.v:49506$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:49201$3020_Y + connect \Y $reduce_or$libresoc.v:49506$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49202$3021 + cell $reduce_or $reduce_or$libresoc.v:49507$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:49202$3021_Y + connect \Y $reduce_or$libresoc.v:49507$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49210$3029 + cell $reduce_or $reduce_or$libresoc.v:49515$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:49210$3029_Y + connect \Y $reduce_or$libresoc.v:49515$3029_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49227.9-49246.4" + attribute \src "libresoc.v:49532.9-49551.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86218,7 +86523,7 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49247.9-49266.4" + attribute \src "libresoc.v:49552.9-49571.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86240,7 +86545,7 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49267.9-49286.4" + attribute \src "libresoc.v:49572.9-49591.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86262,7 +86567,7 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49287.9-49306.4" + attribute \src "libresoc.v:49592.9-49611.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86284,7 +86589,7 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49307.9-49326.4" + attribute \src "libresoc.v:49612.9-49631.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86306,7 +86611,7 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49327.9-49346.4" + attribute \src "libresoc.v:49632.9-49651.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86328,7 +86633,7 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49347.9-49366.4" + attribute \src "libresoc.v:49652.9-49671.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86350,7 +86655,7 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49367.9-49386.4" + attribute \src "libresoc.v:49672.9-49691.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86371,67 +86676,67 @@ module \cr connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end - attribute \src "libresoc.v:48841.7-48841.20" - process $proc$libresoc.v:48841$3057 + attribute \src "libresoc.v:49146.7-49146.20" + process $proc$libresoc.v:49146$3057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49167.13-49167.30" - process $proc$libresoc.v:49167$3058 + attribute \src "libresoc.v:49472.13-49472.30" + process $proc$libresoc.v:49472$3058 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:49169.13-49169.35" - process $proc$libresoc.v:49169$3059 + attribute \src "libresoc.v:49474.13-49474.35" + process $proc$libresoc.v:49474$3059 assign { } { } assign $0\ren_delay$17[7:0]$3060 8'00000000 sync always sync init update \ren_delay$17 $0\ren_delay$17[7:0]$3060 end - attribute \src "libresoc.v:49173.13-49173.35" - process $proc$libresoc.v:49173$3061 + attribute \src "libresoc.v:49478.13-49478.35" + process $proc$libresoc.v:49478$3061 assign { } { } assign $0\ren_delay$34[7:0]$3062 8'00000000 sync always sync init update \ren_delay$34 $0\ren_delay$34[7:0]$3062 end - attribute \src "libresoc.v:49221.3-49222.43" - process $proc$libresoc.v:49221$3040 + attribute \src "libresoc.v:49526.3-49527.43" + process $proc$libresoc.v:49526$3040 assign { } { } assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next sync posedge \coresync_clk update \ren_delay$34 $0\ren_delay$34[7:0]$3041 end - attribute \src "libresoc.v:49223.3-49224.43" - process $proc$libresoc.v:49223$3042 + attribute \src "libresoc.v:49528.3-49529.43" + process $proc$libresoc.v:49528$3042 assign { } { } assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next sync posedge \coresync_clk update \ren_delay$17 $0\ren_delay$17[7:0]$3043 end - attribute \src "libresoc.v:49225.3-49226.35" - process $proc$libresoc.v:49225$3044 + attribute \src "libresoc.v:49530.3-49531.35" + process $proc$libresoc.v:49530$3044 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:49387.3-49395.6" - process $proc$libresoc.v:49387$3045 + attribute \src "libresoc.v:49692.3-49700.6" + process $proc$libresoc.v:49692$3045 assign { } { } assign { } { } assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49388.5-49388.29" + attribute \src "libresoc.v:49693.5-49693.29" switch \initial - attribute \src "libresoc.v:49388.9-49388.17" + attribute \src "libresoc.v:49693.9-49693.17" case 1'1 case end @@ -86447,14 +86752,14 @@ module \cr sync always update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 end - attribute \src "libresoc.v:49396.3-49405.6" - process $proc$libresoc.v:49396$3048 + attribute \src "libresoc.v:49701.3-49710.6" + process $proc$libresoc.v:49701$3048 assign { } { } assign { } { } assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49397.5-49397.29" + attribute \src "libresoc.v:49702.5-49702.29" switch \initial - attribute \src "libresoc.v:49397.9-49397.17" + attribute \src "libresoc.v:49702.9-49702.17" case 1'1 case end @@ -86470,14 +86775,14 @@ module \cr sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:49406.3-49414.6" - process $proc$libresoc.v:49406$3049 + attribute \src "libresoc.v:49711.3-49719.6" + process $proc$libresoc.v:49711$3049 assign { } { } assign { } { } assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49407.5-49407.29" + attribute \src "libresoc.v:49712.5-49712.29" switch \initial - attribute \src "libresoc.v:49407.9-49407.17" + attribute \src "libresoc.v:49712.9-49712.17" case 1'1 case end @@ -86493,14 +86798,14 @@ module \cr sync always update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 end - attribute \src "libresoc.v:49415.3-49424.6" - process $proc$libresoc.v:49415$3052 + attribute \src "libresoc.v:49720.3-49729.6" + process $proc$libresoc.v:49720$3052 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49416.5-49416.29" + attribute \src "libresoc.v:49721.5-49721.29" switch \initial - attribute \src "libresoc.v:49416.9-49416.17" + attribute \src "libresoc.v:49721.9-49721.17" case 1'1 case end @@ -86516,14 +86821,14 @@ module \cr sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:49425.3-49433.6" - process $proc$libresoc.v:49425$3053 + attribute \src "libresoc.v:49730.3-49738.6" + process $proc$libresoc.v:49730$3053 assign { } { } assign { } { } assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49426.5-49426.29" + attribute \src "libresoc.v:49731.5-49731.29" switch \initial - attribute \src "libresoc.v:49426.9-49426.17" + attribute \src "libresoc.v:49731.9-49731.17" case 1'1 case end @@ -86539,14 +86844,14 @@ module \cr sync always update \ren_delay$next $0\ren_delay$next[7:0]$3054 end - attribute \src "libresoc.v:49434.3-49443.6" - process $proc$libresoc.v:49434$3056 + attribute \src "libresoc.v:49739.3-49748.6" + process $proc$libresoc.v:49739$3056 assign { } { } assign { } { } assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49435.5-49435.29" + attribute \src "libresoc.v:49740.5-49740.29" switch \initial - attribute \src "libresoc.v:49435.9-49435.17" + attribute \src "libresoc.v:49740.9-49740.17" case 1'1 case end @@ -86562,30 +86867,30 @@ module \cr sync always update \src1__data_o $0\src1__data_o[3:0] end - connect \$9 $or$libresoc.v:49197$3016_Y - connect \$11 $or$libresoc.v:49198$3017_Y - connect \$13 $or$libresoc.v:49199$3018_Y - connect \$15 $or$libresoc.v:49200$3019_Y - connect \$18 $reduce_or$libresoc.v:49201$3020_Y - connect \$1 $reduce_or$libresoc.v:49202$3021_Y - connect \$20 $or$libresoc.v:49203$3022_Y - connect \$22 $or$libresoc.v:49204$3023_Y - connect \$24 $or$libresoc.v:49205$3024_Y - connect \$26 $or$libresoc.v:49206$3025_Y - connect \$28 $or$libresoc.v:49207$3026_Y - connect \$30 $or$libresoc.v:49208$3027_Y - connect \$32 $or$libresoc.v:49209$3028_Y - connect \$35 $reduce_or$libresoc.v:49210$3029_Y - connect \$37 $or$libresoc.v:49211$3030_Y - connect \$3 $or$libresoc.v:49212$3031_Y - connect \$39 $or$libresoc.v:49213$3032_Y - connect \$41 $or$libresoc.v:49214$3033_Y - connect \$43 $or$libresoc.v:49215$3034_Y - connect \$45 $or$libresoc.v:49216$3035_Y - connect \$47 $or$libresoc.v:49217$3036_Y - connect \$49 $or$libresoc.v:49218$3037_Y - connect \$5 $or$libresoc.v:49219$3038_Y - connect \$7 $or$libresoc.v:49220$3039_Y + connect \$9 $or$libresoc.v:49502$3016_Y + connect \$11 $or$libresoc.v:49503$3017_Y + connect \$13 $or$libresoc.v:49504$3018_Y + connect \$15 $or$libresoc.v:49505$3019_Y + connect \$18 $reduce_or$libresoc.v:49506$3020_Y + connect \$1 $reduce_or$libresoc.v:49507$3021_Y + connect \$20 $or$libresoc.v:49508$3022_Y + connect \$22 $or$libresoc.v:49509$3023_Y + connect \$24 $or$libresoc.v:49510$3024_Y + connect \$26 $or$libresoc.v:49511$3025_Y + connect \$28 $or$libresoc.v:49512$3026_Y + connect \$30 $or$libresoc.v:49513$3027_Y + connect \$32 $or$libresoc.v:49514$3028_Y + connect \$35 $reduce_or$libresoc.v:49515$3029_Y + connect \$37 $or$libresoc.v:49516$3030_Y + connect \$3 $or$libresoc.v:49517$3031_Y + connect \$39 $or$libresoc.v:49518$3032_Y + connect \$41 $or$libresoc.v:49519$3033_Y + connect \$43 $or$libresoc.v:49520$3034_Y + connect \$45 $or$libresoc.v:49521$3035_Y + connect \$47 $or$libresoc.v:49522$3036_Y + connect \$49 $or$libresoc.v:49523$3037_Y + connect \$5 $or$libresoc.v:49524$3038_Y + connect \$7 $or$libresoc.v:49525$3039_Y connect \wen$51 8'00000000 connect \data_i$52 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen @@ -86616,393 +86921,393 @@ module \cr connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:49477.1-50530.10" +attribute \src "libresoc.v:49782.1-50839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:50131.3-50132.25" + attribute \src "libresoc.v:50440.3-50441.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50304.3-50315.6" - wire width 13 $0\alu_cr0_cr_op__fn_unit$next[12:0]$3182 - attribute \src "libresoc.v:50103.3-50104.61" - wire width 13 $0\alu_cr0_cr_op__fn_unit[12:0] - attribute \src "libresoc.v:50304.3-50315.6" + attribute \src "libresoc.v:50613.3-50624.6" + wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 + attribute \src "libresoc.v:50412.3-50413.61" + wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] + attribute \src "libresoc.v:50613.3-50624.6" wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 - attribute \src "libresoc.v:50105.3-50106.55" + attribute \src "libresoc.v:50414.3-50415.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50304.3-50315.6" + attribute \src "libresoc.v:50613.3-50624.6" wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 - attribute \src "libresoc.v:50101.3-50102.65" + attribute \src "libresoc.v:50410.3-50411.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50129.3-50130.39" + attribute \src "libresoc.v:50438.3-50439.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50451.3-50459.6" + attribute \src "libresoc.v:50760.3-50768.6" wire $0\alu_l_r_alu$next[0:0]$3234 - attribute \src "libresoc.v:50073.3-50074.39" + attribute \src "libresoc.v:50382.3-50383.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50442.3-50450.6" + attribute \src "libresoc.v:50751.3-50759.6" wire $0\alui_l_r_alui$next[0:0]$3231 - attribute \src "libresoc.v:50075.3-50076.43" + attribute \src "libresoc.v:50384.3-50385.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50316.3-50337.6" + attribute \src "libresoc.v:50625.3-50646.6" wire width 64 $0\data_r0__o$next[63:0]$3189 - attribute \src "libresoc.v:50097.3-50098.37" + attribute \src "libresoc.v:50406.3-50407.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50316.3-50337.6" + attribute \src "libresoc.v:50625.3-50646.6" wire $0\data_r0__o_ok$next[0:0]$3190 - attribute \src "libresoc.v:50099.3-50100.43" + attribute \src "libresoc.v:50408.3-50409.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50338.3-50359.6" + attribute \src "libresoc.v:50647.3-50668.6" wire width 32 $0\data_r1__full_cr$next[31:0]$3197 - attribute \src "libresoc.v:50093.3-50094.49" + attribute \src "libresoc.v:50402.3-50403.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50338.3-50359.6" + attribute \src "libresoc.v:50647.3-50668.6" wire $0\data_r1__full_cr_ok$next[0:0]$3198 - attribute \src "libresoc.v:50095.3-50096.55" + attribute \src "libresoc.v:50404.3-50405.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50360.3-50381.6" + attribute \src "libresoc.v:50669.3-50690.6" wire width 4 $0\data_r2__cr_a$next[3:0]$3205 - attribute \src "libresoc.v:50089.3-50090.43" + attribute \src "libresoc.v:50398.3-50399.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50360.3-50381.6" + attribute \src "libresoc.v:50669.3-50690.6" wire $0\data_r2__cr_a_ok$next[0:0]$3206 - attribute \src "libresoc.v:50091.3-50092.49" + attribute \src "libresoc.v:50400.3-50401.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50460.3-50469.6" + attribute \src "libresoc.v:50769.3-50778.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50470.3-50479.6" + attribute \src "libresoc.v:50779.3-50788.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50480.3-50489.6" + attribute \src "libresoc.v:50789.3-50798.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49478.7-49478.20" + attribute \src "libresoc.v:49783.7-49783.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50259.3-50267.6" + attribute \src "libresoc.v:50568.3-50576.6" wire $0\opc_l_r_opc$next[0:0]$3167 - attribute \src "libresoc.v:50115.3-50116.39" + attribute \src "libresoc.v:50424.3-50425.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50250.3-50258.6" + attribute \src "libresoc.v:50559.3-50567.6" wire $0\opc_l_s_opc$next[0:0]$3164 - attribute \src "libresoc.v:50117.3-50118.39" + attribute \src "libresoc.v:50426.3-50427.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50490.3-50498.6" + attribute \src "libresoc.v:50799.3-50807.6" wire width 3 $0\prev_wr_go$next[2:0]$3240 - attribute \src "libresoc.v:50127.3-50128.37" + attribute \src "libresoc.v:50436.3-50437.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:50204.3-50213.6" + attribute \src "libresoc.v:50513.3-50522.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:50295.3-50303.6" + attribute \src "libresoc.v:50604.3-50612.6" wire width 3 $0\req_l_r_req$next[2:0]$3179 - attribute \src "libresoc.v:50107.3-50108.39" + attribute \src "libresoc.v:50416.3-50417.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:50286.3-50294.6" + attribute \src "libresoc.v:50595.3-50603.6" wire width 3 $0\req_l_s_req$next[2:0]$3176 - attribute \src "libresoc.v:50109.3-50110.39" + attribute \src "libresoc.v:50418.3-50419.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:50223.3-50231.6" + attribute \src "libresoc.v:50532.3-50540.6" wire $0\rok_l_r_rdok$next[0:0]$3155 - attribute \src "libresoc.v:50123.3-50124.41" + attribute \src "libresoc.v:50432.3-50433.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50214.3-50222.6" + attribute \src "libresoc.v:50523.3-50531.6" wire $0\rok_l_s_rdok$next[0:0]$3152 - attribute \src "libresoc.v:50125.3-50126.41" + attribute \src "libresoc.v:50434.3-50435.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50241.3-50249.6" + attribute \src "libresoc.v:50550.3-50558.6" wire $0\rst_l_r_rst$next[0:0]$3161 - attribute \src "libresoc.v:50119.3-50120.39" + attribute \src "libresoc.v:50428.3-50429.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50232.3-50240.6" + attribute \src "libresoc.v:50541.3-50549.6" wire $0\rst_l_s_rst$next[0:0]$3158 - attribute \src "libresoc.v:50121.3-50122.39" + attribute \src "libresoc.v:50430.3-50431.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50277.3-50285.6" + attribute \src "libresoc.v:50586.3-50594.6" wire width 6 $0\src_l_r_src$next[5:0]$3173 - attribute \src "libresoc.v:50111.3-50112.39" + attribute \src "libresoc.v:50420.3-50421.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:50268.3-50276.6" + attribute \src "libresoc.v:50577.3-50585.6" wire width 6 $0\src_l_s_src$next[5:0]$3170 - attribute \src "libresoc.v:50113.3-50114.39" + attribute \src "libresoc.v:50422.3-50423.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:50382.3-50391.6" + attribute \src "libresoc.v:50691.3-50700.6" wire width 64 $0\src_r0$next[63:0]$3213 - attribute \src "libresoc.v:50087.3-50088.29" + attribute \src "libresoc.v:50396.3-50397.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:50392.3-50401.6" + attribute \src "libresoc.v:50701.3-50710.6" wire width 64 $0\src_r1$next[63:0]$3216 - attribute \src "libresoc.v:50085.3-50086.29" + attribute \src "libresoc.v:50394.3-50395.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:50402.3-50411.6" + attribute \src "libresoc.v:50711.3-50720.6" wire width 32 $0\src_r2$next[31:0]$3219 - attribute \src "libresoc.v:50083.3-50084.29" + attribute \src "libresoc.v:50392.3-50393.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:50412.3-50421.6" + attribute \src "libresoc.v:50721.3-50730.6" wire width 4 $0\src_r3$next[3:0]$3222 - attribute \src "libresoc.v:50081.3-50082.29" + attribute \src "libresoc.v:50390.3-50391.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:50422.3-50431.6" + attribute \src "libresoc.v:50731.3-50740.6" wire width 4 $0\src_r4$next[3:0]$3225 - attribute \src "libresoc.v:50079.3-50080.29" + attribute \src "libresoc.v:50388.3-50389.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:50432.3-50441.6" + attribute \src "libresoc.v:50741.3-50750.6" wire width 4 $0\src_r5$next[3:0]$3228 - attribute \src "libresoc.v:50077.3-50078.29" + attribute \src "libresoc.v:50386.3-50387.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:49596.7-49596.24" + attribute \src "libresoc.v:49901.7-49901.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:50304.3-50315.6" - wire width 13 $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 - attribute \src "libresoc.v:49626.14-49626.47" - wire width 13 $1\alu_cr0_cr_op__fn_unit[12:0] - attribute \src "libresoc.v:50304.3-50315.6" + attribute \src "libresoc.v:50613.3-50624.6" + wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 + attribute \src "libresoc.v:49932.14-49932.47" + wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] + attribute \src "libresoc.v:50613.3-50624.6" wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 - attribute \src "libresoc.v:49630.14-49630.41" + attribute \src "libresoc.v:49936.14-49936.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50304.3-50315.6" + attribute \src "libresoc.v:50613.3-50624.6" wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:49708.13-49708.45" + attribute \src "libresoc.v:50015.13-50015.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:49732.7-49732.26" + attribute \src "libresoc.v:50039.7-50039.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:50451.3-50459.6" + attribute \src "libresoc.v:50760.3-50768.6" wire $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:49740.7-49740.25" + attribute \src "libresoc.v:50047.7-50047.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50442.3-50450.6" + attribute \src "libresoc.v:50751.3-50759.6" wire $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:49752.7-49752.27" + attribute \src "libresoc.v:50059.7-50059.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50316.3-50337.6" + attribute \src "libresoc.v:50625.3-50646.6" wire width 64 $1\data_r0__o$next[63:0]$3191 - attribute \src "libresoc.v:49786.14-49786.47" + attribute \src "libresoc.v:50093.14-50093.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:50316.3-50337.6" + attribute \src "libresoc.v:50625.3-50646.6" wire $1\data_r0__o_ok$next[0:0]$3192 - attribute \src "libresoc.v:49790.7-49790.27" + attribute \src "libresoc.v:50097.7-50097.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50338.3-50359.6" + attribute \src "libresoc.v:50647.3-50668.6" wire width 32 $1\data_r1__full_cr$next[31:0]$3199 - attribute \src "libresoc.v:49794.14-49794.38" + attribute \src "libresoc.v:50101.14-50101.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50338.3-50359.6" + attribute \src "libresoc.v:50647.3-50668.6" wire $1\data_r1__full_cr_ok$next[0:0]$3200 - attribute \src "libresoc.v:49798.7-49798.33" + attribute \src "libresoc.v:50105.7-50105.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50360.3-50381.6" + attribute \src "libresoc.v:50669.3-50690.6" wire width 4 $1\data_r2__cr_a$next[3:0]$3207 - attribute \src "libresoc.v:49802.13-49802.33" + attribute \src "libresoc.v:50109.13-50109.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50360.3-50381.6" + attribute \src "libresoc.v:50669.3-50690.6" wire $1\data_r2__cr_a_ok$next[0:0]$3208 - attribute \src "libresoc.v:49806.7-49806.30" + attribute \src "libresoc.v:50113.7-50113.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50460.3-50469.6" + attribute \src "libresoc.v:50769.3-50778.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:50470.3-50479.6" + attribute \src "libresoc.v:50779.3-50788.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:50480.3-50489.6" + attribute \src "libresoc.v:50789.3-50798.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:50259.3-50267.6" + attribute \src "libresoc.v:50568.3-50576.6" wire $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:49825.7-49825.25" + attribute \src "libresoc.v:50132.7-50132.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50250.3-50258.6" + attribute \src "libresoc.v:50559.3-50567.6" wire $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:49829.7-49829.25" + attribute \src "libresoc.v:50136.7-50136.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50490.3-50498.6" + attribute \src "libresoc.v:50799.3-50807.6" wire width 3 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:49927.13-49927.30" + attribute \src "libresoc.v:50236.13-50236.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:50204.3-50213.6" + attribute \src "libresoc.v:50513.3-50522.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:50295.3-50303.6" + attribute \src "libresoc.v:50604.3-50612.6" wire width 3 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:49935.13-49935.31" + attribute \src "libresoc.v:50244.13-50244.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:50286.3-50294.6" + attribute \src "libresoc.v:50595.3-50603.6" wire width 3 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:49939.13-49939.31" + attribute \src "libresoc.v:50248.13-50248.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:50223.3-50231.6" + attribute \src "libresoc.v:50532.3-50540.6" wire $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:49951.7-49951.26" + attribute \src "libresoc.v:50260.7-50260.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50214.3-50222.6" + attribute \src "libresoc.v:50523.3-50531.6" wire $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:49955.7-49955.26" + attribute \src "libresoc.v:50264.7-50264.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50241.3-50249.6" + attribute \src "libresoc.v:50550.3-50558.6" wire $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:49959.7-49959.25" + attribute \src "libresoc.v:50268.7-50268.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50232.3-50240.6" + attribute \src "libresoc.v:50541.3-50549.6" wire $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:49963.7-49963.25" + attribute \src "libresoc.v:50272.7-50272.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50277.3-50285.6" + attribute \src "libresoc.v:50586.3-50594.6" wire width 6 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:49983.13-49983.32" + attribute \src "libresoc.v:50292.13-50292.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:50268.3-50276.6" + attribute \src "libresoc.v:50577.3-50585.6" wire width 6 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:49987.13-49987.32" + attribute \src "libresoc.v:50296.13-50296.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:50382.3-50391.6" + attribute \src "libresoc.v:50691.3-50700.6" wire width 64 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:49991.14-49991.43" + attribute \src "libresoc.v:50300.14-50300.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:50392.3-50401.6" + attribute \src "libresoc.v:50701.3-50710.6" wire width 64 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:49995.14-49995.43" + attribute \src "libresoc.v:50304.14-50304.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:50402.3-50411.6" + attribute \src "libresoc.v:50711.3-50720.6" wire width 32 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:49999.14-49999.28" + attribute \src "libresoc.v:50308.14-50308.28" wire width 32 $1\src_r2[31:0] - attribute \src "libresoc.v:50412.3-50421.6" + attribute \src "libresoc.v:50721.3-50730.6" wire width 4 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50003.13-50003.26" + attribute \src "libresoc.v:50312.13-50312.26" wire width 4 $1\src_r3[3:0] - attribute \src "libresoc.v:50422.3-50431.6" + attribute \src "libresoc.v:50731.3-50740.6" wire width 4 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50007.13-50007.26" + attribute \src "libresoc.v:50316.13-50316.26" wire width 4 $1\src_r4[3:0] - attribute \src "libresoc.v:50432.3-50441.6" + attribute \src "libresoc.v:50741.3-50750.6" wire width 4 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50011.13-50011.26" + attribute \src "libresoc.v:50320.13-50320.26" wire width 4 $1\src_r5[3:0] - attribute \src "libresoc.v:50316.3-50337.6" + attribute \src "libresoc.v:50625.3-50646.6" wire width 64 $2\data_r0__o$next[63:0]$3193 - attribute \src "libresoc.v:50316.3-50337.6" + attribute \src "libresoc.v:50625.3-50646.6" wire $2\data_r0__o_ok$next[0:0]$3194 - attribute \src "libresoc.v:50338.3-50359.6" + attribute \src "libresoc.v:50647.3-50668.6" wire width 32 $2\data_r1__full_cr$next[31:0]$3201 - attribute \src "libresoc.v:50338.3-50359.6" + attribute \src "libresoc.v:50647.3-50668.6" wire $2\data_r1__full_cr_ok$next[0:0]$3202 - attribute \src "libresoc.v:50360.3-50381.6" + attribute \src "libresoc.v:50669.3-50690.6" wire width 4 $2\data_r2__cr_a$next[3:0]$3209 - attribute \src "libresoc.v:50360.3-50381.6" + attribute \src "libresoc.v:50669.3-50690.6" wire $2\data_r2__cr_a_ok$next[0:0]$3210 - attribute \src "libresoc.v:50316.3-50337.6" + attribute \src "libresoc.v:50625.3-50646.6" wire $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50338.3-50359.6" + attribute \src "libresoc.v:50647.3-50668.6" wire $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50360.3-50381.6" + attribute \src "libresoc.v:50669.3-50690.6" wire $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50017.18-50017.112" - wire width 6 $and$libresoc.v:50017$3064_Y - attribute \src "libresoc.v:50018.19-50018.125" - wire $and$libresoc.v:50018$3065_Y - attribute \src "libresoc.v:50019.19-50019.125" - wire $and$libresoc.v:50019$3066_Y - attribute \src "libresoc.v:50020.19-50020.125" - wire $and$libresoc.v:50020$3067_Y - attribute \src "libresoc.v:50021.19-50021.141" - wire width 3 $and$libresoc.v:50021$3068_Y - attribute \src "libresoc.v:50022.19-50022.121" - wire width 3 $and$libresoc.v:50022$3069_Y - attribute \src "libresoc.v:50023.19-50023.127" - wire $and$libresoc.v:50023$3070_Y - attribute \src "libresoc.v:50024.19-50024.127" - wire $and$libresoc.v:50024$3071_Y - attribute \src "libresoc.v:50025.19-50025.127" - wire $and$libresoc.v:50025$3072_Y - attribute \src "libresoc.v:50026.18-50026.110" - wire $and$libresoc.v:50026$3073_Y - attribute \src "libresoc.v:50028.18-50028.98" - wire $and$libresoc.v:50028$3075_Y - attribute \src "libresoc.v:50030.18-50030.100" - wire $and$libresoc.v:50030$3077_Y - attribute \src "libresoc.v:50031.18-50031.149" - wire width 3 $and$libresoc.v:50031$3078_Y - attribute \src "libresoc.v:50033.18-50033.119" - wire width 3 $and$libresoc.v:50033$3080_Y - attribute \src "libresoc.v:50036.18-50036.116" - wire $and$libresoc.v:50036$3083_Y - attribute \src "libresoc.v:50040.17-50040.123" - wire $and$libresoc.v:50040$3087_Y - attribute \src "libresoc.v:50042.18-50042.113" - wire $and$libresoc.v:50042$3089_Y - attribute \src "libresoc.v:50043.18-50043.125" - wire width 3 $and$libresoc.v:50043$3090_Y - attribute \src "libresoc.v:50045.18-50045.112" - wire $and$libresoc.v:50045$3092_Y - attribute \src "libresoc.v:50047.18-50047.125" - wire $and$libresoc.v:50047$3094_Y - attribute \src "libresoc.v:50048.18-50048.125" - wire $and$libresoc.v:50048$3095_Y - attribute \src "libresoc.v:50049.18-50049.117" - wire $and$libresoc.v:50049$3096_Y - attribute \src "libresoc.v:50054.18-50054.129" - wire $and$libresoc.v:50054$3101_Y - attribute \src "libresoc.v:50055.18-50055.124" - wire width 3 $and$libresoc.v:50055$3102_Y - attribute \src "libresoc.v:50058.18-50058.116" - wire $and$libresoc.v:50058$3105_Y - attribute \src "libresoc.v:50059.18-50059.122" - wire $and$libresoc.v:50059$3106_Y - attribute \src "libresoc.v:50060.18-50060.119" - wire $and$libresoc.v:50060$3107_Y - attribute \src "libresoc.v:50068.18-50068.133" - wire $and$libresoc.v:50068$3115_Y - attribute \src "libresoc.v:50069.18-50069.131" - wire $and$libresoc.v:50069$3116_Y - attribute \src "libresoc.v:50070.18-50070.182" - wire width 6 $and$libresoc.v:50070$3117_Y - attribute \src "libresoc.v:50071.18-50071.113" - wire width 6 $and$libresoc.v:50071$3118_Y - attribute \src "libresoc.v:50044.18-50044.113" - wire $eq$libresoc.v:50044$3091_Y - attribute \src "libresoc.v:50046.18-50046.119" - wire $eq$libresoc.v:50046$3093_Y - attribute \src "libresoc.v:50027.18-50027.97" - wire $not$libresoc.v:50027$3074_Y - attribute \src "libresoc.v:50029.18-50029.99" - wire $not$libresoc.v:50029$3076_Y - attribute \src "libresoc.v:50032.18-50032.113" - wire width 3 $not$libresoc.v:50032$3079_Y - attribute \src "libresoc.v:50035.18-50035.106" - wire $not$libresoc.v:50035$3082_Y - attribute \src "libresoc.v:50041.18-50041.119" - wire $not$libresoc.v:50041$3088_Y - attribute \src "libresoc.v:50056.17-50056.113" - wire width 6 $not$libresoc.v:50056$3103_Y - attribute \src "libresoc.v:50072.18-50072.114" - wire width 6 $not$libresoc.v:50072$3119_Y - attribute \src "libresoc.v:50039.18-50039.112" - wire $or$libresoc.v:50039$3086_Y - attribute \src "libresoc.v:50050.18-50050.122" - wire $or$libresoc.v:50050$3097_Y - attribute \src "libresoc.v:50051.18-50051.124" - wire $or$libresoc.v:50051$3098_Y - attribute \src "libresoc.v:50052.18-50052.155" - wire width 3 $or$libresoc.v:50052$3099_Y - attribute \src "libresoc.v:50053.18-50053.194" - wire width 6 $or$libresoc.v:50053$3100_Y - attribute \src "libresoc.v:50057.18-50057.120" - wire width 3 $or$libresoc.v:50057$3104_Y - attribute \src "libresoc.v:50067.17-50067.117" - wire width 6 $or$libresoc.v:50067$3114_Y - attribute \src "libresoc.v:50016.17-50016.104" - wire $reduce_and$libresoc.v:50016$3063_Y - attribute \src "libresoc.v:50034.18-50034.106" - wire $reduce_or$libresoc.v:50034$3081_Y - attribute \src "libresoc.v:50037.18-50037.113" - wire $reduce_or$libresoc.v:50037$3084_Y - attribute \src "libresoc.v:50038.18-50038.112" - wire $reduce_or$libresoc.v:50038$3085_Y - attribute \src "libresoc.v:50061.18-50061.118" - wire width 64 $ternary$libresoc.v:50061$3108_Y - attribute \src "libresoc.v:50062.18-50062.118" - wire width 64 $ternary$libresoc.v:50062$3109_Y - attribute \src "libresoc.v:50063.18-50063.118" - wire width 32 $ternary$libresoc.v:50063$3110_Y - attribute \src "libresoc.v:50064.18-50064.118" - wire width 4 $ternary$libresoc.v:50064$3111_Y - attribute \src "libresoc.v:50065.18-50065.118" - wire width 4 $ternary$libresoc.v:50065$3112_Y - attribute \src "libresoc.v:50066.18-50066.118" - wire width 4 $ternary$libresoc.v:50066$3113_Y + attribute \src "libresoc.v:50326.18-50326.112" + wire width 6 $and$libresoc.v:50326$3064_Y + attribute \src "libresoc.v:50327.19-50327.125" + wire $and$libresoc.v:50327$3065_Y + attribute \src "libresoc.v:50328.19-50328.125" + wire $and$libresoc.v:50328$3066_Y + attribute \src "libresoc.v:50329.19-50329.125" + wire $and$libresoc.v:50329$3067_Y + attribute \src "libresoc.v:50330.19-50330.141" + wire width 3 $and$libresoc.v:50330$3068_Y + attribute \src "libresoc.v:50331.19-50331.121" + wire width 3 $and$libresoc.v:50331$3069_Y + attribute \src "libresoc.v:50332.19-50332.127" + wire $and$libresoc.v:50332$3070_Y + attribute \src "libresoc.v:50333.19-50333.127" + wire $and$libresoc.v:50333$3071_Y + attribute \src "libresoc.v:50334.19-50334.127" + wire $and$libresoc.v:50334$3072_Y + attribute \src "libresoc.v:50335.18-50335.110" + wire $and$libresoc.v:50335$3073_Y + attribute \src "libresoc.v:50337.18-50337.98" + wire $and$libresoc.v:50337$3075_Y + attribute \src "libresoc.v:50339.18-50339.100" + wire $and$libresoc.v:50339$3077_Y + attribute \src "libresoc.v:50340.18-50340.149" + wire width 3 $and$libresoc.v:50340$3078_Y + attribute \src "libresoc.v:50342.18-50342.119" + wire width 3 $and$libresoc.v:50342$3080_Y + attribute \src "libresoc.v:50345.18-50345.116" + wire $and$libresoc.v:50345$3083_Y + attribute \src "libresoc.v:50349.17-50349.123" + wire $and$libresoc.v:50349$3087_Y + attribute \src "libresoc.v:50351.18-50351.113" + wire $and$libresoc.v:50351$3089_Y + attribute \src "libresoc.v:50352.18-50352.125" + wire width 3 $and$libresoc.v:50352$3090_Y + attribute \src "libresoc.v:50354.18-50354.112" + wire $and$libresoc.v:50354$3092_Y + attribute \src "libresoc.v:50356.18-50356.125" + wire $and$libresoc.v:50356$3094_Y + attribute \src "libresoc.v:50357.18-50357.125" + wire $and$libresoc.v:50357$3095_Y + attribute \src "libresoc.v:50358.18-50358.117" + wire $and$libresoc.v:50358$3096_Y + attribute \src "libresoc.v:50363.18-50363.129" + wire $and$libresoc.v:50363$3101_Y + attribute \src "libresoc.v:50364.18-50364.124" + wire width 3 $and$libresoc.v:50364$3102_Y + attribute \src "libresoc.v:50367.18-50367.116" + wire $and$libresoc.v:50367$3105_Y + attribute \src "libresoc.v:50368.18-50368.122" + wire $and$libresoc.v:50368$3106_Y + attribute \src "libresoc.v:50369.18-50369.119" + wire $and$libresoc.v:50369$3107_Y + attribute \src "libresoc.v:50377.18-50377.133" + wire $and$libresoc.v:50377$3115_Y + attribute \src "libresoc.v:50378.18-50378.131" + wire $and$libresoc.v:50378$3116_Y + attribute \src "libresoc.v:50379.18-50379.182" + wire width 6 $and$libresoc.v:50379$3117_Y + attribute \src "libresoc.v:50380.18-50380.113" + wire width 6 $and$libresoc.v:50380$3118_Y + attribute \src "libresoc.v:50353.18-50353.113" + wire $eq$libresoc.v:50353$3091_Y + attribute \src "libresoc.v:50355.18-50355.119" + wire $eq$libresoc.v:50355$3093_Y + attribute \src "libresoc.v:50336.18-50336.97" + wire $not$libresoc.v:50336$3074_Y + attribute \src "libresoc.v:50338.18-50338.99" + wire $not$libresoc.v:50338$3076_Y + attribute \src "libresoc.v:50341.18-50341.113" + wire width 3 $not$libresoc.v:50341$3079_Y + attribute \src "libresoc.v:50344.18-50344.106" + wire $not$libresoc.v:50344$3082_Y + attribute \src "libresoc.v:50350.18-50350.119" + wire $not$libresoc.v:50350$3088_Y + attribute \src "libresoc.v:50365.17-50365.113" + wire width 6 $not$libresoc.v:50365$3103_Y + attribute \src "libresoc.v:50381.18-50381.114" + wire width 6 $not$libresoc.v:50381$3119_Y + attribute \src "libresoc.v:50348.18-50348.112" + wire $or$libresoc.v:50348$3086_Y + attribute \src "libresoc.v:50359.18-50359.122" + wire $or$libresoc.v:50359$3097_Y + attribute \src "libresoc.v:50360.18-50360.124" + wire $or$libresoc.v:50360$3098_Y + attribute \src "libresoc.v:50361.18-50361.155" + wire width 3 $or$libresoc.v:50361$3099_Y + attribute \src "libresoc.v:50362.18-50362.194" + wire width 6 $or$libresoc.v:50362$3100_Y + attribute \src "libresoc.v:50366.18-50366.120" + wire width 3 $or$libresoc.v:50366$3104_Y + attribute \src "libresoc.v:50376.17-50376.117" + wire width 6 $or$libresoc.v:50376$3114_Y + attribute \src "libresoc.v:50325.17-50325.104" + wire $reduce_and$libresoc.v:50325$3063_Y + attribute \src "libresoc.v:50343.18-50343.106" + wire $reduce_or$libresoc.v:50343$3081_Y + attribute \src "libresoc.v:50346.18-50346.113" + wire $reduce_or$libresoc.v:50346$3084_Y + attribute \src "libresoc.v:50347.18-50347.112" + wire $reduce_or$libresoc.v:50347$3085_Y + attribute \src "libresoc.v:50370.18-50370.118" + wire width 64 $ternary$libresoc.v:50370$3108_Y + attribute \src "libresoc.v:50371.18-50371.118" + wire width 64 $ternary$libresoc.v:50371$3109_Y + attribute \src "libresoc.v:50372.18-50372.118" + wire width 32 $ternary$libresoc.v:50372$3110_Y + attribute \src "libresoc.v:50373.18-50373.118" + wire width 4 $ternary$libresoc.v:50373$3111_Y + attribute \src "libresoc.v:50374.18-50374.118" + wire width 4 $ternary$libresoc.v:50374$3112_Y + attribute \src "libresoc.v:50375.18-50375.118" + wire width 4 $ternary$libresoc.v:50375$3113_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -87136,23 +87441,24 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_cr0_cr_c attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_cr0_cr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_cr0_cr_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_cr0_cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_cr0_cr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_cr0_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -87231,6 +87537,7 @@ module \cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_cr0_cr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -87281,9 +87588,9 @@ module \cr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \cr_a_ok @@ -87341,7 +87648,7 @@ module \cr0 wire width 4 output 23 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 20 \full_cr_ok - attribute \src "libresoc.v:49478.7-49478.15" + attribute \src "libresoc.v:49783.7-49783.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 16 \o_ok @@ -87356,21 +87663,22 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_cr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" @@ -87447,6 +87755,7 @@ module \cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -87540,7 +87849,7 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50017$3064 + cell $and $and$libresoc.v:50326$3064 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87548,10 +87857,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:50017$3064_Y + connect \Y $and$libresoc.v:50326$3064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50018$3065 + cell $and $and$libresoc.v:50327$3065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87559,10 +87868,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50018$3065_Y + connect \Y $and$libresoc.v:50327$3065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50019$3066 + cell $and $and$libresoc.v:50328$3066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87570,10 +87879,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50019$3066_Y + connect \Y $and$libresoc.v:50328$3066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50020$3067 + cell $and $and$libresoc.v:50329$3067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87581,10 +87890,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50020$3067_Y + connect \Y $and$libresoc.v:50329$3067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50021$3068 + cell $and $and$libresoc.v:50330$3068 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87592,10 +87901,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:50021$3068_Y + connect \Y $and$libresoc.v:50330$3068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50022$3069 + cell $and $and$libresoc.v:50331$3069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87603,10 +87912,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50022$3069_Y + connect \Y $and$libresoc.v:50331$3069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50023$3070 + cell $and $and$libresoc.v:50332$3070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87614,10 +87923,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50023$3070_Y + connect \Y $and$libresoc.v:50332$3070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50024$3071 + cell $and $and$libresoc.v:50333$3071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87625,10 +87934,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50024$3071_Y + connect \Y $and$libresoc.v:50333$3071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50025$3072 + cell $and $and$libresoc.v:50334$3072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87636,10 +87945,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50025$3072_Y + connect \Y $and$libresoc.v:50334$3072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:50026$3073 + cell $and $and$libresoc.v:50335$3073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87647,10 +87956,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:50026$3073_Y + connect \Y $and$libresoc.v:50335$3073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50028$3075 + cell $and $and$libresoc.v:50337$3075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87658,10 +87967,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:50028$3075_Y + connect \Y $and$libresoc.v:50337$3075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50030$3077 + cell $and $and$libresoc.v:50339$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87669,10 +87978,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:50030$3077_Y + connect \Y $and$libresoc.v:50339$3077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:50031$3078 + cell $and $and$libresoc.v:50340$3078 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87680,10 +87989,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50031$3078_Y + connect \Y $and$libresoc.v:50340$3078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50033$3080 + cell $and $and$libresoc.v:50342$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87691,10 +88000,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:50033$3080_Y + connect \Y $and$libresoc.v:50342$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50036$3083 + cell $and $and$libresoc.v:50345$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87702,10 +88011,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:50036$3083_Y + connect \Y $and$libresoc.v:50345$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:50040$3087 + cell $and $and$libresoc.v:50349$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87713,10 +88022,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:50040$3087_Y + connect \Y $and$libresoc.v:50349$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:50042$3089 + cell $and $and$libresoc.v:50351$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87724,10 +88033,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:50042$3089_Y + connect \Y $and$libresoc.v:50351$3089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50043$3090 + cell $and $and$libresoc.v:50352$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87735,10 +88044,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50043$3090_Y + connect \Y $and$libresoc.v:50352$3090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50045$3092 + cell $and $and$libresoc.v:50354$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87746,10 +88055,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:50045$3092_Y + connect \Y $and$libresoc.v:50354$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50047$3094 + cell $and $and$libresoc.v:50356$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87757,10 +88066,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:50047$3094_Y + connect \Y $and$libresoc.v:50356$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50048$3095 + cell $and $and$libresoc.v:50357$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87768,10 +88077,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:50048$3095_Y + connect \Y $and$libresoc.v:50357$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50049$3096 + cell $and $and$libresoc.v:50358$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87779,10 +88088,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:50049$3096_Y + connect \Y $and$libresoc.v:50358$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:50054$3101 + cell $and $and$libresoc.v:50363$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87790,10 +88099,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:50054$3101_Y + connect \Y $and$libresoc.v:50363$3101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:50055$3102 + cell $and $and$libresoc.v:50364$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87801,10 +88110,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50055$3102_Y + connect \Y $and$libresoc.v:50364$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50058$3105 + cell $and $and$libresoc.v:50367$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87812,10 +88121,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50058$3105_Y + connect \Y $and$libresoc.v:50367$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50059$3106 + cell $and $and$libresoc.v:50368$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87823,10 +88132,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50059$3106_Y + connect \Y $and$libresoc.v:50368$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50060$3107 + cell $and $and$libresoc.v:50369$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87834,10 +88143,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50060$3107_Y + connect \Y $and$libresoc.v:50369$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:50068$3115 + cell $and $and$libresoc.v:50377$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87845,10 +88154,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:50068$3115_Y + connect \Y $and$libresoc.v:50377$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:50069$3116 + cell $and $and$libresoc.v:50378$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87856,10 +88165,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:50069$3116_Y + connect \Y $and$libresoc.v:50378$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50070$3117 + cell $and $and$libresoc.v:50379$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87867,10 +88176,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50070$3117_Y + connect \Y $and$libresoc.v:50379$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50071$3118 + cell $and $and$libresoc.v:50380$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87878,10 +88187,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:50071$3118_Y + connect \Y $and$libresoc.v:50380$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:50044$3091 + cell $eq $eq$libresoc.v:50353$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87889,10 +88198,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:50044$3091_Y + connect \Y $eq$libresoc.v:50353$3091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:50046$3093 + cell $eq $eq$libresoc.v:50355$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87900,66 +88209,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:50046$3093_Y + connect \Y $eq$libresoc.v:50355$3093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50027$3074 + cell $not $not$libresoc.v:50336$3074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:50027$3074_Y + connect \Y $not$libresoc.v:50336$3074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50029$3076 + cell $not $not$libresoc.v:50338$3076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:50029$3076_Y + connect \Y $not$libresoc.v:50338$3076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50032$3079 + cell $not $not$libresoc.v:50341$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:50032$3079_Y + connect \Y $not$libresoc.v:50341$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50035$3082 + cell $not $not$libresoc.v:50344$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:50035$3082_Y + connect \Y $not$libresoc.v:50344$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:50041$3088 + cell $not $not$libresoc.v:50350$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:50041$3088_Y + connect \Y $not$libresoc.v:50350$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:50056$3103 + cell $not $not$libresoc.v:50365$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:50056$3103_Y + connect \Y $not$libresoc.v:50365$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:50072$3119 + cell $not $not$libresoc.v:50381$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:50072$3119_Y + connect \Y $not$libresoc.v:50381$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:50039$3086 + cell $or $or$libresoc.v:50348$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87967,10 +88276,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:50039$3086_Y + connect \Y $or$libresoc.v:50348$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:50050$3097 + cell $or $or$libresoc.v:50359$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87978,10 +88287,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50050$3097_Y + connect \Y $or$libresoc.v:50359$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:50051$3098 + cell $or $or$libresoc.v:50360$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87989,10 +88298,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50051$3098_Y + connect \Y $or$libresoc.v:50360$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:50052$3099 + cell $or $or$libresoc.v:50361$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88000,10 +88309,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50052$3099_Y + connect \Y $or$libresoc.v:50361$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:50053$3100 + cell $or $or$libresoc.v:50362$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88011,10 +88320,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50053$3100_Y + connect \Y $or$libresoc.v:50362$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:50057$3104 + cell $or $or$libresoc.v:50366$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88022,10 +88331,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:50057$3104_Y + connect \Y $or$libresoc.v:50366$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:50067$3114 + cell $or $or$libresoc.v:50376$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88033,90 +88342,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:50067$3114_Y + connect \Y $or$libresoc.v:50376$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:50016$3063 + cell $reduce_and $reduce_and$libresoc.v:50325$3063 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:50016$3063_Y + connect \Y $reduce_and$libresoc.v:50325$3063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:50034$3081 + cell $reduce_or $reduce_or$libresoc.v:50343$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:50034$3081_Y + connect \Y $reduce_or$libresoc.v:50343$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50037$3084 + cell $reduce_or $reduce_or$libresoc.v:50346$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:50037$3084_Y + connect \Y $reduce_or$libresoc.v:50346$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50038$3085 + cell $reduce_or $reduce_or$libresoc.v:50347$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:50038$3085_Y + connect \Y $reduce_or$libresoc.v:50347$3085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50061$3108 + cell $mux $ternary$libresoc.v:50370$3108 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:50061$3108_Y + connect \Y $ternary$libresoc.v:50370$3108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50062$3109 + cell $mux $ternary$libresoc.v:50371$3109 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:50062$3109_Y + connect \Y $ternary$libresoc.v:50371$3109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50063$3110 + cell $mux $ternary$libresoc.v:50372$3110 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:50063$3110_Y + connect \Y $ternary$libresoc.v:50372$3110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50064$3111 + cell $mux $ternary$libresoc.v:50373$3111 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:50064$3111_Y + connect \Y $ternary$libresoc.v:50373$3111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50065$3112 + cell $mux $ternary$libresoc.v:50374$3112 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:50065$3112_Y + connect \Y $ternary$libresoc.v:50374$3112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50066$3113 + cell $mux $ternary$libresoc.v:50375$3113 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:50066$3113_Y + connect \Y $ternary$libresoc.v:50375$3113_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:50133.11-50155.4" + attribute \src "libresoc.v:50442.11-50464.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88141,7 +88450,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:50156.14-50162.4" + attribute \src "libresoc.v:50465.14-50471.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88150,7 +88459,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:50163.15-50169.4" + attribute \src "libresoc.v:50472.15-50478.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88159,7 +88468,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:50170.14-50176.4" + attribute \src "libresoc.v:50479.14-50485.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88168,7 +88477,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:50177.14-50183.4" + attribute \src "libresoc.v:50486.14-50492.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88177,7 +88486,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:50184.14-50190.4" + attribute \src "libresoc.v:50493.14-50499.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88186,7 +88495,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:50191.14-50196.4" + attribute \src "libresoc.v:50500.14-50505.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88194,7 +88503,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:50197.14-50203.4" + attribute \src "libresoc.v:50506.14-50512.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88202,472 +88511,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49478.7-49478.20" - process $proc$libresoc.v:49478$3242 + attribute \src "libresoc.v:49783.7-49783.20" + process $proc$libresoc.v:49783$3242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49596.7-49596.24" - process $proc$libresoc.v:49596$3243 + attribute \src "libresoc.v:49901.7-49901.24" + process $proc$libresoc.v:49901$3243 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:49626.14-49626.47" - process $proc$libresoc.v:49626$3244 + attribute \src "libresoc.v:49932.14-49932.47" + process $proc$libresoc.v:49932$3244 assign { } { } - assign $1\alu_cr0_cr_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[12:0] + update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:49630.14-49630.41" - process $proc$libresoc.v:49630$3245 + attribute \src "libresoc.v:49936.14-49936.41" + process $proc$libresoc.v:49936$3245 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:49708.13-49708.45" - process $proc$libresoc.v:49708$3246 + attribute \src "libresoc.v:50015.13-50015.45" + process $proc$libresoc.v:50015$3246 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:49732.7-49732.26" - process $proc$libresoc.v:49732$3247 + attribute \src "libresoc.v:50039.7-50039.26" + process $proc$libresoc.v:50039$3247 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:49740.7-49740.25" - process $proc$libresoc.v:49740$3248 + attribute \src "libresoc.v:50047.7-50047.25" + process $proc$libresoc.v:50047$3248 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:49752.7-49752.27" - process $proc$libresoc.v:49752$3249 + attribute \src "libresoc.v:50059.7-50059.27" + process $proc$libresoc.v:50059$3249 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:49786.14-49786.47" - process $proc$libresoc.v:49786$3250 + attribute \src "libresoc.v:50093.14-50093.47" + process $proc$libresoc.v:50093$3250 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:49790.7-49790.27" - process $proc$libresoc.v:49790$3251 + attribute \src "libresoc.v:50097.7-50097.27" + process $proc$libresoc.v:50097$3251 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:49794.14-49794.38" - process $proc$libresoc.v:49794$3252 + attribute \src "libresoc.v:50101.14-50101.38" + process $proc$libresoc.v:50101$3252 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:49798.7-49798.33" - process $proc$libresoc.v:49798$3253 + attribute \src "libresoc.v:50105.7-50105.33" + process $proc$libresoc.v:50105$3253 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:49802.13-49802.33" - process $proc$libresoc.v:49802$3254 + attribute \src "libresoc.v:50109.13-50109.33" + process $proc$libresoc.v:50109$3254 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:49806.7-49806.30" - process $proc$libresoc.v:49806$3255 + attribute \src "libresoc.v:50113.7-50113.30" + process $proc$libresoc.v:50113$3255 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:49825.7-49825.25" - process $proc$libresoc.v:49825$3256 + attribute \src "libresoc.v:50132.7-50132.25" + process $proc$libresoc.v:50132$3256 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:49829.7-49829.25" - process $proc$libresoc.v:49829$3257 + attribute \src "libresoc.v:50136.7-50136.25" + process $proc$libresoc.v:50136$3257 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:49927.13-49927.30" - process $proc$libresoc.v:49927$3258 + attribute \src "libresoc.v:50236.13-50236.30" + process $proc$libresoc.v:50236$3258 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:49935.13-49935.31" - process $proc$libresoc.v:49935$3259 + attribute \src "libresoc.v:50244.13-50244.31" + process $proc$libresoc.v:50244$3259 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:49939.13-49939.31" - process $proc$libresoc.v:49939$3260 + attribute \src "libresoc.v:50248.13-50248.31" + process $proc$libresoc.v:50248$3260 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:49951.7-49951.26" - process $proc$libresoc.v:49951$3261 + attribute \src "libresoc.v:50260.7-50260.26" + process $proc$libresoc.v:50260$3261 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:49955.7-49955.26" - process $proc$libresoc.v:49955$3262 + attribute \src "libresoc.v:50264.7-50264.26" + process $proc$libresoc.v:50264$3262 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:49959.7-49959.25" - process $proc$libresoc.v:49959$3263 + attribute \src "libresoc.v:50268.7-50268.25" + process $proc$libresoc.v:50268$3263 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:49963.7-49963.25" - process $proc$libresoc.v:49963$3264 + attribute \src "libresoc.v:50272.7-50272.25" + process $proc$libresoc.v:50272$3264 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:49983.13-49983.32" - process $proc$libresoc.v:49983$3265 + attribute \src "libresoc.v:50292.13-50292.32" + process $proc$libresoc.v:50292$3265 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:49987.13-49987.32" - process $proc$libresoc.v:49987$3266 + attribute \src "libresoc.v:50296.13-50296.32" + process $proc$libresoc.v:50296$3266 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:49991.14-49991.43" - process $proc$libresoc.v:49991$3267 + attribute \src "libresoc.v:50300.14-50300.43" + process $proc$libresoc.v:50300$3267 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:49995.14-49995.43" - process $proc$libresoc.v:49995$3268 + attribute \src "libresoc.v:50304.14-50304.43" + process $proc$libresoc.v:50304$3268 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:49999.14-49999.28" - process $proc$libresoc.v:49999$3269 + attribute \src "libresoc.v:50308.14-50308.28" + process $proc$libresoc.v:50308$3269 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:50003.13-50003.26" - process $proc$libresoc.v:50003$3270 + attribute \src "libresoc.v:50312.13-50312.26" + process $proc$libresoc.v:50312$3270 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:50007.13-50007.26" - process $proc$libresoc.v:50007$3271 + attribute \src "libresoc.v:50316.13-50316.26" + process $proc$libresoc.v:50316$3271 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:50011.13-50011.26" - process $proc$libresoc.v:50011$3272 + attribute \src "libresoc.v:50320.13-50320.26" + process $proc$libresoc.v:50320$3272 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:50073.3-50074.39" - process $proc$libresoc.v:50073$3120 + attribute \src "libresoc.v:50382.3-50383.39" + process $proc$libresoc.v:50382$3120 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50075.3-50076.43" - process $proc$libresoc.v:50075$3121 + attribute \src "libresoc.v:50384.3-50385.43" + process $proc$libresoc.v:50384$3121 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50077.3-50078.29" - process $proc$libresoc.v:50077$3122 + attribute \src "libresoc.v:50386.3-50387.29" + process $proc$libresoc.v:50386$3122 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:50079.3-50080.29" - process $proc$libresoc.v:50079$3123 + attribute \src "libresoc.v:50388.3-50389.29" + process $proc$libresoc.v:50388$3123 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:50081.3-50082.29" - process $proc$libresoc.v:50081$3124 + attribute \src "libresoc.v:50390.3-50391.29" + process $proc$libresoc.v:50390$3124 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:50083.3-50084.29" - process $proc$libresoc.v:50083$3125 + attribute \src "libresoc.v:50392.3-50393.29" + process $proc$libresoc.v:50392$3125 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:50085.3-50086.29" - process $proc$libresoc.v:50085$3126 + attribute \src "libresoc.v:50394.3-50395.29" + process $proc$libresoc.v:50394$3126 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:50087.3-50088.29" - process $proc$libresoc.v:50087$3127 + attribute \src "libresoc.v:50396.3-50397.29" + process $proc$libresoc.v:50396$3127 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:50089.3-50090.43" - process $proc$libresoc.v:50089$3128 + attribute \src "libresoc.v:50398.3-50399.43" + process $proc$libresoc.v:50398$3128 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50091.3-50092.49" - process $proc$libresoc.v:50091$3129 + attribute \src "libresoc.v:50400.3-50401.49" + process $proc$libresoc.v:50400$3129 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50093.3-50094.49" - process $proc$libresoc.v:50093$3130 + attribute \src "libresoc.v:50402.3-50403.49" + process $proc$libresoc.v:50402$3130 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50095.3-50096.55" - process $proc$libresoc.v:50095$3131 + attribute \src "libresoc.v:50404.3-50405.55" + process $proc$libresoc.v:50404$3131 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50097.3-50098.37" - process $proc$libresoc.v:50097$3132 + attribute \src "libresoc.v:50406.3-50407.37" + process $proc$libresoc.v:50406$3132 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:50099.3-50100.43" - process $proc$libresoc.v:50099$3133 + attribute \src "libresoc.v:50408.3-50409.43" + process $proc$libresoc.v:50408$3133 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50101.3-50102.65" - process $proc$libresoc.v:50101$3134 + attribute \src "libresoc.v:50410.3-50411.65" + process $proc$libresoc.v:50410$3134 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50103.3-50104.61" - process $proc$libresoc.v:50103$3135 + attribute \src "libresoc.v:50412.3-50413.61" + process $proc$libresoc.v:50412$3135 assign { } { } - assign $0\alu_cr0_cr_op__fn_unit[12:0] \alu_cr0_cr_op__fn_unit$next + assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk - update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[12:0] + update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:50105.3-50106.55" - process $proc$libresoc.v:50105$3136 + attribute \src "libresoc.v:50414.3-50415.55" + process $proc$libresoc.v:50414$3136 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50107.3-50108.39" - process $proc$libresoc.v:50107$3137 + attribute \src "libresoc.v:50416.3-50417.39" + process $proc$libresoc.v:50416$3137 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:50109.3-50110.39" - process $proc$libresoc.v:50109$3138 + attribute \src "libresoc.v:50418.3-50419.39" + process $proc$libresoc.v:50418$3138 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:50111.3-50112.39" - process $proc$libresoc.v:50111$3139 + attribute \src "libresoc.v:50420.3-50421.39" + process $proc$libresoc.v:50420$3139 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:50113.3-50114.39" - process $proc$libresoc.v:50113$3140 + attribute \src "libresoc.v:50422.3-50423.39" + process $proc$libresoc.v:50422$3140 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:50115.3-50116.39" - process $proc$libresoc.v:50115$3141 + attribute \src "libresoc.v:50424.3-50425.39" + process $proc$libresoc.v:50424$3141 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50117.3-50118.39" - process $proc$libresoc.v:50117$3142 + attribute \src "libresoc.v:50426.3-50427.39" + process $proc$libresoc.v:50426$3142 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50119.3-50120.39" - process $proc$libresoc.v:50119$3143 + attribute \src "libresoc.v:50428.3-50429.39" + process $proc$libresoc.v:50428$3143 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50121.3-50122.39" - process $proc$libresoc.v:50121$3144 + attribute \src "libresoc.v:50430.3-50431.39" + process $proc$libresoc.v:50430$3144 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50123.3-50124.41" - process $proc$libresoc.v:50123$3145 + attribute \src "libresoc.v:50432.3-50433.41" + process $proc$libresoc.v:50432$3145 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50125.3-50126.41" - process $proc$libresoc.v:50125$3146 + attribute \src "libresoc.v:50434.3-50435.41" + process $proc$libresoc.v:50434$3146 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50127.3-50128.37" - process $proc$libresoc.v:50127$3147 + attribute \src "libresoc.v:50436.3-50437.37" + process $proc$libresoc.v:50436$3147 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:50129.3-50130.39" - process $proc$libresoc.v:50129$3148 + attribute \src "libresoc.v:50438.3-50439.39" + process $proc$libresoc.v:50438$3148 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:50131.3-50132.25" - process $proc$libresoc.v:50131$3149 + attribute \src "libresoc.v:50440.3-50441.25" + process $proc$libresoc.v:50440$3149 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:50204.3-50213.6" - process $proc$libresoc.v:50204$3150 + attribute \src "libresoc.v:50513.3-50522.6" + process $proc$libresoc.v:50513$3150 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:50205.5-50205.29" + attribute \src "libresoc.v:50514.5-50514.29" switch \initial - attribute \src "libresoc.v:50205.9-50205.17" + attribute \src "libresoc.v:50514.9-50514.17" case 1'1 case end @@ -88683,14 +88992,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:50214.3-50222.6" - process $proc$libresoc.v:50214$3151 + attribute \src "libresoc.v:50523.3-50531.6" + process $proc$libresoc.v:50523$3151 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:50215.5-50215.29" + attribute \src "libresoc.v:50524.5-50524.29" switch \initial - attribute \src "libresoc.v:50215.9-50215.17" + attribute \src "libresoc.v:50524.9-50524.17" case 1'1 case end @@ -88706,14 +89015,14 @@ module \cr0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 end - attribute \src "libresoc.v:50223.3-50231.6" - process $proc$libresoc.v:50223$3154 + attribute \src "libresoc.v:50532.3-50540.6" + process $proc$libresoc.v:50532$3154 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:50224.5-50224.29" + attribute \src "libresoc.v:50533.5-50533.29" switch \initial - attribute \src "libresoc.v:50224.9-50224.17" + attribute \src "libresoc.v:50533.9-50533.17" case 1'1 case end @@ -88729,14 +89038,14 @@ module \cr0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 end - attribute \src "libresoc.v:50232.3-50240.6" - process $proc$libresoc.v:50232$3157 + attribute \src "libresoc.v:50541.3-50549.6" + process $proc$libresoc.v:50541$3157 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:50233.5-50233.29" + attribute \src "libresoc.v:50542.5-50542.29" switch \initial - attribute \src "libresoc.v:50233.9-50233.17" + attribute \src "libresoc.v:50542.9-50542.17" case 1'1 case end @@ -88752,14 +89061,14 @@ module \cr0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 end - attribute \src "libresoc.v:50241.3-50249.6" - process $proc$libresoc.v:50241$3160 + attribute \src "libresoc.v:50550.3-50558.6" + process $proc$libresoc.v:50550$3160 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:50242.5-50242.29" + attribute \src "libresoc.v:50551.5-50551.29" switch \initial - attribute \src "libresoc.v:50242.9-50242.17" + attribute \src "libresoc.v:50551.9-50551.17" case 1'1 case end @@ -88775,14 +89084,14 @@ module \cr0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 end - attribute \src "libresoc.v:50250.3-50258.6" - process $proc$libresoc.v:50250$3163 + attribute \src "libresoc.v:50559.3-50567.6" + process $proc$libresoc.v:50559$3163 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:50251.5-50251.29" + attribute \src "libresoc.v:50560.5-50560.29" switch \initial - attribute \src "libresoc.v:50251.9-50251.17" + attribute \src "libresoc.v:50560.9-50560.17" case 1'1 case end @@ -88798,14 +89107,14 @@ module \cr0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 end - attribute \src "libresoc.v:50259.3-50267.6" - process $proc$libresoc.v:50259$3166 + attribute \src "libresoc.v:50568.3-50576.6" + process $proc$libresoc.v:50568$3166 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:50260.5-50260.29" + attribute \src "libresoc.v:50569.5-50569.29" switch \initial - attribute \src "libresoc.v:50260.9-50260.17" + attribute \src "libresoc.v:50569.9-50569.17" case 1'1 case end @@ -88821,14 +89130,14 @@ module \cr0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 end - attribute \src "libresoc.v:50268.3-50276.6" - process $proc$libresoc.v:50268$3169 + attribute \src "libresoc.v:50577.3-50585.6" + process $proc$libresoc.v:50577$3169 assign { } { } assign { } { } assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:50269.5-50269.29" + attribute \src "libresoc.v:50578.5-50578.29" switch \initial - attribute \src "libresoc.v:50269.9-50269.17" + attribute \src "libresoc.v:50578.9-50578.17" case 1'1 case end @@ -88844,14 +89153,14 @@ module \cr0 sync always update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 end - attribute \src "libresoc.v:50277.3-50285.6" - process $proc$libresoc.v:50277$3172 + attribute \src "libresoc.v:50586.3-50594.6" + process $proc$libresoc.v:50586$3172 assign { } { } assign { } { } assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:50278.5-50278.29" + attribute \src "libresoc.v:50587.5-50587.29" switch \initial - attribute \src "libresoc.v:50278.9-50278.17" + attribute \src "libresoc.v:50587.9-50587.17" case 1'1 case end @@ -88867,14 +89176,14 @@ module \cr0 sync always update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 end - attribute \src "libresoc.v:50286.3-50294.6" - process $proc$libresoc.v:50286$3175 + attribute \src "libresoc.v:50595.3-50603.6" + process $proc$libresoc.v:50595$3175 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:50287.5-50287.29" + attribute \src "libresoc.v:50596.5-50596.29" switch \initial - attribute \src "libresoc.v:50287.9-50287.17" + attribute \src "libresoc.v:50596.9-50596.17" case 1'1 case end @@ -88890,14 +89199,14 @@ module \cr0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 end - attribute \src "libresoc.v:50295.3-50303.6" - process $proc$libresoc.v:50295$3178 + attribute \src "libresoc.v:50604.3-50612.6" + process $proc$libresoc.v:50604$3178 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50296.5-50296.29" + attribute \src "libresoc.v:50605.5-50605.29" switch \initial - attribute \src "libresoc.v:50296.9-50296.17" + attribute \src "libresoc.v:50605.9-50605.17" case 1'1 case end @@ -88913,20 +89222,20 @@ module \cr0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 end - attribute \src "libresoc.v:50304.3-50315.6" - process $proc$libresoc.v:50304$3181 + attribute \src "libresoc.v:50613.3-50624.6" + process $proc$libresoc.v:50613$3181 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_cr0_cr_op__fn_unit$next[12:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 + assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:50305.5-50305.29" + attribute \src "libresoc.v:50614.5-50614.29" switch \initial - attribute \src "libresoc.v:50305.9-50305.17" + attribute \src "libresoc.v:50614.9-50614.17" case 1'1 case end @@ -88937,19 +89246,19 @@ module \cr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } case - assign $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 \alu_cr0_cr_op__fn_unit assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type end sync always - update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[12:0]$3182 + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 end - attribute \src "libresoc.v:50316.3-50337.6" - process $proc$libresoc.v:50316$3188 + attribute \src "libresoc.v:50625.3-50646.6" + process $proc$libresoc.v:50625$3188 assign { } { } assign { } { } assign { } { } @@ -88959,9 +89268,9 @@ module \cr0 assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 assign { } { } assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50317.5-50317.29" + attribute \src "libresoc.v:50626.5-50626.29" switch \initial - attribute \src "libresoc.v:50317.9-50317.17" + attribute \src "libresoc.v:50626.9-50626.17" case 1'1 case end @@ -89000,8 +89309,8 @@ module \cr0 update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 end - attribute \src "libresoc.v:50338.3-50359.6" - process $proc$libresoc.v:50338$3196 + attribute \src "libresoc.v:50647.3-50668.6" + process $proc$libresoc.v:50647$3196 assign { } { } assign { } { } assign { } { } @@ -89011,9 +89320,9 @@ module \cr0 assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 assign { } { } assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50339.5-50339.29" + attribute \src "libresoc.v:50648.5-50648.29" switch \initial - attribute \src "libresoc.v:50339.9-50339.17" + attribute \src "libresoc.v:50648.9-50648.17" case 1'1 case end @@ -89052,8 +89361,8 @@ module \cr0 update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 end - attribute \src "libresoc.v:50360.3-50381.6" - process $proc$libresoc.v:50360$3204 + attribute \src "libresoc.v:50669.3-50690.6" + process $proc$libresoc.v:50669$3204 assign { } { } assign { } { } assign { } { } @@ -89063,9 +89372,9 @@ module \cr0 assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 assign { } { } assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50361.5-50361.29" + attribute \src "libresoc.v:50670.5-50670.29" switch \initial - attribute \src "libresoc.v:50361.9-50361.17" + attribute \src "libresoc.v:50670.9-50670.17" case 1'1 case end @@ -89104,14 +89413,14 @@ module \cr0 update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 end - attribute \src "libresoc.v:50382.3-50391.6" - process $proc$libresoc.v:50382$3212 + attribute \src "libresoc.v:50691.3-50700.6" + process $proc$libresoc.v:50691$3212 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50383.5-50383.29" + attribute \src "libresoc.v:50692.5-50692.29" switch \initial - attribute \src "libresoc.v:50383.9-50383.17" + attribute \src "libresoc.v:50692.9-50692.17" case 1'1 case end @@ -89127,14 +89436,14 @@ module \cr0 sync always update \src_r0$next $0\src_r0$next[63:0]$3213 end - attribute \src "libresoc.v:50392.3-50401.6" - process $proc$libresoc.v:50392$3215 + attribute \src "libresoc.v:50701.3-50710.6" + process $proc$libresoc.v:50701$3215 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50393.5-50393.29" + attribute \src "libresoc.v:50702.5-50702.29" switch \initial - attribute \src "libresoc.v:50393.9-50393.17" + attribute \src "libresoc.v:50702.9-50702.17" case 1'1 case end @@ -89150,14 +89459,14 @@ module \cr0 sync always update \src_r1$next $0\src_r1$next[63:0]$3216 end - attribute \src "libresoc.v:50402.3-50411.6" - process $proc$libresoc.v:50402$3218 + attribute \src "libresoc.v:50711.3-50720.6" + process $proc$libresoc.v:50711$3218 assign { } { } assign { } { } assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50403.5-50403.29" + attribute \src "libresoc.v:50712.5-50712.29" switch \initial - attribute \src "libresoc.v:50403.9-50403.17" + attribute \src "libresoc.v:50712.9-50712.17" case 1'1 case end @@ -89173,14 +89482,14 @@ module \cr0 sync always update \src_r2$next $0\src_r2$next[31:0]$3219 end - attribute \src "libresoc.v:50412.3-50421.6" - process $proc$libresoc.v:50412$3221 + attribute \src "libresoc.v:50721.3-50730.6" + process $proc$libresoc.v:50721$3221 assign { } { } assign { } { } assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50413.5-50413.29" + attribute \src "libresoc.v:50722.5-50722.29" switch \initial - attribute \src "libresoc.v:50413.9-50413.17" + attribute \src "libresoc.v:50722.9-50722.17" case 1'1 case end @@ -89196,14 +89505,14 @@ module \cr0 sync always update \src_r3$next $0\src_r3$next[3:0]$3222 end - attribute \src "libresoc.v:50422.3-50431.6" - process $proc$libresoc.v:50422$3224 + attribute \src "libresoc.v:50731.3-50740.6" + process $proc$libresoc.v:50731$3224 assign { } { } assign { } { } assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50423.5-50423.29" + attribute \src "libresoc.v:50732.5-50732.29" switch \initial - attribute \src "libresoc.v:50423.9-50423.17" + attribute \src "libresoc.v:50732.9-50732.17" case 1'1 case end @@ -89219,14 +89528,14 @@ module \cr0 sync always update \src_r4$next $0\src_r4$next[3:0]$3225 end - attribute \src "libresoc.v:50432.3-50441.6" - process $proc$libresoc.v:50432$3227 + attribute \src "libresoc.v:50741.3-50750.6" + process $proc$libresoc.v:50741$3227 assign { } { } assign { } { } assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50433.5-50433.29" + attribute \src "libresoc.v:50742.5-50742.29" switch \initial - attribute \src "libresoc.v:50433.9-50433.17" + attribute \src "libresoc.v:50742.9-50742.17" case 1'1 case end @@ -89242,14 +89551,14 @@ module \cr0 sync always update \src_r5$next $0\src_r5$next[3:0]$3228 end - attribute \src "libresoc.v:50442.3-50450.6" - process $proc$libresoc.v:50442$3230 + attribute \src "libresoc.v:50751.3-50759.6" + process $proc$libresoc.v:50751$3230 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50443.5-50443.29" + attribute \src "libresoc.v:50752.5-50752.29" switch \initial - attribute \src "libresoc.v:50443.9-50443.17" + attribute \src "libresoc.v:50752.9-50752.17" case 1'1 case end @@ -89265,14 +89574,14 @@ module \cr0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 end - attribute \src "libresoc.v:50451.3-50459.6" - process $proc$libresoc.v:50451$3233 + attribute \src "libresoc.v:50760.3-50768.6" + process $proc$libresoc.v:50760$3233 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50452.5-50452.29" + attribute \src "libresoc.v:50761.5-50761.29" switch \initial - attribute \src "libresoc.v:50452.9-50452.17" + attribute \src "libresoc.v:50761.9-50761.17" case 1'1 case end @@ -89288,14 +89597,14 @@ module \cr0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 end - attribute \src "libresoc.v:50460.3-50469.6" - process $proc$libresoc.v:50460$3236 + attribute \src "libresoc.v:50769.3-50778.6" + process $proc$libresoc.v:50769$3236 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50461.5-50461.29" + attribute \src "libresoc.v:50770.5-50770.29" switch \initial - attribute \src "libresoc.v:50461.9-50461.17" + attribute \src "libresoc.v:50770.9-50770.17" case 1'1 case end @@ -89311,14 +89620,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:50470.3-50479.6" - process $proc$libresoc.v:50470$3237 + attribute \src "libresoc.v:50779.3-50788.6" + process $proc$libresoc.v:50779$3237 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50471.5-50471.29" + attribute \src "libresoc.v:50780.5-50780.29" switch \initial - attribute \src "libresoc.v:50471.9-50471.17" + attribute \src "libresoc.v:50780.9-50780.17" case 1'1 case end @@ -89334,14 +89643,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:50480.3-50489.6" - process $proc$libresoc.v:50480$3238 + attribute \src "libresoc.v:50789.3-50798.6" + process $proc$libresoc.v:50789$3238 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50481.5-50481.29" + attribute \src "libresoc.v:50790.5-50790.29" switch \initial - attribute \src "libresoc.v:50481.9-50481.17" + attribute \src "libresoc.v:50790.9-50790.17" case 1'1 case end @@ -89357,14 +89666,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:50490.3-50498.6" - process $proc$libresoc.v:50490$3239 + attribute \src "libresoc.v:50799.3-50807.6" + process $proc$libresoc.v:50799$3239 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50491.5-50491.29" + attribute \src "libresoc.v:50800.5-50800.29" switch \initial - attribute \src "libresoc.v:50491.9-50491.17" + attribute \src "libresoc.v:50800.9-50800.17" case 1'1 case end @@ -89380,63 +89689,63 @@ module \cr0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 end - connect \$5 $reduce_and$libresoc.v:50016$3063_Y - connect \$99 $and$libresoc.v:50017$3064_Y - connect \$101 $and$libresoc.v:50018$3065_Y - connect \$103 $and$libresoc.v:50019$3066_Y - connect \$105 $and$libresoc.v:50020$3067_Y - connect \$107 $and$libresoc.v:50021$3068_Y - connect \$109 $and$libresoc.v:50022$3069_Y - connect \$111 $and$libresoc.v:50023$3070_Y - connect \$113 $and$libresoc.v:50024$3071_Y - connect \$115 $and$libresoc.v:50025$3072_Y - connect \$11 $and$libresoc.v:50026$3073_Y - connect \$13 $not$libresoc.v:50027$3074_Y - connect \$15 $and$libresoc.v:50028$3075_Y - connect \$17 $not$libresoc.v:50029$3076_Y - connect \$19 $and$libresoc.v:50030$3077_Y - connect \$21 $and$libresoc.v:50031$3078_Y - connect \$25 $not$libresoc.v:50032$3079_Y - connect \$27 $and$libresoc.v:50033$3080_Y - connect \$24 $reduce_or$libresoc.v:50034$3081_Y - connect \$23 $not$libresoc.v:50035$3082_Y - connect \$31 $and$libresoc.v:50036$3083_Y - connect \$33 $reduce_or$libresoc.v:50037$3084_Y - connect \$35 $reduce_or$libresoc.v:50038$3085_Y - connect \$37 $or$libresoc.v:50039$3086_Y - connect \$3 $and$libresoc.v:50040$3087_Y - connect \$39 $not$libresoc.v:50041$3088_Y - connect \$41 $and$libresoc.v:50042$3089_Y - connect \$43 $and$libresoc.v:50043$3090_Y - connect \$45 $eq$libresoc.v:50044$3091_Y - connect \$47 $and$libresoc.v:50045$3092_Y - connect \$49 $eq$libresoc.v:50046$3093_Y - connect \$51 $and$libresoc.v:50047$3094_Y - connect \$53 $and$libresoc.v:50048$3095_Y - connect \$55 $and$libresoc.v:50049$3096_Y - connect \$57 $or$libresoc.v:50050$3097_Y - connect \$59 $or$libresoc.v:50051$3098_Y - connect \$61 $or$libresoc.v:50052$3099_Y - connect \$63 $or$libresoc.v:50053$3100_Y - connect \$65 $and$libresoc.v:50054$3101_Y - connect \$67 $and$libresoc.v:50055$3102_Y - connect \$6 $not$libresoc.v:50056$3103_Y - connect \$69 $or$libresoc.v:50057$3104_Y - connect \$71 $and$libresoc.v:50058$3105_Y - connect \$73 $and$libresoc.v:50059$3106_Y - connect \$75 $and$libresoc.v:50060$3107_Y - connect \$77 $ternary$libresoc.v:50061$3108_Y - connect \$79 $ternary$libresoc.v:50062$3109_Y - connect \$81 $ternary$libresoc.v:50063$3110_Y - connect \$83 $ternary$libresoc.v:50064$3111_Y - connect \$85 $ternary$libresoc.v:50065$3112_Y - connect \$87 $ternary$libresoc.v:50066$3113_Y - connect \$8 $or$libresoc.v:50067$3114_Y - connect \$89 $and$libresoc.v:50068$3115_Y - connect \$91 $and$libresoc.v:50069$3116_Y - connect \$93 $and$libresoc.v:50070$3117_Y - connect \$95 $and$libresoc.v:50071$3118_Y - connect \$97 $not$libresoc.v:50072$3119_Y + connect \$5 $reduce_and$libresoc.v:50325$3063_Y + connect \$99 $and$libresoc.v:50326$3064_Y + connect \$101 $and$libresoc.v:50327$3065_Y + connect \$103 $and$libresoc.v:50328$3066_Y + connect \$105 $and$libresoc.v:50329$3067_Y + connect \$107 $and$libresoc.v:50330$3068_Y + connect \$109 $and$libresoc.v:50331$3069_Y + connect \$111 $and$libresoc.v:50332$3070_Y + connect \$113 $and$libresoc.v:50333$3071_Y + connect \$115 $and$libresoc.v:50334$3072_Y + connect \$11 $and$libresoc.v:50335$3073_Y + connect \$13 $not$libresoc.v:50336$3074_Y + connect \$15 $and$libresoc.v:50337$3075_Y + connect \$17 $not$libresoc.v:50338$3076_Y + connect \$19 $and$libresoc.v:50339$3077_Y + connect \$21 $and$libresoc.v:50340$3078_Y + connect \$25 $not$libresoc.v:50341$3079_Y + connect \$27 $and$libresoc.v:50342$3080_Y + connect \$24 $reduce_or$libresoc.v:50343$3081_Y + connect \$23 $not$libresoc.v:50344$3082_Y + connect \$31 $and$libresoc.v:50345$3083_Y + connect \$33 $reduce_or$libresoc.v:50346$3084_Y + connect \$35 $reduce_or$libresoc.v:50347$3085_Y + connect \$37 $or$libresoc.v:50348$3086_Y + connect \$3 $and$libresoc.v:50349$3087_Y + connect \$39 $not$libresoc.v:50350$3088_Y + connect \$41 $and$libresoc.v:50351$3089_Y + connect \$43 $and$libresoc.v:50352$3090_Y + connect \$45 $eq$libresoc.v:50353$3091_Y + connect \$47 $and$libresoc.v:50354$3092_Y + connect \$49 $eq$libresoc.v:50355$3093_Y + connect \$51 $and$libresoc.v:50356$3094_Y + connect \$53 $and$libresoc.v:50357$3095_Y + connect \$55 $and$libresoc.v:50358$3096_Y + connect \$57 $or$libresoc.v:50359$3097_Y + connect \$59 $or$libresoc.v:50360$3098_Y + connect \$61 $or$libresoc.v:50361$3099_Y + connect \$63 $or$libresoc.v:50362$3100_Y + connect \$65 $and$libresoc.v:50363$3101_Y + connect \$67 $and$libresoc.v:50364$3102_Y + connect \$6 $not$libresoc.v:50365$3103_Y + connect \$69 $or$libresoc.v:50366$3104_Y + connect \$71 $and$libresoc.v:50367$3105_Y + connect \$73 $and$libresoc.v:50368$3106_Y + connect \$75 $and$libresoc.v:50369$3107_Y + connect \$77 $ternary$libresoc.v:50370$3108_Y + connect \$79 $ternary$libresoc.v:50371$3109_Y + connect \$81 $ternary$libresoc.v:50372$3110_Y + connect \$83 $ternary$libresoc.v:50373$3111_Y + connect \$85 $ternary$libresoc.v:50374$3112_Y + connect \$87 $ternary$libresoc.v:50375$3113_Y + connect \$8 $or$libresoc.v:50376$3114_Y + connect \$89 $and$libresoc.v:50377$3115_Y + connect \$91 $and$libresoc.v:50378$3116_Y + connect \$93 $and$libresoc.v:50379$3117_Y + connect \$95 $and$libresoc.v:50380$3118_Y + connect \$97 $not$libresoc.v:50381$3119_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -89469,31 +89778,31 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:50534.1-50583.10" +attribute \src "libresoc.v:50843.1-50892.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:50535.7-50535.20" + attribute \src "libresoc.v:50844.7-50844.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50571.3-50579.6" + attribute \src "libresoc.v:50880.3-50888.6" wire $0\q_int$next[0:0]$3280 - attribute \src "libresoc.v:50569.3-50570.27" + attribute \src "libresoc.v:50878.3-50879.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:50571.3-50579.6" + attribute \src "libresoc.v:50880.3-50888.6" wire $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50553.7-50553.19" + attribute \src "libresoc.v:50862.7-50862.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:50566.17-50566.96" - wire $and$libresoc.v:50566$3275_Y - attribute \src "libresoc.v:50565.17-50565.92" - wire $not$libresoc.v:50565$3274_Y - attribute \src "libresoc.v:50568.17-50568.92" - wire $not$libresoc.v:50568$3277_Y - attribute \src "libresoc.v:50564.17-50564.98" - wire $or$libresoc.v:50564$3273_Y - attribute \src "libresoc.v:50567.17-50567.97" - wire $or$libresoc.v:50567$3276_Y + attribute \src "libresoc.v:50875.17-50875.96" + wire $and$libresoc.v:50875$3275_Y + attribute \src "libresoc.v:50874.17-50874.92" + wire $not$libresoc.v:50874$3274_Y + attribute \src "libresoc.v:50877.17-50877.92" + wire $not$libresoc.v:50877$3277_Y + attribute \src "libresoc.v:50873.17-50873.98" + wire $or$libresoc.v:50873$3273_Y + attribute \src "libresoc.v:50876.17-50876.97" + wire $or$libresoc.v:50876$3276_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -89504,11 +89813,11 @@ module \cyc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:50535.7-50535.15" + attribute \src "libresoc.v:50844.7-50844.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc @@ -89525,7 +89834,7 @@ module \cyc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:50566$3275 + cell $and $and$libresoc.v:50875$3275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89533,26 +89842,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:50566$3275_Y + connect \Y $and$libresoc.v:50875$3275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:50565$3274 + cell $not $not$libresoc.v:50874$3274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:50565$3274_Y + connect \Y $not$libresoc.v:50874$3274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:50568$3277 + cell $not $not$libresoc.v:50877$3277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:50568$3277_Y + connect \Y $not$libresoc.v:50877$3277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:50564$3273 + cell $or $or$libresoc.v:50873$3273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89560,10 +89869,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:50564$3273_Y + connect \Y $or$libresoc.v:50873$3273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:50567$3276 + cell $or $or$libresoc.v:50876$3276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89571,39 +89880,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:50567$3276_Y + connect \Y $or$libresoc.v:50876$3276_Y end - attribute \src "libresoc.v:50535.7-50535.20" - process $proc$libresoc.v:50535$3282 + attribute \src "libresoc.v:50844.7-50844.20" + process $proc$libresoc.v:50844$3282 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50553.7-50553.19" - process $proc$libresoc.v:50553$3283 + attribute \src "libresoc.v:50862.7-50862.19" + process $proc$libresoc.v:50862$3283 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:50569.3-50570.27" - process $proc$libresoc.v:50569$3278 + attribute \src "libresoc.v:50878.3-50879.27" + process $proc$libresoc.v:50878$3278 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:50571.3-50579.6" - process $proc$libresoc.v:50571$3279 + attribute \src "libresoc.v:50880.3-50888.6" + process $proc$libresoc.v:50880$3279 assign { } { } assign { } { } assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50572.5-50572.29" + attribute \src "libresoc.v:50881.5-50881.29" switch \initial - attribute \src "libresoc.v:50572.9-50572.17" + attribute \src "libresoc.v:50881.9-50881.17" case 1'1 case end @@ -89619,324 +89928,324 @@ module \cyc_l sync always update \q_int$next $0\q_int$next[0:0]$3280 end - connect \$9 $or$libresoc.v:50564$3273_Y - connect \$1 $not$libresoc.v:50565$3274_Y - connect \$3 $and$libresoc.v:50566$3275_Y - connect \$5 $or$libresoc.v:50567$3276_Y - connect \$7 $not$libresoc.v:50568$3277_Y + connect \$9 $or$libresoc.v:50873$3273_Y + connect \$1 $not$libresoc.v:50874$3274_Y + connect \$3 $and$libresoc.v:50875$3275_Y + connect \$5 $or$libresoc.v:50876$3276_Y + connect \$7 $not$libresoc.v:50877$3277_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:50587.1-51319.10" +attribute \src "libresoc.v:50896.1-51628.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:51132.3-51141.6" + attribute \src "libresoc.v:51441.3-51450.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:50939.3-50948.6" + attribute \src "libresoc.v:51248.3-51257.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:51142.3-51151.6" + attribute \src "libresoc.v:51451.3-51460.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:50921.3-50938.6" + attribute \src "libresoc.v:51230.3-51247.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:51152.3-51185.6" + attribute \src "libresoc.v:51461.3-51494.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:51123.3-51131.6" + attribute \src "libresoc.v:51432.3-51440.6" wire $0\dmi_read_log_data$next[0:0]$3398 - attribute \src "libresoc.v:50899.3-50900.51" + attribute \src "libresoc.v:51208.3-51209.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51114.3-51122.6" + attribute \src "libresoc.v:51423.3-51431.6" wire $0\dmi_read_log_data_1$next[0:0]$3395 - attribute \src "libresoc.v:50901.3-50902.55" + attribute \src "libresoc.v:51210.3-51211.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:50949.3-50957.6" + attribute \src "libresoc.v:51258.3-51266.6" wire $0\dmi_req_i_1$next[0:0]$3361 - attribute \src "libresoc.v:50911.3-50912.39" + attribute \src "libresoc.v:51220.3-51221.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51276.3-51309.6" + attribute \src "libresoc.v:51585.3-51618.6" wire $0\do_dmi_log_rd$next[0:0]$3425 - attribute \src "libresoc.v:50913.3-50914.43" + attribute \src "libresoc.v:51222.3-51223.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51246.3-51275.6" + attribute \src "libresoc.v:51555.3-51584.6" wire $0\do_icreset$next[0:0]$3418 - attribute \src "libresoc.v:50915.3-50916.37" + attribute \src "libresoc.v:51224.3-51225.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:51216.3-51245.6" + attribute \src "libresoc.v:51525.3-51554.6" wire $0\do_reset$next[0:0]$3411 - attribute \src "libresoc.v:50917.3-50918.33" + attribute \src "libresoc.v:51226.3-51227.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:51186.3-51215.6" + attribute \src "libresoc.v:51495.3-51524.6" wire $0\do_step$next[0:0]$3404 - attribute \src "libresoc.v:50919.3-50920.31" + attribute \src "libresoc.v:51228.3-51229.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:51052.3-51079.6" + attribute \src "libresoc.v:51361.3-51388.6" wire width 7 $0\gspr_index$next[6:0]$3383 - attribute \src "libresoc.v:50905.3-50906.37" + attribute \src "libresoc.v:51214.3-51215.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:50588.7-50588.20" + attribute \src "libresoc.v:50897.7-50897.20" wire $0\initial[0:0] - attribute \src "libresoc.v:51080.3-51113.6" + attribute \src "libresoc.v:51389.3-51422.6" wire width 32 $0\log_dmi_addr$next[31:0]$3389 - attribute \src "libresoc.v:50903.3-50904.41" + attribute \src "libresoc.v:51212.3-51213.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:51008.3-51051.6" + attribute \src "libresoc.v:51317.3-51360.6" wire $0\stopping$next[0:0]$3374 - attribute \src "libresoc.v:50907.3-50908.33" + attribute \src "libresoc.v:51216.3-51217.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $0\terminated$next[0:0]$3364 - attribute \src "libresoc.v:50909.3-50910.37" + attribute \src "libresoc.v:51218.3-51219.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:51132.3-51141.6" + attribute \src "libresoc.v:51441.3-51450.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:50939.3-50948.6" + attribute \src "libresoc.v:51248.3-51257.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51142.3-51151.6" + attribute \src "libresoc.v:51451.3-51460.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:50921.3-50938.6" + attribute \src "libresoc.v:51230.3-51247.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51152.3-51185.6" + attribute \src "libresoc.v:51461.3-51494.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:51123.3-51131.6" + attribute \src "libresoc.v:51432.3-51440.6" wire $1\dmi_read_log_data$next[0:0]$3399 - attribute \src "libresoc.v:50775.7-50775.31" + attribute \src "libresoc.v:51084.7-51084.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51114.3-51122.6" + attribute \src "libresoc.v:51423.3-51431.6" wire $1\dmi_read_log_data_1$next[0:0]$3396 - attribute \src "libresoc.v:50779.7-50779.33" + attribute \src "libresoc.v:51088.7-51088.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:50949.3-50957.6" + attribute \src "libresoc.v:51258.3-51266.6" wire $1\dmi_req_i_1$next[0:0]$3362 - attribute \src "libresoc.v:50785.7-50785.25" + attribute \src "libresoc.v:51094.7-51094.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51276.3-51309.6" + attribute \src "libresoc.v:51585.3-51618.6" wire $1\do_dmi_log_rd$next[0:0]$3426 - attribute \src "libresoc.v:50791.7-50791.27" + attribute \src "libresoc.v:51100.7-51100.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51246.3-51275.6" + attribute \src "libresoc.v:51555.3-51584.6" wire $1\do_icreset$next[0:0]$3419 - attribute \src "libresoc.v:50795.7-50795.24" + attribute \src "libresoc.v:51104.7-51104.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:51216.3-51245.6" + attribute \src "libresoc.v:51525.3-51554.6" wire $1\do_reset$next[0:0]$3412 - attribute \src "libresoc.v:50799.7-50799.22" + attribute \src "libresoc.v:51108.7-51108.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:51186.3-51215.6" + attribute \src "libresoc.v:51495.3-51524.6" wire $1\do_step$next[0:0]$3405 - attribute \src "libresoc.v:50803.7-50803.21" + attribute \src "libresoc.v:51112.7-51112.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:51052.3-51079.6" + attribute \src "libresoc.v:51361.3-51388.6" wire width 7 $1\gspr_index$next[6:0]$3384 - attribute \src "libresoc.v:50807.13-50807.31" + attribute \src "libresoc.v:51116.13-51116.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:51080.3-51113.6" + attribute \src "libresoc.v:51389.3-51422.6" wire width 32 $1\log_dmi_addr$next[31:0]$3390 - attribute \src "libresoc.v:50813.14-50813.34" + attribute \src "libresoc.v:51122.14-51122.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:51008.3-51051.6" + attribute \src "libresoc.v:51317.3-51360.6" wire $1\stopping$next[0:0]$3375 - attribute \src "libresoc.v:50825.7-50825.22" + attribute \src "libresoc.v:51134.7-51134.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $1\terminated$next[0:0]$3365 - attribute \src "libresoc.v:50831.7-50831.24" + attribute \src "libresoc.v:51140.7-51140.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:51276.3-51309.6" + attribute \src "libresoc.v:51585.3-51618.6" wire $2\do_dmi_log_rd$next[0:0]$3427 - attribute \src "libresoc.v:51246.3-51275.6" + attribute \src "libresoc.v:51555.3-51584.6" wire $2\do_icreset$next[0:0]$3420 - attribute \src "libresoc.v:51216.3-51245.6" + attribute \src "libresoc.v:51525.3-51554.6" wire $2\do_reset$next[0:0]$3413 - attribute \src "libresoc.v:51186.3-51215.6" + attribute \src "libresoc.v:51495.3-51524.6" wire $2\do_step$next[0:0]$3406 - attribute \src "libresoc.v:51052.3-51079.6" + attribute \src "libresoc.v:51361.3-51388.6" wire width 7 $2\gspr_index$next[6:0]$3385 - attribute \src "libresoc.v:51080.3-51113.6" + attribute \src "libresoc.v:51389.3-51422.6" wire width 32 $2\log_dmi_addr$next[31:0]$3391 - attribute \src "libresoc.v:51008.3-51051.6" + attribute \src "libresoc.v:51317.3-51360.6" wire $2\stopping$next[0:0]$3376 - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $2\terminated$next[0:0]$3366 - attribute \src "libresoc.v:51276.3-51309.6" + attribute \src "libresoc.v:51585.3-51618.6" wire $3\do_dmi_log_rd$next[0:0]$3428 - attribute \src "libresoc.v:51246.3-51275.6" + attribute \src "libresoc.v:51555.3-51584.6" wire $3\do_icreset$next[0:0]$3421 - attribute \src "libresoc.v:51216.3-51245.6" + attribute \src "libresoc.v:51525.3-51554.6" wire $3\do_reset$next[0:0]$3414 - attribute \src "libresoc.v:51186.3-51215.6" + attribute \src "libresoc.v:51495.3-51524.6" wire $3\do_step$next[0:0]$3407 - attribute \src "libresoc.v:51052.3-51079.6" + attribute \src "libresoc.v:51361.3-51388.6" wire width 7 $3\gspr_index$next[6:0]$3386 - attribute \src "libresoc.v:51080.3-51113.6" + attribute \src "libresoc.v:51389.3-51422.6" wire width 32 $3\log_dmi_addr$next[31:0]$3392 - attribute \src "libresoc.v:51008.3-51051.6" + attribute \src "libresoc.v:51317.3-51360.6" wire $3\stopping$next[0:0]$3377 - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $3\terminated$next[0:0]$3367 - attribute \src "libresoc.v:51276.3-51309.6" + attribute \src "libresoc.v:51585.3-51618.6" wire $4\do_dmi_log_rd$next[0:0]$3429 - attribute \src "libresoc.v:51246.3-51275.6" + attribute \src "libresoc.v:51555.3-51584.6" wire $4\do_icreset$next[0:0]$3422 - attribute \src "libresoc.v:51216.3-51245.6" + attribute \src "libresoc.v:51525.3-51554.6" wire $4\do_reset$next[0:0]$3415 - attribute \src "libresoc.v:51186.3-51215.6" + attribute \src "libresoc.v:51495.3-51524.6" wire $4\do_step$next[0:0]$3408 - attribute \src "libresoc.v:51052.3-51079.6" + attribute \src "libresoc.v:51361.3-51388.6" wire width 7 $4\gspr_index$next[6:0]$3387 - attribute \src "libresoc.v:51080.3-51113.6" + attribute \src "libresoc.v:51389.3-51422.6" wire width 32 $4\log_dmi_addr$next[31:0]$3393 - attribute \src "libresoc.v:51008.3-51051.6" + attribute \src "libresoc.v:51317.3-51360.6" wire $4\stopping$next[0:0]$3378 - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $4\terminated$next[0:0]$3368 - attribute \src "libresoc.v:51246.3-51275.6" + attribute \src "libresoc.v:51555.3-51584.6" wire $5\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:51216.3-51245.6" + attribute \src "libresoc.v:51525.3-51554.6" wire $5\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:51186.3-51215.6" + attribute \src "libresoc.v:51495.3-51524.6" wire $5\do_step$next[0:0]$3409 - attribute \src "libresoc.v:51008.3-51051.6" + attribute \src "libresoc.v:51317.3-51360.6" wire $5\stopping$next[0:0]$3379 - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $5\terminated$next[0:0]$3369 - attribute \src "libresoc.v:51008.3-51051.6" + attribute \src "libresoc.v:51317.3-51360.6" wire $6\stopping$next[0:0]$3380 - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $6\terminated$next[0:0]$3370 - attribute \src "libresoc.v:51008.3-51051.6" + attribute \src "libresoc.v:51317.3-51360.6" wire $7\stopping$next[0:0]$3381 - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $7\terminated$next[0:0]$3371 - attribute \src "libresoc.v:50958.3-51007.6" + attribute \src "libresoc.v:51267.3-51316.6" wire $8\terminated$next[0:0]$3372 - attribute \src "libresoc.v:50846.19-50846.110" - wire width 3 $add$libresoc.v:50846$3294_Y - attribute \src "libresoc.v:50840.19-50840.103" - wire $and$libresoc.v:50840$3288_Y - attribute \src "libresoc.v:50842.19-50842.113" - wire $and$libresoc.v:50842$3290_Y - attribute \src "libresoc.v:50847.18-50847.110" - wire $and$libresoc.v:50847$3295_Y - attribute \src "libresoc.v:50849.19-50849.103" - wire $and$libresoc.v:50849$3297_Y - attribute \src "libresoc.v:50851.19-50851.102" - wire $and$libresoc.v:50851$3299_Y - attribute \src "libresoc.v:50857.18-50857.101" - wire $and$libresoc.v:50857$3305_Y - attribute \src "libresoc.v:50859.18-50859.111" - wire $and$libresoc.v:50859$3307_Y - attribute \src "libresoc.v:50864.18-50864.101" - wire $and$libresoc.v:50864$3312_Y - attribute \src "libresoc.v:50867.18-50867.111" - wire $and$libresoc.v:50867$3315_Y - attribute \src "libresoc.v:50872.18-50872.101" - wire $and$libresoc.v:50872$3320_Y - attribute \src "libresoc.v:50874.18-50874.111" - wire $and$libresoc.v:50874$3322_Y - attribute \src "libresoc.v:50880.18-50880.101" - wire $and$libresoc.v:50880$3328_Y - attribute \src "libresoc.v:50882.18-50882.111" - wire $and$libresoc.v:50882$3330_Y - attribute \src "libresoc.v:50887.18-50887.101" - wire $and$libresoc.v:50887$3335_Y - attribute \src "libresoc.v:50888.17-50888.99" - wire $and$libresoc.v:50888$3336_Y - attribute \src "libresoc.v:50890.18-50890.111" - wire $and$libresoc.v:50890$3338_Y - attribute \src "libresoc.v:50895.18-50895.101" - wire $and$libresoc.v:50895$3343_Y - attribute \src "libresoc.v:50897.18-50897.111" - wire $and$libresoc.v:50897$3345_Y - attribute \src "libresoc.v:50837.18-50837.103" - wire $eq$libresoc.v:50837$3285_Y - attribute \src "libresoc.v:50838.19-50838.104" - wire $eq$libresoc.v:50838$3286_Y - attribute \src "libresoc.v:50843.19-50843.104" - wire $eq$libresoc.v:50843$3291_Y - attribute \src "libresoc.v:50844.19-50844.104" - wire $eq$libresoc.v:50844$3292_Y - attribute \src "libresoc.v:50845.19-50845.104" - wire $eq$libresoc.v:50845$3293_Y - attribute \src "libresoc.v:50848.19-50848.104" - wire $eq$libresoc.v:50848$3296_Y - attribute \src "libresoc.v:50852.18-50852.103" - wire $eq$libresoc.v:50852$3300_Y - attribute \src "libresoc.v:50853.18-50853.103" - wire $eq$libresoc.v:50853$3301_Y - attribute \src "libresoc.v:50854.18-50854.103" - wire $eq$libresoc.v:50854$3302_Y - attribute \src "libresoc.v:50860.18-50860.103" - wire $eq$libresoc.v:50860$3308_Y - attribute \src "libresoc.v:50861.18-50861.103" - wire $eq$libresoc.v:50861$3309_Y - attribute \src "libresoc.v:50862.18-50862.103" - wire $eq$libresoc.v:50862$3310_Y - attribute \src "libresoc.v:50868.18-50868.103" - wire $eq$libresoc.v:50868$3316_Y - attribute \src "libresoc.v:50869.18-50869.103" - wire $eq$libresoc.v:50869$3317_Y - attribute \src "libresoc.v:50870.18-50870.103" - wire $eq$libresoc.v:50870$3318_Y - attribute \src "libresoc.v:50875.18-50875.103" - wire $eq$libresoc.v:50875$3323_Y - attribute \src "libresoc.v:50876.18-50876.103" - wire $eq$libresoc.v:50876$3324_Y - attribute \src "libresoc.v:50878.18-50878.103" - wire $eq$libresoc.v:50878$3326_Y - attribute \src "libresoc.v:50883.18-50883.103" - wire $eq$libresoc.v:50883$3331_Y - attribute \src "libresoc.v:50884.18-50884.103" - wire $eq$libresoc.v:50884$3332_Y - attribute \src "libresoc.v:50885.18-50885.103" - wire $eq$libresoc.v:50885$3333_Y - attribute \src "libresoc.v:50891.18-50891.103" - wire $eq$libresoc.v:50891$3339_Y - attribute \src "libresoc.v:50892.18-50892.103" - wire $eq$libresoc.v:50892$3340_Y - attribute \src "libresoc.v:50893.18-50893.103" - wire $eq$libresoc.v:50893$3341_Y - attribute \src "libresoc.v:50898.18-50898.103" - wire $eq$libresoc.v:50898$3346_Y - attribute \src "libresoc.v:50836.17-50836.103" - wire $not$libresoc.v:50836$3284_Y - attribute \src "libresoc.v:50839.19-50839.99" - wire $not$libresoc.v:50839$3287_Y - attribute \src "libresoc.v:50841.19-50841.105" - wire $not$libresoc.v:50841$3289_Y - attribute \src "libresoc.v:50850.19-50850.95" - wire $not$libresoc.v:50850$3298_Y - attribute \src "libresoc.v:50856.18-50856.98" - wire $not$libresoc.v:50856$3304_Y - attribute \src "libresoc.v:50858.18-50858.104" - wire $not$libresoc.v:50858$3306_Y - attribute \src "libresoc.v:50863.18-50863.98" - wire $not$libresoc.v:50863$3311_Y - attribute \src "libresoc.v:50865.18-50865.104" - wire $not$libresoc.v:50865$3313_Y - attribute \src "libresoc.v:50871.18-50871.98" - wire $not$libresoc.v:50871$3319_Y - attribute \src "libresoc.v:50873.18-50873.104" - wire $not$libresoc.v:50873$3321_Y - attribute \src "libresoc.v:50877.17-50877.97" - wire $not$libresoc.v:50877$3325_Y - attribute \src "libresoc.v:50879.18-50879.98" - wire $not$libresoc.v:50879$3327_Y - attribute \src "libresoc.v:50881.18-50881.104" - wire $not$libresoc.v:50881$3329_Y - attribute \src "libresoc.v:50886.18-50886.98" - wire $not$libresoc.v:50886$3334_Y - attribute \src "libresoc.v:50889.18-50889.104" - wire $not$libresoc.v:50889$3337_Y - attribute \src "libresoc.v:50894.18-50894.98" - wire $not$libresoc.v:50894$3342_Y - attribute \src "libresoc.v:50896.18-50896.104" - wire $not$libresoc.v:50896$3344_Y - attribute \src "libresoc.v:50855.17-50855.126" - wire width 64 $pos$libresoc.v:50855$3303_Y - attribute \src "libresoc.v:50866.17-50866.245" - wire width 64 $pos$libresoc.v:50866$3314_Y + attribute \src "libresoc.v:51155.19-51155.110" + wire width 3 $add$libresoc.v:51155$3294_Y + attribute \src "libresoc.v:51149.19-51149.103" + wire $and$libresoc.v:51149$3288_Y + attribute \src "libresoc.v:51151.19-51151.113" + wire $and$libresoc.v:51151$3290_Y + attribute \src "libresoc.v:51156.18-51156.110" + wire $and$libresoc.v:51156$3295_Y + attribute \src "libresoc.v:51158.19-51158.103" + wire $and$libresoc.v:51158$3297_Y + attribute \src "libresoc.v:51160.19-51160.102" + wire $and$libresoc.v:51160$3299_Y + attribute \src "libresoc.v:51166.18-51166.101" + wire $and$libresoc.v:51166$3305_Y + attribute \src "libresoc.v:51168.18-51168.111" + wire $and$libresoc.v:51168$3307_Y + attribute \src "libresoc.v:51173.18-51173.101" + wire $and$libresoc.v:51173$3312_Y + attribute \src "libresoc.v:51176.18-51176.111" + wire $and$libresoc.v:51176$3315_Y + attribute \src "libresoc.v:51181.18-51181.101" + wire $and$libresoc.v:51181$3320_Y + attribute \src "libresoc.v:51183.18-51183.111" + wire $and$libresoc.v:51183$3322_Y + attribute \src "libresoc.v:51189.18-51189.101" + wire $and$libresoc.v:51189$3328_Y + attribute \src "libresoc.v:51191.18-51191.111" + wire $and$libresoc.v:51191$3330_Y + attribute \src "libresoc.v:51196.18-51196.101" + wire $and$libresoc.v:51196$3335_Y + attribute \src "libresoc.v:51197.17-51197.99" + wire $and$libresoc.v:51197$3336_Y + attribute \src "libresoc.v:51199.18-51199.111" + wire $and$libresoc.v:51199$3338_Y + attribute \src "libresoc.v:51204.18-51204.101" + wire $and$libresoc.v:51204$3343_Y + attribute \src "libresoc.v:51206.18-51206.111" + wire $and$libresoc.v:51206$3345_Y + attribute \src "libresoc.v:51146.18-51146.103" + wire $eq$libresoc.v:51146$3285_Y + attribute \src "libresoc.v:51147.19-51147.104" + wire $eq$libresoc.v:51147$3286_Y + attribute \src "libresoc.v:51152.19-51152.104" + wire $eq$libresoc.v:51152$3291_Y + attribute \src "libresoc.v:51153.19-51153.104" + wire $eq$libresoc.v:51153$3292_Y + attribute \src "libresoc.v:51154.19-51154.104" + wire $eq$libresoc.v:51154$3293_Y + attribute \src "libresoc.v:51157.19-51157.104" + wire $eq$libresoc.v:51157$3296_Y + attribute \src "libresoc.v:51161.18-51161.103" + wire $eq$libresoc.v:51161$3300_Y + attribute \src "libresoc.v:51162.18-51162.103" + wire $eq$libresoc.v:51162$3301_Y + attribute \src "libresoc.v:51163.18-51163.103" + wire $eq$libresoc.v:51163$3302_Y + attribute \src "libresoc.v:51169.18-51169.103" + wire $eq$libresoc.v:51169$3308_Y + attribute \src "libresoc.v:51170.18-51170.103" + wire $eq$libresoc.v:51170$3309_Y + attribute \src "libresoc.v:51171.18-51171.103" + wire $eq$libresoc.v:51171$3310_Y + attribute \src "libresoc.v:51177.18-51177.103" + wire $eq$libresoc.v:51177$3316_Y + attribute \src "libresoc.v:51178.18-51178.103" + wire $eq$libresoc.v:51178$3317_Y + attribute \src "libresoc.v:51179.18-51179.103" + wire $eq$libresoc.v:51179$3318_Y + attribute \src "libresoc.v:51184.18-51184.103" + wire $eq$libresoc.v:51184$3323_Y + attribute \src "libresoc.v:51185.18-51185.103" + wire $eq$libresoc.v:51185$3324_Y + attribute \src "libresoc.v:51187.18-51187.103" + wire $eq$libresoc.v:51187$3326_Y + attribute \src "libresoc.v:51192.18-51192.103" + wire $eq$libresoc.v:51192$3331_Y + attribute \src "libresoc.v:51193.18-51193.103" + wire $eq$libresoc.v:51193$3332_Y + attribute \src "libresoc.v:51194.18-51194.103" + wire $eq$libresoc.v:51194$3333_Y + attribute \src "libresoc.v:51200.18-51200.103" + wire $eq$libresoc.v:51200$3339_Y + attribute \src "libresoc.v:51201.18-51201.103" + wire $eq$libresoc.v:51201$3340_Y + attribute \src "libresoc.v:51202.18-51202.103" + wire $eq$libresoc.v:51202$3341_Y + attribute \src "libresoc.v:51207.18-51207.103" + wire $eq$libresoc.v:51207$3346_Y + attribute \src "libresoc.v:51145.17-51145.103" + wire $not$libresoc.v:51145$3284_Y + attribute \src "libresoc.v:51148.19-51148.99" + wire $not$libresoc.v:51148$3287_Y + attribute \src "libresoc.v:51150.19-51150.105" + wire $not$libresoc.v:51150$3289_Y + attribute \src "libresoc.v:51159.19-51159.95" + wire $not$libresoc.v:51159$3298_Y + attribute \src "libresoc.v:51165.18-51165.98" + wire $not$libresoc.v:51165$3304_Y + attribute \src "libresoc.v:51167.18-51167.104" + wire $not$libresoc.v:51167$3306_Y + attribute \src "libresoc.v:51172.18-51172.98" + wire $not$libresoc.v:51172$3311_Y + attribute \src "libresoc.v:51174.18-51174.104" + wire $not$libresoc.v:51174$3313_Y + attribute \src "libresoc.v:51180.18-51180.98" + wire $not$libresoc.v:51180$3319_Y + attribute \src "libresoc.v:51182.18-51182.104" + wire $not$libresoc.v:51182$3321_Y + attribute \src "libresoc.v:51186.17-51186.97" + wire $not$libresoc.v:51186$3325_Y + attribute \src "libresoc.v:51188.18-51188.98" + wire $not$libresoc.v:51188$3327_Y + attribute \src "libresoc.v:51190.18-51190.104" + wire $not$libresoc.v:51190$3329_Y + attribute \src "libresoc.v:51195.18-51195.98" + wire $not$libresoc.v:51195$3334_Y + attribute \src "libresoc.v:51198.18-51198.104" + wire $not$libresoc.v:51198$3337_Y + attribute \src "libresoc.v:51203.18-51203.98" + wire $not$libresoc.v:51203$3342_Y + attribute \src "libresoc.v:51205.18-51205.104" + wire $not$libresoc.v:51205$3344_Y + attribute \src "libresoc.v:51164.17-51164.126" + wire width 64 $pos$libresoc.v:51164$3303_Y + attribute \src "libresoc.v:51175.17-51175.245" + wire width 64 $pos$libresoc.v:51175$3314_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" @@ -90065,7 +90374,7 @@ module \dbg wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 30 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 input 13 \core_dbg_core_dbg_dststep @@ -90084,7 +90393,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 10 \core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" - wire output 7 \core_rst_o + wire output 8 \core_rst_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" wire output 18 \core_stop_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" @@ -90110,13 +90419,13 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire output 27 \d_xer_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" - wire output 5 \dmi_ack_o + wire output 6 \dmi_ack_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 4 input 1 \dmi_addr_i + wire width 4 input 2 \dmi_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 input 4 \dmi_din + wire width 64 input 5 \dmi_din attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire width 64 output 6 \dmi_dout + wire width 64 output 7 \dmi_dout attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" wire \dmi_read_log_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" @@ -90126,13 +90435,13 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" wire \dmi_read_log_data_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire input 2 \dmi_req_i + wire input 3 \dmi_req_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire \dmi_req_i_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire \dmi_req_i_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire input 3 \dmi_we_i + wire input 4 \dmi_we_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" wire \do_dmi_log_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" @@ -90155,7 +90464,7 @@ module \dbg wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" wire \icache_rst_o - attribute \src "libresoc.v:50588.7-50588.15" + attribute \src "libresoc.v:50897.7-50897.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr @@ -90165,8 +90474,8 @@ module \dbg wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 8 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 64 \stat_reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" @@ -90182,7 +90491,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" - cell $add $add$libresoc.v:50846$3294 + cell $add $add$libresoc.v:51155$3294 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -90190,10 +90499,10 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:50846$3294_Y + connect \Y $add$libresoc.v:51155$3294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:50840$3288 + cell $and $and$libresoc.v:51149$3288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90201,10 +90510,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$103 - connect \Y $and$libresoc.v:50840$3288_Y + connect \Y $and$libresoc.v:51149$3288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:50842$3290 + cell $and $and$libresoc.v:51151$3290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90212,10 +90521,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$107 - connect \Y $and$libresoc.v:50842$3290_Y + connect \Y $and$libresoc.v:51151$3290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:50847$3295 + cell $and $and$libresoc.v:51156$3295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90223,10 +90532,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$9 - connect \Y $and$libresoc.v:50847$3295_Y + connect \Y $and$libresoc.v:51156$3295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $and $and$libresoc.v:50849$3297 + cell $and $and$libresoc.v:51158$3297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90234,10 +90543,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$120 - connect \Y $and$libresoc.v:50849$3297_Y + connect \Y $and$libresoc.v:51158$3297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $and $and$libresoc.v:50851$3299 + cell $and $and$libresoc.v:51160$3299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90245,10 +90554,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \stopping connect \B \$124 - connect \Y $and$libresoc.v:50851$3299_Y + connect \Y $and$libresoc.v:51160$3299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:50857$3305 + cell $and $and$libresoc.v:51166$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90256,10 +90565,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$19 - connect \Y $and$libresoc.v:50857$3305_Y + connect \Y $and$libresoc.v:51166$3305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:50859$3307 + cell $and $and$libresoc.v:51168$3307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90267,10 +90576,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$23 - connect \Y $and$libresoc.v:50859$3307_Y + connect \Y $and$libresoc.v:51168$3307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:50864$3312 + cell $and $and$libresoc.v:51173$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90278,10 +90587,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$33 - connect \Y $and$libresoc.v:50864$3312_Y + connect \Y $and$libresoc.v:51173$3312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:50867$3315 + cell $and $and$libresoc.v:51176$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90289,10 +90598,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$37 - connect \Y $and$libresoc.v:50867$3315_Y + connect \Y $and$libresoc.v:51176$3315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:50872$3320 + cell $and $and$libresoc.v:51181$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90300,10 +90609,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$47 - connect \Y $and$libresoc.v:50872$3320_Y + connect \Y $and$libresoc.v:51181$3320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:50874$3322 + cell $and $and$libresoc.v:51183$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90311,10 +90620,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$51 - connect \Y $and$libresoc.v:50874$3322_Y + connect \Y $and$libresoc.v:51183$3322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:50880$3328 + cell $and $and$libresoc.v:51189$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90322,10 +90631,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$61 - connect \Y $and$libresoc.v:50880$3328_Y + connect \Y $and$libresoc.v:51189$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:50882$3330 + cell $and $and$libresoc.v:51191$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90333,10 +90642,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$65 - connect \Y $and$libresoc.v:50882$3330_Y + connect \Y $and$libresoc.v:51191$3330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:50887$3335 + cell $and $and$libresoc.v:51196$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90344,10 +90653,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$75 - connect \Y $and$libresoc.v:50887$3335_Y + connect \Y $and$libresoc.v:51196$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:50888$3336 + cell $and $and$libresoc.v:51197$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90355,10 +90664,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$5 - connect \Y $and$libresoc.v:50888$3336_Y + connect \Y $and$libresoc.v:51197$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:50890$3338 + cell $and $and$libresoc.v:51199$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90366,10 +90675,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$79 - connect \Y $and$libresoc.v:50890$3338_Y + connect \Y $and$libresoc.v:51199$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:50895$3343 + cell $and $and$libresoc.v:51204$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90377,10 +90686,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$89 - connect \Y $and$libresoc.v:50895$3343_Y + connect \Y $and$libresoc.v:51204$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:50897$3345 + cell $and $and$libresoc.v:51206$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90388,10 +90697,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$93 - connect \Y $and$libresoc.v:50897$3345_Y + connect \Y $and$libresoc.v:51206$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:50837$3285 + cell $eq $eq$libresoc.v:51146$3285 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90399,10 +90708,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50837$3285_Y + connect \Y $eq$libresoc.v:51146$3285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:50838$3286 + cell $eq $eq$libresoc.v:51147$3286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90410,10 +90719,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50838$3286_Y + connect \Y $eq$libresoc.v:51147$3286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:50843$3291 + cell $eq $eq$libresoc.v:51152$3291 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90421,10 +90730,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50843$3291_Y + connect \Y $eq$libresoc.v:51152$3291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:50844$3292 + cell $eq $eq$libresoc.v:51153$3292 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90432,10 +90741,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50844$3292_Y + connect \Y $eq$libresoc.v:51153$3292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:50845$3293 + cell $eq $eq$libresoc.v:51154$3293 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90443,10 +90752,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50845$3293_Y + connect \Y $eq$libresoc.v:51154$3293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $eq $eq$libresoc.v:50848$3296 + cell $eq $eq$libresoc.v:51157$3296 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90454,10 +90763,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:50848$3296_Y + connect \Y $eq$libresoc.v:51157$3296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:50852$3300 + cell $eq $eq$libresoc.v:51161$3300 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90465,10 +90774,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50852$3300_Y + connect \Y $eq$libresoc.v:51161$3300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:50853$3301 + cell $eq $eq$libresoc.v:51162$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90476,10 +90785,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50853$3301_Y + connect \Y $eq$libresoc.v:51162$3301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:50854$3302 + cell $eq $eq$libresoc.v:51163$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90487,10 +90796,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50854$3302_Y + connect \Y $eq$libresoc.v:51163$3302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:50860$3308 + cell $eq $eq$libresoc.v:51169$3308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90498,10 +90807,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50860$3308_Y + connect \Y $eq$libresoc.v:51169$3308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:50861$3309 + cell $eq $eq$libresoc.v:51170$3309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90509,10 +90818,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50861$3309_Y + connect \Y $eq$libresoc.v:51170$3309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:50862$3310 + cell $eq $eq$libresoc.v:51171$3310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90520,10 +90829,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50862$3310_Y + connect \Y $eq$libresoc.v:51171$3310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:50868$3316 + cell $eq $eq$libresoc.v:51177$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90531,10 +90840,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50868$3316_Y + connect \Y $eq$libresoc.v:51177$3316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:50869$3317 + cell $eq $eq$libresoc.v:51178$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90542,10 +90851,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50869$3317_Y + connect \Y $eq$libresoc.v:51178$3317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:50870$3318 + cell $eq $eq$libresoc.v:51179$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90553,10 +90862,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50870$3318_Y + connect \Y $eq$libresoc.v:51179$3318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:50875$3323 + cell $eq $eq$libresoc.v:51184$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90564,10 +90873,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50875$3323_Y + connect \Y $eq$libresoc.v:51184$3323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:50876$3324 + cell $eq $eq$libresoc.v:51185$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90575,10 +90884,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50876$3324_Y + connect \Y $eq$libresoc.v:51185$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:50878$3326 + cell $eq $eq$libresoc.v:51187$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90586,10 +90895,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50878$3326_Y + connect \Y $eq$libresoc.v:51187$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:50883$3331 + cell $eq $eq$libresoc.v:51192$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90597,10 +90906,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50883$3331_Y + connect \Y $eq$libresoc.v:51192$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:50884$3332 + cell $eq $eq$libresoc.v:51193$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90608,10 +90917,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50884$3332_Y + connect \Y $eq$libresoc.v:51193$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:50885$3333 + cell $eq $eq$libresoc.v:51194$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90619,10 +90928,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50885$3333_Y + connect \Y $eq$libresoc.v:51194$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:50891$3339 + cell $eq $eq$libresoc.v:51200$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90630,10 +90939,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50891$3339_Y + connect \Y $eq$libresoc.v:51200$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:50892$3340 + cell $eq $eq$libresoc.v:51201$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90641,10 +90950,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50892$3340_Y + connect \Y $eq$libresoc.v:51201$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:50893$3341 + cell $eq $eq$libresoc.v:51202$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90652,10 +90961,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50893$3341_Y + connect \Y $eq$libresoc.v:51202$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:50898$3346 + cell $eq $eq$libresoc.v:51207$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90663,340 +90972,340 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50898$3346_Y + connect \Y $eq$libresoc.v:51207$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:50836$3284 + cell $not $not$libresoc.v:51145$3284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50836$3284_Y + connect \Y $not$libresoc.v:51145$3284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:50839$3287 + cell $not $not$libresoc.v:51148$3287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50839$3287_Y + connect \Y $not$libresoc.v:51148$3287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:50841$3289 + cell $not $not$libresoc.v:51150$3289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50841$3289_Y + connect \Y $not$libresoc.v:51150$3289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $not $not$libresoc.v:50850$3298 + cell $not $not$libresoc.v:51159$3298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:50850$3298_Y + connect \Y $not$libresoc.v:51159$3298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:50856$3304 + cell $not $not$libresoc.v:51165$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50856$3304_Y + connect \Y $not$libresoc.v:51165$3304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:50858$3306 + cell $not $not$libresoc.v:51167$3306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50858$3306_Y + connect \Y $not$libresoc.v:51167$3306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:50863$3311 + cell $not $not$libresoc.v:51172$3311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50863$3311_Y + connect \Y $not$libresoc.v:51172$3311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:50865$3313 + cell $not $not$libresoc.v:51174$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50865$3313_Y + connect \Y $not$libresoc.v:51174$3313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:50871$3319 + cell $not $not$libresoc.v:51180$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50871$3319_Y + connect \Y $not$libresoc.v:51180$3319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:50873$3321 + cell $not $not$libresoc.v:51182$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50873$3321_Y + connect \Y $not$libresoc.v:51182$3321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:50877$3325 + cell $not $not$libresoc.v:51186$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50877$3325_Y + connect \Y $not$libresoc.v:51186$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:50879$3327 + cell $not $not$libresoc.v:51188$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50879$3327_Y + connect \Y $not$libresoc.v:51188$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:50881$3329 + cell $not $not$libresoc.v:51190$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50881$3329_Y + connect \Y $not$libresoc.v:51190$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:50886$3334 + cell $not $not$libresoc.v:51195$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50886$3334_Y + connect \Y $not$libresoc.v:51195$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:50889$3337 + cell $not $not$libresoc.v:51198$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50889$3337_Y + connect \Y $not$libresoc.v:51198$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:50894$3342 + cell $not $not$libresoc.v:51203$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50894$3342_Y + connect \Y $not$libresoc.v:51203$3342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:50896$3344 + cell $not $not$libresoc.v:51205$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50896$3344_Y + connect \Y $not$libresoc.v:51205$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $pos $pos$libresoc.v:50855$3303 + cell $pos $pos$libresoc.v:51164$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:50855$3303_Y + connect \Y $pos$libresoc.v:51164$3303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:50866$3314 + cell $pos $pos$libresoc.v:51175$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } - connect \Y $pos$libresoc.v:50866$3314_Y + connect \Y $pos$libresoc.v:51175$3314_Y end - attribute \src "libresoc.v:50588.7-50588.20" - process $proc$libresoc.v:50588$3430 + attribute \src "libresoc.v:50897.7-50897.20" + process $proc$libresoc.v:50897$3430 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50775.7-50775.31" - process $proc$libresoc.v:50775$3431 + attribute \src "libresoc.v:51084.7-51084.31" + process $proc$libresoc.v:51084$3431 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:50779.7-50779.33" - process $proc$libresoc.v:50779$3432 + attribute \src "libresoc.v:51088.7-51088.33" + process $proc$libresoc.v:51088$3432 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:50785.7-50785.25" - process $proc$libresoc.v:50785$3433 + attribute \src "libresoc.v:51094.7-51094.25" + process $proc$libresoc.v:51094$3433 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:50791.7-50791.27" - process $proc$libresoc.v:50791$3434 + attribute \src "libresoc.v:51100.7-51100.27" + process $proc$libresoc.v:51100$3434 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:50795.7-50795.24" - process $proc$libresoc.v:50795$3435 + attribute \src "libresoc.v:51104.7-51104.24" + process $proc$libresoc.v:51104$3435 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:50799.7-50799.22" - process $proc$libresoc.v:50799$3436 + attribute \src "libresoc.v:51108.7-51108.22" + process $proc$libresoc.v:51108$3436 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:50803.7-50803.21" - process $proc$libresoc.v:50803$3437 + attribute \src "libresoc.v:51112.7-51112.21" + process $proc$libresoc.v:51112$3437 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:50807.13-50807.31" - process $proc$libresoc.v:50807$3438 + attribute \src "libresoc.v:51116.13-51116.31" + process $proc$libresoc.v:51116$3438 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:50813.14-50813.34" - process $proc$libresoc.v:50813$3439 + attribute \src "libresoc.v:51122.14-51122.34" + process $proc$libresoc.v:51122$3439 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:50825.7-50825.22" - process $proc$libresoc.v:50825$3440 + attribute \src "libresoc.v:51134.7-51134.22" + process $proc$libresoc.v:51134$3440 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:50831.7-50831.24" - process $proc$libresoc.v:50831$3441 + attribute \src "libresoc.v:51140.7-51140.24" + process $proc$libresoc.v:51140$3441 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:50899.3-50900.51" - process $proc$libresoc.v:50899$3347 + attribute \src "libresoc.v:51208.3-51209.51" + process $proc$libresoc.v:51208$3347 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:50901.3-50902.55" - process $proc$libresoc.v:50901$3348 + attribute \src "libresoc.v:51210.3-51211.55" + process $proc$libresoc.v:51210$3348 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:50903.3-50904.41" - process $proc$libresoc.v:50903$3349 + attribute \src "libresoc.v:51212.3-51213.41" + process $proc$libresoc.v:51212$3349 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:50905.3-50906.37" - process $proc$libresoc.v:50905$3350 + attribute \src "libresoc.v:51214.3-51215.37" + process $proc$libresoc.v:51214$3350 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:50907.3-50908.33" - process $proc$libresoc.v:50907$3351 + attribute \src "libresoc.v:51216.3-51217.33" + process $proc$libresoc.v:51216$3351 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:50909.3-50910.37" - process $proc$libresoc.v:50909$3352 + attribute \src "libresoc.v:51218.3-51219.37" + process $proc$libresoc.v:51218$3352 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:50911.3-50912.39" - process $proc$libresoc.v:50911$3353 + attribute \src "libresoc.v:51220.3-51221.39" + process $proc$libresoc.v:51220$3353 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:50913.3-50914.43" - process $proc$libresoc.v:50913$3354 + attribute \src "libresoc.v:51222.3-51223.43" + process $proc$libresoc.v:51222$3354 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:50915.3-50916.37" - process $proc$libresoc.v:50915$3355 + attribute \src "libresoc.v:51224.3-51225.37" + process $proc$libresoc.v:51224$3355 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:50917.3-50918.33" - process $proc$libresoc.v:50917$3356 + attribute \src "libresoc.v:51226.3-51227.33" + process $proc$libresoc.v:51226$3356 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:50919.3-50920.31" - process $proc$libresoc.v:50919$3357 + attribute \src "libresoc.v:51228.3-51229.31" + process $proc$libresoc.v:51228$3357 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:50921.3-50938.6" - process $proc$libresoc.v:50921$3358 + attribute \src "libresoc.v:51230.3-51247.6" + process $proc$libresoc.v:51230$3358 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:50922.5-50922.29" + attribute \src "libresoc.v:51231.5-51231.29" switch \initial - attribute \src "libresoc.v:50922.9-50922.17" + attribute \src "libresoc.v:51231.9-51231.17" case 1'1 case end @@ -91022,14 +91331,14 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:50939.3-50948.6" - process $proc$libresoc.v:50939$3359 + attribute \src "libresoc.v:51248.3-51257.6" + process $proc$libresoc.v:51248$3359 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:50940.5-50940.29" + attribute \src "libresoc.v:51249.5-51249.29" switch \initial - attribute \src "libresoc.v:50940.9-50940.17" + attribute \src "libresoc.v:51249.9-51249.17" case 1'1 case end @@ -91045,14 +91354,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:50949.3-50957.6" - process $proc$libresoc.v:50949$3360 + attribute \src "libresoc.v:51258.3-51266.6" + process $proc$libresoc.v:51258$3360 assign { } { } assign { } { } assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362 - attribute \src "libresoc.v:50950.5-50950.29" + attribute \src "libresoc.v:51259.5-51259.29" switch \initial - attribute \src "libresoc.v:50950.9-50950.17" + attribute \src "libresoc.v:51259.9-51259.17" case 1'1 case end @@ -91068,16 +91377,16 @@ module \dbg sync always update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361 end - attribute \src "libresoc.v:50958.3-51007.6" - process $proc$libresoc.v:50958$3363 + attribute \src "libresoc.v:51267.3-51316.6" + process $proc$libresoc.v:51267$3363 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372 - attribute \src "libresoc.v:50959.5-50959.29" + attribute \src "libresoc.v:51268.5-51268.29" switch \initial - attribute \src "libresoc.v:50959.9-50959.17" + attribute \src "libresoc.v:51268.9-51268.17" case 1'1 case end @@ -91158,16 +91467,16 @@ module \dbg sync always update \terminated$next $0\terminated$next[0:0]$3364 end - attribute \src "libresoc.v:51008.3-51051.6" - process $proc$libresoc.v:51008$3373 + attribute \src "libresoc.v:51317.3-51360.6" + process $proc$libresoc.v:51317$3373 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381 - attribute \src "libresoc.v:51009.5-51009.29" + attribute \src "libresoc.v:51318.5-51318.29" switch \initial - attribute \src "libresoc.v:51009.9-51009.17" + attribute \src "libresoc.v:51318.9-51318.17" case 1'1 case end @@ -91238,15 +91547,15 @@ module \dbg sync always update \stopping$next $0\stopping$next[0:0]$3374 end - attribute \src "libresoc.v:51052.3-51079.6" - process $proc$libresoc.v:51052$3382 + attribute \src "libresoc.v:51361.3-51388.6" + process $proc$libresoc.v:51361$3382 assign { } { } assign { } { } assign { } { } assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387 - attribute \src "libresoc.v:51053.5-51053.29" + attribute \src "libresoc.v:51362.5-51362.29" switch \initial - attribute \src "libresoc.v:51053.9-51053.17" + attribute \src "libresoc.v:51362.9-51362.17" case 1'1 case end @@ -91292,15 +91601,15 @@ module \dbg sync always update \gspr_index$next $0\gspr_index$next[6:0]$3383 end - attribute \src "libresoc.v:51080.3-51113.6" - process $proc$libresoc.v:51080$3388 + attribute \src "libresoc.v:51389.3-51422.6" + process $proc$libresoc.v:51389$3388 assign { } { } assign { } { } assign { } { } assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393 - attribute \src "libresoc.v:51081.5-51081.29" + attribute \src "libresoc.v:51390.5-51390.29" switch \initial - attribute \src "libresoc.v:51081.9-51081.17" + attribute \src "libresoc.v:51390.9-51390.17" case 1'1 case end @@ -91353,14 +91662,14 @@ module \dbg sync always update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389 end - attribute \src "libresoc.v:51114.3-51122.6" - process $proc$libresoc.v:51114$3394 + attribute \src "libresoc.v:51423.3-51431.6" + process $proc$libresoc.v:51423$3394 assign { } { } assign { } { } assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396 - attribute \src "libresoc.v:51115.5-51115.29" + attribute \src "libresoc.v:51424.5-51424.29" switch \initial - attribute \src "libresoc.v:51115.9-51115.17" + attribute \src "libresoc.v:51424.9-51424.17" case 1'1 case end @@ -91376,14 +91685,14 @@ module \dbg sync always update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395 end - attribute \src "libresoc.v:51123.3-51131.6" - process $proc$libresoc.v:51123$3397 + attribute \src "libresoc.v:51432.3-51440.6" + process $proc$libresoc.v:51432$3397 assign { } { } assign { } { } assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399 - attribute \src "libresoc.v:51124.5-51124.29" + attribute \src "libresoc.v:51433.5-51433.29" switch \initial - attribute \src "libresoc.v:51124.9-51124.17" + attribute \src "libresoc.v:51433.9-51433.17" case 1'1 case end @@ -91399,14 +91708,14 @@ module \dbg sync always update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398 end - attribute \src "libresoc.v:51132.3-51141.6" - process $proc$libresoc.v:51132$3400 + attribute \src "libresoc.v:51441.3-51450.6" + process $proc$libresoc.v:51441$3400 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:51133.5-51133.29" + attribute \src "libresoc.v:51442.5-51442.29" switch \initial - attribute \src "libresoc.v:51133.9-51133.17" + attribute \src "libresoc.v:51442.9-51442.17" case 1'1 case end @@ -91422,14 +91731,14 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:51142.3-51151.6" - process $proc$libresoc.v:51142$3401 + attribute \src "libresoc.v:51451.3-51460.6" + process $proc$libresoc.v:51451$3401 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:51143.5-51143.29" + attribute \src "libresoc.v:51452.5-51452.29" switch \initial - attribute \src "libresoc.v:51143.9-51143.17" + attribute \src "libresoc.v:51452.9-51452.17" case 1'1 case end @@ -91445,14 +91754,14 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:51152.3-51185.6" - process $proc$libresoc.v:51152$3402 + attribute \src "libresoc.v:51461.3-51494.6" + process $proc$libresoc.v:51461$3402 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:51153.5-51153.29" + attribute \src "libresoc.v:51462.5-51462.29" switch \initial - attribute \src "libresoc.v:51153.9-51153.17" + attribute \src "libresoc.v:51462.9-51462.17" case 1'1 case end @@ -91500,15 +91809,15 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:51186.3-51215.6" - process $proc$libresoc.v:51186$3403 + attribute \src "libresoc.v:51495.3-51524.6" + process $proc$libresoc.v:51495$3403 assign { } { } assign { } { } assign { } { } assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409 - attribute \src "libresoc.v:51187.5-51187.29" + attribute \src "libresoc.v:51496.5-51496.29" switch \initial - attribute \src "libresoc.v:51187.9-51187.17" + attribute \src "libresoc.v:51496.9-51496.17" case 1'1 case end @@ -91560,15 +91869,15 @@ module \dbg sync always update \do_step$next $0\do_step$next[0:0]$3404 end - attribute \src "libresoc.v:51216.3-51245.6" - process $proc$libresoc.v:51216$3410 + attribute \src "libresoc.v:51525.3-51554.6" + process $proc$libresoc.v:51525$3410 assign { } { } assign { } { } assign { } { } assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:51217.5-51217.29" + attribute \src "libresoc.v:51526.5-51526.29" switch \initial - attribute \src "libresoc.v:51217.9-51217.17" + attribute \src "libresoc.v:51526.9-51526.17" case 1'1 case end @@ -91620,15 +91929,15 @@ module \dbg sync always update \do_reset$next $0\do_reset$next[0:0]$3411 end - attribute \src "libresoc.v:51246.3-51275.6" - process $proc$libresoc.v:51246$3417 + attribute \src "libresoc.v:51555.3-51584.6" + process $proc$libresoc.v:51555$3417 assign { } { } assign { } { } assign { } { } assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:51247.5-51247.29" + attribute \src "libresoc.v:51556.5-51556.29" switch \initial - attribute \src "libresoc.v:51247.9-51247.17" + attribute \src "libresoc.v:51556.9-51556.17" case 1'1 case end @@ -91680,15 +91989,15 @@ module \dbg sync always update \do_icreset$next $0\do_icreset$next[0:0]$3418 end - attribute \src "libresoc.v:51276.3-51309.6" - process $proc$libresoc.v:51276$3424 + attribute \src "libresoc.v:51585.3-51618.6" + process $proc$libresoc.v:51585$3424 assign { } { } assign { } { } assign { } { } assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429 - attribute \src "libresoc.v:51277.5-51277.29" + attribute \src "libresoc.v:51586.5-51586.29" switch \initial - attribute \src "libresoc.v:51277.9-51277.17" + attribute \src "libresoc.v:51586.9-51586.17" case 1'1 case end @@ -91741,69 +92050,69 @@ module \dbg sync always update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3425 end - connect \$9 $not$libresoc.v:50836$3284_Y - connect \$99 $eq$libresoc.v:50837$3285_Y - connect \$101 $eq$libresoc.v:50838$3286_Y - connect \$103 $not$libresoc.v:50839$3287_Y - connect \$105 $and$libresoc.v:50840$3288_Y - connect \$107 $not$libresoc.v:50841$3289_Y - connect \$109 $and$libresoc.v:50842$3290_Y - connect \$111 $eq$libresoc.v:50843$3291_Y - connect \$113 $eq$libresoc.v:50844$3292_Y - connect \$115 $eq$libresoc.v:50845$3293_Y - connect \$118 $add$libresoc.v:50846$3294_Y - connect \$11 $and$libresoc.v:50847$3295_Y - connect \$120 $eq$libresoc.v:50848$3296_Y - connect \$122 $and$libresoc.v:50849$3297_Y - connect \$124 $not$libresoc.v:50850$3298_Y - connect \$126 $and$libresoc.v:50851$3299_Y - connect \$13 $eq$libresoc.v:50852$3300_Y - connect \$15 $eq$libresoc.v:50853$3301_Y - connect \$17 $eq$libresoc.v:50854$3302_Y - connect \$1 $pos$libresoc.v:50855$3303_Y - connect \$19 $not$libresoc.v:50856$3304_Y - connect \$21 $and$libresoc.v:50857$3305_Y - connect \$23 $not$libresoc.v:50858$3306_Y - connect \$25 $and$libresoc.v:50859$3307_Y - connect \$27 $eq$libresoc.v:50860$3308_Y - connect \$29 $eq$libresoc.v:50861$3309_Y - connect \$31 $eq$libresoc.v:50862$3310_Y - connect \$33 $not$libresoc.v:50863$3311_Y - connect \$35 $and$libresoc.v:50864$3312_Y - connect \$37 $not$libresoc.v:50865$3313_Y - connect \$3 $pos$libresoc.v:50866$3314_Y - connect \$39 $and$libresoc.v:50867$3315_Y - connect \$41 $eq$libresoc.v:50868$3316_Y - connect \$43 $eq$libresoc.v:50869$3317_Y - connect \$45 $eq$libresoc.v:50870$3318_Y - connect \$47 $not$libresoc.v:50871$3319_Y - connect \$49 $and$libresoc.v:50872$3320_Y - connect \$51 $not$libresoc.v:50873$3321_Y - connect \$53 $and$libresoc.v:50874$3322_Y - connect \$55 $eq$libresoc.v:50875$3323_Y - connect \$57 $eq$libresoc.v:50876$3324_Y - connect \$5 $not$libresoc.v:50877$3325_Y - connect \$59 $eq$libresoc.v:50878$3326_Y - connect \$61 $not$libresoc.v:50879$3327_Y - connect \$63 $and$libresoc.v:50880$3328_Y - connect \$65 $not$libresoc.v:50881$3329_Y - connect \$67 $and$libresoc.v:50882$3330_Y - connect \$69 $eq$libresoc.v:50883$3331_Y - connect \$71 $eq$libresoc.v:50884$3332_Y - connect \$73 $eq$libresoc.v:50885$3333_Y - connect \$75 $not$libresoc.v:50886$3334_Y - connect \$77 $and$libresoc.v:50887$3335_Y - connect \$7 $and$libresoc.v:50888$3336_Y - connect \$79 $not$libresoc.v:50889$3337_Y - connect \$81 $and$libresoc.v:50890$3338_Y - connect \$83 $eq$libresoc.v:50891$3339_Y - connect \$85 $eq$libresoc.v:50892$3340_Y - connect \$87 $eq$libresoc.v:50893$3341_Y - connect \$89 $not$libresoc.v:50894$3342_Y - connect \$91 $and$libresoc.v:50895$3343_Y - connect \$93 $not$libresoc.v:50896$3344_Y - connect \$95 $and$libresoc.v:50897$3345_Y - connect \$97 $eq$libresoc.v:50898$3346_Y + connect \$9 $not$libresoc.v:51145$3284_Y + connect \$99 $eq$libresoc.v:51146$3285_Y + connect \$101 $eq$libresoc.v:51147$3286_Y + connect \$103 $not$libresoc.v:51148$3287_Y + connect \$105 $and$libresoc.v:51149$3288_Y + connect \$107 $not$libresoc.v:51150$3289_Y + connect \$109 $and$libresoc.v:51151$3290_Y + connect \$111 $eq$libresoc.v:51152$3291_Y + connect \$113 $eq$libresoc.v:51153$3292_Y + connect \$115 $eq$libresoc.v:51154$3293_Y + connect \$118 $add$libresoc.v:51155$3294_Y + connect \$11 $and$libresoc.v:51156$3295_Y + connect \$120 $eq$libresoc.v:51157$3296_Y + connect \$122 $and$libresoc.v:51158$3297_Y + connect \$124 $not$libresoc.v:51159$3298_Y + connect \$126 $and$libresoc.v:51160$3299_Y + connect \$13 $eq$libresoc.v:51161$3300_Y + connect \$15 $eq$libresoc.v:51162$3301_Y + connect \$17 $eq$libresoc.v:51163$3302_Y + connect \$1 $pos$libresoc.v:51164$3303_Y + connect \$19 $not$libresoc.v:51165$3304_Y + connect \$21 $and$libresoc.v:51166$3305_Y + connect \$23 $not$libresoc.v:51167$3306_Y + connect \$25 $and$libresoc.v:51168$3307_Y + connect \$27 $eq$libresoc.v:51169$3308_Y + connect \$29 $eq$libresoc.v:51170$3309_Y + connect \$31 $eq$libresoc.v:51171$3310_Y + connect \$33 $not$libresoc.v:51172$3311_Y + connect \$35 $and$libresoc.v:51173$3312_Y + connect \$37 $not$libresoc.v:51174$3313_Y + connect \$3 $pos$libresoc.v:51175$3314_Y + connect \$39 $and$libresoc.v:51176$3315_Y + connect \$41 $eq$libresoc.v:51177$3316_Y + connect \$43 $eq$libresoc.v:51178$3317_Y + connect \$45 $eq$libresoc.v:51179$3318_Y + connect \$47 $not$libresoc.v:51180$3319_Y + connect \$49 $and$libresoc.v:51181$3320_Y + connect \$51 $not$libresoc.v:51182$3321_Y + connect \$53 $and$libresoc.v:51183$3322_Y + connect \$55 $eq$libresoc.v:51184$3323_Y + connect \$57 $eq$libresoc.v:51185$3324_Y + connect \$5 $not$libresoc.v:51186$3325_Y + connect \$59 $eq$libresoc.v:51187$3326_Y + connect \$61 $not$libresoc.v:51188$3327_Y + connect \$63 $and$libresoc.v:51189$3328_Y + connect \$65 $not$libresoc.v:51190$3329_Y + connect \$67 $and$libresoc.v:51191$3330_Y + connect \$69 $eq$libresoc.v:51192$3331_Y + connect \$71 $eq$libresoc.v:51193$3332_Y + connect \$73 $eq$libresoc.v:51194$3333_Y + connect \$75 $not$libresoc.v:51195$3334_Y + connect \$77 $and$libresoc.v:51196$3335_Y + connect \$7 $and$libresoc.v:51197$3336_Y + connect \$79 $not$libresoc.v:51198$3337_Y + connect \$81 $and$libresoc.v:51199$3338_Y + connect \$83 $eq$libresoc.v:51200$3339_Y + connect \$85 $eq$libresoc.v:51201$3340_Y + connect \$87 $eq$libresoc.v:51202$3341_Y + connect \$89 $not$libresoc.v:51203$3342_Y + connect \$91 $and$libresoc.v:51204$3343_Y + connect \$93 $not$libresoc.v:51205$3344_Y + connect \$95 $and$libresoc.v:51206$3345_Y + connect \$97 $eq$libresoc.v:51207$3346_Y connect \$117 \$118 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -91814,71 +92123,71 @@ module \dbg connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end -attribute \src "libresoc.v:51323.1-53367.10" +attribute \src "libresoc.v:51632.1-53682.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec - attribute \src "libresoc.v:52928.3-52961.6" + attribute \src "libresoc.v:53243.3-53276.6" wire width 3 $0\ALU_cr_in[2:0] - attribute \src "libresoc.v:52962.3-52995.6" + attribute \src "libresoc.v:53277.3-53310.6" wire width 3 $0\ALU_cr_out[2:0] - attribute \src "libresoc.v:52588.3-52621.6" + attribute \src "libresoc.v:52903.3-52936.6" wire width 2 $0\ALU_cry_in[1:0] - attribute \src "libresoc.v:52690.3-52723.6" + attribute \src "libresoc.v:53005.3-53038.6" wire $0\ALU_cry_out[0:0] - attribute \src "libresoc.v:52792.3-52825.6" - wire width 13 $0\ALU_function_unit[12:0] - attribute \src "libresoc.v:52860.3-52893.6" + attribute \src "libresoc.v:53107.3-53140.6" + wire width 14 $0\ALU_function_unit[13:0] + attribute \src "libresoc.v:53175.3-53208.6" wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52894.3-52927.6" + attribute \src "libresoc.v:53209.3-53242.6" wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "libresoc.v:52826.3-52859.6" + attribute \src "libresoc.v:53141.3-53174.6" wire width 7 $0\ALU_internal_op[6:0] - attribute \src "libresoc.v:52622.3-52655.6" + attribute \src "libresoc.v:52937.3-52970.6" wire $0\ALU_inv_a[0:0] - attribute \src "libresoc.v:52656.3-52689.6" + attribute \src "libresoc.v:52971.3-53004.6" wire $0\ALU_inv_out[0:0] - attribute \src "libresoc.v:52724.3-52757.6" + attribute \src "libresoc.v:53039.3-53072.6" wire $0\ALU_is_32b[0:0] - attribute \src "libresoc.v:52996.3-53029.6" + attribute \src "libresoc.v:53311.3-53344.6" wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52554.3-52587.6" + attribute \src "libresoc.v:52869.3-52902.6" wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52758.3-52791.6" + attribute \src "libresoc.v:53073.3-53106.6" wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:51324.7-51324.20" + attribute \src "libresoc.v:51633.7-51633.20" wire $0\initial[0:0] - attribute \src "libresoc.v:52928.3-52961.6" + attribute \src "libresoc.v:53243.3-53276.6" wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:52962.3-52995.6" + attribute \src "libresoc.v:53277.3-53310.6" wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52588.3-52621.6" + attribute \src "libresoc.v:52903.3-52936.6" wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52690.3-52723.6" + attribute \src "libresoc.v:53005.3-53038.6" wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:52792.3-52825.6" - wire width 13 $1\ALU_function_unit[12:0] - attribute \src "libresoc.v:52860.3-52893.6" + attribute \src "libresoc.v:53107.3-53140.6" + wire width 14 $1\ALU_function_unit[13:0] + attribute \src "libresoc.v:53175.3-53208.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52894.3-52927.6" + attribute \src "libresoc.v:53209.3-53242.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:52826.3-52859.6" + attribute \src "libresoc.v:53141.3-53174.6" wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:52622.3-52655.6" + attribute \src "libresoc.v:52937.3-52970.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52656.3-52689.6" + attribute \src "libresoc.v:52971.3-53004.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52724.3-52757.6" + attribute \src "libresoc.v:53039.3-53072.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:52996.3-53029.6" + attribute \src "libresoc.v:53311.3-53344.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52554.3-52587.6" + attribute \src "libresoc.v:52869.3-52902.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52758.3-52791.6" + attribute \src "libresoc.v:53073.3-53106.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52519.17-52519.211" - wire width 32 $ternary$libresoc.v:52519$3442_Y + attribute \src "libresoc.v:52834.17-52834.211" + wire width 32 $ternary$libresoc.v:52834$3442_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -91926,6 +92235,8 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 24 \ALU_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \ALU_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 17 \ALU_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_RB @@ -92004,21 +92315,22 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec19_ALU_dec19_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \ALU_dec19_ALU_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec19_ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -92118,6 +92430,7 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec19_ALU_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -92173,21 +92486,22 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \ALU_dec31_ALU_dec31_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \ALU_dec31_ALU_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \ALU_dec31_ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -92287,6 +92601,7 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \ALU_dec31_ALU_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -92314,21 +92629,22 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \ALU_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \ALU_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -92428,6 +92744,7 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \ALU_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -92637,7 +92954,7 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -93049,12 +93366,10 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:51324.7-51324.15" + attribute \src "libresoc.v:51633.7-51633.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -93063,15 +93378,15 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:52519$3442 + cell $mux $ternary$libresoc.v:52834$3442 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:52519$3442_Y + connect \Y $ternary$libresoc.v:52834$3442_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:52520.13-52536.4" + attribute \src "libresoc.v:52835.13-52851.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -93090,7 +93405,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:52537.13-52553.4" + attribute \src "libresoc.v:52852.13-52868.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -93108,22 +93423,22 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:51324.7-51324.20" - process $proc$libresoc.v:51324$3457 + attribute \src "libresoc.v:51633.7-51633.20" + process $proc$libresoc.v:51633$3457 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52554.3-52587.6" - process $proc$libresoc.v:52554$3443 + attribute \src "libresoc.v:52869.3-52902.6" + process $proc$libresoc.v:52869$3443 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52555.5-52555.29" + attribute \src "libresoc.v:52870.5-52870.29" switch \initial - attribute \src "libresoc.v:52555.9-52555.17" + attribute \src "libresoc.v:52870.9-52870.17" case 1'1 case end @@ -93171,14 +93486,14 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:52588.3-52621.6" - process $proc$libresoc.v:52588$3444 + attribute \src "libresoc.v:52903.3-52936.6" + process $proc$libresoc.v:52903$3444 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52589.5-52589.29" + attribute \src "libresoc.v:52904.5-52904.29" switch \initial - attribute \src "libresoc.v:52589.9-52589.17" + attribute \src "libresoc.v:52904.9-52904.17" case 1'1 case end @@ -93226,14 +93541,14 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:52622.3-52655.6" - process $proc$libresoc.v:52622$3445 + attribute \src "libresoc.v:52937.3-52970.6" + process $proc$libresoc.v:52937$3445 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52623.5-52623.29" + attribute \src "libresoc.v:52938.5-52938.29" switch \initial - attribute \src "libresoc.v:52623.9-52623.17" + attribute \src "libresoc.v:52938.9-52938.17" case 1'1 case end @@ -93281,14 +93596,14 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:52656.3-52689.6" - process $proc$libresoc.v:52656$3446 + attribute \src "libresoc.v:52971.3-53004.6" + process $proc$libresoc.v:52971$3446 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52657.5-52657.29" + attribute \src "libresoc.v:52972.5-52972.29" switch \initial - attribute \src "libresoc.v:52657.9-52657.17" + attribute \src "libresoc.v:52972.9-52972.17" case 1'1 case end @@ -93336,14 +93651,14 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:52690.3-52723.6" - process $proc$libresoc.v:52690$3447 + attribute \src "libresoc.v:53005.3-53038.6" + process $proc$libresoc.v:53005$3447 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:52691.5-52691.29" + attribute \src "libresoc.v:53006.5-53006.29" switch \initial - attribute \src "libresoc.v:52691.9-52691.17" + attribute \src "libresoc.v:53006.9-53006.17" case 1'1 case end @@ -93391,14 +93706,14 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:52724.3-52757.6" - process $proc$libresoc.v:52724$3448 + attribute \src "libresoc.v:53039.3-53072.6" + process $proc$libresoc.v:53039$3448 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:52725.5-52725.29" + attribute \src "libresoc.v:53040.5-53040.29" switch \initial - attribute \src "libresoc.v:52725.9-52725.17" + attribute \src "libresoc.v:53040.9-53040.17" case 1'1 case end @@ -93446,14 +93761,14 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:52758.3-52791.6" - process $proc$libresoc.v:52758$3449 + attribute \src "libresoc.v:53073.3-53106.6" + process $proc$libresoc.v:53073$3449 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52759.5-52759.29" + attribute \src "libresoc.v:53074.5-53074.29" switch \initial - attribute \src "libresoc.v:52759.9-52759.17" + attribute \src "libresoc.v:53074.9-53074.17" case 1'1 case end @@ -93501,14 +93816,14 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:52792.3-52825.6" - process $proc$libresoc.v:52792$3450 + attribute \src "libresoc.v:53107.3-53140.6" + process $proc$libresoc.v:53107$3450 assign { } { } assign { } { } - assign $0\ALU_function_unit[12:0] $1\ALU_function_unit[12:0] - attribute \src "libresoc.v:52793.5-52793.29" + assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] + attribute \src "libresoc.v:53108.5-53108.29" switch \initial - attribute \src "libresoc.v:52793.9-52793.17" + attribute \src "libresoc.v:53108.9-53108.17" case 1'1 case end @@ -93517,53 +93832,53 @@ module \dec attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\ALU_function_unit[12:0] \ALU_dec19_ALU_dec19_function_unit + assign $1\ALU_function_unit[13:0] \ALU_dec19_ALU_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\ALU_function_unit[12:0] \ALU_dec31_ALU_dec31_function_unit + assign $1\ALU_function_unit[13:0] \ALU_dec31_ALU_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } - assign $1\ALU_function_unit[12:0] 13'0000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } - assign $1\ALU_function_unit[12:0] 13'0000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } - assign $1\ALU_function_unit[12:0] 13'0000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } - assign $1\ALU_function_unit[12:0] 13'0000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } - assign $1\ALU_function_unit[12:0] 13'0000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } - assign $1\ALU_function_unit[12:0] 13'0000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\ALU_function_unit[12:0] 13'0000000000010 + assign $1\ALU_function_unit[13:0] 14'00000000000010 case - assign $1\ALU_function_unit[12:0] 13'0000000000000 + assign $1\ALU_function_unit[13:0] 14'00000000000000 end sync always - update \ALU_function_unit $0\ALU_function_unit[12:0] + update \ALU_function_unit $0\ALU_function_unit[13:0] end - attribute \src "libresoc.v:52826.3-52859.6" - process $proc$libresoc.v:52826$3451 + attribute \src "libresoc.v:53141.3-53174.6" + process $proc$libresoc.v:53141$3451 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:52827.5-52827.29" + attribute \src "libresoc.v:53142.5-53142.29" switch \initial - attribute \src "libresoc.v:52827.9-52827.17" + attribute \src "libresoc.v:53142.9-53142.17" case 1'1 case end @@ -93611,14 +93926,14 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:52860.3-52893.6" - process $proc$libresoc.v:52860$3452 + attribute \src "libresoc.v:53175.3-53208.6" + process $proc$libresoc.v:53175$3452 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52861.5-52861.29" + attribute \src "libresoc.v:53176.5-53176.29" switch \initial - attribute \src "libresoc.v:52861.9-52861.17" + attribute \src "libresoc.v:53176.9-53176.17" case 1'1 case end @@ -93666,14 +93981,14 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:52894.3-52927.6" - process $proc$libresoc.v:52894$3453 + attribute \src "libresoc.v:53209.3-53242.6" + process $proc$libresoc.v:53209$3453 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:52895.5-52895.29" + attribute \src "libresoc.v:53210.5-53210.29" switch \initial - attribute \src "libresoc.v:52895.9-52895.17" + attribute \src "libresoc.v:53210.9-53210.17" case 1'1 case end @@ -93721,14 +94036,14 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:52928.3-52961.6" - process $proc$libresoc.v:52928$3454 + attribute \src "libresoc.v:53243.3-53276.6" + process $proc$libresoc.v:53243$3454 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:52929.5-52929.29" + attribute \src "libresoc.v:53244.5-53244.29" switch \initial - attribute \src "libresoc.v:52929.9-52929.17" + attribute \src "libresoc.v:53244.9-53244.17" case 1'1 case end @@ -93776,14 +94091,14 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:52962.3-52995.6" - process $proc$libresoc.v:52962$3455 + attribute \src "libresoc.v:53277.3-53310.6" + process $proc$libresoc.v:53277$3455 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52963.5-52963.29" + attribute \src "libresoc.v:53278.5-53278.29" switch \initial - attribute \src "libresoc.v:52963.9-52963.17" + attribute \src "libresoc.v:53278.9-53278.17" case 1'1 case end @@ -93831,14 +94146,14 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:52996.3-53029.6" - process $proc$libresoc.v:52996$3456 + attribute \src "libresoc.v:53311.3-53344.6" + process $proc$libresoc.v:53311$3456 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52997.5-52997.29" + attribute \src "libresoc.v:53312.5-53312.29" switch \initial - attribute \src "libresoc.v:52997.9-52997.17" + attribute \src "libresoc.v:53312.9-53312.17" case 1'1 case end @@ -93886,7 +94201,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:52519$3442_Y + connect \$1 $ternary$libresoc.v:52834$3442_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -93914,17 +94229,16 @@ module \dec connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -94220,40 +94534,41 @@ module \dec connect \ALU_RA \opcode_in [20:16] connect \ALU_RT \opcode_in [25:21] connect \ALU_RS \opcode_in [25:21] + connect \ALU_PO \opcode_in [31:26] connect \opcode_in \$1 connect \ALU_dec31_opcode_in \opcode_in connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53371.1-54830.10" +attribute \src "libresoc.v:53686.1-55151.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" module \dec$138 - attribute \src "libresoc.v:54454.3-54466.6" + attribute \src "libresoc.v:54775.3-54787.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:54467.3-54479.6" + attribute \src "libresoc.v:54788.3-54800.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:54428.3-54440.6" - wire width 13 $0\CR_function_unit[12:0] - attribute \src "libresoc.v:54441.3-54453.6" + attribute \src "libresoc.v:54749.3-54761.6" + wire width 14 $0\CR_function_unit[13:0] + attribute \src "libresoc.v:54762.3-54774.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:54480.3-54492.6" + attribute \src "libresoc.v:54801.3-54813.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:53372.7-53372.20" + attribute \src "libresoc.v:53687.7-53687.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54454.3-54466.6" + attribute \src "libresoc.v:54775.3-54787.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54467.3-54479.6" + attribute \src "libresoc.v:54788.3-54800.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54428.3-54440.6" - wire width 13 $1\CR_function_unit[12:0] - attribute \src "libresoc.v:54441.3-54453.6" + attribute \src "libresoc.v:54749.3-54761.6" + wire width 14 $1\CR_function_unit[13:0] + attribute \src "libresoc.v:54762.3-54774.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54480.3-54492.6" + attribute \src "libresoc.v:54801.3-54813.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54411.17-54411.211" - wire width 32 $ternary$libresoc.v:54411$3458_Y + attribute \src "libresoc.v:54732.17-54732.211" + wire width 32 $ternary$libresoc.v:54732$3458_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -94331,6 +94646,8 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 9 \CR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \CR_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_RB @@ -94393,21 +94710,22 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec19_CR_dec19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \CR_dec19_CR_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec19_CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94482,6 +94800,7 @@ module \dec$138 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec19_CR_dec19_internal_op attribute \enum_base_type "RC" @@ -94513,21 +94832,22 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \CR_dec31_CR_dec31_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \CR_dec31_CR_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \CR_dec31_CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94602,6 +94922,7 @@ module \dec$138 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \CR_dec31_CR_dec31_internal_op attribute \enum_base_type "RC" @@ -94613,21 +94934,22 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \CR_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \CR_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94702,6 +95024,7 @@ module \dec$138 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \CR_internal_op attribute \enum_base_type "RC" @@ -94865,7 +95188,7 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -95277,12 +95600,10 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:53372.7-53372.15" + attribute \src "libresoc.v:53687.7-53687.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -95291,15 +95612,15 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 10 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:54411$3458 + cell $mux $ternary$libresoc.v:54732$3458 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54411$3458_Y + connect \Y $ternary$libresoc.v:54732$3458_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54412.12-54419.4" + attribute \src "libresoc.v:54733.12-54740.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -95309,7 +95630,7 @@ module \dec$138 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:54420.12-54427.4" + attribute \src "libresoc.v:54741.12-54748.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -95318,22 +95639,22 @@ module \dec$138 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:53372.7-53372.20" - process $proc$libresoc.v:53372$3464 + attribute \src "libresoc.v:53687.7-53687.20" + process $proc$libresoc.v:53687$3464 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54428.3-54440.6" - process $proc$libresoc.v:54428$3459 + attribute \src "libresoc.v:54749.3-54761.6" + process $proc$libresoc.v:54749$3459 assign { } { } assign { } { } - assign $0\CR_function_unit[12:0] $1\CR_function_unit[12:0] - attribute \src "libresoc.v:54429.5-54429.29" + assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] + attribute \src "libresoc.v:54750.5-54750.29" switch \initial - attribute \src "libresoc.v:54429.9-54429.17" + attribute \src "libresoc.v:54750.9-54750.17" case 1'1 case end @@ -95342,25 +95663,25 @@ module \dec$138 attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\CR_function_unit[12:0] \CR_dec19_CR_dec19_function_unit + assign $1\CR_function_unit[13:0] \CR_dec19_CR_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\CR_function_unit[12:0] \CR_dec31_CR_dec31_function_unit + assign $1\CR_function_unit[13:0] \CR_dec31_CR_dec31_function_unit case - assign $1\CR_function_unit[12:0] 13'0000000000000 + assign $1\CR_function_unit[13:0] 14'00000000000000 end sync always - update \CR_function_unit $0\CR_function_unit[12:0] + update \CR_function_unit $0\CR_function_unit[13:0] end - attribute \src "libresoc.v:54441.3-54453.6" - process $proc$libresoc.v:54441$3460 + attribute \src "libresoc.v:54762.3-54774.6" + process $proc$libresoc.v:54762$3460 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54442.5-54442.29" + attribute \src "libresoc.v:54763.5-54763.29" switch \initial - attribute \src "libresoc.v:54442.9-54442.17" + attribute \src "libresoc.v:54763.9-54763.17" case 1'1 case end @@ -95380,14 +95701,14 @@ module \dec$138 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:54454.3-54466.6" - process $proc$libresoc.v:54454$3461 + attribute \src "libresoc.v:54775.3-54787.6" + process $proc$libresoc.v:54775$3461 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54455.5-54455.29" + attribute \src "libresoc.v:54776.5-54776.29" switch \initial - attribute \src "libresoc.v:54455.9-54455.17" + attribute \src "libresoc.v:54776.9-54776.17" case 1'1 case end @@ -95407,14 +95728,14 @@ module \dec$138 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:54467.3-54479.6" - process $proc$libresoc.v:54467$3462 + attribute \src "libresoc.v:54788.3-54800.6" + process $proc$libresoc.v:54788$3462 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54468.5-54468.29" + attribute \src "libresoc.v:54789.5-54789.29" switch \initial - attribute \src "libresoc.v:54468.9-54468.17" + attribute \src "libresoc.v:54789.9-54789.17" case 1'1 case end @@ -95434,14 +95755,14 @@ module \dec$138 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:54480.3-54492.6" - process $proc$libresoc.v:54480$3463 + attribute \src "libresoc.v:54801.3-54813.6" + process $proc$libresoc.v:54801$3463 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54481.5-54481.29" + attribute \src "libresoc.v:54802.5-54802.29" switch \initial - attribute \src "libresoc.v:54481.9-54481.17" + attribute \src "libresoc.v:54802.9-54802.17" case 1'1 case end @@ -95461,7 +95782,7 @@ module \dec$138 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:54411$3458_Y + connect \$1 $ternary$libresoc.v:54732$3458_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -95489,17 +95810,16 @@ module \dec$138 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -95795,52 +96115,53 @@ module \dec$138 connect \CR_RA \opcode_in [20:16] connect \CR_RT \opcode_in [25:21] connect \CR_RS \opcode_in [25:21] + connect \CR_PO \opcode_in [31:26] connect \opcode_in \$1 connect \CR_dec31_opcode_in \opcode_in connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:54834.1-56275.10" +attribute \src "libresoc.v:55155.1-56600.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" module \dec$141 - attribute \src "libresoc.v:55859.3-55874.6" + attribute \src "libresoc.v:56184.3-56199.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:55875.3-55890.6" + attribute \src "libresoc.v:56200.3-56215.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:55811.3-55826.6" - wire width 13 $0\BRANCH_function_unit[12:0] - attribute \src "libresoc.v:55843.3-55858.6" + attribute \src "libresoc.v:56136.3-56151.6" + wire width 14 $0\BRANCH_function_unit[13:0] + attribute \src "libresoc.v:56168.3-56183.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:55827.3-55842.6" + attribute \src "libresoc.v:56152.3-56167.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55907.3-55922.6" + attribute \src "libresoc.v:56232.3-56247.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55923.3-55938.6" + attribute \src "libresoc.v:56248.3-56263.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:55891.3-55906.6" + attribute \src "libresoc.v:56216.3-56231.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:54835.7-54835.20" + attribute \src "libresoc.v:55156.7-55156.20" wire $0\initial[0:0] - attribute \src "libresoc.v:55859.3-55874.6" + attribute \src "libresoc.v:56184.3-56199.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:55875.3-55890.6" + attribute \src "libresoc.v:56200.3-56215.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:55811.3-55826.6" - wire width 13 $1\BRANCH_function_unit[12:0] - attribute \src "libresoc.v:55843.3-55858.6" + attribute \src "libresoc.v:56136.3-56151.6" + wire width 14 $1\BRANCH_function_unit[13:0] + attribute \src "libresoc.v:56168.3-56183.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:55827.3-55842.6" + attribute \src "libresoc.v:56152.3-56167.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55907.3-55922.6" + attribute \src "libresoc.v:56232.3-56247.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55923.3-55938.6" + attribute \src "libresoc.v:56248.3-56263.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:55891.3-55906.6" + attribute \src "libresoc.v:56216.3-56231.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55799.17-55799.211" - wire width 32 $ternary$libresoc.v:55799$3465_Y + attribute \src "libresoc.v:56124.17-56124.211" + wire width 32 $ternary$libresoc.v:56124$3465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -95908,6 +96229,8 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 18 \BRANCH_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \BRANCH_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_RB @@ -95970,21 +96293,22 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \BRANCH_dec19_BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -96076,6 +96400,7 @@ module \dec$141 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -96091,21 +96416,22 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \BRANCH_dec19_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \BRANCH_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -96197,6 +96523,7 @@ module \dec$141 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \BRANCH_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -96374,7 +96701,7 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -96786,12 +97113,10 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:54835.7-54835.15" + attribute \src "libresoc.v:55156.7-55156.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -96800,15 +97125,15 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:55799$3465 + cell $mux $ternary$libresoc.v:56124$3465 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:55799$3465_Y + connect \Y $ternary$libresoc.v:56124$3465_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:55800.16-55810.4" + attribute \src "libresoc.v:56125.16-56135.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -96820,22 +97145,22 @@ module \dec$141 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:54835.7-54835.20" - process $proc$libresoc.v:54835$3474 + attribute \src "libresoc.v:55156.7-55156.20" + process $proc$libresoc.v:55156$3474 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:55811.3-55826.6" - process $proc$libresoc.v:55811$3466 + attribute \src "libresoc.v:56136.3-56151.6" + process $proc$libresoc.v:56136$3466 assign { } { } assign { } { } - assign $0\BRANCH_function_unit[12:0] $1\BRANCH_function_unit[12:0] - attribute \src "libresoc.v:55812.5-55812.29" + assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] + attribute \src "libresoc.v:56137.5-56137.29" switch \initial - attribute \src "libresoc.v:55812.9-55812.17" + attribute \src "libresoc.v:56137.9-56137.17" case 1'1 case end @@ -96844,29 +97169,29 @@ module \dec$141 attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\BRANCH_function_unit[12:0] \BRANCH_dec19_BRANCH_dec19_function_unit + assign $1\BRANCH_function_unit[13:0] \BRANCH_dec19_BRANCH_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } - assign $1\BRANCH_function_unit[12:0] 13'0000000100000 + assign $1\BRANCH_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } - assign $1\BRANCH_function_unit[12:0] 13'0000000100000 + assign $1\BRANCH_function_unit[13:0] 14'00000000100000 case - assign $1\BRANCH_function_unit[12:0] 13'0000000000000 + assign $1\BRANCH_function_unit[13:0] 14'00000000000000 end sync always - update \BRANCH_function_unit $0\BRANCH_function_unit[12:0] + update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] end - attribute \src "libresoc.v:55827.3-55842.6" - process $proc$libresoc.v:55827$3467 + attribute \src "libresoc.v:56152.3-56167.6" + process $proc$libresoc.v:56152$3467 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55828.5-55828.29" + attribute \src "libresoc.v:56153.5-56153.29" switch \initial - attribute \src "libresoc.v:55828.9-55828.17" + attribute \src "libresoc.v:56153.9-56153.17" case 1'1 case end @@ -96890,14 +97215,14 @@ module \dec$141 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:55843.3-55858.6" - process $proc$libresoc.v:55843$3468 + attribute \src "libresoc.v:56168.3-56183.6" + process $proc$libresoc.v:56168$3468 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:55844.5-55844.29" + attribute \src "libresoc.v:56169.5-56169.29" switch \initial - attribute \src "libresoc.v:55844.9-55844.17" + attribute \src "libresoc.v:56169.9-56169.17" case 1'1 case end @@ -96921,14 +97246,14 @@ module \dec$141 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:55859.3-55874.6" - process $proc$libresoc.v:55859$3469 + attribute \src "libresoc.v:56184.3-56199.6" + process $proc$libresoc.v:56184$3469 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:55860.5-55860.29" + attribute \src "libresoc.v:56185.5-56185.29" switch \initial - attribute \src "libresoc.v:55860.9-55860.17" + attribute \src "libresoc.v:56185.9-56185.17" case 1'1 case end @@ -96952,14 +97277,14 @@ module \dec$141 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:55875.3-55890.6" - process $proc$libresoc.v:55875$3470 + attribute \src "libresoc.v:56200.3-56215.6" + process $proc$libresoc.v:56200$3470 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:55876.5-55876.29" + attribute \src "libresoc.v:56201.5-56201.29" switch \initial - attribute \src "libresoc.v:55876.9-55876.17" + attribute \src "libresoc.v:56201.9-56201.17" case 1'1 case end @@ -96983,14 +97308,14 @@ module \dec$141 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:55891.3-55906.6" - process $proc$libresoc.v:55891$3471 + attribute \src "libresoc.v:56216.3-56231.6" + process $proc$libresoc.v:56216$3471 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55892.5-55892.29" + attribute \src "libresoc.v:56217.5-56217.29" switch \initial - attribute \src "libresoc.v:55892.9-55892.17" + attribute \src "libresoc.v:56217.9-56217.17" case 1'1 case end @@ -97014,14 +97339,14 @@ module \dec$141 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:55907.3-55922.6" - process $proc$libresoc.v:55907$3472 + attribute \src "libresoc.v:56232.3-56247.6" + process $proc$libresoc.v:56232$3472 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55908.5-55908.29" + attribute \src "libresoc.v:56233.5-56233.29" switch \initial - attribute \src "libresoc.v:55908.9-55908.17" + attribute \src "libresoc.v:56233.9-56233.17" case 1'1 case end @@ -97045,14 +97370,14 @@ module \dec$141 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:55923.3-55938.6" - process $proc$libresoc.v:55923$3473 + attribute \src "libresoc.v:56248.3-56263.6" + process $proc$libresoc.v:56248$3473 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:55924.5-55924.29" + attribute \src "libresoc.v:56249.5-56249.29" switch \initial - attribute \src "libresoc.v:55924.9-55924.17" + attribute \src "libresoc.v:56249.9-56249.17" case 1'1 case end @@ -97076,7 +97401,7 @@ module \dec$141 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:55799$3465_Y + connect \$1 $ternary$libresoc.v:56124$3465_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -97104,17 +97429,16 @@ module \dec$141 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -97410,75 +97734,76 @@ module \dec$141 connect \BRANCH_RA \opcode_in [20:16] connect \BRANCH_RT \opcode_in [25:21] connect \BRANCH_RS \opcode_in [25:21] + connect \BRANCH_PO \opcode_in [31:26] connect \opcode_in \$1 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:56279.1-58052.10" +attribute \src "libresoc.v:56604.1-58381.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" module \dec$145 - attribute \src "libresoc.v:57604.3-57631.6" + attribute \src "libresoc.v:57933.3-57960.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57632.3-57659.6" + attribute \src "libresoc.v:57961.3-57988.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57324.3-57351.6" + attribute \src "libresoc.v:57653.3-57680.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57408.3-57435.6" + attribute \src "libresoc.v:57737.3-57764.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57492.3-57519.6" - wire width 13 $0\LOGICAL_function_unit[12:0] - attribute \src "libresoc.v:57548.3-57575.6" + attribute \src "libresoc.v:57821.3-57848.6" + wire width 14 $0\LOGICAL_function_unit[13:0] + attribute \src "libresoc.v:57877.3-57904.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57576.3-57603.6" + attribute \src "libresoc.v:57905.3-57932.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57520.3-57547.6" + attribute \src "libresoc.v:57849.3-57876.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57352.3-57379.6" + attribute \src "libresoc.v:57681.3-57708.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57380.3-57407.6" + attribute \src "libresoc.v:57709.3-57736.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57436.3-57463.6" + attribute \src "libresoc.v:57765.3-57792.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57660.3-57687.6" + attribute \src "libresoc.v:57989.3-58016.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57688.3-57715.6" + attribute \src "libresoc.v:58017.3-58044.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57464.3-57491.6" + attribute \src "libresoc.v:57793.3-57820.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56280.7-56280.20" + attribute \src "libresoc.v:56605.7-56605.20" wire $0\initial[0:0] - attribute \src "libresoc.v:57604.3-57631.6" + attribute \src "libresoc.v:57933.3-57960.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57632.3-57659.6" + attribute \src "libresoc.v:57961.3-57988.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57324.3-57351.6" + attribute \src "libresoc.v:57653.3-57680.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57408.3-57435.6" + attribute \src "libresoc.v:57737.3-57764.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57492.3-57519.6" - wire width 13 $1\LOGICAL_function_unit[12:0] - attribute \src "libresoc.v:57548.3-57575.6" + attribute \src "libresoc.v:57821.3-57848.6" + wire width 14 $1\LOGICAL_function_unit[13:0] + attribute \src "libresoc.v:57877.3-57904.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57576.3-57603.6" + attribute \src "libresoc.v:57905.3-57932.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57520.3-57547.6" + attribute \src "libresoc.v:57849.3-57876.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57352.3-57379.6" + attribute \src "libresoc.v:57681.3-57708.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57380.3-57407.6" + attribute \src "libresoc.v:57709.3-57736.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57436.3-57463.6" + attribute \src "libresoc.v:57765.3-57792.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57660.3-57687.6" + attribute \src "libresoc.v:57989.3-58016.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57688.3-57715.6" + attribute \src "libresoc.v:58017.3-58044.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57464.3-57491.6" + attribute \src "libresoc.v:57793.3-57820.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57306.17-57306.211" - wire width 32 $ternary$libresoc.v:57306$3475_Y + attribute \src "libresoc.v:57635.17-57635.211" + wire width 32 $ternary$libresoc.v:57635$3475_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -97646,6 +97971,8 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 24 \LOGICAL_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \LOGICAL_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 17 \LOGICAL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_RB @@ -97724,21 +98051,22 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LOGICAL_dec31_LOGICAL_dec31_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -97838,6 +98166,7 @@ module \dec$145 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -97865,21 +98194,22 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LOGICAL_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \LOGICAL_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -97979,6 +98309,7 @@ module \dec$145 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \LOGICAL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -98068,7 +98399,7 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -98480,12 +98811,10 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:56280.7-56280.15" + attribute \src "libresoc.v:56605.7-56605.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -98494,15 +98823,15 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:57306$3475 + cell $mux $ternary$libresoc.v:57635$3475 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:57306$3475_Y + connect \Y $ternary$libresoc.v:57635$3475_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:57307.17-57323.4" + attribute \src "libresoc.v:57636.17-57652.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -98520,22 +98849,22 @@ module \dec$145 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:56280.7-56280.20" - process $proc$libresoc.v:56280$3490 + attribute \src "libresoc.v:56605.7-56605.20" + process $proc$libresoc.v:56605$3490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:57324.3-57351.6" - process $proc$libresoc.v:57324$3476 + attribute \src "libresoc.v:57653.3-57680.6" + process $proc$libresoc.v:57653$3476 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57325.5-57325.29" + attribute \src "libresoc.v:57654.5-57654.29" switch \initial - attribute \src "libresoc.v:57325.9-57325.17" + attribute \src "libresoc.v:57654.9-57654.17" case 1'1 case end @@ -98575,14 +98904,14 @@ module \dec$145 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:57352.3-57379.6" - process $proc$libresoc.v:57352$3477 + attribute \src "libresoc.v:57681.3-57708.6" + process $proc$libresoc.v:57681$3477 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57353.5-57353.29" + attribute \src "libresoc.v:57682.5-57682.29" switch \initial - attribute \src "libresoc.v:57353.9-57353.17" + attribute \src "libresoc.v:57682.9-57682.17" case 1'1 case end @@ -98622,14 +98951,14 @@ module \dec$145 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:57380.3-57407.6" - process $proc$libresoc.v:57380$3478 + attribute \src "libresoc.v:57709.3-57736.6" + process $proc$libresoc.v:57709$3478 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57381.5-57381.29" + attribute \src "libresoc.v:57710.5-57710.29" switch \initial - attribute \src "libresoc.v:57381.9-57381.17" + attribute \src "libresoc.v:57710.9-57710.17" case 1'1 case end @@ -98669,14 +98998,14 @@ module \dec$145 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:57408.3-57435.6" - process $proc$libresoc.v:57408$3479 + attribute \src "libresoc.v:57737.3-57764.6" + process $proc$libresoc.v:57737$3479 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57409.5-57409.29" + attribute \src "libresoc.v:57738.5-57738.29" switch \initial - attribute \src "libresoc.v:57409.9-57409.17" + attribute \src "libresoc.v:57738.9-57738.17" case 1'1 case end @@ -98716,14 +99045,14 @@ module \dec$145 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:57436.3-57463.6" - process $proc$libresoc.v:57436$3480 + attribute \src "libresoc.v:57765.3-57792.6" + process $proc$libresoc.v:57765$3480 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57437.5-57437.29" + attribute \src "libresoc.v:57766.5-57766.29" switch \initial - attribute \src "libresoc.v:57437.9-57437.17" + attribute \src "libresoc.v:57766.9-57766.17" case 1'1 case end @@ -98763,14 +99092,14 @@ module \dec$145 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:57464.3-57491.6" - process $proc$libresoc.v:57464$3481 + attribute \src "libresoc.v:57793.3-57820.6" + process $proc$libresoc.v:57793$3481 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57465.5-57465.29" + attribute \src "libresoc.v:57794.5-57794.29" switch \initial - attribute \src "libresoc.v:57465.9-57465.17" + attribute \src "libresoc.v:57794.9-57794.17" case 1'1 case end @@ -98810,14 +99139,14 @@ module \dec$145 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:57492.3-57519.6" - process $proc$libresoc.v:57492$3482 + attribute \src "libresoc.v:57821.3-57848.6" + process $proc$libresoc.v:57821$3482 assign { } { } assign { } { } - assign $0\LOGICAL_function_unit[12:0] $1\LOGICAL_function_unit[12:0] - attribute \src "libresoc.v:57493.5-57493.29" + assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] + attribute \src "libresoc.v:57822.5-57822.29" switch \initial - attribute \src "libresoc.v:57493.9-57493.17" + attribute \src "libresoc.v:57822.9-57822.17" case 1'1 case end @@ -98826,45 +99155,45 @@ module \dec$145 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\LOGICAL_function_unit[12:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit + assign $1\LOGICAL_function_unit[13:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } - assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } - assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } - assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } - assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 case - assign $1\LOGICAL_function_unit[12:0] 13'0000000000000 + assign $1\LOGICAL_function_unit[13:0] 14'00000000000000 end sync always - update \LOGICAL_function_unit $0\LOGICAL_function_unit[12:0] + update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] end - attribute \src "libresoc.v:57520.3-57547.6" - process $proc$libresoc.v:57520$3483 + attribute \src "libresoc.v:57849.3-57876.6" + process $proc$libresoc.v:57849$3483 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57521.5-57521.29" + attribute \src "libresoc.v:57850.5-57850.29" switch \initial - attribute \src "libresoc.v:57521.9-57521.17" + attribute \src "libresoc.v:57850.9-57850.17" case 1'1 case end @@ -98904,14 +99233,14 @@ module \dec$145 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:57548.3-57575.6" - process $proc$libresoc.v:57548$3484 + attribute \src "libresoc.v:57877.3-57904.6" + process $proc$libresoc.v:57877$3484 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57549.5-57549.29" + attribute \src "libresoc.v:57878.5-57878.29" switch \initial - attribute \src "libresoc.v:57549.9-57549.17" + attribute \src "libresoc.v:57878.9-57878.17" case 1'1 case end @@ -98951,14 +99280,14 @@ module \dec$145 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:57576.3-57603.6" - process $proc$libresoc.v:57576$3485 + attribute \src "libresoc.v:57905.3-57932.6" + process $proc$libresoc.v:57905$3485 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57577.5-57577.29" + attribute \src "libresoc.v:57906.5-57906.29" switch \initial - attribute \src "libresoc.v:57577.9-57577.17" + attribute \src "libresoc.v:57906.9-57906.17" case 1'1 case end @@ -98998,14 +99327,14 @@ module \dec$145 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:57604.3-57631.6" - process $proc$libresoc.v:57604$3486 + attribute \src "libresoc.v:57933.3-57960.6" + process $proc$libresoc.v:57933$3486 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57605.5-57605.29" + attribute \src "libresoc.v:57934.5-57934.29" switch \initial - attribute \src "libresoc.v:57605.9-57605.17" + attribute \src "libresoc.v:57934.9-57934.17" case 1'1 case end @@ -99045,14 +99374,14 @@ module \dec$145 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:57632.3-57659.6" - process $proc$libresoc.v:57632$3487 + attribute \src "libresoc.v:57961.3-57988.6" + process $proc$libresoc.v:57961$3487 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57633.5-57633.29" + attribute \src "libresoc.v:57962.5-57962.29" switch \initial - attribute \src "libresoc.v:57633.9-57633.17" + attribute \src "libresoc.v:57962.9-57962.17" case 1'1 case end @@ -99092,14 +99421,14 @@ module \dec$145 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:57660.3-57687.6" - process $proc$libresoc.v:57660$3488 + attribute \src "libresoc.v:57989.3-58016.6" + process $proc$libresoc.v:57989$3488 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57661.5-57661.29" + attribute \src "libresoc.v:57990.5-57990.29" switch \initial - attribute \src "libresoc.v:57661.9-57661.17" + attribute \src "libresoc.v:57990.9-57990.17" case 1'1 case end @@ -99139,14 +99468,14 @@ module \dec$145 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:57688.3-57715.6" - process $proc$libresoc.v:57688$3489 + attribute \src "libresoc.v:58017.3-58044.6" + process $proc$libresoc.v:58017$3489 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57689.5-57689.29" + attribute \src "libresoc.v:58018.5-58018.29" switch \initial - attribute \src "libresoc.v:57689.9-57689.17" + attribute \src "libresoc.v:58018.9-58018.17" case 1'1 case end @@ -99186,7 +99515,7 @@ module \dec$145 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:57306$3475_Y + connect \$1 $ternary$libresoc.v:57635$3475_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -99214,17 +99543,16 @@ module \dec$145 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -99520,43 +99848,44 @@ module \dec$145 connect \LOGICAL_RA \opcode_in [20:16] connect \LOGICAL_RT \opcode_in [25:21] connect \LOGICAL_RS \opcode_in [25:21] + connect \LOGICAL_PO \opcode_in [31:26] connect \opcode_in \$1 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58056.1-59387.10" +attribute \src "libresoc.v:58385.1-59720.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" module \dec$150 - attribute \src "libresoc.v:59011.3-59020.6" + attribute \src "libresoc.v:59344.3-59353.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:59021.3-59030.6" + attribute \src "libresoc.v:59354.3-59363.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:58991.3-59000.6" - wire width 13 $0\SPR_function_unit[12:0] - attribute \src "libresoc.v:59001.3-59010.6" + attribute \src "libresoc.v:59324.3-59333.6" + wire width 14 $0\SPR_function_unit[13:0] + attribute \src "libresoc.v:59334.3-59343.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:59041.3-59050.6" + attribute \src "libresoc.v:59374.3-59383.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:59031.3-59040.6" + attribute \src "libresoc.v:59364.3-59373.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58057.7-58057.20" + attribute \src "libresoc.v:58386.7-58386.20" wire $0\initial[0:0] - attribute \src "libresoc.v:59011.3-59020.6" + attribute \src "libresoc.v:59344.3-59353.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59021.3-59030.6" + attribute \src "libresoc.v:59354.3-59363.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:58991.3-59000.6" - wire width 13 $1\SPR_function_unit[12:0] - attribute \src "libresoc.v:59001.3-59010.6" + attribute \src "libresoc.v:59324.3-59333.6" + wire width 14 $1\SPR_function_unit[13:0] + attribute \src "libresoc.v:59334.3-59343.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59041.3-59050.6" + attribute \src "libresoc.v:59374.3-59383.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59031.3-59040.6" + attribute \src "libresoc.v:59364.3-59373.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58981.17-58981.211" - wire width 32 $ternary$libresoc.v:58981$3491_Y + attribute \src "libresoc.v:59314.17-59314.211" + wire width 32 $ternary$libresoc.v:59314$3491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -99780,6 +100109,8 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 10 \SPR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \SPR_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_RB @@ -99842,21 +100173,22 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \SPR_dec31_SPR_dec31_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \SPR_dec31_SPR_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SPR_dec31_SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -99931,6 +100263,7 @@ module \dec$150 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SPR_dec31_SPR_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -99944,21 +100277,22 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SPR_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \SPR_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100033,6 +100367,7 @@ module \dec$150 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \SPR_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -100052,7 +100387,7 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -100464,12 +100799,10 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:58057.7-58057.15" + attribute \src "libresoc.v:58386.7-58386.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -100478,15 +100811,15 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 11 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:58981$3491 + cell $mux $ternary$libresoc.v:59314$3491 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:58981$3491_Y + connect \Y $ternary$libresoc.v:59314$3491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:58982.13-58990.4" + attribute \src "libresoc.v:59315.13-59323.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -100496,22 +100829,22 @@ module \dec$150 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:58057.7-58057.20" - process $proc$libresoc.v:58057$3498 + attribute \src "libresoc.v:58386.7-58386.20" + process $proc$libresoc.v:58386$3498 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:58991.3-59000.6" - process $proc$libresoc.v:58991$3492 + attribute \src "libresoc.v:59324.3-59333.6" + process $proc$libresoc.v:59324$3492 assign { } { } assign { } { } - assign $0\SPR_function_unit[12:0] $1\SPR_function_unit[12:0] - attribute \src "libresoc.v:58992.5-58992.29" + assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] + attribute \src "libresoc.v:59325.5-59325.29" switch \initial - attribute \src "libresoc.v:58992.9-58992.17" + attribute \src "libresoc.v:59325.9-59325.17" case 1'1 case end @@ -100520,21 +100853,21 @@ module \dec$150 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\SPR_function_unit[12:0] \SPR_dec31_SPR_dec31_function_unit + assign $1\SPR_function_unit[13:0] \SPR_dec31_SPR_dec31_function_unit case - assign $1\SPR_function_unit[12:0] 13'0000000000000 + assign $1\SPR_function_unit[13:0] 14'00000000000000 end sync always - update \SPR_function_unit $0\SPR_function_unit[12:0] + update \SPR_function_unit $0\SPR_function_unit[13:0] end - attribute \src "libresoc.v:59001.3-59010.6" - process $proc$libresoc.v:59001$3493 + attribute \src "libresoc.v:59334.3-59343.6" + process $proc$libresoc.v:59334$3493 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59002.5-59002.29" + attribute \src "libresoc.v:59335.5-59335.29" switch \initial - attribute \src "libresoc.v:59002.9-59002.17" + attribute \src "libresoc.v:59335.9-59335.17" case 1'1 case end @@ -100550,14 +100883,14 @@ module \dec$150 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:59011.3-59020.6" - process $proc$libresoc.v:59011$3494 + attribute \src "libresoc.v:59344.3-59353.6" + process $proc$libresoc.v:59344$3494 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59012.5-59012.29" + attribute \src "libresoc.v:59345.5-59345.29" switch \initial - attribute \src "libresoc.v:59012.9-59012.17" + attribute \src "libresoc.v:59345.9-59345.17" case 1'1 case end @@ -100573,14 +100906,14 @@ module \dec$150 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:59021.3-59030.6" - process $proc$libresoc.v:59021$3495 + attribute \src "libresoc.v:59354.3-59363.6" + process $proc$libresoc.v:59354$3495 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59022.5-59022.29" + attribute \src "libresoc.v:59355.5-59355.29" switch \initial - attribute \src "libresoc.v:59022.9-59022.17" + attribute \src "libresoc.v:59355.9-59355.17" case 1'1 case end @@ -100596,14 +100929,14 @@ module \dec$150 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:59031.3-59040.6" - process $proc$libresoc.v:59031$3496 + attribute \src "libresoc.v:59364.3-59373.6" + process $proc$libresoc.v:59364$3496 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59032.5-59032.29" + attribute \src "libresoc.v:59365.5-59365.29" switch \initial - attribute \src "libresoc.v:59032.9-59032.17" + attribute \src "libresoc.v:59365.9-59365.17" case 1'1 case end @@ -100619,14 +100952,14 @@ module \dec$150 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:59041.3-59050.6" - process $proc$libresoc.v:59041$3497 + attribute \src "libresoc.v:59374.3-59383.6" + process $proc$libresoc.v:59374$3497 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59042.5-59042.29" + attribute \src "libresoc.v:59375.5-59375.29" switch \initial - attribute \src "libresoc.v:59042.9-59042.17" + attribute \src "libresoc.v:59375.9-59375.17" case 1'1 case end @@ -100642,7 +100975,7 @@ module \dec$150 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:58981$3491_Y + connect \$1 $ternary$libresoc.v:59314$3491_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -100670,17 +101003,16 @@ module \dec$150 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -100976,75 +101308,76 @@ module \dec$150 connect \SPR_RA \opcode_in [20:16] connect \SPR_RT \opcode_in [25:21] connect \SPR_RS \opcode_in [25:21] + connect \SPR_PO \opcode_in [31:26] connect \opcode_in \$1 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:59391.1-60912.10" +attribute \src "libresoc.v:59724.1-61249.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" module \dec$153 - attribute \src "libresoc.v:60536.3-60545.6" + attribute \src "libresoc.v:60873.3-60882.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60546.3-60555.6" + attribute \src "libresoc.v:60883.3-60892.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:60436.3-60445.6" + attribute \src "libresoc.v:60773.3-60782.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60466.3-60475.6" + attribute \src "libresoc.v:60803.3-60812.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60496.3-60505.6" - wire width 13 $0\DIV_function_unit[12:0] - attribute \src "libresoc.v:60516.3-60525.6" + attribute \src "libresoc.v:60833.3-60842.6" + wire width 14 $0\DIV_function_unit[13:0] + attribute \src "libresoc.v:60853.3-60862.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60526.3-60535.6" + attribute \src "libresoc.v:60863.3-60872.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60506.3-60515.6" + attribute \src "libresoc.v:60843.3-60852.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:60446.3-60455.6" + attribute \src "libresoc.v:60783.3-60792.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:60456.3-60465.6" + attribute \src "libresoc.v:60793.3-60802.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:60476.3-60485.6" + attribute \src "libresoc.v:60813.3-60822.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:60556.3-60565.6" + attribute \src "libresoc.v:60893.3-60902.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60566.3-60575.6" + attribute \src "libresoc.v:60903.3-60912.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60486.3-60495.6" + attribute \src "libresoc.v:60823.3-60832.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:59392.7-59392.20" + attribute \src "libresoc.v:59725.7-59725.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60536.3-60545.6" + attribute \src "libresoc.v:60873.3-60882.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60546.3-60555.6" + attribute \src "libresoc.v:60883.3-60892.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60436.3-60445.6" + attribute \src "libresoc.v:60773.3-60782.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60466.3-60475.6" + attribute \src "libresoc.v:60803.3-60812.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60496.3-60505.6" - wire width 13 $1\DIV_function_unit[12:0] - attribute \src "libresoc.v:60516.3-60525.6" + attribute \src "libresoc.v:60833.3-60842.6" + wire width 14 $1\DIV_function_unit[13:0] + attribute \src "libresoc.v:60853.3-60862.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60526.3-60535.6" + attribute \src "libresoc.v:60863.3-60872.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60506.3-60515.6" + attribute \src "libresoc.v:60843.3-60852.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60446.3-60455.6" + attribute \src "libresoc.v:60783.3-60792.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60456.3-60465.6" + attribute \src "libresoc.v:60793.3-60802.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60476.3-60485.6" + attribute \src "libresoc.v:60813.3-60822.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60556.3-60565.6" + attribute \src "libresoc.v:60893.3-60902.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60566.3-60575.6" + attribute \src "libresoc.v:60903.3-60912.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60486.3-60495.6" + attribute \src "libresoc.v:60823.3-60832.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60418.17-60418.211" - wire width 32 $ternary$libresoc.v:60418$3499_Y + attribute \src "libresoc.v:60755.17-60755.211" + wire width 32 $ternary$libresoc.v:60755$3499_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -101122,6 +101455,8 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 24 \DIV_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \DIV_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 17 \DIV_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_RB @@ -101200,21 +101535,22 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \DIV_dec31_DIV_dec31_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \DIV_dec31_DIV_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \DIV_dec31_DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -101314,6 +101650,7 @@ module \dec$153 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \DIV_dec31_DIV_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -101341,21 +101678,22 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \DIV_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \DIV_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -101455,6 +101793,7 @@ module \dec$153 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \DIV_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -101634,7 +101973,7 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -102046,12 +102385,10 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:59392.7-59392.15" + attribute \src "libresoc.v:59725.7-59725.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -102060,15 +102397,15 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:60418$3499 + cell $mux $ternary$libresoc.v:60755$3499 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:60418$3499_Y + connect \Y $ternary$libresoc.v:60755$3499_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:60419.13-60435.4" + attribute \src "libresoc.v:60756.13-60772.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -102086,22 +102423,22 @@ module \dec$153 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:59392.7-59392.20" - process $proc$libresoc.v:59392$3514 + attribute \src "libresoc.v:59725.7-59725.20" + process $proc$libresoc.v:59725$3514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:60436.3-60445.6" - process $proc$libresoc.v:60436$3500 + attribute \src "libresoc.v:60773.3-60782.6" + process $proc$libresoc.v:60773$3500 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60437.5-60437.29" + attribute \src "libresoc.v:60774.5-60774.29" switch \initial - attribute \src "libresoc.v:60437.9-60437.17" + attribute \src "libresoc.v:60774.9-60774.17" case 1'1 case end @@ -102117,14 +102454,14 @@ module \dec$153 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:60446.3-60455.6" - process $proc$libresoc.v:60446$3501 + attribute \src "libresoc.v:60783.3-60792.6" + process $proc$libresoc.v:60783$3501 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60447.5-60447.29" + attribute \src "libresoc.v:60784.5-60784.29" switch \initial - attribute \src "libresoc.v:60447.9-60447.17" + attribute \src "libresoc.v:60784.9-60784.17" case 1'1 case end @@ -102140,14 +102477,14 @@ module \dec$153 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:60456.3-60465.6" - process $proc$libresoc.v:60456$3502 + attribute \src "libresoc.v:60793.3-60802.6" + process $proc$libresoc.v:60793$3502 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60457.5-60457.29" + attribute \src "libresoc.v:60794.5-60794.29" switch \initial - attribute \src "libresoc.v:60457.9-60457.17" + attribute \src "libresoc.v:60794.9-60794.17" case 1'1 case end @@ -102163,14 +102500,14 @@ module \dec$153 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:60466.3-60475.6" - process $proc$libresoc.v:60466$3503 + attribute \src "libresoc.v:60803.3-60812.6" + process $proc$libresoc.v:60803$3503 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60467.5-60467.29" + attribute \src "libresoc.v:60804.5-60804.29" switch \initial - attribute \src "libresoc.v:60467.9-60467.17" + attribute \src "libresoc.v:60804.9-60804.17" case 1'1 case end @@ -102186,14 +102523,14 @@ module \dec$153 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:60476.3-60485.6" - process $proc$libresoc.v:60476$3504 + attribute \src "libresoc.v:60813.3-60822.6" + process $proc$libresoc.v:60813$3504 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60477.5-60477.29" + attribute \src "libresoc.v:60814.5-60814.29" switch \initial - attribute \src "libresoc.v:60477.9-60477.17" + attribute \src "libresoc.v:60814.9-60814.17" case 1'1 case end @@ -102209,14 +102546,14 @@ module \dec$153 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:60486.3-60495.6" - process $proc$libresoc.v:60486$3505 + attribute \src "libresoc.v:60823.3-60832.6" + process $proc$libresoc.v:60823$3505 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60487.5-60487.29" + attribute \src "libresoc.v:60824.5-60824.29" switch \initial - attribute \src "libresoc.v:60487.9-60487.17" + attribute \src "libresoc.v:60824.9-60824.17" case 1'1 case end @@ -102232,14 +102569,14 @@ module \dec$153 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:60496.3-60505.6" - process $proc$libresoc.v:60496$3506 + attribute \src "libresoc.v:60833.3-60842.6" + process $proc$libresoc.v:60833$3506 assign { } { } assign { } { } - assign $0\DIV_function_unit[12:0] $1\DIV_function_unit[12:0] - attribute \src "libresoc.v:60497.5-60497.29" + assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] + attribute \src "libresoc.v:60834.5-60834.29" switch \initial - attribute \src "libresoc.v:60497.9-60497.17" + attribute \src "libresoc.v:60834.9-60834.17" case 1'1 case end @@ -102248,21 +102585,21 @@ module \dec$153 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\DIV_function_unit[12:0] \DIV_dec31_DIV_dec31_function_unit + assign $1\DIV_function_unit[13:0] \DIV_dec31_DIV_dec31_function_unit case - assign $1\DIV_function_unit[12:0] 13'0000000000000 + assign $1\DIV_function_unit[13:0] 14'00000000000000 end sync always - update \DIV_function_unit $0\DIV_function_unit[12:0] + update \DIV_function_unit $0\DIV_function_unit[13:0] end - attribute \src "libresoc.v:60506.3-60515.6" - process $proc$libresoc.v:60506$3507 + attribute \src "libresoc.v:60843.3-60852.6" + process $proc$libresoc.v:60843$3507 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60507.5-60507.29" + attribute \src "libresoc.v:60844.5-60844.29" switch \initial - attribute \src "libresoc.v:60507.9-60507.17" + attribute \src "libresoc.v:60844.9-60844.17" case 1'1 case end @@ -102278,14 +102615,14 @@ module \dec$153 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:60516.3-60525.6" - process $proc$libresoc.v:60516$3508 + attribute \src "libresoc.v:60853.3-60862.6" + process $proc$libresoc.v:60853$3508 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60517.5-60517.29" + attribute \src "libresoc.v:60854.5-60854.29" switch \initial - attribute \src "libresoc.v:60517.9-60517.17" + attribute \src "libresoc.v:60854.9-60854.17" case 1'1 case end @@ -102301,14 +102638,14 @@ module \dec$153 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:60526.3-60535.6" - process $proc$libresoc.v:60526$3509 + attribute \src "libresoc.v:60863.3-60872.6" + process $proc$libresoc.v:60863$3509 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60527.5-60527.29" + attribute \src "libresoc.v:60864.5-60864.29" switch \initial - attribute \src "libresoc.v:60527.9-60527.17" + attribute \src "libresoc.v:60864.9-60864.17" case 1'1 case end @@ -102324,14 +102661,14 @@ module \dec$153 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:60536.3-60545.6" - process $proc$libresoc.v:60536$3510 + attribute \src "libresoc.v:60873.3-60882.6" + process $proc$libresoc.v:60873$3510 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60537.5-60537.29" + attribute \src "libresoc.v:60874.5-60874.29" switch \initial - attribute \src "libresoc.v:60537.9-60537.17" + attribute \src "libresoc.v:60874.9-60874.17" case 1'1 case end @@ -102347,14 +102684,14 @@ module \dec$153 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:60546.3-60555.6" - process $proc$libresoc.v:60546$3511 + attribute \src "libresoc.v:60883.3-60892.6" + process $proc$libresoc.v:60883$3511 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60547.5-60547.29" + attribute \src "libresoc.v:60884.5-60884.29" switch \initial - attribute \src "libresoc.v:60547.9-60547.17" + attribute \src "libresoc.v:60884.9-60884.17" case 1'1 case end @@ -102370,14 +102707,14 @@ module \dec$153 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:60556.3-60565.6" - process $proc$libresoc.v:60556$3512 + attribute \src "libresoc.v:60893.3-60902.6" + process $proc$libresoc.v:60893$3512 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60557.5-60557.29" + attribute \src "libresoc.v:60894.5-60894.29" switch \initial - attribute \src "libresoc.v:60557.9-60557.17" + attribute \src "libresoc.v:60894.9-60894.17" case 1'1 case end @@ -102393,14 +102730,14 @@ module \dec$153 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:60566.3-60575.6" - process $proc$libresoc.v:60566$3513 + attribute \src "libresoc.v:60903.3-60912.6" + process $proc$libresoc.v:60903$3513 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60567.5-60567.29" + attribute \src "libresoc.v:60904.5-60904.29" switch \initial - attribute \src "libresoc.v:60567.9-60567.17" + attribute \src "libresoc.v:60904.9-60904.17" case 1'1 case end @@ -102416,7 +102753,7 @@ module \dec$153 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:60418$3499_Y + connect \$1 $ternary$libresoc.v:60755$3499_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -102444,17 +102781,16 @@ module \dec$153 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -102750,51 +103086,52 @@ module \dec$153 connect \DIV_RA \opcode_in [20:16] connect \DIV_RT \opcode_in [25:21] connect \DIV_RS \opcode_in [25:21] + connect \DIV_PO \opcode_in [31:26] connect \opcode_in \$1 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:60916.1-62333.10" +attribute \src "libresoc.v:61253.1-62674.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" module \dec$158 - attribute \src "libresoc.v:61932.3-61944.6" + attribute \src "libresoc.v:62273.3-62285.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:61945.3-61957.6" + attribute \src "libresoc.v:62286.3-62298.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:61893.3-61905.6" - wire width 13 $0\MUL_function_unit[12:0] - attribute \src "libresoc.v:61919.3-61931.6" + attribute \src "libresoc.v:62234.3-62246.6" + wire width 14 $0\MUL_function_unit[13:0] + attribute \src "libresoc.v:62260.3-62272.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:61906.3-61918.6" + attribute \src "libresoc.v:62247.3-62259.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:61971.3-61983.6" + attribute \src "libresoc.v:62312.3-62324.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:61958.3-61970.6" + attribute \src "libresoc.v:62299.3-62311.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:61984.3-61996.6" + attribute \src "libresoc.v:62325.3-62337.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:60917.7-60917.20" + attribute \src "libresoc.v:61254.7-61254.20" wire $0\initial[0:0] - attribute \src "libresoc.v:61932.3-61944.6" + attribute \src "libresoc.v:62273.3-62285.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:61945.3-61957.6" + attribute \src "libresoc.v:62286.3-62298.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:61893.3-61905.6" - wire width 13 $1\MUL_function_unit[12:0] - attribute \src "libresoc.v:61919.3-61931.6" + attribute \src "libresoc.v:62234.3-62246.6" + wire width 14 $1\MUL_function_unit[13:0] + attribute \src "libresoc.v:62260.3-62272.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:61906.3-61918.6" + attribute \src "libresoc.v:62247.3-62259.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:61971.3-61983.6" + attribute \src "libresoc.v:62312.3-62324.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:61958.3-61970.6" + attribute \src "libresoc.v:62299.3-62311.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:61984.3-61996.6" + attribute \src "libresoc.v:62325.3-62337.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:61881.17-61881.211" - wire width 32 $ternary$libresoc.v:61881$3515_Y + attribute \src "libresoc.v:62222.17-62222.211" + wire width 32 $ternary$libresoc.v:62222$3515_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -102998,6 +103335,8 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 17 \MUL_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \MUL_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_RB @@ -103060,21 +103399,22 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \MUL_dec31_MUL_dec31_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \MUL_dec31_MUL_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \MUL_dec31_MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -103166,6 +103506,7 @@ module \dec$158 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \MUL_dec31_MUL_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -103181,21 +103522,22 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \MUL_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \MUL_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -103287,6 +103629,7 @@ module \dec$158 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \MUL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -103328,7 +103671,7 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -103740,12 +104083,10 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:60917.7-60917.15" + attribute \src "libresoc.v:61254.7-61254.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -103754,15 +104095,15 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 20 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:61881$3515 + cell $mux $ternary$libresoc.v:62222$3515 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:61881$3515_Y + connect \Y $ternary$libresoc.v:62222$3515_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:61882.13-61892.4" + attribute \src "libresoc.v:62223.13-62233.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -103774,22 +104115,22 @@ module \dec$158 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:60917.7-60917.20" - process $proc$libresoc.v:60917$3524 + attribute \src "libresoc.v:61254.7-61254.20" + process $proc$libresoc.v:61254$3524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:61893.3-61905.6" - process $proc$libresoc.v:61893$3516 + attribute \src "libresoc.v:62234.3-62246.6" + process $proc$libresoc.v:62234$3516 assign { } { } assign { } { } - assign $0\MUL_function_unit[12:0] $1\MUL_function_unit[12:0] - attribute \src "libresoc.v:61894.5-61894.29" + assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] + attribute \src "libresoc.v:62235.5-62235.29" switch \initial - attribute \src "libresoc.v:61894.9-61894.17" + attribute \src "libresoc.v:62235.9-62235.17" case 1'1 case end @@ -103798,25 +104139,25 @@ module \dec$158 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\MUL_function_unit[12:0] \MUL_dec31_MUL_dec31_function_unit + assign $1\MUL_function_unit[13:0] \MUL_dec31_MUL_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } - assign $1\MUL_function_unit[12:0] 13'0000100000000 + assign $1\MUL_function_unit[13:0] 14'00000100000000 case - assign $1\MUL_function_unit[12:0] 13'0000000000000 + assign $1\MUL_function_unit[13:0] 14'00000000000000 end sync always - update \MUL_function_unit $0\MUL_function_unit[12:0] + update \MUL_function_unit $0\MUL_function_unit[13:0] end - attribute \src "libresoc.v:61906.3-61918.6" - process $proc$libresoc.v:61906$3517 + attribute \src "libresoc.v:62247.3-62259.6" + process $proc$libresoc.v:62247$3517 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:61907.5-61907.29" + attribute \src "libresoc.v:62248.5-62248.29" switch \initial - attribute \src "libresoc.v:61907.9-61907.17" + attribute \src "libresoc.v:62248.9-62248.17" case 1'1 case end @@ -103836,14 +104177,14 @@ module \dec$158 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:61919.3-61931.6" - process $proc$libresoc.v:61919$3518 + attribute \src "libresoc.v:62260.3-62272.6" + process $proc$libresoc.v:62260$3518 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:61920.5-61920.29" + attribute \src "libresoc.v:62261.5-62261.29" switch \initial - attribute \src "libresoc.v:61920.9-61920.17" + attribute \src "libresoc.v:62261.9-62261.17" case 1'1 case end @@ -103863,14 +104204,14 @@ module \dec$158 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:61932.3-61944.6" - process $proc$libresoc.v:61932$3519 + attribute \src "libresoc.v:62273.3-62285.6" + process $proc$libresoc.v:62273$3519 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:61933.5-61933.29" + attribute \src "libresoc.v:62274.5-62274.29" switch \initial - attribute \src "libresoc.v:61933.9-61933.17" + attribute \src "libresoc.v:62274.9-62274.17" case 1'1 case end @@ -103890,14 +104231,14 @@ module \dec$158 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:61945.3-61957.6" - process $proc$libresoc.v:61945$3520 + attribute \src "libresoc.v:62286.3-62298.6" + process $proc$libresoc.v:62286$3520 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:61946.5-61946.29" + attribute \src "libresoc.v:62287.5-62287.29" switch \initial - attribute \src "libresoc.v:61946.9-61946.17" + attribute \src "libresoc.v:62287.9-62287.17" case 1'1 case end @@ -103917,14 +104258,14 @@ module \dec$158 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:61958.3-61970.6" - process $proc$libresoc.v:61958$3521 + attribute \src "libresoc.v:62299.3-62311.6" + process $proc$libresoc.v:62299$3521 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:61959.5-61959.29" + attribute \src "libresoc.v:62300.5-62300.29" switch \initial - attribute \src "libresoc.v:61959.9-61959.17" + attribute \src "libresoc.v:62300.9-62300.17" case 1'1 case end @@ -103944,14 +104285,14 @@ module \dec$158 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:61971.3-61983.6" - process $proc$libresoc.v:61971$3522 + attribute \src "libresoc.v:62312.3-62324.6" + process $proc$libresoc.v:62312$3522 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:61972.5-61972.29" + attribute \src "libresoc.v:62313.5-62313.29" switch \initial - attribute \src "libresoc.v:61972.9-61972.17" + attribute \src "libresoc.v:62313.9-62313.17" case 1'1 case end @@ -103971,14 +104312,14 @@ module \dec$158 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:61984.3-61996.6" - process $proc$libresoc.v:61984$3523 + attribute \src "libresoc.v:62325.3-62337.6" + process $proc$libresoc.v:62325$3523 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:61985.5-61985.29" + attribute \src "libresoc.v:62326.5-62326.29" switch \initial - attribute \src "libresoc.v:61985.9-61985.17" + attribute \src "libresoc.v:62326.9-62326.17" case 1'1 case end @@ -103998,7 +104339,7 @@ module \dec$158 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:61881$3515_Y + connect \$1 $ternary$libresoc.v:62222$3515_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -104026,17 +104367,16 @@ module \dec$158 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -104332,63 +104672,64 @@ module \dec$158 connect \MUL_RA \opcode_in [20:16] connect \MUL_RT \opcode_in [25:21] connect \MUL_RS \opcode_in [25:21] + connect \MUL_PO \opcode_in [31:26] connect \opcode_in \$1 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:62337.1-64085.10" +attribute \src "libresoc.v:62678.1-64432.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" module \dec$162 - attribute \src "libresoc.v:63660.3-63681.6" + attribute \src "libresoc.v:64007.3-64028.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63682.3-63703.6" + attribute \src "libresoc.v:64029.3-64050.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63726.3-63747.6" + attribute \src "libresoc.v:64073.3-64094.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63528.3-63549.6" + attribute \src "libresoc.v:63875.3-63896.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63594.3-63615.6" - wire width 13 $0\SHIFT_ROT_function_unit[12:0] - attribute \src "libresoc.v:63638.3-63659.6" + attribute \src "libresoc.v:63941.3-63962.6" + wire width 14 $0\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:63985.3-64006.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63616.3-63637.6" + attribute \src "libresoc.v:63963.3-63984.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63506.3-63527.6" + attribute \src "libresoc.v:63853.3-63874.6" wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63550.3-63571.6" + attribute \src "libresoc.v:63897.3-63918.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63704.3-63725.6" + attribute \src "libresoc.v:64051.3-64072.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63572.3-63593.6" + attribute \src "libresoc.v:63919.3-63940.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62338.7-62338.20" + attribute \src "libresoc.v:62679.7-62679.20" wire $0\initial[0:0] - attribute \src "libresoc.v:63660.3-63681.6" + attribute \src "libresoc.v:64007.3-64028.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63682.3-63703.6" + attribute \src "libresoc.v:64029.3-64050.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63726.3-63747.6" + attribute \src "libresoc.v:64073.3-64094.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63528.3-63549.6" + attribute \src "libresoc.v:63875.3-63896.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63594.3-63615.6" - wire width 13 $1\SHIFT_ROT_function_unit[12:0] - attribute \src "libresoc.v:63638.3-63659.6" + attribute \src "libresoc.v:63941.3-63962.6" + wire width 14 $1\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:63985.3-64006.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63616.3-63637.6" + attribute \src "libresoc.v:63963.3-63984.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63506.3-63527.6" + attribute \src "libresoc.v:63853.3-63874.6" wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63550.3-63571.6" + attribute \src "libresoc.v:63897.3-63918.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63704.3-63725.6" + attribute \src "libresoc.v:64051.3-64072.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63572.3-63593.6" + attribute \src "libresoc.v:63919.3-63940.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63477.17-63477.211" - wire width 32 $ternary$libresoc.v:63477$3525_Y + attribute \src "libresoc.v:63824.17-63824.211" + wire width 32 $ternary$libresoc.v:63824$3525_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -104612,6 +104953,8 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 21 \SHIFT_ROT_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \SHIFT_ROT_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_RB @@ -104690,21 +105033,22 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -104796,6 +105140,7 @@ module \dec$162 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -104841,21 +105186,22 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -104947,6 +105293,7 @@ module \dec$162 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -104964,21 +105311,22 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \SHIFT_ROT_dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \SHIFT_ROT_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -105070,6 +105418,7 @@ module \dec$162 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \SHIFT_ROT_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -105093,7 +105442,7 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -105505,12 +105854,10 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:62338.7-62338.15" + attribute \src "libresoc.v:62679.7-62679.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -105519,15 +105866,15 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 24 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:63477$3525 + cell $mux $ternary$libresoc.v:63824$3525 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:63477$3525_Y + connect \Y $ternary$libresoc.v:63824$3525_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:63478.19-63491.4" + attribute \src "libresoc.v:63825.19-63838.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -105543,7 +105890,7 @@ module \dec$162 connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:63492.19-63505.4" + attribute \src "libresoc.v:63839.19-63852.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -105558,22 +105905,22 @@ module \dec$162 connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:62338.7-62338.20" - process $proc$libresoc.v:62338$3537 + attribute \src "libresoc.v:62679.7-62679.20" + process $proc$libresoc.v:62679$3537 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:63506.3-63527.6" - process $proc$libresoc.v:63506$3526 + attribute \src "libresoc.v:63853.3-63874.6" + process $proc$libresoc.v:63853$3526 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63507.5-63507.29" + attribute \src "libresoc.v:63854.5-63854.29" switch \initial - attribute \src "libresoc.v:63507.9-63507.17" + attribute \src "libresoc.v:63854.9-63854.17" case 1'1 case end @@ -105605,14 +105952,14 @@ module \dec$162 sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end - attribute \src "libresoc.v:63528.3-63549.6" - process $proc$libresoc.v:63528$3527 + attribute \src "libresoc.v:63875.3-63896.6" + process $proc$libresoc.v:63875$3527 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63529.5-63529.29" + attribute \src "libresoc.v:63876.5-63876.29" switch \initial - attribute \src "libresoc.v:63529.9-63529.17" + attribute \src "libresoc.v:63876.9-63876.17" case 1'1 case end @@ -105644,14 +105991,14 @@ module \dec$162 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:63550.3-63571.6" - process $proc$libresoc.v:63550$3528 + attribute \src "libresoc.v:63897.3-63918.6" + process $proc$libresoc.v:63897$3528 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63551.5-63551.29" + attribute \src "libresoc.v:63898.5-63898.29" switch \initial - attribute \src "libresoc.v:63551.9-63551.17" + attribute \src "libresoc.v:63898.9-63898.17" case 1'1 case end @@ -105683,14 +106030,14 @@ module \dec$162 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:63572.3-63593.6" - process $proc$libresoc.v:63572$3529 + attribute \src "libresoc.v:63919.3-63940.6" + process $proc$libresoc.v:63919$3529 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63573.5-63573.29" + attribute \src "libresoc.v:63920.5-63920.29" switch \initial - attribute \src "libresoc.v:63573.9-63573.17" + attribute \src "libresoc.v:63920.9-63920.17" case 1'1 case end @@ -105722,14 +106069,14 @@ module \dec$162 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:63594.3-63615.6" - process $proc$libresoc.v:63594$3530 + attribute \src "libresoc.v:63941.3-63962.6" + process $proc$libresoc.v:63941$3530 assign { } { } assign { } { } - assign $0\SHIFT_ROT_function_unit[12:0] $1\SHIFT_ROT_function_unit[12:0] - attribute \src "libresoc.v:63595.5-63595.29" + assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] + attribute \src "libresoc.v:63942.5-63942.29" switch \initial - attribute \src "libresoc.v:63595.9-63595.17" + attribute \src "libresoc.v:63942.9-63942.17" case 1'1 case end @@ -105738,37 +106085,37 @@ module \dec$162 attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } - assign $1\SHIFT_ROT_function_unit[12:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + assign $1\SHIFT_ROT_function_unit[13:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\SHIFT_ROT_function_unit[12:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + assign $1\SHIFT_ROT_function_unit[13:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\SHIFT_ROT_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\SHIFT_ROT_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\SHIFT_ROT_function_unit[12:0] 13'0000000001000 + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 case - assign $1\SHIFT_ROT_function_unit[12:0] 13'0000000000000 + assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000000000 end sync always - update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[12:0] + update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] end - attribute \src "libresoc.v:63616.3-63637.6" - process $proc$libresoc.v:63616$3531 + attribute \src "libresoc.v:63963.3-63984.6" + process $proc$libresoc.v:63963$3531 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63617.5-63617.29" + attribute \src "libresoc.v:63964.5-63964.29" switch \initial - attribute \src "libresoc.v:63617.9-63617.17" + attribute \src "libresoc.v:63964.9-63964.17" case 1'1 case end @@ -105800,14 +106147,14 @@ module \dec$162 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:63638.3-63659.6" - process $proc$libresoc.v:63638$3532 + attribute \src "libresoc.v:63985.3-64006.6" + process $proc$libresoc.v:63985$3532 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63639.5-63639.29" + attribute \src "libresoc.v:63986.5-63986.29" switch \initial - attribute \src "libresoc.v:63639.9-63639.17" + attribute \src "libresoc.v:63986.9-63986.17" case 1'1 case end @@ -105839,14 +106186,14 @@ module \dec$162 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:63660.3-63681.6" - process $proc$libresoc.v:63660$3533 + attribute \src "libresoc.v:64007.3-64028.6" + process $proc$libresoc.v:64007$3533 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63661.5-63661.29" + attribute \src "libresoc.v:64008.5-64008.29" switch \initial - attribute \src "libresoc.v:63661.9-63661.17" + attribute \src "libresoc.v:64008.9-64008.17" case 1'1 case end @@ -105878,14 +106225,14 @@ module \dec$162 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:63682.3-63703.6" - process $proc$libresoc.v:63682$3534 + attribute \src "libresoc.v:64029.3-64050.6" + process $proc$libresoc.v:64029$3534 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63683.5-63683.29" + attribute \src "libresoc.v:64030.5-64030.29" switch \initial - attribute \src "libresoc.v:63683.9-63683.17" + attribute \src "libresoc.v:64030.9-64030.17" case 1'1 case end @@ -105917,14 +106264,14 @@ module \dec$162 sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:63704.3-63725.6" - process $proc$libresoc.v:63704$3535 + attribute \src "libresoc.v:64051.3-64072.6" + process $proc$libresoc.v:64051$3535 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63705.5-63705.29" + attribute \src "libresoc.v:64052.5-64052.29" switch \initial - attribute \src "libresoc.v:63705.9-63705.17" + attribute \src "libresoc.v:64052.9-64052.17" case 1'1 case end @@ -105956,14 +106303,14 @@ module \dec$162 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:63726.3-63747.6" - process $proc$libresoc.v:63726$3536 + attribute \src "libresoc.v:64073.3-64094.6" + process $proc$libresoc.v:64073$3536 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63727.5-63727.29" + attribute \src "libresoc.v:64074.5-64074.29" switch \initial - attribute \src "libresoc.v:63727.9-63727.17" + attribute \src "libresoc.v:64074.9-64074.17" case 1'1 case end @@ -105995,7 +106342,7 @@ module \dec$162 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:63477$3525_Y + connect \$1 $ternary$libresoc.v:63824$3525_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -106023,17 +106370,16 @@ module \dec$162 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -106329,72 +106675,73 @@ module \dec$162 connect \SHIFT_ROT_RA \opcode_in [20:16] connect \SHIFT_ROT_RT \opcode_in [25:21] connect \SHIFT_ROT_RS \opcode_in [25:21] + connect \SHIFT_ROT_PO \opcode_in [31:26] connect \opcode_in \$1 connect \SHIFT_ROT_dec31_opcode_in \opcode_in connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:64089.1-66590.10" +attribute \src "libresoc.v:64436.1-66945.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" module \dec$166 - attribute \src "libresoc.v:65672.3-65729.6" + attribute \src "libresoc.v:66027.3-66084.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:66136.3-66193.6" + attribute \src "libresoc.v:66491.3-66548.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:66194.3-66251.6" + attribute \src "libresoc.v:66549.3-66606.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:65904.3-65961.6" - wire width 13 $0\LDST_function_unit[12:0] - attribute \src "libresoc.v:66020.3-66077.6" + attribute \src "libresoc.v:66259.3-66316.6" + wire width 14 $0\LDST_function_unit[13:0] + attribute \src "libresoc.v:66375.3-66432.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66078.3-66135.6" + attribute \src "libresoc.v:66433.3-66490.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:65962.3-66019.6" + attribute \src "libresoc.v:66317.3-66374.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:65788.3-65845.6" + attribute \src "libresoc.v:66143.3-66200.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:65498.3-65555.6" + attribute \src "libresoc.v:65853.3-65910.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65614.3-65671.6" + attribute \src "libresoc.v:65969.3-66026.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65846.3-65903.6" + attribute \src "libresoc.v:66201.3-66258.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:65730.3-65787.6" + attribute \src "libresoc.v:66085.3-66142.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65556.3-65613.6" + attribute \src "libresoc.v:65911.3-65968.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:64090.7-64090.20" + attribute \src "libresoc.v:64437.7-64437.20" wire $0\initial[0:0] - attribute \src "libresoc.v:65672.3-65729.6" + attribute \src "libresoc.v:66027.3-66084.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:66136.3-66193.6" + attribute \src "libresoc.v:66491.3-66548.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66194.3-66251.6" + attribute \src "libresoc.v:66549.3-66606.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:65904.3-65961.6" - wire width 13 $1\LDST_function_unit[12:0] - attribute \src "libresoc.v:66020.3-66077.6" + attribute \src "libresoc.v:66259.3-66316.6" + wire width 14 $1\LDST_function_unit[13:0] + attribute \src "libresoc.v:66375.3-66432.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66078.3-66135.6" + attribute \src "libresoc.v:66433.3-66490.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:65962.3-66019.6" + attribute \src "libresoc.v:66317.3-66374.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:65788.3-65845.6" + attribute \src "libresoc.v:66143.3-66200.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65498.3-65555.6" + attribute \src "libresoc.v:65853.3-65910.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65614.3-65671.6" + attribute \src "libresoc.v:65969.3-66026.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65846.3-65903.6" + attribute \src "libresoc.v:66201.3-66258.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:65730.3-65787.6" + attribute \src "libresoc.v:66085.3-66142.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65556.3-65613.6" + attribute \src "libresoc.v:65911.3-65968.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:65449.17-65449.211" - wire width 32 $ternary$libresoc.v:65449$3538_Y + attribute \src "libresoc.v:65804.17-65804.211" + wire width 32 $ternary$libresoc.v:65804$3538_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -106562,6 +106909,8 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 23 \LDST_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \LDST_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 16 \LDST_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_RB @@ -106628,21 +106977,22 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec31_LDST_dec31_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LDST_dec31_LDST_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec31_LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -106742,6 +107092,7 @@ module \dec$166 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec31_LDST_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -106796,21 +107147,22 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec58_LDST_dec58_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LDST_dec58_LDST_dec58_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec58_LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -106910,6 +107262,7 @@ module \dec$166 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec58_LDST_dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -106964,21 +107317,22 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \LDST_dec62_LDST_dec62_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \LDST_dec62_LDST_dec62_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \LDST_dec62_LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -107078,6 +107432,7 @@ module \dec$166 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \LDST_dec62_LDST_dec62_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -107110,21 +107465,22 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \LDST_dec62_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \LDST_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -107224,6 +107580,7 @@ module \dec$166 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \LDST_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -107318,7 +107675,7 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -107730,12 +108087,10 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:64090.7-64090.15" + attribute \src "libresoc.v:64437.7-64437.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in @@ -107744,15 +108099,15 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 26 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:65449$3538 + cell $mux $ternary$libresoc.v:65804$3538 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:65449$3538_Y + connect \Y $ternary$libresoc.v:65804$3538_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:65450.14-65465.4" + attribute \src "libresoc.v:65805.14-65820.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -107770,7 +108125,7 @@ module \dec$166 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65466.14-65481.4" + attribute \src "libresoc.v:65821.14-65836.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -107788,7 +108143,7 @@ module \dec$166 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65482.14-65497.4" + attribute \src "libresoc.v:65837.14-65852.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -107805,22 +108160,22 @@ module \dec$166 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:64090.7-64090.20" - process $proc$libresoc.v:64090$3552 + attribute \src "libresoc.v:64437.7-64437.20" + process $proc$libresoc.v:64437$3552 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:65498.3-65555.6" - process $proc$libresoc.v:65498$3539 + attribute \src "libresoc.v:65853.3-65910.6" + process $proc$libresoc.v:65853$3539 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65499.5-65499.29" + attribute \src "libresoc.v:65854.5-65854.29" switch \initial - attribute \src "libresoc.v:65499.9-65499.17" + attribute \src "libresoc.v:65854.9-65854.17" case 1'1 case end @@ -107900,14 +108255,14 @@ module \dec$166 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:65556.3-65613.6" - process $proc$libresoc.v:65556$3540 + attribute \src "libresoc.v:65911.3-65968.6" + process $proc$libresoc.v:65911$3540 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:65557.5-65557.29" + attribute \src "libresoc.v:65912.5-65912.29" switch \initial - attribute \src "libresoc.v:65557.9-65557.17" + attribute \src "libresoc.v:65912.9-65912.17" case 1'1 case end @@ -107987,14 +108342,14 @@ module \dec$166 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:65614.3-65671.6" - process $proc$libresoc.v:65614$3541 + attribute \src "libresoc.v:65969.3-66026.6" + process $proc$libresoc.v:65969$3541 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65615.5-65615.29" + attribute \src "libresoc.v:65970.5-65970.29" switch \initial - attribute \src "libresoc.v:65615.9-65615.17" + attribute \src "libresoc.v:65970.9-65970.17" case 1'1 case end @@ -108074,14 +108429,14 @@ module \dec$166 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:65672.3-65729.6" - process $proc$libresoc.v:65672$3542 + attribute \src "libresoc.v:66027.3-66084.6" + process $proc$libresoc.v:66027$3542 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:65673.5-65673.29" + attribute \src "libresoc.v:66028.5-66028.29" switch \initial - attribute \src "libresoc.v:65673.9-65673.17" + attribute \src "libresoc.v:66028.9-66028.17" case 1'1 case end @@ -108161,14 +108516,14 @@ module \dec$166 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:65730.3-65787.6" - process $proc$libresoc.v:65730$3543 + attribute \src "libresoc.v:66085.3-66142.6" + process $proc$libresoc.v:66085$3543 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65731.5-65731.29" + attribute \src "libresoc.v:66086.5-66086.29" switch \initial - attribute \src "libresoc.v:65731.9-65731.17" + attribute \src "libresoc.v:66086.9-66086.17" case 1'1 case end @@ -108248,14 +108603,14 @@ module \dec$166 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:65788.3-65845.6" - process $proc$libresoc.v:65788$3544 + attribute \src "libresoc.v:66143.3-66200.6" + process $proc$libresoc.v:66143$3544 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65789.5-65789.29" + attribute \src "libresoc.v:66144.5-66144.29" switch \initial - attribute \src "libresoc.v:65789.9-65789.17" + attribute \src "libresoc.v:66144.9-66144.17" case 1'1 case end @@ -108335,14 +108690,14 @@ module \dec$166 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:65846.3-65903.6" - process $proc$libresoc.v:65846$3545 + attribute \src "libresoc.v:66201.3-66258.6" + process $proc$libresoc.v:66201$3545 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:65847.5-65847.29" + attribute \src "libresoc.v:66202.5-66202.29" switch \initial - attribute \src "libresoc.v:65847.9-65847.17" + attribute \src "libresoc.v:66202.9-66202.17" case 1'1 case end @@ -108422,14 +108777,14 @@ module \dec$166 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:65904.3-65961.6" - process $proc$libresoc.v:65904$3546 + attribute \src "libresoc.v:66259.3-66316.6" + process $proc$libresoc.v:66259$3546 assign { } { } assign { } { } - assign $0\LDST_function_unit[12:0] $1\LDST_function_unit[12:0] - attribute \src "libresoc.v:65905.5-65905.29" + assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] + attribute \src "libresoc.v:66260.5-66260.29" switch \initial - attribute \src "libresoc.v:65905.9-65905.17" + attribute \src "libresoc.v:66260.9-66260.17" case 1'1 case end @@ -108438,85 +108793,85 @@ module \dec$166 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\LDST_function_unit[12:0] \LDST_dec31_LDST_dec31_function_unit + assign $1\LDST_function_unit[13:0] \LDST_dec31_LDST_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } - assign $1\LDST_function_unit[12:0] \LDST_dec58_LDST_dec58_function_unit + assign $1\LDST_function_unit[13:0] \LDST_dec58_LDST_dec58_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } - assign $1\LDST_function_unit[12:0] \LDST_dec62_LDST_dec62_function_unit + assign $1\LDST_function_unit[13:0] \LDST_dec62_LDST_dec62_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\LDST_function_unit[12:0] 13'0000000000100 + assign $1\LDST_function_unit[13:0] 14'00000000000100 case - assign $1\LDST_function_unit[12:0] 13'0000000000000 + assign $1\LDST_function_unit[13:0] 14'00000000000000 end sync always - update \LDST_function_unit $0\LDST_function_unit[12:0] + update \LDST_function_unit $0\LDST_function_unit[13:0] end - attribute \src "libresoc.v:65962.3-66019.6" - process $proc$libresoc.v:65962$3547 + attribute \src "libresoc.v:66317.3-66374.6" + process $proc$libresoc.v:66317$3547 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:65963.5-65963.29" + attribute \src "libresoc.v:66318.5-66318.29" switch \initial - attribute \src "libresoc.v:65963.9-65963.17" + attribute \src "libresoc.v:66318.9-66318.17" case 1'1 case end @@ -108596,14 +108951,14 @@ module \dec$166 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:66020.3-66077.6" - process $proc$libresoc.v:66020$3548 + attribute \src "libresoc.v:66375.3-66432.6" + process $proc$libresoc.v:66375$3548 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66021.5-66021.29" + attribute \src "libresoc.v:66376.5-66376.29" switch \initial - attribute \src "libresoc.v:66021.9-66021.17" + attribute \src "libresoc.v:66376.9-66376.17" case 1'1 case end @@ -108683,14 +109038,14 @@ module \dec$166 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:66078.3-66135.6" - process $proc$libresoc.v:66078$3549 + attribute \src "libresoc.v:66433.3-66490.6" + process $proc$libresoc.v:66433$3549 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66079.5-66079.29" + attribute \src "libresoc.v:66434.5-66434.29" switch \initial - attribute \src "libresoc.v:66079.9-66079.17" + attribute \src "libresoc.v:66434.9-66434.17" case 1'1 case end @@ -108770,14 +109125,14 @@ module \dec$166 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:66136.3-66193.6" - process $proc$libresoc.v:66136$3550 + attribute \src "libresoc.v:66491.3-66548.6" + process $proc$libresoc.v:66491$3550 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66137.5-66137.29" + attribute \src "libresoc.v:66492.5-66492.29" switch \initial - attribute \src "libresoc.v:66137.9-66137.17" + attribute \src "libresoc.v:66492.9-66492.17" case 1'1 case end @@ -108857,14 +109212,14 @@ module \dec$166 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:66194.3-66251.6" - process $proc$libresoc.v:66194$3551 + attribute \src "libresoc.v:66549.3-66606.6" + process $proc$libresoc.v:66549$3551 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66195.5-66195.29" + attribute \src "libresoc.v:66550.5-66550.29" switch \initial - attribute \src "libresoc.v:66195.9-66195.17" + attribute \src "libresoc.v:66550.9-66550.17" case 1'1 case end @@ -108944,7 +109299,7 @@ module \dec$166 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:65449$3538_Y + connect \$1 $ternary$libresoc.v:65804$3538_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -108972,17 +109327,16 @@ module \dec$166 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -109278,213 +109632,214 @@ module \dec$166 connect \LDST_RA \opcode_in [20:16] connect \LDST_RT \opcode_in [25:21] connect \LDST_RS \opcode_in [25:21] + connect \LDST_PO \opcode_in [31:26] connect \opcode_in \$1 connect \LDST_dec62_opcode_in \opcode_in connect \LDST_dec58_opcode_in \opcode_in connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:66594.1-74144.10" +attribute \src "libresoc.v:66949.1-74952.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" module \dec$171 - attribute \src "libresoc.v:69401.3-69542.6" + attribute \src "libresoc.v:70260.3-70404.6" wire width 2 $0\SV_Etype[1:0] - attribute \src "libresoc.v:69543.3-69684.6" + attribute \src "libresoc.v:70405.3-70549.6" wire width 2 $0\SV_Ptype[1:0] - attribute \src "libresoc.v:69262.3-69400.6" + attribute \src "libresoc.v:70118.3-70259.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:72383.3-72524.6" + attribute \src "libresoc.v:73305.3-73449.6" wire $0\br[0:0] - attribute \src "libresoc.v:70253.3-70394.6" + attribute \src "libresoc.v:71130.3-71274.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:70395.3-70536.6" + attribute \src "libresoc.v:71275.3-71419.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:71815.3-71956.6" + attribute \src "libresoc.v:72725.3-72869.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:72241.3-72382.6" + attribute \src "libresoc.v:73160.3-73304.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:73661.3-73802.6" + attribute \src "libresoc.v:69973.3-70117.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:73377.3-73518.6" - wire width 13 $0\function_unit[12:0] - attribute \src "libresoc.v:69685.3-69826.6" + attribute \src "libresoc.v:74320.3-74464.6" + wire width 14 $0\function_unit[13:0] + attribute \src "libresoc.v:70550.3-70694.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:69827.3-69968.6" + attribute \src "libresoc.v:70695.3-70839.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:69969.3-70110.6" + attribute \src "libresoc.v:70840.3-70984.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:66595.7-66595.20" + attribute \src "libresoc.v:66950.7-66950.20" wire $0\initial[0:0] - attribute \src "libresoc.v:73519.3-73660.6" + attribute \src "libresoc.v:74465.3-74609.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:71957.3-72098.6" + attribute \src "libresoc.v:72870.3-73014.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:72099.3-72240.6" + attribute \src "libresoc.v:73015.3-73159.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:72809.3-72950.6" + attribute \src "libresoc.v:73740.3-73884.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:71389.3-71530.6" + attribute \src "libresoc.v:72290.3-72434.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:73093.3-73234.6" + attribute \src "libresoc.v:74030.3-74174.6" wire $0\lk[0:0] - attribute \src "libresoc.v:70111.3-70252.6" - wire width 2 $0\out_sel[1:0] - attribute \src "libresoc.v:71673.3-71814.6" + attribute \src "libresoc.v:70985.3-71129.6" + wire width 3 $0\out_sel[2:0] + attribute \src "libresoc.v:72580.3-72724.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:72667.3-72808.6" + attribute \src "libresoc.v:73595.3-73739.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:73235.3-73376.6" + attribute \src "libresoc.v:74175.3-74319.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:72951.3-73092.6" + attribute \src "libresoc.v:73885.3-74029.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:72525.3-72666.6" + attribute \src "libresoc.v:73450.3-73594.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:71105.3-71246.6" + attribute \src "libresoc.v:72000.3-72144.6" wire width 3 $0\sv_cr_in[2:0] - attribute \src "libresoc.v:71247.3-71388.6" + attribute \src "libresoc.v:72145.3-72289.6" wire width 3 $0\sv_cr_out[2:0] - attribute \src "libresoc.v:70537.3-70678.6" + attribute \src "libresoc.v:71420.3-71564.6" wire width 3 $0\sv_in1[2:0] - attribute \src "libresoc.v:70679.3-70820.6" + attribute \src "libresoc.v:71565.3-71709.6" wire width 3 $0\sv_in2[2:0] - attribute \src "libresoc.v:70821.3-70962.6" + attribute \src "libresoc.v:71710.3-71854.6" wire width 3 $0\sv_in3[2:0] - attribute \src "libresoc.v:70963.3-71104.6" + attribute \src "libresoc.v:71855.3-71999.6" wire width 3 $0\sv_out[2:0] - attribute \src "libresoc.v:71531.3-71672.6" + attribute \src "libresoc.v:72435.3-72579.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:69401.3-69542.6" + attribute \src "libresoc.v:70260.3-70404.6" wire width 2 $1\SV_Etype[1:0] - attribute \src "libresoc.v:69543.3-69684.6" + attribute \src "libresoc.v:70405.3-70549.6" wire width 2 $1\SV_Ptype[1:0] - attribute \src "libresoc.v:69262.3-69400.6" + attribute \src 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attribute \src "libresoc.v:73305.3-73449.6" wire $2\br[0:0] - attribute \src "libresoc.v:70253.3-70394.6" + attribute \src "libresoc.v:71130.3-71274.6" wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:70395.3-70536.6" + attribute \src "libresoc.v:71275.3-71419.6" wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:71815.3-71956.6" + attribute \src "libresoc.v:72725.3-72869.6" wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:72241.3-72382.6" + attribute \src "libresoc.v:73160.3-73304.6" wire $2\cry_out[0:0] - attribute \src "libresoc.v:73661.3-73802.6" + attribute \src "libresoc.v:69973.3-70117.6" wire width 5 $2\form[4:0] - attribute \src "libresoc.v:73377.3-73518.6" - wire width 13 $2\function_unit[12:0] - attribute \src "libresoc.v:69685.3-69826.6" + attribute \src "libresoc.v:74320.3-74464.6" + wire width 14 $2\function_unit[13:0] + attribute \src "libresoc.v:70550.3-70694.6" wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:69827.3-69968.6" + attribute \src "libresoc.v:70695.3-70839.6" wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:69969.3-70110.6" + attribute \src "libresoc.v:70840.3-70984.6" wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:73519.3-73660.6" + attribute \src "libresoc.v:74465.3-74609.6" wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:71957.3-72098.6" + attribute \src "libresoc.v:72870.3-73014.6" wire $2\inv_a[0:0] - attribute \src "libresoc.v:72099.3-72240.6" + attribute \src "libresoc.v:73015.3-73159.6" wire $2\inv_out[0:0] - attribute \src "libresoc.v:72809.3-72950.6" + attribute \src "libresoc.v:73740.3-73884.6" wire $2\is_32b[0:0] - attribute \src "libresoc.v:71389.3-71530.6" + attribute \src "libresoc.v:72290.3-72434.6" wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:73093.3-73234.6" + attribute \src "libresoc.v:74030.3-74174.6" wire $2\lk[0:0] - attribute \src "libresoc.v:70111.3-70252.6" - wire width 2 $2\out_sel[1:0] - attribute \src "libresoc.v:71673.3-71814.6" + attribute \src "libresoc.v:70985.3-71129.6" + wire width 3 $2\out_sel[2:0] + attribute \src "libresoc.v:72580.3-72724.6" wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:72667.3-72808.6" + attribute \src "libresoc.v:73595.3-73739.6" wire $2\rsrv[0:0] - attribute \src "libresoc.v:73235.3-73376.6" + attribute \src "libresoc.v:74175.3-74319.6" wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:72951.3-73092.6" + attribute \src "libresoc.v:73885.3-74029.6" wire $2\sgn[0:0] - attribute \src "libresoc.v:72525.3-72666.6" + attribute \src "libresoc.v:73450.3-73594.6" wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:71105.3-71246.6" + attribute \src "libresoc.v:72000.3-72144.6" wire width 3 $2\sv_cr_in[2:0] - attribute \src "libresoc.v:71247.3-71388.6" + attribute \src "libresoc.v:72145.3-72289.6" wire width 3 $2\sv_cr_out[2:0] - attribute \src "libresoc.v:70537.3-70678.6" + attribute \src "libresoc.v:71420.3-71564.6" wire width 3 $2\sv_in1[2:0] - attribute \src "libresoc.v:70679.3-70820.6" + attribute \src "libresoc.v:71565.3-71709.6" wire width 3 $2\sv_in2[2:0] - attribute \src "libresoc.v:70821.3-70962.6" + attribute \src "libresoc.v:71710.3-71854.6" wire width 3 $2\sv_in3[2:0] - attribute \src "libresoc.v:70963.3-71104.6" + attribute \src "libresoc.v:71855.3-71999.6" wire width 3 $2\sv_out[2:0] - attribute \src "libresoc.v:71531.3-71672.6" + attribute \src "libresoc.v:72435.3-72579.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:69086.17-69086.211" - wire width 32 $ternary$libresoc.v:69086$3553_Y + attribute \src "libresoc.v:69762.17-69762.211" + wire width 32 $ternary$libresoc.v:69762$3553_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -109702,6 +110057,8 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire output 24 \OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 21 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 output 22 \RB @@ -109732,7 +110089,7 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \SVL_SVi + wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -110160,8 +110517,6 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 output 17 \asmcode @@ -110275,21 +110630,22 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec19_dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec19_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -110395,6 +110751,7 @@ module \dec$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec19_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -110414,12 +110771,13 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec19_dec19_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec19_dec19_out_sel + wire width 3 \dec19_dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -110502,6 +110860,309 @@ module \dec$171 attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 \dec22_dec22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 \dec22_dec22_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec22_dec22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec22_dec22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec22_dec22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec22_dec22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec22_dec22_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec22_dec22_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec22_dec22_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec22_opcode_in + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec30_dec30_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" @@ -110575,21 +111236,22 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec30_dec30_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec30_dec30_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec30_dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -110695,6 +111357,7 @@ module \dec$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec30_dec30_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -110714,12 +111377,13 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec30_dec30_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec30_dec30_out_sel + wire width 3 \dec30_dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -110875,21 +111539,22 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec31_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -110995,6 +111660,7 @@ module \dec$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -111014,12 +111680,13 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec31_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec31_out_sel + wire width 3 \dec31_dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -111175,21 +111842,22 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec58_dec58_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec58_dec58_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec58_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -111295,6 +111963,7 @@ module \dec$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec58_dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -111314,12 +111983,13 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec58_dec58_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec58_dec58_out_sel + wire width 3 \dec58_dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -111475,21 +112145,22 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec62_dec62_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec62_dec62_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec62_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -111595,6 +112266,7 @@ module \dec$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec62_dec62_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -111614,12 +112286,13 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec62_dec62_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec62_dec62_out_sel + wire width 3 \dec62_dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -111731,21 +112404,22 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 6 \function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 6 \function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -111777,7 +112451,7 @@ module \dec$171 attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 15 \in3_sel - attribute \src "libresoc.v:66595.7-66595.15" + attribute \src "libresoc.v:66950.7-66950.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111853,6 +112527,7 @@ module \dec$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 4 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -111878,12 +112553,13 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 32 \opcode_switch$1 attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 16 \out_sel + wire width 3 output 16 \out_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 1 \raw_opcode_in attribute \enum_base_type "RC" @@ -111964,15 +112640,15 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 18 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:69086$3553 + cell $mux $ternary$libresoc.v:69762$3553 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:69086$3553_Y + connect \Y $ternary$libresoc.v:69762$3553_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:69087.9-69121.4" + attribute \src "libresoc.v:69763.9-69797.4" cell \dec19 \dec19 connect \dec19_SV_Etype \dec19_dec19_SV_Etype connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype @@ -112009,7 +112685,44 @@ module \dec$171 connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69122.9-69156.4" + attribute \src "libresoc.v:69798.9-69832.4" + cell \dec22 \dec22 + connect \dec22_SV_Etype \dec22_dec22_SV_Etype + connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype + connect \dec22_asmcode \dec22_dec22_asmcode + connect \dec22_br \dec22_dec22_br + connect \dec22_cr_in \dec22_dec22_cr_in + connect \dec22_cr_out \dec22_dec22_cr_out + connect \dec22_cry_in \dec22_dec22_cry_in + connect \dec22_cry_out \dec22_dec22_cry_out + connect \dec22_form \dec22_dec22_form + connect \dec22_function_unit \dec22_dec22_function_unit + connect \dec22_in1_sel \dec22_dec22_in1_sel + connect \dec22_in2_sel \dec22_dec22_in2_sel + connect \dec22_in3_sel \dec22_dec22_in3_sel + connect \dec22_internal_op \dec22_dec22_internal_op + connect \dec22_inv_a \dec22_dec22_inv_a + connect \dec22_inv_out \dec22_dec22_inv_out + connect \dec22_is_32b \dec22_dec22_is_32b + connect \dec22_ldst_len \dec22_dec22_ldst_len + connect \dec22_lk \dec22_dec22_lk + connect \dec22_out_sel \dec22_dec22_out_sel + connect \dec22_rc_sel \dec22_dec22_rc_sel + connect \dec22_rsrv \dec22_dec22_rsrv + connect \dec22_sgl_pipe \dec22_dec22_sgl_pipe + connect \dec22_sgn \dec22_dec22_sgn + connect \dec22_sgn_ext \dec22_dec22_sgn_ext + connect \dec22_sv_cr_in \dec22_dec22_sv_cr_in + connect \dec22_sv_cr_out \dec22_dec22_sv_cr_out + connect \dec22_sv_in1 \dec22_dec22_sv_in1 + connect \dec22_sv_in2 \dec22_dec22_sv_in2 + connect \dec22_sv_in3 \dec22_dec22_sv_in3 + connect \dec22_sv_out \dec22_dec22_sv_out + connect \dec22_upd \dec22_dec22_upd + connect \opcode_in \dec22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69833.9-69867.4" cell \dec30 \dec30 connect \dec30_SV_Etype \dec30_dec30_SV_Etype connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype @@ -112046,7 +112759,7 @@ module \dec$171 connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69157.9-69191.4" + attribute \src "libresoc.v:69868.9-69902.4" cell \dec31 \dec31 connect \dec31_SV_Etype \dec31_dec31_SV_Etype connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype @@ -112083,7 +112796,7 @@ module \dec$171 connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69192.9-69226.4" + attribute \src "libresoc.v:69903.9-69937.4" cell \dec58 \dec58 connect \dec58_SV_Etype \dec58_dec58_SV_Etype connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype @@ -112120,7 +112833,7 @@ module \dec$171 connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69227.9-69261.4" + attribute \src "libresoc.v:69938.9-69972.4" cell \dec62 \dec62 connect \dec62_SV_Etype \dec62_dec62_SV_Etype connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype @@ -112156,23 +112869,228 @@ module \dec$171 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:66595.7-66595.20" - process $proc$libresoc.v:66595$3586 + attribute \src "libresoc.v:66950.7-66950.20" + process $proc$libresoc.v:66950$3586 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:69262.3-69400.6" - process $proc$libresoc.v:69262$3554 + attribute \src "libresoc.v:69973.3-70117.6" + process $proc$libresoc.v:69973$3554 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:69974.5-69974.29" + switch \initial + attribute \src "libresoc.v:69974.9-69974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\form[4:0] \dec22_dec22_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + attribute \src "libresoc.v:70118.3-70259.6" + process $proc$libresoc.v:70118$3555 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:69263.5-69263.29" + attribute \src "libresoc.v:70119.5-70119.29" switch \initial - attribute \src "libresoc.v:69263.9-69263.17" + attribute \src "libresoc.v:70119.9-70119.17" case 1'1 case end @@ -112199,6 +113117,10 @@ module \dec$171 assign { } { } assign $1\asmcode[7:0] \dec62_dec62_asmcode attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\asmcode[7:0] \dec22_dec22_asmcode + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\asmcode[7:0] 8'00000111 @@ -112361,15 +113283,15 @@ module \dec$171 sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:69401.3-69542.6" - process $proc$libresoc.v:69401$3555 + attribute \src "libresoc.v:70260.3-70404.6" + process $proc$libresoc.v:70260$3556 assign { } { } assign { } { } assign { } { } assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] - attribute \src "libresoc.v:69402.5-69402.29" + attribute \src "libresoc.v:70261.5-70261.29" switch \initial - attribute \src "libresoc.v:69402.9-69402.17" + attribute \src "libresoc.v:70261.9-70261.17" case 1'1 case end @@ -112396,6 +113318,10 @@ module \dec$171 assign { } { } assign $1\SV_Etype[1:0] \dec62_dec62_SV_Etype attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\SV_Etype[1:0] \dec22_dec22_SV_Etype + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\SV_Etype[1:0] 2'10 @@ -112562,15 +113488,15 @@ module \dec$171 sync always update \SV_Etype $0\SV_Etype[1:0] end - attribute \src "libresoc.v:69543.3-69684.6" - process $proc$libresoc.v:69543$3556 + attribute \src "libresoc.v:70405.3-70549.6" + process $proc$libresoc.v:70405$3557 assign { } { } assign { } { } assign { } { } assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] - attribute \src "libresoc.v:69544.5-69544.29" + attribute \src "libresoc.v:70406.5-70406.29" switch \initial - attribute \src "libresoc.v:69544.9-69544.17" + attribute \src "libresoc.v:70406.9-70406.17" case 1'1 case end @@ -112597,6 +113523,10 @@ module \dec$171 assign { } { } assign $1\SV_Ptype[1:0] \dec62_dec62_SV_Ptype attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec22_dec22_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\SV_Ptype[1:0] 2'10 @@ -112763,15 +113693,15 @@ module \dec$171 sync always update \SV_Ptype $0\SV_Ptype[1:0] end - attribute \src "libresoc.v:69685.3-69826.6" - process $proc$libresoc.v:69685$3557 + attribute \src "libresoc.v:70550.3-70694.6" + process $proc$libresoc.v:70550$3558 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:69686.5-69686.29" + attribute \src "libresoc.v:70551.5-70551.29" switch \initial - attribute \src "libresoc.v:69686.9-69686.17" + attribute \src "libresoc.v:70551.9-70551.17" case 1'1 case end @@ -112798,6 +113728,10 @@ module \dec$171 assign { } { } assign $1\in1_sel[2:0] \dec62_dec62_in1_sel attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in1_sel[2:0] \dec22_dec22_in1_sel + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in1_sel[2:0] 3'001 @@ -112964,15 +113898,15 @@ module \dec$171 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:69827.3-69968.6" - process $proc$libresoc.v:69827$3558 + attribute \src "libresoc.v:70695.3-70839.6" + process $proc$libresoc.v:70695$3559 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:69828.5-69828.29" + attribute \src "libresoc.v:70696.5-70696.29" switch \initial - attribute \src "libresoc.v:69828.9-69828.17" + attribute \src "libresoc.v:70696.9-70696.17" case 1'1 case end @@ -112999,6 +113933,10 @@ module \dec$171 assign { } { } assign $1\in2_sel[3:0] \dec62_dec62_in2_sel attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in2_sel[3:0] \dec22_dec22_in2_sel + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in2_sel[3:0] 4'0011 @@ -113165,15 +114103,15 @@ module \dec$171 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:69969.3-70110.6" - process $proc$libresoc.v:69969$3559 + attribute \src "libresoc.v:70840.3-70984.6" + process $proc$libresoc.v:70840$3560 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:69970.5-69970.29" + attribute \src "libresoc.v:70841.5-70841.29" switch \initial - attribute \src "libresoc.v:69970.9-69970.17" + attribute \src "libresoc.v:70841.9-70841.17" case 1'1 case end @@ -113200,6 +114138,10 @@ module \dec$171 assign { } { } assign $1\in3_sel[1:0] \dec62_dec62_in3_sel attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\in3_sel[1:0] \dec22_dec22_in3_sel + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in3_sel[1:0] 2'00 @@ -113366,15 +114308,15 @@ module \dec$171 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:70111.3-70252.6" - process $proc$libresoc.v:70111$3560 + attribute \src "libresoc.v:70985.3-71129.6" + process $proc$libresoc.v:70985$3561 assign { } { } assign { } { } assign { } { } - assign $0\out_sel[1:0] $2\out_sel[1:0] - attribute \src "libresoc.v:70112.5-70112.29" + assign $0\out_sel[2:0] $2\out_sel[2:0] + attribute \src "libresoc.v:70986.5-70986.29" switch \initial - attribute \src "libresoc.v:70112.9-70112.17" + attribute \src "libresoc.v:70986.9-70986.17" case 1'1 case end @@ -113383,199 +114325,203 @@ module \dec$171 attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\out_sel[1:0] \dec19_dec19_out_sel + assign $1\out_sel[2:0] \dec19_dec19_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } - assign $1\out_sel[1:0] \dec30_dec30_out_sel + assign $1\out_sel[2:0] \dec30_dec30_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\out_sel[1:0] \dec31_dec31_out_sel + assign $1\out_sel[2:0] \dec31_dec31_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } - assign $1\out_sel[1:0] \dec58_dec58_out_sel + assign $1\out_sel[2:0] \dec58_dec58_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } - assign $1\out_sel[1:0] \dec62_dec62_out_sel + assign $1\out_sel[2:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\out_sel[2:0] \dec22_dec22_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } - assign $1\out_sel[1:0] 2'11 + assign $1\out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\out_sel[1:0] 2'01 + assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\out_sel[1:0] 2'10 + assign $1\out_sel[2:0] 3'010 case - assign $1\out_sel[1:0] 2'00 + assign $1\out_sel[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } - assign $2\out_sel[1:0] 2'00 + assign $2\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } - assign $2\out_sel[1:0] 2'00 + assign $2\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } - assign $2\out_sel[1:0] 2'01 + assign $2\out_sel[2:0] 3'001 case - assign $2\out_sel[1:0] $1\out_sel[1:0] + assign $2\out_sel[2:0] $1\out_sel[2:0] end sync always - update \out_sel $0\out_sel[1:0] + update \out_sel $0\out_sel[2:0] end - attribute \src "libresoc.v:70253.3-70394.6" - process $proc$libresoc.v:70253$3561 + attribute \src "libresoc.v:71130.3-71274.6" + process $proc$libresoc.v:71130$3562 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:70254.5-70254.29" + attribute \src "libresoc.v:71131.5-71131.29" switch \initial - attribute \src "libresoc.v:70254.9-70254.17" + attribute \src "libresoc.v:71131.9-71131.17" case 1'1 case end @@ -113602,6 +114548,10 @@ module \dec$171 assign { } { } assign $1\cr_in[2:0] \dec62_dec62_cr_in attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cr_in[2:0] \dec22_dec22_cr_in + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cr_in[2:0] 3'000 @@ -113768,15 +114718,15 @@ module \dec$171 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:70395.3-70536.6" - process $proc$libresoc.v:70395$3562 + attribute \src "libresoc.v:71275.3-71419.6" + process $proc$libresoc.v:71275$3563 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:70396.5-70396.29" + attribute \src "libresoc.v:71276.5-71276.29" switch \initial - attribute \src "libresoc.v:70396.9-70396.17" + attribute \src "libresoc.v:71276.9-71276.17" case 1'1 case end @@ -113803,6 +114753,10 @@ module \dec$171 assign { } { } assign $1\cr_out[2:0] \dec62_dec62_cr_out attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cr_out[2:0] \dec22_dec22_cr_out + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cr_out[2:0] 3'000 @@ -113969,15 +114923,15 @@ module \dec$171 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:70537.3-70678.6" - process $proc$libresoc.v:70537$3563 + attribute \src "libresoc.v:71420.3-71564.6" + process $proc$libresoc.v:71420$3564 assign { } { } assign { } { } assign { } { } assign $0\sv_in1[2:0] $2\sv_in1[2:0] - attribute \src "libresoc.v:70538.5-70538.29" + attribute \src "libresoc.v:71421.5-71421.29" switch \initial - attribute \src "libresoc.v:70538.9-70538.17" + attribute \src "libresoc.v:71421.9-71421.17" case 1'1 case end @@ -114004,6 +114958,10 @@ module \dec$171 assign { } { } assign $1\sv_in1[2:0] \dec62_dec62_sv_in1 attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in1[2:0] \dec22_dec22_sv_in1 + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_in1[2:0] 3'010 @@ -114170,15 +115128,15 @@ module \dec$171 sync always update \sv_in1 $0\sv_in1[2:0] end - attribute \src "libresoc.v:70679.3-70820.6" - process $proc$libresoc.v:70679$3564 + attribute \src "libresoc.v:71565.3-71709.6" + process $proc$libresoc.v:71565$3565 assign { } { } assign { } { } assign { } { } assign $0\sv_in2[2:0] $2\sv_in2[2:0] - attribute \src "libresoc.v:70680.5-70680.29" + attribute \src "libresoc.v:71566.5-71566.29" switch \initial - attribute \src "libresoc.v:70680.9-70680.17" + attribute \src "libresoc.v:71566.9-71566.17" case 1'1 case end @@ -114205,6 +115163,10 @@ module \dec$171 assign { } { } assign $1\sv_in2[2:0] \dec62_dec62_sv_in2 attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in2[2:0] \dec22_dec22_sv_in2 + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_in2[2:0] 3'000 @@ -114371,15 +115333,15 @@ module \dec$171 sync always update \sv_in2 $0\sv_in2[2:0] end - attribute \src "libresoc.v:70821.3-70962.6" - process $proc$libresoc.v:70821$3565 + attribute \src "libresoc.v:71710.3-71854.6" + process $proc$libresoc.v:71710$3566 assign { } { } assign { } { } assign { } { } assign $0\sv_in3[2:0] $2\sv_in3[2:0] - attribute \src "libresoc.v:70822.5-70822.29" + attribute \src "libresoc.v:71711.5-71711.29" switch \initial - attribute \src "libresoc.v:70822.9-70822.17" + attribute \src "libresoc.v:71711.9-71711.17" case 1'1 case end @@ -114406,6 +115368,10 @@ module \dec$171 assign { } { } assign $1\sv_in3[2:0] \dec62_dec62_sv_in3 attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_in3[2:0] \dec22_dec22_sv_in3 + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_in3[2:0] 3'000 @@ -114508,7 +115474,7 @@ module \dec$171 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\sv_in3[2:0] 3'000 + assign $1\sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } @@ -114516,7 +115482,7 @@ module \dec$171 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\sv_in3[2:0] 3'000 + assign $1\sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } @@ -114524,7 +115490,7 @@ module \dec$171 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\sv_in3[2:0] 3'000 + assign $1\sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } @@ -114572,15 +115538,15 @@ module \dec$171 sync always update \sv_in3 $0\sv_in3[2:0] end - attribute \src "libresoc.v:70963.3-71104.6" - process $proc$libresoc.v:70963$3566 + attribute \src "libresoc.v:71855.3-71999.6" + process $proc$libresoc.v:71855$3567 assign { } { } assign { } { } assign { } { } assign $0\sv_out[2:0] $2\sv_out[2:0] - attribute \src "libresoc.v:70964.5-70964.29" + attribute \src "libresoc.v:71856.5-71856.29" switch \initial - attribute \src "libresoc.v:70964.9-70964.17" + attribute \src "libresoc.v:71856.9-71856.17" case 1'1 case end @@ -114607,6 +115573,10 @@ module \dec$171 assign { } { } assign $1\sv_out[2:0] \dec62_dec62_sv_out attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_out[2:0] \dec22_dec22_sv_out + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_out[2:0] 3'001 @@ -114773,15 +115743,15 @@ module \dec$171 sync always update \sv_out $0\sv_out[2:0] end - attribute \src "libresoc.v:71105.3-71246.6" - process $proc$libresoc.v:71105$3567 + attribute \src "libresoc.v:72000.3-72144.6" + process $proc$libresoc.v:72000$3568 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] - attribute \src "libresoc.v:71106.5-71106.29" + attribute \src "libresoc.v:72001.5-72001.29" switch \initial - attribute \src "libresoc.v:71106.9-71106.17" + attribute \src "libresoc.v:72001.9-72001.17" case 1'1 case end @@ -114808,6 +115778,10 @@ module \dec$171 assign { } { } assign $1\sv_cr_in[2:0] \dec62_dec62_sv_cr_in attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec22_dec22_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_cr_in[2:0] 3'000 @@ -114974,15 +115948,15 @@ module \dec$171 sync always update \sv_cr_in $0\sv_cr_in[2:0] end - attribute \src "libresoc.v:71247.3-71388.6" - process $proc$libresoc.v:71247$3568 + attribute \src "libresoc.v:72145.3-72289.6" + process $proc$libresoc.v:72145$3569 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] - attribute \src "libresoc.v:71248.5-71248.29" + attribute \src "libresoc.v:72146.5-72146.29" switch \initial - attribute \src "libresoc.v:71248.9-71248.17" + attribute \src "libresoc.v:72146.9-72146.17" case 1'1 case end @@ -115009,6 +115983,10 @@ module \dec$171 assign { } { } assign $1\sv_cr_out[2:0] \dec62_dec62_sv_cr_out attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec22_dec22_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_cr_out[2:0] 3'000 @@ -115175,15 +116153,15 @@ module \dec$171 sync always update \sv_cr_out $0\sv_cr_out[2:0] end - attribute \src "libresoc.v:71389.3-71530.6" - process $proc$libresoc.v:71389$3569 + attribute \src "libresoc.v:72290.3-72434.6" + process $proc$libresoc.v:72290$3570 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:71390.5-71390.29" + attribute \src "libresoc.v:72291.5-72291.29" switch \initial - attribute \src "libresoc.v:71390.9-71390.17" + attribute \src "libresoc.v:72291.9-72291.17" case 1'1 case end @@ -115210,6 +116188,10 @@ module \dec$171 assign { } { } assign $1\ldst_len[3:0] \dec62_dec62_ldst_len attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\ldst_len[3:0] \dec22_dec22_ldst_len + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ldst_len[3:0] 4'0000 @@ -115376,15 +116358,15 @@ module \dec$171 sync always update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:71531.3-71672.6" - process $proc$libresoc.v:71531$3570 + attribute \src "libresoc.v:72435.3-72579.6" + process $proc$libresoc.v:72435$3571 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:71532.5-71532.29" + attribute \src "libresoc.v:72436.5-72436.29" switch \initial - attribute \src "libresoc.v:71532.9-71532.17" + attribute \src "libresoc.v:72436.9-72436.17" case 1'1 case end @@ -115411,6 +116393,10 @@ module \dec$171 assign { } { } assign $1\upd[1:0] \dec62_dec62_upd attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\upd[1:0] \dec22_dec22_upd + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\upd[1:0] 2'00 @@ -115577,15 +116563,15 @@ module \dec$171 sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:71673.3-71814.6" - process $proc$libresoc.v:71673$3571 + attribute \src "libresoc.v:72580.3-72724.6" + process $proc$libresoc.v:72580$3572 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:71674.5-71674.29" + attribute \src "libresoc.v:72581.5-72581.29" switch \initial - attribute \src "libresoc.v:71674.9-71674.17" + attribute \src "libresoc.v:72581.9-72581.17" case 1'1 case end @@ -115612,6 +116598,10 @@ module \dec$171 assign { } { } assign $1\rc_sel[1:0] \dec62_dec62_rc_sel attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\rc_sel[1:0] \dec22_dec22_rc_sel + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\rc_sel[1:0] 2'00 @@ -115778,15 +116768,15 @@ module \dec$171 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:71815.3-71956.6" - process $proc$libresoc.v:71815$3572 + attribute \src "libresoc.v:72725.3-72869.6" + process $proc$libresoc.v:72725$3573 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:71816.5-71816.29" + attribute \src "libresoc.v:72726.5-72726.29" switch \initial - attribute \src "libresoc.v:71816.9-71816.17" + attribute \src "libresoc.v:72726.9-72726.17" case 1'1 case end @@ -115813,6 +116803,10 @@ module \dec$171 assign { } { } assign $1\cry_in[1:0] \dec62_dec62_cry_in attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cry_in[1:0] \dec22_dec22_cry_in + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cry_in[1:0] 2'00 @@ -115979,15 +116973,15 @@ module \dec$171 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:71957.3-72098.6" - process $proc$libresoc.v:71957$3573 + attribute \src "libresoc.v:72870.3-73014.6" + process $proc$libresoc.v:72870$3574 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:71958.5-71958.29" + attribute \src "libresoc.v:72871.5-72871.29" switch \initial - attribute \src "libresoc.v:71958.9-71958.17" + attribute \src "libresoc.v:72871.9-72871.17" case 1'1 case end @@ -116014,6 +117008,10 @@ module \dec$171 assign { } { } assign $1\inv_a[0:0] \dec62_dec62_inv_a attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\inv_a[0:0] \dec22_dec22_inv_a + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\inv_a[0:0] 1'0 @@ -116180,15 +117178,15 @@ module \dec$171 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:72099.3-72240.6" - process $proc$libresoc.v:72099$3574 + attribute \src "libresoc.v:73015.3-73159.6" + process $proc$libresoc.v:73015$3575 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:72100.5-72100.29" + attribute \src "libresoc.v:73016.5-73016.29" switch \initial - attribute \src "libresoc.v:72100.9-72100.17" + attribute \src "libresoc.v:73016.9-73016.17" case 1'1 case end @@ -116215,6 +117213,10 @@ module \dec$171 assign { } { } assign $1\inv_out[0:0] \dec62_dec62_inv_out attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\inv_out[0:0] \dec22_dec22_inv_out + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\inv_out[0:0] 1'0 @@ -116381,15 +117383,15 @@ module \dec$171 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:72241.3-72382.6" - process $proc$libresoc.v:72241$3575 + attribute \src "libresoc.v:73160.3-73304.6" + process $proc$libresoc.v:73160$3576 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:72242.5-72242.29" + attribute \src "libresoc.v:73161.5-73161.29" switch \initial - attribute \src "libresoc.v:72242.9-72242.17" + attribute \src "libresoc.v:73161.9-73161.17" case 1'1 case end @@ -116416,6 +117418,10 @@ module \dec$171 assign { } { } assign $1\cry_out[0:0] \dec62_dec62_cry_out attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\cry_out[0:0] \dec22_dec22_cry_out + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cry_out[0:0] 1'1 @@ -116582,15 +117588,15 @@ module \dec$171 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:72383.3-72524.6" - process $proc$libresoc.v:72383$3576 + attribute \src "libresoc.v:73305.3-73449.6" + process $proc$libresoc.v:73305$3577 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:72384.5-72384.29" + attribute \src "libresoc.v:73306.5-73306.29" switch \initial - attribute \src "libresoc.v:72384.9-72384.17" + attribute \src "libresoc.v:73306.9-73306.17" case 1'1 case end @@ -116617,6 +117623,10 @@ module \dec$171 assign { } { } assign $1\br[0:0] \dec62_dec62_br attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\br[0:0] \dec22_dec22_br + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\br[0:0] 1'0 @@ -116783,15 +117793,15 @@ module \dec$171 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:72525.3-72666.6" - process $proc$libresoc.v:72525$3577 + attribute \src "libresoc.v:73450.3-73594.6" + process $proc$libresoc.v:73450$3578 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:72526.5-72526.29" + attribute \src "libresoc.v:73451.5-73451.29" switch \initial - attribute \src "libresoc.v:72526.9-72526.17" + attribute \src "libresoc.v:73451.9-73451.17" case 1'1 case end @@ -116818,6 +117828,10 @@ module \dec$171 assign { } { } assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgn_ext[0:0] \dec22_dec22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgn_ext[0:0] 1'0 @@ -116984,15 +117998,15 @@ module \dec$171 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:72667.3-72808.6" - process $proc$libresoc.v:72667$3578 + attribute \src "libresoc.v:73595.3-73739.6" + process $proc$libresoc.v:73595$3579 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:72668.5-72668.29" + attribute \src "libresoc.v:73596.5-73596.29" switch \initial - attribute \src "libresoc.v:72668.9-72668.17" + attribute \src "libresoc.v:73596.9-73596.17" case 1'1 case end @@ -117019,6 +118033,10 @@ module \dec$171 assign { } { } assign $1\rsrv[0:0] \dec62_dec62_rsrv attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\rsrv[0:0] \dec22_dec22_rsrv + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\rsrv[0:0] 1'0 @@ -117185,15 +118203,15 @@ module \dec$171 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:72809.3-72950.6" - process $proc$libresoc.v:72809$3579 + attribute \src "libresoc.v:73740.3-73884.6" + process $proc$libresoc.v:73740$3580 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:72810.5-72810.29" + attribute \src "libresoc.v:73741.5-73741.29" switch \initial - attribute \src "libresoc.v:72810.9-72810.17" + attribute \src "libresoc.v:73741.9-73741.17" case 1'1 case end @@ -117220,6 +118238,10 @@ module \dec$171 assign { } { } assign $1\is_32b[0:0] \dec62_dec62_is_32b attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\is_32b[0:0] \dec22_dec22_is_32b + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\is_32b[0:0] 1'0 @@ -117386,15 +118408,15 @@ module \dec$171 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:72951.3-73092.6" - process $proc$libresoc.v:72951$3580 + attribute \src "libresoc.v:73885.3-74029.6" + process $proc$libresoc.v:73885$3581 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:72952.5-72952.29" + attribute \src "libresoc.v:73886.5-73886.29" switch \initial - attribute \src "libresoc.v:72952.9-72952.17" + attribute \src "libresoc.v:73886.9-73886.17" case 1'1 case end @@ -117421,6 +118443,10 @@ module \dec$171 assign { } { } assign $1\sgn[0:0] \dec62_dec62_sgn attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgn[0:0] \dec22_dec22_sgn + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgn[0:0] 1'0 @@ -117587,15 +118613,15 @@ module \dec$171 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:73093.3-73234.6" - process $proc$libresoc.v:73093$3581 + attribute \src "libresoc.v:74030.3-74174.6" + process $proc$libresoc.v:74030$3582 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:73094.5-73094.29" + attribute \src "libresoc.v:74031.5-74031.29" switch \initial - attribute \src "libresoc.v:73094.9-73094.17" + attribute \src "libresoc.v:74031.9-74031.17" case 1'1 case end @@ -117622,6 +118648,10 @@ module \dec$171 assign { } { } assign $1\lk[0:0] \dec62_dec62_lk attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\lk[0:0] \dec22_dec22_lk + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\lk[0:0] 1'0 @@ -117788,15 +118818,15 @@ module \dec$171 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:73235.3-73376.6" - process $proc$libresoc.v:73235$3582 + attribute \src "libresoc.v:74175.3-74319.6" + process $proc$libresoc.v:74175$3583 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:73236.5-73236.29" + attribute \src "libresoc.v:74176.5-74176.29" switch \initial - attribute \src "libresoc.v:73236.9-73236.17" + attribute \src "libresoc.v:74176.9-74176.17" case 1'1 case end @@ -117823,6 +118853,10 @@ module \dec$171 assign { } { } assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec22_dec22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgl_pipe[0:0] 1'0 @@ -117989,15 +119023,15 @@ module \dec$171 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:73377.3-73518.6" - process $proc$libresoc.v:73377$3583 + attribute \src "libresoc.v:74320.3-74464.6" + process $proc$libresoc.v:74320$3584 assign { } { } assign { } { } assign { } { } - assign $0\function_unit[12:0] $2\function_unit[12:0] - attribute \src "libresoc.v:73378.5-73378.29" + assign $0\function_unit[13:0] $2\function_unit[13:0] + attribute \src "libresoc.v:74321.5-74321.29" switch \initial - attribute \src "libresoc.v:73378.9-73378.17" + attribute \src "libresoc.v:74321.9-74321.17" case 1'1 case end @@ -118006,199 +119040,203 @@ module \dec$171 attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } - assign $1\function_unit[12:0] \dec19_dec19_function_unit + assign $1\function_unit[13:0] \dec19_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } - assign $1\function_unit[12:0] \dec30_dec30_function_unit + assign $1\function_unit[13:0] \dec30_dec30_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } - assign $1\function_unit[12:0] \dec31_dec31_function_unit + assign $1\function_unit[13:0] \dec31_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } - assign $1\function_unit[12:0] \dec58_dec58_function_unit + assign $1\function_unit[13:0] \dec58_dec58_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } - assign $1\function_unit[12:0] \dec62_dec62_function_unit + assign $1\function_unit[13:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\function_unit[13:0] \dec22_dec22_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } - assign $1\function_unit[12:0] 13'0000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } - assign $1\function_unit[12:0] 13'0000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } - assign $1\function_unit[12:0] 13'0000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } - assign $1\function_unit[12:0] 13'0000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } - assign $1\function_unit[12:0] 13'0000010000000 + assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } - assign $1\function_unit[12:0] 13'0000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } - assign $1\function_unit[12:0] 13'0000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } - assign $1\function_unit[12:0] 13'0000000100000 + assign $1\function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } - assign $1\function_unit[12:0] 13'0000000100000 + assign $1\function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } - assign $1\function_unit[12:0] 13'0000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } - assign $1\function_unit[12:0] 13'0000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } - assign $1\function_unit[12:0] 13'0000100000000 + assign $1\function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } - assign $1\function_unit[12:0] 13'0000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } - assign $1\function_unit[12:0] 13'0000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\function_unit[12:0] 13'0000000001000 + assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\function_unit[12:0] 13'0000000001000 + assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\function_unit[12:0] 13'0000000001000 + assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } - assign $1\function_unit[12:0] 13'0000000000100 + assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } - assign $1\function_unit[12:0] 13'0000000000010 + assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } - assign $1\function_unit[12:0] 13'0000010000000 + assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } - assign $1\function_unit[12:0] 13'0000010000000 + assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } - assign $1\function_unit[12:0] 13'0000000010000 + assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } - assign $1\function_unit[12:0] 13'0000000010000 + assign $1\function_unit[13:0] 14'00000000010000 case - assign $1\function_unit[12:0] 13'0000000000000 + assign $1\function_unit[13:0] 14'00000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } - assign $2\function_unit[12:0] 13'0000000000000 + assign $2\function_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } - assign $2\function_unit[12:0] 13'0000000000000 + assign $2\function_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } - assign $2\function_unit[12:0] 13'0000000000000 + assign $2\function_unit[13:0] 14'00000000000000 case - assign $2\function_unit[12:0] $1\function_unit[12:0] + assign $2\function_unit[13:0] $1\function_unit[13:0] end sync always - update \function_unit $0\function_unit[12:0] + update \function_unit $0\function_unit[13:0] end - attribute \src "libresoc.v:73519.3-73660.6" - process $proc$libresoc.v:73519$3584 + attribute \src "libresoc.v:74465.3-74609.6" + process $proc$libresoc.v:74465$3585 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:73520.5-73520.29" + attribute \src "libresoc.v:74466.5-74466.29" switch \initial - attribute \src "libresoc.v:73520.9-73520.17" + attribute \src "libresoc.v:74466.9-74466.17" case 1'1 case end @@ -118225,6 +119263,10 @@ module \dec$171 assign { } { } assign $1\internal_op[6:0] \dec62_dec62_internal_op attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\internal_op[6:0] \dec22_dec22_internal_op + attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\internal_op[6:0] 7'0000010 @@ -118391,208 +119433,7 @@ module \dec$171 sync always update \internal_op $0\internal_op[6:0] end - attribute \src "libresoc.v:73661.3-73802.6" - process $proc$libresoc.v:73661$3585 - assign { } { } - assign { } { } - assign { } { } - assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:73662.5-73662.29" - switch \initial - attribute \src "libresoc.v:73662.9-73662.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\form[4:0] \dec19_dec19_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\form[4:0] \dec30_dec30_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\form[4:0] \dec31_dec31_form - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\form[4:0] \dec58_dec58_form - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\form[4:0] \dec62_dec62_form - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\form[4:0] 5'00011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\form[4:0] 5'00001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\form[4:0] 5'00100 - case - assign $1\form[4:0] 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\form[4:0] 5'00000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\form[4:0] 5'00000 - case - assign $2\form[4:0] $1\form[4:0] - end - sync always - update \form $0\form[4:0] - end - connect \$2 $ternary$libresoc.v:69086$3553_Y + connect \$2 $ternary$libresoc.v:69762$3553_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -118620,17 +119461,16 @@ module \dec$171 connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] + connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] - connect \SVL_SVi \opcode_in [15:10] + connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] @@ -118926,8 +119766,10 @@ module \dec$171 connect \RA \opcode_in [20:16] connect \RT \opcode_in [25:21] connect \RS \opcode_in [25:21] + connect \PO \opcode_in [31:26] connect \opcode_in \$2 connect \opcode_switch$1 \opcode_in + connect \dec22_opcode_in \opcode_in connect \dec62_opcode_in \opcode_in connect \dec58_opcode_in \opcode_in connect \dec31_opcode_in \opcode_in @@ -118935,140 +119777,140 @@ module \dec$171 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:74148.1-76149.10" +attribute \src "libresoc.v:74956.1-76960.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:75836.3-75887.6" + attribute \src "libresoc.v:76647.3-76698.6" wire width 2 $0\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:75888.3-75939.6" + attribute \src "libresoc.v:76699.3-76750.6" wire width 2 $0\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:75212.3-75263.6" + attribute \src "libresoc.v:76023.3-76074.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:75420.3-75471.6" + attribute \src "libresoc.v:76231.3-76282.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:74536.3-74587.6" + attribute \src "libresoc.v:75347.3-75398.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:74588.3-74639.6" + attribute \src "libresoc.v:75399.3-75450.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:75160.3-75211.6" + attribute \src "libresoc.v:75971.3-76022.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:75368.3-75419.6" + attribute \src "libresoc.v:76179.3-76230.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:75628.3-75679.6" + attribute \src "libresoc.v:76439.3-76490.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:74484.3-74535.6" - wire width 13 $0\dec19_function_unit[12:0] - attribute \src "libresoc.v:75940.3-75991.6" + attribute \src "libresoc.v:75295.3-75346.6" + wire width 14 $0\dec19_function_unit[13:0] + attribute \src "libresoc.v:76751.3-76802.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:75992.3-76043.6" + attribute \src "libresoc.v:76803.3-76854.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76044.3-76095.6" + attribute \src "libresoc.v:76855.3-76906.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:75056.3-75107.6" + attribute \src "libresoc.v:75867.3-75918.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:75264.3-75315.6" + attribute \src "libresoc.v:76075.3-76126.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:75316.3-75367.6" + attribute \src "libresoc.v:76127.3-76178.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:75576.3-75627.6" + attribute \src "libresoc.v:76387.3-76438.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:74952.3-75003.6" + attribute \src "libresoc.v:75763.3-75814.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:75732.3-75783.6" + attribute \src "libresoc.v:76543.3-76594.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:76096.3-76147.6" - wire width 2 $0\dec19_out_sel[1:0] - attribute \src "libresoc.v:75108.3-75159.6" + attribute \src "libresoc.v:76907.3-76958.6" + wire width 3 $0\dec19_out_sel[2:0] + attribute \src "libresoc.v:75919.3-75970.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:75524.3-75575.6" + attribute \src "libresoc.v:76335.3-76386.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:75784.3-75835.6" + attribute \src "libresoc.v:76595.3-76646.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:75680.3-75731.6" + attribute \src "libresoc.v:76491.3-76542.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:75472.3-75523.6" + attribute \src "libresoc.v:76283.3-76334.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:74848.3-74899.6" + attribute \src "libresoc.v:75659.3-75710.6" wire width 3 $0\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:74900.3-74951.6" + attribute \src "libresoc.v:75711.3-75762.6" wire width 3 $0\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:74640.3-74691.6" + attribute \src "libresoc.v:75451.3-75502.6" wire width 3 $0\dec19_sv_in1[2:0] - attribute \src "libresoc.v:74692.3-74743.6" + attribute \src "libresoc.v:75503.3-75554.6" wire width 3 $0\dec19_sv_in2[2:0] - attribute \src "libresoc.v:74744.3-74795.6" + attribute \src "libresoc.v:75555.3-75606.6" wire width 3 $0\dec19_sv_in3[2:0] - attribute \src "libresoc.v:74796.3-74847.6" + attribute \src "libresoc.v:75607.3-75658.6" wire width 3 $0\dec19_sv_out[2:0] - attribute \src "libresoc.v:75004.3-75055.6" + attribute \src "libresoc.v:75815.3-75866.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:74149.7-74149.20" + attribute \src "libresoc.v:74957.7-74957.20" wire $0\initial[0:0] - attribute \src "libresoc.v:75836.3-75887.6" + attribute \src "libresoc.v:76647.3-76698.6" wire width 2 $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:75888.3-75939.6" + attribute \src "libresoc.v:76699.3-76750.6" wire width 2 $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:75212.3-75263.6" + attribute \src "libresoc.v:76023.3-76074.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:75420.3-75471.6" + attribute \src "libresoc.v:76231.3-76282.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:74536.3-74587.6" + attribute \src "libresoc.v:75347.3-75398.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:74588.3-74639.6" + attribute \src "libresoc.v:75399.3-75450.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75160.3-75211.6" + attribute \src "libresoc.v:75971.3-76022.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:75368.3-75419.6" + attribute \src "libresoc.v:76179.3-76230.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:75628.3-75679.6" + attribute \src "libresoc.v:76439.3-76490.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:74484.3-74535.6" - wire width 13 $1\dec19_function_unit[12:0] - attribute \src "libresoc.v:75940.3-75991.6" + attribute \src "libresoc.v:75295.3-75346.6" + wire width 14 $1\dec19_function_unit[13:0] + attribute \src "libresoc.v:76751.3-76802.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:75992.3-76043.6" + attribute \src "libresoc.v:76803.3-76854.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76044.3-76095.6" + attribute \src "libresoc.v:76855.3-76906.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:75056.3-75107.6" + attribute \src "libresoc.v:75867.3-75918.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:75264.3-75315.6" + attribute \src "libresoc.v:76075.3-76126.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:75316.3-75367.6" + attribute \src "libresoc.v:76127.3-76178.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:75576.3-75627.6" + attribute \src "libresoc.v:76387.3-76438.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:74952.3-75003.6" + attribute \src "libresoc.v:75763.3-75814.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:75732.3-75783.6" + attribute \src "libresoc.v:76543.3-76594.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:76096.3-76147.6" - wire width 2 $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:75108.3-75159.6" + attribute \src "libresoc.v:76907.3-76958.6" + wire width 3 $1\dec19_out_sel[2:0] + attribute \src "libresoc.v:75919.3-75970.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:75524.3-75575.6" + attribute \src "libresoc.v:76335.3-76386.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:75784.3-75835.6" + attribute \src "libresoc.v:76595.3-76646.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:75680.3-75731.6" + attribute \src "libresoc.v:76491.3-76542.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:75472.3-75523.6" + attribute \src "libresoc.v:76283.3-76334.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:74848.3-74899.6" + attribute \src "libresoc.v:75659.3-75710.6" wire width 3 $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:74900.3-74951.6" + attribute \src "libresoc.v:75711.3-75762.6" wire width 3 $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:74640.3-74691.6" + attribute \src "libresoc.v:75451.3-75502.6" wire width 3 $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:74692.3-74743.6" + attribute \src "libresoc.v:75503.3-75554.6" wire width 3 $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:74744.3-74795.6" + attribute \src "libresoc.v:75555.3-75606.6" wire width 3 $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:74796.3-74847.6" + attribute \src "libresoc.v:75607.3-75658.6" wire width 3 $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75004.3-75055.6" + attribute \src "libresoc.v:75815.3-75866.6" wire width 2 $1\dec19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -119148,21 +119990,22 @@ module \dec19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec19_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -119268,6 +120111,7 @@ module \dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -119287,12 +120131,13 @@ module \dec19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec19_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec19_out_sel + wire width 3 output 10 \dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -119368,28 +120213,28 @@ module \dec19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec19_upd - attribute \src "libresoc.v:74149.7-74149.15" + attribute \src "libresoc.v:74957.7-74957.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:74149.7-74149.20" - process $proc$libresoc.v:74149$3619 + attribute \src "libresoc.v:74957.7-74957.20" + process $proc$libresoc.v:74957$3619 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:74484.3-74535.6" - process $proc$libresoc.v:74484$3587 + attribute \src "libresoc.v:75295.3-75346.6" + process $proc$libresoc.v:75295$3587 assign { } { } assign { } { } - assign $0\dec19_function_unit[12:0] $1\dec19_function_unit[12:0] - attribute \src "libresoc.v:74485.5-74485.29" + assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] + attribute \src "libresoc.v:75296.5-75296.29" switch \initial - attribute \src "libresoc.v:74485.9-74485.17" + attribute \src "libresoc.v:75296.9-75296.17" case 1'1 case end @@ -119398,77 +120243,77 @@ module \dec19 attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000001000000 + assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000000100000 + assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000000100000 + assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000000100000 + assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000000000010 + assign $1\dec19_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000010000000 + assign $1\dec19_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_function_unit[12:0] 13'0000010000000 + assign $1\dec19_function_unit[13:0] 14'00000010000000 case - assign $1\dec19_function_unit[12:0] 13'0000000000000 + assign $1\dec19_function_unit[13:0] 14'00000000000000 end sync always - update \dec19_function_unit $0\dec19_function_unit[12:0] + update \dec19_function_unit $0\dec19_function_unit[13:0] end - attribute \src "libresoc.v:74536.3-74587.6" - process $proc$libresoc.v:74536$3588 + attribute \src "libresoc.v:75347.3-75398.6" + process $proc$libresoc.v:75347$3588 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:74537.5-74537.29" + attribute \src "libresoc.v:75348.5-75348.29" switch \initial - attribute \src "libresoc.v:74537.9-74537.17" + attribute \src "libresoc.v:75348.9-75348.17" case 1'1 case end @@ -119540,14 +120385,14 @@ module \dec19 sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:74588.3-74639.6" - process $proc$libresoc.v:74588$3589 + attribute \src "libresoc.v:75399.3-75450.6" + process $proc$libresoc.v:75399$3589 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:74589.5-74589.29" + attribute \src "libresoc.v:75400.5-75400.29" switch \initial - attribute \src "libresoc.v:74589.9-74589.17" + attribute \src "libresoc.v:75400.9-75400.17" case 1'1 case end @@ -119619,14 +120464,14 @@ module \dec19 sync always update \dec19_cr_out $0\dec19_cr_out[2:0] end - attribute \src "libresoc.v:74640.3-74691.6" - process $proc$libresoc.v:74640$3590 + attribute \src "libresoc.v:75451.3-75502.6" + process $proc$libresoc.v:75451$3590 assign { } { } assign { } { } assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:74641.5-74641.29" + attribute \src "libresoc.v:75452.5-75452.29" switch \initial - attribute \src "libresoc.v:74641.9-74641.17" + attribute \src "libresoc.v:75452.9-75452.17" case 1'1 case end @@ -119698,14 +120543,14 @@ module \dec19 sync always update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end - attribute \src "libresoc.v:74692.3-74743.6" - process $proc$libresoc.v:74692$3591 + attribute \src "libresoc.v:75503.3-75554.6" + process $proc$libresoc.v:75503$3591 assign { } { } assign { } { } assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:74693.5-74693.29" + attribute \src "libresoc.v:75504.5-75504.29" switch \initial - attribute \src "libresoc.v:74693.9-74693.17" + attribute \src "libresoc.v:75504.9-75504.17" case 1'1 case end @@ -119777,14 +120622,14 @@ module \dec19 sync always update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end - attribute \src "libresoc.v:74744.3-74795.6" - process $proc$libresoc.v:74744$3592 + attribute \src "libresoc.v:75555.3-75606.6" + process $proc$libresoc.v:75555$3592 assign { } { } assign { } { } assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:74745.5-74745.29" + attribute \src "libresoc.v:75556.5-75556.29" switch \initial - attribute \src "libresoc.v:74745.9-74745.17" + attribute \src "libresoc.v:75556.9-75556.17" case 1'1 case end @@ -119856,14 +120701,14 @@ module \dec19 sync always update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end - attribute \src "libresoc.v:74796.3-74847.6" - process $proc$libresoc.v:74796$3593 + attribute \src "libresoc.v:75607.3-75658.6" + process $proc$libresoc.v:75607$3593 assign { } { } assign { } { } assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:74797.5-74797.29" + attribute \src "libresoc.v:75608.5-75608.29" switch \initial - attribute \src "libresoc.v:74797.9-74797.17" + attribute \src "libresoc.v:75608.9-75608.17" case 1'1 case end @@ -119935,14 +120780,14 @@ module \dec19 sync always update \dec19_sv_out $0\dec19_sv_out[2:0] end - attribute \src "libresoc.v:74848.3-74899.6" - process $proc$libresoc.v:74848$3594 + attribute \src "libresoc.v:75659.3-75710.6" + process $proc$libresoc.v:75659$3594 assign { } { } assign { } { } assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:74849.5-74849.29" + attribute \src "libresoc.v:75660.5-75660.29" switch \initial - attribute \src "libresoc.v:74849.9-74849.17" + attribute \src "libresoc.v:75660.9-75660.17" case 1'1 case end @@ -120014,14 +120859,14 @@ module \dec19 sync always update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end - attribute \src "libresoc.v:74900.3-74951.6" - process $proc$libresoc.v:74900$3595 + attribute \src "libresoc.v:75711.3-75762.6" + process $proc$libresoc.v:75711$3595 assign { } { } assign { } { } assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:74901.5-74901.29" + attribute \src "libresoc.v:75712.5-75712.29" switch \initial - attribute \src "libresoc.v:74901.9-74901.17" + attribute \src "libresoc.v:75712.9-75712.17" case 1'1 case end @@ -120093,14 +120938,14 @@ module \dec19 sync always update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end - attribute \src "libresoc.v:74952.3-75003.6" - process $proc$libresoc.v:74952$3596 + attribute \src "libresoc.v:75763.3-75814.6" + process $proc$libresoc.v:75763$3596 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:74953.5-74953.29" + attribute \src "libresoc.v:75764.5-75764.29" switch \initial - attribute \src "libresoc.v:74953.9-74953.17" + attribute \src "libresoc.v:75764.9-75764.17" case 1'1 case end @@ -120172,14 +121017,14 @@ module \dec19 sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:75004.3-75055.6" - process $proc$libresoc.v:75004$3597 + attribute \src "libresoc.v:75815.3-75866.6" + process $proc$libresoc.v:75815$3597 assign { } { } assign { } { } assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:75005.5-75005.29" + attribute \src "libresoc.v:75816.5-75816.29" switch \initial - attribute \src "libresoc.v:75005.9-75005.17" + attribute \src "libresoc.v:75816.9-75816.17" case 1'1 case end @@ -120251,14 +121096,14 @@ module \dec19 sync always update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:75056.3-75107.6" - process $proc$libresoc.v:75056$3598 + attribute \src "libresoc.v:75867.3-75918.6" + process $proc$libresoc.v:75867$3598 assign { } { } assign { } { } assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:75057.5-75057.29" + attribute \src "libresoc.v:75868.5-75868.29" switch \initial - attribute \src "libresoc.v:75057.9-75057.17" + attribute \src "libresoc.v:75868.9-75868.17" case 1'1 case end @@ -120330,14 +121175,14 @@ module \dec19 sync always update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:75108.3-75159.6" - process $proc$libresoc.v:75108$3599 + attribute \src "libresoc.v:75919.3-75970.6" + process $proc$libresoc.v:75919$3599 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:75109.5-75109.29" + attribute \src "libresoc.v:75920.5-75920.29" switch \initial - attribute \src "libresoc.v:75109.9-75109.17" + attribute \src "libresoc.v:75920.9-75920.17" case 1'1 case end @@ -120409,14 +121254,14 @@ module \dec19 sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:75160.3-75211.6" - process $proc$libresoc.v:75160$3600 + attribute \src "libresoc.v:75971.3-76022.6" + process $proc$libresoc.v:75971$3600 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:75161.5-75161.29" + attribute \src "libresoc.v:75972.5-75972.29" switch \initial - attribute \src "libresoc.v:75161.9-75161.17" + attribute \src "libresoc.v:75972.9-75972.17" case 1'1 case end @@ -120488,14 +121333,14 @@ module \dec19 sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:75212.3-75263.6" - process $proc$libresoc.v:75212$3601 + attribute \src "libresoc.v:76023.3-76074.6" + process $proc$libresoc.v:76023$3601 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:75213.5-75213.29" + attribute \src "libresoc.v:76024.5-76024.29" switch \initial - attribute \src "libresoc.v:75213.9-75213.17" + attribute \src "libresoc.v:76024.9-76024.17" case 1'1 case end @@ -120567,14 +121412,14 @@ module \dec19 sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:75264.3-75315.6" - process $proc$libresoc.v:75264$3602 + attribute \src "libresoc.v:76075.3-76126.6" + process $proc$libresoc.v:76075$3602 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:75265.5-75265.29" + attribute \src "libresoc.v:76076.5-76076.29" switch \initial - attribute \src "libresoc.v:75265.9-75265.17" + attribute \src "libresoc.v:76076.9-76076.17" case 1'1 case end @@ -120646,14 +121491,14 @@ module \dec19 sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:75316.3-75367.6" - process $proc$libresoc.v:75316$3603 + attribute \src "libresoc.v:76127.3-76178.6" + process $proc$libresoc.v:76127$3603 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:75317.5-75317.29" + attribute \src "libresoc.v:76128.5-76128.29" switch \initial - attribute \src "libresoc.v:75317.9-75317.17" + attribute \src "libresoc.v:76128.9-76128.17" case 1'1 case end @@ -120725,14 +121570,14 @@ module \dec19 sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:75368.3-75419.6" - process $proc$libresoc.v:75368$3604 + attribute \src "libresoc.v:76179.3-76230.6" + process $proc$libresoc.v:76179$3604 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:75369.5-75369.29" + attribute \src "libresoc.v:76180.5-76180.29" switch \initial - attribute \src "libresoc.v:75369.9-75369.17" + attribute \src "libresoc.v:76180.9-76180.17" case 1'1 case end @@ -120804,14 +121649,14 @@ module \dec19 sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:75420.3-75471.6" - process $proc$libresoc.v:75420$3605 + attribute \src "libresoc.v:76231.3-76282.6" + process $proc$libresoc.v:76231$3605 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:75421.5-75421.29" + attribute \src "libresoc.v:76232.5-76232.29" switch \initial - attribute \src "libresoc.v:75421.9-75421.17" + attribute \src "libresoc.v:76232.9-76232.17" case 1'1 case end @@ -120883,14 +121728,14 @@ module \dec19 sync always update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:75472.3-75523.6" - process $proc$libresoc.v:75472$3606 + attribute \src "libresoc.v:76283.3-76334.6" + process $proc$libresoc.v:76283$3606 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75473.5-75473.29" + attribute \src "libresoc.v:76284.5-76284.29" switch \initial - attribute \src "libresoc.v:75473.9-75473.17" + attribute \src "libresoc.v:76284.9-76284.17" case 1'1 case end @@ -120962,14 +121807,14 @@ module \dec19 sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "libresoc.v:75524.3-75575.6" - process $proc$libresoc.v:75524$3607 + attribute \src "libresoc.v:76335.3-76386.6" + process $proc$libresoc.v:76335$3607 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:75525.5-75525.29" + attribute \src "libresoc.v:76336.5-76336.29" switch \initial - attribute \src "libresoc.v:75525.9-75525.17" + attribute \src "libresoc.v:76336.9-76336.17" case 1'1 case end @@ -121041,14 +121886,14 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:75576.3-75627.6" - process $proc$libresoc.v:75576$3608 + attribute \src "libresoc.v:76387.3-76438.6" + process $proc$libresoc.v:76387$3608 assign { } { } assign { } { } assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:75577.5-75577.29" + attribute \src "libresoc.v:76388.5-76388.29" switch \initial - attribute \src "libresoc.v:75577.9-75577.17" + attribute \src "libresoc.v:76388.9-76388.17" case 1'1 case end @@ -121120,14 +121965,14 @@ module \dec19 sync always update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:75628.3-75679.6" - process $proc$libresoc.v:75628$3609 + attribute \src "libresoc.v:76439.3-76490.6" + process $proc$libresoc.v:76439$3609 assign { } { } assign { } { } assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:75629.5-75629.29" + attribute \src "libresoc.v:76440.5-76440.29" switch \initial - attribute \src "libresoc.v:75629.9-75629.17" + attribute \src "libresoc.v:76440.9-76440.17" case 1'1 case end @@ -121199,14 +122044,14 @@ module \dec19 sync always update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:75680.3-75731.6" - process $proc$libresoc.v:75680$3610 + attribute \src "libresoc.v:76491.3-76542.6" + process $proc$libresoc.v:76491$3610 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:75681.5-75681.29" + attribute \src "libresoc.v:76492.5-76492.29" switch \initial - attribute \src "libresoc.v:75681.9-75681.17" + attribute \src "libresoc.v:76492.9-76492.17" case 1'1 case end @@ -121278,14 +122123,14 @@ module \dec19 sync always update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:75732.3-75783.6" - process $proc$libresoc.v:75732$3611 + attribute \src "libresoc.v:76543.3-76594.6" + process $proc$libresoc.v:76543$3611 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:75733.5-75733.29" + attribute \src "libresoc.v:76544.5-76544.29" switch \initial - attribute \src "libresoc.v:75733.9-75733.17" + attribute \src "libresoc.v:76544.9-76544.17" case 1'1 case end @@ -121357,14 +122202,14 @@ module \dec19 sync always update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:75784.3-75835.6" - process $proc$libresoc.v:75784$3612 + attribute \src "libresoc.v:76595.3-76646.6" + process $proc$libresoc.v:76595$3612 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:75785.5-75785.29" + attribute \src "libresoc.v:76596.5-76596.29" switch \initial - attribute \src "libresoc.v:75785.9-75785.17" + attribute \src "libresoc.v:76596.9-76596.17" case 1'1 case end @@ -121436,14 +122281,14 @@ module \dec19 sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:75836.3-75887.6" - process $proc$libresoc.v:75836$3613 + attribute \src "libresoc.v:76647.3-76698.6" + process $proc$libresoc.v:76647$3613 assign { } { } assign { } { } assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:75837.5-75837.29" + attribute \src "libresoc.v:76648.5-76648.29" switch \initial - attribute \src "libresoc.v:75837.9-75837.17" + attribute \src "libresoc.v:76648.9-76648.17" case 1'1 case end @@ -121515,14 +122360,14 @@ module \dec19 sync always update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end - attribute \src "libresoc.v:75888.3-75939.6" - process $proc$libresoc.v:75888$3614 + attribute \src "libresoc.v:76699.3-76750.6" + process $proc$libresoc.v:76699$3614 assign { } { } assign { } { } assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:75889.5-75889.29" + attribute \src "libresoc.v:76700.5-76700.29" switch \initial - attribute \src "libresoc.v:75889.9-75889.17" + attribute \src "libresoc.v:76700.9-76700.17" case 1'1 case end @@ -121594,14 +122439,14 @@ module \dec19 sync always update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end - attribute \src "libresoc.v:75940.3-75991.6" - process $proc$libresoc.v:75940$3615 + attribute \src "libresoc.v:76751.3-76802.6" + process $proc$libresoc.v:76751$3615 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:75941.5-75941.29" + attribute \src "libresoc.v:76752.5-76752.29" switch \initial - attribute \src "libresoc.v:75941.9-75941.17" + attribute \src "libresoc.v:76752.9-76752.17" case 1'1 case end @@ -121673,14 +122518,14 @@ module \dec19 sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:75992.3-76043.6" - process $proc$libresoc.v:75992$3616 + attribute \src "libresoc.v:76803.3-76854.6" + process $proc$libresoc.v:76803$3616 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:75993.5-75993.29" + attribute \src "libresoc.v:76804.5-76804.29" switch \initial - attribute \src "libresoc.v:75993.9-75993.17" + attribute \src "libresoc.v:76804.9-76804.17" case 1'1 case end @@ -121752,14 +122597,14 @@ module \dec19 sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:76044.3-76095.6" - process $proc$libresoc.v:76044$3617 + attribute \src "libresoc.v:76855.3-76906.6" + process $proc$libresoc.v:76855$3617 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76045.5-76045.29" + attribute \src "libresoc.v:76856.5-76856.29" switch \initial - attribute \src "libresoc.v:76045.9-76045.17" + attribute \src "libresoc.v:76856.9-76856.17" case 1'1 case end @@ -121831,14 +122676,14 @@ module \dec19 sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:76096.3-76147.6" - process $proc$libresoc.v:76096$3618 + attribute \src "libresoc.v:76907.3-76958.6" + process $proc$libresoc.v:76907$3618 assign { } { } assign { } { } - assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:76097.5-76097.29" + assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] + attribute \src "libresoc.v:76908.5-76908.29" switch \initial - attribute \src "libresoc.v:76097.9-76097.17" + attribute \src "libresoc.v:76908.9-76908.17" case 1'1 case end @@ -121847,897 +122692,897 @@ module \dec19 attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 + assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 case - assign $1\dec19_out_sel[1:0] 2'00 + assign $1\dec19_out_sel[2:0] 3'000 end sync always - update \dec19_out_sel $0\dec19_out_sel[1:0] + update \dec19_out_sel $0\dec19_out_sel[2:0] end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:76153.1-78359.10" +attribute \src "libresoc.v:76964.1-79185.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\cr_in1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\cr_in2$1[6:0]$3680 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\cr_in2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_in2_ok$2[0:0]$3681 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\ea[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\exc_$signal$3[0:0]$3683 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\exc_$signal$4[0:0]$3684 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\exc_$signal$5[0:0]$3685 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\exc_$signal$6[0:0]$3686 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\exc_$signal$7[0:0]$3687 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\exc_$signal$8[0:0]$3688 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\exc_$signal$9[0:0]$3689 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\exc_$signal[0:0]$3682 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" - wire width 13 $0\fn_unit[12:0] - attribute \src "libresoc.v:76154.7-76154.20" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $0\fn_unit[13:0] + attribute \src "libresoc.v:76965.7-76965.20" wire $0\initial[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:78099.3-78122.6" + attribute \src "libresoc.v:78924.3-78947.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\lk[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\oe[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\rc[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\reg1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\reg2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\reg3[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $0\rego[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:78025.3-78039.6" - wire width 13 $0\tmp_tmp_fn_unit[12:0] - attribute \src "libresoc.v:78050.3-78062.6" + attribute \src "libresoc.v:78850.3-78864.6" + wire width 14 $0\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:78875.3-78887.6" wire width 7 $0\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78040.3-78049.6" + attribute \src "libresoc.v:78865.3-78874.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78089.3-78098.6" + attribute \src "libresoc.v:78914.3-78923.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78063.3-78078.6" + attribute \src "libresoc.v:78888.3-78903.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:78079.3-78088.6" + attribute \src "libresoc.v:78904.3-78913.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\cr_in1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\cr_in2$1[6:0]$3690 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\cr_in2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_in2_ok$2[0:0]$3691 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\ea[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\exc_$signal$3[0:0]$3693 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\exc_$signal$4[0:0]$3694 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\exc_$signal$5[0:0]$3695 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\exc_$signal$6[0:0]$3696 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\exc_$signal$7[0:0]$3697 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\exc_$signal$8[0:0]$3698 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\exc_$signal$9[0:0]$3699 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\exc_$signal[0:0]$3692 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" - wire width 13 $1\fn_unit[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $1\fn_unit[13:0] + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:78099.3-78122.6" + attribute \src "libresoc.v:78924.3-78947.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\lk[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\oe[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\rc[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\reg1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\reg2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\reg3[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $1\rego[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:78025.3-78039.6" - wire width 13 $1\tmp_tmp_fn_unit[12:0] - attribute \src "libresoc.v:78050.3-78062.6" + attribute \src "libresoc.v:78850.3-78864.6" + wire width 14 $1\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:78875.3-78887.6" wire width 7 $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78040.3-78049.6" + attribute \src "libresoc.v:78865.3-78874.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78089.3-78098.6" + attribute \src "libresoc.v:78914.3-78923.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78063.3-78078.6" + attribute \src "libresoc.v:78888.3-78903.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:78079.3-78088.6" + attribute \src "libresoc.v:78904.3-78913.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\cr_in1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\cr_in2$1[6:0]$3700 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\cr_in2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_in2_ok$2[0:0]$3701 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\cr_out[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\ea[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\ea_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\exc_$signal$3[0:0]$3703 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\exc_$signal$4[0:0]$3704 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\exc_$signal$5[0:0]$3705 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\exc_$signal$6[0:0]$3706 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\exc_$signal$7[0:0]$3707 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\exc_$signal$8[0:0]$3708 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\exc_$signal$9[0:0]$3709 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\exc_$signal[0:0]$3702 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" - wire width 13 $2\fn_unit[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $2\fn_unit[13:0] + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\is_32bit[0:0] - attribute \src "libresoc.v:78099.3-78122.6" + attribute \src "libresoc.v:78924.3-78947.6" wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\lk[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\oe[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\oe_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\rc[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\rc_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\reg1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\reg2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\reg3[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $2\rego[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\rego_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\spro_ok[0:0] - attribute \src "libresoc.v:78063.3-78078.6" + attribute \src "libresoc.v:78888.3-78903.6" wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $2\xer_out[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\cr_in1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\cr_in2$1[6:0]$3710 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\cr_in2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_in2_ok$2[0:0]$3711 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\cr_out[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\ea[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\ea_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\exc_$signal$3[0:0]$3713 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\exc_$signal$4[0:0]$3714 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\exc_$signal$5[0:0]$3715 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\exc_$signal$6[0:0]$3716 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\exc_$signal$7[0:0]$3717 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\exc_$signal$8[0:0]$3718 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\exc_$signal$9[0:0]$3719 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\exc_$signal[0:0]$3712 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" - wire width 13 $3\fn_unit[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $3\fn_unit[13:0] + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\is_32bit[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\lk[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\oe[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\oe_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\rc[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\rc_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\reg1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\reg2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\reg3[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $3\rego[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\rego_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\spro_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $3\xer_out[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $4\asmcode[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $4\cia[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\cr_in1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_in1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\cr_in2$1[6:0]$3720 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\cr_in2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_in2_ok$2[0:0]$3721 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_in2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\cr_out[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_out_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $4\cr_rd[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_rd_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $4\cr_wr[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\cr_wr_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\ea[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\ea_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\exc_$signal$3[0:0]$3723 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\exc_$signal$4[0:0]$3724 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\exc_$signal$5[0:0]$3725 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\exc_$signal$6[0:0]$3726 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\exc_$signal$7[0:0]$3727 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\exc_$signal$8[0:0]$3728 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\exc_$signal$9[0:0]$3729 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\exc_$signal[0:0]$3722 - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\fast1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\fast1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\fast2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\fast2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\fasto1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\fasto1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\fasto2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\fasto2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" - wire width 13 $4\fn_unit[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" + wire width 14 $4\fn_unit[13:0] + attribute \src "libresoc.v:78948.3-79105.6" wire width 2 $4\input_carry[1:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 32 $4\insn[31:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\insn_type[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\is_32bit[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\lk[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 64 $4\msr[63:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\oe[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\oe_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\rc[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\rc_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\reg1[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\reg1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\reg2[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\reg2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\reg3[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\reg3_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 7 $4\rego[6:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\rego_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $4\spr1[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\spr1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 10 $4\spro[9:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\spro_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 13 $4\trapaddr[12:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 8 $4\traptype[7:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $4\xer_in[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $4\xer_out[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $5\fast1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $5\fast1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $5\fast2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $5\fast2_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $5\fasto1[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $5\fasto1_ok[0:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire width 3 $5\fasto2[2:0] - attribute \src "libresoc.v:78123.3-78280.6" + attribute \src "libresoc.v:78948.3-79105.6" wire $5\fasto2_ok[0:0] - attribute \src "libresoc.v:77847.19-77847.122" - wire $and$libresoc.v:77847$3630_Y - attribute \src "libresoc.v:77848.19-77848.125" - wire $and$libresoc.v:77848$3631_Y - attribute \src "libresoc.v:77849.19-77849.126" - wire $and$libresoc.v:77849$3632_Y - attribute \src "libresoc.v:77856.18-77856.114" - wire $and$libresoc.v:77856$3639_Y - attribute \src "libresoc.v:77857.18-77857.116" - wire $and$libresoc.v:77857$3640_Y - attribute \src "libresoc.v:77859.18-77859.114" - wire $and$libresoc.v:77859$3642_Y - attribute \src "libresoc.v:77861.18-77861.110" - wire $and$libresoc.v:77861$3644_Y - attribute \src "libresoc.v:77873.18-77873.114" - wire $and$libresoc.v:77873$3656_Y - attribute \src "libresoc.v:77874.18-77874.116" - wire $and$libresoc.v:77874$3657_Y - attribute \src "libresoc.v:77876.18-77876.114" - wire $and$libresoc.v:77876$3659_Y - attribute \src "libresoc.v:77878.18-77878.110" - wire $and$libresoc.v:77878$3661_Y - attribute \src "libresoc.v:77843.19-77843.124" - wire $eq$libresoc.v:77843$3626_Y - attribute \src "libresoc.v:77844.19-77844.124" - wire $eq$libresoc.v:77844$3627_Y - attribute \src "libresoc.v:77845.19-77845.124" - wire $eq$libresoc.v:77845$3628_Y - attribute \src "libresoc.v:77846.19-77846.124" - wire $eq$libresoc.v:77846$3629_Y - attribute \src "libresoc.v:77850.19-77850.124" - wire $eq$libresoc.v:77850$3633_Y - attribute \src "libresoc.v:77851.18-77851.117" - wire $eq$libresoc.v:77851$3634_Y - attribute \src "libresoc.v:77852.18-77852.117" - wire $eq$libresoc.v:77852$3635_Y - attribute \src "libresoc.v:77854.18-77854.117" - wire $eq$libresoc.v:77854$3637_Y - attribute \src "libresoc.v:77855.18-77855.127" - wire $eq$libresoc.v:77855$3638_Y - attribute \src "libresoc.v:77858.18-77858.127" - wire $eq$libresoc.v:77858$3641_Y - attribute \src "libresoc.v:77862.18-77862.122" - wire $eq$libresoc.v:77862$3645_Y - attribute \src "libresoc.v:77863.18-77863.122" - wire $eq$libresoc.v:77863$3646_Y - attribute \src "libresoc.v:77865.18-77865.110" - wire $eq$libresoc.v:77865$3648_Y - attribute \src "libresoc.v:77866.18-77866.110" - wire $eq$libresoc.v:77866$3649_Y - attribute \src "libresoc.v:77868.18-77868.112" - wire $eq$libresoc.v:77868$3651_Y - attribute \src "libresoc.v:77870.18-77870.110" - wire $eq$libresoc.v:77870$3653_Y - attribute \src "libresoc.v:77872.18-77872.127" - wire $eq$libresoc.v:77872$3655_Y - attribute \src "libresoc.v:77875.18-77875.127" - wire $eq$libresoc.v:77875$3658_Y - attribute \src "libresoc.v:77840.19-77840.124" - wire width 7 $extend$libresoc.v:77840$3620_Y - attribute \src "libresoc.v:77841.19-77841.124" - wire width 7 $extend$libresoc.v:77841$3622_Y - attribute \src "libresoc.v:77842.19-77842.123" - wire width 7 $extend$libresoc.v:77842$3624_Y - attribute \src "libresoc.v:77879.18-77879.111" - wire width 7 $extend$libresoc.v:77879$3662_Y - attribute \src "libresoc.v:77880.18-77880.111" - wire width 7 $extend$libresoc.v:77880$3664_Y - attribute \src "libresoc.v:77881.18-77881.111" - wire width 7 $extend$libresoc.v:77881$3666_Y - attribute \src "libresoc.v:77882.18-77882.113" - wire width 7 $extend$libresoc.v:77882$3668_Y - attribute \src "libresoc.v:77883.18-77883.121" - wire width 7 $extend$libresoc.v:77883$3670_Y - attribute \src "libresoc.v:77860.18-77860.110" - wire $not$libresoc.v:77860$3643_Y - attribute \src "libresoc.v:77877.18-77877.110" - wire $not$libresoc.v:77877$3660_Y - attribute \src "libresoc.v:77853.18-77853.111" - wire $or$libresoc.v:77853$3636_Y - attribute \src "libresoc.v:77864.18-77864.110" - wire $or$libresoc.v:77864$3647_Y - attribute \src "libresoc.v:77867.18-77867.110" - wire $or$libresoc.v:77867$3650_Y - attribute \src "libresoc.v:77869.18-77869.110" - wire $or$libresoc.v:77869$3652_Y - attribute \src "libresoc.v:77871.18-77871.110" - wire $or$libresoc.v:77871$3654_Y - attribute \src "libresoc.v:77840.19-77840.124" - wire width 7 $pos$libresoc.v:77840$3621_Y - attribute \src "libresoc.v:77841.19-77841.124" - wire width 7 $pos$libresoc.v:77841$3623_Y - attribute \src "libresoc.v:77842.19-77842.123" - wire width 7 $pos$libresoc.v:77842$3625_Y - attribute \src "libresoc.v:77879.18-77879.111" - wire width 7 $pos$libresoc.v:77879$3663_Y - attribute \src "libresoc.v:77880.18-77880.111" - wire width 7 $pos$libresoc.v:77880$3665_Y - attribute \src "libresoc.v:77881.18-77881.111" - wire width 7 $pos$libresoc.v:77881$3667_Y - attribute \src "libresoc.v:77882.18-77882.113" - wire width 7 $pos$libresoc.v:77882$3669_Y - attribute \src "libresoc.v:77883.18-77883.121" - wire width 7 $pos$libresoc.v:77883$3671_Y + attribute \src "libresoc.v:78671.19-78671.122" + wire $and$libresoc.v:78671$3630_Y + attribute \src "libresoc.v:78672.19-78672.125" + wire $and$libresoc.v:78672$3631_Y + attribute \src "libresoc.v:78673.19-78673.126" + wire $and$libresoc.v:78673$3632_Y + attribute \src "libresoc.v:78680.18-78680.114" + wire $and$libresoc.v:78680$3639_Y + attribute \src "libresoc.v:78681.18-78681.116" + wire $and$libresoc.v:78681$3640_Y + attribute \src "libresoc.v:78683.18-78683.114" + wire $and$libresoc.v:78683$3642_Y + attribute \src "libresoc.v:78685.18-78685.110" + wire $and$libresoc.v:78685$3644_Y + attribute \src "libresoc.v:78697.18-78697.114" + wire $and$libresoc.v:78697$3656_Y + attribute \src "libresoc.v:78698.18-78698.116" + wire $and$libresoc.v:78698$3657_Y + attribute \src "libresoc.v:78700.18-78700.114" + wire $and$libresoc.v:78700$3659_Y + attribute \src "libresoc.v:78702.18-78702.110" + wire $and$libresoc.v:78702$3661_Y + attribute \src "libresoc.v:78667.19-78667.124" + wire $eq$libresoc.v:78667$3626_Y + attribute \src "libresoc.v:78668.19-78668.124" + wire $eq$libresoc.v:78668$3627_Y + attribute \src "libresoc.v:78669.19-78669.124" + wire $eq$libresoc.v:78669$3628_Y + attribute \src "libresoc.v:78670.19-78670.124" + wire $eq$libresoc.v:78670$3629_Y + attribute \src "libresoc.v:78674.19-78674.124" + wire $eq$libresoc.v:78674$3633_Y + attribute \src "libresoc.v:78675.18-78675.117" + wire $eq$libresoc.v:78675$3634_Y + attribute \src "libresoc.v:78676.18-78676.117" + wire $eq$libresoc.v:78676$3635_Y + attribute \src "libresoc.v:78678.18-78678.117" + wire $eq$libresoc.v:78678$3637_Y + attribute \src "libresoc.v:78679.18-78679.127" + wire $eq$libresoc.v:78679$3638_Y + attribute \src "libresoc.v:78682.18-78682.127" + wire $eq$libresoc.v:78682$3641_Y + attribute \src "libresoc.v:78686.18-78686.122" + wire $eq$libresoc.v:78686$3645_Y + attribute \src "libresoc.v:78687.18-78687.122" + wire $eq$libresoc.v:78687$3646_Y + attribute \src "libresoc.v:78689.18-78689.110" + wire $eq$libresoc.v:78689$3648_Y + attribute \src "libresoc.v:78690.18-78690.110" + wire $eq$libresoc.v:78690$3649_Y + attribute \src "libresoc.v:78692.18-78692.112" + wire $eq$libresoc.v:78692$3651_Y + attribute \src "libresoc.v:78694.18-78694.110" + wire $eq$libresoc.v:78694$3653_Y + attribute \src "libresoc.v:78696.18-78696.127" + wire $eq$libresoc.v:78696$3655_Y + attribute \src "libresoc.v:78699.18-78699.127" + wire $eq$libresoc.v:78699$3658_Y + attribute \src "libresoc.v:78664.19-78664.124" + wire width 7 $extend$libresoc.v:78664$3620_Y + attribute \src "libresoc.v:78665.19-78665.124" + wire width 7 $extend$libresoc.v:78665$3622_Y + attribute \src "libresoc.v:78666.19-78666.123" + wire width 7 $extend$libresoc.v:78666$3624_Y + attribute \src "libresoc.v:78703.18-78703.111" + wire width 7 $extend$libresoc.v:78703$3662_Y + attribute \src "libresoc.v:78704.18-78704.111" + wire width 7 $extend$libresoc.v:78704$3664_Y + attribute \src "libresoc.v:78705.18-78705.111" + wire width 7 $extend$libresoc.v:78705$3666_Y + attribute \src "libresoc.v:78706.18-78706.113" + wire width 7 $extend$libresoc.v:78706$3668_Y + attribute \src "libresoc.v:78707.18-78707.121" + wire width 7 $extend$libresoc.v:78707$3670_Y + attribute \src "libresoc.v:78684.18-78684.110" + wire $not$libresoc.v:78684$3643_Y + attribute \src "libresoc.v:78701.18-78701.110" + wire $not$libresoc.v:78701$3660_Y + attribute \src "libresoc.v:78677.18-78677.111" + wire $or$libresoc.v:78677$3636_Y + attribute \src "libresoc.v:78688.18-78688.110" + wire $or$libresoc.v:78688$3647_Y + attribute \src "libresoc.v:78691.18-78691.110" + wire $or$libresoc.v:78691$3650_Y + attribute \src "libresoc.v:78693.18-78693.110" + wire $or$libresoc.v:78693$3652_Y + attribute \src "libresoc.v:78695.18-78695.110" + wire $or$libresoc.v:78695$3654_Y + attribute \src "libresoc.v:78664.19-78664.124" + wire width 7 $pos$libresoc.v:78664$3621_Y + attribute \src "libresoc.v:78665.19-78665.124" + wire width 7 $pos$libresoc.v:78665$3623_Y + attribute \src "libresoc.v:78666.19-78666.123" + wire width 7 $pos$libresoc.v:78666$3625_Y + attribute \src "libresoc.v:78703.18-78703.111" + wire width 7 $pos$libresoc.v:78703$3663_Y + attribute \src "libresoc.v:78704.18-78704.111" + wire width 7 $pos$libresoc.v:78704$3665_Y + attribute \src "libresoc.v:78705.18-78705.111" + wire width 7 $pos$libresoc.v:78705$3667_Y + attribute \src "libresoc.v:78706.18-78706.113" + wire width 7 $pos$libresoc.v:78706$3669_Y + attribute \src "libresoc.v:78707.18-78707.121" + wire width 7 $pos$libresoc.v:78707$3671_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1146" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1203" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1228" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1253" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$90 @@ -122782,7 +123627,7 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 input 64 \cur_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" - wire input 65 \cur_eint + wire input 66 \cur_eint attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 input 3 \cur_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" @@ -122975,6 +123820,8 @@ module \dec2 wire width 10 \dec_a_spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_a_spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + wire \dec_a_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 8 \dec_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -123000,7 +123847,7 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_c_reg_c @@ -123010,7 +123857,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298" wire width 2 \dec_c_sel_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123039,7 +123886,7 @@ module \dec2 wire width 8 \dec_cr_in_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123050,7 +123897,7 @@ module \dec2 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:516" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520" wire width 3 \dec_cr_in_sel_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123069,9 +123916,9 @@ module \dec2 wire width 8 \dec_cr_out_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123080,7 +123927,7 @@ module \dec2 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:591" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -123089,21 +123936,22 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_cry_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -123209,9 +124057,10 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" wire \dec_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_is_32b @@ -123221,7 +124070,7 @@ module \dec2 wire width 3 \dec_o2_fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o2_fast_o2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" wire \dec_o2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_o2_reg_o2 @@ -123236,12 +124085,13 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o_reg_o_ok attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - wire width 2 \dec_o_sel_in + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 3 \dec_o_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -123368,17 +124218,18 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec_out_sel + wire width 3 \dec_out_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -123393,7 +124244,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" @@ -123422,7 +124273,7 @@ module \dec2 wire output 56 \exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 57 \exc_$signal$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1196" wire \ext_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 22 \fast1 @@ -123441,24 +124292,25 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \fasto2_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 13 output 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1174" + wire width 14 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1199" wire \illeg_ok - attribute \src "libresoc.v:76154.7-76154.15" + attribute \src "libresoc.v:76965.7-76965.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -123468,19 +124320,19 @@ module \dec2 wire width 2 output 48 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 output 40 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" wire width 32 \insn_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" wire width 32 \insn_in$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" wire width 32 \insn_in$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" wire width 32 \insn_in$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:391" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" wire width 32 \insn_in$89 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -123556,15 +124408,16 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 output 41 \insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire output 63 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:51" wire \is_priv_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire output 43 \lk @@ -123574,7 +124427,7 @@ module \dec2 wire output 46 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1198" wire \priv_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 4 \raw_opcode_in @@ -123599,13 +124452,14 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 7 \rego_ok attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" - wire width 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -123843,6 +124697,8 @@ module \dec2 wire width 10 output 16 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 65 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \tmp_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -124160,21 +125016,22 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$27 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 13 \tmp_tmp_fn_unit + wire width 14 \tmp_tmp_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -124257,6 +125114,7 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \tmp_tmp_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" @@ -124289,8 +125147,8 @@ module \dec2 wire width 3 output 20 \xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1177" - cell $and $and$libresoc.v:77847$3630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" + cell $and $and$libresoc.v:78671$3630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124298,10 +125156,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] - connect \Y $and$libresoc.v:77847$3630_Y + connect \Y $and$libresoc.v:78671$3630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1178" - cell $and $and$libresoc.v:77848$3631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1203" + cell $and $and$libresoc.v:78672$3631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124309,10 +125167,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:77848$3631_Y + connect \Y $and$libresoc.v:78672$3631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" - cell $and $and$libresoc.v:77849$3632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" + cell $and $and$libresoc.v:78673$3632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124320,10 +125178,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:77849$3632_Y + connect \Y $and$libresoc.v:78673$3632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:77856$3639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:78680$3639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124331,10 +125189,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$37 - connect \Y $and$libresoc.v:77856$3639_Y + connect \Y $and$libresoc.v:78680$3639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:77857$3640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:78681$3640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124342,10 +125200,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$39 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:77857$3640_Y + connect \Y $and$libresoc.v:78681$3640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:77859$3642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:78683$3642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124353,10 +125211,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$43 - connect \Y $and$libresoc.v:77859$3642_Y + connect \Y $and$libresoc.v:78683$3642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:77861$3644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:78685$3644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124364,10 +125222,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:77861$3644_Y + connect \Y $and$libresoc.v:78685$3644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:77873$3656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:78697$3656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124375,10 +125233,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$71 - connect \Y $and$libresoc.v:77873$3656_Y + connect \Y $and$libresoc.v:78697$3656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:77874$3657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:78698$3657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124386,10 +125244,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$73 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:77874$3657_Y + connect \Y $and$libresoc.v:78698$3657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:77876$3659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:78700$3659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124397,10 +125255,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$77 - connect \Y $and$libresoc.v:77876$3659_Y + connect \Y $and$libresoc.v:78700$3659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:77878$3661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:78702$3661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124408,10 +125266,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:77878$3661_Y + connect \Y $and$libresoc.v:78702$3661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1146" - cell $eq $eq$libresoc.v:77843$3626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" + cell $eq $eq$libresoc.v:78667$3626 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124419,10 +125277,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:77843$3626_Y + connect \Y $eq$libresoc.v:78667$3626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1148" - cell $eq $eq$libresoc.v:77844$3627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" + cell $eq $eq$libresoc.v:78668$3627 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124430,10 +125288,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 - connect \Y $eq$libresoc.v:77844$3627_Y + connect \Y $eq$libresoc.v:78668$3627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" - cell $eq $eq$libresoc.v:77845$3628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" + cell $eq $eq$libresoc.v:78669$3628 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124441,10 +125299,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:77845$3628_Y + connect \Y $eq$libresoc.v:78669$3628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1154" - cell $eq $eq$libresoc.v:77846$3629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + cell $eq $eq$libresoc.v:78670$3629 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124452,10 +125310,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $eq$libresoc.v:77846$3629_Y + connect \Y $eq$libresoc.v:78670$3629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1180" - cell $eq $eq$libresoc.v:77850$3633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" + cell $eq $eq$libresoc.v:78674$3633 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124463,10 +125321,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 - connect \Y $eq$libresoc.v:77850$3633_Y + connect \Y $eq$libresoc.v:78674$3633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1228" - cell $eq $eq$libresoc.v:77851$3634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1253" + cell $eq $eq$libresoc.v:78675$3634 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124474,10 +125332,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'0111111 - connect \Y $eq$libresoc.v:77851$3634_Y + connect \Y $eq$libresoc.v:78675$3634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1229" - cell $eq $eq$libresoc.v:77852$3635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + cell $eq $eq$libresoc.v:78676$3635 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124485,10 +125343,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1001001 - connect \Y $eq$libresoc.v:77852$3635_Y + connect \Y $eq$libresoc.v:78676$3635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1238" - cell $eq $eq$libresoc.v:77854$3637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" + cell $eq $eq$libresoc.v:78678$3637 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124496,32 +125354,32 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1000110 - connect \Y $eq$libresoc.v:77854$3637_Y + connect \Y $eq$libresoc.v:78678$3637_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:77855$3638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:78679$3638 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:77855$3638_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:78679$3638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:77858$3641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:78682$3641 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:77858$3641_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:78682$3641_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:77862$3645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:78686$3645 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124529,10 +125387,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:77862$3645_Y + connect \Y $eq$libresoc.v:78686$3645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:77863$3646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:78687$3646 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -124540,10 +125398,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:77863$3646_Y + connect \Y $eq$libresoc.v:78687$3646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:77865$3648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:78689$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -124551,10 +125409,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:77865$3648_Y + connect \Y $eq$libresoc.v:78689$3648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:77866$3649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:78690$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -124562,10 +125420,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:77866$3649_Y + connect \Y $eq$libresoc.v:78690$3649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:77868$3651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:78692$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -124573,10 +125431,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:77868$3651_Y + connect \Y $eq$libresoc.v:78692$3651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:77870$3653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:78694$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -124584,112 +125442,112 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:77870$3653_Y + connect \Y $eq$libresoc.v:78694$3653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:77872$3655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:78696$3655 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:77872$3655_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:78696$3655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:77875$3658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:78699$3658 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:77875$3658_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:78699$3658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:77840$3620 + cell $pos $extend$libresoc.v:78664$3620 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_b - connect \Y $extend$libresoc.v:77840$3620_Y + connect \Y $extend$libresoc.v:78664$3620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:77841$3622 + cell $pos $extend$libresoc.v:78665$3622 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_o - connect \Y $extend$libresoc.v:77841$3622_Y + connect \Y $extend$libresoc.v:78665$3622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:77842$3624 + cell $pos $extend$libresoc.v:78666$3624 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_out_cr_bitfield - connect \Y $extend$libresoc.v:77842$3624_Y + connect \Y $extend$libresoc.v:78666$3624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:77879$3662 + cell $pos $extend$libresoc.v:78703$3662 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_a_reg_a - connect \Y $extend$libresoc.v:77879$3662_Y + connect \Y $extend$libresoc.v:78703$3662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:77880$3664 + cell $pos $extend$libresoc.v:78704$3664 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_c_reg_c - connect \Y $extend$libresoc.v:77880$3664_Y + connect \Y $extend$libresoc.v:78704$3664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:77881$3666 + cell $pos $extend$libresoc.v:78705$3666 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o_reg_o - connect \Y $extend$libresoc.v:77881$3666_Y + connect \Y $extend$libresoc.v:78705$3666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:77882$3668 + cell $pos $extend$libresoc.v:78706$3668 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o2_reg_o2 - connect \Y $extend$libresoc.v:77882$3668_Y + connect \Y $extend$libresoc.v:78706$3668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:77883$3670 + cell $pos $extend$libresoc.v:78707$3670 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield - connect \Y $extend$libresoc.v:77883$3670_Y + connect \Y $extend$libresoc.v:78707$3670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:77860$3643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:78684$3643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:77860$3643_Y + connect \Y $not$libresoc.v:78684$3643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:77877$3660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:78701$3660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:77877$3660_Y + connect \Y $not$libresoc.v:78701$3660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1229" - cell $or $or$libresoc.v:77853$3636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + cell $or $or$libresoc.v:78677$3636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124697,10 +125555,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 - connect \Y $or$libresoc.v:77853$3636_Y + connect \Y $or$libresoc.v:78677$3636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:77864$3647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:78688$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124708,10 +125566,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:77864$3647_Y + connect \Y $or$libresoc.v:78688$3647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:77867$3650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:78691$3650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124719,10 +125577,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$57 connect \B \$59 - connect \Y $or$libresoc.v:77867$3650_Y + connect \Y $or$libresoc.v:78691$3650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:77869$3652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:78693$3652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124730,10 +125588,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$61 connect \B \$63 - connect \Y $or$libresoc.v:77869$3652_Y + connect \Y $or$libresoc.v:78693$3652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:77871$3654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:78695$3654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -124741,74 +125599,74 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$65 connect \B \$67 - connect \Y $or$libresoc.v:77871$3654_Y + connect \Y $or$libresoc.v:78695$3654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:77840$3621 + cell $pos $pos$libresoc.v:78664$3621 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:77840$3620_Y - connect \Y $pos$libresoc.v:77840$3621_Y + connect \A $extend$libresoc.v:78664$3620_Y + connect \Y $pos$libresoc.v:78664$3621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:77841$3623 + cell $pos $pos$libresoc.v:78665$3623 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:77841$3622_Y - connect \Y $pos$libresoc.v:77841$3623_Y + connect \A $extend$libresoc.v:78665$3622_Y + connect \Y $pos$libresoc.v:78665$3623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:77842$3625 + cell $pos $pos$libresoc.v:78666$3625 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:77842$3624_Y - connect \Y $pos$libresoc.v:77842$3625_Y + connect \A $extend$libresoc.v:78666$3624_Y + connect \Y $pos$libresoc.v:78666$3625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:77879$3663 + cell $pos $pos$libresoc.v:78703$3663 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:77879$3662_Y - connect \Y $pos$libresoc.v:77879$3663_Y + connect \A $extend$libresoc.v:78703$3662_Y + connect \Y $pos$libresoc.v:78703$3663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:77880$3665 + cell $pos $pos$libresoc.v:78704$3665 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:77880$3664_Y - connect \Y $pos$libresoc.v:77880$3665_Y + connect \A $extend$libresoc.v:78704$3664_Y + connect \Y $pos$libresoc.v:78704$3665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:77881$3667 + cell $pos $pos$libresoc.v:78705$3667 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:77881$3666_Y - connect \Y $pos$libresoc.v:77881$3667_Y + connect \A $extend$libresoc.v:78705$3666_Y + connect \Y $pos$libresoc.v:78705$3667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:77882$3669 + cell $pos $pos$libresoc.v:78706$3669 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:77882$3668_Y - connect \Y $pos$libresoc.v:77882$3669_Y + connect \A $extend$libresoc.v:78706$3668_Y + connect \Y $pos$libresoc.v:78706$3669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:77883$3671 + cell $pos $pos$libresoc.v:78707$3671 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:77883$3670_Y - connect \Y $pos$libresoc.v:77883$3671_Y + connect \A $extend$libresoc.v:78707$3670_Y + connect \Y $pos$libresoc.v:78707$3671_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:77884.13-77921.4" + attribute \src "libresoc.v:78708.13-78745.4" cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB @@ -124848,7 +125706,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:77922.9-77936.4" + attribute \src "libresoc.v:78746.9-78761.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -124863,9 +125721,10 @@ module \dec2 connect \sel_in \dec_a_sel_in connect \spr_a \dec_a_spr_a connect \spr_a_ok \dec_a_spr_a_ok + connect \sv_nz \dec_a_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:77937.9-77947.4" + attribute \src "libresoc.v:78762.9-78772.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -124878,7 +125737,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:77948.9-77954.4" + attribute \src "libresoc.v:78773.9-78779.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -124887,7 +125746,7 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:77955.13-77974.4" + attribute \src "libresoc.v:78780.13-78799.4" cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB @@ -124909,7 +125768,7 @@ module \dec2 connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:77975.14-77987.4" + attribute \src "libresoc.v:78800.14-78812.4" cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT @@ -124924,7 +125783,7 @@ module \dec2 connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:77988.9-78001.4" + attribute \src "libresoc.v:78813.9-78826.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -124940,7 +125799,7 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:78002.10-78011.4" + attribute \src "libresoc.v:78827.10-78836.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o2 \dec_o2_fast_o2 @@ -124952,7 +125811,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:78012.16-78018.4" + attribute \src "libresoc.v:78837.16-78843.4" cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op @@ -124961,61 +125820,61 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78019.16-78024.4" + attribute \src "libresoc.v:78844.16-78849.4" cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:76154.7-76154.20" - process $proc$libresoc.v:76154$3730 + attribute \src "libresoc.v:76965.7-76965.20" + process $proc$libresoc.v:76965$3730 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:78025.3-78039.6" - process $proc$libresoc.v:78025$3672 + attribute \src "libresoc.v:78850.3-78864.6" + process $proc$libresoc.v:78850$3672 assign { } { } - assign $0\tmp_tmp_fn_unit[12:0] $1\tmp_tmp_fn_unit[12:0] - attribute \src "libresoc.v:78026.5-78026.29" + assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] + attribute \src "libresoc.v:78851.5-78851.29" switch \initial - attribute \src "libresoc.v:78026.9-78026.17" + attribute \src "libresoc.v:78851.9-78851.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$83 \$75 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\tmp_tmp_fn_unit[12:0] 13'0000000000000 + assign $1\tmp_tmp_fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\tmp_tmp_fn_unit[12:0] 13'0000000000000 + assign $1\tmp_tmp_fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\tmp_tmp_fn_unit[12:0] \dec_function_unit + assign $1\tmp_tmp_fn_unit[13:0] \dec_function_unit end sync always - update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[12:0] + update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] end - attribute \src "libresoc.v:78040.3-78049.6" - process $proc$libresoc.v:78040$3673 + attribute \src "libresoc.v:78865.3-78874.6" + process $proc$libresoc.v:78865$3673 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78041.5-78041.29" + attribute \src "libresoc.v:78866.5-78866.29" switch \initial - attribute \src "libresoc.v:78041.9-78041.17" + attribute \src "libresoc.v:78866.9-78866.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:869" switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125027,18 +125886,18 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:78050.3-78062.6" - process $proc$libresoc.v:78050$3674 + attribute \src "libresoc.v:78875.3-78887.6" + process $proc$libresoc.v:78875$3674 assign { } { } assign { } { } assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78051.5-78051.29" + attribute \src "libresoc.v:78876.5-78876.29" switch \initial - attribute \src "libresoc.v:78051.9-78051.17" + attribute \src "libresoc.v:78876.9-78876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$49 \$41 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -125054,19 +125913,19 @@ module \dec2 sync always update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] end - attribute \src "libresoc.v:78063.3-78078.6" - process $proc$libresoc.v:78063$3675 + attribute \src "libresoc.v:78888.3-78903.6" + process $proc$libresoc.v:78888$3675 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:78064.5-78064.29" + attribute \src "libresoc.v:78889.5-78889.29" switch \initial - attribute \src "libresoc.v:78064.9-78064.17" + attribute \src "libresoc.v:78889.9-78889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1146" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" switch \$106 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125075,7 +125934,7 @@ module \dec2 case assign $1\tmp_xer_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" switch \$108 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125087,18 +125946,18 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:78079.3-78088.6" - process $proc$libresoc.v:78079$3676 + attribute \src "libresoc.v:78904.3-78913.6" + process $proc$libresoc.v:78904$3676 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:78080.5-78080.29" + attribute \src "libresoc.v:78905.5-78905.29" switch \initial - attribute \src "libresoc.v:78080.9-78080.17" + attribute \src "libresoc.v:78905.9-78905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125110,18 +125969,18 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:78089.3-78098.6" - process $proc$libresoc.v:78089$3677 + attribute \src "libresoc.v:78914.3-78923.6" + process $proc$libresoc.v:78914$3677 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78090.5-78090.29" + attribute \src "libresoc.v:78915.5-78915.29" switch \initial - attribute \src "libresoc.v:78090.9-78090.17" + attribute \src "libresoc.v:78915.9-78915.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" switch \$112 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125133,14 +125992,14 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:78099.3-78122.6" - process $proc$libresoc.v:78099$3678 + attribute \src "libresoc.v:78924.3-78947.6" + process $proc$libresoc.v:78924$3678 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:78100.5-78100.29" + attribute \src "libresoc.v:78925.5-78925.29" switch \initial - attribute \src "libresoc.v:78100.9-78100.17" + attribute \src "libresoc.v:78925.9-78925.17" case 1'1 case end @@ -125173,8 +126032,8 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:78123.3-78280.6" - process $proc$libresoc.v:78123$3679 + attribute \src "libresoc.v:78948.3-79105.6" + process $proc$libresoc.v:78948$3679 assign { } { } assign { } { } assign { } { } @@ -125271,7 +126130,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign $0\fn_unit[12:0] $1\fn_unit[12:0] + assign $0\fn_unit[13:0] $1\fn_unit[13:0] assign $0\input_carry[1:0] $1\input_carry[1:0] assign $0\insn[31:0] $1\insn[31:0] assign $0\insn_type[6:0] $1\insn_type[6:0] @@ -125302,13 +126161,13 @@ module \dec2 assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:78124.5-78124.29" + attribute \src "libresoc.v:78949.5-78949.29" switch \initial - attribute \src "libresoc.v:78124.9-78124.17" + attribute \src "libresoc.v:78949.9-78949.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1209" switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" case 5'----1 @@ -125408,7 +126267,7 @@ module \dec2 assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] assign $1\fasto2[2:0] $2\fasto2[2:0] assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] - assign $1\fn_unit[12:0] $2\fn_unit[12:0] + assign $1\fn_unit[13:0] $2\fn_unit[13:0] assign $1\input_carry[1:0] $2\input_carry[1:0] assign $1\insn[31:0] $2\insn[31:0] assign $1\insn_type[6:0] $2\insn_type[6:0] @@ -125430,7 +126289,7 @@ module \dec2 assign $1\traptype[7:0] $2\traptype[7:0] assign $1\xer_in[2:0] $2\xer_in[2:0] assign $1\xer_out[0:0] $2\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1210" switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -125496,7 +126355,7 @@ module \dec2 assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3709 $2\exc_$signal$8[0:0]$3708 $2\exc_$signal$7[0:0]$3707 $2\exc_$signal$6[0:0]$3706 $2\exc_$signal$5[0:0]$3705 $2\exc_$signal$4[0:0]$3704 $2\exc_$signal$3[0:0]$3703 $2\exc_$signal[0:0]$3702 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3701 $2\cr_in2$1[6:0]$3700 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $2\insn[31:0] \dec_opcode_in assign $2\insn_type[6:0] 7'0111111 - assign $2\fn_unit[12:0] 13'0000010000000 + assign $2\fn_unit[13:0] 14'00000010000000 assign $2\trapaddr[12:0] 13'0000001100000 assign $2\traptype[7:0] 8'00000010 assign $2\msr[63:0] \cur_msr @@ -125599,7 +126458,7 @@ module \dec2 assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] assign $2\fasto2[2:0] $3\fasto2[2:0] assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] - assign $2\fn_unit[12:0] $3\fn_unit[12:0] + assign $2\fn_unit[13:0] $3\fn_unit[13:0] assign $2\input_carry[1:0] $3\input_carry[1:0] assign $2\insn[31:0] $3\insn[31:0] assign $2\insn_type[6:0] $3\insn_type[6:0] @@ -125621,7 +126480,7 @@ module \dec2 assign $2\traptype[7:0] $3\traptype[7:0] assign $2\xer_in[2:0] $3\xer_in[2:0] assign $2\xer_out[0:0] $3\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1213" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125687,7 +126546,7 @@ module \dec2 assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 - assign $3\fn_unit[12:0] 13'0000010000000 + assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001001000 assign $3\traptype[7:0] 8'00000010 assign $3\msr[63:0] \cur_msr @@ -125756,7 +126615,7 @@ module \dec2 assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 - assign $3\fn_unit[12:0] 13'0000010000000 + assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001000000 assign $3\traptype[7:0] 8'01000000 assign { $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } @@ -125861,7 +126720,7 @@ module \dec2 assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] assign $2\fasto2[2:0] $4\fasto2[2:0] assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] - assign $2\fn_unit[12:0] $4\fn_unit[12:0] + assign $2\fn_unit[13:0] $4\fn_unit[13:0] assign $2\input_carry[1:0] $4\input_carry[1:0] assign $2\insn[31:0] $4\insn[31:0] assign $2\insn_type[6:0] $4\insn_type[6:0] @@ -125883,7 +126742,7 @@ module \dec2 assign $2\traptype[7:0] $4\traptype[7:0] assign $2\xer_in[2:0] $4\xer_in[2:0] assign $2\xer_out[0:0] $4\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1219" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125949,7 +126808,7 @@ module \dec2 assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 - assign $4\fn_unit[12:0] 13'0000010000000 + assign $4\fn_unit[13:0] 14'00000010000000 assign $4\trapaddr[12:0] 13'0000000111000 assign $4\traptype[7:0] 8'00000010 assign $4\msr[63:0] \cur_msr @@ -126018,7 +126877,7 @@ module \dec2 assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 - assign $4\fn_unit[12:0] 13'0000010000000 + assign $4\fn_unit[13:0] 14'00000010000000 assign $4\trapaddr[12:0] 13'0000000110000 assign $4\traptype[7:0] 8'00000010 assign $4\msr[63:0] \cur_msr @@ -126089,7 +126948,7 @@ module \dec2 assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[12:0] 13'0000010000000 + assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000010010000 assign $1\traptype[7:0] 8'00100000 assign $1\msr[63:0] \cur_msr @@ -126158,7 +127017,7 @@ module \dec2 assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[12:0] 13'0000010000000 + assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001010000 assign $1\traptype[7:0] 8'00010000 assign $1\msr[63:0] \cur_msr @@ -126227,7 +127086,7 @@ module \dec2 assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[12:0] 13'0000010000000 + assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001110000 assign $1\traptype[7:0] 8'00000010 assign $1\msr[63:0] \cur_msr @@ -126296,7 +127155,7 @@ module \dec2 assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[12:0] 13'0000010000000 + assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001110000 assign $1\traptype[7:0] 8'10000000 assign $1\msr[63:0] \cur_msr @@ -126362,9 +127221,9 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[12:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126382,7 +127241,7 @@ module \dec2 assign $5\fasto2[2:0] $1\fasto2[2:0] assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126438,7 +127297,7 @@ module \dec2 update \fasto1_ok $0\fasto1_ok[0:0] update \fasto2 $0\fasto2[2:0] update \fasto2_ok $0\fasto2_ok[0:0] - update \fn_unit $0\fn_unit[12:0] + update \fn_unit $0\fn_unit[13:0] update \input_carry $0\input_carry[1:0] update \insn $0\insn[31:0] update \insn_type $0\insn_type[6:0] @@ -126461,50 +127320,50 @@ module \dec2 update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - connect \$100 $pos$libresoc.v:77840$3621_Y - connect \$102 $pos$libresoc.v:77841$3623_Y - connect \$104 $pos$libresoc.v:77842$3625_Y - connect \$106 $eq$libresoc.v:77843$3626_Y - connect \$108 $eq$libresoc.v:77844$3627_Y - connect \$110 $eq$libresoc.v:77845$3628_Y - connect \$112 $eq$libresoc.v:77846$3629_Y - connect \$114 $and$libresoc.v:77847$3630_Y - connect \$116 $and$libresoc.v:77848$3631_Y - connect \$118 $and$libresoc.v:77849$3632_Y - connect \$120 $eq$libresoc.v:77850$3633_Y - connect \$28 $eq$libresoc.v:77851$3634_Y - connect \$30 $eq$libresoc.v:77852$3635_Y - connect \$32 $or$libresoc.v:77853$3636_Y - connect \$34 $eq$libresoc.v:77854$3637_Y - connect \$37 $eq$libresoc.v:77855$3638_Y - connect \$39 $and$libresoc.v:77856$3639_Y - connect \$41 $and$libresoc.v:77857$3640_Y - connect \$43 $eq$libresoc.v:77858$3641_Y - connect \$45 $and$libresoc.v:77859$3642_Y - connect \$47 $not$libresoc.v:77860$3643_Y - connect \$49 $and$libresoc.v:77861$3644_Y - connect \$51 $eq$libresoc.v:77862$3645_Y - connect \$53 $eq$libresoc.v:77863$3646_Y - connect \$55 $or$libresoc.v:77864$3647_Y - connect \$57 $eq$libresoc.v:77865$3648_Y - connect \$59 $eq$libresoc.v:77866$3649_Y - connect \$61 $or$libresoc.v:77867$3650_Y - connect \$63 $eq$libresoc.v:77868$3651_Y - connect \$65 $or$libresoc.v:77869$3652_Y - connect \$67 $eq$libresoc.v:77870$3653_Y - connect \$69 $or$libresoc.v:77871$3654_Y - connect \$71 $eq$libresoc.v:77872$3655_Y - connect \$73 $and$libresoc.v:77873$3656_Y - connect \$75 $and$libresoc.v:77874$3657_Y - connect \$77 $eq$libresoc.v:77875$3658_Y - connect \$79 $and$libresoc.v:77876$3659_Y - connect \$81 $not$libresoc.v:77877$3660_Y - connect \$83 $and$libresoc.v:77878$3661_Y - connect \$90 $pos$libresoc.v:77879$3663_Y - connect \$92 $pos$libresoc.v:77880$3665_Y - connect \$94 $pos$libresoc.v:77881$3667_Y - connect \$96 $pos$libresoc.v:77882$3669_Y - connect \$98 $pos$libresoc.v:77883$3671_Y + connect \$100 $pos$libresoc.v:78664$3621_Y + connect \$102 $pos$libresoc.v:78665$3623_Y + connect \$104 $pos$libresoc.v:78666$3625_Y + connect \$106 $eq$libresoc.v:78667$3626_Y + connect \$108 $eq$libresoc.v:78668$3627_Y + connect \$110 $eq$libresoc.v:78669$3628_Y + connect \$112 $eq$libresoc.v:78670$3629_Y + connect \$114 $and$libresoc.v:78671$3630_Y + connect \$116 $and$libresoc.v:78672$3631_Y + connect \$118 $and$libresoc.v:78673$3632_Y + connect \$120 $eq$libresoc.v:78674$3633_Y + connect \$28 $eq$libresoc.v:78675$3634_Y + connect \$30 $eq$libresoc.v:78676$3635_Y + connect \$32 $or$libresoc.v:78677$3636_Y + connect \$34 $eq$libresoc.v:78678$3637_Y + connect \$37 $eq$libresoc.v:78679$3638_Y + connect \$39 $and$libresoc.v:78680$3639_Y + connect \$41 $and$libresoc.v:78681$3640_Y + connect \$43 $eq$libresoc.v:78682$3641_Y + connect \$45 $and$libresoc.v:78683$3642_Y + connect \$47 $not$libresoc.v:78684$3643_Y + connect \$49 $and$libresoc.v:78685$3644_Y + connect \$51 $eq$libresoc.v:78686$3645_Y + connect \$53 $eq$libresoc.v:78687$3646_Y + connect \$55 $or$libresoc.v:78688$3647_Y + connect \$57 $eq$libresoc.v:78689$3648_Y + connect \$59 $eq$libresoc.v:78690$3649_Y + connect \$61 $or$libresoc.v:78691$3650_Y + connect \$63 $eq$libresoc.v:78692$3651_Y + connect \$65 $or$libresoc.v:78693$3652_Y + connect \$67 $eq$libresoc.v:78694$3653_Y + connect \$69 $or$libresoc.v:78695$3654_Y + connect \$71 $eq$libresoc.v:78696$3655_Y + connect \$73 $and$libresoc.v:78697$3656_Y + connect \$75 $and$libresoc.v:78698$3657_Y + connect \$77 $eq$libresoc.v:78699$3658_Y + connect \$79 $and$libresoc.v:78700$3659_Y + connect \$81 $not$libresoc.v:78701$3660_Y + connect \$83 $and$libresoc.v:78702$3661_Y + connect \$90 $pos$libresoc.v:78703$3663_Y + connect \$92 $pos$libresoc.v:78704$3665_Y + connect \$94 $pos$libresoc.v:78705$3667_Y + connect \$96 $pos$libresoc.v:78706$3669_Y + connect \$98 $pos$libresoc.v:78707$3671_Y connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 @@ -126570,6 +127429,7 @@ module \dec2 connect \insn_in$86 \dec_opcode_in connect \insn_in$85 \dec_opcode_in connect \tmp_tmp_insn \dec_opcode_in + connect \dec_a_sv_nz \sv_a_nz connect \tmp_tmp_is_32bit \dec_is_32b connect \tmp_tmp_input_carry \dec_cry_in connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } @@ -126584,140 +127444,1328 @@ module \dec2 connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:78363.1-79884.10" +attribute \src "libresoc.v:79189.1-79849.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" +attribute \generator "nMigen" +module \dec22 + attribute \src "libresoc.v:79788.3-79797.6" + wire width 2 $0\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:79798.3-79807.6" + wire width 2 $0\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:79668.3-79677.6" + wire width 8 $0\dec22_asmcode[7:0] + attribute \src "libresoc.v:79708.3-79717.6" + wire $0\dec22_br[0:0] + attribute \src "libresoc.v:79538.3-79547.6" + wire width 3 $0\dec22_cr_in[2:0] + attribute \src "libresoc.v:79548.3-79557.6" + wire width 3 $0\dec22_cr_out[2:0] + attribute \src "libresoc.v:79658.3-79667.6" + wire width 2 $0\dec22_cry_in[1:0] + attribute \src "libresoc.v:79698.3-79707.6" + wire $0\dec22_cry_out[0:0] + attribute \src "libresoc.v:79748.3-79757.6" + wire width 5 $0\dec22_form[4:0] + attribute \src "libresoc.v:79528.3-79537.6" + wire width 14 $0\dec22_function_unit[13:0] + attribute \src "libresoc.v:79808.3-79817.6" + wire width 3 $0\dec22_in1_sel[2:0] + attribute \src "libresoc.v:79818.3-79827.6" + wire width 4 $0\dec22_in2_sel[3:0] + attribute \src "libresoc.v:79828.3-79837.6" + wire width 2 $0\dec22_in3_sel[1:0] + attribute \src "libresoc.v:79638.3-79647.6" + wire width 7 $0\dec22_internal_op[6:0] + attribute \src "libresoc.v:79678.3-79687.6" + wire $0\dec22_inv_a[0:0] + attribute \src "libresoc.v:79688.3-79697.6" + wire $0\dec22_inv_out[0:0] + attribute \src "libresoc.v:79738.3-79747.6" + wire $0\dec22_is_32b[0:0] + attribute \src "libresoc.v:79618.3-79627.6" + wire width 4 $0\dec22_ldst_len[3:0] + attribute \src "libresoc.v:79768.3-79777.6" + wire $0\dec22_lk[0:0] + attribute \src "libresoc.v:79838.3-79847.6" + wire width 3 $0\dec22_out_sel[2:0] + attribute \src "libresoc.v:79648.3-79657.6" + wire width 2 $0\dec22_rc_sel[1:0] + attribute \src "libresoc.v:79728.3-79737.6" + wire $0\dec22_rsrv[0:0] + attribute \src "libresoc.v:79778.3-79787.6" + wire $0\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:79758.3-79767.6" + wire $0\dec22_sgn[0:0] + attribute \src "libresoc.v:79718.3-79727.6" + wire $0\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:79598.3-79607.6" + wire width 3 $0\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:79608.3-79617.6" + wire width 3 $0\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:79558.3-79567.6" + wire width 3 $0\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79568.3-79577.6" + wire width 3 $0\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79578.3-79587.6" + wire width 3 $0\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79588.3-79597.6" + wire width 3 $0\dec22_sv_out[2:0] + attribute \src "libresoc.v:79628.3-79637.6" + wire width 2 $0\dec22_upd[1:0] + attribute \src "libresoc.v:79190.7-79190.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:79788.3-79797.6" + wire width 2 $1\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:79798.3-79807.6" + wire width 2 $1\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:79668.3-79677.6" + wire width 8 $1\dec22_asmcode[7:0] + attribute \src "libresoc.v:79708.3-79717.6" + wire $1\dec22_br[0:0] + attribute \src "libresoc.v:79538.3-79547.6" + wire width 3 $1\dec22_cr_in[2:0] + attribute \src "libresoc.v:79548.3-79557.6" + wire width 3 $1\dec22_cr_out[2:0] + attribute \src "libresoc.v:79658.3-79667.6" + wire width 2 $1\dec22_cry_in[1:0] + attribute \src "libresoc.v:79698.3-79707.6" + wire $1\dec22_cry_out[0:0] + attribute \src "libresoc.v:79748.3-79757.6" + wire width 5 $1\dec22_form[4:0] + attribute \src "libresoc.v:79528.3-79537.6" + wire width 14 $1\dec22_function_unit[13:0] + attribute \src "libresoc.v:79808.3-79817.6" + wire width 3 $1\dec22_in1_sel[2:0] + attribute \src "libresoc.v:79818.3-79827.6" + wire width 4 $1\dec22_in2_sel[3:0] + attribute \src "libresoc.v:79828.3-79837.6" + wire width 2 $1\dec22_in3_sel[1:0] + attribute \src "libresoc.v:79638.3-79647.6" + wire width 7 $1\dec22_internal_op[6:0] + attribute \src "libresoc.v:79678.3-79687.6" + wire $1\dec22_inv_a[0:0] + attribute \src "libresoc.v:79688.3-79697.6" + wire $1\dec22_inv_out[0:0] + attribute \src "libresoc.v:79738.3-79747.6" + wire $1\dec22_is_32b[0:0] + attribute \src "libresoc.v:79618.3-79627.6" + wire width 4 $1\dec22_ldst_len[3:0] + attribute \src "libresoc.v:79768.3-79777.6" + wire $1\dec22_lk[0:0] + attribute \src "libresoc.v:79838.3-79847.6" + wire width 3 $1\dec22_out_sel[2:0] + attribute \src "libresoc.v:79648.3-79657.6" + wire width 2 $1\dec22_rc_sel[1:0] + attribute \src "libresoc.v:79728.3-79737.6" + wire $1\dec22_rsrv[0:0] + attribute \src "libresoc.v:79778.3-79787.6" + wire $1\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:79758.3-79767.6" + wire $1\dec22_sgn[0:0] + attribute \src "libresoc.v:79718.3-79727.6" + wire $1\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:79598.3-79607.6" + wire width 3 $1\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:79608.3-79617.6" + wire width 3 $1\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:79558.3-79567.6" + wire width 3 $1\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79568.3-79577.6" + wire width 3 $1\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79578.3-79587.6" + wire width 3 $1\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79588.3-79597.6" + wire width 3 $1\dec22_sv_out[2:0] + attribute \src "libresoc.v:79628.3-79637.6" + wire width 2 $1\dec22_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec22_form + attribute \enum_base_type "Function" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 10 \dec22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec22_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec22_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec22_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec22_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec22_upd + attribute \src "libresoc.v:79190.7-79190.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 4 \opcode_switch + attribute \src "libresoc.v:79190.7-79190.20" + process $proc$libresoc.v:79190$3763 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:79528.3-79537.6" + process $proc$libresoc.v:79528$3731 + assign { } { } + assign { } { } + assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] + attribute \src "libresoc.v:79529.5-79529.29" + switch \initial + attribute \src "libresoc.v:79529.9-79529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_function_unit[13:0] 14'10000000000000 + case + assign $1\dec22_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec22_function_unit $0\dec22_function_unit[13:0] + end + attribute \src "libresoc.v:79538.3-79547.6" + process $proc$libresoc.v:79538$3732 + assign { } { } + assign { } { } + assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] + attribute \src "libresoc.v:79539.5-79539.29" + switch \initial + attribute \src "libresoc.v:79539.9-79539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cr_in[2:0] 3'000 + case + assign $1\dec22_cr_in[2:0] 3'000 + end + sync always + update \dec22_cr_in $0\dec22_cr_in[2:0] + end + attribute \src "libresoc.v:79548.3-79557.6" + process $proc$libresoc.v:79548$3733 + assign { } { } + assign { } { } + assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] + attribute \src "libresoc.v:79549.5-79549.29" + switch \initial + attribute \src "libresoc.v:79549.9-79549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cr_out[2:0] 3'001 + case + assign $1\dec22_cr_out[2:0] 3'000 + end + sync always + update \dec22_cr_out $0\dec22_cr_out[2:0] + end + attribute \src "libresoc.v:79558.3-79567.6" + process $proc$libresoc.v:79558$3734 + assign { } { } + assign { } { } + assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] + attribute \src "libresoc.v:79559.5-79559.29" + switch \initial + attribute \src "libresoc.v:79559.9-79559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in1[2:0] 3'000 + case + assign $1\dec22_sv_in1[2:0] 3'000 + end + sync always + update \dec22_sv_in1 $0\dec22_sv_in1[2:0] + end + attribute \src "libresoc.v:79568.3-79577.6" + process $proc$libresoc.v:79568$3735 + assign { } { } + assign { } { } + assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] + attribute \src "libresoc.v:79569.5-79569.29" + switch \initial + attribute \src "libresoc.v:79569.9-79569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in2[2:0] 3'000 + case + assign $1\dec22_sv_in2[2:0] 3'000 + end + sync always + update \dec22_sv_in2 $0\dec22_sv_in2[2:0] + end + attribute \src "libresoc.v:79578.3-79587.6" + process $proc$libresoc.v:79578$3736 + assign { } { } + assign { } { } + assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] + attribute \src "libresoc.v:79579.5-79579.29" + switch \initial + attribute \src "libresoc.v:79579.9-79579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_in3[2:0] 3'000 + case + assign $1\dec22_sv_in3[2:0] 3'000 + end + sync always + update \dec22_sv_in3 $0\dec22_sv_in3[2:0] + end + attribute \src "libresoc.v:79588.3-79597.6" + process $proc$libresoc.v:79588$3737 + assign { } { } + assign { } { } + assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] + attribute \src "libresoc.v:79589.5-79589.29" + switch \initial + attribute \src "libresoc.v:79589.9-79589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_out[2:0] 3'000 + case + assign $1\dec22_sv_out[2:0] 3'000 + end + sync always + update \dec22_sv_out $0\dec22_sv_out[2:0] + end + attribute \src "libresoc.v:79598.3-79607.6" + process $proc$libresoc.v:79598$3738 + assign { } { } + assign { } { } + assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] + attribute \src "libresoc.v:79599.5-79599.29" + switch \initial + attribute \src "libresoc.v:79599.9-79599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_cr_in[2:0] 3'000 + case + assign $1\dec22_sv_cr_in[2:0] 3'000 + end + sync always + update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] + end + attribute \src "libresoc.v:79608.3-79617.6" + process $proc$libresoc.v:79608$3739 + assign { } { } + assign { } { } + assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] + attribute \src "libresoc.v:79609.5-79609.29" + switch \initial + attribute \src "libresoc.v:79609.9-79609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_cr_out[2:0] 3'000 + case + assign $1\dec22_sv_cr_out[2:0] 3'000 + end + sync always + update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] + end + attribute \src "libresoc.v:79618.3-79627.6" + process $proc$libresoc.v:79618$3740 + assign { } { } + assign { } { } + assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] + attribute \src "libresoc.v:79619.5-79619.29" + switch \initial + attribute \src "libresoc.v:79619.9-79619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_ldst_len[3:0] 4'0000 + case + assign $1\dec22_ldst_len[3:0] 4'0000 + end + sync always + update \dec22_ldst_len $0\dec22_ldst_len[3:0] + end + attribute \src "libresoc.v:79628.3-79637.6" + process $proc$libresoc.v:79628$3741 + assign { } { } + assign { } { } + assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] + attribute \src "libresoc.v:79629.5-79629.29" + switch \initial + attribute \src "libresoc.v:79629.9-79629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_upd[1:0] 2'00 + case + assign $1\dec22_upd[1:0] 2'00 + end + sync always + update \dec22_upd $0\dec22_upd[1:0] + end + attribute \src "libresoc.v:79638.3-79647.6" + process $proc$libresoc.v:79638$3742 + assign { } { } + assign { } { } + assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] + attribute \src "libresoc.v:79639.5-79639.29" + switch \initial + attribute \src "libresoc.v:79639.9-79639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_internal_op[6:0] 7'1001100 + case + assign $1\dec22_internal_op[6:0] 7'0000000 + end + sync always + update \dec22_internal_op $0\dec22_internal_op[6:0] + end + attribute \src "libresoc.v:79648.3-79657.6" + process $proc$libresoc.v:79648$3743 + assign { } { } + assign { } { } + assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] + attribute \src "libresoc.v:79649.5-79649.29" + switch \initial + attribute \src "libresoc.v:79649.9-79649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_rc_sel[1:0] 2'10 + case + assign $1\dec22_rc_sel[1:0] 2'00 + end + sync always + update \dec22_rc_sel $0\dec22_rc_sel[1:0] + end + attribute \src "libresoc.v:79658.3-79667.6" + process $proc$libresoc.v:79658$3744 + assign { } { } + assign { } { } + assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] + attribute \src "libresoc.v:79659.5-79659.29" + switch \initial + attribute \src "libresoc.v:79659.9-79659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cry_in[1:0] 2'00 + case + assign $1\dec22_cry_in[1:0] 2'00 + end + sync always + update \dec22_cry_in $0\dec22_cry_in[1:0] + end + attribute \src "libresoc.v:79668.3-79677.6" + process $proc$libresoc.v:79668$3745 + assign { } { } + assign { } { } + assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] + attribute \src "libresoc.v:79669.5-79669.29" + switch \initial + attribute \src "libresoc.v:79669.9-79669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_asmcode[7:0] 8'10011100 + case + assign $1\dec22_asmcode[7:0] 8'00000000 + end + sync always + update \dec22_asmcode $0\dec22_asmcode[7:0] + end + attribute \src "libresoc.v:79678.3-79687.6" + process $proc$libresoc.v:79678$3746 + assign { } { } + assign { } { } + assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] + attribute \src "libresoc.v:79679.5-79679.29" + switch \initial + attribute \src "libresoc.v:79679.9-79679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_inv_a[0:0] 1'0 + case + assign $1\dec22_inv_a[0:0] 1'0 + end + sync always + update \dec22_inv_a $0\dec22_inv_a[0:0] + end + attribute \src "libresoc.v:79688.3-79697.6" + process $proc$libresoc.v:79688$3747 + assign { } { } + assign { } { } + assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] + attribute \src "libresoc.v:79689.5-79689.29" + switch \initial + attribute \src "libresoc.v:79689.9-79689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_inv_out[0:0] 1'0 + case + assign $1\dec22_inv_out[0:0] 1'0 + end + sync always + update \dec22_inv_out $0\dec22_inv_out[0:0] + end + attribute \src "libresoc.v:79698.3-79707.6" + process $proc$libresoc.v:79698$3748 + assign { } { } + assign { } { } + assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] + attribute \src "libresoc.v:79699.5-79699.29" + switch \initial + attribute \src "libresoc.v:79699.9-79699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_cry_out[0:0] 1'0 + case + assign $1\dec22_cry_out[0:0] 1'0 + end + sync always + update \dec22_cry_out $0\dec22_cry_out[0:0] + end + attribute \src "libresoc.v:79708.3-79717.6" + process $proc$libresoc.v:79708$3749 + assign { } { } + assign { } { } + assign $0\dec22_br[0:0] $1\dec22_br[0:0] + attribute \src "libresoc.v:79709.5-79709.29" + switch \initial + attribute \src "libresoc.v:79709.9-79709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_br[0:0] 1'0 + case + assign $1\dec22_br[0:0] 1'0 + end + sync always + update \dec22_br $0\dec22_br[0:0] + end + attribute \src "libresoc.v:79718.3-79727.6" + process $proc$libresoc.v:79718$3750 + assign { } { } + assign { } { } + assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] + attribute \src "libresoc.v:79719.5-79719.29" + switch \initial + attribute \src "libresoc.v:79719.9-79719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgn_ext[0:0] 1'0 + case + assign $1\dec22_sgn_ext[0:0] 1'0 + end + sync always + update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] + end + attribute \src "libresoc.v:79728.3-79737.6" + process $proc$libresoc.v:79728$3751 + assign { } { } + assign { } { } + assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] + attribute \src "libresoc.v:79729.5-79729.29" + switch \initial + attribute \src "libresoc.v:79729.9-79729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_rsrv[0:0] 1'0 + case + assign $1\dec22_rsrv[0:0] 1'0 + end + sync always + update \dec22_rsrv $0\dec22_rsrv[0:0] + end + attribute \src "libresoc.v:79738.3-79747.6" + process $proc$libresoc.v:79738$3752 + assign { } { } + assign { } { } + assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] + attribute \src "libresoc.v:79739.5-79739.29" + switch \initial + attribute \src "libresoc.v:79739.9-79739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_is_32b[0:0] 1'0 + case + assign $1\dec22_is_32b[0:0] 1'0 + end + sync always + update \dec22_is_32b $0\dec22_is_32b[0:0] + end + attribute \src "libresoc.v:79748.3-79757.6" + process $proc$libresoc.v:79748$3753 + assign { } { } + assign { } { } + assign $0\dec22_form[4:0] $1\dec22_form[4:0] + attribute \src "libresoc.v:79749.5-79749.29" + switch \initial + attribute \src "libresoc.v:79749.9-79749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_form[4:0] 5'11101 + case + assign $1\dec22_form[4:0] 5'00000 + end + sync always + update \dec22_form $0\dec22_form[4:0] + end + attribute \src "libresoc.v:79758.3-79767.6" + process $proc$libresoc.v:79758$3754 + assign { } { } + assign { } { } + assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] + attribute \src "libresoc.v:79759.5-79759.29" + switch \initial + attribute \src "libresoc.v:79759.9-79759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgn[0:0] 1'0 + case + assign $1\dec22_sgn[0:0] 1'0 + end + sync always + update \dec22_sgn $0\dec22_sgn[0:0] + end + attribute \src "libresoc.v:79768.3-79777.6" + process $proc$libresoc.v:79768$3755 + assign { } { } + assign { } { } + assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] + attribute \src "libresoc.v:79769.5-79769.29" + switch \initial + attribute \src "libresoc.v:79769.9-79769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_lk[0:0] 1'0 + case + assign $1\dec22_lk[0:0] 1'0 + end + sync always + update \dec22_lk $0\dec22_lk[0:0] + end + attribute \src "libresoc.v:79778.3-79787.6" + process $proc$libresoc.v:79778$3756 + assign { } { } + assign { } { } + assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] + attribute \src "libresoc.v:79779.5-79779.29" + switch \initial + attribute \src "libresoc.v:79779.9-79779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sgl_pipe[0:0] 1'0 + case + assign $1\dec22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:79788.3-79797.6" + process $proc$libresoc.v:79788$3757 + assign { } { } + assign { } { } + assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] + attribute \src "libresoc.v:79789.5-79789.29" + switch \initial + attribute \src "libresoc.v:79789.9-79789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_SV_Etype[1:0] 2'00 + case + assign $1\dec22_SV_Etype[1:0] 2'00 + end + sync always + update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] + end + attribute \src "libresoc.v:79798.3-79807.6" + process $proc$libresoc.v:79798$3758 + assign { } { } + assign { } { } + assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] + attribute \src "libresoc.v:79799.5-79799.29" + switch \initial + attribute \src "libresoc.v:79799.9-79799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_SV_Ptype[1:0] 2'00 + case + assign $1\dec22_SV_Ptype[1:0] 2'00 + end + sync always + update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] + end + attribute \src "libresoc.v:79808.3-79817.6" + process $proc$libresoc.v:79808$3759 + assign { } { } + assign { } { } + assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] + attribute \src "libresoc.v:79809.5-79809.29" + switch \initial + attribute \src "libresoc.v:79809.9-79809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in1_sel[2:0] 3'010 + case + assign $1\dec22_in1_sel[2:0] 3'000 + end + sync always + update \dec22_in1_sel $0\dec22_in1_sel[2:0] + end + attribute \src "libresoc.v:79818.3-79827.6" + process $proc$libresoc.v:79818$3760 + assign { } { } + assign { } { } + assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] + attribute \src "libresoc.v:79819.5-79819.29" + switch \initial + attribute \src "libresoc.v:79819.9-79819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in2_sel[3:0] 4'0000 + case + assign $1\dec22_in2_sel[3:0] 4'0000 + end + sync always + update \dec22_in2_sel $0\dec22_in2_sel[3:0] + end + attribute \src "libresoc.v:79828.3-79837.6" + process $proc$libresoc.v:79828$3761 + assign { } { } + assign { } { } + assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] + attribute \src "libresoc.v:79829.5-79829.29" + switch \initial + attribute \src "libresoc.v:79829.9-79829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_in3_sel[1:0] 2'00 + case + assign $1\dec22_in3_sel[1:0] 2'00 + end + sync always + update \dec22_in3_sel $0\dec22_in3_sel[1:0] + end + attribute \src "libresoc.v:79838.3-79847.6" + process $proc$libresoc.v:79838$3762 + assign { } { } + assign { } { } + assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] + attribute \src "libresoc.v:79839.5-79839.29" + switch \initial + attribute \src "libresoc.v:79839.9-79839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_out_sel[2:0] 3'100 + case + assign $1\dec22_out_sel[2:0] 3'000 + end + sync always + update \dec22_out_sel $0\dec22_out_sel[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:79853.1-81377.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:79661.3-79697.6" + attribute \src "libresoc.v:81154.3-81190.6" wire width 2 $0\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:79698.3-79734.6" + attribute \src "libresoc.v:81191.3-81227.6" wire width 2 $0\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:79217.3-79253.6" + attribute \src "libresoc.v:80710.3-80746.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:79365.3-79401.6" + attribute \src "libresoc.v:80858.3-80894.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:78736.3-78772.6" + attribute \src "libresoc.v:80229.3-80265.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:78773.3-78809.6" + attribute \src "libresoc.v:80266.3-80302.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:79180.3-79216.6" + attribute \src "libresoc.v:80673.3-80709.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:79328.3-79364.6" + attribute \src "libresoc.v:80821.3-80857.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:79513.3-79549.6" + attribute \src "libresoc.v:81006.3-81042.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:78699.3-78735.6" - wire width 13 $0\dec30_function_unit[12:0] - attribute \src "libresoc.v:79735.3-79771.6" + attribute \src "libresoc.v:80192.3-80228.6" + wire width 14 $0\dec30_function_unit[13:0] + attribute \src "libresoc.v:81228.3-81264.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:79772.3-79808.6" + attribute \src "libresoc.v:81265.3-81301.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:79809.3-79845.6" + attribute \src "libresoc.v:81302.3-81338.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:79106.3-79142.6" + attribute \src "libresoc.v:80599.3-80635.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:79254.3-79290.6" + attribute \src "libresoc.v:80747.3-80783.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:79291.3-79327.6" + attribute \src "libresoc.v:80784.3-80820.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:79476.3-79512.6" + attribute \src "libresoc.v:80969.3-81005.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:79032.3-79068.6" + attribute \src "libresoc.v:80525.3-80561.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:79587.3-79623.6" + attribute \src "libresoc.v:81080.3-81116.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:79846.3-79882.6" - wire width 2 $0\dec30_out_sel[1:0] - attribute \src "libresoc.v:79143.3-79179.6" + attribute \src "libresoc.v:81339.3-81375.6" + wire width 3 $0\dec30_out_sel[2:0] + attribute \src "libresoc.v:80636.3-80672.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:79439.3-79475.6" + attribute \src "libresoc.v:80932.3-80968.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:79624.3-79660.6" + attribute \src "libresoc.v:81117.3-81153.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:79550.3-79586.6" + attribute \src "libresoc.v:81043.3-81079.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:79402.3-79438.6" + attribute \src "libresoc.v:80895.3-80931.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:78958.3-78994.6" + attribute \src "libresoc.v:80451.3-80487.6" wire width 3 $0\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:78995.3-79031.6" + attribute \src "libresoc.v:80488.3-80524.6" wire width 3 $0\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:78810.3-78846.6" + attribute \src "libresoc.v:80303.3-80339.6" wire width 3 $0\dec30_sv_in1[2:0] - attribute \src "libresoc.v:78847.3-78883.6" + attribute \src "libresoc.v:80340.3-80376.6" wire width 3 $0\dec30_sv_in2[2:0] - attribute \src "libresoc.v:78884.3-78920.6" + attribute \src "libresoc.v:80377.3-80413.6" wire width 3 $0\dec30_sv_in3[2:0] - attribute \src "libresoc.v:78921.3-78957.6" + attribute \src "libresoc.v:80414.3-80450.6" wire width 3 $0\dec30_sv_out[2:0] - attribute \src "libresoc.v:79069.3-79105.6" + attribute \src "libresoc.v:80562.3-80598.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:78364.7-78364.20" + attribute \src "libresoc.v:79854.7-79854.20" wire $0\initial[0:0] - attribute \src "libresoc.v:79661.3-79697.6" + attribute \src "libresoc.v:81154.3-81190.6" wire width 2 $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:79698.3-79734.6" + attribute \src "libresoc.v:81191.3-81227.6" wire width 2 $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:79217.3-79253.6" + attribute \src "libresoc.v:80710.3-80746.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:79365.3-79401.6" + attribute \src "libresoc.v:80858.3-80894.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:78736.3-78772.6" + attribute \src "libresoc.v:80229.3-80265.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:78773.3-78809.6" + attribute \src "libresoc.v:80266.3-80302.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:79180.3-79216.6" + attribute \src "libresoc.v:80673.3-80709.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:79328.3-79364.6" + attribute \src "libresoc.v:80821.3-80857.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:79513.3-79549.6" + attribute \src "libresoc.v:81006.3-81042.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:78699.3-78735.6" - wire width 13 $1\dec30_function_unit[12:0] - attribute \src "libresoc.v:79735.3-79771.6" + attribute \src "libresoc.v:80192.3-80228.6" + wire width 14 $1\dec30_function_unit[13:0] + attribute \src "libresoc.v:81228.3-81264.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:79772.3-79808.6" + attribute \src "libresoc.v:81265.3-81301.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:79809.3-79845.6" + attribute \src "libresoc.v:81302.3-81338.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:79106.3-79142.6" + attribute \src "libresoc.v:80599.3-80635.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:79254.3-79290.6" + attribute \src "libresoc.v:80747.3-80783.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:79291.3-79327.6" + attribute \src "libresoc.v:80784.3-80820.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:79476.3-79512.6" + attribute \src "libresoc.v:80969.3-81005.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:79032.3-79068.6" + attribute \src "libresoc.v:80525.3-80561.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:79587.3-79623.6" + attribute \src "libresoc.v:81080.3-81116.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:79846.3-79882.6" - wire width 2 $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:79143.3-79179.6" + attribute \src "libresoc.v:81339.3-81375.6" + wire width 3 $1\dec30_out_sel[2:0] + attribute \src "libresoc.v:80636.3-80672.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:79439.3-79475.6" + attribute \src "libresoc.v:80932.3-80968.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:79624.3-79660.6" + attribute \src "libresoc.v:81117.3-81153.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:79550.3-79586.6" + attribute \src "libresoc.v:81043.3-81079.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:79402.3-79438.6" + attribute \src "libresoc.v:80895.3-80931.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:78958.3-78994.6" + attribute \src "libresoc.v:80451.3-80487.6" wire width 3 $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:78995.3-79031.6" + attribute \src "libresoc.v:80488.3-80524.6" wire width 3 $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:78810.3-78846.6" + attribute \src "libresoc.v:80303.3-80339.6" wire width 3 $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:78847.3-78883.6" + attribute \src "libresoc.v:80340.3-80376.6" wire width 3 $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:78884.3-78920.6" + attribute \src "libresoc.v:80377.3-80413.6" wire width 3 $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:78921.3-78957.6" + attribute \src "libresoc.v:80414.3-80450.6" wire width 3 $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:79069.3-79105.6" + attribute \src "libresoc.v:80562.3-80598.6" wire width 2 $1\dec30_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -126797,21 +128845,22 @@ module \dec30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec30_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -126917,6 +128966,7 @@ module \dec30 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec30_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -126936,12 +128986,13 @@ module \dec30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec30_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec30_out_sel + wire width 3 output 10 \dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -127017,28 +129068,28 @@ module \dec30 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec30_upd - attribute \src "libresoc.v:78364.7-78364.15" + attribute \src "libresoc.v:79854.7-79854.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 4 \opcode_switch - attribute \src "libresoc.v:78364.7-78364.20" - process $proc$libresoc.v:78364$3763 + attribute \src "libresoc.v:79854.7-79854.20" + process $proc$libresoc.v:79854$3796 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:78699.3-78735.6" - process $proc$libresoc.v:78699$3731 + attribute \src "libresoc.v:80192.3-80228.6" + process $proc$libresoc.v:80192$3764 assign { } { } assign { } { } - assign $0\dec30_function_unit[12:0] $1\dec30_function_unit[12:0] - attribute \src "libresoc.v:78700.5-78700.29" + assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] + attribute \src "libresoc.v:80193.5-80193.29" switch \initial - attribute \src "libresoc.v:78700.9-78700.17" + attribute \src "libresoc.v:80193.9-80193.17" case 1'1 case end @@ -127047,57 +129098,57 @@ module \dec30 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_function_unit[12:0] 13'0000000001000 + assign $1\dec30_function_unit[13:0] 14'00000000001000 case - assign $1\dec30_function_unit[12:0] 13'0000000000000 + assign $1\dec30_function_unit[13:0] 14'00000000000000 end sync always - update \dec30_function_unit $0\dec30_function_unit[12:0] + update \dec30_function_unit $0\dec30_function_unit[13:0] end - attribute \src "libresoc.v:78736.3-78772.6" - process $proc$libresoc.v:78736$3732 + attribute \src "libresoc.v:80229.3-80265.6" + process $proc$libresoc.v:80229$3765 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:78737.5-78737.29" + attribute \src "libresoc.v:80230.5-80230.29" switch \initial - attribute \src "libresoc.v:78737.9-78737.17" + attribute \src "libresoc.v:80230.9-80230.17" case 1'1 case end @@ -127149,14 +129200,14 @@ module \dec30 sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:78773.3-78809.6" - process $proc$libresoc.v:78773$3733 + attribute \src "libresoc.v:80266.3-80302.6" + process $proc$libresoc.v:80266$3766 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:78774.5-78774.29" + attribute \src "libresoc.v:80267.5-80267.29" switch \initial - attribute \src "libresoc.v:78774.9-78774.17" + attribute \src "libresoc.v:80267.9-80267.17" case 1'1 case end @@ -127208,14 +129259,14 @@ module \dec30 sync always update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "libresoc.v:78810.3-78846.6" - process $proc$libresoc.v:78810$3734 + attribute \src "libresoc.v:80303.3-80339.6" + process $proc$libresoc.v:80303$3767 assign { } { } assign { } { } assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:78811.5-78811.29" + attribute \src "libresoc.v:80304.5-80304.29" switch \initial - attribute \src "libresoc.v:78811.9-78811.17" + attribute \src "libresoc.v:80304.9-80304.17" case 1'1 case end @@ -127267,14 +129318,14 @@ module \dec30 sync always update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end - attribute \src "libresoc.v:78847.3-78883.6" - process $proc$libresoc.v:78847$3735 + attribute \src "libresoc.v:80340.3-80376.6" + process $proc$libresoc.v:80340$3768 assign { } { } assign { } { } assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:78848.5-78848.29" + attribute \src "libresoc.v:80341.5-80341.29" switch \initial - attribute \src "libresoc.v:78848.9-78848.17" + attribute \src "libresoc.v:80341.9-80341.17" case 1'1 case end @@ -127326,14 +129377,14 @@ module \dec30 sync always update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end - attribute \src "libresoc.v:78884.3-78920.6" - process $proc$libresoc.v:78884$3736 + attribute \src "libresoc.v:80377.3-80413.6" + process $proc$libresoc.v:80377$3769 assign { } { } assign { } { } assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:78885.5-78885.29" + attribute \src "libresoc.v:80378.5-80378.29" switch \initial - attribute \src "libresoc.v:78885.9-78885.17" + attribute \src "libresoc.v:80378.9-80378.17" case 1'1 case end @@ -127385,14 +129436,14 @@ module \dec30 sync always update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end - attribute \src "libresoc.v:78921.3-78957.6" - process $proc$libresoc.v:78921$3737 + attribute \src "libresoc.v:80414.3-80450.6" + process $proc$libresoc.v:80414$3770 assign { } { } assign { } { } assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:78922.5-78922.29" + attribute \src "libresoc.v:80415.5-80415.29" switch \initial - attribute \src "libresoc.v:78922.9-78922.17" + attribute \src "libresoc.v:80415.9-80415.17" case 1'1 case end @@ -127444,14 +129495,14 @@ module \dec30 sync always update \dec30_sv_out $0\dec30_sv_out[2:0] end - attribute \src "libresoc.v:78958.3-78994.6" - process $proc$libresoc.v:78958$3738 + attribute \src "libresoc.v:80451.3-80487.6" + process $proc$libresoc.v:80451$3771 assign { } { } assign { } { } assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:78959.5-78959.29" + attribute \src "libresoc.v:80452.5-80452.29" switch \initial - attribute \src "libresoc.v:78959.9-78959.17" + attribute \src "libresoc.v:80452.9-80452.17" case 1'1 case end @@ -127503,14 +129554,14 @@ module \dec30 sync always update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end - attribute \src "libresoc.v:78995.3-79031.6" - process $proc$libresoc.v:78995$3739 + attribute \src "libresoc.v:80488.3-80524.6" + process $proc$libresoc.v:80488$3772 assign { } { } assign { } { } assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:78996.5-78996.29" + attribute \src "libresoc.v:80489.5-80489.29" switch \initial - attribute \src "libresoc.v:78996.9-78996.17" + attribute \src "libresoc.v:80489.9-80489.17" case 1'1 case end @@ -127562,14 +129613,14 @@ module \dec30 sync always update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end - attribute \src "libresoc.v:79032.3-79068.6" - process $proc$libresoc.v:79032$3740 + attribute \src "libresoc.v:80525.3-80561.6" + process $proc$libresoc.v:80525$3773 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:79033.5-79033.29" + attribute \src "libresoc.v:80526.5-80526.29" switch \initial - attribute \src "libresoc.v:79033.9-79033.17" + attribute \src "libresoc.v:80526.9-80526.17" case 1'1 case end @@ -127621,14 +129672,14 @@ module \dec30 sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:79069.3-79105.6" - process $proc$libresoc.v:79069$3741 + attribute \src "libresoc.v:80562.3-80598.6" + process $proc$libresoc.v:80562$3774 assign { } { } assign { } { } assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:79070.5-79070.29" + attribute \src "libresoc.v:80563.5-80563.29" switch \initial - attribute \src "libresoc.v:79070.9-79070.17" + attribute \src "libresoc.v:80563.9-80563.17" case 1'1 case end @@ -127680,14 +129731,14 @@ module \dec30 sync always update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:79106.3-79142.6" - process $proc$libresoc.v:79106$3742 + attribute \src "libresoc.v:80599.3-80635.6" + process $proc$libresoc.v:80599$3775 assign { } { } assign { } { } assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:79107.5-79107.29" + attribute \src "libresoc.v:80600.5-80600.29" switch \initial - attribute \src "libresoc.v:79107.9-79107.17" + attribute \src "libresoc.v:80600.9-80600.17" case 1'1 case end @@ -127739,14 +129790,14 @@ module \dec30 sync always update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:79143.3-79179.6" - process $proc$libresoc.v:79143$3743 + attribute \src "libresoc.v:80636.3-80672.6" + process $proc$libresoc.v:80636$3776 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:79144.5-79144.29" + attribute \src "libresoc.v:80637.5-80637.29" switch \initial - attribute \src "libresoc.v:79144.9-79144.17" + attribute \src "libresoc.v:80637.9-80637.17" case 1'1 case end @@ -127798,14 +129849,14 @@ module \dec30 sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:79180.3-79216.6" - process $proc$libresoc.v:79180$3744 + attribute \src "libresoc.v:80673.3-80709.6" + process $proc$libresoc.v:80673$3777 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:79181.5-79181.29" + attribute \src "libresoc.v:80674.5-80674.29" switch \initial - attribute \src "libresoc.v:79181.9-79181.17" + attribute \src "libresoc.v:80674.9-80674.17" case 1'1 case end @@ -127857,14 +129908,14 @@ module \dec30 sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:79217.3-79253.6" - process $proc$libresoc.v:79217$3745 + attribute \src "libresoc.v:80710.3-80746.6" + process $proc$libresoc.v:80710$3778 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:79218.5-79218.29" + attribute \src "libresoc.v:80711.5-80711.29" switch \initial - attribute \src "libresoc.v:79218.9-79218.17" + attribute \src "libresoc.v:80711.9-80711.17" case 1'1 case end @@ -127916,14 +129967,14 @@ module \dec30 sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:79254.3-79290.6" - process $proc$libresoc.v:79254$3746 + attribute \src "libresoc.v:80747.3-80783.6" + process $proc$libresoc.v:80747$3779 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:79255.5-79255.29" + attribute \src "libresoc.v:80748.5-80748.29" switch \initial - attribute \src "libresoc.v:79255.9-79255.17" + attribute \src "libresoc.v:80748.9-80748.17" case 1'1 case end @@ -127975,14 +130026,14 @@ module \dec30 sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:79291.3-79327.6" - process $proc$libresoc.v:79291$3747 + attribute \src "libresoc.v:80784.3-80820.6" + process $proc$libresoc.v:80784$3780 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:79292.5-79292.29" + attribute \src "libresoc.v:80785.5-80785.29" switch \initial - attribute \src "libresoc.v:79292.9-79292.17" + attribute \src "libresoc.v:80785.9-80785.17" case 1'1 case end @@ -128034,14 +130085,14 @@ module \dec30 sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:79328.3-79364.6" - process $proc$libresoc.v:79328$3748 + attribute \src "libresoc.v:80821.3-80857.6" + process $proc$libresoc.v:80821$3781 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:79329.5-79329.29" + attribute \src "libresoc.v:80822.5-80822.29" switch \initial - attribute \src "libresoc.v:79329.9-79329.17" + attribute \src "libresoc.v:80822.9-80822.17" case 1'1 case end @@ -128093,14 +130144,14 @@ module \dec30 sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:79365.3-79401.6" - process $proc$libresoc.v:79365$3749 + attribute \src "libresoc.v:80858.3-80894.6" + process $proc$libresoc.v:80858$3782 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:79366.5-79366.29" + attribute \src "libresoc.v:80859.5-80859.29" switch \initial - attribute \src "libresoc.v:79366.9-79366.17" + attribute \src "libresoc.v:80859.9-80859.17" case 1'1 case end @@ -128152,14 +130203,14 @@ module \dec30 sync always update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:79402.3-79438.6" - process $proc$libresoc.v:79402$3750 + attribute \src "libresoc.v:80895.3-80931.6" + process $proc$libresoc.v:80895$3783 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:79403.5-79403.29" + attribute \src "libresoc.v:80896.5-80896.29" switch \initial - attribute \src "libresoc.v:79403.9-79403.17" + attribute \src "libresoc.v:80896.9-80896.17" case 1'1 case end @@ -128211,14 +130262,14 @@ module \dec30 sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:79439.3-79475.6" - process $proc$libresoc.v:79439$3751 + attribute \src "libresoc.v:80932.3-80968.6" + process $proc$libresoc.v:80932$3784 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:79440.5-79440.29" + attribute \src "libresoc.v:80933.5-80933.29" switch \initial - attribute \src "libresoc.v:79440.9-79440.17" + attribute \src "libresoc.v:80933.9-80933.17" case 1'1 case end @@ -128270,14 +130321,14 @@ module \dec30 sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:79476.3-79512.6" - process $proc$libresoc.v:79476$3752 + attribute \src "libresoc.v:80969.3-81005.6" + process $proc$libresoc.v:80969$3785 assign { } { } assign { } { } assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:79477.5-79477.29" + attribute \src "libresoc.v:80970.5-80970.29" switch \initial - attribute \src "libresoc.v:79477.9-79477.17" + attribute \src "libresoc.v:80970.9-80970.17" case 1'1 case end @@ -128329,14 +130380,14 @@ module \dec30 sync always update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:79513.3-79549.6" - process $proc$libresoc.v:79513$3753 + attribute \src "libresoc.v:81006.3-81042.6" + process $proc$libresoc.v:81006$3786 assign { } { } assign { } { } assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:79514.5-79514.29" + attribute \src "libresoc.v:81007.5-81007.29" switch \initial - attribute \src "libresoc.v:79514.9-79514.17" + attribute \src "libresoc.v:81007.9-81007.17" case 1'1 case end @@ -128388,14 +130439,14 @@ module \dec30 sync always update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:79550.3-79586.6" - process $proc$libresoc.v:79550$3754 + attribute \src "libresoc.v:81043.3-81079.6" + process $proc$libresoc.v:81043$3787 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:79551.5-79551.29" + attribute \src "libresoc.v:81044.5-81044.29" switch \initial - attribute \src "libresoc.v:79551.9-79551.17" + attribute \src "libresoc.v:81044.9-81044.17" case 1'1 case end @@ -128447,14 +130498,14 @@ module \dec30 sync always update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "libresoc.v:79587.3-79623.6" - process $proc$libresoc.v:79587$3755 + attribute \src "libresoc.v:81080.3-81116.6" + process $proc$libresoc.v:81080$3788 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:79588.5-79588.29" + attribute \src "libresoc.v:81081.5-81081.29" switch \initial - attribute \src "libresoc.v:79588.9-79588.17" + attribute \src "libresoc.v:81081.9-81081.17" case 1'1 case end @@ -128506,14 +130557,14 @@ module \dec30 sync always update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "libresoc.v:79624.3-79660.6" - process $proc$libresoc.v:79624$3756 + attribute \src "libresoc.v:81117.3-81153.6" + process $proc$libresoc.v:81117$3789 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:79625.5-79625.29" + attribute \src "libresoc.v:81118.5-81118.29" switch \initial - attribute \src "libresoc.v:79625.9-79625.17" + attribute \src "libresoc.v:81118.9-81118.17" case 1'1 case end @@ -128565,14 +130616,14 @@ module \dec30 sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "libresoc.v:79661.3-79697.6" - process $proc$libresoc.v:79661$3757 + attribute \src "libresoc.v:81154.3-81190.6" + process $proc$libresoc.v:81154$3790 assign { } { } assign { } { } assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:79662.5-79662.29" + attribute \src "libresoc.v:81155.5-81155.29" switch \initial - attribute \src "libresoc.v:79662.9-79662.17" + attribute \src "libresoc.v:81155.9-81155.17" case 1'1 case end @@ -128624,14 +130675,14 @@ module \dec30 sync always update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] end - attribute \src "libresoc.v:79698.3-79734.6" - process $proc$libresoc.v:79698$3758 + attribute \src "libresoc.v:81191.3-81227.6" + process $proc$libresoc.v:81191$3791 assign { } { } assign { } { } assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:79699.5-79699.29" + attribute \src "libresoc.v:81192.5-81192.29" switch \initial - attribute \src "libresoc.v:79699.9-79699.17" + attribute \src "libresoc.v:81192.9-81192.17" case 1'1 case end @@ -128683,14 +130734,14 @@ module \dec30 sync always update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] end - attribute \src "libresoc.v:79735.3-79771.6" - process $proc$libresoc.v:79735$3759 + attribute \src "libresoc.v:81228.3-81264.6" + process $proc$libresoc.v:81228$3792 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:79736.5-79736.29" + attribute \src "libresoc.v:81229.5-81229.29" switch \initial - attribute \src "libresoc.v:79736.9-79736.17" + attribute \src "libresoc.v:81229.9-81229.17" case 1'1 case end @@ -128742,14 +130793,14 @@ module \dec30 sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "libresoc.v:79772.3-79808.6" - process $proc$libresoc.v:79772$3760 + attribute \src "libresoc.v:81265.3-81301.6" + process $proc$libresoc.v:81265$3793 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:79773.5-79773.29" + attribute \src "libresoc.v:81266.5-81266.29" switch \initial - attribute \src "libresoc.v:79773.9-79773.17" + attribute \src "libresoc.v:81266.9-81266.17" case 1'1 case end @@ -128801,14 +130852,14 @@ module \dec30 sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "libresoc.v:79809.3-79845.6" - process $proc$libresoc.v:79809$3761 + attribute \src "libresoc.v:81302.3-81338.6" + process $proc$libresoc.v:81302$3794 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:79810.5-79810.29" + attribute \src "libresoc.v:81303.5-81303.29" switch \initial - attribute \src "libresoc.v:79810.9-79810.17" + attribute \src "libresoc.v:81303.9-81303.17" case 1'1 case end @@ -128860,14 +130911,14 @@ module \dec30 sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "libresoc.v:79846.3-79882.6" - process $proc$libresoc.v:79846$3762 + attribute \src "libresoc.v:81339.3-81375.6" + process $proc$libresoc.v:81339$3795 assign { } { } assign { } { } - assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:79847.5-79847.29" + assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] + attribute \src "libresoc.v:81340.5-81340.29" switch \initial - attribute \src "libresoc.v:79847.9-79847.17" + attribute \src "libresoc.v:81340.9-81340.17" case 1'1 case end @@ -128876,185 +130927,185 @@ module \dec30 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 + assign $1\dec30_out_sel[2:0] 3'010 case - assign $1\dec30_out_sel[1:0] 2'00 + assign $1\dec30_out_sel[2:0] 3'000 end sync always - update \dec30_out_sel $0\dec30_out_sel[1:0] + update \dec30_out_sel $0\dec30_out_sel[2:0] end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:79888.1-88228.10" +attribute \src "libresoc.v:81381.1-89778.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:86500.3-86560.6" + attribute \src "libresoc.v:88050.3-88110.6" wire width 2 $0\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:86561.3-86621.6" + attribute \src "libresoc.v:88111.3-88171.6" wire width 2 $0\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:86439.3-86499.6" + attribute \src "libresoc.v:87989.3-88049.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:87781.3-87841.6" + attribute \src "libresoc.v:89331.3-89391.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:86866.3-86926.6" + attribute \src "libresoc.v:88416.3-88476.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:86927.3-86987.6" + attribute \src "libresoc.v:88477.3-88537.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:87537.3-87597.6" + attribute \src "libresoc.v:89087.3-89147.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:87720.3-87780.6" + attribute \src "libresoc.v:89270.3-89330.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:86378.3-86438.6" + attribute \src "libresoc.v:87928.3-87988.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:86256.3-86316.6" - wire width 13 $0\dec31_function_unit[12:0] - attribute \src "libresoc.v:86622.3-86682.6" + attribute \src "libresoc.v:87806.3-87866.6" + wire width 14 $0\dec31_function_unit[13:0] + attribute \src "libresoc.v:88172.3-88232.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:86683.3-86743.6" + attribute \src "libresoc.v:88233.3-88293.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:86744.3-86804.6" + attribute \src "libresoc.v:88294.3-88354.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:86317.3-86377.6" + attribute \src "libresoc.v:87867.3-87927.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:87598.3-87658.6" + attribute \src "libresoc.v:89148.3-89208.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:87659.3-87719.6" + attribute \src "libresoc.v:89209.3-89269.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:87964.3-88024.6" + attribute \src "libresoc.v:89514.3-89574.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:87354.3-87414.6" + attribute \src "libresoc.v:88904.3-88964.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:88086.3-88146.6" + attribute \src "libresoc.v:89636.3-89696.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:86805.3-86865.6" - wire width 2 $0\dec31_out_sel[1:0] - attribute \src "libresoc.v:87476.3-87536.6" + attribute \src "libresoc.v:88355.3-88415.6" + wire width 3 $0\dec31_out_sel[2:0] + attribute \src "libresoc.v:89026.3-89086.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:87903.3-87963.6" + attribute \src "libresoc.v:89453.3-89513.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:88147.3-88207.6" + attribute \src "libresoc.v:89697.3-89757.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:88025.3-88085.6" + attribute \src "libresoc.v:89575.3-89635.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:87842.3-87902.6" + attribute \src "libresoc.v:89392.3-89452.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:87232.3-87292.6" + attribute \src "libresoc.v:88782.3-88842.6" wire width 3 $0\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:87293.3-87353.6" + attribute \src "libresoc.v:88843.3-88903.6" wire width 3 $0\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:86988.3-87048.6" + attribute \src "libresoc.v:88538.3-88598.6" wire width 3 $0\dec31_sv_in1[2:0] - attribute \src "libresoc.v:87049.3-87109.6" + attribute \src "libresoc.v:88599.3-88659.6" wire width 3 $0\dec31_sv_in2[2:0] - attribute \src "libresoc.v:87110.3-87170.6" + attribute \src "libresoc.v:88660.3-88720.6" wire width 3 $0\dec31_sv_in3[2:0] - attribute \src "libresoc.v:87171.3-87231.6" + attribute \src "libresoc.v:88721.3-88781.6" wire width 3 $0\dec31_sv_out[2:0] - attribute \src "libresoc.v:87415.3-87475.6" + attribute \src "libresoc.v:88965.3-89025.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:79889.7-79889.20" + attribute \src "libresoc.v:81382.7-81382.20" wire $0\initial[0:0] - attribute \src "libresoc.v:86500.3-86560.6" + attribute \src "libresoc.v:88050.3-88110.6" wire width 2 $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:86561.3-86621.6" + attribute \src "libresoc.v:88111.3-88171.6" wire width 2 $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:86439.3-86499.6" + attribute \src "libresoc.v:87989.3-88049.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:87781.3-87841.6" + attribute \src "libresoc.v:89331.3-89391.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:86866.3-86926.6" + attribute \src "libresoc.v:88416.3-88476.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:86927.3-86987.6" + attribute \src "libresoc.v:88477.3-88537.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:87537.3-87597.6" + attribute \src "libresoc.v:89087.3-89147.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:87720.3-87780.6" + attribute \src "libresoc.v:89270.3-89330.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:86378.3-86438.6" + attribute \src "libresoc.v:87928.3-87988.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:86256.3-86316.6" - wire width 13 $1\dec31_function_unit[12:0] - attribute \src "libresoc.v:86622.3-86682.6" + attribute \src "libresoc.v:87806.3-87866.6" + wire width 14 $1\dec31_function_unit[13:0] + attribute \src "libresoc.v:88172.3-88232.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:86683.3-86743.6" + attribute \src "libresoc.v:88233.3-88293.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:86744.3-86804.6" + attribute \src "libresoc.v:88294.3-88354.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:86317.3-86377.6" + attribute \src "libresoc.v:87867.3-87927.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:87598.3-87658.6" + attribute \src "libresoc.v:89148.3-89208.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:87659.3-87719.6" + attribute \src "libresoc.v:89209.3-89269.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:87964.3-88024.6" + attribute \src "libresoc.v:89514.3-89574.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:87354.3-87414.6" + attribute \src "libresoc.v:88904.3-88964.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:88086.3-88146.6" + attribute \src "libresoc.v:89636.3-89696.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:86805.3-86865.6" - wire width 2 $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:87476.3-87536.6" + attribute \src "libresoc.v:88355.3-88415.6" + wire width 3 $1\dec31_out_sel[2:0] + attribute \src "libresoc.v:89026.3-89086.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:87903.3-87963.6" + attribute \src "libresoc.v:89453.3-89513.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:88147.3-88207.6" + attribute \src "libresoc.v:89697.3-89757.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:88025.3-88085.6" + attribute \src "libresoc.v:89575.3-89635.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:87842.3-87902.6" + attribute \src "libresoc.v:89392.3-89452.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:87232.3-87292.6" + attribute \src "libresoc.v:88782.3-88842.6" wire width 3 $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:87293.3-87353.6" + attribute \src "libresoc.v:88843.3-88903.6" wire width 3 $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:86988.3-87048.6" + attribute \src "libresoc.v:88538.3-88598.6" wire width 3 $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:87049.3-87109.6" + attribute \src "libresoc.v:88599.3-88659.6" wire width 3 $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:87110.3-87170.6" + attribute \src "libresoc.v:88660.3-88720.6" wire width 3 $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:87171.3-87231.6" + attribute \src "libresoc.v:88721.3-88781.6" wire width 3 $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:87415.3-87475.6" + attribute \src "libresoc.v:88965.3-89025.6" wire width 2 $1\dec31_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -129178,21 +131229,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -129298,6 +131350,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -129317,12 +131370,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub0_dec31_dec_sub0_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -129478,21 +131532,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -129598,6 +131653,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -129617,12 +131673,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub10_dec31_dec_sub10_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -129778,21 +131835,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub11_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -129898,6 +131956,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -129917,12 +131976,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub11_dec31_dec_sub11_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -130078,21 +132138,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -130198,6 +132259,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -130217,12 +132279,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub15_dec31_dec_sub15_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -130378,21 +132441,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -130498,6 +132562,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -130517,12 +132582,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub16_dec31_dec_sub16_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -130678,21 +132744,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub18_dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -130798,6 +132865,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -130817,12 +132885,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub18_dec31_dec_sub18_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -130978,21 +133047,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub19_dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -131098,6 +133168,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -131117,12 +133188,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub19_dec31_dec_sub19_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -131278,21 +133350,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub20_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -131398,6 +133471,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -131417,12 +133491,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub20_dec31_dec_sub20_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -131578,21 +133653,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub21_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -131698,6 +133774,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -131717,12 +133794,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub21_dec31_dec_sub21_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -131878,21 +133956,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub22_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -131998,6 +134077,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -132017,12 +134097,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub22_dec31_dec_sub22_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -132178,21 +134259,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub23_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -132298,6 +134380,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -132317,12 +134400,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub23_dec31_dec_sub23_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -132478,21 +134562,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub24_dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -132598,6 +134683,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -132617,12 +134703,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub24_dec31_dec_sub24_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -132778,21 +134865,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub26_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -132898,6 +134986,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -132917,12 +135006,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub26_dec31_dec_sub26_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -133078,21 +135168,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub27_dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -133198,6 +135289,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -133217,12 +135309,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub27_dec31_dec_sub27_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -133378,21 +135471,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub28_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -133498,6 +135592,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -133517,12 +135612,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub28_dec31_dec_sub28_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -133678,21 +135774,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub4_dec31_dec_sub4_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub4_dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -133798,6 +135895,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -133817,12 +135915,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub4_dec31_dec_sub4_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -133978,21 +136077,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub8_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -134098,6 +136198,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -134117,12 +136218,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub8_dec31_dec_sub8_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -134278,21 +136380,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec31_dec_sub9_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -134398,6 +136501,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -134417,12 +136521,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec31_dec_sub9_dec31_dec_sub9_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -134534,21 +136639,22 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -134654,6 +136760,7 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -134673,12 +136780,13 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_out_sel + wire width 3 output 10 \dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -134754,7 +136862,7 @@ module \dec31 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_upd - attribute \src "libresoc.v:79889.7-79889.15" + attribute \src "libresoc.v:81382.7-81382.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -134763,7 +136871,7 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:85626.18-85660.4" + attribute \src "libresoc.v:87176.18-87210.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype @@ -134800,7 +136908,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85661.19-85695.4" + attribute \src "libresoc.v:87211.19-87245.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype @@ -134837,7 +136945,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85696.19-85730.4" + attribute \src "libresoc.v:87246.19-87280.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype @@ -134874,7 +136982,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85731.19-85765.4" + attribute \src "libresoc.v:87281.19-87315.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype @@ -134911,7 +137019,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85766.19-85800.4" + attribute \src "libresoc.v:87316.19-87350.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype @@ -134948,7 +137056,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85801.19-85835.4" + attribute \src "libresoc.v:87351.19-87385.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype @@ -134985,7 +137093,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85836.19-85870.4" + attribute \src "libresoc.v:87386.19-87420.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype @@ -135022,7 +137130,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85871.19-85905.4" + attribute \src "libresoc.v:87421.19-87455.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype @@ -135059,7 +137167,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85906.19-85940.4" + attribute \src "libresoc.v:87456.19-87490.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype @@ -135096,7 +137204,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85941.19-85975.4" + attribute \src "libresoc.v:87491.19-87525.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype @@ -135133,7 +137241,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:85976.19-86010.4" + attribute \src "libresoc.v:87526.19-87560.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype @@ -135170,7 +137278,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86011.19-86045.4" + attribute \src "libresoc.v:87561.19-87595.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype @@ -135207,7 +137315,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86046.19-86080.4" + attribute \src "libresoc.v:87596.19-87630.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype @@ -135244,7 +137352,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86081.19-86115.4" + attribute \src "libresoc.v:87631.19-87665.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype @@ -135281,7 +137389,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86116.19-86150.4" + attribute \src "libresoc.v:87666.19-87700.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype @@ -135318,7 +137426,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86151.18-86185.4" + attribute \src "libresoc.v:87701.18-87735.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype @@ -135355,7 +137463,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86186.18-86220.4" + attribute \src "libresoc.v:87736.18-87770.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype @@ -135392,7 +137500,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86221.18-86255.4" + attribute \src "libresoc.v:87771.18-87805.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype @@ -135428,22 +137536,22 @@ module \dec31 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:79889.7-79889.20" - process $proc$libresoc.v:79889$3796 + attribute \src "libresoc.v:81382.7-81382.20" + process $proc$libresoc.v:81382$3829 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:86256.3-86316.6" - process $proc$libresoc.v:86256$3764 + attribute \src "libresoc.v:87806.3-87866.6" + process $proc$libresoc.v:87806$3797 assign { } { } assign { } { } - assign $0\dec31_function_unit[12:0] $1\dec31_function_unit[12:0] - attribute \src "libresoc.v:86257.5-86257.29" + assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] + attribute \src "libresoc.v:87807.5-87807.29" switch \initial - attribute \src "libresoc.v:86257.9-86257.17" + attribute \src "libresoc.v:87807.9-87807.17" case 1'1 case end @@ -135452,89 +137560,89 @@ module \dec31 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_function_unit[12:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + assign $1\dec31_function_unit[13:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit case - assign $1\dec31_function_unit[12:0] 13'0000000000000 + assign $1\dec31_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_function_unit $0\dec31_function_unit[12:0] + update \dec31_function_unit $0\dec31_function_unit[13:0] end - attribute \src "libresoc.v:86317.3-86377.6" - process $proc$libresoc.v:86317$3765 + attribute \src "libresoc.v:87867.3-87927.6" + process $proc$libresoc.v:87867$3798 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:86318.5-86318.29" + attribute \src "libresoc.v:87868.5-87868.29" switch \initial - attribute \src "libresoc.v:86318.9-86318.17" + attribute \src "libresoc.v:87868.9-87868.17" case 1'1 case end @@ -135618,14 +137726,14 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:86378.3-86438.6" - process $proc$libresoc.v:86378$3766 + attribute \src "libresoc.v:87928.3-87988.6" + process $proc$libresoc.v:87928$3799 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:86379.5-86379.29" + attribute \src "libresoc.v:87929.5-87929.29" switch \initial - attribute \src "libresoc.v:86379.9-86379.17" + attribute \src "libresoc.v:87929.9-87929.17" case 1'1 case end @@ -135709,14 +137817,14 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:86439.3-86499.6" - process $proc$libresoc.v:86439$3767 + attribute \src "libresoc.v:87989.3-88049.6" + process $proc$libresoc.v:87989$3800 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:86440.5-86440.29" + attribute \src "libresoc.v:87990.5-87990.29" switch \initial - attribute \src "libresoc.v:86440.9-86440.17" + attribute \src "libresoc.v:87990.9-87990.17" case 1'1 case end @@ -135800,14 +137908,14 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:86500.3-86560.6" - process $proc$libresoc.v:86500$3768 + attribute \src "libresoc.v:88050.3-88110.6" + process $proc$libresoc.v:88050$3801 assign { } { } assign { } { } assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:86501.5-86501.29" + attribute \src "libresoc.v:88051.5-88051.29" switch \initial - attribute \src "libresoc.v:86501.9-86501.17" + attribute \src "libresoc.v:88051.9-88051.17" case 1'1 case end @@ -135891,14 +137999,14 @@ module \dec31 sync always update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] end - attribute \src "libresoc.v:86561.3-86621.6" - process $proc$libresoc.v:86561$3769 + attribute \src "libresoc.v:88111.3-88171.6" + process $proc$libresoc.v:88111$3802 assign { } { } assign { } { } assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:86562.5-86562.29" + attribute \src "libresoc.v:88112.5-88112.29" switch \initial - attribute \src "libresoc.v:86562.9-86562.17" + attribute \src "libresoc.v:88112.9-88112.17" case 1'1 case end @@ -135982,14 +138090,14 @@ module \dec31 sync always update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] end - attribute \src "libresoc.v:86622.3-86682.6" - process $proc$libresoc.v:86622$3770 + attribute \src "libresoc.v:88172.3-88232.6" + process $proc$libresoc.v:88172$3803 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:86623.5-86623.29" + attribute \src "libresoc.v:88173.5-88173.29" switch \initial - attribute \src "libresoc.v:86623.9-86623.17" + attribute \src "libresoc.v:88173.9-88173.17" case 1'1 case end @@ -136073,14 +138181,14 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:86683.3-86743.6" - process $proc$libresoc.v:86683$3771 + attribute \src "libresoc.v:88233.3-88293.6" + process $proc$libresoc.v:88233$3804 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:86684.5-86684.29" + attribute \src "libresoc.v:88234.5-88234.29" switch \initial - attribute \src "libresoc.v:86684.9-86684.17" + attribute \src "libresoc.v:88234.9-88234.17" case 1'1 case end @@ -136164,14 +138272,14 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:86744.3-86804.6" - process $proc$libresoc.v:86744$3772 + attribute \src "libresoc.v:88294.3-88354.6" + process $proc$libresoc.v:88294$3805 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:86745.5-86745.29" + attribute \src "libresoc.v:88295.5-88295.29" switch \initial - attribute \src "libresoc.v:86745.9-86745.17" + attribute \src "libresoc.v:88295.9-88295.17" case 1'1 case end @@ -136255,14 +138363,14 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:86805.3-86865.6" - process $proc$libresoc.v:86805$3773 + attribute \src "libresoc.v:88355.3-88415.6" + process $proc$libresoc.v:88355$3806 assign { } { } assign { } { } - assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:86806.5-86806.29" + assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] + attribute \src "libresoc.v:88356.5-88356.29" switch \initial - attribute \src "libresoc.v:86806.9-86806.17" + attribute \src "libresoc.v:88356.9-88356.17" case 1'1 case end @@ -136271,89 +138379,89 @@ module \dec31 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + assign $1\dec31_out_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel case - assign $1\dec31_out_sel[1:0] 2'00 + assign $1\dec31_out_sel[2:0] 3'000 end sync always - update \dec31_out_sel $0\dec31_out_sel[1:0] + update \dec31_out_sel $0\dec31_out_sel[2:0] end - attribute \src "libresoc.v:86866.3-86926.6" - process $proc$libresoc.v:86866$3774 + attribute \src "libresoc.v:88416.3-88476.6" + process $proc$libresoc.v:88416$3807 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:86867.5-86867.29" + attribute \src "libresoc.v:88417.5-88417.29" switch \initial - attribute \src "libresoc.v:86867.9-86867.17" + attribute \src "libresoc.v:88417.9-88417.17" case 1'1 case end @@ -136437,14 +138545,14 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:86927.3-86987.6" - process $proc$libresoc.v:86927$3775 + attribute \src "libresoc.v:88477.3-88537.6" + process $proc$libresoc.v:88477$3808 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:86928.5-86928.29" + attribute \src "libresoc.v:88478.5-88478.29" switch \initial - attribute \src "libresoc.v:86928.9-86928.17" + attribute \src "libresoc.v:88478.9-88478.17" case 1'1 case end @@ -136528,14 +138636,14 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:86988.3-87048.6" - process $proc$libresoc.v:86988$3776 + attribute \src "libresoc.v:88538.3-88598.6" + process $proc$libresoc.v:88538$3809 assign { } { } assign { } { } assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:86989.5-86989.29" + attribute \src "libresoc.v:88539.5-88539.29" switch \initial - attribute \src "libresoc.v:86989.9-86989.17" + attribute \src "libresoc.v:88539.9-88539.17" case 1'1 case end @@ -136619,14 +138727,14 @@ module \dec31 sync always update \dec31_sv_in1 $0\dec31_sv_in1[2:0] end - attribute \src "libresoc.v:87049.3-87109.6" - process $proc$libresoc.v:87049$3777 + attribute \src "libresoc.v:88599.3-88659.6" + process $proc$libresoc.v:88599$3810 assign { } { } assign { } { } assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:87050.5-87050.29" + attribute \src "libresoc.v:88600.5-88600.29" switch \initial - attribute \src "libresoc.v:87050.9-87050.17" + attribute \src "libresoc.v:88600.9-88600.17" case 1'1 case end @@ -136710,14 +138818,14 @@ module \dec31 sync always update \dec31_sv_in2 $0\dec31_sv_in2[2:0] end - attribute \src "libresoc.v:87110.3-87170.6" - process $proc$libresoc.v:87110$3778 + attribute \src "libresoc.v:88660.3-88720.6" + process $proc$libresoc.v:88660$3811 assign { } { } assign { } { } assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:87111.5-87111.29" + attribute \src "libresoc.v:88661.5-88661.29" switch \initial - attribute \src "libresoc.v:87111.9-87111.17" + attribute \src "libresoc.v:88661.9-88661.17" case 1'1 case end @@ -136801,14 +138909,14 @@ module \dec31 sync always update \dec31_sv_in3 $0\dec31_sv_in3[2:0] end - attribute \src "libresoc.v:87171.3-87231.6" - process $proc$libresoc.v:87171$3779 + attribute \src "libresoc.v:88721.3-88781.6" + process $proc$libresoc.v:88721$3812 assign { } { } assign { } { } assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:87172.5-87172.29" + attribute \src "libresoc.v:88722.5-88722.29" switch \initial - attribute \src "libresoc.v:87172.9-87172.17" + attribute \src "libresoc.v:88722.9-88722.17" case 1'1 case end @@ -136892,14 +139000,14 @@ module \dec31 sync always update \dec31_sv_out $0\dec31_sv_out[2:0] end - attribute \src "libresoc.v:87232.3-87292.6" - process $proc$libresoc.v:87232$3780 + attribute \src "libresoc.v:88782.3-88842.6" + process $proc$libresoc.v:88782$3813 assign { } { } assign { } { } assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:87233.5-87233.29" + attribute \src "libresoc.v:88783.5-88783.29" switch \initial - attribute \src "libresoc.v:87233.9-87233.17" + attribute \src "libresoc.v:88783.9-88783.17" case 1'1 case end @@ -136983,14 +139091,14 @@ module \dec31 sync always update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] end - attribute \src "libresoc.v:87293.3-87353.6" - process $proc$libresoc.v:87293$3781 + attribute \src "libresoc.v:88843.3-88903.6" + process $proc$libresoc.v:88843$3814 assign { } { } assign { } { } assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:87294.5-87294.29" + attribute \src "libresoc.v:88844.5-88844.29" switch \initial - attribute \src "libresoc.v:87294.9-87294.17" + attribute \src "libresoc.v:88844.9-88844.17" case 1'1 case end @@ -137074,14 +139182,14 @@ module \dec31 sync always update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] end - attribute \src "libresoc.v:87354.3-87414.6" - process $proc$libresoc.v:87354$3782 + attribute \src "libresoc.v:88904.3-88964.6" + process $proc$libresoc.v:88904$3815 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:87355.5-87355.29" + attribute \src "libresoc.v:88905.5-88905.29" switch \initial - attribute \src "libresoc.v:87355.9-87355.17" + attribute \src "libresoc.v:88905.9-88905.17" case 1'1 case end @@ -137165,14 +139273,14 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:87415.3-87475.6" - process $proc$libresoc.v:87415$3783 + attribute \src "libresoc.v:88965.3-89025.6" + process $proc$libresoc.v:88965$3816 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:87416.5-87416.29" + attribute \src "libresoc.v:88966.5-88966.29" switch \initial - attribute \src "libresoc.v:87416.9-87416.17" + attribute \src "libresoc.v:88966.9-88966.17" case 1'1 case end @@ -137256,14 +139364,14 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:87476.3-87536.6" - process $proc$libresoc.v:87476$3784 + attribute \src "libresoc.v:89026.3-89086.6" + process $proc$libresoc.v:89026$3817 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:87477.5-87477.29" + attribute \src "libresoc.v:89027.5-89027.29" switch \initial - attribute \src "libresoc.v:87477.9-87477.17" + attribute \src "libresoc.v:89027.9-89027.17" case 1'1 case end @@ -137347,14 +139455,14 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:87537.3-87597.6" - process $proc$libresoc.v:87537$3785 + attribute \src "libresoc.v:89087.3-89147.6" + process $proc$libresoc.v:89087$3818 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:87538.5-87538.29" + attribute \src "libresoc.v:89088.5-89088.29" switch \initial - attribute \src "libresoc.v:87538.9-87538.17" + attribute \src "libresoc.v:89088.9-89088.17" case 1'1 case end @@ -137438,14 +139546,14 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:87598.3-87658.6" - process $proc$libresoc.v:87598$3786 + attribute \src "libresoc.v:89148.3-89208.6" + process $proc$libresoc.v:89148$3819 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:87599.5-87599.29" + attribute \src "libresoc.v:89149.5-89149.29" switch \initial - attribute \src "libresoc.v:87599.9-87599.17" + attribute \src "libresoc.v:89149.9-89149.17" case 1'1 case end @@ -137529,14 +139637,14 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:87659.3-87719.6" - process $proc$libresoc.v:87659$3787 + attribute \src "libresoc.v:89209.3-89269.6" + process $proc$libresoc.v:89209$3820 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:87660.5-87660.29" + attribute \src "libresoc.v:89210.5-89210.29" switch \initial - attribute \src "libresoc.v:87660.9-87660.17" + attribute \src "libresoc.v:89210.9-89210.17" case 1'1 case end @@ -137620,14 +139728,14 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:87720.3-87780.6" - process $proc$libresoc.v:87720$3788 + attribute \src "libresoc.v:89270.3-89330.6" + process $proc$libresoc.v:89270$3821 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:87721.5-87721.29" + attribute \src "libresoc.v:89271.5-89271.29" switch \initial - attribute \src "libresoc.v:87721.9-87721.17" + attribute \src "libresoc.v:89271.9-89271.17" case 1'1 case end @@ -137711,14 +139819,14 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:87781.3-87841.6" - process $proc$libresoc.v:87781$3789 + attribute \src "libresoc.v:89331.3-89391.6" + process $proc$libresoc.v:89331$3822 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:87782.5-87782.29" + attribute \src "libresoc.v:89332.5-89332.29" switch \initial - attribute \src "libresoc.v:87782.9-87782.17" + attribute \src "libresoc.v:89332.9-89332.17" case 1'1 case end @@ -137802,14 +139910,14 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:87842.3-87902.6" - process $proc$libresoc.v:87842$3790 + attribute \src "libresoc.v:89392.3-89452.6" + process $proc$libresoc.v:89392$3823 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:87843.5-87843.29" + attribute \src "libresoc.v:89393.5-89393.29" switch \initial - attribute \src "libresoc.v:87843.9-87843.17" + attribute \src "libresoc.v:89393.9-89393.17" case 1'1 case end @@ -137893,14 +140001,14 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:87903.3-87963.6" - process $proc$libresoc.v:87903$3791 + attribute \src "libresoc.v:89453.3-89513.6" + process $proc$libresoc.v:89453$3824 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:87904.5-87904.29" + attribute \src "libresoc.v:89454.5-89454.29" switch \initial - attribute \src "libresoc.v:87904.9-87904.17" + attribute \src "libresoc.v:89454.9-89454.17" case 1'1 case end @@ -137984,14 +140092,14 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:87964.3-88024.6" - process $proc$libresoc.v:87964$3792 + attribute \src "libresoc.v:89514.3-89574.6" + process $proc$libresoc.v:89514$3825 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:87965.5-87965.29" + attribute \src "libresoc.v:89515.5-89515.29" switch \initial - attribute \src "libresoc.v:87965.9-87965.17" + attribute \src "libresoc.v:89515.9-89515.17" case 1'1 case end @@ -138075,14 +140183,14 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:88025.3-88085.6" - process $proc$libresoc.v:88025$3793 + attribute \src "libresoc.v:89575.3-89635.6" + process $proc$libresoc.v:89575$3826 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:88026.5-88026.29" + attribute \src "libresoc.v:89576.5-89576.29" switch \initial - attribute \src "libresoc.v:88026.9-88026.17" + attribute \src "libresoc.v:89576.9-89576.17" case 1'1 case end @@ -138166,14 +140274,14 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:88086.3-88146.6" - process $proc$libresoc.v:88086$3794 + attribute \src "libresoc.v:89636.3-89696.6" + process $proc$libresoc.v:89636$3827 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:88087.5-88087.29" + attribute \src "libresoc.v:89637.5-89637.29" switch \initial - attribute \src "libresoc.v:88087.9-88087.17" + attribute \src "libresoc.v:89637.9-89637.17" case 1'1 case end @@ -138257,14 +140365,14 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:88147.3-88207.6" - process $proc$libresoc.v:88147$3795 + attribute \src "libresoc.v:89697.3-89757.6" + process $proc$libresoc.v:89697$3828 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:88148.5-88148.29" + attribute \src "libresoc.v:89698.5-89698.29" switch \initial - attribute \src "libresoc.v:88148.9-88148.17" + attribute \src "libresoc.v:89698.9-89698.17" case 1'1 case end @@ -138369,140 +140477,140 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:88232.1-89177.10" +attribute \src "libresoc.v:89782.1-90730.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:89062.3-89080.6" + attribute \src "libresoc.v:90615.3-90633.6" wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:89081.3-89099.6" + attribute \src "libresoc.v:90634.3-90652.6" wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:88834.3-88852.6" + attribute \src "libresoc.v:90387.3-90405.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:88910.3-88928.6" + attribute \src "libresoc.v:90463.3-90481.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:88587.3-88605.6" + attribute \src "libresoc.v:90140.3-90158.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:88606.3-88624.6" + attribute \src "libresoc.v:90159.3-90177.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:88815.3-88833.6" + attribute \src "libresoc.v:90368.3-90386.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:88891.3-88909.6" + attribute \src "libresoc.v:90444.3-90462.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:88986.3-89004.6" + attribute \src "libresoc.v:90539.3-90557.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:88568.3-88586.6" - wire width 13 $0\dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:89100.3-89118.6" + attribute \src "libresoc.v:90121.3-90139.6" + wire width 14 $0\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:90653.3-90671.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:89119.3-89137.6" + attribute \src "libresoc.v:90672.3-90690.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:89138.3-89156.6" + attribute \src "libresoc.v:90691.3-90709.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:88777.3-88795.6" + attribute \src "libresoc.v:90330.3-90348.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:88853.3-88871.6" + attribute \src "libresoc.v:90406.3-90424.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:88872.3-88890.6" + attribute \src "libresoc.v:90425.3-90443.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:88967.3-88985.6" + attribute \src "libresoc.v:90520.3-90538.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:88739.3-88757.6" + attribute \src "libresoc.v:90292.3-90310.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:89024.3-89042.6" + attribute \src "libresoc.v:90577.3-90595.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:89157.3-89175.6" - wire width 2 $0\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:88796.3-88814.6" + attribute \src "libresoc.v:90710.3-90728.6" + wire width 3 $0\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:90349.3-90367.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:88948.3-88966.6" + attribute \src "libresoc.v:90501.3-90519.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:89043.3-89061.6" + attribute \src "libresoc.v:90596.3-90614.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:89005.3-89023.6" + attribute \src "libresoc.v:90558.3-90576.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:88929.3-88947.6" + attribute \src "libresoc.v:90482.3-90500.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:88701.3-88719.6" + attribute \src "libresoc.v:90254.3-90272.6" wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:88720.3-88738.6" + attribute \src "libresoc.v:90273.3-90291.6" wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:88625.3-88643.6" + attribute \src "libresoc.v:90178.3-90196.6" wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:88644.3-88662.6" + attribute \src "libresoc.v:90197.3-90215.6" wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:88663.3-88681.6" + attribute \src "libresoc.v:90216.3-90234.6" wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:88682.3-88700.6" + attribute \src "libresoc.v:90235.3-90253.6" wire width 3 $0\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:88758.3-88776.6" + attribute \src "libresoc.v:90311.3-90329.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:88233.7-88233.20" + attribute \src "libresoc.v:89783.7-89783.20" wire $0\initial[0:0] - attribute \src "libresoc.v:89062.3-89080.6" + attribute \src "libresoc.v:90615.3-90633.6" wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:89081.3-89099.6" + attribute \src "libresoc.v:90634.3-90652.6" wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:88834.3-88852.6" + attribute \src "libresoc.v:90387.3-90405.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:88910.3-88928.6" + attribute \src "libresoc.v:90463.3-90481.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:88587.3-88605.6" + attribute \src "libresoc.v:90140.3-90158.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:88606.3-88624.6" + attribute \src "libresoc.v:90159.3-90177.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:88815.3-88833.6" + attribute \src "libresoc.v:90368.3-90386.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:88891.3-88909.6" + attribute \src "libresoc.v:90444.3-90462.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:88986.3-89004.6" + attribute \src "libresoc.v:90539.3-90557.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:88568.3-88586.6" - wire width 13 $1\dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:89100.3-89118.6" + attribute \src "libresoc.v:90121.3-90139.6" + wire width 14 $1\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:90653.3-90671.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:89119.3-89137.6" + attribute \src "libresoc.v:90672.3-90690.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:89138.3-89156.6" + attribute \src "libresoc.v:90691.3-90709.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:88777.3-88795.6" + attribute \src "libresoc.v:90330.3-90348.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:88853.3-88871.6" + attribute \src "libresoc.v:90406.3-90424.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:88872.3-88890.6" + attribute \src "libresoc.v:90425.3-90443.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:88967.3-88985.6" + attribute \src "libresoc.v:90520.3-90538.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:88739.3-88757.6" + attribute \src "libresoc.v:90292.3-90310.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:89024.3-89042.6" + attribute \src "libresoc.v:90577.3-90595.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:89157.3-89175.6" - wire width 2 $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:88796.3-88814.6" + attribute \src "libresoc.v:90710.3-90728.6" + wire width 3 $1\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:90349.3-90367.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:88948.3-88966.6" + attribute \src "libresoc.v:90501.3-90519.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:89043.3-89061.6" + attribute \src "libresoc.v:90596.3-90614.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:89005.3-89023.6" + attribute \src "libresoc.v:90558.3-90576.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:88929.3-88947.6" + attribute \src "libresoc.v:90482.3-90500.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:88701.3-88719.6" + attribute \src "libresoc.v:90254.3-90272.6" wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:88720.3-88738.6" + attribute \src "libresoc.v:90273.3-90291.6" wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:88625.3-88643.6" + attribute \src "libresoc.v:90178.3-90196.6" wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:88644.3-88662.6" + attribute \src "libresoc.v:90197.3-90215.6" wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:88663.3-88681.6" + attribute \src "libresoc.v:90216.3-90234.6" wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:88682.3-88700.6" + attribute \src "libresoc.v:90235.3-90253.6" wire width 3 $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:88758.3-88776.6" + attribute \src "libresoc.v:90311.3-90329.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -138582,21 +140690,22 @@ module \dec31_dec_sub0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub0_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub0_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -138702,6 +140811,7 @@ module \dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub0_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -138721,12 +140831,13 @@ module \dec31_dec_sub0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub0_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub0_out_sel + wire width 3 output 10 \dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -138802,28 +140913,28 @@ module \dec31_dec_sub0 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub0_upd - attribute \src "libresoc.v:88233.7-88233.15" + attribute \src "libresoc.v:89783.7-89783.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:88233.7-88233.20" - process $proc$libresoc.v:88233$3829 + attribute \src "libresoc.v:89783.7-89783.20" + process $proc$libresoc.v:89783$3862 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:88568.3-88586.6" - process $proc$libresoc.v:88568$3797 + attribute \src "libresoc.v:90121.3-90139.6" + process $proc$libresoc.v:90121$3830 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_function_unit[12:0] $1\dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:88569.5-88569.29" + assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] + attribute \src "libresoc.v:90122.5-90122.29" switch \initial - attribute \src "libresoc.v:88569.9-88569.17" + attribute \src "libresoc.v:90122.9-90122.17" case 1'1 case end @@ -138832,33 +140943,33 @@ module \dec31_dec_sub0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000001000000 case - assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[12:0] + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:88587.3-88605.6" - process $proc$libresoc.v:88587$3798 + attribute \src "libresoc.v:90140.3-90158.6" + process $proc$libresoc.v:90140$3831 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:88588.5-88588.29" + attribute \src "libresoc.v:90141.5-90141.29" switch \initial - attribute \src "libresoc.v:88588.9-88588.17" + attribute \src "libresoc.v:90141.9-90141.17" case 1'1 case end @@ -138886,14 +140997,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:88606.3-88624.6" - process $proc$libresoc.v:88606$3799 + attribute \src "libresoc.v:90159.3-90177.6" + process $proc$libresoc.v:90159$3832 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:88607.5-88607.29" + attribute \src "libresoc.v:90160.5-90160.29" switch \initial - attribute \src "libresoc.v:88607.9-88607.17" + attribute \src "libresoc.v:90160.9-90160.17" case 1'1 case end @@ -138921,14 +141032,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:88625.3-88643.6" - process $proc$libresoc.v:88625$3800 + attribute \src "libresoc.v:90178.3-90196.6" + process $proc$libresoc.v:90178$3833 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:88626.5-88626.29" + attribute \src "libresoc.v:90179.5-90179.29" switch \initial - attribute \src "libresoc.v:88626.9-88626.17" + attribute \src "libresoc.v:90179.9-90179.17" case 1'1 case end @@ -138956,14 +141067,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] end - attribute \src "libresoc.v:88644.3-88662.6" - process $proc$libresoc.v:88644$3801 + attribute \src "libresoc.v:90197.3-90215.6" + process $proc$libresoc.v:90197$3834 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:88645.5-88645.29" + attribute \src "libresoc.v:90198.5-90198.29" switch \initial - attribute \src "libresoc.v:88645.9-88645.17" + attribute \src "libresoc.v:90198.9-90198.17" case 1'1 case end @@ -138991,14 +141102,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end - attribute \src "libresoc.v:88663.3-88681.6" - process $proc$libresoc.v:88663$3802 + attribute \src "libresoc.v:90216.3-90234.6" + process $proc$libresoc.v:90216$3835 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:88664.5-88664.29" + attribute \src "libresoc.v:90217.5-90217.29" switch \initial - attribute \src "libresoc.v:88664.9-88664.17" + attribute \src "libresoc.v:90217.9-90217.17" case 1'1 case end @@ -139026,14 +141137,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] end - attribute \src "libresoc.v:88682.3-88700.6" - process $proc$libresoc.v:88682$3803 + attribute \src "libresoc.v:90235.3-90253.6" + process $proc$libresoc.v:90235$3836 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:88683.5-88683.29" + attribute \src "libresoc.v:90236.5-90236.29" switch \initial - attribute \src "libresoc.v:88683.9-88683.17" + attribute \src "libresoc.v:90236.9-90236.17" case 1'1 case end @@ -139061,14 +141172,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] end - attribute \src "libresoc.v:88701.3-88719.6" - process $proc$libresoc.v:88701$3804 + attribute \src "libresoc.v:90254.3-90272.6" + process $proc$libresoc.v:90254$3837 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:88702.5-88702.29" + attribute \src "libresoc.v:90255.5-90255.29" switch \initial - attribute \src "libresoc.v:88702.9-88702.17" + attribute \src "libresoc.v:90255.9-90255.17" case 1'1 case end @@ -139096,14 +141207,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] end - attribute \src "libresoc.v:88720.3-88738.6" - process $proc$libresoc.v:88720$3805 + attribute \src "libresoc.v:90273.3-90291.6" + process $proc$libresoc.v:90273$3838 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:88721.5-88721.29" + attribute \src "libresoc.v:90274.5-90274.29" switch \initial - attribute \src "libresoc.v:88721.9-88721.17" + attribute \src "libresoc.v:90274.9-90274.17" case 1'1 case end @@ -139131,14 +141242,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] end - attribute \src "libresoc.v:88739.3-88757.6" - process $proc$libresoc.v:88739$3806 + attribute \src "libresoc.v:90292.3-90310.6" + process $proc$libresoc.v:90292$3839 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:88740.5-88740.29" + attribute \src "libresoc.v:90293.5-90293.29" switch \initial - attribute \src "libresoc.v:88740.9-88740.17" + attribute \src "libresoc.v:90293.9-90293.17" case 1'1 case end @@ -139166,14 +141277,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:88758.3-88776.6" - process $proc$libresoc.v:88758$3807 + attribute \src "libresoc.v:90311.3-90329.6" + process $proc$libresoc.v:90311$3840 assign { } { } assign { } { } assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:88759.5-88759.29" + attribute \src "libresoc.v:90312.5-90312.29" switch \initial - attribute \src "libresoc.v:88759.9-88759.17" + attribute \src "libresoc.v:90312.9-90312.17" case 1'1 case end @@ -139201,14 +141312,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:88777.3-88795.6" - process $proc$libresoc.v:88777$3808 + attribute \src "libresoc.v:90330.3-90348.6" + process $proc$libresoc.v:90330$3841 assign { } { } assign { } { } assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:88778.5-88778.29" + attribute \src "libresoc.v:90331.5-90331.29" switch \initial - attribute \src "libresoc.v:88778.9-88778.17" + attribute \src "libresoc.v:90331.9-90331.17" case 1'1 case end @@ -139236,14 +141347,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:88796.3-88814.6" - process $proc$libresoc.v:88796$3809 + attribute \src "libresoc.v:90349.3-90367.6" + process $proc$libresoc.v:90349$3842 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:88797.5-88797.29" + attribute \src "libresoc.v:90350.5-90350.29" switch \initial - attribute \src "libresoc.v:88797.9-88797.17" + attribute \src "libresoc.v:90350.9-90350.17" case 1'1 case end @@ -139271,14 +141382,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:88815.3-88833.6" - process $proc$libresoc.v:88815$3810 + attribute \src "libresoc.v:90368.3-90386.6" + process $proc$libresoc.v:90368$3843 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:88816.5-88816.29" + attribute \src "libresoc.v:90369.5-90369.29" switch \initial - attribute \src "libresoc.v:88816.9-88816.17" + attribute \src "libresoc.v:90369.9-90369.17" case 1'1 case end @@ -139306,14 +141417,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:88834.3-88852.6" - process $proc$libresoc.v:88834$3811 + attribute \src "libresoc.v:90387.3-90405.6" + process $proc$libresoc.v:90387$3844 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:88835.5-88835.29" + attribute \src "libresoc.v:90388.5-90388.29" switch \initial - attribute \src "libresoc.v:88835.9-88835.17" + attribute \src "libresoc.v:90388.9-90388.17" case 1'1 case end @@ -139341,14 +141452,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:88853.3-88871.6" - process $proc$libresoc.v:88853$3812 + attribute \src "libresoc.v:90406.3-90424.6" + process $proc$libresoc.v:90406$3845 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:88854.5-88854.29" + attribute \src "libresoc.v:90407.5-90407.29" switch \initial - attribute \src "libresoc.v:88854.9-88854.17" + attribute \src "libresoc.v:90407.9-90407.17" case 1'1 case end @@ -139376,14 +141487,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:88872.3-88890.6" - process $proc$libresoc.v:88872$3813 + attribute \src "libresoc.v:90425.3-90443.6" + process $proc$libresoc.v:90425$3846 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:88873.5-88873.29" + attribute \src "libresoc.v:90426.5-90426.29" switch \initial - attribute \src "libresoc.v:88873.9-88873.17" + attribute \src "libresoc.v:90426.9-90426.17" case 1'1 case end @@ -139411,14 +141522,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:88891.3-88909.6" - process $proc$libresoc.v:88891$3814 + attribute \src "libresoc.v:90444.3-90462.6" + process $proc$libresoc.v:90444$3847 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:88892.5-88892.29" + attribute \src "libresoc.v:90445.5-90445.29" switch \initial - attribute \src "libresoc.v:88892.9-88892.17" + attribute \src "libresoc.v:90445.9-90445.17" case 1'1 case end @@ -139446,14 +141557,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:88910.3-88928.6" - process $proc$libresoc.v:88910$3815 + attribute \src "libresoc.v:90463.3-90481.6" + process $proc$libresoc.v:90463$3848 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:88911.5-88911.29" + attribute \src "libresoc.v:90464.5-90464.29" switch \initial - attribute \src "libresoc.v:88911.9-88911.17" + attribute \src "libresoc.v:90464.9-90464.17" case 1'1 case end @@ -139481,14 +141592,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:88929.3-88947.6" - process $proc$libresoc.v:88929$3816 + attribute \src "libresoc.v:90482.3-90500.6" + process $proc$libresoc.v:90482$3849 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:88930.5-88930.29" + attribute \src "libresoc.v:90483.5-90483.29" switch \initial - attribute \src "libresoc.v:88930.9-88930.17" + attribute \src "libresoc.v:90483.9-90483.17" case 1'1 case end @@ -139516,14 +141627,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:88948.3-88966.6" - process $proc$libresoc.v:88948$3817 + attribute \src "libresoc.v:90501.3-90519.6" + process $proc$libresoc.v:90501$3850 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:88949.5-88949.29" + attribute \src "libresoc.v:90502.5-90502.29" switch \initial - attribute \src "libresoc.v:88949.9-88949.17" + attribute \src "libresoc.v:90502.9-90502.17" case 1'1 case end @@ -139551,14 +141662,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:88967.3-88985.6" - process $proc$libresoc.v:88967$3818 + attribute \src "libresoc.v:90520.3-90538.6" + process $proc$libresoc.v:90520$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:88968.5-88968.29" + attribute \src "libresoc.v:90521.5-90521.29" switch \initial - attribute \src "libresoc.v:88968.9-88968.17" + attribute \src "libresoc.v:90521.9-90521.17" case 1'1 case end @@ -139586,14 +141697,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:88986.3-89004.6" - process $proc$libresoc.v:88986$3819 + attribute \src "libresoc.v:90539.3-90557.6" + process $proc$libresoc.v:90539$3852 assign { } { } assign { } { } assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:88987.5-88987.29" + attribute \src "libresoc.v:90540.5-90540.29" switch \initial - attribute \src "libresoc.v:88987.9-88987.17" + attribute \src "libresoc.v:90540.9-90540.17" case 1'1 case end @@ -139621,14 +141732,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:89005.3-89023.6" - process $proc$libresoc.v:89005$3820 + attribute \src "libresoc.v:90558.3-90576.6" + process $proc$libresoc.v:90558$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:89006.5-89006.29" + attribute \src "libresoc.v:90559.5-90559.29" switch \initial - attribute \src "libresoc.v:89006.9-89006.17" + attribute \src "libresoc.v:90559.9-90559.17" case 1'1 case end @@ -139656,14 +141767,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:89024.3-89042.6" - process $proc$libresoc.v:89024$3821 + attribute \src "libresoc.v:90577.3-90595.6" + process $proc$libresoc.v:90577$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:89025.5-89025.29" + attribute \src "libresoc.v:90578.5-90578.29" switch \initial - attribute \src "libresoc.v:89025.9-89025.17" + attribute \src "libresoc.v:90578.9-90578.17" case 1'1 case end @@ -139691,14 +141802,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:89043.3-89061.6" - process $proc$libresoc.v:89043$3822 + attribute \src "libresoc.v:90596.3-90614.6" + process $proc$libresoc.v:90596$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:89044.5-89044.29" + attribute \src "libresoc.v:90597.5-90597.29" switch \initial - attribute \src "libresoc.v:89044.9-89044.17" + attribute \src "libresoc.v:90597.9-90597.17" case 1'1 case end @@ -139726,14 +141837,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:89062.3-89080.6" - process $proc$libresoc.v:89062$3823 + attribute \src "libresoc.v:90615.3-90633.6" + process $proc$libresoc.v:90615$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:89063.5-89063.29" + attribute \src "libresoc.v:90616.5-90616.29" switch \initial - attribute \src "libresoc.v:89063.9-89063.17" + attribute \src "libresoc.v:90616.9-90616.17" case 1'1 case end @@ -139761,14 +141872,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end - attribute \src "libresoc.v:89081.3-89099.6" - process $proc$libresoc.v:89081$3824 + attribute \src "libresoc.v:90634.3-90652.6" + process $proc$libresoc.v:90634$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:89082.5-89082.29" + attribute \src "libresoc.v:90635.5-90635.29" switch \initial - attribute \src "libresoc.v:89082.9-89082.17" + attribute \src "libresoc.v:90635.9-90635.17" case 1'1 case end @@ -139796,14 +141907,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end - attribute \src "libresoc.v:89100.3-89118.6" - process $proc$libresoc.v:89100$3825 + attribute \src "libresoc.v:90653.3-90671.6" + process $proc$libresoc.v:90653$3858 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:89101.5-89101.29" + attribute \src "libresoc.v:90654.5-90654.29" switch \initial - attribute \src "libresoc.v:89101.9-89101.17" + attribute \src "libresoc.v:90654.9-90654.17" case 1'1 case end @@ -139831,14 +141942,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:89119.3-89137.6" - process $proc$libresoc.v:89119$3826 + attribute \src "libresoc.v:90672.3-90690.6" + process $proc$libresoc.v:90672$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:89120.5-89120.29" + attribute \src "libresoc.v:90673.5-90673.29" switch \initial - attribute \src "libresoc.v:89120.9-89120.17" + attribute \src "libresoc.v:90673.9-90673.17" case 1'1 case end @@ -139866,14 +141977,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:89138.3-89156.6" - process $proc$libresoc.v:89138$3827 + attribute \src "libresoc.v:90691.3-90709.6" + process $proc$libresoc.v:90691$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:89139.5-89139.29" + attribute \src "libresoc.v:90692.5-90692.29" switch \initial - attribute \src "libresoc.v:89139.9-89139.17" + attribute \src "libresoc.v:90692.9-90692.17" case 1'1 case end @@ -139901,14 +142012,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:89157.3-89175.6" - process $proc$libresoc.v:89157$3828 + attribute \src "libresoc.v:90710.3-90728.6" + process $proc$libresoc.v:90710$3861 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:89158.5-89158.29" + assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] + attribute \src "libresoc.v:90711.5-90711.29" switch \initial - attribute \src "libresoc.v:89158.9-89158.17" + attribute \src "libresoc.v:90711.9-90711.17" case 1'1 case end @@ -139917,161 +142028,161 @@ module \dec31_dec_sub0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:89181.1-90702.10" +attribute \src "libresoc.v:90734.1-92258.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:90479.3-90515.6" + attribute \src "libresoc.v:92035.3-92071.6" wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:90516.3-90552.6" + attribute \src "libresoc.v:92072.3-92108.6" wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:90035.3-90071.6" + attribute \src "libresoc.v:91591.3-91627.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:90183.3-90219.6" + attribute \src "libresoc.v:91739.3-91775.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:89554.3-89590.6" + attribute \src "libresoc.v:91110.3-91146.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:89591.3-89627.6" + attribute \src "libresoc.v:91147.3-91183.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:89998.3-90034.6" + attribute \src "libresoc.v:91554.3-91590.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:90146.3-90182.6" + attribute \src "libresoc.v:91702.3-91738.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:90331.3-90367.6" + attribute \src "libresoc.v:91887.3-91923.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:89517.3-89553.6" - wire width 13 $0\dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:90553.3-90589.6" + attribute \src "libresoc.v:91073.3-91109.6" + wire width 14 $0\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:92109.3-92145.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:90590.3-90626.6" + attribute \src "libresoc.v:92146.3-92182.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:90627.3-90663.6" + attribute \src "libresoc.v:92183.3-92219.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:89924.3-89960.6" + attribute \src "libresoc.v:91480.3-91516.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:90072.3-90108.6" + attribute \src "libresoc.v:91628.3-91664.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:90109.3-90145.6" + attribute \src "libresoc.v:91665.3-91701.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:90294.3-90330.6" + attribute \src "libresoc.v:91850.3-91886.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:89850.3-89886.6" + attribute \src "libresoc.v:91406.3-91442.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:90405.3-90441.6" + attribute \src "libresoc.v:91961.3-91997.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:90664.3-90700.6" - wire width 2 $0\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:89961.3-89997.6" + attribute \src "libresoc.v:92220.3-92256.6" + wire width 3 $0\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:91517.3-91553.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:90257.3-90293.6" + attribute \src "libresoc.v:91813.3-91849.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:90442.3-90478.6" + attribute \src "libresoc.v:91998.3-92034.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:90368.3-90404.6" + attribute \src "libresoc.v:91924.3-91960.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:90220.3-90256.6" + attribute \src "libresoc.v:91776.3-91812.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:89776.3-89812.6" + attribute \src "libresoc.v:91332.3-91368.6" wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:89813.3-89849.6" + attribute \src "libresoc.v:91369.3-91405.6" wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:89628.3-89664.6" + attribute \src "libresoc.v:91184.3-91220.6" wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:89665.3-89701.6" + attribute \src "libresoc.v:91221.3-91257.6" wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:89702.3-89738.6" + attribute \src "libresoc.v:91258.3-91294.6" wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:89739.3-89775.6" + attribute \src "libresoc.v:91295.3-91331.6" wire width 3 $0\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:89887.3-89923.6" + attribute \src "libresoc.v:91443.3-91479.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:89182.7-89182.20" + attribute \src "libresoc.v:90735.7-90735.20" wire $0\initial[0:0] - attribute \src "libresoc.v:90479.3-90515.6" + attribute \src "libresoc.v:92035.3-92071.6" wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:90516.3-90552.6" + attribute \src "libresoc.v:92072.3-92108.6" wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:90035.3-90071.6" + attribute \src "libresoc.v:91591.3-91627.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:90183.3-90219.6" + attribute \src "libresoc.v:91739.3-91775.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:89554.3-89590.6" + attribute \src "libresoc.v:91110.3-91146.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:89591.3-89627.6" + attribute \src "libresoc.v:91147.3-91183.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:89998.3-90034.6" + attribute \src "libresoc.v:91554.3-91590.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:90146.3-90182.6" + attribute \src "libresoc.v:91702.3-91738.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:90331.3-90367.6" + attribute \src "libresoc.v:91887.3-91923.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:89517.3-89553.6" - wire width 13 $1\dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:90553.3-90589.6" + attribute \src "libresoc.v:91073.3-91109.6" + wire width 14 $1\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:92109.3-92145.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:90590.3-90626.6" + attribute \src "libresoc.v:92146.3-92182.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:90627.3-90663.6" + attribute \src "libresoc.v:92183.3-92219.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:89924.3-89960.6" + attribute \src "libresoc.v:91480.3-91516.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:90072.3-90108.6" + attribute \src "libresoc.v:91628.3-91664.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:90109.3-90145.6" + attribute \src "libresoc.v:91665.3-91701.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:90294.3-90330.6" + attribute \src "libresoc.v:91850.3-91886.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:89850.3-89886.6" + attribute \src "libresoc.v:91406.3-91442.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:90405.3-90441.6" + attribute \src "libresoc.v:91961.3-91997.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:90664.3-90700.6" - wire width 2 $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:89961.3-89997.6" + attribute \src "libresoc.v:92220.3-92256.6" + wire width 3 $1\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:91517.3-91553.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:90257.3-90293.6" + attribute \src "libresoc.v:91813.3-91849.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:90442.3-90478.6" + attribute \src "libresoc.v:91998.3-92034.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:90368.3-90404.6" + attribute \src "libresoc.v:91924.3-91960.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:90220.3-90256.6" + attribute \src "libresoc.v:91776.3-91812.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:89776.3-89812.6" + attribute \src "libresoc.v:91332.3-91368.6" wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:89813.3-89849.6" + attribute \src "libresoc.v:91369.3-91405.6" wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:89628.3-89664.6" + attribute \src "libresoc.v:91184.3-91220.6" wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:89665.3-89701.6" + attribute \src "libresoc.v:91221.3-91257.6" wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:89702.3-89738.6" + attribute \src "libresoc.v:91258.3-91294.6" wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:89739.3-89775.6" + attribute \src "libresoc.v:91295.3-91331.6" wire width 3 $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:89887.3-89923.6" + attribute \src "libresoc.v:91443.3-91479.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -140151,21 +142262,22 @@ module \dec31_dec_sub10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub10_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub10_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -140271,6 +142383,7 @@ module \dec31_dec_sub10 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub10_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -140290,12 +142403,13 @@ module \dec31_dec_sub10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub10_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub10_out_sel + wire width 3 output 10 \dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -140371,28 +142485,28 @@ module \dec31_dec_sub10 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub10_upd - attribute \src "libresoc.v:89182.7-89182.15" + attribute \src "libresoc.v:90735.7-90735.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:89182.7-89182.20" - process $proc$libresoc.v:89182$3862 + attribute \src "libresoc.v:90735.7-90735.20" + process $proc$libresoc.v:90735$3895 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:89517.3-89553.6" - process $proc$libresoc.v:89517$3830 + attribute \src "libresoc.v:91073.3-91109.6" + process $proc$libresoc.v:91073$3863 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_function_unit[12:0] $1\dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:89518.5-89518.29" + assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] + attribute \src "libresoc.v:91074.5-91074.29" switch \initial - attribute \src "libresoc.v:89518.9-89518.17" + attribute \src "libresoc.v:91074.9-91074.17" case 1'1 case end @@ -140401,57 +142515,57 @@ module \dec31_dec_sub10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 case - assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[12:0] + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:89554.3-89590.6" - process $proc$libresoc.v:89554$3831 + attribute \src "libresoc.v:91110.3-91146.6" + process $proc$libresoc.v:91110$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:89555.5-89555.29" + attribute \src "libresoc.v:91111.5-91111.29" switch \initial - attribute \src "libresoc.v:89555.9-89555.17" + attribute \src "libresoc.v:91111.9-91111.17" case 1'1 case end @@ -140503,14 +142617,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:89591.3-89627.6" - process $proc$libresoc.v:89591$3832 + attribute \src "libresoc.v:91147.3-91183.6" + process $proc$libresoc.v:91147$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:89592.5-89592.29" + attribute \src "libresoc.v:91148.5-91148.29" switch \initial - attribute \src "libresoc.v:89592.9-89592.17" + attribute \src "libresoc.v:91148.9-91148.17" case 1'1 case end @@ -140562,14 +142676,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:89628.3-89664.6" - process $proc$libresoc.v:89628$3833 + attribute \src "libresoc.v:91184.3-91220.6" + process $proc$libresoc.v:91184$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:89629.5-89629.29" + attribute \src "libresoc.v:91185.5-91185.29" switch \initial - attribute \src "libresoc.v:89629.9-89629.17" + attribute \src "libresoc.v:91185.9-91185.17" case 1'1 case end @@ -140621,14 +142735,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end - attribute \src "libresoc.v:89665.3-89701.6" - process $proc$libresoc.v:89665$3834 + attribute \src "libresoc.v:91221.3-91257.6" + process $proc$libresoc.v:91221$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:89666.5-89666.29" + attribute \src "libresoc.v:91222.5-91222.29" switch \initial - attribute \src "libresoc.v:89666.9-89666.17" + attribute \src "libresoc.v:91222.9-91222.17" case 1'1 case end @@ -140680,14 +142794,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end - attribute \src "libresoc.v:89702.3-89738.6" - process $proc$libresoc.v:89702$3835 + attribute \src "libresoc.v:91258.3-91294.6" + process $proc$libresoc.v:91258$3868 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:89703.5-89703.29" + attribute \src "libresoc.v:91259.5-91259.29" switch \initial - attribute \src "libresoc.v:89703.9-89703.17" + attribute \src "libresoc.v:91259.9-91259.17" case 1'1 case end @@ -140739,14 +142853,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end - attribute \src "libresoc.v:89739.3-89775.6" - process $proc$libresoc.v:89739$3836 + attribute \src "libresoc.v:91295.3-91331.6" + process $proc$libresoc.v:91295$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:89740.5-89740.29" + attribute \src "libresoc.v:91296.5-91296.29" switch \initial - attribute \src "libresoc.v:89740.9-89740.17" + attribute \src "libresoc.v:91296.9-91296.17" case 1'1 case end @@ -140798,14 +142912,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end - attribute \src "libresoc.v:89776.3-89812.6" - process $proc$libresoc.v:89776$3837 + attribute \src "libresoc.v:91332.3-91368.6" + process $proc$libresoc.v:91332$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:89777.5-89777.29" + attribute \src "libresoc.v:91333.5-91333.29" switch \initial - attribute \src "libresoc.v:89777.9-89777.17" + attribute \src "libresoc.v:91333.9-91333.17" case 1'1 case end @@ -140857,14 +142971,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end - attribute \src "libresoc.v:89813.3-89849.6" - process $proc$libresoc.v:89813$3838 + attribute \src "libresoc.v:91369.3-91405.6" + process $proc$libresoc.v:91369$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:89814.5-89814.29" + attribute \src "libresoc.v:91370.5-91370.29" switch \initial - attribute \src "libresoc.v:89814.9-89814.17" + attribute \src "libresoc.v:91370.9-91370.17" case 1'1 case end @@ -140916,14 +143030,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end - attribute \src "libresoc.v:89850.3-89886.6" - process $proc$libresoc.v:89850$3839 + attribute \src "libresoc.v:91406.3-91442.6" + process $proc$libresoc.v:91406$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:89851.5-89851.29" + attribute \src "libresoc.v:91407.5-91407.29" switch \initial - attribute \src "libresoc.v:89851.9-89851.17" + attribute \src "libresoc.v:91407.9-91407.17" case 1'1 case end @@ -140975,14 +143089,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:89887.3-89923.6" - process $proc$libresoc.v:89887$3840 + attribute \src "libresoc.v:91443.3-91479.6" + process $proc$libresoc.v:91443$3873 assign { } { } assign { } { } assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:89888.5-89888.29" + attribute \src "libresoc.v:91444.5-91444.29" switch \initial - attribute \src "libresoc.v:89888.9-89888.17" + attribute \src "libresoc.v:91444.9-91444.17" case 1'1 case end @@ -141034,14 +143148,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:89924.3-89960.6" - process $proc$libresoc.v:89924$3841 + attribute \src "libresoc.v:91480.3-91516.6" + process $proc$libresoc.v:91480$3874 assign { } { } assign { } { } assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:89925.5-89925.29" + attribute \src "libresoc.v:91481.5-91481.29" switch \initial - attribute \src "libresoc.v:89925.9-89925.17" + attribute \src "libresoc.v:91481.9-91481.17" case 1'1 case end @@ -141093,14 +143207,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:89961.3-89997.6" - process $proc$libresoc.v:89961$3842 + attribute \src "libresoc.v:91517.3-91553.6" + process $proc$libresoc.v:91517$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:89962.5-89962.29" + attribute \src "libresoc.v:91518.5-91518.29" switch \initial - attribute \src "libresoc.v:89962.9-89962.17" + attribute \src "libresoc.v:91518.9-91518.17" case 1'1 case end @@ -141152,14 +143266,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:89998.3-90034.6" - process $proc$libresoc.v:89998$3843 + attribute \src "libresoc.v:91554.3-91590.6" + process $proc$libresoc.v:91554$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:89999.5-89999.29" + attribute \src "libresoc.v:91555.5-91555.29" switch \initial - attribute \src "libresoc.v:89999.9-89999.17" + attribute \src "libresoc.v:91555.9-91555.17" case 1'1 case end @@ -141211,14 +143325,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "libresoc.v:90035.3-90071.6" - process $proc$libresoc.v:90035$3844 + attribute \src "libresoc.v:91591.3-91627.6" + process $proc$libresoc.v:91591$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:90036.5-90036.29" + attribute \src "libresoc.v:91592.5-91592.29" switch \initial - attribute \src "libresoc.v:90036.9-90036.17" + attribute \src "libresoc.v:91592.9-91592.17" case 1'1 case end @@ -141270,14 +143384,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "libresoc.v:90072.3-90108.6" - process $proc$libresoc.v:90072$3845 + attribute \src "libresoc.v:91628.3-91664.6" + process $proc$libresoc.v:91628$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:90073.5-90073.29" + attribute \src "libresoc.v:91629.5-91629.29" switch \initial - attribute \src "libresoc.v:90073.9-90073.17" + attribute \src "libresoc.v:91629.9-91629.17" case 1'1 case end @@ -141329,14 +143443,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:90109.3-90145.6" - process $proc$libresoc.v:90109$3846 + attribute \src "libresoc.v:91665.3-91701.6" + process $proc$libresoc.v:91665$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:90110.5-90110.29" + attribute \src "libresoc.v:91666.5-91666.29" switch \initial - attribute \src "libresoc.v:90110.9-90110.17" + attribute \src "libresoc.v:91666.9-91666.17" case 1'1 case end @@ -141388,14 +143502,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:90146.3-90182.6" - process $proc$libresoc.v:90146$3847 + attribute \src "libresoc.v:91702.3-91738.6" + process $proc$libresoc.v:91702$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:90147.5-90147.29" + attribute \src "libresoc.v:91703.5-91703.29" switch \initial - attribute \src "libresoc.v:90147.9-90147.17" + attribute \src "libresoc.v:91703.9-91703.17" case 1'1 case end @@ -141447,14 +143561,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:90183.3-90219.6" - process $proc$libresoc.v:90183$3848 + attribute \src "libresoc.v:91739.3-91775.6" + process $proc$libresoc.v:91739$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:90184.5-90184.29" + attribute \src "libresoc.v:91740.5-91740.29" switch \initial - attribute \src "libresoc.v:90184.9-90184.17" + attribute \src "libresoc.v:91740.9-91740.17" case 1'1 case end @@ -141506,14 +143620,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "libresoc.v:90220.3-90256.6" - process $proc$libresoc.v:90220$3849 + attribute \src "libresoc.v:91776.3-91812.6" + process $proc$libresoc.v:91776$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:90221.5-90221.29" + attribute \src "libresoc.v:91777.5-91777.29" switch \initial - attribute \src "libresoc.v:90221.9-90221.17" + attribute \src "libresoc.v:91777.9-91777.17" case 1'1 case end @@ -141565,14 +143679,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "libresoc.v:90257.3-90293.6" - process $proc$libresoc.v:90257$3850 + attribute \src "libresoc.v:91813.3-91849.6" + process $proc$libresoc.v:91813$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:90258.5-90258.29" + attribute \src "libresoc.v:91814.5-91814.29" switch \initial - attribute \src "libresoc.v:90258.9-90258.17" + attribute \src "libresoc.v:91814.9-91814.17" case 1'1 case end @@ -141624,14 +143738,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:90294.3-90330.6" - process $proc$libresoc.v:90294$3851 + attribute \src "libresoc.v:91850.3-91886.6" + process $proc$libresoc.v:91850$3884 assign { } { } assign { } { } assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:90295.5-90295.29" + attribute \src "libresoc.v:91851.5-91851.29" switch \initial - attribute \src "libresoc.v:90295.9-90295.17" + attribute \src "libresoc.v:91851.9-91851.17" case 1'1 case end @@ -141683,14 +143797,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:90331.3-90367.6" - process $proc$libresoc.v:90331$3852 + attribute \src "libresoc.v:91887.3-91923.6" + process $proc$libresoc.v:91887$3885 assign { } { } assign { } { } assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:90332.5-90332.29" + attribute \src "libresoc.v:91888.5-91888.29" switch \initial - attribute \src "libresoc.v:90332.9-90332.17" + attribute \src "libresoc.v:91888.9-91888.17" case 1'1 case end @@ -141742,14 +143856,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:90368.3-90404.6" - process $proc$libresoc.v:90368$3853 + attribute \src "libresoc.v:91924.3-91960.6" + process $proc$libresoc.v:91924$3886 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:90369.5-90369.29" + attribute \src "libresoc.v:91925.5-91925.29" switch \initial - attribute \src "libresoc.v:90369.9-90369.17" + attribute \src "libresoc.v:91925.9-91925.17" case 1'1 case end @@ -141801,14 +143915,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:90405.3-90441.6" - process $proc$libresoc.v:90405$3854 + attribute \src "libresoc.v:91961.3-91997.6" + process $proc$libresoc.v:91961$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:90406.5-90406.29" + attribute \src "libresoc.v:91962.5-91962.29" switch \initial - attribute \src "libresoc.v:90406.9-90406.17" + attribute \src "libresoc.v:91962.9-91962.17" case 1'1 case end @@ -141860,14 +143974,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:90442.3-90478.6" - process $proc$libresoc.v:90442$3855 + attribute \src "libresoc.v:91998.3-92034.6" + process $proc$libresoc.v:91998$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:90443.5-90443.29" + attribute \src "libresoc.v:91999.5-91999.29" switch \initial - attribute \src "libresoc.v:90443.9-90443.17" + attribute \src "libresoc.v:91999.9-91999.17" case 1'1 case end @@ -141919,14 +144033,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:90479.3-90515.6" - process $proc$libresoc.v:90479$3856 + attribute \src "libresoc.v:92035.3-92071.6" + process $proc$libresoc.v:92035$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:90480.5-90480.29" + attribute \src "libresoc.v:92036.5-92036.29" switch \initial - attribute \src "libresoc.v:90480.9-90480.17" + attribute \src "libresoc.v:92036.9-92036.17" case 1'1 case end @@ -141978,14 +144092,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end - attribute \src "libresoc.v:90516.3-90552.6" - process $proc$libresoc.v:90516$3857 + attribute \src "libresoc.v:92072.3-92108.6" + process $proc$libresoc.v:92072$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:90517.5-90517.29" + attribute \src "libresoc.v:92073.5-92073.29" switch \initial - attribute \src "libresoc.v:90517.9-90517.17" + attribute \src "libresoc.v:92073.9-92073.17" case 1'1 case end @@ -142037,14 +144151,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end - attribute \src "libresoc.v:90553.3-90589.6" - process $proc$libresoc.v:90553$3858 + attribute \src "libresoc.v:92109.3-92145.6" + process $proc$libresoc.v:92109$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:90554.5-90554.29" + attribute \src "libresoc.v:92110.5-92110.29" switch \initial - attribute \src "libresoc.v:90554.9-90554.17" + attribute \src "libresoc.v:92110.9-92110.17" case 1'1 case end @@ -142096,14 +144210,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:90590.3-90626.6" - process $proc$libresoc.v:90590$3859 + attribute \src "libresoc.v:92146.3-92182.6" + process $proc$libresoc.v:92146$3892 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:90591.5-90591.29" + attribute \src "libresoc.v:92147.5-92147.29" switch \initial - attribute \src "libresoc.v:90591.9-90591.17" + attribute \src "libresoc.v:92147.9-92147.17" case 1'1 case end @@ -142155,14 +144269,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:90627.3-90663.6" - process $proc$libresoc.v:90627$3860 + attribute \src "libresoc.v:92183.3-92219.6" + process $proc$libresoc.v:92183$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:90628.5-90628.29" + attribute \src "libresoc.v:92184.5-92184.29" switch \initial - attribute \src "libresoc.v:90628.9-90628.17" + attribute \src "libresoc.v:92184.9-92184.17" case 1'1 case end @@ -142214,14 +144328,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:90664.3-90700.6" - process $proc$libresoc.v:90664$3861 + attribute \src "libresoc.v:92220.3-92256.6" + process $proc$libresoc.v:92220$3894 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:90665.5-90665.29" + assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] + attribute \src "libresoc.v:92221.5-92221.29" switch \initial - attribute \src "libresoc.v:90665.9-90665.17" + attribute \src "libresoc.v:92221.9-92221.17" case 1'1 case end @@ -142230,185 +144344,185 @@ module \dec31_dec_sub10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub10_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:90706.1-92803.10" +attribute \src "libresoc.v:92262.1-94362.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:92472.3-92526.6" + attribute \src "libresoc.v:94031.3-94085.6" wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:92527.3-92581.6" + attribute \src "libresoc.v:94086.3-94140.6" wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:91812.3-91866.6" + attribute \src "libresoc.v:93371.3-93425.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:92032.3-92086.6" + attribute \src "libresoc.v:93591.3-93645.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:91097.3-91151.6" + attribute \src "libresoc.v:92656.3-92710.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:91152.3-91206.6" + attribute \src "libresoc.v:92711.3-92765.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:91757.3-91811.6" + attribute \src "libresoc.v:93316.3-93370.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:91977.3-92031.6" + attribute \src "libresoc.v:93536.3-93590.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:92252.3-92306.6" + attribute \src "libresoc.v:93811.3-93865.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:91042.3-91096.6" - wire width 13 $0\dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:92582.3-92636.6" + attribute \src "libresoc.v:92601.3-92655.6" + wire width 14 $0\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:94141.3-94195.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:92637.3-92691.6" + attribute \src "libresoc.v:94196.3-94250.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:92692.3-92746.6" + attribute \src "libresoc.v:94251.3-94305.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:91647.3-91701.6" + attribute \src "libresoc.v:93206.3-93260.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:91867.3-91921.6" + attribute \src "libresoc.v:93426.3-93480.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:91922.3-91976.6" + attribute \src "libresoc.v:93481.3-93535.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:92197.3-92251.6" + attribute \src "libresoc.v:93756.3-93810.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:91537.3-91591.6" + attribute \src "libresoc.v:93096.3-93150.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:92362.3-92416.6" + attribute \src "libresoc.v:93921.3-93975.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:92747.3-92801.6" - wire width 2 $0\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:91702.3-91756.6" + attribute \src "libresoc.v:94306.3-94360.6" + wire width 3 $0\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:93261.3-93315.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:92142.3-92196.6" + attribute \src "libresoc.v:93701.3-93755.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:92417.3-92471.6" + attribute \src "libresoc.v:93976.3-94030.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:92307.3-92361.6" + attribute \src "libresoc.v:93866.3-93920.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:92087.3-92141.6" + attribute \src "libresoc.v:93646.3-93700.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:91427.3-91481.6" + attribute \src "libresoc.v:92986.3-93040.6" wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:91482.3-91536.6" + attribute \src "libresoc.v:93041.3-93095.6" wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:91207.3-91261.6" + attribute \src "libresoc.v:92766.3-92820.6" wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:91262.3-91316.6" + attribute \src "libresoc.v:92821.3-92875.6" wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:91317.3-91371.6" + attribute \src "libresoc.v:92876.3-92930.6" wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:91372.3-91426.6" + attribute \src "libresoc.v:92931.3-92985.6" wire width 3 $0\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:91592.3-91646.6" + attribute \src "libresoc.v:93151.3-93205.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:90707.7-90707.20" + attribute \src "libresoc.v:92263.7-92263.20" wire $0\initial[0:0] - attribute \src "libresoc.v:92472.3-92526.6" + attribute \src "libresoc.v:94031.3-94085.6" wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:92527.3-92581.6" + attribute \src "libresoc.v:94086.3-94140.6" wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:91812.3-91866.6" + attribute \src "libresoc.v:93371.3-93425.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:92032.3-92086.6" + attribute \src "libresoc.v:93591.3-93645.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:91097.3-91151.6" + attribute \src "libresoc.v:92656.3-92710.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:91152.3-91206.6" + attribute \src "libresoc.v:92711.3-92765.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:91757.3-91811.6" + attribute \src "libresoc.v:93316.3-93370.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:91977.3-92031.6" + attribute \src "libresoc.v:93536.3-93590.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:92252.3-92306.6" + attribute \src "libresoc.v:93811.3-93865.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:91042.3-91096.6" - wire width 13 $1\dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:92582.3-92636.6" + attribute \src "libresoc.v:92601.3-92655.6" + wire width 14 $1\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:94141.3-94195.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:92637.3-92691.6" + attribute \src "libresoc.v:94196.3-94250.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:92692.3-92746.6" + attribute \src "libresoc.v:94251.3-94305.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:91647.3-91701.6" + attribute \src "libresoc.v:93206.3-93260.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:91867.3-91921.6" + attribute \src "libresoc.v:93426.3-93480.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:91922.3-91976.6" + attribute \src "libresoc.v:93481.3-93535.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:92197.3-92251.6" + attribute \src "libresoc.v:93756.3-93810.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:91537.3-91591.6" + attribute \src "libresoc.v:93096.3-93150.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:92362.3-92416.6" + attribute \src "libresoc.v:93921.3-93975.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:92747.3-92801.6" - wire width 2 $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:91702.3-91756.6" + attribute \src "libresoc.v:94306.3-94360.6" + wire width 3 $1\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:93261.3-93315.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:92142.3-92196.6" + attribute \src "libresoc.v:93701.3-93755.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:92417.3-92471.6" + attribute \src "libresoc.v:93976.3-94030.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:92307.3-92361.6" + attribute \src "libresoc.v:93866.3-93920.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:92087.3-92141.6" + attribute \src "libresoc.v:93646.3-93700.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:91427.3-91481.6" + attribute \src "libresoc.v:92986.3-93040.6" wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:91482.3-91536.6" + attribute \src "libresoc.v:93041.3-93095.6" wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:91207.3-91261.6" + attribute \src "libresoc.v:92766.3-92820.6" wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:91262.3-91316.6" + attribute \src "libresoc.v:92821.3-92875.6" wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:91317.3-91371.6" + attribute \src "libresoc.v:92876.3-92930.6" wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:91372.3-91426.6" + attribute \src "libresoc.v:92931.3-92985.6" wire width 3 $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:91592.3-91646.6" + attribute \src "libresoc.v:93151.3-93205.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -142488,21 +144602,22 @@ module \dec31_dec_sub11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub11_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub11_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -142608,6 +144723,7 @@ module \dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -142627,12 +144743,13 @@ module \dec31_dec_sub11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub11_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub11_out_sel + wire width 3 output 10 \dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -142708,28 +144825,28 @@ module \dec31_dec_sub11 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub11_upd - attribute \src "libresoc.v:90707.7-90707.15" + attribute \src "libresoc.v:92263.7-92263.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:90707.7-90707.20" - process $proc$libresoc.v:90707$3895 + attribute \src "libresoc.v:92263.7-92263.20" + process $proc$libresoc.v:92263$3928 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91042.3-91096.6" - process $proc$libresoc.v:91042$3863 + attribute \src "libresoc.v:92601.3-92655.6" + process $proc$libresoc.v:92601$3896 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_function_unit[12:0] $1\dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:91043.5-91043.29" + assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] + attribute \src "libresoc.v:92602.5-92602.29" switch \initial - attribute \src "libresoc.v:91043.9-91043.17" + attribute \src "libresoc.v:92602.9-92602.17" case 1'1 case end @@ -142738,81 +144855,81 @@ module \dec31_dec_sub11 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 case - assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[12:0] + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:91097.3-91151.6" - process $proc$libresoc.v:91097$3864 + attribute \src "libresoc.v:92656.3-92710.6" + process $proc$libresoc.v:92656$3897 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:91098.5-91098.29" + attribute \src "libresoc.v:92657.5-92657.29" switch \initial - attribute \src "libresoc.v:91098.9-91098.17" + attribute \src "libresoc.v:92657.9-92657.17" case 1'1 case end @@ -142888,14 +145005,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:91152.3-91206.6" - process $proc$libresoc.v:91152$3865 + attribute \src "libresoc.v:92711.3-92765.6" + process $proc$libresoc.v:92711$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:91153.5-91153.29" + attribute \src "libresoc.v:92712.5-92712.29" switch \initial - attribute \src "libresoc.v:91153.9-91153.17" + attribute \src "libresoc.v:92712.9-92712.17" case 1'1 case end @@ -142971,14 +145088,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:91207.3-91261.6" - process $proc$libresoc.v:91207$3866 + attribute \src "libresoc.v:92766.3-92820.6" + process $proc$libresoc.v:92766$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:91208.5-91208.29" + attribute \src "libresoc.v:92767.5-92767.29" switch \initial - attribute \src "libresoc.v:91208.9-91208.17" + attribute \src "libresoc.v:92767.9-92767.17" case 1'1 case end @@ -143054,14 +145171,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end - attribute \src "libresoc.v:91262.3-91316.6" - process $proc$libresoc.v:91262$3867 + attribute \src "libresoc.v:92821.3-92875.6" + process $proc$libresoc.v:92821$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:91263.5-91263.29" + attribute \src "libresoc.v:92822.5-92822.29" switch \initial - attribute \src "libresoc.v:91263.9-91263.17" + attribute \src "libresoc.v:92822.9-92822.17" case 1'1 case end @@ -143137,14 +145254,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end - attribute \src "libresoc.v:91317.3-91371.6" - process $proc$libresoc.v:91317$3868 + attribute \src "libresoc.v:92876.3-92930.6" + process $proc$libresoc.v:92876$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:91318.5-91318.29" + attribute \src "libresoc.v:92877.5-92877.29" switch \initial - attribute \src "libresoc.v:91318.9-91318.17" + attribute \src "libresoc.v:92877.9-92877.17" case 1'1 case end @@ -143220,14 +145337,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end - attribute \src "libresoc.v:91372.3-91426.6" - process $proc$libresoc.v:91372$3869 + attribute \src "libresoc.v:92931.3-92985.6" + process $proc$libresoc.v:92931$3902 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:91373.5-91373.29" + attribute \src "libresoc.v:92932.5-92932.29" switch \initial - attribute \src "libresoc.v:91373.9-91373.17" + attribute \src "libresoc.v:92932.9-92932.17" case 1'1 case end @@ -143303,14 +145420,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end - attribute \src "libresoc.v:91427.3-91481.6" - process $proc$libresoc.v:91427$3870 + attribute \src "libresoc.v:92986.3-93040.6" + process $proc$libresoc.v:92986$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:91428.5-91428.29" + attribute \src "libresoc.v:92987.5-92987.29" switch \initial - attribute \src "libresoc.v:91428.9-91428.17" + attribute \src "libresoc.v:92987.9-92987.17" case 1'1 case end @@ -143386,14 +145503,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end - attribute \src "libresoc.v:91482.3-91536.6" - process $proc$libresoc.v:91482$3871 + attribute \src "libresoc.v:93041.3-93095.6" + process $proc$libresoc.v:93041$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:91483.5-91483.29" + attribute \src "libresoc.v:93042.5-93042.29" switch \initial - attribute \src "libresoc.v:91483.9-91483.17" + attribute \src "libresoc.v:93042.9-93042.17" case 1'1 case end @@ -143469,14 +145586,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end - attribute \src "libresoc.v:91537.3-91591.6" - process $proc$libresoc.v:91537$3872 + attribute \src "libresoc.v:93096.3-93150.6" + process $proc$libresoc.v:93096$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:91538.5-91538.29" + attribute \src "libresoc.v:93097.5-93097.29" switch \initial - attribute \src "libresoc.v:91538.9-91538.17" + attribute \src "libresoc.v:93097.9-93097.17" case 1'1 case end @@ -143552,14 +145669,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:91592.3-91646.6" - process $proc$libresoc.v:91592$3873 + attribute \src "libresoc.v:93151.3-93205.6" + process $proc$libresoc.v:93151$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:91593.5-91593.29" + attribute \src "libresoc.v:93152.5-93152.29" switch \initial - attribute \src "libresoc.v:91593.9-91593.17" + attribute \src "libresoc.v:93152.9-93152.17" case 1'1 case end @@ -143635,14 +145752,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:91647.3-91701.6" - process $proc$libresoc.v:91647$3874 + attribute \src "libresoc.v:93206.3-93260.6" + process $proc$libresoc.v:93206$3907 assign { } { } assign { } { } assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:91648.5-91648.29" + attribute \src "libresoc.v:93207.5-93207.29" switch \initial - attribute \src "libresoc.v:91648.9-91648.17" + attribute \src "libresoc.v:93207.9-93207.17" case 1'1 case end @@ -143718,14 +145835,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:91702.3-91756.6" - process $proc$libresoc.v:91702$3875 + attribute \src "libresoc.v:93261.3-93315.6" + process $proc$libresoc.v:93261$3908 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:91703.5-91703.29" + attribute \src "libresoc.v:93262.5-93262.29" switch \initial - attribute \src "libresoc.v:91703.9-91703.17" + attribute \src "libresoc.v:93262.9-93262.17" case 1'1 case end @@ -143801,14 +145918,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:91757.3-91811.6" - process $proc$libresoc.v:91757$3876 + attribute \src "libresoc.v:93316.3-93370.6" + process $proc$libresoc.v:93316$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:91758.5-91758.29" + attribute \src "libresoc.v:93317.5-93317.29" switch \initial - attribute \src "libresoc.v:91758.9-91758.17" + attribute \src "libresoc.v:93317.9-93317.17" case 1'1 case end @@ -143884,14 +146001,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:91812.3-91866.6" - process $proc$libresoc.v:91812$3877 + attribute \src "libresoc.v:93371.3-93425.6" + process $proc$libresoc.v:93371$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:91813.5-91813.29" + attribute \src "libresoc.v:93372.5-93372.29" switch \initial - attribute \src "libresoc.v:91813.9-91813.17" + attribute \src "libresoc.v:93372.9-93372.17" case 1'1 case end @@ -143967,14 +146084,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:91867.3-91921.6" - process $proc$libresoc.v:91867$3878 + attribute \src "libresoc.v:93426.3-93480.6" + process $proc$libresoc.v:93426$3911 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:91868.5-91868.29" + attribute \src "libresoc.v:93427.5-93427.29" switch \initial - attribute \src "libresoc.v:91868.9-91868.17" + attribute \src "libresoc.v:93427.9-93427.17" case 1'1 case end @@ -144050,14 +146167,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:91922.3-91976.6" - process $proc$libresoc.v:91922$3879 + attribute \src "libresoc.v:93481.3-93535.6" + process $proc$libresoc.v:93481$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:91923.5-91923.29" + attribute \src "libresoc.v:93482.5-93482.29" switch \initial - attribute \src "libresoc.v:91923.9-91923.17" + attribute \src "libresoc.v:93482.9-93482.17" case 1'1 case end @@ -144133,14 +146250,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:91977.3-92031.6" - process $proc$libresoc.v:91977$3880 + attribute \src "libresoc.v:93536.3-93590.6" + process $proc$libresoc.v:93536$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:91978.5-91978.29" + attribute \src "libresoc.v:93537.5-93537.29" switch \initial - attribute \src "libresoc.v:91978.9-91978.17" + attribute \src "libresoc.v:93537.9-93537.17" case 1'1 case end @@ -144216,14 +146333,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:92032.3-92086.6" - process $proc$libresoc.v:92032$3881 + attribute \src "libresoc.v:93591.3-93645.6" + process $proc$libresoc.v:93591$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:92033.5-92033.29" + attribute \src "libresoc.v:93592.5-93592.29" switch \initial - attribute \src "libresoc.v:92033.9-92033.17" + attribute \src "libresoc.v:93592.9-93592.17" case 1'1 case end @@ -144299,14 +146416,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "libresoc.v:92087.3-92141.6" - process $proc$libresoc.v:92087$3882 + attribute \src "libresoc.v:93646.3-93700.6" + process $proc$libresoc.v:93646$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:92088.5-92088.29" + attribute \src "libresoc.v:93647.5-93647.29" switch \initial - attribute \src "libresoc.v:92088.9-92088.17" + attribute \src "libresoc.v:93647.9-93647.17" case 1'1 case end @@ -144382,14 +146499,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "libresoc.v:92142.3-92196.6" - process $proc$libresoc.v:92142$3883 + attribute \src "libresoc.v:93701.3-93755.6" + process $proc$libresoc.v:93701$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:92143.5-92143.29" + attribute \src "libresoc.v:93702.5-93702.29" switch \initial - attribute \src "libresoc.v:92143.9-92143.17" + attribute \src "libresoc.v:93702.9-93702.17" case 1'1 case end @@ -144465,14 +146582,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "libresoc.v:92197.3-92251.6" - process $proc$libresoc.v:92197$3884 + attribute \src "libresoc.v:93756.3-93810.6" + process $proc$libresoc.v:93756$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:92198.5-92198.29" + attribute \src "libresoc.v:93757.5-93757.29" switch \initial - attribute \src "libresoc.v:92198.9-92198.17" + attribute \src "libresoc.v:93757.9-93757.17" case 1'1 case end @@ -144548,14 +146665,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:92252.3-92306.6" - process $proc$libresoc.v:92252$3885 + attribute \src "libresoc.v:93811.3-93865.6" + process $proc$libresoc.v:93811$3918 assign { } { } assign { } { } assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:92253.5-92253.29" + attribute \src "libresoc.v:93812.5-93812.29" switch \initial - attribute \src "libresoc.v:92253.9-92253.17" + attribute \src "libresoc.v:93812.9-93812.17" case 1'1 case end @@ -144631,14 +146748,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:92307.3-92361.6" - process $proc$libresoc.v:92307$3886 + attribute \src "libresoc.v:93866.3-93920.6" + process $proc$libresoc.v:93866$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:92308.5-92308.29" + attribute \src "libresoc.v:93867.5-93867.29" switch \initial - attribute \src "libresoc.v:92308.9-92308.17" + attribute \src "libresoc.v:93867.9-93867.17" case 1'1 case end @@ -144714,14 +146831,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:92362.3-92416.6" - process $proc$libresoc.v:92362$3887 + attribute \src "libresoc.v:93921.3-93975.6" + process $proc$libresoc.v:93921$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:92363.5-92363.29" + attribute \src "libresoc.v:93922.5-93922.29" switch \initial - attribute \src "libresoc.v:92363.9-92363.17" + attribute \src "libresoc.v:93922.9-93922.17" case 1'1 case end @@ -144797,14 +146914,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:92417.3-92471.6" - process $proc$libresoc.v:92417$3888 + attribute \src "libresoc.v:93976.3-94030.6" + process $proc$libresoc.v:93976$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:92418.5-92418.29" + attribute \src "libresoc.v:93977.5-93977.29" switch \initial - attribute \src "libresoc.v:92418.9-92418.17" + attribute \src "libresoc.v:93977.9-93977.17" case 1'1 case end @@ -144880,14 +146997,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:92472.3-92526.6" - process $proc$libresoc.v:92472$3889 + attribute \src "libresoc.v:94031.3-94085.6" + process $proc$libresoc.v:94031$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:92473.5-92473.29" + attribute \src "libresoc.v:94032.5-94032.29" switch \initial - attribute \src "libresoc.v:92473.9-92473.17" + attribute \src "libresoc.v:94032.9-94032.17" case 1'1 case end @@ -144963,14 +147080,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end - attribute \src "libresoc.v:92527.3-92581.6" - process $proc$libresoc.v:92527$3890 + attribute \src "libresoc.v:94086.3-94140.6" + process $proc$libresoc.v:94086$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:92528.5-92528.29" + attribute \src "libresoc.v:94087.5-94087.29" switch \initial - attribute \src "libresoc.v:92528.9-92528.17" + attribute \src "libresoc.v:94087.9-94087.17" case 1'1 case end @@ -145046,14 +147163,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end - attribute \src "libresoc.v:92582.3-92636.6" - process $proc$libresoc.v:92582$3891 + attribute \src "libresoc.v:94141.3-94195.6" + process $proc$libresoc.v:94141$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:92583.5-92583.29" + attribute \src "libresoc.v:94142.5-94142.29" switch \initial - attribute \src "libresoc.v:92583.9-92583.17" + attribute \src "libresoc.v:94142.9-94142.17" case 1'1 case end @@ -145129,14 +147246,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:92637.3-92691.6" - process $proc$libresoc.v:92637$3892 + attribute \src "libresoc.v:94196.3-94250.6" + process $proc$libresoc.v:94196$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:92638.5-92638.29" + attribute \src "libresoc.v:94197.5-94197.29" switch \initial - attribute \src "libresoc.v:92638.9-92638.17" + attribute \src "libresoc.v:94197.9-94197.17" case 1'1 case end @@ -145212,14 +147329,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:92692.3-92746.6" - process $proc$libresoc.v:92692$3893 + attribute \src "libresoc.v:94251.3-94305.6" + process $proc$libresoc.v:94251$3926 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:92693.5-92693.29" + attribute \src "libresoc.v:94252.5-94252.29" switch \initial - attribute \src "libresoc.v:92693.9-92693.17" + attribute \src "libresoc.v:94252.9-94252.17" case 1'1 case end @@ -145295,14 +147412,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "libresoc.v:92747.3-92801.6" - process $proc$libresoc.v:92747$3894 + attribute \src "libresoc.v:94306.3-94360.6" + process $proc$libresoc.v:94306$3927 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:92748.5-92748.29" + assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] + attribute \src "libresoc.v:94307.5-94307.29" switch \initial - attribute \src "libresoc.v:92748.9-92748.17" + attribute \src "libresoc.v:94307.9-94307.17" case 1'1 case end @@ -145311,209 +147428,209 @@ module \dec31_dec_sub11 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub11_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:92807.1-96440.10" +attribute \src "libresoc.v:94366.1-98002.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:95821.3-95923.6" + attribute \src "libresoc.v:97383.3-97485.6" wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:95924.3-96026.6" + attribute \src "libresoc.v:97486.3-97588.6" wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:94585.3-94687.6" + attribute \src "libresoc.v:96147.3-96249.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:94997.3-95099.6" + attribute \src "libresoc.v:96559.3-96661.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:93246.3-93348.6" + attribute \src "libresoc.v:94808.3-94910.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:93349.3-93451.6" + attribute \src "libresoc.v:94911.3-95013.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:94482.3-94584.6" + attribute \src "libresoc.v:96044.3-96146.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:94894.3-94996.6" + attribute \src "libresoc.v:96456.3-96558.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:95409.3-95511.6" + attribute \src "libresoc.v:96971.3-97073.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:93143.3-93245.6" - wire width 13 $0\dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:96027.3-96129.6" + attribute \src "libresoc.v:94705.3-94807.6" + wire width 14 $0\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:97589.3-97691.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:96130.3-96232.6" + attribute \src "libresoc.v:97692.3-97794.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:96233.3-96335.6" + attribute \src "libresoc.v:97795.3-97897.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:94276.3-94378.6" + attribute \src "libresoc.v:95838.3-95940.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:94688.3-94790.6" + attribute \src "libresoc.v:96250.3-96352.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:94791.3-94893.6" + attribute \src "libresoc.v:96353.3-96455.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:95306.3-95408.6" + attribute \src "libresoc.v:96868.3-96970.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:94070.3-94172.6" + attribute \src "libresoc.v:95632.3-95734.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:95615.3-95717.6" + attribute \src "libresoc.v:97177.3-97279.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:96336.3-96438.6" - wire width 2 $0\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:94379.3-94481.6" + attribute \src "libresoc.v:97898.3-98000.6" + wire width 3 $0\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:95941.3-96043.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:95203.3-95305.6" + attribute \src "libresoc.v:96765.3-96867.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:95718.3-95820.6" + attribute \src "libresoc.v:97280.3-97382.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:95512.3-95614.6" + attribute \src "libresoc.v:97074.3-97176.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:95100.3-95202.6" + attribute \src "libresoc.v:96662.3-96764.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:93864.3-93966.6" + attribute \src "libresoc.v:95426.3-95528.6" wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:93967.3-94069.6" + attribute \src "libresoc.v:95529.3-95631.6" wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:93452.3-93554.6" + attribute \src "libresoc.v:95014.3-95116.6" wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:93555.3-93657.6" + attribute \src "libresoc.v:95117.3-95219.6" wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:93658.3-93760.6" + attribute \src "libresoc.v:95220.3-95322.6" wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:93761.3-93863.6" + attribute \src "libresoc.v:95323.3-95425.6" wire width 3 $0\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:94173.3-94275.6" + attribute \src "libresoc.v:95735.3-95837.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:92808.7-92808.20" + attribute \src "libresoc.v:94367.7-94367.20" wire $0\initial[0:0] - attribute \src "libresoc.v:95821.3-95923.6" + attribute \src "libresoc.v:97383.3-97485.6" wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:95924.3-96026.6" + attribute \src "libresoc.v:97486.3-97588.6" wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:94585.3-94687.6" + attribute \src "libresoc.v:96147.3-96249.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:94997.3-95099.6" + attribute \src "libresoc.v:96559.3-96661.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:93246.3-93348.6" + attribute \src "libresoc.v:94808.3-94910.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:93349.3-93451.6" + attribute \src "libresoc.v:94911.3-95013.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:94482.3-94584.6" + attribute \src "libresoc.v:96044.3-96146.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:94894.3-94996.6" + attribute \src "libresoc.v:96456.3-96558.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:95409.3-95511.6" + attribute \src "libresoc.v:96971.3-97073.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:93143.3-93245.6" - wire width 13 $1\dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:96027.3-96129.6" + attribute \src "libresoc.v:94705.3-94807.6" + wire width 14 $1\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:97589.3-97691.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:96130.3-96232.6" + attribute \src "libresoc.v:97692.3-97794.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:96233.3-96335.6" + attribute \src "libresoc.v:97795.3-97897.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:94276.3-94378.6" + attribute \src "libresoc.v:95838.3-95940.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:94688.3-94790.6" + attribute \src "libresoc.v:96250.3-96352.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:94791.3-94893.6" + attribute \src "libresoc.v:96353.3-96455.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:95306.3-95408.6" + attribute \src "libresoc.v:96868.3-96970.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:94070.3-94172.6" + attribute \src "libresoc.v:95632.3-95734.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:95615.3-95717.6" + attribute \src "libresoc.v:97177.3-97279.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:96336.3-96438.6" - wire width 2 $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:94379.3-94481.6" + attribute \src "libresoc.v:97898.3-98000.6" + wire width 3 $1\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:95941.3-96043.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:95203.3-95305.6" + attribute \src "libresoc.v:96765.3-96867.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:95718.3-95820.6" + attribute \src "libresoc.v:97280.3-97382.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:95512.3-95614.6" + attribute \src "libresoc.v:97074.3-97176.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:95100.3-95202.6" + attribute \src "libresoc.v:96662.3-96764.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:93864.3-93966.6" + attribute \src "libresoc.v:95426.3-95528.6" wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:93967.3-94069.6" + attribute \src "libresoc.v:95529.3-95631.6" wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:93452.3-93554.6" + attribute \src "libresoc.v:95014.3-95116.6" wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:93555.3-93657.6" + attribute \src "libresoc.v:95117.3-95219.6" wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:93658.3-93760.6" + attribute \src "libresoc.v:95220.3-95322.6" wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:93761.3-93863.6" + attribute \src "libresoc.v:95323.3-95425.6" wire width 3 $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:94173.3-94275.6" + attribute \src "libresoc.v:95735.3-95837.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -145593,21 +147710,22 @@ module \dec31_dec_sub15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub15_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub15_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -145713,6 +147831,7 @@ module \dec31_dec_sub15 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub15_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -145732,12 +147851,13 @@ module \dec31_dec_sub15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub15_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub15_out_sel + wire width 3 output 10 \dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -145813,28 +147933,28 @@ module \dec31_dec_sub15 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub15_upd - attribute \src "libresoc.v:92808.7-92808.15" + attribute \src "libresoc.v:94367.7-94367.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:92808.7-92808.20" - process $proc$libresoc.v:92808$3928 + attribute \src "libresoc.v:94367.7-94367.20" + process $proc$libresoc.v:94367$3961 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:93143.3-93245.6" - process $proc$libresoc.v:93143$3896 + attribute \src "libresoc.v:94705.3-94807.6" + process $proc$libresoc.v:94705$3929 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_function_unit[12:0] $1\dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:93144.5-93144.29" + assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] + attribute \src "libresoc.v:94706.5-94706.29" switch \initial - attribute \src "libresoc.v:93144.9-93144.17" + attribute \src "libresoc.v:94706.9-94706.17" case 1'1 case end @@ -145843,145 +147963,145 @@ module \dec31_dec_sub15 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 case - assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[12:0] + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:93246.3-93348.6" - process $proc$libresoc.v:93246$3897 + attribute \src "libresoc.v:94808.3-94910.6" + process $proc$libresoc.v:94808$3930 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:93247.5-93247.29" + attribute \src "libresoc.v:94809.5-94809.29" switch \initial - attribute \src "libresoc.v:93247.9-93247.17" + attribute \src "libresoc.v:94809.9-94809.17" case 1'1 case end @@ -146121,14 +148241,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:93349.3-93451.6" - process $proc$libresoc.v:93349$3898 + attribute \src "libresoc.v:94911.3-95013.6" + process $proc$libresoc.v:94911$3931 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:93350.5-93350.29" + attribute \src "libresoc.v:94912.5-94912.29" switch \initial - attribute \src "libresoc.v:93350.9-93350.17" + attribute \src "libresoc.v:94912.9-94912.17" case 1'1 case end @@ -146268,14 +148388,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:93452.3-93554.6" - process $proc$libresoc.v:93452$3899 + attribute \src "libresoc.v:95014.3-95116.6" + process $proc$libresoc.v:95014$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:93453.5-93453.29" + attribute \src "libresoc.v:95015.5-95015.29" switch \initial - attribute \src "libresoc.v:93453.9-93453.17" + attribute \src "libresoc.v:95015.9-95015.17" case 1'1 case end @@ -146415,14 +148535,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end - attribute \src "libresoc.v:93555.3-93657.6" - process $proc$libresoc.v:93555$3900 + attribute \src "libresoc.v:95117.3-95219.6" + process $proc$libresoc.v:95117$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:93556.5-93556.29" + attribute \src "libresoc.v:95118.5-95118.29" switch \initial - attribute \src "libresoc.v:93556.9-93556.17" + attribute \src "libresoc.v:95118.9-95118.17" case 1'1 case end @@ -146562,14 +148682,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end - attribute \src "libresoc.v:93658.3-93760.6" - process $proc$libresoc.v:93658$3901 + attribute \src "libresoc.v:95220.3-95322.6" + process $proc$libresoc.v:95220$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:93659.5-93659.29" + attribute \src "libresoc.v:95221.5-95221.29" switch \initial - attribute \src "libresoc.v:93659.9-93659.17" + attribute \src "libresoc.v:95221.9-95221.17" case 1'1 case end @@ -146709,14 +148829,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end - attribute \src "libresoc.v:93761.3-93863.6" - process $proc$libresoc.v:93761$3902 + attribute \src "libresoc.v:95323.3-95425.6" + process $proc$libresoc.v:95323$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:93762.5-93762.29" + attribute \src "libresoc.v:95324.5-95324.29" switch \initial - attribute \src "libresoc.v:93762.9-93762.17" + attribute \src "libresoc.v:95324.9-95324.17" case 1'1 case end @@ -146856,14 +148976,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end - attribute \src "libresoc.v:93864.3-93966.6" - process $proc$libresoc.v:93864$3903 + attribute \src "libresoc.v:95426.3-95528.6" + process $proc$libresoc.v:95426$3936 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:93865.5-93865.29" + attribute \src "libresoc.v:95427.5-95427.29" switch \initial - attribute \src "libresoc.v:93865.9-93865.17" + attribute \src "libresoc.v:95427.9-95427.17" case 1'1 case end @@ -147003,14 +149123,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end - attribute \src "libresoc.v:93967.3-94069.6" - process $proc$libresoc.v:93967$3904 + attribute \src "libresoc.v:95529.3-95631.6" + process $proc$libresoc.v:95529$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:93968.5-93968.29" + attribute \src "libresoc.v:95530.5-95530.29" switch \initial - attribute \src "libresoc.v:93968.9-93968.17" + attribute \src "libresoc.v:95530.9-95530.17" case 1'1 case end @@ -147150,14 +149270,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end - attribute \src "libresoc.v:94070.3-94172.6" - process $proc$libresoc.v:94070$3905 + attribute \src "libresoc.v:95632.3-95734.6" + process $proc$libresoc.v:95632$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:94071.5-94071.29" + attribute \src "libresoc.v:95633.5-95633.29" switch \initial - attribute \src "libresoc.v:94071.9-94071.17" + attribute \src "libresoc.v:95633.9-95633.17" case 1'1 case end @@ -147297,14 +149417,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:94173.3-94275.6" - process $proc$libresoc.v:94173$3906 + attribute \src "libresoc.v:95735.3-95837.6" + process $proc$libresoc.v:95735$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:94174.5-94174.29" + attribute \src "libresoc.v:95736.5-95736.29" switch \initial - attribute \src "libresoc.v:94174.9-94174.17" + attribute \src "libresoc.v:95736.9-95736.17" case 1'1 case end @@ -147444,14 +149564,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:94276.3-94378.6" - process $proc$libresoc.v:94276$3907 + attribute \src "libresoc.v:95838.3-95940.6" + process $proc$libresoc.v:95838$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:94277.5-94277.29" + attribute \src "libresoc.v:95839.5-95839.29" switch \initial - attribute \src "libresoc.v:94277.9-94277.17" + attribute \src "libresoc.v:95839.9-95839.17" case 1'1 case end @@ -147591,14 +149711,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:94379.3-94481.6" - process $proc$libresoc.v:94379$3908 + attribute \src "libresoc.v:95941.3-96043.6" + process $proc$libresoc.v:95941$3941 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:94380.5-94380.29" + attribute \src "libresoc.v:95942.5-95942.29" switch \initial - attribute \src "libresoc.v:94380.9-94380.17" + attribute \src "libresoc.v:95942.9-95942.17" case 1'1 case end @@ -147738,14 +149858,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:94482.3-94584.6" - process $proc$libresoc.v:94482$3909 + attribute \src "libresoc.v:96044.3-96146.6" + process $proc$libresoc.v:96044$3942 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:94483.5-94483.29" + attribute \src "libresoc.v:96045.5-96045.29" switch \initial - attribute \src "libresoc.v:94483.9-94483.17" + attribute \src "libresoc.v:96045.9-96045.17" case 1'1 case end @@ -147885,14 +150005,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:94585.3-94687.6" - process $proc$libresoc.v:94585$3910 + attribute \src "libresoc.v:96147.3-96249.6" + process $proc$libresoc.v:96147$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:94586.5-94586.29" + attribute \src "libresoc.v:96148.5-96148.29" switch \initial - attribute \src "libresoc.v:94586.9-94586.17" + attribute \src "libresoc.v:96148.9-96148.17" case 1'1 case end @@ -148032,14 +150152,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:94688.3-94790.6" - process $proc$libresoc.v:94688$3911 + attribute \src "libresoc.v:96250.3-96352.6" + process $proc$libresoc.v:96250$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:94689.5-94689.29" + attribute \src "libresoc.v:96251.5-96251.29" switch \initial - attribute \src "libresoc.v:94689.9-94689.17" + attribute \src "libresoc.v:96251.9-96251.17" case 1'1 case end @@ -148179,14 +150299,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:94791.3-94893.6" - process $proc$libresoc.v:94791$3912 + attribute \src "libresoc.v:96353.3-96455.6" + process $proc$libresoc.v:96353$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:94792.5-94792.29" + attribute \src "libresoc.v:96354.5-96354.29" switch \initial - attribute \src "libresoc.v:94792.9-94792.17" + attribute \src "libresoc.v:96354.9-96354.17" case 1'1 case end @@ -148326,14 +150446,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:94894.3-94996.6" - process $proc$libresoc.v:94894$3913 + attribute \src "libresoc.v:96456.3-96558.6" + process $proc$libresoc.v:96456$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:94895.5-94895.29" + attribute \src "libresoc.v:96457.5-96457.29" switch \initial - attribute \src "libresoc.v:94895.9-94895.17" + attribute \src "libresoc.v:96457.9-96457.17" case 1'1 case end @@ -148473,14 +150593,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:94997.3-95099.6" - process $proc$libresoc.v:94997$3914 + attribute \src "libresoc.v:96559.3-96661.6" + process $proc$libresoc.v:96559$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:94998.5-94998.29" + attribute \src "libresoc.v:96560.5-96560.29" switch \initial - attribute \src "libresoc.v:94998.9-94998.17" + attribute \src "libresoc.v:96560.9-96560.17" case 1'1 case end @@ -148620,14 +150740,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:95100.3-95202.6" - process $proc$libresoc.v:95100$3915 + attribute \src "libresoc.v:96662.3-96764.6" + process $proc$libresoc.v:96662$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:95101.5-95101.29" + attribute \src "libresoc.v:96663.5-96663.29" switch \initial - attribute \src "libresoc.v:95101.9-95101.17" + attribute \src "libresoc.v:96663.9-96663.17" case 1'1 case end @@ -148767,14 +150887,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:95203.3-95305.6" - process $proc$libresoc.v:95203$3916 + attribute \src "libresoc.v:96765.3-96867.6" + process $proc$libresoc.v:96765$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:95204.5-95204.29" + attribute \src "libresoc.v:96766.5-96766.29" switch \initial - attribute \src "libresoc.v:95204.9-95204.17" + attribute \src "libresoc.v:96766.9-96766.17" case 1'1 case end @@ -148914,14 +151034,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:95306.3-95408.6" - process $proc$libresoc.v:95306$3917 + attribute \src "libresoc.v:96868.3-96970.6" + process $proc$libresoc.v:96868$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:95307.5-95307.29" + attribute \src "libresoc.v:96869.5-96869.29" switch \initial - attribute \src "libresoc.v:95307.9-95307.17" + attribute \src "libresoc.v:96869.9-96869.17" case 1'1 case end @@ -149061,14 +151181,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:95409.3-95511.6" - process $proc$libresoc.v:95409$3918 + attribute \src "libresoc.v:96971.3-97073.6" + process $proc$libresoc.v:96971$3951 assign { } { } assign { } { } assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:95410.5-95410.29" + attribute \src "libresoc.v:96972.5-96972.29" switch \initial - attribute \src "libresoc.v:95410.9-95410.17" + attribute \src "libresoc.v:96972.9-96972.17" case 1'1 case end @@ -149208,14 +151328,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:95512.3-95614.6" - process $proc$libresoc.v:95512$3919 + attribute \src "libresoc.v:97074.3-97176.6" + process $proc$libresoc.v:97074$3952 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:95513.5-95513.29" + attribute \src "libresoc.v:97075.5-97075.29" switch \initial - attribute \src "libresoc.v:95513.9-95513.17" + attribute \src "libresoc.v:97075.9-97075.17" case 1'1 case end @@ -149355,14 +151475,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "libresoc.v:95615.3-95717.6" - process $proc$libresoc.v:95615$3920 + attribute \src "libresoc.v:97177.3-97279.6" + process $proc$libresoc.v:97177$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:95616.5-95616.29" + attribute \src "libresoc.v:97178.5-97178.29" switch \initial - attribute \src "libresoc.v:95616.9-95616.17" + attribute \src "libresoc.v:97178.9-97178.17" case 1'1 case end @@ -149502,14 +151622,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:95718.3-95820.6" - process $proc$libresoc.v:95718$3921 + attribute \src "libresoc.v:97280.3-97382.6" + process $proc$libresoc.v:97280$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:95719.5-95719.29" + attribute \src "libresoc.v:97281.5-97281.29" switch \initial - attribute \src "libresoc.v:95719.9-95719.17" + attribute \src "libresoc.v:97281.9-97281.17" case 1'1 case end @@ -149649,14 +151769,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:95821.3-95923.6" - process $proc$libresoc.v:95821$3922 + attribute \src "libresoc.v:97383.3-97485.6" + process $proc$libresoc.v:97383$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:95822.5-95822.29" + attribute \src "libresoc.v:97384.5-97384.29" switch \initial - attribute \src "libresoc.v:95822.9-95822.17" + attribute \src "libresoc.v:97384.9-97384.17" case 1'1 case end @@ -149796,14 +151916,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end - attribute \src "libresoc.v:95924.3-96026.6" - process $proc$libresoc.v:95924$3923 + attribute \src "libresoc.v:97486.3-97588.6" + process $proc$libresoc.v:97486$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:95925.5-95925.29" + attribute \src "libresoc.v:97487.5-97487.29" switch \initial - attribute \src "libresoc.v:95925.9-95925.17" + attribute \src "libresoc.v:97487.9-97487.17" case 1'1 case end @@ -149943,14 +152063,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end - attribute \src "libresoc.v:96027.3-96129.6" - process $proc$libresoc.v:96027$3924 + attribute \src "libresoc.v:97589.3-97691.6" + process $proc$libresoc.v:97589$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:96028.5-96028.29" + attribute \src "libresoc.v:97590.5-97590.29" switch \initial - attribute \src "libresoc.v:96028.9-96028.17" + attribute \src "libresoc.v:97590.9-97590.17" case 1'1 case end @@ -150090,14 +152210,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:96130.3-96232.6" - process $proc$libresoc.v:96130$3925 + attribute \src "libresoc.v:97692.3-97794.6" + process $proc$libresoc.v:97692$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:96131.5-96131.29" + attribute \src "libresoc.v:97693.5-97693.29" switch \initial - attribute \src "libresoc.v:96131.9-96131.17" + attribute \src "libresoc.v:97693.9-97693.17" case 1'1 case end @@ -150237,14 +152357,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:96233.3-96335.6" - process $proc$libresoc.v:96233$3926 + attribute \src "libresoc.v:97795.3-97897.6" + process $proc$libresoc.v:97795$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:96234.5-96234.29" + attribute \src "libresoc.v:97796.5-97796.29" switch \initial - attribute \src "libresoc.v:96234.9-96234.17" + attribute \src "libresoc.v:97796.9-97796.17" case 1'1 case end @@ -150384,14 +152504,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:96336.3-96438.6" - process $proc$libresoc.v:96336$3927 + attribute \src "libresoc.v:97898.3-98000.6" + process $proc$libresoc.v:97898$3960 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:96337.5-96337.29" + assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] + attribute \src "libresoc.v:97899.5-97899.29" switch \initial - attribute \src "libresoc.v:96337.9-96337.17" + attribute \src "libresoc.v:97899.9-97899.17" case 1'1 case end @@ -150400,273 +152520,273 @@ module \dec31_dec_sub15 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub15_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:96444.1-97101.10" +attribute \src "libresoc.v:98006.1-98666.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 - attribute \src "libresoc.v:97040.3-97049.6" + attribute \src "libresoc.v:98605.3-98614.6" wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:97050.3-97059.6" + attribute \src "libresoc.v:98615.3-98624.6" wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:96920.3-96929.6" + attribute \src "libresoc.v:98485.3-98494.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:96960.3-96969.6" + attribute \src "libresoc.v:98525.3-98534.6" wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:96790.3-96799.6" + attribute \src "libresoc.v:98355.3-98364.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:96800.3-96809.6" + attribute \src "libresoc.v:98365.3-98374.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:96910.3-96919.6" + attribute \src "libresoc.v:98475.3-98484.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:96950.3-96959.6" + attribute \src "libresoc.v:98515.3-98524.6" wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:97000.3-97009.6" + attribute \src "libresoc.v:98565.3-98574.6" wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:96780.3-96789.6" - wire width 13 $0\dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:97060.3-97069.6" + attribute \src "libresoc.v:98345.3-98354.6" + wire width 14 $0\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:98625.3-98634.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:97070.3-97079.6" + attribute \src "libresoc.v:98635.3-98644.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:97080.3-97089.6" + attribute \src "libresoc.v:98645.3-98654.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:96890.3-96899.6" + attribute \src "libresoc.v:98455.3-98464.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:96930.3-96939.6" + attribute \src "libresoc.v:98495.3-98504.6" wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:96940.3-96949.6" + attribute \src "libresoc.v:98505.3-98514.6" wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:96990.3-96999.6" + attribute \src "libresoc.v:98555.3-98564.6" wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:96870.3-96879.6" + attribute \src "libresoc.v:98435.3-98444.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:97020.3-97029.6" + attribute \src "libresoc.v:98585.3-98594.6" wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:97090.3-97099.6" - wire width 2 $0\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:96900.3-96909.6" + attribute \src "libresoc.v:98655.3-98664.6" + wire width 3 $0\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:98465.3-98474.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:96980.3-96989.6" + attribute \src "libresoc.v:98545.3-98554.6" wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:97030.3-97039.6" + attribute \src "libresoc.v:98595.3-98604.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:97010.3-97019.6" + attribute \src "libresoc.v:98575.3-98584.6" wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:96970.3-96979.6" + attribute \src "libresoc.v:98535.3-98544.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:96850.3-96859.6" + attribute \src "libresoc.v:98415.3-98424.6" wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:96860.3-96869.6" + attribute \src "libresoc.v:98425.3-98434.6" wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:96810.3-96819.6" + attribute \src "libresoc.v:98375.3-98384.6" wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:96820.3-96829.6" + attribute \src "libresoc.v:98385.3-98394.6" wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:96830.3-96839.6" + attribute \src "libresoc.v:98395.3-98404.6" wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:96840.3-96849.6" + attribute \src "libresoc.v:98405.3-98414.6" wire width 3 $0\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:96880.3-96889.6" + attribute \src "libresoc.v:98445.3-98454.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:96445.7-96445.20" + attribute \src "libresoc.v:98007.7-98007.20" wire $0\initial[0:0] - attribute \src "libresoc.v:97040.3-97049.6" + attribute \src "libresoc.v:98605.3-98614.6" wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:97050.3-97059.6" + attribute \src "libresoc.v:98615.3-98624.6" wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:96920.3-96929.6" + attribute \src "libresoc.v:98485.3-98494.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:96960.3-96969.6" + attribute \src "libresoc.v:98525.3-98534.6" wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:96790.3-96799.6" + attribute \src "libresoc.v:98355.3-98364.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:96800.3-96809.6" + attribute \src "libresoc.v:98365.3-98374.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:96910.3-96919.6" + attribute \src "libresoc.v:98475.3-98484.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:96950.3-96959.6" + attribute \src "libresoc.v:98515.3-98524.6" wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:97000.3-97009.6" + attribute \src "libresoc.v:98565.3-98574.6" wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:96780.3-96789.6" - wire width 13 $1\dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:97060.3-97069.6" + attribute \src "libresoc.v:98345.3-98354.6" + wire width 14 $1\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:98625.3-98634.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:97070.3-97079.6" + attribute \src "libresoc.v:98635.3-98644.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:97080.3-97089.6" + attribute \src "libresoc.v:98645.3-98654.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:96890.3-96899.6" + attribute \src "libresoc.v:98455.3-98464.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:96930.3-96939.6" + attribute \src "libresoc.v:98495.3-98504.6" wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:96940.3-96949.6" + attribute \src "libresoc.v:98505.3-98514.6" wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:96990.3-96999.6" + attribute \src "libresoc.v:98555.3-98564.6" wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:96870.3-96879.6" + attribute \src "libresoc.v:98435.3-98444.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:97020.3-97029.6" + attribute \src "libresoc.v:98585.3-98594.6" wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:97090.3-97099.6" - wire width 2 $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:96900.3-96909.6" + attribute \src "libresoc.v:98655.3-98664.6" + wire width 3 $1\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:98465.3-98474.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:96980.3-96989.6" + attribute \src "libresoc.v:98545.3-98554.6" wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:97030.3-97039.6" + attribute \src "libresoc.v:98595.3-98604.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:97010.3-97019.6" + attribute \src "libresoc.v:98575.3-98584.6" wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:96970.3-96979.6" + attribute \src "libresoc.v:98535.3-98544.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:96850.3-96859.6" + attribute \src "libresoc.v:98415.3-98424.6" wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:96860.3-96869.6" + attribute \src "libresoc.v:98425.3-98434.6" wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:96810.3-96819.6" + attribute \src "libresoc.v:98375.3-98384.6" wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:96820.3-96829.6" + attribute \src "libresoc.v:98385.3-98394.6" wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:96830.3-96839.6" + attribute \src "libresoc.v:98395.3-98404.6" wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:96840.3-96849.6" + attribute \src "libresoc.v:98405.3-98414.6" wire width 3 $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:96880.3-96889.6" + attribute \src "libresoc.v:98445.3-98454.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -150746,21 +152866,22 @@ module \dec31_dec_sub16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub16_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub16_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -150866,6 +152987,7 @@ module \dec31_dec_sub16 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub16_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -150885,12 +153007,13 @@ module \dec31_dec_sub16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub16_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub16_out_sel + wire width 3 output 10 \dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -150966,28 +153089,28 @@ module \dec31_dec_sub16 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub16_upd - attribute \src "libresoc.v:96445.7-96445.15" + attribute \src "libresoc.v:98007.7-98007.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:96445.7-96445.20" - process $proc$libresoc.v:96445$3961 + attribute \src "libresoc.v:98007.7-98007.20" + process $proc$libresoc.v:98007$3994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:96780.3-96789.6" - process $proc$libresoc.v:96780$3929 + attribute \src "libresoc.v:98345.3-98354.6" + process $proc$libresoc.v:98345$3962 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_function_unit[12:0] $1\dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:96781.5-96781.29" + assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] + attribute \src "libresoc.v:98346.5-98346.29" switch \initial - attribute \src "libresoc.v:96781.9-96781.17" + attribute \src "libresoc.v:98346.9-98346.17" case 1'1 case end @@ -150996,21 +153119,21 @@ module \dec31_dec_sub16 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub16_function_unit[13:0] 14'00000001000000 case - assign $1\dec31_dec_sub16_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub16_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[12:0] + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:96790.3-96799.6" - process $proc$libresoc.v:96790$3930 + attribute \src "libresoc.v:98355.3-98364.6" + process $proc$libresoc.v:98355$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:96791.5-96791.29" + attribute \src "libresoc.v:98356.5-98356.29" switch \initial - attribute \src "libresoc.v:96791.9-96791.17" + attribute \src "libresoc.v:98356.9-98356.17" case 1'1 case end @@ -151026,14 +153149,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:96800.3-96809.6" - process $proc$libresoc.v:96800$3931 + attribute \src "libresoc.v:98365.3-98374.6" + process $proc$libresoc.v:98365$3964 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:96801.5-96801.29" + attribute \src "libresoc.v:98366.5-98366.29" switch \initial - attribute \src "libresoc.v:96801.9-96801.17" + attribute \src "libresoc.v:98366.9-98366.17" case 1'1 case end @@ -151049,14 +153172,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:96810.3-96819.6" - process $proc$libresoc.v:96810$3932 + attribute \src "libresoc.v:98375.3-98384.6" + process $proc$libresoc.v:98375$3965 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:96811.5-96811.29" + attribute \src "libresoc.v:98376.5-98376.29" switch \initial - attribute \src "libresoc.v:96811.9-96811.17" + attribute \src "libresoc.v:98376.9-98376.17" case 1'1 case end @@ -151072,14 +153195,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end - attribute \src "libresoc.v:96820.3-96829.6" - process $proc$libresoc.v:96820$3933 + attribute \src "libresoc.v:98385.3-98394.6" + process $proc$libresoc.v:98385$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:96821.5-96821.29" + attribute \src "libresoc.v:98386.5-98386.29" switch \initial - attribute \src "libresoc.v:96821.9-96821.17" + attribute \src "libresoc.v:98386.9-98386.17" case 1'1 case end @@ -151095,14 +153218,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end - attribute \src "libresoc.v:96830.3-96839.6" - process $proc$libresoc.v:96830$3934 + attribute \src "libresoc.v:98395.3-98404.6" + process $proc$libresoc.v:98395$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:96831.5-96831.29" + attribute \src "libresoc.v:98396.5-98396.29" switch \initial - attribute \src "libresoc.v:96831.9-96831.17" + attribute \src "libresoc.v:98396.9-98396.17" case 1'1 case end @@ -151118,14 +153241,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end - attribute \src "libresoc.v:96840.3-96849.6" - process $proc$libresoc.v:96840$3935 + attribute \src "libresoc.v:98405.3-98414.6" + process $proc$libresoc.v:98405$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:96841.5-96841.29" + attribute \src "libresoc.v:98406.5-98406.29" switch \initial - attribute \src "libresoc.v:96841.9-96841.17" + attribute \src "libresoc.v:98406.9-98406.17" case 1'1 case end @@ -151141,14 +153264,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end - attribute \src "libresoc.v:96850.3-96859.6" - process $proc$libresoc.v:96850$3936 + attribute \src "libresoc.v:98415.3-98424.6" + process $proc$libresoc.v:98415$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:96851.5-96851.29" + attribute \src "libresoc.v:98416.5-98416.29" switch \initial - attribute \src "libresoc.v:96851.9-96851.17" + attribute \src "libresoc.v:98416.9-98416.17" case 1'1 case end @@ -151164,14 +153287,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end - attribute \src "libresoc.v:96860.3-96869.6" - process $proc$libresoc.v:96860$3937 + attribute \src "libresoc.v:98425.3-98434.6" + process $proc$libresoc.v:98425$3970 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:96861.5-96861.29" + attribute \src "libresoc.v:98426.5-98426.29" switch \initial - attribute \src "libresoc.v:96861.9-96861.17" + attribute \src "libresoc.v:98426.9-98426.17" case 1'1 case end @@ -151187,14 +153310,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end - attribute \src "libresoc.v:96870.3-96879.6" - process $proc$libresoc.v:96870$3938 + attribute \src "libresoc.v:98435.3-98444.6" + process $proc$libresoc.v:98435$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:96871.5-96871.29" + attribute \src "libresoc.v:98436.5-98436.29" switch \initial - attribute \src "libresoc.v:96871.9-96871.17" + attribute \src "libresoc.v:98436.9-98436.17" case 1'1 case end @@ -151210,14 +153333,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:96880.3-96889.6" - process $proc$libresoc.v:96880$3939 + attribute \src "libresoc.v:98445.3-98454.6" + process $proc$libresoc.v:98445$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:96881.5-96881.29" + attribute \src "libresoc.v:98446.5-98446.29" switch \initial - attribute \src "libresoc.v:96881.9-96881.17" + attribute \src "libresoc.v:98446.9-98446.17" case 1'1 case end @@ -151233,14 +153356,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:96890.3-96899.6" - process $proc$libresoc.v:96890$3940 + attribute \src "libresoc.v:98455.3-98464.6" + process $proc$libresoc.v:98455$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:96891.5-96891.29" + attribute \src "libresoc.v:98456.5-98456.29" switch \initial - attribute \src "libresoc.v:96891.9-96891.17" + attribute \src "libresoc.v:98456.9-98456.17" case 1'1 case end @@ -151256,14 +153379,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:96900.3-96909.6" - process $proc$libresoc.v:96900$3941 + attribute \src "libresoc.v:98465.3-98474.6" + process $proc$libresoc.v:98465$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:96901.5-96901.29" + attribute \src "libresoc.v:98466.5-98466.29" switch \initial - attribute \src "libresoc.v:96901.9-96901.17" + attribute \src "libresoc.v:98466.9-98466.17" case 1'1 case end @@ -151279,14 +153402,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:96910.3-96919.6" - process $proc$libresoc.v:96910$3942 + attribute \src "libresoc.v:98475.3-98484.6" + process $proc$libresoc.v:98475$3975 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:96911.5-96911.29" + attribute \src "libresoc.v:98476.5-98476.29" switch \initial - attribute \src "libresoc.v:96911.9-96911.17" + attribute \src "libresoc.v:98476.9-98476.17" case 1'1 case end @@ -151302,14 +153425,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:96920.3-96929.6" - process $proc$libresoc.v:96920$3943 + attribute \src "libresoc.v:98485.3-98494.6" + process $proc$libresoc.v:98485$3976 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:96921.5-96921.29" + attribute \src "libresoc.v:98486.5-98486.29" switch \initial - attribute \src "libresoc.v:96921.9-96921.17" + attribute \src "libresoc.v:98486.9-98486.17" case 1'1 case end @@ -151325,14 +153448,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:96930.3-96939.6" - process $proc$libresoc.v:96930$3944 + attribute \src "libresoc.v:98495.3-98504.6" + process $proc$libresoc.v:98495$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:96931.5-96931.29" + attribute \src "libresoc.v:98496.5-98496.29" switch \initial - attribute \src "libresoc.v:96931.9-96931.17" + attribute \src "libresoc.v:98496.9-98496.17" case 1'1 case end @@ -151348,14 +153471,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:96940.3-96949.6" - process $proc$libresoc.v:96940$3945 + attribute \src "libresoc.v:98505.3-98514.6" + process $proc$libresoc.v:98505$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:96941.5-96941.29" + attribute \src "libresoc.v:98506.5-98506.29" switch \initial - attribute \src "libresoc.v:96941.9-96941.17" + attribute \src "libresoc.v:98506.9-98506.17" case 1'1 case end @@ -151371,14 +153494,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:96950.3-96959.6" - process $proc$libresoc.v:96950$3946 + attribute \src "libresoc.v:98515.3-98524.6" + process $proc$libresoc.v:98515$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:96951.5-96951.29" + attribute \src "libresoc.v:98516.5-98516.29" switch \initial - attribute \src "libresoc.v:96951.9-96951.17" + attribute \src "libresoc.v:98516.9-98516.17" case 1'1 case end @@ -151394,14 +153517,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:96960.3-96969.6" - process $proc$libresoc.v:96960$3947 + attribute \src "libresoc.v:98525.3-98534.6" + process $proc$libresoc.v:98525$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:96961.5-96961.29" + attribute \src "libresoc.v:98526.5-98526.29" switch \initial - attribute \src "libresoc.v:96961.9-96961.17" + attribute \src "libresoc.v:98526.9-98526.17" case 1'1 case end @@ -151417,14 +153540,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:96970.3-96979.6" - process $proc$libresoc.v:96970$3948 + attribute \src "libresoc.v:98535.3-98544.6" + process $proc$libresoc.v:98535$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:96971.5-96971.29" + attribute \src "libresoc.v:98536.5-98536.29" switch \initial - attribute \src "libresoc.v:96971.9-96971.17" + attribute \src "libresoc.v:98536.9-98536.17" case 1'1 case end @@ -151440,14 +153563,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:96980.3-96989.6" - process $proc$libresoc.v:96980$3949 + attribute \src "libresoc.v:98545.3-98554.6" + process $proc$libresoc.v:98545$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:96981.5-96981.29" + attribute \src "libresoc.v:98546.5-98546.29" switch \initial - attribute \src "libresoc.v:96981.9-96981.17" + attribute \src "libresoc.v:98546.9-98546.17" case 1'1 case end @@ -151463,14 +153586,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:96990.3-96999.6" - process $proc$libresoc.v:96990$3950 + attribute \src "libresoc.v:98555.3-98564.6" + process $proc$libresoc.v:98555$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:96991.5-96991.29" + attribute \src "libresoc.v:98556.5-98556.29" switch \initial - attribute \src "libresoc.v:96991.9-96991.17" + attribute \src "libresoc.v:98556.9-98556.17" case 1'1 case end @@ -151486,14 +153609,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "libresoc.v:97000.3-97009.6" - process $proc$libresoc.v:97000$3951 + attribute \src "libresoc.v:98565.3-98574.6" + process $proc$libresoc.v:98565$3984 assign { } { } assign { } { } assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:97001.5-97001.29" + attribute \src "libresoc.v:98566.5-98566.29" switch \initial - attribute \src "libresoc.v:97001.9-97001.17" + attribute \src "libresoc.v:98566.9-98566.17" case 1'1 case end @@ -151509,14 +153632,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "libresoc.v:97010.3-97019.6" - process $proc$libresoc.v:97010$3952 + attribute \src "libresoc.v:98575.3-98584.6" + process $proc$libresoc.v:98575$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:97011.5-97011.29" + attribute \src "libresoc.v:98576.5-98576.29" switch \initial - attribute \src "libresoc.v:97011.9-97011.17" + attribute \src "libresoc.v:98576.9-98576.17" case 1'1 case end @@ -151532,14 +153655,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:97020.3-97029.6" - process $proc$libresoc.v:97020$3953 + attribute \src "libresoc.v:98585.3-98594.6" + process $proc$libresoc.v:98585$3986 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:97021.5-97021.29" + attribute \src "libresoc.v:98586.5-98586.29" switch \initial - attribute \src "libresoc.v:97021.9-97021.17" + attribute \src "libresoc.v:98586.9-98586.17" case 1'1 case end @@ -151555,14 +153678,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "libresoc.v:97030.3-97039.6" - process $proc$libresoc.v:97030$3954 + attribute \src "libresoc.v:98595.3-98604.6" + process $proc$libresoc.v:98595$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:97031.5-97031.29" + attribute \src "libresoc.v:98596.5-98596.29" switch \initial - attribute \src "libresoc.v:97031.9-97031.17" + attribute \src "libresoc.v:98596.9-98596.17" case 1'1 case end @@ -151578,14 +153701,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "libresoc.v:97040.3-97049.6" - process $proc$libresoc.v:97040$3955 + attribute \src "libresoc.v:98605.3-98614.6" + process $proc$libresoc.v:98605$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:97041.5-97041.29" + attribute \src "libresoc.v:98606.5-98606.29" switch \initial - attribute \src "libresoc.v:97041.9-97041.17" + attribute \src "libresoc.v:98606.9-98606.17" case 1'1 case end @@ -151601,14 +153724,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] end - attribute \src "libresoc.v:97050.3-97059.6" - process $proc$libresoc.v:97050$3956 + attribute \src "libresoc.v:98615.3-98624.6" + process $proc$libresoc.v:98615$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:97051.5-97051.29" + attribute \src "libresoc.v:98616.5-98616.29" switch \initial - attribute \src "libresoc.v:97051.9-97051.17" + attribute \src "libresoc.v:98616.9-98616.17" case 1'1 case end @@ -151624,14 +153747,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end - attribute \src "libresoc.v:97060.3-97069.6" - process $proc$libresoc.v:97060$3957 + attribute \src "libresoc.v:98625.3-98634.6" + process $proc$libresoc.v:98625$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:97061.5-97061.29" + attribute \src "libresoc.v:98626.5-98626.29" switch \initial - attribute \src "libresoc.v:97061.9-97061.17" + attribute \src "libresoc.v:98626.9-98626.17" case 1'1 case end @@ -151647,14 +153770,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "libresoc.v:97070.3-97079.6" - process $proc$libresoc.v:97070$3958 + attribute \src "libresoc.v:98635.3-98644.6" + process $proc$libresoc.v:98635$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:97071.5-97071.29" + attribute \src "libresoc.v:98636.5-98636.29" switch \initial - attribute \src "libresoc.v:97071.9-97071.17" + attribute \src "libresoc.v:98636.9-98636.17" case 1'1 case end @@ -151670,14 +153793,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "libresoc.v:97080.3-97089.6" - process $proc$libresoc.v:97080$3959 + attribute \src "libresoc.v:98645.3-98654.6" + process $proc$libresoc.v:98645$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:97081.5-97081.29" + attribute \src "libresoc.v:98646.5-98646.29" switch \initial - attribute \src "libresoc.v:97081.9-97081.17" + attribute \src "libresoc.v:98646.9-98646.17" case 1'1 case end @@ -151693,14 +153816,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "libresoc.v:97090.3-97099.6" - process $proc$libresoc.v:97090$3960 + attribute \src "libresoc.v:98655.3-98664.6" + process $proc$libresoc.v:98655$3993 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:97091.5-97091.29" + assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] + attribute \src "libresoc.v:98656.5-98656.29" switch \initial - attribute \src "libresoc.v:97091.9-97091.17" + attribute \src "libresoc.v:98656.9-98656.17" case 1'1 case end @@ -151709,149 +153832,149 @@ module \dec31_dec_sub16 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub16_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub16_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:97105.1-98146.10" +attribute \src "libresoc.v:98670.1-99714.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 - attribute \src "libresoc.v:98013.3-98034.6" + attribute \src "libresoc.v:99581.3-99602.6" wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:98035.3-98056.6" + attribute \src "libresoc.v:99603.3-99624.6" wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:97749.3-97770.6" + attribute \src "libresoc.v:99317.3-99338.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:97837.3-97858.6" + attribute \src "libresoc.v:99405.3-99426.6" wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:97463.3-97484.6" + attribute \src "libresoc.v:99031.3-99052.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:97485.3-97506.6" + attribute \src "libresoc.v:99053.3-99074.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:97727.3-97748.6" + attribute \src "libresoc.v:99295.3-99316.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:97815.3-97836.6" + attribute \src "libresoc.v:99383.3-99404.6" wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:97925.3-97946.6" + attribute \src "libresoc.v:99493.3-99514.6" wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:97441.3-97462.6" - wire width 13 $0\dec31_dec_sub18_function_unit[12:0] - attribute \src "libresoc.v:98057.3-98078.6" + attribute \src "libresoc.v:99009.3-99030.6" + wire width 14 $0\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99625.3-99646.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:98079.3-98100.6" + attribute \src "libresoc.v:99647.3-99668.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:98101.3-98122.6" + attribute \src "libresoc.v:99669.3-99690.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:97683.3-97704.6" + attribute \src "libresoc.v:99251.3-99272.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:97771.3-97792.6" + attribute \src "libresoc.v:99339.3-99360.6" wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:97793.3-97814.6" + attribute \src "libresoc.v:99361.3-99382.6" wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:97903.3-97924.6" + attribute \src "libresoc.v:99471.3-99492.6" wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:97639.3-97660.6" + attribute \src "libresoc.v:99207.3-99228.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:97969.3-97990.6" + attribute \src "libresoc.v:99537.3-99558.6" wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:98123.3-98144.6" - wire width 2 $0\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:97705.3-97726.6" + attribute \src "libresoc.v:99691.3-99712.6" + wire width 3 $0\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:99273.3-99294.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:97881.3-97902.6" + attribute \src "libresoc.v:99449.3-99470.6" wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:97991.3-98012.6" + attribute \src "libresoc.v:99559.3-99580.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:97947.3-97968.6" + attribute \src "libresoc.v:99515.3-99536.6" wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:97859.3-97880.6" + attribute \src "libresoc.v:99427.3-99448.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:97595.3-97616.6" + attribute \src "libresoc.v:99163.3-99184.6" wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:97617.3-97638.6" + attribute \src "libresoc.v:99185.3-99206.6" wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:97507.3-97528.6" + attribute \src "libresoc.v:99075.3-99096.6" wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:97529.3-97550.6" + attribute \src "libresoc.v:99097.3-99118.6" wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:97551.3-97572.6" + attribute \src "libresoc.v:99119.3-99140.6" wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:97573.3-97594.6" + attribute \src "libresoc.v:99141.3-99162.6" wire width 3 $0\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:97661.3-97682.6" + attribute \src "libresoc.v:99229.3-99250.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:97106.7-97106.20" + attribute \src "libresoc.v:98671.7-98671.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98013.3-98034.6" + attribute \src "libresoc.v:99581.3-99602.6" wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:98035.3-98056.6" + attribute \src "libresoc.v:99603.3-99624.6" wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:97749.3-97770.6" + attribute \src "libresoc.v:99317.3-99338.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:97837.3-97858.6" + attribute \src "libresoc.v:99405.3-99426.6" wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:97463.3-97484.6" + attribute \src "libresoc.v:99031.3-99052.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:97485.3-97506.6" + attribute \src "libresoc.v:99053.3-99074.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:97727.3-97748.6" + attribute \src "libresoc.v:99295.3-99316.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:97815.3-97836.6" + attribute \src "libresoc.v:99383.3-99404.6" wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:97925.3-97946.6" + attribute \src "libresoc.v:99493.3-99514.6" wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:97441.3-97462.6" - wire width 13 $1\dec31_dec_sub18_function_unit[12:0] - attribute \src "libresoc.v:98057.3-98078.6" + attribute \src "libresoc.v:99009.3-99030.6" + wire width 14 $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99625.3-99646.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:98079.3-98100.6" + attribute \src "libresoc.v:99647.3-99668.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:98101.3-98122.6" + attribute \src "libresoc.v:99669.3-99690.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:97683.3-97704.6" + attribute \src "libresoc.v:99251.3-99272.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:97771.3-97792.6" + attribute \src "libresoc.v:99339.3-99360.6" wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:97793.3-97814.6" + attribute \src "libresoc.v:99361.3-99382.6" wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:97903.3-97924.6" + attribute \src "libresoc.v:99471.3-99492.6" wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:97639.3-97660.6" + attribute \src "libresoc.v:99207.3-99228.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:97969.3-97990.6" + attribute \src "libresoc.v:99537.3-99558.6" wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:98123.3-98144.6" - wire width 2 $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:97705.3-97726.6" + attribute \src "libresoc.v:99691.3-99712.6" + wire width 3 $1\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:99273.3-99294.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:97881.3-97902.6" + attribute \src "libresoc.v:99449.3-99470.6" wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:97991.3-98012.6" + attribute \src "libresoc.v:99559.3-99580.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:97947.3-97968.6" + attribute \src "libresoc.v:99515.3-99536.6" wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:97859.3-97880.6" + attribute \src "libresoc.v:99427.3-99448.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:97595.3-97616.6" + attribute \src "libresoc.v:99163.3-99184.6" wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:97617.3-97638.6" + attribute \src "libresoc.v:99185.3-99206.6" wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:97507.3-97528.6" + attribute \src "libresoc.v:99075.3-99096.6" wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:97529.3-97550.6" + attribute \src "libresoc.v:99097.3-99118.6" wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:97551.3-97572.6" + attribute \src "libresoc.v:99119.3-99140.6" wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:97573.3-97594.6" + attribute \src "libresoc.v:99141.3-99162.6" wire width 3 $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:97661.3-97682.6" + attribute \src "libresoc.v:99229.3-99250.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -151931,21 +154054,22 @@ module \dec31_dec_sub18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub18_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -152051,6 +154175,7 @@ module \dec31_dec_sub18 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub18_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -152070,12 +154195,13 @@ module \dec31_dec_sub18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub18_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub18_out_sel + wire width 3 output 10 \dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -152151,28 +154277,28 @@ module \dec31_dec_sub18 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub18_upd - attribute \src "libresoc.v:97106.7-97106.15" + attribute \src "libresoc.v:98671.7-98671.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:97106.7-97106.20" - process $proc$libresoc.v:97106$3994 + attribute \src "libresoc.v:98671.7-98671.20" + process $proc$libresoc.v:98671$4027 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:97441.3-97462.6" - process $proc$libresoc.v:97441$3962 + attribute \src "libresoc.v:99009.3-99030.6" + process $proc$libresoc.v:99009$3995 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_function_unit[12:0] $1\dec31_dec_sub18_function_unit[12:0] - attribute \src "libresoc.v:97442.5-97442.29" + assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99010.5-99010.29" switch \initial - attribute \src "libresoc.v:97442.9-97442.17" + attribute \src "libresoc.v:99010.9-99010.17" case 1'1 case end @@ -152181,37 +154307,37 @@ module \dec31_dec_sub18 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_function_unit[12:0] 13'0000010000000 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_function_unit[12:0] 13'0000010000000 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_function_unit[12:0] 13'0100000000000 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_function_unit[12:0] 13'0100000000000 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_function_unit[12:0] 13'0100000000000 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 case - assign $1\dec31_dec_sub18_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[12:0] + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] end - attribute \src "libresoc.v:97463.3-97484.6" - process $proc$libresoc.v:97463$3963 + attribute \src "libresoc.v:99031.3-99052.6" + process $proc$libresoc.v:99031$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:97464.5-97464.29" + attribute \src "libresoc.v:99032.5-99032.29" switch \initial - attribute \src "libresoc.v:97464.9-97464.17" + attribute \src "libresoc.v:99032.9-99032.17" case 1'1 case end @@ -152243,14 +154369,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "libresoc.v:97485.3-97506.6" - process $proc$libresoc.v:97485$3964 + attribute \src "libresoc.v:99053.3-99074.6" + process $proc$libresoc.v:99053$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:97486.5-97486.29" + attribute \src "libresoc.v:99054.5-99054.29" switch \initial - attribute \src "libresoc.v:97486.9-97486.17" + attribute \src "libresoc.v:99054.9-99054.17" case 1'1 case end @@ -152282,14 +154408,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end - attribute \src "libresoc.v:97507.3-97528.6" - process $proc$libresoc.v:97507$3965 + attribute \src "libresoc.v:99075.3-99096.6" + process $proc$libresoc.v:99075$3998 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:97508.5-97508.29" + attribute \src "libresoc.v:99076.5-99076.29" switch \initial - attribute \src "libresoc.v:97508.9-97508.17" + attribute \src "libresoc.v:99076.9-99076.17" case 1'1 case end @@ -152321,14 +154447,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] end - attribute \src "libresoc.v:97529.3-97550.6" - process $proc$libresoc.v:97529$3966 + attribute \src "libresoc.v:99097.3-99118.6" + process $proc$libresoc.v:99097$3999 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:97530.5-97530.29" + attribute \src "libresoc.v:99098.5-99098.29" switch \initial - attribute \src "libresoc.v:97530.9-97530.17" + attribute \src "libresoc.v:99098.9-99098.17" case 1'1 case end @@ -152360,14 +154486,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] end - attribute \src "libresoc.v:97551.3-97572.6" - process $proc$libresoc.v:97551$3967 + attribute \src "libresoc.v:99119.3-99140.6" + process $proc$libresoc.v:99119$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:97552.5-97552.29" + attribute \src "libresoc.v:99120.5-99120.29" switch \initial - attribute \src "libresoc.v:97552.9-97552.17" + attribute \src "libresoc.v:99120.9-99120.17" case 1'1 case end @@ -152399,14 +154525,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] end - attribute \src "libresoc.v:97573.3-97594.6" - process $proc$libresoc.v:97573$3968 + attribute \src "libresoc.v:99141.3-99162.6" + process $proc$libresoc.v:99141$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:97574.5-97574.29" + attribute \src "libresoc.v:99142.5-99142.29" switch \initial - attribute \src "libresoc.v:97574.9-97574.17" + attribute \src "libresoc.v:99142.9-99142.17" case 1'1 case end @@ -152438,14 +154564,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] end - attribute \src "libresoc.v:97595.3-97616.6" - process $proc$libresoc.v:97595$3969 + attribute \src "libresoc.v:99163.3-99184.6" + process $proc$libresoc.v:99163$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:97596.5-97596.29" + attribute \src "libresoc.v:99164.5-99164.29" switch \initial - attribute \src "libresoc.v:97596.9-97596.17" + attribute \src "libresoc.v:99164.9-99164.17" case 1'1 case end @@ -152477,14 +154603,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] end - attribute \src "libresoc.v:97617.3-97638.6" - process $proc$libresoc.v:97617$3970 + attribute \src "libresoc.v:99185.3-99206.6" + process $proc$libresoc.v:99185$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:97618.5-97618.29" + attribute \src "libresoc.v:99186.5-99186.29" switch \initial - attribute \src "libresoc.v:97618.9-97618.17" + attribute \src "libresoc.v:99186.9-99186.17" case 1'1 case end @@ -152516,14 +154642,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] end - attribute \src "libresoc.v:97639.3-97660.6" - process $proc$libresoc.v:97639$3971 + attribute \src "libresoc.v:99207.3-99228.6" + process $proc$libresoc.v:99207$4004 assign { } { } assign { } { } assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:97640.5-97640.29" + attribute \src "libresoc.v:99208.5-99208.29" switch \initial - attribute \src "libresoc.v:97640.9-97640.17" + attribute \src "libresoc.v:99208.9-99208.17" case 1'1 case end @@ -152555,14 +154681,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end - attribute \src "libresoc.v:97661.3-97682.6" - process $proc$libresoc.v:97661$3972 + attribute \src "libresoc.v:99229.3-99250.6" + process $proc$libresoc.v:99229$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:97662.5-97662.29" + attribute \src "libresoc.v:99230.5-99230.29" switch \initial - attribute \src "libresoc.v:97662.9-97662.17" + attribute \src "libresoc.v:99230.9-99230.17" case 1'1 case end @@ -152594,14 +154720,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end - attribute \src "libresoc.v:97683.3-97704.6" - process $proc$libresoc.v:97683$3973 + attribute \src "libresoc.v:99251.3-99272.6" + process $proc$libresoc.v:99251$4006 assign { } { } assign { } { } assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:97684.5-97684.29" + attribute \src "libresoc.v:99252.5-99252.29" switch \initial - attribute \src "libresoc.v:97684.9-97684.17" + attribute \src "libresoc.v:99252.9-99252.17" case 1'1 case end @@ -152633,14 +154759,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end - attribute \src "libresoc.v:97705.3-97726.6" - process $proc$libresoc.v:97705$3974 + attribute \src "libresoc.v:99273.3-99294.6" + process $proc$libresoc.v:99273$4007 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:97706.5-97706.29" + attribute \src "libresoc.v:99274.5-99274.29" switch \initial - attribute \src "libresoc.v:97706.9-97706.17" + attribute \src "libresoc.v:99274.9-99274.17" case 1'1 case end @@ -152672,14 +154798,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end - attribute \src "libresoc.v:97727.3-97748.6" - process $proc$libresoc.v:97727$3975 + attribute \src "libresoc.v:99295.3-99316.6" + process $proc$libresoc.v:99295$4008 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:97728.5-97728.29" + attribute \src "libresoc.v:99296.5-99296.29" switch \initial - attribute \src "libresoc.v:97728.9-97728.17" + attribute \src "libresoc.v:99296.9-99296.17" case 1'1 case end @@ -152711,14 +154837,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end - attribute \src "libresoc.v:97749.3-97770.6" - process $proc$libresoc.v:97749$3976 + attribute \src "libresoc.v:99317.3-99338.6" + process $proc$libresoc.v:99317$4009 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:97750.5-97750.29" + attribute \src "libresoc.v:99318.5-99318.29" switch \initial - attribute \src "libresoc.v:97750.9-97750.17" + attribute \src "libresoc.v:99318.9-99318.17" case 1'1 case end @@ -152750,14 +154876,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:97771.3-97792.6" - process $proc$libresoc.v:97771$3977 + attribute \src "libresoc.v:99339.3-99360.6" + process $proc$libresoc.v:99339$4010 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:97772.5-97772.29" + attribute \src "libresoc.v:99340.5-99340.29" switch \initial - attribute \src "libresoc.v:97772.9-97772.17" + attribute \src "libresoc.v:99340.9-99340.17" case 1'1 case end @@ -152789,14 +154915,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:97793.3-97814.6" - process $proc$libresoc.v:97793$3978 + attribute \src "libresoc.v:99361.3-99382.6" + process $proc$libresoc.v:99361$4011 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:97794.5-97794.29" + attribute \src "libresoc.v:99362.5-99362.29" switch \initial - attribute \src "libresoc.v:97794.9-97794.17" + attribute \src "libresoc.v:99362.9-99362.17" case 1'1 case end @@ -152828,14 +154954,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:97815.3-97836.6" - process $proc$libresoc.v:97815$3979 + attribute \src "libresoc.v:99383.3-99404.6" + process $proc$libresoc.v:99383$4012 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:97816.5-97816.29" + attribute \src "libresoc.v:99384.5-99384.29" switch \initial - attribute \src "libresoc.v:97816.9-97816.17" + attribute \src "libresoc.v:99384.9-99384.17" case 1'1 case end @@ -152867,14 +154993,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:97837.3-97858.6" - process $proc$libresoc.v:97837$3980 + attribute \src "libresoc.v:99405.3-99426.6" + process $proc$libresoc.v:99405$4013 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:97838.5-97838.29" + attribute \src "libresoc.v:99406.5-99406.29" switch \initial - attribute \src "libresoc.v:97838.9-97838.17" + attribute \src "libresoc.v:99406.9-99406.17" case 1'1 case end @@ -152906,14 +155032,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:97859.3-97880.6" - process $proc$libresoc.v:97859$3981 + attribute \src "libresoc.v:99427.3-99448.6" + process $proc$libresoc.v:99427$4014 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:97860.5-97860.29" + attribute \src "libresoc.v:99428.5-99428.29" switch \initial - attribute \src "libresoc.v:97860.9-97860.17" + attribute \src "libresoc.v:99428.9-99428.17" case 1'1 case end @@ -152945,14 +155071,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:97881.3-97902.6" - process $proc$libresoc.v:97881$3982 + attribute \src "libresoc.v:99449.3-99470.6" + process $proc$libresoc.v:99449$4015 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:97882.5-97882.29" + attribute \src "libresoc.v:99450.5-99450.29" switch \initial - attribute \src "libresoc.v:97882.9-97882.17" + attribute \src "libresoc.v:99450.9-99450.17" case 1'1 case end @@ -152984,14 +155110,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:97903.3-97924.6" - process $proc$libresoc.v:97903$3983 + attribute \src "libresoc.v:99471.3-99492.6" + process $proc$libresoc.v:99471$4016 assign { } { } assign { } { } assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:97904.5-97904.29" + attribute \src "libresoc.v:99472.5-99472.29" switch \initial - attribute \src "libresoc.v:97904.9-97904.17" + attribute \src "libresoc.v:99472.9-99472.17" case 1'1 case end @@ -153023,14 +155149,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - attribute \src "libresoc.v:97925.3-97946.6" - process $proc$libresoc.v:97925$3984 + attribute \src "libresoc.v:99493.3-99514.6" + process $proc$libresoc.v:99493$4017 assign { } { } assign { } { } assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:97926.5-97926.29" + attribute \src "libresoc.v:99494.5-99494.29" switch \initial - attribute \src "libresoc.v:97926.9-97926.17" + attribute \src "libresoc.v:99494.9-99494.17" case 1'1 case end @@ -153062,14 +155188,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:97947.3-97968.6" - process $proc$libresoc.v:97947$3985 + attribute \src "libresoc.v:99515.3-99536.6" + process $proc$libresoc.v:99515$4018 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:97948.5-97948.29" + attribute \src "libresoc.v:99516.5-99516.29" switch \initial - attribute \src "libresoc.v:97948.9-97948.17" + attribute \src "libresoc.v:99516.9-99516.17" case 1'1 case end @@ -153101,14 +155227,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "libresoc.v:97969.3-97990.6" - process $proc$libresoc.v:97969$3986 + attribute \src "libresoc.v:99537.3-99558.6" + process $proc$libresoc.v:99537$4019 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:97970.5-97970.29" + attribute \src "libresoc.v:99538.5-99538.29" switch \initial - attribute \src "libresoc.v:97970.9-97970.17" + attribute \src "libresoc.v:99538.9-99538.17" case 1'1 case end @@ -153140,14 +155266,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:97991.3-98012.6" - process $proc$libresoc.v:97991$3987 + attribute \src "libresoc.v:99559.3-99580.6" + process $proc$libresoc.v:99559$4020 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:97992.5-97992.29" + attribute \src "libresoc.v:99560.5-99560.29" switch \initial - attribute \src "libresoc.v:97992.9-97992.17" + attribute \src "libresoc.v:99560.9-99560.17" case 1'1 case end @@ -153179,14 +155305,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "libresoc.v:98013.3-98034.6" - process $proc$libresoc.v:98013$3988 + attribute \src "libresoc.v:99581.3-99602.6" + process $proc$libresoc.v:99581$4021 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:98014.5-98014.29" + attribute \src "libresoc.v:99582.5-99582.29" switch \initial - attribute \src "libresoc.v:98014.9-98014.17" + attribute \src "libresoc.v:99582.9-99582.17" case 1'1 case end @@ -153218,14 +155344,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] end - attribute \src "libresoc.v:98035.3-98056.6" - process $proc$libresoc.v:98035$3989 + attribute \src "libresoc.v:99603.3-99624.6" + process $proc$libresoc.v:99603$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:98036.5-98036.29" + attribute \src "libresoc.v:99604.5-99604.29" switch \initial - attribute \src "libresoc.v:98036.9-98036.17" + attribute \src "libresoc.v:99604.9-99604.17" case 1'1 case end @@ -153257,14 +155383,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] end - attribute \src "libresoc.v:98057.3-98078.6" - process $proc$libresoc.v:98057$3990 + attribute \src "libresoc.v:99625.3-99646.6" + process $proc$libresoc.v:99625$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:98058.5-98058.29" + attribute \src "libresoc.v:99626.5-99626.29" switch \initial - attribute \src "libresoc.v:98058.9-98058.17" + attribute \src "libresoc.v:99626.9-99626.17" case 1'1 case end @@ -153296,14 +155422,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "libresoc.v:98079.3-98100.6" - process $proc$libresoc.v:98079$3991 + attribute \src "libresoc.v:99647.3-99668.6" + process $proc$libresoc.v:99647$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:98080.5-98080.29" + attribute \src "libresoc.v:99648.5-99648.29" switch \initial - attribute \src "libresoc.v:98080.9-98080.17" + attribute \src "libresoc.v:99648.9-99648.17" case 1'1 case end @@ -153335,14 +155461,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "libresoc.v:98101.3-98122.6" - process $proc$libresoc.v:98101$3992 + attribute \src "libresoc.v:99669.3-99690.6" + process $proc$libresoc.v:99669$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:98102.5-98102.29" + attribute \src "libresoc.v:99670.5-99670.29" switch \initial - attribute \src "libresoc.v:98102.9-98102.17" + attribute \src "libresoc.v:99670.9-99670.17" case 1'1 case end @@ -153374,14 +155500,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "libresoc.v:98123.3-98144.6" - process $proc$libresoc.v:98123$3993 + attribute \src "libresoc.v:99691.3-99712.6" + process $proc$libresoc.v:99691$4026 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:98124.5-98124.29" + assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] + attribute \src "libresoc.v:99692.5-99692.29" switch \initial - attribute \src "libresoc.v:98124.9-98124.17" + attribute \src "libresoc.v:99692.9-99692.17" case 1'1 case end @@ -153390,165 +155516,165 @@ module \dec31_dec_sub18 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98150.1-99095.10" +attribute \src "libresoc.v:99718.1-100666.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 - attribute \src "libresoc.v:98980.3-98998.6" + attribute \src "libresoc.v:100551.3-100569.6" wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:98999.3-99017.6" + attribute \src "libresoc.v:100570.3-100588.6" wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:98752.3-98770.6" + attribute \src "libresoc.v:100323.3-100341.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:98828.3-98846.6" + attribute \src "libresoc.v:100399.3-100417.6" wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:98505.3-98523.6" + attribute \src "libresoc.v:100076.3-100094.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:98524.3-98542.6" + attribute \src "libresoc.v:100095.3-100113.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:98733.3-98751.6" + attribute \src "libresoc.v:100304.3-100322.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:98809.3-98827.6" + attribute \src "libresoc.v:100380.3-100398.6" wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:98904.3-98922.6" + attribute \src "libresoc.v:100475.3-100493.6" wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:98486.3-98504.6" - wire width 13 $0\dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:99018.3-99036.6" + attribute \src "libresoc.v:100057.3-100075.6" + wire width 14 $0\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:100589.3-100607.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:99037.3-99055.6" + attribute \src "libresoc.v:100608.3-100626.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:99056.3-99074.6" + attribute \src "libresoc.v:100627.3-100645.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:98695.3-98713.6" + attribute \src "libresoc.v:100266.3-100284.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:98771.3-98789.6" + attribute \src "libresoc.v:100342.3-100360.6" wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:98790.3-98808.6" + attribute \src "libresoc.v:100361.3-100379.6" wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:98885.3-98903.6" + attribute \src "libresoc.v:100456.3-100474.6" wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:98657.3-98675.6" + attribute \src "libresoc.v:100228.3-100246.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:98942.3-98960.6" + attribute \src "libresoc.v:100513.3-100531.6" wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:99075.3-99093.6" - wire width 2 $0\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:98714.3-98732.6" + attribute \src "libresoc.v:100646.3-100664.6" + wire width 3 $0\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:100285.3-100303.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:98866.3-98884.6" + attribute \src "libresoc.v:100437.3-100455.6" wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:98961.3-98979.6" + attribute \src "libresoc.v:100532.3-100550.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:98923.3-98941.6" + attribute \src "libresoc.v:100494.3-100512.6" wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:98847.3-98865.6" + attribute \src "libresoc.v:100418.3-100436.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:98619.3-98637.6" + attribute \src "libresoc.v:100190.3-100208.6" wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:98638.3-98656.6" + attribute \src "libresoc.v:100209.3-100227.6" wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:98543.3-98561.6" + attribute \src "libresoc.v:100114.3-100132.6" wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:98562.3-98580.6" + attribute \src "libresoc.v:100133.3-100151.6" wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:98581.3-98599.6" + attribute \src "libresoc.v:100152.3-100170.6" wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:98600.3-98618.6" + attribute \src "libresoc.v:100171.3-100189.6" wire width 3 $0\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:98676.3-98694.6" + attribute \src "libresoc.v:100247.3-100265.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:98151.7-98151.20" + attribute \src "libresoc.v:99719.7-99719.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98980.3-98998.6" + attribute \src "libresoc.v:100551.3-100569.6" wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:98999.3-99017.6" + attribute \src "libresoc.v:100570.3-100588.6" wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:98752.3-98770.6" + attribute \src "libresoc.v:100323.3-100341.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:98828.3-98846.6" + attribute \src "libresoc.v:100399.3-100417.6" wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:98505.3-98523.6" + attribute \src "libresoc.v:100076.3-100094.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:98524.3-98542.6" + attribute \src "libresoc.v:100095.3-100113.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:98733.3-98751.6" + attribute \src "libresoc.v:100304.3-100322.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:98809.3-98827.6" + attribute \src "libresoc.v:100380.3-100398.6" wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:98904.3-98922.6" + attribute \src "libresoc.v:100475.3-100493.6" wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:98486.3-98504.6" - wire width 13 $1\dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:99018.3-99036.6" + attribute \src "libresoc.v:100057.3-100075.6" + wire width 14 $1\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:100589.3-100607.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:99037.3-99055.6" + attribute \src "libresoc.v:100608.3-100626.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:99056.3-99074.6" + attribute \src "libresoc.v:100627.3-100645.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:98695.3-98713.6" + attribute \src "libresoc.v:100266.3-100284.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:98771.3-98789.6" + attribute \src "libresoc.v:100342.3-100360.6" wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:98790.3-98808.6" + attribute \src "libresoc.v:100361.3-100379.6" wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:98885.3-98903.6" + attribute \src "libresoc.v:100456.3-100474.6" wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:98657.3-98675.6" + attribute \src "libresoc.v:100228.3-100246.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:98942.3-98960.6" + attribute \src "libresoc.v:100513.3-100531.6" wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:99075.3-99093.6" - wire width 2 $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:98714.3-98732.6" + attribute \src "libresoc.v:100646.3-100664.6" + wire width 3 $1\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:100285.3-100303.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:98866.3-98884.6" + attribute \src "libresoc.v:100437.3-100455.6" wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:98961.3-98979.6" + attribute \src "libresoc.v:100532.3-100550.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:98923.3-98941.6" + attribute \src "libresoc.v:100494.3-100512.6" wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:98847.3-98865.6" + attribute \src "libresoc.v:100418.3-100436.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:98619.3-98637.6" + attribute \src "libresoc.v:100190.3-100208.6" wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:98638.3-98656.6" + attribute \src "libresoc.v:100209.3-100227.6" wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:98543.3-98561.6" + attribute \src "libresoc.v:100114.3-100132.6" wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:98562.3-98580.6" + attribute \src "libresoc.v:100133.3-100151.6" wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:98581.3-98599.6" + attribute \src "libresoc.v:100152.3-100170.6" wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:98600.3-98618.6" + attribute \src "libresoc.v:100171.3-100189.6" wire width 3 $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:98676.3-98694.6" + attribute \src "libresoc.v:100247.3-100265.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -153628,21 +155754,22 @@ module \dec31_dec_sub19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub19_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -153748,6 +155875,7 @@ module \dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -153767,12 +155895,13 @@ module \dec31_dec_sub19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub19_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub19_out_sel + wire width 3 output 10 \dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -153848,28 +155977,20 @@ module \dec31_dec_sub19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub19_upd - attribute \src "libresoc.v:98151.7-98151.15" + attribute \src "libresoc.v:99719.7-99719.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:98151.7-98151.20" - process $proc$libresoc.v:98151$4027 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:98486.3-98504.6" - process $proc$libresoc.v:98486$3995 + attribute \src "libresoc.v:100057.3-100075.6" + process $proc$libresoc.v:100057$4028 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_function_unit[12:0] $1\dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:98487.5-98487.29" + assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] + attribute \src "libresoc.v:100058.5-100058.29" switch \initial - attribute \src "libresoc.v:98487.9-98487.17" + attribute \src "libresoc.v:100058.9-100058.17" case 1'1 case end @@ -153878,33 +155999,33 @@ module \dec31_dec_sub19 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000001000000 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000010000000 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00010000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00010000000000 case - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[12:0] + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:98505.3-98523.6" - process $proc$libresoc.v:98505$3996 + attribute \src "libresoc.v:100076.3-100094.6" + process $proc$libresoc.v:100076$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:98506.5-98506.29" + attribute \src "libresoc.v:100077.5-100077.29" switch \initial - attribute \src "libresoc.v:98506.9-98506.17" + attribute \src "libresoc.v:100077.9-100077.17" case 1'1 case end @@ -153932,14 +156053,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:98524.3-98542.6" - process $proc$libresoc.v:98524$3997 + attribute \src "libresoc.v:100095.3-100113.6" + process $proc$libresoc.v:100095$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:98525.5-98525.29" + attribute \src "libresoc.v:100096.5-100096.29" switch \initial - attribute \src "libresoc.v:98525.9-98525.17" + attribute \src "libresoc.v:100096.9-100096.17" case 1'1 case end @@ -153967,14 +156088,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:98543.3-98561.6" - process $proc$libresoc.v:98543$3998 + attribute \src "libresoc.v:100114.3-100132.6" + process $proc$libresoc.v:100114$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:98544.5-98544.29" + attribute \src "libresoc.v:100115.5-100115.29" switch \initial - attribute \src "libresoc.v:98544.9-98544.17" + attribute \src "libresoc.v:100115.9-100115.17" case 1'1 case end @@ -154002,14 +156123,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] end - attribute \src "libresoc.v:98562.3-98580.6" - process $proc$libresoc.v:98562$3999 + attribute \src "libresoc.v:100133.3-100151.6" + process $proc$libresoc.v:100133$4032 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:98563.5-98563.29" + attribute \src "libresoc.v:100134.5-100134.29" switch \initial - attribute \src "libresoc.v:98563.9-98563.17" + attribute \src "libresoc.v:100134.9-100134.17" case 1'1 case end @@ -154037,14 +156158,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] end - attribute \src "libresoc.v:98581.3-98599.6" - process $proc$libresoc.v:98581$4000 + attribute \src "libresoc.v:100152.3-100170.6" + process $proc$libresoc.v:100152$4033 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:98582.5-98582.29" + attribute \src "libresoc.v:100153.5-100153.29" switch \initial - attribute \src "libresoc.v:98582.9-98582.17" + attribute \src "libresoc.v:100153.9-100153.17" case 1'1 case end @@ -154072,14 +156193,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] end - attribute \src "libresoc.v:98600.3-98618.6" - process $proc$libresoc.v:98600$4001 + attribute \src "libresoc.v:100171.3-100189.6" + process $proc$libresoc.v:100171$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:98601.5-98601.29" + attribute \src "libresoc.v:100172.5-100172.29" switch \initial - attribute \src "libresoc.v:98601.9-98601.17" + attribute \src "libresoc.v:100172.9-100172.17" case 1'1 case end @@ -154107,14 +156228,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] end - attribute \src "libresoc.v:98619.3-98637.6" - process $proc$libresoc.v:98619$4002 + attribute \src "libresoc.v:100190.3-100208.6" + process $proc$libresoc.v:100190$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:98620.5-98620.29" + attribute \src "libresoc.v:100191.5-100191.29" switch \initial - attribute \src "libresoc.v:98620.9-98620.17" + attribute \src "libresoc.v:100191.9-100191.17" case 1'1 case end @@ -154142,14 +156263,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] end - attribute \src "libresoc.v:98638.3-98656.6" - process $proc$libresoc.v:98638$4003 + attribute \src "libresoc.v:100209.3-100227.6" + process $proc$libresoc.v:100209$4036 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:98639.5-98639.29" + attribute \src "libresoc.v:100210.5-100210.29" switch \initial - attribute \src "libresoc.v:98639.9-98639.17" + attribute \src "libresoc.v:100210.9-100210.17" case 1'1 case end @@ -154177,14 +156298,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end - attribute \src "libresoc.v:98657.3-98675.6" - process $proc$libresoc.v:98657$4004 + attribute \src "libresoc.v:100228.3-100246.6" + process $proc$libresoc.v:100228$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:98658.5-98658.29" + attribute \src "libresoc.v:100229.5-100229.29" switch \initial - attribute \src "libresoc.v:98658.9-98658.17" + attribute \src "libresoc.v:100229.9-100229.17" case 1'1 case end @@ -154212,14 +156333,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "libresoc.v:98676.3-98694.6" - process $proc$libresoc.v:98676$4005 + attribute \src "libresoc.v:100247.3-100265.6" + process $proc$libresoc.v:100247$4038 assign { } { } assign { } { } assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:98677.5-98677.29" + attribute \src "libresoc.v:100248.5-100248.29" switch \initial - attribute \src "libresoc.v:98677.9-98677.17" + attribute \src "libresoc.v:100248.9-100248.17" case 1'1 case end @@ -154247,14 +156368,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "libresoc.v:98695.3-98713.6" - process $proc$libresoc.v:98695$4006 + attribute \src "libresoc.v:100266.3-100284.6" + process $proc$libresoc.v:100266$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:98696.5-98696.29" + attribute \src "libresoc.v:100267.5-100267.29" switch \initial - attribute \src "libresoc.v:98696.9-98696.17" + attribute \src "libresoc.v:100267.9-100267.17" case 1'1 case end @@ -154282,14 +156403,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:98714.3-98732.6" - process $proc$libresoc.v:98714$4007 + attribute \src "libresoc.v:100285.3-100303.6" + process $proc$libresoc.v:100285$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:98715.5-98715.29" + attribute \src "libresoc.v:100286.5-100286.29" switch \initial - attribute \src "libresoc.v:98715.9-98715.17" + attribute \src "libresoc.v:100286.9-100286.17" case 1'1 case end @@ -154317,14 +156438,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:98733.3-98751.6" - process $proc$libresoc.v:98733$4008 + attribute \src "libresoc.v:100304.3-100322.6" + process $proc$libresoc.v:100304$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:98734.5-98734.29" + attribute \src "libresoc.v:100305.5-100305.29" switch \initial - attribute \src "libresoc.v:98734.9-98734.17" + attribute \src "libresoc.v:100305.9-100305.17" case 1'1 case end @@ -154352,14 +156473,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "libresoc.v:98752.3-98770.6" - process $proc$libresoc.v:98752$4009 + attribute \src "libresoc.v:100323.3-100341.6" + process $proc$libresoc.v:100323$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:98753.5-98753.29" + attribute \src "libresoc.v:100324.5-100324.29" switch \initial - attribute \src "libresoc.v:98753.9-98753.17" + attribute \src "libresoc.v:100324.9-100324.17" case 1'1 case end @@ -154387,14 +156508,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:98771.3-98789.6" - process $proc$libresoc.v:98771$4010 + attribute \src "libresoc.v:100342.3-100360.6" + process $proc$libresoc.v:100342$4043 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:98772.5-98772.29" + attribute \src "libresoc.v:100343.5-100343.29" switch \initial - attribute \src "libresoc.v:98772.9-98772.17" + attribute \src "libresoc.v:100343.9-100343.17" case 1'1 case end @@ -154422,14 +156543,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "libresoc.v:98790.3-98808.6" - process $proc$libresoc.v:98790$4011 + attribute \src "libresoc.v:100361.3-100379.6" + process $proc$libresoc.v:100361$4044 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:98791.5-98791.29" + attribute \src "libresoc.v:100362.5-100362.29" switch \initial - attribute \src "libresoc.v:98791.9-98791.17" + attribute \src "libresoc.v:100362.9-100362.17" case 1'1 case end @@ -154457,14 +156578,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "libresoc.v:98809.3-98827.6" - process $proc$libresoc.v:98809$4012 + attribute \src "libresoc.v:100380.3-100398.6" + process $proc$libresoc.v:100380$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:98810.5-98810.29" + attribute \src "libresoc.v:100381.5-100381.29" switch \initial - attribute \src "libresoc.v:98810.9-98810.17" + attribute \src "libresoc.v:100381.9-100381.17" case 1'1 case end @@ -154492,14 +156613,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:98828.3-98846.6" - process $proc$libresoc.v:98828$4013 + attribute \src "libresoc.v:100399.3-100417.6" + process $proc$libresoc.v:100399$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:98829.5-98829.29" + attribute \src "libresoc.v:100400.5-100400.29" switch \initial - attribute \src "libresoc.v:98829.9-98829.17" + attribute \src "libresoc.v:100400.9-100400.17" case 1'1 case end @@ -154527,14 +156648,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "libresoc.v:98847.3-98865.6" - process $proc$libresoc.v:98847$4014 + attribute \src "libresoc.v:100418.3-100436.6" + process $proc$libresoc.v:100418$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:98848.5-98848.29" + attribute \src "libresoc.v:100419.5-100419.29" switch \initial - attribute \src "libresoc.v:98848.9-98848.17" + attribute \src "libresoc.v:100419.9-100419.17" case 1'1 case end @@ -154562,14 +156683,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "libresoc.v:98866.3-98884.6" - process $proc$libresoc.v:98866$4015 + attribute \src "libresoc.v:100437.3-100455.6" + process $proc$libresoc.v:100437$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:98867.5-98867.29" + attribute \src "libresoc.v:100438.5-100438.29" switch \initial - attribute \src "libresoc.v:98867.9-98867.17" + attribute \src "libresoc.v:100438.9-100438.17" case 1'1 case end @@ -154597,14 +156718,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:98885.3-98903.6" - process $proc$libresoc.v:98885$4016 + attribute \src "libresoc.v:100456.3-100474.6" + process $proc$libresoc.v:100456$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:98886.5-98886.29" + attribute \src "libresoc.v:100457.5-100457.29" switch \initial - attribute \src "libresoc.v:98886.9-98886.17" + attribute \src "libresoc.v:100457.9-100457.17" case 1'1 case end @@ -154632,14 +156753,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "libresoc.v:98904.3-98922.6" - process $proc$libresoc.v:98904$4017 + attribute \src "libresoc.v:100475.3-100493.6" + process $proc$libresoc.v:100475$4050 assign { } { } assign { } { } assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:98905.5-98905.29" + attribute \src "libresoc.v:100476.5-100476.29" switch \initial - attribute \src "libresoc.v:98905.9-98905.17" + attribute \src "libresoc.v:100476.9-100476.17" case 1'1 case end @@ -154667,14 +156788,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "libresoc.v:98923.3-98941.6" - process $proc$libresoc.v:98923$4018 + attribute \src "libresoc.v:100494.3-100512.6" + process $proc$libresoc.v:100494$4051 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:98924.5-98924.29" + attribute \src "libresoc.v:100495.5-100495.29" switch \initial - attribute \src "libresoc.v:98924.9-98924.17" + attribute \src "libresoc.v:100495.9-100495.17" case 1'1 case end @@ -154702,14 +156823,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:98942.3-98960.6" - process $proc$libresoc.v:98942$4019 + attribute \src "libresoc.v:100513.3-100531.6" + process $proc$libresoc.v:100513$4052 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:98943.5-98943.29" + attribute \src "libresoc.v:100514.5-100514.29" switch \initial - attribute \src "libresoc.v:98943.9-98943.17" + attribute \src "libresoc.v:100514.9-100514.17" case 1'1 case end @@ -154737,14 +156858,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "libresoc.v:98961.3-98979.6" - process $proc$libresoc.v:98961$4020 + attribute \src "libresoc.v:100532.3-100550.6" + process $proc$libresoc.v:100532$4053 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:98962.5-98962.29" + attribute \src "libresoc.v:100533.5-100533.29" switch \initial - attribute \src "libresoc.v:98962.9-98962.17" + attribute \src "libresoc.v:100533.9-100533.17" case 1'1 case end @@ -154772,14 +156893,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "libresoc.v:98980.3-98998.6" - process $proc$libresoc.v:98980$4021 + attribute \src "libresoc.v:100551.3-100569.6" + process $proc$libresoc.v:100551$4054 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:98981.5-98981.29" + attribute \src "libresoc.v:100552.5-100552.29" switch \initial - attribute \src "libresoc.v:98981.9-98981.17" + attribute \src "libresoc.v:100552.9-100552.17" case 1'1 case end @@ -154807,14 +156928,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end - attribute \src "libresoc.v:98999.3-99017.6" - process $proc$libresoc.v:98999$4022 + attribute \src "libresoc.v:100570.3-100588.6" + process $proc$libresoc.v:100570$4055 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:99000.5-99000.29" + attribute \src "libresoc.v:100571.5-100571.29" switch \initial - attribute \src "libresoc.v:99000.9-99000.17" + attribute \src "libresoc.v:100571.9-100571.17" case 1'1 case end @@ -154842,14 +156963,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] end - attribute \src "libresoc.v:99018.3-99036.6" - process $proc$libresoc.v:99018$4023 + attribute \src "libresoc.v:100589.3-100607.6" + process $proc$libresoc.v:100589$4056 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:99019.5-99019.29" + attribute \src "libresoc.v:100590.5-100590.29" switch \initial - attribute \src "libresoc.v:99019.9-99019.17" + attribute \src "libresoc.v:100590.9-100590.17" case 1'1 case end @@ -154877,14 +156998,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "libresoc.v:99037.3-99055.6" - process $proc$libresoc.v:99037$4024 + attribute \src "libresoc.v:100608.3-100626.6" + process $proc$libresoc.v:100608$4057 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:99038.5-99038.29" + attribute \src "libresoc.v:100609.5-100609.29" switch \initial - attribute \src "libresoc.v:99038.9-99038.17" + attribute \src "libresoc.v:100609.9-100609.17" case 1'1 case end @@ -154912,14 +157033,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:99056.3-99074.6" - process $proc$libresoc.v:99056$4025 + attribute \src "libresoc.v:100627.3-100645.6" + process $proc$libresoc.v:100627$4058 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:99057.5-99057.29" + attribute \src "libresoc.v:100628.5-100628.29" switch \initial - attribute \src "libresoc.v:99057.9-99057.17" + attribute \src "libresoc.v:100628.9-100628.17" case 1'1 case end @@ -154947,14 +157068,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "libresoc.v:99075.3-99093.6" - process $proc$libresoc.v:99075$4026 + attribute \src "libresoc.v:100646.3-100664.6" + process $proc$libresoc.v:100646$4059 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:99076.5-99076.29" + assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] + attribute \src "libresoc.v:100647.5-100647.29" switch \initial - attribute \src "libresoc.v:99076.9-99076.17" + attribute \src "libresoc.v:100647.9-100647.17" case 1'1 case end @@ -154963,161 +157084,169 @@ module \dec31_dec_sub19 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'011 case - assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub19_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[2:0] + end + attribute \src "libresoc.v:99719.7-99719.20" + process $proc$libresoc.v:99719$4060 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99099.1-100236.10" +attribute \src "libresoc.v:100670.1-101810.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 - attribute \src "libresoc.v:100085.3-100109.6" + attribute \src "libresoc.v:101659.3-101683.6" wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:100110.3-100134.6" + attribute \src "libresoc.v:101684.3-101708.6" wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:99785.3-99809.6" + attribute \src "libresoc.v:101359.3-101383.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:99885.3-99909.6" + attribute \src "libresoc.v:101459.3-101483.6" wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:99460.3-99484.6" + attribute \src "libresoc.v:101034.3-101058.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:99485.3-99509.6" + attribute \src "libresoc.v:101059.3-101083.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:99760.3-99784.6" + attribute \src "libresoc.v:101334.3-101358.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:99860.3-99884.6" + attribute \src "libresoc.v:101434.3-101458.6" wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:99985.3-100009.6" + attribute \src "libresoc.v:101559.3-101583.6" wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:99435.3-99459.6" - wire width 13 $0\dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:100135.3-100159.6" + attribute \src "libresoc.v:101009.3-101033.6" + wire width 14 $0\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:101709.3-101733.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:100160.3-100184.6" + attribute \src "libresoc.v:101734.3-101758.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:100185.3-100209.6" + attribute \src "libresoc.v:101759.3-101783.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:99710.3-99734.6" + attribute \src "libresoc.v:101284.3-101308.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:99810.3-99834.6" + attribute \src "libresoc.v:101384.3-101408.6" wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:99835.3-99859.6" + attribute \src "libresoc.v:101409.3-101433.6" wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:99960.3-99984.6" + attribute \src "libresoc.v:101534.3-101558.6" wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:99660.3-99684.6" + attribute \src "libresoc.v:101234.3-101258.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:100035.3-100059.6" + attribute \src "libresoc.v:101609.3-101633.6" wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:100210.3-100234.6" - wire width 2 $0\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:99735.3-99759.6" + attribute \src "libresoc.v:101784.3-101808.6" + wire width 3 $0\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:101309.3-101333.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:99935.3-99959.6" + attribute \src "libresoc.v:101509.3-101533.6" wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:100060.3-100084.6" + attribute \src "libresoc.v:101634.3-101658.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:100010.3-100034.6" + attribute \src "libresoc.v:101584.3-101608.6" wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:99910.3-99934.6" + attribute \src "libresoc.v:101484.3-101508.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:99610.3-99634.6" + attribute \src "libresoc.v:101184.3-101208.6" wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:99635.3-99659.6" + attribute \src "libresoc.v:101209.3-101233.6" wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:99510.3-99534.6" + attribute \src "libresoc.v:101084.3-101108.6" wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:99535.3-99559.6" + attribute \src "libresoc.v:101109.3-101133.6" wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:99560.3-99584.6" + attribute \src "libresoc.v:101134.3-101158.6" wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:99585.3-99609.6" + attribute \src "libresoc.v:101159.3-101183.6" wire width 3 $0\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:99685.3-99709.6" + attribute \src "libresoc.v:101259.3-101283.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:99100.7-99100.20" + attribute \src "libresoc.v:100671.7-100671.20" wire $0\initial[0:0] - attribute \src "libresoc.v:100085.3-100109.6" + attribute \src "libresoc.v:101659.3-101683.6" wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:100110.3-100134.6" + attribute \src "libresoc.v:101684.3-101708.6" wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:99785.3-99809.6" + attribute \src "libresoc.v:101359.3-101383.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:99885.3-99909.6" + attribute \src "libresoc.v:101459.3-101483.6" wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:99460.3-99484.6" + attribute \src "libresoc.v:101034.3-101058.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:99485.3-99509.6" + attribute \src "libresoc.v:101059.3-101083.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:99760.3-99784.6" + attribute \src "libresoc.v:101334.3-101358.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:99860.3-99884.6" + attribute \src "libresoc.v:101434.3-101458.6" wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:99985.3-100009.6" + attribute \src "libresoc.v:101559.3-101583.6" wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:99435.3-99459.6" - wire width 13 $1\dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:100135.3-100159.6" + attribute \src "libresoc.v:101009.3-101033.6" + wire width 14 $1\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:101709.3-101733.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:100160.3-100184.6" + attribute \src "libresoc.v:101734.3-101758.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:100185.3-100209.6" + attribute \src "libresoc.v:101759.3-101783.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:99710.3-99734.6" + attribute \src "libresoc.v:101284.3-101308.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:99810.3-99834.6" + attribute \src "libresoc.v:101384.3-101408.6" wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:99835.3-99859.6" + attribute \src "libresoc.v:101409.3-101433.6" wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:99960.3-99984.6" + attribute \src "libresoc.v:101534.3-101558.6" wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:99660.3-99684.6" + attribute \src "libresoc.v:101234.3-101258.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:100035.3-100059.6" + attribute \src "libresoc.v:101609.3-101633.6" wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:100210.3-100234.6" - wire width 2 $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:99735.3-99759.6" + attribute \src "libresoc.v:101784.3-101808.6" + wire width 3 $1\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:101309.3-101333.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:99935.3-99959.6" + attribute \src "libresoc.v:101509.3-101533.6" wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:100060.3-100084.6" + attribute \src "libresoc.v:101634.3-101658.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:100010.3-100034.6" + attribute \src "libresoc.v:101584.3-101608.6" wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:99910.3-99934.6" + attribute \src "libresoc.v:101484.3-101508.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:99610.3-99634.6" + attribute \src "libresoc.v:101184.3-101208.6" wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:99635.3-99659.6" + attribute \src "libresoc.v:101209.3-101233.6" wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:99510.3-99534.6" + attribute \src "libresoc.v:101084.3-101108.6" wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:99535.3-99559.6" + attribute \src "libresoc.v:101109.3-101133.6" wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:99560.3-99584.6" + attribute \src "libresoc.v:101134.3-101158.6" wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:99585.3-99609.6" + attribute \src "libresoc.v:101159.3-101183.6" wire width 3 $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:99685.3-99709.6" + attribute \src "libresoc.v:101259.3-101283.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -155197,21 +157326,22 @@ module \dec31_dec_sub20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub20_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub20_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -155317,6 +157447,7 @@ module \dec31_dec_sub20 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub20_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -155336,12 +157467,13 @@ module \dec31_dec_sub20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub20_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub20_out_sel + wire width 3 output 10 \dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -155417,415 +157549,28 @@ module \dec31_dec_sub20 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub20_upd - attribute \src "libresoc.v:99100.7-99100.15" + attribute \src "libresoc.v:100671.7-100671.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:100010.3-100034.6" - process $proc$libresoc.v:100010$4051 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:100011.5-100011.29" - switch \initial - attribute \src "libresoc.v:100011.9-100011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] - end - attribute \src "libresoc.v:100035.3-100059.6" - process $proc$libresoc.v:100035$4052 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:100036.5-100036.29" - switch \initial - attribute \src "libresoc.v:100036.9-100036.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] - end - attribute \src "libresoc.v:100060.3-100084.6" - process $proc$libresoc.v:100060$4053 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:100061.5-100061.29" - switch \initial - attribute \src "libresoc.v:100061.9-100061.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] - end - attribute \src "libresoc.v:100085.3-100109.6" - process $proc$libresoc.v:100085$4054 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:100086.5-100086.29" - switch \initial - attribute \src "libresoc.v:100086.9-100086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 - case - assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] - end - attribute \src "libresoc.v:100110.3-100134.6" - process $proc$libresoc.v:100110$4055 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:100111.5-100111.29" - switch \initial - attribute \src "libresoc.v:100111.9-100111.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 - case - assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] - end - attribute \src "libresoc.v:100135.3-100159.6" - process $proc$libresoc.v:100135$4056 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:100136.5-100136.29" - switch \initial - attribute \src "libresoc.v:100136.9-100136.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] - end - attribute \src "libresoc.v:100160.3-100184.6" - process $proc$libresoc.v:100160$4057 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:100161.5-100161.29" - switch \initial - attribute \src "libresoc.v:100161.9-100161.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] - end - attribute \src "libresoc.v:100185.3-100209.6" - process $proc$libresoc.v:100185$4058 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:100186.5-100186.29" - switch \initial - attribute \src "libresoc.v:100186.9-100186.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] - end - attribute \src "libresoc.v:100210.3-100234.6" - process $proc$libresoc.v:100210$4059 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:100211.5-100211.29" - switch \initial - attribute \src "libresoc.v:100211.9-100211.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] - end - attribute \src "libresoc.v:99100.7-99100.20" - process $proc$libresoc.v:99100$4060 + attribute \src "libresoc.v:100671.7-100671.20" + process $proc$libresoc.v:100671$4093 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:99435.3-99459.6" - process $proc$libresoc.v:99435$4028 + attribute \src "libresoc.v:101009.3-101033.6" + process $proc$libresoc.v:101009$4061 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_function_unit[12:0] $1\dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:99436.5-99436.29" + assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] + attribute \src "libresoc.v:101010.5-101010.29" switch \initial - attribute \src "libresoc.v:99436.9-99436.17" + attribute \src "libresoc.v:101010.9-101010.17" case 1'1 case end @@ -155834,41 +157579,41 @@ module \dec31_dec_sub20 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 case - assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[12:0] + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:99460.3-99484.6" - process $proc$libresoc.v:99460$4029 + attribute \src "libresoc.v:101034.3-101058.6" + process $proc$libresoc.v:101034$4062 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:99461.5-99461.29" + attribute \src "libresoc.v:101035.5-101035.29" switch \initial - attribute \src "libresoc.v:99461.9-99461.17" + attribute \src "libresoc.v:101035.9-101035.17" case 1'1 case end @@ -155904,14 +157649,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:99485.3-99509.6" - process $proc$libresoc.v:99485$4030 + attribute \src "libresoc.v:101059.3-101083.6" + process $proc$libresoc.v:101059$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:99486.5-99486.29" + attribute \src "libresoc.v:101060.5-101060.29" switch \initial - attribute \src "libresoc.v:99486.9-99486.17" + attribute \src "libresoc.v:101060.9-101060.17" case 1'1 case end @@ -155947,14 +157692,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:99510.3-99534.6" - process $proc$libresoc.v:99510$4031 + attribute \src "libresoc.v:101084.3-101108.6" + process $proc$libresoc.v:101084$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:99511.5-99511.29" + attribute \src "libresoc.v:101085.5-101085.29" switch \initial - attribute \src "libresoc.v:99511.9-99511.17" + attribute \src "libresoc.v:101085.9-101085.17" case 1'1 case end @@ -155990,14 +157735,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] end - attribute \src "libresoc.v:99535.3-99559.6" - process $proc$libresoc.v:99535$4032 + attribute \src "libresoc.v:101109.3-101133.6" + process $proc$libresoc.v:101109$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:99536.5-99536.29" + attribute \src "libresoc.v:101110.5-101110.29" switch \initial - attribute \src "libresoc.v:99536.9-99536.17" + attribute \src "libresoc.v:101110.9-101110.17" case 1'1 case end @@ -156033,14 +157778,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end - attribute \src "libresoc.v:99560.3-99584.6" - process $proc$libresoc.v:99560$4033 + attribute \src "libresoc.v:101134.3-101158.6" + process $proc$libresoc.v:101134$4066 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:99561.5-99561.29" + attribute \src "libresoc.v:101135.5-101135.29" switch \initial - attribute \src "libresoc.v:99561.9-99561.17" + attribute \src "libresoc.v:101135.9-101135.17" case 1'1 case end @@ -156076,14 +157821,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] end - attribute \src "libresoc.v:99585.3-99609.6" - process $proc$libresoc.v:99585$4034 + attribute \src "libresoc.v:101159.3-101183.6" + process $proc$libresoc.v:101159$4067 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:99586.5-99586.29" + attribute \src "libresoc.v:101160.5-101160.29" switch \initial - attribute \src "libresoc.v:99586.9-99586.17" + attribute \src "libresoc.v:101160.9-101160.17" case 1'1 case end @@ -156119,14 +157864,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end - attribute \src "libresoc.v:99610.3-99634.6" - process $proc$libresoc.v:99610$4035 + attribute \src "libresoc.v:101184.3-101208.6" + process $proc$libresoc.v:101184$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:99611.5-99611.29" + attribute \src "libresoc.v:101185.5-101185.29" switch \initial - attribute \src "libresoc.v:99611.9-99611.17" + attribute \src "libresoc.v:101185.9-101185.17" case 1'1 case end @@ -156162,14 +157907,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] end - attribute \src "libresoc.v:99635.3-99659.6" - process $proc$libresoc.v:99635$4036 + attribute \src "libresoc.v:101209.3-101233.6" + process $proc$libresoc.v:101209$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:99636.5-99636.29" + attribute \src "libresoc.v:101210.5-101210.29" switch \initial - attribute \src "libresoc.v:99636.9-99636.17" + attribute \src "libresoc.v:101210.9-101210.17" case 1'1 case end @@ -156205,14 +157950,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end - attribute \src "libresoc.v:99660.3-99684.6" - process $proc$libresoc.v:99660$4037 + attribute \src "libresoc.v:101234.3-101258.6" + process $proc$libresoc.v:101234$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:99661.5-99661.29" + attribute \src "libresoc.v:101235.5-101235.29" switch \initial - attribute \src "libresoc.v:99661.9-99661.17" + attribute \src "libresoc.v:101235.9-101235.17" case 1'1 case end @@ -156248,14 +157993,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:99685.3-99709.6" - process $proc$libresoc.v:99685$4038 + attribute \src "libresoc.v:101259.3-101283.6" + process $proc$libresoc.v:101259$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:99686.5-99686.29" + attribute \src "libresoc.v:101260.5-101260.29" switch \initial - attribute \src "libresoc.v:99686.9-99686.17" + attribute \src "libresoc.v:101260.9-101260.17" case 1'1 case end @@ -156291,14 +158036,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:99710.3-99734.6" - process $proc$libresoc.v:99710$4039 + attribute \src "libresoc.v:101284.3-101308.6" + process $proc$libresoc.v:101284$4072 assign { } { } assign { } { } assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:99711.5-99711.29" + attribute \src "libresoc.v:101285.5-101285.29" switch \initial - attribute \src "libresoc.v:99711.9-99711.17" + attribute \src "libresoc.v:101285.9-101285.17" case 1'1 case end @@ -156334,14 +158079,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:99735.3-99759.6" - process $proc$libresoc.v:99735$4040 + attribute \src "libresoc.v:101309.3-101333.6" + process $proc$libresoc.v:101309$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:99736.5-99736.29" + attribute \src "libresoc.v:101310.5-101310.29" switch \initial - attribute \src "libresoc.v:99736.9-99736.17" + attribute \src "libresoc.v:101310.9-101310.17" case 1'1 case end @@ -156377,14 +158122,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - attribute \src "libresoc.v:99760.3-99784.6" - process $proc$libresoc.v:99760$4041 + attribute \src "libresoc.v:101334.3-101358.6" + process $proc$libresoc.v:101334$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:99761.5-99761.29" + attribute \src "libresoc.v:101335.5-101335.29" switch \initial - attribute \src "libresoc.v:99761.9-99761.17" + attribute \src "libresoc.v:101335.9-101335.17" case 1'1 case end @@ -156420,14 +158165,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:99785.3-99809.6" - process $proc$libresoc.v:99785$4042 + attribute \src "libresoc.v:101359.3-101383.6" + process $proc$libresoc.v:101359$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:99786.5-99786.29" + attribute \src "libresoc.v:101360.5-101360.29" switch \initial - attribute \src "libresoc.v:99786.9-99786.17" + attribute \src "libresoc.v:101360.9-101360.17" case 1'1 case end @@ -156463,14 +158208,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "libresoc.v:99810.3-99834.6" - process $proc$libresoc.v:99810$4043 + attribute \src "libresoc.v:101384.3-101408.6" + process $proc$libresoc.v:101384$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:99811.5-99811.29" + attribute \src "libresoc.v:101385.5-101385.29" switch \initial - attribute \src "libresoc.v:99811.9-99811.17" + attribute \src "libresoc.v:101385.9-101385.17" case 1'1 case end @@ -156506,14 +158251,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:99835.3-99859.6" - process $proc$libresoc.v:99835$4044 + attribute \src "libresoc.v:101409.3-101433.6" + process $proc$libresoc.v:101409$4077 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:99836.5-99836.29" + attribute \src "libresoc.v:101410.5-101410.29" switch \initial - attribute \src "libresoc.v:99836.9-99836.17" + attribute \src "libresoc.v:101410.9-101410.17" case 1'1 case end @@ -156549,14 +158294,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "libresoc.v:99860.3-99884.6" - process $proc$libresoc.v:99860$4045 + attribute \src "libresoc.v:101434.3-101458.6" + process $proc$libresoc.v:101434$4078 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:99861.5-99861.29" + attribute \src "libresoc.v:101435.5-101435.29" switch \initial - attribute \src "libresoc.v:99861.9-99861.17" + attribute \src "libresoc.v:101435.9-101435.17" case 1'1 case end @@ -156592,14 +158337,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "libresoc.v:99885.3-99909.6" - process $proc$libresoc.v:99885$4046 + attribute \src "libresoc.v:101459.3-101483.6" + process $proc$libresoc.v:101459$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:99886.5-99886.29" + attribute \src "libresoc.v:101460.5-101460.29" switch \initial - attribute \src "libresoc.v:99886.9-99886.17" + attribute \src "libresoc.v:101460.9-101460.17" case 1'1 case end @@ -156635,14 +158380,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:99910.3-99934.6" - process $proc$libresoc.v:99910$4047 + attribute \src "libresoc.v:101484.3-101508.6" + process $proc$libresoc.v:101484$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:99911.5-99911.29" + attribute \src "libresoc.v:101485.5-101485.29" switch \initial - attribute \src "libresoc.v:99911.9-99911.17" + attribute \src "libresoc.v:101485.9-101485.17" case 1'1 case end @@ -156678,14 +158423,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:99935.3-99959.6" - process $proc$libresoc.v:99935$4048 + attribute \src "libresoc.v:101509.3-101533.6" + process $proc$libresoc.v:101509$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:99936.5-99936.29" + attribute \src "libresoc.v:101510.5-101510.29" switch \initial - attribute \src "libresoc.v:99936.9-99936.17" + attribute \src "libresoc.v:101510.9-101510.17" case 1'1 case end @@ -156721,14 +158466,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - attribute \src "libresoc.v:99960.3-99984.6" - process $proc$libresoc.v:99960$4049 + attribute \src "libresoc.v:101534.3-101558.6" + process $proc$libresoc.v:101534$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:99961.5-99961.29" + attribute \src "libresoc.v:101535.5-101535.29" switch \initial - attribute \src "libresoc.v:99961.9-99961.17" + attribute \src "libresoc.v:101535.9-101535.17" case 1'1 case end @@ -156764,14 +158509,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:99985.3-100009.6" - process $proc$libresoc.v:99985$4050 + attribute \src "libresoc.v:101559.3-101583.6" + process $proc$libresoc.v:101559$4083 assign { } { } assign { } { } assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:99986.5-99986.29" + attribute \src "libresoc.v:101560.5-101560.29" switch \initial - attribute \src "libresoc.v:99986.9-99986.17" + attribute \src "libresoc.v:101560.9-101560.17" case 1'1 case end @@ -156807,142 +158552,529 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end + attribute \src "libresoc.v:101584.3-101608.6" + process $proc$libresoc.v:101584$4084 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:101585.5-101585.29" + switch \initial + attribute \src "libresoc.v:101585.9-101585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:101609.3-101633.6" + process $proc$libresoc.v:101609$4085 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:101610.5-101610.29" + switch \initial + attribute \src "libresoc.v:101610.9-101610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "libresoc.v:101634.3-101658.6" + process $proc$libresoc.v:101634$4086 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:101635.5-101635.29" + switch \initial + attribute \src "libresoc.v:101635.9-101635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:101659.3-101683.6" + process $proc$libresoc.v:101659$4087 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:101660.5-101660.29" + switch \initial + attribute \src "libresoc.v:101660.9-101660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] + end + attribute \src "libresoc.v:101684.3-101708.6" + process $proc$libresoc.v:101684$4088 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:101685.5-101685.29" + switch \initial + attribute \src "libresoc.v:101685.9-101685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] + end + attribute \src "libresoc.v:101709.3-101733.6" + process $proc$libresoc.v:101709$4089 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:101710.5-101710.29" + switch \initial + attribute \src "libresoc.v:101710.9-101710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:101734.3-101758.6" + process $proc$libresoc.v:101734$4090 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:101735.5-101735.29" + switch \initial + attribute \src "libresoc.v:101735.9-101735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:101759.3-101783.6" + process $proc$libresoc.v:101759$4091 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:101760.5-101760.29" + switch \initial + attribute \src "libresoc.v:101760.9-101760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:101784.3-101808.6" + process $proc$libresoc.v:101784$4092 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] + attribute \src "libresoc.v:101785.5-101785.29" + switch \initial + attribute \src "libresoc.v:101785.9-101785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub20_out_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[2:0] + end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:100240.1-102127.10" +attribute \src "libresoc.v:101814.1-103704.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 - attribute \src "libresoc.v:101832.3-101880.6" + attribute \src "libresoc.v:103409.3-103457.6" wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:101881.3-101929.6" + attribute \src "libresoc.v:103458.3-103506.6" wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:101801.3-101831.6" + attribute \src "libresoc.v:103378.3-103408.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:101409.3-101457.6" + attribute \src "libresoc.v:102986.3-103034.6" wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:100625.3-100673.6" + attribute \src "libresoc.v:102202.3-102250.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:100674.3-100722.6" + attribute \src "libresoc.v:102251.3-102299.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:101213.3-101261.6" + attribute \src "libresoc.v:102790.3-102838.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:101360.3-101408.6" + attribute \src "libresoc.v:102937.3-102985.6" wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:101654.3-101702.6" + attribute \src "libresoc.v:103231.3-103279.6" wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:100576.3-100624.6" - wire width 13 $0\dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:101930.3-101978.6" + attribute \src "libresoc.v:102153.3-102201.6" + wire width 14 $0\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:103507.3-103555.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:101979.3-102027.6" + attribute \src "libresoc.v:103556.3-103604.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:102028.3-102076.6" + attribute \src "libresoc.v:103605.3-103653.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:101115.3-101163.6" + attribute \src "libresoc.v:102692.3-102740.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:101262.3-101310.6" + attribute \src "libresoc.v:102839.3-102887.6" wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:101311.3-101359.6" + attribute \src "libresoc.v:102888.3-102936.6" wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:101556.3-101604.6" + attribute \src "libresoc.v:103133.3-103181.6" wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:101017.3-101065.6" + attribute \src "libresoc.v:102594.3-102642.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:101703.3-101751.6" + attribute \src "libresoc.v:103280.3-103328.6" wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:102077.3-102125.6" - wire width 2 $0\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:101164.3-101212.6" + attribute \src "libresoc.v:103654.3-103702.6" + wire width 3 $0\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:102741.3-102789.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:101507.3-101555.6" + attribute \src "libresoc.v:103084.3-103132.6" wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:101752.3-101800.6" + attribute \src "libresoc.v:103329.3-103377.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:101605.3-101653.6" + attribute \src "libresoc.v:103182.3-103230.6" wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:101458.3-101506.6" + attribute \src "libresoc.v:103035.3-103083.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:100919.3-100967.6" + attribute \src "libresoc.v:102496.3-102544.6" wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:100968.3-101016.6" + attribute \src "libresoc.v:102545.3-102593.6" wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:100723.3-100771.6" + attribute \src "libresoc.v:102300.3-102348.6" wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:100772.3-100820.6" + attribute \src "libresoc.v:102349.3-102397.6" wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:100821.3-100869.6" + attribute \src "libresoc.v:102398.3-102446.6" wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:100870.3-100918.6" + attribute \src "libresoc.v:102447.3-102495.6" wire width 3 $0\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:101066.3-101114.6" + attribute \src "libresoc.v:102643.3-102691.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:100241.7-100241.20" + attribute \src "libresoc.v:101815.7-101815.20" wire $0\initial[0:0] - attribute \src "libresoc.v:101832.3-101880.6" + attribute \src "libresoc.v:103409.3-103457.6" wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:101881.3-101929.6" + attribute \src "libresoc.v:103458.3-103506.6" wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:101801.3-101831.6" + attribute \src "libresoc.v:103378.3-103408.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:101409.3-101457.6" + attribute \src "libresoc.v:102986.3-103034.6" wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:100625.3-100673.6" + attribute \src "libresoc.v:102202.3-102250.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:100674.3-100722.6" + attribute \src "libresoc.v:102251.3-102299.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:101213.3-101261.6" + attribute \src "libresoc.v:102790.3-102838.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:101360.3-101408.6" + attribute \src "libresoc.v:102937.3-102985.6" wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:101654.3-101702.6" + attribute \src "libresoc.v:103231.3-103279.6" wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:100576.3-100624.6" - wire width 13 $1\dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:101930.3-101978.6" + attribute \src "libresoc.v:102153.3-102201.6" + wire width 14 $1\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:103507.3-103555.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:101979.3-102027.6" + attribute \src "libresoc.v:103556.3-103604.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:102028.3-102076.6" + attribute \src "libresoc.v:103605.3-103653.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:101115.3-101163.6" + attribute \src "libresoc.v:102692.3-102740.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:101262.3-101310.6" + attribute \src "libresoc.v:102839.3-102887.6" wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:101311.3-101359.6" + attribute \src "libresoc.v:102888.3-102936.6" wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:101556.3-101604.6" + attribute \src "libresoc.v:103133.3-103181.6" wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:101017.3-101065.6" + attribute \src "libresoc.v:102594.3-102642.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:101703.3-101751.6" + attribute \src "libresoc.v:103280.3-103328.6" wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:102077.3-102125.6" - wire width 2 $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:101164.3-101212.6" + attribute \src "libresoc.v:103654.3-103702.6" + wire width 3 $1\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:102741.3-102789.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:101507.3-101555.6" + attribute \src "libresoc.v:103084.3-103132.6" wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:101752.3-101800.6" + attribute \src "libresoc.v:103329.3-103377.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:101605.3-101653.6" + attribute \src "libresoc.v:103182.3-103230.6" wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:101458.3-101506.6" + attribute \src "libresoc.v:103035.3-103083.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:100919.3-100967.6" + attribute \src "libresoc.v:102496.3-102544.6" wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:100968.3-101016.6" + attribute \src "libresoc.v:102545.3-102593.6" wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:100723.3-100771.6" + attribute \src "libresoc.v:102300.3-102348.6" wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:100772.3-100820.6" + attribute \src "libresoc.v:102349.3-102397.6" wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:100821.3-100869.6" + attribute \src "libresoc.v:102398.3-102446.6" wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:100870.3-100918.6" + attribute \src "libresoc.v:102447.3-102495.6" wire width 3 $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:101066.3-101114.6" + attribute \src "libresoc.v:102643.3-102691.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -157022,21 +159154,22 @@ module \dec31_dec_sub21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub21_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -157142,6 +159275,7 @@ module \dec31_dec_sub21 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub21_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -157161,12 +159295,13 @@ module \dec31_dec_sub21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub21_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub21_out_sel + wire width 3 output 10 \dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -157242,28 +159377,28 @@ module \dec31_dec_sub21 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub21_upd - attribute \src "libresoc.v:100241.7-100241.15" + attribute \src "libresoc.v:101815.7-101815.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:100241.7-100241.20" - process $proc$libresoc.v:100241$4093 + attribute \src "libresoc.v:101815.7-101815.20" + process $proc$libresoc.v:101815$4126 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:100576.3-100624.6" - process $proc$libresoc.v:100576$4061 + attribute \src "libresoc.v:102153.3-102201.6" + process $proc$libresoc.v:102153$4094 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_function_unit[12:0] $1\dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:100577.5-100577.29" + assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] + attribute \src "libresoc.v:102154.5-102154.29" switch \initial - attribute \src "libresoc.v:100577.9-100577.17" + attribute \src "libresoc.v:102154.9-102154.17" case 1'1 case end @@ -157272,73 +159407,73 @@ module \dec31_dec_sub21 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 case - assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[12:0] + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:100625.3-100673.6" - process $proc$libresoc.v:100625$4062 + attribute \src "libresoc.v:102202.3-102250.6" + process $proc$libresoc.v:102202$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:100626.5-100626.29" + attribute \src "libresoc.v:102203.5-102203.29" switch \initial - attribute \src "libresoc.v:100626.9-100626.17" + attribute \src "libresoc.v:102203.9-102203.17" case 1'1 case end @@ -157406,14 +159541,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:100674.3-100722.6" - process $proc$libresoc.v:100674$4063 + attribute \src "libresoc.v:102251.3-102299.6" + process $proc$libresoc.v:102251$4096 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:100675.5-100675.29" + attribute \src "libresoc.v:102252.5-102252.29" switch \initial - attribute \src "libresoc.v:100675.9-100675.17" + attribute \src "libresoc.v:102252.9-102252.17" case 1'1 case end @@ -157481,14 +159616,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:100723.3-100771.6" - process $proc$libresoc.v:100723$4064 + attribute \src "libresoc.v:102300.3-102348.6" + process $proc$libresoc.v:102300$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:100724.5-100724.29" + attribute \src "libresoc.v:102301.5-102301.29" switch \initial - attribute \src "libresoc.v:100724.9-100724.17" + attribute \src "libresoc.v:102301.9-102301.17" case 1'1 case end @@ -157556,14 +159691,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end - attribute \src "libresoc.v:100772.3-100820.6" - process $proc$libresoc.v:100772$4065 + attribute \src "libresoc.v:102349.3-102397.6" + process $proc$libresoc.v:102349$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:100773.5-100773.29" + attribute \src "libresoc.v:102350.5-102350.29" switch \initial - attribute \src "libresoc.v:100773.9-100773.17" + attribute \src "libresoc.v:102350.9-102350.17" case 1'1 case end @@ -157631,14 +159766,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end - attribute \src "libresoc.v:100821.3-100869.6" - process $proc$libresoc.v:100821$4066 + attribute \src "libresoc.v:102398.3-102446.6" + process $proc$libresoc.v:102398$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:100822.5-100822.29" + attribute \src "libresoc.v:102399.5-102399.29" switch \initial - attribute \src "libresoc.v:100822.9-100822.17" + attribute \src "libresoc.v:102399.9-102399.17" case 1'1 case end @@ -157706,14 +159841,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end - attribute \src "libresoc.v:100870.3-100918.6" - process $proc$libresoc.v:100870$4067 + attribute \src "libresoc.v:102447.3-102495.6" + process $proc$libresoc.v:102447$4100 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:100871.5-100871.29" + attribute \src "libresoc.v:102448.5-102448.29" switch \initial - attribute \src "libresoc.v:100871.9-100871.17" + attribute \src "libresoc.v:102448.9-102448.17" case 1'1 case end @@ -157781,14 +159916,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end - attribute \src "libresoc.v:100919.3-100967.6" - process $proc$libresoc.v:100919$4068 + attribute \src "libresoc.v:102496.3-102544.6" + process $proc$libresoc.v:102496$4101 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:100920.5-100920.29" + attribute \src "libresoc.v:102497.5-102497.29" switch \initial - attribute \src "libresoc.v:100920.9-100920.17" + attribute \src "libresoc.v:102497.9-102497.17" case 1'1 case end @@ -157856,14 +159991,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end - attribute \src "libresoc.v:100968.3-101016.6" - process $proc$libresoc.v:100968$4069 + attribute \src "libresoc.v:102545.3-102593.6" + process $proc$libresoc.v:102545$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:100969.5-100969.29" + attribute \src "libresoc.v:102546.5-102546.29" switch \initial - attribute \src "libresoc.v:100969.9-100969.17" + attribute \src "libresoc.v:102546.9-102546.17" case 1'1 case end @@ -157931,14 +160066,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end - attribute \src "libresoc.v:101017.3-101065.6" - process $proc$libresoc.v:101017$4070 + attribute \src "libresoc.v:102594.3-102642.6" + process $proc$libresoc.v:102594$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:101018.5-101018.29" + attribute \src "libresoc.v:102595.5-102595.29" switch \initial - attribute \src "libresoc.v:101018.9-101018.17" + attribute \src "libresoc.v:102595.9-102595.17" case 1'1 case end @@ -158006,14 +160141,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:101066.3-101114.6" - process $proc$libresoc.v:101066$4071 + attribute \src "libresoc.v:102643.3-102691.6" + process $proc$libresoc.v:102643$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:101067.5-101067.29" + attribute \src "libresoc.v:102644.5-102644.29" switch \initial - attribute \src "libresoc.v:101067.9-101067.17" + attribute \src "libresoc.v:102644.9-102644.17" case 1'1 case end @@ -158081,14 +160216,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:101115.3-101163.6" - process $proc$libresoc.v:101115$4072 + attribute \src "libresoc.v:102692.3-102740.6" + process $proc$libresoc.v:102692$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:101116.5-101116.29" + attribute \src "libresoc.v:102693.5-102693.29" switch \initial - attribute \src "libresoc.v:101116.9-101116.17" + attribute \src "libresoc.v:102693.9-102693.17" case 1'1 case end @@ -158156,14 +160291,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:101164.3-101212.6" - process $proc$libresoc.v:101164$4073 + attribute \src "libresoc.v:102741.3-102789.6" + process $proc$libresoc.v:102741$4106 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:101165.5-101165.29" + attribute \src "libresoc.v:102742.5-102742.29" switch \initial - attribute \src "libresoc.v:101165.9-101165.17" + attribute \src "libresoc.v:102742.9-102742.17" case 1'1 case end @@ -158231,14 +160366,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:101213.3-101261.6" - process $proc$libresoc.v:101213$4074 + attribute \src "libresoc.v:102790.3-102838.6" + process $proc$libresoc.v:102790$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:101214.5-101214.29" + attribute \src "libresoc.v:102791.5-102791.29" switch \initial - attribute \src "libresoc.v:101214.9-101214.17" + attribute \src "libresoc.v:102791.9-102791.17" case 1'1 case end @@ -158306,14 +160441,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:101262.3-101310.6" - process $proc$libresoc.v:101262$4075 + attribute \src "libresoc.v:102839.3-102887.6" + process $proc$libresoc.v:102839$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:101263.5-101263.29" + attribute \src "libresoc.v:102840.5-102840.29" switch \initial - attribute \src "libresoc.v:101263.9-101263.17" + attribute \src "libresoc.v:102840.9-102840.17" case 1'1 case end @@ -158381,14 +160516,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:101311.3-101359.6" - process $proc$libresoc.v:101311$4076 + attribute \src "libresoc.v:102888.3-102936.6" + process $proc$libresoc.v:102888$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:101312.5-101312.29" + attribute \src "libresoc.v:102889.5-102889.29" switch \initial - attribute \src "libresoc.v:101312.9-101312.17" + attribute \src "libresoc.v:102889.9-102889.17" case 1'1 case end @@ -158456,14 +160591,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:101360.3-101408.6" - process $proc$libresoc.v:101360$4077 + attribute \src "libresoc.v:102937.3-102985.6" + process $proc$libresoc.v:102937$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:101361.5-101361.29" + attribute \src "libresoc.v:102938.5-102938.29" switch \initial - attribute \src "libresoc.v:101361.9-101361.17" + attribute \src "libresoc.v:102938.9-102938.17" case 1'1 case end @@ -158531,14 +160666,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:101409.3-101457.6" - process $proc$libresoc.v:101409$4078 + attribute \src "libresoc.v:102986.3-103034.6" + process $proc$libresoc.v:102986$4111 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:101410.5-101410.29" + attribute \src "libresoc.v:102987.5-102987.29" switch \initial - attribute \src "libresoc.v:101410.9-101410.17" + attribute \src "libresoc.v:102987.9-102987.17" case 1'1 case end @@ -158606,14 +160741,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:101458.3-101506.6" - process $proc$libresoc.v:101458$4079 + attribute \src "libresoc.v:103035.3-103083.6" + process $proc$libresoc.v:103035$4112 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:101459.5-101459.29" + attribute \src "libresoc.v:103036.5-103036.29" switch \initial - attribute \src "libresoc.v:101459.9-101459.17" + attribute \src "libresoc.v:103036.9-103036.17" case 1'1 case end @@ -158681,14 +160816,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:101507.3-101555.6" - process $proc$libresoc.v:101507$4080 + attribute \src "libresoc.v:103084.3-103132.6" + process $proc$libresoc.v:103084$4113 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:101508.5-101508.29" + attribute \src "libresoc.v:103085.5-103085.29" switch \initial - attribute \src "libresoc.v:101508.9-101508.17" + attribute \src "libresoc.v:103085.9-103085.17" case 1'1 case end @@ -158756,14 +160891,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:101556.3-101604.6" - process $proc$libresoc.v:101556$4081 + attribute \src "libresoc.v:103133.3-103181.6" + process $proc$libresoc.v:103133$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:101557.5-101557.29" + attribute \src "libresoc.v:103134.5-103134.29" switch \initial - attribute \src "libresoc.v:101557.9-101557.17" + attribute \src "libresoc.v:103134.9-103134.17" case 1'1 case end @@ -158831,14 +160966,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:101605.3-101653.6" - process $proc$libresoc.v:101605$4082 + attribute \src "libresoc.v:103182.3-103230.6" + process $proc$libresoc.v:103182$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:101606.5-101606.29" + attribute \src "libresoc.v:103183.5-103183.29" switch \initial - attribute \src "libresoc.v:101606.9-101606.17" + attribute \src "libresoc.v:103183.9-103183.17" case 1'1 case end @@ -158906,14 +161041,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:101654.3-101702.6" - process $proc$libresoc.v:101654$4083 + attribute \src "libresoc.v:103231.3-103279.6" + process $proc$libresoc.v:103231$4116 assign { } { } assign { } { } assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:101655.5-101655.29" + attribute \src "libresoc.v:103232.5-103232.29" switch \initial - attribute \src "libresoc.v:101655.9-101655.17" + attribute \src "libresoc.v:103232.9-103232.17" case 1'1 case end @@ -158981,14 +161116,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:101703.3-101751.6" - process $proc$libresoc.v:101703$4084 + attribute \src "libresoc.v:103280.3-103328.6" + process $proc$libresoc.v:103280$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:101704.5-101704.29" + attribute \src "libresoc.v:103281.5-103281.29" switch \initial - attribute \src "libresoc.v:101704.9-101704.17" + attribute \src "libresoc.v:103281.9-103281.17" case 1'1 case end @@ -159056,14 +161191,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "libresoc.v:101752.3-101800.6" - process $proc$libresoc.v:101752$4085 + attribute \src "libresoc.v:103329.3-103377.6" + process $proc$libresoc.v:103329$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:101753.5-101753.29" + attribute \src "libresoc.v:103330.5-103330.29" switch \initial - attribute \src "libresoc.v:101753.9-101753.17" + attribute \src "libresoc.v:103330.9-103330.17" case 1'1 case end @@ -159131,14 +161266,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "libresoc.v:101801.3-101831.6" - process $proc$libresoc.v:101801$4086 + attribute \src "libresoc.v:103378.3-103408.6" + process $proc$libresoc.v:103378$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:101802.5-101802.29" + attribute \src "libresoc.v:103379.5-103379.29" switch \initial - attribute \src "libresoc.v:101802.9-101802.17" + attribute \src "libresoc.v:103379.9-103379.17" case 1'1 case end @@ -159182,14 +161317,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:101832.3-101880.6" - process $proc$libresoc.v:101832$4087 + attribute \src "libresoc.v:103409.3-103457.6" + process $proc$libresoc.v:103409$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:101833.5-101833.29" + attribute \src "libresoc.v:103410.5-103410.29" switch \initial - attribute \src "libresoc.v:101833.9-101833.17" + attribute \src "libresoc.v:103410.9-103410.17" case 1'1 case end @@ -159257,14 +161392,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] end - attribute \src "libresoc.v:101881.3-101929.6" - process $proc$libresoc.v:101881$4088 + attribute \src "libresoc.v:103458.3-103506.6" + process $proc$libresoc.v:103458$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:101882.5-101882.29" + attribute \src "libresoc.v:103459.5-103459.29" switch \initial - attribute \src "libresoc.v:101882.9-101882.17" + attribute \src "libresoc.v:103459.9-103459.17" case 1'1 case end @@ -159332,14 +161467,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] end - attribute \src "libresoc.v:101930.3-101978.6" - process $proc$libresoc.v:101930$4089 + attribute \src "libresoc.v:103507.3-103555.6" + process $proc$libresoc.v:103507$4122 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:101931.5-101931.29" + attribute \src "libresoc.v:103508.5-103508.29" switch \initial - attribute \src "libresoc.v:101931.9-101931.17" + attribute \src "libresoc.v:103508.9-103508.17" case 1'1 case end @@ -159407,14 +161542,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:101979.3-102027.6" - process $proc$libresoc.v:101979$4090 + attribute \src "libresoc.v:103556.3-103604.6" + process $proc$libresoc.v:103556$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:101980.5-101980.29" + attribute \src "libresoc.v:103557.5-103557.29" switch \initial - attribute \src "libresoc.v:101980.9-101980.17" + attribute \src "libresoc.v:103557.9-103557.17" case 1'1 case end @@ -159482,14 +161617,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:102028.3-102076.6" - process $proc$libresoc.v:102028$4091 + attribute \src "libresoc.v:103605.3-103653.6" + process $proc$libresoc.v:103605$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:102029.5-102029.29" + attribute \src "libresoc.v:103606.5-103606.29" switch \initial - attribute \src "libresoc.v:102029.9-102029.17" + attribute \src "libresoc.v:103606.9-103606.17" case 1'1 case end @@ -159557,14 +161692,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:102077.3-102125.6" - process $proc$libresoc.v:102077$4092 + attribute \src "libresoc.v:103654.3-103702.6" + process $proc$libresoc.v:103654$4125 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:102078.5-102078.29" + assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] + attribute \src "libresoc.v:103655.5-103655.29" switch \initial - attribute \src "libresoc.v:102078.9-102078.17" + attribute \src "libresoc.v:103655.9-103655.17" case 1'1 case end @@ -159573,201 +161708,201 @@ module \dec31_dec_sub21 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:102131.1-104228.10" +attribute \src "libresoc.v:103708.1-105808.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 - attribute \src "libresoc.v:103897.3-103951.6" + attribute \src "libresoc.v:105477.3-105531.6" wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:103952.3-104006.6" + attribute \src "libresoc.v:105532.3-105586.6" wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:103237.3-103291.6" + attribute \src "libresoc.v:104817.3-104871.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:103457.3-103511.6" + attribute \src "libresoc.v:105037.3-105091.6" wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:102522.3-102576.6" + attribute \src "libresoc.v:104102.3-104156.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:102577.3-102631.6" + attribute \src "libresoc.v:104157.3-104211.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:103182.3-103236.6" + attribute \src "libresoc.v:104762.3-104816.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:103402.3-103456.6" + attribute \src "libresoc.v:104982.3-105036.6" wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:103677.3-103731.6" + attribute \src "libresoc.v:105257.3-105311.6" wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:102467.3-102521.6" - wire width 13 $0\dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:104007.3-104061.6" + attribute \src "libresoc.v:104047.3-104101.6" + wire width 14 $0\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:105587.3-105641.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:104062.3-104116.6" + attribute \src "libresoc.v:105642.3-105696.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:104117.3-104171.6" + attribute \src "libresoc.v:105697.3-105751.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:103072.3-103126.6" + attribute \src "libresoc.v:104652.3-104706.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:103292.3-103346.6" + attribute \src "libresoc.v:104872.3-104926.6" wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:103347.3-103401.6" + attribute \src "libresoc.v:104927.3-104981.6" wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:103622.3-103676.6" + attribute \src "libresoc.v:105202.3-105256.6" wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:102962.3-103016.6" + attribute \src "libresoc.v:104542.3-104596.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:103787.3-103841.6" + attribute \src "libresoc.v:105367.3-105421.6" wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:104172.3-104226.6" - wire width 2 $0\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:103127.3-103181.6" + attribute \src "libresoc.v:105752.3-105806.6" + wire width 3 $0\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:104707.3-104761.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:103567.3-103621.6" + attribute \src "libresoc.v:105147.3-105201.6" wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:103842.3-103896.6" + attribute \src "libresoc.v:105422.3-105476.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:103732.3-103786.6" + attribute \src "libresoc.v:105312.3-105366.6" wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:103512.3-103566.6" + attribute \src "libresoc.v:105092.3-105146.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:102852.3-102906.6" + attribute \src "libresoc.v:104432.3-104486.6" wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:102907.3-102961.6" + attribute \src "libresoc.v:104487.3-104541.6" wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:102632.3-102686.6" + attribute \src "libresoc.v:104212.3-104266.6" wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:102687.3-102741.6" + attribute \src "libresoc.v:104267.3-104321.6" wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:102742.3-102796.6" + attribute \src "libresoc.v:104322.3-104376.6" wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:102797.3-102851.6" + attribute \src "libresoc.v:104377.3-104431.6" wire width 3 $0\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:103017.3-103071.6" + attribute \src "libresoc.v:104597.3-104651.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:102132.7-102132.20" + attribute \src "libresoc.v:103709.7-103709.20" wire $0\initial[0:0] - attribute \src "libresoc.v:103897.3-103951.6" + attribute \src "libresoc.v:105477.3-105531.6" wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:103952.3-104006.6" + attribute \src "libresoc.v:105532.3-105586.6" wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:103237.3-103291.6" + attribute \src "libresoc.v:104817.3-104871.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:103457.3-103511.6" + attribute \src "libresoc.v:105037.3-105091.6" wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:102522.3-102576.6" + attribute \src "libresoc.v:104102.3-104156.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:102577.3-102631.6" + attribute \src "libresoc.v:104157.3-104211.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:103182.3-103236.6" + attribute \src "libresoc.v:104762.3-104816.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:103402.3-103456.6" + attribute \src "libresoc.v:104982.3-105036.6" wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:103677.3-103731.6" + attribute \src "libresoc.v:105257.3-105311.6" wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:102467.3-102521.6" - wire width 13 $1\dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:104007.3-104061.6" + attribute \src "libresoc.v:104047.3-104101.6" + wire width 14 $1\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:105587.3-105641.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:104062.3-104116.6" + attribute \src "libresoc.v:105642.3-105696.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:104117.3-104171.6" + attribute \src "libresoc.v:105697.3-105751.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:103072.3-103126.6" + attribute \src "libresoc.v:104652.3-104706.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:103292.3-103346.6" + attribute \src "libresoc.v:104872.3-104926.6" wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:103347.3-103401.6" + attribute \src "libresoc.v:104927.3-104981.6" wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:103622.3-103676.6" + attribute \src "libresoc.v:105202.3-105256.6" wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:102962.3-103016.6" + attribute \src "libresoc.v:104542.3-104596.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:103787.3-103841.6" + attribute \src "libresoc.v:105367.3-105421.6" wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:104172.3-104226.6" - wire width 2 $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:103127.3-103181.6" + attribute \src "libresoc.v:105752.3-105806.6" + wire width 3 $1\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:104707.3-104761.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:103567.3-103621.6" + attribute \src "libresoc.v:105147.3-105201.6" wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:103842.3-103896.6" + attribute \src "libresoc.v:105422.3-105476.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:103732.3-103786.6" + attribute \src "libresoc.v:105312.3-105366.6" wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:103512.3-103566.6" + attribute \src "libresoc.v:105092.3-105146.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:102852.3-102906.6" + attribute \src "libresoc.v:104432.3-104486.6" wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:102907.3-102961.6" + attribute \src "libresoc.v:104487.3-104541.6" wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:102632.3-102686.6" + attribute \src "libresoc.v:104212.3-104266.6" wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:102687.3-102741.6" + attribute \src "libresoc.v:104267.3-104321.6" wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:102742.3-102796.6" + attribute \src "libresoc.v:104322.3-104376.6" wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:102797.3-102851.6" + attribute \src "libresoc.v:104377.3-104431.6" wire width 3 $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:103017.3-103071.6" + attribute \src "libresoc.v:104597.3-104651.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -159847,21 +161982,22 @@ module \dec31_dec_sub22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub22_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub22_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -159967,6 +162103,7 @@ module \dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -159986,12 +162123,13 @@ module \dec31_dec_sub22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub22_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub22_out_sel + wire width 3 output 10 \dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -160067,28 +162205,28 @@ module \dec31_dec_sub22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub22_upd - attribute \src "libresoc.v:102132.7-102132.15" + attribute \src "libresoc.v:103709.7-103709.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:102132.7-102132.20" - process $proc$libresoc.v:102132$4126 + attribute \src "libresoc.v:103709.7-103709.20" + process $proc$libresoc.v:103709$4159 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:102467.3-102521.6" - process $proc$libresoc.v:102467$4094 + attribute \src "libresoc.v:104047.3-104101.6" + process $proc$libresoc.v:104047$4127 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_function_unit[12:0] $1\dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:102468.5-102468.29" + assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] + attribute \src "libresoc.v:104048.5-104048.29" switch \initial - attribute \src "libresoc.v:102468.9-102468.17" + attribute \src "libresoc.v:104048.9-104048.17" case 1'1 case end @@ -160097,81 +162235,81 @@ module \dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0100000000000 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 case - assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[12:0] + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:102522.3-102576.6" - process $proc$libresoc.v:102522$4095 + attribute \src "libresoc.v:104102.3-104156.6" + process $proc$libresoc.v:104102$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:102523.5-102523.29" + attribute \src "libresoc.v:104103.5-104103.29" switch \initial - attribute \src "libresoc.v:102523.9-102523.17" + attribute \src "libresoc.v:104103.9-104103.17" case 1'1 case end @@ -160247,14 +162385,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:102577.3-102631.6" - process $proc$libresoc.v:102577$4096 + attribute \src "libresoc.v:104157.3-104211.6" + process $proc$libresoc.v:104157$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:102578.5-102578.29" + attribute \src "libresoc.v:104158.5-104158.29" switch \initial - attribute \src "libresoc.v:102578.9-102578.17" + attribute \src "libresoc.v:104158.9-104158.17" case 1'1 case end @@ -160330,14 +162468,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:102632.3-102686.6" - process $proc$libresoc.v:102632$4097 + attribute \src "libresoc.v:104212.3-104266.6" + process $proc$libresoc.v:104212$4130 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:102633.5-102633.29" + attribute \src "libresoc.v:104213.5-104213.29" switch \initial - attribute \src "libresoc.v:102633.9-102633.17" + attribute \src "libresoc.v:104213.9-104213.17" case 1'1 case end @@ -160413,14 +162551,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end - attribute \src "libresoc.v:102687.3-102741.6" - process $proc$libresoc.v:102687$4098 + attribute \src "libresoc.v:104267.3-104321.6" + process $proc$libresoc.v:104267$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:102688.5-102688.29" + attribute \src "libresoc.v:104268.5-104268.29" switch \initial - attribute \src "libresoc.v:102688.9-102688.17" + attribute \src "libresoc.v:104268.9-104268.17" case 1'1 case end @@ -160496,14 +162634,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end - attribute \src "libresoc.v:102742.3-102796.6" - process $proc$libresoc.v:102742$4099 + attribute \src "libresoc.v:104322.3-104376.6" + process $proc$libresoc.v:104322$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:102743.5-102743.29" + attribute \src "libresoc.v:104323.5-104323.29" switch \initial - attribute \src "libresoc.v:102743.9-102743.17" + attribute \src "libresoc.v:104323.9-104323.17" case 1'1 case end @@ -160579,14 +162717,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end - attribute \src "libresoc.v:102797.3-102851.6" - process $proc$libresoc.v:102797$4100 + attribute \src "libresoc.v:104377.3-104431.6" + process $proc$libresoc.v:104377$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:102798.5-102798.29" + attribute \src "libresoc.v:104378.5-104378.29" switch \initial - attribute \src "libresoc.v:102798.9-102798.17" + attribute \src "libresoc.v:104378.9-104378.17" case 1'1 case end @@ -160662,14 +162800,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end - attribute \src "libresoc.v:102852.3-102906.6" - process $proc$libresoc.v:102852$4101 + attribute \src "libresoc.v:104432.3-104486.6" + process $proc$libresoc.v:104432$4134 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:102853.5-102853.29" + attribute \src "libresoc.v:104433.5-104433.29" switch \initial - attribute \src "libresoc.v:102853.9-102853.17" + attribute \src "libresoc.v:104433.9-104433.17" case 1'1 case end @@ -160745,14 +162883,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end - attribute \src "libresoc.v:102907.3-102961.6" - process $proc$libresoc.v:102907$4102 + attribute \src "libresoc.v:104487.3-104541.6" + process $proc$libresoc.v:104487$4135 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:102908.5-102908.29" + attribute \src "libresoc.v:104488.5-104488.29" switch \initial - attribute \src "libresoc.v:102908.9-102908.17" + attribute \src "libresoc.v:104488.9-104488.17" case 1'1 case end @@ -160828,14 +162966,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end - attribute \src "libresoc.v:102962.3-103016.6" - process $proc$libresoc.v:102962$4103 + attribute \src "libresoc.v:104542.3-104596.6" + process $proc$libresoc.v:104542$4136 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:102963.5-102963.29" + attribute \src "libresoc.v:104543.5-104543.29" switch \initial - attribute \src "libresoc.v:102963.9-102963.17" + attribute \src "libresoc.v:104543.9-104543.17" case 1'1 case end @@ -160911,14 +163049,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:103017.3-103071.6" - process $proc$libresoc.v:103017$4104 + attribute \src "libresoc.v:104597.3-104651.6" + process $proc$libresoc.v:104597$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:103018.5-103018.29" + attribute \src "libresoc.v:104598.5-104598.29" switch \initial - attribute \src "libresoc.v:103018.9-103018.17" + attribute \src "libresoc.v:104598.9-104598.17" case 1'1 case end @@ -160994,14 +163132,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:103072.3-103126.6" - process $proc$libresoc.v:103072$4105 + attribute \src "libresoc.v:104652.3-104706.6" + process $proc$libresoc.v:104652$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:103073.5-103073.29" + attribute \src "libresoc.v:104653.5-104653.29" switch \initial - attribute \src "libresoc.v:103073.9-103073.17" + attribute \src "libresoc.v:104653.9-104653.17" case 1'1 case end @@ -161077,14 +163215,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:103127.3-103181.6" - process $proc$libresoc.v:103127$4106 + attribute \src "libresoc.v:104707.3-104761.6" + process $proc$libresoc.v:104707$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:103128.5-103128.29" + attribute \src "libresoc.v:104708.5-104708.29" switch \initial - attribute \src "libresoc.v:103128.9-103128.17" + attribute \src "libresoc.v:104708.9-104708.17" case 1'1 case end @@ -161160,14 +163298,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:103182.3-103236.6" - process $proc$libresoc.v:103182$4107 + attribute \src "libresoc.v:104762.3-104816.6" + process $proc$libresoc.v:104762$4140 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:103183.5-103183.29" + attribute \src "libresoc.v:104763.5-104763.29" switch \initial - attribute \src "libresoc.v:103183.9-103183.17" + attribute \src "libresoc.v:104763.9-104763.17" case 1'1 case end @@ -161243,14 +163381,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:103237.3-103291.6" - process $proc$libresoc.v:103237$4108 + attribute \src "libresoc.v:104817.3-104871.6" + process $proc$libresoc.v:104817$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:103238.5-103238.29" + attribute \src "libresoc.v:104818.5-104818.29" switch \initial - attribute \src "libresoc.v:103238.9-103238.17" + attribute \src "libresoc.v:104818.9-104818.17" case 1'1 case end @@ -161326,14 +163464,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:103292.3-103346.6" - process $proc$libresoc.v:103292$4109 + attribute \src "libresoc.v:104872.3-104926.6" + process $proc$libresoc.v:104872$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:103293.5-103293.29" + attribute \src "libresoc.v:104873.5-104873.29" switch \initial - attribute \src "libresoc.v:103293.9-103293.17" + attribute \src "libresoc.v:104873.9-104873.17" case 1'1 case end @@ -161409,14 +163547,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:103347.3-103401.6" - process $proc$libresoc.v:103347$4110 + attribute \src "libresoc.v:104927.3-104981.6" + process $proc$libresoc.v:104927$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:103348.5-103348.29" + attribute \src "libresoc.v:104928.5-104928.29" switch \initial - attribute \src "libresoc.v:103348.9-103348.17" + attribute \src "libresoc.v:104928.9-104928.17" case 1'1 case end @@ -161492,14 +163630,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:103402.3-103456.6" - process $proc$libresoc.v:103402$4111 + attribute \src "libresoc.v:104982.3-105036.6" + process $proc$libresoc.v:104982$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:103403.5-103403.29" + attribute \src "libresoc.v:104983.5-104983.29" switch \initial - attribute \src "libresoc.v:103403.9-103403.17" + attribute \src "libresoc.v:104983.9-104983.17" case 1'1 case end @@ -161575,14 +163713,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:103457.3-103511.6" - process $proc$libresoc.v:103457$4112 + attribute \src "libresoc.v:105037.3-105091.6" + process $proc$libresoc.v:105037$4145 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:103458.5-103458.29" + attribute \src "libresoc.v:105038.5-105038.29" switch \initial - attribute \src "libresoc.v:103458.9-103458.17" + attribute \src "libresoc.v:105038.9-105038.17" case 1'1 case end @@ -161658,14 +163796,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:103512.3-103566.6" - process $proc$libresoc.v:103512$4113 + attribute \src "libresoc.v:105092.3-105146.6" + process $proc$libresoc.v:105092$4146 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:103513.5-103513.29" + attribute \src "libresoc.v:105093.5-105093.29" switch \initial - attribute \src "libresoc.v:103513.9-103513.17" + attribute \src "libresoc.v:105093.9-105093.17" case 1'1 case end @@ -161741,14 +163879,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:103567.3-103621.6" - process $proc$libresoc.v:103567$4114 + attribute \src "libresoc.v:105147.3-105201.6" + process $proc$libresoc.v:105147$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:103568.5-103568.29" + attribute \src "libresoc.v:105148.5-105148.29" switch \initial - attribute \src "libresoc.v:103568.9-103568.17" + attribute \src "libresoc.v:105148.9-105148.17" case 1'1 case end @@ -161824,14 +163962,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:103622.3-103676.6" - process $proc$libresoc.v:103622$4115 + attribute \src "libresoc.v:105202.3-105256.6" + process $proc$libresoc.v:105202$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:103623.5-103623.29" + attribute \src "libresoc.v:105203.5-105203.29" switch \initial - attribute \src "libresoc.v:103623.9-103623.17" + attribute \src "libresoc.v:105203.9-105203.17" case 1'1 case end @@ -161907,14 +164045,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:103677.3-103731.6" - process $proc$libresoc.v:103677$4116 + attribute \src "libresoc.v:105257.3-105311.6" + process $proc$libresoc.v:105257$4149 assign { } { } assign { } { } assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:103678.5-103678.29" + attribute \src "libresoc.v:105258.5-105258.29" switch \initial - attribute \src "libresoc.v:103678.9-103678.17" + attribute \src "libresoc.v:105258.9-105258.17" case 1'1 case end @@ -161990,14 +164128,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:103732.3-103786.6" - process $proc$libresoc.v:103732$4117 + attribute \src "libresoc.v:105312.3-105366.6" + process $proc$libresoc.v:105312$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:103733.5-103733.29" + attribute \src "libresoc.v:105313.5-105313.29" switch \initial - attribute \src "libresoc.v:103733.9-103733.17" + attribute \src "libresoc.v:105313.9-105313.17" case 1'1 case end @@ -162073,14 +164211,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:103787.3-103841.6" - process $proc$libresoc.v:103787$4118 + attribute \src "libresoc.v:105367.3-105421.6" + process $proc$libresoc.v:105367$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:103788.5-103788.29" + attribute \src "libresoc.v:105368.5-105368.29" switch \initial - attribute \src "libresoc.v:103788.9-103788.17" + attribute \src "libresoc.v:105368.9-105368.17" case 1'1 case end @@ -162156,14 +164294,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:103842.3-103896.6" - process $proc$libresoc.v:103842$4119 + attribute \src "libresoc.v:105422.3-105476.6" + process $proc$libresoc.v:105422$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:103843.5-103843.29" + attribute \src "libresoc.v:105423.5-105423.29" switch \initial - attribute \src "libresoc.v:103843.9-103843.17" + attribute \src "libresoc.v:105423.9-105423.17" case 1'1 case end @@ -162239,14 +164377,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:103897.3-103951.6" - process $proc$libresoc.v:103897$4120 + attribute \src "libresoc.v:105477.3-105531.6" + process $proc$libresoc.v:105477$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:103898.5-103898.29" + attribute \src "libresoc.v:105478.5-105478.29" switch \initial - attribute \src "libresoc.v:103898.9-103898.17" + attribute \src "libresoc.v:105478.9-105478.17" case 1'1 case end @@ -162322,14 +164460,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end - attribute \src "libresoc.v:103952.3-104006.6" - process $proc$libresoc.v:103952$4121 + attribute \src "libresoc.v:105532.3-105586.6" + process $proc$libresoc.v:105532$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:103953.5-103953.29" + attribute \src "libresoc.v:105533.5-105533.29" switch \initial - attribute \src "libresoc.v:103953.9-103953.17" + attribute \src "libresoc.v:105533.9-105533.17" case 1'1 case end @@ -162405,14 +164543,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end - attribute \src "libresoc.v:104007.3-104061.6" - process $proc$libresoc.v:104007$4122 + attribute \src "libresoc.v:105587.3-105641.6" + process $proc$libresoc.v:105587$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:104008.5-104008.29" + attribute \src "libresoc.v:105588.5-105588.29" switch \initial - attribute \src "libresoc.v:104008.9-104008.17" + attribute \src "libresoc.v:105588.9-105588.17" case 1'1 case end @@ -162488,14 +164626,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:104062.3-104116.6" - process $proc$libresoc.v:104062$4123 + attribute \src "libresoc.v:105642.3-105696.6" + process $proc$libresoc.v:105642$4156 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:104063.5-104063.29" + attribute \src "libresoc.v:105643.5-105643.29" switch \initial - attribute \src "libresoc.v:104063.9-104063.17" + attribute \src "libresoc.v:105643.9-105643.17" case 1'1 case end @@ -162571,14 +164709,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:104117.3-104171.6" - process $proc$libresoc.v:104117$4124 + attribute \src "libresoc.v:105697.3-105751.6" + process $proc$libresoc.v:105697$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:104118.5-104118.29" + attribute \src "libresoc.v:105698.5-105698.29" switch \initial - attribute \src "libresoc.v:104118.9-104118.17" + attribute \src "libresoc.v:105698.9-105698.17" case 1'1 case end @@ -162654,14 +164792,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:104172.3-104226.6" - process $proc$libresoc.v:104172$4125 + attribute \src "libresoc.v:105752.3-105806.6" + process $proc$libresoc.v:105752$4158 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:104173.5-104173.29" + assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] + attribute \src "libresoc.v:105753.5-105753.29" switch \initial - attribute \src "libresoc.v:104173.9-104173.17" + attribute \src "libresoc.v:105753.9-105753.17" case 1'1 case end @@ -162670,209 +164808,209 @@ module \dec31_dec_sub22 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:104232.1-106137.10" +attribute \src "libresoc.v:105812.1-107720.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 - attribute \src "libresoc.v:105842.3-105890.6" + attribute \src "libresoc.v:107425.3-107473.6" wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:105891.3-105939.6" + attribute \src "libresoc.v:107474.3-107522.6" wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:105254.3-105302.6" + attribute \src "libresoc.v:106837.3-106885.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:105450.3-105498.6" + attribute \src "libresoc.v:107033.3-107081.6" wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:104617.3-104665.6" + attribute \src "libresoc.v:106200.3-106248.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:104666.3-104714.6" + attribute \src "libresoc.v:106249.3-106297.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:105205.3-105253.6" + attribute \src "libresoc.v:106788.3-106836.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:105401.3-105449.6" + attribute \src "libresoc.v:106984.3-107032.6" wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:105646.3-105694.6" + attribute \src "libresoc.v:107229.3-107277.6" wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:104568.3-104616.6" - wire width 13 $0\dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:105940.3-105988.6" + attribute \src "libresoc.v:106151.3-106199.6" + wire width 14 $0\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:107523.3-107571.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:105989.3-106037.6" + attribute \src "libresoc.v:107572.3-107620.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:106038.3-106086.6" + attribute \src "libresoc.v:107621.3-107669.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:105107.3-105155.6" + attribute \src "libresoc.v:106690.3-106738.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:105303.3-105351.6" + attribute \src "libresoc.v:106886.3-106934.6" wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:105352.3-105400.6" + attribute \src "libresoc.v:106935.3-106983.6" wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:105597.3-105645.6" + attribute \src "libresoc.v:107180.3-107228.6" wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:105009.3-105057.6" + attribute \src "libresoc.v:106592.3-106640.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:105744.3-105792.6" + attribute \src "libresoc.v:107327.3-107375.6" wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:106087.3-106135.6" - wire width 2 $0\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:105156.3-105204.6" + attribute \src "libresoc.v:107670.3-107718.6" + wire width 3 $0\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:106739.3-106787.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:105548.3-105596.6" + attribute \src "libresoc.v:107131.3-107179.6" wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:105793.3-105841.6" + attribute \src "libresoc.v:107376.3-107424.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:105695.3-105743.6" + attribute \src "libresoc.v:107278.3-107326.6" wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:105499.3-105547.6" + attribute \src "libresoc.v:107082.3-107130.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:104911.3-104959.6" + attribute \src "libresoc.v:106494.3-106542.6" wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:104960.3-105008.6" + attribute \src "libresoc.v:106543.3-106591.6" wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:104715.3-104763.6" + attribute \src "libresoc.v:106298.3-106346.6" wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:104764.3-104812.6" + attribute \src "libresoc.v:106347.3-106395.6" wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:104813.3-104861.6" + attribute \src "libresoc.v:106396.3-106444.6" wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:104862.3-104910.6" + attribute \src "libresoc.v:106445.3-106493.6" wire width 3 $0\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:105058.3-105106.6" + attribute \src "libresoc.v:106641.3-106689.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:104233.7-104233.20" + attribute \src "libresoc.v:105813.7-105813.20" wire $0\initial[0:0] - attribute \src "libresoc.v:105842.3-105890.6" + attribute \src "libresoc.v:107425.3-107473.6" wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:105891.3-105939.6" + attribute \src "libresoc.v:107474.3-107522.6" wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:105254.3-105302.6" + attribute \src "libresoc.v:106837.3-106885.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:105450.3-105498.6" + attribute \src "libresoc.v:107033.3-107081.6" wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:104617.3-104665.6" + attribute \src "libresoc.v:106200.3-106248.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:104666.3-104714.6" + attribute \src "libresoc.v:106249.3-106297.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:105205.3-105253.6" + attribute \src "libresoc.v:106788.3-106836.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:105401.3-105449.6" + attribute \src "libresoc.v:106984.3-107032.6" wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:105646.3-105694.6" + attribute \src "libresoc.v:107229.3-107277.6" wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:104568.3-104616.6" - wire width 13 $1\dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:105940.3-105988.6" + attribute \src "libresoc.v:106151.3-106199.6" + wire width 14 $1\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:107523.3-107571.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:105989.3-106037.6" + attribute \src "libresoc.v:107572.3-107620.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:106038.3-106086.6" + attribute \src "libresoc.v:107621.3-107669.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:105107.3-105155.6" + attribute \src "libresoc.v:106690.3-106738.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:105303.3-105351.6" + attribute \src "libresoc.v:106886.3-106934.6" wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:105352.3-105400.6" + attribute \src "libresoc.v:106935.3-106983.6" wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:105597.3-105645.6" + attribute \src "libresoc.v:107180.3-107228.6" wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:105009.3-105057.6" + attribute \src "libresoc.v:106592.3-106640.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:105744.3-105792.6" + attribute \src "libresoc.v:107327.3-107375.6" wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:106087.3-106135.6" - wire width 2 $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:105156.3-105204.6" + attribute \src "libresoc.v:107670.3-107718.6" + wire width 3 $1\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:106739.3-106787.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:105548.3-105596.6" + attribute \src "libresoc.v:107131.3-107179.6" wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:105793.3-105841.6" + attribute \src "libresoc.v:107376.3-107424.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:105695.3-105743.6" + attribute \src "libresoc.v:107278.3-107326.6" wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:105499.3-105547.6" + attribute \src "libresoc.v:107082.3-107130.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:104911.3-104959.6" + attribute \src "libresoc.v:106494.3-106542.6" wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:104960.3-105008.6" + attribute \src "libresoc.v:106543.3-106591.6" wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:104715.3-104763.6" + attribute \src "libresoc.v:106298.3-106346.6" wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:104764.3-104812.6" + attribute \src "libresoc.v:106347.3-106395.6" wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:104813.3-104861.6" + attribute \src "libresoc.v:106396.3-106444.6" wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:104862.3-104910.6" + attribute \src "libresoc.v:106445.3-106493.6" wire width 3 $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:105058.3-105106.6" + attribute \src "libresoc.v:106641.3-106689.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -162952,21 +165090,22 @@ module \dec31_dec_sub23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub23_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub23_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -163072,6 +165211,7 @@ module \dec31_dec_sub23 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub23_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -163091,12 +165231,13 @@ module \dec31_dec_sub23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub23_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub23_out_sel + wire width 3 output 10 \dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -163172,28 +165313,28 @@ module \dec31_dec_sub23 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub23_upd - attribute \src "libresoc.v:104233.7-104233.15" + attribute \src "libresoc.v:105813.7-105813.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:104233.7-104233.20" - process $proc$libresoc.v:104233$4159 + attribute \src "libresoc.v:105813.7-105813.20" + process $proc$libresoc.v:105813$4192 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:104568.3-104616.6" - process $proc$libresoc.v:104568$4127 + attribute \src "libresoc.v:106151.3-106199.6" + process $proc$libresoc.v:106151$4160 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_function_unit[12:0] $1\dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:104569.5-104569.29" + assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] + attribute \src "libresoc.v:106152.5-106152.29" switch \initial - attribute \src "libresoc.v:104569.9-104569.17" + attribute \src "libresoc.v:106152.9-106152.17" case 1'1 case end @@ -163202,73 +165343,73 @@ module \dec31_dec_sub23 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 case - assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[12:0] + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:104617.3-104665.6" - process $proc$libresoc.v:104617$4128 + attribute \src "libresoc.v:106200.3-106248.6" + process $proc$libresoc.v:106200$4161 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:104618.5-104618.29" + attribute \src "libresoc.v:106201.5-106201.29" switch \initial - attribute \src "libresoc.v:104618.9-104618.17" + attribute \src "libresoc.v:106201.9-106201.17" case 1'1 case end @@ -163336,14 +165477,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:104666.3-104714.6" - process $proc$libresoc.v:104666$4129 + attribute \src "libresoc.v:106249.3-106297.6" + process $proc$libresoc.v:106249$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:104667.5-104667.29" + attribute \src "libresoc.v:106250.5-106250.29" switch \initial - attribute \src "libresoc.v:104667.9-104667.17" + attribute \src "libresoc.v:106250.9-106250.17" case 1'1 case end @@ -163411,14 +165552,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:104715.3-104763.6" - process $proc$libresoc.v:104715$4130 + attribute \src "libresoc.v:106298.3-106346.6" + process $proc$libresoc.v:106298$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:104716.5-104716.29" + attribute \src "libresoc.v:106299.5-106299.29" switch \initial - attribute \src "libresoc.v:104716.9-104716.17" + attribute \src "libresoc.v:106299.9-106299.17" case 1'1 case end @@ -163486,14 +165627,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end - attribute \src "libresoc.v:104764.3-104812.6" - process $proc$libresoc.v:104764$4131 + attribute \src "libresoc.v:106347.3-106395.6" + process $proc$libresoc.v:106347$4164 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:104765.5-104765.29" + attribute \src "libresoc.v:106348.5-106348.29" switch \initial - attribute \src "libresoc.v:104765.9-104765.17" + attribute \src "libresoc.v:106348.9-106348.17" case 1'1 case end @@ -163561,14 +165702,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end - attribute \src "libresoc.v:104813.3-104861.6" - process $proc$libresoc.v:104813$4132 + attribute \src "libresoc.v:106396.3-106444.6" + process $proc$libresoc.v:106396$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:104814.5-104814.29" + attribute \src "libresoc.v:106397.5-106397.29" switch \initial - attribute \src "libresoc.v:104814.9-104814.17" + attribute \src "libresoc.v:106397.9-106397.17" case 1'1 case end @@ -163636,14 +165777,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end - attribute \src "libresoc.v:104862.3-104910.6" - process $proc$libresoc.v:104862$4133 + attribute \src "libresoc.v:106445.3-106493.6" + process $proc$libresoc.v:106445$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:104863.5-104863.29" + attribute \src "libresoc.v:106446.5-106446.29" switch \initial - attribute \src "libresoc.v:104863.9-104863.17" + attribute \src "libresoc.v:106446.9-106446.17" case 1'1 case end @@ -163711,14 +165852,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end - attribute \src "libresoc.v:104911.3-104959.6" - process $proc$libresoc.v:104911$4134 + attribute \src "libresoc.v:106494.3-106542.6" + process $proc$libresoc.v:106494$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:104912.5-104912.29" + attribute \src "libresoc.v:106495.5-106495.29" switch \initial - attribute \src "libresoc.v:104912.9-104912.17" + attribute \src "libresoc.v:106495.9-106495.17" case 1'1 case end @@ -163786,14 +165927,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end - attribute \src "libresoc.v:104960.3-105008.6" - process $proc$libresoc.v:104960$4135 + attribute \src "libresoc.v:106543.3-106591.6" + process $proc$libresoc.v:106543$4168 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:104961.5-104961.29" + attribute \src "libresoc.v:106544.5-106544.29" switch \initial - attribute \src "libresoc.v:104961.9-104961.17" + attribute \src "libresoc.v:106544.9-106544.17" case 1'1 case end @@ -163861,14 +166002,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end - attribute \src "libresoc.v:105009.3-105057.6" - process $proc$libresoc.v:105009$4136 + attribute \src "libresoc.v:106592.3-106640.6" + process $proc$libresoc.v:106592$4169 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:105010.5-105010.29" + attribute \src "libresoc.v:106593.5-106593.29" switch \initial - attribute \src "libresoc.v:105010.9-105010.17" + attribute \src "libresoc.v:106593.9-106593.17" case 1'1 case end @@ -163936,14 +166077,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:105058.3-105106.6" - process $proc$libresoc.v:105058$4137 + attribute \src "libresoc.v:106641.3-106689.6" + process $proc$libresoc.v:106641$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:105059.5-105059.29" + attribute \src "libresoc.v:106642.5-106642.29" switch \initial - attribute \src "libresoc.v:105059.9-105059.17" + attribute \src "libresoc.v:106642.9-106642.17" case 1'1 case end @@ -164011,14 +166152,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:105107.3-105155.6" - process $proc$libresoc.v:105107$4138 + attribute \src "libresoc.v:106690.3-106738.6" + process $proc$libresoc.v:106690$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:105108.5-105108.29" + attribute \src "libresoc.v:106691.5-106691.29" switch \initial - attribute \src "libresoc.v:105108.9-105108.17" + attribute \src "libresoc.v:106691.9-106691.17" case 1'1 case end @@ -164086,14 +166227,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:105156.3-105204.6" - process $proc$libresoc.v:105156$4139 + attribute \src "libresoc.v:106739.3-106787.6" + process $proc$libresoc.v:106739$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:105157.5-105157.29" + attribute \src "libresoc.v:106740.5-106740.29" switch \initial - attribute \src "libresoc.v:105157.9-105157.17" + attribute \src "libresoc.v:106740.9-106740.17" case 1'1 case end @@ -164161,14 +166302,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:105205.3-105253.6" - process $proc$libresoc.v:105205$4140 + attribute \src "libresoc.v:106788.3-106836.6" + process $proc$libresoc.v:106788$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:105206.5-105206.29" + attribute \src "libresoc.v:106789.5-106789.29" switch \initial - attribute \src "libresoc.v:105206.9-105206.17" + attribute \src "libresoc.v:106789.9-106789.17" case 1'1 case end @@ -164236,14 +166377,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:105254.3-105302.6" - process $proc$libresoc.v:105254$4141 + attribute \src "libresoc.v:106837.3-106885.6" + process $proc$libresoc.v:106837$4174 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:105255.5-105255.29" + attribute \src "libresoc.v:106838.5-106838.29" switch \initial - attribute \src "libresoc.v:105255.9-105255.17" + attribute \src "libresoc.v:106838.9-106838.17" case 1'1 case end @@ -164311,14 +166452,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:105303.3-105351.6" - process $proc$libresoc.v:105303$4142 + attribute \src "libresoc.v:106886.3-106934.6" + process $proc$libresoc.v:106886$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:105304.5-105304.29" + attribute \src "libresoc.v:106887.5-106887.29" switch \initial - attribute \src "libresoc.v:105304.9-105304.17" + attribute \src "libresoc.v:106887.9-106887.17" case 1'1 case end @@ -164386,14 +166527,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:105352.3-105400.6" - process $proc$libresoc.v:105352$4143 + attribute \src "libresoc.v:106935.3-106983.6" + process $proc$libresoc.v:106935$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:105353.5-105353.29" + attribute \src "libresoc.v:106936.5-106936.29" switch \initial - attribute \src "libresoc.v:105353.9-105353.17" + attribute \src "libresoc.v:106936.9-106936.17" case 1'1 case end @@ -164461,14 +166602,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:105401.3-105449.6" - process $proc$libresoc.v:105401$4144 + attribute \src "libresoc.v:106984.3-107032.6" + process $proc$libresoc.v:106984$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:105402.5-105402.29" + attribute \src "libresoc.v:106985.5-106985.29" switch \initial - attribute \src "libresoc.v:105402.9-105402.17" + attribute \src "libresoc.v:106985.9-106985.17" case 1'1 case end @@ -164536,14 +166677,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:105450.3-105498.6" - process $proc$libresoc.v:105450$4145 + attribute \src "libresoc.v:107033.3-107081.6" + process $proc$libresoc.v:107033$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:105451.5-105451.29" + attribute \src "libresoc.v:107034.5-107034.29" switch \initial - attribute \src "libresoc.v:105451.9-105451.17" + attribute \src "libresoc.v:107034.9-107034.17" case 1'1 case end @@ -164611,14 +166752,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:105499.3-105547.6" - process $proc$libresoc.v:105499$4146 + attribute \src "libresoc.v:107082.3-107130.6" + process $proc$libresoc.v:107082$4179 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:105500.5-105500.29" + attribute \src "libresoc.v:107083.5-107083.29" switch \initial - attribute \src "libresoc.v:105500.9-105500.17" + attribute \src "libresoc.v:107083.9-107083.17" case 1'1 case end @@ -164686,14 +166827,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:105548.3-105596.6" - process $proc$libresoc.v:105548$4147 + attribute \src "libresoc.v:107131.3-107179.6" + process $proc$libresoc.v:107131$4180 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:105549.5-105549.29" + attribute \src "libresoc.v:107132.5-107132.29" switch \initial - attribute \src "libresoc.v:105549.9-105549.17" + attribute \src "libresoc.v:107132.9-107132.17" case 1'1 case end @@ -164761,14 +166902,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:105597.3-105645.6" - process $proc$libresoc.v:105597$4148 + attribute \src "libresoc.v:107180.3-107228.6" + process $proc$libresoc.v:107180$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:105598.5-105598.29" + attribute \src "libresoc.v:107181.5-107181.29" switch \initial - attribute \src "libresoc.v:105598.9-105598.17" + attribute \src "libresoc.v:107181.9-107181.17" case 1'1 case end @@ -164836,14 +166977,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:105646.3-105694.6" - process $proc$libresoc.v:105646$4149 + attribute \src "libresoc.v:107229.3-107277.6" + process $proc$libresoc.v:107229$4182 assign { } { } assign { } { } assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:105647.5-105647.29" + attribute \src "libresoc.v:107230.5-107230.29" switch \initial - attribute \src "libresoc.v:105647.9-105647.17" + attribute \src "libresoc.v:107230.9-107230.17" case 1'1 case end @@ -164911,14 +167052,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:105695.3-105743.6" - process $proc$libresoc.v:105695$4150 + attribute \src "libresoc.v:107278.3-107326.6" + process $proc$libresoc.v:107278$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:105696.5-105696.29" + attribute \src "libresoc.v:107279.5-107279.29" switch \initial - attribute \src "libresoc.v:105696.9-105696.17" + attribute \src "libresoc.v:107279.9-107279.17" case 1'1 case end @@ -164986,14 +167127,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:105744.3-105792.6" - process $proc$libresoc.v:105744$4151 + attribute \src "libresoc.v:107327.3-107375.6" + process $proc$libresoc.v:107327$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:105745.5-105745.29" + attribute \src "libresoc.v:107328.5-107328.29" switch \initial - attribute \src "libresoc.v:105745.9-105745.17" + attribute \src "libresoc.v:107328.9-107328.17" case 1'1 case end @@ -165061,14 +167202,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:105793.3-105841.6" - process $proc$libresoc.v:105793$4152 + attribute \src "libresoc.v:107376.3-107424.6" + process $proc$libresoc.v:107376$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:105794.5-105794.29" + attribute \src "libresoc.v:107377.5-107377.29" switch \initial - attribute \src "libresoc.v:105794.9-105794.17" + attribute \src "libresoc.v:107377.9-107377.17" case 1'1 case end @@ -165136,14 +167277,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:105842.3-105890.6" - process $proc$libresoc.v:105842$4153 + attribute \src "libresoc.v:107425.3-107473.6" + process $proc$libresoc.v:107425$4186 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:105843.5-105843.29" + attribute \src "libresoc.v:107426.5-107426.29" switch \initial - attribute \src "libresoc.v:105843.9-105843.17" + attribute \src "libresoc.v:107426.9-107426.17" case 1'1 case end @@ -165211,14 +167352,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] end - attribute \src "libresoc.v:105891.3-105939.6" - process $proc$libresoc.v:105891$4154 + attribute \src "libresoc.v:107474.3-107522.6" + process $proc$libresoc.v:107474$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:105892.5-105892.29" + attribute \src "libresoc.v:107475.5-107475.29" switch \initial - attribute \src "libresoc.v:105892.9-105892.17" + attribute \src "libresoc.v:107475.9-107475.17" case 1'1 case end @@ -165286,14 +167427,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] end - attribute \src "libresoc.v:105940.3-105988.6" - process $proc$libresoc.v:105940$4155 + attribute \src "libresoc.v:107523.3-107571.6" + process $proc$libresoc.v:107523$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:105941.5-105941.29" + attribute \src "libresoc.v:107524.5-107524.29" switch \initial - attribute \src "libresoc.v:105941.9-105941.17" + attribute \src "libresoc.v:107524.9-107524.17" case 1'1 case end @@ -165361,14 +167502,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:105989.3-106037.6" - process $proc$libresoc.v:105989$4156 + attribute \src "libresoc.v:107572.3-107620.6" + process $proc$libresoc.v:107572$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:105990.5-105990.29" + attribute \src "libresoc.v:107573.5-107573.29" switch \initial - attribute \src "libresoc.v:105990.9-105990.17" + attribute \src "libresoc.v:107573.9-107573.17" case 1'1 case end @@ -165436,14 +167577,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:106038.3-106086.6" - process $proc$libresoc.v:106038$4157 + attribute \src "libresoc.v:107621.3-107669.6" + process $proc$libresoc.v:107621$4190 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:106039.5-106039.29" + attribute \src "libresoc.v:107622.5-107622.29" switch \initial - attribute \src "libresoc.v:106039.9-106039.17" + attribute \src "libresoc.v:107622.9-107622.17" case 1'1 case end @@ -165511,14 +167652,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:106087.3-106135.6" - process $proc$libresoc.v:106087$4158 + attribute \src "libresoc.v:107670.3-107718.6" + process $proc$libresoc.v:107670$4191 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:106088.5-106088.29" + assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] + attribute \src "libresoc.v:107671.5-107671.29" switch \initial - attribute \src "libresoc.v:106088.9-106088.17" + attribute \src "libresoc.v:107671.9-107671.17" case 1'1 case end @@ -165527,201 +167668,201 @@ module \dec31_dec_sub23 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:106141.1-107086.10" +attribute \src "libresoc.v:107724.1-108672.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 - attribute \src "libresoc.v:106971.3-106989.6" + attribute \src "libresoc.v:108557.3-108575.6" wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:106990.3-107008.6" + attribute \src "libresoc.v:108576.3-108594.6" wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:106743.3-106761.6" + attribute \src "libresoc.v:108329.3-108347.6" wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:106819.3-106837.6" + attribute \src "libresoc.v:108405.3-108423.6" wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:106496.3-106514.6" + attribute \src "libresoc.v:108082.3-108100.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:106515.3-106533.6" + attribute \src "libresoc.v:108101.3-108119.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:106724.3-106742.6" + attribute \src "libresoc.v:108310.3-108328.6" wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:106800.3-106818.6" + attribute \src "libresoc.v:108386.3-108404.6" wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:106895.3-106913.6" + attribute \src "libresoc.v:108481.3-108499.6" wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:106477.3-106495.6" - wire width 13 $0\dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:107009.3-107027.6" + attribute \src "libresoc.v:108063.3-108081.6" + wire width 14 $0\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:108595.3-108613.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:107028.3-107046.6" + attribute \src "libresoc.v:108614.3-108632.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:107047.3-107065.6" + attribute \src "libresoc.v:108633.3-108651.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:106686.3-106704.6" + attribute \src "libresoc.v:108272.3-108290.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:106762.3-106780.6" + attribute \src "libresoc.v:108348.3-108366.6" wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:106781.3-106799.6" + attribute \src "libresoc.v:108367.3-108385.6" wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:106876.3-106894.6" + attribute \src "libresoc.v:108462.3-108480.6" wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:106648.3-106666.6" + attribute \src "libresoc.v:108234.3-108252.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:106933.3-106951.6" + attribute \src "libresoc.v:108519.3-108537.6" wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:107066.3-107084.6" - wire width 2 $0\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:106705.3-106723.6" + attribute \src "libresoc.v:108652.3-108670.6" + wire width 3 $0\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:108291.3-108309.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:106857.3-106875.6" + attribute \src "libresoc.v:108443.3-108461.6" wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:106952.3-106970.6" + attribute \src "libresoc.v:108538.3-108556.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:106914.3-106932.6" + attribute \src "libresoc.v:108500.3-108518.6" wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:106838.3-106856.6" + attribute \src "libresoc.v:108424.3-108442.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:106610.3-106628.6" + attribute \src "libresoc.v:108196.3-108214.6" wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:106629.3-106647.6" + attribute \src "libresoc.v:108215.3-108233.6" wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:106534.3-106552.6" + attribute \src "libresoc.v:108120.3-108138.6" wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:106553.3-106571.6" + attribute \src "libresoc.v:108139.3-108157.6" wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:106572.3-106590.6" + attribute \src "libresoc.v:108158.3-108176.6" wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:106591.3-106609.6" + attribute \src "libresoc.v:108177.3-108195.6" wire width 3 $0\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:106667.3-106685.6" + attribute \src "libresoc.v:108253.3-108271.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:106142.7-106142.20" + attribute \src "libresoc.v:107725.7-107725.20" wire $0\initial[0:0] - attribute \src "libresoc.v:106971.3-106989.6" + attribute \src "libresoc.v:108557.3-108575.6" wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:106990.3-107008.6" + attribute \src "libresoc.v:108576.3-108594.6" wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:106743.3-106761.6" + attribute \src "libresoc.v:108329.3-108347.6" wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:106819.3-106837.6" + attribute \src "libresoc.v:108405.3-108423.6" wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:106496.3-106514.6" + attribute \src "libresoc.v:108082.3-108100.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:106515.3-106533.6" + attribute \src "libresoc.v:108101.3-108119.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:106724.3-106742.6" + attribute \src "libresoc.v:108310.3-108328.6" wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:106800.3-106818.6" + attribute \src "libresoc.v:108386.3-108404.6" wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:106895.3-106913.6" + attribute \src "libresoc.v:108481.3-108499.6" wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:106477.3-106495.6" - wire width 13 $1\dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:107009.3-107027.6" + attribute \src "libresoc.v:108063.3-108081.6" + wire width 14 $1\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:108595.3-108613.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:107028.3-107046.6" + attribute \src "libresoc.v:108614.3-108632.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:107047.3-107065.6" + attribute \src "libresoc.v:108633.3-108651.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:106686.3-106704.6" + attribute \src "libresoc.v:108272.3-108290.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:106762.3-106780.6" + attribute \src "libresoc.v:108348.3-108366.6" wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:106781.3-106799.6" + attribute \src "libresoc.v:108367.3-108385.6" wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:106876.3-106894.6" + attribute \src "libresoc.v:108462.3-108480.6" wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:106648.3-106666.6" + attribute \src "libresoc.v:108234.3-108252.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:106933.3-106951.6" + attribute \src "libresoc.v:108519.3-108537.6" wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:107066.3-107084.6" - wire width 2 $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:106705.3-106723.6" + attribute \src "libresoc.v:108652.3-108670.6" + wire width 3 $1\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:108291.3-108309.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:106857.3-106875.6" + attribute \src "libresoc.v:108443.3-108461.6" wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:106952.3-106970.6" + attribute \src "libresoc.v:108538.3-108556.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:106914.3-106932.6" + attribute \src "libresoc.v:108500.3-108518.6" wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:106838.3-106856.6" + attribute \src "libresoc.v:108424.3-108442.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:106610.3-106628.6" + attribute \src "libresoc.v:108196.3-108214.6" wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:106629.3-106647.6" + attribute \src "libresoc.v:108215.3-108233.6" wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:106534.3-106552.6" + attribute \src "libresoc.v:108120.3-108138.6" wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:106553.3-106571.6" + attribute \src "libresoc.v:108139.3-108157.6" wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:106572.3-106590.6" + attribute \src "libresoc.v:108158.3-108176.6" wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:106591.3-106609.6" + attribute \src "libresoc.v:108177.3-108195.6" wire width 3 $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:106667.3-106685.6" + attribute \src "libresoc.v:108253.3-108271.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -165801,21 +167942,22 @@ module \dec31_dec_sub24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub24_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub24_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -165921,6 +168063,7 @@ module \dec31_dec_sub24 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub24_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -165940,12 +168083,13 @@ module \dec31_dec_sub24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub24_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub24_out_sel + wire width 3 output 10 \dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -166021,28 +168165,28 @@ module \dec31_dec_sub24 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub24_upd - attribute \src "libresoc.v:106142.7-106142.15" + attribute \src "libresoc.v:107725.7-107725.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:106142.7-106142.20" - process $proc$libresoc.v:106142$4192 + attribute \src "libresoc.v:107725.7-107725.20" + process $proc$libresoc.v:107725$4225 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:106477.3-106495.6" - process $proc$libresoc.v:106477$4160 + attribute \src "libresoc.v:108063.3-108081.6" + process $proc$libresoc.v:108063$4193 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_function_unit[12:0] $1\dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:106478.5-106478.29" + assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] + attribute \src "libresoc.v:108064.5-108064.29" switch \initial - attribute \src "libresoc.v:106478.9-106478.17" + attribute \src "libresoc.v:108064.9-108064.17" case 1'1 case end @@ -166051,33 +168195,33 @@ module \dec31_dec_sub24 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 case - assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[12:0] + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:106496.3-106514.6" - process $proc$libresoc.v:106496$4161 + attribute \src "libresoc.v:108082.3-108100.6" + process $proc$libresoc.v:108082$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:106497.5-106497.29" + attribute \src "libresoc.v:108083.5-108083.29" switch \initial - attribute \src "libresoc.v:106497.9-106497.17" + attribute \src "libresoc.v:108083.9-108083.17" case 1'1 case end @@ -166105,14 +168249,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:106515.3-106533.6" - process $proc$libresoc.v:106515$4162 + attribute \src "libresoc.v:108101.3-108119.6" + process $proc$libresoc.v:108101$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:106516.5-106516.29" + attribute \src "libresoc.v:108102.5-108102.29" switch \initial - attribute \src "libresoc.v:106516.9-106516.17" + attribute \src "libresoc.v:108102.9-108102.17" case 1'1 case end @@ -166140,14 +168284,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:106534.3-106552.6" - process $proc$libresoc.v:106534$4163 + attribute \src "libresoc.v:108120.3-108138.6" + process $proc$libresoc.v:108120$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:106535.5-106535.29" + attribute \src "libresoc.v:108121.5-108121.29" switch \initial - attribute \src "libresoc.v:106535.9-106535.17" + attribute \src "libresoc.v:108121.9-108121.17" case 1'1 case end @@ -166175,14 +168319,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end - attribute \src "libresoc.v:106553.3-106571.6" - process $proc$libresoc.v:106553$4164 + attribute \src "libresoc.v:108139.3-108157.6" + process $proc$libresoc.v:108139$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:106554.5-106554.29" + attribute \src "libresoc.v:108140.5-108140.29" switch \initial - attribute \src "libresoc.v:106554.9-106554.17" + attribute \src "libresoc.v:108140.9-108140.17" case 1'1 case end @@ -166210,14 +168354,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end - attribute \src "libresoc.v:106572.3-106590.6" - process $proc$libresoc.v:106572$4165 + attribute \src "libresoc.v:108158.3-108176.6" + process $proc$libresoc.v:108158$4198 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:106573.5-106573.29" + attribute \src "libresoc.v:108159.5-108159.29" switch \initial - attribute \src "libresoc.v:106573.9-106573.17" + attribute \src "libresoc.v:108159.9-108159.17" case 1'1 case end @@ -166245,14 +168389,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end - attribute \src "libresoc.v:106591.3-106609.6" - process $proc$libresoc.v:106591$4166 + attribute \src "libresoc.v:108177.3-108195.6" + process $proc$libresoc.v:108177$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:106592.5-106592.29" + attribute \src "libresoc.v:108178.5-108178.29" switch \initial - attribute \src "libresoc.v:106592.9-106592.17" + attribute \src "libresoc.v:108178.9-108178.17" case 1'1 case end @@ -166280,14 +168424,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end - attribute \src "libresoc.v:106610.3-106628.6" - process $proc$libresoc.v:106610$4167 + attribute \src "libresoc.v:108196.3-108214.6" + process $proc$libresoc.v:108196$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:106611.5-106611.29" + attribute \src "libresoc.v:108197.5-108197.29" switch \initial - attribute \src "libresoc.v:106611.9-106611.17" + attribute \src "libresoc.v:108197.9-108197.17" case 1'1 case end @@ -166315,14 +168459,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end - attribute \src "libresoc.v:106629.3-106647.6" - process $proc$libresoc.v:106629$4168 + attribute \src "libresoc.v:108215.3-108233.6" + process $proc$libresoc.v:108215$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:106630.5-106630.29" + attribute \src "libresoc.v:108216.5-108216.29" switch \initial - attribute \src "libresoc.v:106630.9-106630.17" + attribute \src "libresoc.v:108216.9-108216.17" case 1'1 case end @@ -166350,14 +168494,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end - attribute \src "libresoc.v:106648.3-106666.6" - process $proc$libresoc.v:106648$4169 + attribute \src "libresoc.v:108234.3-108252.6" + process $proc$libresoc.v:108234$4202 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:106649.5-106649.29" + attribute \src "libresoc.v:108235.5-108235.29" switch \initial - attribute \src "libresoc.v:106649.9-106649.17" + attribute \src "libresoc.v:108235.9-108235.17" case 1'1 case end @@ -166385,14 +168529,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:106667.3-106685.6" - process $proc$libresoc.v:106667$4170 + attribute \src "libresoc.v:108253.3-108271.6" + process $proc$libresoc.v:108253$4203 assign { } { } assign { } { } assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:106668.5-106668.29" + attribute \src "libresoc.v:108254.5-108254.29" switch \initial - attribute \src "libresoc.v:106668.9-106668.17" + attribute \src "libresoc.v:108254.9-108254.17" case 1'1 case end @@ -166420,14 +168564,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:106686.3-106704.6" - process $proc$libresoc.v:106686$4171 + attribute \src "libresoc.v:108272.3-108290.6" + process $proc$libresoc.v:108272$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:106687.5-106687.29" + attribute \src "libresoc.v:108273.5-108273.29" switch \initial - attribute \src "libresoc.v:106687.9-106687.17" + attribute \src "libresoc.v:108273.9-108273.17" case 1'1 case end @@ -166455,14 +168599,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:106705.3-106723.6" - process $proc$libresoc.v:106705$4172 + attribute \src "libresoc.v:108291.3-108309.6" + process $proc$libresoc.v:108291$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:106706.5-106706.29" + attribute \src "libresoc.v:108292.5-108292.29" switch \initial - attribute \src "libresoc.v:106706.9-106706.17" + attribute \src "libresoc.v:108292.9-108292.17" case 1'1 case end @@ -166490,14 +168634,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:106724.3-106742.6" - process $proc$libresoc.v:106724$4173 + attribute \src "libresoc.v:108310.3-108328.6" + process $proc$libresoc.v:108310$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:106725.5-106725.29" + attribute \src "libresoc.v:108311.5-108311.29" switch \initial - attribute \src "libresoc.v:106725.9-106725.17" + attribute \src "libresoc.v:108311.9-108311.17" case 1'1 case end @@ -166525,14 +168669,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:106743.3-106761.6" - process $proc$libresoc.v:106743$4174 + attribute \src "libresoc.v:108329.3-108347.6" + process $proc$libresoc.v:108329$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:106744.5-106744.29" + attribute \src "libresoc.v:108330.5-108330.29" switch \initial - attribute \src "libresoc.v:106744.9-106744.17" + attribute \src "libresoc.v:108330.9-108330.17" case 1'1 case end @@ -166560,14 +168704,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:106762.3-106780.6" - process $proc$libresoc.v:106762$4175 + attribute \src "libresoc.v:108348.3-108366.6" + process $proc$libresoc.v:108348$4208 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:106763.5-106763.29" + attribute \src "libresoc.v:108349.5-108349.29" switch \initial - attribute \src "libresoc.v:106763.9-106763.17" + attribute \src "libresoc.v:108349.9-108349.17" case 1'1 case end @@ -166595,14 +168739,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:106781.3-106799.6" - process $proc$libresoc.v:106781$4176 + attribute \src "libresoc.v:108367.3-108385.6" + process $proc$libresoc.v:108367$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:106782.5-106782.29" + attribute \src "libresoc.v:108368.5-108368.29" switch \initial - attribute \src "libresoc.v:106782.9-106782.17" + attribute \src "libresoc.v:108368.9-108368.17" case 1'1 case end @@ -166630,14 +168774,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:106800.3-106818.6" - process $proc$libresoc.v:106800$4177 + attribute \src "libresoc.v:108386.3-108404.6" + process $proc$libresoc.v:108386$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:106801.5-106801.29" + attribute \src "libresoc.v:108387.5-108387.29" switch \initial - attribute \src "libresoc.v:106801.9-106801.17" + attribute \src "libresoc.v:108387.9-108387.17" case 1'1 case end @@ -166665,14 +168809,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:106819.3-106837.6" - process $proc$libresoc.v:106819$4178 + attribute \src "libresoc.v:108405.3-108423.6" + process $proc$libresoc.v:108405$4211 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:106820.5-106820.29" + attribute \src "libresoc.v:108406.5-108406.29" switch \initial - attribute \src "libresoc.v:106820.9-106820.17" + attribute \src "libresoc.v:108406.9-108406.17" case 1'1 case end @@ -166700,14 +168844,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:106838.3-106856.6" - process $proc$libresoc.v:106838$4179 + attribute \src "libresoc.v:108424.3-108442.6" + process $proc$libresoc.v:108424$4212 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:106839.5-106839.29" + attribute \src "libresoc.v:108425.5-108425.29" switch \initial - attribute \src "libresoc.v:106839.9-106839.17" + attribute \src "libresoc.v:108425.9-108425.17" case 1'1 case end @@ -166735,14 +168879,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:106857.3-106875.6" - process $proc$libresoc.v:106857$4180 + attribute \src "libresoc.v:108443.3-108461.6" + process $proc$libresoc.v:108443$4213 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:106858.5-106858.29" + attribute \src "libresoc.v:108444.5-108444.29" switch \initial - attribute \src "libresoc.v:106858.9-106858.17" + attribute \src "libresoc.v:108444.9-108444.17" case 1'1 case end @@ -166770,14 +168914,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:106876.3-106894.6" - process $proc$libresoc.v:106876$4181 + attribute \src "libresoc.v:108462.3-108480.6" + process $proc$libresoc.v:108462$4214 assign { } { } assign { } { } assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:106877.5-106877.29" + attribute \src "libresoc.v:108463.5-108463.29" switch \initial - attribute \src "libresoc.v:106877.9-106877.17" + attribute \src "libresoc.v:108463.9-108463.17" case 1'1 case end @@ -166805,14 +168949,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:106895.3-106913.6" - process $proc$libresoc.v:106895$4182 + attribute \src "libresoc.v:108481.3-108499.6" + process $proc$libresoc.v:108481$4215 assign { } { } assign { } { } assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:106896.5-106896.29" + attribute \src "libresoc.v:108482.5-108482.29" switch \initial - attribute \src "libresoc.v:106896.9-106896.17" + attribute \src "libresoc.v:108482.9-108482.17" case 1'1 case end @@ -166840,14 +168984,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:106914.3-106932.6" - process $proc$libresoc.v:106914$4183 + attribute \src "libresoc.v:108500.3-108518.6" + process $proc$libresoc.v:108500$4216 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:106915.5-106915.29" + attribute \src "libresoc.v:108501.5-108501.29" switch \initial - attribute \src "libresoc.v:106915.9-106915.17" + attribute \src "libresoc.v:108501.9-108501.17" case 1'1 case end @@ -166875,14 +169019,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:106933.3-106951.6" - process $proc$libresoc.v:106933$4184 + attribute \src "libresoc.v:108519.3-108537.6" + process $proc$libresoc.v:108519$4217 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:106934.5-106934.29" + attribute \src "libresoc.v:108520.5-108520.29" switch \initial - attribute \src "libresoc.v:106934.9-106934.17" + attribute \src "libresoc.v:108520.9-108520.17" case 1'1 case end @@ -166910,14 +169054,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "libresoc.v:106952.3-106970.6" - process $proc$libresoc.v:106952$4185 + attribute \src "libresoc.v:108538.3-108556.6" + process $proc$libresoc.v:108538$4218 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:106953.5-106953.29" + attribute \src "libresoc.v:108539.5-108539.29" switch \initial - attribute \src "libresoc.v:106953.9-106953.17" + attribute \src "libresoc.v:108539.9-108539.17" case 1'1 case end @@ -166945,14 +169089,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:106971.3-106989.6" - process $proc$libresoc.v:106971$4186 + attribute \src "libresoc.v:108557.3-108575.6" + process $proc$libresoc.v:108557$4219 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:106972.5-106972.29" + attribute \src "libresoc.v:108558.5-108558.29" switch \initial - attribute \src "libresoc.v:106972.9-106972.17" + attribute \src "libresoc.v:108558.9-108558.17" case 1'1 case end @@ -166980,14 +169124,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] end - attribute \src "libresoc.v:106990.3-107008.6" - process $proc$libresoc.v:106990$4187 + attribute \src "libresoc.v:108576.3-108594.6" + process $proc$libresoc.v:108576$4220 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:106991.5-106991.29" + attribute \src "libresoc.v:108577.5-108577.29" switch \initial - attribute \src "libresoc.v:106991.9-106991.17" + attribute \src "libresoc.v:108577.9-108577.17" case 1'1 case end @@ -167015,14 +169159,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end - attribute \src "libresoc.v:107009.3-107027.6" - process $proc$libresoc.v:107009$4188 + attribute \src "libresoc.v:108595.3-108613.6" + process $proc$libresoc.v:108595$4221 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:107010.5-107010.29" + attribute \src "libresoc.v:108596.5-108596.29" switch \initial - attribute \src "libresoc.v:107010.9-107010.17" + attribute \src "libresoc.v:108596.9-108596.17" case 1'1 case end @@ -167050,14 +169194,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "libresoc.v:107028.3-107046.6" - process $proc$libresoc.v:107028$4189 + attribute \src "libresoc.v:108614.3-108632.6" + process $proc$libresoc.v:108614$4222 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:107029.5-107029.29" + attribute \src "libresoc.v:108615.5-108615.29" switch \initial - attribute \src "libresoc.v:107029.9-107029.17" + attribute \src "libresoc.v:108615.9-108615.17" case 1'1 case end @@ -167085,14 +169229,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:107047.3-107065.6" - process $proc$libresoc.v:107047$4190 + attribute \src "libresoc.v:108633.3-108651.6" + process $proc$libresoc.v:108633$4223 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:107048.5-107048.29" + attribute \src "libresoc.v:108634.5-108634.29" switch \initial - attribute \src "libresoc.v:107048.9-107048.17" + attribute \src "libresoc.v:108634.9-108634.17" case 1'1 case end @@ -167120,14 +169264,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:107066.3-107084.6" - process $proc$libresoc.v:107066$4191 + attribute \src "libresoc.v:108652.3-108670.6" + process $proc$libresoc.v:108652$4224 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:107067.5-107067.29" + assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] + attribute \src "libresoc.v:108653.5-108653.29" switch \initial - attribute \src "libresoc.v:107067.9-107067.17" + attribute \src "libresoc.v:108653.9-108653.17" case 1'1 case end @@ -167136,161 +169280,161 @@ module \dec31_dec_sub24 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 case - assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub24_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:107090.1-109091.10" +attribute \src "libresoc.v:108676.1-110680.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 - attribute \src "libresoc.v:108778.3-108829.6" + attribute \src "libresoc.v:110367.3-110418.6" wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:108830.3-108881.6" + attribute \src "libresoc.v:110419.3-110470.6" wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:108154.3-108205.6" + attribute \src "libresoc.v:109743.3-109794.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:108362.3-108413.6" + attribute \src "libresoc.v:109951.3-110002.6" wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:107478.3-107529.6" + attribute \src "libresoc.v:109067.3-109118.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:107530.3-107581.6" + attribute \src "libresoc.v:109119.3-109170.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:108102.3-108153.6" + attribute \src "libresoc.v:109691.3-109742.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:108310.3-108361.6" + attribute \src "libresoc.v:109899.3-109950.6" wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:108570.3-108621.6" + attribute \src "libresoc.v:110159.3-110210.6" wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:107426.3-107477.6" - wire width 13 $0\dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:108882.3-108933.6" + attribute \src "libresoc.v:109015.3-109066.6" + wire width 14 $0\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:110471.3-110522.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:108934.3-108985.6" + attribute \src "libresoc.v:110523.3-110574.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:108986.3-109037.6" + attribute \src "libresoc.v:110575.3-110626.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:107998.3-108049.6" + attribute \src "libresoc.v:109587.3-109638.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:108206.3-108257.6" + attribute \src "libresoc.v:109795.3-109846.6" wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:108258.3-108309.6" + attribute \src "libresoc.v:109847.3-109898.6" wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:108518.3-108569.6" + attribute \src "libresoc.v:110107.3-110158.6" wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:107894.3-107945.6" + attribute \src "libresoc.v:109483.3-109534.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:108674.3-108725.6" + attribute \src "libresoc.v:110263.3-110314.6" wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:109038.3-109089.6" - wire width 2 $0\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:108050.3-108101.6" + attribute \src "libresoc.v:110627.3-110678.6" + wire width 3 $0\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:109639.3-109690.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:108466.3-108517.6" + attribute \src "libresoc.v:110055.3-110106.6" wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:108726.3-108777.6" + attribute \src "libresoc.v:110315.3-110366.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:108622.3-108673.6" + attribute \src "libresoc.v:110211.3-110262.6" wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:108414.3-108465.6" + attribute \src "libresoc.v:110003.3-110054.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:107790.3-107841.6" + attribute \src "libresoc.v:109379.3-109430.6" wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:107842.3-107893.6" + attribute \src "libresoc.v:109431.3-109482.6" wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:107582.3-107633.6" + attribute \src "libresoc.v:109171.3-109222.6" wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:107634.3-107685.6" + attribute \src "libresoc.v:109223.3-109274.6" wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:107686.3-107737.6" + attribute \src "libresoc.v:109275.3-109326.6" wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:107738.3-107789.6" + attribute \src "libresoc.v:109327.3-109378.6" wire width 3 $0\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:107946.3-107997.6" + attribute \src "libresoc.v:109535.3-109586.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:107091.7-107091.20" + attribute \src "libresoc.v:108677.7-108677.20" wire $0\initial[0:0] - attribute \src "libresoc.v:108778.3-108829.6" + attribute \src "libresoc.v:110367.3-110418.6" wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:108830.3-108881.6" + attribute \src "libresoc.v:110419.3-110470.6" wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:108154.3-108205.6" + attribute \src "libresoc.v:109743.3-109794.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:108362.3-108413.6" + attribute \src "libresoc.v:109951.3-110002.6" wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:107478.3-107529.6" + attribute \src "libresoc.v:109067.3-109118.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:107530.3-107581.6" + attribute \src "libresoc.v:109119.3-109170.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:108102.3-108153.6" + attribute \src "libresoc.v:109691.3-109742.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:108310.3-108361.6" + attribute \src "libresoc.v:109899.3-109950.6" wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:108570.3-108621.6" + attribute \src "libresoc.v:110159.3-110210.6" wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:107426.3-107477.6" - wire width 13 $1\dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:108882.3-108933.6" + attribute \src "libresoc.v:109015.3-109066.6" + wire width 14 $1\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:110471.3-110522.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:108934.3-108985.6" + attribute \src "libresoc.v:110523.3-110574.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:108986.3-109037.6" + attribute \src "libresoc.v:110575.3-110626.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:107998.3-108049.6" + attribute \src "libresoc.v:109587.3-109638.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:108206.3-108257.6" + attribute \src "libresoc.v:109795.3-109846.6" wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:108258.3-108309.6" + attribute \src "libresoc.v:109847.3-109898.6" wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:108518.3-108569.6" + attribute \src "libresoc.v:110107.3-110158.6" wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:107894.3-107945.6" + attribute \src "libresoc.v:109483.3-109534.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:108674.3-108725.6" + attribute \src "libresoc.v:110263.3-110314.6" wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:109038.3-109089.6" - wire width 2 $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:108050.3-108101.6" + attribute \src "libresoc.v:110627.3-110678.6" + wire width 3 $1\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:109639.3-109690.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:108466.3-108517.6" + attribute \src "libresoc.v:110055.3-110106.6" wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:108726.3-108777.6" + attribute \src "libresoc.v:110315.3-110366.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:108622.3-108673.6" + attribute \src "libresoc.v:110211.3-110262.6" wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:108414.3-108465.6" + attribute \src "libresoc.v:110003.3-110054.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:107790.3-107841.6" + attribute \src "libresoc.v:109379.3-109430.6" wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:107842.3-107893.6" + attribute \src "libresoc.v:109431.3-109482.6" wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:107582.3-107633.6" + attribute \src "libresoc.v:109171.3-109222.6" wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:107634.3-107685.6" + attribute \src "libresoc.v:109223.3-109274.6" wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:107686.3-107737.6" + attribute \src "libresoc.v:109275.3-109326.6" wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:107738.3-107789.6" + attribute \src "libresoc.v:109327.3-109378.6" wire width 3 $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:107946.3-107997.6" + attribute \src "libresoc.v:109535.3-109586.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -167370,21 +169514,22 @@ module \dec31_dec_sub26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub26_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub26_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -167490,6 +169635,7 @@ module \dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -167509,12 +169655,13 @@ module \dec31_dec_sub26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub26_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub26_out_sel + wire width 3 output 10 \dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -167590,28 +169737,28 @@ module \dec31_dec_sub26 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub26_upd - attribute \src "libresoc.v:107091.7-107091.15" + attribute \src "libresoc.v:108677.7-108677.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:107091.7-107091.20" - process $proc$libresoc.v:107091$4225 + attribute \src "libresoc.v:108677.7-108677.20" + process $proc$libresoc.v:108677$4258 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:107426.3-107477.6" - process $proc$libresoc.v:107426$4193 + attribute \src "libresoc.v:109015.3-109066.6" + process $proc$libresoc.v:109015$4226 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_function_unit[12:0] $1\dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:107427.5-107427.29" + assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] + attribute \src "libresoc.v:109016.5-109016.29" switch \initial - attribute \src "libresoc.v:107427.9-107427.17" + attribute \src "libresoc.v:109016.9-109016.17" case 1'1 case end @@ -167620,77 +169767,77 @@ module \dec31_dec_sub26 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 case - assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[12:0] + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:107478.3-107529.6" - process $proc$libresoc.v:107478$4194 + attribute \src "libresoc.v:109067.3-109118.6" + process $proc$libresoc.v:109067$4227 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:107479.5-107479.29" + attribute \src "libresoc.v:109068.5-109068.29" switch \initial - attribute \src "libresoc.v:107479.9-107479.17" + attribute \src "libresoc.v:109068.9-109068.17" case 1'1 case end @@ -167762,14 +169909,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:107530.3-107581.6" - process $proc$libresoc.v:107530$4195 + attribute \src "libresoc.v:109119.3-109170.6" + process $proc$libresoc.v:109119$4228 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:107531.5-107531.29" + attribute \src "libresoc.v:109120.5-109120.29" switch \initial - attribute \src "libresoc.v:107531.9-107531.17" + attribute \src "libresoc.v:109120.9-109120.17" case 1'1 case end @@ -167841,14 +169988,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:107582.3-107633.6" - process $proc$libresoc.v:107582$4196 + attribute \src "libresoc.v:109171.3-109222.6" + process $proc$libresoc.v:109171$4229 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:107583.5-107583.29" + attribute \src "libresoc.v:109172.5-109172.29" switch \initial - attribute \src "libresoc.v:107583.9-107583.17" + attribute \src "libresoc.v:109172.9-109172.17" case 1'1 case end @@ -167920,14 +170067,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end - attribute \src "libresoc.v:107634.3-107685.6" - process $proc$libresoc.v:107634$4197 + attribute \src "libresoc.v:109223.3-109274.6" + process $proc$libresoc.v:109223$4230 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:107635.5-107635.29" + attribute \src "libresoc.v:109224.5-109224.29" switch \initial - attribute \src "libresoc.v:107635.9-107635.17" + attribute \src "libresoc.v:109224.9-109224.17" case 1'1 case end @@ -167999,14 +170146,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end - attribute \src "libresoc.v:107686.3-107737.6" - process $proc$libresoc.v:107686$4198 + attribute \src "libresoc.v:109275.3-109326.6" + process $proc$libresoc.v:109275$4231 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:107687.5-107687.29" + attribute \src "libresoc.v:109276.5-109276.29" switch \initial - attribute \src "libresoc.v:107687.9-107687.17" + attribute \src "libresoc.v:109276.9-109276.17" case 1'1 case end @@ -168078,14 +170225,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end - attribute \src "libresoc.v:107738.3-107789.6" - process $proc$libresoc.v:107738$4199 + attribute \src "libresoc.v:109327.3-109378.6" + process $proc$libresoc.v:109327$4232 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:107739.5-107739.29" + attribute \src "libresoc.v:109328.5-109328.29" switch \initial - attribute \src "libresoc.v:107739.9-107739.17" + attribute \src "libresoc.v:109328.9-109328.17" case 1'1 case end @@ -168157,14 +170304,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end - attribute \src "libresoc.v:107790.3-107841.6" - process $proc$libresoc.v:107790$4200 + attribute \src "libresoc.v:109379.3-109430.6" + process $proc$libresoc.v:109379$4233 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:107791.5-107791.29" + attribute \src "libresoc.v:109380.5-109380.29" switch \initial - attribute \src "libresoc.v:107791.9-107791.17" + attribute \src "libresoc.v:109380.9-109380.17" case 1'1 case end @@ -168236,14 +170383,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end - attribute \src "libresoc.v:107842.3-107893.6" - process $proc$libresoc.v:107842$4201 + attribute \src "libresoc.v:109431.3-109482.6" + process $proc$libresoc.v:109431$4234 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:107843.5-107843.29" + attribute \src "libresoc.v:109432.5-109432.29" switch \initial - attribute \src "libresoc.v:107843.9-107843.17" + attribute \src "libresoc.v:109432.9-109432.17" case 1'1 case end @@ -168315,14 +170462,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end - attribute \src "libresoc.v:107894.3-107945.6" - process $proc$libresoc.v:107894$4202 + attribute \src "libresoc.v:109483.3-109534.6" + process $proc$libresoc.v:109483$4235 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:107895.5-107895.29" + attribute \src "libresoc.v:109484.5-109484.29" switch \initial - attribute \src "libresoc.v:107895.9-107895.17" + attribute \src "libresoc.v:109484.9-109484.17" case 1'1 case end @@ -168394,14 +170541,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:107946.3-107997.6" - process $proc$libresoc.v:107946$4203 + attribute \src "libresoc.v:109535.3-109586.6" + process $proc$libresoc.v:109535$4236 assign { } { } assign { } { } assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:107947.5-107947.29" + attribute \src "libresoc.v:109536.5-109536.29" switch \initial - attribute \src "libresoc.v:107947.9-107947.17" + attribute \src "libresoc.v:109536.9-109536.17" case 1'1 case end @@ -168473,14 +170620,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:107998.3-108049.6" - process $proc$libresoc.v:107998$4204 + attribute \src "libresoc.v:109587.3-109638.6" + process $proc$libresoc.v:109587$4237 assign { } { } assign { } { } assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:107999.5-107999.29" + attribute \src "libresoc.v:109588.5-109588.29" switch \initial - attribute \src "libresoc.v:107999.9-107999.17" + attribute \src "libresoc.v:109588.9-109588.17" case 1'1 case end @@ -168552,14 +170699,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:108050.3-108101.6" - process $proc$libresoc.v:108050$4205 + attribute \src "libresoc.v:109639.3-109690.6" + process $proc$libresoc.v:109639$4238 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:108051.5-108051.29" + attribute \src "libresoc.v:109640.5-109640.29" switch \initial - attribute \src "libresoc.v:108051.9-108051.17" + attribute \src "libresoc.v:109640.9-109640.17" case 1'1 case end @@ -168631,14 +170778,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:108102.3-108153.6" - process $proc$libresoc.v:108102$4206 + attribute \src "libresoc.v:109691.3-109742.6" + process $proc$libresoc.v:109691$4239 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:108103.5-108103.29" + attribute \src "libresoc.v:109692.5-109692.29" switch \initial - attribute \src "libresoc.v:108103.9-108103.17" + attribute \src "libresoc.v:109692.9-109692.17" case 1'1 case end @@ -168710,14 +170857,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:108154.3-108205.6" - process $proc$libresoc.v:108154$4207 + attribute \src "libresoc.v:109743.3-109794.6" + process $proc$libresoc.v:109743$4240 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:108155.5-108155.29" + attribute \src "libresoc.v:109744.5-109744.29" switch \initial - attribute \src "libresoc.v:108155.9-108155.17" + attribute \src "libresoc.v:109744.9-109744.17" case 1'1 case end @@ -168789,14 +170936,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:108206.3-108257.6" - process $proc$libresoc.v:108206$4208 + attribute \src "libresoc.v:109795.3-109846.6" + process $proc$libresoc.v:109795$4241 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:108207.5-108207.29" + attribute \src "libresoc.v:109796.5-109796.29" switch \initial - attribute \src "libresoc.v:108207.9-108207.17" + attribute \src "libresoc.v:109796.9-109796.17" case 1'1 case end @@ -168868,14 +171015,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:108258.3-108309.6" - process $proc$libresoc.v:108258$4209 + attribute \src "libresoc.v:109847.3-109898.6" + process $proc$libresoc.v:109847$4242 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:108259.5-108259.29" + attribute \src "libresoc.v:109848.5-109848.29" switch \initial - attribute \src "libresoc.v:108259.9-108259.17" + attribute \src "libresoc.v:109848.9-109848.17" case 1'1 case end @@ -168947,14 +171094,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:108310.3-108361.6" - process $proc$libresoc.v:108310$4210 + attribute \src "libresoc.v:109899.3-109950.6" + process $proc$libresoc.v:109899$4243 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:108311.5-108311.29" + attribute \src "libresoc.v:109900.5-109900.29" switch \initial - attribute \src "libresoc.v:108311.9-108311.17" + attribute \src "libresoc.v:109900.9-109900.17" case 1'1 case end @@ -169026,14 +171173,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:108362.3-108413.6" - process $proc$libresoc.v:108362$4211 + attribute \src "libresoc.v:109951.3-110002.6" + process $proc$libresoc.v:109951$4244 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:108363.5-108363.29" + attribute \src "libresoc.v:109952.5-109952.29" switch \initial - attribute \src "libresoc.v:108363.9-108363.17" + attribute \src "libresoc.v:109952.9-109952.17" case 1'1 case end @@ -169105,14 +171252,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:108414.3-108465.6" - process $proc$libresoc.v:108414$4212 + attribute \src "libresoc.v:110003.3-110054.6" + process $proc$libresoc.v:110003$4245 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:108415.5-108415.29" + attribute \src "libresoc.v:110004.5-110004.29" switch \initial - attribute \src "libresoc.v:108415.9-108415.17" + attribute \src "libresoc.v:110004.9-110004.17" case 1'1 case end @@ -169184,14 +171331,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:108466.3-108517.6" - process $proc$libresoc.v:108466$4213 + attribute \src "libresoc.v:110055.3-110106.6" + process $proc$libresoc.v:110055$4246 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:108467.5-108467.29" + attribute \src "libresoc.v:110056.5-110056.29" switch \initial - attribute \src "libresoc.v:108467.9-108467.17" + attribute \src "libresoc.v:110056.9-110056.17" case 1'1 case end @@ -169263,14 +171410,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:108518.3-108569.6" - process $proc$libresoc.v:108518$4214 + attribute \src "libresoc.v:110107.3-110158.6" + process $proc$libresoc.v:110107$4247 assign { } { } assign { } { } assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:108519.5-108519.29" + attribute \src "libresoc.v:110108.5-110108.29" switch \initial - attribute \src "libresoc.v:108519.9-108519.17" + attribute \src "libresoc.v:110108.9-110108.17" case 1'1 case end @@ -169342,14 +171489,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:108570.3-108621.6" - process $proc$libresoc.v:108570$4215 + attribute \src "libresoc.v:110159.3-110210.6" + process $proc$libresoc.v:110159$4248 assign { } { } assign { } { } assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:108571.5-108571.29" + attribute \src "libresoc.v:110160.5-110160.29" switch \initial - attribute \src "libresoc.v:108571.9-108571.17" + attribute \src "libresoc.v:110160.9-110160.17" case 1'1 case end @@ -169421,14 +171568,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:108622.3-108673.6" - process $proc$libresoc.v:108622$4216 + attribute \src "libresoc.v:110211.3-110262.6" + process $proc$libresoc.v:110211$4249 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:108623.5-108623.29" + attribute \src "libresoc.v:110212.5-110212.29" switch \initial - attribute \src "libresoc.v:108623.9-108623.17" + attribute \src "libresoc.v:110212.9-110212.17" case 1'1 case end @@ -169500,14 +171647,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:108674.3-108725.6" - process $proc$libresoc.v:108674$4217 + attribute \src "libresoc.v:110263.3-110314.6" + process $proc$libresoc.v:110263$4250 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:108675.5-108675.29" + attribute \src "libresoc.v:110264.5-110264.29" switch \initial - attribute \src "libresoc.v:108675.9-108675.17" + attribute \src "libresoc.v:110264.9-110264.17" case 1'1 case end @@ -169579,14 +171726,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:108726.3-108777.6" - process $proc$libresoc.v:108726$4218 + attribute \src "libresoc.v:110315.3-110366.6" + process $proc$libresoc.v:110315$4251 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:108727.5-108727.29" + attribute \src "libresoc.v:110316.5-110316.29" switch \initial - attribute \src "libresoc.v:108727.9-108727.17" + attribute \src "libresoc.v:110316.9-110316.17" case 1'1 case end @@ -169658,14 +171805,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:108778.3-108829.6" - process $proc$libresoc.v:108778$4219 + attribute \src "libresoc.v:110367.3-110418.6" + process $proc$libresoc.v:110367$4252 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:108779.5-108779.29" + attribute \src "libresoc.v:110368.5-110368.29" switch \initial - attribute \src "libresoc.v:108779.9-108779.17" + attribute \src "libresoc.v:110368.9-110368.17" case 1'1 case end @@ -169737,14 +171884,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] end - attribute \src "libresoc.v:108830.3-108881.6" - process $proc$libresoc.v:108830$4220 + attribute \src "libresoc.v:110419.3-110470.6" + process $proc$libresoc.v:110419$4253 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:108831.5-108831.29" + attribute \src "libresoc.v:110420.5-110420.29" switch \initial - attribute \src "libresoc.v:108831.9-108831.17" + attribute \src "libresoc.v:110420.9-110420.17" case 1'1 case end @@ -169816,14 +171963,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] end - attribute \src "libresoc.v:108882.3-108933.6" - process $proc$libresoc.v:108882$4221 + attribute \src "libresoc.v:110471.3-110522.6" + process $proc$libresoc.v:110471$4254 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:108883.5-108883.29" + attribute \src "libresoc.v:110472.5-110472.29" switch \initial - attribute \src "libresoc.v:108883.9-108883.17" + attribute \src "libresoc.v:110472.9-110472.17" case 1'1 case end @@ -169895,14 +172042,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:108934.3-108985.6" - process $proc$libresoc.v:108934$4222 + attribute \src "libresoc.v:110523.3-110574.6" + process $proc$libresoc.v:110523$4255 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:108935.5-108935.29" + attribute \src "libresoc.v:110524.5-110524.29" switch \initial - attribute \src "libresoc.v:108935.9-108935.17" + attribute \src "libresoc.v:110524.9-110524.17" case 1'1 case end @@ -169974,14 +172121,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:108986.3-109037.6" - process $proc$libresoc.v:108986$4223 + attribute \src "libresoc.v:110575.3-110626.6" + process $proc$libresoc.v:110575$4256 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:108987.5-108987.29" + attribute \src "libresoc.v:110576.5-110576.29" switch \initial - attribute \src "libresoc.v:108987.9-108987.17" + attribute \src "libresoc.v:110576.9-110576.17" case 1'1 case end @@ -170053,14 +172200,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:109038.3-109089.6" - process $proc$libresoc.v:109038$4224 + attribute \src "libresoc.v:110627.3-110678.6" + process $proc$libresoc.v:110627$4257 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:109039.5-109039.29" + assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] + attribute \src "libresoc.v:110628.5-110628.29" switch \initial - attribute \src "libresoc.v:109039.9-109039.17" + attribute \src "libresoc.v:110628.9-110628.17" case 1'1 case end @@ -170069,205 +172216,205 @@ module \dec31_dec_sub26 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 case - assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub26_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:109095.1-110040.10" +attribute \src "libresoc.v:110684.1-111632.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 - attribute \src "libresoc.v:109925.3-109943.6" + attribute \src "libresoc.v:111517.3-111535.6" wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:109944.3-109962.6" + attribute \src "libresoc.v:111536.3-111554.6" wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:109697.3-109715.6" + attribute \src "libresoc.v:111289.3-111307.6" wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:109773.3-109791.6" + attribute \src "libresoc.v:111365.3-111383.6" wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:109450.3-109468.6" + attribute \src "libresoc.v:111042.3-111060.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:109469.3-109487.6" + attribute \src "libresoc.v:111061.3-111079.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:109678.3-109696.6" + attribute \src "libresoc.v:111270.3-111288.6" wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:109754.3-109772.6" + attribute \src "libresoc.v:111346.3-111364.6" wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:109849.3-109867.6" + attribute \src "libresoc.v:111441.3-111459.6" wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:109431.3-109449.6" - wire width 13 $0\dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:109963.3-109981.6" + attribute \src "libresoc.v:111023.3-111041.6" + wire width 14 $0\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:111555.3-111573.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:109982.3-110000.6" + attribute \src "libresoc.v:111574.3-111592.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:110001.3-110019.6" + attribute \src "libresoc.v:111593.3-111611.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:109640.3-109658.6" + attribute \src "libresoc.v:111232.3-111250.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:109716.3-109734.6" + attribute \src "libresoc.v:111308.3-111326.6" wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:109735.3-109753.6" + attribute \src "libresoc.v:111327.3-111345.6" wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:109830.3-109848.6" + attribute \src "libresoc.v:111422.3-111440.6" wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:109602.3-109620.6" + attribute \src "libresoc.v:111194.3-111212.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:109887.3-109905.6" + attribute \src "libresoc.v:111479.3-111497.6" wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:110020.3-110038.6" - wire width 2 $0\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:109659.3-109677.6" + attribute \src "libresoc.v:111612.3-111630.6" + wire width 3 $0\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:111251.3-111269.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:109811.3-109829.6" + attribute \src "libresoc.v:111403.3-111421.6" wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:109906.3-109924.6" + attribute \src "libresoc.v:111498.3-111516.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:109868.3-109886.6" + attribute \src "libresoc.v:111460.3-111478.6" wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:109792.3-109810.6" + attribute \src "libresoc.v:111384.3-111402.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:109564.3-109582.6" + attribute \src "libresoc.v:111156.3-111174.6" wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:109583.3-109601.6" + attribute \src "libresoc.v:111175.3-111193.6" wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:109488.3-109506.6" + attribute \src "libresoc.v:111080.3-111098.6" wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:109507.3-109525.6" + attribute \src "libresoc.v:111099.3-111117.6" wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:109526.3-109544.6" + attribute \src "libresoc.v:111118.3-111136.6" wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:109545.3-109563.6" + attribute \src "libresoc.v:111137.3-111155.6" wire width 3 $0\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:109621.3-109639.6" + attribute \src "libresoc.v:111213.3-111231.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:109096.7-109096.20" + attribute \src "libresoc.v:110685.7-110685.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109925.3-109943.6" + attribute \src "libresoc.v:111517.3-111535.6" wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:109944.3-109962.6" + attribute \src "libresoc.v:111536.3-111554.6" wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:109697.3-109715.6" + attribute \src "libresoc.v:111289.3-111307.6" wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:109773.3-109791.6" + attribute \src "libresoc.v:111365.3-111383.6" wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:109450.3-109468.6" + attribute \src "libresoc.v:111042.3-111060.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:109469.3-109487.6" + attribute \src "libresoc.v:111061.3-111079.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:109678.3-109696.6" + attribute \src "libresoc.v:111270.3-111288.6" wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:109754.3-109772.6" + attribute \src "libresoc.v:111346.3-111364.6" wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:109849.3-109867.6" + attribute \src "libresoc.v:111441.3-111459.6" wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:109431.3-109449.6" - wire width 13 $1\dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:109963.3-109981.6" + attribute \src "libresoc.v:111023.3-111041.6" + wire width 14 $1\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:111555.3-111573.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:109982.3-110000.6" + attribute \src "libresoc.v:111574.3-111592.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:110001.3-110019.6" + attribute \src "libresoc.v:111593.3-111611.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:109640.3-109658.6" + attribute \src "libresoc.v:111232.3-111250.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:109716.3-109734.6" + attribute \src "libresoc.v:111308.3-111326.6" wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:109735.3-109753.6" + attribute \src "libresoc.v:111327.3-111345.6" wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:109830.3-109848.6" + attribute \src "libresoc.v:111422.3-111440.6" wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:109602.3-109620.6" + attribute \src "libresoc.v:111194.3-111212.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:109887.3-109905.6" + attribute \src "libresoc.v:111479.3-111497.6" wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:110020.3-110038.6" - wire width 2 $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:109659.3-109677.6" + attribute \src "libresoc.v:111612.3-111630.6" + wire width 3 $1\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:111251.3-111269.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:109811.3-109829.6" + attribute \src "libresoc.v:111403.3-111421.6" wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:109906.3-109924.6" + attribute \src "libresoc.v:111498.3-111516.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:109868.3-109886.6" + attribute \src "libresoc.v:111460.3-111478.6" wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:109792.3-109810.6" + attribute \src "libresoc.v:111384.3-111402.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:109564.3-109582.6" + attribute \src "libresoc.v:111156.3-111174.6" wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:109583.3-109601.6" + attribute \src "libresoc.v:111175.3-111193.6" wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:109488.3-109506.6" + attribute \src "libresoc.v:111080.3-111098.6" wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:109507.3-109525.6" + attribute \src "libresoc.v:111099.3-111117.6" wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:109526.3-109544.6" + attribute \src "libresoc.v:111118.3-111136.6" wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:109545.3-109563.6" + attribute \src "libresoc.v:111137.3-111155.6" wire width 3 $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:109621.3-109639.6" + attribute \src "libresoc.v:111213.3-111231.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -170347,21 +172494,22 @@ module \dec31_dec_sub27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub27_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub27_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -170467,6 +172615,7 @@ module \dec31_dec_sub27 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub27_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -170486,12 +172635,13 @@ module \dec31_dec_sub27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub27_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub27_out_sel + wire width 3 output 10 \dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -170567,28 +172717,28 @@ module \dec31_dec_sub27 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub27_upd - attribute \src "libresoc.v:109096.7-109096.15" + attribute \src "libresoc.v:110685.7-110685.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:109096.7-109096.20" - process $proc$libresoc.v:109096$4258 + attribute \src "libresoc.v:110685.7-110685.20" + process $proc$libresoc.v:110685$4291 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109431.3-109449.6" - process $proc$libresoc.v:109431$4226 + attribute \src "libresoc.v:111023.3-111041.6" + process $proc$libresoc.v:111023$4259 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_function_unit[12:0] $1\dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:109432.5-109432.29" + assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] + attribute \src "libresoc.v:111024.5-111024.29" switch \initial - attribute \src "libresoc.v:109432.9-109432.17" + attribute \src "libresoc.v:111024.9-111024.17" case 1'1 case end @@ -170597,33 +172747,33 @@ module \dec31_dec_sub27 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 case - assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[12:0] + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:109450.3-109468.6" - process $proc$libresoc.v:109450$4227 + attribute \src "libresoc.v:111042.3-111060.6" + process $proc$libresoc.v:111042$4260 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:109451.5-109451.29" + attribute \src "libresoc.v:111043.5-111043.29" switch \initial - attribute \src "libresoc.v:109451.9-109451.17" + attribute \src "libresoc.v:111043.9-111043.17" case 1'1 case end @@ -170651,14 +172801,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:109469.3-109487.6" - process $proc$libresoc.v:109469$4228 + attribute \src "libresoc.v:111061.3-111079.6" + process $proc$libresoc.v:111061$4261 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:109470.5-109470.29" + attribute \src "libresoc.v:111062.5-111062.29" switch \initial - attribute \src "libresoc.v:109470.9-109470.17" + attribute \src "libresoc.v:111062.9-111062.17" case 1'1 case end @@ -170686,14 +172836,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:109488.3-109506.6" - process $proc$libresoc.v:109488$4229 + attribute \src "libresoc.v:111080.3-111098.6" + process $proc$libresoc.v:111080$4262 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:109489.5-109489.29" + attribute \src "libresoc.v:111081.5-111081.29" switch \initial - attribute \src "libresoc.v:109489.9-109489.17" + attribute \src "libresoc.v:111081.9-111081.17" case 1'1 case end @@ -170721,14 +172871,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end - attribute \src "libresoc.v:109507.3-109525.6" - process $proc$libresoc.v:109507$4230 + attribute \src "libresoc.v:111099.3-111117.6" + process $proc$libresoc.v:111099$4263 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:109508.5-109508.29" + attribute \src "libresoc.v:111100.5-111100.29" switch \initial - attribute \src "libresoc.v:109508.9-109508.17" + attribute \src "libresoc.v:111100.9-111100.17" case 1'1 case end @@ -170756,14 +172906,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end - attribute \src "libresoc.v:109526.3-109544.6" - process $proc$libresoc.v:109526$4231 + attribute \src "libresoc.v:111118.3-111136.6" + process $proc$libresoc.v:111118$4264 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:109527.5-109527.29" + attribute \src "libresoc.v:111119.5-111119.29" switch \initial - attribute \src "libresoc.v:109527.9-109527.17" + attribute \src "libresoc.v:111119.9-111119.17" case 1'1 case end @@ -170791,14 +172941,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end - attribute \src "libresoc.v:109545.3-109563.6" - process $proc$libresoc.v:109545$4232 + attribute \src "libresoc.v:111137.3-111155.6" + process $proc$libresoc.v:111137$4265 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:109546.5-109546.29" + attribute \src "libresoc.v:111138.5-111138.29" switch \initial - attribute \src "libresoc.v:109546.9-109546.17" + attribute \src "libresoc.v:111138.9-111138.17" case 1'1 case end @@ -170826,14 +172976,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end - attribute \src "libresoc.v:109564.3-109582.6" - process $proc$libresoc.v:109564$4233 + attribute \src "libresoc.v:111156.3-111174.6" + process $proc$libresoc.v:111156$4266 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:109565.5-109565.29" + attribute \src "libresoc.v:111157.5-111157.29" switch \initial - attribute \src "libresoc.v:109565.9-109565.17" + attribute \src "libresoc.v:111157.9-111157.17" case 1'1 case end @@ -170861,14 +173011,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end - attribute \src "libresoc.v:109583.3-109601.6" - process $proc$libresoc.v:109583$4234 + attribute \src "libresoc.v:111175.3-111193.6" + process $proc$libresoc.v:111175$4267 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:109584.5-109584.29" + attribute \src "libresoc.v:111176.5-111176.29" switch \initial - attribute \src "libresoc.v:109584.9-109584.17" + attribute \src "libresoc.v:111176.9-111176.17" case 1'1 case end @@ -170896,14 +173046,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end - attribute \src "libresoc.v:109602.3-109620.6" - process $proc$libresoc.v:109602$4235 + attribute \src "libresoc.v:111194.3-111212.6" + process $proc$libresoc.v:111194$4268 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:109603.5-109603.29" + attribute \src "libresoc.v:111195.5-111195.29" switch \initial - attribute \src "libresoc.v:109603.9-109603.17" + attribute \src "libresoc.v:111195.9-111195.17" case 1'1 case end @@ -170931,14 +173081,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:109621.3-109639.6" - process $proc$libresoc.v:109621$4236 + attribute \src "libresoc.v:111213.3-111231.6" + process $proc$libresoc.v:111213$4269 assign { } { } assign { } { } assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:109622.5-109622.29" + attribute \src "libresoc.v:111214.5-111214.29" switch \initial - attribute \src "libresoc.v:109622.9-109622.17" + attribute \src "libresoc.v:111214.9-111214.17" case 1'1 case end @@ -170966,14 +173116,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:109640.3-109658.6" - process $proc$libresoc.v:109640$4237 + attribute \src "libresoc.v:111232.3-111250.6" + process $proc$libresoc.v:111232$4270 assign { } { } assign { } { } assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:109641.5-109641.29" + attribute \src "libresoc.v:111233.5-111233.29" switch \initial - attribute \src "libresoc.v:109641.9-109641.17" + attribute \src "libresoc.v:111233.9-111233.17" case 1'1 case end @@ -171001,14 +173151,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:109659.3-109677.6" - process $proc$libresoc.v:109659$4238 + attribute \src "libresoc.v:111251.3-111269.6" + process $proc$libresoc.v:111251$4271 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:109660.5-109660.29" + attribute \src "libresoc.v:111252.5-111252.29" switch \initial - attribute \src "libresoc.v:109660.9-109660.17" + attribute \src "libresoc.v:111252.9-111252.17" case 1'1 case end @@ -171036,14 +173186,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:109678.3-109696.6" - process $proc$libresoc.v:109678$4239 + attribute \src "libresoc.v:111270.3-111288.6" + process $proc$libresoc.v:111270$4272 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:109679.5-109679.29" + attribute \src "libresoc.v:111271.5-111271.29" switch \initial - attribute \src "libresoc.v:109679.9-109679.17" + attribute \src "libresoc.v:111271.9-111271.17" case 1'1 case end @@ -171071,14 +173221,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:109697.3-109715.6" - process $proc$libresoc.v:109697$4240 + attribute \src "libresoc.v:111289.3-111307.6" + process $proc$libresoc.v:111289$4273 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:109698.5-109698.29" + attribute \src "libresoc.v:111290.5-111290.29" switch \initial - attribute \src "libresoc.v:109698.9-109698.17" + attribute \src "libresoc.v:111290.9-111290.17" case 1'1 case end @@ -171106,14 +173256,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:109716.3-109734.6" - process $proc$libresoc.v:109716$4241 + attribute \src "libresoc.v:111308.3-111326.6" + process $proc$libresoc.v:111308$4274 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:109717.5-109717.29" + attribute \src "libresoc.v:111309.5-111309.29" switch \initial - attribute \src "libresoc.v:109717.9-109717.17" + attribute \src "libresoc.v:111309.9-111309.17" case 1'1 case end @@ -171141,14 +173291,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:109735.3-109753.6" - process $proc$libresoc.v:109735$4242 + attribute \src "libresoc.v:111327.3-111345.6" + process $proc$libresoc.v:111327$4275 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:109736.5-109736.29" + attribute \src "libresoc.v:111328.5-111328.29" switch \initial - attribute \src "libresoc.v:109736.9-109736.17" + attribute \src "libresoc.v:111328.9-111328.17" case 1'1 case end @@ -171176,14 +173326,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:109754.3-109772.6" - process $proc$libresoc.v:109754$4243 + attribute \src "libresoc.v:111346.3-111364.6" + process $proc$libresoc.v:111346$4276 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:109755.5-109755.29" + attribute \src "libresoc.v:111347.5-111347.29" switch \initial - attribute \src "libresoc.v:109755.9-109755.17" + attribute \src "libresoc.v:111347.9-111347.17" case 1'1 case end @@ -171211,14 +173361,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:109773.3-109791.6" - process $proc$libresoc.v:109773$4244 + attribute \src "libresoc.v:111365.3-111383.6" + process $proc$libresoc.v:111365$4277 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:109774.5-109774.29" + attribute \src "libresoc.v:111366.5-111366.29" switch \initial - attribute \src "libresoc.v:109774.9-109774.17" + attribute \src "libresoc.v:111366.9-111366.17" case 1'1 case end @@ -171246,14 +173396,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:109792.3-109810.6" - process $proc$libresoc.v:109792$4245 + attribute \src "libresoc.v:111384.3-111402.6" + process $proc$libresoc.v:111384$4278 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:109793.5-109793.29" + attribute \src "libresoc.v:111385.5-111385.29" switch \initial - attribute \src "libresoc.v:109793.9-109793.17" + attribute \src "libresoc.v:111385.9-111385.17" case 1'1 case end @@ -171281,14 +173431,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:109811.3-109829.6" - process $proc$libresoc.v:109811$4246 + attribute \src "libresoc.v:111403.3-111421.6" + process $proc$libresoc.v:111403$4279 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:109812.5-109812.29" + attribute \src "libresoc.v:111404.5-111404.29" switch \initial - attribute \src "libresoc.v:109812.9-109812.17" + attribute \src "libresoc.v:111404.9-111404.17" case 1'1 case end @@ -171316,14 +173466,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:109830.3-109848.6" - process $proc$libresoc.v:109830$4247 + attribute \src "libresoc.v:111422.3-111440.6" + process $proc$libresoc.v:111422$4280 assign { } { } assign { } { } assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:109831.5-109831.29" + attribute \src "libresoc.v:111423.5-111423.29" switch \initial - attribute \src "libresoc.v:109831.9-109831.17" + attribute \src "libresoc.v:111423.9-111423.17" case 1'1 case end @@ -171351,14 +173501,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:109849.3-109867.6" - process $proc$libresoc.v:109849$4248 + attribute \src "libresoc.v:111441.3-111459.6" + process $proc$libresoc.v:111441$4281 assign { } { } assign { } { } assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:109850.5-109850.29" + attribute \src "libresoc.v:111442.5-111442.29" switch \initial - attribute \src "libresoc.v:109850.9-109850.17" + attribute \src "libresoc.v:111442.9-111442.17" case 1'1 case end @@ -171386,14 +173536,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:109868.3-109886.6" - process $proc$libresoc.v:109868$4249 + attribute \src "libresoc.v:111460.3-111478.6" + process $proc$libresoc.v:111460$4282 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:109869.5-109869.29" + attribute \src "libresoc.v:111461.5-111461.29" switch \initial - attribute \src "libresoc.v:109869.9-109869.17" + attribute \src "libresoc.v:111461.9-111461.17" case 1'1 case end @@ -171421,14 +173571,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:109887.3-109905.6" - process $proc$libresoc.v:109887$4250 + attribute \src "libresoc.v:111479.3-111497.6" + process $proc$libresoc.v:111479$4283 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:109888.5-109888.29" + attribute \src "libresoc.v:111480.5-111480.29" switch \initial - attribute \src "libresoc.v:109888.9-109888.17" + attribute \src "libresoc.v:111480.9-111480.17" case 1'1 case end @@ -171456,14 +173606,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:109906.3-109924.6" - process $proc$libresoc.v:109906$4251 + attribute \src "libresoc.v:111498.3-111516.6" + process $proc$libresoc.v:111498$4284 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:109907.5-109907.29" + attribute \src "libresoc.v:111499.5-111499.29" switch \initial - attribute \src "libresoc.v:109907.9-109907.17" + attribute \src "libresoc.v:111499.9-111499.17" case 1'1 case end @@ -171491,14 +173641,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:109925.3-109943.6" - process $proc$libresoc.v:109925$4252 + attribute \src "libresoc.v:111517.3-111535.6" + process $proc$libresoc.v:111517$4285 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:109926.5-109926.29" + attribute \src "libresoc.v:111518.5-111518.29" switch \initial - attribute \src "libresoc.v:109926.9-109926.17" + attribute \src "libresoc.v:111518.9-111518.17" case 1'1 case end @@ -171526,14 +173676,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] end - attribute \src "libresoc.v:109944.3-109962.6" - process $proc$libresoc.v:109944$4253 + attribute \src "libresoc.v:111536.3-111554.6" + process $proc$libresoc.v:111536$4286 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:109945.5-109945.29" + attribute \src "libresoc.v:111537.5-111537.29" switch \initial - attribute \src "libresoc.v:109945.9-109945.17" + attribute \src "libresoc.v:111537.9-111537.17" case 1'1 case end @@ -171561,14 +173711,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] end - attribute \src "libresoc.v:109963.3-109981.6" - process $proc$libresoc.v:109963$4254 + attribute \src "libresoc.v:111555.3-111573.6" + process $proc$libresoc.v:111555$4287 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:109964.5-109964.29" + attribute \src "libresoc.v:111556.5-111556.29" switch \initial - attribute \src "libresoc.v:109964.9-109964.17" + attribute \src "libresoc.v:111556.9-111556.17" case 1'1 case end @@ -171596,14 +173746,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:109982.3-110000.6" - process $proc$libresoc.v:109982$4255 + attribute \src "libresoc.v:111574.3-111592.6" + process $proc$libresoc.v:111574$4288 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:109983.5-109983.29" + attribute \src "libresoc.v:111575.5-111575.29" switch \initial - attribute \src "libresoc.v:109983.9-109983.17" + attribute \src "libresoc.v:111575.9-111575.17" case 1'1 case end @@ -171631,14 +173781,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:110001.3-110019.6" - process $proc$libresoc.v:110001$4256 + attribute \src "libresoc.v:111593.3-111611.6" + process $proc$libresoc.v:111593$4289 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:110002.5-110002.29" + attribute \src "libresoc.v:111594.5-111594.29" switch \initial - attribute \src "libresoc.v:110002.9-110002.17" + attribute \src "libresoc.v:111594.9-111594.17" case 1'1 case end @@ -171666,14 +173816,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:110020.3-110038.6" - process $proc$libresoc.v:110020$4257 + attribute \src "libresoc.v:111612.3-111630.6" + process $proc$libresoc.v:111612$4290 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:110021.5-110021.29" + assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] + attribute \src "libresoc.v:111613.5-111613.29" switch \initial - attribute \src "libresoc.v:110021.9-110021.17" + attribute \src "libresoc.v:111613.9-111613.17" case 1'1 case end @@ -171682,161 +173832,161 @@ module \dec31_dec_sub27 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 case - assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub27_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:110044.1-111565.10" +attribute \src "libresoc.v:111636.1-113160.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 - attribute \src "libresoc.v:111342.3-111378.6" + attribute \src "libresoc.v:112937.3-112973.6" wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:111379.3-111415.6" + attribute \src "libresoc.v:112974.3-113010.6" wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:110898.3-110934.6" + attribute \src "libresoc.v:112493.3-112529.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:111046.3-111082.6" + attribute \src "libresoc.v:112641.3-112677.6" wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:110417.3-110453.6" + attribute \src "libresoc.v:112012.3-112048.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:110454.3-110490.6" + attribute \src "libresoc.v:112049.3-112085.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:110861.3-110897.6" + attribute \src "libresoc.v:112456.3-112492.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:111009.3-111045.6" + attribute \src "libresoc.v:112604.3-112640.6" wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:111194.3-111230.6" + attribute \src "libresoc.v:112789.3-112825.6" wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:110380.3-110416.6" - wire width 13 $0\dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:111416.3-111452.6" + attribute \src "libresoc.v:111975.3-112011.6" + wire width 14 $0\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:113011.3-113047.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:111453.3-111489.6" + attribute \src "libresoc.v:113048.3-113084.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:111490.3-111526.6" + attribute \src "libresoc.v:113085.3-113121.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:110787.3-110823.6" + attribute \src "libresoc.v:112382.3-112418.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:110935.3-110971.6" + attribute \src "libresoc.v:112530.3-112566.6" wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:110972.3-111008.6" + attribute \src "libresoc.v:112567.3-112603.6" wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:111157.3-111193.6" + attribute \src "libresoc.v:112752.3-112788.6" wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:110713.3-110749.6" + attribute \src "libresoc.v:112308.3-112344.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:111268.3-111304.6" + attribute \src "libresoc.v:112863.3-112899.6" wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:111527.3-111563.6" - wire width 2 $0\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:110824.3-110860.6" + attribute \src "libresoc.v:113122.3-113158.6" + wire width 3 $0\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:112419.3-112455.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:111120.3-111156.6" + attribute \src "libresoc.v:112715.3-112751.6" wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:111305.3-111341.6" + attribute \src "libresoc.v:112900.3-112936.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:111231.3-111267.6" + attribute \src "libresoc.v:112826.3-112862.6" wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:111083.3-111119.6" + attribute \src "libresoc.v:112678.3-112714.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:110639.3-110675.6" + attribute \src "libresoc.v:112234.3-112270.6" wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:110676.3-110712.6" + attribute \src "libresoc.v:112271.3-112307.6" wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:110491.3-110527.6" + attribute \src "libresoc.v:112086.3-112122.6" wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:110528.3-110564.6" + attribute \src "libresoc.v:112123.3-112159.6" wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:110565.3-110601.6" + attribute \src "libresoc.v:112160.3-112196.6" wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:110602.3-110638.6" + attribute \src "libresoc.v:112197.3-112233.6" wire width 3 $0\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:110750.3-110786.6" + attribute \src "libresoc.v:112345.3-112381.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:110045.7-110045.20" + attribute \src "libresoc.v:111637.7-111637.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111342.3-111378.6" + attribute \src "libresoc.v:112937.3-112973.6" wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:111379.3-111415.6" + attribute \src "libresoc.v:112974.3-113010.6" wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:110898.3-110934.6" + attribute \src "libresoc.v:112493.3-112529.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:111046.3-111082.6" + attribute \src "libresoc.v:112641.3-112677.6" wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:110417.3-110453.6" + attribute \src "libresoc.v:112012.3-112048.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:110454.3-110490.6" + attribute \src "libresoc.v:112049.3-112085.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:110861.3-110897.6" + attribute \src "libresoc.v:112456.3-112492.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:111009.3-111045.6" + attribute \src "libresoc.v:112604.3-112640.6" wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:111194.3-111230.6" + attribute \src "libresoc.v:112789.3-112825.6" wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:110380.3-110416.6" - wire width 13 $1\dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:111416.3-111452.6" + attribute \src "libresoc.v:111975.3-112011.6" + wire width 14 $1\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:113011.3-113047.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:111453.3-111489.6" + attribute \src "libresoc.v:113048.3-113084.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:111490.3-111526.6" + attribute \src "libresoc.v:113085.3-113121.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:110787.3-110823.6" + attribute \src "libresoc.v:112382.3-112418.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:110935.3-110971.6" + attribute \src "libresoc.v:112530.3-112566.6" wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:110972.3-111008.6" + attribute \src "libresoc.v:112567.3-112603.6" wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:111157.3-111193.6" + attribute \src "libresoc.v:112752.3-112788.6" wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:110713.3-110749.6" + attribute \src "libresoc.v:112308.3-112344.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:111268.3-111304.6" + attribute \src "libresoc.v:112863.3-112899.6" wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:111527.3-111563.6" - wire width 2 $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:110824.3-110860.6" + attribute \src "libresoc.v:113122.3-113158.6" + wire width 3 $1\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:112419.3-112455.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:111120.3-111156.6" + attribute \src "libresoc.v:112715.3-112751.6" wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:111305.3-111341.6" + attribute \src "libresoc.v:112900.3-112936.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:111231.3-111267.6" + attribute \src "libresoc.v:112826.3-112862.6" wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:111083.3-111119.6" + attribute \src "libresoc.v:112678.3-112714.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:110639.3-110675.6" + attribute \src "libresoc.v:112234.3-112270.6" wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:110676.3-110712.6" + attribute \src "libresoc.v:112271.3-112307.6" wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:110491.3-110527.6" + attribute \src "libresoc.v:112086.3-112122.6" wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:110528.3-110564.6" + attribute \src "libresoc.v:112123.3-112159.6" wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:110565.3-110601.6" + attribute \src "libresoc.v:112160.3-112196.6" wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:110602.3-110638.6" + attribute \src "libresoc.v:112197.3-112233.6" wire width 3 $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:110750.3-110786.6" + attribute \src "libresoc.v:112345.3-112381.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -171916,21 +174066,22 @@ module \dec31_dec_sub28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub28_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub28_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -172036,6 +174187,7 @@ module \dec31_dec_sub28 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub28_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -172055,12 +174207,13 @@ module \dec31_dec_sub28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub28_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub28_out_sel + wire width 3 output 10 \dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -172136,28 +174289,28 @@ module \dec31_dec_sub28 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub28_upd - attribute \src "libresoc.v:110045.7-110045.15" + attribute \src "libresoc.v:111637.7-111637.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:110045.7-110045.20" - process $proc$libresoc.v:110045$4291 + attribute \src "libresoc.v:111637.7-111637.20" + process $proc$libresoc.v:111637$4324 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110380.3-110416.6" - process $proc$libresoc.v:110380$4259 + attribute \src "libresoc.v:111975.3-112011.6" + process $proc$libresoc.v:111975$4292 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_function_unit[12:0] $1\dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:110381.5-110381.29" + assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] + attribute \src "libresoc.v:111976.5-111976.29" switch \initial - attribute \src "libresoc.v:110381.9-110381.17" + attribute \src "libresoc.v:111976.9-111976.17" case 1'1 case end @@ -172166,57 +174319,57 @@ module \dec31_dec_sub28 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 case - assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[12:0] + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:110417.3-110453.6" - process $proc$libresoc.v:110417$4260 + attribute \src "libresoc.v:112012.3-112048.6" + process $proc$libresoc.v:112012$4293 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:110418.5-110418.29" + attribute \src "libresoc.v:112013.5-112013.29" switch \initial - attribute \src "libresoc.v:110418.9-110418.17" + attribute \src "libresoc.v:112013.9-112013.17" case 1'1 case end @@ -172268,14 +174421,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:110454.3-110490.6" - process $proc$libresoc.v:110454$4261 + attribute \src "libresoc.v:112049.3-112085.6" + process $proc$libresoc.v:112049$4294 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:110455.5-110455.29" + attribute \src "libresoc.v:112050.5-112050.29" switch \initial - attribute \src "libresoc.v:110455.9-110455.17" + attribute \src "libresoc.v:112050.9-112050.17" case 1'1 case end @@ -172327,14 +174480,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:110491.3-110527.6" - process $proc$libresoc.v:110491$4262 + attribute \src "libresoc.v:112086.3-112122.6" + process $proc$libresoc.v:112086$4295 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:110492.5-110492.29" + attribute \src "libresoc.v:112087.5-112087.29" switch \initial - attribute \src "libresoc.v:110492.9-110492.17" + attribute \src "libresoc.v:112087.9-112087.17" case 1'1 case end @@ -172386,14 +174539,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end - attribute \src "libresoc.v:110528.3-110564.6" - process $proc$libresoc.v:110528$4263 + attribute \src "libresoc.v:112123.3-112159.6" + process $proc$libresoc.v:112123$4296 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:110529.5-110529.29" + attribute \src "libresoc.v:112124.5-112124.29" switch \initial - attribute \src "libresoc.v:110529.9-110529.17" + attribute \src "libresoc.v:112124.9-112124.17" case 1'1 case end @@ -172445,14 +174598,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end - attribute \src "libresoc.v:110565.3-110601.6" - process $proc$libresoc.v:110565$4264 + attribute \src "libresoc.v:112160.3-112196.6" + process $proc$libresoc.v:112160$4297 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:110566.5-110566.29" + attribute \src "libresoc.v:112161.5-112161.29" switch \initial - attribute \src "libresoc.v:110566.9-110566.17" + attribute \src "libresoc.v:112161.9-112161.17" case 1'1 case end @@ -172504,14 +174657,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end - attribute \src "libresoc.v:110602.3-110638.6" - process $proc$libresoc.v:110602$4265 + attribute \src "libresoc.v:112197.3-112233.6" + process $proc$libresoc.v:112197$4298 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:110603.5-110603.29" + attribute \src "libresoc.v:112198.5-112198.29" switch \initial - attribute \src "libresoc.v:110603.9-110603.17" + attribute \src "libresoc.v:112198.9-112198.17" case 1'1 case end @@ -172563,14 +174716,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end - attribute \src "libresoc.v:110639.3-110675.6" - process $proc$libresoc.v:110639$4266 + attribute \src "libresoc.v:112234.3-112270.6" + process $proc$libresoc.v:112234$4299 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:110640.5-110640.29" + attribute \src "libresoc.v:112235.5-112235.29" switch \initial - attribute \src "libresoc.v:110640.9-110640.17" + attribute \src "libresoc.v:112235.9-112235.17" case 1'1 case end @@ -172622,14 +174775,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end - attribute \src "libresoc.v:110676.3-110712.6" - process $proc$libresoc.v:110676$4267 + attribute \src "libresoc.v:112271.3-112307.6" + process $proc$libresoc.v:112271$4300 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:110677.5-110677.29" + attribute \src "libresoc.v:112272.5-112272.29" switch \initial - attribute \src "libresoc.v:110677.9-110677.17" + attribute \src "libresoc.v:112272.9-112272.17" case 1'1 case end @@ -172681,14 +174834,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end - attribute \src "libresoc.v:110713.3-110749.6" - process $proc$libresoc.v:110713$4268 + attribute \src "libresoc.v:112308.3-112344.6" + process $proc$libresoc.v:112308$4301 assign { } { } assign { } { } assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:110714.5-110714.29" + attribute \src "libresoc.v:112309.5-112309.29" switch \initial - attribute \src "libresoc.v:110714.9-110714.17" + attribute \src "libresoc.v:112309.9-112309.17" case 1'1 case end @@ -172740,14 +174893,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:110750.3-110786.6" - process $proc$libresoc.v:110750$4269 + attribute \src "libresoc.v:112345.3-112381.6" + process $proc$libresoc.v:112345$4302 assign { } { } assign { } { } assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:110751.5-110751.29" + attribute \src "libresoc.v:112346.5-112346.29" switch \initial - attribute \src "libresoc.v:110751.9-110751.17" + attribute \src "libresoc.v:112346.9-112346.17" case 1'1 case end @@ -172799,14 +174952,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:110787.3-110823.6" - process $proc$libresoc.v:110787$4270 + attribute \src "libresoc.v:112382.3-112418.6" + process $proc$libresoc.v:112382$4303 assign { } { } assign { } { } assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:110788.5-110788.29" + attribute \src "libresoc.v:112383.5-112383.29" switch \initial - attribute \src "libresoc.v:110788.9-110788.17" + attribute \src "libresoc.v:112383.9-112383.17" case 1'1 case end @@ -172858,14 +175011,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:110824.3-110860.6" - process $proc$libresoc.v:110824$4271 + attribute \src "libresoc.v:112419.3-112455.6" + process $proc$libresoc.v:112419$4304 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:110825.5-110825.29" + attribute \src "libresoc.v:112420.5-112420.29" switch \initial - attribute \src "libresoc.v:110825.9-110825.17" + attribute \src "libresoc.v:112420.9-112420.17" case 1'1 case end @@ -172917,14 +175070,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:110861.3-110897.6" - process $proc$libresoc.v:110861$4272 + attribute \src "libresoc.v:112456.3-112492.6" + process $proc$libresoc.v:112456$4305 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:110862.5-110862.29" + attribute \src "libresoc.v:112457.5-112457.29" switch \initial - attribute \src "libresoc.v:110862.9-110862.17" + attribute \src "libresoc.v:112457.9-112457.17" case 1'1 case end @@ -172976,14 +175129,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:110898.3-110934.6" - process $proc$libresoc.v:110898$4273 + attribute \src "libresoc.v:112493.3-112529.6" + process $proc$libresoc.v:112493$4306 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:110899.5-110899.29" + attribute \src "libresoc.v:112494.5-112494.29" switch \initial - attribute \src "libresoc.v:110899.9-110899.17" + attribute \src "libresoc.v:112494.9-112494.17" case 1'1 case end @@ -173035,14 +175188,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:110935.3-110971.6" - process $proc$libresoc.v:110935$4274 + attribute \src "libresoc.v:112530.3-112566.6" + process $proc$libresoc.v:112530$4307 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:110936.5-110936.29" + attribute \src "libresoc.v:112531.5-112531.29" switch \initial - attribute \src "libresoc.v:110936.9-110936.17" + attribute \src "libresoc.v:112531.9-112531.17" case 1'1 case end @@ -173094,14 +175247,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:110972.3-111008.6" - process $proc$libresoc.v:110972$4275 + attribute \src "libresoc.v:112567.3-112603.6" + process $proc$libresoc.v:112567$4308 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:110973.5-110973.29" + attribute \src "libresoc.v:112568.5-112568.29" switch \initial - attribute \src "libresoc.v:110973.9-110973.17" + attribute \src "libresoc.v:112568.9-112568.17" case 1'1 case end @@ -173153,14 +175306,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:111009.3-111045.6" - process $proc$libresoc.v:111009$4276 + attribute \src "libresoc.v:112604.3-112640.6" + process $proc$libresoc.v:112604$4309 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:111010.5-111010.29" + attribute \src "libresoc.v:112605.5-112605.29" switch \initial - attribute \src "libresoc.v:111010.9-111010.17" + attribute \src "libresoc.v:112605.9-112605.17" case 1'1 case end @@ -173212,14 +175365,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:111046.3-111082.6" - process $proc$libresoc.v:111046$4277 + attribute \src "libresoc.v:112641.3-112677.6" + process $proc$libresoc.v:112641$4310 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:111047.5-111047.29" + attribute \src "libresoc.v:112642.5-112642.29" switch \initial - attribute \src "libresoc.v:111047.9-111047.17" + attribute \src "libresoc.v:112642.9-112642.17" case 1'1 case end @@ -173271,14 +175424,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:111083.3-111119.6" - process $proc$libresoc.v:111083$4278 + attribute \src "libresoc.v:112678.3-112714.6" + process $proc$libresoc.v:112678$4311 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:111084.5-111084.29" + attribute \src "libresoc.v:112679.5-112679.29" switch \initial - attribute \src "libresoc.v:111084.9-111084.17" + attribute \src "libresoc.v:112679.9-112679.17" case 1'1 case end @@ -173330,14 +175483,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:111120.3-111156.6" - process $proc$libresoc.v:111120$4279 + attribute \src "libresoc.v:112715.3-112751.6" + process $proc$libresoc.v:112715$4312 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:111121.5-111121.29" + attribute \src "libresoc.v:112716.5-112716.29" switch \initial - attribute \src "libresoc.v:111121.9-111121.17" + attribute \src "libresoc.v:112716.9-112716.17" case 1'1 case end @@ -173389,14 +175542,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:111157.3-111193.6" - process $proc$libresoc.v:111157$4280 + attribute \src "libresoc.v:112752.3-112788.6" + process $proc$libresoc.v:112752$4313 assign { } { } assign { } { } assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:111158.5-111158.29" + attribute \src "libresoc.v:112753.5-112753.29" switch \initial - attribute \src "libresoc.v:111158.9-111158.17" + attribute \src "libresoc.v:112753.9-112753.17" case 1'1 case end @@ -173448,14 +175601,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:111194.3-111230.6" - process $proc$libresoc.v:111194$4281 + attribute \src "libresoc.v:112789.3-112825.6" + process $proc$libresoc.v:112789$4314 assign { } { } assign { } { } assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:111195.5-111195.29" + attribute \src "libresoc.v:112790.5-112790.29" switch \initial - attribute \src "libresoc.v:111195.9-111195.17" + attribute \src "libresoc.v:112790.9-112790.17" case 1'1 case end @@ -173507,14 +175660,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:111231.3-111267.6" - process $proc$libresoc.v:111231$4282 + attribute \src "libresoc.v:112826.3-112862.6" + process $proc$libresoc.v:112826$4315 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:111232.5-111232.29" + attribute \src "libresoc.v:112827.5-112827.29" switch \initial - attribute \src "libresoc.v:111232.9-111232.17" + attribute \src "libresoc.v:112827.9-112827.17" case 1'1 case end @@ -173566,14 +175719,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:111268.3-111304.6" - process $proc$libresoc.v:111268$4283 + attribute \src "libresoc.v:112863.3-112899.6" + process $proc$libresoc.v:112863$4316 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:111269.5-111269.29" + attribute \src "libresoc.v:112864.5-112864.29" switch \initial - attribute \src "libresoc.v:111269.9-111269.17" + attribute \src "libresoc.v:112864.9-112864.17" case 1'1 case end @@ -173625,14 +175778,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:111305.3-111341.6" - process $proc$libresoc.v:111305$4284 + attribute \src "libresoc.v:112900.3-112936.6" + process $proc$libresoc.v:112900$4317 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:111306.5-111306.29" + attribute \src "libresoc.v:112901.5-112901.29" switch \initial - attribute \src "libresoc.v:111306.9-111306.17" + attribute \src "libresoc.v:112901.9-112901.17" case 1'1 case end @@ -173684,14 +175837,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:111342.3-111378.6" - process $proc$libresoc.v:111342$4285 + attribute \src "libresoc.v:112937.3-112973.6" + process $proc$libresoc.v:112937$4318 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:111343.5-111343.29" + attribute \src "libresoc.v:112938.5-112938.29" switch \initial - attribute \src "libresoc.v:111343.9-111343.17" + attribute \src "libresoc.v:112938.9-112938.17" case 1'1 case end @@ -173743,14 +175896,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] end - attribute \src "libresoc.v:111379.3-111415.6" - process $proc$libresoc.v:111379$4286 + attribute \src "libresoc.v:112974.3-113010.6" + process $proc$libresoc.v:112974$4319 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:111380.5-111380.29" + attribute \src "libresoc.v:112975.5-112975.29" switch \initial - attribute \src "libresoc.v:111380.9-111380.17" + attribute \src "libresoc.v:112975.9-112975.17" case 1'1 case end @@ -173802,14 +175955,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end - attribute \src "libresoc.v:111416.3-111452.6" - process $proc$libresoc.v:111416$4287 + attribute \src "libresoc.v:113011.3-113047.6" + process $proc$libresoc.v:113011$4320 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:111417.5-111417.29" + attribute \src "libresoc.v:113012.5-113012.29" switch \initial - attribute \src "libresoc.v:111417.9-111417.17" + attribute \src "libresoc.v:113012.9-113012.17" case 1'1 case end @@ -173861,14 +176014,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:111453.3-111489.6" - process $proc$libresoc.v:111453$4288 + attribute \src "libresoc.v:113048.3-113084.6" + process $proc$libresoc.v:113048$4321 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:111454.5-111454.29" + attribute \src "libresoc.v:113049.5-113049.29" switch \initial - attribute \src "libresoc.v:111454.9-111454.17" + attribute \src "libresoc.v:113049.9-113049.17" case 1'1 case end @@ -173920,14 +176073,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:111490.3-111526.6" - process $proc$libresoc.v:111490$4289 + attribute \src "libresoc.v:113085.3-113121.6" + process $proc$libresoc.v:113085$4322 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:111491.5-111491.29" + attribute \src "libresoc.v:113086.5-113086.29" switch \initial - attribute \src "libresoc.v:111491.9-111491.17" + attribute \src "libresoc.v:113086.9-113086.17" case 1'1 case end @@ -173979,14 +176132,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:111527.3-111563.6" - process $proc$libresoc.v:111527$4290 + attribute \src "libresoc.v:113122.3-113158.6" + process $proc$libresoc.v:113122$4323 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:111528.5-111528.29" + assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] + attribute \src "libresoc.v:113123.5-113123.29" switch \initial - attribute \src "libresoc.v:111528.9-111528.17" + attribute \src "libresoc.v:113123.9-113123.17" case 1'1 case end @@ -173995,185 +176148,185 @@ module \dec31_dec_sub28 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 case - assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub28_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:111569.1-112322.10" +attribute \src "libresoc.v:113164.1-113920.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 - attribute \src "libresoc.v:112243.3-112255.6" + attribute \src "libresoc.v:113841.3-113853.6" wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:112256.3-112268.6" + attribute \src "libresoc.v:113854.3-113866.6" wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:112087.3-112099.6" + attribute \src "libresoc.v:113685.3-113697.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:112139.3-112151.6" + attribute \src "libresoc.v:113737.3-113749.6" wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:111918.3-111930.6" + attribute \src "libresoc.v:113516.3-113528.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:111931.3-111943.6" + attribute \src "libresoc.v:113529.3-113541.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:112074.3-112086.6" + attribute \src "libresoc.v:113672.3-113684.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:112126.3-112138.6" + attribute \src "libresoc.v:113724.3-113736.6" wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:112191.3-112203.6" + attribute \src "libresoc.v:113789.3-113801.6" wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:111905.3-111917.6" - wire width 13 $0\dec31_dec_sub4_function_unit[12:0] - attribute \src "libresoc.v:112269.3-112281.6" + attribute \src "libresoc.v:113503.3-113515.6" + wire width 14 $0\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:113867.3-113879.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:112282.3-112294.6" + attribute \src "libresoc.v:113880.3-113892.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:112295.3-112307.6" + attribute \src "libresoc.v:113893.3-113905.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:112048.3-112060.6" + attribute \src "libresoc.v:113646.3-113658.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:112100.3-112112.6" + attribute \src "libresoc.v:113698.3-113710.6" wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:112113.3-112125.6" + attribute \src "libresoc.v:113711.3-113723.6" wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:112178.3-112190.6" + attribute \src "libresoc.v:113776.3-113788.6" wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:112022.3-112034.6" + attribute \src "libresoc.v:113620.3-113632.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:112217.3-112229.6" + attribute \src "libresoc.v:113815.3-113827.6" wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:112308.3-112320.6" - wire width 2 $0\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:112061.3-112073.6" + attribute \src "libresoc.v:113906.3-113918.6" + wire width 3 $0\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:113659.3-113671.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:112165.3-112177.6" + attribute \src "libresoc.v:113763.3-113775.6" wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:112230.3-112242.6" + attribute \src "libresoc.v:113828.3-113840.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:112204.3-112216.6" + attribute \src "libresoc.v:113802.3-113814.6" wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:112152.3-112164.6" + attribute \src "libresoc.v:113750.3-113762.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:111996.3-112008.6" + attribute \src "libresoc.v:113594.3-113606.6" wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:112009.3-112021.6" + attribute \src "libresoc.v:113607.3-113619.6" wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:111944.3-111956.6" + attribute \src "libresoc.v:113542.3-113554.6" wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:111957.3-111969.6" + attribute \src "libresoc.v:113555.3-113567.6" wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:111970.3-111982.6" + attribute \src "libresoc.v:113568.3-113580.6" wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:111983.3-111995.6" + attribute \src "libresoc.v:113581.3-113593.6" wire width 3 $0\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:112035.3-112047.6" + attribute \src "libresoc.v:113633.3-113645.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:111570.7-111570.20" + attribute \src "libresoc.v:113165.7-113165.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112243.3-112255.6" + attribute \src "libresoc.v:113841.3-113853.6" wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:112256.3-112268.6" + attribute \src "libresoc.v:113854.3-113866.6" wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:112087.3-112099.6" + attribute \src "libresoc.v:113685.3-113697.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:112139.3-112151.6" + attribute \src "libresoc.v:113737.3-113749.6" wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:111918.3-111930.6" + attribute \src "libresoc.v:113516.3-113528.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:111931.3-111943.6" + attribute \src "libresoc.v:113529.3-113541.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:112074.3-112086.6" + attribute \src "libresoc.v:113672.3-113684.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:112126.3-112138.6" + attribute \src "libresoc.v:113724.3-113736.6" wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:112191.3-112203.6" + attribute \src "libresoc.v:113789.3-113801.6" wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:111905.3-111917.6" - wire width 13 $1\dec31_dec_sub4_function_unit[12:0] - attribute \src "libresoc.v:112269.3-112281.6" + attribute \src "libresoc.v:113503.3-113515.6" + wire width 14 $1\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:113867.3-113879.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:112282.3-112294.6" + attribute \src "libresoc.v:113880.3-113892.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:112295.3-112307.6" + attribute \src "libresoc.v:113893.3-113905.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:112048.3-112060.6" + attribute \src "libresoc.v:113646.3-113658.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:112100.3-112112.6" + attribute \src "libresoc.v:113698.3-113710.6" wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:112113.3-112125.6" + attribute \src "libresoc.v:113711.3-113723.6" wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:112178.3-112190.6" + attribute \src "libresoc.v:113776.3-113788.6" wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:112022.3-112034.6" + attribute \src "libresoc.v:113620.3-113632.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:112217.3-112229.6" + attribute \src "libresoc.v:113815.3-113827.6" wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:112308.3-112320.6" - wire width 2 $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:112061.3-112073.6" + attribute \src "libresoc.v:113906.3-113918.6" + wire width 3 $1\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:113659.3-113671.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:112165.3-112177.6" + attribute \src "libresoc.v:113763.3-113775.6" wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:112230.3-112242.6" + attribute \src "libresoc.v:113828.3-113840.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:112204.3-112216.6" + attribute \src "libresoc.v:113802.3-113814.6" wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:112152.3-112164.6" + attribute \src "libresoc.v:113750.3-113762.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:111996.3-112008.6" + attribute \src "libresoc.v:113594.3-113606.6" wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:112009.3-112021.6" + attribute \src "libresoc.v:113607.3-113619.6" wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:111944.3-111956.6" + attribute \src "libresoc.v:113542.3-113554.6" wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:111957.3-111969.6" + attribute \src "libresoc.v:113555.3-113567.6" wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:111970.3-111982.6" + attribute \src "libresoc.v:113568.3-113580.6" wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:111983.3-111995.6" + attribute \src "libresoc.v:113581.3-113593.6" wire width 3 $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:112035.3-112047.6" + attribute \src "libresoc.v:113633.3-113645.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -174253,21 +176406,22 @@ module \dec31_dec_sub4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub4_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -174373,6 +176527,7 @@ module \dec31_dec_sub4 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub4_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -174392,12 +176547,13 @@ module \dec31_dec_sub4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub4_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub4_out_sel + wire width 3 output 10 \dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -174473,28 +176629,28 @@ module \dec31_dec_sub4 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub4_upd - attribute \src "libresoc.v:111570.7-111570.15" + attribute \src "libresoc.v:113165.7-113165.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:111570.7-111570.20" - process $proc$libresoc.v:111570$4324 + attribute \src "libresoc.v:113165.7-113165.20" + process $proc$libresoc.v:113165$4357 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111905.3-111917.6" - process $proc$libresoc.v:111905$4292 + attribute \src "libresoc.v:113503.3-113515.6" + process $proc$libresoc.v:113503$4325 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_function_unit[12:0] $1\dec31_dec_sub4_function_unit[12:0] - attribute \src "libresoc.v:111906.5-111906.29" + assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] + attribute \src "libresoc.v:113504.5-113504.29" switch \initial - attribute \src "libresoc.v:111906.9-111906.17" + attribute \src "libresoc.v:113504.9-113504.17" case 1'1 case end @@ -174503,25 +176659,25 @@ module \dec31_dec_sub4 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_function_unit[12:0] 13'0000010000000 + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_function_unit[12:0] 13'0000010000000 + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000010000000 case - assign $1\dec31_dec_sub4_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[12:0] + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] end - attribute \src "libresoc.v:111918.3-111930.6" - process $proc$libresoc.v:111918$4293 + attribute \src "libresoc.v:113516.3-113528.6" + process $proc$libresoc.v:113516$4326 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:111919.5-111919.29" + attribute \src "libresoc.v:113517.5-113517.29" switch \initial - attribute \src "libresoc.v:111919.9-111919.17" + attribute \src "libresoc.v:113517.9-113517.17" case 1'1 case end @@ -174541,14 +176697,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:111931.3-111943.6" - process $proc$libresoc.v:111931$4294 + attribute \src "libresoc.v:113529.3-113541.6" + process $proc$libresoc.v:113529$4327 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:111932.5-111932.29" + attribute \src "libresoc.v:113530.5-113530.29" switch \initial - attribute \src "libresoc.v:111932.9-111932.17" + attribute \src "libresoc.v:113530.9-113530.17" case 1'1 case end @@ -174568,14 +176724,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "libresoc.v:111944.3-111956.6" - process $proc$libresoc.v:111944$4295 + attribute \src "libresoc.v:113542.3-113554.6" + process $proc$libresoc.v:113542$4328 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:111945.5-111945.29" + attribute \src "libresoc.v:113543.5-113543.29" switch \initial - attribute \src "libresoc.v:111945.9-111945.17" + attribute \src "libresoc.v:113543.9-113543.17" case 1'1 case end @@ -174595,14 +176751,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] end - attribute \src "libresoc.v:111957.3-111969.6" - process $proc$libresoc.v:111957$4296 + attribute \src "libresoc.v:113555.3-113567.6" + process $proc$libresoc.v:113555$4329 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:111958.5-111958.29" + attribute \src "libresoc.v:113556.5-113556.29" switch \initial - attribute \src "libresoc.v:111958.9-111958.17" + attribute \src "libresoc.v:113556.9-113556.17" case 1'1 case end @@ -174622,14 +176778,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] end - attribute \src "libresoc.v:111970.3-111982.6" - process $proc$libresoc.v:111970$4297 + attribute \src "libresoc.v:113568.3-113580.6" + process $proc$libresoc.v:113568$4330 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:111971.5-111971.29" + attribute \src "libresoc.v:113569.5-113569.29" switch \initial - attribute \src "libresoc.v:111971.9-111971.17" + attribute \src "libresoc.v:113569.9-113569.17" case 1'1 case end @@ -174649,14 +176805,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] end - attribute \src "libresoc.v:111983.3-111995.6" - process $proc$libresoc.v:111983$4298 + attribute \src "libresoc.v:113581.3-113593.6" + process $proc$libresoc.v:113581$4331 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:111984.5-111984.29" + attribute \src "libresoc.v:113582.5-113582.29" switch \initial - attribute \src "libresoc.v:111984.9-111984.17" + attribute \src "libresoc.v:113582.9-113582.17" case 1'1 case end @@ -174676,14 +176832,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] end - attribute \src "libresoc.v:111996.3-112008.6" - process $proc$libresoc.v:111996$4299 + attribute \src "libresoc.v:113594.3-113606.6" + process $proc$libresoc.v:113594$4332 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:111997.5-111997.29" + attribute \src "libresoc.v:113595.5-113595.29" switch \initial - attribute \src "libresoc.v:111997.9-111997.17" + attribute \src "libresoc.v:113595.9-113595.17" case 1'1 case end @@ -174703,14 +176859,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] end - attribute \src "libresoc.v:112009.3-112021.6" - process $proc$libresoc.v:112009$4300 + attribute \src "libresoc.v:113607.3-113619.6" + process $proc$libresoc.v:113607$4333 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:112010.5-112010.29" + attribute \src "libresoc.v:113608.5-113608.29" switch \initial - attribute \src "libresoc.v:112010.9-112010.17" + attribute \src "libresoc.v:113608.9-113608.17" case 1'1 case end @@ -174730,14 +176886,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] end - attribute \src "libresoc.v:112022.3-112034.6" - process $proc$libresoc.v:112022$4301 + attribute \src "libresoc.v:113620.3-113632.6" + process $proc$libresoc.v:113620$4334 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:112023.5-112023.29" + attribute \src "libresoc.v:113621.5-113621.29" switch \initial - attribute \src "libresoc.v:112023.9-112023.17" + attribute \src "libresoc.v:113621.9-113621.17" case 1'1 case end @@ -174757,14 +176913,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:112035.3-112047.6" - process $proc$libresoc.v:112035$4302 + attribute \src "libresoc.v:113633.3-113645.6" + process $proc$libresoc.v:113633$4335 assign { } { } assign { } { } assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:112036.5-112036.29" + attribute \src "libresoc.v:113634.5-113634.29" switch \initial - attribute \src "libresoc.v:112036.9-112036.17" + attribute \src "libresoc.v:113634.9-113634.17" case 1'1 case end @@ -174784,14 +176940,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "libresoc.v:112048.3-112060.6" - process $proc$libresoc.v:112048$4303 + attribute \src "libresoc.v:113646.3-113658.6" + process $proc$libresoc.v:113646$4336 assign { } { } assign { } { } assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:112049.5-112049.29" + attribute \src "libresoc.v:113647.5-113647.29" switch \initial - attribute \src "libresoc.v:112049.9-112049.17" + attribute \src "libresoc.v:113647.9-113647.17" case 1'1 case end @@ -174811,14 +176967,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "libresoc.v:112061.3-112073.6" - process $proc$libresoc.v:112061$4304 + attribute \src "libresoc.v:113659.3-113671.6" + process $proc$libresoc.v:113659$4337 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:112062.5-112062.29" + attribute \src "libresoc.v:113660.5-113660.29" switch \initial - attribute \src "libresoc.v:112062.9-112062.17" + attribute \src "libresoc.v:113660.9-113660.17" case 1'1 case end @@ -174838,14 +176994,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "libresoc.v:112074.3-112086.6" - process $proc$libresoc.v:112074$4305 + attribute \src "libresoc.v:113672.3-113684.6" + process $proc$libresoc.v:113672$4338 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:112075.5-112075.29" + attribute \src "libresoc.v:113673.5-113673.29" switch \initial - attribute \src "libresoc.v:112075.9-112075.17" + attribute \src "libresoc.v:113673.9-113673.17" case 1'1 case end @@ -174865,14 +177021,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:112087.3-112099.6" - process $proc$libresoc.v:112087$4306 + attribute \src "libresoc.v:113685.3-113697.6" + process $proc$libresoc.v:113685$4339 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:112088.5-112088.29" + attribute \src "libresoc.v:113686.5-113686.29" switch \initial - attribute \src "libresoc.v:112088.9-112088.17" + attribute \src "libresoc.v:113686.9-113686.17" case 1'1 case end @@ -174892,14 +177048,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "libresoc.v:112100.3-112112.6" - process $proc$libresoc.v:112100$4307 + attribute \src "libresoc.v:113698.3-113710.6" + process $proc$libresoc.v:113698$4340 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:112101.5-112101.29" + attribute \src "libresoc.v:113699.5-113699.29" switch \initial - attribute \src "libresoc.v:112101.9-112101.17" + attribute \src "libresoc.v:113699.9-113699.17" case 1'1 case end @@ -174919,14 +177075,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "libresoc.v:112113.3-112125.6" - process $proc$libresoc.v:112113$4308 + attribute \src "libresoc.v:113711.3-113723.6" + process $proc$libresoc.v:113711$4341 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:112114.5-112114.29" + attribute \src "libresoc.v:113712.5-113712.29" switch \initial - attribute \src "libresoc.v:112114.9-112114.17" + attribute \src "libresoc.v:113712.9-113712.17" case 1'1 case end @@ -174946,14 +177102,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "libresoc.v:112126.3-112138.6" - process $proc$libresoc.v:112126$4309 + attribute \src "libresoc.v:113724.3-113736.6" + process $proc$libresoc.v:113724$4342 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:112127.5-112127.29" + attribute \src "libresoc.v:113725.5-113725.29" switch \initial - attribute \src "libresoc.v:112127.9-112127.17" + attribute \src "libresoc.v:113725.9-113725.17" case 1'1 case end @@ -174973,14 +177129,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "libresoc.v:112139.3-112151.6" - process $proc$libresoc.v:112139$4310 + attribute \src "libresoc.v:113737.3-113749.6" + process $proc$libresoc.v:113737$4343 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:112140.5-112140.29" + attribute \src "libresoc.v:113738.5-113738.29" switch \initial - attribute \src "libresoc.v:112140.9-112140.17" + attribute \src "libresoc.v:113738.9-113738.17" case 1'1 case end @@ -175000,14 +177156,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "libresoc.v:112152.3-112164.6" - process $proc$libresoc.v:112152$4311 + attribute \src "libresoc.v:113750.3-113762.6" + process $proc$libresoc.v:113750$4344 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:112153.5-112153.29" + attribute \src "libresoc.v:113751.5-113751.29" switch \initial - attribute \src "libresoc.v:112153.9-112153.17" + attribute \src "libresoc.v:113751.9-113751.17" case 1'1 case end @@ -175027,14 +177183,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "libresoc.v:112165.3-112177.6" - process $proc$libresoc.v:112165$4312 + attribute \src "libresoc.v:113763.3-113775.6" + process $proc$libresoc.v:113763$4345 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:112166.5-112166.29" + attribute \src "libresoc.v:113764.5-113764.29" switch \initial - attribute \src "libresoc.v:112166.9-112166.17" + attribute \src "libresoc.v:113764.9-113764.17" case 1'1 case end @@ -175054,14 +177210,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "libresoc.v:112178.3-112190.6" - process $proc$libresoc.v:112178$4313 + attribute \src "libresoc.v:113776.3-113788.6" + process $proc$libresoc.v:113776$4346 assign { } { } assign { } { } assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:112179.5-112179.29" + attribute \src "libresoc.v:113777.5-113777.29" switch \initial - attribute \src "libresoc.v:112179.9-112179.17" + attribute \src "libresoc.v:113777.9-113777.17" case 1'1 case end @@ -175081,14 +177237,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:112191.3-112203.6" - process $proc$libresoc.v:112191$4314 + attribute \src "libresoc.v:113789.3-113801.6" + process $proc$libresoc.v:113789$4347 assign { } { } assign { } { } assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:112192.5-112192.29" + attribute \src "libresoc.v:113790.5-113790.29" switch \initial - attribute \src "libresoc.v:112192.9-112192.17" + attribute \src "libresoc.v:113790.9-113790.17" case 1'1 case end @@ -175108,14 +177264,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "libresoc.v:112204.3-112216.6" - process $proc$libresoc.v:112204$4315 + attribute \src "libresoc.v:113802.3-113814.6" + process $proc$libresoc.v:113802$4348 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:112205.5-112205.29" + attribute \src "libresoc.v:113803.5-113803.29" switch \initial - attribute \src "libresoc.v:112205.9-112205.17" + attribute \src "libresoc.v:113803.9-113803.17" case 1'1 case end @@ -175135,14 +177291,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "libresoc.v:112217.3-112229.6" - process $proc$libresoc.v:112217$4316 + attribute \src "libresoc.v:113815.3-113827.6" + process $proc$libresoc.v:113815$4349 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:112218.5-112218.29" + attribute \src "libresoc.v:113816.5-113816.29" switch \initial - attribute \src "libresoc.v:112218.9-112218.17" + attribute \src "libresoc.v:113816.9-113816.17" case 1'1 case end @@ -175162,14 +177318,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "libresoc.v:112230.3-112242.6" - process $proc$libresoc.v:112230$4317 + attribute \src "libresoc.v:113828.3-113840.6" + process $proc$libresoc.v:113828$4350 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:112231.5-112231.29" + attribute \src "libresoc.v:113829.5-113829.29" switch \initial - attribute \src "libresoc.v:112231.9-112231.17" + attribute \src "libresoc.v:113829.9-113829.17" case 1'1 case end @@ -175189,14 +177345,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "libresoc.v:112243.3-112255.6" - process $proc$libresoc.v:112243$4318 + attribute \src "libresoc.v:113841.3-113853.6" + process $proc$libresoc.v:113841$4351 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:112244.5-112244.29" + attribute \src "libresoc.v:113842.5-113842.29" switch \initial - attribute \src "libresoc.v:112244.9-112244.17" + attribute \src "libresoc.v:113842.9-113842.17" case 1'1 case end @@ -175216,14 +177372,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] end - attribute \src "libresoc.v:112256.3-112268.6" - process $proc$libresoc.v:112256$4319 + attribute \src "libresoc.v:113854.3-113866.6" + process $proc$libresoc.v:113854$4352 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:112257.5-112257.29" + attribute \src "libresoc.v:113855.5-113855.29" switch \initial - attribute \src "libresoc.v:112257.9-112257.17" + attribute \src "libresoc.v:113855.9-113855.17" case 1'1 case end @@ -175243,14 +177399,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] end - attribute \src "libresoc.v:112269.3-112281.6" - process $proc$libresoc.v:112269$4320 + attribute \src "libresoc.v:113867.3-113879.6" + process $proc$libresoc.v:113867$4353 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:112270.5-112270.29" + attribute \src "libresoc.v:113868.5-113868.29" switch \initial - attribute \src "libresoc.v:112270.9-112270.17" + attribute \src "libresoc.v:113868.9-113868.17" case 1'1 case end @@ -175270,14 +177426,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "libresoc.v:112282.3-112294.6" - process $proc$libresoc.v:112282$4321 + attribute \src "libresoc.v:113880.3-113892.6" + process $proc$libresoc.v:113880$4354 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:112283.5-112283.29" + attribute \src "libresoc.v:113881.5-113881.29" switch \initial - attribute \src "libresoc.v:112283.9-112283.17" + attribute \src "libresoc.v:113881.9-113881.17" case 1'1 case end @@ -175297,14 +177453,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:112295.3-112307.6" - process $proc$libresoc.v:112295$4322 + attribute \src "libresoc.v:113893.3-113905.6" + process $proc$libresoc.v:113893$4355 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:112296.5-112296.29" + attribute \src "libresoc.v:113894.5-113894.29" switch \initial - attribute \src "libresoc.v:112296.9-112296.17" + attribute \src "libresoc.v:113894.9-113894.17" case 1'1 case end @@ -175324,14 +177480,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "libresoc.v:112308.3-112320.6" - process $proc$libresoc.v:112308$4323 + attribute \src "libresoc.v:113906.3-113918.6" + process $proc$libresoc.v:113906$4356 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:112309.5-112309.29" + assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] + attribute \src "libresoc.v:113907.5-113907.29" switch \initial - attribute \src "libresoc.v:112309.9-112309.17" + attribute \src "libresoc.v:113907.9-113907.17" case 1'1 case end @@ -175340,153 +177496,153 @@ module \dec31_dec_sub4 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 case - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:112326.1-114039.10" +attribute \src "libresoc.v:113924.1-115640.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 - attribute \src "libresoc.v:113780.3-113822.6" + attribute \src "libresoc.v:115381.3-115423.6" wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:113823.3-113865.6" + attribute \src "libresoc.v:115424.3-115466.6" wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:113264.3-113306.6" + attribute \src "libresoc.v:114865.3-114907.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:113436.3-113478.6" + attribute \src "libresoc.v:115037.3-115079.6" wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:112705.3-112747.6" + attribute \src "libresoc.v:114306.3-114348.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:112748.3-112790.6" + attribute \src "libresoc.v:114349.3-114391.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:113221.3-113263.6" + attribute \src "libresoc.v:114822.3-114864.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:113393.3-113435.6" + attribute \src "libresoc.v:114994.3-115036.6" wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:113608.3-113650.6" + attribute \src "libresoc.v:115209.3-115251.6" wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:112662.3-112704.6" - wire width 13 $0\dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:113866.3-113908.6" + attribute \src "libresoc.v:114263.3-114305.6" + wire width 14 $0\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:115467.3-115509.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:113909.3-113951.6" + attribute \src "libresoc.v:115510.3-115552.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:113952.3-113994.6" + attribute \src "libresoc.v:115553.3-115595.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:113135.3-113177.6" + attribute \src "libresoc.v:114736.3-114778.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:113307.3-113349.6" + attribute \src "libresoc.v:114908.3-114950.6" wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:113350.3-113392.6" + attribute \src "libresoc.v:114951.3-114993.6" wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:113565.3-113607.6" + attribute \src "libresoc.v:115166.3-115208.6" wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:113049.3-113091.6" + attribute \src "libresoc.v:114650.3-114692.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:113694.3-113736.6" + attribute \src "libresoc.v:115295.3-115337.6" wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:113995.3-114037.6" - wire width 2 $0\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:113178.3-113220.6" + attribute \src "libresoc.v:115596.3-115638.6" + wire width 3 $0\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:114779.3-114821.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:113522.3-113564.6" + attribute \src "libresoc.v:115123.3-115165.6" wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:113737.3-113779.6" + attribute \src "libresoc.v:115338.3-115380.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:113651.3-113693.6" + attribute \src "libresoc.v:115252.3-115294.6" wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:113479.3-113521.6" + attribute \src "libresoc.v:115080.3-115122.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:112963.3-113005.6" + attribute \src "libresoc.v:114564.3-114606.6" wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:113006.3-113048.6" + attribute \src "libresoc.v:114607.3-114649.6" wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:112791.3-112833.6" + attribute \src "libresoc.v:114392.3-114434.6" wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:112834.3-112876.6" + attribute \src "libresoc.v:114435.3-114477.6" wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:112877.3-112919.6" + attribute \src "libresoc.v:114478.3-114520.6" wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:112920.3-112962.6" + attribute \src "libresoc.v:114521.3-114563.6" wire width 3 $0\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:113092.3-113134.6" + attribute \src "libresoc.v:114693.3-114735.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:112327.7-112327.20" + attribute \src "libresoc.v:113925.7-113925.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113780.3-113822.6" + attribute \src "libresoc.v:115381.3-115423.6" wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:113823.3-113865.6" + attribute \src "libresoc.v:115424.3-115466.6" wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:113264.3-113306.6" + attribute \src "libresoc.v:114865.3-114907.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:113436.3-113478.6" + attribute \src "libresoc.v:115037.3-115079.6" wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:112705.3-112747.6" + attribute \src "libresoc.v:114306.3-114348.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:112748.3-112790.6" + attribute \src "libresoc.v:114349.3-114391.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:113221.3-113263.6" + attribute \src "libresoc.v:114822.3-114864.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:113393.3-113435.6" + attribute \src "libresoc.v:114994.3-115036.6" wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:113608.3-113650.6" + attribute \src "libresoc.v:115209.3-115251.6" wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:112662.3-112704.6" - wire width 13 $1\dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:113866.3-113908.6" + attribute \src "libresoc.v:114263.3-114305.6" + wire width 14 $1\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:115467.3-115509.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:113909.3-113951.6" + attribute \src "libresoc.v:115510.3-115552.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:113952.3-113994.6" + attribute \src "libresoc.v:115553.3-115595.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:113135.3-113177.6" + attribute \src "libresoc.v:114736.3-114778.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:113307.3-113349.6" + attribute \src "libresoc.v:114908.3-114950.6" wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:113350.3-113392.6" + attribute \src "libresoc.v:114951.3-114993.6" wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:113565.3-113607.6" + attribute \src "libresoc.v:115166.3-115208.6" wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:113049.3-113091.6" + attribute \src "libresoc.v:114650.3-114692.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:113694.3-113736.6" + attribute \src "libresoc.v:115295.3-115337.6" wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:113995.3-114037.6" - wire width 2 $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:113178.3-113220.6" + attribute \src "libresoc.v:115596.3-115638.6" + wire width 3 $1\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:114779.3-114821.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:113522.3-113564.6" + attribute \src "libresoc.v:115123.3-115165.6" wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:113737.3-113779.6" + attribute \src "libresoc.v:115338.3-115380.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:113651.3-113693.6" + attribute \src "libresoc.v:115252.3-115294.6" wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:113479.3-113521.6" + attribute \src "libresoc.v:115080.3-115122.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:112963.3-113005.6" + attribute \src "libresoc.v:114564.3-114606.6" wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:113006.3-113048.6" + attribute \src "libresoc.v:114607.3-114649.6" wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:112791.3-112833.6" + attribute \src "libresoc.v:114392.3-114434.6" wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:112834.3-112876.6" + attribute \src "libresoc.v:114435.3-114477.6" wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:112877.3-112919.6" + attribute \src "libresoc.v:114478.3-114520.6" wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:112920.3-112962.6" + attribute \src "libresoc.v:114521.3-114563.6" wire width 3 $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:113092.3-113134.6" + attribute \src "libresoc.v:114693.3-114735.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -175566,21 +177722,22 @@ module \dec31_dec_sub8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub8_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub8_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -175686,6 +177843,7 @@ module \dec31_dec_sub8 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub8_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -175705,12 +177863,13 @@ module \dec31_dec_sub8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub8_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub8_out_sel + wire width 3 output 10 \dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -175786,28 +177945,28 @@ module \dec31_dec_sub8 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub8_upd - attribute \src "libresoc.v:112327.7-112327.15" + attribute \src "libresoc.v:113925.7-113925.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:112327.7-112327.20" - process $proc$libresoc.v:112327$4357 + attribute \src "libresoc.v:113925.7-113925.20" + process $proc$libresoc.v:113925$4390 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112662.3-112704.6" - process $proc$libresoc.v:112662$4325 + attribute \src "libresoc.v:114263.3-114305.6" + process $proc$libresoc.v:114263$4358 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_function_unit[12:0] $1\dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:112663.5-112663.29" + assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] + attribute \src "libresoc.v:114264.5-114264.29" switch \initial - attribute \src "libresoc.v:112663.9-112663.17" + attribute \src "libresoc.v:114264.9-114264.17" case 1'1 case end @@ -175816,65 +177975,65 @@ module \dec31_dec_sub8 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 case - assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[12:0] + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:112705.3-112747.6" - process $proc$libresoc.v:112705$4326 + attribute \src "libresoc.v:114306.3-114348.6" + process $proc$libresoc.v:114306$4359 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:112706.5-112706.29" + attribute \src "libresoc.v:114307.5-114307.29" switch \initial - attribute \src "libresoc.v:112706.9-112706.17" + attribute \src "libresoc.v:114307.9-114307.17" case 1'1 case end @@ -175934,14 +178093,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:112748.3-112790.6" - process $proc$libresoc.v:112748$4327 + attribute \src "libresoc.v:114349.3-114391.6" + process $proc$libresoc.v:114349$4360 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:112749.5-112749.29" + attribute \src "libresoc.v:114350.5-114350.29" switch \initial - attribute \src "libresoc.v:112749.9-112749.17" + attribute \src "libresoc.v:114350.9-114350.17" case 1'1 case end @@ -176001,14 +178160,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:112791.3-112833.6" - process $proc$libresoc.v:112791$4328 + attribute \src "libresoc.v:114392.3-114434.6" + process $proc$libresoc.v:114392$4361 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:112792.5-112792.29" + attribute \src "libresoc.v:114393.5-114393.29" switch \initial - attribute \src "libresoc.v:112792.9-112792.17" + attribute \src "libresoc.v:114393.9-114393.17" case 1'1 case end @@ -176068,14 +178227,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end - attribute \src "libresoc.v:112834.3-112876.6" - process $proc$libresoc.v:112834$4329 + attribute \src "libresoc.v:114435.3-114477.6" + process $proc$libresoc.v:114435$4362 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:112835.5-112835.29" + attribute \src "libresoc.v:114436.5-114436.29" switch \initial - attribute \src "libresoc.v:112835.9-112835.17" + attribute \src "libresoc.v:114436.9-114436.17" case 1'1 case end @@ -176135,14 +178294,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end - attribute \src "libresoc.v:112877.3-112919.6" - process $proc$libresoc.v:112877$4330 + attribute \src "libresoc.v:114478.3-114520.6" + process $proc$libresoc.v:114478$4363 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:112878.5-112878.29" + attribute \src "libresoc.v:114479.5-114479.29" switch \initial - attribute \src "libresoc.v:112878.9-112878.17" + attribute \src "libresoc.v:114479.9-114479.17" case 1'1 case end @@ -176202,14 +178361,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end - attribute \src "libresoc.v:112920.3-112962.6" - process $proc$libresoc.v:112920$4331 + attribute \src "libresoc.v:114521.3-114563.6" + process $proc$libresoc.v:114521$4364 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:112921.5-112921.29" + attribute \src "libresoc.v:114522.5-114522.29" switch \initial - attribute \src "libresoc.v:112921.9-112921.17" + attribute \src "libresoc.v:114522.9-114522.17" case 1'1 case end @@ -176269,14 +178428,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end - attribute \src "libresoc.v:112963.3-113005.6" - process $proc$libresoc.v:112963$4332 + attribute \src "libresoc.v:114564.3-114606.6" + process $proc$libresoc.v:114564$4365 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:112964.5-112964.29" + attribute \src "libresoc.v:114565.5-114565.29" switch \initial - attribute \src "libresoc.v:112964.9-112964.17" + attribute \src "libresoc.v:114565.9-114565.17" case 1'1 case end @@ -176336,14 +178495,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end - attribute \src "libresoc.v:113006.3-113048.6" - process $proc$libresoc.v:113006$4333 + attribute \src "libresoc.v:114607.3-114649.6" + process $proc$libresoc.v:114607$4366 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:113007.5-113007.29" + attribute \src "libresoc.v:114608.5-114608.29" switch \initial - attribute \src "libresoc.v:113007.9-113007.17" + attribute \src "libresoc.v:114608.9-114608.17" case 1'1 case end @@ -176403,14 +178562,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end - attribute \src "libresoc.v:113049.3-113091.6" - process $proc$libresoc.v:113049$4334 + attribute \src "libresoc.v:114650.3-114692.6" + process $proc$libresoc.v:114650$4367 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:113050.5-113050.29" + attribute \src "libresoc.v:114651.5-114651.29" switch \initial - attribute \src "libresoc.v:113050.9-113050.17" + attribute \src "libresoc.v:114651.9-114651.17" case 1'1 case end @@ -176470,14 +178629,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:113092.3-113134.6" - process $proc$libresoc.v:113092$4335 + attribute \src "libresoc.v:114693.3-114735.6" + process $proc$libresoc.v:114693$4368 assign { } { } assign { } { } assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:113093.5-113093.29" + attribute \src "libresoc.v:114694.5-114694.29" switch \initial - attribute \src "libresoc.v:113093.9-113093.17" + attribute \src "libresoc.v:114694.9-114694.17" case 1'1 case end @@ -176537,14 +178696,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:113135.3-113177.6" - process $proc$libresoc.v:113135$4336 + attribute \src "libresoc.v:114736.3-114778.6" + process $proc$libresoc.v:114736$4369 assign { } { } assign { } { } assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:113136.5-113136.29" + attribute \src "libresoc.v:114737.5-114737.29" switch \initial - attribute \src "libresoc.v:113136.9-113136.17" + attribute \src "libresoc.v:114737.9-114737.17" case 1'1 case end @@ -176604,14 +178763,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:113178.3-113220.6" - process $proc$libresoc.v:113178$4337 + attribute \src "libresoc.v:114779.3-114821.6" + process $proc$libresoc.v:114779$4370 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:113179.5-113179.29" + attribute \src "libresoc.v:114780.5-114780.29" switch \initial - attribute \src "libresoc.v:113179.9-113179.17" + attribute \src "libresoc.v:114780.9-114780.17" case 1'1 case end @@ -176671,14 +178830,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:113221.3-113263.6" - process $proc$libresoc.v:113221$4338 + attribute \src "libresoc.v:114822.3-114864.6" + process $proc$libresoc.v:114822$4371 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:113222.5-113222.29" + attribute \src "libresoc.v:114823.5-114823.29" switch \initial - attribute \src "libresoc.v:113222.9-113222.17" + attribute \src "libresoc.v:114823.9-114823.17" case 1'1 case end @@ -176738,14 +178897,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:113264.3-113306.6" - process $proc$libresoc.v:113264$4339 + attribute \src "libresoc.v:114865.3-114907.6" + process $proc$libresoc.v:114865$4372 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:113265.5-113265.29" + attribute \src "libresoc.v:114866.5-114866.29" switch \initial - attribute \src "libresoc.v:113265.9-113265.17" + attribute \src "libresoc.v:114866.9-114866.17" case 1'1 case end @@ -176805,14 +178964,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:113307.3-113349.6" - process $proc$libresoc.v:113307$4340 + attribute \src "libresoc.v:114908.3-114950.6" + process $proc$libresoc.v:114908$4373 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:113308.5-113308.29" + attribute \src "libresoc.v:114909.5-114909.29" switch \initial - attribute \src "libresoc.v:113308.9-113308.17" + attribute \src "libresoc.v:114909.9-114909.17" case 1'1 case end @@ -176872,14 +179031,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:113350.3-113392.6" - process $proc$libresoc.v:113350$4341 + attribute \src "libresoc.v:114951.3-114993.6" + process $proc$libresoc.v:114951$4374 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:113351.5-113351.29" + attribute \src "libresoc.v:114952.5-114952.29" switch \initial - attribute \src "libresoc.v:113351.9-113351.17" + attribute \src "libresoc.v:114952.9-114952.17" case 1'1 case end @@ -176939,14 +179098,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:113393.3-113435.6" - process $proc$libresoc.v:113393$4342 + attribute \src "libresoc.v:114994.3-115036.6" + process $proc$libresoc.v:114994$4375 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:113394.5-113394.29" + attribute \src "libresoc.v:114995.5-114995.29" switch \initial - attribute \src "libresoc.v:113394.9-113394.17" + attribute \src "libresoc.v:114995.9-114995.17" case 1'1 case end @@ -177006,14 +179165,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:113436.3-113478.6" - process $proc$libresoc.v:113436$4343 + attribute \src "libresoc.v:115037.3-115079.6" + process $proc$libresoc.v:115037$4376 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:113437.5-113437.29" + attribute \src "libresoc.v:115038.5-115038.29" switch \initial - attribute \src "libresoc.v:113437.9-113437.17" + attribute \src "libresoc.v:115038.9-115038.17" case 1'1 case end @@ -177073,14 +179232,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:113479.3-113521.6" - process $proc$libresoc.v:113479$4344 + attribute \src "libresoc.v:115080.3-115122.6" + process $proc$libresoc.v:115080$4377 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:113480.5-113480.29" + attribute \src "libresoc.v:115081.5-115081.29" switch \initial - attribute \src "libresoc.v:113480.9-113480.17" + attribute \src "libresoc.v:115081.9-115081.17" case 1'1 case end @@ -177140,14 +179299,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:113522.3-113564.6" - process $proc$libresoc.v:113522$4345 + attribute \src "libresoc.v:115123.3-115165.6" + process $proc$libresoc.v:115123$4378 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:113523.5-113523.29" + attribute \src "libresoc.v:115124.5-115124.29" switch \initial - attribute \src "libresoc.v:113523.9-113523.17" + attribute \src "libresoc.v:115124.9-115124.17" case 1'1 case end @@ -177207,14 +179366,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:113565.3-113607.6" - process $proc$libresoc.v:113565$4346 + attribute \src "libresoc.v:115166.3-115208.6" + process $proc$libresoc.v:115166$4379 assign { } { } assign { } { } assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:113566.5-113566.29" + attribute \src "libresoc.v:115167.5-115167.29" switch \initial - attribute \src "libresoc.v:113566.9-113566.17" + attribute \src "libresoc.v:115167.9-115167.17" case 1'1 case end @@ -177274,14 +179433,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:113608.3-113650.6" - process $proc$libresoc.v:113608$4347 + attribute \src "libresoc.v:115209.3-115251.6" + process $proc$libresoc.v:115209$4380 assign { } { } assign { } { } assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:113609.5-113609.29" + attribute \src "libresoc.v:115210.5-115210.29" switch \initial - attribute \src "libresoc.v:113609.9-113609.17" + attribute \src "libresoc.v:115210.9-115210.17" case 1'1 case end @@ -177341,14 +179500,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:113651.3-113693.6" - process $proc$libresoc.v:113651$4348 + attribute \src "libresoc.v:115252.3-115294.6" + process $proc$libresoc.v:115252$4381 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:113652.5-113652.29" + attribute \src "libresoc.v:115253.5-115253.29" switch \initial - attribute \src "libresoc.v:113652.9-113652.17" + attribute \src "libresoc.v:115253.9-115253.17" case 1'1 case end @@ -177408,14 +179567,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:113694.3-113736.6" - process $proc$libresoc.v:113694$4349 + attribute \src "libresoc.v:115295.3-115337.6" + process $proc$libresoc.v:115295$4382 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:113695.5-113695.29" + attribute \src "libresoc.v:115296.5-115296.29" switch \initial - attribute \src "libresoc.v:113695.9-113695.17" + attribute \src "libresoc.v:115296.9-115296.17" case 1'1 case end @@ -177475,14 +179634,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:113737.3-113779.6" - process $proc$libresoc.v:113737$4350 + attribute \src "libresoc.v:115338.3-115380.6" + process $proc$libresoc.v:115338$4383 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:113738.5-113738.29" + attribute \src "libresoc.v:115339.5-115339.29" switch \initial - attribute \src "libresoc.v:113738.9-113738.17" + attribute \src "libresoc.v:115339.9-115339.17" case 1'1 case end @@ -177542,14 +179701,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:113780.3-113822.6" - process $proc$libresoc.v:113780$4351 + attribute \src "libresoc.v:115381.3-115423.6" + process $proc$libresoc.v:115381$4384 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:113781.5-113781.29" + attribute \src "libresoc.v:115382.5-115382.29" switch \initial - attribute \src "libresoc.v:113781.9-113781.17" + attribute \src "libresoc.v:115382.9-115382.17" case 1'1 case end @@ -177609,14 +179768,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end - attribute \src "libresoc.v:113823.3-113865.6" - process $proc$libresoc.v:113823$4352 + attribute \src "libresoc.v:115424.3-115466.6" + process $proc$libresoc.v:115424$4385 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:113824.5-113824.29" + attribute \src "libresoc.v:115425.5-115425.29" switch \initial - attribute \src "libresoc.v:113824.9-113824.17" + attribute \src "libresoc.v:115425.9-115425.17" case 1'1 case end @@ -177676,14 +179835,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end - attribute \src "libresoc.v:113866.3-113908.6" - process $proc$libresoc.v:113866$4353 + attribute \src "libresoc.v:115467.3-115509.6" + process $proc$libresoc.v:115467$4386 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:113867.5-113867.29" + attribute \src "libresoc.v:115468.5-115468.29" switch \initial - attribute \src "libresoc.v:113867.9-113867.17" + attribute \src "libresoc.v:115468.9-115468.17" case 1'1 case end @@ -177743,14 +179902,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:113909.3-113951.6" - process $proc$libresoc.v:113909$4354 + attribute \src "libresoc.v:115510.3-115552.6" + process $proc$libresoc.v:115510$4387 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:113910.5-113910.29" + attribute \src "libresoc.v:115511.5-115511.29" switch \initial - attribute \src "libresoc.v:113910.9-113910.17" + attribute \src "libresoc.v:115511.9-115511.17" case 1'1 case end @@ -177810,14 +179969,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:113952.3-113994.6" - process $proc$libresoc.v:113952$4355 + attribute \src "libresoc.v:115553.3-115595.6" + process $proc$libresoc.v:115553$4388 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:113953.5-113953.29" + attribute \src "libresoc.v:115554.5-115554.29" switch \initial - attribute \src "libresoc.v:113953.9-113953.17" + attribute \src "libresoc.v:115554.9-115554.17" case 1'1 case end @@ -177877,14 +180036,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:113995.3-114037.6" - process $proc$libresoc.v:113995$4356 + attribute \src "libresoc.v:115596.3-115638.6" + process $proc$libresoc.v:115596$4389 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:113996.5-113996.29" + assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] + attribute \src "libresoc.v:115597.5-115597.29" switch \initial - attribute \src "libresoc.v:113996.9-113996.17" + attribute \src "libresoc.v:115597.9-115597.17" case 1'1 case end @@ -177893,193 +180052,193 @@ module \dec31_dec_sub8 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub8_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:114043.1-116140.10" +attribute \src "libresoc.v:115644.1-117744.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 - attribute \src "libresoc.v:115809.3-115863.6" + attribute \src "libresoc.v:117413.3-117467.6" wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:115864.3-115918.6" + attribute \src "libresoc.v:117468.3-117522.6" wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:115149.3-115203.6" + attribute \src "libresoc.v:116753.3-116807.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:115369.3-115423.6" + attribute \src "libresoc.v:116973.3-117027.6" wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:114434.3-114488.6" + attribute \src "libresoc.v:116038.3-116092.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:114489.3-114543.6" + attribute \src "libresoc.v:116093.3-116147.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:115094.3-115148.6" + attribute \src "libresoc.v:116698.3-116752.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:115314.3-115368.6" + attribute \src "libresoc.v:116918.3-116972.6" wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:115589.3-115643.6" + attribute \src "libresoc.v:117193.3-117247.6" wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:114379.3-114433.6" - wire width 13 $0\dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:115919.3-115973.6" + attribute \src "libresoc.v:115983.3-116037.6" + wire width 14 $0\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:117523.3-117577.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:115974.3-116028.6" + attribute \src "libresoc.v:117578.3-117632.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:116029.3-116083.6" + attribute \src "libresoc.v:117633.3-117687.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:114984.3-115038.6" + attribute \src "libresoc.v:116588.3-116642.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:115204.3-115258.6" + attribute \src "libresoc.v:116808.3-116862.6" wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:115259.3-115313.6" + attribute \src "libresoc.v:116863.3-116917.6" wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:115534.3-115588.6" + attribute \src "libresoc.v:117138.3-117192.6" wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:114874.3-114928.6" + attribute \src "libresoc.v:116478.3-116532.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:115699.3-115753.6" + attribute \src "libresoc.v:117303.3-117357.6" wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:116084.3-116138.6" - wire width 2 $0\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:115039.3-115093.6" + attribute \src "libresoc.v:117688.3-117742.6" + wire width 3 $0\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:116643.3-116697.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:115479.3-115533.6" + attribute \src "libresoc.v:117083.3-117137.6" wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:115754.3-115808.6" + attribute \src "libresoc.v:117358.3-117412.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:115644.3-115698.6" + attribute \src "libresoc.v:117248.3-117302.6" wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:115424.3-115478.6" + attribute \src "libresoc.v:117028.3-117082.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:114764.3-114818.6" + attribute \src "libresoc.v:116368.3-116422.6" wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:114819.3-114873.6" + attribute \src "libresoc.v:116423.3-116477.6" wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:114544.3-114598.6" + attribute \src "libresoc.v:116148.3-116202.6" wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:114599.3-114653.6" + attribute \src "libresoc.v:116203.3-116257.6" wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:114654.3-114708.6" + attribute \src "libresoc.v:116258.3-116312.6" wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:114709.3-114763.6" + attribute \src "libresoc.v:116313.3-116367.6" wire width 3 $0\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:114929.3-114983.6" + attribute \src "libresoc.v:116533.3-116587.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:114044.7-114044.20" + attribute \src "libresoc.v:115645.7-115645.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115809.3-115863.6" + attribute \src "libresoc.v:117413.3-117467.6" wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:115864.3-115918.6" + attribute \src "libresoc.v:117468.3-117522.6" wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:115149.3-115203.6" + attribute \src "libresoc.v:116753.3-116807.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:115369.3-115423.6" + attribute \src "libresoc.v:116973.3-117027.6" wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:114434.3-114488.6" + attribute \src "libresoc.v:116038.3-116092.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:114489.3-114543.6" + attribute \src "libresoc.v:116093.3-116147.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:115094.3-115148.6" + attribute \src "libresoc.v:116698.3-116752.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:115314.3-115368.6" + attribute \src "libresoc.v:116918.3-116972.6" wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:115589.3-115643.6" + attribute \src "libresoc.v:117193.3-117247.6" wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:114379.3-114433.6" - wire width 13 $1\dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:115919.3-115973.6" + attribute \src "libresoc.v:115983.3-116037.6" + wire width 14 $1\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:117523.3-117577.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:115974.3-116028.6" + attribute \src "libresoc.v:117578.3-117632.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:116029.3-116083.6" + attribute \src "libresoc.v:117633.3-117687.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:114984.3-115038.6" + attribute \src "libresoc.v:116588.3-116642.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:115204.3-115258.6" + attribute \src "libresoc.v:116808.3-116862.6" wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:115259.3-115313.6" + attribute \src "libresoc.v:116863.3-116917.6" wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:115534.3-115588.6" + attribute \src "libresoc.v:117138.3-117192.6" wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:114874.3-114928.6" + attribute \src "libresoc.v:116478.3-116532.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:115699.3-115753.6" + attribute \src "libresoc.v:117303.3-117357.6" wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:116084.3-116138.6" - wire width 2 $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:115039.3-115093.6" + attribute \src "libresoc.v:117688.3-117742.6" + wire width 3 $1\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:116643.3-116697.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:115479.3-115533.6" + attribute \src "libresoc.v:117083.3-117137.6" wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:115754.3-115808.6" + attribute \src "libresoc.v:117358.3-117412.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:115644.3-115698.6" + attribute \src "libresoc.v:117248.3-117302.6" wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:115424.3-115478.6" + attribute \src "libresoc.v:117028.3-117082.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:114764.3-114818.6" + attribute \src "libresoc.v:116368.3-116422.6" wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:114819.3-114873.6" + attribute \src "libresoc.v:116423.3-116477.6" wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:114544.3-114598.6" + attribute \src "libresoc.v:116148.3-116202.6" wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:114599.3-114653.6" + attribute \src "libresoc.v:116203.3-116257.6" wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:114654.3-114708.6" + attribute \src "libresoc.v:116258.3-116312.6" wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:114709.3-114763.6" + attribute \src "libresoc.v:116313.3-116367.6" wire width 3 $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:114929.3-114983.6" + attribute \src "libresoc.v:116533.3-116587.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -178159,21 +180318,22 @@ module \dec31_dec_sub9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub9_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec31_dec_sub9_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -178279,6 +180439,7 @@ module \dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -178298,12 +180459,13 @@ module \dec31_dec_sub9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec31_dec_sub9_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec31_dec_sub9_out_sel + wire width 3 output 10 \dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -178379,28 +180541,28 @@ module \dec31_dec_sub9 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub9_upd - attribute \src "libresoc.v:114044.7-114044.15" + attribute \src "libresoc.v:115645.7-115645.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:114044.7-114044.20" - process $proc$libresoc.v:114044$4390 + attribute \src "libresoc.v:115645.7-115645.20" + process $proc$libresoc.v:115645$4423 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114379.3-114433.6" - process $proc$libresoc.v:114379$4358 + attribute \src "libresoc.v:115983.3-116037.6" + process $proc$libresoc.v:115983$4391 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_function_unit[12:0] $1\dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:114380.5-114380.29" + assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] + attribute \src "libresoc.v:115984.5-115984.29" switch \initial - attribute \src "libresoc.v:114380.9-114380.17" + attribute \src "libresoc.v:115984.9-115984.17" case 1'1 case end @@ -178409,81 +180571,81 @@ module \dec31_dec_sub9 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 case - assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000000000000 + assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always - update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[12:0] + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:114434.3-114488.6" - process $proc$libresoc.v:114434$4359 + attribute \src "libresoc.v:116038.3-116092.6" + process $proc$libresoc.v:116038$4392 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:114435.5-114435.29" + attribute \src "libresoc.v:116039.5-116039.29" switch \initial - attribute \src "libresoc.v:114435.9-114435.17" + attribute \src "libresoc.v:116039.9-116039.17" case 1'1 case end @@ -178559,14 +180721,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:114489.3-114543.6" - process $proc$libresoc.v:114489$4360 + attribute \src "libresoc.v:116093.3-116147.6" + process $proc$libresoc.v:116093$4393 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:114490.5-114490.29" + attribute \src "libresoc.v:116094.5-116094.29" switch \initial - attribute \src "libresoc.v:114490.9-114490.17" + attribute \src "libresoc.v:116094.9-116094.17" case 1'1 case end @@ -178642,14 +180804,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:114544.3-114598.6" - process $proc$libresoc.v:114544$4361 + attribute \src "libresoc.v:116148.3-116202.6" + process $proc$libresoc.v:116148$4394 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:114545.5-114545.29" + attribute \src "libresoc.v:116149.5-116149.29" switch \initial - attribute \src "libresoc.v:114545.9-114545.17" + attribute \src "libresoc.v:116149.9-116149.17" case 1'1 case end @@ -178725,14 +180887,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end - attribute \src "libresoc.v:114599.3-114653.6" - process $proc$libresoc.v:114599$4362 + attribute \src "libresoc.v:116203.3-116257.6" + process $proc$libresoc.v:116203$4395 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:114600.5-114600.29" + attribute \src "libresoc.v:116204.5-116204.29" switch \initial - attribute \src "libresoc.v:114600.9-114600.17" + attribute \src "libresoc.v:116204.9-116204.17" case 1'1 case end @@ -178808,14 +180970,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end - attribute \src "libresoc.v:114654.3-114708.6" - process $proc$libresoc.v:114654$4363 + attribute \src "libresoc.v:116258.3-116312.6" + process $proc$libresoc.v:116258$4396 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:114655.5-114655.29" + attribute \src "libresoc.v:116259.5-116259.29" switch \initial - attribute \src "libresoc.v:114655.9-114655.17" + attribute \src "libresoc.v:116259.9-116259.17" case 1'1 case end @@ -178891,14 +181053,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end - attribute \src "libresoc.v:114709.3-114763.6" - process $proc$libresoc.v:114709$4364 + attribute \src "libresoc.v:116313.3-116367.6" + process $proc$libresoc.v:116313$4397 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:114710.5-114710.29" + attribute \src "libresoc.v:116314.5-116314.29" switch \initial - attribute \src "libresoc.v:114710.9-114710.17" + attribute \src "libresoc.v:116314.9-116314.17" case 1'1 case end @@ -178974,14 +181136,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end - attribute \src "libresoc.v:114764.3-114818.6" - process $proc$libresoc.v:114764$4365 + attribute \src "libresoc.v:116368.3-116422.6" + process $proc$libresoc.v:116368$4398 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:114765.5-114765.29" + attribute \src "libresoc.v:116369.5-116369.29" switch \initial - attribute \src "libresoc.v:114765.9-114765.17" + attribute \src "libresoc.v:116369.9-116369.17" case 1'1 case end @@ -179057,14 +181219,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end - attribute \src "libresoc.v:114819.3-114873.6" - process $proc$libresoc.v:114819$4366 + attribute \src "libresoc.v:116423.3-116477.6" + process $proc$libresoc.v:116423$4399 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:114820.5-114820.29" + attribute \src "libresoc.v:116424.5-116424.29" switch \initial - attribute \src "libresoc.v:114820.9-114820.17" + attribute \src "libresoc.v:116424.9-116424.17" case 1'1 case end @@ -179140,14 +181302,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end - attribute \src "libresoc.v:114874.3-114928.6" - process $proc$libresoc.v:114874$4367 + attribute \src "libresoc.v:116478.3-116532.6" + process $proc$libresoc.v:116478$4400 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:114875.5-114875.29" + attribute \src "libresoc.v:116479.5-116479.29" switch \initial - attribute \src "libresoc.v:114875.9-114875.17" + attribute \src "libresoc.v:116479.9-116479.17" case 1'1 case end @@ -179223,14 +181385,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:114929.3-114983.6" - process $proc$libresoc.v:114929$4368 + attribute \src "libresoc.v:116533.3-116587.6" + process $proc$libresoc.v:116533$4401 assign { } { } assign { } { } assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:114930.5-114930.29" + attribute \src "libresoc.v:116534.5-116534.29" switch \initial - attribute \src "libresoc.v:114930.9-114930.17" + attribute \src "libresoc.v:116534.9-116534.17" case 1'1 case end @@ -179306,14 +181468,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:114984.3-115038.6" - process $proc$libresoc.v:114984$4369 + attribute \src "libresoc.v:116588.3-116642.6" + process $proc$libresoc.v:116588$4402 assign { } { } assign { } { } assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:114985.5-114985.29" + attribute \src "libresoc.v:116589.5-116589.29" switch \initial - attribute \src "libresoc.v:114985.9-114985.17" + attribute \src "libresoc.v:116589.9-116589.17" case 1'1 case end @@ -179389,14 +181551,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:115039.3-115093.6" - process $proc$libresoc.v:115039$4370 + attribute \src "libresoc.v:116643.3-116697.6" + process $proc$libresoc.v:116643$4403 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:115040.5-115040.29" + attribute \src "libresoc.v:116644.5-116644.29" switch \initial - attribute \src "libresoc.v:115040.9-115040.17" + attribute \src "libresoc.v:116644.9-116644.17" case 1'1 case end @@ -179472,14 +181634,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:115094.3-115148.6" - process $proc$libresoc.v:115094$4371 + attribute \src "libresoc.v:116698.3-116752.6" + process $proc$libresoc.v:116698$4404 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:115095.5-115095.29" + attribute \src "libresoc.v:116699.5-116699.29" switch \initial - attribute \src "libresoc.v:115095.9-115095.17" + attribute \src "libresoc.v:116699.9-116699.17" case 1'1 case end @@ -179555,14 +181717,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:115149.3-115203.6" - process $proc$libresoc.v:115149$4372 + attribute \src "libresoc.v:116753.3-116807.6" + process $proc$libresoc.v:116753$4405 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:115150.5-115150.29" + attribute \src "libresoc.v:116754.5-116754.29" switch \initial - attribute \src "libresoc.v:115150.9-115150.17" + attribute \src "libresoc.v:116754.9-116754.17" case 1'1 case end @@ -179638,14 +181800,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:115204.3-115258.6" - process $proc$libresoc.v:115204$4373 + attribute \src "libresoc.v:116808.3-116862.6" + process $proc$libresoc.v:116808$4406 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:115205.5-115205.29" + attribute \src "libresoc.v:116809.5-116809.29" switch \initial - attribute \src "libresoc.v:115205.9-115205.17" + attribute \src "libresoc.v:116809.9-116809.17" case 1'1 case end @@ -179721,14 +181883,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:115259.3-115313.6" - process $proc$libresoc.v:115259$4374 + attribute \src "libresoc.v:116863.3-116917.6" + process $proc$libresoc.v:116863$4407 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:115260.5-115260.29" + attribute \src "libresoc.v:116864.5-116864.29" switch \initial - attribute \src "libresoc.v:115260.9-115260.17" + attribute \src "libresoc.v:116864.9-116864.17" case 1'1 case end @@ -179804,14 +181966,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:115314.3-115368.6" - process $proc$libresoc.v:115314$4375 + attribute \src "libresoc.v:116918.3-116972.6" + process $proc$libresoc.v:116918$4408 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:115315.5-115315.29" + attribute \src "libresoc.v:116919.5-116919.29" switch \initial - attribute \src "libresoc.v:115315.9-115315.17" + attribute \src "libresoc.v:116919.9-116919.17" case 1'1 case end @@ -179887,14 +182049,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:115369.3-115423.6" - process $proc$libresoc.v:115369$4376 + attribute \src "libresoc.v:116973.3-117027.6" + process $proc$libresoc.v:116973$4409 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:115370.5-115370.29" + attribute \src "libresoc.v:116974.5-116974.29" switch \initial - attribute \src "libresoc.v:115370.9-115370.17" + attribute \src "libresoc.v:116974.9-116974.17" case 1'1 case end @@ -179970,14 +182132,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:115424.3-115478.6" - process $proc$libresoc.v:115424$4377 + attribute \src "libresoc.v:117028.3-117082.6" + process $proc$libresoc.v:117028$4410 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:115425.5-115425.29" + attribute \src "libresoc.v:117029.5-117029.29" switch \initial - attribute \src "libresoc.v:115425.9-115425.17" + attribute \src "libresoc.v:117029.9-117029.17" case 1'1 case end @@ -180053,14 +182215,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:115479.3-115533.6" - process $proc$libresoc.v:115479$4378 + attribute \src "libresoc.v:117083.3-117137.6" + process $proc$libresoc.v:117083$4411 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:115480.5-115480.29" + attribute \src "libresoc.v:117084.5-117084.29" switch \initial - attribute \src "libresoc.v:115480.9-115480.17" + attribute \src "libresoc.v:117084.9-117084.17" case 1'1 case end @@ -180136,14 +182298,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:115534.3-115588.6" - process $proc$libresoc.v:115534$4379 + attribute \src "libresoc.v:117138.3-117192.6" + process $proc$libresoc.v:117138$4412 assign { } { } assign { } { } assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:115535.5-115535.29" + attribute \src "libresoc.v:117139.5-117139.29" switch \initial - attribute \src "libresoc.v:115535.9-115535.17" + attribute \src "libresoc.v:117139.9-117139.17" case 1'1 case end @@ -180219,14 +182381,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:115589.3-115643.6" - process $proc$libresoc.v:115589$4380 + attribute \src "libresoc.v:117193.3-117247.6" + process $proc$libresoc.v:117193$4413 assign { } { } assign { } { } assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:115590.5-115590.29" + attribute \src "libresoc.v:117194.5-117194.29" switch \initial - attribute \src "libresoc.v:115590.9-115590.17" + attribute \src "libresoc.v:117194.9-117194.17" case 1'1 case end @@ -180302,14 +182464,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:115644.3-115698.6" - process $proc$libresoc.v:115644$4381 + attribute \src "libresoc.v:117248.3-117302.6" + process $proc$libresoc.v:117248$4414 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:115645.5-115645.29" + attribute \src "libresoc.v:117249.5-117249.29" switch \initial - attribute \src "libresoc.v:115645.9-115645.17" + attribute \src "libresoc.v:117249.9-117249.17" case 1'1 case end @@ -180385,14 +182547,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:115699.3-115753.6" - process $proc$libresoc.v:115699$4382 + attribute \src "libresoc.v:117303.3-117357.6" + process $proc$libresoc.v:117303$4415 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:115700.5-115700.29" + attribute \src "libresoc.v:117304.5-117304.29" switch \initial - attribute \src "libresoc.v:115700.9-115700.17" + attribute \src "libresoc.v:117304.9-117304.17" case 1'1 case end @@ -180468,14 +182630,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:115754.3-115808.6" - process $proc$libresoc.v:115754$4383 + attribute \src "libresoc.v:117358.3-117412.6" + process $proc$libresoc.v:117358$4416 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:115755.5-115755.29" + attribute \src "libresoc.v:117359.5-117359.29" switch \initial - attribute \src "libresoc.v:115755.9-115755.17" + attribute \src "libresoc.v:117359.9-117359.17" case 1'1 case end @@ -180551,14 +182713,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:115809.3-115863.6" - process $proc$libresoc.v:115809$4384 + attribute \src "libresoc.v:117413.3-117467.6" + process $proc$libresoc.v:117413$4417 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:115810.5-115810.29" + attribute \src "libresoc.v:117414.5-117414.29" switch \initial - attribute \src "libresoc.v:115810.9-115810.17" + attribute \src "libresoc.v:117414.9-117414.17" case 1'1 case end @@ -180634,14 +182796,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end - attribute \src "libresoc.v:115864.3-115918.6" - process $proc$libresoc.v:115864$4385 + attribute \src "libresoc.v:117468.3-117522.6" + process $proc$libresoc.v:117468$4418 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:115865.5-115865.29" + attribute \src "libresoc.v:117469.5-117469.29" switch \initial - attribute \src "libresoc.v:115865.9-115865.17" + attribute \src "libresoc.v:117469.9-117469.17" case 1'1 case end @@ -180717,14 +182879,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end - attribute \src "libresoc.v:115919.3-115973.6" - process $proc$libresoc.v:115919$4386 + attribute \src "libresoc.v:117523.3-117577.6" + process $proc$libresoc.v:117523$4419 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:115920.5-115920.29" + attribute \src "libresoc.v:117524.5-117524.29" switch \initial - attribute \src "libresoc.v:115920.9-115920.17" + attribute \src "libresoc.v:117524.9-117524.17" case 1'1 case end @@ -180800,14 +182962,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:115974.3-116028.6" - process $proc$libresoc.v:115974$4387 + attribute \src "libresoc.v:117578.3-117632.6" + process $proc$libresoc.v:117578$4420 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:115975.5-115975.29" + attribute \src "libresoc.v:117579.5-117579.29" switch \initial - attribute \src "libresoc.v:115975.9-115975.17" + attribute \src "libresoc.v:117579.9-117579.17" case 1'1 case end @@ -180883,14 +183045,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:116029.3-116083.6" - process $proc$libresoc.v:116029$4388 + attribute \src "libresoc.v:117633.3-117687.6" + process $proc$libresoc.v:117633$4421 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:116030.5-116030.29" + attribute \src "libresoc.v:117634.5-117634.29" switch \initial - attribute \src "libresoc.v:116030.9-116030.17" + attribute \src "libresoc.v:117634.9-117634.17" case 1'1 case end @@ -180966,14 +183128,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:116084.3-116138.6" - process $proc$libresoc.v:116084$4389 + attribute \src "libresoc.v:117688.3-117742.6" + process $proc$libresoc.v:117688$4422 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:116085.5-116085.29" + assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] + attribute \src "libresoc.v:117689.5-117689.29" switch \initial - attribute \src "libresoc.v:116085.9-116085.17" + attribute \src "libresoc.v:117689.9-117689.17" case 1'1 case end @@ -180982,209 +183144,209 @@ module \dec31_dec_sub9 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 case - assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + assign $1\dec31_dec_sub9_out_sel[2:0] 3'000 end sync always - update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:116144.1-116993.10" +attribute \src "libresoc.v:117748.1-118600.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 - attribute \src "libresoc.v:116896.3-116911.6" + attribute \src "libresoc.v:118503.3-118518.6" wire width 2 $0\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:116912.3-116927.6" + attribute \src "libresoc.v:118519.3-118534.6" wire width 2 $0\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:116704.3-116719.6" + attribute \src "libresoc.v:118311.3-118326.6" wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:116768.3-116783.6" + attribute \src "libresoc.v:118375.3-118390.6" wire $0\dec58_br[0:0] - attribute \src "libresoc.v:116496.3-116511.6" + attribute \src "libresoc.v:118103.3-118118.6" wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:116512.3-116527.6" + attribute \src "libresoc.v:118119.3-118134.6" wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:116688.3-116703.6" + attribute \src "libresoc.v:118295.3-118310.6" wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:116752.3-116767.6" + attribute \src "libresoc.v:118359.3-118374.6" wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:116832.3-116847.6" + attribute \src "libresoc.v:118439.3-118454.6" wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:116480.3-116495.6" - wire width 13 $0\dec58_function_unit[12:0] - attribute \src "libresoc.v:116928.3-116943.6" + attribute \src "libresoc.v:118087.3-118102.6" + wire width 14 $0\dec58_function_unit[13:0] + attribute \src "libresoc.v:118535.3-118550.6" wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:116944.3-116959.6" + attribute \src "libresoc.v:118551.3-118566.6" wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:116960.3-116975.6" + attribute \src "libresoc.v:118567.3-118582.6" wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:116656.3-116671.6" + attribute \src "libresoc.v:118263.3-118278.6" wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:116720.3-116735.6" + attribute \src "libresoc.v:118327.3-118342.6" wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:116736.3-116751.6" + attribute \src "libresoc.v:118343.3-118358.6" wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:116816.3-116831.6" + attribute \src "libresoc.v:118423.3-118438.6" wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:116624.3-116639.6" + attribute \src "libresoc.v:118231.3-118246.6" wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:116864.3-116879.6" + attribute \src "libresoc.v:118471.3-118486.6" wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:116976.3-116991.6" - wire width 2 $0\dec58_out_sel[1:0] - attribute \src "libresoc.v:116672.3-116687.6" + attribute \src "libresoc.v:118583.3-118598.6" + wire width 3 $0\dec58_out_sel[2:0] + attribute \src "libresoc.v:118279.3-118294.6" wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:116800.3-116815.6" + attribute \src "libresoc.v:118407.3-118422.6" wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:116880.3-116895.6" + attribute \src "libresoc.v:118487.3-118502.6" wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:116848.3-116863.6" + attribute \src "libresoc.v:118455.3-118470.6" wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:116784.3-116799.6" + attribute \src "libresoc.v:118391.3-118406.6" wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:116592.3-116607.6" + attribute \src "libresoc.v:118199.3-118214.6" wire width 3 $0\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:116608.3-116623.6" + attribute \src "libresoc.v:118215.3-118230.6" wire width 3 $0\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:116528.3-116543.6" + attribute \src "libresoc.v:118135.3-118150.6" wire width 3 $0\dec58_sv_in1[2:0] - attribute \src "libresoc.v:116544.3-116559.6" + attribute \src "libresoc.v:118151.3-118166.6" wire width 3 $0\dec58_sv_in2[2:0] - attribute \src "libresoc.v:116560.3-116575.6" + attribute \src "libresoc.v:118167.3-118182.6" wire width 3 $0\dec58_sv_in3[2:0] - attribute \src "libresoc.v:116576.3-116591.6" + attribute \src "libresoc.v:118183.3-118198.6" wire width 3 $0\dec58_sv_out[2:0] - attribute \src "libresoc.v:116640.3-116655.6" + attribute \src "libresoc.v:118247.3-118262.6" wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:116145.7-116145.20" + attribute \src "libresoc.v:117749.7-117749.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116896.3-116911.6" + attribute \src "libresoc.v:118503.3-118518.6" wire width 2 $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:116912.3-116927.6" + attribute \src "libresoc.v:118519.3-118534.6" wire width 2 $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:116704.3-116719.6" + attribute \src "libresoc.v:118311.3-118326.6" wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:116768.3-116783.6" + attribute \src "libresoc.v:118375.3-118390.6" wire $1\dec58_br[0:0] - attribute \src "libresoc.v:116496.3-116511.6" + attribute \src "libresoc.v:118103.3-118118.6" wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:116512.3-116527.6" + attribute \src "libresoc.v:118119.3-118134.6" wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:116688.3-116703.6" + attribute \src "libresoc.v:118295.3-118310.6" wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:116752.3-116767.6" + attribute \src "libresoc.v:118359.3-118374.6" wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:116832.3-116847.6" + attribute \src "libresoc.v:118439.3-118454.6" wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:116480.3-116495.6" - wire width 13 $1\dec58_function_unit[12:0] - attribute \src "libresoc.v:116928.3-116943.6" + attribute \src "libresoc.v:118087.3-118102.6" + wire width 14 $1\dec58_function_unit[13:0] + attribute \src "libresoc.v:118535.3-118550.6" wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:116944.3-116959.6" + attribute \src "libresoc.v:118551.3-118566.6" wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:116960.3-116975.6" + attribute \src "libresoc.v:118567.3-118582.6" wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:116656.3-116671.6" + attribute \src "libresoc.v:118263.3-118278.6" wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:116720.3-116735.6" + attribute \src "libresoc.v:118327.3-118342.6" wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:116736.3-116751.6" + attribute \src "libresoc.v:118343.3-118358.6" wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:116816.3-116831.6" + attribute \src "libresoc.v:118423.3-118438.6" wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:116624.3-116639.6" + attribute \src "libresoc.v:118231.3-118246.6" wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:116864.3-116879.6" + attribute \src "libresoc.v:118471.3-118486.6" wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:116976.3-116991.6" - wire width 2 $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:116672.3-116687.6" + attribute \src "libresoc.v:118583.3-118598.6" + wire width 3 $1\dec58_out_sel[2:0] + attribute \src "libresoc.v:118279.3-118294.6" wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:116800.3-116815.6" + attribute \src "libresoc.v:118407.3-118422.6" wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:116880.3-116895.6" + attribute \src "libresoc.v:118487.3-118502.6" wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:116848.3-116863.6" + attribute \src "libresoc.v:118455.3-118470.6" wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:116784.3-116799.6" + attribute \src "libresoc.v:118391.3-118406.6" wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:116592.3-116607.6" + attribute \src "libresoc.v:118199.3-118214.6" wire width 3 $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:116608.3-116623.6" + attribute \src "libresoc.v:118215.3-118230.6" wire width 3 $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:116528.3-116543.6" + attribute \src "libresoc.v:118135.3-118150.6" wire width 3 $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:116544.3-116559.6" + attribute \src "libresoc.v:118151.3-118166.6" wire width 3 $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:116560.3-116575.6" + attribute \src "libresoc.v:118167.3-118182.6" wire width 3 $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:116576.3-116591.6" + attribute \src "libresoc.v:118183.3-118198.6" wire width 3 $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:116640.3-116655.6" + attribute \src "libresoc.v:118247.3-118262.6" wire width 2 $1\dec58_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -181264,21 +183426,22 @@ module \dec58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec58_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec58_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -181384,6 +183547,7 @@ module \dec58 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -181403,12 +183567,13 @@ module \dec58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec58_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec58_out_sel + wire width 3 output 10 \dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -181484,28 +183649,28 @@ module \dec58 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec58_upd - attribute \src "libresoc.v:116145.7-116145.15" + attribute \src "libresoc.v:117749.7-117749.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 2 \opcode_switch - attribute \src "libresoc.v:116145.7-116145.20" - process $proc$libresoc.v:116145$4423 + attribute \src "libresoc.v:117749.7-117749.20" + process $proc$libresoc.v:117749$4456 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116480.3-116495.6" - process $proc$libresoc.v:116480$4391 + attribute \src "libresoc.v:118087.3-118102.6" + process $proc$libresoc.v:118087$4424 assign { } { } assign { } { } - assign $0\dec58_function_unit[12:0] $1\dec58_function_unit[12:0] - attribute \src "libresoc.v:116481.5-116481.29" + assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] + attribute \src "libresoc.v:118088.5-118088.29" switch \initial - attribute \src "libresoc.v:116481.9-116481.17" + attribute \src "libresoc.v:118088.9-118088.17" case 1'1 case end @@ -181514,29 +183679,29 @@ module \dec58 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_function_unit[12:0] 13'0000000000100 + assign $1\dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_function_unit[12:0] 13'0000000000100 + assign $1\dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_function_unit[12:0] 13'0000000000100 + assign $1\dec58_function_unit[13:0] 14'00000000000100 case - assign $1\dec58_function_unit[12:0] 13'0000000000000 + assign $1\dec58_function_unit[13:0] 14'00000000000000 end sync always - update \dec58_function_unit $0\dec58_function_unit[12:0] + update \dec58_function_unit $0\dec58_function_unit[13:0] end - attribute \src "libresoc.v:116496.3-116511.6" - process $proc$libresoc.v:116496$4392 + attribute \src "libresoc.v:118103.3-118118.6" + process $proc$libresoc.v:118103$4425 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:116497.5-116497.29" + attribute \src "libresoc.v:118104.5-118104.29" switch \initial - attribute \src "libresoc.v:116497.9-116497.17" + attribute \src "libresoc.v:118104.9-118104.17" case 1'1 case end @@ -181560,14 +183725,14 @@ module \dec58 sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:116512.3-116527.6" - process $proc$libresoc.v:116512$4393 + attribute \src "libresoc.v:118119.3-118134.6" + process $proc$libresoc.v:118119$4426 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:116513.5-116513.29" + attribute \src "libresoc.v:118120.5-118120.29" switch \initial - attribute \src "libresoc.v:116513.9-116513.17" + attribute \src "libresoc.v:118120.9-118120.17" case 1'1 case end @@ -181591,14 +183756,14 @@ module \dec58 sync always update \dec58_cr_out $0\dec58_cr_out[2:0] end - attribute \src "libresoc.v:116528.3-116543.6" - process $proc$libresoc.v:116528$4394 + attribute \src "libresoc.v:118135.3-118150.6" + process $proc$libresoc.v:118135$4427 assign { } { } assign { } { } assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:116529.5-116529.29" + attribute \src "libresoc.v:118136.5-118136.29" switch \initial - attribute \src "libresoc.v:116529.9-116529.17" + attribute \src "libresoc.v:118136.9-118136.17" case 1'1 case end @@ -181622,14 +183787,14 @@ module \dec58 sync always update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end - attribute \src "libresoc.v:116544.3-116559.6" - process $proc$libresoc.v:116544$4395 + attribute \src "libresoc.v:118151.3-118166.6" + process $proc$libresoc.v:118151$4428 assign { } { } assign { } { } assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:116545.5-116545.29" + attribute \src "libresoc.v:118152.5-118152.29" switch \initial - attribute \src "libresoc.v:116545.9-116545.17" + attribute \src "libresoc.v:118152.9-118152.17" case 1'1 case end @@ -181653,14 +183818,14 @@ module \dec58 sync always update \dec58_sv_in2 $0\dec58_sv_in2[2:0] end - attribute \src "libresoc.v:116560.3-116575.6" - process $proc$libresoc.v:116560$4396 + attribute \src "libresoc.v:118167.3-118182.6" + process $proc$libresoc.v:118167$4429 assign { } { } assign { } { } assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:116561.5-116561.29" + attribute \src "libresoc.v:118168.5-118168.29" switch \initial - attribute \src "libresoc.v:116561.9-116561.17" + attribute \src "libresoc.v:118168.9-118168.17" case 1'1 case end @@ -181684,14 +183849,14 @@ module \dec58 sync always update \dec58_sv_in3 $0\dec58_sv_in3[2:0] end - attribute \src "libresoc.v:116576.3-116591.6" - process $proc$libresoc.v:116576$4397 + attribute \src "libresoc.v:118183.3-118198.6" + process $proc$libresoc.v:118183$4430 assign { } { } assign { } { } assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:116577.5-116577.29" + attribute \src "libresoc.v:118184.5-118184.29" switch \initial - attribute \src "libresoc.v:116577.9-116577.17" + attribute \src "libresoc.v:118184.9-118184.17" case 1'1 case end @@ -181715,14 +183880,14 @@ module \dec58 sync always update \dec58_sv_out $0\dec58_sv_out[2:0] end - attribute \src "libresoc.v:116592.3-116607.6" - process $proc$libresoc.v:116592$4398 + attribute \src "libresoc.v:118199.3-118214.6" + process $proc$libresoc.v:118199$4431 assign { } { } assign { } { } assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:116593.5-116593.29" + attribute \src "libresoc.v:118200.5-118200.29" switch \initial - attribute \src "libresoc.v:116593.9-116593.17" + attribute \src "libresoc.v:118200.9-118200.17" case 1'1 case end @@ -181746,14 +183911,14 @@ module \dec58 sync always update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end - attribute \src "libresoc.v:116608.3-116623.6" - process $proc$libresoc.v:116608$4399 + attribute \src "libresoc.v:118215.3-118230.6" + process $proc$libresoc.v:118215$4432 assign { } { } assign { } { } assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:116609.5-116609.29" + attribute \src "libresoc.v:118216.5-118216.29" switch \initial - attribute \src "libresoc.v:116609.9-116609.17" + attribute \src "libresoc.v:118216.9-118216.17" case 1'1 case end @@ -181777,14 +183942,14 @@ module \dec58 sync always update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end - attribute \src "libresoc.v:116624.3-116639.6" - process $proc$libresoc.v:116624$4400 + attribute \src "libresoc.v:118231.3-118246.6" + process $proc$libresoc.v:118231$4433 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:116625.5-116625.29" + attribute \src "libresoc.v:118232.5-118232.29" switch \initial - attribute \src "libresoc.v:116625.9-116625.17" + attribute \src "libresoc.v:118232.9-118232.17" case 1'1 case end @@ -181808,14 +183973,14 @@ module \dec58 sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "libresoc.v:116640.3-116655.6" - process $proc$libresoc.v:116640$4401 + attribute \src "libresoc.v:118247.3-118262.6" + process $proc$libresoc.v:118247$4434 assign { } { } assign { } { } assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:116641.5-116641.29" + attribute \src "libresoc.v:118248.5-118248.29" switch \initial - attribute \src "libresoc.v:116641.9-116641.17" + attribute \src "libresoc.v:118248.9-118248.17" case 1'1 case end @@ -181839,14 +184004,14 @@ module \dec58 sync always update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:116656.3-116671.6" - process $proc$libresoc.v:116656$4402 + attribute \src "libresoc.v:118263.3-118278.6" + process $proc$libresoc.v:118263$4435 assign { } { } assign { } { } assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:116657.5-116657.29" + attribute \src "libresoc.v:118264.5-118264.29" switch \initial - attribute \src "libresoc.v:116657.9-116657.17" + attribute \src "libresoc.v:118264.9-118264.17" case 1'1 case end @@ -181870,14 +184035,14 @@ module \dec58 sync always update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:116672.3-116687.6" - process $proc$libresoc.v:116672$4403 + attribute \src "libresoc.v:118279.3-118294.6" + process $proc$libresoc.v:118279$4436 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:116673.5-116673.29" + attribute \src "libresoc.v:118280.5-118280.29" switch \initial - attribute \src "libresoc.v:116673.9-116673.17" + attribute \src "libresoc.v:118280.9-118280.17" case 1'1 case end @@ -181901,14 +184066,14 @@ module \dec58 sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "libresoc.v:116688.3-116703.6" - process $proc$libresoc.v:116688$4404 + attribute \src "libresoc.v:118295.3-118310.6" + process $proc$libresoc.v:118295$4437 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:116689.5-116689.29" + attribute \src "libresoc.v:118296.5-118296.29" switch \initial - attribute \src "libresoc.v:116689.9-116689.17" + attribute \src "libresoc.v:118296.9-118296.17" case 1'1 case end @@ -181932,14 +184097,14 @@ module \dec58 sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "libresoc.v:116704.3-116719.6" - process $proc$libresoc.v:116704$4405 + attribute \src "libresoc.v:118311.3-118326.6" + process $proc$libresoc.v:118311$4438 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:116705.5-116705.29" + attribute \src "libresoc.v:118312.5-118312.29" switch \initial - attribute \src "libresoc.v:116705.9-116705.17" + attribute \src "libresoc.v:118312.9-118312.17" case 1'1 case end @@ -181963,14 +184128,14 @@ module \dec58 sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:116720.3-116735.6" - process $proc$libresoc.v:116720$4406 + attribute \src "libresoc.v:118327.3-118342.6" + process $proc$libresoc.v:118327$4439 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:116721.5-116721.29" + attribute \src "libresoc.v:118328.5-118328.29" switch \initial - attribute \src "libresoc.v:116721.9-116721.17" + attribute \src "libresoc.v:118328.9-118328.17" case 1'1 case end @@ -181994,14 +184159,14 @@ module \dec58 sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "libresoc.v:116736.3-116751.6" - process $proc$libresoc.v:116736$4407 + attribute \src "libresoc.v:118343.3-118358.6" + process $proc$libresoc.v:118343$4440 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:116737.5-116737.29" + attribute \src "libresoc.v:118344.5-118344.29" switch \initial - attribute \src "libresoc.v:116737.9-116737.17" + attribute \src "libresoc.v:118344.9-118344.17" case 1'1 case end @@ -182025,14 +184190,14 @@ module \dec58 sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:116752.3-116767.6" - process $proc$libresoc.v:116752$4408 + attribute \src "libresoc.v:118359.3-118374.6" + process $proc$libresoc.v:118359$4441 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:116753.5-116753.29" + attribute \src "libresoc.v:118360.5-118360.29" switch \initial - attribute \src "libresoc.v:116753.9-116753.17" + attribute \src "libresoc.v:118360.9-118360.17" case 1'1 case end @@ -182056,14 +184221,14 @@ module \dec58 sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:116768.3-116783.6" - process $proc$libresoc.v:116768$4409 + attribute \src "libresoc.v:118375.3-118390.6" + process $proc$libresoc.v:118375$4442 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:116769.5-116769.29" + attribute \src "libresoc.v:118376.5-118376.29" switch \initial - attribute \src "libresoc.v:116769.9-116769.17" + attribute \src "libresoc.v:118376.9-118376.17" case 1'1 case end @@ -182087,14 +184252,14 @@ module \dec58 sync always update \dec58_br $0\dec58_br[0:0] end - attribute \src "libresoc.v:116784.3-116799.6" - process $proc$libresoc.v:116784$4410 + attribute \src "libresoc.v:118391.3-118406.6" + process $proc$libresoc.v:118391$4443 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:116785.5-116785.29" + attribute \src "libresoc.v:118392.5-118392.29" switch \initial - attribute \src "libresoc.v:116785.9-116785.17" + attribute \src "libresoc.v:118392.9-118392.17" case 1'1 case end @@ -182118,14 +184283,14 @@ module \dec58 sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:116800.3-116815.6" - process $proc$libresoc.v:116800$4411 + attribute \src "libresoc.v:118407.3-118422.6" + process $proc$libresoc.v:118407$4444 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:116801.5-116801.29" + attribute \src "libresoc.v:118408.5-118408.29" switch \initial - attribute \src "libresoc.v:116801.9-116801.17" + attribute \src "libresoc.v:118408.9-118408.17" case 1'1 case end @@ -182149,14 +184314,14 @@ module \dec58 sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "libresoc.v:116816.3-116831.6" - process $proc$libresoc.v:116816$4412 + attribute \src "libresoc.v:118423.3-118438.6" + process $proc$libresoc.v:118423$4445 assign { } { } assign { } { } assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:116817.5-116817.29" + attribute \src "libresoc.v:118424.5-118424.29" switch \initial - attribute \src "libresoc.v:116817.9-116817.17" + attribute \src "libresoc.v:118424.9-118424.17" case 1'1 case end @@ -182180,14 +184345,14 @@ module \dec58 sync always update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "libresoc.v:116832.3-116847.6" - process $proc$libresoc.v:116832$4413 + attribute \src "libresoc.v:118439.3-118454.6" + process $proc$libresoc.v:118439$4446 assign { } { } assign { } { } assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:116833.5-116833.29" + attribute \src "libresoc.v:118440.5-118440.29" switch \initial - attribute \src "libresoc.v:116833.9-116833.17" + attribute \src "libresoc.v:118440.9-118440.17" case 1'1 case end @@ -182211,14 +184376,14 @@ module \dec58 sync always update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:116848.3-116863.6" - process $proc$libresoc.v:116848$4414 + attribute \src "libresoc.v:118455.3-118470.6" + process $proc$libresoc.v:118455$4447 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:116849.5-116849.29" + attribute \src "libresoc.v:118456.5-118456.29" switch \initial - attribute \src "libresoc.v:116849.9-116849.17" + attribute \src "libresoc.v:118456.9-118456.17" case 1'1 case end @@ -182242,14 +184407,14 @@ module \dec58 sync always update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:116864.3-116879.6" - process $proc$libresoc.v:116864$4415 + attribute \src "libresoc.v:118471.3-118486.6" + process $proc$libresoc.v:118471$4448 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:116865.5-116865.29" + attribute \src "libresoc.v:118472.5-118472.29" switch \initial - attribute \src "libresoc.v:116865.9-116865.17" + attribute \src "libresoc.v:118472.9-118472.17" case 1'1 case end @@ -182273,14 +184438,14 @@ module \dec58 sync always update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "libresoc.v:116880.3-116895.6" - process $proc$libresoc.v:116880$4416 + attribute \src "libresoc.v:118487.3-118502.6" + process $proc$libresoc.v:118487$4449 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:116881.5-116881.29" + attribute \src "libresoc.v:118488.5-118488.29" switch \initial - attribute \src "libresoc.v:116881.9-116881.17" + attribute \src "libresoc.v:118488.9-118488.17" case 1'1 case end @@ -182304,14 +184469,14 @@ module \dec58 sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "libresoc.v:116896.3-116911.6" - process $proc$libresoc.v:116896$4417 + attribute \src "libresoc.v:118503.3-118518.6" + process $proc$libresoc.v:118503$4450 assign { } { } assign { } { } assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:116897.5-116897.29" + attribute \src "libresoc.v:118504.5-118504.29" switch \initial - attribute \src "libresoc.v:116897.9-116897.17" + attribute \src "libresoc.v:118504.9-118504.17" case 1'1 case end @@ -182335,14 +184500,14 @@ module \dec58 sync always update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end - attribute \src "libresoc.v:116912.3-116927.6" - process $proc$libresoc.v:116912$4418 + attribute \src "libresoc.v:118519.3-118534.6" + process $proc$libresoc.v:118519$4451 assign { } { } assign { } { } assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:116913.5-116913.29" + attribute \src "libresoc.v:118520.5-118520.29" switch \initial - attribute \src "libresoc.v:116913.9-116913.17" + attribute \src "libresoc.v:118520.9-118520.17" case 1'1 case end @@ -182366,14 +184531,14 @@ module \dec58 sync always update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end - attribute \src "libresoc.v:116928.3-116943.6" - process $proc$libresoc.v:116928$4419 + attribute \src "libresoc.v:118535.3-118550.6" + process $proc$libresoc.v:118535$4452 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:116929.5-116929.29" + attribute \src "libresoc.v:118536.5-118536.29" switch \initial - attribute \src "libresoc.v:116929.9-116929.17" + attribute \src "libresoc.v:118536.9-118536.17" case 1'1 case end @@ -182397,14 +184562,14 @@ module \dec58 sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:116944.3-116959.6" - process $proc$libresoc.v:116944$4420 + attribute \src "libresoc.v:118551.3-118566.6" + process $proc$libresoc.v:118551$4453 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:116945.5-116945.29" + attribute \src "libresoc.v:118552.5-118552.29" switch \initial - attribute \src "libresoc.v:116945.9-116945.17" + attribute \src "libresoc.v:118552.9-118552.17" case 1'1 case end @@ -182428,14 +184593,14 @@ module \dec58 sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:116960.3-116975.6" - process $proc$libresoc.v:116960$4421 + attribute \src "libresoc.v:118567.3-118582.6" + process $proc$libresoc.v:118567$4454 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:116961.5-116961.29" + attribute \src "libresoc.v:118568.5-118568.29" switch \initial - attribute \src "libresoc.v:116961.9-116961.17" + attribute \src "libresoc.v:118568.9-118568.17" case 1'1 case end @@ -182459,14 +184624,14 @@ module \dec58 sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "libresoc.v:116976.3-116991.6" - process $proc$libresoc.v:116976$4422 + attribute \src "libresoc.v:118583.3-118598.6" + process $proc$libresoc.v:118583$4455 assign { } { } assign { } { } - assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:116977.5-116977.29" + assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] + attribute \src "libresoc.v:118584.5-118584.29" switch \initial - attribute \src "libresoc.v:116977.9-116977.17" + attribute \src "libresoc.v:118584.9-118584.17" case 1'1 case end @@ -182475,157 +184640,157 @@ module \dec58 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 + assign $1\dec58_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 + assign $1\dec58_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 + assign $1\dec58_out_sel[2:0] 3'001 case - assign $1\dec58_out_sel[1:0] 2'00 + assign $1\dec58_out_sel[2:0] 3'000 end sync always - update \dec58_out_sel $0\dec58_out_sel[1:0] + update \dec58_out_sel $0\dec58_out_sel[2:0] end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:116997.1-117750.10" +attribute \src "libresoc.v:118604.1-119360.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 - attribute \src "libresoc.v:117671.3-117683.6" + attribute \src "libresoc.v:119281.3-119293.6" wire width 2 $0\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:117684.3-117696.6" + attribute \src "libresoc.v:119294.3-119306.6" wire width 2 $0\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:117515.3-117527.6" + attribute \src "libresoc.v:119125.3-119137.6" wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:117567.3-117579.6" + attribute \src "libresoc.v:119177.3-119189.6" wire $0\dec62_br[0:0] - attribute \src "libresoc.v:117346.3-117358.6" + attribute \src "libresoc.v:118956.3-118968.6" wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:117359.3-117371.6" + attribute \src "libresoc.v:118969.3-118981.6" wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:117502.3-117514.6" + attribute \src "libresoc.v:119112.3-119124.6" wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:117554.3-117566.6" + attribute \src "libresoc.v:119164.3-119176.6" wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:117619.3-117631.6" + attribute \src "libresoc.v:119229.3-119241.6" wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:117333.3-117345.6" - wire width 13 $0\dec62_function_unit[12:0] - attribute \src "libresoc.v:117697.3-117709.6" + attribute \src "libresoc.v:118943.3-118955.6" + wire width 14 $0\dec62_function_unit[13:0] + attribute \src "libresoc.v:119307.3-119319.6" wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:117710.3-117722.6" + attribute \src "libresoc.v:119320.3-119332.6" wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:117723.3-117735.6" + attribute \src "libresoc.v:119333.3-119345.6" wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:117476.3-117488.6" + attribute \src "libresoc.v:119086.3-119098.6" wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:117528.3-117540.6" + attribute \src "libresoc.v:119138.3-119150.6" wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:117541.3-117553.6" + attribute \src "libresoc.v:119151.3-119163.6" wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:117606.3-117618.6" + attribute \src "libresoc.v:119216.3-119228.6" wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:117450.3-117462.6" + attribute \src "libresoc.v:119060.3-119072.6" wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:117645.3-117657.6" + attribute \src "libresoc.v:119255.3-119267.6" wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:117736.3-117748.6" - wire width 2 $0\dec62_out_sel[1:0] - attribute \src "libresoc.v:117489.3-117501.6" + attribute \src "libresoc.v:119346.3-119358.6" + wire width 3 $0\dec62_out_sel[2:0] + attribute \src "libresoc.v:119099.3-119111.6" wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:117593.3-117605.6" + attribute \src "libresoc.v:119203.3-119215.6" wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:117658.3-117670.6" + attribute \src "libresoc.v:119268.3-119280.6" wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:117632.3-117644.6" + attribute \src "libresoc.v:119242.3-119254.6" wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:117580.3-117592.6" + attribute \src "libresoc.v:119190.3-119202.6" wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:117424.3-117436.6" + attribute \src "libresoc.v:119034.3-119046.6" wire width 3 $0\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:117437.3-117449.6" + attribute \src "libresoc.v:119047.3-119059.6" wire width 3 $0\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:117372.3-117384.6" + attribute \src "libresoc.v:118982.3-118994.6" wire width 3 $0\dec62_sv_in1[2:0] - attribute \src "libresoc.v:117385.3-117397.6" + attribute \src "libresoc.v:118995.3-119007.6" wire width 3 $0\dec62_sv_in2[2:0] - attribute \src "libresoc.v:117398.3-117410.6" + attribute \src "libresoc.v:119008.3-119020.6" wire width 3 $0\dec62_sv_in3[2:0] - attribute \src "libresoc.v:117411.3-117423.6" + attribute \src "libresoc.v:119021.3-119033.6" wire width 3 $0\dec62_sv_out[2:0] - attribute \src "libresoc.v:117463.3-117475.6" + attribute \src "libresoc.v:119073.3-119085.6" wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:116998.7-116998.20" + attribute \src "libresoc.v:118605.7-118605.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117671.3-117683.6" + attribute \src "libresoc.v:119281.3-119293.6" wire width 2 $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:117684.3-117696.6" + attribute \src "libresoc.v:119294.3-119306.6" wire width 2 $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:117515.3-117527.6" + attribute \src "libresoc.v:119125.3-119137.6" wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:117567.3-117579.6" + attribute \src "libresoc.v:119177.3-119189.6" wire $1\dec62_br[0:0] - attribute \src "libresoc.v:117346.3-117358.6" + attribute \src "libresoc.v:118956.3-118968.6" wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:117359.3-117371.6" + attribute \src "libresoc.v:118969.3-118981.6" wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:117502.3-117514.6" + attribute \src "libresoc.v:119112.3-119124.6" wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:117554.3-117566.6" + attribute \src "libresoc.v:119164.3-119176.6" wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:117619.3-117631.6" + attribute \src "libresoc.v:119229.3-119241.6" wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:117333.3-117345.6" - wire width 13 $1\dec62_function_unit[12:0] - attribute \src "libresoc.v:117697.3-117709.6" + attribute \src "libresoc.v:118943.3-118955.6" + wire width 14 $1\dec62_function_unit[13:0] + attribute \src "libresoc.v:119307.3-119319.6" wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:117710.3-117722.6" + attribute \src "libresoc.v:119320.3-119332.6" wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:117723.3-117735.6" + attribute \src "libresoc.v:119333.3-119345.6" wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:117476.3-117488.6" + attribute \src "libresoc.v:119086.3-119098.6" wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:117528.3-117540.6" + attribute \src "libresoc.v:119138.3-119150.6" wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:117541.3-117553.6" + attribute \src "libresoc.v:119151.3-119163.6" wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:117606.3-117618.6" + attribute \src "libresoc.v:119216.3-119228.6" wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:117450.3-117462.6" + attribute \src "libresoc.v:119060.3-119072.6" wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:117645.3-117657.6" + attribute \src "libresoc.v:119255.3-119267.6" wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:117736.3-117748.6" - wire width 2 $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:117489.3-117501.6" + attribute \src "libresoc.v:119346.3-119358.6" + wire width 3 $1\dec62_out_sel[2:0] + attribute \src "libresoc.v:119099.3-119111.6" wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:117593.3-117605.6" + attribute \src "libresoc.v:119203.3-119215.6" wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:117658.3-117670.6" + attribute \src "libresoc.v:119268.3-119280.6" wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:117632.3-117644.6" + attribute \src "libresoc.v:119242.3-119254.6" wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:117580.3-117592.6" + attribute \src "libresoc.v:119190.3-119202.6" wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:117424.3-117436.6" + attribute \src "libresoc.v:119034.3-119046.6" wire width 3 $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:117437.3-117449.6" + attribute \src "libresoc.v:119047.3-119059.6" wire width 3 $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:117372.3-117384.6" + attribute \src "libresoc.v:118982.3-118994.6" wire width 3 $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:117385.3-117397.6" + attribute \src "libresoc.v:118995.3-119007.6" wire width 3 $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:117398.3-117410.6" + attribute \src "libresoc.v:119008.3-119020.6" wire width 3 $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:117411.3-117423.6" + attribute \src "libresoc.v:119021.3-119033.6" wire width 3 $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:117463.3-117475.6" + attribute \src "libresoc.v:119073.3-119085.6" wire width 2 $1\dec62_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -182705,21 +184870,22 @@ module \dec62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec62_form attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 1 \dec62_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 output 1 \dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -182825,6 +184991,7 @@ module \dec62 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 output 2 \dec62_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -182844,12 +185011,13 @@ module \dec62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 31 \dec62_lk attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 10 \dec62_out_sel + wire width 3 output 10 \dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -182925,28 +185093,28 @@ module \dec62 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec62_upd - attribute \src "libresoc.v:116998.7-116998.15" + attribute \src "libresoc.v:118605.7-118605.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 2 \opcode_switch - attribute \src "libresoc.v:116998.7-116998.20" - process $proc$libresoc.v:116998$4456 + attribute \src "libresoc.v:118605.7-118605.20" + process $proc$libresoc.v:118605$4489 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117333.3-117345.6" - process $proc$libresoc.v:117333$4424 + attribute \src "libresoc.v:118943.3-118955.6" + process $proc$libresoc.v:118943$4457 assign { } { } assign { } { } - assign $0\dec62_function_unit[12:0] $1\dec62_function_unit[12:0] - attribute \src "libresoc.v:117334.5-117334.29" + assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] + attribute \src "libresoc.v:118944.5-118944.29" switch \initial - attribute \src "libresoc.v:117334.9-117334.17" + attribute \src "libresoc.v:118944.9-118944.17" case 1'1 case end @@ -182955,25 +185123,25 @@ module \dec62 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_function_unit[12:0] 13'0000000000100 + assign $1\dec62_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_function_unit[12:0] 13'0000000000100 + assign $1\dec62_function_unit[13:0] 14'00000000000100 case - assign $1\dec62_function_unit[12:0] 13'0000000000000 + assign $1\dec62_function_unit[13:0] 14'00000000000000 end sync always - update \dec62_function_unit $0\dec62_function_unit[12:0] + update \dec62_function_unit $0\dec62_function_unit[13:0] end - attribute \src "libresoc.v:117346.3-117358.6" - process $proc$libresoc.v:117346$4425 + attribute \src "libresoc.v:118956.3-118968.6" + process $proc$libresoc.v:118956$4458 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:117347.5-117347.29" + attribute \src "libresoc.v:118957.5-118957.29" switch \initial - attribute \src "libresoc.v:117347.9-117347.17" + attribute \src "libresoc.v:118957.9-118957.17" case 1'1 case end @@ -182993,14 +185161,14 @@ module \dec62 sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:117359.3-117371.6" - process $proc$libresoc.v:117359$4426 + attribute \src "libresoc.v:118969.3-118981.6" + process $proc$libresoc.v:118969$4459 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:117360.5-117360.29" + attribute \src "libresoc.v:118970.5-118970.29" switch \initial - attribute \src "libresoc.v:117360.9-117360.17" + attribute \src "libresoc.v:118970.9-118970.17" case 1'1 case end @@ -183020,14 +185188,14 @@ module \dec62 sync always update \dec62_cr_out $0\dec62_cr_out[2:0] end - attribute \src "libresoc.v:117372.3-117384.6" - process $proc$libresoc.v:117372$4427 + attribute \src "libresoc.v:118982.3-118994.6" + process $proc$libresoc.v:118982$4460 assign { } { } assign { } { } assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:117373.5-117373.29" + attribute \src "libresoc.v:118983.5-118983.29" switch \initial - attribute \src "libresoc.v:117373.9-117373.17" + attribute \src "libresoc.v:118983.9-118983.17" case 1'1 case end @@ -183047,14 +185215,14 @@ module \dec62 sync always update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end - attribute \src "libresoc.v:117385.3-117397.6" - process $proc$libresoc.v:117385$4428 + attribute \src "libresoc.v:118995.3-119007.6" + process $proc$libresoc.v:118995$4461 assign { } { } assign { } { } assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:117386.5-117386.29" + attribute \src "libresoc.v:118996.5-118996.29" switch \initial - attribute \src "libresoc.v:117386.9-117386.17" + attribute \src "libresoc.v:118996.9-118996.17" case 1'1 case end @@ -183074,14 +185242,14 @@ module \dec62 sync always update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end - attribute \src "libresoc.v:117398.3-117410.6" - process $proc$libresoc.v:117398$4429 + attribute \src "libresoc.v:119008.3-119020.6" + process $proc$libresoc.v:119008$4462 assign { } { } assign { } { } assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:117399.5-117399.29" + attribute \src "libresoc.v:119009.5-119009.29" switch \initial - attribute \src "libresoc.v:117399.9-117399.17" + attribute \src "libresoc.v:119009.9-119009.17" case 1'1 case end @@ -183090,7 +185258,7 @@ module \dec62 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_sv_in3[2:0] 3'000 + assign $1\dec62_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } @@ -183101,14 +185269,14 @@ module \dec62 sync always update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end - attribute \src "libresoc.v:117411.3-117423.6" - process $proc$libresoc.v:117411$4430 + attribute \src "libresoc.v:119021.3-119033.6" + process $proc$libresoc.v:119021$4463 assign { } { } assign { } { } assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:117412.5-117412.29" + attribute \src "libresoc.v:119022.5-119022.29" switch \initial - attribute \src "libresoc.v:117412.9-117412.17" + attribute \src "libresoc.v:119022.9-119022.17" case 1'1 case end @@ -183128,14 +185296,14 @@ module \dec62 sync always update \dec62_sv_out $0\dec62_sv_out[2:0] end - attribute \src "libresoc.v:117424.3-117436.6" - process $proc$libresoc.v:117424$4431 + attribute \src "libresoc.v:119034.3-119046.6" + process $proc$libresoc.v:119034$4464 assign { } { } assign { } { } assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:117425.5-117425.29" + attribute \src "libresoc.v:119035.5-119035.29" switch \initial - attribute \src "libresoc.v:117425.9-117425.17" + attribute \src "libresoc.v:119035.9-119035.17" case 1'1 case end @@ -183155,14 +185323,14 @@ module \dec62 sync always update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end - attribute \src "libresoc.v:117437.3-117449.6" - process $proc$libresoc.v:117437$4432 + attribute \src "libresoc.v:119047.3-119059.6" + process $proc$libresoc.v:119047$4465 assign { } { } assign { } { } assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:117438.5-117438.29" + attribute \src "libresoc.v:119048.5-119048.29" switch \initial - attribute \src "libresoc.v:117438.9-117438.17" + attribute \src "libresoc.v:119048.9-119048.17" case 1'1 case end @@ -183182,14 +185350,14 @@ module \dec62 sync always update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end - attribute \src "libresoc.v:117450.3-117462.6" - process $proc$libresoc.v:117450$4433 + attribute \src "libresoc.v:119060.3-119072.6" + process $proc$libresoc.v:119060$4466 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:117451.5-117451.29" + attribute \src "libresoc.v:119061.5-119061.29" switch \initial - attribute \src "libresoc.v:117451.9-117451.17" + attribute \src "libresoc.v:119061.9-119061.17" case 1'1 case end @@ -183209,14 +185377,14 @@ module \dec62 sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:117463.3-117475.6" - process $proc$libresoc.v:117463$4434 + attribute \src "libresoc.v:119073.3-119085.6" + process $proc$libresoc.v:119073$4467 assign { } { } assign { } { } assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:117464.5-117464.29" + attribute \src "libresoc.v:119074.5-119074.29" switch \initial - attribute \src "libresoc.v:117464.9-117464.17" + attribute \src "libresoc.v:119074.9-119074.17" case 1'1 case end @@ -183236,14 +185404,14 @@ module \dec62 sync always update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:117476.3-117488.6" - process $proc$libresoc.v:117476$4435 + attribute \src "libresoc.v:119086.3-119098.6" + process $proc$libresoc.v:119086$4468 assign { } { } assign { } { } assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:117477.5-117477.29" + attribute \src "libresoc.v:119087.5-119087.29" switch \initial - attribute \src "libresoc.v:117477.9-117477.17" + attribute \src "libresoc.v:119087.9-119087.17" case 1'1 case end @@ -183263,14 +185431,14 @@ module \dec62 sync always update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:117489.3-117501.6" - process $proc$libresoc.v:117489$4436 + attribute \src "libresoc.v:119099.3-119111.6" + process $proc$libresoc.v:119099$4469 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:117490.5-117490.29" + attribute \src "libresoc.v:119100.5-119100.29" switch \initial - attribute \src "libresoc.v:117490.9-117490.17" + attribute \src "libresoc.v:119100.9-119100.17" case 1'1 case end @@ -183290,14 +185458,14 @@ module \dec62 sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:117502.3-117514.6" - process $proc$libresoc.v:117502$4437 + attribute \src "libresoc.v:119112.3-119124.6" + process $proc$libresoc.v:119112$4470 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:117503.5-117503.29" + attribute \src "libresoc.v:119113.5-119113.29" switch \initial - attribute \src "libresoc.v:117503.9-117503.17" + attribute \src "libresoc.v:119113.9-119113.17" case 1'1 case end @@ -183317,14 +185485,14 @@ module \dec62 sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:117515.3-117527.6" - process $proc$libresoc.v:117515$4438 + attribute \src "libresoc.v:119125.3-119137.6" + process $proc$libresoc.v:119125$4471 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:117516.5-117516.29" + attribute \src "libresoc.v:119126.5-119126.29" switch \initial - attribute \src "libresoc.v:117516.9-117516.17" + attribute \src "libresoc.v:119126.9-119126.17" case 1'1 case end @@ -183344,14 +185512,14 @@ module \dec62 sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:117528.3-117540.6" - process $proc$libresoc.v:117528$4439 + attribute \src "libresoc.v:119138.3-119150.6" + process $proc$libresoc.v:119138$4472 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:117529.5-117529.29" + attribute \src "libresoc.v:119139.5-119139.29" switch \initial - attribute \src "libresoc.v:117529.9-117529.17" + attribute \src "libresoc.v:119139.9-119139.17" case 1'1 case end @@ -183371,14 +185539,14 @@ module \dec62 sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:117541.3-117553.6" - process $proc$libresoc.v:117541$4440 + attribute \src "libresoc.v:119151.3-119163.6" + process $proc$libresoc.v:119151$4473 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:117542.5-117542.29" + attribute \src "libresoc.v:119152.5-119152.29" switch \initial - attribute \src "libresoc.v:117542.9-117542.17" + attribute \src "libresoc.v:119152.9-119152.17" case 1'1 case end @@ -183398,14 +185566,14 @@ module \dec62 sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "libresoc.v:117554.3-117566.6" - process $proc$libresoc.v:117554$4441 + attribute \src "libresoc.v:119164.3-119176.6" + process $proc$libresoc.v:119164$4474 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:117555.5-117555.29" + attribute \src "libresoc.v:119165.5-119165.29" switch \initial - attribute \src "libresoc.v:117555.9-117555.17" + attribute \src "libresoc.v:119165.9-119165.17" case 1'1 case end @@ -183425,14 +185593,14 @@ module \dec62 sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "libresoc.v:117567.3-117579.6" - process $proc$libresoc.v:117567$4442 + attribute \src "libresoc.v:119177.3-119189.6" + process $proc$libresoc.v:119177$4475 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:117568.5-117568.29" + attribute \src "libresoc.v:119178.5-119178.29" switch \initial - attribute \src "libresoc.v:117568.9-117568.17" + attribute \src "libresoc.v:119178.9-119178.17" case 1'1 case end @@ -183452,14 +185620,14 @@ module \dec62 sync always update \dec62_br $0\dec62_br[0:0] end - attribute \src "libresoc.v:117580.3-117592.6" - process $proc$libresoc.v:117580$4443 + attribute \src "libresoc.v:119190.3-119202.6" + process $proc$libresoc.v:119190$4476 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:117581.5-117581.29" + attribute \src "libresoc.v:119191.5-119191.29" switch \initial - attribute \src "libresoc.v:117581.9-117581.17" + attribute \src "libresoc.v:119191.9-119191.17" case 1'1 case end @@ -183479,14 +185647,14 @@ module \dec62 sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:117593.3-117605.6" - process $proc$libresoc.v:117593$4444 + attribute \src "libresoc.v:119203.3-119215.6" + process $proc$libresoc.v:119203$4477 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:117594.5-117594.29" + attribute \src "libresoc.v:119204.5-119204.29" switch \initial - attribute \src "libresoc.v:117594.9-117594.17" + attribute \src "libresoc.v:119204.9-119204.17" case 1'1 case end @@ -183506,14 +185674,14 @@ module \dec62 sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:117606.3-117618.6" - process $proc$libresoc.v:117606$4445 + attribute \src "libresoc.v:119216.3-119228.6" + process $proc$libresoc.v:119216$4478 assign { } { } assign { } { } assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:117607.5-117607.29" + attribute \src "libresoc.v:119217.5-119217.29" switch \initial - attribute \src "libresoc.v:117607.9-117607.17" + attribute \src "libresoc.v:119217.9-119217.17" case 1'1 case end @@ -183533,14 +185701,14 @@ module \dec62 sync always update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "libresoc.v:117619.3-117631.6" - process $proc$libresoc.v:117619$4446 + attribute \src "libresoc.v:119229.3-119241.6" + process $proc$libresoc.v:119229$4479 assign { } { } assign { } { } assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:117620.5-117620.29" + attribute \src "libresoc.v:119230.5-119230.29" switch \initial - attribute \src "libresoc.v:117620.9-117620.17" + attribute \src "libresoc.v:119230.9-119230.17" case 1'1 case end @@ -183560,14 +185728,14 @@ module \dec62 sync always update \dec62_form $0\dec62_form[4:0] end - attribute \src "libresoc.v:117632.3-117644.6" - process $proc$libresoc.v:117632$4447 + attribute \src "libresoc.v:119242.3-119254.6" + process $proc$libresoc.v:119242$4480 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:117633.5-117633.29" + attribute \src "libresoc.v:119243.5-119243.29" switch \initial - attribute \src "libresoc.v:117633.9-117633.17" + attribute \src "libresoc.v:119243.9-119243.17" case 1'1 case end @@ -183587,14 +185755,14 @@ module \dec62 sync always update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "libresoc.v:117645.3-117657.6" - process $proc$libresoc.v:117645$4448 + attribute \src "libresoc.v:119255.3-119267.6" + process $proc$libresoc.v:119255$4481 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:117646.5-117646.29" + attribute \src "libresoc.v:119256.5-119256.29" switch \initial - attribute \src "libresoc.v:117646.9-117646.17" + attribute \src "libresoc.v:119256.9-119256.17" case 1'1 case end @@ -183614,14 +185782,14 @@ module \dec62 sync always update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "libresoc.v:117658.3-117670.6" - process $proc$libresoc.v:117658$4449 + attribute \src "libresoc.v:119268.3-119280.6" + process $proc$libresoc.v:119268$4482 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:117659.5-117659.29" + attribute \src "libresoc.v:119269.5-119269.29" switch \initial - attribute \src "libresoc.v:117659.9-117659.17" + attribute \src "libresoc.v:119269.9-119269.17" case 1'1 case end @@ -183641,14 +185809,14 @@ module \dec62 sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:117671.3-117683.6" - process $proc$libresoc.v:117671$4450 + attribute \src "libresoc.v:119281.3-119293.6" + process $proc$libresoc.v:119281$4483 assign { } { } assign { } { } assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:117672.5-117672.29" + attribute \src "libresoc.v:119282.5-119282.29" switch \initial - attribute \src "libresoc.v:117672.9-117672.17" + attribute \src "libresoc.v:119282.9-119282.17" case 1'1 case end @@ -183668,14 +185836,14 @@ module \dec62 sync always update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end - attribute \src "libresoc.v:117684.3-117696.6" - process $proc$libresoc.v:117684$4451 + attribute \src "libresoc.v:119294.3-119306.6" + process $proc$libresoc.v:119294$4484 assign { } { } assign { } { } assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:117685.5-117685.29" + attribute \src "libresoc.v:119295.5-119295.29" switch \initial - attribute \src "libresoc.v:117685.9-117685.17" + attribute \src "libresoc.v:119295.9-119295.17" case 1'1 case end @@ -183695,14 +185863,14 @@ module \dec62 sync always update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end - attribute \src "libresoc.v:117697.3-117709.6" - process $proc$libresoc.v:117697$4452 + attribute \src "libresoc.v:119307.3-119319.6" + process $proc$libresoc.v:119307$4485 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:117698.5-117698.29" + attribute \src "libresoc.v:119308.5-119308.29" switch \initial - attribute \src "libresoc.v:117698.9-117698.17" + attribute \src "libresoc.v:119308.9-119308.17" case 1'1 case end @@ -183722,14 +185890,14 @@ module \dec62 sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:117710.3-117722.6" - process $proc$libresoc.v:117710$4453 + attribute \src "libresoc.v:119320.3-119332.6" + process $proc$libresoc.v:119320$4486 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:117711.5-117711.29" + attribute \src "libresoc.v:119321.5-119321.29" switch \initial - attribute \src "libresoc.v:117711.9-117711.17" + attribute \src "libresoc.v:119321.9-119321.17" case 1'1 case end @@ -183749,14 +185917,14 @@ module \dec62 sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:117723.3-117735.6" - process $proc$libresoc.v:117723$4454 + attribute \src "libresoc.v:119333.3-119345.6" + process $proc$libresoc.v:119333$4487 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:117724.5-117724.29" + attribute \src "libresoc.v:119334.5-119334.29" switch \initial - attribute \src "libresoc.v:117724.9-117724.17" + attribute \src "libresoc.v:119334.9-119334.17" case 1'1 case end @@ -183776,14 +185944,14 @@ module \dec62 sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:117736.3-117748.6" - process $proc$libresoc.v:117736$4455 + attribute \src "libresoc.v:119346.3-119358.6" + process $proc$libresoc.v:119346$4488 assign { } { } assign { } { } - assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:117737.5-117737.29" + assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] + attribute \src "libresoc.v:119347.5-119347.29" switch \initial - attribute \src "libresoc.v:117737.9-117737.17" + attribute \src "libresoc.v:119347.9-119347.17" case 1'1 case end @@ -183792,164 +185960,165 @@ module \dec62 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 + assign $1\dec62_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 + assign $1\dec62_out_sel[2:0] 3'000 case - assign $1\dec62_out_sel[1:0] 2'00 + assign $1\dec62_out_sel[2:0] 3'000 end sync always - update \dec62_out_sel $0\dec62_out_sel[1:0] + update \dec62_out_sel $0\dec62_out_sel[2:0] end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:117754.1-118327.10" +attribute \src "libresoc.v:119364.1-119947.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU - attribute \src "libresoc.v:118291.3-118305.6" - wire width 13 $0\ALU__fn_unit[12:0] - attribute \src "libresoc.v:118278.3-118290.6" + attribute \src "libresoc.v:119910.3-119924.6" + wire width 14 $0\ALU__fn_unit[13:0] + attribute \src "libresoc.v:119897.3-119909.6" wire width 7 $0\ALU__insn_type[6:0] - attribute \src "libresoc.v:118263.3-118277.6" + attribute \src "libresoc.v:119882.3-119896.6" wire $0\ALU__write_cr0[0:0] - attribute \src "libresoc.v:117755.7-117755.20" + attribute \src "libresoc.v:119365.7-119365.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118291.3-118305.6" - wire width 13 $1\ALU__fn_unit[12:0] - attribute \src "libresoc.v:118278.3-118290.6" + attribute \src "libresoc.v:119910.3-119924.6" + wire width 14 $1\ALU__fn_unit[13:0] + attribute \src "libresoc.v:119897.3-119909.6" wire width 7 $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:118263.3-118277.6" + attribute \src "libresoc.v:119882.3-119896.6" wire $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:118180.18-118180.113" - wire $and$libresoc.v:118180$4457_Y - attribute \src "libresoc.v:118182.18-118182.110" - wire $and$libresoc.v:118182$4459_Y - attribute \src "libresoc.v:118195.18-118195.114" - wire $and$libresoc.v:118195$4472_Y - attribute \src "libresoc.v:118196.18-118196.116" - wire $and$libresoc.v:118196$4473_Y - attribute \src "libresoc.v:118198.18-118198.114" - wire $and$libresoc.v:118198$4475_Y - attribute \src "libresoc.v:118200.18-118200.110" - wire $and$libresoc.v:118200$4477_Y - attribute \src "libresoc.v:118201.17-118201.112" - wire $and$libresoc.v:118201$4478_Y - attribute \src "libresoc.v:118202.17-118202.114" - wire $and$libresoc.v:118202$4479_Y - attribute \src "libresoc.v:118183.18-118183.126" - wire $eq$libresoc.v:118183$4460_Y - attribute \src "libresoc.v:118184.18-118184.126" - wire $eq$libresoc.v:118184$4461_Y - attribute \src "libresoc.v:118186.18-118186.110" - wire $eq$libresoc.v:118186$4463_Y - attribute \src "libresoc.v:118187.18-118187.110" - wire $eq$libresoc.v:118187$4464_Y - attribute \src "libresoc.v:118189.18-118189.112" - wire $eq$libresoc.v:118189$4466_Y - attribute \src "libresoc.v:118190.17-118190.130" - wire $eq$libresoc.v:118190$4467_Y - attribute \src "libresoc.v:118192.18-118192.110" - wire $eq$libresoc.v:118192$4469_Y - attribute \src "libresoc.v:118194.18-118194.131" - wire $eq$libresoc.v:118194$4471_Y - attribute \src "libresoc.v:118197.18-118197.131" - wire $eq$libresoc.v:118197$4474_Y - attribute \src "libresoc.v:118203.17-118203.130" - wire $eq$libresoc.v:118203$4480_Y - attribute \src "libresoc.v:118181.18-118181.110" - wire $not$libresoc.v:118181$4458_Y - attribute \src "libresoc.v:118199.18-118199.110" - wire $not$libresoc.v:118199$4476_Y - attribute \src "libresoc.v:118185.18-118185.110" - wire $or$libresoc.v:118185$4462_Y - attribute \src "libresoc.v:118188.18-118188.110" - wire $or$libresoc.v:118188$4465_Y - attribute \src "libresoc.v:118191.18-118191.110" - wire $or$libresoc.v:118191$4468_Y - attribute \src "libresoc.v:118193.18-118193.110" - wire $or$libresoc.v:118193$4470_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "libresoc.v:119798.18-119798.113" + wire $and$libresoc.v:119798$4490_Y + attribute \src "libresoc.v:119800.18-119800.110" + wire $and$libresoc.v:119800$4492_Y + attribute \src "libresoc.v:119813.18-119813.114" + wire $and$libresoc.v:119813$4505_Y + attribute \src "libresoc.v:119814.18-119814.116" + wire $and$libresoc.v:119814$4506_Y + attribute \src "libresoc.v:119816.18-119816.114" + wire $and$libresoc.v:119816$4508_Y + attribute \src "libresoc.v:119818.18-119818.110" + wire $and$libresoc.v:119818$4510_Y + attribute \src "libresoc.v:119819.17-119819.112" + wire $and$libresoc.v:119819$4511_Y + attribute \src "libresoc.v:119820.17-119820.114" + wire $and$libresoc.v:119820$4512_Y + attribute \src "libresoc.v:119801.18-119801.126" + wire $eq$libresoc.v:119801$4493_Y + attribute \src "libresoc.v:119802.18-119802.126" + wire $eq$libresoc.v:119802$4494_Y + attribute \src "libresoc.v:119804.18-119804.110" + wire $eq$libresoc.v:119804$4496_Y + attribute \src "libresoc.v:119805.18-119805.110" + wire $eq$libresoc.v:119805$4497_Y + attribute \src "libresoc.v:119807.18-119807.112" + wire $eq$libresoc.v:119807$4499_Y + attribute \src "libresoc.v:119808.17-119808.130" + wire $eq$libresoc.v:119808$4500_Y + attribute \src "libresoc.v:119810.18-119810.110" + wire $eq$libresoc.v:119810$4502_Y + attribute \src "libresoc.v:119812.18-119812.131" + wire $eq$libresoc.v:119812$4504_Y + attribute \src "libresoc.v:119815.18-119815.131" + wire $eq$libresoc.v:119815$4507_Y + attribute \src "libresoc.v:119821.17-119821.130" + wire $eq$libresoc.v:119821$4513_Y + attribute \src "libresoc.v:119799.18-119799.110" + wire $not$libresoc.v:119799$4491_Y + attribute \src "libresoc.v:119817.18-119817.110" + wire $not$libresoc.v:119817$4509_Y + attribute \src "libresoc.v:119803.18-119803.110" + wire $or$libresoc.v:119803$4495_Y + attribute \src "libresoc.v:119806.18-119806.110" + wire $or$libresoc.v:119806$4498_Y + attribute \src "libresoc.v:119809.18-119809.110" + wire $or$libresoc.v:119809$4501_Y + attribute \src "libresoc.v:119811.18-119811.110" + wire $or$libresoc.v:119811$4503_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \ALU__data_len + wire width 4 output 19 \ALU__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 3 \ALU__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \ALU__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \ALU__imm_data__ok + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \ALU__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 14 \ALU__input_carry + wire width 2 output 15 \ALU__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \ALU__insn + wire width 32 output 20 \ALU__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -184024,30 +186193,31 @@ module \dec_ALU attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \ALU__insn_type + wire width 7 output 3 \ALU__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \ALU__invert_in + wire output 11 \ALU__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \ALU__invert_out + wire output 13 \ALU__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \ALU__is_32bit + wire output 17 \ALU__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \ALU__is_signed + wire output 18 \ALU__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \ALU__oe__oe + wire output 9 \ALU__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \ALU__oe__ok + wire output 10 \ALU__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \ALU__output_carry + wire output 16 \ALU__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \ALU__rc__ok + wire output 8 \ALU__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \ALU__rc__rc + wire output 7 \ALU__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \ALU__write_cr0 + wire output 14 \ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \ALU__zero_a + wire output 12 \ALU__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -184088,21 +186258,22 @@ module \dec_ALU attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_ALU_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_ALU_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -184202,6 +186373,7 @@ module \dec_ALU attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_ALU_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -184228,7 +186400,7 @@ module \dec_ALU wire \dec_ALU_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -184236,8 +186408,10 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -184257,7 +186431,7 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -184267,7 +186441,7 @@ module \dec_ALU attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -184279,24 +186453,26 @@ module \dec_ALU attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:117755.7-117755.15" + attribute \src "libresoc.v:119365.7-119365.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:118180$4457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:119798$4490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184304,10 +186480,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:118180$4457_Y + connect \Y $and$libresoc.v:119798$4490_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:118182$4459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:119800$4492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184315,10 +186491,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:118182$4459_Y + connect \Y $and$libresoc.v:119800$4492_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:118195$4472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:119813$4505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184326,10 +186502,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:118195$4472_Y + connect \Y $and$libresoc.v:119813$4505_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:118196$4473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:119814$4506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184337,10 +186513,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:118196$4473_Y + connect \Y $and$libresoc.v:119814$4506_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:118198$4475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:119816$4508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184348,10 +186524,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:118198$4475_Y + connect \Y $and$libresoc.v:119816$4508_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:118200$4477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:119818$4510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184359,10 +186535,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:118200$4477_Y + connect \Y $and$libresoc.v:119818$4510_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:118201$4478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:119819$4511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184370,10 +186546,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:118201$4478_Y + connect \Y $and$libresoc.v:119819$4511_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:118202$4479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:119820$4512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184381,10 +186557,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:118202$4479_Y + connect \Y $and$libresoc.v:119820$4512_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:118183$4460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:119801$4493 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -184392,10 +186568,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:118183$4460_Y + connect \Y $eq$libresoc.v:119801$4493_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:118184$4461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:119802$4494 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -184403,10 +186579,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:118184$4461_Y + connect \Y $eq$libresoc.v:119802$4494_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:118186$4463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:119804$4496 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -184414,10 +186590,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:118186$4463_Y + connect \Y $eq$libresoc.v:119804$4496_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:118187$4464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:119805$4497 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -184425,10 +186601,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:118187$4464_Y + connect \Y $eq$libresoc.v:119805$4497_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:118189$4466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:119807$4499 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -184436,21 +186612,21 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:118189$4466_Y + connect \Y $eq$libresoc.v:119807$4499_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:118190$4467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:119808$4500 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:118190$4467_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:119808$4500_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:118192$4469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:119810$4502 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -184458,59 +186634,59 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:118192$4469_Y + connect \Y $eq$libresoc.v:119810$4502_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:118194$4471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:119812$4504 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:118194$4471_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:119812$4504_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:118197$4474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:119815$4507 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:118197$4474_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:119815$4507_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:118203$4480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:119821$4513 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:118203$4480_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:119821$4513_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:118181$4458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:119799$4491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:118181$4458_Y + connect \Y $not$libresoc.v:119799$4491_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:118199$4476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:119817$4509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:118199$4476_Y + connect \Y $not$libresoc.v:119817$4509_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:118185$4462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:119803$4495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184518,10 +186694,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:118185$4462_Y + connect \Y $or$libresoc.v:119803$4495_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:118188$4465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:119806$4498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184529,10 +186705,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:118188$4465_Y + connect \Y $or$libresoc.v:119806$4498_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:118191$4468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:119809$4501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184540,10 +186716,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:118191$4468_Y + connect \Y $or$libresoc.v:119809$4501_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:118193$4470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:119811$4503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -184551,10 +186727,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:118193$4470_Y + connect \Y $or$libresoc.v:119811$4503_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:118204.7-118232.4" + attribute \src "libresoc.v:119822.7-119850.4" cell \dec \dec connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -184585,14 +186761,15 @@ module \dec_ALU connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:118233.10-118237.4" + attribute \src "libresoc.v:119851.10-119856.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:118238.10-118249.4" + attribute \src "libresoc.v:119857.10-119868.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -184606,7 +186783,7 @@ module \dec_ALU connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:118250.10-118256.4" + attribute \src "libresoc.v:119869.10-119875.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op @@ -184615,33 +186792,33 @@ module \dec_ALU connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:118257.10-118262.4" + attribute \src "libresoc.v:119876.10-119881.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:117755.7-117755.20" - process $proc$libresoc.v:117755$4484 + attribute \src "libresoc.v:119365.7-119365.20" + process $proc$libresoc.v:119365$4517 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118263.3-118277.6" - process $proc$libresoc.v:118263$4481 + attribute \src "libresoc.v:119882.3-119896.6" + process $proc$libresoc.v:119882$4514 assign { } { } assign { } { } assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:118264.5-118264.29" + attribute \src "libresoc.v:119883.5-119883.29" switch \initial - attribute \src "libresoc.v:118264.9-118264.17" + attribute \src "libresoc.v:119883.9-119883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch \dec_ALU_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -184657,18 +186834,18 @@ module \dec_ALU sync always update \ALU__write_cr0 $0\ALU__write_cr0[0:0] end - attribute \src "libresoc.v:118278.3-118290.6" - process $proc$libresoc.v:118278$4482 + attribute \src "libresoc.v:119897.3-119909.6" + process $proc$libresoc.v:119897$4515 assign { } { } assign { } { } assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:118279.5-118279.29" + attribute \src "libresoc.v:119898.5-119898.29" switch \initial - attribute \src "libresoc.v:118279.9-118279.17" + attribute \src "libresoc.v:119898.9-119898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -184684,58 +186861,58 @@ module \dec_ALU sync always update \ALU__insn_type $0\ALU__insn_type[6:0] end - attribute \src "libresoc.v:118291.3-118305.6" - process $proc$libresoc.v:118291$4483 + attribute \src "libresoc.v:119910.3-119924.6" + process $proc$libresoc.v:119910$4516 assign { } { } - assign $0\ALU__fn_unit[12:0] $1\ALU__fn_unit[12:0] - attribute \src "libresoc.v:118292.5-118292.29" + assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] + attribute \src "libresoc.v:119911.5-119911.29" switch \initial - attribute \src "libresoc.v:118292.9-118292.17" + attribute \src "libresoc.v:119911.9-119911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ALU__fn_unit[12:0] 13'0000000000000 + assign $1\ALU__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ALU__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ALU__fn_unit[12:0] \dec_ALU_function_unit - end - sync always - update \ALU__fn_unit $0\ALU__fn_unit[12:0] - end - connect \$10 $and$libresoc.v:118180$4457_Y - connect \$12 $not$libresoc.v:118181$4458_Y - connect \$14 $and$libresoc.v:118182$4459_Y - connect \$16 $eq$libresoc.v:118183$4460_Y - connect \$18 $eq$libresoc.v:118184$4461_Y - connect \$20 $or$libresoc.v:118185$4462_Y - connect \$22 $eq$libresoc.v:118186$4463_Y - connect \$24 $eq$libresoc.v:118187$4464_Y - connect \$26 $or$libresoc.v:118188$4465_Y - connect \$28 $eq$libresoc.v:118189$4466_Y - connect \$2 $eq$libresoc.v:118190$4467_Y - connect \$30 $or$libresoc.v:118191$4468_Y - connect \$32 $eq$libresoc.v:118192$4469_Y - connect \$34 $or$libresoc.v:118193$4470_Y - connect \$36 $eq$libresoc.v:118194$4471_Y - connect \$38 $and$libresoc.v:118195$4472_Y - connect \$40 $and$libresoc.v:118196$4473_Y - connect \$42 $eq$libresoc.v:118197$4474_Y - connect \$44 $and$libresoc.v:118198$4475_Y - connect \$46 $not$libresoc.v:118199$4476_Y - connect \$48 $and$libresoc.v:118200$4477_Y - connect \$4 $and$libresoc.v:118201$4478_Y - connect \$6 $and$libresoc.v:118202$4479_Y - connect \$8 $eq$libresoc.v:118203$4480_Y + assign $1\ALU__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ALU__fn_unit[13:0] \dec_ALU_function_unit + end + sync always + update \ALU__fn_unit $0\ALU__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:119798$4490_Y + connect \$12 $not$libresoc.v:119799$4491_Y + connect \$14 $and$libresoc.v:119800$4492_Y + connect \$16 $eq$libresoc.v:119801$4493_Y + connect \$18 $eq$libresoc.v:119802$4494_Y + connect \$20 $or$libresoc.v:119803$4495_Y + connect \$22 $eq$libresoc.v:119804$4496_Y + connect \$24 $eq$libresoc.v:119805$4497_Y + connect \$26 $or$libresoc.v:119806$4498_Y + connect \$28 $eq$libresoc.v:119807$4499_Y + connect \$2 $eq$libresoc.v:119808$4500_Y + connect \$30 $or$libresoc.v:119809$4501_Y + connect \$32 $eq$libresoc.v:119810$4502_Y + connect \$34 $or$libresoc.v:119811$4503_Y + connect \$36 $eq$libresoc.v:119812$4504_Y + connect \$38 $and$libresoc.v:119813$4505_Y + connect \$40 $and$libresoc.v:119814$4506_Y + connect \$42 $eq$libresoc.v:119815$4507_Y + connect \$44 $and$libresoc.v:119816$4508_Y + connect \$46 $not$libresoc.v:119817$4509_Y + connect \$48 $and$libresoc.v:119818$4510_Y + connect \$4 $and$libresoc.v:119819$4511_Y + connect \$6 $and$libresoc.v:119820$4512_Y + connect \$8 $eq$libresoc.v:119821$4513_Y connect \ALU__is_signed \dec_ALU_sgn connect \ALU__is_32bit \dec_ALU_is_32b connect \ALU__output_carry \dec_ALU_cry_out @@ -184749,6 +186926,7 @@ module \dec_ALU connect \dec_bi_sel_in \dec_ALU_in2_sel connect \ALU__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_ALU_in1_sel + connect \dec_ai_sv_nz \sv_a_nz connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_ALU_SPR [4:0] \dec_ALU_SPR [9:5] } @@ -184758,139 +186936,140 @@ module \dec_ALU connect \insn_in \dec_opcode_in connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:118331.1-118807.10" +attribute \src "libresoc.v:119951.1-120431.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH - attribute \src "libresoc.v:118757.3-118771.6" - wire width 13 $0\BRANCH__fn_unit[12:0] - attribute \src "libresoc.v:118782.3-118794.6" + attribute \src "libresoc.v:120381.3-120395.6" + wire width 14 $0\BRANCH__fn_unit[13:0] + attribute \src "libresoc.v:120406.3-120418.6" wire width 7 $0\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:118772.3-118781.6" + attribute \src "libresoc.v:120396.3-120405.6" wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:118332.7-118332.20" + attribute \src "libresoc.v:119952.7-119952.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118757.3-118771.6" - wire width 13 $1\BRANCH__fn_unit[12:0] - attribute \src "libresoc.v:118782.3-118794.6" + attribute \src "libresoc.v:120381.3-120395.6" + wire width 14 $1\BRANCH__fn_unit[13:0] + attribute \src "libresoc.v:120406.3-120418.6" wire width 7 $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:118772.3-118781.6" + attribute \src "libresoc.v:120396.3-120405.6" wire $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:118689.18-118689.113" - wire $and$libresoc.v:118689$4485_Y - attribute \src "libresoc.v:118691.18-118691.110" - wire $and$libresoc.v:118691$4487_Y - attribute \src "libresoc.v:118704.18-118704.114" - wire $and$libresoc.v:118704$4500_Y - attribute \src "libresoc.v:118705.18-118705.116" - wire $and$libresoc.v:118705$4501_Y - attribute \src "libresoc.v:118707.18-118707.114" - wire $and$libresoc.v:118707$4503_Y - attribute \src "libresoc.v:118709.18-118709.110" - wire $and$libresoc.v:118709$4505_Y - attribute \src "libresoc.v:118710.17-118710.112" - wire $and$libresoc.v:118710$4506_Y - attribute \src "libresoc.v:118711.17-118711.114" - wire $and$libresoc.v:118711$4507_Y - attribute \src "libresoc.v:118692.18-118692.129" - wire $eq$libresoc.v:118692$4488_Y - attribute \src "libresoc.v:118693.18-118693.129" - wire $eq$libresoc.v:118693$4489_Y - attribute \src "libresoc.v:118695.18-118695.110" - wire $eq$libresoc.v:118695$4491_Y - attribute \src "libresoc.v:118696.18-118696.110" - wire $eq$libresoc.v:118696$4492_Y - attribute \src "libresoc.v:118698.18-118698.112" - wire $eq$libresoc.v:118698$4494_Y - attribute \src "libresoc.v:118699.17-118699.133" - wire $eq$libresoc.v:118699$4495_Y - attribute \src "libresoc.v:118701.18-118701.110" - wire $eq$libresoc.v:118701$4497_Y - attribute \src "libresoc.v:118703.18-118703.134" - wire $eq$libresoc.v:118703$4499_Y - attribute \src "libresoc.v:118706.18-118706.134" - wire $eq$libresoc.v:118706$4502_Y - attribute \src "libresoc.v:118712.17-118712.133" - wire $eq$libresoc.v:118712$4508_Y - attribute \src "libresoc.v:118690.18-118690.110" - wire $not$libresoc.v:118690$4486_Y - attribute \src "libresoc.v:118708.18-118708.110" - wire $not$libresoc.v:118708$4504_Y - attribute \src "libresoc.v:118694.18-118694.110" - wire $or$libresoc.v:118694$4490_Y - attribute \src "libresoc.v:118697.18-118697.110" - wire $or$libresoc.v:118697$4493_Y - attribute \src "libresoc.v:118700.18-118700.110" - wire $or$libresoc.v:118700$4496_Y - attribute \src "libresoc.v:118702.18-118702.110" - wire $or$libresoc.v:118702$4498_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "libresoc.v:120313.18-120313.113" + wire $and$libresoc.v:120313$4518_Y + attribute \src "libresoc.v:120315.18-120315.110" + wire $and$libresoc.v:120315$4520_Y + attribute \src "libresoc.v:120328.18-120328.114" + wire $and$libresoc.v:120328$4533_Y + attribute \src "libresoc.v:120329.18-120329.116" + wire $and$libresoc.v:120329$4534_Y + attribute \src "libresoc.v:120331.18-120331.114" + wire $and$libresoc.v:120331$4536_Y + attribute \src "libresoc.v:120333.18-120333.110" + wire $and$libresoc.v:120333$4538_Y + attribute \src "libresoc.v:120334.17-120334.112" + wire $and$libresoc.v:120334$4539_Y + attribute \src "libresoc.v:120335.17-120335.114" + wire $and$libresoc.v:120335$4540_Y + attribute \src "libresoc.v:120316.18-120316.129" + wire $eq$libresoc.v:120316$4521_Y + attribute \src "libresoc.v:120317.18-120317.129" + wire $eq$libresoc.v:120317$4522_Y + attribute \src "libresoc.v:120319.18-120319.110" + wire $eq$libresoc.v:120319$4524_Y + attribute \src "libresoc.v:120320.18-120320.110" + wire $eq$libresoc.v:120320$4525_Y + attribute \src "libresoc.v:120322.18-120322.112" + wire $eq$libresoc.v:120322$4527_Y + attribute \src "libresoc.v:120323.17-120323.133" + wire $eq$libresoc.v:120323$4528_Y + attribute \src "libresoc.v:120325.18-120325.110" + wire $eq$libresoc.v:120325$4530_Y + attribute \src "libresoc.v:120327.18-120327.134" + wire $eq$libresoc.v:120327$4532_Y + attribute \src "libresoc.v:120330.18-120330.134" + wire $eq$libresoc.v:120330$4535_Y + attribute \src "libresoc.v:120336.17-120336.133" + wire $eq$libresoc.v:120336$4541_Y + attribute \src "libresoc.v:120314.18-120314.110" + wire $not$libresoc.v:120314$4519_Y + attribute \src "libresoc.v:120332.18-120332.110" + wire $not$libresoc.v:120332$4537_Y + attribute \src "libresoc.v:120318.18-120318.110" + wire $or$libresoc.v:120318$4523_Y + attribute \src "libresoc.v:120321.18-120321.110" + wire $or$libresoc.v:120321$4526_Y + attribute \src "libresoc.v:120324.18-120324.110" + wire $or$libresoc.v:120324$4529_Y + attribute \src "libresoc.v:120326.18-120326.110" + wire $or$libresoc.v:120326$4531_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 3 \BRANCH__cia attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 5 \BRANCH__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 5 \BRANCH__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \BRANCH__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -184971,6 +187150,7 @@ module \dec_BRANCH attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 4 \BRANCH__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -185011,21 +187191,22 @@ module \dec_BRANCH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_BRANCH_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_BRANCH_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -185117,6 +187298,7 @@ module \dec_BRANCH attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_BRANCH_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -185150,13 +187332,13 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 \dec_bi_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -185164,24 +187346,24 @@ module \dec_BRANCH attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:118332.7-118332.15" + attribute \src "libresoc.v:119952.7-119952.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 1 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:118689$4485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120313$4518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185189,10 +187371,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:118689$4485_Y + connect \Y $and$libresoc.v:120313$4518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:118691$4487 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120315$4520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185200,10 +187382,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:118691$4487_Y + connect \Y $and$libresoc.v:120315$4520_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:118704$4500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120328$4533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185211,10 +187393,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:118704$4500_Y + connect \Y $and$libresoc.v:120328$4533_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:118705$4501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120329$4534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185222,10 +187404,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:118705$4501_Y + connect \Y $and$libresoc.v:120329$4534_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:118707$4503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120331$4536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185233,10 +187415,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:118707$4503_Y + connect \Y $and$libresoc.v:120331$4536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:118709$4505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120333$4538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185244,10 +187426,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:118709$4505_Y + connect \Y $and$libresoc.v:120333$4538_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:118710$4506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120334$4539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185255,10 +187437,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:118710$4506_Y + connect \Y $and$libresoc.v:120334$4539_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:118711$4507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120335$4540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185266,10 +187448,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:118711$4507_Y + connect \Y $and$libresoc.v:120335$4540_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:118692$4488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:120316$4521 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185277,10 +187459,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:118692$4488_Y + connect \Y $eq$libresoc.v:120316$4521_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:118693$4489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:120317$4522 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185288,10 +187470,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:118693$4489_Y + connect \Y $eq$libresoc.v:120317$4522_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:118695$4491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120319$4524 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -185299,10 +187481,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:118695$4491_Y + connect \Y $eq$libresoc.v:120319$4524_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:118696$4492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120320$4525 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -185310,10 +187492,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:118696$4492_Y + connect \Y $eq$libresoc.v:120320$4525_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:118698$4494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120322$4527 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -185321,21 +187503,21 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:118698$4494_Y + connect \Y $eq$libresoc.v:120322$4527_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:118699$4495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:120323$4528 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:118699$4495_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:120323$4528_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:118701$4497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:120325$4530 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -185343,59 +187525,59 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:118701$4497_Y + connect \Y $eq$libresoc.v:120325$4530_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:118703$4499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:120327$4532 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:118703$4499_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:120327$4532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:118706$4502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:120330$4535 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:118706$4502_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:120330$4535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:118712$4508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:120336$4541 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:118712$4508_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:120336$4541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:118690$4486 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:120314$4519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:118690$4486_Y + connect \Y $not$libresoc.v:120314$4519_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:118708$4504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:120332$4537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:118708$4504_Y + connect \Y $not$libresoc.v:120332$4537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:118694$4490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:120318$4523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185403,10 +187585,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:118694$4490_Y + connect \Y $or$libresoc.v:120318$4523_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:118697$4493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:120321$4526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185414,10 +187596,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:118697$4493_Y + connect \Y $or$libresoc.v:120321$4526_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:118700$4496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:120324$4529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185425,10 +187607,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:118700$4496_Y + connect \Y $or$libresoc.v:120324$4529_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:118702$4498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:120326$4531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185436,10 +187618,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:118702$4498_Y + connect \Y $or$libresoc.v:120326$4531_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:118713.13-118735.4" + attribute \src "libresoc.v:120337.13-120359.4" cell \dec$141 \dec connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -185464,7 +187646,7 @@ module \dec_BRANCH connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:118736.16-118747.4" + attribute \src "libresoc.v:120360.16-120371.4" cell \dec_bi$144 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -185478,66 +187660,66 @@ module \dec_BRANCH connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:118748.16-118752.4" + attribute \src "libresoc.v:120372.16-120376.4" cell \dec_oe$143 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:118753.16-118756.4" + attribute \src "libresoc.v:120377.16-120380.4" cell \dec_rc$142 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:118332.7-118332.20" - process $proc$libresoc.v:118332$4512 + attribute \src "libresoc.v:119952.7-119952.20" + process $proc$libresoc.v:119952$4545 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118757.3-118771.6" - process $proc$libresoc.v:118757$4509 + attribute \src "libresoc.v:120381.3-120395.6" + process $proc$libresoc.v:120381$4542 assign { } { } - assign $0\BRANCH__fn_unit[12:0] $1\BRANCH__fn_unit[12:0] - attribute \src "libresoc.v:118758.5-118758.29" + assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0] + attribute \src "libresoc.v:120382.5-120382.29" switch \initial - attribute \src "libresoc.v:118758.9-118758.17" + attribute \src "libresoc.v:120382.9-120382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\BRANCH__fn_unit[12:0] 13'0000000000000 + assign $1\BRANCH__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\BRANCH__fn_unit[12:0] 13'0000000000000 + assign $1\BRANCH__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\BRANCH__fn_unit[12:0] \dec_BRANCH_function_unit + assign $1\BRANCH__fn_unit[13:0] \dec_BRANCH_function_unit end sync always - update \BRANCH__fn_unit $0\BRANCH__fn_unit[12:0] + update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] end - attribute \src "libresoc.v:118772.3-118781.6" - process $proc$libresoc.v:118772$4510 + attribute \src "libresoc.v:120396.3-120405.6" + process $proc$libresoc.v:120396$4543 assign { } { } assign { } { } assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:118773.5-118773.29" + attribute \src "libresoc.v:120397.5-120397.29" switch \initial - attribute \src "libresoc.v:118773.9-118773.17" + attribute \src "libresoc.v:120397.9-120397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:869" switch \dec_BRANCH_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -185549,18 +187731,18 @@ module \dec_BRANCH sync always update \BRANCH__lk $0\BRANCH__lk[0:0] end - attribute \src "libresoc.v:118782.3-118794.6" - process $proc$libresoc.v:118782$4511 + attribute \src "libresoc.v:120406.3-120418.6" + process $proc$libresoc.v:120406$4544 assign { } { } assign { } { } assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:118783.5-118783.29" + attribute \src "libresoc.v:120407.5-120407.29" switch \initial - attribute \src "libresoc.v:118783.9-118783.17" + attribute \src "libresoc.v:120407.9-120407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -185576,30 +187758,30 @@ module \dec_BRANCH sync always update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] end - connect \$10 $and$libresoc.v:118689$4485_Y - connect \$12 $not$libresoc.v:118690$4486_Y - connect \$14 $and$libresoc.v:118691$4487_Y - connect \$16 $eq$libresoc.v:118692$4488_Y - connect \$18 $eq$libresoc.v:118693$4489_Y - connect \$20 $or$libresoc.v:118694$4490_Y - connect \$22 $eq$libresoc.v:118695$4491_Y - connect \$24 $eq$libresoc.v:118696$4492_Y - connect \$26 $or$libresoc.v:118697$4493_Y - connect \$28 $eq$libresoc.v:118698$4494_Y - connect \$2 $eq$libresoc.v:118699$4495_Y - connect \$30 $or$libresoc.v:118700$4496_Y - connect \$32 $eq$libresoc.v:118701$4497_Y - connect \$34 $or$libresoc.v:118702$4498_Y - connect \$36 $eq$libresoc.v:118703$4499_Y - connect \$38 $and$libresoc.v:118704$4500_Y - connect \$40 $and$libresoc.v:118705$4501_Y - connect \$42 $eq$libresoc.v:118706$4502_Y - connect \$44 $and$libresoc.v:118707$4503_Y - connect \$46 $not$libresoc.v:118708$4504_Y - connect \$48 $and$libresoc.v:118709$4505_Y - connect \$4 $and$libresoc.v:118710$4506_Y - connect \$6 $and$libresoc.v:118711$4507_Y - connect \$8 $eq$libresoc.v:118712$4508_Y + connect \$10 $and$libresoc.v:120313$4518_Y + connect \$12 $not$libresoc.v:120314$4519_Y + connect \$14 $and$libresoc.v:120315$4520_Y + connect \$16 $eq$libresoc.v:120316$4521_Y + connect \$18 $eq$libresoc.v:120317$4522_Y + connect \$20 $or$libresoc.v:120318$4523_Y + connect \$22 $eq$libresoc.v:120319$4524_Y + connect \$24 $eq$libresoc.v:120320$4525_Y + connect \$26 $or$libresoc.v:120321$4526_Y + connect \$28 $eq$libresoc.v:120322$4527_Y + connect \$2 $eq$libresoc.v:120323$4528_Y + connect \$30 $or$libresoc.v:120324$4529_Y + connect \$32 $eq$libresoc.v:120325$4530_Y + connect \$34 $or$libresoc.v:120326$4531_Y + connect \$36 $eq$libresoc.v:120327$4532_Y + connect \$38 $and$libresoc.v:120328$4533_Y + connect \$40 $and$libresoc.v:120329$4534_Y + connect \$42 $eq$libresoc.v:120330$4535_Y + connect \$44 $and$libresoc.v:120331$4536_Y + connect \$46 $not$libresoc.v:120332$4537_Y + connect \$48 $and$libresoc.v:120333$4538_Y + connect \$4 $and$libresoc.v:120334$4539_Y + connect \$6 $and$libresoc.v:120335$4540_Y + connect \$8 $eq$libresoc.v:120336$4541_Y connect \BRANCH__is_32bit \dec_BRANCH_is_32b connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel @@ -185613,133 +187795,134 @@ module \dec_BRANCH connect \insn_in \dec_opcode_in connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:118811.1-119179.10" +attribute \src "libresoc.v:120435.1-120807.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR - attribute \src "libresoc.v:119156.3-119170.6" - wire width 13 $0\CR__fn_unit[12:0] - attribute \src "libresoc.v:119143.3-119155.6" + attribute \src "libresoc.v:120784.3-120798.6" + wire width 14 $0\CR__fn_unit[13:0] + attribute \src "libresoc.v:120771.3-120783.6" wire width 7 $0\CR__insn_type[6:0] - attribute \src "libresoc.v:118812.7-118812.20" + attribute \src "libresoc.v:120436.7-120436.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119156.3-119170.6" - wire width 13 $1\CR__fn_unit[12:0] - attribute \src "libresoc.v:119143.3-119155.6" + attribute \src "libresoc.v:120784.3-120798.6" + wire width 14 $1\CR__fn_unit[13:0] + attribute \src "libresoc.v:120771.3-120783.6" wire width 7 $1\CR__insn_type[6:0] - attribute \src "libresoc.v:119098.18-119098.113" - wire $and$libresoc.v:119098$4513_Y - attribute \src "libresoc.v:119100.18-119100.110" - wire $and$libresoc.v:119100$4515_Y - attribute \src "libresoc.v:119113.18-119113.114" - wire $and$libresoc.v:119113$4528_Y - attribute \src "libresoc.v:119114.18-119114.116" - wire $and$libresoc.v:119114$4529_Y - attribute \src "libresoc.v:119116.18-119116.114" - wire $and$libresoc.v:119116$4531_Y - attribute \src "libresoc.v:119118.18-119118.110" - wire $and$libresoc.v:119118$4533_Y - attribute \src "libresoc.v:119119.17-119119.112" - wire $and$libresoc.v:119119$4534_Y - attribute \src "libresoc.v:119120.17-119120.114" - wire $and$libresoc.v:119120$4535_Y - attribute \src "libresoc.v:119101.18-119101.125" - wire $eq$libresoc.v:119101$4516_Y - attribute \src "libresoc.v:119102.18-119102.125" - wire $eq$libresoc.v:119102$4517_Y - attribute \src "libresoc.v:119104.18-119104.110" - wire $eq$libresoc.v:119104$4519_Y - attribute \src "libresoc.v:119105.18-119105.110" - wire $eq$libresoc.v:119105$4520_Y - attribute \src "libresoc.v:119107.18-119107.112" - wire $eq$libresoc.v:119107$4522_Y - attribute \src "libresoc.v:119108.17-119108.129" - wire $eq$libresoc.v:119108$4523_Y - attribute \src "libresoc.v:119110.18-119110.110" - wire $eq$libresoc.v:119110$4525_Y - attribute \src "libresoc.v:119112.18-119112.130" - wire $eq$libresoc.v:119112$4527_Y - attribute \src "libresoc.v:119115.18-119115.130" - wire $eq$libresoc.v:119115$4530_Y - attribute \src "libresoc.v:119121.17-119121.129" - wire $eq$libresoc.v:119121$4536_Y - attribute \src "libresoc.v:119099.18-119099.110" - wire $not$libresoc.v:119099$4514_Y - attribute \src "libresoc.v:119117.18-119117.110" - wire $not$libresoc.v:119117$4532_Y - attribute \src "libresoc.v:119103.18-119103.110" - wire $or$libresoc.v:119103$4518_Y - attribute \src "libresoc.v:119106.18-119106.110" - wire $or$libresoc.v:119106$4521_Y - attribute \src "libresoc.v:119109.18-119109.110" - wire $or$libresoc.v:119109$4524_Y - attribute \src "libresoc.v:119111.18-119111.110" - wire $or$libresoc.v:119111$4526_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "libresoc.v:120726.18-120726.113" + wire $and$libresoc.v:120726$4546_Y + attribute \src "libresoc.v:120728.18-120728.110" + wire $and$libresoc.v:120728$4548_Y + attribute \src "libresoc.v:120741.18-120741.114" + wire $and$libresoc.v:120741$4561_Y + attribute \src "libresoc.v:120742.18-120742.116" + wire $and$libresoc.v:120742$4562_Y + attribute \src "libresoc.v:120744.18-120744.114" + wire $and$libresoc.v:120744$4564_Y + attribute \src "libresoc.v:120746.18-120746.110" + wire $and$libresoc.v:120746$4566_Y + attribute \src "libresoc.v:120747.17-120747.112" + wire $and$libresoc.v:120747$4567_Y + attribute \src "libresoc.v:120748.17-120748.114" + wire $and$libresoc.v:120748$4568_Y + attribute \src "libresoc.v:120729.18-120729.125" + wire $eq$libresoc.v:120729$4549_Y + attribute \src "libresoc.v:120730.18-120730.125" + wire $eq$libresoc.v:120730$4550_Y + attribute \src "libresoc.v:120732.18-120732.110" + wire $eq$libresoc.v:120732$4552_Y + attribute \src "libresoc.v:120733.18-120733.110" + wire $eq$libresoc.v:120733$4553_Y + attribute \src "libresoc.v:120735.18-120735.112" + wire $eq$libresoc.v:120735$4555_Y + attribute \src "libresoc.v:120736.17-120736.129" + wire $eq$libresoc.v:120736$4556_Y + attribute \src "libresoc.v:120738.18-120738.110" + wire $eq$libresoc.v:120738$4558_Y + attribute \src "libresoc.v:120740.18-120740.130" + wire $eq$libresoc.v:120740$4560_Y + attribute \src "libresoc.v:120743.18-120743.130" + wire $eq$libresoc.v:120743$4563_Y + attribute \src "libresoc.v:120749.17-120749.129" + wire $eq$libresoc.v:120749$4569_Y + attribute \src "libresoc.v:120727.18-120727.110" + wire $not$libresoc.v:120727$4547_Y + attribute \src "libresoc.v:120745.18-120745.110" + wire $not$libresoc.v:120745$4565_Y + attribute \src "libresoc.v:120731.18-120731.110" + wire $or$libresoc.v:120731$4551_Y + attribute \src "libresoc.v:120734.18-120734.110" + wire $or$libresoc.v:120734$4554_Y + attribute \src "libresoc.v:120737.18-120737.110" + wire $or$libresoc.v:120737$4557_Y + attribute \src "libresoc.v:120739.18-120739.110" + wire $or$libresoc.v:120739$4559_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 3 \CR__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 3 \CR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 4 \CR__insn attribute \enum_base_type "MicrOp" @@ -185816,6 +187999,7 @@ module \dec_CR attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \CR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" @@ -185836,21 +188020,22 @@ module \dec_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_CR_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_CR_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -185925,6 +188110,7 @@ module \dec_CR attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_CR_internal_op attribute \enum_base_type "RC" @@ -185937,7 +188123,7 @@ module \dec_CR attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -185945,24 +188131,24 @@ module \dec_CR attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:118812.7-118812.15" + attribute \src "libresoc.v:120436.7-120436.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 5 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:119098$4513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120726$4546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185970,10 +188156,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:119098$4513_Y + connect \Y $and$libresoc.v:120726$4546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:119100$4515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120728$4548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185981,10 +188167,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:119100$4515_Y + connect \Y $and$libresoc.v:120728$4548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:119113$4528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120741$4561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -185992,10 +188178,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:119113$4528_Y + connect \Y $and$libresoc.v:120741$4561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:119114$4529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120742$4562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186003,10 +188189,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:119114$4529_Y + connect \Y $and$libresoc.v:120742$4562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:119116$4531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120744$4564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186014,10 +188200,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:119116$4531_Y + connect \Y $and$libresoc.v:120744$4564_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:119118$4533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:120746$4566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186025,10 +188211,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:119118$4533_Y + connect \Y $and$libresoc.v:120746$4566_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:119119$4534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120747$4567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186036,10 +188222,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:119119$4534_Y + connect \Y $and$libresoc.v:120747$4567_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:119120$4535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:120748$4568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186047,10 +188233,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:119120$4535_Y + connect \Y $and$libresoc.v:120748$4568_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:119101$4516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:120729$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186058,10 +188244,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:119101$4516_Y + connect \Y $eq$libresoc.v:120729$4549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:119102$4517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:120730$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186069,10 +188255,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:119102$4517_Y + connect \Y $eq$libresoc.v:120730$4550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:119104$4519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120732$4552 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186080,10 +188266,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:119104$4519_Y + connect \Y $eq$libresoc.v:120732$4552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:119105$4520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120733$4553 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186091,10 +188277,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:119105$4520_Y + connect \Y $eq$libresoc.v:120733$4553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:119107$4522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:120735$4555 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186102,21 +188288,21 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:119107$4522_Y + connect \Y $eq$libresoc.v:120735$4555_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:119108$4523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:120736$4556 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:119108$4523_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:120736$4556_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:119110$4525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:120738$4558 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186124,59 +188310,59 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:119110$4525_Y + connect \Y $eq$libresoc.v:120738$4558_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:119112$4527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:120740$4560 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:119112$4527_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:120740$4560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:119115$4530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:120743$4563 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:119115$4530_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:120743$4563_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:119121$4536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:120749$4569 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:119121$4536_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:120749$4569_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:119099$4514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:120727$4547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:119099$4514_Y + connect \Y $not$libresoc.v:120727$4547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:119117$4532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:120745$4565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:119117$4532_Y + connect \Y $not$libresoc.v:120745$4565_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:119103$4518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:120731$4551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186184,10 +188370,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:119103$4518_Y + connect \Y $or$libresoc.v:120731$4551_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:119106$4521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:120734$4554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186195,10 +188381,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:119106$4521_Y + connect \Y $or$libresoc.v:120734$4554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:119109$4524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:120737$4557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186206,10 +188392,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:119109$4524_Y + connect \Y $or$libresoc.v:120737$4557_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:119111$4526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:120739$4559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186217,10 +188403,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:119111$4526_Y + connect \Y $or$libresoc.v:120739$4559_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:119122.13-119133.4" + attribute \src "libresoc.v:120750.13-120761.4" cell \dec$138 \dec connect \CR_OE \dec_CR_OE connect \CR_Rc \dec_CR_Rc @@ -186234,38 +188420,38 @@ module \dec_CR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119134.16-119138.4" + attribute \src "libresoc.v:120762.16-120766.4" cell \dec_oe$140 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119139.16-119142.4" + attribute \src "libresoc.v:120767.16-120770.4" cell \dec_rc$139 \dec_rc connect \CR_Rc \dec_CR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:118812.7-118812.20" - process $proc$libresoc.v:118812$4539 + attribute \src "libresoc.v:120436.7-120436.20" + process $proc$libresoc.v:120436$4572 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119143.3-119155.6" - process $proc$libresoc.v:119143$4537 + attribute \src "libresoc.v:120771.3-120783.6" + process $proc$libresoc.v:120771$4570 assign { } { } assign { } { } assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0] - attribute \src "libresoc.v:119144.5-119144.29" + attribute \src "libresoc.v:120772.5-120772.29" switch \initial - attribute \src "libresoc.v:119144.9-119144.17" + attribute \src "libresoc.v:120772.9-120772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -186281,58 +188467,58 @@ module \dec_CR sync always update \CR__insn_type $0\CR__insn_type[6:0] end - attribute \src "libresoc.v:119156.3-119170.6" - process $proc$libresoc.v:119156$4538 + attribute \src "libresoc.v:120784.3-120798.6" + process $proc$libresoc.v:120784$4571 assign { } { } - assign $0\CR__fn_unit[12:0] $1\CR__fn_unit[12:0] - attribute \src "libresoc.v:119157.5-119157.29" + assign $0\CR__fn_unit[13:0] $1\CR__fn_unit[13:0] + attribute \src "libresoc.v:120785.5-120785.29" switch \initial - attribute \src "libresoc.v:119157.9-119157.17" + attribute \src "libresoc.v:120785.9-120785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\CR__fn_unit[12:0] 13'0000000000000 + assign $1\CR__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\CR__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\CR__fn_unit[12:0] \dec_CR_function_unit - end - sync always - update \CR__fn_unit $0\CR__fn_unit[12:0] - end - connect \$10 $and$libresoc.v:119098$4513_Y - connect \$12 $not$libresoc.v:119099$4514_Y - connect \$14 $and$libresoc.v:119100$4515_Y - connect \$16 $eq$libresoc.v:119101$4516_Y - connect \$18 $eq$libresoc.v:119102$4517_Y - connect \$20 $or$libresoc.v:119103$4518_Y - connect \$22 $eq$libresoc.v:119104$4519_Y - connect \$24 $eq$libresoc.v:119105$4520_Y - connect \$26 $or$libresoc.v:119106$4521_Y - connect \$28 $eq$libresoc.v:119107$4522_Y - connect \$2 $eq$libresoc.v:119108$4523_Y - connect \$30 $or$libresoc.v:119109$4524_Y - connect \$32 $eq$libresoc.v:119110$4525_Y - connect \$34 $or$libresoc.v:119111$4526_Y - connect \$36 $eq$libresoc.v:119112$4527_Y - connect \$38 $and$libresoc.v:119113$4528_Y - connect \$40 $and$libresoc.v:119114$4529_Y - connect \$42 $eq$libresoc.v:119115$4530_Y - connect \$44 $and$libresoc.v:119116$4531_Y - connect \$46 $not$libresoc.v:119117$4532_Y - connect \$48 $and$libresoc.v:119118$4533_Y - connect \$4 $and$libresoc.v:119119$4534_Y - connect \$6 $and$libresoc.v:119120$4535_Y - connect \$8 $eq$libresoc.v:119121$4536_Y + assign $1\CR__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\CR__fn_unit[13:0] \dec_CR_function_unit + end + sync always + update \CR__fn_unit $0\CR__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:120726$4546_Y + connect \$12 $not$libresoc.v:120727$4547_Y + connect \$14 $and$libresoc.v:120728$4548_Y + connect \$16 $eq$libresoc.v:120729$4549_Y + connect \$18 $eq$libresoc.v:120730$4550_Y + connect \$20 $or$libresoc.v:120731$4551_Y + connect \$22 $eq$libresoc.v:120732$4552_Y + connect \$24 $eq$libresoc.v:120733$4553_Y + connect \$26 $or$libresoc.v:120734$4554_Y + connect \$28 $eq$libresoc.v:120735$4555_Y + connect \$2 $eq$libresoc.v:120736$4556_Y + connect \$30 $or$libresoc.v:120737$4557_Y + connect \$32 $eq$libresoc.v:120738$4558_Y + connect \$34 $or$libresoc.v:120739$4559_Y + connect \$36 $eq$libresoc.v:120740$4560_Y + connect \$38 $and$libresoc.v:120741$4561_Y + connect \$40 $and$libresoc.v:120742$4562_Y + connect \$42 $eq$libresoc.v:120743$4563_Y + connect \$44 $and$libresoc.v:120744$4564_Y + connect \$46 $not$libresoc.v:120745$4565_Y + connect \$48 $and$libresoc.v:120746$4566_Y + connect \$4 $and$libresoc.v:120747$4567_Y + connect \$6 $and$libresoc.v:120748$4568_Y + connect \$8 $eq$libresoc.v:120749$4569_Y connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] } @@ -186342,151 +188528,152 @@ module \dec_CR connect \insn_in \dec_opcode_in connect \CR__insn \dec_opcode_in end -attribute \src "libresoc.v:119183.1-119756.10" +attribute \src "libresoc.v:120811.1-121394.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV - attribute \src "libresoc.v:119720.3-119734.6" - wire width 13 $0\DIV__fn_unit[12:0] - attribute \src "libresoc.v:119707.3-119719.6" + attribute \src "libresoc.v:121357.3-121371.6" + wire width 14 $0\DIV__fn_unit[13:0] + attribute \src "libresoc.v:121344.3-121356.6" wire width 7 $0\DIV__insn_type[6:0] - attribute \src "libresoc.v:119692.3-119706.6" + attribute \src "libresoc.v:121329.3-121343.6" wire $0\DIV__write_cr0[0:0] - attribute \src "libresoc.v:119184.7-119184.20" + attribute \src "libresoc.v:120812.7-120812.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119720.3-119734.6" - wire width 13 $1\DIV__fn_unit[12:0] - attribute \src "libresoc.v:119707.3-119719.6" + attribute \src "libresoc.v:121357.3-121371.6" + wire width 14 $1\DIV__fn_unit[13:0] + attribute \src "libresoc.v:121344.3-121356.6" wire width 7 $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:119692.3-119706.6" + attribute \src "libresoc.v:121329.3-121343.6" wire $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:119609.18-119609.113" - wire $and$libresoc.v:119609$4540_Y - attribute \src "libresoc.v:119611.18-119611.110" - wire $and$libresoc.v:119611$4542_Y - attribute \src "libresoc.v:119624.18-119624.114" - wire $and$libresoc.v:119624$4555_Y - attribute \src "libresoc.v:119625.18-119625.116" - wire $and$libresoc.v:119625$4556_Y - attribute \src "libresoc.v:119627.18-119627.114" - wire $and$libresoc.v:119627$4558_Y - attribute \src "libresoc.v:119629.18-119629.110" - wire $and$libresoc.v:119629$4560_Y - attribute \src "libresoc.v:119630.17-119630.112" - wire $and$libresoc.v:119630$4561_Y - attribute \src "libresoc.v:119631.17-119631.114" - wire $and$libresoc.v:119631$4562_Y - attribute \src "libresoc.v:119612.18-119612.126" - wire $eq$libresoc.v:119612$4543_Y - attribute \src "libresoc.v:119613.18-119613.126" - wire $eq$libresoc.v:119613$4544_Y - attribute \src "libresoc.v:119615.18-119615.110" - wire $eq$libresoc.v:119615$4546_Y - attribute \src "libresoc.v:119616.18-119616.110" - wire $eq$libresoc.v:119616$4547_Y - attribute \src "libresoc.v:119618.18-119618.112" - wire $eq$libresoc.v:119618$4549_Y - attribute \src "libresoc.v:119619.17-119619.130" - wire $eq$libresoc.v:119619$4550_Y - attribute \src "libresoc.v:119621.18-119621.110" - wire $eq$libresoc.v:119621$4552_Y - attribute \src "libresoc.v:119623.18-119623.131" - wire $eq$libresoc.v:119623$4554_Y - attribute \src "libresoc.v:119626.18-119626.131" - wire $eq$libresoc.v:119626$4557_Y - attribute \src "libresoc.v:119632.17-119632.130" - wire $eq$libresoc.v:119632$4563_Y - attribute \src "libresoc.v:119610.18-119610.110" - wire $not$libresoc.v:119610$4541_Y - attribute \src "libresoc.v:119628.18-119628.110" - wire $not$libresoc.v:119628$4559_Y - attribute \src "libresoc.v:119614.18-119614.110" - wire $or$libresoc.v:119614$4545_Y - attribute \src "libresoc.v:119617.18-119617.110" - wire $or$libresoc.v:119617$4548_Y - attribute \src "libresoc.v:119620.18-119620.110" - wire $or$libresoc.v:119620$4551_Y - attribute \src "libresoc.v:119622.18-119622.110" - wire $or$libresoc.v:119622$4553_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "libresoc.v:121245.18-121245.113" + wire $and$libresoc.v:121245$4573_Y + attribute \src "libresoc.v:121247.18-121247.110" + wire $and$libresoc.v:121247$4575_Y + attribute \src "libresoc.v:121260.18-121260.114" + wire $and$libresoc.v:121260$4588_Y + attribute \src "libresoc.v:121261.18-121261.116" + wire $and$libresoc.v:121261$4589_Y + attribute \src "libresoc.v:121263.18-121263.114" + wire $and$libresoc.v:121263$4591_Y + attribute \src "libresoc.v:121265.18-121265.110" + wire $and$libresoc.v:121265$4593_Y + attribute \src "libresoc.v:121266.17-121266.112" + wire $and$libresoc.v:121266$4594_Y + attribute \src "libresoc.v:121267.17-121267.114" + wire $and$libresoc.v:121267$4595_Y + attribute \src "libresoc.v:121248.18-121248.126" + wire $eq$libresoc.v:121248$4576_Y + attribute \src "libresoc.v:121249.18-121249.126" + wire $eq$libresoc.v:121249$4577_Y + attribute \src "libresoc.v:121251.18-121251.110" + wire $eq$libresoc.v:121251$4579_Y + attribute \src "libresoc.v:121252.18-121252.110" + wire $eq$libresoc.v:121252$4580_Y + attribute \src "libresoc.v:121254.18-121254.112" + wire $eq$libresoc.v:121254$4582_Y + attribute \src "libresoc.v:121255.17-121255.130" + wire $eq$libresoc.v:121255$4583_Y + attribute \src "libresoc.v:121257.18-121257.110" + wire $eq$libresoc.v:121257$4585_Y + attribute \src "libresoc.v:121259.18-121259.131" + wire $eq$libresoc.v:121259$4587_Y + attribute \src "libresoc.v:121262.18-121262.131" + wire $eq$libresoc.v:121262$4590_Y + attribute \src "libresoc.v:121268.17-121268.130" + wire $eq$libresoc.v:121268$4596_Y + attribute \src "libresoc.v:121246.18-121246.110" + wire $not$libresoc.v:121246$4574_Y + attribute \src "libresoc.v:121264.18-121264.110" + wire $not$libresoc.v:121264$4592_Y + attribute \src "libresoc.v:121250.18-121250.110" + wire $or$libresoc.v:121250$4578_Y + attribute \src "libresoc.v:121253.18-121253.110" + wire $or$libresoc.v:121253$4581_Y + attribute \src "libresoc.v:121256.18-121256.110" + wire $or$libresoc.v:121256$4584_Y + attribute \src "libresoc.v:121258.18-121258.110" + wire $or$libresoc.v:121258$4586_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \DIV__data_len + wire width 4 output 19 \DIV__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 3 \DIV__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \DIV__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \DIV__imm_data__ok + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \DIV__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \DIV__input_carry + wire width 2 output 13 \DIV__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \DIV__insn + wire width 32 output 20 \DIV__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -186561,30 +188748,31 @@ module \dec_DIV attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \DIV__insn_type + wire width 7 output 3 \DIV__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \DIV__invert_in + wire output 11 \DIV__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \DIV__invert_out + wire output 14 \DIV__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \DIV__is_32bit + wire output 17 \DIV__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \DIV__is_signed + wire output 18 \DIV__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \DIV__oe__oe + wire output 9 \DIV__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \DIV__oe__ok + wire output 10 \DIV__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \DIV__output_carry + wire output 16 \DIV__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \DIV__rc__ok + wire output 8 \DIV__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \DIV__rc__rc + wire output 7 \DIV__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \DIV__write_cr0 + wire output 15 \DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \DIV__zero_a + wire output 12 \DIV__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -186625,21 +188813,22 @@ module \dec_DIV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_DIV_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_DIV_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -186739,6 +188928,7 @@ module \dec_DIV attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_DIV_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -186765,7 +188955,7 @@ module \dec_DIV wire \dec_DIV_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -186773,8 +188963,10 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -186794,7 +188986,7 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -186804,7 +188996,7 @@ module \dec_DIV attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -186816,24 +189008,26 @@ module \dec_DIV attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:119184.7-119184.15" + attribute \src "libresoc.v:120812.7-120812.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:119609$4540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121245$4573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186841,10 +189035,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:119609$4540_Y + connect \Y $and$libresoc.v:121245$4573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:119611$4542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121247$4575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186852,10 +189046,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:119611$4542_Y + connect \Y $and$libresoc.v:121247$4575_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:119624$4555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121260$4588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186863,10 +189057,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:119624$4555_Y + connect \Y $and$libresoc.v:121260$4588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:119625$4556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121261$4589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186874,10 +189068,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:119625$4556_Y + connect \Y $and$libresoc.v:121261$4589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:119627$4558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121263$4591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186885,10 +189079,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:119627$4558_Y + connect \Y $and$libresoc.v:121263$4591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:119629$4560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121265$4593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186896,10 +189090,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:119629$4560_Y + connect \Y $and$libresoc.v:121265$4593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:119630$4561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121266$4594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186907,10 +189101,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:119630$4561_Y + connect \Y $and$libresoc.v:121266$4594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:119631$4562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121267$4595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186918,10 +189112,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:119631$4562_Y + connect \Y $and$libresoc.v:121267$4595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:119612$4543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:121248$4576 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186929,10 +189123,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:119612$4543_Y + connect \Y $eq$libresoc.v:121248$4576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:119613$4544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121249$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186940,10 +189134,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:119613$4544_Y + connect \Y $eq$libresoc.v:121249$4577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:119615$4546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121251$4579 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186951,10 +189145,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:119615$4546_Y + connect \Y $eq$libresoc.v:121251$4579_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:119616$4547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121252$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186962,10 +189156,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:119616$4547_Y + connect \Y $eq$libresoc.v:121252$4580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:119618$4549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121254$4582 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186973,21 +189167,21 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:119618$4549_Y + connect \Y $eq$libresoc.v:121254$4582_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:119619$4550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:121255$4583 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:119619$4550_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121255$4583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:119621$4552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121257$4585 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186995,59 +189189,59 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:119621$4552_Y + connect \Y $eq$libresoc.v:121257$4585_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:119623$4554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:121259$4587 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:119623$4554_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121259$4587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:119626$4557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:121262$4590 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:119626$4557_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121262$4590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:119632$4563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:121268$4596 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:119632$4563_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121268$4596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:119610$4541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:121246$4574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:119610$4541_Y + connect \Y $not$libresoc.v:121246$4574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:119628$4559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:121264$4592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:119628$4559_Y + connect \Y $not$libresoc.v:121264$4592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:119614$4545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:121250$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187055,10 +189249,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:119614$4545_Y + connect \Y $or$libresoc.v:121250$4578_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:119617$4548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:121253$4581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187066,10 +189260,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:119617$4548_Y + connect \Y $or$libresoc.v:121253$4581_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:119620$4551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:121256$4584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187077,10 +189271,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:119620$4551_Y + connect \Y $or$libresoc.v:121256$4584_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:119622$4553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121258$4586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187088,10 +189282,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:119622$4553_Y + connect \Y $or$libresoc.v:121258$4586_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:119633.13-119661.4" + attribute \src "libresoc.v:121269.13-121297.4" cell \dec$153 \dec connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -187122,14 +189316,15 @@ module \dec_DIV connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119662.16-119666.4" + attribute \src "libresoc.v:121298.16-121303.4" cell \dec_ai$156 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:119667.16-119678.4" + attribute \src "libresoc.v:121304.16-121315.4" cell \dec_bi$157 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -187143,7 +189338,7 @@ module \dec_DIV connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119679.16-119685.4" + attribute \src "libresoc.v:121316.16-121322.4" cell \dec_oe$155 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op @@ -187152,33 +189347,33 @@ module \dec_DIV connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119686.16-119691.4" + attribute \src "libresoc.v:121323.16-121328.4" cell \dec_rc$154 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:119184.7-119184.20" - process $proc$libresoc.v:119184$4567 + attribute \src "libresoc.v:120812.7-120812.20" + process $proc$libresoc.v:120812$4600 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119692.3-119706.6" - process $proc$libresoc.v:119692$4564 + attribute \src "libresoc.v:121329.3-121343.6" + process $proc$libresoc.v:121329$4597 assign { } { } assign { } { } assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:119693.5-119693.29" + attribute \src "libresoc.v:121330.5-121330.29" switch \initial - attribute \src "libresoc.v:119693.9-119693.17" + attribute \src "libresoc.v:121330.9-121330.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch \dec_DIV_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -187194,18 +189389,18 @@ module \dec_DIV sync always update \DIV__write_cr0 $0\DIV__write_cr0[0:0] end - attribute \src "libresoc.v:119707.3-119719.6" - process $proc$libresoc.v:119707$4565 + attribute \src "libresoc.v:121344.3-121356.6" + process $proc$libresoc.v:121344$4598 assign { } { } assign { } { } assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:119708.5-119708.29" + attribute \src "libresoc.v:121345.5-121345.29" switch \initial - attribute \src "libresoc.v:119708.9-119708.17" + attribute \src "libresoc.v:121345.9-121345.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -187221,58 +189416,58 @@ module \dec_DIV sync always update \DIV__insn_type $0\DIV__insn_type[6:0] end - attribute \src "libresoc.v:119720.3-119734.6" - process $proc$libresoc.v:119720$4566 + attribute \src "libresoc.v:121357.3-121371.6" + process $proc$libresoc.v:121357$4599 assign { } { } - assign $0\DIV__fn_unit[12:0] $1\DIV__fn_unit[12:0] - attribute \src "libresoc.v:119721.5-119721.29" + assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] + attribute \src "libresoc.v:121358.5-121358.29" switch \initial - attribute \src "libresoc.v:119721.9-119721.17" + attribute \src "libresoc.v:121358.9-121358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\DIV__fn_unit[12:0] 13'0000000000000 + assign $1\DIV__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\DIV__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\DIV__fn_unit[12:0] \dec_DIV_function_unit - end - sync always - update \DIV__fn_unit $0\DIV__fn_unit[12:0] - end - connect \$10 $and$libresoc.v:119609$4540_Y - connect \$12 $not$libresoc.v:119610$4541_Y - connect \$14 $and$libresoc.v:119611$4542_Y - connect \$16 $eq$libresoc.v:119612$4543_Y - connect \$18 $eq$libresoc.v:119613$4544_Y - connect \$20 $or$libresoc.v:119614$4545_Y - connect \$22 $eq$libresoc.v:119615$4546_Y - connect \$24 $eq$libresoc.v:119616$4547_Y - connect \$26 $or$libresoc.v:119617$4548_Y - connect \$28 $eq$libresoc.v:119618$4549_Y - connect \$2 $eq$libresoc.v:119619$4550_Y - connect \$30 $or$libresoc.v:119620$4551_Y - connect \$32 $eq$libresoc.v:119621$4552_Y - connect \$34 $or$libresoc.v:119622$4553_Y - connect \$36 $eq$libresoc.v:119623$4554_Y - connect \$38 $and$libresoc.v:119624$4555_Y - connect \$40 $and$libresoc.v:119625$4556_Y - connect \$42 $eq$libresoc.v:119626$4557_Y - connect \$44 $and$libresoc.v:119627$4558_Y - connect \$46 $not$libresoc.v:119628$4559_Y - connect \$48 $and$libresoc.v:119629$4560_Y - connect \$4 $and$libresoc.v:119630$4561_Y - connect \$6 $and$libresoc.v:119631$4562_Y - connect \$8 $eq$libresoc.v:119632$4563_Y + assign $1\DIV__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\DIV__fn_unit[13:0] \dec_DIV_function_unit + end + sync always + update \DIV__fn_unit $0\DIV__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:121245$4573_Y + connect \$12 $not$libresoc.v:121246$4574_Y + connect \$14 $and$libresoc.v:121247$4575_Y + connect \$16 $eq$libresoc.v:121248$4576_Y + connect \$18 $eq$libresoc.v:121249$4577_Y + connect \$20 $or$libresoc.v:121250$4578_Y + connect \$22 $eq$libresoc.v:121251$4579_Y + connect \$24 $eq$libresoc.v:121252$4580_Y + connect \$26 $or$libresoc.v:121253$4581_Y + connect \$28 $eq$libresoc.v:121254$4582_Y + connect \$2 $eq$libresoc.v:121255$4583_Y + connect \$30 $or$libresoc.v:121256$4584_Y + connect \$32 $eq$libresoc.v:121257$4585_Y + connect \$34 $or$libresoc.v:121258$4586_Y + connect \$36 $eq$libresoc.v:121259$4587_Y + connect \$38 $and$libresoc.v:121260$4588_Y + connect \$40 $and$libresoc.v:121261$4589_Y + connect \$42 $eq$libresoc.v:121262$4590_Y + connect \$44 $and$libresoc.v:121263$4591_Y + connect \$46 $not$libresoc.v:121264$4592_Y + connect \$48 $and$libresoc.v:121265$4593_Y + connect \$4 $and$libresoc.v:121266$4594_Y + connect \$6 $and$libresoc.v:121267$4595_Y + connect \$8 $eq$libresoc.v:121268$4596_Y connect \DIV__is_signed \dec_DIV_sgn connect \DIV__is_32bit \dec_DIV_is_32b connect \DIV__output_carry \dec_DIV_cry_out @@ -187286,6 +189481,7 @@ module \dec_DIV connect \dec_bi_sel_in \dec_DIV_in2_sel connect \DIV__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_DIV_in1_sel + connect \dec_ai_sv_nz \sv_a_nz connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_DIV_SPR [4:0] \dec_DIV_SPR [9:5] } @@ -187295,143 +189491,144 @@ module \dec_DIV connect \insn_in \dec_opcode_in connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:119760.1-120311.10" +attribute \src "libresoc.v:121398.1-121959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST - attribute \src "libresoc.v:120276.3-120290.6" - wire width 13 $0\LDST__fn_unit[12:0] - attribute \src "libresoc.v:120263.3-120275.6" + attribute \src "libresoc.v:121923.3-121937.6" + wire width 14 $0\LDST__fn_unit[13:0] + attribute \src "libresoc.v:121910.3-121922.6" wire width 7 $0\LDST__insn_type[6:0] - attribute \src "libresoc.v:119761.7-119761.20" + attribute \src "libresoc.v:121399.7-121399.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120276.3-120290.6" - wire width 13 $1\LDST__fn_unit[12:0] - attribute \src "libresoc.v:120263.3-120275.6" + attribute \src "libresoc.v:121923.3-121937.6" + wire width 14 $1\LDST__fn_unit[13:0] + attribute \src "libresoc.v:121910.3-121922.6" wire width 7 $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:120181.18-120181.113" - wire $and$libresoc.v:120181$4568_Y - attribute \src "libresoc.v:120183.18-120183.110" - wire $and$libresoc.v:120183$4570_Y - attribute \src "libresoc.v:120196.18-120196.114" - wire $and$libresoc.v:120196$4583_Y - attribute \src "libresoc.v:120197.18-120197.116" - wire $and$libresoc.v:120197$4584_Y - attribute \src "libresoc.v:120199.18-120199.114" - wire $and$libresoc.v:120199$4586_Y - attribute \src "libresoc.v:120201.18-120201.110" - wire $and$libresoc.v:120201$4588_Y - attribute \src "libresoc.v:120202.17-120202.112" - wire $and$libresoc.v:120202$4589_Y - attribute \src "libresoc.v:120203.17-120203.114" - wire $and$libresoc.v:120203$4590_Y - attribute \src "libresoc.v:120184.18-120184.127" - wire $eq$libresoc.v:120184$4571_Y - attribute \src "libresoc.v:120185.18-120185.127" - wire $eq$libresoc.v:120185$4572_Y - attribute \src "libresoc.v:120187.18-120187.110" - wire $eq$libresoc.v:120187$4574_Y - attribute \src "libresoc.v:120188.18-120188.110" - wire $eq$libresoc.v:120188$4575_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LDST__byte_reverse + wire output 15 \LDST__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 13 \LDST__data_len + wire width 4 output 14 \LDST__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 3 \LDST__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \LDST__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \LDST__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \LDST__insn + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 18 \LDST__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -187506,31 +189703,32 @@ module \dec_LDST attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LDST__insn_type + wire width 7 output 3 \LDST__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LDST__is_32bit + wire output 12 \LDST__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \LDST__is_signed + wire output 13 \LDST__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 16 \LDST__ldst_mode + wire width 2 output 17 \LDST__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LDST__oe__oe + wire output 10 \LDST__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LDST__oe__ok + wire output 11 \LDST__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LDST__rc__ok + wire output 9 \LDST__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LDST__rc__rc + wire output 8 \LDST__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LDST__sign_extend + wire output 16 \LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LDST__zero_a + wire output 7 \LDST__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -187565,21 +189763,22 @@ module \dec_LDST attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_LDST_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_LDST_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -187679,6 +189878,7 @@ module \dec_LDST attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_LDST_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -187710,7 +189910,7 @@ module \dec_LDST attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -187718,8 +189918,10 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -187739,7 +189941,7 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -187749,7 +189951,7 @@ module \dec_LDST attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -187761,24 +189963,26 @@ module \dec_LDST attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:119761.7-119761.15" + attribute \src "libresoc.v:121399.7-121399.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 18 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:120181$4568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121827$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187786,10 +189990,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:120181$4568_Y + connect \Y $and$libresoc.v:121827$4601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:120183$4570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121829$4603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187797,10 +190001,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:120183$4570_Y + connect \Y $and$libresoc.v:121829$4603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:120196$4583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121842$4616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187808,10 +190012,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:120196$4583_Y + connect \Y $and$libresoc.v:121842$4616_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:120197$4584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121843$4617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187819,10 +190023,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120197$4584_Y + connect \Y $and$libresoc.v:121843$4617_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:120199$4586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121845$4619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187830,10 +190034,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:120199$4586_Y + connect \Y $and$libresoc.v:121845$4619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:120201$4588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:121847$4621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187841,10 +190045,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:120201$4588_Y + connect \Y $and$libresoc.v:121847$4621_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:120202$4589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121848$4622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187852,10 +190056,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:120202$4589_Y + connect \Y $and$libresoc.v:121848$4622_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:120203$4590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:121849$4623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187863,10 +190067,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120203$4590_Y + connect \Y $and$libresoc.v:121849$4623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:120184$4571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:121830$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -187874,10 +190078,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:120184$4571_Y + connect \Y $eq$libresoc.v:121830$4604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:120185$4572 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121831$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -187885,10 +190089,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:120185$4572_Y + connect \Y $eq$libresoc.v:121831$4605_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:120187$4574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121833$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187896,10 +190100,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:120187$4574_Y + connect \Y $eq$libresoc.v:121833$4607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:120188$4575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121834$4608 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187907,10 +190111,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:120188$4575_Y + connect \Y $eq$libresoc.v:121834$4608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:120190$4577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:121836$4610 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187918,21 +190122,21 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:120190$4577_Y + connect \Y $eq$libresoc.v:121836$4610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:120191$4578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:121837$4611 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:120191$4578_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121837$4611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:120193$4580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121839$4613 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187940,59 +190144,59 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:120193$4580_Y + connect \Y $eq$libresoc.v:121839$4613_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:120195$4582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:121841$4615 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:120195$4582_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:121841$4615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:120198$4585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:121844$4618 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:120198$4585_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121844$4618_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:120204$4591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:121850$4624 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:120204$4591_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:121850$4624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:120182$4569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:121828$4602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120182$4569_Y + connect \Y $not$libresoc.v:121828$4602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:120200$4587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:121846$4620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120200$4587_Y + connect \Y $not$libresoc.v:121846$4620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:120186$4573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:121832$4606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188000,10 +190204,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:120186$4573_Y + connect \Y $or$libresoc.v:121832$4606_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:120189$4576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:121835$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188011,10 +190215,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:120189$4576_Y + connect \Y $or$libresoc.v:121835$4609_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:120192$4579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:121838$4612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188022,10 +190226,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:120192$4579_Y + connect \Y $or$libresoc.v:121838$4612_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:120194$4581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121840$4614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188033,10 +190237,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:120194$4581_Y + connect \Y $or$libresoc.v:121840$4614_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120205.13-120232.4" + attribute \src "libresoc.v:121851.13-121878.4" cell \dec$166 \dec connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -188066,14 +190270,15 @@ module \dec_LDST connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120233.16-120237.4" + attribute \src "libresoc.v:121879.16-121884.4" cell \dec_ai$169 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:120238.16-120249.4" + attribute \src "libresoc.v:121885.16-121896.4" cell \dec_bi$170 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -188087,7 +190292,7 @@ module \dec_LDST connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120250.16-120256.4" + attribute \src "libresoc.v:121897.16-121903.4" cell \dec_oe$168 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op @@ -188096,33 +190301,33 @@ module \dec_LDST connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120257.16-120262.4" + attribute \src "libresoc.v:121904.16-121909.4" cell \dec_rc$167 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:119761.7-119761.20" - process $proc$libresoc.v:119761$4594 + attribute \src "libresoc.v:121399.7-121399.20" + process $proc$libresoc.v:121399$4627 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120263.3-120275.6" - process $proc$libresoc.v:120263$4592 + attribute \src "libresoc.v:121910.3-121922.6" + process $proc$libresoc.v:121910$4625 assign { } { } assign { } { } assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:120264.5-120264.29" + attribute \src "libresoc.v:121911.5-121911.29" switch \initial - attribute \src "libresoc.v:120264.9-120264.17" + attribute \src "libresoc.v:121911.9-121911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -188138,58 +190343,58 @@ module \dec_LDST sync always update \LDST__insn_type $0\LDST__insn_type[6:0] end - attribute \src "libresoc.v:120276.3-120290.6" - process $proc$libresoc.v:120276$4593 + attribute \src "libresoc.v:121923.3-121937.6" + process $proc$libresoc.v:121923$4626 assign { } { } - assign $0\LDST__fn_unit[12:0] $1\LDST__fn_unit[12:0] - attribute \src "libresoc.v:120277.5-120277.29" + assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0] + attribute \src "libresoc.v:121924.5-121924.29" switch \initial - attribute \src "libresoc.v:120277.9-120277.17" + attribute \src "libresoc.v:121924.9-121924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\LDST__fn_unit[12:0] 13'0000000000000 + assign $1\LDST__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\LDST__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\LDST__fn_unit[12:0] \dec_LDST_function_unit - end - sync always - update \LDST__fn_unit $0\LDST__fn_unit[12:0] - end - connect \$10 $and$libresoc.v:120181$4568_Y - connect \$12 $not$libresoc.v:120182$4569_Y - connect \$14 $and$libresoc.v:120183$4570_Y - connect \$16 $eq$libresoc.v:120184$4571_Y - connect \$18 $eq$libresoc.v:120185$4572_Y - connect \$20 $or$libresoc.v:120186$4573_Y - connect \$22 $eq$libresoc.v:120187$4574_Y - connect \$24 $eq$libresoc.v:120188$4575_Y - connect \$26 $or$libresoc.v:120189$4576_Y - connect \$28 $eq$libresoc.v:120190$4577_Y - connect \$2 $eq$libresoc.v:120191$4578_Y - connect \$30 $or$libresoc.v:120192$4579_Y - connect \$32 $eq$libresoc.v:120193$4580_Y - connect \$34 $or$libresoc.v:120194$4581_Y - connect \$36 $eq$libresoc.v:120195$4582_Y - connect \$38 $and$libresoc.v:120196$4583_Y - connect \$40 $and$libresoc.v:120197$4584_Y - connect \$42 $eq$libresoc.v:120198$4585_Y - connect \$44 $and$libresoc.v:120199$4586_Y - connect \$46 $not$libresoc.v:120200$4587_Y - connect \$48 $and$libresoc.v:120201$4588_Y - connect \$4 $and$libresoc.v:120202$4589_Y - connect \$6 $and$libresoc.v:120203$4590_Y - connect \$8 $eq$libresoc.v:120204$4591_Y + assign $1\LDST__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\LDST__fn_unit[13:0] \dec_LDST_function_unit + end + sync always + update \LDST__fn_unit $0\LDST__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:121827$4601_Y + connect \$12 $not$libresoc.v:121828$4602_Y + connect \$14 $and$libresoc.v:121829$4603_Y + connect \$16 $eq$libresoc.v:121830$4604_Y + connect \$18 $eq$libresoc.v:121831$4605_Y + connect \$20 $or$libresoc.v:121832$4606_Y + connect \$22 $eq$libresoc.v:121833$4607_Y + connect \$24 $eq$libresoc.v:121834$4608_Y + connect \$26 $or$libresoc.v:121835$4609_Y + connect \$28 $eq$libresoc.v:121836$4610_Y + connect \$2 $eq$libresoc.v:121837$4611_Y + connect \$30 $or$libresoc.v:121838$4612_Y + connect \$32 $eq$libresoc.v:121839$4613_Y + connect \$34 $or$libresoc.v:121840$4614_Y + connect \$36 $eq$libresoc.v:121841$4615_Y + connect \$38 $and$libresoc.v:121842$4616_Y + connect \$40 $and$libresoc.v:121843$4617_Y + connect \$42 $eq$libresoc.v:121844$4618_Y + connect \$44 $and$libresoc.v:121845$4619_Y + connect \$46 $not$libresoc.v:121846$4620_Y + connect \$48 $and$libresoc.v:121847$4621_Y + connect \$4 $and$libresoc.v:121848$4622_Y + connect \$6 $and$libresoc.v:121849$4623_Y + connect \$8 $eq$libresoc.v:121850$4624_Y connect \LDST__ldst_mode \dec_LDST_upd connect \LDST__sign_extend \dec_LDST_sgn_ext connect \LDST__byte_reverse \dec_LDST_br @@ -188202,6 +190407,7 @@ module \dec_LDST connect \dec_bi_sel_in \dec_LDST_in2_sel connect \LDST__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_LDST_in1_sel + connect \dec_ai_sv_nz \sv_a_nz connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_LDST_SPR [4:0] \dec_LDST_SPR [9:5] } @@ -188211,151 +190417,152 @@ module \dec_LDST connect \insn_in \dec_opcode_in connect \LDST__insn \dec_opcode_in end -attribute \src "libresoc.v:120315.1-120888.10" +attribute \src "libresoc.v:121963.1-122546.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL - attribute \src "libresoc.v:120852.3-120866.6" - wire width 13 $0\LOGICAL__fn_unit[12:0] - attribute \src "libresoc.v:120839.3-120851.6" + attribute \src "libresoc.v:122509.3-122523.6" + wire width 14 $0\LOGICAL__fn_unit[13:0] + attribute \src "libresoc.v:122496.3-122508.6" wire width 7 $0\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:120824.3-120838.6" + attribute \src "libresoc.v:122481.3-122495.6" wire $0\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:120316.7-120316.20" + attribute \src "libresoc.v:121964.7-121964.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120852.3-120866.6" - wire width 13 $1\LOGICAL__fn_unit[12:0] - attribute \src "libresoc.v:120839.3-120851.6" + attribute \src "libresoc.v:122509.3-122523.6" + wire width 14 $1\LOGICAL__fn_unit[13:0] + attribute \src "libresoc.v:122496.3-122508.6" wire width 7 $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:120824.3-120838.6" + attribute \src "libresoc.v:122481.3-122495.6" wire $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:120741.18-120741.113" - wire $and$libresoc.v:120741$4595_Y - attribute \src "libresoc.v:120743.18-120743.110" - wire $and$libresoc.v:120743$4597_Y - attribute \src "libresoc.v:120756.18-120756.114" - wire $and$libresoc.v:120756$4610_Y - attribute \src "libresoc.v:120757.18-120757.116" - wire $and$libresoc.v:120757$4611_Y - attribute \src "libresoc.v:120759.18-120759.114" - wire $and$libresoc.v:120759$4613_Y - attribute \src "libresoc.v:120761.18-120761.110" - wire $and$libresoc.v:120761$4615_Y - attribute \src "libresoc.v:120762.17-120762.112" - wire $and$libresoc.v:120762$4616_Y - attribute \src "libresoc.v:120763.17-120763.114" - wire $and$libresoc.v:120763$4617_Y - attribute \src "libresoc.v:120744.18-120744.130" - wire $eq$libresoc.v:120744$4598_Y - attribute \src "libresoc.v:120745.18-120745.130" - wire $eq$libresoc.v:120745$4599_Y - attribute \src "libresoc.v:120747.18-120747.110" - wire $eq$libresoc.v:120747$4601_Y - attribute \src "libresoc.v:120748.18-120748.110" - wire $eq$libresoc.v:120748$4602_Y - attribute \src "libresoc.v:120750.18-120750.112" - wire $eq$libresoc.v:120750$4604_Y - attribute \src "libresoc.v:120751.17-120751.134" - wire $eq$libresoc.v:120751$4605_Y - attribute \src "libresoc.v:120753.18-120753.110" - wire $eq$libresoc.v:120753$4607_Y - attribute \src "libresoc.v:120755.18-120755.135" - wire $eq$libresoc.v:120755$4609_Y - attribute \src "libresoc.v:120758.18-120758.135" - wire $eq$libresoc.v:120758$4612_Y - attribute \src "libresoc.v:120764.17-120764.134" - wire $eq$libresoc.v:120764$4618_Y - attribute \src "libresoc.v:120742.18-120742.110" - wire $not$libresoc.v:120742$4596_Y - attribute \src "libresoc.v:120760.18-120760.110" - wire $not$libresoc.v:120760$4614_Y - attribute \src "libresoc.v:120746.18-120746.110" - wire $or$libresoc.v:120746$4600_Y - attribute \src "libresoc.v:120749.18-120749.110" - wire $or$libresoc.v:120749$4603_Y - attribute \src "libresoc.v:120752.18-120752.110" - wire $or$libresoc.v:120752$4606_Y - attribute \src "libresoc.v:120754.18-120754.110" - wire $or$libresoc.v:120754$4608_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "libresoc.v:122397.18-122397.113" + wire $and$libresoc.v:122397$4628_Y + attribute \src "libresoc.v:122399.18-122399.110" + wire $and$libresoc.v:122399$4630_Y + attribute \src "libresoc.v:122412.18-122412.114" + wire $and$libresoc.v:122412$4643_Y + attribute \src "libresoc.v:122413.18-122413.116" + wire $and$libresoc.v:122413$4644_Y + attribute \src "libresoc.v:122415.18-122415.114" + wire $and$libresoc.v:122415$4646_Y + attribute \src "libresoc.v:122417.18-122417.110" + wire $and$libresoc.v:122417$4648_Y + attribute \src "libresoc.v:122418.17-122418.112" + wire $and$libresoc.v:122418$4649_Y + attribute \src "libresoc.v:122419.17-122419.114" + wire $and$libresoc.v:122419$4650_Y + attribute \src "libresoc.v:122400.18-122400.130" + wire $eq$libresoc.v:122400$4631_Y + attribute \src "libresoc.v:122401.18-122401.130" + wire $eq$libresoc.v:122401$4632_Y + attribute \src "libresoc.v:122403.18-122403.110" + wire $eq$libresoc.v:122403$4634_Y + attribute \src "libresoc.v:122404.18-122404.110" + wire $eq$libresoc.v:122404$4635_Y + attribute \src "libresoc.v:122406.18-122406.112" + wire $eq$libresoc.v:122406$4637_Y + attribute \src "libresoc.v:122407.17-122407.134" + wire $eq$libresoc.v:122407$4638_Y + attribute \src "libresoc.v:122409.18-122409.110" + wire $eq$libresoc.v:122409$4640_Y + attribute \src "libresoc.v:122411.18-122411.135" + wire $eq$libresoc.v:122411$4642_Y + attribute \src "libresoc.v:122414.18-122414.135" + wire $eq$libresoc.v:122414$4645_Y + attribute \src "libresoc.v:122420.17-122420.134" + wire $eq$libresoc.v:122420$4651_Y + attribute \src "libresoc.v:122398.18-122398.110" + wire $not$libresoc.v:122398$4629_Y + attribute \src "libresoc.v:122416.18-122416.110" + wire $not$libresoc.v:122416$4647_Y + attribute \src "libresoc.v:122402.18-122402.110" + wire $or$libresoc.v:122402$4633_Y + attribute \src "libresoc.v:122405.18-122405.110" + wire $or$libresoc.v:122405$4636_Y + attribute \src "libresoc.v:122408.18-122408.110" + wire $or$libresoc.v:122408$4639_Y + attribute \src "libresoc.v:122410.18-122410.110" + wire $or$libresoc.v:122410$4641_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \LOGICAL__data_len + wire width 4 output 19 \LOGICAL__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 3 \LOGICAL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \LOGICAL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \LOGICAL__imm_data__ok + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 4 \LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 5 \LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LOGICAL__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \LOGICAL__input_carry + wire width 2 output 13 \LOGICAL__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \LOGICAL__insn + wire width 32 output 20 \LOGICAL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -188430,30 +190637,31 @@ module \dec_LOGICAL attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LOGICAL__insn_type + wire width 7 output 3 \LOGICAL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LOGICAL__invert_in + wire output 11 \LOGICAL__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \LOGICAL__invert_out + wire output 14 \LOGICAL__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \LOGICAL__is_32bit + wire output 17 \LOGICAL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \LOGICAL__is_signed + wire output 18 \LOGICAL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LOGICAL__oe__oe + wire output 9 \LOGICAL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LOGICAL__oe__ok + wire output 10 \LOGICAL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LOGICAL__output_carry + wire output 16 \LOGICAL__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LOGICAL__rc__ok + wire output 8 \LOGICAL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LOGICAL__rc__rc + wire output 7 \LOGICAL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LOGICAL__write_cr0 + wire output 15 \LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LOGICAL__zero_a + wire output 12 \LOGICAL__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -188494,21 +190702,22 @@ module \dec_LOGICAL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_LOGICAL_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_LOGICAL_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -188608,6 +190817,7 @@ module \dec_LOGICAL attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_LOGICAL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -188634,7 +190844,7 @@ module \dec_LOGICAL wire \dec_LOGICAL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -188642,8 +190852,10 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -188663,7 +190875,7 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -188673,7 +190885,7 @@ module \dec_LOGICAL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -188685,24 +190897,26 @@ module \dec_LOGICAL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120316.7-120316.15" + attribute \src "libresoc.v:121964.7-121964.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:120741$4595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire input 2 \sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122397$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188710,10 +190924,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:120741$4595_Y + connect \Y $and$libresoc.v:122397$4628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:120743$4597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122399$4630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188721,10 +190935,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:120743$4597_Y + connect \Y $and$libresoc.v:122399$4630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:120756$4610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122412$4643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188732,10 +190946,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:120756$4610_Y + connect \Y $and$libresoc.v:122412$4643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:120757$4611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122413$4644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188743,10 +190957,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120757$4611_Y + connect \Y $and$libresoc.v:122413$4644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:120759$4613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122415$4646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188754,10 +190968,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:120759$4613_Y + connect \Y $and$libresoc.v:122415$4646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:120761$4615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122417$4648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188765,10 +190979,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:120761$4615_Y + connect \Y $and$libresoc.v:122417$4648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:120762$4616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122418$4649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188776,10 +190990,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:120762$4616_Y + connect \Y $and$libresoc.v:122418$4649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:120763$4617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122419$4650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188787,10 +191001,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120763$4617_Y + connect \Y $and$libresoc.v:122419$4650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:120744$4598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:122400$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188798,10 +191012,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:120744$4598_Y + connect \Y $eq$libresoc.v:122400$4631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:120745$4599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122401$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188809,10 +191023,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:120745$4599_Y + connect \Y $eq$libresoc.v:122401$4632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:120747$4601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122403$4634 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188820,10 +191034,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:120747$4601_Y + connect \Y $eq$libresoc.v:122403$4634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:120748$4602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122404$4635 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188831,10 +191045,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:120748$4602_Y + connect \Y $eq$libresoc.v:122404$4635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:120750$4604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122406$4637 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188842,21 +191056,21 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:120750$4604_Y + connect \Y $eq$libresoc.v:122406$4637_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:120751$4605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:122407$4638 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:120751$4605_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122407$4638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:120753$4607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122409$4640 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188864,59 +191078,59 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:120753$4607_Y + connect \Y $eq$libresoc.v:122409$4640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:120755$4609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:122411$4642 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:120755$4609_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122411$4642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:120758$4612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:122414$4645 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:120758$4612_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122414$4645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:120764$4618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:122420$4651 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:120764$4618_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122420$4651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:120742$4596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:122398$4629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120742$4596_Y + connect \Y $not$libresoc.v:122398$4629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:120760$4614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:122416$4647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120760$4614_Y + connect \Y $not$libresoc.v:122416$4647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:120746$4600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:122402$4633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188924,10 +191138,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:120746$4600_Y + connect \Y $or$libresoc.v:122402$4633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:120749$4603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:122405$4636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188935,10 +191149,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:120749$4603_Y + connect \Y $or$libresoc.v:122405$4636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:120752$4606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:122408$4639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188946,10 +191160,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:120752$4606_Y + connect \Y $or$libresoc.v:122408$4639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:120754$4608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122410$4641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188957,10 +191171,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:120754$4608_Y + connect \Y $or$libresoc.v:122410$4641_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120765.13-120793.4" + attribute \src "libresoc.v:122421.13-122449.4" cell \dec$145 \dec connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -188991,14 +191205,15 @@ module \dec_LOGICAL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120794.16-120798.4" + attribute \src "libresoc.v:122450.16-122455.4" cell \dec_ai$148 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in + connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:120799.16-120810.4" + attribute \src "libresoc.v:122456.16-122467.4" cell \dec_bi$149 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -189012,7 +191227,7 @@ module \dec_LOGICAL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120811.16-120817.4" + attribute \src "libresoc.v:122468.16-122474.4" cell \dec_oe$147 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op @@ -189021,33 +191236,33 @@ module \dec_LOGICAL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120818.16-120823.4" + attribute \src "libresoc.v:122475.16-122480.4" cell \dec_rc$146 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120316.7-120316.20" - process $proc$libresoc.v:120316$4622 + attribute \src "libresoc.v:121964.7-121964.20" + process $proc$libresoc.v:121964$4655 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120824.3-120838.6" - process $proc$libresoc.v:120824$4619 + attribute \src "libresoc.v:122481.3-122495.6" + process $proc$libresoc.v:122481$4652 assign { } { } assign { } { } assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:120825.5-120825.29" + attribute \src "libresoc.v:122482.5-122482.29" switch \initial - attribute \src "libresoc.v:120825.9-120825.17" + attribute \src "libresoc.v:122482.9-122482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch \dec_LOGICAL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -189063,18 +191278,18 @@ module \dec_LOGICAL sync always update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] end - attribute \src "libresoc.v:120839.3-120851.6" - process $proc$libresoc.v:120839$4620 + attribute \src "libresoc.v:122496.3-122508.6" + process $proc$libresoc.v:122496$4653 assign { } { } assign { } { } assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:120840.5-120840.29" + attribute \src "libresoc.v:122497.5-122497.29" switch \initial - attribute \src "libresoc.v:120840.9-120840.17" + attribute \src "libresoc.v:122497.9-122497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -189090,58 +191305,58 @@ module \dec_LOGICAL sync always update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] end - attribute \src "libresoc.v:120852.3-120866.6" - process $proc$libresoc.v:120852$4621 + attribute \src "libresoc.v:122509.3-122523.6" + process $proc$libresoc.v:122509$4654 assign { } { } - assign $0\LOGICAL__fn_unit[12:0] $1\LOGICAL__fn_unit[12:0] - attribute \src "libresoc.v:120853.5-120853.29" + assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0] + attribute \src "libresoc.v:122510.5-122510.29" switch \initial - attribute \src "libresoc.v:120853.9-120853.17" + attribute \src "libresoc.v:122510.9-122510.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\LOGICAL__fn_unit[12:0] 13'0000000000000 + assign $1\LOGICAL__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\LOGICAL__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\LOGICAL__fn_unit[12:0] \dec_LOGICAL_function_unit - end - sync always - update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[12:0] - end - connect \$10 $and$libresoc.v:120741$4595_Y - connect \$12 $not$libresoc.v:120742$4596_Y - connect \$14 $and$libresoc.v:120743$4597_Y - connect \$16 $eq$libresoc.v:120744$4598_Y - connect \$18 $eq$libresoc.v:120745$4599_Y - connect \$20 $or$libresoc.v:120746$4600_Y - connect \$22 $eq$libresoc.v:120747$4601_Y - connect \$24 $eq$libresoc.v:120748$4602_Y - connect \$26 $or$libresoc.v:120749$4603_Y - connect \$28 $eq$libresoc.v:120750$4604_Y - connect \$2 $eq$libresoc.v:120751$4605_Y - connect \$30 $or$libresoc.v:120752$4606_Y - connect \$32 $eq$libresoc.v:120753$4607_Y - connect \$34 $or$libresoc.v:120754$4608_Y - connect \$36 $eq$libresoc.v:120755$4609_Y - connect \$38 $and$libresoc.v:120756$4610_Y - connect \$40 $and$libresoc.v:120757$4611_Y - connect \$42 $eq$libresoc.v:120758$4612_Y - connect \$44 $and$libresoc.v:120759$4613_Y - connect \$46 $not$libresoc.v:120760$4614_Y - connect \$48 $and$libresoc.v:120761$4615_Y - connect \$4 $and$libresoc.v:120762$4616_Y - connect \$6 $and$libresoc.v:120763$4617_Y - connect \$8 $eq$libresoc.v:120764$4618_Y + assign $1\LOGICAL__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\LOGICAL__fn_unit[13:0] \dec_LOGICAL_function_unit + end + sync always + update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:122397$4628_Y + connect \$12 $not$libresoc.v:122398$4629_Y + connect \$14 $and$libresoc.v:122399$4630_Y + connect \$16 $eq$libresoc.v:122400$4631_Y + connect \$18 $eq$libresoc.v:122401$4632_Y + connect \$20 $or$libresoc.v:122402$4633_Y + connect \$22 $eq$libresoc.v:122403$4634_Y + connect \$24 $eq$libresoc.v:122404$4635_Y + connect \$26 $or$libresoc.v:122405$4636_Y + connect \$28 $eq$libresoc.v:122406$4637_Y + connect \$2 $eq$libresoc.v:122407$4638_Y + connect \$30 $or$libresoc.v:122408$4639_Y + connect \$32 $eq$libresoc.v:122409$4640_Y + connect \$34 $or$libresoc.v:122410$4641_Y + connect \$36 $eq$libresoc.v:122411$4642_Y + connect \$38 $and$libresoc.v:122412$4643_Y + connect \$40 $and$libresoc.v:122413$4644_Y + connect \$42 $eq$libresoc.v:122414$4645_Y + connect \$44 $and$libresoc.v:122415$4646_Y + connect \$46 $not$libresoc.v:122416$4647_Y + connect \$48 $and$libresoc.v:122417$4648_Y + connect \$4 $and$libresoc.v:122418$4649_Y + connect \$6 $and$libresoc.v:122419$4650_Y + connect \$8 $eq$libresoc.v:122420$4651_Y connect \LOGICAL__is_signed \dec_LOGICAL_sgn connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b connect \LOGICAL__output_carry \dec_LOGICAL_cry_out @@ -189155,6 +191370,7 @@ module \dec_LOGICAL connect \dec_bi_sel_in \dec_LOGICAL_in2_sel connect \LOGICAL__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_LOGICAL_in1_sel + connect \dec_ai_sv_nz \sv_a_nz connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_LOGICAL_SPR [4:0] \dec_LOGICAL_SPR [9:5] } @@ -189164,137 +191380,138 @@ module \dec_LOGICAL connect \insn_in \dec_opcode_in connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:120892.1-121390.10" +attribute \src "libresoc.v:122550.1-123052.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL - attribute \src "libresoc.v:121361.3-121375.6" - wire width 13 $0\MUL__fn_unit[12:0] - attribute \src "libresoc.v:121348.3-121360.6" + attribute \src "libresoc.v:123023.3-123037.6" + wire width 14 $0\MUL__fn_unit[13:0] + attribute \src "libresoc.v:123010.3-123022.6" wire width 7 $0\MUL__insn_type[6:0] - attribute \src "libresoc.v:121333.3-121347.6" + attribute \src "libresoc.v:122995.3-123009.6" wire $0\MUL__write_cr0[0:0] - attribute \src "libresoc.v:120893.7-120893.20" + attribute \src "libresoc.v:122551.7-122551.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121361.3-121375.6" - wire width 13 $1\MUL__fn_unit[12:0] - attribute \src "libresoc.v:121348.3-121360.6" + attribute \src "libresoc.v:123023.3-123037.6" + wire width 14 $1\MUL__fn_unit[13:0] + attribute \src "libresoc.v:123010.3-123022.6" wire width 7 $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:121333.3-121347.6" + attribute \src "libresoc.v:122995.3-123009.6" wire $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:121262.18-121262.113" - wire $and$libresoc.v:121262$4623_Y - attribute \src "libresoc.v:121264.18-121264.110" - wire $and$libresoc.v:121264$4625_Y - attribute \src "libresoc.v:121277.18-121277.114" - wire $and$libresoc.v:121277$4638_Y - attribute \src "libresoc.v:121278.18-121278.116" - wire $and$libresoc.v:121278$4639_Y - attribute \src "libresoc.v:121280.18-121280.114" - wire $and$libresoc.v:121280$4641_Y - attribute \src "libresoc.v:121282.18-121282.110" - wire $and$libresoc.v:121282$4643_Y - attribute \src "libresoc.v:121283.17-121283.112" - wire $and$libresoc.v:121283$4644_Y - attribute \src "libresoc.v:121284.17-121284.114" - wire $and$libresoc.v:121284$4645_Y - attribute \src "libresoc.v:121265.18-121265.126" - wire $eq$libresoc.v:121265$4626_Y - attribute \src "libresoc.v:121266.18-121266.126" - wire $eq$libresoc.v:121266$4627_Y - attribute \src "libresoc.v:121268.18-121268.110" - wire $eq$libresoc.v:121268$4629_Y - attribute \src "libresoc.v:121269.18-121269.110" - wire $eq$libresoc.v:121269$4630_Y - attribute \src "libresoc.v:121271.18-121271.112" - wire $eq$libresoc.v:121271$4632_Y - attribute \src "libresoc.v:121272.17-121272.130" - wire $eq$libresoc.v:121272$4633_Y - attribute \src "libresoc.v:121274.18-121274.110" - wire $eq$libresoc.v:121274$4635_Y - attribute \src "libresoc.v:121276.18-121276.131" - wire $eq$libresoc.v:121276$4637_Y - attribute \src "libresoc.v:121279.18-121279.131" - wire $eq$libresoc.v:121279$4640_Y - attribute \src "libresoc.v:121285.17-121285.130" - wire $eq$libresoc.v:121285$4646_Y - attribute \src "libresoc.v:121263.18-121263.110" - wire $not$libresoc.v:121263$4624_Y - attribute \src "libresoc.v:121281.18-121281.110" - wire $not$libresoc.v:121281$4642_Y - attribute \src "libresoc.v:121267.18-121267.110" - wire $or$libresoc.v:121267$4628_Y - attribute \src "libresoc.v:121270.18-121270.110" - wire $or$libresoc.v:121270$4631_Y - attribute \src "libresoc.v:121273.18-121273.110" - wire $or$libresoc.v:121273$4634_Y - attribute \src "libresoc.v:121275.18-121275.110" - wire $or$libresoc.v:121275$4636_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "libresoc.v:122924.18-122924.113" + wire $and$libresoc.v:122924$4656_Y + attribute \src "libresoc.v:122926.18-122926.110" + wire $and$libresoc.v:122926$4658_Y + attribute \src "libresoc.v:122939.18-122939.114" + wire $and$libresoc.v:122939$4671_Y + attribute \src "libresoc.v:122940.18-122940.116" + wire $and$libresoc.v:122940$4672_Y + attribute \src "libresoc.v:122942.18-122942.114" + wire $and$libresoc.v:122942$4674_Y + attribute \src "libresoc.v:122944.18-122944.110" + wire $and$libresoc.v:122944$4676_Y + attribute \src "libresoc.v:122945.17-122945.112" + wire $and$libresoc.v:122945$4677_Y + attribute \src "libresoc.v:122946.17-122946.114" + wire $and$libresoc.v:122946$4678_Y + attribute \src "libresoc.v:122927.18-122927.126" + wire $eq$libresoc.v:122927$4659_Y + attribute \src "libresoc.v:122928.18-122928.126" + wire $eq$libresoc.v:122928$4660_Y + attribute \src "libresoc.v:122930.18-122930.110" + wire $eq$libresoc.v:122930$4662_Y + attribute \src "libresoc.v:122931.18-122931.110" + wire $eq$libresoc.v:122931$4663_Y + attribute \src "libresoc.v:122933.18-122933.112" + wire $eq$libresoc.v:122933$4665_Y + attribute \src "libresoc.v:122934.17-122934.130" + wire $eq$libresoc.v:122934$4666_Y + attribute \src "libresoc.v:122936.18-122936.110" + wire $eq$libresoc.v:122936$4668_Y + attribute \src "libresoc.v:122938.18-122938.131" + wire $eq$libresoc.v:122938$4670_Y + attribute \src "libresoc.v:122941.18-122941.131" + wire $eq$libresoc.v:122941$4673_Y + attribute \src "libresoc.v:122947.17-122947.130" + wire $eq$libresoc.v:122947$4679_Y + attribute \src "libresoc.v:122925.18-122925.110" + wire $not$libresoc.v:122925$4657_Y + attribute \src "libresoc.v:122943.18-122943.110" + wire $not$libresoc.v:122943$4675_Y + attribute \src "libresoc.v:122929.18-122929.110" + wire $or$libresoc.v:122929$4661_Y + attribute \src "libresoc.v:122932.18-122932.110" + wire $or$libresoc.v:122932$4664_Y + attribute \src "libresoc.v:122935.18-122935.110" + wire $or$libresoc.v:122935$4667_Y + attribute \src "libresoc.v:122937.18-122937.110" + wire $or$libresoc.v:122937$4669_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 3 \MUL__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 3 \MUL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 4 \MUL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -189375,6 +191592,7 @@ module \dec_MUL attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \MUL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -189421,21 +191639,22 @@ module \dec_MUL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_MUL_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_MUL_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -189527,6 +191746,7 @@ module \dec_MUL attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_MUL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -189560,7 +191780,7 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -189570,7 +191790,7 @@ module \dec_MUL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -189582,24 +191802,24 @@ module \dec_MUL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120893.7-120893.15" + attribute \src "libresoc.v:122551.7-122551.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 14 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:121262$4623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122924$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189607,10 +191827,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121262$4623_Y + connect \Y $and$libresoc.v:122924$4656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:121264$4625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122926$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189618,10 +191838,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121264$4625_Y + connect \Y $and$libresoc.v:122926$4658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:121277$4638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122939$4671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189629,10 +191849,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121277$4638_Y + connect \Y $and$libresoc.v:122939$4671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:121278$4639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122940$4672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189640,10 +191860,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121278$4639_Y + connect \Y $and$libresoc.v:122940$4672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:121280$4641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122942$4674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189651,10 +191871,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121280$4641_Y + connect \Y $and$libresoc.v:122942$4674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:121282$4643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:122944$4676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189662,10 +191882,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121282$4643_Y + connect \Y $and$libresoc.v:122944$4676_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:121283$4644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122945$4677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189673,10 +191893,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121283$4644_Y + connect \Y $and$libresoc.v:122945$4677_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:121284$4645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:122946$4678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189684,10 +191904,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121284$4645_Y + connect \Y $and$libresoc.v:122946$4678_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:121265$4626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:122927$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189695,10 +191915,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121265$4626_Y + connect \Y $eq$libresoc.v:122927$4659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:121266$4627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122928$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189706,10 +191926,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121266$4627_Y + connect \Y $eq$libresoc.v:122928$4660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:121268$4629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122930$4662 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189717,10 +191937,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121268$4629_Y + connect \Y $eq$libresoc.v:122930$4662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:121269$4630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122931$4663 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189728,10 +191948,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121269$4630_Y + connect \Y $eq$libresoc.v:122931$4663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:121271$4632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:122933$4665 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189739,21 +191959,21 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121271$4632_Y + connect \Y $eq$libresoc.v:122933$4665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:121272$4633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:122934$4666 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:121272$4633_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122934$4666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:121274$4635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122936$4668 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189761,59 +191981,59 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121274$4635_Y + connect \Y $eq$libresoc.v:122936$4668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:121276$4637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:122938$4670 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:121276$4637_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:122938$4670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:121279$4640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:122941$4673 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:121279$4640_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122941$4673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:121285$4646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:122947$4679 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:121285$4646_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:122947$4679_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:121263$4624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:122925$4657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121263$4624_Y + connect \Y $not$libresoc.v:122925$4657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:121281$4642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:122943$4675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121281$4642_Y + connect \Y $not$libresoc.v:122943$4675_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:121267$4628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:122929$4661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189821,10 +192041,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121267$4628_Y + connect \Y $or$libresoc.v:122929$4661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:121270$4631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:122932$4664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189832,10 +192052,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121270$4631_Y + connect \Y $or$libresoc.v:122932$4664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:121273$4634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:122935$4667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189843,10 +192063,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121273$4634_Y + connect \Y $or$libresoc.v:122935$4667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:121275$4636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122937$4669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189854,10 +192074,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121275$4636_Y + connect \Y $or$libresoc.v:122937$4669_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121286.13-121307.4" + attribute \src "libresoc.v:122948.13-122969.4" cell \dec$158 \dec connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -189881,7 +192101,7 @@ module \dec_MUL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121308.16-121319.4" + attribute \src "libresoc.v:122970.16-122981.4" cell \dec_bi$161 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -189895,7 +192115,7 @@ module \dec_MUL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121320.16-121326.4" + attribute \src "libresoc.v:122982.16-122988.4" cell \dec_oe$160 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op @@ -189904,33 +192124,33 @@ module \dec_MUL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121327.16-121332.4" + attribute \src "libresoc.v:122989.16-122994.4" cell \dec_rc$159 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120893.7-120893.20" - process $proc$libresoc.v:120893$4650 + attribute \src "libresoc.v:122551.7-122551.20" + process $proc$libresoc.v:122551$4683 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121333.3-121347.6" - process $proc$libresoc.v:121333$4647 + attribute \src "libresoc.v:122995.3-123009.6" + process $proc$libresoc.v:122995$4680 assign { } { } assign { } { } assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:121334.5-121334.29" + attribute \src "libresoc.v:122996.5-122996.29" switch \initial - attribute \src "libresoc.v:121334.9-121334.17" + attribute \src "libresoc.v:122996.9-122996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch \dec_MUL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -189946,18 +192166,18 @@ module \dec_MUL sync always update \MUL__write_cr0 $0\MUL__write_cr0[0:0] end - attribute \src "libresoc.v:121348.3-121360.6" - process $proc$libresoc.v:121348$4648 + attribute \src "libresoc.v:123010.3-123022.6" + process $proc$libresoc.v:123010$4681 assign { } { } assign { } { } assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:121349.5-121349.29" + attribute \src "libresoc.v:123011.5-123011.29" switch \initial - attribute \src "libresoc.v:121349.9-121349.17" + attribute \src "libresoc.v:123011.9-123011.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -189973,58 +192193,58 @@ module \dec_MUL sync always update \MUL__insn_type $0\MUL__insn_type[6:0] end - attribute \src "libresoc.v:121361.3-121375.6" - process $proc$libresoc.v:121361$4649 + attribute \src "libresoc.v:123023.3-123037.6" + process $proc$libresoc.v:123023$4682 assign { } { } - assign $0\MUL__fn_unit[12:0] $1\MUL__fn_unit[12:0] - attribute \src "libresoc.v:121362.5-121362.29" + assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] + attribute \src "libresoc.v:123024.5-123024.29" switch \initial - attribute \src "libresoc.v:121362.9-121362.17" + attribute \src "libresoc.v:123024.9-123024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\MUL__fn_unit[12:0] 13'0000000000000 + assign $1\MUL__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\MUL__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\MUL__fn_unit[12:0] \dec_MUL_function_unit - end - sync always - update \MUL__fn_unit $0\MUL__fn_unit[12:0] - end - connect \$10 $and$libresoc.v:121262$4623_Y - connect \$12 $not$libresoc.v:121263$4624_Y - connect \$14 $and$libresoc.v:121264$4625_Y - connect \$16 $eq$libresoc.v:121265$4626_Y - connect \$18 $eq$libresoc.v:121266$4627_Y - connect \$20 $or$libresoc.v:121267$4628_Y - connect \$22 $eq$libresoc.v:121268$4629_Y - connect \$24 $eq$libresoc.v:121269$4630_Y - connect \$26 $or$libresoc.v:121270$4631_Y - connect \$28 $eq$libresoc.v:121271$4632_Y - connect \$2 $eq$libresoc.v:121272$4633_Y - connect \$30 $or$libresoc.v:121273$4634_Y - connect \$32 $eq$libresoc.v:121274$4635_Y - connect \$34 $or$libresoc.v:121275$4636_Y - connect \$36 $eq$libresoc.v:121276$4637_Y - connect \$38 $and$libresoc.v:121277$4638_Y - connect \$40 $and$libresoc.v:121278$4639_Y - connect \$42 $eq$libresoc.v:121279$4640_Y - connect \$44 $and$libresoc.v:121280$4641_Y - connect \$46 $not$libresoc.v:121281$4642_Y - connect \$48 $and$libresoc.v:121282$4643_Y - connect \$4 $and$libresoc.v:121283$4644_Y - connect \$6 $and$libresoc.v:121284$4645_Y - connect \$8 $eq$libresoc.v:121285$4646_Y + assign $1\MUL__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\MUL__fn_unit[13:0] \dec_MUL_function_unit + end + sync always + update \MUL__fn_unit $0\MUL__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:122924$4656_Y + connect \$12 $not$libresoc.v:122925$4657_Y + connect \$14 $and$libresoc.v:122926$4658_Y + connect \$16 $eq$libresoc.v:122927$4659_Y + connect \$18 $eq$libresoc.v:122928$4660_Y + connect \$20 $or$libresoc.v:122929$4661_Y + connect \$22 $eq$libresoc.v:122930$4662_Y + connect \$24 $eq$libresoc.v:122931$4663_Y + connect \$26 $or$libresoc.v:122932$4664_Y + connect \$28 $eq$libresoc.v:122933$4665_Y + connect \$2 $eq$libresoc.v:122934$4666_Y + connect \$30 $or$libresoc.v:122935$4667_Y + connect \$32 $eq$libresoc.v:122936$4668_Y + connect \$34 $or$libresoc.v:122937$4669_Y + connect \$36 $eq$libresoc.v:122938$4670_Y + connect \$38 $and$libresoc.v:122939$4671_Y + connect \$40 $and$libresoc.v:122940$4672_Y + connect \$42 $eq$libresoc.v:122941$4673_Y + connect \$44 $and$libresoc.v:122942$4674_Y + connect \$46 $not$libresoc.v:122943$4675_Y + connect \$48 $and$libresoc.v:122944$4676_Y + connect \$4 $and$libresoc.v:122945$4677_Y + connect \$6 $and$libresoc.v:122946$4678_Y + connect \$8 $eq$libresoc.v:122947$4679_Y connect \MUL__is_signed \dec_MUL_sgn connect \MUL__is_32bit \dec_MUL_is_32b connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } @@ -190040,137 +192260,138 @@ module \dec_MUL connect \insn_in \dec_opcode_in connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:121394.1-121936.10" +attribute \src "libresoc.v:123056.1-123602.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT - attribute \src "libresoc.v:121902.3-121916.6" - wire width 13 $0\SHIFT_ROT__fn_unit[12:0] - attribute \src "libresoc.v:121889.3-121901.6" + attribute \src "libresoc.v:123568.3-123582.6" + wire width 14 $0\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:123555.3-123567.6" wire width 7 $0\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:121874.3-121888.6" + attribute \src "libresoc.v:123540.3-123554.6" wire $0\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:121395.7-121395.20" + attribute \src "libresoc.v:123057.7-123057.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121902.3-121916.6" - wire width 13 $1\SHIFT_ROT__fn_unit[12:0] - attribute \src "libresoc.v:121889.3-121901.6" + attribute \src "libresoc.v:123568.3-123582.6" + wire width 14 $1\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:123555.3-123567.6" wire width 7 $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:121874.3-121888.6" + attribute \src "libresoc.v:123540.3-123554.6" wire $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:121799.18-121799.113" - wire $and$libresoc.v:121799$4651_Y - attribute \src "libresoc.v:121801.18-121801.110" - wire $and$libresoc.v:121801$4653_Y - attribute \src "libresoc.v:121814.18-121814.114" - wire $and$libresoc.v:121814$4666_Y - attribute \src "libresoc.v:121815.18-121815.116" - wire $and$libresoc.v:121815$4667_Y - attribute \src "libresoc.v:121817.18-121817.114" - wire $and$libresoc.v:121817$4669_Y - attribute \src "libresoc.v:121819.18-121819.110" - wire $and$libresoc.v:121819$4671_Y - attribute \src "libresoc.v:121820.17-121820.112" - wire $and$libresoc.v:121820$4672_Y - attribute \src "libresoc.v:121821.17-121821.114" - wire $and$libresoc.v:121821$4673_Y - attribute \src "libresoc.v:121802.18-121802.132" - wire $eq$libresoc.v:121802$4654_Y - attribute \src "libresoc.v:121803.18-121803.132" - wire $eq$libresoc.v:121803$4655_Y - attribute \src "libresoc.v:121805.18-121805.110" - wire $eq$libresoc.v:121805$4657_Y - attribute \src "libresoc.v:121806.18-121806.110" - wire $eq$libresoc.v:121806$4658_Y - attribute \src "libresoc.v:121808.18-121808.112" - wire $eq$libresoc.v:121808$4660_Y - attribute \src "libresoc.v:121809.17-121809.136" - wire $eq$libresoc.v:121809$4661_Y - attribute \src "libresoc.v:121811.18-121811.110" - wire $eq$libresoc.v:121811$4663_Y - attribute \src "libresoc.v:121813.18-121813.137" - wire $eq$libresoc.v:121813$4665_Y - attribute \src "libresoc.v:121816.18-121816.137" - wire $eq$libresoc.v:121816$4668_Y - attribute \src "libresoc.v:121822.17-121822.136" - wire $eq$libresoc.v:121822$4674_Y - attribute \src "libresoc.v:121800.18-121800.110" - wire $not$libresoc.v:121800$4652_Y - attribute \src "libresoc.v:121818.18-121818.110" - wire $not$libresoc.v:121818$4670_Y - attribute \src "libresoc.v:121804.18-121804.110" - wire $or$libresoc.v:121804$4656_Y - attribute \src "libresoc.v:121807.18-121807.110" - wire $or$libresoc.v:121807$4659_Y - attribute \src "libresoc.v:121810.18-121810.110" - wire $or$libresoc.v:121810$4662_Y - attribute \src "libresoc.v:121812.18-121812.110" - wire $or$libresoc.v:121812$4664_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "libresoc.v:123465.18-123465.113" + wire $and$libresoc.v:123465$4684_Y + attribute \src "libresoc.v:123467.18-123467.110" + wire $and$libresoc.v:123467$4686_Y + attribute \src "libresoc.v:123480.18-123480.114" + wire $and$libresoc.v:123480$4699_Y + attribute \src "libresoc.v:123481.18-123481.116" + wire $and$libresoc.v:123481$4700_Y + attribute \src "libresoc.v:123483.18-123483.114" + wire $and$libresoc.v:123483$4702_Y + attribute \src "libresoc.v:123485.18-123485.110" + wire $and$libresoc.v:123485$4704_Y + attribute \src "libresoc.v:123486.17-123486.112" + wire $and$libresoc.v:123486$4705_Y + attribute \src "libresoc.v:123487.17-123487.114" + wire $and$libresoc.v:123487$4706_Y + attribute \src "libresoc.v:123468.18-123468.132" + wire $eq$libresoc.v:123468$4687_Y + attribute \src "libresoc.v:123469.18-123469.132" + wire $eq$libresoc.v:123469$4688_Y + attribute \src "libresoc.v:123471.18-123471.110" + wire $eq$libresoc.v:123471$4690_Y + attribute \src "libresoc.v:123472.18-123472.110" + wire $eq$libresoc.v:123472$4691_Y + attribute \src "libresoc.v:123474.18-123474.112" + wire $eq$libresoc.v:123474$4693_Y + attribute \src "libresoc.v:123475.17-123475.136" + wire $eq$libresoc.v:123475$4694_Y + attribute \src "libresoc.v:123477.18-123477.110" + wire $eq$libresoc.v:123477$4696_Y + attribute \src "libresoc.v:123479.18-123479.137" + wire $eq$libresoc.v:123479$4698_Y + attribute \src "libresoc.v:123482.18-123482.137" + wire $eq$libresoc.v:123482$4701_Y + attribute \src "libresoc.v:123488.17-123488.136" + wire $eq$libresoc.v:123488$4707_Y + attribute \src "libresoc.v:123466.18-123466.110" + wire $not$libresoc.v:123466$4685_Y + attribute \src "libresoc.v:123484.18-123484.110" + wire $not$libresoc.v:123484$4703_Y + attribute \src "libresoc.v:123470.18-123470.110" + wire $or$libresoc.v:123470$4689_Y + attribute \src "libresoc.v:123473.18-123473.110" + wire $or$libresoc.v:123473$4692_Y + attribute \src "libresoc.v:123476.18-123476.110" + wire $or$libresoc.v:123476$4695_Y + attribute \src "libresoc.v:123478.18-123478.110" + wire $or$libresoc.v:123478$4697_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 3 \SHIFT_ROT__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 3 \SHIFT_ROT__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 4 \SHIFT_ROT__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -190259,6 +192480,7 @@ module \dec_SHIFT_ROT attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \SHIFT_ROT__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -190330,21 +192552,22 @@ module \dec_SHIFT_ROT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_SHIFT_ROT_cry_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_SHIFT_ROT_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -190436,6 +192659,7 @@ module \dec_SHIFT_ROT attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_SHIFT_ROT_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -190471,7 +192695,7 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -190481,7 +192705,7 @@ module \dec_SHIFT_ROT attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -190493,24 +192717,24 @@ module \dec_SHIFT_ROT attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121395.7-121395.15" + attribute \src "libresoc.v:123057.7-123057.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:121799$4651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123465$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190518,10 +192742,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121799$4651_Y + connect \Y $and$libresoc.v:123465$4684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:121801$4653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123467$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190529,10 +192753,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121801$4653_Y + connect \Y $and$libresoc.v:123467$4686_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:121814$4666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123480$4699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190540,10 +192764,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121814$4666_Y + connect \Y $and$libresoc.v:123480$4699_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:121815$4667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123481$4700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190551,10 +192775,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121815$4667_Y + connect \Y $and$libresoc.v:123481$4700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:121817$4669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123483$4702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190562,10 +192786,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121817$4669_Y + connect \Y $and$libresoc.v:123483$4702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:121819$4671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123485$4704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190573,10 +192797,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121819$4671_Y + connect \Y $and$libresoc.v:123485$4704_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:121820$4672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123486$4705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190584,10 +192808,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121820$4672_Y + connect \Y $and$libresoc.v:123486$4705_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:121821$4673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123487$4706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190595,10 +192819,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121821$4673_Y + connect \Y $and$libresoc.v:123487$4706_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:121802$4654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:123468$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190606,10 +192830,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121802$4654_Y + connect \Y $eq$libresoc.v:123468$4687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:121803$4655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:123469$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190617,10 +192841,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121803$4655_Y + connect \Y $eq$libresoc.v:123469$4688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:121805$4657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123471$4690 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190628,10 +192852,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121805$4657_Y + connect \Y $eq$libresoc.v:123471$4690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:121806$4658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123472$4691 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190639,10 +192863,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121806$4658_Y + connect \Y $eq$libresoc.v:123472$4691_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:121808$4660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123474$4693 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190650,21 +192874,21 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121808$4660_Y + connect \Y $eq$libresoc.v:123474$4693_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:121809$4661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:123475$4694 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:121809$4661_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123475$4694_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:121811$4663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123477$4696 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190672,59 +192896,59 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121811$4663_Y + connect \Y $eq$libresoc.v:123477$4696_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:121813$4665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:123479$4698 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:121813$4665_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123479$4698_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:121816$4668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:123482$4701 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:121816$4668_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123482$4701_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:121822$4674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:123488$4707 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:121822$4674_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123488$4707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:121800$4652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:123466$4685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121800$4652_Y + connect \Y $not$libresoc.v:123466$4685_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:121818$4670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:123484$4703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121818$4670_Y + connect \Y $not$libresoc.v:123484$4703_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:121804$4656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:123470$4689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190732,10 +192956,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121804$4656_Y + connect \Y $or$libresoc.v:123470$4689_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:121807$4659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:123473$4692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190743,10 +192967,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121807$4659_Y + connect \Y $or$libresoc.v:123473$4692_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:121810$4662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:123476$4695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190754,10 +192978,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121810$4662_Y + connect \Y $or$libresoc.v:123476$4695_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:121812$4664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123478$4697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190765,10 +192989,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121812$4664_Y + connect \Y $or$libresoc.v:123478$4697_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121823.13-121848.4" + attribute \src "libresoc.v:123489.13-123514.4" cell \dec$162 \dec connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -190796,7 +193020,7 @@ module \dec_SHIFT_ROT connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121849.16-121860.4" + attribute \src "libresoc.v:123515.16-123526.4" cell \dec_bi$165 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -190810,7 +193034,7 @@ module \dec_SHIFT_ROT connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121861.16-121867.4" + attribute \src "libresoc.v:123527.16-123533.4" cell \dec_oe$164 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op @@ -190819,33 +193043,33 @@ module \dec_SHIFT_ROT connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121868.16-121873.4" + attribute \src "libresoc.v:123534.16-123539.4" cell \dec_rc$163 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121395.7-121395.20" - process $proc$libresoc.v:121395$4678 + attribute \src "libresoc.v:123057.7-123057.20" + process $proc$libresoc.v:123057$4711 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121874.3-121888.6" - process $proc$libresoc.v:121874$4675 + attribute \src "libresoc.v:123540.3-123554.6" + process $proc$libresoc.v:123540$4708 assign { } { } assign { } { } assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:121875.5-121875.29" + attribute \src "libresoc.v:123541.5-123541.29" switch \initial - attribute \src "libresoc.v:121875.9-121875.17" + attribute \src "libresoc.v:123541.9-123541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch \dec_SHIFT_ROT_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -190861,18 +193085,18 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] end - attribute \src "libresoc.v:121889.3-121901.6" - process $proc$libresoc.v:121889$4676 + attribute \src "libresoc.v:123555.3-123567.6" + process $proc$libresoc.v:123555$4709 assign { } { } assign { } { } assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:121890.5-121890.29" + attribute \src "libresoc.v:123556.5-123556.29" switch \initial - attribute \src "libresoc.v:121890.9-121890.17" + attribute \src "libresoc.v:123556.9-123556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190888,58 +193112,58 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] end - attribute \src "libresoc.v:121902.3-121916.6" - process $proc$libresoc.v:121902$4677 + attribute \src "libresoc.v:123568.3-123582.6" + process $proc$libresoc.v:123568$4710 assign { } { } - assign $0\SHIFT_ROT__fn_unit[12:0] $1\SHIFT_ROT__fn_unit[12:0] - attribute \src "libresoc.v:121903.5-121903.29" + assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] + attribute \src "libresoc.v:123569.5-123569.29" switch \initial - attribute \src "libresoc.v:121903.9-121903.17" + attribute \src "libresoc.v:123569.9-123569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\SHIFT_ROT__fn_unit[12:0] 13'0000000000000 + assign $1\SHIFT_ROT__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\SHIFT_ROT__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\SHIFT_ROT__fn_unit[12:0] \dec_SHIFT_ROT_function_unit - end - sync always - update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[12:0] - end - connect \$10 $and$libresoc.v:121799$4651_Y - connect \$12 $not$libresoc.v:121800$4652_Y - connect \$14 $and$libresoc.v:121801$4653_Y - connect \$16 $eq$libresoc.v:121802$4654_Y - connect \$18 $eq$libresoc.v:121803$4655_Y - connect \$20 $or$libresoc.v:121804$4656_Y - connect \$22 $eq$libresoc.v:121805$4657_Y - connect \$24 $eq$libresoc.v:121806$4658_Y - connect \$26 $or$libresoc.v:121807$4659_Y - connect \$28 $eq$libresoc.v:121808$4660_Y - connect \$2 $eq$libresoc.v:121809$4661_Y - connect \$30 $or$libresoc.v:121810$4662_Y - connect \$32 $eq$libresoc.v:121811$4663_Y - connect \$34 $or$libresoc.v:121812$4664_Y - connect \$36 $eq$libresoc.v:121813$4665_Y - connect \$38 $and$libresoc.v:121814$4666_Y - connect \$40 $and$libresoc.v:121815$4667_Y - connect \$42 $eq$libresoc.v:121816$4668_Y - connect \$44 $and$libresoc.v:121817$4669_Y - connect \$46 $not$libresoc.v:121818$4670_Y - connect \$48 $and$libresoc.v:121819$4671_Y - connect \$4 $and$libresoc.v:121820$4672_Y - connect \$6 $and$libresoc.v:121821$4673_Y - connect \$8 $eq$libresoc.v:121822$4674_Y + assign $1\SHIFT_ROT__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\SHIFT_ROT__fn_unit[13:0] \dec_SHIFT_ROT_function_unit + end + sync always + update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:123465$4684_Y + connect \$12 $not$libresoc.v:123466$4685_Y + connect \$14 $and$libresoc.v:123467$4686_Y + connect \$16 $eq$libresoc.v:123468$4687_Y + connect \$18 $eq$libresoc.v:123469$4688_Y + connect \$20 $or$libresoc.v:123470$4689_Y + connect \$22 $eq$libresoc.v:123471$4690_Y + connect \$24 $eq$libresoc.v:123472$4691_Y + connect \$26 $or$libresoc.v:123473$4692_Y + connect \$28 $eq$libresoc.v:123474$4693_Y + connect \$2 $eq$libresoc.v:123475$4694_Y + connect \$30 $or$libresoc.v:123476$4695_Y + connect \$32 $eq$libresoc.v:123477$4696_Y + connect \$34 $or$libresoc.v:123478$4697_Y + connect \$36 $eq$libresoc.v:123479$4698_Y + connect \$38 $and$libresoc.v:123480$4699_Y + connect \$40 $and$libresoc.v:123481$4700_Y + connect \$42 $eq$libresoc.v:123482$4701_Y + connect \$44 $and$libresoc.v:123483$4702_Y + connect \$46 $not$libresoc.v:123484$4703_Y + connect \$48 $and$libresoc.v:123485$4704_Y + connect \$4 $and$libresoc.v:123486$4705_Y + connect \$6 $and$libresoc.v:123487$4706_Y + connect \$8 $eq$libresoc.v:123488$4707_Y connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out @@ -190960,133 +193184,134 @@ module \dec_SHIFT_ROT connect \insn_in \dec_opcode_in connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:121940.1-122314.10" +attribute \src "libresoc.v:123606.1-123984.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR - attribute \src "libresoc.v:122290.3-122304.6" - wire width 13 $0\SPR__fn_unit[12:0] - attribute \src "libresoc.v:122277.3-122289.6" + attribute \src "libresoc.v:123960.3-123974.6" + wire width 14 $0\SPR__fn_unit[13:0] + attribute \src "libresoc.v:123947.3-123959.6" wire width 7 $0\SPR__insn_type[6:0] - attribute \src "libresoc.v:121941.7-121941.20" + attribute \src "libresoc.v:123607.7-123607.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122290.3-122304.6" - wire width 13 $1\SPR__fn_unit[12:0] - attribute \src "libresoc.v:122277.3-122289.6" + attribute \src "libresoc.v:123960.3-123974.6" + wire width 14 $1\SPR__fn_unit[13:0] + attribute \src "libresoc.v:123947.3-123959.6" wire width 7 $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:122231.18-122231.113" - wire $and$libresoc.v:122231$4679_Y - attribute \src "libresoc.v:122233.18-122233.110" - wire $and$libresoc.v:122233$4681_Y - attribute \src "libresoc.v:122246.18-122246.114" - wire $and$libresoc.v:122246$4694_Y - attribute \src "libresoc.v:122247.18-122247.116" - wire $and$libresoc.v:122247$4695_Y - attribute \src "libresoc.v:122249.18-122249.114" - wire $and$libresoc.v:122249$4697_Y - attribute \src "libresoc.v:122251.18-122251.110" - wire $and$libresoc.v:122251$4699_Y - attribute \src "libresoc.v:122252.17-122252.112" - wire $and$libresoc.v:122252$4700_Y - attribute \src "libresoc.v:122253.17-122253.114" - wire $and$libresoc.v:122253$4701_Y - attribute \src "libresoc.v:122234.18-122234.126" - wire $eq$libresoc.v:122234$4682_Y - attribute \src "libresoc.v:122235.18-122235.126" - wire $eq$libresoc.v:122235$4683_Y - attribute \src "libresoc.v:122237.18-122237.110" - wire $eq$libresoc.v:122237$4685_Y - attribute \src "libresoc.v:122238.18-122238.110" - wire $eq$libresoc.v:122238$4686_Y - attribute \src "libresoc.v:122240.18-122240.112" - wire $eq$libresoc.v:122240$4688_Y - attribute \src "libresoc.v:122241.17-122241.130" - wire $eq$libresoc.v:122241$4689_Y - attribute \src "libresoc.v:122243.18-122243.110" - wire $eq$libresoc.v:122243$4691_Y - attribute \src "libresoc.v:122245.18-122245.131" - wire $eq$libresoc.v:122245$4693_Y - attribute \src "libresoc.v:122248.18-122248.131" - wire $eq$libresoc.v:122248$4696_Y - attribute \src "libresoc.v:122254.17-122254.130" - wire $eq$libresoc.v:122254$4702_Y - attribute \src "libresoc.v:122232.18-122232.110" - wire $not$libresoc.v:122232$4680_Y - attribute \src "libresoc.v:122250.18-122250.110" - wire $not$libresoc.v:122250$4698_Y - attribute \src "libresoc.v:122236.18-122236.110" - wire $or$libresoc.v:122236$4684_Y - attribute \src "libresoc.v:122239.18-122239.110" - wire $or$libresoc.v:122239$4687_Y - attribute \src "libresoc.v:122242.18-122242.110" - wire $or$libresoc.v:122242$4690_Y - attribute \src "libresoc.v:122244.18-122244.110" - wire $or$libresoc.v:122244$4692_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "libresoc.v:123901.18-123901.113" + wire $and$libresoc.v:123901$4712_Y + attribute \src "libresoc.v:123903.18-123903.110" + wire $and$libresoc.v:123903$4714_Y + attribute \src "libresoc.v:123916.18-123916.114" + wire $and$libresoc.v:123916$4727_Y + attribute \src "libresoc.v:123917.18-123917.116" + wire $and$libresoc.v:123917$4728_Y + attribute \src "libresoc.v:123919.18-123919.114" + wire $and$libresoc.v:123919$4730_Y + attribute \src "libresoc.v:123921.18-123921.110" + wire $and$libresoc.v:123921$4732_Y + attribute \src "libresoc.v:123922.17-123922.112" + wire $and$libresoc.v:123922$4733_Y + attribute \src "libresoc.v:123923.17-123923.114" + wire $and$libresoc.v:123923$4734_Y + attribute \src "libresoc.v:123904.18-123904.126" + wire $eq$libresoc.v:123904$4715_Y + attribute \src "libresoc.v:123905.18-123905.126" + wire $eq$libresoc.v:123905$4716_Y + attribute \src "libresoc.v:123907.18-123907.110" + wire $eq$libresoc.v:123907$4718_Y + attribute \src "libresoc.v:123908.18-123908.110" + wire $eq$libresoc.v:123908$4719_Y + attribute \src "libresoc.v:123910.18-123910.112" + wire $eq$libresoc.v:123910$4721_Y + attribute \src "libresoc.v:123911.17-123911.130" + wire $eq$libresoc.v:123911$4722_Y + attribute \src "libresoc.v:123913.18-123913.110" + wire $eq$libresoc.v:123913$4724_Y + attribute \src "libresoc.v:123915.18-123915.131" + wire $eq$libresoc.v:123915$4726_Y + attribute \src "libresoc.v:123918.18-123918.131" + wire $eq$libresoc.v:123918$4729_Y + attribute \src "libresoc.v:123924.17-123924.130" + wire $eq$libresoc.v:123924$4735_Y + attribute \src "libresoc.v:123902.18-123902.110" + wire $not$libresoc.v:123902$4713_Y + attribute \src "libresoc.v:123920.18-123920.110" + wire $not$libresoc.v:123920$4731_Y + attribute \src "libresoc.v:123906.18-123906.110" + wire $or$libresoc.v:123906$4717_Y + attribute \src "libresoc.v:123909.18-123909.110" + wire $or$libresoc.v:123909$4720_Y + attribute \src "libresoc.v:123912.18-123912.110" + wire $or$libresoc.v:123912$4723_Y + attribute \src "libresoc.v:123914.18-123914.110" + wire $or$libresoc.v:123914$4725_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" wire \$8 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 3 \SPR__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 3 \SPR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 4 \SPR__insn attribute \enum_base_type "MicrOp" @@ -191163,6 +193388,7 @@ module \dec_SPR attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -191185,21 +193411,22 @@ module \dec_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_SPR_cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 \dec_SPR_function_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 14 \dec_SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -191274,6 +193501,7 @@ module \dec_SPR attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_SPR_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -191288,7 +193516,7 @@ module \dec_SPR attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -191296,24 +193524,24 @@ module \dec_SPR attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121941.7-121941.15" + attribute \src "libresoc.v:123607.7-123607.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 6 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:122231$4679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123901$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191321,10 +193549,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122231$4679_Y + connect \Y $and$libresoc.v:123901$4712_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:122233$4681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123903$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191332,10 +193560,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122233$4681_Y + connect \Y $and$libresoc.v:123903$4714_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:122246$4694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123916$4727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191343,10 +193571,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122246$4694_Y + connect \Y $and$libresoc.v:123916$4727_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:122247$4695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123917$4728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191354,10 +193582,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122247$4695_Y + connect \Y $and$libresoc.v:123917$4728_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:122249$4697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123919$4730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191365,10 +193593,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122249$4697_Y + connect \Y $and$libresoc.v:123919$4730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $and $and$libresoc.v:122251$4699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $and $and$libresoc.v:123921$4732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191376,10 +193604,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122251$4699_Y + connect \Y $and$libresoc.v:123921$4732_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:122252$4700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123922$4733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191387,10 +193615,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122252$4700_Y + connect \Y $and$libresoc.v:123922$4733_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $and $and$libresoc.v:122253$4701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $and $and$libresoc.v:123923$4734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191398,10 +193626,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122253$4701_Y + connect \Y $and$libresoc.v:123923$4734_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:809" - cell $eq $eq$libresoc.v:122234$4682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:123904$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191409,10 +193637,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122234$4682_Y + connect \Y $eq$libresoc.v:123904$4715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $eq $eq$libresoc.v:122235$4683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:123905$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191420,10 +193648,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122235$4683_Y + connect \Y $eq$libresoc.v:123905$4716_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:122237$4685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123907$4718 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191431,10 +193659,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122237$4685_Y + connect \Y $eq$libresoc.v:123907$4718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:122238$4686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123908$4719 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191442,10 +193670,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122238$4686_Y + connect \Y $eq$libresoc.v:123908$4719_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $eq $eq$libresoc.v:122240$4688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $eq $eq$libresoc.v:123910$4721 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191453,21 +193681,21 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122240$4688_Y + connect \Y $eq$libresoc.v:123910$4721_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:122241$4689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:123911$4722 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:122241$4689_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123911$4722_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:122243$4691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123913$4724 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191475,59 +193703,59 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122243$4691_Y + connect \Y $eq$libresoc.v:123913$4724_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:122245$4693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + cell $eq $eq$libresoc.v:123915$4726 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit - connect \B 13'0010000000000 - connect \Y $eq$libresoc.v:122245$4693_Y + connect \B 14'00010000000000 + connect \Y $eq$libresoc.v:123915$4726_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:122248$4696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:123918$4729 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:122248$4696_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123918$4729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:122254$4702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $eq $eq$libresoc.v:123924$4735 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit - connect \B 13'0100000000000 - connect \Y $eq$libresoc.v:122254$4702_Y + connect \B 14'00100000000000 + connect \Y $eq$libresoc.v:123924$4735_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:122232$4680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:123902$4713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122232$4680_Y + connect \Y $not$libresoc.v:123902$4713_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $not $not$libresoc.v:122250$4698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + cell $not $not$libresoc.v:123920$4731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122250$4698_Y + connect \Y $not$libresoc.v:123920$4731_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" - cell $or $or$libresoc.v:122236$4684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $or $or$libresoc.v:123906$4717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191535,10 +193763,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122236$4684_Y + connect \Y $or$libresoc.v:123906$4717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:122239$4687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:123909$4720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191546,10 +193774,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122239$4687_Y + connect \Y $or$libresoc.v:123909$4720_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" - cell $or $or$libresoc.v:122242$4690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + cell $or $or$libresoc.v:123912$4723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191557,10 +193785,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122242$4690_Y + connect \Y $or$libresoc.v:123912$4723_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $or $or$libresoc.v:122244$4692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123914$4725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191568,10 +193796,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122244$4692_Y + connect \Y $or$libresoc.v:123914$4725_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122255.13-122267.4" + attribute \src "libresoc.v:123925.13-123937.4" cell \dec$150 \dec connect \SPR_OE \dec_SPR_OE connect \SPR_Rc \dec_SPR_Rc @@ -191586,38 +193814,38 @@ module \dec_SPR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122268.16-122272.4" + attribute \src "libresoc.v:123938.16-123942.4" cell \dec_oe$152 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122273.16-122276.4" + attribute \src "libresoc.v:123943.16-123946.4" cell \dec_rc$151 \dec_rc connect \SPR_Rc \dec_SPR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121941.7-121941.20" - process $proc$libresoc.v:121941$4705 + attribute \src "libresoc.v:123607.7-123607.20" + process $proc$libresoc.v:123607$4738 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122277.3-122289.6" - process $proc$libresoc.v:122277$4703 + attribute \src "libresoc.v:123947.3-123959.6" + process $proc$libresoc.v:123947$4736 assign { } { } assign { } { } assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:122278.5-122278.29" + attribute \src "libresoc.v:123948.5-123948.29" switch \initial - attribute \src "libresoc.v:122278.9-122278.17" + attribute \src "libresoc.v:123948.9-123948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -191633,58 +193861,58 @@ module \dec_SPR sync always update \SPR__insn_type $0\SPR__insn_type[6:0] end - attribute \src "libresoc.v:122290.3-122304.6" - process $proc$libresoc.v:122290$4704 + attribute \src "libresoc.v:123960.3-123974.6" + process $proc$libresoc.v:123960$4737 assign { } { } - assign $0\SPR__fn_unit[12:0] $1\SPR__fn_unit[12:0] - attribute \src "libresoc.v:122291.5-122291.29" + assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] + attribute \src "libresoc.v:123961.5-123961.29" switch \initial - attribute \src "libresoc.v:122291.9-122291.17" + attribute \src "libresoc.v:123961.9-123961.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\SPR__fn_unit[12:0] 13'0000000000000 + assign $1\SPR__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\SPR__fn_unit[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\SPR__fn_unit[12:0] \dec_SPR_function_unit - end - sync always - update \SPR__fn_unit $0\SPR__fn_unit[12:0] - end - connect \$10 $and$libresoc.v:122231$4679_Y - connect \$12 $not$libresoc.v:122232$4680_Y - connect \$14 $and$libresoc.v:122233$4681_Y - connect \$16 $eq$libresoc.v:122234$4682_Y - connect \$18 $eq$libresoc.v:122235$4683_Y - connect \$20 $or$libresoc.v:122236$4684_Y - connect \$22 $eq$libresoc.v:122237$4685_Y - connect \$24 $eq$libresoc.v:122238$4686_Y - connect \$26 $or$libresoc.v:122239$4687_Y - connect \$28 $eq$libresoc.v:122240$4688_Y - connect \$2 $eq$libresoc.v:122241$4689_Y - connect \$30 $or$libresoc.v:122242$4690_Y - connect \$32 $eq$libresoc.v:122243$4691_Y - connect \$34 $or$libresoc.v:122244$4692_Y - connect \$36 $eq$libresoc.v:122245$4693_Y - connect \$38 $and$libresoc.v:122246$4694_Y - connect \$40 $and$libresoc.v:122247$4695_Y - connect \$42 $eq$libresoc.v:122248$4696_Y - connect \$44 $and$libresoc.v:122249$4697_Y - connect \$46 $not$libresoc.v:122250$4698_Y - connect \$48 $and$libresoc.v:122251$4699_Y - connect \$4 $and$libresoc.v:122252$4700_Y - connect \$6 $and$libresoc.v:122253$4701_Y - connect \$8 $eq$libresoc.v:122254$4702_Y + assign $1\SPR__fn_unit[13:0] 14'00000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\SPR__fn_unit[13:0] \dec_SPR_function_unit + end + sync always + update \SPR__fn_unit $0\SPR__fn_unit[13:0] + end + connect \$10 $and$libresoc.v:123901$4712_Y + connect \$12 $not$libresoc.v:123902$4713_Y + connect \$14 $and$libresoc.v:123903$4714_Y + connect \$16 $eq$libresoc.v:123904$4715_Y + connect \$18 $eq$libresoc.v:123905$4716_Y + connect \$20 $or$libresoc.v:123906$4717_Y + connect \$22 $eq$libresoc.v:123907$4718_Y + connect \$24 $eq$libresoc.v:123908$4719_Y + connect \$26 $or$libresoc.v:123909$4720_Y + connect \$28 $eq$libresoc.v:123910$4721_Y + connect \$2 $eq$libresoc.v:123911$4722_Y + connect \$30 $or$libresoc.v:123912$4723_Y + connect \$32 $eq$libresoc.v:123913$4724_Y + connect \$34 $or$libresoc.v:123914$4725_Y + connect \$36 $eq$libresoc.v:123915$4726_Y + connect \$38 $and$libresoc.v:123916$4727_Y + connect \$40 $and$libresoc.v:123917$4728_Y + connect \$42 $eq$libresoc.v:123918$4729_Y + connect \$44 $and$libresoc.v:123919$4730_Y + connect \$46 $not$libresoc.v:123920$4731_Y + connect \$48 $and$libresoc.v:123921$4732_Y + connect \$4 $and$libresoc.v:123922$4733_Y + connect \$6 $and$libresoc.v:123923$4734_Y + connect \$8 $eq$libresoc.v:123924$4735_Y connect \SPR__is_32bit \dec_SPR_is_32b connect \is_mmu_spr \$34 connect \is_spr_mv \$20 @@ -191695,132 +193923,148 @@ module \dec_SPR connect \insn_in \dec_opcode_in connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:122318.1-122832.10" +attribute \src "libresoc.v:123988.1-124517.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a - attribute \src "libresoc.v:122760.3-122795.6" + attribute \src "libresoc.v:124445.3-124480.6" wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:122760.3-122795.6" + attribute \src "libresoc.v:124445.3-124480.6" wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:122319.7-122319.20" + attribute \src "libresoc.v:123989.7-123989.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122728.3-122743.6" + attribute \src "libresoc.v:124413.3-124428.6" wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:122744.3-122759.6" + attribute \src "libresoc.v:124429.3-124444.6" wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:122796.3-122806.6" + attribute \src "libresoc.v:124481.3-124491.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:122818.3-122829.6" + attribute \src "libresoc.v:124503.3-124514.6" wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:122818.3-122829.6" + attribute \src "libresoc.v:124503.3-124514.6" wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:122807.3-122817.6" + attribute \src "libresoc.v:124492.3-124502.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:122760.3-122795.6" + attribute \src "libresoc.v:124445.3-124480.6" wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:122760.3-122795.6" + attribute \src "libresoc.v:124445.3-124480.6" wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:122728.3-122743.6" + attribute \src "libresoc.v:124413.3-124428.6" wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:122744.3-122759.6" + attribute \src "libresoc.v:124429.3-124444.6" wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:122796.3-122806.6" + attribute \src "libresoc.v:124481.3-124491.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:122818.3-122829.6" + attribute \src "libresoc.v:124503.3-124514.6" wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:122818.3-122829.6" + attribute \src "libresoc.v:124503.3-124514.6" wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:122807.3-122817.6" + attribute \src "libresoc.v:124492.3-124502.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:122760.3-122795.6" + attribute \src "libresoc.v:124445.3-124480.6" wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:122760.3-122795.6" + attribute \src "libresoc.v:124445.3-124480.6" wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:122728.3-122743.6" + attribute \src "libresoc.v:124413.3-124428.6" wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:122744.3-122759.6" + attribute \src "libresoc.v:124429.3-124444.6" wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:122760.3-122795.6" + attribute \src "libresoc.v:124445.3-124480.6" wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:122760.3-122795.6" + attribute \src "libresoc.v:124445.3-124480.6" wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:122712.18-122712.110" - wire $and$libresoc.v:122712$4712_Y - attribute \src "libresoc.v:122717.18-122717.113" - wire $and$libresoc.v:122717$4717_Y - attribute \src "libresoc.v:122720.17-122720.107" - wire $and$libresoc.v:122720$4720_Y - attribute \src "libresoc.v:122707.18-122707.112" - wire $eq$libresoc.v:122707$4707_Y - attribute \src "libresoc.v:122708.18-122708.112" - wire $eq$libresoc.v:122708$4708_Y - attribute \src "libresoc.v:122709.18-122709.112" - wire $eq$libresoc.v:122709$4709_Y - attribute \src "libresoc.v:122711.17-122711.111" - wire $eq$libresoc.v:122711$4711_Y - attribute \src "libresoc.v:122714.18-122714.112" - wire $eq$libresoc.v:122714$4714_Y - attribute \src "libresoc.v:122718.17-122718.111" - wire $eq$libresoc.v:122718$4718_Y - attribute \src "libresoc.v:122710.18-122710.109" - wire $ne$libresoc.v:122710$4710_Y - attribute \src "libresoc.v:122719.17-122719.108" - wire $ne$libresoc.v:122719$4719_Y - attribute \src "libresoc.v:122715.18-122715.105" - wire $not$libresoc.v:122715$4715_Y - attribute \src "libresoc.v:122716.18-122716.108" - wire $not$libresoc.v:122716$4716_Y - attribute \src "libresoc.v:122706.17-122706.107" - wire $or$libresoc.v:122706$4706_Y - attribute \src "libresoc.v:122713.18-122713.110" - wire $or$libresoc.v:122713$4713_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + attribute \src "libresoc.v:124388.18-124388.108" + wire $and$libresoc.v:124388$4740_Y + attribute \src "libresoc.v:124397.18-124397.110" + wire $and$libresoc.v:124397$4749_Y + attribute \src "libresoc.v:124402.18-124402.113" + wire $and$libresoc.v:124402$4754_Y + attribute \src "libresoc.v:124390.18-124390.112" + wire $eq$libresoc.v:124390$4742_Y + attribute \src "libresoc.v:124391.18-124391.112" + wire $eq$libresoc.v:124391$4743_Y + attribute \src "libresoc.v:124392.17-124392.111" + wire $eq$libresoc.v:124392$4744_Y + attribute \src "libresoc.v:124393.18-124393.112" + wire $eq$libresoc.v:124393$4745_Y + attribute \src "libresoc.v:124399.18-124399.112" + wire $eq$libresoc.v:124399$4751_Y + attribute \src "libresoc.v:124403.17-124403.111" + wire $eq$libresoc.v:124403$4755_Y + attribute \src "libresoc.v:124394.18-124394.109" + wire $ne$libresoc.v:124394$4746_Y + attribute \src "libresoc.v:124395.18-124395.111" + wire $ne$libresoc.v:124395$4747_Y + attribute \src "libresoc.v:124404.17-124404.108" + wire $ne$libresoc.v:124404$4756_Y + attribute \src "libresoc.v:124405.17-124405.110" + wire $ne$libresoc.v:124405$4757_Y + attribute \src "libresoc.v:124400.18-124400.105" + wire $not$libresoc.v:124400$4752_Y + attribute \src "libresoc.v:124401.18-124401.108" + wire $not$libresoc.v:124401$4753_Y + attribute \src "libresoc.v:124387.17-124387.107" + wire $or$libresoc.v:124387$4739_Y + attribute \src "libresoc.v:124389.18-124389.109" + wire $or$libresoc.v:124389$4741_Y + attribute \src "libresoc.v:124396.18-124396.110" + wire $or$libresoc.v:124396$4748_Y + attribute \src "libresoc.v:124398.18-124398.110" + wire $or$libresoc.v:124398$4750_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 11 \BO + wire width 5 input 12 \BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 10 \RA + wire width 5 input 11 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 9 \RS + wire width 5 input 10 \RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 input 1 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 10 input 12 \XL_XO + wire width 10 input 13 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 7 \fast_a + wire width 3 output 8 \fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 8 \fast_a_ok - attribute \src "libresoc.v:122319.7-122319.15" + wire output 9 \fast_a_ok + attribute \src "libresoc.v:123989.7-123989.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -191896,15 +194140,16 @@ module \dec_a attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 13 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108" + wire width 7 input 14 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" wire width 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 3 \reg_a + wire width 5 output 4 \reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + wire output 5 \reg_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" wire width 5 \rs attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -191913,8 +194158,8 @@ module \dec_a attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -192031,9 +194276,9 @@ module \dec_a attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 output 5 \spr_a + wire width 10 output 6 \spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 6 \spr_a_ok + wire output 7 \spr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -192158,41 +194403,43 @@ module \dec_a wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $and $and$libresoc.v:122712$4712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + wire input 2 \sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $and $and$libresoc.v:124388$4740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \$17 - connect \Y $and$libresoc.v:122712$4712_Y + connect \A \$3 + connect \B \$9 + connect \Y $and$libresoc.v:124388$4740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" - cell $and $and$libresoc.v:122717$4717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $and $and$libresoc.v:124397$4749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B \$27 - connect \Y $and$libresoc.v:122717$4717_Y + connect \A \$19 + connect \B \$25 + connect \Y $and$libresoc.v:124397$4749_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $and $and$libresoc.v:122720$4720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + cell $and $and$libresoc.v:124402$4754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \$5 - connect \Y $and$libresoc.v:122720$4720_Y + connect \A \XL_XO [9] + connect \B \$35 + connect \Y $and$libresoc.v:124402$4754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" - cell $eq $eq$libresoc.v:122707$4707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $eq $eq$libresoc.v:124390$4742 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192200,10 +194447,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:122707$4707_Y + connect \Y $eq$libresoc.v:124390$4742_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - cell $eq $eq$libresoc.v:122708$4708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" + cell $eq $eq$libresoc.v:124391$4743 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192211,32 +194458,32 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:122708$4708_Y + connect \Y $eq$libresoc.v:124391$4743_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - cell $eq $eq$libresoc.v:122709$4709 + cell $eq $eq$libresoc.v:124392$4744 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:122709$4709_Y + connect \B 3'001 + connect \Y $eq$libresoc.v:124392$4744_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - cell $eq $eq$libresoc.v:122711$4711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $eq $eq$libresoc.v:124393$4745 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in - connect \B 3'001 - connect \Y $eq$libresoc.v:122711$4711_Y + connect \B 3'010 + connect \Y $eq$libresoc.v:124393$4745_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" - cell $eq $eq$libresoc.v:122714$4714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $eq $eq$libresoc.v:124399$4751 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192244,10 +194491,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:122714$4714_Y + connect \Y $eq$libresoc.v:124399$4751_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - cell $eq $eq$libresoc.v:122718$4718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $eq $eq$libresoc.v:124403$4755 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192255,10 +194502,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:122718$4718_Y + connect \Y $eq$libresoc.v:124403$4755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $ne $ne$libresoc.v:122710$4710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $ne $ne$libresoc.v:124394$4746 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192266,10 +194513,21 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:122710$4710_Y + connect \Y $ne$libresoc.v:124394$4746_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $ne $ne$libresoc.v:122719$4719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $ne $ne$libresoc.v:124395$4747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $ne$libresoc.v:124395$4747_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $ne $ne$libresoc.v:124404$4756 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192277,48 +194535,81 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:122719$4719_Y + connect \Y $ne$libresoc.v:124404$4756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" - cell $not $not$libresoc.v:122715$4715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $ne $ne$libresoc.v:124405$4757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $ne$libresoc.v:124405$4757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + cell $not $not$libresoc.v:124400$4752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:122715$4715_Y + connect \Y $not$libresoc.v:124400$4752_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" - cell $not $not$libresoc.v:122716$4716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + cell $not $not$libresoc.v:124401$4753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $not$libresoc.v:122716$4716_Y + connect \Y $not$libresoc.v:124401$4753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $or $or$libresoc.v:122706$4706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $or $or$libresoc.v:124387$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1 + connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:122706$4706_Y + connect \Y $or$libresoc.v:124387$4739_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $or $or$libresoc.v:122713$4713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $or $or$libresoc.v:124389$4741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$13 - connect \B \$19 - connect \Y $or$libresoc.v:122713$4713_Y + connect \A \$1 + connect \B \$11 + connect \Y $or$libresoc.v:124389$4741_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $or $or$libresoc.v:124396$4748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \$23 + connect \Y $or$libresoc.v:124396$4748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $or $or$libresoc.v:124398$4750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \$27 + connect \Y $or$libresoc.v:124398$4750_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122721.10-122727.4" + attribute \src "libresoc.v:124406.10-124412.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -192326,28 +194617,28 @@ module \dec_a connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:122319.7-122319.20" - process $proc$libresoc.v:122319$4727 + attribute \src "libresoc.v:123989.7-123989.20" + process $proc$libresoc.v:123989$4764 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122728.3-122743.6" - process $proc$libresoc.v:122728$4721 + attribute \src "libresoc.v:124413.3-124428.6" + process $proc$libresoc.v:124413$4758 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:122729.5-122729.29" + attribute \src "libresoc.v:124414.5-124414.29" switch \initial - attribute \src "libresoc.v:122729.9-122729.17" + attribute \src "libresoc.v:124414.9-124414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192355,8 +194646,8 @@ module \dec_a case assign $1\reg_a[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" - switch \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192367,20 +194658,20 @@ module \dec_a sync always update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:122744.3-122759.6" - process $proc$libresoc.v:122744$4722 + attribute \src "libresoc.v:124429.3-124444.6" + process $proc$libresoc.v:124429$4759 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:122745.5-122745.29" + attribute \src "libresoc.v:124430.5-124430.29" switch \initial - attribute \src "libresoc.v:122745.9-122745.17" + attribute \src "libresoc.v:124430.9-124430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192388,8 +194679,8 @@ module \dec_a case assign $1\reg_a_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" - switch \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192400,21 +194691,21 @@ module \dec_a sync always update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:122760.3-122795.6" - process $proc$libresoc.v:122760$4723 + attribute \src "libresoc.v:124445.3-124480.6" + process $proc$libresoc.v:124445$4760 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:122761.5-122761.29" + attribute \src "libresoc.v:124446.5-124446.29" switch \initial - attribute \src "libresoc.v:122761.9-122761.17" + attribute \src "libresoc.v:124446.9-124446.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:125" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 @@ -192422,8 +194713,8 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $2\fast_a[2:0] assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" - switch \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192440,8 +194731,8 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $3\fast_a[2:0] assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" - switch \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192465,18 +194756,18 @@ module \dec_a update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:122796.3-122806.6" - process $proc$libresoc.v:122796$4724 + attribute \src "libresoc.v:124481.3-124491.6" + process $proc$libresoc.v:124481$4761 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:122797.5-122797.29" + attribute \src "libresoc.v:124482.5-124482.29" switch \initial - attribute \src "libresoc.v:122797.9-122797.17" + attribute \src "libresoc.v:124482.9-124482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:125" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -192488,18 +194779,18 @@ module \dec_a sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:122807.3-122817.6" - process $proc$libresoc.v:122807$4725 + attribute \src "libresoc.v:124492.3-124502.6" + process $proc$libresoc.v:124492$4762 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:122808.5-122808.29" + attribute \src "libresoc.v:124493.5-124493.29" switch \initial - attribute \src "libresoc.v:122808.9-122808.17" + attribute \src "libresoc.v:124493.9-124493.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:125" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -192511,21 +194802,21 @@ module \dec_a sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:122818.3-122829.6" - process $proc$libresoc.v:122818$4726 + attribute \src "libresoc.v:124503.3-124514.6" + process $proc$libresoc.v:124503$4763 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:122819.5-122819.29" + attribute \src "libresoc.v:124504.5-124504.29" switch \initial - attribute \src "libresoc.v:122819.9-122819.17" + attribute \src "libresoc.v:124504.9-124504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:125" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -192540,54 +194831,66 @@ module \dec_a update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $or$libresoc.v:122706$4706_Y - connect \$11 $eq$libresoc.v:122707$4707_Y - connect \$13 $eq$libresoc.v:122708$4708_Y - connect \$15 $eq$libresoc.v:122709$4709_Y - connect \$17 $ne$libresoc.v:122710$4710_Y - connect \$1 $eq$libresoc.v:122711$4711_Y - connect \$19 $and$libresoc.v:122712$4712_Y - connect \$21 $or$libresoc.v:122713$4713_Y - connect \$23 $eq$libresoc.v:122714$4714_Y - connect \$25 $not$libresoc.v:122715$4715_Y - connect \$27 $not$libresoc.v:122716$4716_Y - connect \$29 $and$libresoc.v:122717$4717_Y - connect \$3 $eq$libresoc.v:122718$4718_Y - connect \$5 $ne$libresoc.v:122719$4719_Y - connect \$7 $and$libresoc.v:122720$4720_Y + connect \$9 $or$libresoc.v:124387$4739_Y + connect \$11 $and$libresoc.v:124388$4740_Y + connect \$13 $or$libresoc.v:124389$4741_Y + connect \$15 $eq$libresoc.v:124390$4742_Y + connect \$17 $eq$libresoc.v:124391$4743_Y + connect \$1 $eq$libresoc.v:124392$4744_Y + connect \$19 $eq$libresoc.v:124393$4745_Y + connect \$21 $ne$libresoc.v:124394$4746_Y + connect \$23 $ne$libresoc.v:124395$4747_Y + connect \$25 $or$libresoc.v:124396$4748_Y + connect \$27 $and$libresoc.v:124397$4749_Y + connect \$29 $or$libresoc.v:124398$4750_Y + connect \$31 $eq$libresoc.v:124399$4751_Y + connect \$33 $not$libresoc.v:124400$4752_Y + connect \$35 $not$libresoc.v:124401$4753_Y + connect \$37 $and$libresoc.v:124402$4754_Y + connect \$3 $eq$libresoc.v:124403$4755_Y + connect \$5 $ne$libresoc.v:124404$4756_Y + connect \$7 $ne$libresoc.v:124405$4757_Y connect \rs \RS connect \ra \RA end -attribute \src "libresoc.v:122836.1-122873.10" +attribute \src "libresoc.v:124521.1-124566.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai - attribute \src "libresoc.v:122862.3-122871.6" + attribute \src "libresoc.v:124555.3-124564.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:122837.7-122837.20" + attribute \src "libresoc.v:124522.7-124522.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122862.3-122871.6" + attribute \src "libresoc.v:124555.3-124564.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:122861.17-122861.107" - wire $and$libresoc.v:122861$4730_Y - attribute \src "libresoc.v:122859.17-122859.111" - wire $eq$libresoc.v:122859$4728_Y - attribute \src "libresoc.v:122860.17-122860.108" - wire $eq$libresoc.v:122860$4729_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "libresoc.v:124550.17-124550.107" + wire $and$libresoc.v:124550$4765_Y + attribute \src "libresoc.v:124553.17-124553.107" + wire $and$libresoc.v:124553$4768_Y + attribute \src "libresoc.v:124551.17-124551.111" + wire $eq$libresoc.v:124551$4766_Y + attribute \src "libresoc.v:124552.17-124552.108" + wire $eq$libresoc.v:124552$4767_Y + attribute \src "libresoc.v:124554.17-124554.110" + wire $eq$libresoc.v:124554$4769_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 2 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" - wire output 1 \immz_out - attribute \src "libresoc.v:122837.7-122837.15" + wire width 5 input 3 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire output 2 \immz_out + attribute \src "libresoc.v:124522.7-124522.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192595,10 +194898,23 @@ module \dec_ai attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $and $and$libresoc.v:122861$4730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire input 4 \sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:124550$4765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $and$libresoc.v:124550$4765_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $and $and$libresoc.v:124553$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192606,10 +194922,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:122861$4730_Y + connect \Y $and$libresoc.v:124553$4768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $eq $eq$libresoc.v:122859$4728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124551$4766 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192617,10 +194933,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:122859$4728_Y + connect \Y $eq$libresoc.v:124551$4766_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $eq $eq$libresoc.v:122860$4729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124552$4767 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192628,29 +194944,40 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:122860$4729_Y + connect \Y $eq$libresoc.v:124552$4767_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:124554$4769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $eq$libresoc.v:124554$4769_Y end - attribute \src "libresoc.v:122837.7-122837.20" - process $proc$libresoc.v:122837$4732 + attribute \src "libresoc.v:124522.7-124522.20" + process $proc$libresoc.v:124522$4771 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122862.3-122871.6" - process $proc$libresoc.v:122862$4731 + attribute \src "libresoc.v:124555.3-124564.6" + process $proc$libresoc.v:124555$4770 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:122863.5-122863.29" + attribute \src "libresoc.v:124556.5-124556.29" switch \initial - attribute \src "libresoc.v:122863.9-122863.17" + attribute \src "libresoc.v:124556.9-124556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192661,41 +194988,51 @@ module \dec_ai sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:122859$4728_Y - connect \$3 $eq$libresoc.v:122860$4729_Y - connect \$5 $and$libresoc.v:122861$4730_Y + connect \$9 $and$libresoc.v:124550$4765_Y + connect \$1 $eq$libresoc.v:124551$4766_Y + connect \$3 $eq$libresoc.v:124552$4767_Y + connect \$5 $and$libresoc.v:124553$4768_Y + connect \$7 $eq$libresoc.v:124554$4769_Y connect \ra \ALU_RA end -attribute \src "libresoc.v:122877.1-122914.10" +attribute \src "libresoc.v:124570.1-124615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" module \dec_ai$148 - attribute \src "libresoc.v:122903.3-122912.6" + attribute \src "libresoc.v:124604.3-124613.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:122878.7-122878.20" + attribute \src "libresoc.v:124571.7-124571.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122903.3-122912.6" + attribute \src "libresoc.v:124604.3-124613.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:122902.17-122902.107" - wire $and$libresoc.v:122902$4735_Y - attribute \src "libresoc.v:122900.17-122900.111" - wire $eq$libresoc.v:122900$4733_Y - attribute \src "libresoc.v:122901.17-122901.108" - wire $eq$libresoc.v:122901$4734_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "libresoc.v:124599.17-124599.107" + wire $and$libresoc.v:124599$4772_Y + attribute \src "libresoc.v:124602.17-124602.107" + wire $and$libresoc.v:124602$4775_Y + attribute \src "libresoc.v:124600.17-124600.111" + wire $eq$libresoc.v:124600$4773_Y + attribute \src "libresoc.v:124601.17-124601.108" + wire $eq$libresoc.v:124601$4774_Y + attribute \src "libresoc.v:124603.17-124603.110" + wire $eq$libresoc.v:124603$4776_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 2 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" - wire output 1 \immz_out - attribute \src "libresoc.v:122878.7-122878.15" + wire width 5 input 3 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire output 2 \immz_out + attribute \src "libresoc.v:124571.7-124571.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192703,10 +195040,23 @@ module \dec_ai$148 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $and $and$libresoc.v:122902$4735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire input 4 \sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:124599$4772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $and$libresoc.v:124599$4772_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $and $and$libresoc.v:124602$4775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192714,10 +195064,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:122902$4735_Y + connect \Y $and$libresoc.v:124602$4775_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $eq $eq$libresoc.v:122900$4733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124600$4773 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192725,10 +195075,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:122900$4733_Y + connect \Y $eq$libresoc.v:124600$4773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $eq $eq$libresoc.v:122901$4734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124601$4774 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192736,29 +195086,40 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:122901$4734_Y + connect \Y $eq$libresoc.v:124601$4774_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:124603$4776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $eq$libresoc.v:124603$4776_Y end - attribute \src "libresoc.v:122878.7-122878.20" - process $proc$libresoc.v:122878$4737 + attribute \src "libresoc.v:124571.7-124571.20" + process $proc$libresoc.v:124571$4778 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122903.3-122912.6" - process $proc$libresoc.v:122903$4736 + attribute \src "libresoc.v:124604.3-124613.6" + process $proc$libresoc.v:124604$4777 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:122904.5-122904.29" + attribute \src "libresoc.v:124605.5-124605.29" switch \initial - attribute \src "libresoc.v:122904.9-122904.17" + attribute \src "libresoc.v:124605.9-124605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192769,41 +195130,51 @@ module \dec_ai$148 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:122900$4733_Y - connect \$3 $eq$libresoc.v:122901$4734_Y - connect \$5 $and$libresoc.v:122902$4735_Y + connect \$9 $and$libresoc.v:124599$4772_Y + connect \$1 $eq$libresoc.v:124600$4773_Y + connect \$3 $eq$libresoc.v:124601$4774_Y + connect \$5 $and$libresoc.v:124602$4775_Y + connect \$7 $eq$libresoc.v:124603$4776_Y connect \ra \LOGICAL_RA end -attribute \src "libresoc.v:122918.1-122955.10" +attribute \src "libresoc.v:124619.1-124664.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" module \dec_ai$156 - attribute \src "libresoc.v:122944.3-122953.6" + attribute \src "libresoc.v:124653.3-124662.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:122919.7-122919.20" + attribute \src "libresoc.v:124620.7-124620.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122944.3-122953.6" + attribute \src "libresoc.v:124653.3-124662.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:122943.17-122943.107" - wire $and$libresoc.v:122943$4740_Y - attribute \src "libresoc.v:122941.17-122941.111" - wire $eq$libresoc.v:122941$4738_Y - attribute \src "libresoc.v:122942.17-122942.108" - wire $eq$libresoc.v:122942$4739_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "libresoc.v:124648.17-124648.107" + wire $and$libresoc.v:124648$4779_Y + attribute \src "libresoc.v:124651.17-124651.107" + wire $and$libresoc.v:124651$4782_Y + attribute \src "libresoc.v:124649.17-124649.111" + wire $eq$libresoc.v:124649$4780_Y + attribute \src "libresoc.v:124650.17-124650.108" + wire $eq$libresoc.v:124650$4781_Y + attribute \src "libresoc.v:124652.17-124652.110" + wire $eq$libresoc.v:124652$4783_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 2 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" - wire output 1 \immz_out - attribute \src "libresoc.v:122919.7-122919.15" + wire width 5 input 3 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire output 2 \immz_out + attribute \src "libresoc.v:124620.7-124620.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192811,10 +195182,23 @@ module \dec_ai$156 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $and $and$libresoc.v:122943$4740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire input 4 \sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:124648$4779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $and$libresoc.v:124648$4779_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $and $and$libresoc.v:124651$4782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192822,10 +195206,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:122943$4740_Y + connect \Y $and$libresoc.v:124651$4782_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $eq $eq$libresoc.v:122941$4738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124649$4780 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192833,10 +195217,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:122941$4738_Y + connect \Y $eq$libresoc.v:124649$4780_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $eq $eq$libresoc.v:122942$4739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124650$4781 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192844,29 +195228,40 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:122942$4739_Y + connect \Y $eq$libresoc.v:124650$4781_Y end - attribute \src "libresoc.v:122919.7-122919.20" - process $proc$libresoc.v:122919$4742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:124652$4783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $eq$libresoc.v:124652$4783_Y + end + attribute \src "libresoc.v:124620.7-124620.20" + process $proc$libresoc.v:124620$4785 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122944.3-122953.6" - process $proc$libresoc.v:122944$4741 + attribute \src "libresoc.v:124653.3-124662.6" + process $proc$libresoc.v:124653$4784 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:122945.5-122945.29" + attribute \src "libresoc.v:124654.5-124654.29" switch \initial - attribute \src "libresoc.v:122945.9-122945.17" + attribute \src "libresoc.v:124654.9-124654.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192877,41 +195272,51 @@ module \dec_ai$156 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:122941$4738_Y - connect \$3 $eq$libresoc.v:122942$4739_Y - connect \$5 $and$libresoc.v:122943$4740_Y + connect \$9 $and$libresoc.v:124648$4779_Y + connect \$1 $eq$libresoc.v:124649$4780_Y + connect \$3 $eq$libresoc.v:124650$4781_Y + connect \$5 $and$libresoc.v:124651$4782_Y + connect \$7 $eq$libresoc.v:124652$4783_Y connect \ra \DIV_RA end -attribute \src "libresoc.v:122959.1-122996.10" +attribute \src "libresoc.v:124668.1-124713.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" module \dec_ai$169 - attribute \src "libresoc.v:122985.3-122994.6" + attribute \src "libresoc.v:124702.3-124711.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:122960.7-122960.20" + attribute \src "libresoc.v:124669.7-124669.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122985.3-122994.6" + attribute \src "libresoc.v:124702.3-124711.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:122984.17-122984.107" - wire $and$libresoc.v:122984$4745_Y - attribute \src "libresoc.v:122982.17-122982.111" - wire $eq$libresoc.v:122982$4743_Y - attribute \src "libresoc.v:122983.17-122983.108" - wire $eq$libresoc.v:122983$4744_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "libresoc.v:124697.17-124697.107" + wire $and$libresoc.v:124697$4786_Y + attribute \src "libresoc.v:124700.17-124700.107" + wire $and$libresoc.v:124700$4789_Y + attribute \src "libresoc.v:124698.17-124698.111" + wire $eq$libresoc.v:124698$4787_Y + attribute \src "libresoc.v:124699.17-124699.108" + wire $eq$libresoc.v:124699$4788_Y + attribute \src "libresoc.v:124701.17-124701.110" + wire $eq$libresoc.v:124701$4790_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 2 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" - wire output 1 \immz_out - attribute \src "libresoc.v:122960.7-122960.15" + wire width 5 input 3 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + wire output 2 \immz_out + attribute \src "libresoc.v:124669.7-124669.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192919,10 +195324,23 @@ module \dec_ai$169 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $and $and$libresoc.v:122984$4745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + wire input 4 \sv_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:124697$4786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $and$libresoc.v:124697$4786_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $and $and$libresoc.v:124700$4789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192930,10 +195348,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:122984$4745_Y + connect \Y $and$libresoc.v:124700$4789_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $eq $eq$libresoc.v:122982$4743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124698$4787 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192941,10 +195359,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:122982$4743_Y + connect \Y $eq$libresoc.v:124698$4787_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - cell $eq $eq$libresoc.v:122983$4744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + cell $eq $eq$libresoc.v:124699$4788 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192952,29 +195370,40 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:122983$4744_Y + connect \Y $eq$libresoc.v:124699$4788_Y end - attribute \src "libresoc.v:122960.7-122960.20" - process $proc$libresoc.v:122960$4747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:124701$4790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sv_nz + connect \B 1'0 + connect \Y $eq$libresoc.v:124701$4790_Y + end + attribute \src "libresoc.v:124669.7-124669.20" + process $proc$libresoc.v:124669$4792 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122985.3-122994.6" - process $proc$libresoc.v:122985$4746 + attribute \src "libresoc.v:124702.3-124711.6" + process $proc$libresoc.v:124702$4791 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:122986.5-122986.29" + attribute \src "libresoc.v:124703.5-124703.29" switch \initial - attribute \src "libresoc.v:122986.9-122986.17" + attribute \src "libresoc.v:124703.9-124703.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -192985,65 +195414,67 @@ module \dec_ai$169 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:122982$4743_Y - connect \$3 $eq$libresoc.v:122983$4744_Y - connect \$5 $and$libresoc.v:122984$4745_Y + connect \$9 $and$libresoc.v:124697$4786_Y + connect \$1 $eq$libresoc.v:124698$4787_Y + connect \$3 $eq$libresoc.v:124699$4788_Y + connect \$5 $and$libresoc.v:124700$4789_Y + connect \$7 $eq$libresoc.v:124701$4790_Y connect \ra \LDST_RA end -attribute \src "libresoc.v:123000.1-123197.10" +attribute \src "libresoc.v:124717.1-124915.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b - attribute \src "libresoc.v:123161.3-123178.6" + attribute \src "libresoc.v:124879.3-124896.6" wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:123179.3-123196.6" + attribute \src "libresoc.v:124897.3-124914.6" wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:123001.7-123001.20" + attribute \src "libresoc.v:124718.7-124718.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123131.3-123145.6" + attribute \src "libresoc.v:124849.3-124863.6" wire width 7 $0\reg_b[6:0] - attribute \src "libresoc.v:123146.3-123160.6" + attribute \src "libresoc.v:124864.3-124878.6" wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:123161.3-123178.6" + attribute \src "libresoc.v:124879.3-124896.6" wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:123179.3-123196.6" + attribute \src "libresoc.v:124897.3-124914.6" wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:123131.3-123145.6" + attribute \src "libresoc.v:124849.3-124863.6" wire width 7 $1\reg_b[6:0] - attribute \src "libresoc.v:123146.3-123160.6" + attribute \src "libresoc.v:124864.3-124878.6" wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:123161.3-123178.6" + attribute \src "libresoc.v:124879.3-124896.6" wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:123179.3-123196.6" + attribute \src "libresoc.v:124897.3-124914.6" wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:123125.17-123125.117" - wire $eq$libresoc.v:123125$4748_Y - attribute \src "libresoc.v:123129.17-123129.117" - wire $eq$libresoc.v:123129$4754_Y - attribute \src "libresoc.v:123127.17-123127.100" - wire width 7 $extend$libresoc.v:123127$4750_Y - attribute \src "libresoc.v:123128.17-123128.100" - wire width 7 $extend$libresoc.v:123128$4752_Y - attribute \src "libresoc.v:123126.18-123126.108" - wire $not$libresoc.v:123126$4749_Y - attribute \src "libresoc.v:123130.17-123130.107" - wire $not$libresoc.v:123130$4755_Y - attribute \src "libresoc.v:123127.17-123127.100" - wire width 7 $pos$libresoc.v:123127$4751_Y - attribute \src "libresoc.v:123128.17-123128.100" - wire width 7 $pos$libresoc.v:123128$4753_Y + attribute \src "libresoc.v:124843.17-124843.117" + wire $eq$libresoc.v:124843$4793_Y + attribute \src "libresoc.v:124847.17-124847.117" + wire $eq$libresoc.v:124847$4799_Y + attribute \src "libresoc.v:124845.17-124845.100" + wire width 7 $extend$libresoc.v:124845$4795_Y + attribute \src "libresoc.v:124846.17-124846.100" + wire width 7 $extend$libresoc.v:124846$4797_Y + attribute \src "libresoc.v:124844.18-124844.108" + wire $not$libresoc.v:124844$4794_Y + attribute \src "libresoc.v:124848.17-124848.107" + wire $not$libresoc.v:124848$4800_Y + attribute \src "libresoc.v:124845.17-124845.100" + wire width 7 $pos$libresoc.v:124845$4796_Y + attribute \src "libresoc.v:124846.17-124846.100" + wire width 7 $pos$libresoc.v:124846$4798_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 7 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 7 \RB @@ -193055,7 +195486,7 @@ module \dec_b wire width 3 output 4 \fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_b_ok - attribute \src "libresoc.v:123001.7-123001.15" + attribute \src "libresoc.v:124718.7-124718.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -193131,6 +195562,7 @@ module \dec_b attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 9 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -193152,10 +195584,10 @@ module \dec_b attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" - cell $eq $eq$libresoc.v:123125$4748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + cell $eq $eq$libresoc.v:124843$4793 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193163,10 +195595,10 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:123125$4748_Y + connect \Y $eq$libresoc.v:124843$4793_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" - cell $eq $eq$libresoc.v:123129$4754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + cell $eq $eq$libresoc.v:124847$4799 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193174,76 +195606,76 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:123129$4754_Y + connect \Y $eq$libresoc.v:124847$4799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123127$4750 + cell $pos $extend$libresoc.v:124845$4795 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RB - connect \Y $extend$libresoc.v:123127$4750_Y + connect \Y $extend$libresoc.v:124845$4795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123128$4752 + cell $pos $extend$libresoc.v:124846$4797 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RS - connect \Y $extend$libresoc.v:123128$4752_Y + connect \Y $extend$libresoc.v:124846$4797_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - cell $not $not$libresoc.v:123126$4749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + cell $not $not$libresoc.v:124844$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:123126$4749_Y + connect \Y $not$libresoc.v:124844$4794_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - cell $not $not$libresoc.v:123130$4755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + cell $not $not$libresoc.v:124848$4800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:123130$4755_Y + connect \Y $not$libresoc.v:124848$4800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123127$4751 + cell $pos $pos$libresoc.v:124845$4796 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:123127$4750_Y - connect \Y $pos$libresoc.v:123127$4751_Y + connect \A $extend$libresoc.v:124845$4795_Y + connect \Y $pos$libresoc.v:124845$4796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123128$4753 + cell $pos $pos$libresoc.v:124846$4798 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:123128$4752_Y - connect \Y $pos$libresoc.v:123128$4753_Y + connect \A $extend$libresoc.v:124846$4797_Y + connect \Y $pos$libresoc.v:124846$4798_Y end - attribute \src "libresoc.v:123001.7-123001.20" - process $proc$libresoc.v:123001$4760 + attribute \src "libresoc.v:124718.7-124718.20" + process $proc$libresoc.v:124718$4805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123131.3-123145.6" - process $proc$libresoc.v:123131$4756 + attribute \src "libresoc.v:124849.3-124863.6" + process $proc$libresoc.v:124849$4801 assign { } { } assign { } { } assign $0\reg_b[6:0] $1\reg_b[6:0] - attribute \src "libresoc.v:123132.5-123132.29" + attribute \src "libresoc.v:124850.5-124850.29" switch \initial - attribute \src "libresoc.v:123132.9-123132.17" + attribute \src "libresoc.v:124850.9-124850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -193259,18 +195691,18 @@ module \dec_b sync always update \reg_b $0\reg_b[6:0] end - attribute \src "libresoc.v:123146.3-123160.6" - process $proc$libresoc.v:123146$4757 + attribute \src "libresoc.v:124864.3-124878.6" + process $proc$libresoc.v:124864$4802 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:123147.5-123147.29" + attribute \src "libresoc.v:124865.5-124865.29" switch \initial - attribute \src "libresoc.v:123147.9-123147.17" + attribute \src "libresoc.v:124865.9-124865.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -193286,24 +195718,24 @@ module \dec_b sync always update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:123161.3-123178.6" - process $proc$libresoc.v:123161$4758 + attribute \src "libresoc.v:124879.3-124896.6" + process $proc$libresoc.v:124879$4803 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:123162.5-123162.29" + attribute \src "libresoc.v:124880.5-124880.29" switch \initial - attribute \src "libresoc.v:123162.9-123162.17" + attribute \src "libresoc.v:124880.9-124880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" switch { \XL_XO [5] \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193322,24 +195754,24 @@ module \dec_b sync always update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:123179.3-123196.6" - process $proc$libresoc.v:123179$4759 + attribute \src "libresoc.v:124897.3-124914.6" + process $proc$libresoc.v:124897$4804 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:123180.5-123180.29" + attribute \src "libresoc.v:124898.5-124898.29" switch \initial - attribute \src "libresoc.v:123180.9-123180.17" + attribute \src "libresoc.v:124898.9-124898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" switch { \XL_XO [5] \$11 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193358,103 +195790,103 @@ module \dec_b sync always update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$9 $eq$libresoc.v:123125$4748_Y - connect \$11 $not$libresoc.v:123126$4749_Y - connect \$1 $pos$libresoc.v:123127$4751_Y - connect \$3 $pos$libresoc.v:123128$4753_Y - connect \$5 $eq$libresoc.v:123129$4754_Y - connect \$7 $not$libresoc.v:123130$4755_Y + connect \$9 $eq$libresoc.v:124843$4793_Y + connect \$11 $not$libresoc.v:124844$4794_Y + connect \$1 $pos$libresoc.v:124845$4796_Y + connect \$3 $pos$libresoc.v:124846$4798_Y + connect \$5 $eq$libresoc.v:124847$4799_Y + connect \$7 $not$libresoc.v:124848$4800_Y end -attribute \src "libresoc.v:123201.1-123454.10" +attribute \src "libresoc.v:124919.1-125172.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi - attribute \src "libresoc.v:123428.3-123438.6" + attribute \src "libresoc.v:125146.3-125156.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:123439.3-123449.6" + attribute \src "libresoc.v:125157.3-125167.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:123290.3-123336.6" + attribute \src "libresoc.v:125008.3-125054.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:123337.3-123383.6" + attribute \src "libresoc.v:125055.3-125101.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:123202.7-123202.20" + attribute \src "libresoc.v:124920.7-124920.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123417.3-123427.6" + attribute \src "libresoc.v:125135.3-125145.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:123384.3-123394.6" + attribute \src "libresoc.v:125102.3-125112.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:123395.3-123405.6" + attribute \src "libresoc.v:125113.3-125123.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:123406.3-123416.6" + attribute \src "libresoc.v:125124.3-125134.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:123428.3-123438.6" + attribute \src "libresoc.v:125146.3-125156.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:123439.3-123449.6" + attribute \src "libresoc.v:125157.3-125167.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:123290.3-123336.6" + attribute \src "libresoc.v:125008.3-125054.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:123337.3-123383.6" + attribute \src "libresoc.v:125055.3-125101.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:123417.3-123427.6" + attribute \src "libresoc.v:125135.3-125145.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:123384.3-123394.6" + attribute \src "libresoc.v:125102.3-125112.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:123395.3-123405.6" + attribute \src "libresoc.v:125113.3-125123.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:123406.3-123416.6" + attribute \src "libresoc.v:125124.3-125134.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:123280.17-123280.104" - wire width 64 $extend$libresoc.v:123280$4761_Y - attribute \src "libresoc.v:123281.18-123281.107" - wire width 64 $extend$libresoc.v:123281$4763_Y - attribute \src "libresoc.v:123284.17-123284.104" - wire width 64 $extend$libresoc.v:123284$4767_Y - attribute \src "libresoc.v:123288.17-123288.102" - wire width 64 $extend$libresoc.v:123288$4772_Y - attribute \src "libresoc.v:123280.17-123280.104" - wire width 64 $pos$libresoc.v:123280$4762_Y - attribute \src "libresoc.v:123281.18-123281.107" - wire width 64 $pos$libresoc.v:123281$4764_Y - attribute \src "libresoc.v:123284.17-123284.104" - wire width 64 $pos$libresoc.v:123284$4768_Y - attribute \src "libresoc.v:123288.17-123288.102" - wire width 64 $pos$libresoc.v:123288$4773_Y - attribute \src "libresoc.v:123282.18-123282.114" - wire width 47 $sshl$libresoc.v:123282$4765_Y - attribute \src "libresoc.v:123283.18-123283.113" - wire width 27 $sshl$libresoc.v:123283$4766_Y - attribute \src "libresoc.v:123285.18-123285.113" - wire width 17 $sshl$libresoc.v:123285$4769_Y - attribute \src "libresoc.v:123286.18-123286.113" - wire width 17 $sshl$libresoc.v:123286$4770_Y - attribute \src "libresoc.v:123287.17-123287.109" - wire width 47 $sshl$libresoc.v:123287$4771_Y + attribute \src "libresoc.v:124998.17-124998.104" + wire width 64 $extend$libresoc.v:124998$4806_Y + attribute \src "libresoc.v:124999.18-124999.107" + wire width 64 $extend$libresoc.v:124999$4808_Y + attribute \src "libresoc.v:125002.17-125002.104" + wire width 64 $extend$libresoc.v:125002$4812_Y + attribute \src "libresoc.v:125006.17-125006.102" + wire width 64 $extend$libresoc.v:125006$4817_Y + attribute \src "libresoc.v:124998.17-124998.104" + wire width 64 $pos$libresoc.v:124998$4807_Y + attribute \src "libresoc.v:124999.18-124999.107" + wire width 64 $pos$libresoc.v:124999$4809_Y + attribute \src "libresoc.v:125002.17-125002.104" + wire width 64 $pos$libresoc.v:125002$4813_Y + attribute \src "libresoc.v:125006.17-125006.102" + wire width 64 $pos$libresoc.v:125006$4818_Y + attribute \src "libresoc.v:125000.18-125000.114" + wire width 47 $sshl$libresoc.v:125000$4810_Y + attribute \src "libresoc.v:125001.18-125001.113" + wire width 27 $sshl$libresoc.v:125001$4811_Y + attribute \src "libresoc.v:125003.18-125003.113" + wire width 17 $sshl$libresoc.v:125003$4814_Y + attribute \src "libresoc.v:125004.18-125004.113" + wire width 17 $sshl$libresoc.v:125004$4815_Y + attribute \src "libresoc.v:125005.17-125005.109" + wire width 47 $sshl$libresoc.v:125005$4816_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -193472,17 +195904,17 @@ module \dec_bi wire width 16 input 4 \ALU_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:123202.7-123202.15" + attribute \src "libresoc.v:124920.7-124920.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -193499,80 +195931,80 @@ module \dec_bi attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123280$4761 + cell $pos $extend$libresoc.v:124998$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh - connect \Y $extend$libresoc.v:123280$4761_Y + connect \Y $extend$libresoc.v:124998$4806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123281$4763 + cell $pos $extend$libresoc.v:124999$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:123281$4763_Y + connect \Y $extend$libresoc.v:124999$4808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123284$4767 + cell $pos $extend$libresoc.v:125002$4812 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI - connect \Y $extend$libresoc.v:123284$4767_Y + connect \Y $extend$libresoc.v:125002$4812_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $extend$libresoc.v:123288$4772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:125006$4817 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:123288$4772_Y + connect \Y $extend$libresoc.v:125006$4817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123280$4762 + cell $pos $pos$libresoc.v:124998$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123280$4761_Y - connect \Y $pos$libresoc.v:123280$4762_Y + connect \A $extend$libresoc.v:124998$4806_Y + connect \Y $pos$libresoc.v:124998$4807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123281$4764 + cell $pos $pos$libresoc.v:124999$4809 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123281$4763_Y - connect \Y $pos$libresoc.v:123281$4764_Y + connect \A $extend$libresoc.v:124999$4808_Y + connect \Y $pos$libresoc.v:124999$4809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123284$4768 + cell $pos $pos$libresoc.v:125002$4813 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123284$4767_Y - connect \Y $pos$libresoc.v:123284$4768_Y + connect \A $extend$libresoc.v:125002$4812_Y + connect \Y $pos$libresoc.v:125002$4813_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $pos$libresoc.v:123288$4773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:125006$4818 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123288$4772_Y - connect \Y $pos$libresoc.v:123288$4773_Y + connect \A $extend$libresoc.v:125006$4817_Y + connect \Y $pos$libresoc.v:125006$4818_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:123282$4765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:125000$4810 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -193580,10 +196012,10 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:123282$4765_Y + connect \Y $sshl$libresoc.v:125000$4810_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:123283$4766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:125001$4811 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -193591,10 +196023,10 @@ module \dec_bi parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:123283$4766_Y + connect \Y $sshl$libresoc.v:125001$4811_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:123285$4769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:125003$4814 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193602,10 +196034,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:123285$4769_Y + connect \Y $sshl$libresoc.v:125003$4814_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:123286$4770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:125004$4815 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193613,10 +196045,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:123286$4770_Y + connect \Y $sshl$libresoc.v:125004$4815_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $sshl $sshl$libresoc.v:123287$4771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125005$4816 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -193624,28 +196056,28 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:123287$4771_Y + connect \Y $sshl$libresoc.v:125005$4816_Y end - attribute \src "libresoc.v:123202.7-123202.20" - process $proc$libresoc.v:123202$4782 + attribute \src "libresoc.v:124920.7-124920.20" + process $proc$libresoc.v:124920$4827 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123290.3-123336.6" - process $proc$libresoc.v:123290$4774 + attribute \src "libresoc.v:125008.3-125054.6" + process $proc$libresoc.v:125008$4819 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:123291.5-123291.29" + attribute \src "libresoc.v:125009.5-125009.29" switch \initial - attribute \src "libresoc.v:123291.9-123291.17" + attribute \src "libresoc.v:125009.9-125009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -193693,18 +196125,18 @@ module \dec_bi sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:123337.3-123383.6" - process $proc$libresoc.v:123337$4775 + attribute \src "libresoc.v:125055.3-125101.6" + process $proc$libresoc.v:125055$4820 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:123338.5-123338.29" + attribute \src "libresoc.v:125056.5-125056.29" switch \initial - attribute \src "libresoc.v:123338.9-123338.17" + attribute \src "libresoc.v:125056.9-125056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -193752,18 +196184,18 @@ module \dec_bi sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:123384.3-123394.6" - process $proc$libresoc.v:123384$4776 + attribute \src "libresoc.v:125102.3-125112.6" + process $proc$libresoc.v:125102$4821 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:123385.5-123385.29" + attribute \src "libresoc.v:125103.5-125103.29" switch \initial - attribute \src "libresoc.v:123385.9-123385.17" + attribute \src "libresoc.v:125103.9-125103.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -193775,18 +196207,18 @@ module \dec_bi sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:123395.3-123405.6" - process $proc$libresoc.v:123395$4777 + attribute \src "libresoc.v:125113.3-125123.6" + process $proc$libresoc.v:125113$4822 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:123396.5-123396.29" + attribute \src "libresoc.v:125114.5-125114.29" switch \initial - attribute \src "libresoc.v:123396.9-123396.17" + attribute \src "libresoc.v:125114.9-125114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -193798,18 +196230,18 @@ module \dec_bi sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:123406.3-123416.6" - process $proc$libresoc.v:123406$4778 + attribute \src "libresoc.v:125124.3-125134.6" + process $proc$libresoc.v:125124$4823 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:123407.5-123407.29" + attribute \src "libresoc.v:125125.5-125125.29" switch \initial - attribute \src "libresoc.v:123407.9-123407.17" + attribute \src "libresoc.v:125125.9-125125.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -193821,18 +196253,18 @@ module \dec_bi sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:123417.3-123427.6" - process $proc$libresoc.v:123417$4779 + attribute \src "libresoc.v:125135.3-125145.6" + process $proc$libresoc.v:125135$4824 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:123418.5-123418.29" + attribute \src "libresoc.v:125136.5-125136.29" switch \initial - attribute \src "libresoc.v:123418.9-123418.17" + attribute \src "libresoc.v:125136.9-125136.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -193844,18 +196276,18 @@ module \dec_bi sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:123428.3-123438.6" - process $proc$libresoc.v:123428$4780 + attribute \src "libresoc.v:125146.3-125156.6" + process $proc$libresoc.v:125146$4825 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:123429.5-123429.29" + attribute \src "libresoc.v:125147.5-125147.29" switch \initial - attribute \src "libresoc.v:123429.9-123429.17" + attribute \src "libresoc.v:125147.9-125147.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -193867,18 +196299,18 @@ module \dec_bi sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:123439.3-123449.6" - process $proc$libresoc.v:123439$4781 + attribute \src "libresoc.v:125157.3-125167.6" + process $proc$libresoc.v:125157$4826 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:123440.5-123440.29" + attribute \src "libresoc.v:125158.5-125158.29" switch \initial - attribute \src "libresoc.v:123440.9-123440.17" + attribute \src "libresoc.v:125158.9-125158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -193890,111 +196322,111 @@ module \dec_bi sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:123280$4762_Y - connect \$11 $pos$libresoc.v:123281$4764_Y - connect \$14 $sshl$libresoc.v:123282$4765_Y - connect \$17 $sshl$libresoc.v:123283$4766_Y - connect \$1 $pos$libresoc.v:123284$4768_Y - connect \$20 $sshl$libresoc.v:123285$4769_Y - connect \$23 $sshl$libresoc.v:123286$4770_Y - connect \$4 $sshl$libresoc.v:123287$4771_Y - connect \$3 $pos$libresoc.v:123288$4773_Y + connect \$9 $pos$libresoc.v:124998$4807_Y + connect \$11 $pos$libresoc.v:124999$4809_Y + connect \$14 $sshl$libresoc.v:125000$4810_Y + connect \$17 $sshl$libresoc.v:125001$4811_Y + connect \$1 $pos$libresoc.v:125002$4813_Y + connect \$20 $sshl$libresoc.v:125003$4814_Y + connect \$23 $sshl$libresoc.v:125004$4815_Y + connect \$4 $sshl$libresoc.v:125005$4816_Y + connect \$3 $pos$libresoc.v:125006$4818_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:123458.1-123711.10" +attribute \src "libresoc.v:125176.1-125429.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" module \dec_bi$144 - attribute \src "libresoc.v:123685.3-123695.6" + attribute \src "libresoc.v:125403.3-125413.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:123696.3-123706.6" + attribute \src "libresoc.v:125414.3-125424.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:123547.3-123593.6" + attribute \src "libresoc.v:125265.3-125311.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:123594.3-123640.6" + attribute \src "libresoc.v:125312.3-125358.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:123459.7-123459.20" + attribute \src "libresoc.v:125177.7-125177.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123674.3-123684.6" + attribute \src "libresoc.v:125392.3-125402.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:123641.3-123651.6" + attribute \src "libresoc.v:125359.3-125369.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:123652.3-123662.6" + attribute \src "libresoc.v:125370.3-125380.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:123663.3-123673.6" + attribute \src "libresoc.v:125381.3-125391.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:123685.3-123695.6" + attribute \src "libresoc.v:125403.3-125413.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:123696.3-123706.6" + attribute \src "libresoc.v:125414.3-125424.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:123547.3-123593.6" + attribute \src "libresoc.v:125265.3-125311.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:123594.3-123640.6" + attribute \src "libresoc.v:125312.3-125358.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:123674.3-123684.6" + attribute \src "libresoc.v:125392.3-125402.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:123641.3-123651.6" + attribute \src "libresoc.v:125359.3-125369.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:123652.3-123662.6" + attribute \src "libresoc.v:125370.3-125380.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:123663.3-123673.6" + attribute \src "libresoc.v:125381.3-125391.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:123537.17-123537.107" - wire width 64 $extend$libresoc.v:123537$4783_Y - attribute \src "libresoc.v:123538.18-123538.110" - wire width 64 $extend$libresoc.v:123538$4785_Y - attribute \src "libresoc.v:123541.17-123541.107" - wire width 64 $extend$libresoc.v:123541$4789_Y - attribute \src "libresoc.v:123545.17-123545.102" - wire width 64 $extend$libresoc.v:123545$4794_Y - attribute \src "libresoc.v:123537.17-123537.107" - wire width 64 $pos$libresoc.v:123537$4784_Y - attribute \src "libresoc.v:123538.18-123538.110" - wire width 64 $pos$libresoc.v:123538$4786_Y - attribute \src "libresoc.v:123541.17-123541.107" - wire width 64 $pos$libresoc.v:123541$4790_Y - attribute \src "libresoc.v:123545.17-123545.102" - wire width 64 $pos$libresoc.v:123545$4795_Y - attribute \src "libresoc.v:123539.18-123539.117" - wire width 47 $sshl$libresoc.v:123539$4787_Y - attribute \src "libresoc.v:123540.18-123540.116" - wire width 27 $sshl$libresoc.v:123540$4788_Y - attribute \src "libresoc.v:123542.18-123542.116" - wire width 17 $sshl$libresoc.v:123542$4791_Y - attribute \src "libresoc.v:123543.18-123543.116" - wire width 17 $sshl$libresoc.v:123543$4792_Y - attribute \src "libresoc.v:123544.17-123544.109" - wire width 47 $sshl$libresoc.v:123544$4793_Y + attribute \src "libresoc.v:125255.17-125255.107" + wire width 64 $extend$libresoc.v:125255$4828_Y + attribute \src "libresoc.v:125256.18-125256.110" + wire width 64 $extend$libresoc.v:125256$4830_Y + attribute \src "libresoc.v:125259.17-125259.107" + wire width 64 $extend$libresoc.v:125259$4834_Y + attribute \src "libresoc.v:125263.17-125263.102" + wire width 64 $extend$libresoc.v:125263$4839_Y + attribute \src "libresoc.v:125255.17-125255.107" + wire width 64 $pos$libresoc.v:125255$4829_Y + attribute \src "libresoc.v:125256.18-125256.110" + wire width 64 $pos$libresoc.v:125256$4831_Y + attribute \src "libresoc.v:125259.17-125259.107" + wire width 64 $pos$libresoc.v:125259$4835_Y + attribute \src "libresoc.v:125263.17-125263.102" + wire width 64 $pos$libresoc.v:125263$4840_Y + attribute \src "libresoc.v:125257.18-125257.117" + wire width 47 $sshl$libresoc.v:125257$4832_Y + attribute \src "libresoc.v:125258.18-125258.116" + wire width 27 $sshl$libresoc.v:125258$4833_Y + attribute \src "libresoc.v:125260.18-125260.116" + wire width 17 $sshl$libresoc.v:125260$4836_Y + attribute \src "libresoc.v:125261.18-125261.116" + wire width 17 $sshl$libresoc.v:125261$4837_Y + attribute \src "libresoc.v:125262.17-125262.109" + wire width 47 $sshl$libresoc.v:125262$4838_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -194012,17 +196444,17 @@ module \dec_bi$144 wire width 16 input 4 \BRANCH_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:123459.7-123459.15" + attribute \src "libresoc.v:125177.7-125177.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -194039,80 +196471,80 @@ module \dec_bi$144 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123537$4783 + cell $pos $extend$libresoc.v:125255$4828 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh - connect \Y $extend$libresoc.v:123537$4783_Y + connect \Y $extend$libresoc.v:125255$4828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123538$4785 + cell $pos $extend$libresoc.v:125256$4830 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 - connect \Y $extend$libresoc.v:123538$4785_Y + connect \Y $extend$libresoc.v:125256$4830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123541$4789 + cell $pos $extend$libresoc.v:125259$4834 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI - connect \Y $extend$libresoc.v:123541$4789_Y + connect \Y $extend$libresoc.v:125259$4834_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $extend$libresoc.v:123545$4794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:125263$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:123545$4794_Y + connect \Y $extend$libresoc.v:125263$4839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123537$4784 + cell $pos $pos$libresoc.v:125255$4829 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123537$4783_Y - connect \Y $pos$libresoc.v:123537$4784_Y + connect \A $extend$libresoc.v:125255$4828_Y + connect \Y $pos$libresoc.v:125255$4829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123538$4786 + cell $pos $pos$libresoc.v:125256$4831 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123538$4785_Y - connect \Y $pos$libresoc.v:123538$4786_Y + connect \A $extend$libresoc.v:125256$4830_Y + connect \Y $pos$libresoc.v:125256$4831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123541$4790 + cell $pos $pos$libresoc.v:125259$4835 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123541$4789_Y - connect \Y $pos$libresoc.v:123541$4790_Y + connect \A $extend$libresoc.v:125259$4834_Y + connect \Y $pos$libresoc.v:125259$4835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $pos$libresoc.v:123545$4795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:125263$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123545$4794_Y - connect \Y $pos$libresoc.v:123545$4795_Y + connect \A $extend$libresoc.v:125263$4839_Y + connect \Y $pos$libresoc.v:125263$4840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:123539$4787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:125257$4832 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -194120,10 +196552,10 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:123539$4787_Y + connect \Y $sshl$libresoc.v:125257$4832_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:123540$4788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:125258$4833 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -194131,10 +196563,10 @@ module \dec_bi$144 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:123540$4788_Y + connect \Y $sshl$libresoc.v:125258$4833_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:123542$4791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:125260$4836 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194142,10 +196574,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:123542$4791_Y + connect \Y $sshl$libresoc.v:125260$4836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:123543$4792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:125261$4837 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194153,10 +196585,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:123543$4792_Y + connect \Y $sshl$libresoc.v:125261$4837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $sshl $sshl$libresoc.v:123544$4793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125262$4838 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -194164,28 +196596,28 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:123544$4793_Y + connect \Y $sshl$libresoc.v:125262$4838_Y end - attribute \src "libresoc.v:123459.7-123459.20" - process $proc$libresoc.v:123459$4804 + attribute \src "libresoc.v:125177.7-125177.20" + process $proc$libresoc.v:125177$4849 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123547.3-123593.6" - process $proc$libresoc.v:123547$4796 + attribute \src "libresoc.v:125265.3-125311.6" + process $proc$libresoc.v:125265$4841 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:123548.5-123548.29" + attribute \src "libresoc.v:125266.5-125266.29" switch \initial - attribute \src "libresoc.v:123548.9-123548.17" + attribute \src "libresoc.v:125266.9-125266.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -194233,18 +196665,18 @@ module \dec_bi$144 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:123594.3-123640.6" - process $proc$libresoc.v:123594$4797 + attribute \src "libresoc.v:125312.3-125358.6" + process $proc$libresoc.v:125312$4842 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:123595.5-123595.29" + attribute \src "libresoc.v:125313.5-125313.29" switch \initial - attribute \src "libresoc.v:123595.9-123595.17" + attribute \src "libresoc.v:125313.9-125313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -194292,18 +196724,18 @@ module \dec_bi$144 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:123641.3-123651.6" - process $proc$libresoc.v:123641$4798 + attribute \src "libresoc.v:125359.3-125369.6" + process $proc$libresoc.v:125359$4843 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:123642.5-123642.29" + attribute \src "libresoc.v:125360.5-125360.29" switch \initial - attribute \src "libresoc.v:123642.9-123642.17" + attribute \src "libresoc.v:125360.9-125360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -194315,18 +196747,18 @@ module \dec_bi$144 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:123652.3-123662.6" - process $proc$libresoc.v:123652$4799 + attribute \src "libresoc.v:125370.3-125380.6" + process $proc$libresoc.v:125370$4844 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:123653.5-123653.29" + attribute \src "libresoc.v:125371.5-125371.29" switch \initial - attribute \src "libresoc.v:123653.9-123653.17" + attribute \src "libresoc.v:125371.9-125371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -194338,18 +196770,18 @@ module \dec_bi$144 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:123663.3-123673.6" - process $proc$libresoc.v:123663$4800 + attribute \src "libresoc.v:125381.3-125391.6" + process $proc$libresoc.v:125381$4845 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:123664.5-123664.29" + attribute \src "libresoc.v:125382.5-125382.29" switch \initial - attribute \src "libresoc.v:123664.9-123664.17" + attribute \src "libresoc.v:125382.9-125382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -194361,18 +196793,18 @@ module \dec_bi$144 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:123674.3-123684.6" - process $proc$libresoc.v:123674$4801 + attribute \src "libresoc.v:125392.3-125402.6" + process $proc$libresoc.v:125392$4846 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:123675.5-123675.29" + attribute \src "libresoc.v:125393.5-125393.29" switch \initial - attribute \src "libresoc.v:123675.9-123675.17" + attribute \src "libresoc.v:125393.9-125393.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -194384,18 +196816,18 @@ module \dec_bi$144 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:123685.3-123695.6" - process $proc$libresoc.v:123685$4802 + attribute \src "libresoc.v:125403.3-125413.6" + process $proc$libresoc.v:125403$4847 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:123686.5-123686.29" + attribute \src "libresoc.v:125404.5-125404.29" switch \initial - attribute \src "libresoc.v:123686.9-123686.17" + attribute \src "libresoc.v:125404.9-125404.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -194407,18 +196839,18 @@ module \dec_bi$144 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:123696.3-123706.6" - process $proc$libresoc.v:123696$4803 + attribute \src "libresoc.v:125414.3-125424.6" + process $proc$libresoc.v:125414$4848 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:123697.5-123697.29" + attribute \src "libresoc.v:125415.5-125415.29" switch \initial - attribute \src "libresoc.v:123697.9-123697.17" + attribute \src "libresoc.v:125415.9-125415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -194430,111 +196862,111 @@ module \dec_bi$144 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:123537$4784_Y - connect \$11 $pos$libresoc.v:123538$4786_Y - connect \$14 $sshl$libresoc.v:123539$4787_Y - connect \$17 $sshl$libresoc.v:123540$4788_Y - connect \$1 $pos$libresoc.v:123541$4790_Y - connect \$20 $sshl$libresoc.v:123542$4791_Y - connect \$23 $sshl$libresoc.v:123543$4792_Y - connect \$4 $sshl$libresoc.v:123544$4793_Y - connect \$3 $pos$libresoc.v:123545$4795_Y + connect \$9 $pos$libresoc.v:125255$4829_Y + connect \$11 $pos$libresoc.v:125256$4831_Y + connect \$14 $sshl$libresoc.v:125257$4832_Y + connect \$17 $sshl$libresoc.v:125258$4833_Y + connect \$1 $pos$libresoc.v:125259$4835_Y + connect \$20 $sshl$libresoc.v:125260$4836_Y + connect \$23 $sshl$libresoc.v:125261$4837_Y + connect \$4 $sshl$libresoc.v:125262$4838_Y + connect \$3 $pos$libresoc.v:125263$4840_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:123715.1-123968.10" +attribute \src "libresoc.v:125433.1-125686.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" module \dec_bi$149 - attribute \src "libresoc.v:123942.3-123952.6" + attribute \src "libresoc.v:125660.3-125670.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:123953.3-123963.6" + attribute \src "libresoc.v:125671.3-125681.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:123804.3-123850.6" + attribute \src "libresoc.v:125522.3-125568.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:123851.3-123897.6" + attribute \src "libresoc.v:125569.3-125615.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:123716.7-123716.20" + attribute \src "libresoc.v:125434.7-125434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123931.3-123941.6" + attribute \src "libresoc.v:125649.3-125659.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:123898.3-123908.6" + attribute \src "libresoc.v:125616.3-125626.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:123909.3-123919.6" + attribute \src "libresoc.v:125627.3-125637.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:123920.3-123930.6" + attribute \src "libresoc.v:125638.3-125648.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:123942.3-123952.6" + attribute \src "libresoc.v:125660.3-125670.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:123953.3-123963.6" + attribute \src "libresoc.v:125671.3-125681.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:123804.3-123850.6" + attribute \src "libresoc.v:125522.3-125568.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:123851.3-123897.6" + attribute \src "libresoc.v:125569.3-125615.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:123931.3-123941.6" + attribute \src "libresoc.v:125649.3-125659.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:123898.3-123908.6" + attribute \src "libresoc.v:125616.3-125626.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:123909.3-123919.6" + attribute \src "libresoc.v:125627.3-125637.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:123920.3-123930.6" + attribute \src "libresoc.v:125638.3-125648.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:123794.17-123794.108" - wire width 64 $extend$libresoc.v:123794$4805_Y - attribute \src "libresoc.v:123795.18-123795.111" - wire width 64 $extend$libresoc.v:123795$4807_Y - attribute \src "libresoc.v:123798.17-123798.108" - wire width 64 $extend$libresoc.v:123798$4811_Y - attribute \src "libresoc.v:123802.17-123802.102" - wire width 64 $extend$libresoc.v:123802$4816_Y - attribute \src "libresoc.v:123794.17-123794.108" - wire width 64 $pos$libresoc.v:123794$4806_Y - attribute \src "libresoc.v:123795.18-123795.111" - wire width 64 $pos$libresoc.v:123795$4808_Y - attribute \src "libresoc.v:123798.17-123798.108" - wire width 64 $pos$libresoc.v:123798$4812_Y - attribute \src "libresoc.v:123802.17-123802.102" - wire width 64 $pos$libresoc.v:123802$4817_Y - attribute \src "libresoc.v:123796.18-123796.118" - wire width 47 $sshl$libresoc.v:123796$4809_Y - attribute \src "libresoc.v:123797.18-123797.117" - wire width 27 $sshl$libresoc.v:123797$4810_Y - attribute \src "libresoc.v:123799.18-123799.117" - wire width 17 $sshl$libresoc.v:123799$4813_Y - attribute \src "libresoc.v:123800.18-123800.117" - wire width 17 $sshl$libresoc.v:123800$4814_Y - attribute \src "libresoc.v:123801.17-123801.109" - wire width 47 $sshl$libresoc.v:123801$4815_Y + attribute \src "libresoc.v:125512.17-125512.108" + wire width 64 $extend$libresoc.v:125512$4850_Y + attribute \src "libresoc.v:125513.18-125513.111" + wire width 64 $extend$libresoc.v:125513$4852_Y + attribute \src "libresoc.v:125516.17-125516.108" + wire width 64 $extend$libresoc.v:125516$4856_Y + attribute \src "libresoc.v:125520.17-125520.102" + wire width 64 $extend$libresoc.v:125520$4861_Y + attribute \src "libresoc.v:125512.17-125512.108" + wire width 64 $pos$libresoc.v:125512$4851_Y + attribute \src "libresoc.v:125513.18-125513.111" + wire width 64 $pos$libresoc.v:125513$4853_Y + attribute \src "libresoc.v:125516.17-125516.108" + wire width 64 $pos$libresoc.v:125516$4857_Y + attribute \src "libresoc.v:125520.17-125520.102" + wire width 64 $pos$libresoc.v:125520$4862_Y + attribute \src "libresoc.v:125514.18-125514.118" + wire width 47 $sshl$libresoc.v:125514$4854_Y + attribute \src "libresoc.v:125515.18-125515.117" + wire width 27 $sshl$libresoc.v:125515$4855_Y + attribute \src "libresoc.v:125517.18-125517.117" + wire width 17 $sshl$libresoc.v:125517$4858_Y + attribute \src "libresoc.v:125518.18-125518.117" + wire width 17 $sshl$libresoc.v:125518$4859_Y + attribute \src "libresoc.v:125519.17-125519.109" + wire width 47 $sshl$libresoc.v:125519$4860_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -194552,17 +196984,17 @@ module \dec_bi$149 wire width 16 input 4 \LOGICAL_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:123716.7-123716.15" + attribute \src "libresoc.v:125434.7-125434.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -194579,80 +197011,80 @@ module \dec_bi$149 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123794$4805 + cell $pos $extend$libresoc.v:125512$4850 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:123794$4805_Y + connect \Y $extend$libresoc.v:125512$4850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123795$4807 + cell $pos $extend$libresoc.v:125513$4852 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:123795$4807_Y + connect \Y $extend$libresoc.v:125513$4852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:123798$4811 + cell $pos $extend$libresoc.v:125516$4856 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:123798$4811_Y + connect \Y $extend$libresoc.v:125516$4856_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $extend$libresoc.v:123802$4816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:125520$4861 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:123802$4816_Y + connect \Y $extend$libresoc.v:125520$4861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123794$4806 + cell $pos $pos$libresoc.v:125512$4851 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123794$4805_Y - connect \Y $pos$libresoc.v:123794$4806_Y + connect \A $extend$libresoc.v:125512$4850_Y + connect \Y $pos$libresoc.v:125512$4851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123795$4808 + cell $pos $pos$libresoc.v:125513$4853 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123795$4807_Y - connect \Y $pos$libresoc.v:123795$4808_Y + connect \A $extend$libresoc.v:125513$4852_Y + connect \Y $pos$libresoc.v:125513$4853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:123798$4812 + cell $pos $pos$libresoc.v:125516$4857 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123798$4811_Y - connect \Y $pos$libresoc.v:123798$4812_Y + connect \A $extend$libresoc.v:125516$4856_Y + connect \Y $pos$libresoc.v:125516$4857_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $pos$libresoc.v:123802$4817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:125520$4862 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:123802$4816_Y - connect \Y $pos$libresoc.v:123802$4817_Y + connect \A $extend$libresoc.v:125520$4861_Y + connect \Y $pos$libresoc.v:125520$4862_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:123796$4809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:125514$4854 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -194660,10 +197092,10 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:123796$4809_Y + connect \Y $sshl$libresoc.v:125514$4854_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:123797$4810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:125515$4855 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -194671,10 +197103,10 @@ module \dec_bi$149 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:123797$4810_Y + connect \Y $sshl$libresoc.v:125515$4855_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:123799$4813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:125517$4858 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194682,10 +197114,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:123799$4813_Y + connect \Y $sshl$libresoc.v:125517$4858_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:123800$4814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:125518$4859 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194693,10 +197125,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:123800$4814_Y + connect \Y $sshl$libresoc.v:125518$4859_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $sshl $sshl$libresoc.v:123801$4815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125519$4860 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -194704,28 +197136,28 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:123801$4815_Y + connect \Y $sshl$libresoc.v:125519$4860_Y end - attribute \src "libresoc.v:123716.7-123716.20" - process $proc$libresoc.v:123716$4826 + attribute \src "libresoc.v:125434.7-125434.20" + process $proc$libresoc.v:125434$4871 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123804.3-123850.6" - process $proc$libresoc.v:123804$4818 + attribute \src "libresoc.v:125522.3-125568.6" + process $proc$libresoc.v:125522$4863 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:123805.5-123805.29" + attribute \src "libresoc.v:125523.5-125523.29" switch \initial - attribute \src "libresoc.v:123805.9-123805.17" + attribute \src "libresoc.v:125523.9-125523.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -194773,18 +197205,18 @@ module \dec_bi$149 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:123851.3-123897.6" - process $proc$libresoc.v:123851$4819 + attribute \src "libresoc.v:125569.3-125615.6" + process $proc$libresoc.v:125569$4864 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:123852.5-123852.29" + attribute \src "libresoc.v:125570.5-125570.29" switch \initial - attribute \src "libresoc.v:123852.9-123852.17" + attribute \src "libresoc.v:125570.9-125570.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -194832,18 +197264,18 @@ module \dec_bi$149 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:123898.3-123908.6" - process $proc$libresoc.v:123898$4820 + attribute \src "libresoc.v:125616.3-125626.6" + process $proc$libresoc.v:125616$4865 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:123899.5-123899.29" + attribute \src "libresoc.v:125617.5-125617.29" switch \initial - attribute \src "libresoc.v:123899.9-123899.17" + attribute \src "libresoc.v:125617.9-125617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -194855,18 +197287,18 @@ module \dec_bi$149 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:123909.3-123919.6" - process $proc$libresoc.v:123909$4821 + attribute \src "libresoc.v:125627.3-125637.6" + process $proc$libresoc.v:125627$4866 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:123910.5-123910.29" + attribute \src "libresoc.v:125628.5-125628.29" switch \initial - attribute \src "libresoc.v:123910.9-123910.17" + attribute \src "libresoc.v:125628.9-125628.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -194878,18 +197310,18 @@ module \dec_bi$149 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:123920.3-123930.6" - process $proc$libresoc.v:123920$4822 + attribute \src "libresoc.v:125638.3-125648.6" + process $proc$libresoc.v:125638$4867 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:123921.5-123921.29" + attribute \src "libresoc.v:125639.5-125639.29" switch \initial - attribute \src "libresoc.v:123921.9-123921.17" + attribute \src "libresoc.v:125639.9-125639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -194901,18 +197333,18 @@ module \dec_bi$149 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:123931.3-123941.6" - process $proc$libresoc.v:123931$4823 + attribute \src "libresoc.v:125649.3-125659.6" + process $proc$libresoc.v:125649$4868 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:123932.5-123932.29" + attribute \src "libresoc.v:125650.5-125650.29" switch \initial - attribute \src "libresoc.v:123932.9-123932.17" + attribute \src "libresoc.v:125650.9-125650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -194924,18 +197356,18 @@ module \dec_bi$149 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:123942.3-123952.6" - process $proc$libresoc.v:123942$4824 + attribute \src "libresoc.v:125660.3-125670.6" + process $proc$libresoc.v:125660$4869 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:123943.5-123943.29" + attribute \src "libresoc.v:125661.5-125661.29" switch \initial - attribute \src "libresoc.v:123943.9-123943.17" + attribute \src "libresoc.v:125661.9-125661.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -194947,18 +197379,18 @@ module \dec_bi$149 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:123953.3-123963.6" - process $proc$libresoc.v:123953$4825 + attribute \src "libresoc.v:125671.3-125681.6" + process $proc$libresoc.v:125671$4870 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:123954.5-123954.29" + attribute \src "libresoc.v:125672.5-125672.29" switch \initial - attribute \src "libresoc.v:123954.9-123954.17" + attribute \src "libresoc.v:125672.9-125672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -194970,111 +197402,111 @@ module \dec_bi$149 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:123794$4806_Y - connect \$11 $pos$libresoc.v:123795$4808_Y - connect \$14 $sshl$libresoc.v:123796$4809_Y - connect \$17 $sshl$libresoc.v:123797$4810_Y - connect \$1 $pos$libresoc.v:123798$4812_Y - connect \$20 $sshl$libresoc.v:123799$4813_Y - connect \$23 $sshl$libresoc.v:123800$4814_Y - connect \$4 $sshl$libresoc.v:123801$4815_Y - connect \$3 $pos$libresoc.v:123802$4817_Y + connect \$9 $pos$libresoc.v:125512$4851_Y + connect \$11 $pos$libresoc.v:125513$4853_Y + connect \$14 $sshl$libresoc.v:125514$4854_Y + connect \$17 $sshl$libresoc.v:125515$4855_Y + connect \$1 $pos$libresoc.v:125516$4857_Y + connect \$20 $sshl$libresoc.v:125517$4858_Y + connect \$23 $sshl$libresoc.v:125518$4859_Y + connect \$4 $sshl$libresoc.v:125519$4860_Y + connect \$3 $pos$libresoc.v:125520$4862_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:123972.1-124225.10" +attribute \src "libresoc.v:125690.1-125943.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" module \dec_bi$157 - attribute \src "libresoc.v:124199.3-124209.6" + attribute \src "libresoc.v:125917.3-125927.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:124210.3-124220.6" + attribute \src "libresoc.v:125928.3-125938.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:124061.3-124107.6" + attribute \src "libresoc.v:125779.3-125825.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:124108.3-124154.6" + attribute \src "libresoc.v:125826.3-125872.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:123973.7-123973.20" + attribute \src "libresoc.v:125691.7-125691.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124188.3-124198.6" + attribute \src "libresoc.v:125906.3-125916.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:124155.3-124165.6" + attribute \src "libresoc.v:125873.3-125883.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:124166.3-124176.6" + attribute \src "libresoc.v:125884.3-125894.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:124177.3-124187.6" + attribute \src "libresoc.v:125895.3-125905.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:124199.3-124209.6" + attribute \src "libresoc.v:125917.3-125927.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:124210.3-124220.6" + attribute \src "libresoc.v:125928.3-125938.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:124061.3-124107.6" + attribute \src "libresoc.v:125779.3-125825.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:124108.3-124154.6" + attribute \src "libresoc.v:125826.3-125872.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124188.3-124198.6" + attribute \src "libresoc.v:125906.3-125916.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:124155.3-124165.6" + attribute \src "libresoc.v:125873.3-125883.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:124166.3-124176.6" + attribute \src "libresoc.v:125884.3-125894.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:124177.3-124187.6" + attribute \src "libresoc.v:125895.3-125905.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124051.17-124051.104" - wire width 64 $extend$libresoc.v:124051$4827_Y - attribute \src "libresoc.v:124052.18-124052.107" - wire width 64 $extend$libresoc.v:124052$4829_Y - attribute \src "libresoc.v:124055.17-124055.104" - wire width 64 $extend$libresoc.v:124055$4833_Y - attribute \src "libresoc.v:124059.17-124059.102" - wire width 64 $extend$libresoc.v:124059$4838_Y - attribute \src "libresoc.v:124051.17-124051.104" - wire width 64 $pos$libresoc.v:124051$4828_Y - attribute \src "libresoc.v:124052.18-124052.107" - wire width 64 $pos$libresoc.v:124052$4830_Y - attribute \src "libresoc.v:124055.17-124055.104" - wire width 64 $pos$libresoc.v:124055$4834_Y - attribute \src "libresoc.v:124059.17-124059.102" - wire width 64 $pos$libresoc.v:124059$4839_Y - attribute \src "libresoc.v:124053.18-124053.114" - wire width 47 $sshl$libresoc.v:124053$4831_Y - attribute \src "libresoc.v:124054.18-124054.113" - wire width 27 $sshl$libresoc.v:124054$4832_Y - attribute \src "libresoc.v:124056.18-124056.113" - wire width 17 $sshl$libresoc.v:124056$4835_Y - attribute \src "libresoc.v:124057.18-124057.113" - wire width 17 $sshl$libresoc.v:124057$4836_Y - attribute \src "libresoc.v:124058.17-124058.109" - wire width 47 $sshl$libresoc.v:124058$4837_Y + attribute \src "libresoc.v:125769.17-125769.104" + wire width 64 $extend$libresoc.v:125769$4872_Y + attribute \src "libresoc.v:125770.18-125770.107" + wire width 64 $extend$libresoc.v:125770$4874_Y + attribute \src "libresoc.v:125773.17-125773.104" + wire width 64 $extend$libresoc.v:125773$4878_Y + attribute \src "libresoc.v:125777.17-125777.102" + wire width 64 $extend$libresoc.v:125777$4883_Y + attribute \src "libresoc.v:125769.17-125769.104" + wire width 64 $pos$libresoc.v:125769$4873_Y + attribute \src "libresoc.v:125770.18-125770.107" + wire width 64 $pos$libresoc.v:125770$4875_Y + attribute \src "libresoc.v:125773.17-125773.104" + wire width 64 $pos$libresoc.v:125773$4879_Y + attribute \src "libresoc.v:125777.17-125777.102" + wire width 64 $pos$libresoc.v:125777$4884_Y + attribute \src "libresoc.v:125771.18-125771.114" + wire width 47 $sshl$libresoc.v:125771$4876_Y + attribute \src "libresoc.v:125772.18-125772.113" + wire width 27 $sshl$libresoc.v:125772$4877_Y + attribute \src "libresoc.v:125774.18-125774.113" + wire width 17 $sshl$libresoc.v:125774$4880_Y + attribute \src "libresoc.v:125775.18-125775.113" + wire width 17 $sshl$libresoc.v:125775$4881_Y + attribute \src "libresoc.v:125776.17-125776.109" + wire width 47 $sshl$libresoc.v:125776$4882_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -195092,17 +197524,17 @@ module \dec_bi$157 wire width 16 input 4 \DIV_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:123973.7-123973.15" + attribute \src "libresoc.v:125691.7-125691.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -195119,80 +197551,80 @@ module \dec_bi$157 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124051$4827 + cell $pos $extend$libresoc.v:125769$4872 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh - connect \Y $extend$libresoc.v:124051$4827_Y + connect \Y $extend$libresoc.v:125769$4872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124052$4829 + cell $pos $extend$libresoc.v:125770$4874 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:124052$4829_Y + connect \Y $extend$libresoc.v:125770$4874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124055$4833 + cell $pos $extend$libresoc.v:125773$4878 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI - connect \Y $extend$libresoc.v:124055$4833_Y + connect \Y $extend$libresoc.v:125773$4878_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $extend$libresoc.v:124059$4838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:125777$4883 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:124059$4838_Y + connect \Y $extend$libresoc.v:125777$4883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124051$4828 + cell $pos $pos$libresoc.v:125769$4873 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124051$4827_Y - connect \Y $pos$libresoc.v:124051$4828_Y + connect \A $extend$libresoc.v:125769$4872_Y + connect \Y $pos$libresoc.v:125769$4873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124052$4830 + cell $pos $pos$libresoc.v:125770$4875 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124052$4829_Y - connect \Y $pos$libresoc.v:124052$4830_Y + connect \A $extend$libresoc.v:125770$4874_Y + connect \Y $pos$libresoc.v:125770$4875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124055$4834 + cell $pos $pos$libresoc.v:125773$4879 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124055$4833_Y - connect \Y $pos$libresoc.v:124055$4834_Y + connect \A $extend$libresoc.v:125773$4878_Y + connect \Y $pos$libresoc.v:125773$4879_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $pos$libresoc.v:124059$4839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:125777$4884 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124059$4838_Y - connect \Y $pos$libresoc.v:124059$4839_Y + connect \A $extend$libresoc.v:125777$4883_Y + connect \Y $pos$libresoc.v:125777$4884_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:124053$4831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:125771$4876 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -195200,10 +197632,10 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:124053$4831_Y + connect \Y $sshl$libresoc.v:125771$4876_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:124054$4832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:125772$4877 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -195211,10 +197643,10 @@ module \dec_bi$157 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:124054$4832_Y + connect \Y $sshl$libresoc.v:125772$4877_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:124056$4835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:125774$4880 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195222,10 +197654,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:124056$4835_Y + connect \Y $sshl$libresoc.v:125774$4880_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:124057$4836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:125775$4881 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195233,10 +197665,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:124057$4836_Y + connect \Y $sshl$libresoc.v:125775$4881_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $sshl $sshl$libresoc.v:124058$4837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125776$4882 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -195244,28 +197676,28 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:124058$4837_Y + connect \Y $sshl$libresoc.v:125776$4882_Y end - attribute \src "libresoc.v:123973.7-123973.20" - process $proc$libresoc.v:123973$4848 + attribute \src "libresoc.v:125691.7-125691.20" + process $proc$libresoc.v:125691$4893 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124061.3-124107.6" - process $proc$libresoc.v:124061$4840 + attribute \src "libresoc.v:125779.3-125825.6" + process $proc$libresoc.v:125779$4885 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:124062.5-124062.29" + attribute \src "libresoc.v:125780.5-125780.29" switch \initial - attribute \src "libresoc.v:124062.9-124062.17" + attribute \src "libresoc.v:125780.9-125780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -195313,18 +197745,18 @@ module \dec_bi$157 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:124108.3-124154.6" - process $proc$libresoc.v:124108$4841 + attribute \src "libresoc.v:125826.3-125872.6" + process $proc$libresoc.v:125826$4886 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124109.5-124109.29" + attribute \src "libresoc.v:125827.5-125827.29" switch \initial - attribute \src "libresoc.v:124109.9-124109.17" + attribute \src "libresoc.v:125827.9-125827.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -195372,18 +197804,18 @@ module \dec_bi$157 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:124155.3-124165.6" - process $proc$libresoc.v:124155$4842 + attribute \src "libresoc.v:125873.3-125883.6" + process $proc$libresoc.v:125873$4887 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:124156.5-124156.29" + attribute \src "libresoc.v:125874.5-125874.29" switch \initial - attribute \src "libresoc.v:124156.9-124156.17" + attribute \src "libresoc.v:125874.9-125874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -195395,18 +197827,18 @@ module \dec_bi$157 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:124166.3-124176.6" - process $proc$libresoc.v:124166$4843 + attribute \src "libresoc.v:125884.3-125894.6" + process $proc$libresoc.v:125884$4888 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:124167.5-124167.29" + attribute \src "libresoc.v:125885.5-125885.29" switch \initial - attribute \src "libresoc.v:124167.9-124167.17" + attribute \src "libresoc.v:125885.9-125885.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -195418,18 +197850,18 @@ module \dec_bi$157 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:124177.3-124187.6" - process $proc$libresoc.v:124177$4844 + attribute \src "libresoc.v:125895.3-125905.6" + process $proc$libresoc.v:125895$4889 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:124178.5-124178.29" + attribute \src "libresoc.v:125896.5-125896.29" switch \initial - attribute \src "libresoc.v:124178.9-124178.17" + attribute \src "libresoc.v:125896.9-125896.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -195441,18 +197873,18 @@ module \dec_bi$157 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:124188.3-124198.6" - process $proc$libresoc.v:124188$4845 + attribute \src "libresoc.v:125906.3-125916.6" + process $proc$libresoc.v:125906$4890 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:124189.5-124189.29" + attribute \src "libresoc.v:125907.5-125907.29" switch \initial - attribute \src "libresoc.v:124189.9-124189.17" + attribute \src "libresoc.v:125907.9-125907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -195464,18 +197896,18 @@ module \dec_bi$157 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:124199.3-124209.6" - process $proc$libresoc.v:124199$4846 + attribute \src "libresoc.v:125917.3-125927.6" + process $proc$libresoc.v:125917$4891 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:124200.5-124200.29" + attribute \src "libresoc.v:125918.5-125918.29" switch \initial - attribute \src "libresoc.v:124200.9-124200.17" + attribute \src "libresoc.v:125918.9-125918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -195487,18 +197919,18 @@ module \dec_bi$157 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:124210.3-124220.6" - process $proc$libresoc.v:124210$4847 + attribute \src "libresoc.v:125928.3-125938.6" + process $proc$libresoc.v:125928$4892 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:124211.5-124211.29" + attribute \src "libresoc.v:125929.5-125929.29" switch \initial - attribute \src "libresoc.v:124211.9-124211.17" + attribute \src "libresoc.v:125929.9-125929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -195510,111 +197942,111 @@ module \dec_bi$157 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124051$4828_Y - connect \$11 $pos$libresoc.v:124052$4830_Y - connect \$14 $sshl$libresoc.v:124053$4831_Y - connect \$17 $sshl$libresoc.v:124054$4832_Y - connect \$1 $pos$libresoc.v:124055$4834_Y - connect \$20 $sshl$libresoc.v:124056$4835_Y - connect \$23 $sshl$libresoc.v:124057$4836_Y - connect \$4 $sshl$libresoc.v:124058$4837_Y - connect \$3 $pos$libresoc.v:124059$4839_Y + connect \$9 $pos$libresoc.v:125769$4873_Y + connect \$11 $pos$libresoc.v:125770$4875_Y + connect \$14 $sshl$libresoc.v:125771$4876_Y + connect \$17 $sshl$libresoc.v:125772$4877_Y + connect \$1 $pos$libresoc.v:125773$4879_Y + connect \$20 $sshl$libresoc.v:125774$4880_Y + connect \$23 $sshl$libresoc.v:125775$4881_Y + connect \$4 $sshl$libresoc.v:125776$4882_Y + connect \$3 $pos$libresoc.v:125777$4884_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:124229.1-124482.10" +attribute \src "libresoc.v:125947.1-126200.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" module \dec_bi$161 - attribute \src "libresoc.v:124456.3-124466.6" + attribute \src "libresoc.v:126174.3-126184.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:124467.3-124477.6" + attribute \src "libresoc.v:126185.3-126195.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:124318.3-124364.6" + attribute \src "libresoc.v:126036.3-126082.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:124365.3-124411.6" + attribute \src "libresoc.v:126083.3-126129.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:124230.7-124230.20" + attribute \src "libresoc.v:125948.7-125948.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124445.3-124455.6" + attribute \src "libresoc.v:126163.3-126173.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:124412.3-124422.6" + attribute \src "libresoc.v:126130.3-126140.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:124423.3-124433.6" + attribute \src "libresoc.v:126141.3-126151.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:124434.3-124444.6" + attribute \src "libresoc.v:126152.3-126162.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:124456.3-124466.6" + attribute \src "libresoc.v:126174.3-126184.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:124467.3-124477.6" + attribute \src "libresoc.v:126185.3-126195.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:124318.3-124364.6" + attribute \src "libresoc.v:126036.3-126082.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:124365.3-124411.6" + attribute \src "libresoc.v:126083.3-126129.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124445.3-124455.6" + attribute \src "libresoc.v:126163.3-126173.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:124412.3-124422.6" + attribute \src "libresoc.v:126130.3-126140.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:124423.3-124433.6" + attribute \src "libresoc.v:126141.3-126151.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:124434.3-124444.6" + attribute \src "libresoc.v:126152.3-126162.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124308.17-124308.104" - wire width 64 $extend$libresoc.v:124308$4849_Y - attribute \src "libresoc.v:124309.18-124309.107" - wire width 64 $extend$libresoc.v:124309$4851_Y - attribute \src "libresoc.v:124312.17-124312.104" - wire width 64 $extend$libresoc.v:124312$4855_Y - attribute \src "libresoc.v:124316.17-124316.102" - wire width 64 $extend$libresoc.v:124316$4860_Y - attribute \src "libresoc.v:124308.17-124308.104" - wire width 64 $pos$libresoc.v:124308$4850_Y - attribute \src "libresoc.v:124309.18-124309.107" - wire width 64 $pos$libresoc.v:124309$4852_Y - attribute \src "libresoc.v:124312.17-124312.104" - wire width 64 $pos$libresoc.v:124312$4856_Y - attribute \src "libresoc.v:124316.17-124316.102" - wire width 64 $pos$libresoc.v:124316$4861_Y - attribute \src "libresoc.v:124310.18-124310.114" - wire width 47 $sshl$libresoc.v:124310$4853_Y - attribute \src "libresoc.v:124311.18-124311.113" - wire width 27 $sshl$libresoc.v:124311$4854_Y - attribute \src "libresoc.v:124313.18-124313.113" - wire width 17 $sshl$libresoc.v:124313$4857_Y - attribute \src "libresoc.v:124314.18-124314.113" - wire width 17 $sshl$libresoc.v:124314$4858_Y - attribute \src "libresoc.v:124315.17-124315.109" - wire width 47 $sshl$libresoc.v:124315$4859_Y + attribute \src "libresoc.v:126026.17-126026.104" + wire width 64 $extend$libresoc.v:126026$4894_Y + attribute \src "libresoc.v:126027.18-126027.107" + wire width 64 $extend$libresoc.v:126027$4896_Y + attribute \src "libresoc.v:126030.17-126030.104" + wire width 64 $extend$libresoc.v:126030$4900_Y + attribute \src "libresoc.v:126034.17-126034.102" + wire width 64 $extend$libresoc.v:126034$4905_Y + attribute \src "libresoc.v:126026.17-126026.104" + wire width 64 $pos$libresoc.v:126026$4895_Y + attribute \src "libresoc.v:126027.18-126027.107" + wire width 64 $pos$libresoc.v:126027$4897_Y + attribute \src "libresoc.v:126030.17-126030.104" + wire width 64 $pos$libresoc.v:126030$4901_Y + attribute \src "libresoc.v:126034.17-126034.102" + wire width 64 $pos$libresoc.v:126034$4906_Y + attribute \src "libresoc.v:126028.18-126028.114" + wire width 47 $sshl$libresoc.v:126028$4898_Y + attribute \src "libresoc.v:126029.18-126029.113" + wire width 27 $sshl$libresoc.v:126029$4899_Y + attribute \src "libresoc.v:126031.18-126031.113" + wire width 17 $sshl$libresoc.v:126031$4902_Y + attribute \src "libresoc.v:126032.18-126032.113" + wire width 17 $sshl$libresoc.v:126032$4903_Y + attribute \src "libresoc.v:126033.17-126033.109" + wire width 47 $sshl$libresoc.v:126033$4904_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -195632,17 +198064,17 @@ module \dec_bi$161 wire width 16 input 4 \MUL_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:124230.7-124230.15" + attribute \src "libresoc.v:125948.7-125948.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -195659,80 +198091,80 @@ module \dec_bi$161 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124308$4849 + cell $pos $extend$libresoc.v:126026$4894 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh - connect \Y $extend$libresoc.v:124308$4849_Y + connect \Y $extend$libresoc.v:126026$4894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124309$4851 + cell $pos $extend$libresoc.v:126027$4896 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:124309$4851_Y + connect \Y $extend$libresoc.v:126027$4896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124312$4855 + cell $pos $extend$libresoc.v:126030$4900 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI - connect \Y $extend$libresoc.v:124312$4855_Y + connect \Y $extend$libresoc.v:126030$4900_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $extend$libresoc.v:124316$4860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:126034$4905 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:124316$4860_Y + connect \Y $extend$libresoc.v:126034$4905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124308$4850 + cell $pos $pos$libresoc.v:126026$4895 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124308$4849_Y - connect \Y $pos$libresoc.v:124308$4850_Y + connect \A $extend$libresoc.v:126026$4894_Y + connect \Y $pos$libresoc.v:126026$4895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124309$4852 + cell $pos $pos$libresoc.v:126027$4897 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124309$4851_Y - connect \Y $pos$libresoc.v:124309$4852_Y + connect \A $extend$libresoc.v:126027$4896_Y + connect \Y $pos$libresoc.v:126027$4897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124312$4856 + cell $pos $pos$libresoc.v:126030$4901 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124312$4855_Y - connect \Y $pos$libresoc.v:124312$4856_Y + connect \A $extend$libresoc.v:126030$4900_Y + connect \Y $pos$libresoc.v:126030$4901_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $pos$libresoc.v:124316$4861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:126034$4906 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124316$4860_Y - connect \Y $pos$libresoc.v:124316$4861_Y + connect \A $extend$libresoc.v:126034$4905_Y + connect \Y $pos$libresoc.v:126034$4906_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:124310$4853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:126028$4898 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -195740,10 +198172,10 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:124310$4853_Y + connect \Y $sshl$libresoc.v:126028$4898_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:124311$4854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:126029$4899 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -195751,10 +198183,10 @@ module \dec_bi$161 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:124311$4854_Y + connect \Y $sshl$libresoc.v:126029$4899_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:124313$4857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:126031$4902 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195762,10 +198194,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:124313$4857_Y + connect \Y $sshl$libresoc.v:126031$4902_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:124314$4858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:126032$4903 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195773,10 +198205,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:124314$4858_Y + connect \Y $sshl$libresoc.v:126032$4903_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $sshl $sshl$libresoc.v:124315$4859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:126033$4904 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -195784,28 +198216,28 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:124315$4859_Y + connect \Y $sshl$libresoc.v:126033$4904_Y end - attribute \src "libresoc.v:124230.7-124230.20" - process $proc$libresoc.v:124230$4870 + attribute \src "libresoc.v:125948.7-125948.20" + process $proc$libresoc.v:125948$4915 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124318.3-124364.6" - process $proc$libresoc.v:124318$4862 + attribute \src "libresoc.v:126036.3-126082.6" + process $proc$libresoc.v:126036$4907 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:124319.5-124319.29" + attribute \src "libresoc.v:126037.5-126037.29" switch \initial - attribute \src "libresoc.v:124319.9-124319.17" + attribute \src "libresoc.v:126037.9-126037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -195853,18 +198285,18 @@ module \dec_bi$161 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:124365.3-124411.6" - process $proc$libresoc.v:124365$4863 + attribute \src "libresoc.v:126083.3-126129.6" + process $proc$libresoc.v:126083$4908 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124366.5-124366.29" + attribute \src "libresoc.v:126084.5-126084.29" switch \initial - attribute \src "libresoc.v:124366.9-124366.17" + attribute \src "libresoc.v:126084.9-126084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -195912,18 +198344,18 @@ module \dec_bi$161 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:124412.3-124422.6" - process $proc$libresoc.v:124412$4864 + attribute \src "libresoc.v:126130.3-126140.6" + process $proc$libresoc.v:126130$4909 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:124413.5-124413.29" + attribute \src "libresoc.v:126131.5-126131.29" switch \initial - attribute \src "libresoc.v:124413.9-124413.17" + attribute \src "libresoc.v:126131.9-126131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -195935,18 +198367,18 @@ module \dec_bi$161 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:124423.3-124433.6" - process $proc$libresoc.v:124423$4865 + attribute \src "libresoc.v:126141.3-126151.6" + process $proc$libresoc.v:126141$4910 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:124424.5-124424.29" + attribute \src "libresoc.v:126142.5-126142.29" switch \initial - attribute \src "libresoc.v:124424.9-124424.17" + attribute \src "libresoc.v:126142.9-126142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -195958,18 +198390,18 @@ module \dec_bi$161 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:124434.3-124444.6" - process $proc$libresoc.v:124434$4866 + attribute \src "libresoc.v:126152.3-126162.6" + process $proc$libresoc.v:126152$4911 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:124435.5-124435.29" + attribute \src "libresoc.v:126153.5-126153.29" switch \initial - attribute \src "libresoc.v:124435.9-124435.17" + attribute \src "libresoc.v:126153.9-126153.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -195981,18 +198413,18 @@ module \dec_bi$161 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:124445.3-124455.6" - process $proc$libresoc.v:124445$4867 + attribute \src "libresoc.v:126163.3-126173.6" + process $proc$libresoc.v:126163$4912 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:124446.5-124446.29" + attribute \src "libresoc.v:126164.5-126164.29" switch \initial - attribute \src "libresoc.v:124446.9-124446.17" + attribute \src "libresoc.v:126164.9-126164.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -196004,18 +198436,18 @@ module \dec_bi$161 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:124456.3-124466.6" - process $proc$libresoc.v:124456$4868 + attribute \src "libresoc.v:126174.3-126184.6" + process $proc$libresoc.v:126174$4913 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:124457.5-124457.29" + attribute \src "libresoc.v:126175.5-126175.29" switch \initial - attribute \src "libresoc.v:124457.9-124457.17" + attribute \src "libresoc.v:126175.9-126175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -196027,18 +198459,18 @@ module \dec_bi$161 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:124467.3-124477.6" - process $proc$libresoc.v:124467$4869 + attribute \src "libresoc.v:126185.3-126195.6" + process $proc$libresoc.v:126185$4914 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:124468.5-124468.29" + attribute \src "libresoc.v:126186.5-126186.29" switch \initial - attribute \src "libresoc.v:124468.9-124468.17" + attribute \src "libresoc.v:126186.9-126186.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -196050,111 +198482,111 @@ module \dec_bi$161 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124308$4850_Y - connect \$11 $pos$libresoc.v:124309$4852_Y - connect \$14 $sshl$libresoc.v:124310$4853_Y - connect \$17 $sshl$libresoc.v:124311$4854_Y - connect \$1 $pos$libresoc.v:124312$4856_Y - connect \$20 $sshl$libresoc.v:124313$4857_Y - connect \$23 $sshl$libresoc.v:124314$4858_Y - connect \$4 $sshl$libresoc.v:124315$4859_Y - connect \$3 $pos$libresoc.v:124316$4861_Y + connect \$9 $pos$libresoc.v:126026$4895_Y + connect \$11 $pos$libresoc.v:126027$4897_Y + connect \$14 $sshl$libresoc.v:126028$4898_Y + connect \$17 $sshl$libresoc.v:126029$4899_Y + connect \$1 $pos$libresoc.v:126030$4901_Y + connect \$20 $sshl$libresoc.v:126031$4902_Y + connect \$23 $sshl$libresoc.v:126032$4903_Y + connect \$4 $sshl$libresoc.v:126033$4904_Y + connect \$3 $pos$libresoc.v:126034$4906_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:124486.1-124739.10" +attribute \src "libresoc.v:126204.1-126457.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" module \dec_bi$165 - attribute \src "libresoc.v:124713.3-124723.6" + attribute \src "libresoc.v:126431.3-126441.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:124724.3-124734.6" + attribute \src "libresoc.v:126442.3-126452.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:124575.3-124621.6" + attribute \src "libresoc.v:126293.3-126339.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:124622.3-124668.6" + attribute \src "libresoc.v:126340.3-126386.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:124487.7-124487.20" + attribute \src "libresoc.v:126205.7-126205.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124702.3-124712.6" + attribute \src "libresoc.v:126420.3-126430.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:124669.3-124679.6" + attribute \src "libresoc.v:126387.3-126397.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:124680.3-124690.6" + attribute \src "libresoc.v:126398.3-126408.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:124691.3-124701.6" + attribute \src "libresoc.v:126409.3-126419.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:124713.3-124723.6" + attribute \src "libresoc.v:126431.3-126441.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:124724.3-124734.6" + attribute \src "libresoc.v:126442.3-126452.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:124575.3-124621.6" + attribute \src "libresoc.v:126293.3-126339.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:124622.3-124668.6" + attribute \src "libresoc.v:126340.3-126386.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124702.3-124712.6" + attribute \src "libresoc.v:126420.3-126430.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:124669.3-124679.6" + attribute \src "libresoc.v:126387.3-126397.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:124680.3-124690.6" + attribute \src "libresoc.v:126398.3-126408.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:124691.3-124701.6" + attribute \src "libresoc.v:126409.3-126419.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124565.17-124565.110" - wire width 64 $extend$libresoc.v:124565$4871_Y - attribute \src "libresoc.v:124566.18-124566.113" - wire width 64 $extend$libresoc.v:124566$4873_Y - attribute \src "libresoc.v:124569.17-124569.110" - wire width 64 $extend$libresoc.v:124569$4877_Y - attribute \src "libresoc.v:124573.17-124573.102" - wire width 64 $extend$libresoc.v:124573$4882_Y - attribute \src "libresoc.v:124565.17-124565.110" - wire width 64 $pos$libresoc.v:124565$4872_Y - attribute \src "libresoc.v:124566.18-124566.113" - wire width 64 $pos$libresoc.v:124566$4874_Y - attribute \src "libresoc.v:124569.17-124569.110" - wire width 64 $pos$libresoc.v:124569$4878_Y - attribute \src "libresoc.v:124573.17-124573.102" - wire width 64 $pos$libresoc.v:124573$4883_Y - attribute \src "libresoc.v:124567.18-124567.120" - wire width 47 $sshl$libresoc.v:124567$4875_Y - attribute \src "libresoc.v:124568.18-124568.119" - wire width 27 $sshl$libresoc.v:124568$4876_Y - attribute \src "libresoc.v:124570.18-124570.119" - wire width 17 $sshl$libresoc.v:124570$4879_Y - attribute \src "libresoc.v:124571.18-124571.119" - wire width 17 $sshl$libresoc.v:124571$4880_Y - attribute \src "libresoc.v:124572.17-124572.109" - wire width 47 $sshl$libresoc.v:124572$4881_Y + attribute \src "libresoc.v:126283.17-126283.110" + wire width 64 $extend$libresoc.v:126283$4916_Y + attribute \src "libresoc.v:126284.18-126284.113" + wire width 64 $extend$libresoc.v:126284$4918_Y + attribute \src "libresoc.v:126287.17-126287.110" + wire width 64 $extend$libresoc.v:126287$4922_Y + attribute \src "libresoc.v:126291.17-126291.102" + wire width 64 $extend$libresoc.v:126291$4927_Y + attribute \src "libresoc.v:126283.17-126283.110" + wire width 64 $pos$libresoc.v:126283$4917_Y + attribute \src "libresoc.v:126284.18-126284.113" + wire width 64 $pos$libresoc.v:126284$4919_Y + attribute \src "libresoc.v:126287.17-126287.110" + wire width 64 $pos$libresoc.v:126287$4923_Y + attribute \src "libresoc.v:126291.17-126291.102" + wire width 64 $pos$libresoc.v:126291$4928_Y + attribute \src "libresoc.v:126285.18-126285.120" + wire width 47 $sshl$libresoc.v:126285$4920_Y + attribute \src "libresoc.v:126286.18-126286.119" + wire width 27 $sshl$libresoc.v:126286$4921_Y + attribute \src "libresoc.v:126288.18-126288.119" + wire width 17 $sshl$libresoc.v:126288$4924_Y + attribute \src "libresoc.v:126289.18-126289.119" + wire width 17 $sshl$libresoc.v:126289$4925_Y + attribute \src "libresoc.v:126290.17-126290.109" + wire width 47 $sshl$libresoc.v:126290$4926_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -196172,17 +198604,17 @@ module \dec_bi$165 wire width 16 input 4 \SHIFT_ROT_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:124487.7-124487.15" + attribute \src "libresoc.v:126205.7-126205.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -196199,80 +198631,80 @@ module \dec_bi$165 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124565$4871 + cell $pos $extend$libresoc.v:126283$4916 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:124565$4871_Y + connect \Y $extend$libresoc.v:126283$4916_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124566$4873 + cell $pos $extend$libresoc.v:126284$4918 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:124566$4873_Y + connect \Y $extend$libresoc.v:126284$4918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124569$4877 + cell $pos $extend$libresoc.v:126287$4922 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:124569$4877_Y + connect \Y $extend$libresoc.v:126287$4922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $extend$libresoc.v:124573$4882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:126291$4927 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:124573$4882_Y + connect \Y $extend$libresoc.v:126291$4927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124565$4872 + cell $pos $pos$libresoc.v:126283$4917 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124565$4871_Y - connect \Y $pos$libresoc.v:124565$4872_Y + connect \A $extend$libresoc.v:126283$4916_Y + connect \Y $pos$libresoc.v:126283$4917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124566$4874 + cell $pos $pos$libresoc.v:126284$4919 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124566$4873_Y - connect \Y $pos$libresoc.v:124566$4874_Y + connect \A $extend$libresoc.v:126284$4918_Y + connect \Y $pos$libresoc.v:126284$4919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124569$4878 + cell $pos $pos$libresoc.v:126287$4923 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124569$4877_Y - connect \Y $pos$libresoc.v:124569$4878_Y + connect \A $extend$libresoc.v:126287$4922_Y + connect \Y $pos$libresoc.v:126287$4923_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $pos$libresoc.v:124573$4883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:126291$4928 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124573$4882_Y - connect \Y $pos$libresoc.v:124573$4883_Y + connect \A $extend$libresoc.v:126291$4927_Y + connect \Y $pos$libresoc.v:126291$4928_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:124567$4875 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:126285$4920 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196280,10 +198712,10 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:124567$4875_Y + connect \Y $sshl$libresoc.v:126285$4920_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:124568$4876 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:126286$4921 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -196291,10 +198723,10 @@ module \dec_bi$165 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:124568$4876_Y + connect \Y $sshl$libresoc.v:126286$4921_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:124570$4879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:126288$4924 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196302,10 +198734,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:124570$4879_Y + connect \Y $sshl$libresoc.v:126288$4924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:124571$4880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:126289$4925 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196313,10 +198745,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:124571$4880_Y + connect \Y $sshl$libresoc.v:126289$4925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $sshl $sshl$libresoc.v:124572$4881 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:126290$4926 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196324,28 +198756,28 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:124572$4881_Y + connect \Y $sshl$libresoc.v:126290$4926_Y end - attribute \src "libresoc.v:124487.7-124487.20" - process $proc$libresoc.v:124487$4892 + attribute \src "libresoc.v:126205.7-126205.20" + process $proc$libresoc.v:126205$4937 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124575.3-124621.6" - process $proc$libresoc.v:124575$4884 + attribute \src "libresoc.v:126293.3-126339.6" + process $proc$libresoc.v:126293$4929 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:124576.5-124576.29" + attribute \src "libresoc.v:126294.5-126294.29" switch \initial - attribute \src "libresoc.v:124576.9-124576.17" + attribute \src "libresoc.v:126294.9-126294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196393,18 +198825,18 @@ module \dec_bi$165 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:124622.3-124668.6" - process $proc$libresoc.v:124622$4885 + attribute \src "libresoc.v:126340.3-126386.6" + process $proc$libresoc.v:126340$4930 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124623.5-124623.29" + attribute \src "libresoc.v:126341.5-126341.29" switch \initial - attribute \src "libresoc.v:124623.9-124623.17" + attribute \src "libresoc.v:126341.9-126341.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196452,18 +198884,18 @@ module \dec_bi$165 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:124669.3-124679.6" - process $proc$libresoc.v:124669$4886 + attribute \src "libresoc.v:126387.3-126397.6" + process $proc$libresoc.v:126387$4931 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:124670.5-124670.29" + attribute \src "libresoc.v:126388.5-126388.29" switch \initial - attribute \src "libresoc.v:124670.9-124670.17" + attribute \src "libresoc.v:126388.9-126388.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -196475,18 +198907,18 @@ module \dec_bi$165 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:124680.3-124690.6" - process $proc$libresoc.v:124680$4887 + attribute \src "libresoc.v:126398.3-126408.6" + process $proc$libresoc.v:126398$4932 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:124681.5-124681.29" + attribute \src "libresoc.v:126399.5-126399.29" switch \initial - attribute \src "libresoc.v:124681.9-124681.17" + attribute \src "libresoc.v:126399.9-126399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -196498,18 +198930,18 @@ module \dec_bi$165 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:124691.3-124701.6" - process $proc$libresoc.v:124691$4888 + attribute \src "libresoc.v:126409.3-126419.6" + process $proc$libresoc.v:126409$4933 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:124692.5-124692.29" + attribute \src "libresoc.v:126410.5-126410.29" switch \initial - attribute \src "libresoc.v:124692.9-124692.17" + attribute \src "libresoc.v:126410.9-126410.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -196521,18 +198953,18 @@ module \dec_bi$165 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:124702.3-124712.6" - process $proc$libresoc.v:124702$4889 + attribute \src "libresoc.v:126420.3-126430.6" + process $proc$libresoc.v:126420$4934 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:124703.5-124703.29" + attribute \src "libresoc.v:126421.5-126421.29" switch \initial - attribute \src "libresoc.v:124703.9-124703.17" + attribute \src "libresoc.v:126421.9-126421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -196544,18 +198976,18 @@ module \dec_bi$165 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:124713.3-124723.6" - process $proc$libresoc.v:124713$4890 + attribute \src "libresoc.v:126431.3-126441.6" + process $proc$libresoc.v:126431$4935 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:124714.5-124714.29" + attribute \src "libresoc.v:126432.5-126432.29" switch \initial - attribute \src "libresoc.v:124714.9-124714.17" + attribute \src "libresoc.v:126432.9-126432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -196567,18 +198999,18 @@ module \dec_bi$165 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:124724.3-124734.6" - process $proc$libresoc.v:124724$4891 + attribute \src "libresoc.v:126442.3-126452.6" + process $proc$libresoc.v:126442$4936 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:124725.5-124725.29" + attribute \src "libresoc.v:126443.5-126443.29" switch \initial - attribute \src "libresoc.v:124725.9-124725.17" + attribute \src "libresoc.v:126443.9-126443.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -196590,111 +199022,111 @@ module \dec_bi$165 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124565$4872_Y - connect \$11 $pos$libresoc.v:124566$4874_Y - connect \$14 $sshl$libresoc.v:124567$4875_Y - connect \$17 $sshl$libresoc.v:124568$4876_Y - connect \$1 $pos$libresoc.v:124569$4878_Y - connect \$20 $sshl$libresoc.v:124570$4879_Y - connect \$23 $sshl$libresoc.v:124571$4880_Y - connect \$4 $sshl$libresoc.v:124572$4881_Y - connect \$3 $pos$libresoc.v:124573$4883_Y + connect \$9 $pos$libresoc.v:126283$4917_Y + connect \$11 $pos$libresoc.v:126284$4919_Y + connect \$14 $sshl$libresoc.v:126285$4920_Y + connect \$17 $sshl$libresoc.v:126286$4921_Y + connect \$1 $pos$libresoc.v:126287$4923_Y + connect \$20 $sshl$libresoc.v:126288$4924_Y + connect \$23 $sshl$libresoc.v:126289$4925_Y + connect \$4 $sshl$libresoc.v:126290$4926_Y + connect \$3 $pos$libresoc.v:126291$4928_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:124743.1-124996.10" +attribute \src "libresoc.v:126461.1-126714.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" module \dec_bi$170 - attribute \src "libresoc.v:124970.3-124980.6" + attribute \src "libresoc.v:126688.3-126698.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:124981.3-124991.6" + attribute \src "libresoc.v:126699.3-126709.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:124832.3-124878.6" + attribute \src "libresoc.v:126550.3-126596.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:124879.3-124925.6" + attribute \src "libresoc.v:126597.3-126643.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:124744.7-124744.20" + attribute \src "libresoc.v:126462.7-126462.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124959.3-124969.6" + attribute \src "libresoc.v:126677.3-126687.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:124926.3-124936.6" + attribute \src "libresoc.v:126644.3-126654.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:124937.3-124947.6" + attribute \src "libresoc.v:126655.3-126665.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:124948.3-124958.6" + attribute \src "libresoc.v:126666.3-126676.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:124970.3-124980.6" + attribute \src "libresoc.v:126688.3-126698.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:124981.3-124991.6" + attribute \src "libresoc.v:126699.3-126709.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:124832.3-124878.6" + attribute \src "libresoc.v:126550.3-126596.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:124879.3-124925.6" + attribute \src "libresoc.v:126597.3-126643.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124959.3-124969.6" + attribute \src "libresoc.v:126677.3-126687.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:124926.3-124936.6" + attribute \src "libresoc.v:126644.3-126654.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:124937.3-124947.6" + attribute \src "libresoc.v:126655.3-126665.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:124948.3-124958.6" + attribute \src "libresoc.v:126666.3-126676.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124822.17-124822.105" - wire width 64 $extend$libresoc.v:124822$4893_Y - attribute \src "libresoc.v:124823.18-124823.108" - wire width 64 $extend$libresoc.v:124823$4895_Y - attribute \src "libresoc.v:124826.17-124826.105" - wire width 64 $extend$libresoc.v:124826$4899_Y - attribute \src "libresoc.v:124830.17-124830.102" - wire width 64 $extend$libresoc.v:124830$4904_Y - attribute \src "libresoc.v:124822.17-124822.105" - wire width 64 $pos$libresoc.v:124822$4894_Y - attribute \src "libresoc.v:124823.18-124823.108" - wire width 64 $pos$libresoc.v:124823$4896_Y - attribute \src "libresoc.v:124826.17-124826.105" - wire width 64 $pos$libresoc.v:124826$4900_Y - attribute \src "libresoc.v:124830.17-124830.102" - wire width 64 $pos$libresoc.v:124830$4905_Y - attribute \src "libresoc.v:124824.18-124824.115" - wire width 47 $sshl$libresoc.v:124824$4897_Y - attribute \src "libresoc.v:124825.18-124825.114" - wire width 27 $sshl$libresoc.v:124825$4898_Y - attribute \src "libresoc.v:124827.18-124827.114" - wire width 17 $sshl$libresoc.v:124827$4901_Y - attribute \src "libresoc.v:124828.18-124828.114" - wire width 17 $sshl$libresoc.v:124828$4902_Y - attribute \src "libresoc.v:124829.17-124829.109" - wire width 47 $sshl$libresoc.v:124829$4903_Y + attribute \src "libresoc.v:126540.17-126540.105" + wire width 64 $extend$libresoc.v:126540$4938_Y + attribute \src "libresoc.v:126541.18-126541.108" + wire width 64 $extend$libresoc.v:126541$4940_Y + attribute \src "libresoc.v:126544.17-126544.105" + wire width 64 $extend$libresoc.v:126544$4944_Y + attribute \src "libresoc.v:126548.17-126548.102" + wire width 64 $extend$libresoc.v:126548$4949_Y + attribute \src "libresoc.v:126540.17-126540.105" + wire width 64 $pos$libresoc.v:126540$4939_Y + attribute \src "libresoc.v:126541.18-126541.108" + wire width 64 $pos$libresoc.v:126541$4941_Y + attribute \src "libresoc.v:126544.17-126544.105" + wire width 64 $pos$libresoc.v:126544$4945_Y + attribute \src "libresoc.v:126548.17-126548.102" + wire width 64 $pos$libresoc.v:126548$4950_Y + attribute \src "libresoc.v:126542.18-126542.115" + wire width 47 $sshl$libresoc.v:126542$4942_Y + attribute \src "libresoc.v:126543.18-126543.114" + wire width 27 $sshl$libresoc.v:126543$4943_Y + attribute \src "libresoc.v:126545.18-126545.114" + wire width 17 $sshl$libresoc.v:126545$4946_Y + attribute \src "libresoc.v:126546.18-126546.114" + wire width 17 $sshl$libresoc.v:126546$4947_Y + attribute \src "libresoc.v:126547.17-126547.109" + wire width 47 $sshl$libresoc.v:126547$4948_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -196712,17 +199144,17 @@ module \dec_bi$170 wire width 16 input 4 \LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \LDST_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:124744.7-124744.15" + attribute \src "libresoc.v:126462.7-126462.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -196739,80 +199171,80 @@ module \dec_bi$170 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124822$4893 + cell $pos $extend$libresoc.v:126540$4938 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh - connect \Y $extend$libresoc.v:124822$4893_Y + connect \Y $extend$libresoc.v:126540$4938_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124823$4895 + cell $pos $extend$libresoc.v:126541$4940 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:124823$4895_Y + connect \Y $extend$libresoc.v:126541$4940_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124826$4899 + cell $pos $extend$libresoc.v:126544$4944 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI - connect \Y $extend$libresoc.v:124826$4899_Y + connect \Y $extend$libresoc.v:126544$4944_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $extend$libresoc.v:124830$4904 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $extend$libresoc.v:126548$4949 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:124830$4904_Y + connect \Y $extend$libresoc.v:126548$4949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124822$4894 + cell $pos $pos$libresoc.v:126540$4939 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124822$4893_Y - connect \Y $pos$libresoc.v:124822$4894_Y + connect \A $extend$libresoc.v:126540$4938_Y + connect \Y $pos$libresoc.v:126540$4939_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124823$4896 + cell $pos $pos$libresoc.v:126541$4941 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124823$4895_Y - connect \Y $pos$libresoc.v:124823$4896_Y + connect \A $extend$libresoc.v:126541$4940_Y + connect \Y $pos$libresoc.v:126541$4941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124826$4900 + cell $pos $pos$libresoc.v:126544$4945 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124826$4899_Y - connect \Y $pos$libresoc.v:124826$4900_Y + connect \A $extend$libresoc.v:126544$4944_Y + connect \Y $pos$libresoc.v:126544$4945_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $pos $pos$libresoc.v:124830$4905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $pos $pos$libresoc.v:126548$4950 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124830$4904_Y - connect \Y $pos$libresoc.v:124830$4905_Y + connect \A $extend$libresoc.v:126548$4949_Y + connect \Y $pos$libresoc.v:126548$4950_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:124824$4897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + cell $sshl $sshl$libresoc.v:126542$4942 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196820,10 +199252,10 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:124824$4897_Y + connect \Y $sshl$libresoc.v:126542$4942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:124825$4898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + cell $sshl $sshl$libresoc.v:126543$4943 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -196831,10 +199263,10 @@ module \dec_bi$170 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:124825$4898_Y + connect \Y $sshl$libresoc.v:126543$4943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:124827$4901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + cell $sshl $sshl$libresoc.v:126545$4946 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196842,10 +199274,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:124827$4901_Y + connect \Y $sshl$libresoc.v:126545$4946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:124828$4902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + cell $sshl $sshl$libresoc.v:126546$4947 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196853,10 +199285,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:124828$4902_Y + connect \Y $sshl$libresoc.v:126546$4947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" - cell $sshl $sshl$libresoc.v:124829$4903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:126547$4948 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196864,28 +199296,28 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:124829$4903_Y + connect \Y $sshl$libresoc.v:126547$4948_Y end - attribute \src "libresoc.v:124744.7-124744.20" - process $proc$libresoc.v:124744$4914 + attribute \src "libresoc.v:126462.7-126462.20" + process $proc$libresoc.v:126462$4959 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124832.3-124878.6" - process $proc$libresoc.v:124832$4906 + attribute \src "libresoc.v:126550.3-126596.6" + process $proc$libresoc.v:126550$4951 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:124833.5-124833.29" + attribute \src "libresoc.v:126551.5-126551.29" switch \initial - attribute \src "libresoc.v:124833.9-124833.17" + attribute \src "libresoc.v:126551.9-126551.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196933,18 +199365,18 @@ module \dec_bi$170 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:124879.3-124925.6" - process $proc$libresoc.v:124879$4907 + attribute \src "libresoc.v:126597.3-126643.6" + process $proc$libresoc.v:126597$4952 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124880.5-124880.29" + attribute \src "libresoc.v:126598.5-126598.29" switch \initial - attribute \src "libresoc.v:124880.9-124880.17" + attribute \src "libresoc.v:126598.9-126598.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196992,18 +199424,18 @@ module \dec_bi$170 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:124926.3-124936.6" - process $proc$libresoc.v:124926$4908 + attribute \src "libresoc.v:126644.3-126654.6" + process $proc$libresoc.v:126644$4953 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:124927.5-124927.29" + attribute \src "libresoc.v:126645.5-126645.29" switch \initial - attribute \src "libresoc.v:124927.9-124927.17" + attribute \src "libresoc.v:126645.9-126645.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -197015,18 +199447,18 @@ module \dec_bi$170 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:124937.3-124947.6" - process $proc$libresoc.v:124937$4909 + attribute \src "libresoc.v:126655.3-126665.6" + process $proc$libresoc.v:126655$4954 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:124938.5-124938.29" + attribute \src "libresoc.v:126656.5-126656.29" switch \initial - attribute \src "libresoc.v:124938.9-124938.17" + attribute \src "libresoc.v:126656.9-126656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -197038,18 +199470,18 @@ module \dec_bi$170 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:124948.3-124958.6" - process $proc$libresoc.v:124948$4910 + attribute \src "libresoc.v:126666.3-126676.6" + process $proc$libresoc.v:126666$4955 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:124949.5-124949.29" + attribute \src "libresoc.v:126667.5-126667.29" switch \initial - attribute \src "libresoc.v:124949.9-124949.17" + attribute \src "libresoc.v:126667.9-126667.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -197061,18 +199493,18 @@ module \dec_bi$170 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:124959.3-124969.6" - process $proc$libresoc.v:124959$4911 + attribute \src "libresoc.v:126677.3-126687.6" + process $proc$libresoc.v:126677$4956 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:124960.5-124960.29" + attribute \src "libresoc.v:126678.5-126678.29" switch \initial - attribute \src "libresoc.v:124960.9-124960.17" + attribute \src "libresoc.v:126678.9-126678.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -197084,18 +199516,18 @@ module \dec_bi$170 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:124970.3-124980.6" - process $proc$libresoc.v:124970$4912 + attribute \src "libresoc.v:126688.3-126698.6" + process $proc$libresoc.v:126688$4957 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:124971.5-124971.29" + attribute \src "libresoc.v:126689.5-126689.29" switch \initial - attribute \src "libresoc.v:124971.9-124971.17" + attribute \src "libresoc.v:126689.9-126689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -197107,18 +199539,18 @@ module \dec_bi$170 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:124981.3-124991.6" - process $proc$libresoc.v:124981$4913 + attribute \src "libresoc.v:126699.3-126709.6" + process $proc$libresoc.v:126699$4958 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:124982.5-124982.29" + attribute \src "libresoc.v:126700.5-126700.29" switch \initial - attribute \src "libresoc.v:124982.9-124982.17" + attribute \src "libresoc.v:126700.9-126700.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -197130,41 +199562,41 @@ module \dec_bi$170 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124822$4894_Y - connect \$11 $pos$libresoc.v:124823$4896_Y - connect \$14 $sshl$libresoc.v:124824$4897_Y - connect \$17 $sshl$libresoc.v:124825$4898_Y - connect \$1 $pos$libresoc.v:124826$4900_Y - connect \$20 $sshl$libresoc.v:124827$4901_Y - connect \$23 $sshl$libresoc.v:124828$4902_Y - connect \$4 $sshl$libresoc.v:124829$4903_Y - connect \$3 $pos$libresoc.v:124830$4905_Y + connect \$9 $pos$libresoc.v:126540$4939_Y + connect \$11 $pos$libresoc.v:126541$4941_Y + connect \$14 $sshl$libresoc.v:126542$4942_Y + connect \$17 $sshl$libresoc.v:126543$4943_Y + connect \$1 $pos$libresoc.v:126544$4945_Y + connect \$20 $sshl$libresoc.v:126545$4946_Y + connect \$23 $sshl$libresoc.v:126546$4947_Y + connect \$4 $sshl$libresoc.v:126547$4948_Y + connect \$3 $pos$libresoc.v:126548$4950_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125000.1-125048.10" +attribute \src "libresoc.v:126718.1-126766.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c - attribute \src "libresoc.v:125001.7-125001.20" + attribute \src "libresoc.v:126719.7-126719.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125018.3-125032.6" + attribute \src "libresoc.v:126736.3-126750.6" wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:125033.3-125047.6" + attribute \src "libresoc.v:126751.3-126765.6" wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:125018.3-125032.6" + attribute \src "libresoc.v:126736.3-126750.6" wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:125033.3-125047.6" + attribute \src "libresoc.v:126751.3-126765.6" wire $1\reg_c_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 4 \RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 3 \RS - attribute \src "libresoc.v:125001.7-125001.15" + attribute \src "libresoc.v:126719.7-126719.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 1 \reg_c @@ -197174,28 +199606,28 @@ module \dec_c attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:125001.7-125001.20" - process $proc$libresoc.v:125001$4917 + attribute \src "libresoc.v:126719.7-126719.20" + process $proc$libresoc.v:126719$4962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125018.3-125032.6" - process $proc$libresoc.v:125018$4915 + attribute \src "libresoc.v:126736.3-126750.6" + process $proc$libresoc.v:126736$4960 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:125019.5-125019.29" + attribute \src "libresoc.v:126737.5-126737.29" switch \initial - attribute \src "libresoc.v:125019.9-125019.17" + attribute \src "libresoc.v:126737.9-126737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -197211,18 +199643,18 @@ module \dec_c sync always update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:125033.3-125047.6" - process $proc$libresoc.v:125033$4916 + attribute \src "libresoc.v:126751.3-126765.6" + process $proc$libresoc.v:126751$4961 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:125034.5-125034.29" + attribute \src "libresoc.v:126752.5-126752.29" switch \initial - attribute \src "libresoc.v:125034.9-125034.17" + attribute \src "libresoc.v:126752.9-126752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -197239,76 +199671,76 @@ module \dec_c update \reg_c_ok $0\reg_c_ok[0:0] end end -attribute \src "libresoc.v:125052.1-125383.10" +attribute \src "libresoc.v:126770.1-127102.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in - attribute \src "libresoc.v:125303.3-125333.6" + attribute \src "libresoc.v:127022.3-127052.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:125334.3-125344.6" + attribute \src "libresoc.v:127053.3-127063.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:125236.3-125246.6" + attribute \src "libresoc.v:126955.3-126965.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:125345.3-125355.6" + attribute \src "libresoc.v:127064.3-127074.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:125266.3-125276.6" + attribute \src "libresoc.v:126985.3-126995.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:125205.3-125235.6" + attribute \src "libresoc.v:126924.3-126954.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:125247.3-125265.6" + attribute \src "libresoc.v:126966.3-126984.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:125277.3-125287.6" + attribute \src "libresoc.v:126996.3-127006.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:125053.7-125053.20" + attribute \src "libresoc.v:126771.7-126771.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125356.3-125366.6" + attribute \src "libresoc.v:127075.3-127085.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:125367.3-125382.6" + attribute \src "libresoc.v:127086.3-127101.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:125288.3-125302.6" + attribute \src "libresoc.v:127007.3-127021.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:125303.3-125333.6" + attribute \src "libresoc.v:127022.3-127052.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:125334.3-125344.6" + attribute \src "libresoc.v:127053.3-127063.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:125236.3-125246.6" + attribute \src "libresoc.v:126955.3-126965.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:125345.3-125355.6" + attribute \src "libresoc.v:127064.3-127074.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:125266.3-125276.6" + attribute \src "libresoc.v:126985.3-126995.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:125205.3-125235.6" + attribute \src "libresoc.v:126924.3-126954.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:125247.3-125265.6" + attribute \src "libresoc.v:126966.3-126984.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:125277.3-125287.6" + attribute \src "libresoc.v:126996.3-127006.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:125356.3-125366.6" + attribute \src "libresoc.v:127075.3-127085.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:125367.3-125382.6" + attribute \src "libresoc.v:127086.3-127101.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:125288.3-125302.6" + attribute \src "libresoc.v:127007.3-127021.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:125247.3-125265.6" + attribute \src "libresoc.v:126966.3-126984.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:125367.3-125382.6" + attribute \src "libresoc.v:127086.3-127101.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:125198.17-125198.112" - wire $and$libresoc.v:125198$4919_Y - attribute \src "libresoc.v:125200.17-125200.112" - wire $and$libresoc.v:125200$4921_Y - attribute \src "libresoc.v:125197.17-125197.117" - wire $eq$libresoc.v:125197$4918_Y - attribute \src "libresoc.v:125199.17-125199.117" - wire $eq$libresoc.v:125199$4920_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "libresoc.v:126917.17-126917.112" + wire $and$libresoc.v:126917$4964_Y + attribute \src "libresoc.v:126919.17-126919.112" + wire $and$libresoc.v:126919$4966_Y + attribute \src "libresoc.v:126916.17-126916.117" + wire $eq$libresoc.v:126916$4963_Y + attribute \src "libresoc.v:126918.17-126918.117" + wire $eq$libresoc.v:126918$4965_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 12 \BA @@ -197340,9 +199772,9 @@ module \dec_cr_in wire width 8 output 3 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:125053.7-125053.15" + attribute \src "libresoc.v:126771.7-126771.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -197418,9 +199850,10 @@ module \dec_cr_in attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 18 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i @@ -197435,12 +199868,12 @@ module \dec_cr_in attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:516" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" wire width 2 \sv_override - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - cell $and $and$libresoc.v:125198$4919 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + cell $and $and$libresoc.v:126917$4964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197448,10 +199881,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:125198$4919_Y + connect \Y $and$libresoc.v:126917$4964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - cell $and $and$libresoc.v:125200$4921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + cell $and $and$libresoc.v:126919$4966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197459,10 +199892,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:125200$4921_Y + connect \Y $and$libresoc.v:126919$4966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - cell $eq $eq$libresoc.v:125197$4918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + cell $eq $eq$libresoc.v:126916$4963 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -197470,10 +199903,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:125197$4918_Y + connect \Y $eq$libresoc.v:126916$4963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - cell $eq $eq$libresoc.v:125199$4920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + cell $eq $eq$libresoc.v:126918$4965 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -197481,34 +199914,34 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:125199$4920_Y + connect \Y $eq$libresoc.v:126918$4965_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:125201.9-125204.4" + attribute \src "libresoc.v:126920.9-126923.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:125053.7-125053.20" - process $proc$libresoc.v:125053$4933 + attribute \src "libresoc.v:126771.7-126771.20" + process $proc$libresoc.v:126771$4978 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125205.3-125235.6" - process $proc$libresoc.v:125205$4922 + attribute \src "libresoc.v:126924.3-126954.6" + process $proc$libresoc.v:126924$4967 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:125206.5-125206.29" + attribute \src "libresoc.v:126925.5-126925.29" switch \initial - attribute \src "libresoc.v:125206.9-125206.17" + attribute \src "libresoc.v:126925.9-126925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -197540,18 +199973,18 @@ module \dec_cr_in sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:125236.3-125246.6" - process $proc$libresoc.v:125236$4923 + attribute \src "libresoc.v:126955.3-126965.6" + process $proc$libresoc.v:126955$4968 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:125237.5-125237.29" + attribute \src "libresoc.v:126956.5-126956.29" switch \initial - attribute \src "libresoc.v:125237.9-125237.17" + attribute \src "libresoc.v:126956.9-126956.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -197563,24 +199996,24 @@ module \dec_cr_in sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:125247.3-125265.6" - process $proc$libresoc.v:125247$4924 + attribute \src "libresoc.v:126966.3-126984.6" + process $proc$libresoc.v:126966$4969 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:125248.5-125248.29" + attribute \src "libresoc.v:126967.5-126967.29" switch \initial - attribute \src "libresoc.v:125248.9-125248.17" + attribute \src "libresoc.v:126967.9-126967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197597,18 +200030,18 @@ module \dec_cr_in sync always update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:125266.3-125276.6" - process $proc$libresoc.v:125266$4925 + attribute \src "libresoc.v:126985.3-126995.6" + process $proc$libresoc.v:126985$4970 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:125267.5-125267.29" + attribute \src "libresoc.v:126986.5-126986.29" switch \initial - attribute \src "libresoc.v:125267.9-125267.17" + attribute \src "libresoc.v:126986.9-126986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -197620,18 +200053,18 @@ module \dec_cr_in sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:125277.3-125287.6" - process $proc$libresoc.v:125277$4926 + attribute \src "libresoc.v:126996.3-127006.6" + process $proc$libresoc.v:126996$4971 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:125278.5-125278.29" + attribute \src "libresoc.v:126997.5-126997.29" switch \initial - attribute \src "libresoc.v:125278.9-125278.17" + attribute \src "libresoc.v:126997.9-126997.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -197643,18 +200076,18 @@ module \dec_cr_in sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:125288.3-125302.6" - process $proc$libresoc.v:125288$4927 + attribute \src "libresoc.v:127007.3-127021.6" + process $proc$libresoc.v:127007$4972 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:125289.5-125289.29" + attribute \src "libresoc.v:127008.5-127008.29" switch \initial - attribute \src "libresoc.v:125289.9-125289.17" + attribute \src "libresoc.v:127008.9-127008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -197670,18 +200103,18 @@ module \dec_cr_in sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:125303.3-125333.6" - process $proc$libresoc.v:125303$4928 + attribute \src "libresoc.v:127022.3-127052.6" + process $proc$libresoc.v:127022$4973 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:125304.5-125304.29" + attribute \src "libresoc.v:127023.5-127023.29" switch \initial - attribute \src "libresoc.v:125304.9-125304.17" + attribute \src "libresoc.v:127023.9-127023.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -197713,18 +200146,18 @@ module \dec_cr_in sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:125334.3-125344.6" - process $proc$libresoc.v:125334$4929 + attribute \src "libresoc.v:127053.3-127063.6" + process $proc$libresoc.v:127053$4974 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:125335.5-125335.29" + attribute \src "libresoc.v:127054.5-127054.29" switch \initial - attribute \src "libresoc.v:125335.9-125335.17" + attribute \src "libresoc.v:127054.9-127054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -197736,18 +200169,18 @@ module \dec_cr_in sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:125345.3-125355.6" - process $proc$libresoc.v:125345$4930 + attribute \src "libresoc.v:127064.3-127074.6" + process $proc$libresoc.v:127064$4975 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:125346.5-125346.29" + attribute \src "libresoc.v:127065.5-127065.29" switch \initial - attribute \src "libresoc.v:125346.9-125346.17" + attribute \src "libresoc.v:127065.9-127065.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -197759,18 +200192,18 @@ module \dec_cr_in sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:125356.3-125366.6" - process $proc$libresoc.v:125356$4931 + attribute \src "libresoc.v:127075.3-127085.6" + process $proc$libresoc.v:127075$4976 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:125357.5-125357.29" + attribute \src "libresoc.v:127076.5-127076.29" switch \initial - attribute \src "libresoc.v:125357.9-125357.17" + attribute \src "libresoc.v:127076.9-127076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -197782,24 +200215,24 @@ module \dec_cr_in sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:125367.3-125382.6" - process $proc$libresoc.v:125367$4932 + attribute \src "libresoc.v:127086.3-127101.6" + process $proc$libresoc.v:127086$4977 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:125368.5-125368.29" + attribute \src "libresoc.v:127087.5-127087.29" switch \initial - attribute \src "libresoc.v:125368.9-125368.17" + attribute \src "libresoc.v:127087.9-127087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197814,63 +200247,63 @@ module \dec_cr_in sync always update \ppick_i $0\ppick_i[7:0] end - connect \$1 $eq$libresoc.v:125197$4918_Y - connect \$3 $and$libresoc.v:125198$4919_Y - connect \$5 $eq$libresoc.v:125199$4920_Y - connect \$7 $and$libresoc.v:125200$4921_Y + connect \$1 $eq$libresoc.v:126916$4963_Y + connect \$3 $and$libresoc.v:126917$4964_Y + connect \$5 $eq$libresoc.v:126918$4965_Y + connect \$7 $and$libresoc.v:126919$4966_Y end -attribute \src "libresoc.v:125387.1-125656.10" +attribute \src "libresoc.v:127106.1-127376.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" module \dec_cr_out - attribute \src "libresoc.v:125566.3-125588.6" + attribute \src "libresoc.v:127286.3-127308.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:125517.3-125539.6" + attribute \src "libresoc.v:127237.3-127259.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:125621.3-125655.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:125540.3-125550.6" + attribute \src "libresoc.v:127260.3-127270.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:125388.7-125388.20" + attribute \src "libresoc.v:127107.7-127107.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125589.3-125599.6" + attribute \src "libresoc.v:127309.3-127319.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:125600.3-125620.6" + attribute \src "libresoc.v:127320.3-127340.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:125551.3-125565.6" + attribute \src "libresoc.v:127271.3-127285.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:125566.3-125588.6" + attribute \src "libresoc.v:127286.3-127308.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:125517.3-125539.6" + attribute \src "libresoc.v:127237.3-127259.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:125621.3-125655.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:125540.3-125550.6" + attribute \src "libresoc.v:127260.3-127270.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:125589.3-125599.6" + attribute \src "libresoc.v:127309.3-127319.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:125600.3-125620.6" + attribute \src "libresoc.v:127320.3-127340.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:125551.3-125565.6" + attribute \src "libresoc.v:127271.3-127285.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:125621.3-125655.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:125600.3-125620.6" + attribute \src "libresoc.v:127320.3-127340.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:125621.3-125655.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:125600.3-125620.6" + attribute \src "libresoc.v:127320.3-127340.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:125621.3-125655.6" + attribute \src "libresoc.v:127341.3-127375.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:125510.17-125510.117" - wire $eq$libresoc.v:125510$4934_Y - attribute \src "libresoc.v:125511.17-125511.117" - wire $eq$libresoc.v:125511$4935_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" + attribute \src "libresoc.v:127230.17-127230.117" + wire $eq$libresoc.v:127230$4979_Y + attribute \src "libresoc.v:127231.17-127231.117" + wire $eq$libresoc.v:127231$4980_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 8 input 8 \FXM @@ -197886,9 +200319,9 @@ module \dec_cr_out wire width 8 output 4 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:125388.7-125388.15" + attribute \src "libresoc.v:127107.7-127107.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -197964,9 +200397,10 @@ module \dec_cr_out attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 11 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:637" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \ppick_en_o @@ -197974,7 +200408,7 @@ module \dec_cr_out wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" wire input 3 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -197983,12 +200417,12 @@ module \dec_cr_out attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:591" - wire width 3 input 2 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:599" wire width 2 \sv_override - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" - cell $eq $eq$libresoc.v:125510$4934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + cell $eq $eq$libresoc.v:127230$4979 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -197996,10 +200430,10 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:125510$4934_Y + connect \Y $eq$libresoc.v:127230$4979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" - cell $eq $eq$libresoc.v:125511$4935 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + cell $eq $eq$libresoc.v:127231$4980 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -198007,35 +200441,35 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:125511$4935_Y + connect \Y $eq$libresoc.v:127231$4980_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:125512.15-125516.4" + attribute \src "libresoc.v:127232.15-127236.4" cell \ppick$175 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:125388.7-125388.20" - process $proc$libresoc.v:125388$4943 + attribute \src "libresoc.v:127107.7-127107.20" + process $proc$libresoc.v:127107$4988 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125517.3-125539.6" - process $proc$libresoc.v:125517$4936 + attribute \src "libresoc.v:127237.3-127259.6" + process $proc$libresoc.v:127237$4981 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:125518.5-125518.29" + attribute \src "libresoc.v:127238.5-127238.29" switch \initial - attribute \src "libresoc.v:125518.9-125518.17" + attribute \src "libresoc.v:127238.9-127238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -198059,18 +200493,18 @@ module \dec_cr_out sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:125540.3-125550.6" - process $proc$libresoc.v:125540$4937 + attribute \src "libresoc.v:127260.3-127270.6" + process $proc$libresoc.v:127260$4982 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:125541.5-125541.29" + attribute \src "libresoc.v:127261.5-127261.29" switch \initial - attribute \src "libresoc.v:125541.9-125541.17" + attribute \src "libresoc.v:127261.9-127261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -198082,18 +200516,18 @@ module \dec_cr_out sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:125551.3-125565.6" - process $proc$libresoc.v:125551$4938 + attribute \src "libresoc.v:127271.3-127285.6" + process $proc$libresoc.v:127271$4983 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:125552.5-125552.29" + attribute \src "libresoc.v:127272.5-127272.29" switch \initial - attribute \src "libresoc.v:125552.9-125552.17" + attribute \src "libresoc.v:127272.9-127272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -198109,18 +200543,18 @@ module \dec_cr_out sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:125566.3-125588.6" - process $proc$libresoc.v:125566$4939 + attribute \src "libresoc.v:127286.3-127308.6" + process $proc$libresoc.v:127286$4984 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:125567.5-125567.29" + attribute \src "libresoc.v:127287.5-127287.29" switch \initial - attribute \src "libresoc.v:125567.9-125567.17" + attribute \src "libresoc.v:127287.9-127287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -198144,18 +200578,18 @@ module \dec_cr_out sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:125589.3-125599.6" - process $proc$libresoc.v:125589$4940 + attribute \src "libresoc.v:127309.3-127319.6" + process $proc$libresoc.v:127309$4985 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:125590.5-125590.29" + attribute \src "libresoc.v:127310.5-127310.29" switch \initial - attribute \src "libresoc.v:125590.9-125590.17" + attribute \src "libresoc.v:127310.9-127310.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -198167,30 +200601,30 @@ module \dec_cr_out sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:125600.3-125620.6" - process $proc$libresoc.v:125600$4941 + attribute \src "libresoc.v:127320.3-127340.6" + process $proc$libresoc.v:127320$4986 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:125601.5-125601.29" + attribute \src "libresoc.v:127321.5-127321.29" switch \initial - attribute \src "libresoc.v:125601.9-125601.17" + attribute \src "libresoc.v:127321.9-127321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -198208,36 +200642,36 @@ module \dec_cr_out sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:125621.3-125655.6" - process $proc$libresoc.v:125621$4942 + attribute \src "libresoc.v:127341.3-127375.6" + process $proc$libresoc.v:127341$4987 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:125622.5-125622.29" + attribute \src "libresoc.v:127342.5-127342.29" switch \initial - attribute \src "libresoc.v:125622.9-125622.17" + attribute \src "libresoc.v:127342.9-127342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -198264,81 +200698,81 @@ module \dec_cr_out sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:125510$4934_Y - connect \$3 $eq$libresoc.v:125511$4935_Y + connect \$1 $eq$libresoc.v:127230$4979_Y + connect \$3 $eq$libresoc.v:127231$4980_Y end -attribute \src "libresoc.v:125660.1-126143.10" +attribute \src "libresoc.v:127380.1-127865.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:125661.7-125661.20" + attribute \src "libresoc.v:127381.7-127381.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126030.3-126044.6" + attribute \src "libresoc.v:127752.3-127766.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:126045.3-126059.6" + attribute \src "libresoc.v:127767.3-127781.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:126060.3-126070.6" + attribute \src "libresoc.v:127782.3-127792.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:126087.3-126103.6" + attribute \src "libresoc.v:127809.3-127825.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:126087.3-126103.6" + attribute \src "libresoc.v:127809.3-127825.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:126071.3-126086.6" + attribute \src "libresoc.v:127793.3-127808.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:126030.3-126044.6" + attribute \src "libresoc.v:127752.3-127766.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:126045.3-126059.6" + attribute \src "libresoc.v:127767.3-127781.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:126060.3-126070.6" + attribute \src "libresoc.v:127782.3-127792.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:126087.3-126103.6" + attribute \src "libresoc.v:127809.3-127825.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:126087.3-126103.6" + attribute \src "libresoc.v:127809.3-127825.6" wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:126071.3-126086.6" + attribute \src "libresoc.v:127793.3-127808.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:126087.3-126103.6" + attribute \src "libresoc.v:127809.3-127825.6" wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:126087.3-126103.6" + attribute \src "libresoc.v:127809.3-127825.6" wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:126071.3-126086.6" + attribute \src "libresoc.v:127793.3-127808.6" wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:126104.3-126142.6" + attribute \src "libresoc.v:127826.3-127864.6" wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:126019.17-126019.117" - wire $eq$libresoc.v:126019$4944_Y - attribute \src "libresoc.v:126020.17-126020.117" - wire $eq$libresoc.v:126020$4945_Y - attribute \src "libresoc.v:126021.17-126021.117" - wire $eq$libresoc.v:126021$4946_Y - attribute \src "libresoc.v:126022.17-126022.104" - wire $not$libresoc.v:126022$4947_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "libresoc.v:127741.17-127741.117" + wire $eq$libresoc.v:127741$4989_Y + attribute \src "libresoc.v:127742.17-127742.117" + wire $eq$libresoc.v:127742$4990_Y + attribute \src "libresoc.v:127743.17-127743.117" + wire $eq$libresoc.v:127743$4991_Y + attribute \src "libresoc.v:127744.17-127744.104" + wire $not$libresoc.v:127744$4992_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 11 \BO @@ -198352,7 +200786,7 @@ module \dec_o wire width 3 output 7 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 8 \fast_o_ok - attribute \src "libresoc.v:125661.7-125661.15" + attribute \src "libresoc.v:127381.7-127381.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -198428,6 +200862,7 @@ module \dec_o attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 12 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -198435,13 +200870,14 @@ module \dec_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \reg_o_ok attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - wire width 2 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RT" + attribute \enum_value_010 "RA" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RT_OR_ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -198685,8 +201121,8 @@ module \dec_o wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" - cell $eq $eq$libresoc.v:126019$4944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + cell $eq $eq$libresoc.v:127741$4989 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -198694,10 +201130,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:126019$4944_Y + connect \Y $eq$libresoc.v:127741$4989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" - cell $eq $eq$libresoc.v:126020$4945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + cell $eq $eq$libresoc.v:127742$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -198705,10 +201141,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:126020$4945_Y + connect \Y $eq$libresoc.v:127742$4990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" - cell $eq $eq$libresoc.v:126021$4946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + cell $eq $eq$libresoc.v:127743$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -198716,18 +201152,18 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:126021$4946_Y + connect \Y $eq$libresoc.v:127743$4991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" - cell $not $not$libresoc.v:126022$4947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + cell $not $not$libresoc.v:127744$4992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:126022$4947_Y + connect \Y $not$libresoc.v:127744$4992_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:126023.16-126029.4" + attribute \src "libresoc.v:127745.16-127751.4" cell \sprmap$174 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -198735,33 +201171,33 @@ module \dec_o connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:125661.7-125661.20" - process $proc$libresoc.v:125661$4954 + attribute \src "libresoc.v:127381.7-127381.20" + process $proc$libresoc.v:127381$4999 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126030.3-126044.6" - process $proc$libresoc.v:126030$4948 + attribute \src "libresoc.v:127752.3-127766.6" + process $proc$libresoc.v:127752$4993 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:126031.5-126031.29" + attribute \src "libresoc.v:127753.5-127753.29" switch \initial - attribute \src "libresoc.v:126031.9-126031.17" + attribute \src "libresoc.v:127753.9-127753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'001 assign { } { } assign $1\reg_o[4:0] \RT attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 3'010 assign { } { } assign $1\reg_o[4:0] \RA case @@ -198770,25 +201206,25 @@ module \dec_o sync always update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:126045.3-126059.6" - process $proc$libresoc.v:126045$4949 + attribute \src "libresoc.v:127767.3-127781.6" + process $proc$libresoc.v:127767$4994 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:126046.5-126046.29" + attribute \src "libresoc.v:127768.5-127768.29" switch \initial - attribute \src "libresoc.v:126046.9-126046.17" + attribute \src "libresoc.v:127768.9-127768.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'001 assign { } { } assign $1\reg_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 3'010 assign { } { } assign $1\reg_o_ok[0:0] 1'1 case @@ -198797,21 +201233,21 @@ module \dec_o sync always update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:126060.3-126070.6" - process $proc$libresoc.v:126060$4950 + attribute \src "libresoc.v:127782.3-127792.6" + process $proc$libresoc.v:127782$4995 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:126061.5-126061.29" + attribute \src "libresoc.v:127783.5-127783.29" switch \initial - attribute \src "libresoc.v:126061.9-126061.17" + attribute \src "libresoc.v:127783.9-127783.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 assign { } { } assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case @@ -198820,24 +201256,24 @@ module \dec_o sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:126071.3-126086.6" - process $proc$libresoc.v:126071$4951 + attribute \src "libresoc.v:127793.3-127808.6" + process $proc$libresoc.v:127793$4996 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126072.5-126072.29" + attribute \src "libresoc.v:127794.5-127794.29" switch \initial - attribute \src "libresoc.v:126072.9-126072.17" + attribute \src "libresoc.v:127794.9-127794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 assign { } { } assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -198852,29 +201288,29 @@ module \dec_o sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:126087.3-126103.6" - process $proc$libresoc.v:126087$4952 + attribute \src "libresoc.v:127809.3-127825.6" + process $proc$libresoc.v:127809$4997 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:126088.5-126088.29" + attribute \src "libresoc.v:127810.5-127810.29" switch \initial - attribute \src "libresoc.v:126088.9-126088.17" + attribute \src "libresoc.v:127810.9-127810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 assign { } { } assign { } { } assign $1\spr_o[9:0] $2\spr_o[9:0] assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -198893,8 +201329,8 @@ module \dec_o update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:126104.3-126142.6" - process $proc$libresoc.v:126104$4953 + attribute \src "libresoc.v:127826.3-127864.6" + process $proc$libresoc.v:127826$4998 assign { } { } assign { } { } assign { } { } @@ -198903,21 +201339,21 @@ module \dec_o assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:126105.5-126105.29" + attribute \src "libresoc.v:127827.5-127827.29" switch \initial - attribute \src "libresoc.v:126105.9-126105.17" + attribute \src "libresoc.v:127827.9-127827.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'011 assign { } { } assign { } { } assign $1\fast_o[2:0] $2\fast_o[2:0] assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -198932,7 +201368,7 @@ module \dec_o assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:356" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0001000 @@ -198940,7 +201376,7 @@ module \dec_o assign { } { } assign $3\fast_o[2:0] $4\fast_o[2:0] assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -198966,45 +201402,45 @@ module \dec_o update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:126019$4944_Y - connect \$3 $eq$libresoc.v:126020$4945_Y - connect \$5 $eq$libresoc.v:126021$4946_Y - connect \$7 $not$libresoc.v:126022$4947_Y + connect \$1 $eq$libresoc.v:127741$4989_Y + connect \$3 $eq$libresoc.v:127742$4990_Y + connect \$5 $eq$libresoc.v:127743$4991_Y + connect \$7 $not$libresoc.v:127744$4992_Y end -attribute \src "libresoc.v:126147.1-126314.10" +attribute \src "libresoc.v:127869.1-128037.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 - attribute \src "libresoc.v:126274.3-126293.6" + attribute \src "libresoc.v:127997.3-128016.6" wire width 3 $0\fast_o2[2:0] - attribute \src "libresoc.v:126294.3-126313.6" + attribute \src "libresoc.v:128017.3-128036.6" wire $0\fast_o2_ok[0:0] - attribute \src "libresoc.v:126148.7-126148.20" + attribute \src "libresoc.v:127870.7-127870.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126254.3-126263.6" + attribute \src "libresoc.v:127977.3-127986.6" wire width 5 $0\reg_o2[4:0] - attribute \src "libresoc.v:126264.3-126273.6" + attribute \src "libresoc.v:127987.3-127996.6" wire $0\reg_o2_ok[0:0] - attribute \src "libresoc.v:126274.3-126293.6" + attribute \src "libresoc.v:127997.3-128016.6" wire width 3 $1\fast_o2[2:0] - attribute \src "libresoc.v:126294.3-126313.6" + attribute \src "libresoc.v:128017.3-128036.6" wire $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:126254.3-126263.6" + attribute \src "libresoc.v:127977.3-127986.6" wire width 5 $1\reg_o2[4:0] - attribute \src "libresoc.v:126264.3-126273.6" + attribute \src "libresoc.v:127987.3-127996.6" wire $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:126274.3-126293.6" + attribute \src "libresoc.v:127997.3-128016.6" wire width 3 $2\fast_o2[2:0] - attribute \src "libresoc.v:126294.3-126313.6" + attribute \src "libresoc.v:128017.3-128036.6" wire $2\fast_o2_ok[0:0] - attribute \src "libresoc.v:126252.17-126252.108" - wire $eq$libresoc.v:126252$4955_Y - attribute \src "libresoc.v:126253.17-126253.108" - wire $eq$libresoc.v:126253$4956_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "libresoc.v:127975.17-127975.108" + wire $eq$libresoc.v:127975$5000_Y + attribute \src "libresoc.v:127976.17-127976.108" + wire $eq$libresoc.v:127976$5001_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 7 \RA @@ -199012,7 +201448,7 @@ module \dec_o2 wire width 3 output 4 \fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_o2_ok - attribute \src "libresoc.v:126148.7-126148.15" + attribute \src "libresoc.v:127870.7-127870.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -199088,9 +201524,10 @@ module \dec_o2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" wire input 1 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 2 \reg_o2 @@ -199103,8 +201540,8 @@ module \dec_o2 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" - cell $eq $eq$libresoc.v:126252$4955 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + cell $eq $eq$libresoc.v:127975$5000 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -199112,10 +201549,10 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:126252$4955_Y + connect \Y $eq$libresoc.v:127975$5000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" - cell $eq $eq$libresoc.v:126253$4956 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + cell $eq $eq$libresoc.v:127976$5001 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -199123,28 +201560,28 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:126253$4956_Y + connect \Y $eq$libresoc.v:127976$5001_Y end - attribute \src "libresoc.v:126148.7-126148.20" - process $proc$libresoc.v:126148$4961 + attribute \src "libresoc.v:127870.7-127870.20" + process $proc$libresoc.v:127870$5006 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126254.3-126263.6" - process $proc$libresoc.v:126254$4957 + attribute \src "libresoc.v:127977.3-127986.6" + process $proc$libresoc.v:127977$5002 assign { } { } assign { } { } assign $0\reg_o2[4:0] $1\reg_o2[4:0] - attribute \src "libresoc.v:126255.5-126255.29" + attribute \src "libresoc.v:127978.5-127978.29" switch \initial - attribute \src "libresoc.v:126255.9-126255.17" + attribute \src "libresoc.v:127978.9-127978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -199156,18 +201593,18 @@ module \dec_o2 sync always update \reg_o2 $0\reg_o2[4:0] end - attribute \src "libresoc.v:126264.3-126273.6" - process $proc$libresoc.v:126264$4958 + attribute \src "libresoc.v:127987.3-127996.6" + process $proc$libresoc.v:127987$5003 assign { } { } assign { } { } assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:126265.5-126265.29" + attribute \src "libresoc.v:127988.5-127988.29" switch \initial - attribute \src "libresoc.v:126265.9-126265.17" + attribute \src "libresoc.v:127988.9-127988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -199179,24 +201616,24 @@ module \dec_o2 sync always update \reg_o2_ok $0\reg_o2_ok[0:0] end - attribute \src "libresoc.v:126274.3-126293.6" - process $proc$libresoc.v:126274$4959 + attribute \src "libresoc.v:127997.3-128016.6" + process $proc$libresoc.v:127997$5004 assign { } { } assign { } { } assign $0\fast_o2[2:0] $1\fast_o2[2:0] - attribute \src "libresoc.v:126275.5-126275.29" + attribute \src "libresoc.v:127998.5-127998.29" switch \initial - attribute \src "libresoc.v:126275.9-126275.17" + attribute \src "libresoc.v:127998.9-127998.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2[2:0] $2\fast_o2[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -199215,24 +201652,24 @@ module \dec_o2 sync always update \fast_o2 $0\fast_o2[2:0] end - attribute \src "libresoc.v:126294.3-126313.6" - process $proc$libresoc.v:126294$4960 + attribute \src "libresoc.v:128017.3-128036.6" + process $proc$libresoc.v:128017$5005 assign { } { } assign { } { } assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:126295.5-126295.29" + attribute \src "libresoc.v:128018.5-128018.29" switch \initial - attribute \src "libresoc.v:126295.9-126295.17" + attribute \src "libresoc.v:128018.9-128018.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:412" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -199251,27 +201688,27 @@ module \dec_o2 sync always update \fast_o2_ok $0\fast_o2_ok[0:0] end - connect \$1 $eq$libresoc.v:126252$4955_Y - connect \$3 $eq$libresoc.v:126253$4956_Y + connect \$1 $eq$libresoc.v:127975$5000_Y + connect \$3 $eq$libresoc.v:127976$5001_Y end -attribute \src "libresoc.v:126318.1-126452.10" +attribute \src "libresoc.v:128041.1-128176.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe - attribute \src "libresoc.v:126319.7-126319.20" + attribute \src "libresoc.v:128042.7-128042.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126410.3-126430.6" + attribute \src "libresoc.v:128134.3-128154.6" wire $0\oe[0:0] - attribute \src "libresoc.v:126431.3-126451.6" + attribute \src "libresoc.v:128155.3-128175.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:126410.3-126430.6" + attribute \src "libresoc.v:128134.3-128154.6" wire $1\oe[0:0] - attribute \src "libresoc.v:126431.3-126451.6" + attribute \src "libresoc.v:128155.3-128175.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:126410.3-126430.6" + attribute \src "libresoc.v:128134.3-128154.6" wire $2\oe[0:0] - attribute \src "libresoc.v:126431.3-126451.6" + attribute \src "libresoc.v:128155.3-128175.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \ALU_OE @@ -199349,9 +201786,10 @@ module \dec_oe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:126319.7-126319.15" + attribute \src "libresoc.v:128042.7-128042.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -199361,28 +201799,28 @@ module \dec_oe attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:126319.7-126319.20" - process $proc$libresoc.v:126319$4964 + attribute \src "libresoc.v:128042.7-128042.20" + process $proc$libresoc.v:128042$5009 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126410.3-126430.6" - process $proc$libresoc.v:126410$4962 + attribute \src "libresoc.v:128134.3-128154.6" + process $proc$libresoc.v:128134$5007 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:126411.5-126411.29" + attribute \src "libresoc.v:128135.5-128135.29" switch \initial - attribute \src "libresoc.v:126411.9-126411.17" + attribute \src "libresoc.v:128135.9-128135.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -199391,7 +201829,7 @@ module \dec_oe case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199404,18 +201842,18 @@ module \dec_oe sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:126431.3-126451.6" - process $proc$libresoc.v:126431$4963 + attribute \src "libresoc.v:128155.3-128175.6" + process $proc$libresoc.v:128155$5008 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:126432.5-126432.29" + attribute \src "libresoc.v:128156.5-128156.29" switch \initial - attribute \src "libresoc.v:126432.9-126432.17" + attribute \src "libresoc.v:128156.9-128156.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -199424,7 +201862,7 @@ module \dec_oe case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199438,24 +201876,24 @@ module \dec_oe update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:126456.1-126588.10" +attribute \src "libresoc.v:128180.1-128313.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" module \dec_oe$140 - attribute \src "libresoc.v:126457.7-126457.20" + attribute \src "libresoc.v:128181.7-128181.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126546.3-126566.6" + attribute \src "libresoc.v:128271.3-128291.6" wire $0\oe[0:0] - attribute \src "libresoc.v:126567.3-126587.6" + attribute \src "libresoc.v:128292.3-128312.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:126546.3-126566.6" + attribute \src "libresoc.v:128271.3-128291.6" wire $1\oe[0:0] - attribute \src "libresoc.v:126567.3-126587.6" + attribute \src "libresoc.v:128292.3-128312.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:126546.3-126566.6" + attribute \src "libresoc.v:128271.3-128291.6" wire $2\oe[0:0] - attribute \src "libresoc.v:126567.3-126587.6" + attribute \src "libresoc.v:128292.3-128312.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 2 \CR_OE @@ -199533,9 +201971,10 @@ module \dec_oe$140 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:126457.7-126457.15" + attribute \src "libresoc.v:128181.7-128181.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -199545,28 +201984,28 @@ module \dec_oe$140 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:126457.7-126457.20" - process $proc$libresoc.v:126457$4967 + attribute \src "libresoc.v:128181.7-128181.20" + process $proc$libresoc.v:128181$5012 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126546.3-126566.6" - process $proc$libresoc.v:126546$4965 + attribute \src "libresoc.v:128271.3-128291.6" + process $proc$libresoc.v:128271$5010 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:126547.5-126547.29" + attribute \src "libresoc.v:128272.5-128272.29" switch \initial - attribute \src "libresoc.v:126547.9-126547.17" + attribute \src "libresoc.v:128272.9-128272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -199575,7 +202014,7 @@ module \dec_oe$140 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199588,18 +202027,18 @@ module \dec_oe$140 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:126567.3-126587.6" - process $proc$libresoc.v:126567$4966 + attribute \src "libresoc.v:128292.3-128312.6" + process $proc$libresoc.v:128292$5011 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:126568.5-126568.29" + attribute \src "libresoc.v:128293.5-128293.29" switch \initial - attribute \src "libresoc.v:126568.9-126568.17" + attribute \src "libresoc.v:128293.9-128293.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -199608,7 +202047,7 @@ module \dec_oe$140 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199622,24 +202061,24 @@ module \dec_oe$140 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:126592.1-126724.10" +attribute \src "libresoc.v:128317.1-128450.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" module \dec_oe$143 - attribute \src "libresoc.v:126593.7-126593.20" + attribute \src "libresoc.v:128318.7-128318.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126682.3-126702.6" + attribute \src "libresoc.v:128408.3-128428.6" wire $0\oe[0:0] - attribute \src "libresoc.v:126703.3-126723.6" + attribute \src "libresoc.v:128429.3-128449.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:126682.3-126702.6" + attribute \src "libresoc.v:128408.3-128428.6" wire $1\oe[0:0] - attribute \src "libresoc.v:126703.3-126723.6" + attribute \src "libresoc.v:128429.3-128449.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:126682.3-126702.6" + attribute \src "libresoc.v:128408.3-128428.6" wire $2\oe[0:0] - attribute \src "libresoc.v:126703.3-126723.6" + attribute \src "libresoc.v:128429.3-128449.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 2 \BRANCH_OE @@ -199717,9 +202156,10 @@ module \dec_oe$143 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:126593.7-126593.15" + attribute \src "libresoc.v:128318.7-128318.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -199729,28 +202169,28 @@ module \dec_oe$143 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:126593.7-126593.20" - process $proc$libresoc.v:126593$4970 + attribute \src "libresoc.v:128318.7-128318.20" + process $proc$libresoc.v:128318$5015 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126682.3-126702.6" - process $proc$libresoc.v:126682$4968 + attribute \src "libresoc.v:128408.3-128428.6" + process $proc$libresoc.v:128408$5013 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:126683.5-126683.29" + attribute \src "libresoc.v:128409.5-128409.29" switch \initial - attribute \src "libresoc.v:126683.9-126683.17" + attribute \src "libresoc.v:128409.9-128409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -199759,7 +202199,7 @@ module \dec_oe$143 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199772,18 +202212,18 @@ module \dec_oe$143 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:126703.3-126723.6" - process $proc$libresoc.v:126703$4969 + attribute \src "libresoc.v:128429.3-128449.6" + process $proc$libresoc.v:128429$5014 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:126704.5-126704.29" + attribute \src "libresoc.v:128430.5-128430.29" switch \initial - attribute \src "libresoc.v:126704.9-126704.17" + attribute \src "libresoc.v:128430.9-128430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -199792,7 +202232,7 @@ module \dec_oe$143 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199806,24 +202246,24 @@ module \dec_oe$143 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:126728.1-126862.10" +attribute \src "libresoc.v:128454.1-128589.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" module \dec_oe$147 - attribute \src "libresoc.v:126729.7-126729.20" + attribute \src "libresoc.v:128455.7-128455.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126820.3-126840.6" + attribute \src "libresoc.v:128547.3-128567.6" wire $0\oe[0:0] - attribute \src "libresoc.v:126841.3-126861.6" + attribute \src "libresoc.v:128568.3-128588.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:126820.3-126840.6" + attribute \src "libresoc.v:128547.3-128567.6" wire $1\oe[0:0] - attribute \src "libresoc.v:126841.3-126861.6" + attribute \src "libresoc.v:128568.3-128588.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:126820.3-126840.6" + attribute \src "libresoc.v:128547.3-128567.6" wire $2\oe[0:0] - attribute \src "libresoc.v:126841.3-126861.6" + attribute \src "libresoc.v:128568.3-128588.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \LOGICAL_OE @@ -199901,9 +202341,10 @@ module \dec_oe$147 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:126729.7-126729.15" + attribute \src "libresoc.v:128455.7-128455.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -199913,28 +202354,28 @@ module \dec_oe$147 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:126729.7-126729.20" - process $proc$libresoc.v:126729$4973 + attribute \src "libresoc.v:128455.7-128455.20" + process $proc$libresoc.v:128455$5018 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126820.3-126840.6" - process $proc$libresoc.v:126820$4971 + attribute \src "libresoc.v:128547.3-128567.6" + process $proc$libresoc.v:128547$5016 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:126821.5-126821.29" + attribute \src "libresoc.v:128548.5-128548.29" switch \initial - attribute \src "libresoc.v:126821.9-126821.17" + attribute \src "libresoc.v:128548.9-128548.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -199943,7 +202384,7 @@ module \dec_oe$147 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199956,18 +202397,18 @@ module \dec_oe$147 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:126841.3-126861.6" - process $proc$libresoc.v:126841$4972 + attribute \src "libresoc.v:128568.3-128588.6" + process $proc$libresoc.v:128568$5017 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:126842.5-126842.29" + attribute \src "libresoc.v:128569.5-128569.29" switch \initial - attribute \src "libresoc.v:126842.9-126842.17" + attribute \src "libresoc.v:128569.9-128569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -199976,7 +202417,7 @@ module \dec_oe$147 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199990,24 +202431,24 @@ module \dec_oe$147 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:126866.1-126998.10" +attribute \src "libresoc.v:128593.1-128726.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" module \dec_oe$152 - attribute \src "libresoc.v:126867.7-126867.20" + attribute \src "libresoc.v:128594.7-128594.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126956.3-126976.6" + attribute \src "libresoc.v:128684.3-128704.6" wire $0\oe[0:0] - attribute \src "libresoc.v:126977.3-126997.6" + attribute \src "libresoc.v:128705.3-128725.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:126956.3-126976.6" + attribute \src "libresoc.v:128684.3-128704.6" wire $1\oe[0:0] - attribute \src "libresoc.v:126977.3-126997.6" + attribute \src "libresoc.v:128705.3-128725.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:126956.3-126976.6" + attribute \src "libresoc.v:128684.3-128704.6" wire $2\oe[0:0] - attribute \src "libresoc.v:126977.3-126997.6" + attribute \src "libresoc.v:128705.3-128725.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 2 \SPR_OE @@ -200085,9 +202526,10 @@ module \dec_oe$152 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:126867.7-126867.15" + attribute \src "libresoc.v:128594.7-128594.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -200097,28 +202539,28 @@ module \dec_oe$152 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:126867.7-126867.20" - process $proc$libresoc.v:126867$4976 + attribute \src "libresoc.v:128594.7-128594.20" + process $proc$libresoc.v:128594$5021 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126956.3-126976.6" - process $proc$libresoc.v:126956$4974 + attribute \src "libresoc.v:128684.3-128704.6" + process $proc$libresoc.v:128684$5019 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:126957.5-126957.29" + attribute \src "libresoc.v:128685.5-128685.29" switch \initial - attribute \src "libresoc.v:126957.9-126957.17" + attribute \src "libresoc.v:128685.9-128685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200127,7 +202569,7 @@ module \dec_oe$152 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200140,18 +202582,18 @@ module \dec_oe$152 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:126977.3-126997.6" - process $proc$libresoc.v:126977$4975 + attribute \src "libresoc.v:128705.3-128725.6" + process $proc$libresoc.v:128705$5020 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:126978.5-126978.29" + attribute \src "libresoc.v:128706.5-128706.29" switch \initial - attribute \src "libresoc.v:126978.9-126978.17" + attribute \src "libresoc.v:128706.9-128706.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200160,7 +202602,7 @@ module \dec_oe$152 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200174,24 +202616,24 @@ module \dec_oe$152 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:127002.1-127136.10" +attribute \src "libresoc.v:128730.1-128865.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" module \dec_oe$155 - attribute \src "libresoc.v:127003.7-127003.20" + attribute \src "libresoc.v:128731.7-128731.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127094.3-127114.6" + attribute \src "libresoc.v:128823.3-128843.6" wire $0\oe[0:0] - attribute \src "libresoc.v:127115.3-127135.6" + attribute \src "libresoc.v:128844.3-128864.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:127094.3-127114.6" + attribute \src "libresoc.v:128823.3-128843.6" wire $1\oe[0:0] - attribute \src "libresoc.v:127115.3-127135.6" + attribute \src "libresoc.v:128844.3-128864.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:127094.3-127114.6" + attribute \src "libresoc.v:128823.3-128843.6" wire $2\oe[0:0] - attribute \src "libresoc.v:127115.3-127135.6" + attribute \src "libresoc.v:128844.3-128864.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \DIV_OE @@ -200269,9 +202711,10 @@ module \dec_oe$155 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:127003.7-127003.15" + attribute \src "libresoc.v:128731.7-128731.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -200281,28 +202724,28 @@ module \dec_oe$155 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:127003.7-127003.20" - process $proc$libresoc.v:127003$4979 + attribute \src "libresoc.v:128731.7-128731.20" + process $proc$libresoc.v:128731$5024 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127094.3-127114.6" - process $proc$libresoc.v:127094$4977 + attribute \src "libresoc.v:128823.3-128843.6" + process $proc$libresoc.v:128823$5022 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:127095.5-127095.29" + attribute \src "libresoc.v:128824.5-128824.29" switch \initial - attribute \src "libresoc.v:127095.9-127095.17" + attribute \src "libresoc.v:128824.9-128824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200311,7 +202754,7 @@ module \dec_oe$155 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200324,18 +202767,18 @@ module \dec_oe$155 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:127115.3-127135.6" - process $proc$libresoc.v:127115$4978 + attribute \src "libresoc.v:128844.3-128864.6" + process $proc$libresoc.v:128844$5023 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:127116.5-127116.29" + attribute \src "libresoc.v:128845.5-128845.29" switch \initial - attribute \src "libresoc.v:127116.9-127116.17" + attribute \src "libresoc.v:128845.9-128845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200344,7 +202787,7 @@ module \dec_oe$155 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200358,24 +202801,24 @@ module \dec_oe$155 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:127140.1-127274.10" +attribute \src "libresoc.v:128869.1-129004.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" module \dec_oe$160 - attribute \src "libresoc.v:127141.7-127141.20" + attribute \src "libresoc.v:128870.7-128870.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127232.3-127252.6" + attribute \src "libresoc.v:128962.3-128982.6" wire $0\oe[0:0] - attribute \src "libresoc.v:127253.3-127273.6" + attribute \src "libresoc.v:128983.3-129003.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:127232.3-127252.6" + attribute \src "libresoc.v:128962.3-128982.6" wire $1\oe[0:0] - attribute \src "libresoc.v:127253.3-127273.6" + attribute \src "libresoc.v:128983.3-129003.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:127232.3-127252.6" + attribute \src "libresoc.v:128962.3-128982.6" wire $2\oe[0:0] - attribute \src "libresoc.v:127253.3-127273.6" + attribute \src "libresoc.v:128983.3-129003.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \MUL_OE @@ -200453,9 +202896,10 @@ module \dec_oe$160 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:127141.7-127141.15" + attribute \src "libresoc.v:128870.7-128870.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -200465,28 +202909,28 @@ module \dec_oe$160 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:127141.7-127141.20" - process $proc$libresoc.v:127141$4982 + attribute \src "libresoc.v:128870.7-128870.20" + process $proc$libresoc.v:128870$5027 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127232.3-127252.6" - process $proc$libresoc.v:127232$4980 + attribute \src "libresoc.v:128962.3-128982.6" + process $proc$libresoc.v:128962$5025 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:127233.5-127233.29" + attribute \src "libresoc.v:128963.5-128963.29" switch \initial - attribute \src "libresoc.v:127233.9-127233.17" + attribute \src "libresoc.v:128963.9-128963.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200495,7 +202939,7 @@ module \dec_oe$160 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200508,18 +202952,18 @@ module \dec_oe$160 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:127253.3-127273.6" - process $proc$libresoc.v:127253$4981 + attribute \src "libresoc.v:128983.3-129003.6" + process $proc$libresoc.v:128983$5026 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:127254.5-127254.29" + attribute \src "libresoc.v:128984.5-128984.29" switch \initial - attribute \src "libresoc.v:127254.9-127254.17" + attribute \src "libresoc.v:128984.9-128984.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200528,7 +202972,7 @@ module \dec_oe$160 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200542,24 +202986,24 @@ module \dec_oe$160 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:127278.1-127412.10" +attribute \src "libresoc.v:129008.1-129143.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" module \dec_oe$164 - attribute \src "libresoc.v:127279.7-127279.20" + attribute \src "libresoc.v:129009.7-129009.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127370.3-127390.6" + attribute \src "libresoc.v:129101.3-129121.6" wire $0\oe[0:0] - attribute \src "libresoc.v:127391.3-127411.6" + attribute \src "libresoc.v:129122.3-129142.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:127370.3-127390.6" + attribute \src "libresoc.v:129101.3-129121.6" wire $1\oe[0:0] - attribute \src "libresoc.v:127391.3-127411.6" + attribute \src "libresoc.v:129122.3-129142.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:127370.3-127390.6" + attribute \src "libresoc.v:129101.3-129121.6" wire $2\oe[0:0] - attribute \src "libresoc.v:127391.3-127411.6" + attribute \src "libresoc.v:129122.3-129142.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \SHIFT_ROT_OE @@ -200637,9 +203081,10 @@ module \dec_oe$164 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:127279.7-127279.15" + attribute \src "libresoc.v:129009.7-129009.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -200649,28 +203094,28 @@ module \dec_oe$164 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:127279.7-127279.20" - process $proc$libresoc.v:127279$4985 + attribute \src "libresoc.v:129009.7-129009.20" + process $proc$libresoc.v:129009$5030 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127370.3-127390.6" - process $proc$libresoc.v:127370$4983 + attribute \src "libresoc.v:129101.3-129121.6" + process $proc$libresoc.v:129101$5028 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:127371.5-127371.29" + attribute \src "libresoc.v:129102.5-129102.29" switch \initial - attribute \src "libresoc.v:127371.9-127371.17" + attribute \src "libresoc.v:129102.9-129102.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200679,7 +203124,7 @@ module \dec_oe$164 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200692,18 +203137,18 @@ module \dec_oe$164 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:127391.3-127411.6" - process $proc$libresoc.v:127391$4984 + attribute \src "libresoc.v:129122.3-129142.6" + process $proc$libresoc.v:129122$5029 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:127392.5-127392.29" + attribute \src "libresoc.v:129123.5-129123.29" switch \initial - attribute \src "libresoc.v:127392.9-127392.17" + attribute \src "libresoc.v:129123.9-129123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200712,7 +203157,7 @@ module \dec_oe$164 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200726,24 +203171,24 @@ module \dec_oe$164 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:127416.1-127550.10" +attribute \src "libresoc.v:129147.1-129282.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" module \dec_oe$168 - attribute \src "libresoc.v:127417.7-127417.20" + attribute \src "libresoc.v:129148.7-129148.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127508.3-127528.6" + attribute \src "libresoc.v:129240.3-129260.6" wire $0\oe[0:0] - attribute \src "libresoc.v:127529.3-127549.6" + attribute \src "libresoc.v:129261.3-129281.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:127508.3-127528.6" + attribute \src "libresoc.v:129240.3-129260.6" wire $1\oe[0:0] - attribute \src "libresoc.v:127529.3-127549.6" + attribute \src "libresoc.v:129261.3-129281.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:127508.3-127528.6" + attribute \src "libresoc.v:129240.3-129260.6" wire $2\oe[0:0] - attribute \src "libresoc.v:127529.3-127549.6" + attribute \src "libresoc.v:129261.3-129281.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \LDST_OE @@ -200821,9 +203266,10 @@ module \dec_oe$168 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:127417.7-127417.15" + attribute \src "libresoc.v:129148.7-129148.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -200833,28 +203279,28 @@ module \dec_oe$168 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:127417.7-127417.20" - process $proc$libresoc.v:127417$4988 + attribute \src "libresoc.v:129148.7-129148.20" + process $proc$libresoc.v:129148$5033 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127508.3-127528.6" - process $proc$libresoc.v:127508$4986 + attribute \src "libresoc.v:129240.3-129260.6" + process $proc$libresoc.v:129240$5031 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:127509.5-127509.29" + attribute \src "libresoc.v:129241.5-129241.29" switch \initial - attribute \src "libresoc.v:127509.9-127509.17" + attribute \src "libresoc.v:129241.9-129241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200863,7 +203309,7 @@ module \dec_oe$168 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200876,18 +203322,18 @@ module \dec_oe$168 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:127529.3-127549.6" - process $proc$libresoc.v:127529$4987 + attribute \src "libresoc.v:129261.3-129281.6" + process $proc$libresoc.v:129261$5032 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:127530.5-127530.29" + attribute \src "libresoc.v:129262.5-129262.29" switch \initial - attribute \src "libresoc.v:127530.9-127530.17" + attribute \src "libresoc.v:129262.9-129262.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -200896,7 +203342,7 @@ module \dec_oe$168 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -200910,28 +203356,28 @@ module \dec_oe$168 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:127554.1-127688.10" +attribute \src "libresoc.v:129286.1-129421.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" module \dec_oe$173 - attribute \src "libresoc.v:127555.7-127555.20" + attribute \src "libresoc.v:129287.7-129287.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127646.3-127666.6" + attribute \src "libresoc.v:129379.3-129399.6" wire $0\oe[0:0] - attribute \src "libresoc.v:127667.3-127687.6" + attribute \src "libresoc.v:129400.3-129420.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:127646.3-127666.6" + attribute \src "libresoc.v:129379.3-129399.6" wire $1\oe[0:0] - attribute \src "libresoc.v:127667.3-127687.6" + attribute \src "libresoc.v:129400.3-129420.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:127646.3-127666.6" + attribute \src "libresoc.v:129379.3-129399.6" wire $2\oe[0:0] - attribute \src "libresoc.v:127667.3-127687.6" + attribute \src "libresoc.v:129400.3-129420.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 4 \OE - attribute \src "libresoc.v:127555.7-127555.15" + attribute \src "libresoc.v:129287.7-129287.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -201007,6 +203453,7 @@ module \dec_oe$173 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 1 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -201017,28 +203464,28 @@ module \dec_oe$173 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:127555.7-127555.20" - process $proc$libresoc.v:127555$4991 + attribute \src "libresoc.v:129287.7-129287.20" + process $proc$libresoc.v:129287$5036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127646.3-127666.6" - process $proc$libresoc.v:127646$4989 + attribute \src "libresoc.v:129379.3-129399.6" + process $proc$libresoc.v:129379$5034 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:127647.5-127647.29" + attribute \src "libresoc.v:129380.5-129380.29" switch \initial - attribute \src "libresoc.v:127647.9-127647.17" + attribute \src "libresoc.v:129380.9-129380.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -201047,7 +203494,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201060,18 +203507,18 @@ module \dec_oe$173 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:127667.3-127687.6" - process $proc$libresoc.v:127667$4990 + attribute \src "libresoc.v:129400.3-129420.6" + process $proc$libresoc.v:129400$5035 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:127668.5-127668.29" + attribute \src "libresoc.v:129401.5-129401.29" switch \initial - attribute \src "libresoc.v:127668.9-127668.17" + attribute \src "libresoc.v:129401.9-129401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -201080,7 +203527,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201094,24 +203541,24 @@ module \dec_oe$173 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:127692.1-127746.10" +attribute \src "libresoc.v:129425.1-129479.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc - attribute \src "libresoc.v:127693.7-127693.20" + attribute \src "libresoc.v:129426.7-129426.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127708.3-127726.6" + attribute \src "libresoc.v:129441.3-129459.6" wire $0\rc[0:0] - attribute \src "libresoc.v:127727.3-127745.6" + attribute \src "libresoc.v:129460.3-129478.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:127708.3-127726.6" + attribute \src "libresoc.v:129441.3-129459.6" wire $1\rc[0:0] - attribute \src "libresoc.v:127727.3-127745.6" + attribute \src "libresoc.v:129460.3-129478.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \ALU_Rc - attribute \src "libresoc.v:127693.7-127693.15" + attribute \src "libresoc.v:129426.7-129426.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -201121,28 +203568,28 @@ module \dec_rc attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:127693.7-127693.20" - process $proc$libresoc.v:127693$4994 + attribute \src "libresoc.v:129426.7-129426.20" + process $proc$libresoc.v:129426$5039 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127708.3-127726.6" - process $proc$libresoc.v:127708$4992 + attribute \src "libresoc.v:129441.3-129459.6" + process $proc$libresoc.v:129441$5037 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:127709.5-127709.29" + attribute \src "libresoc.v:129442.5-129442.29" switch \initial - attribute \src "libresoc.v:127709.9-127709.17" + attribute \src "libresoc.v:129442.9-129442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201162,18 +203609,18 @@ module \dec_rc sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:127727.3-127745.6" - process $proc$libresoc.v:127727$4993 + attribute \src "libresoc.v:129460.3-129478.6" + process $proc$libresoc.v:129460$5038 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:127728.5-127728.29" + attribute \src "libresoc.v:129461.5-129461.29" switch \initial - attribute \src "libresoc.v:127728.9-127728.17" + attribute \src "libresoc.v:129461.9-129461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201194,24 +203641,24 @@ module \dec_rc update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:127750.1-127802.10" +attribute \src "libresoc.v:129483.1-129535.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" module \dec_rc$139 - attribute \src "libresoc.v:127751.7-127751.20" + attribute \src "libresoc.v:129484.7-129484.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127764.3-127782.6" + attribute \src "libresoc.v:129497.3-129515.6" wire $0\rc[0:0] - attribute \src "libresoc.v:127783.3-127801.6" + attribute \src "libresoc.v:129516.3-129534.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:127764.3-127782.6" + attribute \src "libresoc.v:129497.3-129515.6" wire $1\rc[0:0] - attribute \src "libresoc.v:127783.3-127801.6" + attribute \src "libresoc.v:129516.3-129534.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 1 \CR_Rc - attribute \src "libresoc.v:127751.7-127751.15" + attribute \src "libresoc.v:129484.7-129484.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -201221,28 +203668,28 @@ module \dec_rc$139 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:127751.7-127751.20" - process $proc$libresoc.v:127751$4997 + attribute \src "libresoc.v:129484.7-129484.20" + process $proc$libresoc.v:129484$5042 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127764.3-127782.6" - process $proc$libresoc.v:127764$4995 + attribute \src "libresoc.v:129497.3-129515.6" + process $proc$libresoc.v:129497$5040 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:127765.5-127765.29" + attribute \src "libresoc.v:129498.5-129498.29" switch \initial - attribute \src "libresoc.v:127765.9-127765.17" + attribute \src "libresoc.v:129498.9-129498.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201262,18 +203709,18 @@ module \dec_rc$139 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:127783.3-127801.6" - process $proc$libresoc.v:127783$4996 + attribute \src "libresoc.v:129516.3-129534.6" + process $proc$libresoc.v:129516$5041 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:127784.5-127784.29" + attribute \src "libresoc.v:129517.5-129517.29" switch \initial - attribute \src "libresoc.v:127784.9-127784.17" + attribute \src "libresoc.v:129517.9-129517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201294,24 +203741,24 @@ module \dec_rc$139 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:127806.1-127858.10" +attribute \src "libresoc.v:129539.1-129591.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" module \dec_rc$142 - attribute \src "libresoc.v:127807.7-127807.20" + attribute \src "libresoc.v:129540.7-129540.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127820.3-127838.6" + attribute \src "libresoc.v:129553.3-129571.6" wire $0\rc[0:0] - attribute \src "libresoc.v:127839.3-127857.6" + attribute \src "libresoc.v:129572.3-129590.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:127820.3-127838.6" + attribute \src "libresoc.v:129553.3-129571.6" wire $1\rc[0:0] - attribute \src "libresoc.v:127839.3-127857.6" + attribute \src "libresoc.v:129572.3-129590.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 1 \BRANCH_Rc - attribute \src "libresoc.v:127807.7-127807.15" + attribute \src "libresoc.v:129540.7-129540.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -201321,28 +203768,28 @@ module \dec_rc$142 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:127807.7-127807.20" - process $proc$libresoc.v:127807$5000 + attribute \src "libresoc.v:129540.7-129540.20" + process $proc$libresoc.v:129540$5045 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127820.3-127838.6" - process $proc$libresoc.v:127820$4998 + attribute \src "libresoc.v:129553.3-129571.6" + process $proc$libresoc.v:129553$5043 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:127821.5-127821.29" + attribute \src "libresoc.v:129554.5-129554.29" switch \initial - attribute \src "libresoc.v:127821.9-127821.17" + attribute \src "libresoc.v:129554.9-129554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201362,18 +203809,18 @@ module \dec_rc$142 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:127839.3-127857.6" - process $proc$libresoc.v:127839$4999 + attribute \src "libresoc.v:129572.3-129590.6" + process $proc$libresoc.v:129572$5044 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:127840.5-127840.29" + attribute \src "libresoc.v:129573.5-129573.29" switch \initial - attribute \src "libresoc.v:127840.9-127840.17" + attribute \src "libresoc.v:129573.9-129573.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201394,24 +203841,24 @@ module \dec_rc$142 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:127862.1-127916.10" +attribute \src "libresoc.v:129595.1-129649.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" module \dec_rc$146 - attribute \src "libresoc.v:127863.7-127863.20" + attribute \src "libresoc.v:129596.7-129596.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127878.3-127896.6" + attribute \src "libresoc.v:129611.3-129629.6" wire $0\rc[0:0] - attribute \src "libresoc.v:127897.3-127915.6" + attribute \src "libresoc.v:129630.3-129648.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:127878.3-127896.6" + attribute \src "libresoc.v:129611.3-129629.6" wire $1\rc[0:0] - attribute \src "libresoc.v:127897.3-127915.6" + attribute \src "libresoc.v:129630.3-129648.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:127863.7-127863.15" + attribute \src "libresoc.v:129596.7-129596.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -201421,28 +203868,28 @@ module \dec_rc$146 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:127863.7-127863.20" - process $proc$libresoc.v:127863$5003 + attribute \src "libresoc.v:129596.7-129596.20" + process $proc$libresoc.v:129596$5048 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127878.3-127896.6" - process $proc$libresoc.v:127878$5001 + attribute \src "libresoc.v:129611.3-129629.6" + process $proc$libresoc.v:129611$5046 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:127879.5-127879.29" + attribute \src "libresoc.v:129612.5-129612.29" switch \initial - attribute \src "libresoc.v:127879.9-127879.17" + attribute \src "libresoc.v:129612.9-129612.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201462,18 +203909,18 @@ module \dec_rc$146 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:127897.3-127915.6" - process $proc$libresoc.v:127897$5002 + attribute \src "libresoc.v:129630.3-129648.6" + process $proc$libresoc.v:129630$5047 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:127898.5-127898.29" + attribute \src "libresoc.v:129631.5-129631.29" switch \initial - attribute \src "libresoc.v:127898.9-127898.17" + attribute \src "libresoc.v:129631.9-129631.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201494,24 +203941,24 @@ module \dec_rc$146 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:127920.1-127972.10" +attribute \src "libresoc.v:129653.1-129705.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" module \dec_rc$151 - attribute \src "libresoc.v:127921.7-127921.20" + attribute \src "libresoc.v:129654.7-129654.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127934.3-127952.6" + attribute \src "libresoc.v:129667.3-129685.6" wire $0\rc[0:0] - attribute \src "libresoc.v:127953.3-127971.6" + attribute \src "libresoc.v:129686.3-129704.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:127934.3-127952.6" + attribute \src "libresoc.v:129667.3-129685.6" wire $1\rc[0:0] - attribute \src "libresoc.v:127953.3-127971.6" + attribute \src "libresoc.v:129686.3-129704.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 1 \SPR_Rc - attribute \src "libresoc.v:127921.7-127921.15" + attribute \src "libresoc.v:129654.7-129654.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -201521,28 +203968,28 @@ module \dec_rc$151 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:127921.7-127921.20" - process $proc$libresoc.v:127921$5006 + attribute \src "libresoc.v:129654.7-129654.20" + process $proc$libresoc.v:129654$5051 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127934.3-127952.6" - process $proc$libresoc.v:127934$5004 + attribute \src "libresoc.v:129667.3-129685.6" + process $proc$libresoc.v:129667$5049 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:127935.5-127935.29" + attribute \src "libresoc.v:129668.5-129668.29" switch \initial - attribute \src "libresoc.v:127935.9-127935.17" + attribute \src "libresoc.v:129668.9-129668.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201562,18 +204009,18 @@ module \dec_rc$151 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:127953.3-127971.6" - process $proc$libresoc.v:127953$5005 + attribute \src "libresoc.v:129686.3-129704.6" + process $proc$libresoc.v:129686$5050 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:127954.5-127954.29" + attribute \src "libresoc.v:129687.5-129687.29" switch \initial - attribute \src "libresoc.v:127954.9-127954.17" + attribute \src "libresoc.v:129687.9-129687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201594,24 +204041,24 @@ module \dec_rc$151 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:127976.1-128030.10" +attribute \src "libresoc.v:129709.1-129763.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" module \dec_rc$154 - attribute \src "libresoc.v:127977.7-127977.20" + attribute \src "libresoc.v:129710.7-129710.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127992.3-128010.6" + attribute \src "libresoc.v:129725.3-129743.6" wire $0\rc[0:0] - attribute \src "libresoc.v:128011.3-128029.6" + attribute \src "libresoc.v:129744.3-129762.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:127992.3-128010.6" + attribute \src "libresoc.v:129725.3-129743.6" wire $1\rc[0:0] - attribute \src "libresoc.v:128011.3-128029.6" + attribute \src "libresoc.v:129744.3-129762.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \DIV_Rc - attribute \src "libresoc.v:127977.7-127977.15" + attribute \src "libresoc.v:129710.7-129710.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -201621,28 +204068,28 @@ module \dec_rc$154 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:127977.7-127977.20" - process $proc$libresoc.v:127977$5009 + attribute \src "libresoc.v:129710.7-129710.20" + process $proc$libresoc.v:129710$5054 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127992.3-128010.6" - process $proc$libresoc.v:127992$5007 + attribute \src "libresoc.v:129725.3-129743.6" + process $proc$libresoc.v:129725$5052 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:127993.5-127993.29" + attribute \src "libresoc.v:129726.5-129726.29" switch \initial - attribute \src "libresoc.v:127993.9-127993.17" + attribute \src "libresoc.v:129726.9-129726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201662,18 +204109,18 @@ module \dec_rc$154 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:128011.3-128029.6" - process $proc$libresoc.v:128011$5008 + attribute \src "libresoc.v:129744.3-129762.6" + process $proc$libresoc.v:129744$5053 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:128012.5-128012.29" + attribute \src "libresoc.v:129745.5-129745.29" switch \initial - attribute \src "libresoc.v:128012.9-128012.17" + attribute \src "libresoc.v:129745.9-129745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201694,24 +204141,24 @@ module \dec_rc$154 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:128034.1-128088.10" +attribute \src "libresoc.v:129767.1-129821.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" module \dec_rc$159 - attribute \src "libresoc.v:128035.7-128035.20" + attribute \src "libresoc.v:129768.7-129768.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128050.3-128068.6" + attribute \src "libresoc.v:129783.3-129801.6" wire $0\rc[0:0] - attribute \src "libresoc.v:128069.3-128087.6" + attribute \src "libresoc.v:129802.3-129820.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:128050.3-128068.6" + attribute \src "libresoc.v:129783.3-129801.6" wire $1\rc[0:0] - attribute \src "libresoc.v:128069.3-128087.6" + attribute \src "libresoc.v:129802.3-129820.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \MUL_Rc - attribute \src "libresoc.v:128035.7-128035.15" + attribute \src "libresoc.v:129768.7-129768.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -201721,28 +204168,28 @@ module \dec_rc$159 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:128035.7-128035.20" - process $proc$libresoc.v:128035$5012 + attribute \src "libresoc.v:129768.7-129768.20" + process $proc$libresoc.v:129768$5057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128050.3-128068.6" - process $proc$libresoc.v:128050$5010 + attribute \src "libresoc.v:129783.3-129801.6" + process $proc$libresoc.v:129783$5055 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:128051.5-128051.29" + attribute \src "libresoc.v:129784.5-129784.29" switch \initial - attribute \src "libresoc.v:128051.9-128051.17" + attribute \src "libresoc.v:129784.9-129784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201762,18 +204209,18 @@ module \dec_rc$159 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:128069.3-128087.6" - process $proc$libresoc.v:128069$5011 + attribute \src "libresoc.v:129802.3-129820.6" + process $proc$libresoc.v:129802$5056 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:128070.5-128070.29" + attribute \src "libresoc.v:129803.5-129803.29" switch \initial - attribute \src "libresoc.v:128070.9-128070.17" + attribute \src "libresoc.v:129803.9-129803.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201794,24 +204241,24 @@ module \dec_rc$159 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:128092.1-128146.10" +attribute \src "libresoc.v:129825.1-129879.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" module \dec_rc$163 - attribute \src "libresoc.v:128093.7-128093.20" + attribute \src "libresoc.v:129826.7-129826.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128108.3-128126.6" + attribute \src "libresoc.v:129841.3-129859.6" wire $0\rc[0:0] - attribute \src "libresoc.v:128127.3-128145.6" + attribute \src "libresoc.v:129860.3-129878.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:128108.3-128126.6" + attribute \src "libresoc.v:129841.3-129859.6" wire $1\rc[0:0] - attribute \src "libresoc.v:128127.3-128145.6" + attribute \src "libresoc.v:129860.3-129878.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:128093.7-128093.15" + attribute \src "libresoc.v:129826.7-129826.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -201821,28 +204268,28 @@ module \dec_rc$163 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:128093.7-128093.20" - process $proc$libresoc.v:128093$5015 + attribute \src "libresoc.v:129826.7-129826.20" + process $proc$libresoc.v:129826$5060 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128108.3-128126.6" - process $proc$libresoc.v:128108$5013 + attribute \src "libresoc.v:129841.3-129859.6" + process $proc$libresoc.v:129841$5058 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:128109.5-128109.29" + attribute \src "libresoc.v:129842.5-129842.29" switch \initial - attribute \src "libresoc.v:128109.9-128109.17" + attribute \src "libresoc.v:129842.9-129842.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201862,18 +204309,18 @@ module \dec_rc$163 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:128127.3-128145.6" - process $proc$libresoc.v:128127$5014 + attribute \src "libresoc.v:129860.3-129878.6" + process $proc$libresoc.v:129860$5059 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:128128.5-128128.29" + attribute \src "libresoc.v:129861.5-129861.29" switch \initial - attribute \src "libresoc.v:128128.9-128128.17" + attribute \src "libresoc.v:129861.9-129861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201894,24 +204341,24 @@ module \dec_rc$163 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:128150.1-128204.10" +attribute \src "libresoc.v:129883.1-129937.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" module \dec_rc$167 - attribute \src "libresoc.v:128151.7-128151.20" + attribute \src "libresoc.v:129884.7-129884.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128166.3-128184.6" + attribute \src "libresoc.v:129899.3-129917.6" wire $0\rc[0:0] - attribute \src "libresoc.v:128185.3-128203.6" + attribute \src "libresoc.v:129918.3-129936.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:128166.3-128184.6" + attribute \src "libresoc.v:129899.3-129917.6" wire $1\rc[0:0] - attribute \src "libresoc.v:128185.3-128203.6" + attribute \src "libresoc.v:129918.3-129936.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \LDST_Rc - attribute \src "libresoc.v:128151.7-128151.15" + attribute \src "libresoc.v:129884.7-129884.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -201921,28 +204368,28 @@ module \dec_rc$167 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:128151.7-128151.20" - process $proc$libresoc.v:128151$5018 + attribute \src "libresoc.v:129884.7-129884.20" + process $proc$libresoc.v:129884$5063 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128166.3-128184.6" - process $proc$libresoc.v:128166$5016 + attribute \src "libresoc.v:129899.3-129917.6" + process $proc$libresoc.v:129899$5061 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:128167.5-128167.29" + attribute \src "libresoc.v:129900.5-129900.29" switch \initial - attribute \src "libresoc.v:128167.9-128167.17" + attribute \src "libresoc.v:129900.9-129900.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201962,18 +204409,18 @@ module \dec_rc$167 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:128185.3-128203.6" - process $proc$libresoc.v:128185$5017 + attribute \src "libresoc.v:129918.3-129936.6" + process $proc$libresoc.v:129918$5062 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:128186.5-128186.29" + attribute \src "libresoc.v:129919.5-129919.29" switch \initial - attribute \src "libresoc.v:128186.9-128186.17" + attribute \src "libresoc.v:129919.9-129919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201994,24 +204441,24 @@ module \dec_rc$167 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:128208.1-128262.10" +attribute \src "libresoc.v:129941.1-129995.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" module \dec_rc$172 - attribute \src "libresoc.v:128209.7-128209.20" + attribute \src "libresoc.v:129942.7-129942.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128224.3-128242.6" + attribute \src "libresoc.v:129957.3-129975.6" wire $0\rc[0:0] - attribute \src "libresoc.v:128243.3-128261.6" + attribute \src "libresoc.v:129976.3-129994.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:128224.3-128242.6" + attribute \src "libresoc.v:129957.3-129975.6" wire $1\rc[0:0] - attribute \src "libresoc.v:128243.3-128261.6" + attribute \src "libresoc.v:129976.3-129994.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire input 3 \Rc - attribute \src "libresoc.v:128209.7-128209.15" + attribute \src "libresoc.v:129942.7-129942.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -202021,28 +204468,28 @@ module \dec_rc$172 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:128209.7-128209.20" - process $proc$libresoc.v:128209$5021 + attribute \src "libresoc.v:129942.7-129942.20" + process $proc$libresoc.v:129942$5066 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128224.3-128242.6" - process $proc$libresoc.v:128224$5019 + attribute \src "libresoc.v:129957.3-129975.6" + process $proc$libresoc.v:129957$5064 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:128225.5-128225.29" + attribute \src "libresoc.v:129958.5-129958.29" switch \initial - attribute \src "libresoc.v:128225.9-128225.17" + attribute \src "libresoc.v:129958.9-129958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202062,18 +204509,18 @@ module \dec_rc$172 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:128243.3-128261.6" - process $proc$libresoc.v:128243$5020 + attribute \src "libresoc.v:129976.3-129994.6" + process $proc$libresoc.v:129976$5065 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:128244.5-128244.29" + attribute \src "libresoc.v:129977.5-129977.29" switch \initial - attribute \src "libresoc.v:128244.9-128244.17" + attribute \src "libresoc.v:129977.9-129977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202094,539 +204541,539 @@ module \dec_rc$172 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:128266.1-129506.10" +attribute \src "libresoc.v:129999.1-131243.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 - attribute \src "libresoc.v:129063.3-129064.25" + attribute \src "libresoc.v:130800.3-130801.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5161 - attribute \src "libresoc.v:129035.3-129036.75" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5206 + attribute \src "libresoc.v:130772.3-130773.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 13 $0\alu_div0_logical_op__fn_unit$next[12:0]$5162 - attribute \src "libresoc.v:129005.3-129006.73" - wire width 13 $0\alu_div0_logical_op__fn_unit[12:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5163 - attribute \src "libresoc.v:129007.3-129008.87" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 + attribute \src "libresoc.v:130742.3-130743.73" + wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:130987.3-131025.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 + attribute \src "libresoc.v:130744.3-130745.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5164 - attribute \src "libresoc.v:129009.3-129010.83" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 + attribute \src "libresoc.v:130746.3-130747.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5165 - attribute \src "libresoc.v:129023.3-129024.81" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5210 + attribute \src "libresoc.v:130760.3-130761.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5166 - attribute \src "libresoc.v:129037.3-129038.67" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5211 + attribute \src "libresoc.v:130774.3-130775.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5167 - attribute \src "libresoc.v:129003.3-129004.77" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5212 + attribute \src "libresoc.v:130740.3-130741.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$5168 - attribute \src "libresoc.v:129019.3-129020.77" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$5213 + attribute \src "libresoc.v:130756.3-130757.77" wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$5169 - attribute \src "libresoc.v:129025.3-129026.79" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$5214 + attribute \src "libresoc.v:130762.3-130763.79" wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5170 - attribute \src "libresoc.v:129031.3-129032.75" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 + attribute \src "libresoc.v:130768.3-130769.75" wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$5171 - attribute \src "libresoc.v:129033.3-129034.77" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$5216 + attribute \src "libresoc.v:130770.3-130771.77" wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5172 - attribute \src "libresoc.v:129015.3-129016.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 + attribute \src "libresoc.v:130752.3-130753.71" wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5173 - attribute \src "libresoc.v:129017.3-129018.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 + attribute \src "libresoc.v:130754.3-130755.71" wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$5174 - attribute \src "libresoc.v:129029.3-129030.83" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$5219 + attribute \src "libresoc.v:130766.3-130767.83" wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5175 - attribute \src "libresoc.v:129013.3-129014.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 + attribute \src "libresoc.v:130750.3-130751.71" wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5176 - attribute \src "libresoc.v:129011.3-129012.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 + attribute \src "libresoc.v:130748.3-130749.71" wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5177 - attribute \src "libresoc.v:129027.3-129028.77" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 + attribute \src "libresoc.v:130764.3-130765.77" wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$5178 - attribute \src "libresoc.v:129021.3-129022.71" + attribute \src "libresoc.v:130987.3-131025.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$5223 + attribute \src "libresoc.v:130758.3-130759.71" wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:129061.3-129062.40" + attribute \src "libresoc.v:130798.3-130799.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:129416.3-129424.6" - wire $0\alu_l_r_alu$next[0:0]$5248 - attribute \src "libresoc.v:128977.3-128978.39" + attribute \src "libresoc.v:131153.3-131161.6" + wire $0\alu_l_r_alu$next[0:0]$5293 + attribute \src "libresoc.v:130714.3-130715.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:129407.3-129415.6" - wire $0\alui_l_r_alui$next[0:0]$5245 - attribute \src "libresoc.v:128979.3-128980.43" + attribute \src "libresoc.v:131144.3-131152.6" + wire $0\alui_l_r_alui$next[0:0]$5290 + attribute \src "libresoc.v:130716.3-130717.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:129289.3-129310.6" - wire width 64 $0\data_r0__o$next[63:0]$5204 - attribute \src "libresoc.v:128999.3-129000.37" + attribute \src "libresoc.v:131026.3-131047.6" + wire width 64 $0\data_r0__o$next[63:0]$5249 + attribute \src "libresoc.v:130736.3-130737.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:129289.3-129310.6" - wire $0\data_r0__o_ok$next[0:0]$5205 - attribute \src "libresoc.v:129001.3-129002.43" + attribute \src "libresoc.v:131026.3-131047.6" + wire $0\data_r0__o_ok$next[0:0]$5250 + attribute \src "libresoc.v:130738.3-130739.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:129311.3-129332.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$5212 - attribute \src "libresoc.v:128995.3-128996.43" + attribute \src "libresoc.v:131048.3-131069.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5257 + attribute \src "libresoc.v:130732.3-130733.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:129311.3-129332.6" - wire $0\data_r1__cr_a_ok$next[0:0]$5213 - attribute \src "libresoc.v:128997.3-128998.49" + attribute \src "libresoc.v:131048.3-131069.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5258 + attribute \src "libresoc.v:130734.3-130735.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:129333.3-129354.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$5220 - attribute \src "libresoc.v:128991.3-128992.47" + attribute \src "libresoc.v:131070.3-131091.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$5265 + attribute \src "libresoc.v:130728.3-130729.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:129333.3-129354.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$5221 - attribute \src "libresoc.v:128993.3-128994.53" + attribute \src "libresoc.v:131070.3-131091.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$5266 + attribute \src "libresoc.v:130730.3-130731.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:129355.3-129376.6" - wire $0\data_r3__xer_so$next[0:0]$5228 - attribute \src "libresoc.v:128987.3-128988.47" + attribute \src "libresoc.v:131092.3-131113.6" + wire $0\data_r3__xer_so$next[0:0]$5273 + attribute \src "libresoc.v:130724.3-130725.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:129355.3-129376.6" - wire $0\data_r3__xer_so_ok$next[0:0]$5229 - attribute \src "libresoc.v:128989.3-128990.53" + attribute \src "libresoc.v:131092.3-131113.6" + wire $0\data_r3__xer_so_ok$next[0:0]$5274 + attribute \src "libresoc.v:130726.3-130727.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:129425.3-129434.6" + attribute \src "libresoc.v:131162.3-131171.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:129435.3-129444.6" + attribute \src "libresoc.v:131172.3-131181.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:129445.3-129454.6" + attribute \src "libresoc.v:131182.3-131191.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:129455.3-129464.6" + attribute \src "libresoc.v:131192.3-131201.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:128267.7-128267.20" + attribute \src "libresoc.v:130000.7-130000.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129205.3-129213.6" - wire $0\opc_l_r_opc$next[0:0]$5146 - attribute \src "libresoc.v:129047.3-129048.39" + attribute \src "libresoc.v:130942.3-130950.6" + wire $0\opc_l_r_opc$next[0:0]$5191 + attribute \src "libresoc.v:130784.3-130785.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:129196.3-129204.6" - wire $0\opc_l_s_opc$next[0:0]$5143 - attribute \src "libresoc.v:129049.3-129050.39" + attribute \src "libresoc.v:130933.3-130941.6" + wire $0\opc_l_s_opc$next[0:0]$5188 + attribute \src "libresoc.v:130786.3-130787.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:129465.3-129473.6" - wire width 4 $0\prev_wr_go$next[3:0]$5255 - attribute \src "libresoc.v:129059.3-129060.37" + attribute \src "libresoc.v:131202.3-131210.6" + wire width 4 $0\prev_wr_go$next[3:0]$5300 + attribute \src "libresoc.v:130796.3-130797.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:129150.3-129159.6" + attribute \src "libresoc.v:130887.3-130896.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:129241.3-129249.6" - wire width 4 $0\req_l_r_req$next[3:0]$5158 - attribute \src "libresoc.v:129039.3-129040.39" + attribute \src "libresoc.v:130978.3-130986.6" + wire width 4 $0\req_l_r_req$next[3:0]$5203 + attribute \src "libresoc.v:130776.3-130777.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:129232.3-129240.6" - wire width 4 $0\req_l_s_req$next[3:0]$5155 - attribute \src "libresoc.v:129041.3-129042.39" + attribute \src "libresoc.v:130969.3-130977.6" + wire width 4 $0\req_l_s_req$next[3:0]$5200 + attribute \src "libresoc.v:130778.3-130779.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:129169.3-129177.6" - wire $0\rok_l_r_rdok$next[0:0]$5134 - attribute \src "libresoc.v:129055.3-129056.41" + attribute \src "libresoc.v:130906.3-130914.6" + wire $0\rok_l_r_rdok$next[0:0]$5179 + attribute \src "libresoc.v:130792.3-130793.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:129160.3-129168.6" - wire $0\rok_l_s_rdok$next[0:0]$5131 - attribute \src "libresoc.v:129057.3-129058.41" + attribute \src "libresoc.v:130897.3-130905.6" + wire $0\rok_l_s_rdok$next[0:0]$5176 + attribute \src "libresoc.v:130794.3-130795.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:129187.3-129195.6" - wire $0\rst_l_r_rst$next[0:0]$5140 - attribute \src "libresoc.v:129051.3-129052.39" + attribute \src "libresoc.v:130924.3-130932.6" + wire $0\rst_l_r_rst$next[0:0]$5185 + attribute \src "libresoc.v:130788.3-130789.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:129178.3-129186.6" - wire $0\rst_l_s_rst$next[0:0]$5137 - attribute \src "libresoc.v:129053.3-129054.39" + attribute \src "libresoc.v:130915.3-130923.6" + wire $0\rst_l_s_rst$next[0:0]$5182 + attribute \src "libresoc.v:130790.3-130791.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:129223.3-129231.6" - wire width 3 $0\src_l_r_src$next[2:0]$5152 - attribute \src "libresoc.v:129043.3-129044.39" + attribute \src "libresoc.v:130960.3-130968.6" + wire width 3 $0\src_l_r_src$next[2:0]$5197 + attribute \src "libresoc.v:130780.3-130781.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:129214.3-129222.6" - wire width 3 $0\src_l_s_src$next[2:0]$5149 - attribute \src "libresoc.v:129045.3-129046.39" + attribute \src "libresoc.v:130951.3-130959.6" + wire width 3 $0\src_l_s_src$next[2:0]$5194 + attribute \src "libresoc.v:130782.3-130783.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:129377.3-129386.6" - wire width 64 $0\src_r0$next[63:0]$5236 - attribute \src "libresoc.v:128985.3-128986.29" + attribute \src "libresoc.v:131114.3-131123.6" + wire width 64 $0\src_r0$next[63:0]$5281 + attribute \src "libresoc.v:130722.3-130723.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:129387.3-129396.6" - wire width 64 $0\src_r1$next[63:0]$5239 - attribute \src "libresoc.v:128983.3-128984.29" + attribute \src "libresoc.v:131124.3-131133.6" + wire width 64 $0\src_r1$next[63:0]$5284 + attribute \src "libresoc.v:130720.3-130721.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:129397.3-129406.6" - wire $0\src_r2$next[0:0]$5242 - attribute \src "libresoc.v:128981.3-128982.29" + attribute \src "libresoc.v:131134.3-131143.6" + wire $0\src_r2$next[0:0]$5287 + attribute \src "libresoc.v:130718.3-130719.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:128397.7-128397.24" + attribute \src "libresoc.v:130130.7-130130.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5179 - attribute \src "libresoc.v:128407.13-128407.49" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5224 + attribute \src "libresoc.v:130140.13-130140.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 13 $1\alu_div0_logical_op__fn_unit$next[12:0]$5180 - attribute \src "libresoc.v:128425.14-128425.53" - wire width 13 $1\alu_div0_logical_op__fn_unit[12:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5181 - attribute \src "libresoc.v:128429.14-128429.72" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 + attribute \src "libresoc.v:130159.14-130159.53" + wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:130987.3-131025.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 + attribute \src "libresoc.v:130163.14-130163.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5182 - attribute \src "libresoc.v:128433.7-128433.47" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 + attribute \src "libresoc.v:130167.7-130167.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5183 - attribute \src "libresoc.v:128441.13-128441.52" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 + attribute \src "libresoc.v:130175.13-130175.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5184 - attribute \src "libresoc.v:128445.14-128445.47" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5229 + attribute \src "libresoc.v:130179.14-130179.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5185 - attribute \src "libresoc.v:128523.13-128523.51" + attribute \src "libresoc.v:130987.3-131025.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 + attribute \src "libresoc.v:130258.13-130258.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$5186 - attribute \src "libresoc.v:128527.7-128527.44" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$5231 + attribute \src "libresoc.v:130262.7-130262.44" wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$5187 - attribute \src "libresoc.v:128531.7-128531.45" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$5232 + attribute \src "libresoc.v:130266.7-130266.45" wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5188 - attribute \src "libresoc.v:128535.7-128535.43" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 + attribute \src "libresoc.v:130270.7-130270.43" wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$5189 - attribute \src "libresoc.v:128539.7-128539.44" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$5234 + attribute \src "libresoc.v:130274.7-130274.44" wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5190 - attribute \src "libresoc.v:128543.7-128543.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 + attribute \src "libresoc.v:130278.7-130278.41" wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5191 - attribute \src "libresoc.v:128547.7-128547.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 + attribute \src "libresoc.v:130282.7-130282.41" wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$5192 - attribute \src "libresoc.v:128551.7-128551.47" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$5237 + attribute \src "libresoc.v:130286.7-130286.47" wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5193 - attribute \src "libresoc.v:128555.7-128555.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 + attribute \src "libresoc.v:130290.7-130290.41" wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5194 - attribute \src "libresoc.v:128559.7-128559.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 + attribute \src "libresoc.v:130294.7-130294.41" wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5195 - attribute \src "libresoc.v:128563.7-128563.44" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 + attribute \src "libresoc.v:130298.7-130298.44" wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$5196 - attribute \src "libresoc.v:128567.7-128567.41" + attribute \src "libresoc.v:130987.3-131025.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$5241 + attribute \src "libresoc.v:130302.7-130302.41" wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:128593.7-128593.26" + attribute \src "libresoc.v:130328.7-130328.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:129416.3-129424.6" - wire $1\alu_l_r_alu$next[0:0]$5249 - attribute \src "libresoc.v:128601.7-128601.25" + attribute \src "libresoc.v:131153.3-131161.6" + wire $1\alu_l_r_alu$next[0:0]$5294 + attribute \src "libresoc.v:130336.7-130336.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:129407.3-129415.6" - wire $1\alui_l_r_alui$next[0:0]$5246 - attribute \src "libresoc.v:128613.7-128613.27" + attribute \src "libresoc.v:131144.3-131152.6" + wire $1\alui_l_r_alui$next[0:0]$5291 + attribute \src "libresoc.v:130348.7-130348.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:129289.3-129310.6" - wire width 64 $1\data_r0__o$next[63:0]$5206 - attribute \src "libresoc.v:128647.14-128647.47" + attribute \src "libresoc.v:131026.3-131047.6" + wire width 64 $1\data_r0__o$next[63:0]$5251 + attribute \src "libresoc.v:130382.14-130382.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:129289.3-129310.6" - wire $1\data_r0__o_ok$next[0:0]$5207 - attribute \src "libresoc.v:128651.7-128651.27" + attribute \src "libresoc.v:131026.3-131047.6" + wire $1\data_r0__o_ok$next[0:0]$5252 + attribute \src "libresoc.v:130386.7-130386.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:129311.3-129332.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$5214 - attribute \src "libresoc.v:128655.13-128655.33" + attribute \src "libresoc.v:131048.3-131069.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5259 + attribute \src "libresoc.v:130390.13-130390.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:129311.3-129332.6" - wire $1\data_r1__cr_a_ok$next[0:0]$5215 - attribute \src "libresoc.v:128659.7-128659.30" + attribute \src "libresoc.v:131048.3-131069.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5260 + attribute \src "libresoc.v:130394.7-130394.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:129333.3-129354.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$5222 - attribute \src "libresoc.v:128663.13-128663.35" + attribute \src "libresoc.v:131070.3-131091.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$5267 + attribute \src "libresoc.v:130398.13-130398.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:129333.3-129354.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$5223 - attribute \src "libresoc.v:128667.7-128667.32" + attribute \src "libresoc.v:131070.3-131091.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$5268 + attribute \src "libresoc.v:130402.7-130402.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:129355.3-129376.6" - wire $1\data_r3__xer_so$next[0:0]$5230 - attribute \src "libresoc.v:128671.7-128671.29" + attribute \src "libresoc.v:131092.3-131113.6" + wire $1\data_r3__xer_so$next[0:0]$5275 + attribute \src "libresoc.v:130406.7-130406.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:129355.3-129376.6" - wire $1\data_r3__xer_so_ok$next[0:0]$5231 - attribute \src "libresoc.v:128675.7-128675.32" + attribute \src "libresoc.v:131092.3-131113.6" + wire $1\data_r3__xer_so_ok$next[0:0]$5276 + attribute \src "libresoc.v:130410.7-130410.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:129425.3-129434.6" + attribute \src "libresoc.v:131162.3-131171.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:129435.3-129444.6" + attribute \src "libresoc.v:131172.3-131181.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:129445.3-129454.6" + attribute \src "libresoc.v:131182.3-131191.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:129455.3-129464.6" + attribute \src "libresoc.v:131192.3-131201.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:129205.3-129213.6" - wire $1\opc_l_r_opc$next[0:0]$5147 - attribute \src "libresoc.v:128695.7-128695.25" + attribute \src "libresoc.v:130942.3-130950.6" + wire $1\opc_l_r_opc$next[0:0]$5192 + attribute \src "libresoc.v:130430.7-130430.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:129196.3-129204.6" - wire $1\opc_l_s_opc$next[0:0]$5144 - attribute \src "libresoc.v:128699.7-128699.25" + attribute \src "libresoc.v:130933.3-130941.6" + wire $1\opc_l_s_opc$next[0:0]$5189 + attribute \src "libresoc.v:130434.7-130434.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:129465.3-129473.6" - wire width 4 $1\prev_wr_go$next[3:0]$5256 - attribute \src "libresoc.v:128831.13-128831.30" + attribute \src "libresoc.v:131202.3-131210.6" + wire width 4 $1\prev_wr_go$next[3:0]$5301 + attribute \src "libresoc.v:130568.13-130568.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:129150.3-129159.6" + attribute \src "libresoc.v:130887.3-130896.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:129241.3-129249.6" - wire width 4 $1\req_l_r_req$next[3:0]$5159 - attribute \src "libresoc.v:128839.13-128839.31" + attribute \src "libresoc.v:130978.3-130986.6" + wire width 4 $1\req_l_r_req$next[3:0]$5204 + attribute \src "libresoc.v:130576.13-130576.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:129232.3-129240.6" - wire width 4 $1\req_l_s_req$next[3:0]$5156 - attribute \src "libresoc.v:128843.13-128843.31" + attribute \src "libresoc.v:130969.3-130977.6" + wire width 4 $1\req_l_s_req$next[3:0]$5201 + attribute \src "libresoc.v:130580.13-130580.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:129169.3-129177.6" - wire $1\rok_l_r_rdok$next[0:0]$5135 - attribute \src "libresoc.v:128855.7-128855.26" + attribute \src "libresoc.v:130906.3-130914.6" + wire $1\rok_l_r_rdok$next[0:0]$5180 + attribute \src "libresoc.v:130592.7-130592.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:129160.3-129168.6" - wire $1\rok_l_s_rdok$next[0:0]$5132 - attribute \src "libresoc.v:128859.7-128859.26" + attribute \src "libresoc.v:130897.3-130905.6" + wire $1\rok_l_s_rdok$next[0:0]$5177 + attribute \src "libresoc.v:130596.7-130596.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:129187.3-129195.6" - wire $1\rst_l_r_rst$next[0:0]$5141 - attribute \src "libresoc.v:128863.7-128863.25" + attribute \src "libresoc.v:130924.3-130932.6" + wire $1\rst_l_r_rst$next[0:0]$5186 + attribute \src "libresoc.v:130600.7-130600.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:129178.3-129186.6" - wire $1\rst_l_s_rst$next[0:0]$5138 - attribute \src "libresoc.v:128867.7-128867.25" + attribute \src "libresoc.v:130915.3-130923.6" + wire $1\rst_l_s_rst$next[0:0]$5183 + attribute \src "libresoc.v:130604.7-130604.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:129223.3-129231.6" - wire width 3 $1\src_l_r_src$next[2:0]$5153 - attribute \src "libresoc.v:128881.13-128881.31" + attribute \src "libresoc.v:130960.3-130968.6" + wire width 3 $1\src_l_r_src$next[2:0]$5198 + attribute \src "libresoc.v:130618.13-130618.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:129214.3-129222.6" - wire width 3 $1\src_l_s_src$next[2:0]$5150 - attribute \src "libresoc.v:128885.13-128885.31" + attribute \src "libresoc.v:130951.3-130959.6" + wire width 3 $1\src_l_s_src$next[2:0]$5195 + attribute \src "libresoc.v:130622.13-130622.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:129377.3-129386.6" - wire width 64 $1\src_r0$next[63:0]$5237 - attribute \src "libresoc.v:128893.14-128893.43" + attribute \src "libresoc.v:131114.3-131123.6" + wire width 64 $1\src_r0$next[63:0]$5282 + attribute \src "libresoc.v:130630.14-130630.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:129387.3-129396.6" - wire width 64 $1\src_r1$next[63:0]$5240 - attribute \src "libresoc.v:128897.14-128897.43" + attribute \src "libresoc.v:131124.3-131133.6" + wire width 64 $1\src_r1$next[63:0]$5285 + attribute \src "libresoc.v:130634.14-130634.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:129397.3-129406.6" - wire $1\src_r2$next[0:0]$5243 - attribute \src "libresoc.v:128901.7-128901.20" + attribute \src "libresoc.v:131134.3-131143.6" + wire $1\src_r2$next[0:0]$5288 + attribute \src "libresoc.v:130638.7-130638.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:129250.3-129288.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5197 - attribute \src "libresoc.v:129250.3-129288.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5198 - attribute \src "libresoc.v:129250.3-129288.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5199 - attribute \src "libresoc.v:129250.3-129288.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5200 - attribute \src "libresoc.v:129250.3-129288.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5201 - attribute \src "libresoc.v:129250.3-129288.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5202 - attribute \src "libresoc.v:129289.3-129310.6" - wire width 64 $2\data_r0__o$next[63:0]$5208 - attribute \src "libresoc.v:129289.3-129310.6" - wire $2\data_r0__o_ok$next[0:0]$5209 - attribute \src "libresoc.v:129311.3-129332.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$5216 - attribute \src "libresoc.v:129311.3-129332.6" - wire $2\data_r1__cr_a_ok$next[0:0]$5217 - attribute \src "libresoc.v:129333.3-129354.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$5224 - attribute \src "libresoc.v:129333.3-129354.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$5225 - attribute \src "libresoc.v:129355.3-129376.6" - wire $2\data_r3__xer_so$next[0:0]$5232 - attribute \src "libresoc.v:129355.3-129376.6" - wire $2\data_r3__xer_so_ok$next[0:0]$5233 - attribute \src "libresoc.v:129289.3-129310.6" - wire $3\data_r0__o_ok$next[0:0]$5210 - attribute \src "libresoc.v:129311.3-129332.6" - wire $3\data_r1__cr_a_ok$next[0:0]$5218 - attribute \src "libresoc.v:129333.3-129354.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$5226 - attribute \src "libresoc.v:129355.3-129376.6" - wire $3\data_r3__xer_so_ok$next[0:0]$5234 - attribute \src "libresoc.v:128916.19-128916.133" - wire width 3 $and$libresoc.v:128916$5024_Y - attribute \src "libresoc.v:128918.19-128918.115" - wire width 3 $and$libresoc.v:128918$5026_Y - attribute \src "libresoc.v:128919.18-128919.110" - wire $and$libresoc.v:128919$5027_Y - attribute \src "libresoc.v:128920.19-128920.125" - wire $and$libresoc.v:128920$5028_Y - attribute \src "libresoc.v:128921.19-128921.125" - wire $and$libresoc.v:128921$5029_Y - attribute \src "libresoc.v:128922.19-128922.125" - wire $and$libresoc.v:128922$5030_Y - attribute \src "libresoc.v:128923.19-128923.125" - wire $and$libresoc.v:128923$5031_Y - attribute \src "libresoc.v:128924.19-128924.149" - wire width 4 $and$libresoc.v:128924$5032_Y - attribute \src "libresoc.v:128925.19-128925.121" - wire width 4 $and$libresoc.v:128925$5033_Y - attribute \src "libresoc.v:128926.19-128926.127" - wire $and$libresoc.v:128926$5034_Y - attribute \src "libresoc.v:128927.19-128927.127" - wire $and$libresoc.v:128927$5035_Y - attribute \src "libresoc.v:128928.19-128928.127" - wire $and$libresoc.v:128928$5036_Y - attribute \src "libresoc.v:128929.19-128929.127" - wire $and$libresoc.v:128929$5037_Y - attribute \src "libresoc.v:128931.18-128931.98" - wire $and$libresoc.v:128931$5039_Y - attribute \src "libresoc.v:128933.18-128933.100" - wire $and$libresoc.v:128933$5041_Y - attribute \src "libresoc.v:128934.18-128934.160" - wire width 4 $and$libresoc.v:128934$5042_Y - attribute \src "libresoc.v:128936.18-128936.119" - wire width 4 $and$libresoc.v:128936$5044_Y - attribute \src "libresoc.v:128939.17-128939.123" - wire $and$libresoc.v:128939$5047_Y - attribute \src "libresoc.v:128940.18-128940.116" - wire $and$libresoc.v:128940$5048_Y - attribute \src "libresoc.v:128945.18-128945.113" - wire $and$libresoc.v:128945$5053_Y - attribute \src "libresoc.v:128946.18-128946.125" - wire width 4 $and$libresoc.v:128946$5054_Y - attribute \src "libresoc.v:128948.18-128948.112" - wire $and$libresoc.v:128948$5056_Y - attribute \src "libresoc.v:128950.18-128950.126" - wire $and$libresoc.v:128950$5058_Y - attribute \src "libresoc.v:128951.18-128951.126" - wire $and$libresoc.v:128951$5059_Y - attribute \src "libresoc.v:128952.18-128952.117" - wire $and$libresoc.v:128952$5060_Y - attribute \src "libresoc.v:128958.18-128958.130" - wire $and$libresoc.v:128958$5066_Y - attribute \src "libresoc.v:128959.18-128959.124" - wire width 4 $and$libresoc.v:128959$5067_Y - attribute \src "libresoc.v:128961.18-128961.116" - wire $and$libresoc.v:128961$5069_Y - attribute \src "libresoc.v:128962.18-128962.119" - wire $and$libresoc.v:128962$5070_Y - attribute \src "libresoc.v:128963.18-128963.121" - wire $and$libresoc.v:128963$5071_Y - attribute \src "libresoc.v:128964.18-128964.121" - wire $and$libresoc.v:128964$5072_Y - attribute \src "libresoc.v:128974.18-128974.134" - wire $and$libresoc.v:128974$5082_Y - attribute \src "libresoc.v:128975.18-128975.132" - wire $and$libresoc.v:128975$5083_Y - attribute \src "libresoc.v:128976.18-128976.149" - wire width 3 $and$libresoc.v:128976$5084_Y - attribute \src "libresoc.v:128947.18-128947.113" - wire $eq$libresoc.v:128947$5055_Y - attribute \src "libresoc.v:128949.18-128949.119" - wire $eq$libresoc.v:128949$5057_Y - attribute \src "libresoc.v:128914.19-128914.130" - wire $not$libresoc.v:128914$5022_Y - attribute \src "libresoc.v:128915.19-128915.136" - wire $not$libresoc.v:128915$5023_Y - attribute \src "libresoc.v:128917.19-128917.115" - wire width 3 $not$libresoc.v:128917$5025_Y - attribute \src "libresoc.v:128930.18-128930.97" - wire $not$libresoc.v:128930$5038_Y - attribute \src "libresoc.v:128932.18-128932.99" - wire $not$libresoc.v:128932$5040_Y - attribute \src "libresoc.v:128935.18-128935.113" - wire width 4 $not$libresoc.v:128935$5043_Y - attribute \src "libresoc.v:128938.18-128938.106" - wire $not$libresoc.v:128938$5046_Y - attribute \src "libresoc.v:128944.18-128944.120" - wire $not$libresoc.v:128944$5052_Y - attribute \src "libresoc.v:128955.17-128955.113" - wire width 3 $not$libresoc.v:128955$5063_Y - attribute \src "libresoc.v:128943.18-128943.112" - wire $or$libresoc.v:128943$5051_Y - attribute \src "libresoc.v:128953.18-128953.122" - wire $or$libresoc.v:128953$5061_Y - attribute \src "libresoc.v:128954.18-128954.124" - wire $or$libresoc.v:128954$5062_Y - attribute \src "libresoc.v:128956.18-128956.168" - wire width 4 $or$libresoc.v:128956$5064_Y - attribute \src "libresoc.v:128957.18-128957.155" - wire width 3 $or$libresoc.v:128957$5065_Y - attribute \src "libresoc.v:128960.18-128960.120" - wire width 4 $or$libresoc.v:128960$5068_Y - attribute \src "libresoc.v:128966.17-128966.117" - wire width 3 $or$libresoc.v:128966$5074_Y - attribute \src "libresoc.v:128971.17-128971.104" - wire $reduce_and$libresoc.v:128971$5079_Y - attribute \src "libresoc.v:128937.18-128937.106" - wire $reduce_or$libresoc.v:128937$5045_Y - attribute \src "libresoc.v:128941.18-128941.113" - wire $reduce_or$libresoc.v:128941$5049_Y - attribute \src "libresoc.v:128942.18-128942.112" - wire $reduce_or$libresoc.v:128942$5050_Y - attribute \src "libresoc.v:128965.18-128965.158" - wire $ternary$libresoc.v:128965$5073_Y - attribute \src "libresoc.v:128967.18-128967.159" - wire width 64 $ternary$libresoc.v:128967$5075_Y - attribute \src "libresoc.v:128968.18-128968.164" - wire $ternary$libresoc.v:128968$5076_Y - attribute \src "libresoc.v:128969.18-128969.180" - wire width 64 $ternary$libresoc.v:128969$5077_Y - attribute \src "libresoc.v:128970.18-128970.115" - wire width 64 $ternary$libresoc.v:128970$5078_Y - attribute \src "libresoc.v:128972.18-128972.125" - wire width 64 $ternary$libresoc.v:128972$5080_Y - attribute \src "libresoc.v:128973.18-128973.118" - wire $ternary$libresoc.v:128973$5081_Y + attribute \src "libresoc.v:130987.3-131025.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 + attribute \src "libresoc.v:130987.3-131025.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 + attribute \src "libresoc.v:131026.3-131047.6" + wire width 64 $2\data_r0__o$next[63:0]$5253 + attribute \src "libresoc.v:131026.3-131047.6" + wire $2\data_r0__o_ok$next[0:0]$5254 + attribute \src "libresoc.v:131048.3-131069.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$5261 + attribute \src "libresoc.v:131048.3-131069.6" + wire $2\data_r1__cr_a_ok$next[0:0]$5262 + attribute \src "libresoc.v:131070.3-131091.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$5269 + attribute \src "libresoc.v:131070.3-131091.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$5270 + attribute \src "libresoc.v:131092.3-131113.6" + wire $2\data_r3__xer_so$next[0:0]$5277 + attribute \src "libresoc.v:131092.3-131113.6" + wire $2\data_r3__xer_so_ok$next[0:0]$5278 + attribute \src "libresoc.v:131026.3-131047.6" + wire $3\data_r0__o_ok$next[0:0]$5255 + attribute \src "libresoc.v:131048.3-131069.6" + wire $3\data_r1__cr_a_ok$next[0:0]$5263 + attribute \src "libresoc.v:131070.3-131091.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$5271 + attribute \src "libresoc.v:131092.3-131113.6" + wire $3\data_r3__xer_so_ok$next[0:0]$5279 + attribute \src "libresoc.v:130653.19-130653.133" + wire width 3 $and$libresoc.v:130653$5069_Y + attribute \src "libresoc.v:130655.19-130655.115" + wire width 3 $and$libresoc.v:130655$5071_Y + attribute \src "libresoc.v:130656.18-130656.110" + wire $and$libresoc.v:130656$5072_Y + attribute \src "libresoc.v:130657.19-130657.125" + wire $and$libresoc.v:130657$5073_Y + attribute \src "libresoc.v:130658.19-130658.125" + wire $and$libresoc.v:130658$5074_Y + attribute \src "libresoc.v:130659.19-130659.125" + wire $and$libresoc.v:130659$5075_Y + attribute \src "libresoc.v:130660.19-130660.125" + wire $and$libresoc.v:130660$5076_Y + attribute \src "libresoc.v:130661.19-130661.149" + wire width 4 $and$libresoc.v:130661$5077_Y + attribute \src "libresoc.v:130662.19-130662.121" + wire width 4 $and$libresoc.v:130662$5078_Y + attribute \src "libresoc.v:130663.19-130663.127" + wire $and$libresoc.v:130663$5079_Y + attribute \src "libresoc.v:130664.19-130664.127" + wire $and$libresoc.v:130664$5080_Y + attribute \src "libresoc.v:130665.19-130665.127" + wire $and$libresoc.v:130665$5081_Y + attribute \src "libresoc.v:130666.19-130666.127" + wire $and$libresoc.v:130666$5082_Y + attribute \src "libresoc.v:130668.18-130668.98" + wire $and$libresoc.v:130668$5084_Y + attribute \src "libresoc.v:130670.18-130670.100" + wire $and$libresoc.v:130670$5086_Y + attribute \src "libresoc.v:130671.18-130671.160" + wire width 4 $and$libresoc.v:130671$5087_Y + attribute \src "libresoc.v:130673.18-130673.119" + wire width 4 $and$libresoc.v:130673$5089_Y + attribute \src "libresoc.v:130676.17-130676.123" + wire $and$libresoc.v:130676$5092_Y + attribute \src "libresoc.v:130677.18-130677.116" + wire $and$libresoc.v:130677$5093_Y + attribute \src "libresoc.v:130682.18-130682.113" + wire $and$libresoc.v:130682$5098_Y + attribute \src "libresoc.v:130683.18-130683.125" + wire width 4 $and$libresoc.v:130683$5099_Y + attribute \src "libresoc.v:130685.18-130685.112" + wire $and$libresoc.v:130685$5101_Y + attribute \src "libresoc.v:130687.18-130687.126" + wire $and$libresoc.v:130687$5103_Y + attribute \src "libresoc.v:130688.18-130688.126" + wire $and$libresoc.v:130688$5104_Y + attribute \src "libresoc.v:130689.18-130689.117" + wire $and$libresoc.v:130689$5105_Y + attribute \src "libresoc.v:130695.18-130695.130" + wire $and$libresoc.v:130695$5111_Y + attribute \src "libresoc.v:130696.18-130696.124" + wire width 4 $and$libresoc.v:130696$5112_Y + attribute \src "libresoc.v:130698.18-130698.116" + wire $and$libresoc.v:130698$5114_Y + attribute \src "libresoc.v:130699.18-130699.119" + wire $and$libresoc.v:130699$5115_Y + attribute \src "libresoc.v:130700.18-130700.121" + wire $and$libresoc.v:130700$5116_Y + attribute \src "libresoc.v:130701.18-130701.121" + wire $and$libresoc.v:130701$5117_Y + attribute \src "libresoc.v:130711.18-130711.134" + wire $and$libresoc.v:130711$5127_Y + attribute \src "libresoc.v:130712.18-130712.132" + wire $and$libresoc.v:130712$5128_Y + attribute \src "libresoc.v:130713.18-130713.149" + wire width 3 $and$libresoc.v:130713$5129_Y + attribute \src "libresoc.v:130684.18-130684.113" + wire $eq$libresoc.v:130684$5100_Y + attribute \src "libresoc.v:130686.18-130686.119" + wire $eq$libresoc.v:130686$5102_Y + attribute \src "libresoc.v:130651.19-130651.130" + wire $not$libresoc.v:130651$5067_Y + attribute \src "libresoc.v:130652.19-130652.136" + wire $not$libresoc.v:130652$5068_Y + attribute \src "libresoc.v:130654.19-130654.115" + wire width 3 $not$libresoc.v:130654$5070_Y + attribute \src "libresoc.v:130667.18-130667.97" + wire $not$libresoc.v:130667$5083_Y + attribute \src "libresoc.v:130669.18-130669.99" + wire $not$libresoc.v:130669$5085_Y + attribute \src "libresoc.v:130672.18-130672.113" + wire width 4 $not$libresoc.v:130672$5088_Y + attribute \src "libresoc.v:130675.18-130675.106" + wire $not$libresoc.v:130675$5091_Y + attribute \src "libresoc.v:130681.18-130681.120" + wire $not$libresoc.v:130681$5097_Y + attribute \src "libresoc.v:130692.17-130692.113" + wire width 3 $not$libresoc.v:130692$5108_Y + attribute \src "libresoc.v:130680.18-130680.112" + wire $or$libresoc.v:130680$5096_Y + attribute \src "libresoc.v:130690.18-130690.122" + wire $or$libresoc.v:130690$5106_Y + attribute \src "libresoc.v:130691.18-130691.124" + wire $or$libresoc.v:130691$5107_Y + attribute \src "libresoc.v:130693.18-130693.168" + wire width 4 $or$libresoc.v:130693$5109_Y + attribute \src "libresoc.v:130694.18-130694.155" + wire width 3 $or$libresoc.v:130694$5110_Y + attribute \src "libresoc.v:130697.18-130697.120" + wire width 4 $or$libresoc.v:130697$5113_Y + attribute \src "libresoc.v:130703.17-130703.117" + wire width 3 $or$libresoc.v:130703$5119_Y + attribute \src "libresoc.v:130708.17-130708.104" + wire $reduce_and$libresoc.v:130708$5124_Y + attribute \src "libresoc.v:130674.18-130674.106" + wire $reduce_or$libresoc.v:130674$5090_Y + attribute \src "libresoc.v:130678.18-130678.113" + wire $reduce_or$libresoc.v:130678$5094_Y + attribute \src "libresoc.v:130679.18-130679.112" + wire $reduce_or$libresoc.v:130679$5095_Y + attribute \src "libresoc.v:130702.18-130702.158" + wire $ternary$libresoc.v:130702$5118_Y + attribute \src "libresoc.v:130704.18-130704.159" + wire width 64 $ternary$libresoc.v:130704$5120_Y + attribute \src "libresoc.v:130705.18-130705.164" + wire $ternary$libresoc.v:130705$5121_Y + attribute \src "libresoc.v:130706.18-130706.180" + wire width 64 $ternary$libresoc.v:130706$5122_Y + attribute \src "libresoc.v:130707.18-130707.115" + wire width 64 $ternary$libresoc.v:130707$5123_Y + attribute \src "libresoc.v:130709.18-130709.125" + wire width 64 $ternary$libresoc.v:130709$5125_Y + attribute \src "libresoc.v:130710.18-130710.118" + wire $ternary$libresoc.v:130710$5126_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -202770,23 +205217,24 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_div0_logical_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_div0_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_div0_logical_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_div0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_div0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_div0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -202881,6 +205329,7 @@ module \div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_div0_logical_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -202977,9 +205426,9 @@ module \div0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -203045,7 +205494,7 @@ module \div0 wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 37 \dest4_o - attribute \src "libresoc.v:128267.7-128267.15" + attribute \src "libresoc.v:130000.7-130000.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -203062,21 +205511,22 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_div0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_div0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -203163,6 +205613,7 @@ module \div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -203272,7 +205723,7 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:128916$5024 + cell $and $and$libresoc.v:130653$5069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -203280,10 +205731,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } - connect \Y $and$libresoc.v:128916$5024_Y + connect \Y $and$libresoc.v:130653$5069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:128918$5026 + cell $and $and$libresoc.v:130655$5071 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -203291,10 +205742,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:128918$5026_Y + connect \Y $and$libresoc.v:130655$5071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:128919$5027 + cell $and $and$libresoc.v:130656$5072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203302,10 +205753,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:128919$5027_Y + connect \Y $and$libresoc.v:130656$5072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:128920$5028 + cell $and $and$libresoc.v:130657$5073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203313,10 +205764,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:128920$5028_Y + connect \Y $and$libresoc.v:130657$5073_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:128921$5029 + cell $and $and$libresoc.v:130658$5074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203324,10 +205775,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:128921$5029_Y + connect \Y $and$libresoc.v:130658$5074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:128922$5030 + cell $and $and$libresoc.v:130659$5075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203335,10 +205786,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:128922$5030_Y + connect \Y $and$libresoc.v:130659$5075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:128923$5031 + cell $and $and$libresoc.v:130660$5076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203346,10 +205797,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:128923$5031_Y + connect \Y $and$libresoc.v:130660$5076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:128924$5032 + cell $and $and$libresoc.v:130661$5077 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203357,10 +205808,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } - connect \Y $and$libresoc.v:128924$5032_Y + connect \Y $and$libresoc.v:130661$5077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:128925$5033 + cell $and $and$libresoc.v:130662$5078 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203368,10 +205819,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:128925$5033_Y + connect \Y $and$libresoc.v:130662$5078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:128926$5034 + cell $and $and$libresoc.v:130663$5079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203379,10 +205830,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:128926$5034_Y + connect \Y $and$libresoc.v:130663$5079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:128927$5035 + cell $and $and$libresoc.v:130664$5080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203390,10 +205841,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:128927$5035_Y + connect \Y $and$libresoc.v:130664$5080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:128928$5036 + cell $and $and$libresoc.v:130665$5081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203401,10 +205852,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:128928$5036_Y + connect \Y $and$libresoc.v:130665$5081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:128929$5037 + cell $and $and$libresoc.v:130666$5082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203412,10 +205863,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:128929$5037_Y + connect \Y $and$libresoc.v:130666$5082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:128931$5039 + cell $and $and$libresoc.v:130668$5084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203423,10 +205874,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:128931$5039_Y + connect \Y $and$libresoc.v:130668$5084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:128933$5041 + cell $and $and$libresoc.v:130670$5086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203434,10 +205885,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:128933$5041_Y + connect \Y $and$libresoc.v:130670$5086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:128934$5042 + cell $and $and$libresoc.v:130671$5087 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203445,10 +205896,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:128934$5042_Y + connect \Y $and$libresoc.v:130671$5087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:128936$5044 + cell $and $and$libresoc.v:130673$5089 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203456,10 +205907,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:128936$5044_Y + connect \Y $and$libresoc.v:130673$5089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:128939$5047 + cell $and $and$libresoc.v:130676$5092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203467,10 +205918,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:128939$5047_Y + connect \Y $and$libresoc.v:130676$5092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:128940$5048 + cell $and $and$libresoc.v:130677$5093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203478,10 +205929,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:128940$5048_Y + connect \Y $and$libresoc.v:130677$5093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:128945$5053 + cell $and $and$libresoc.v:130682$5098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203489,10 +205940,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:128945$5053_Y + connect \Y $and$libresoc.v:130682$5098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:128946$5054 + cell $and $and$libresoc.v:130683$5099 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203500,10 +205951,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:128946$5054_Y + connect \Y $and$libresoc.v:130683$5099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:128948$5056 + cell $and $and$libresoc.v:130685$5101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203511,10 +205962,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:128948$5056_Y + connect \Y $and$libresoc.v:130685$5101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:128950$5058 + cell $and $and$libresoc.v:130687$5103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203522,10 +205973,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i - connect \Y $and$libresoc.v:128950$5058_Y + connect \Y $and$libresoc.v:130687$5103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:128951$5059 + cell $and $and$libresoc.v:130688$5104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203533,10 +205984,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o - connect \Y $and$libresoc.v:128951$5059_Y + connect \Y $and$libresoc.v:130688$5104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:128952$5060 + cell $and $and$libresoc.v:130689$5105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203544,10 +205995,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:128952$5060_Y + connect \Y $and$libresoc.v:130689$5105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:128958$5066 + cell $and $and$libresoc.v:130695$5111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203555,10 +206006,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:128958$5066_Y + connect \Y $and$libresoc.v:130695$5111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:128959$5067 + cell $and $and$libresoc.v:130696$5112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203566,10 +206017,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:128959$5067_Y + connect \Y $and$libresoc.v:130696$5112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:128961$5069 + cell $and $and$libresoc.v:130698$5114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203577,10 +206028,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:128961$5069_Y + connect \Y $and$libresoc.v:130698$5114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:128962$5070 + cell $and $and$libresoc.v:130699$5115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203588,10 +206039,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:128962$5070_Y + connect \Y $and$libresoc.v:130699$5115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:128963$5071 + cell $and $and$libresoc.v:130700$5116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203599,10 +206050,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:128963$5071_Y + connect \Y $and$libresoc.v:130700$5116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:128964$5072 + cell $and $and$libresoc.v:130701$5117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203610,10 +206061,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:128964$5072_Y + connect \Y $and$libresoc.v:130701$5117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:128974$5082 + cell $and $and$libresoc.v:130711$5127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203621,10 +206072,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:128974$5082_Y + connect \Y $and$libresoc.v:130711$5127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:128975$5083 + cell $and $and$libresoc.v:130712$5128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203632,10 +206083,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:128975$5083_Y + connect \Y $and$libresoc.v:130712$5128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:128976$5084 + cell $and $and$libresoc.v:130713$5129 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -203643,10 +206094,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:128976$5084_Y + connect \Y $and$libresoc.v:130713$5129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:128947$5055 + cell $eq $eq$libresoc.v:130684$5100 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203654,10 +206105,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:128947$5055_Y + connect \Y $eq$libresoc.v:130684$5100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:128949$5057 + cell $eq $eq$libresoc.v:130686$5102 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203665,82 +206116,82 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:128949$5057_Y + connect \Y $eq$libresoc.v:130686$5102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:128914$5022 + cell $not $not$libresoc.v:130651$5067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:128914$5022_Y + connect \Y $not$libresoc.v:130651$5067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:128915$5023 + cell $not $not$libresoc.v:130652$5068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:128915$5023_Y + connect \Y $not$libresoc.v:130652$5068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:128917$5025 + cell $not $not$libresoc.v:130654$5070 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:128917$5025_Y + connect \Y $not$libresoc.v:130654$5070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:128930$5038 + cell $not $not$libresoc.v:130667$5083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:128930$5038_Y + connect \Y $not$libresoc.v:130667$5083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:128932$5040 + cell $not $not$libresoc.v:130669$5085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:128932$5040_Y + connect \Y $not$libresoc.v:130669$5085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:128935$5043 + cell $not $not$libresoc.v:130672$5088 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:128935$5043_Y + connect \Y $not$libresoc.v:130672$5088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:128938$5046 + cell $not $not$libresoc.v:130675$5091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:128938$5046_Y + connect \Y $not$libresoc.v:130675$5091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:128944$5052 + cell $not $not$libresoc.v:130681$5097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:128944$5052_Y + connect \Y $not$libresoc.v:130681$5097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:128955$5063 + cell $not $not$libresoc.v:130692$5108 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:128955$5063_Y + connect \Y $not$libresoc.v:130692$5108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:128943$5051 + cell $or $or$libresoc.v:130680$5096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203748,10 +206199,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:128943$5051_Y + connect \Y $or$libresoc.v:130680$5096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:128953$5061 + cell $or $or$libresoc.v:130690$5106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203759,10 +206210,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:128953$5061_Y + connect \Y $or$libresoc.v:130690$5106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:128954$5062 + cell $or $or$libresoc.v:130691$5107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -203770,10 +206221,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:128954$5062_Y + connect \Y $or$libresoc.v:130691$5107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:128956$5064 + cell $or $or$libresoc.v:130693$5109 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203781,10 +206232,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:128956$5064_Y + connect \Y $or$libresoc.v:130693$5109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:128957$5065 + cell $or $or$libresoc.v:130694$5110 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -203792,10 +206243,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:128957$5065_Y + connect \Y $or$libresoc.v:130694$5110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:128960$5068 + cell $or $or$libresoc.v:130697$5113 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -203803,10 +206254,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:128960$5068_Y + connect \Y $or$libresoc.v:130697$5113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:128966$5074 + cell $or $or$libresoc.v:130703$5119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -203814,98 +206265,98 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:128966$5074_Y + connect \Y $or$libresoc.v:130703$5119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:128971$5079 + cell $reduce_and $reduce_and$libresoc.v:130708$5124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:128971$5079_Y + connect \Y $reduce_and$libresoc.v:130708$5124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:128937$5045 + cell $reduce_or $reduce_or$libresoc.v:130674$5090 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:128937$5045_Y + connect \Y $reduce_or$libresoc.v:130674$5090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:128941$5049 + cell $reduce_or $reduce_or$libresoc.v:130678$5094 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:128941$5049_Y + connect \Y $reduce_or$libresoc.v:130678$5094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:128942$5050 + cell $reduce_or $reduce_or$libresoc.v:130679$5095 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:128942$5050_Y + connect \Y $reduce_or$libresoc.v:130679$5095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:128965$5073 + cell $mux $ternary$libresoc.v:130702$5118 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:128965$5073_Y + connect \Y $ternary$libresoc.v:130702$5118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:128967$5075 + cell $mux $ternary$libresoc.v:130704$5120 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:128967$5075_Y + connect \Y $ternary$libresoc.v:130704$5120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:128968$5076 + cell $mux $ternary$libresoc.v:130705$5121 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:128968$5076_Y + connect \Y $ternary$libresoc.v:130705$5121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:128969$5077 + cell $mux $ternary$libresoc.v:130706$5122 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:128969$5077_Y + connect \Y $ternary$libresoc.v:130706$5122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:128970$5078 + cell $mux $ternary$libresoc.v:130707$5123 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:128970$5078_Y + connect \Y $ternary$libresoc.v:130707$5123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:128972$5080 + cell $mux $ternary$libresoc.v:130709$5125 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:128972$5080_Y + connect \Y $ternary$libresoc.v:130709$5125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:128973$5081 + cell $mux $ternary$libresoc.v:130710$5126 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:128973$5081_Y + connect \Y $ternary$libresoc.v:130710$5126_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:129065.12-129101.4" + attribute \src "libresoc.v:130802.12-130838.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -203944,7 +206395,7 @@ module \div0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:129102.14-129108.4" + attribute \src "libresoc.v:130839.14-130845.4" cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -203953,7 +206404,7 @@ module \div0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:129109.15-129115.4" + attribute \src "libresoc.v:130846.15-130852.4" cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -203962,7 +206413,7 @@ module \div0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:129116.14-129122.4" + attribute \src "libresoc.v:130853.14-130859.4" cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -203971,7 +206422,7 @@ module \div0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:129123.14-129129.4" + attribute \src "libresoc.v:130860.14-130866.4" cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -203980,7 +206431,7 @@ module \div0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:129130.14-129136.4" + attribute \src "libresoc.v:130867.14-130873.4" cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -203989,7 +206440,7 @@ module \div0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:129137.14-129142.4" + attribute \src "libresoc.v:130874.14-130879.4" cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -203997,7 +206448,7 @@ module \div0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:129143.14-129149.4" + attribute \src "libresoc.v:130880.14-130886.4" cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -204005,682 +206456,682 @@ module \div0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:128267.7-128267.20" - process $proc$libresoc.v:128267$5257 + attribute \src "libresoc.v:130000.7-130000.20" + process $proc$libresoc.v:130000$5302 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128397.7-128397.24" - process $proc$libresoc.v:128397$5258 + attribute \src "libresoc.v:130130.7-130130.24" + process $proc$libresoc.v:130130$5303 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:128407.13-128407.49" - process $proc$libresoc.v:128407$5259 + attribute \src "libresoc.v:130140.13-130140.49" + process $proc$libresoc.v:130140$5304 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:128425.14-128425.53" - process $proc$libresoc.v:128425$5260 + attribute \src "libresoc.v:130159.14-130159.53" + process $proc$libresoc.v:130159$5305 assign { } { } - assign $1\alu_div0_logical_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[12:0] + update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:128429.14-128429.72" - process $proc$libresoc.v:128429$5261 + attribute \src "libresoc.v:130163.14-130163.72" + process $proc$libresoc.v:130163$5306 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:128433.7-128433.47" - process $proc$libresoc.v:128433$5262 + attribute \src "libresoc.v:130167.7-130167.47" + process $proc$libresoc.v:130167$5307 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:128441.13-128441.52" - process $proc$libresoc.v:128441$5263 + attribute \src "libresoc.v:130175.13-130175.52" + process $proc$libresoc.v:130175$5308 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:128445.14-128445.47" - process $proc$libresoc.v:128445$5264 + attribute \src "libresoc.v:130179.14-130179.47" + process $proc$libresoc.v:130179$5309 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:128523.13-128523.51" - process $proc$libresoc.v:128523$5265 + attribute \src "libresoc.v:130258.13-130258.51" + process $proc$libresoc.v:130258$5310 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:128527.7-128527.44" - process $proc$libresoc.v:128527$5266 + attribute \src "libresoc.v:130262.7-130262.44" + process $proc$libresoc.v:130262$5311 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:128531.7-128531.45" - process $proc$libresoc.v:128531$5267 + attribute \src "libresoc.v:130266.7-130266.45" + process $proc$libresoc.v:130266$5312 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:128535.7-128535.43" - process $proc$libresoc.v:128535$5268 + attribute \src "libresoc.v:130270.7-130270.43" + process $proc$libresoc.v:130270$5313 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:128539.7-128539.44" - process $proc$libresoc.v:128539$5269 + attribute \src "libresoc.v:130274.7-130274.44" + process $proc$libresoc.v:130274$5314 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:128543.7-128543.41" - process $proc$libresoc.v:128543$5270 + attribute \src "libresoc.v:130278.7-130278.41" + process $proc$libresoc.v:130278$5315 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:128547.7-128547.41" - process $proc$libresoc.v:128547$5271 + attribute \src "libresoc.v:130282.7-130282.41" + process $proc$libresoc.v:130282$5316 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:128551.7-128551.47" - process $proc$libresoc.v:128551$5272 + attribute \src "libresoc.v:130286.7-130286.47" + process $proc$libresoc.v:130286$5317 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:128555.7-128555.41" - process $proc$libresoc.v:128555$5273 + attribute \src "libresoc.v:130290.7-130290.41" + process $proc$libresoc.v:130290$5318 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:128559.7-128559.41" - process $proc$libresoc.v:128559$5274 + attribute \src "libresoc.v:130294.7-130294.41" + process $proc$libresoc.v:130294$5319 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:128563.7-128563.44" - process $proc$libresoc.v:128563$5275 + attribute \src "libresoc.v:130298.7-130298.44" + process $proc$libresoc.v:130298$5320 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:128567.7-128567.41" - process $proc$libresoc.v:128567$5276 + attribute \src "libresoc.v:130302.7-130302.41" + process $proc$libresoc.v:130302$5321 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:128593.7-128593.26" - process $proc$libresoc.v:128593$5277 + attribute \src "libresoc.v:130328.7-130328.26" + process $proc$libresoc.v:130328$5322 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:128601.7-128601.25" - process $proc$libresoc.v:128601$5278 + attribute \src "libresoc.v:130336.7-130336.25" + process $proc$libresoc.v:130336$5323 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:128613.7-128613.27" - process $proc$libresoc.v:128613$5279 + attribute \src "libresoc.v:130348.7-130348.27" + process $proc$libresoc.v:130348$5324 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:128647.14-128647.47" - process $proc$libresoc.v:128647$5280 + attribute \src "libresoc.v:130382.14-130382.47" + process $proc$libresoc.v:130382$5325 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:128651.7-128651.27" - process $proc$libresoc.v:128651$5281 + attribute \src "libresoc.v:130386.7-130386.27" + process $proc$libresoc.v:130386$5326 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:128655.13-128655.33" - process $proc$libresoc.v:128655$5282 + attribute \src "libresoc.v:130390.13-130390.33" + process $proc$libresoc.v:130390$5327 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:128659.7-128659.30" - process $proc$libresoc.v:128659$5283 + attribute \src "libresoc.v:130394.7-130394.30" + process $proc$libresoc.v:130394$5328 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:128663.13-128663.35" - process $proc$libresoc.v:128663$5284 + attribute \src "libresoc.v:130398.13-130398.35" + process $proc$libresoc.v:130398$5329 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:128667.7-128667.32" - process $proc$libresoc.v:128667$5285 + attribute \src "libresoc.v:130402.7-130402.32" + process $proc$libresoc.v:130402$5330 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:128671.7-128671.29" - process $proc$libresoc.v:128671$5286 + attribute \src "libresoc.v:130406.7-130406.29" + process $proc$libresoc.v:130406$5331 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:128675.7-128675.32" - process $proc$libresoc.v:128675$5287 + attribute \src "libresoc.v:130410.7-130410.32" + process $proc$libresoc.v:130410$5332 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:128695.7-128695.25" - process $proc$libresoc.v:128695$5288 + attribute \src "libresoc.v:130430.7-130430.25" + process $proc$libresoc.v:130430$5333 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:128699.7-128699.25" - process $proc$libresoc.v:128699$5289 + attribute \src "libresoc.v:130434.7-130434.25" + process $proc$libresoc.v:130434$5334 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:128831.13-128831.30" - process $proc$libresoc.v:128831$5290 + attribute \src "libresoc.v:130568.13-130568.30" + process $proc$libresoc.v:130568$5335 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:128839.13-128839.31" - process $proc$libresoc.v:128839$5291 + attribute \src "libresoc.v:130576.13-130576.31" + process $proc$libresoc.v:130576$5336 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:128843.13-128843.31" - process $proc$libresoc.v:128843$5292 + attribute \src "libresoc.v:130580.13-130580.31" + process $proc$libresoc.v:130580$5337 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:128855.7-128855.26" - process $proc$libresoc.v:128855$5293 + attribute \src "libresoc.v:130592.7-130592.26" + process $proc$libresoc.v:130592$5338 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:128859.7-128859.26" - process $proc$libresoc.v:128859$5294 + attribute \src "libresoc.v:130596.7-130596.26" + process $proc$libresoc.v:130596$5339 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:128863.7-128863.25" - process $proc$libresoc.v:128863$5295 + attribute \src "libresoc.v:130600.7-130600.25" + process $proc$libresoc.v:130600$5340 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:128867.7-128867.25" - process $proc$libresoc.v:128867$5296 + attribute \src "libresoc.v:130604.7-130604.25" + process $proc$libresoc.v:130604$5341 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:128881.13-128881.31" - process $proc$libresoc.v:128881$5297 + attribute \src "libresoc.v:130618.13-130618.31" + process $proc$libresoc.v:130618$5342 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:128885.13-128885.31" - process $proc$libresoc.v:128885$5298 + attribute \src "libresoc.v:130622.13-130622.31" + process $proc$libresoc.v:130622$5343 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:128893.14-128893.43" - process $proc$libresoc.v:128893$5299 + attribute \src "libresoc.v:130630.14-130630.43" + process $proc$libresoc.v:130630$5344 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:128897.14-128897.43" - process $proc$libresoc.v:128897$5300 + attribute \src "libresoc.v:130634.14-130634.43" + process $proc$libresoc.v:130634$5345 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:128901.7-128901.20" - process $proc$libresoc.v:128901$5301 + attribute \src "libresoc.v:130638.7-130638.20" + process $proc$libresoc.v:130638$5346 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:128977.3-128978.39" - process $proc$libresoc.v:128977$5085 + attribute \src "libresoc.v:130714.3-130715.39" + process $proc$libresoc.v:130714$5130 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:128979.3-128980.43" - process $proc$libresoc.v:128979$5086 + attribute \src "libresoc.v:130716.3-130717.43" + process $proc$libresoc.v:130716$5131 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:128981.3-128982.29" - process $proc$libresoc.v:128981$5087 + attribute \src "libresoc.v:130718.3-130719.29" + process $proc$libresoc.v:130718$5132 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:128983.3-128984.29" - process $proc$libresoc.v:128983$5088 + attribute \src "libresoc.v:130720.3-130721.29" + process $proc$libresoc.v:130720$5133 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:128985.3-128986.29" - process $proc$libresoc.v:128985$5089 + attribute \src "libresoc.v:130722.3-130723.29" + process $proc$libresoc.v:130722$5134 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:128987.3-128988.47" - process $proc$libresoc.v:128987$5090 + attribute \src "libresoc.v:130724.3-130725.47" + process $proc$libresoc.v:130724$5135 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:128989.3-128990.53" - process $proc$libresoc.v:128989$5091 + attribute \src "libresoc.v:130726.3-130727.53" + process $proc$libresoc.v:130726$5136 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:128991.3-128992.47" - process $proc$libresoc.v:128991$5092 + attribute \src "libresoc.v:130728.3-130729.47" + process $proc$libresoc.v:130728$5137 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:128993.3-128994.53" - process $proc$libresoc.v:128993$5093 + attribute \src "libresoc.v:130730.3-130731.53" + process $proc$libresoc.v:130730$5138 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:128995.3-128996.43" - process $proc$libresoc.v:128995$5094 + attribute \src "libresoc.v:130732.3-130733.43" + process $proc$libresoc.v:130732$5139 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:128997.3-128998.49" - process $proc$libresoc.v:128997$5095 + attribute \src "libresoc.v:130734.3-130735.49" + process $proc$libresoc.v:130734$5140 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:128999.3-129000.37" - process $proc$libresoc.v:128999$5096 + attribute \src "libresoc.v:130736.3-130737.37" + process $proc$libresoc.v:130736$5141 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:129001.3-129002.43" - process $proc$libresoc.v:129001$5097 + attribute \src "libresoc.v:130738.3-130739.43" + process $proc$libresoc.v:130738$5142 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:129003.3-129004.77" - process $proc$libresoc.v:129003$5098 + attribute \src "libresoc.v:130740.3-130741.77" + process $proc$libresoc.v:130740$5143 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:129005.3-129006.73" - process $proc$libresoc.v:129005$5099 + attribute \src "libresoc.v:130742.3-130743.73" + process $proc$libresoc.v:130742$5144 assign { } { } - assign $0\alu_div0_logical_op__fn_unit[12:0] \alu_div0_logical_op__fn_unit$next + assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk - update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[12:0] + update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:129007.3-129008.87" - process $proc$libresoc.v:129007$5100 + attribute \src "libresoc.v:130744.3-130745.87" + process $proc$libresoc.v:130744$5145 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:129009.3-129010.83" - process $proc$libresoc.v:129009$5101 + attribute \src "libresoc.v:130746.3-130747.83" + process $proc$libresoc.v:130746$5146 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:129011.3-129012.71" - process $proc$libresoc.v:129011$5102 + attribute \src "libresoc.v:130748.3-130749.71" + process $proc$libresoc.v:130748$5147 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:129013.3-129014.71" - process $proc$libresoc.v:129013$5103 + attribute \src "libresoc.v:130750.3-130751.71" + process $proc$libresoc.v:130750$5148 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:129015.3-129016.71" - process $proc$libresoc.v:129015$5104 + attribute \src "libresoc.v:130752.3-130753.71" + process $proc$libresoc.v:130752$5149 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:129017.3-129018.71" - process $proc$libresoc.v:129017$5105 + attribute \src "libresoc.v:130754.3-130755.71" + process $proc$libresoc.v:130754$5150 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:129019.3-129020.77" - process $proc$libresoc.v:129019$5106 + attribute \src "libresoc.v:130756.3-130757.77" + process $proc$libresoc.v:130756$5151 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:129021.3-129022.71" - process $proc$libresoc.v:129021$5107 + attribute \src "libresoc.v:130758.3-130759.71" + process $proc$libresoc.v:130758$5152 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:129023.3-129024.81" - process $proc$libresoc.v:129023$5108 + attribute \src "libresoc.v:130760.3-130761.81" + process $proc$libresoc.v:130760$5153 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:129025.3-129026.79" - process $proc$libresoc.v:129025$5109 + attribute \src "libresoc.v:130762.3-130763.79" + process $proc$libresoc.v:130762$5154 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:129027.3-129028.77" - process $proc$libresoc.v:129027$5110 + attribute \src "libresoc.v:130764.3-130765.77" + process $proc$libresoc.v:130764$5155 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:129029.3-129030.83" - process $proc$libresoc.v:129029$5111 + attribute \src "libresoc.v:130766.3-130767.83" + process $proc$libresoc.v:130766$5156 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:129031.3-129032.75" - process $proc$libresoc.v:129031$5112 + attribute \src "libresoc.v:130768.3-130769.75" + process $proc$libresoc.v:130768$5157 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:129033.3-129034.77" - process $proc$libresoc.v:129033$5113 + attribute \src "libresoc.v:130770.3-130771.77" + process $proc$libresoc.v:130770$5158 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:129035.3-129036.75" - process $proc$libresoc.v:129035$5114 + attribute \src "libresoc.v:130772.3-130773.75" + process $proc$libresoc.v:130772$5159 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:129037.3-129038.67" - process $proc$libresoc.v:129037$5115 + attribute \src "libresoc.v:130774.3-130775.67" + process $proc$libresoc.v:130774$5160 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:129039.3-129040.39" - process $proc$libresoc.v:129039$5116 + attribute \src "libresoc.v:130776.3-130777.39" + process $proc$libresoc.v:130776$5161 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:129041.3-129042.39" - process $proc$libresoc.v:129041$5117 + attribute \src "libresoc.v:130778.3-130779.39" + process $proc$libresoc.v:130778$5162 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:129043.3-129044.39" - process $proc$libresoc.v:129043$5118 + attribute \src "libresoc.v:130780.3-130781.39" + process $proc$libresoc.v:130780$5163 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:129045.3-129046.39" - process $proc$libresoc.v:129045$5119 + attribute \src "libresoc.v:130782.3-130783.39" + process $proc$libresoc.v:130782$5164 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:129047.3-129048.39" - process $proc$libresoc.v:129047$5120 + attribute \src "libresoc.v:130784.3-130785.39" + process $proc$libresoc.v:130784$5165 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:129049.3-129050.39" - process $proc$libresoc.v:129049$5121 + attribute \src "libresoc.v:130786.3-130787.39" + process $proc$libresoc.v:130786$5166 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:129051.3-129052.39" - process $proc$libresoc.v:129051$5122 + attribute \src "libresoc.v:130788.3-130789.39" + process $proc$libresoc.v:130788$5167 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:129053.3-129054.39" - process $proc$libresoc.v:129053$5123 + attribute \src "libresoc.v:130790.3-130791.39" + process $proc$libresoc.v:130790$5168 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:129055.3-129056.41" - process $proc$libresoc.v:129055$5124 + attribute \src "libresoc.v:130792.3-130793.41" + process $proc$libresoc.v:130792$5169 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:129057.3-129058.41" - process $proc$libresoc.v:129057$5125 + attribute \src "libresoc.v:130794.3-130795.41" + process $proc$libresoc.v:130794$5170 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:129059.3-129060.37" - process $proc$libresoc.v:129059$5126 + attribute \src "libresoc.v:130796.3-130797.37" + process $proc$libresoc.v:130796$5171 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:129061.3-129062.40" - process $proc$libresoc.v:129061$5127 + attribute \src "libresoc.v:130798.3-130799.40" + process $proc$libresoc.v:130798$5172 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:129063.3-129064.25" - process $proc$libresoc.v:129063$5128 + attribute \src "libresoc.v:130800.3-130801.25" + process $proc$libresoc.v:130800$5173 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:129150.3-129159.6" - process $proc$libresoc.v:129150$5129 + attribute \src "libresoc.v:130887.3-130896.6" + process $proc$libresoc.v:130887$5174 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:129151.5-129151.29" + attribute \src "libresoc.v:130888.5-130888.29" switch \initial - attribute \src "libresoc.v:129151.9-129151.17" + attribute \src "libresoc.v:130888.9-130888.17" case 1'1 case end @@ -204696,14 +207147,14 @@ module \div0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:129160.3-129168.6" - process $proc$libresoc.v:129160$5130 + attribute \src "libresoc.v:130897.3-130905.6" + process $proc$libresoc.v:130897$5175 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$5131 $1\rok_l_s_rdok$next[0:0]$5132 - attribute \src "libresoc.v:129161.5-129161.29" + assign $0\rok_l_s_rdok$next[0:0]$5176 $1\rok_l_s_rdok$next[0:0]$5177 + attribute \src "libresoc.v:130898.5-130898.29" switch \initial - attribute \src "libresoc.v:129161.9-129161.17" + attribute \src "libresoc.v:130898.9-130898.17" case 1'1 case end @@ -204712,21 +207163,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$5132 1'0 + assign $1\rok_l_s_rdok$next[0:0]$5177 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$5132 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$5177 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5131 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5176 end - attribute \src "libresoc.v:129169.3-129177.6" - process $proc$libresoc.v:129169$5133 + attribute \src "libresoc.v:130906.3-130914.6" + process $proc$libresoc.v:130906$5178 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$5134 $1\rok_l_r_rdok$next[0:0]$5135 - attribute \src "libresoc.v:129170.5-129170.29" + assign $0\rok_l_r_rdok$next[0:0]$5179 $1\rok_l_r_rdok$next[0:0]$5180 + attribute \src "libresoc.v:130907.5-130907.29" switch \initial - attribute \src "libresoc.v:129170.9-129170.17" + attribute \src "libresoc.v:130907.9-130907.17" case 1'1 case end @@ -204735,21 +207186,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$5135 1'1 + assign $1\rok_l_r_rdok$next[0:0]$5180 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$5135 \$64 + assign $1\rok_l_r_rdok$next[0:0]$5180 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5134 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5179 end - attribute \src "libresoc.v:129178.3-129186.6" - process $proc$libresoc.v:129178$5136 + attribute \src "libresoc.v:130915.3-130923.6" + process $proc$libresoc.v:130915$5181 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$5137 $1\rst_l_s_rst$next[0:0]$5138 - attribute \src "libresoc.v:129179.5-129179.29" + assign $0\rst_l_s_rst$next[0:0]$5182 $1\rst_l_s_rst$next[0:0]$5183 + attribute \src "libresoc.v:130916.5-130916.29" switch \initial - attribute \src "libresoc.v:129179.9-129179.17" + attribute \src "libresoc.v:130916.9-130916.17" case 1'1 case end @@ -204758,21 +207209,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$5138 1'0 + assign $1\rst_l_s_rst$next[0:0]$5183 1'0 case - assign $1\rst_l_s_rst$next[0:0]$5138 \all_rd + assign $1\rst_l_s_rst$next[0:0]$5183 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5137 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5182 end - attribute \src "libresoc.v:129187.3-129195.6" - process $proc$libresoc.v:129187$5139 + attribute \src "libresoc.v:130924.3-130932.6" + process $proc$libresoc.v:130924$5184 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$5140 $1\rst_l_r_rst$next[0:0]$5141 - attribute \src "libresoc.v:129188.5-129188.29" + assign $0\rst_l_r_rst$next[0:0]$5185 $1\rst_l_r_rst$next[0:0]$5186 + attribute \src "libresoc.v:130925.5-130925.29" switch \initial - attribute \src "libresoc.v:129188.9-129188.17" + attribute \src "libresoc.v:130925.9-130925.17" case 1'1 case end @@ -204781,21 +207232,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$5141 1'1 + assign $1\rst_l_r_rst$next[0:0]$5186 1'1 case - assign $1\rst_l_r_rst$next[0:0]$5141 \rst_r + assign $1\rst_l_r_rst$next[0:0]$5186 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5140 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5185 end - attribute \src "libresoc.v:129196.3-129204.6" - process $proc$libresoc.v:129196$5142 + attribute \src "libresoc.v:130933.3-130941.6" + process $proc$libresoc.v:130933$5187 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$5143 $1\opc_l_s_opc$next[0:0]$5144 - attribute \src "libresoc.v:129197.5-129197.29" + assign $0\opc_l_s_opc$next[0:0]$5188 $1\opc_l_s_opc$next[0:0]$5189 + attribute \src "libresoc.v:130934.5-130934.29" switch \initial - attribute \src "libresoc.v:129197.9-129197.17" + attribute \src "libresoc.v:130934.9-130934.17" case 1'1 case end @@ -204804,21 +207255,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$5144 1'0 + assign $1\opc_l_s_opc$next[0:0]$5189 1'0 case - assign $1\opc_l_s_opc$next[0:0]$5144 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$5189 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5143 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5188 end - attribute \src "libresoc.v:129205.3-129213.6" - process $proc$libresoc.v:129205$5145 + attribute \src "libresoc.v:130942.3-130950.6" + process $proc$libresoc.v:130942$5190 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$5146 $1\opc_l_r_opc$next[0:0]$5147 - attribute \src "libresoc.v:129206.5-129206.29" + assign $0\opc_l_r_opc$next[0:0]$5191 $1\opc_l_r_opc$next[0:0]$5192 + attribute \src "libresoc.v:130943.5-130943.29" switch \initial - attribute \src "libresoc.v:129206.9-129206.17" + attribute \src "libresoc.v:130943.9-130943.17" case 1'1 case end @@ -204827,21 +207278,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$5147 1'1 + assign $1\opc_l_r_opc$next[0:0]$5192 1'1 case - assign $1\opc_l_r_opc$next[0:0]$5147 \req_done + assign $1\opc_l_r_opc$next[0:0]$5192 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5146 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5191 end - attribute \src "libresoc.v:129214.3-129222.6" - process $proc$libresoc.v:129214$5148 + attribute \src "libresoc.v:130951.3-130959.6" + process $proc$libresoc.v:130951$5193 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$5149 $1\src_l_s_src$next[2:0]$5150 - attribute \src "libresoc.v:129215.5-129215.29" + assign $0\src_l_s_src$next[2:0]$5194 $1\src_l_s_src$next[2:0]$5195 + attribute \src "libresoc.v:130952.5-130952.29" switch \initial - attribute \src "libresoc.v:129215.9-129215.17" + attribute \src "libresoc.v:130952.9-130952.17" case 1'1 case end @@ -204850,21 +207301,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$5150 3'000 + assign $1\src_l_s_src$next[2:0]$5195 3'000 case - assign $1\src_l_s_src$next[2:0]$5150 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$5195 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5149 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5194 end - attribute \src "libresoc.v:129223.3-129231.6" - process $proc$libresoc.v:129223$5151 + attribute \src "libresoc.v:130960.3-130968.6" + process $proc$libresoc.v:130960$5196 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$5152 $1\src_l_r_src$next[2:0]$5153 - attribute \src "libresoc.v:129224.5-129224.29" + assign $0\src_l_r_src$next[2:0]$5197 $1\src_l_r_src$next[2:0]$5198 + attribute \src "libresoc.v:130961.5-130961.29" switch \initial - attribute \src "libresoc.v:129224.9-129224.17" + attribute \src "libresoc.v:130961.9-130961.17" case 1'1 case end @@ -204873,21 +207324,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$5153 3'111 + assign $1\src_l_r_src$next[2:0]$5198 3'111 case - assign $1\src_l_r_src$next[2:0]$5153 \reset_r + assign $1\src_l_r_src$next[2:0]$5198 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5152 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5197 end - attribute \src "libresoc.v:129232.3-129240.6" - process $proc$libresoc.v:129232$5154 + attribute \src "libresoc.v:130969.3-130977.6" + process $proc$libresoc.v:130969$5199 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$5155 $1\req_l_s_req$next[3:0]$5156 - attribute \src "libresoc.v:129233.5-129233.29" + assign $0\req_l_s_req$next[3:0]$5200 $1\req_l_s_req$next[3:0]$5201 + attribute \src "libresoc.v:130970.5-130970.29" switch \initial - attribute \src "libresoc.v:129233.9-129233.17" + attribute \src "libresoc.v:130970.9-130970.17" case 1'1 case end @@ -204896,21 +207347,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$5156 4'0000 + assign $1\req_l_s_req$next[3:0]$5201 4'0000 case - assign $1\req_l_s_req$next[3:0]$5156 \$66 + assign $1\req_l_s_req$next[3:0]$5201 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5155 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5200 end - attribute \src "libresoc.v:129241.3-129249.6" - process $proc$libresoc.v:129241$5157 + attribute \src "libresoc.v:130978.3-130986.6" + process $proc$libresoc.v:130978$5202 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$5158 $1\req_l_r_req$next[3:0]$5159 - attribute \src "libresoc.v:129242.5-129242.29" + assign $0\req_l_r_req$next[3:0]$5203 $1\req_l_r_req$next[3:0]$5204 + attribute \src "libresoc.v:130979.5-130979.29" switch \initial - attribute \src "libresoc.v:129242.9-129242.17" + attribute \src "libresoc.v:130979.9-130979.17" case 1'1 case end @@ -204919,15 +207370,15 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$5159 4'1111 + assign $1\req_l_r_req$next[3:0]$5204 4'1111 case - assign $1\req_l_r_req$next[3:0]$5159 \$68 + assign $1\req_l_r_req$next[3:0]$5204 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5158 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5203 end - attribute \src "libresoc.v:129250.3-129288.6" - process $proc$libresoc.v:129250$5160 + attribute \src "libresoc.v:130987.3-131025.6" + process $proc$libresoc.v:130987$5205 assign { } { } assign { } { } assign { } { } @@ -204964,33 +207415,33 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$5161 $1\alu_div0_logical_op__data_len$next[3:0]$5179 - assign $0\alu_div0_logical_op__fn_unit$next[12:0]$5162 $1\alu_div0_logical_op__fn_unit$next[12:0]$5180 + assign $0\alu_div0_logical_op__data_len$next[3:0]$5206 $1\alu_div0_logical_op__data_len$next[3:0]$5224 + assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$5165 $1\alu_div0_logical_op__input_carry$next[1:0]$5183 - assign $0\alu_div0_logical_op__insn$next[31:0]$5166 $1\alu_div0_logical_op__insn$next[31:0]$5184 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$5167 $1\alu_div0_logical_op__insn_type$next[6:0]$5185 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$5168 $1\alu_div0_logical_op__invert_in$next[0:0]$5186 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$5169 $1\alu_div0_logical_op__invert_out$next[0:0]$5187 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5170 $1\alu_div0_logical_op__is_32bit$next[0:0]$5188 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$5171 $1\alu_div0_logical_op__is_signed$next[0:0]$5189 + assign $0\alu_div0_logical_op__input_carry$next[1:0]$5210 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 + assign $0\alu_div0_logical_op__insn$next[31:0]$5211 $1\alu_div0_logical_op__insn$next[31:0]$5229 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$5212 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$5213 $1\alu_div0_logical_op__invert_in$next[0:0]$5231 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$5214 $1\alu_div0_logical_op__invert_out$next[0:0]$5232 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$5216 $1\alu_div0_logical_op__is_signed$next[0:0]$5234 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$5174 $1\alu_div0_logical_op__output_carry$next[0:0]$5192 + assign $0\alu_div0_logical_op__output_carry$next[0:0]$5219 $1\alu_div0_logical_op__output_carry$next[0:0]$5237 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5177 $1\alu_div0_logical_op__write_cr0$next[0:0]$5195 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$5178 $1\alu_div0_logical_op__zero_a$next[0:0]$5196 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5163 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5197 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5164 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5198 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5172 $2\alu_div0_logical_op__oe__oe$next[0:0]$5199 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5173 $2\alu_div0_logical_op__oe__ok$next[0:0]$5200 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5175 $2\alu_div0_logical_op__rc__ok$next[0:0]$5201 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5176 $2\alu_div0_logical_op__rc__rc$next[0:0]$5202 - attribute \src "libresoc.v:129251.5-129251.29" + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$5223 $1\alu_div0_logical_op__zero_a$next[0:0]$5241 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 + attribute \src "libresoc.v:130988.5-130988.29" switch \initial - attribute \src "libresoc.v:129251.9-129251.17" + attribute \src "libresoc.v:130988.9-130988.17" case 1'1 case end @@ -205016,26 +207467,26 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$5184 $1\alu_div0_logical_op__data_len$next[3:0]$5179 $1\alu_div0_logical_op__is_signed$next[0:0]$5189 $1\alu_div0_logical_op__is_32bit$next[0:0]$5188 $1\alu_div0_logical_op__output_carry$next[0:0]$5192 $1\alu_div0_logical_op__write_cr0$next[0:0]$5195 $1\alu_div0_logical_op__invert_out$next[0:0]$5187 $1\alu_div0_logical_op__input_carry$next[1:0]$5183 $1\alu_div0_logical_op__zero_a$next[0:0]$5196 $1\alu_div0_logical_op__invert_in$next[0:0]$5186 $1\alu_div0_logical_op__oe__ok$next[0:0]$5191 $1\alu_div0_logical_op__oe__oe$next[0:0]$5190 $1\alu_div0_logical_op__rc__ok$next[0:0]$5193 $1\alu_div0_logical_op__rc__rc$next[0:0]$5194 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5182 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5181 $1\alu_div0_logical_op__fn_unit$next[12:0]$5180 $1\alu_div0_logical_op__insn_type$next[6:0]$5185 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + assign { $1\alu_div0_logical_op__insn$next[31:0]$5229 $1\alu_div0_logical_op__data_len$next[3:0]$5224 $1\alu_div0_logical_op__is_signed$next[0:0]$5234 $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 $1\alu_div0_logical_op__output_carry$next[0:0]$5237 $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 $1\alu_div0_logical_op__invert_out$next[0:0]$5232 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 $1\alu_div0_logical_op__zero_a$next[0:0]$5241 $1\alu_div0_logical_op__invert_in$next[0:0]$5231 $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } case - assign $1\alu_div0_logical_op__data_len$next[3:0]$5179 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[12:0]$5180 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5181 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5182 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$5183 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$5184 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$5185 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$5186 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$5187 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5188 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$5189 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5190 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5191 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$5192 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5193 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5194 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5195 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$5196 \alu_div0_logical_op__zero_a + assign $1\alu_div0_logical_op__data_len$next[3:0]$5224 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$5228 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$5229 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$5230 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$5231 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$5232 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$5234 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$5237 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$5241 \alu_div0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -205047,54 +207498,54 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5197 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5198 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5202 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5201 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5199 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5200 1'0 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 1'0 case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5197 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5181 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5198 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5182 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5199 $1\alu_div0_logical_op__oe__oe$next[0:0]$5190 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5200 $1\alu_div0_logical_op__oe__ok$next[0:0]$5191 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5201 $1\alu_div0_logical_op__rc__ok$next[0:0]$5193 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5202 $1\alu_div0_logical_op__rc__rc$next[0:0]$5194 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 end sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5161 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[12:0]$5162 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5163 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5164 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5165 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5166 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5167 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5168 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5169 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5170 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5171 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5172 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5173 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5174 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5175 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5176 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5177 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5178 + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5206 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5210 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5211 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5212 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5213 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5214 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5216 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5219 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5223 end - attribute \src "libresoc.v:129289.3-129310.6" - process $proc$libresoc.v:129289$5203 + attribute \src "libresoc.v:131026.3-131047.6" + process $proc$libresoc.v:131026$5248 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$5204 $2\data_r0__o$next[63:0]$5208 + assign $0\data_r0__o$next[63:0]$5249 $2\data_r0__o$next[63:0]$5253 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$5205 $3\data_r0__o_ok$next[0:0]$5210 - attribute \src "libresoc.v:129290.5-129290.29" + assign $0\data_r0__o_ok$next[0:0]$5250 $3\data_r0__o_ok$next[0:0]$5255 + attribute \src "libresoc.v:131027.5-131027.29" switch \initial - attribute \src "libresoc.v:129290.9-129290.17" + attribute \src "libresoc.v:131027.9-131027.17" case 1'1 case end @@ -205104,10 +207555,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$5207 $1\data_r0__o$next[63:0]$5206 } { \o_ok \alu_div0_o } + assign { $1\data_r0__o_ok$next[0:0]$5252 $1\data_r0__o$next[63:0]$5251 } { \o_ok \alu_div0_o } case - assign $1\data_r0__o$next[63:0]$5206 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$5207 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$5251 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5252 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -205115,38 +207566,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$5209 $2\data_r0__o$next[63:0]$5208 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$5254 $2\data_r0__o$next[63:0]$5253 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$5208 $1\data_r0__o$next[63:0]$5206 - assign $2\data_r0__o_ok$next[0:0]$5209 $1\data_r0__o_ok$next[0:0]$5207 + assign $2\data_r0__o$next[63:0]$5253 $1\data_r0__o$next[63:0]$5251 + assign $2\data_r0__o_ok$next[0:0]$5254 $1\data_r0__o_ok$next[0:0]$5252 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$5210 1'0 + assign $3\data_r0__o_ok$next[0:0]$5255 1'0 case - assign $3\data_r0__o_ok$next[0:0]$5210 $2\data_r0__o_ok$next[0:0]$5209 + assign $3\data_r0__o_ok$next[0:0]$5255 $2\data_r0__o_ok$next[0:0]$5254 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$5204 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5205 + update \data_r0__o$next $0\data_r0__o$next[63:0]$5249 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5250 end - attribute \src "libresoc.v:129311.3-129332.6" - process $proc$libresoc.v:129311$5211 + attribute \src "libresoc.v:131048.3-131069.6" + process $proc$libresoc.v:131048$5256 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$5212 $2\data_r1__cr_a$next[3:0]$5216 + assign $0\data_r1__cr_a$next[3:0]$5257 $2\data_r1__cr_a$next[3:0]$5261 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$5213 $3\data_r1__cr_a_ok$next[0:0]$5218 - attribute \src "libresoc.v:129312.5-129312.29" + assign $0\data_r1__cr_a_ok$next[0:0]$5258 $3\data_r1__cr_a_ok$next[0:0]$5263 + attribute \src "libresoc.v:131049.5-131049.29" switch \initial - attribute \src "libresoc.v:129312.9-129312.17" + attribute \src "libresoc.v:131049.9-131049.17" case 1'1 case end @@ -205156,10 +207607,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$5215 $1\data_r1__cr_a$next[3:0]$5214 } { \cr_a_ok \alu_div0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$5260 $1\data_r1__cr_a$next[3:0]$5259 } { \cr_a_ok \alu_div0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$5214 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$5215 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$5259 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5260 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -205167,38 +207618,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$5217 $2\data_r1__cr_a$next[3:0]$5216 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$5262 $2\data_r1__cr_a$next[3:0]$5261 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$5216 $1\data_r1__cr_a$next[3:0]$5214 - assign $2\data_r1__cr_a_ok$next[0:0]$5217 $1\data_r1__cr_a_ok$next[0:0]$5215 + assign $2\data_r1__cr_a$next[3:0]$5261 $1\data_r1__cr_a$next[3:0]$5259 + assign $2\data_r1__cr_a_ok$next[0:0]$5262 $1\data_r1__cr_a_ok$next[0:0]$5260 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$5218 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$5263 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$5218 $2\data_r1__cr_a_ok$next[0:0]$5217 + assign $3\data_r1__cr_a_ok$next[0:0]$5263 $2\data_r1__cr_a_ok$next[0:0]$5262 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5212 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5213 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5257 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5258 end - attribute \src "libresoc.v:129333.3-129354.6" - process $proc$libresoc.v:129333$5219 + attribute \src "libresoc.v:131070.3-131091.6" + process $proc$libresoc.v:131070$5264 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$5220 $2\data_r2__xer_ov$next[1:0]$5224 + assign $0\data_r2__xer_ov$next[1:0]$5265 $2\data_r2__xer_ov$next[1:0]$5269 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$5221 $3\data_r2__xer_ov_ok$next[0:0]$5226 - attribute \src "libresoc.v:129334.5-129334.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$5266 $3\data_r2__xer_ov_ok$next[0:0]$5271 + attribute \src "libresoc.v:131071.5-131071.29" switch \initial - attribute \src "libresoc.v:129334.9-129334.17" + attribute \src "libresoc.v:131071.9-131071.17" case 1'1 case end @@ -205208,10 +207659,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$5223 $1\data_r2__xer_ov$next[1:0]$5222 } { \xer_ov_ok \alu_div0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$5268 $1\data_r2__xer_ov$next[1:0]$5267 } { \xer_ov_ok \alu_div0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$5222 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$5223 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$5267 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$5268 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -205219,38 +207670,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$5225 $2\data_r2__xer_ov$next[1:0]$5224 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$5270 $2\data_r2__xer_ov$next[1:0]$5269 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$5224 $1\data_r2__xer_ov$next[1:0]$5222 - assign $2\data_r2__xer_ov_ok$next[0:0]$5225 $1\data_r2__xer_ov_ok$next[0:0]$5223 + assign $2\data_r2__xer_ov$next[1:0]$5269 $1\data_r2__xer_ov$next[1:0]$5267 + assign $2\data_r2__xer_ov_ok$next[0:0]$5270 $1\data_r2__xer_ov_ok$next[0:0]$5268 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$5226 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$5271 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$5226 $2\data_r2__xer_ov_ok$next[0:0]$5225 + assign $3\data_r2__xer_ov_ok$next[0:0]$5271 $2\data_r2__xer_ov_ok$next[0:0]$5270 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5220 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5221 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5265 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5266 end - attribute \src "libresoc.v:129355.3-129376.6" - process $proc$libresoc.v:129355$5227 + attribute \src "libresoc.v:131092.3-131113.6" + process $proc$libresoc.v:131092$5272 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$5228 $2\data_r3__xer_so$next[0:0]$5232 + assign $0\data_r3__xer_so$next[0:0]$5273 $2\data_r3__xer_so$next[0:0]$5277 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$5229 $3\data_r3__xer_so_ok$next[0:0]$5234 - attribute \src "libresoc.v:129356.5-129356.29" + assign $0\data_r3__xer_so_ok$next[0:0]$5274 $3\data_r3__xer_so_ok$next[0:0]$5279 + attribute \src "libresoc.v:131093.5-131093.29" switch \initial - attribute \src "libresoc.v:129356.9-129356.17" + attribute \src "libresoc.v:131093.9-131093.17" case 1'1 case end @@ -205260,10 +207711,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$5231 $1\data_r3__xer_so$next[0:0]$5230 } { \xer_so_ok \alu_div0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$5276 $1\data_r3__xer_so$next[0:0]$5275 } { \xer_so_ok \alu_div0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$5230 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$5231 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$5275 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$5276 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -205271,32 +207722,32 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$5233 $2\data_r3__xer_so$next[0:0]$5232 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$5278 $2\data_r3__xer_so$next[0:0]$5277 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$5232 $1\data_r3__xer_so$next[0:0]$5230 - assign $2\data_r3__xer_so_ok$next[0:0]$5233 $1\data_r3__xer_so_ok$next[0:0]$5231 + assign $2\data_r3__xer_so$next[0:0]$5277 $1\data_r3__xer_so$next[0:0]$5275 + assign $2\data_r3__xer_so_ok$next[0:0]$5278 $1\data_r3__xer_so_ok$next[0:0]$5276 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$5234 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$5279 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$5234 $2\data_r3__xer_so_ok$next[0:0]$5233 + assign $3\data_r3__xer_so_ok$next[0:0]$5279 $2\data_r3__xer_so_ok$next[0:0]$5278 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5228 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5229 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5273 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5274 end - attribute \src "libresoc.v:129377.3-129386.6" - process $proc$libresoc.v:129377$5235 + attribute \src "libresoc.v:131114.3-131123.6" + process $proc$libresoc.v:131114$5280 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$5236 $1\src_r0$next[63:0]$5237 - attribute \src "libresoc.v:129378.5-129378.29" + assign $0\src_r0$next[63:0]$5281 $1\src_r0$next[63:0]$5282 + attribute \src "libresoc.v:131115.5-131115.29" switch \initial - attribute \src "libresoc.v:129378.9-129378.17" + attribute \src "libresoc.v:131115.9-131115.17" case 1'1 case end @@ -205305,21 +207756,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$5237 \src_or_imm + assign $1\src_r0$next[63:0]$5282 \src_or_imm case - assign $1\src_r0$next[63:0]$5237 \src_r0 + assign $1\src_r0$next[63:0]$5282 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$5236 + update \src_r0$next $0\src_r0$next[63:0]$5281 end - attribute \src "libresoc.v:129387.3-129396.6" - process $proc$libresoc.v:129387$5238 + attribute \src "libresoc.v:131124.3-131133.6" + process $proc$libresoc.v:131124$5283 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$5239 $1\src_r1$next[63:0]$5240 - attribute \src "libresoc.v:129388.5-129388.29" + assign $0\src_r1$next[63:0]$5284 $1\src_r1$next[63:0]$5285 + attribute \src "libresoc.v:131125.5-131125.29" switch \initial - attribute \src "libresoc.v:129388.9-129388.17" + attribute \src "libresoc.v:131125.9-131125.17" case 1'1 case end @@ -205328,21 +207779,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$5240 \src_or_imm$85 + assign $1\src_r1$next[63:0]$5285 \src_or_imm$85 case - assign $1\src_r1$next[63:0]$5240 \src_r1 + assign $1\src_r1$next[63:0]$5285 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$5239 + update \src_r1$next $0\src_r1$next[63:0]$5284 end - attribute \src "libresoc.v:129397.3-129406.6" - process $proc$libresoc.v:129397$5241 + attribute \src "libresoc.v:131134.3-131143.6" + process $proc$libresoc.v:131134$5286 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$5242 $1\src_r2$next[0:0]$5243 - attribute \src "libresoc.v:129398.5-129398.29" + assign $0\src_r2$next[0:0]$5287 $1\src_r2$next[0:0]$5288 + attribute \src "libresoc.v:131135.5-131135.29" switch \initial - attribute \src "libresoc.v:129398.9-129398.17" + attribute \src "libresoc.v:131135.9-131135.17" case 1'1 case end @@ -205351,21 +207802,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$5243 \src3_i + assign $1\src_r2$next[0:0]$5288 \src3_i case - assign $1\src_r2$next[0:0]$5243 \src_r2 + assign $1\src_r2$next[0:0]$5288 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$5242 + update \src_r2$next $0\src_r2$next[0:0]$5287 end - attribute \src "libresoc.v:129407.3-129415.6" - process $proc$libresoc.v:129407$5244 + attribute \src "libresoc.v:131144.3-131152.6" + process $proc$libresoc.v:131144$5289 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$5245 $1\alui_l_r_alui$next[0:0]$5246 - attribute \src "libresoc.v:129408.5-129408.29" + assign $0\alui_l_r_alui$next[0:0]$5290 $1\alui_l_r_alui$next[0:0]$5291 + attribute \src "libresoc.v:131145.5-131145.29" switch \initial - attribute \src "libresoc.v:129408.9-129408.17" + attribute \src "libresoc.v:131145.9-131145.17" case 1'1 case end @@ -205374,21 +207825,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$5246 1'1 + assign $1\alui_l_r_alui$next[0:0]$5291 1'1 case - assign $1\alui_l_r_alui$next[0:0]$5246 \$94 + assign $1\alui_l_r_alui$next[0:0]$5291 \$94 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5245 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5290 end - attribute \src "libresoc.v:129416.3-129424.6" - process $proc$libresoc.v:129416$5247 + attribute \src "libresoc.v:131153.3-131161.6" + process $proc$libresoc.v:131153$5292 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$5248 $1\alu_l_r_alu$next[0:0]$5249 - attribute \src "libresoc.v:129417.5-129417.29" + assign $0\alu_l_r_alu$next[0:0]$5293 $1\alu_l_r_alu$next[0:0]$5294 + attribute \src "libresoc.v:131154.5-131154.29" switch \initial - attribute \src "libresoc.v:129417.9-129417.17" + attribute \src "libresoc.v:131154.9-131154.17" case 1'1 case end @@ -205397,21 +207848,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$5249 1'1 + assign $1\alu_l_r_alu$next[0:0]$5294 1'1 case - assign $1\alu_l_r_alu$next[0:0]$5249 \$96 + assign $1\alu_l_r_alu$next[0:0]$5294 \$96 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5248 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5293 end - attribute \src "libresoc.v:129425.3-129434.6" - process $proc$libresoc.v:129425$5250 + attribute \src "libresoc.v:131162.3-131171.6" + process $proc$libresoc.v:131162$5295 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:129426.5-129426.29" + attribute \src "libresoc.v:131163.5-131163.29" switch \initial - attribute \src "libresoc.v:129426.9-129426.17" + attribute \src "libresoc.v:131163.9-131163.17" case 1'1 case end @@ -205427,14 +207878,14 @@ module \div0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:129435.3-129444.6" - process $proc$libresoc.v:129435$5251 + attribute \src "libresoc.v:131172.3-131181.6" + process $proc$libresoc.v:131172$5296 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:129436.5-129436.29" + attribute \src "libresoc.v:131173.5-131173.29" switch \initial - attribute \src "libresoc.v:129436.9-129436.17" + attribute \src "libresoc.v:131173.9-131173.17" case 1'1 case end @@ -205450,14 +207901,14 @@ module \div0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:129445.3-129454.6" - process $proc$libresoc.v:129445$5252 + attribute \src "libresoc.v:131182.3-131191.6" + process $proc$libresoc.v:131182$5297 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:129446.5-129446.29" + attribute \src "libresoc.v:131183.5-131183.29" switch \initial - attribute \src "libresoc.v:129446.9-129446.17" + attribute \src "libresoc.v:131183.9-131183.17" case 1'1 case end @@ -205473,14 +207924,14 @@ module \div0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:129455.3-129464.6" - process $proc$libresoc.v:129455$5253 + attribute \src "libresoc.v:131192.3-131201.6" + process $proc$libresoc.v:131192$5298 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:129456.5-129456.29" + attribute \src "libresoc.v:131193.5-131193.29" switch \initial - attribute \src "libresoc.v:129456.9-129456.17" + attribute \src "libresoc.v:131193.9-131193.17" case 1'1 case end @@ -205496,14 +207947,14 @@ module \div0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:129465.3-129473.6" - process $proc$libresoc.v:129465$5254 + attribute \src "libresoc.v:131202.3-131210.6" + process $proc$libresoc.v:131202$5299 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$5255 $1\prev_wr_go$next[3:0]$5256 - attribute \src "libresoc.v:129466.5-129466.29" + assign $0\prev_wr_go$next[3:0]$5300 $1\prev_wr_go$next[3:0]$5301 + attribute \src "libresoc.v:131203.5-131203.29" switch \initial - attribute \src "libresoc.v:129466.9-129466.17" + attribute \src "libresoc.v:131203.9-131203.17" case 1'1 case end @@ -205512,76 +207963,76 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$5256 4'0000 - case - assign $1\prev_wr_go$next[3:0]$5256 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5255 - end - connect \$100 $not$libresoc.v:128914$5022_Y - connect \$102 $not$libresoc.v:128915$5023_Y - connect \$104 $and$libresoc.v:128916$5024_Y - connect \$106 $not$libresoc.v:128917$5025_Y - connect \$108 $and$libresoc.v:128918$5026_Y - connect \$10 $and$libresoc.v:128919$5027_Y - connect \$110 $and$libresoc.v:128920$5028_Y - connect \$112 $and$libresoc.v:128921$5029_Y - connect \$114 $and$libresoc.v:128922$5030_Y - connect \$116 $and$libresoc.v:128923$5031_Y - connect \$118 $and$libresoc.v:128924$5032_Y - connect \$120 $and$libresoc.v:128925$5033_Y - connect \$122 $and$libresoc.v:128926$5034_Y - connect \$124 $and$libresoc.v:128927$5035_Y - connect \$126 $and$libresoc.v:128928$5036_Y - connect \$128 $and$libresoc.v:128929$5037_Y - connect \$12 $not$libresoc.v:128930$5038_Y - connect \$14 $and$libresoc.v:128931$5039_Y - connect \$16 $not$libresoc.v:128932$5040_Y - connect \$18 $and$libresoc.v:128933$5041_Y - connect \$20 $and$libresoc.v:128934$5042_Y - connect \$24 $not$libresoc.v:128935$5043_Y - connect \$26 $and$libresoc.v:128936$5044_Y - connect \$23 $reduce_or$libresoc.v:128937$5045_Y - connect \$22 $not$libresoc.v:128938$5046_Y - connect \$2 $and$libresoc.v:128939$5047_Y - connect \$30 $and$libresoc.v:128940$5048_Y - connect \$32 $reduce_or$libresoc.v:128941$5049_Y - connect \$34 $reduce_or$libresoc.v:128942$5050_Y - connect \$36 $or$libresoc.v:128943$5051_Y - connect \$38 $not$libresoc.v:128944$5052_Y - connect \$40 $and$libresoc.v:128945$5053_Y - connect \$42 $and$libresoc.v:128946$5054_Y - connect \$44 $eq$libresoc.v:128947$5055_Y - connect \$46 $and$libresoc.v:128948$5056_Y - connect \$48 $eq$libresoc.v:128949$5057_Y - connect \$50 $and$libresoc.v:128950$5058_Y - connect \$52 $and$libresoc.v:128951$5059_Y - connect \$54 $and$libresoc.v:128952$5060_Y - connect \$56 $or$libresoc.v:128953$5061_Y - connect \$58 $or$libresoc.v:128954$5062_Y - connect \$5 $not$libresoc.v:128955$5063_Y - connect \$60 $or$libresoc.v:128956$5064_Y - connect \$62 $or$libresoc.v:128957$5065_Y - connect \$64 $and$libresoc.v:128958$5066_Y - connect \$66 $and$libresoc.v:128959$5067_Y - connect \$68 $or$libresoc.v:128960$5068_Y - connect \$70 $and$libresoc.v:128961$5069_Y - connect \$72 $and$libresoc.v:128962$5070_Y - connect \$74 $and$libresoc.v:128963$5071_Y - connect \$76 $and$libresoc.v:128964$5072_Y - connect \$78 $ternary$libresoc.v:128965$5073_Y - connect \$7 $or$libresoc.v:128966$5074_Y - connect \$80 $ternary$libresoc.v:128967$5075_Y - connect \$83 $ternary$libresoc.v:128968$5076_Y - connect \$86 $ternary$libresoc.v:128969$5077_Y - connect \$88 $ternary$libresoc.v:128970$5078_Y - connect \$4 $reduce_and$libresoc.v:128971$5079_Y - connect \$90 $ternary$libresoc.v:128972$5080_Y - connect \$92 $ternary$libresoc.v:128973$5081_Y - connect \$94 $and$libresoc.v:128974$5082_Y - connect \$96 $and$libresoc.v:128975$5083_Y - connect \$98 $and$libresoc.v:128976$5084_Y + assign $1\prev_wr_go$next[3:0]$5301 4'0000 + case + assign $1\prev_wr_go$next[3:0]$5301 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5300 + end + connect \$100 $not$libresoc.v:130651$5067_Y + connect \$102 $not$libresoc.v:130652$5068_Y + connect \$104 $and$libresoc.v:130653$5069_Y + connect \$106 $not$libresoc.v:130654$5070_Y + connect \$108 $and$libresoc.v:130655$5071_Y + connect \$10 $and$libresoc.v:130656$5072_Y + connect \$110 $and$libresoc.v:130657$5073_Y + connect \$112 $and$libresoc.v:130658$5074_Y + connect \$114 $and$libresoc.v:130659$5075_Y + connect \$116 $and$libresoc.v:130660$5076_Y + connect \$118 $and$libresoc.v:130661$5077_Y + connect \$120 $and$libresoc.v:130662$5078_Y + connect \$122 $and$libresoc.v:130663$5079_Y + connect \$124 $and$libresoc.v:130664$5080_Y + connect \$126 $and$libresoc.v:130665$5081_Y + connect \$128 $and$libresoc.v:130666$5082_Y + connect \$12 $not$libresoc.v:130667$5083_Y + connect \$14 $and$libresoc.v:130668$5084_Y + connect \$16 $not$libresoc.v:130669$5085_Y + connect \$18 $and$libresoc.v:130670$5086_Y + connect \$20 $and$libresoc.v:130671$5087_Y + connect \$24 $not$libresoc.v:130672$5088_Y + connect \$26 $and$libresoc.v:130673$5089_Y + connect \$23 $reduce_or$libresoc.v:130674$5090_Y + connect \$22 $not$libresoc.v:130675$5091_Y + connect \$2 $and$libresoc.v:130676$5092_Y + connect \$30 $and$libresoc.v:130677$5093_Y + connect \$32 $reduce_or$libresoc.v:130678$5094_Y + connect \$34 $reduce_or$libresoc.v:130679$5095_Y + connect \$36 $or$libresoc.v:130680$5096_Y + connect \$38 $not$libresoc.v:130681$5097_Y + connect \$40 $and$libresoc.v:130682$5098_Y + connect \$42 $and$libresoc.v:130683$5099_Y + connect \$44 $eq$libresoc.v:130684$5100_Y + connect \$46 $and$libresoc.v:130685$5101_Y + connect \$48 $eq$libresoc.v:130686$5102_Y + connect \$50 $and$libresoc.v:130687$5103_Y + connect \$52 $and$libresoc.v:130688$5104_Y + connect \$54 $and$libresoc.v:130689$5105_Y + connect \$56 $or$libresoc.v:130690$5106_Y + connect \$58 $or$libresoc.v:130691$5107_Y + connect \$5 $not$libresoc.v:130692$5108_Y + connect \$60 $or$libresoc.v:130693$5109_Y + connect \$62 $or$libresoc.v:130694$5110_Y + connect \$64 $and$libresoc.v:130695$5111_Y + connect \$66 $and$libresoc.v:130696$5112_Y + connect \$68 $or$libresoc.v:130697$5113_Y + connect \$70 $and$libresoc.v:130698$5114_Y + connect \$72 $and$libresoc.v:130699$5115_Y + connect \$74 $and$libresoc.v:130700$5116_Y + connect \$76 $and$libresoc.v:130701$5117_Y + connect \$78 $ternary$libresoc.v:130702$5118_Y + connect \$7 $or$libresoc.v:130703$5119_Y + connect \$80 $ternary$libresoc.v:130704$5120_Y + connect \$83 $ternary$libresoc.v:130705$5121_Y + connect \$86 $ternary$libresoc.v:130706$5122_Y + connect \$88 $ternary$libresoc.v:130707$5123_Y + connect \$4 $reduce_and$libresoc.v:130708$5124_Y + connect \$90 $ternary$libresoc.v:130709$5125_Y + connect \$92 $ternary$libresoc.v:130710$5126_Y + connect \$94 $and$libresoc.v:130711$5127_Y + connect \$96 $and$libresoc.v:130712$5128_Y + connect \$98 $and$libresoc.v:130713$5129_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 @@ -205615,7 +208066,7 @@ module \div0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:129510.1-129519.10" +attribute \src "libresoc.v:131247.1-131256.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" @@ -205629,37 +208080,37 @@ module \div_state_init connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end -attribute \src "libresoc.v:129523.1-129605.10" +attribute \src "libresoc.v:131260.1-131342.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next - attribute \src "libresoc.v:129524.7-129524.20" + attribute \src "libresoc.v:131261.7-131261.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129589.3-129600.6" + attribute \src "libresoc.v:131326.3-131337.6" wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:129577.3-129588.6" + attribute \src "libresoc.v:131314.3-131325.6" wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:129565.3-129576.6" + attribute \src "libresoc.v:131302.3-131313.6" wire width 128 $0\value[127:0] - attribute \src "libresoc.v:129589.3-129600.6" + attribute \src "libresoc.v:131326.3-131337.6" wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:129577.3-129588.6" + attribute \src "libresoc.v:131314.3-131325.6" wire width 7 $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:129565.3-129576.6" + attribute \src "libresoc.v:131302.3-131313.6" wire width 128 $1\value[127:0] - attribute \src "libresoc.v:129559.18-129559.106" - wire width 8 $add$libresoc.v:129559$5302_Y - attribute \src "libresoc.v:129560.18-129560.109" - wire $ge$libresoc.v:129560$5303_Y - attribute \src "libresoc.v:129564.17-129564.108" - wire $ge$libresoc.v:129564$5307_Y - attribute \src "libresoc.v:129563.17-129563.101" - wire $not$libresoc.v:129563$5306_Y - attribute \src "libresoc.v:129561.17-129561.101" - wire width 127 $sshl$libresoc.v:129561$5304_Y - attribute \src "libresoc.v:129562.17-129562.109" - wire width 129 $sub$libresoc.v:129562$5305_Y + attribute \src "libresoc.v:131296.18-131296.106" + wire width 8 $add$libresoc.v:131296$5347_Y + attribute \src "libresoc.v:131297.18-131297.109" + wire $ge$libresoc.v:131297$5348_Y + attribute \src "libresoc.v:131301.17-131301.108" + wire $ge$libresoc.v:131301$5352_Y + attribute \src "libresoc.v:131300.17-131300.101" + wire $not$libresoc.v:131300$5351_Y + attribute \src "libresoc.v:131298.17-131298.101" + wire width 127 $sshl$libresoc.v:131298$5349_Y + attribute \src "libresoc.v:131299.17-131299.109" + wire width 129 $sub$libresoc.v:131299$5350_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" @@ -205684,7 +208135,7 @@ module \div_state_next wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:129524.7-129524.15" + attribute \src "libresoc.v:131261.7-131261.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit @@ -205695,7 +208146,7 @@ module \div_state_next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:129559$5302 + cell $add $add$libresoc.v:131296$5347 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -205703,10 +208154,10 @@ module \div_state_next parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 - connect \Y $add$libresoc.v:129559$5302_Y + connect \Y $add$libresoc.v:131296$5347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:129560$5303 + cell $ge $ge$libresoc.v:131297$5348 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -205714,10 +208165,10 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:129560$5303_Y + connect \Y $ge$libresoc.v:131297$5348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:129564$5307 + cell $ge $ge$libresoc.v:131301$5352 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -205725,18 +208176,18 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:129564$5307_Y + connect \Y $ge$libresoc.v:131301$5352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:129563$5306 + cell $not $not$libresoc.v:131300$5351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] - connect \Y $not$libresoc.v:129563$5306_Y + connect \Y $not$libresoc.v:131300$5351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:129561$5304 + cell $sshl $sshl$libresoc.v:131298$5349 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -205744,10 +208195,10 @@ module \div_state_next parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 - connect \Y $sshl$libresoc.v:129561$5304_Y + connect \Y $sshl$libresoc.v:131298$5349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:129562$5305 + cell $sub $sub$libresoc.v:131299$5350 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -205755,23 +208206,23 @@ module \div_state_next parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 - connect \Y $sub$libresoc.v:129562$5305_Y + connect \Y $sub$libresoc.v:131299$5350_Y end - attribute \src "libresoc.v:129524.7-129524.20" - process $proc$libresoc.v:129524$5311 + attribute \src "libresoc.v:131261.7-131261.20" + process $proc$libresoc.v:131261$5356 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129565.3-129576.6" - process $proc$libresoc.v:129565$5308 + attribute \src "libresoc.v:131302.3-131313.6" + process $proc$libresoc.v:131302$5353 assign { } { } assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:129566.5-129566.29" + attribute \src "libresoc.v:131303.5-131303.29" switch \initial - attribute \src "libresoc.v:129566.9-129566.17" + attribute \src "libresoc.v:131303.9-131303.17" case 1'1 case end @@ -205789,13 +208240,13 @@ module \div_state_next sync always update \value $0\value[127:0] end - attribute \src "libresoc.v:129577.3-129588.6" - process $proc$libresoc.v:129577$5309 + attribute \src "libresoc.v:131314.3-131325.6" + process $proc$libresoc.v:131314$5354 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:129578.5-129578.29" + attribute \src "libresoc.v:131315.5-131315.29" switch \initial - attribute \src "libresoc.v:129578.9-129578.17" + attribute \src "libresoc.v:131315.9-131315.17" case 1'1 case end @@ -205813,13 +208264,13 @@ module \div_state_next sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end - attribute \src "libresoc.v:129589.3-129600.6" - process $proc$libresoc.v:129589$5310 + attribute \src "libresoc.v:131326.3-131337.6" + process $proc$libresoc.v:131326$5355 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:129590.5-129590.29" + attribute \src "libresoc.v:131327.5-131327.29" switch \initial - attribute \src "libresoc.v:129590.9-129590.17" + attribute \src "libresoc.v:131327.9-131327.17" case 1'1 case end @@ -205837,18 +208288,18 @@ module \div_state_next sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end - connect \$11 $add$libresoc.v:129559$5302_Y - connect \$13 $ge$libresoc.v:129560$5303_Y - connect \$2 $sshl$libresoc.v:129561$5304_Y - connect \$4 $sub$libresoc.v:129562$5305_Y - connect \$6 $not$libresoc.v:129563$5306_Y - connect \$8 $ge$libresoc.v:129564$5307_Y + connect \$11 $add$libresoc.v:131296$5347_Y + connect \$13 $ge$libresoc.v:131297$5348_Y + connect \$2 $sshl$libresoc.v:131298$5349_Y + connect \$4 $sub$libresoc.v:131299$5350_Y + connect \$6 $not$libresoc.v:131300$5351_Y + connect \$8 $ge$libresoc.v:131301$5352_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end -attribute \src "libresoc.v:129609.1-129848.10" +attribute \src "libresoc.v:131346.1-131589.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" @@ -205878,37 +208329,39 @@ module \dummy attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \trap_op__cia$6 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 16 \trap_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 16 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -205987,6 +208440,7 @@ module \dummy attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -206063,6 +208517,7 @@ module \dummy attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 15 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -206092,94 +208547,94 @@ module \dummy connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:129852.1-130023.10" +attribute \src "libresoc.v:131593.1-131764.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast - attribute \src "libresoc.v:129947.3-129953.6" - wire width 3 $0$memwr$\memory$libresoc.v:129951$5320_ADDR[2:0]$5328 - attribute \src "libresoc.v:129947.3-129953.6" - wire width 64 $0$memwr$\memory$libresoc.v:129951$5320_DATA[63:0]$5329 - attribute \src "libresoc.v:129947.3-129953.6" - wire width 64 $0$memwr$\memory$libresoc.v:129951$5320_EN[63:0]$5330 - attribute \src "libresoc.v:129947.3-129953.6" - wire width 3 $0$memwr$\memory$libresoc.v:129952$5321_ADDR[2:0]$5331 - attribute \src "libresoc.v:129947.3-129953.6" - wire width 64 $0$memwr$\memory$libresoc.v:129952$5321_DATA[63:0]$5332 - attribute \src "libresoc.v:129947.3-129953.6" - wire width 64 $0$memwr$\memory$libresoc.v:129952$5321_EN[63:0]$5333 - attribute \src "libresoc.v:129947.3-129953.6" + attribute \src "libresoc.v:131688.3-131694.6" + wire width 3 $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 64 $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 64 $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 3 $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 64 $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 + attribute \src "libresoc.v:131688.3-131694.6" + wire width 64 $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 + attribute \src "libresoc.v:131688.3-131694.6" wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:129947.3-129953.6" + attribute \src "libresoc.v:131688.3-131694.6" wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:129947.3-129953.6" + attribute \src "libresoc.v:131688.3-131694.6" wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:129853.7-129853.20" + attribute \src "libresoc.v:131594.7-131594.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130004.3-130013.6" + attribute \src "libresoc.v:131745.3-131754.6" wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:129976.3-129984.6" - wire $0\ren_delay$10$next[0:0]$5342 - attribute \src "libresoc.v:129929.3-129930.43" - wire $0\ren_delay$10[0:0]$5325 - attribute \src "libresoc.v:129904.7-129904.28" - wire $0\ren_delay$10[0:0]$5362 - attribute \src "libresoc.v:129995.3-130003.6" - wire $0\ren_delay$11$next[0:0]$5346 - attribute \src "libresoc.v:129927.3-129928.43" - wire $0\ren_delay$11[0:0]$5323 - attribute \src "libresoc.v:129908.7-129908.28" - wire $0\ren_delay$11[0:0]$5364 - attribute \src "libresoc.v:129957.3-129965.6" - wire $0\ren_delay$next[0:0]$5338 - attribute \src "libresoc.v:129931.3-129932.35" + attribute \src "libresoc.v:131717.3-131725.6" + wire $0\ren_delay$10$next[0:0]$5387 + attribute \src "libresoc.v:131670.3-131671.43" + wire $0\ren_delay$10[0:0]$5370 + attribute \src "libresoc.v:131645.7-131645.28" + wire $0\ren_delay$10[0:0]$5407 + attribute \src "libresoc.v:131736.3-131744.6" + wire $0\ren_delay$11$next[0:0]$5391 + attribute \src "libresoc.v:131668.3-131669.43" + wire $0\ren_delay$11[0:0]$5368 + attribute \src "libresoc.v:131649.7-131649.28" + wire $0\ren_delay$11[0:0]$5409 + attribute \src "libresoc.v:131698.3-131706.6" + wire $0\ren_delay$next[0:0]$5383 + attribute \src "libresoc.v:131672.3-131673.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:129966.3-129975.6" + attribute \src "libresoc.v:131707.3-131716.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:129985.3-129994.6" + attribute \src "libresoc.v:131726.3-131735.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:130004.3-130013.6" + attribute \src "libresoc.v:131745.3-131754.6" wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:129976.3-129984.6" - wire $1\ren_delay$10$next[0:0]$5343 - attribute \src "libresoc.v:129995.3-130003.6" - wire $1\ren_delay$11$next[0:0]$5347 - attribute \src "libresoc.v:129957.3-129965.6" - wire $1\ren_delay$next[0:0]$5339 - attribute \src "libresoc.v:129902.7-129902.23" + attribute \src "libresoc.v:131717.3-131725.6" + wire $1\ren_delay$10$next[0:0]$5388 + attribute \src "libresoc.v:131736.3-131744.6" + wire $1\ren_delay$11$next[0:0]$5392 + attribute \src "libresoc.v:131698.3-131706.6" + wire $1\ren_delay$next[0:0]$5384 + attribute \src "libresoc.v:131643.7-131643.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:129966.3-129975.6" + attribute \src "libresoc.v:131707.3-131716.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:129985.3-129994.6" + attribute \src "libresoc.v:131726.3-131735.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:129954.26-129954.32" - wire width 64 $memrd$\memory$libresoc.v:129954$5334_DATA - attribute \src "libresoc.v:129955.30-129955.36" - wire width 64 $memrd$\memory$libresoc.v:129955$5335_DATA - attribute \src "libresoc.v:129956.30-129956.36" - wire width 64 $memrd$\memory$libresoc.v:129956$5336_DATA + attribute \src "libresoc.v:131695.26-131695.32" + wire width 64 $memrd$\memory$libresoc.v:131695$5379_DATA + attribute \src "libresoc.v:131696.30-131696.36" + wire width 64 $memrd$\memory$libresoc.v:131696$5380_DATA + attribute \src "libresoc.v:131697.30-131697.36" + wire width 64 $memrd$\memory$libresoc.v:131697$5381_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:129951$5320_ADDR + wire width 3 $memwr$\memory$libresoc.v:131692$5365_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:129951$5320_DATA + wire width 64 $memwr$\memory$libresoc.v:131692$5365_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:129951$5320_EN + wire width 64 $memwr$\memory$libresoc.v:131692$5365_EN attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:129952$5321_ADDR + wire width 3 $memwr$\memory$libresoc.v:131693$5366_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:129952$5321_DATA + wire width 64 $memwr$\memory$libresoc.v:131693$5366_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:129952$5321_EN - attribute \src "libresoc.v:129944.13-129944.16" + wire width 64 $memwr$\memory$libresoc.v:131693$5366_EN + attribute \src "libresoc.v:131685.13-131685.16" wire width 3 \_0_ - attribute \src "libresoc.v:129945.13-129945.16" + attribute \src "libresoc.v:131686.13-131686.16" wire width 3 \_1_ - attribute \src "libresoc.v:129946.13-129946.16" + attribute \src "libresoc.v:131687.13-131687.16" wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \dest1__addr @@ -206187,7 +208642,7 @@ module \fast wire width 64 input 14 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 16 \dest1__wen - attribute \src "libresoc.v:129853.7-129853.15" + attribute \src "libresoc.v:131594.7-131594.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \issue__addr @@ -206249,90 +208704,90 @@ module \fast wire width 64 output 11 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src2__ren - attribute \src "libresoc.v:129933.14-129933.20" + attribute \src "libresoc.v:131674.14-131674.20" memory width 64 size 8 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5349 + cell $meminit $meminit$\memory$libresoc.v:0$5394 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5349 + parameter \PRIORITY 5394 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5350 + cell $meminit $meminit$\memory$libresoc.v:0$5395 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5350 + parameter \PRIORITY 5395 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5351 + cell $meminit $meminit$\memory$libresoc.v:0$5396 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5351 + parameter \PRIORITY 5396 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5352 + cell $meminit $meminit$\memory$libresoc.v:0$5397 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5352 + parameter \PRIORITY 5397 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5353 + cell $meminit $meminit$\memory$libresoc.v:0$5398 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5353 + parameter \PRIORITY 5398 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5354 + cell $meminit $meminit$\memory$libresoc.v:0$5399 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5354 + parameter \PRIORITY 5399 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5355 + cell $meminit $meminit$\memory$libresoc.v:0$5400 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5355 + parameter \PRIORITY 5400 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5356 + cell $meminit $meminit$\memory$libresoc.v:0$5401 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5356 + parameter \PRIORITY 5401 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:129954.26-129954.32" - cell $memrd $memrd$\memory$libresoc.v:129954$5334 + attribute \src "libresoc.v:131695.26-131695.32" + cell $memrd $memrd$\memory$libresoc.v:131695$5379 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -206341,11 +208796,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:129954$5334_DATA + connect \DATA $memrd$\memory$libresoc.v:131695$5379_DATA connect \EN 1'x end - attribute \src "libresoc.v:129955.30-129955.36" - cell $memrd $memrd$\memory$libresoc.v:129955$5335 + attribute \src "libresoc.v:131696.30-131696.36" + cell $memrd $memrd$\memory$libresoc.v:131696$5380 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -206354,11 +208809,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:129955$5335_DATA + connect \DATA $memrd$\memory$libresoc.v:131696$5380_DATA connect \EN 1'x end - attribute \src "libresoc.v:129956.30-129956.36" - cell $memrd $memrd$\memory$libresoc.v:129956$5336 + attribute \src "libresoc.v:131697.30-131697.36" + cell $memrd $memrd$\memory$libresoc.v:131697$5381 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -206367,95 +208822,95 @@ module \fast parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:129956$5336_DATA + connect \DATA $memrd$\memory$libresoc.v:131697$5381_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5357 + cell $memwr $memwr$\memory$libresoc.v:0$5402 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5357 + parameter \PRIORITY 5402 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:129951$5320_ADDR + connect \ADDR $memwr$\memory$libresoc.v:131692$5365_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:129951$5320_DATA - connect \EN $memwr$\memory$libresoc.v:129951$5320_EN + connect \DATA $memwr$\memory$libresoc.v:131692$5365_DATA + connect \EN $memwr$\memory$libresoc.v:131692$5365_EN end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5358 + cell $memwr $memwr$\memory$libresoc.v:0$5403 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5358 + parameter \PRIORITY 5403 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:129952$5321_ADDR + connect \ADDR $memwr$\memory$libresoc.v:131693$5366_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:129952$5321_DATA - connect \EN $memwr$\memory$libresoc.v:129952$5321_EN + connect \DATA $memwr$\memory$libresoc.v:131693$5366_DATA + connect \EN $memwr$\memory$libresoc.v:131693$5366_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5365 + process $proc$libresoc.v:0$5410 sync always sync init end - attribute \src "libresoc.v:129853.7-129853.20" - process $proc$libresoc.v:129853$5359 + attribute \src "libresoc.v:131594.7-131594.20" + process $proc$libresoc.v:131594$5404 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129902.7-129902.23" - process $proc$libresoc.v:129902$5360 + attribute \src "libresoc.v:131643.7-131643.23" + process $proc$libresoc.v:131643$5405 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:129904.7-129904.28" - process $proc$libresoc.v:129904$5361 + attribute \src "libresoc.v:131645.7-131645.28" + process $proc$libresoc.v:131645$5406 assign { } { } - assign $0\ren_delay$10[0:0]$5362 1'0 + assign $0\ren_delay$10[0:0]$5407 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5362 + update \ren_delay$10 $0\ren_delay$10[0:0]$5407 end - attribute \src "libresoc.v:129908.7-129908.28" - process $proc$libresoc.v:129908$5363 + attribute \src "libresoc.v:131649.7-131649.28" + process $proc$libresoc.v:131649$5408 assign { } { } - assign $0\ren_delay$11[0:0]$5364 1'0 + assign $0\ren_delay$11[0:0]$5409 1'0 sync always sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5364 + update \ren_delay$11 $0\ren_delay$11[0:0]$5409 end - attribute \src "libresoc.v:129927.3-129928.43" - process $proc$libresoc.v:129927$5322 + attribute \src "libresoc.v:131668.3-131669.43" + process $proc$libresoc.v:131668$5367 assign { } { } - assign $0\ren_delay$11[0:0]$5323 \ren_delay$11$next + assign $0\ren_delay$11[0:0]$5368 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5323 + update \ren_delay$11 $0\ren_delay$11[0:0]$5368 end - attribute \src "libresoc.v:129929.3-129930.43" - process $proc$libresoc.v:129929$5324 + attribute \src "libresoc.v:131670.3-131671.43" + process $proc$libresoc.v:131670$5369 assign { } { } - assign $0\ren_delay$10[0:0]$5325 \ren_delay$10$next + assign $0\ren_delay$10[0:0]$5370 \ren_delay$10$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5325 + update \ren_delay$10 $0\ren_delay$10[0:0]$5370 end - attribute \src "libresoc.v:129931.3-129932.35" - process $proc$libresoc.v:129931$5326 + attribute \src "libresoc.v:131672.3-131673.35" + process $proc$libresoc.v:131672$5371 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:129947.3-129953.6" - process $proc$libresoc.v:129947$5327 + attribute \src "libresoc.v:131688.3-131694.6" + process $proc$libresoc.v:131688$5372 assign { } { } assign { } { } assign { } { } @@ -206465,52 +208920,52 @@ module \fast assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:129952$5321_ADDR[2:0]$5331 3'xxx - assign $0$memwr$\memory$libresoc.v:129952$5321_DATA[63:0]$5332 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:129952$5321_EN[63:0]$5333 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:129951$5320_ADDR[2:0]$5328 3'xxx - assign $0$memwr$\memory$libresoc.v:129951$5320_DATA[63:0]$5329 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:129951$5320_EN[63:0]$5330 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 3'xxx + assign $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 3'xxx + assign $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[2:0] \src1__addr assign $0\_1_[2:0] \src2__addr assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:129951.5-129951.62" + attribute \src "libresoc.v:131692.5-131692.62" switch \issue__wen - attribute \src "libresoc.v:129951.9-129951.19" + attribute \src "libresoc.v:131692.9-131692.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:129951$5320_ADDR[2:0]$5328 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:129951$5320_DATA[63:0]$5329 \issue__data_i - assign $0$memwr$\memory$libresoc.v:129951$5320_EN[63:0]$5330 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 \issue__data_i + assign $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 64'1111111111111111111111111111111111111111111111111111111111111111 case end - attribute \src "libresoc.v:129952.5-129952.58" + attribute \src "libresoc.v:131693.5-131693.58" switch \dest1__wen - attribute \src "libresoc.v:129952.9-129952.19" + attribute \src "libresoc.v:131693.9-131693.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:129952$5321_ADDR[2:0]$5331 \dest1__addr - assign $0$memwr$\memory$libresoc.v:129952$5321_DATA[63:0]$5332 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:129952$5321_EN[63:0]$5333 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 \dest1__addr + assign $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:129951$5320_ADDR $0$memwr$\memory$libresoc.v:129951$5320_ADDR[2:0]$5328 - update $memwr$\memory$libresoc.v:129951$5320_DATA $0$memwr$\memory$libresoc.v:129951$5320_DATA[63:0]$5329 - update $memwr$\memory$libresoc.v:129951$5320_EN $0$memwr$\memory$libresoc.v:129951$5320_EN[63:0]$5330 - update $memwr$\memory$libresoc.v:129952$5321_ADDR $0$memwr$\memory$libresoc.v:129952$5321_ADDR[2:0]$5331 - update $memwr$\memory$libresoc.v:129952$5321_DATA $0$memwr$\memory$libresoc.v:129952$5321_DATA[63:0]$5332 - update $memwr$\memory$libresoc.v:129952$5321_EN $0$memwr$\memory$libresoc.v:129952$5321_EN[63:0]$5333 + update $memwr$\memory$libresoc.v:131692$5365_ADDR $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 + update $memwr$\memory$libresoc.v:131692$5365_DATA $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 + update $memwr$\memory$libresoc.v:131692$5365_EN $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 + update $memwr$\memory$libresoc.v:131693$5366_ADDR $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 + update $memwr$\memory$libresoc.v:131693$5366_DATA $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 + update $memwr$\memory$libresoc.v:131693$5366_EN $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 end - attribute \src "libresoc.v:129957.3-129965.6" - process $proc$libresoc.v:129957$5337 + attribute \src "libresoc.v:131698.3-131706.6" + process $proc$libresoc.v:131698$5382 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5338 $1\ren_delay$next[0:0]$5339 - attribute \src "libresoc.v:129958.5-129958.29" + assign $0\ren_delay$next[0:0]$5383 $1\ren_delay$next[0:0]$5384 + attribute \src "libresoc.v:131699.5-131699.29" switch \initial - attribute \src "libresoc.v:129958.9-129958.17" + attribute \src "libresoc.v:131699.9-131699.17" case 1'1 case end @@ -206519,21 +208974,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5339 1'0 + assign $1\ren_delay$next[0:0]$5384 1'0 case - assign $1\ren_delay$next[0:0]$5339 \src1__ren + assign $1\ren_delay$next[0:0]$5384 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5338 + update \ren_delay$next $0\ren_delay$next[0:0]$5383 end - attribute \src "libresoc.v:129966.3-129975.6" - process $proc$libresoc.v:129966$5340 + attribute \src "libresoc.v:131707.3-131716.6" + process $proc$libresoc.v:131707$5385 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:129967.5-129967.29" + attribute \src "libresoc.v:131708.5-131708.29" switch \initial - attribute \src "libresoc.v:129967.9-129967.17" + attribute \src "libresoc.v:131708.9-131708.17" case 1'1 case end @@ -206549,14 +209004,14 @@ module \fast sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:129976.3-129984.6" - process $proc$libresoc.v:129976$5341 + attribute \src "libresoc.v:131717.3-131725.6" + process $proc$libresoc.v:131717$5386 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5342 $1\ren_delay$10$next[0:0]$5343 - attribute \src "libresoc.v:129977.5-129977.29" + assign $0\ren_delay$10$next[0:0]$5387 $1\ren_delay$10$next[0:0]$5388 + attribute \src "libresoc.v:131718.5-131718.29" switch \initial - attribute \src "libresoc.v:129977.9-129977.17" + attribute \src "libresoc.v:131718.9-131718.17" case 1'1 case end @@ -206565,21 +209020,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5343 1'0 + assign $1\ren_delay$10$next[0:0]$5388 1'0 case - assign $1\ren_delay$10$next[0:0]$5343 \src2__ren + assign $1\ren_delay$10$next[0:0]$5388 \src2__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5342 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5387 end - attribute \src "libresoc.v:129985.3-129994.6" - process $proc$libresoc.v:129985$5344 + attribute \src "libresoc.v:131726.3-131735.6" + process $proc$libresoc.v:131726$5389 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:129986.5-129986.29" + attribute \src "libresoc.v:131727.5-131727.29" switch \initial - attribute \src "libresoc.v:129986.9-129986.17" + attribute \src "libresoc.v:131727.9-131727.17" case 1'1 case end @@ -206595,14 +209050,14 @@ module \fast sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:129995.3-130003.6" - process $proc$libresoc.v:129995$5345 + attribute \src "libresoc.v:131736.3-131744.6" + process $proc$libresoc.v:131736$5390 assign { } { } assign { } { } - assign $0\ren_delay$11$next[0:0]$5346 $1\ren_delay$11$next[0:0]$5347 - attribute \src "libresoc.v:129996.5-129996.29" + assign $0\ren_delay$11$next[0:0]$5391 $1\ren_delay$11$next[0:0]$5392 + attribute \src "libresoc.v:131737.5-131737.29" switch \initial - attribute \src "libresoc.v:129996.9-129996.17" + attribute \src "libresoc.v:131737.9-131737.17" case 1'1 case end @@ -206611,21 +209066,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[0:0]$5347 1'0 + assign $1\ren_delay$11$next[0:0]$5392 1'0 case - assign $1\ren_delay$11$next[0:0]$5347 \issue__ren + assign $1\ren_delay$11$next[0:0]$5392 \issue__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5346 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5391 end - attribute \src "libresoc.v:130004.3-130013.6" - process $proc$libresoc.v:130004$5348 + attribute \src "libresoc.v:131745.3-131754.6" + process $proc$libresoc.v:131745$5393 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:130005.5-130005.29" + attribute \src "libresoc.v:131746.5-131746.29" switch \initial - attribute \src "libresoc.v:130005.9-130005.17" + attribute \src "libresoc.v:131746.9-131746.17" case 1'1 case end @@ -206641,9 +209096,9 @@ module \fast sync always update \issue__data_o $0\issue__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:129954$5334_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:129955$5335_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:129956$5336_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:131695$5379_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:131696$5380_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:131697$5381_DATA connect \memory_w_data$9 \issue__data_i connect \memory_w_en$7 \issue__wen connect \memory_w_addr$8 \issue__addr$1 @@ -206654,14 +209109,14 @@ module \fast connect \memory_r_addr$3 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:130027.1-131957.10" +attribute \src "libresoc.v:131768.1-133718.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 257 \cr_a_ok @@ -206972,21 +209427,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 22 \oper_i_alu_alu0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 7 \oper_i_alu_alu0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207073,6 +209529,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207100,21 +209557,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 33 \oper_i_alu_branch0__cia attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 35 \oper_i_alu_branch0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 35 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 37 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207195,6 +209653,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 34 \oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207202,21 +209661,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 39 \oper_i_alu_branch0__lk attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 28 \oper_i_alu_cr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 28 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 29 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" @@ -207293,26 +209753,28 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 27 \oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 100 \oper_i_alu_div0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 85 \oper_i_alu_div0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 85 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 86 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207399,6 +209861,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 84 \oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207426,21 +209889,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 72 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 57 \oper_i_alu_logical0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 57 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 58 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207527,6 +209991,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 56 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207552,21 +210017,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 65 \oper_i_alu_logical0__zero_a attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 106 \oper_i_alu_mul0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 106 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 107 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207647,6 +210113,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 105 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207664,21 +210131,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 113 \oper_i_alu_mul0__write_cr0 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 121 \oper_i_alu_shift_rot0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 121 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207767,6 +210235,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207790,21 +210259,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 128 \oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 78 \oper_i_alu_spr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 78 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 79 \oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" @@ -207881,6 +210351,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 77 \oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207888,21 +210359,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 48 \oper_i_alu_trap0__cia attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 45 \oper_i_alu_trap0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 45 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 46 \oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" @@ -207979,6 +210451,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 44 \oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -207996,21 +210469,22 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 151 \oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 141 \oper_i_ldst_ldst0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 141 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 142 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -208091,6 +210565,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 140 \oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -208221,7 +210696,7 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 - attribute \src "libresoc.v:131589.8-131631.4" + attribute \src "libresoc.v:133350.8-133392.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208266,7 +210741,7 @@ module \fus connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:131632.11-131659.4" + attribute \src "libresoc.v:133393.11-133420.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208296,7 +210771,7 @@ module \fus connect \src3_i \src3_i$71 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131660.7-131685.4" + attribute \src "libresoc.v:133421.7-133446.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208324,7 +210799,7 @@ module \fus connect \src6_i \src6_i$73 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131686.8-131725.4" + attribute \src "libresoc.v:133447.8-133486.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208366,7 +210841,7 @@ module \fus connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131726.9-131780.4" + attribute \src "libresoc.v:133487.9-133541.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208423,7 +210898,7 @@ module \fus connect \src3_i \src3_i$59 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131781.12-131816.4" + attribute \src "libresoc.v:133542.12-133577.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208461,7 +210936,7 @@ module \fus connect \src3_i \src3_i$61 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131817.8-131850.4" + attribute \src "libresoc.v:133578.8-133611.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208497,7 +210972,7 @@ module \fus connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131851.13-131889.4" + attribute \src "libresoc.v:133612.13-133650.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208538,7 +211013,7 @@ module \fus connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131890.8-131922.4" + attribute \src "libresoc.v:133651.8-133683.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208573,7 +211048,7 @@ module \fus connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131923.9-131956.4" + attribute \src "libresoc.v:133684.9-133717.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208609,37 +211084,37 @@ module \fus connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:131961.1-132019.10" +attribute \src "libresoc.v:133722.1-133780.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l - attribute \src "libresoc.v:131962.7-131962.20" + attribute \src "libresoc.v:133723.7-133723.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132007.3-132015.6" - wire $0\q_int$next[0:0]$5376 - attribute \src "libresoc.v:132005.3-132006.27" + attribute \src "libresoc.v:133768.3-133776.6" + wire $0\q_int$next[0:0]$5421 + attribute \src "libresoc.v:133766.3-133767.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:132007.3-132015.6" - wire $1\q_int$next[0:0]$5377 - attribute \src "libresoc.v:131986.7-131986.19" + attribute \src "libresoc.v:133768.3-133776.6" + wire $1\q_int$next[0:0]$5422 + attribute \src "libresoc.v:133747.7-133747.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:131997.17-131997.96" - wire $and$libresoc.v:131997$5366_Y - attribute \src "libresoc.v:132002.17-132002.96" - wire $and$libresoc.v:132002$5371_Y - attribute \src "libresoc.v:131999.18-131999.95" - wire $not$libresoc.v:131999$5368_Y - attribute \src "libresoc.v:132001.17-132001.94" - wire $not$libresoc.v:132001$5370_Y - attribute \src "libresoc.v:132004.17-132004.94" - wire $not$libresoc.v:132004$5373_Y - attribute \src "libresoc.v:131998.18-131998.100" - wire $or$libresoc.v:131998$5367_Y - attribute \src "libresoc.v:132000.18-132000.101" - wire $or$libresoc.v:132000$5369_Y - attribute \src "libresoc.v:132003.17-132003.99" - wire $or$libresoc.v:132003$5372_Y + attribute \src "libresoc.v:133758.17-133758.96" + wire $and$libresoc.v:133758$5411_Y + attribute \src "libresoc.v:133763.17-133763.96" + wire $and$libresoc.v:133763$5416_Y + attribute \src "libresoc.v:133760.18-133760.95" + wire $not$libresoc.v:133760$5413_Y + attribute \src "libresoc.v:133762.17-133762.94" + wire $not$libresoc.v:133762$5415_Y + attribute \src "libresoc.v:133765.17-133765.94" + wire $not$libresoc.v:133765$5418_Y + attribute \src "libresoc.v:133759.18-133759.100" + wire $or$libresoc.v:133759$5412_Y + attribute \src "libresoc.v:133761.18-133761.101" + wire $or$libresoc.v:133761$5414_Y + attribute \src "libresoc.v:133764.17-133764.99" + wire $or$libresoc.v:133764$5417_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -208656,11 +211131,11 @@ module \idx_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:131962.7-131962.15" + attribute \src "libresoc.v:133723.7-133723.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_idx_l @@ -208677,7 +211152,7 @@ module \idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:131997$5366 + cell $and $and$libresoc.v:133758$5411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208685,10 +211160,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:131997$5366_Y + connect \Y $and$libresoc.v:133758$5411_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:132002$5371 + cell $and $and$libresoc.v:133763$5416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208696,34 +211171,34 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:132002$5371_Y + connect \Y $and$libresoc.v:133763$5416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:131999$5368 + cell $not $not$libresoc.v:133760$5413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l - connect \Y $not$libresoc.v:131999$5368_Y + connect \Y $not$libresoc.v:133760$5413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:132001$5370 + cell $not $not$libresoc.v:133762$5415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:132001$5370_Y + connect \Y $not$libresoc.v:133762$5415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:132004$5373 + cell $not $not$libresoc.v:133765$5418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:132004$5373_Y + connect \Y $not$libresoc.v:133765$5418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:131998$5367 + cell $or $or$libresoc.v:133759$5412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208731,10 +211206,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l - connect \Y $or$libresoc.v:131998$5367_Y + connect \Y $or$libresoc.v:133759$5412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:132000$5369 + cell $or $or$libresoc.v:133761$5414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208742,10 +211217,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int - connect \Y $or$libresoc.v:132000$5369_Y + connect \Y $or$libresoc.v:133761$5414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:132003$5372 + cell $or $or$libresoc.v:133764$5417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208753,39 +211228,39 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l - connect \Y $or$libresoc.v:132003$5372_Y + connect \Y $or$libresoc.v:133764$5417_Y end - attribute \src "libresoc.v:131962.7-131962.20" - process $proc$libresoc.v:131962$5378 + attribute \src "libresoc.v:133723.7-133723.20" + process $proc$libresoc.v:133723$5423 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131986.7-131986.19" - process $proc$libresoc.v:131986$5379 + attribute \src "libresoc.v:133747.7-133747.19" + process $proc$libresoc.v:133747$5424 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:132005.3-132006.27" - process $proc$libresoc.v:132005$5374 + attribute \src "libresoc.v:133766.3-133767.27" + process $proc$libresoc.v:133766$5419 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:132007.3-132015.6" - process $proc$libresoc.v:132007$5375 + attribute \src "libresoc.v:133768.3-133776.6" + process $proc$libresoc.v:133768$5420 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5376 $1\q_int$next[0:0]$5377 - attribute \src "libresoc.v:132008.5-132008.29" + assign $0\q_int$next[0:0]$5421 $1\q_int$next[0:0]$5422 + attribute \src "libresoc.v:133769.5-133769.29" switch \initial - attribute \src "libresoc.v:132008.9-132008.17" + attribute \src "libresoc.v:133769.9-133769.17" case 1'1 case end @@ -208794,192 +211269,192 @@ module \idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5377 1'0 + assign $1\q_int$next[0:0]$5422 1'0 case - assign $1\q_int$next[0:0]$5377 \$5 + assign $1\q_int$next[0:0]$5422 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5376 + update \q_int$next $0\q_int$next[0:0]$5421 end - connect \$9 $and$libresoc.v:131997$5366_Y - connect \$11 $or$libresoc.v:131998$5367_Y - connect \$13 $not$libresoc.v:131999$5368_Y - connect \$15 $or$libresoc.v:132000$5369_Y - connect \$1 $not$libresoc.v:132001$5370_Y - connect \$3 $and$libresoc.v:132002$5371_Y - connect \$5 $or$libresoc.v:132003$5372_Y - connect \$7 $not$libresoc.v:132004$5373_Y + connect \$9 $and$libresoc.v:133758$5411_Y + connect \$11 $or$libresoc.v:133759$5412_Y + connect \$13 $not$libresoc.v:133760$5413_Y + connect \$15 $or$libresoc.v:133761$5414_Y + connect \$1 $not$libresoc.v:133762$5415_Y + connect \$3 $and$libresoc.v:133763$5416_Y + connect \$5 $or$libresoc.v:133764$5417_Y + connect \$7 $not$libresoc.v:133765$5418_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end -attribute \src "libresoc.v:132023.1-132402.10" +attribute \src "libresoc.v:133784.1-134163.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem - attribute \src "libresoc.v:132354.3-132363.6" + attribute \src "libresoc.v:134115.3-134124.6" wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:132334.3-132353.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5448 - attribute \src "libresoc.v:132165.3-132166.39" + attribute \src "libresoc.v:134095.3-134114.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5493 + attribute \src "libresoc.v:133926.3-133927.39" wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:132364.3-132381.6" + attribute \src "libresoc.v:134125.3-134142.6" wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:132311.3-132333.6" - wire $0\f_fetch_err_o$next[0:0]$5443 - attribute \src "libresoc.v:132167.3-132168.43" + attribute \src "libresoc.v:134072.3-134094.6" + wire $0\f_fetch_err_o$next[0:0]$5488 + attribute \src "libresoc.v:133928.3-133929.43" wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:132382.3-132399.6" + attribute \src "libresoc.v:134143.3-134160.6" wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:132288.3-132310.6" - wire width 45 $0\ibus__adr$next[44:0]$5438 - attribute \src "libresoc.v:132169.3-132170.35" + attribute \src "libresoc.v:134049.3-134071.6" + wire width 45 $0\ibus__adr$next[44:0]$5483 + attribute \src "libresoc.v:133930.3-133931.35" wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:132179.3-132206.6" - wire $0\ibus__cyc$next[0:0]$5414 - attribute \src "libresoc.v:132177.3-132178.35" + attribute \src "libresoc.v:133940.3-133967.6" + wire $0\ibus__cyc$next[0:0]$5459 + attribute \src "libresoc.v:133938.3-133939.35" wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:132235.3-132262.6" - wire width 8 $0\ibus__sel$next[7:0]$5426 - attribute \src "libresoc.v:132173.3-132174.35" + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $0\ibus__sel$next[7:0]$5471 + attribute \src "libresoc.v:133934.3-133935.35" wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:132207.3-132234.6" - wire $0\ibus__stb$next[0:0]$5420 - attribute \src "libresoc.v:132175.3-132176.35" + attribute \src "libresoc.v:133968.3-133995.6" + wire $0\ibus__stb$next[0:0]$5465 + attribute \src "libresoc.v:133936.3-133937.35" wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:132263.3-132287.6" - wire width 64 $0\ibus_rdata$next[63:0]$5432 - attribute \src "libresoc.v:132171.3-132172.37" + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $0\ibus_rdata$next[63:0]$5477 + attribute \src "libresoc.v:133932.3-133933.37" wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:132024.7-132024.20" + attribute \src "libresoc.v:133785.7-133785.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132354.3-132363.6" + attribute \src "libresoc.v:134115.3-134124.6" wire $1\a_busy_o[0:0] - attribute \src "libresoc.v:132334.3-132353.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5449 - attribute \src "libresoc.v:132088.14-132088.44" + attribute \src "libresoc.v:134095.3-134114.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5494 + attribute \src "libresoc.v:133849.14-133849.44" wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:132364.3-132381.6" + attribute \src "libresoc.v:134125.3-134142.6" wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:132311.3-132333.6" - wire $1\f_fetch_err_o$next[0:0]$5444 - attribute \src "libresoc.v:132095.7-132095.27" + attribute \src "libresoc.v:134072.3-134094.6" + wire $1\f_fetch_err_o$next[0:0]$5489 + attribute \src "libresoc.v:133856.7-133856.27" wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:132382.3-132399.6" + attribute \src "libresoc.v:134143.3-134160.6" wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:132288.3-132310.6" - wire width 45 $1\ibus__adr$next[44:0]$5439 - attribute \src "libresoc.v:132109.14-132109.42" + attribute \src "libresoc.v:134049.3-134071.6" + wire width 45 $1\ibus__adr$next[44:0]$5484 + attribute \src "libresoc.v:133870.14-133870.42" wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:132179.3-132206.6" - wire $1\ibus__cyc$next[0:0]$5415 - attribute \src "libresoc.v:132114.7-132114.23" + attribute \src "libresoc.v:133940.3-133967.6" + wire $1\ibus__cyc$next[0:0]$5460 + attribute \src "libresoc.v:133875.7-133875.23" wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:132235.3-132262.6" - wire width 8 $1\ibus__sel$next[7:0]$5427 - attribute \src "libresoc.v:132123.13-132123.30" + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $1\ibus__sel$next[7:0]$5472 + attribute \src "libresoc.v:133884.13-133884.30" wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:132207.3-132234.6" - wire $1\ibus__stb$next[0:0]$5421 - attribute \src "libresoc.v:132128.7-132128.23" + attribute \src "libresoc.v:133968.3-133995.6" + wire $1\ibus__stb$next[0:0]$5466 + attribute \src "libresoc.v:133889.7-133889.23" wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:132263.3-132287.6" - wire width 64 $1\ibus_rdata$next[63:0]$5433 - attribute \src "libresoc.v:132132.14-132132.47" + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $1\ibus_rdata$next[63:0]$5478 + attribute \src "libresoc.v:133893.14-133893.47" wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:132334.3-132353.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5450 - attribute \src "libresoc.v:132364.3-132381.6" + attribute \src "libresoc.v:134095.3-134114.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5495 + attribute \src "libresoc.v:134125.3-134142.6" wire $2\f_busy_o[0:0] - attribute \src "libresoc.v:132311.3-132333.6" - wire $2\f_fetch_err_o$next[0:0]$5445 - attribute \src "libresoc.v:132382.3-132399.6" + attribute \src "libresoc.v:134072.3-134094.6" + wire $2\f_fetch_err_o$next[0:0]$5490 + attribute \src "libresoc.v:134143.3-134160.6" wire width 64 $2\f_instr_o[63:0] - attribute \src "libresoc.v:132288.3-132310.6" - wire width 45 $2\ibus__adr$next[44:0]$5440 - attribute \src "libresoc.v:132179.3-132206.6" - wire $2\ibus__cyc$next[0:0]$5416 - attribute \src "libresoc.v:132235.3-132262.6" - wire width 8 $2\ibus__sel$next[7:0]$5428 - attribute \src "libresoc.v:132207.3-132234.6" - wire $2\ibus__stb$next[0:0]$5422 - attribute \src "libresoc.v:132263.3-132287.6" - wire width 64 $2\ibus_rdata$next[63:0]$5434 - attribute \src "libresoc.v:132334.3-132353.6" - wire width 45 $3\f_badaddr_o$next[44:0]$5451 - attribute \src "libresoc.v:132311.3-132333.6" - wire $3\f_fetch_err_o$next[0:0]$5446 - attribute \src "libresoc.v:132288.3-132310.6" - wire width 45 $3\ibus__adr$next[44:0]$5441 - attribute \src "libresoc.v:132179.3-132206.6" - wire $3\ibus__cyc$next[0:0]$5417 - attribute \src "libresoc.v:132235.3-132262.6" - wire width 8 $3\ibus__sel$next[7:0]$5429 - attribute \src "libresoc.v:132207.3-132234.6" - wire $3\ibus__stb$next[0:0]$5423 - attribute \src "libresoc.v:132263.3-132287.6" - wire width 64 $3\ibus_rdata$next[63:0]$5435 - attribute \src "libresoc.v:132179.3-132206.6" - wire $4\ibus__cyc$next[0:0]$5418 - attribute \src "libresoc.v:132235.3-132262.6" - wire width 8 $4\ibus__sel$next[7:0]$5430 - attribute \src "libresoc.v:132207.3-132234.6" - wire $4\ibus__stb$next[0:0]$5424 - attribute \src "libresoc.v:132263.3-132287.6" - wire width 64 $4\ibus_rdata$next[63:0]$5436 - attribute \src "libresoc.v:132141.18-132141.110" - wire $and$libresoc.v:132141$5382_Y - attribute \src "libresoc.v:132147.18-132147.110" - wire $and$libresoc.v:132147$5388_Y - attribute \src "libresoc.v:132152.18-132152.110" - wire $and$libresoc.v:132152$5393_Y - attribute \src "libresoc.v:132155.17-132155.108" - wire $and$libresoc.v:132155$5396_Y - attribute \src "libresoc.v:132158.18-132158.110" - wire $and$libresoc.v:132158$5399_Y - attribute \src "libresoc.v:132159.18-132159.115" - wire $and$libresoc.v:132159$5400_Y - attribute \src "libresoc.v:132161.18-132161.115" - wire $and$libresoc.v:132161$5402_Y - attribute \src "libresoc.v:132140.18-132140.105" - wire $not$libresoc.v:132140$5381_Y - attribute \src "libresoc.v:132143.18-132143.105" - wire $not$libresoc.v:132143$5384_Y - attribute \src "libresoc.v:132144.17-132144.104" - wire $not$libresoc.v:132144$5385_Y - attribute \src "libresoc.v:132146.18-132146.105" - wire $not$libresoc.v:132146$5387_Y - attribute \src "libresoc.v:132149.18-132149.105" - wire $not$libresoc.v:132149$5390_Y - attribute \src "libresoc.v:132151.18-132151.105" - wire $not$libresoc.v:132151$5392_Y - attribute \src "libresoc.v:132154.18-132154.105" - wire $not$libresoc.v:132154$5395_Y - attribute \src "libresoc.v:132157.18-132157.105" - wire $not$libresoc.v:132157$5398_Y - attribute \src "libresoc.v:132160.18-132160.105" - wire $not$libresoc.v:132160$5401_Y - attribute \src "libresoc.v:132162.18-132162.105" - wire $not$libresoc.v:132162$5403_Y - attribute \src "libresoc.v:132164.17-132164.104" - wire $not$libresoc.v:132164$5405_Y - attribute \src "libresoc.v:132139.17-132139.103" - wire $or$libresoc.v:132139$5380_Y - attribute \src "libresoc.v:132142.18-132142.115" - wire $or$libresoc.v:132142$5383_Y - attribute \src "libresoc.v:132145.18-132145.106" - wire $or$libresoc.v:132145$5386_Y - attribute \src "libresoc.v:132148.18-132148.115" - wire $or$libresoc.v:132148$5389_Y - attribute \src "libresoc.v:132150.18-132150.106" - wire $or$libresoc.v:132150$5391_Y - attribute \src "libresoc.v:132153.18-132153.115" - wire $or$libresoc.v:132153$5394_Y - attribute \src "libresoc.v:132156.18-132156.106" - wire $or$libresoc.v:132156$5397_Y - attribute \src "libresoc.v:132163.17-132163.114" - wire $or$libresoc.v:132163$5404_Y + attribute \src "libresoc.v:134049.3-134071.6" + wire width 45 $2\ibus__adr$next[44:0]$5485 + attribute \src "libresoc.v:133940.3-133967.6" + wire $2\ibus__cyc$next[0:0]$5461 + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $2\ibus__sel$next[7:0]$5473 + attribute \src "libresoc.v:133968.3-133995.6" + wire $2\ibus__stb$next[0:0]$5467 + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $2\ibus_rdata$next[63:0]$5479 + attribute \src "libresoc.v:134095.3-134114.6" + wire width 45 $3\f_badaddr_o$next[44:0]$5496 + attribute \src "libresoc.v:134072.3-134094.6" + wire $3\f_fetch_err_o$next[0:0]$5491 + attribute \src "libresoc.v:134049.3-134071.6" + wire width 45 $3\ibus__adr$next[44:0]$5486 + attribute \src "libresoc.v:133940.3-133967.6" + wire $3\ibus__cyc$next[0:0]$5462 + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $3\ibus__sel$next[7:0]$5474 + attribute \src "libresoc.v:133968.3-133995.6" + wire $3\ibus__stb$next[0:0]$5468 + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $3\ibus_rdata$next[63:0]$5480 + attribute \src "libresoc.v:133940.3-133967.6" + wire $4\ibus__cyc$next[0:0]$5463 + attribute \src "libresoc.v:133996.3-134023.6" + wire width 8 $4\ibus__sel$next[7:0]$5475 + attribute \src "libresoc.v:133968.3-133995.6" + wire $4\ibus__stb$next[0:0]$5469 + attribute \src "libresoc.v:134024.3-134048.6" + wire width 64 $4\ibus_rdata$next[63:0]$5481 + attribute \src "libresoc.v:133902.18-133902.110" + wire $and$libresoc.v:133902$5427_Y + attribute \src "libresoc.v:133908.18-133908.110" + wire $and$libresoc.v:133908$5433_Y + attribute \src "libresoc.v:133913.18-133913.110" + wire $and$libresoc.v:133913$5438_Y + attribute \src "libresoc.v:133916.17-133916.108" + wire $and$libresoc.v:133916$5441_Y + attribute \src "libresoc.v:133919.18-133919.110" + wire $and$libresoc.v:133919$5444_Y + attribute \src "libresoc.v:133920.18-133920.115" + wire $and$libresoc.v:133920$5445_Y + attribute \src "libresoc.v:133922.18-133922.115" + wire $and$libresoc.v:133922$5447_Y + attribute \src "libresoc.v:133901.18-133901.105" + wire $not$libresoc.v:133901$5426_Y + attribute \src "libresoc.v:133904.18-133904.105" + wire $not$libresoc.v:133904$5429_Y + attribute \src "libresoc.v:133905.17-133905.104" + wire $not$libresoc.v:133905$5430_Y + attribute \src "libresoc.v:133907.18-133907.105" + wire $not$libresoc.v:133907$5432_Y + attribute \src "libresoc.v:133910.18-133910.105" + wire $not$libresoc.v:133910$5435_Y + attribute \src "libresoc.v:133912.18-133912.105" + wire $not$libresoc.v:133912$5437_Y + attribute \src "libresoc.v:133915.18-133915.105" + wire $not$libresoc.v:133915$5440_Y + attribute \src "libresoc.v:133918.18-133918.105" + wire $not$libresoc.v:133918$5443_Y + attribute \src "libresoc.v:133921.18-133921.105" + wire $not$libresoc.v:133921$5446_Y + attribute \src "libresoc.v:133923.18-133923.105" + wire $not$libresoc.v:133923$5448_Y + attribute \src "libresoc.v:133925.17-133925.104" + wire $not$libresoc.v:133925$5450_Y + attribute \src "libresoc.v:133900.17-133900.103" + wire $or$libresoc.v:133900$5425_Y + attribute \src "libresoc.v:133903.18-133903.115" + wire $or$libresoc.v:133903$5428_Y + attribute \src "libresoc.v:133906.18-133906.106" + wire $or$libresoc.v:133906$5431_Y + attribute \src "libresoc.v:133909.18-133909.115" + wire $or$libresoc.v:133909$5434_Y + attribute \src "libresoc.v:133911.18-133911.106" + wire $or$libresoc.v:133911$5436_Y + attribute \src "libresoc.v:133914.18-133914.115" + wire $or$libresoc.v:133914$5439_Y + attribute \src "libresoc.v:133917.18-133917.106" + wire $or$libresoc.v:133917$5442_Y + attribute \src "libresoc.v:133924.17-133924.114" + wire $or$libresoc.v:133924$5449_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" @@ -209040,7 +211515,7 @@ module \imem wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o @@ -209084,14 +211559,14 @@ module \imem wire width 64 \ibus_rdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:132024.7-132024.15" + attribute \src "libresoc.v:133785.7-133785.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire input 7 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:132141$5382 + cell $and $and$libresoc.v:133902$5427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209099,10 +211574,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 - connect \Y $and$libresoc.v:132141$5382_Y + connect \Y $and$libresoc.v:133902$5427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:132147$5388 + cell $and $and$libresoc.v:133908$5433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209110,10 +211585,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 - connect \Y $and$libresoc.v:132147$5388_Y + connect \Y $and$libresoc.v:133908$5433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:132152$5393 + cell $and $and$libresoc.v:133913$5438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209121,10 +211596,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 - connect \Y $and$libresoc.v:132152$5393_Y + connect \Y $and$libresoc.v:133913$5438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:132155$5396 + cell $and $and$libresoc.v:133916$5441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209132,10 +211607,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 - connect \Y $and$libresoc.v:132155$5396_Y + connect \Y $and$libresoc.v:133916$5441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:132158$5399 + cell $and $and$libresoc.v:133919$5444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209143,10 +211618,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 - connect \Y $and$libresoc.v:132158$5399_Y + connect \Y $and$libresoc.v:133919$5444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:132159$5400 + cell $and $and$libresoc.v:133920$5445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209154,10 +211629,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:132159$5400_Y + connect \Y $and$libresoc.v:133920$5445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:132161$5402 + cell $and $and$libresoc.v:133922$5447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209165,98 +211640,98 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:132161$5402_Y + connect \Y $and$libresoc.v:133922$5447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:132140$5381 + cell $not $not$libresoc.v:133901$5426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:132140$5381_Y + connect \Y $not$libresoc.v:133901$5426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:132143$5384 + cell $not $not$libresoc.v:133904$5429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:132143$5384_Y + connect \Y $not$libresoc.v:133904$5429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:132144$5385 + cell $not $not$libresoc.v:133905$5430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:132144$5385_Y + connect \Y $not$libresoc.v:133905$5430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:132146$5387 + cell $not $not$libresoc.v:133907$5432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:132146$5387_Y + connect \Y $not$libresoc.v:133907$5432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:132149$5390 + cell $not $not$libresoc.v:133910$5435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:132149$5390_Y + connect \Y $not$libresoc.v:133910$5435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:132151$5392 + cell $not $not$libresoc.v:133912$5437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:132151$5392_Y + connect \Y $not$libresoc.v:133912$5437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:132154$5395 + cell $not $not$libresoc.v:133915$5440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:132154$5395_Y + connect \Y $not$libresoc.v:133915$5440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:132157$5398 + cell $not $not$libresoc.v:133918$5443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:132157$5398_Y + connect \Y $not$libresoc.v:133918$5443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:132160$5401 + cell $not $not$libresoc.v:133921$5446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:132160$5401_Y + connect \Y $not$libresoc.v:133921$5446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:132162$5403 + cell $not $not$libresoc.v:133923$5448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:132162$5403_Y + connect \Y $not$libresoc.v:133923$5448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:132164$5405 + cell $not $not$libresoc.v:133925$5450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:132164$5405_Y + connect \Y $not$libresoc.v:133925$5450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:132139$5380 + cell $or $or$libresoc.v:133900$5425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209264,10 +211739,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:132139$5380_Y + connect \Y $or$libresoc.v:133900$5425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:132142$5383 + cell $or $or$libresoc.v:133903$5428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209275,10 +211750,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:132142$5383_Y + connect \Y $or$libresoc.v:133903$5428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:132145$5386 + cell $or $or$libresoc.v:133906$5431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209286,10 +211761,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:132145$5386_Y + connect \Y $or$libresoc.v:133906$5431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:132148$5389 + cell $or $or$libresoc.v:133909$5434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209297,10 +211772,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:132148$5389_Y + connect \Y $or$libresoc.v:133909$5434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:132150$5391 + cell $or $or$libresoc.v:133911$5436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209308,10 +211783,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 - connect \Y $or$libresoc.v:132150$5391_Y + connect \Y $or$libresoc.v:133911$5436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:132153$5394 + cell $or $or$libresoc.v:133914$5439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209319,10 +211794,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:132153$5394_Y + connect \Y $or$libresoc.v:133914$5439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:132156$5397 + cell $or $or$libresoc.v:133917$5442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209330,10 +211805,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 - connect \Y $or$libresoc.v:132156$5397_Y + connect \Y $or$libresoc.v:133917$5442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:132163$5404 + cell $or $or$libresoc.v:133924$5449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209341,130 +211816,130 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:132163$5404_Y + connect \Y $or$libresoc.v:133924$5449_Y end - attribute \src "libresoc.v:132024.7-132024.20" - process $proc$libresoc.v:132024$5455 + attribute \src "libresoc.v:133785.7-133785.20" + process $proc$libresoc.v:133785$5500 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132088.14-132088.44" - process $proc$libresoc.v:132088$5456 + attribute \src "libresoc.v:133849.14-133849.44" + process $proc$libresoc.v:133849$5501 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:132095.7-132095.27" - process $proc$libresoc.v:132095$5457 + attribute \src "libresoc.v:133856.7-133856.27" + process $proc$libresoc.v:133856$5502 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:132109.14-132109.42" - process $proc$libresoc.v:132109$5458 + attribute \src "libresoc.v:133870.14-133870.42" + process $proc$libresoc.v:133870$5503 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:132114.7-132114.23" - process $proc$libresoc.v:132114$5459 + attribute \src "libresoc.v:133875.7-133875.23" + process $proc$libresoc.v:133875$5504 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end - attribute \src "libresoc.v:132123.13-132123.30" - process $proc$libresoc.v:132123$5460 + attribute \src "libresoc.v:133884.13-133884.30" + process $proc$libresoc.v:133884$5505 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:132128.7-132128.23" - process $proc$libresoc.v:132128$5461 + attribute \src "libresoc.v:133889.7-133889.23" + process $proc$libresoc.v:133889$5506 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end - attribute \src "libresoc.v:132132.14-132132.47" - process $proc$libresoc.v:132132$5462 + attribute \src "libresoc.v:133893.14-133893.47" + process $proc$libresoc.v:133893$5507 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:132165.3-132166.39" - process $proc$libresoc.v:132165$5406 + attribute \src "libresoc.v:133926.3-133927.39" + process $proc$libresoc.v:133926$5451 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end - attribute \src "libresoc.v:132167.3-132168.43" - process $proc$libresoc.v:132167$5407 + attribute \src "libresoc.v:133928.3-133929.43" + process $proc$libresoc.v:133928$5452 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:132169.3-132170.35" - process $proc$libresoc.v:132169$5408 + attribute \src "libresoc.v:133930.3-133931.35" + process $proc$libresoc.v:133930$5453 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end - attribute \src "libresoc.v:132171.3-132172.37" - process $proc$libresoc.v:132171$5409 + attribute \src "libresoc.v:133932.3-133933.37" + process $proc$libresoc.v:133932$5454 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end - attribute \src "libresoc.v:132173.3-132174.35" - process $proc$libresoc.v:132173$5410 + attribute \src "libresoc.v:133934.3-133935.35" + process $proc$libresoc.v:133934$5455 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end - attribute \src "libresoc.v:132175.3-132176.35" - process $proc$libresoc.v:132175$5411 + attribute \src "libresoc.v:133936.3-133937.35" + process $proc$libresoc.v:133936$5456 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end - attribute \src "libresoc.v:132177.3-132178.35" - process $proc$libresoc.v:132177$5412 + attribute \src "libresoc.v:133938.3-133939.35" + process $proc$libresoc.v:133938$5457 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end - attribute \src "libresoc.v:132179.3-132206.6" - process $proc$libresoc.v:132179$5413 + attribute \src "libresoc.v:133940.3-133967.6" + process $proc$libresoc.v:133940$5458 assign { } { } assign { } { } assign { } { } - assign $0\ibus__cyc$next[0:0]$5414 $4\ibus__cyc$next[0:0]$5418 - attribute \src "libresoc.v:132180.5-132180.29" + assign $0\ibus__cyc$next[0:0]$5459 $4\ibus__cyc$next[0:0]$5463 + attribute \src "libresoc.v:133941.5-133941.29" switch \initial - attribute \src "libresoc.v:132180.9-132180.17" + attribute \src "libresoc.v:133941.9-133941.17" case 1'1 case end @@ -209473,53 +211948,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__cyc$next[0:0]$5415 $2\ibus__cyc$next[0:0]$5416 + assign $1\ibus__cyc$next[0:0]$5460 $2\ibus__cyc$next[0:0]$5461 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$3 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__cyc$next[0:0]$5416 $3\ibus__cyc$next[0:0]$5417 + assign $2\ibus__cyc$next[0:0]$5461 $3\ibus__cyc$next[0:0]$5462 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__cyc$next[0:0]$5417 1'0 + assign $3\ibus__cyc$next[0:0]$5462 1'0 case - assign $3\ibus__cyc$next[0:0]$5417 \ibus__cyc + assign $3\ibus__cyc$next[0:0]$5462 \ibus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__cyc$next[0:0]$5416 1'1 + assign $2\ibus__cyc$next[0:0]$5461 1'1 case - assign $2\ibus__cyc$next[0:0]$5416 \ibus__cyc + assign $2\ibus__cyc$next[0:0]$5461 \ibus__cyc end case - assign $1\ibus__cyc$next[0:0]$5415 \ibus__cyc + assign $1\ibus__cyc$next[0:0]$5460 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__cyc$next[0:0]$5418 1'0 + assign $4\ibus__cyc$next[0:0]$5463 1'0 case - assign $4\ibus__cyc$next[0:0]$5418 $1\ibus__cyc$next[0:0]$5415 + assign $4\ibus__cyc$next[0:0]$5463 $1\ibus__cyc$next[0:0]$5460 end sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5414 + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5459 end - attribute \src "libresoc.v:132207.3-132234.6" - process $proc$libresoc.v:132207$5419 + attribute \src "libresoc.v:133968.3-133995.6" + process $proc$libresoc.v:133968$5464 assign { } { } assign { } { } assign { } { } - assign $0\ibus__stb$next[0:0]$5420 $4\ibus__stb$next[0:0]$5424 - attribute \src "libresoc.v:132208.5-132208.29" + assign $0\ibus__stb$next[0:0]$5465 $4\ibus__stb$next[0:0]$5469 + attribute \src "libresoc.v:133969.5-133969.29" switch \initial - attribute \src "libresoc.v:132208.9-132208.17" + attribute \src "libresoc.v:133969.9-133969.17" case 1'1 case end @@ -209528,53 +212003,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__stb$next[0:0]$5421 $2\ibus__stb$next[0:0]$5422 + assign $1\ibus__stb$next[0:0]$5466 $2\ibus__stb$next[0:0]$5467 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$13 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__stb$next[0:0]$5422 $3\ibus__stb$next[0:0]$5423 + assign $2\ibus__stb$next[0:0]$5467 $3\ibus__stb$next[0:0]$5468 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__stb$next[0:0]$5423 1'0 + assign $3\ibus__stb$next[0:0]$5468 1'0 case - assign $3\ibus__stb$next[0:0]$5423 \ibus__stb + assign $3\ibus__stb$next[0:0]$5468 \ibus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__stb$next[0:0]$5422 1'1 + assign $2\ibus__stb$next[0:0]$5467 1'1 case - assign $2\ibus__stb$next[0:0]$5422 \ibus__stb + assign $2\ibus__stb$next[0:0]$5467 \ibus__stb end case - assign $1\ibus__stb$next[0:0]$5421 \ibus__stb + assign $1\ibus__stb$next[0:0]$5466 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__stb$next[0:0]$5424 1'0 + assign $4\ibus__stb$next[0:0]$5469 1'0 case - assign $4\ibus__stb$next[0:0]$5424 $1\ibus__stb$next[0:0]$5421 + assign $4\ibus__stb$next[0:0]$5469 $1\ibus__stb$next[0:0]$5466 end sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5420 + update \ibus__stb$next $0\ibus__stb$next[0:0]$5465 end - attribute \src "libresoc.v:132235.3-132262.6" - process $proc$libresoc.v:132235$5425 + attribute \src "libresoc.v:133996.3-134023.6" + process $proc$libresoc.v:133996$5470 assign { } { } assign { } { } assign { } { } - assign $0\ibus__sel$next[7:0]$5426 $4\ibus__sel$next[7:0]$5430 - attribute \src "libresoc.v:132236.5-132236.29" + assign $0\ibus__sel$next[7:0]$5471 $4\ibus__sel$next[7:0]$5475 + attribute \src "libresoc.v:133997.5-133997.29" switch \initial - attribute \src "libresoc.v:132236.9-132236.17" + attribute \src "libresoc.v:133997.9-133997.17" case 1'1 case end @@ -209583,53 +212058,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__sel$next[7:0]$5427 $2\ibus__sel$next[7:0]$5428 + assign $1\ibus__sel$next[7:0]$5472 $2\ibus__sel$next[7:0]$5473 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$23 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__sel$next[7:0]$5428 $3\ibus__sel$next[7:0]$5429 + assign $2\ibus__sel$next[7:0]$5473 $3\ibus__sel$next[7:0]$5474 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__sel$next[7:0]$5429 8'00000000 + assign $3\ibus__sel$next[7:0]$5474 8'00000000 case - assign $3\ibus__sel$next[7:0]$5429 \ibus__sel + assign $3\ibus__sel$next[7:0]$5474 \ibus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__sel$next[7:0]$5428 8'11111111 + assign $2\ibus__sel$next[7:0]$5473 8'11111111 case - assign $2\ibus__sel$next[7:0]$5428 \ibus__sel + assign $2\ibus__sel$next[7:0]$5473 \ibus__sel end case - assign $1\ibus__sel$next[7:0]$5427 \ibus__sel + assign $1\ibus__sel$next[7:0]$5472 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__sel$next[7:0]$5430 8'00000000 + assign $4\ibus__sel$next[7:0]$5475 8'00000000 case - assign $4\ibus__sel$next[7:0]$5430 $1\ibus__sel$next[7:0]$5427 + assign $4\ibus__sel$next[7:0]$5475 $1\ibus__sel$next[7:0]$5472 end sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5426 + update \ibus__sel$next $0\ibus__sel$next[7:0]$5471 end - attribute \src "libresoc.v:132263.3-132287.6" - process $proc$libresoc.v:132263$5431 + attribute \src "libresoc.v:134024.3-134048.6" + process $proc$libresoc.v:134024$5476 assign { } { } assign { } { } assign { } { } - assign $0\ibus_rdata$next[63:0]$5432 $4\ibus_rdata$next[63:0]$5436 - attribute \src "libresoc.v:132264.5-132264.29" + assign $0\ibus_rdata$next[63:0]$5477 $4\ibus_rdata$next[63:0]$5481 + attribute \src "libresoc.v:134025.5-134025.29" switch \initial - attribute \src "libresoc.v:132264.9-132264.17" + attribute \src "libresoc.v:134025.9-134025.17" case 1'1 case end @@ -209638,49 +212113,49 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus_rdata$next[63:0]$5433 $2\ibus_rdata$next[63:0]$5434 + assign $1\ibus_rdata$next[63:0]$5478 $2\ibus_rdata$next[63:0]$5479 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$33 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus_rdata$next[63:0]$5434 $3\ibus_rdata$next[63:0]$5435 + assign $2\ibus_rdata$next[63:0]$5479 $3\ibus_rdata$next[63:0]$5480 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus_rdata$next[63:0]$5435 \ibus__dat_r + assign $3\ibus_rdata$next[63:0]$5480 \ibus__dat_r case - assign $3\ibus_rdata$next[63:0]$5435 \ibus_rdata + assign $3\ibus_rdata$next[63:0]$5480 \ibus_rdata end case - assign $2\ibus_rdata$next[63:0]$5434 \ibus_rdata + assign $2\ibus_rdata$next[63:0]$5479 \ibus_rdata end case - assign $1\ibus_rdata$next[63:0]$5433 \ibus_rdata + assign $1\ibus_rdata$next[63:0]$5478 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus_rdata$next[63:0]$5436 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\ibus_rdata$next[63:0]$5481 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\ibus_rdata$next[63:0]$5436 $1\ibus_rdata$next[63:0]$5433 + assign $4\ibus_rdata$next[63:0]$5481 $1\ibus_rdata$next[63:0]$5478 end sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5432 + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5477 end - attribute \src "libresoc.v:132288.3-132310.6" - process $proc$libresoc.v:132288$5437 + attribute \src "libresoc.v:134049.3-134071.6" + process $proc$libresoc.v:134049$5482 assign { } { } assign { } { } assign { } { } - assign $0\ibus__adr$next[44:0]$5438 $3\ibus__adr$next[44:0]$5441 - attribute \src "libresoc.v:132289.5-132289.29" + assign $0\ibus__adr$next[44:0]$5483 $3\ibus__adr$next[44:0]$5486 + attribute \src "libresoc.v:134050.5-134050.29" switch \initial - attribute \src "libresoc.v:132289.9-132289.17" + attribute \src "libresoc.v:134050.9-134050.17" case 1'1 case end @@ -209689,43 +212164,43 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__adr$next[44:0]$5439 $2\ibus__adr$next[44:0]$5440 + assign $1\ibus__adr$next[44:0]$5484 $2\ibus__adr$next[44:0]$5485 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$43 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\ibus__adr$next[44:0]$5440 \ibus__adr + assign $2\ibus__adr$next[44:0]$5485 \ibus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__adr$next[44:0]$5440 \a_pc_i [47:3] + assign $2\ibus__adr$next[44:0]$5485 \a_pc_i [47:3] case - assign $2\ibus__adr$next[44:0]$5440 \ibus__adr + assign $2\ibus__adr$next[44:0]$5485 \ibus__adr end case - assign $1\ibus__adr$next[44:0]$5439 \ibus__adr + assign $1\ibus__adr$next[44:0]$5484 \ibus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__adr$next[44:0]$5441 45'000000000000000000000000000000000000000000000 + assign $3\ibus__adr$next[44:0]$5486 45'000000000000000000000000000000000000000000000 case - assign $3\ibus__adr$next[44:0]$5441 $1\ibus__adr$next[44:0]$5439 + assign $3\ibus__adr$next[44:0]$5486 $1\ibus__adr$next[44:0]$5484 end sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5438 + update \ibus__adr$next $0\ibus__adr$next[44:0]$5483 end - attribute \src "libresoc.v:132311.3-132333.6" - process $proc$libresoc.v:132311$5442 + attribute \src "libresoc.v:134072.3-134094.6" + process $proc$libresoc.v:134072$5487 assign { } { } assign { } { } assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5443 $3\f_fetch_err_o$next[0:0]$5446 - attribute \src "libresoc.v:132312.5-132312.29" + assign $0\f_fetch_err_o$next[0:0]$5488 $3\f_fetch_err_o$next[0:0]$5491 + attribute \src "libresoc.v:134073.5-134073.29" switch \initial - attribute \src "libresoc.v:132312.9-132312.17" + attribute \src "libresoc.v:134073.9-134073.17" case 1'1 case end @@ -209734,44 +212209,44 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5444 $2\f_fetch_err_o$next[0:0]$5445 + assign $1\f_fetch_err_o$next[0:0]$5489 $2\f_fetch_err_o$next[0:0]$5490 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$47 \$45 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5445 1'1 + assign $2\f_fetch_err_o$next[0:0]$5490 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5445 1'0 + assign $2\f_fetch_err_o$next[0:0]$5490 1'0 case - assign $2\f_fetch_err_o$next[0:0]$5445 \f_fetch_err_o + assign $2\f_fetch_err_o$next[0:0]$5490 \f_fetch_err_o end case - assign $1\f_fetch_err_o$next[0:0]$5444 \f_fetch_err_o + assign $1\f_fetch_err_o$next[0:0]$5489 \f_fetch_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_fetch_err_o$next[0:0]$5446 1'0 + assign $3\f_fetch_err_o$next[0:0]$5491 1'0 case - assign $3\f_fetch_err_o$next[0:0]$5446 $1\f_fetch_err_o$next[0:0]$5444 + assign $3\f_fetch_err_o$next[0:0]$5491 $1\f_fetch_err_o$next[0:0]$5489 end sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5443 + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5488 end - attribute \src "libresoc.v:132334.3-132353.6" - process $proc$libresoc.v:132334$5447 + attribute \src "libresoc.v:134095.3-134114.6" + process $proc$libresoc.v:134095$5492 assign { } { } assign { } { } assign { } { } - assign $0\f_badaddr_o$next[44:0]$5448 $3\f_badaddr_o$next[44:0]$5451 - attribute \src "libresoc.v:132335.5-132335.29" + assign $0\f_badaddr_o$next[44:0]$5493 $3\f_badaddr_o$next[44:0]$5496 + attribute \src "libresoc.v:134096.5-134096.29" switch \initial - attribute \src "libresoc.v:132335.9-132335.17" + attribute \src "libresoc.v:134096.9-134096.17" case 1'1 case end @@ -209780,39 +212255,39 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_badaddr_o$next[44:0]$5449 $2\f_badaddr_o$next[44:0]$5450 + assign $1\f_badaddr_o$next[44:0]$5494 $2\f_badaddr_o$next[44:0]$5495 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$51 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_badaddr_o$next[44:0]$5450 \ibus__adr + assign $2\f_badaddr_o$next[44:0]$5495 \ibus__adr case - assign $2\f_badaddr_o$next[44:0]$5450 \f_badaddr_o + assign $2\f_badaddr_o$next[44:0]$5495 \f_badaddr_o end case - assign $1\f_badaddr_o$next[44:0]$5449 \f_badaddr_o + assign $1\f_badaddr_o$next[44:0]$5494 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_badaddr_o$next[44:0]$5451 45'000000000000000000000000000000000000000000000 + assign $3\f_badaddr_o$next[44:0]$5496 45'000000000000000000000000000000000000000000000 case - assign $3\f_badaddr_o$next[44:0]$5451 $1\f_badaddr_o$next[44:0]$5449 + assign $3\f_badaddr_o$next[44:0]$5496 $1\f_badaddr_o$next[44:0]$5494 end sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5448 + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5493 end - attribute \src "libresoc.v:132354.3-132363.6" - process $proc$libresoc.v:132354$5452 + attribute \src "libresoc.v:134115.3-134124.6" + process $proc$libresoc.v:134115$5497 assign { } { } assign { } { } assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:132355.5-132355.29" + attribute \src "libresoc.v:134116.5-134116.29" switch \initial - attribute \src "libresoc.v:132355.9-132355.17" + attribute \src "libresoc.v:134116.9-134116.17" case 1'1 case end @@ -209828,14 +212303,14 @@ module \imem sync always update \a_busy_o $0\a_busy_o[0:0] end - attribute \src "libresoc.v:132364.3-132381.6" - process $proc$libresoc.v:132364$5453 + attribute \src "libresoc.v:134125.3-134142.6" + process $proc$libresoc.v:134125$5498 assign { } { } assign { } { } assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:132365.5-132365.29" + attribute \src "libresoc.v:134126.5-134126.29" switch \initial - attribute \src "libresoc.v:132365.9-132365.17" + attribute \src "libresoc.v:134126.9-134126.17" case 1'1 case end @@ -209862,14 +212337,14 @@ module \imem sync always update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:132382.3-132399.6" - process $proc$libresoc.v:132382$5454 + attribute \src "libresoc.v:134143.3-134160.6" + process $proc$libresoc.v:134143$5499 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:132383.5-132383.29" + attribute \src "libresoc.v:134144.5-134144.29" switch \initial - attribute \src "libresoc.v:132383.9-132383.17" + attribute \src "libresoc.v:134144.9-134144.17" case 1'1 case end @@ -209895,52 +212370,52 @@ module \imem sync always update \f_instr_o $0\f_instr_o[63:0] end - connect \$9 $or$libresoc.v:132139$5380_Y - connect \$11 $not$libresoc.v:132140$5381_Y - connect \$13 $and$libresoc.v:132141$5382_Y - connect \$15 $or$libresoc.v:132142$5383_Y - connect \$17 $not$libresoc.v:132143$5384_Y - connect \$1 $not$libresoc.v:132144$5385_Y - connect \$19 $or$libresoc.v:132145$5386_Y - connect \$21 $not$libresoc.v:132146$5387_Y - connect \$23 $and$libresoc.v:132147$5388_Y - connect \$25 $or$libresoc.v:132148$5389_Y - connect \$27 $not$libresoc.v:132149$5390_Y - connect \$29 $or$libresoc.v:132150$5391_Y - connect \$31 $not$libresoc.v:132151$5392_Y - connect \$33 $and$libresoc.v:132152$5393_Y - connect \$35 $or$libresoc.v:132153$5394_Y - connect \$37 $not$libresoc.v:132154$5395_Y - connect \$3 $and$libresoc.v:132155$5396_Y - connect \$39 $or$libresoc.v:132156$5397_Y - connect \$41 $not$libresoc.v:132157$5398_Y - connect \$43 $and$libresoc.v:132158$5399_Y - connect \$45 $and$libresoc.v:132159$5400_Y - connect \$47 $not$libresoc.v:132160$5401_Y - connect \$49 $and$libresoc.v:132161$5402_Y - connect \$51 $not$libresoc.v:132162$5403_Y - connect \$5 $or$libresoc.v:132163$5404_Y - connect \$7 $not$libresoc.v:132164$5405_Y + connect \$9 $or$libresoc.v:133900$5425_Y + connect \$11 $not$libresoc.v:133901$5426_Y + connect \$13 $and$libresoc.v:133902$5427_Y + connect \$15 $or$libresoc.v:133903$5428_Y + connect \$17 $not$libresoc.v:133904$5429_Y + connect \$1 $not$libresoc.v:133905$5430_Y + connect \$19 $or$libresoc.v:133906$5431_Y + connect \$21 $not$libresoc.v:133907$5432_Y + connect \$23 $and$libresoc.v:133908$5433_Y + connect \$25 $or$libresoc.v:133909$5434_Y + connect \$27 $not$libresoc.v:133910$5435_Y + connect \$29 $or$libresoc.v:133911$5436_Y + connect \$31 $not$libresoc.v:133912$5437_Y + connect \$33 $and$libresoc.v:133913$5438_Y + connect \$35 $or$libresoc.v:133914$5439_Y + connect \$37 $not$libresoc.v:133915$5440_Y + connect \$3 $and$libresoc.v:133916$5441_Y + connect \$39 $or$libresoc.v:133917$5442_Y + connect \$41 $not$libresoc.v:133918$5443_Y + connect \$43 $and$libresoc.v:133919$5444_Y + connect \$45 $and$libresoc.v:133920$5445_Y + connect \$47 $not$libresoc.v:133921$5446_Y + connect \$49 $and$libresoc.v:133922$5447_Y + connect \$51 $not$libresoc.v:133923$5448_Y + connect \$5 $or$libresoc.v:133924$5449_Y + connect \$7 $not$libresoc.v:133925$5450_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 end -attribute \src "libresoc.v:132406.1-132729.10" +attribute \src "libresoc.v:134167.1-134494.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input - attribute \src "libresoc.v:132692.3-132703.6" + attribute \src "libresoc.v:134457.3-134468.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:132407.7-132407.20" + attribute \src "libresoc.v:134168.7-134168.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132704.3-132722.6" - wire width 2 $0\xer_ca$23[1:0]$5466 - attribute \src "libresoc.v:132692.3-132703.6" + attribute \src "libresoc.v:134469.3-134487.6" + wire width 2 $0\xer_ca$23[1:0]$5511 + attribute \src "libresoc.v:134457.3-134468.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:132704.3-132722.6" - wire width 2 $1\xer_ca$23[1:0]$5467 - attribute \src "libresoc.v:132691.18-132691.100" - wire width 64 $not$libresoc.v:132691$5463_Y + attribute \src "libresoc.v:134469.3-134487.6" + wire width 2 $1\xer_ca$23[1:0]$5512 + attribute \src "libresoc.v:134456.18-134456.100" + wire width 64 $not$libresoc.v:134456$5508_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" @@ -209950,37 +212425,39 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \alu_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \alu_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -210079,6 +212556,7 @@ module \input attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -210155,6 +212633,7 @@ module \input attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -210203,7 +212682,7 @@ module \input wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:132407.7-132407.15" + attribute \src "libresoc.v:134168.7-134168.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -210226,28 +212705,28 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:132691$5463 + cell $not $not$libresoc.v:134456$5508 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:132691$5463_Y + connect \Y $not$libresoc.v:134456$5508_Y end - attribute \src "libresoc.v:132407.7-132407.20" - process $proc$libresoc.v:132407$5468 + attribute \src "libresoc.v:134168.7-134168.20" + process $proc$libresoc.v:134168$5513 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132692.3-132703.6" - process $proc$libresoc.v:132692$5464 + attribute \src "libresoc.v:134457.3-134468.6" + process $proc$libresoc.v:134457$5509 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:132693.5-132693.29" + attribute \src "libresoc.v:134458.5-134458.29" switch \initial - attribute \src "libresoc.v:132693.9-132693.17" + attribute \src "libresoc.v:134458.9-134458.17" case 1'1 case end @@ -210265,14 +212744,14 @@ module \input sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:132704.3-132722.6" - process $proc$libresoc.v:132704$5465 + attribute \src "libresoc.v:134469.3-134487.6" + process $proc$libresoc.v:134469$5510 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5466 $1\xer_ca$23[1:0]$5467 - attribute \src "libresoc.v:132705.5-132705.29" + assign $0\xer_ca$23[1:0]$5511 $1\xer_ca$23[1:0]$5512 + attribute \src "libresoc.v:134470.5-134470.29" switch \initial - attribute \src "libresoc.v:132705.9-132705.17" + attribute \src "libresoc.v:134470.9-134470.17" case 1'1 case end @@ -210281,22 +212760,22 @@ module \input attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5467 2'00 + assign $1\xer_ca$23[1:0]$5512 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5467 2'11 + assign $1\xer_ca$23[1:0]$5512 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5467 \xer_ca + assign $1\xer_ca$23[1:0]$5512 \xer_ca case - assign $1\xer_ca$23[1:0]$5467 2'00 + assign $1\xer_ca$23[1:0]$5512 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5466 + update \xer_ca$23 $0\xer_ca$23[1:0]$5511 end - connect \$24 $not$libresoc.v:132691$5463_Y + connect \$24 $not$libresoc.v:134456$5508_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -210304,30 +212783,30 @@ module \input connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:132733.1-133057.10" +attribute \src "libresoc.v:134498.1-134826.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" module \input$113 - attribute \src "libresoc.v:133019.3-133030.6" + attribute \src "libresoc.v:134788.3-134799.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:132734.7-132734.20" + attribute \src "libresoc.v:134499.7-134499.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133031.3-133049.6" - wire width 2 $0\xer_ca$23[1:0]$5472 - attribute \src "libresoc.v:133019.3-133030.6" + attribute \src "libresoc.v:134800.3-134818.6" + wire width 2 $0\xer_ca$23[1:0]$5517 + attribute \src "libresoc.v:134788.3-134799.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:133031.3-133049.6" - wire width 2 $1\xer_ca$23[1:0]$5473 - attribute \src "libresoc.v:133018.18-133018.100" - wire width 64 $not$libresoc.v:133018$5469_Y + attribute \src "libresoc.v:134800.3-134818.6" + wire width 2 $1\xer_ca$23[1:0]$5518 + attribute \src "libresoc.v:134787.18-134787.100" + wire width 64 $not$libresoc.v:134787$5514_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:132734.7-132734.15" + attribute \src "libresoc.v:134499.7-134499.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -210346,37 +212825,39 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 43 \rc$21 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \sr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -210479,6 +212960,7 @@ module \input$113 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -210555,6 +213037,7 @@ module \input$113 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -210606,28 +213089,28 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:133018$5469 + cell $not $not$libresoc.v:134787$5514 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:133018$5469_Y + connect \Y $not$libresoc.v:134787$5514_Y end - attribute \src "libresoc.v:132734.7-132734.20" - process $proc$libresoc.v:132734$5474 + attribute \src "libresoc.v:134499.7-134499.20" + process $proc$libresoc.v:134499$5519 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133019.3-133030.6" - process $proc$libresoc.v:133019$5470 + attribute \src "libresoc.v:134788.3-134799.6" + process $proc$libresoc.v:134788$5515 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:133020.5-133020.29" + attribute \src "libresoc.v:134789.5-134789.29" switch \initial - attribute \src "libresoc.v:133020.9-133020.17" + attribute \src "libresoc.v:134789.9-134789.17" case 1'1 case end @@ -210645,14 +213128,14 @@ module \input$113 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:133031.3-133049.6" - process $proc$libresoc.v:133031$5471 + attribute \src "libresoc.v:134800.3-134818.6" + process $proc$libresoc.v:134800$5516 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5472 $1\xer_ca$23[1:0]$5473 - attribute \src "libresoc.v:133032.5-133032.29" + assign $0\xer_ca$23[1:0]$5517 $1\xer_ca$23[1:0]$5518 + attribute \src "libresoc.v:134801.5-134801.29" switch \initial - attribute \src "libresoc.v:133032.9-133032.17" + attribute \src "libresoc.v:134801.9-134801.17" case 1'1 case end @@ -210661,22 +213144,22 @@ module \input$113 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5473 2'00 + assign $1\xer_ca$23[1:0]$5518 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5473 2'11 + assign $1\xer_ca$23[1:0]$5518 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5473 \xer_ca + assign $1\xer_ca$23[1:0]$5518 \xer_ca case - assign $1\xer_ca$23[1:0]$5473 2'00 + assign $1\xer_ca$23[1:0]$5518 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5472 + update \xer_ca$23 $0\xer_ca$23[1:0]$5517 end - connect \$24 $not$libresoc.v:133018$5469_Y + connect \$24 $not$libresoc.v:134787$5514_Y connect \rc$21 \rc connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid @@ -210685,63 +213168,65 @@ module \input$113 connect \b \rb connect \ra$19 \a end -attribute \src "libresoc.v:133061.1-133360.10" +attribute \src "libresoc.v:134830.1-135133.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" module \input$50 - attribute \src "libresoc.v:133342.3-133353.6" + attribute \src "libresoc.v:135115.3-135126.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:133062.7-133062.20" + attribute \src "libresoc.v:134831.7-134831.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133342.3-133353.6" + attribute \src "libresoc.v:135115.3-135126.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:133341.18-133341.100" - wire width 64 $not$libresoc.v:133341$5475_Y + attribute \src "libresoc.v:135114.18-135114.100" + wire width 64 $not$libresoc.v:135114$5520_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:133062.7-133062.15" + attribute \src "libresoc.v:134831.7-134831.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 24 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -210840,6 +213325,7 @@ module \input$50 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -210916,6 +213402,7 @@ module \input$50 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -210979,28 +213466,28 @@ module \input$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:133341$5475 + cell $not $not$libresoc.v:135114$5520 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $not$libresoc.v:133341$5475_Y + connect \Y $not$libresoc.v:135114$5520_Y end - attribute \src "libresoc.v:133062.7-133062.20" - process $proc$libresoc.v:133062$5477 + attribute \src "libresoc.v:134831.7-134831.20" + process $proc$libresoc.v:134831$5522 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133342.3-133353.6" - process $proc$libresoc.v:133342$5476 + attribute \src "libresoc.v:135115.3-135126.6" + process $proc$libresoc.v:135115$5521 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:133343.5-133343.29" + attribute \src "libresoc.v:135116.5-135116.29" switch \initial - attribute \src "libresoc.v:133343.9-133343.17" + attribute \src "libresoc.v:135116.9-135116.17" case 1'1 case end @@ -211018,7 +213505,7 @@ module \input$50 sync always update \b $0\b[63:0] end - connect \$23 $not$libresoc.v:133341$5475_Y + connect \$23 $not$libresoc.v:135114$5520_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -211026,63 +213513,65 @@ module \input$50 connect \ra$20 \a connect \a \ra end -attribute \src "libresoc.v:133364.1-133663.10" +attribute \src "libresoc.v:135137.1-135440.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" module \input$78 - attribute \src "libresoc.v:133645.3-133656.6" + attribute \src "libresoc.v:135422.3-135433.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:133365.7-133365.20" + attribute \src "libresoc.v:135138.7-135138.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133645.3-133656.6" + attribute \src "libresoc.v:135422.3-135433.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:133644.18-133644.100" - wire width 64 $not$libresoc.v:133644$5478_Y + attribute \src "libresoc.v:135421.18-135421.100" + wire width 64 $not$libresoc.v:135421$5523_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:133365.7-133365.15" + attribute \src "libresoc.v:135138.7-135138.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 24 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -211181,6 +213670,7 @@ module \input$78 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -211257,6 +213747,7 @@ module \input$78 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -211320,28 +213811,28 @@ module \input$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:133644$5478 + cell $not $not$libresoc.v:135421$5523 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:133644$5478_Y + connect \Y $not$libresoc.v:135421$5523_Y end - attribute \src "libresoc.v:133365.7-133365.20" - process $proc$libresoc.v:133365$5480 + attribute \src "libresoc.v:135138.7-135138.20" + process $proc$libresoc.v:135138$5525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133645.3-133656.6" - process $proc$libresoc.v:133645$5479 + attribute \src "libresoc.v:135422.3-135433.6" + process $proc$libresoc.v:135422$5524 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:133646.5-133646.29" + attribute \src "libresoc.v:135423.5-135423.29" switch \initial - attribute \src "libresoc.v:133646.9-133646.17" + attribute \src "libresoc.v:135423.9-135423.17" case 1'1 case end @@ -211359,7 +213850,7 @@ module \input$78 sync always update \a $0\a[63:0] end - connect \$23 $not$libresoc.v:133644$5478_Y + connect \$23 $not$libresoc.v:135421$5523_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -211367,7 +213858,7 @@ module \input$78 connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:133667.1-133919.10" +attribute \src "libresoc.v:135444.1-135700.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" @@ -211377,37 +213868,39 @@ module \input$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 18 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -211494,6 +213987,7 @@ module \input$95 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -211570,6 +214064,7 @@ module \input$95 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -211624,100 +214119,100 @@ module \input$95 connect \ra$14 \a connect \a \ra end -attribute \src "libresoc.v:133923.1-134142.10" +attribute \src "libresoc.v:135704.1-135923.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int - attribute \src "libresoc.v:134048.3-134054.6" - wire width 5 $0$memwr$\memory$libresoc.v:134053$5513_ADDR[4:0]$5522 - attribute \src "libresoc.v:134048.3-134054.6" - wire width 64 $0$memwr$\memory$libresoc.v:134053$5513_DATA[63:0]$5523 - attribute \src "libresoc.v:134048.3-134054.6" - wire width 64 $0$memwr$\memory$libresoc.v:134053$5513_EN[63:0]$5524 - attribute \src "libresoc.v:134048.3-134054.6" + attribute \src "libresoc.v:135829.3-135835.6" + wire width 5 $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 + attribute \src "libresoc.v:135829.3-135835.6" + wire width 64 $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 + attribute \src "libresoc.v:135829.3-135835.6" + wire width 64 $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 + attribute \src "libresoc.v:135829.3-135835.6" wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:134048.3-134054.6" + attribute \src "libresoc.v:135829.3-135835.6" wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:134048.3-134054.6" + attribute \src "libresoc.v:135829.3-135835.6" wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:134048.3-134054.6" + attribute \src "libresoc.v:135829.3-135835.6" wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:134077.3-134086.6" + attribute \src "libresoc.v:135858.3-135867.6" wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:133924.7-133924.20" + attribute \src "libresoc.v:135705.7-135705.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134068.3-134076.6" - wire $0\ren_delay$10$next[0:0]$5533 - attribute \src "libresoc.v:134001.3-134002.43" - wire $0\ren_delay$10[0:0]$5515 - attribute \src "libresoc.v:133967.7-133967.28" - wire $0\ren_delay$10[0:0]$5581 - attribute \src "libresoc.v:134097.3-134105.6" - wire $0\ren_delay$8$next[0:0]$5538 - attribute \src "libresoc.v:134005.3-134006.41" - wire $0\ren_delay$8[0:0]$5519 - attribute \src "libresoc.v:133971.7-133971.27" - wire $0\ren_delay$8[0:0]$5583 - attribute \src "libresoc.v:134116.3-134124.6" - wire $0\ren_delay$9$next[0:0]$5542 - attribute \src "libresoc.v:134003.3-134004.41" - wire $0\ren_delay$9[0:0]$5517 - attribute \src "libresoc.v:133975.7-133975.27" - wire $0\ren_delay$9[0:0]$5585 - attribute \src "libresoc.v:134059.3-134067.6" - wire $0\ren_delay$next[0:0]$5530 - attribute \src "libresoc.v:134007.3-134008.35" + attribute \src "libresoc.v:135849.3-135857.6" + wire $0\ren_delay$10$next[0:0]$5578 + attribute \src "libresoc.v:135782.3-135783.43" + wire $0\ren_delay$10[0:0]$5560 + attribute \src "libresoc.v:135748.7-135748.28" + wire $0\ren_delay$10[0:0]$5626 + attribute \src "libresoc.v:135878.3-135886.6" + wire $0\ren_delay$8$next[0:0]$5583 + attribute \src "libresoc.v:135786.3-135787.41" + wire $0\ren_delay$8[0:0]$5564 + attribute \src "libresoc.v:135752.7-135752.27" + wire $0\ren_delay$8[0:0]$5628 + attribute \src "libresoc.v:135897.3-135905.6" + wire $0\ren_delay$9$next[0:0]$5587 + attribute \src "libresoc.v:135784.3-135785.41" + wire $0\ren_delay$9[0:0]$5562 + attribute \src "libresoc.v:135756.7-135756.27" + wire $0\ren_delay$9[0:0]$5630 + attribute \src "libresoc.v:135840.3-135848.6" + wire $0\ren_delay$next[0:0]$5575 + attribute \src "libresoc.v:135788.3-135789.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:134087.3-134096.6" + attribute \src "libresoc.v:135868.3-135877.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:134106.3-134115.6" + attribute \src "libresoc.v:135887.3-135896.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:134125.3-134134.6" + attribute \src "libresoc.v:135906.3-135915.6" wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:134077.3-134086.6" + attribute \src "libresoc.v:135858.3-135867.6" wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:134068.3-134076.6" - wire $1\ren_delay$10$next[0:0]$5534 - attribute \src "libresoc.v:134097.3-134105.6" - wire $1\ren_delay$8$next[0:0]$5539 - attribute \src "libresoc.v:134116.3-134124.6" - wire $1\ren_delay$9$next[0:0]$5543 - attribute \src "libresoc.v:134059.3-134067.6" - wire $1\ren_delay$next[0:0]$5531 - attribute \src "libresoc.v:133965.7-133965.23" + attribute \src "libresoc.v:135849.3-135857.6" + wire $1\ren_delay$10$next[0:0]$5579 + attribute \src "libresoc.v:135878.3-135886.6" + wire $1\ren_delay$8$next[0:0]$5584 + attribute \src "libresoc.v:135897.3-135905.6" + wire $1\ren_delay$9$next[0:0]$5588 + attribute \src "libresoc.v:135840.3-135848.6" + wire $1\ren_delay$next[0:0]$5576 + attribute \src "libresoc.v:135746.7-135746.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:134087.3-134096.6" + attribute \src "libresoc.v:135868.3-135877.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:134106.3-134115.6" + attribute \src "libresoc.v:135887.3-135896.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:134125.3-134134.6" + attribute \src "libresoc.v:135906.3-135915.6" wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:134055.26-134055.32" - wire width 64 $memrd$\memory$libresoc.v:134055$5525_DATA - attribute \src "libresoc.v:134056.30-134056.36" - wire width 64 $memrd$\memory$libresoc.v:134056$5526_DATA - attribute \src "libresoc.v:134057.30-134057.36" - wire width 64 $memrd$\memory$libresoc.v:134057$5527_DATA - attribute \src "libresoc.v:134058.30-134058.36" - wire width 64 $memrd$\memory$libresoc.v:134058$5528_DATA + attribute \src "libresoc.v:135836.26-135836.32" + wire width 64 $memrd$\memory$libresoc.v:135836$5570_DATA + attribute \src "libresoc.v:135837.30-135837.36" + wire width 64 $memrd$\memory$libresoc.v:135837$5571_DATA + attribute \src "libresoc.v:135838.30-135838.36" + wire width 64 $memrd$\memory$libresoc.v:135838$5572_DATA + attribute \src "libresoc.v:135839.30-135839.36" + wire width 64 $memrd$\memory$libresoc.v:135839$5573_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:134053$5513_ADDR + wire width 5 $memwr$\memory$libresoc.v:135834$5558_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:134053$5513_DATA + wire width 64 $memwr$\memory$libresoc.v:135834$5558_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:134053$5513_EN - attribute \src "libresoc.v:134044.13-134044.16" + wire width 64 $memwr$\memory$libresoc.v:135834$5558_EN + attribute \src "libresoc.v:135825.13-135825.16" wire width 5 \_0_ - attribute \src "libresoc.v:134045.13-134045.16" + attribute \src "libresoc.v:135826.13-135826.16" wire width 5 \_1_ - attribute \src "libresoc.v:134046.13-134046.16" + attribute \src "libresoc.v:135827.13-135827.16" wire width 5 \_2_ - attribute \src "libresoc.v:134047.13-134047.16" + attribute \src "libresoc.v:135828.13-135828.16" wire width 5 \_3_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 15 \dest1__addr @@ -211731,7 +214226,7 @@ module \int wire width 64 output 4 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \dmi__ren - attribute \src "libresoc.v:133924.7-133924.15" + attribute \src "libresoc.v:135705.7-135705.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr @@ -211789,330 +214284,330 @@ module \int wire width 64 output 11 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src3__ren - attribute \src "libresoc.v:134009.14-134009.20" + attribute \src "libresoc.v:135790.14-135790.20" memory width 64 size 32 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5545 + cell $meminit $meminit$\memory$libresoc.v:0$5590 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5545 + parameter \PRIORITY 5590 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5546 + cell $meminit $meminit$\memory$libresoc.v:0$5591 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5546 + parameter \PRIORITY 5591 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5547 + cell $meminit $meminit$\memory$libresoc.v:0$5592 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5547 + parameter \PRIORITY 5592 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5548 + cell $meminit $meminit$\memory$libresoc.v:0$5593 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5548 + parameter \PRIORITY 5593 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5549 + cell $meminit $meminit$\memory$libresoc.v:0$5594 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5549 + parameter \PRIORITY 5594 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5550 + cell $meminit $meminit$\memory$libresoc.v:0$5595 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5550 + parameter \PRIORITY 5595 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5551 + cell $meminit $meminit$\memory$libresoc.v:0$5596 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5551 + parameter \PRIORITY 5596 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5552 + cell $meminit $meminit$\memory$libresoc.v:0$5597 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5552 + parameter \PRIORITY 5597 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5553 + cell $meminit $meminit$\memory$libresoc.v:0$5598 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5553 + parameter \PRIORITY 5598 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5554 + cell $meminit $meminit$\memory$libresoc.v:0$5599 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5554 + parameter \PRIORITY 5599 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5555 + cell $meminit $meminit$\memory$libresoc.v:0$5600 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5555 + parameter \PRIORITY 5600 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5556 + cell $meminit $meminit$\memory$libresoc.v:0$5601 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5556 + parameter \PRIORITY 5601 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5557 + cell $meminit $meminit$\memory$libresoc.v:0$5602 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5557 + parameter \PRIORITY 5602 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5558 + cell $meminit $meminit$\memory$libresoc.v:0$5603 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5558 + parameter \PRIORITY 5603 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5559 + cell $meminit $meminit$\memory$libresoc.v:0$5604 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5559 + parameter \PRIORITY 5604 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5560 + cell $meminit $meminit$\memory$libresoc.v:0$5605 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5560 + parameter \PRIORITY 5605 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5561 + cell $meminit $meminit$\memory$libresoc.v:0$5606 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5561 + parameter \PRIORITY 5606 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5562 + cell $meminit $meminit$\memory$libresoc.v:0$5607 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5562 + parameter \PRIORITY 5607 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5563 + cell $meminit $meminit$\memory$libresoc.v:0$5608 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5563 + parameter \PRIORITY 5608 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5564 + cell $meminit $meminit$\memory$libresoc.v:0$5609 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5564 + parameter \PRIORITY 5609 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5565 + cell $meminit $meminit$\memory$libresoc.v:0$5610 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5565 + parameter \PRIORITY 5610 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5566 + cell $meminit $meminit$\memory$libresoc.v:0$5611 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5566 + parameter \PRIORITY 5611 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5567 + cell $meminit $meminit$\memory$libresoc.v:0$5612 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5567 + parameter \PRIORITY 5612 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5568 + cell $meminit $meminit$\memory$libresoc.v:0$5613 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5568 + parameter \PRIORITY 5613 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5569 + cell $meminit $meminit$\memory$libresoc.v:0$5614 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5569 + parameter \PRIORITY 5614 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5570 + cell $meminit $meminit$\memory$libresoc.v:0$5615 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5570 + parameter \PRIORITY 5615 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5571 + cell $meminit $meminit$\memory$libresoc.v:0$5616 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5571 + parameter \PRIORITY 5616 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5572 + cell $meminit $meminit$\memory$libresoc.v:0$5617 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5572 + parameter \PRIORITY 5617 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5573 + cell $meminit $meminit$\memory$libresoc.v:0$5618 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5573 + parameter \PRIORITY 5618 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5574 + cell $meminit $meminit$\memory$libresoc.v:0$5619 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5574 + parameter \PRIORITY 5619 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5575 + cell $meminit $meminit$\memory$libresoc.v:0$5620 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5575 + parameter \PRIORITY 5620 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5576 + cell $meminit $meminit$\memory$libresoc.v:0$5621 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5576 + parameter \PRIORITY 5621 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:134055.26-134055.32" - cell $memrd $memrd$\memory$libresoc.v:134055$5525 + attribute \src "libresoc.v:135836.26-135836.32" + cell $memrd $memrd$\memory$libresoc.v:135836$5570 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -212121,11 +214616,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:134055$5525_DATA + connect \DATA $memrd$\memory$libresoc.v:135836$5570_DATA connect \EN 1'x end - attribute \src "libresoc.v:134056.30-134056.36" - cell $memrd $memrd$\memory$libresoc.v:134056$5526 + attribute \src "libresoc.v:135837.30-135837.36" + cell $memrd $memrd$\memory$libresoc.v:135837$5571 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -212134,11 +214629,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:134056$5526_DATA + connect \DATA $memrd$\memory$libresoc.v:135837$5571_DATA connect \EN 1'x end - attribute \src "libresoc.v:134057.30-134057.36" - cell $memrd $memrd$\memory$libresoc.v:134057$5527 + attribute \src "libresoc.v:135838.30-135838.36" + cell $memrd $memrd$\memory$libresoc.v:135838$5572 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -212147,11 +214642,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:134057$5527_DATA + connect \DATA $memrd$\memory$libresoc.v:135838$5572_DATA connect \EN 1'x end - attribute \src "libresoc.v:134058.30-134058.36" - cell $memrd $memrd$\memory$libresoc.v:134058$5528 + attribute \src "libresoc.v:135839.30-135839.36" + cell $memrd $memrd$\memory$libresoc.v:135839$5573 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -212160,97 +214655,97 @@ module \int parameter \WIDTH 64 connect \ADDR \_3_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:134058$5528_DATA + connect \DATA $memrd$\memory$libresoc.v:135839$5573_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5577 + cell $memwr $memwr$\memory$libresoc.v:0$5622 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5577 + parameter \PRIORITY 5622 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:134053$5513_ADDR + connect \ADDR $memwr$\memory$libresoc.v:135834$5558_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:134053$5513_DATA - connect \EN $memwr$\memory$libresoc.v:134053$5513_EN + connect \DATA $memwr$\memory$libresoc.v:135834$5558_DATA + connect \EN $memwr$\memory$libresoc.v:135834$5558_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5586 + process $proc$libresoc.v:0$5631 sync always sync init end - attribute \src "libresoc.v:133924.7-133924.20" - process $proc$libresoc.v:133924$5578 + attribute \src "libresoc.v:135705.7-135705.20" + process $proc$libresoc.v:135705$5623 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133965.7-133965.23" - process $proc$libresoc.v:133965$5579 + attribute \src "libresoc.v:135746.7-135746.23" + process $proc$libresoc.v:135746$5624 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:133967.7-133967.28" - process $proc$libresoc.v:133967$5580 + attribute \src "libresoc.v:135748.7-135748.28" + process $proc$libresoc.v:135748$5625 assign { } { } - assign $0\ren_delay$10[0:0]$5581 1'0 + assign $0\ren_delay$10[0:0]$5626 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5581 + update \ren_delay$10 $0\ren_delay$10[0:0]$5626 end - attribute \src "libresoc.v:133971.7-133971.27" - process $proc$libresoc.v:133971$5582 + attribute \src "libresoc.v:135752.7-135752.27" + process $proc$libresoc.v:135752$5627 assign { } { } - assign $0\ren_delay$8[0:0]$5583 1'0 + assign $0\ren_delay$8[0:0]$5628 1'0 sync always sync init - update \ren_delay$8 $0\ren_delay$8[0:0]$5583 + update \ren_delay$8 $0\ren_delay$8[0:0]$5628 end - attribute \src "libresoc.v:133975.7-133975.27" - process $proc$libresoc.v:133975$5584 + attribute \src "libresoc.v:135756.7-135756.27" + process $proc$libresoc.v:135756$5629 assign { } { } - assign $0\ren_delay$9[0:0]$5585 1'0 + assign $0\ren_delay$9[0:0]$5630 1'0 sync always sync init - update \ren_delay$9 $0\ren_delay$9[0:0]$5585 + update \ren_delay$9 $0\ren_delay$9[0:0]$5630 end - attribute \src "libresoc.v:134001.3-134002.43" - process $proc$libresoc.v:134001$5514 + attribute \src "libresoc.v:135782.3-135783.43" + process $proc$libresoc.v:135782$5559 assign { } { } - assign $0\ren_delay$10[0:0]$5515 \ren_delay$10$next + assign $0\ren_delay$10[0:0]$5560 \ren_delay$10$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5515 + update \ren_delay$10 $0\ren_delay$10[0:0]$5560 end - attribute \src "libresoc.v:134003.3-134004.41" - process $proc$libresoc.v:134003$5516 + attribute \src "libresoc.v:135784.3-135785.41" + process $proc$libresoc.v:135784$5561 assign { } { } - assign $0\ren_delay$9[0:0]$5517 \ren_delay$9$next + assign $0\ren_delay$9[0:0]$5562 \ren_delay$9$next sync posedge \coresync_clk - update \ren_delay$9 $0\ren_delay$9[0:0]$5517 + update \ren_delay$9 $0\ren_delay$9[0:0]$5562 end - attribute \src "libresoc.v:134005.3-134006.41" - process $proc$libresoc.v:134005$5518 + attribute \src "libresoc.v:135786.3-135787.41" + process $proc$libresoc.v:135786$5563 assign { } { } - assign $0\ren_delay$8[0:0]$5519 \ren_delay$8$next + assign $0\ren_delay$8[0:0]$5564 \ren_delay$8$next sync posedge \coresync_clk - update \ren_delay$8 $0\ren_delay$8[0:0]$5519 + update \ren_delay$8 $0\ren_delay$8[0:0]$5564 end - attribute \src "libresoc.v:134007.3-134008.35" - process $proc$libresoc.v:134007$5520 + attribute \src "libresoc.v:135788.3-135789.35" + process $proc$libresoc.v:135788$5565 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:134048.3-134054.6" - process $proc$libresoc.v:134048$5521 + attribute \src "libresoc.v:135829.3-135835.6" + process $proc$libresoc.v:135829$5566 assign { } { } assign { } { } assign { } { } @@ -212258,20 +214753,20 @@ module \int assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:134053$5513_ADDR[4:0]$5522 5'xxxxx - assign $0$memwr$\memory$libresoc.v:134053$5513_DATA[63:0]$5523 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:134053$5513_EN[63:0]$5524 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 5'xxxxx + assign $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[4:0] \src1__addr assign $0\_1_[4:0] \src2__addr assign $0\_2_[4:0] \src3__addr assign $0\_3_[4:0] \dmi__addr - attribute \src "libresoc.v:134053.5-134053.58" + attribute \src "libresoc.v:135834.5-135834.58" switch \dest1__wen - attribute \src "libresoc.v:134053.9-134053.19" + attribute \src "libresoc.v:135834.9-135834.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:134053$5513_ADDR[4:0]$5522 \dest1__addr - assign $0$memwr$\memory$libresoc.v:134053$5513_DATA[63:0]$5523 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:134053$5513_EN[63:0]$5524 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 \dest1__addr + assign $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk @@ -212279,18 +214774,18 @@ module \int update \_1_ $0\_1_[4:0] update \_2_ $0\_2_[4:0] update \_3_ $0\_3_[4:0] - update $memwr$\memory$libresoc.v:134053$5513_ADDR $0$memwr$\memory$libresoc.v:134053$5513_ADDR[4:0]$5522 - update $memwr$\memory$libresoc.v:134053$5513_DATA $0$memwr$\memory$libresoc.v:134053$5513_DATA[63:0]$5523 - update $memwr$\memory$libresoc.v:134053$5513_EN $0$memwr$\memory$libresoc.v:134053$5513_EN[63:0]$5524 + update $memwr$\memory$libresoc.v:135834$5558_ADDR $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 + update $memwr$\memory$libresoc.v:135834$5558_DATA $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 + update $memwr$\memory$libresoc.v:135834$5558_EN $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 end - attribute \src "libresoc.v:134059.3-134067.6" - process $proc$libresoc.v:134059$5529 + attribute \src "libresoc.v:135840.3-135848.6" + process $proc$libresoc.v:135840$5574 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5530 $1\ren_delay$next[0:0]$5531 - attribute \src "libresoc.v:134060.5-134060.29" + assign $0\ren_delay$next[0:0]$5575 $1\ren_delay$next[0:0]$5576 + attribute \src "libresoc.v:135841.5-135841.29" switch \initial - attribute \src "libresoc.v:134060.9-134060.17" + attribute \src "libresoc.v:135841.9-135841.17" case 1'1 case end @@ -212299,21 +214794,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5531 1'0 + assign $1\ren_delay$next[0:0]$5576 1'0 case - assign $1\ren_delay$next[0:0]$5531 \src1__ren + assign $1\ren_delay$next[0:0]$5576 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5530 + update \ren_delay$next $0\ren_delay$next[0:0]$5575 end - attribute \src "libresoc.v:134068.3-134076.6" - process $proc$libresoc.v:134068$5532 + attribute \src "libresoc.v:135849.3-135857.6" + process $proc$libresoc.v:135849$5577 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5533 $1\ren_delay$10$next[0:0]$5534 - attribute \src "libresoc.v:134069.5-134069.29" + assign $0\ren_delay$10$next[0:0]$5578 $1\ren_delay$10$next[0:0]$5579 + attribute \src "libresoc.v:135850.5-135850.29" switch \initial - attribute \src "libresoc.v:134069.9-134069.17" + attribute \src "libresoc.v:135850.9-135850.17" case 1'1 case end @@ -212322,21 +214817,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5534 1'0 + assign $1\ren_delay$10$next[0:0]$5579 1'0 case - assign $1\ren_delay$10$next[0:0]$5534 \dmi__ren + assign $1\ren_delay$10$next[0:0]$5579 \dmi__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5533 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5578 end - attribute \src "libresoc.v:134077.3-134086.6" - process $proc$libresoc.v:134077$5535 + attribute \src "libresoc.v:135858.3-135867.6" + process $proc$libresoc.v:135858$5580 assign { } { } assign { } { } assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:134078.5-134078.29" + attribute \src "libresoc.v:135859.5-135859.29" switch \initial - attribute \src "libresoc.v:134078.9-134078.17" + attribute \src "libresoc.v:135859.9-135859.17" case 1'1 case end @@ -212352,14 +214847,14 @@ module \int sync always update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:134087.3-134096.6" - process $proc$libresoc.v:134087$5536 + attribute \src "libresoc.v:135868.3-135877.6" + process $proc$libresoc.v:135868$5581 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:134088.5-134088.29" + attribute \src "libresoc.v:135869.5-135869.29" switch \initial - attribute \src "libresoc.v:134088.9-134088.17" + attribute \src "libresoc.v:135869.9-135869.17" case 1'1 case end @@ -212375,14 +214870,14 @@ module \int sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:134097.3-134105.6" - process $proc$libresoc.v:134097$5537 + attribute \src "libresoc.v:135878.3-135886.6" + process $proc$libresoc.v:135878$5582 assign { } { } assign { } { } - assign $0\ren_delay$8$next[0:0]$5538 $1\ren_delay$8$next[0:0]$5539 - attribute \src "libresoc.v:134098.5-134098.29" + assign $0\ren_delay$8$next[0:0]$5583 $1\ren_delay$8$next[0:0]$5584 + attribute \src "libresoc.v:135879.5-135879.29" switch \initial - attribute \src "libresoc.v:134098.9-134098.17" + attribute \src "libresoc.v:135879.9-135879.17" case 1'1 case end @@ -212391,21 +214886,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$8$next[0:0]$5539 1'0 + assign $1\ren_delay$8$next[0:0]$5584 1'0 case - assign $1\ren_delay$8$next[0:0]$5539 \src2__ren + assign $1\ren_delay$8$next[0:0]$5584 \src2__ren end sync always - update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5538 + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5583 end - attribute \src "libresoc.v:134106.3-134115.6" - process $proc$libresoc.v:134106$5540 + attribute \src "libresoc.v:135887.3-135896.6" + process $proc$libresoc.v:135887$5585 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:134107.5-134107.29" + attribute \src "libresoc.v:135888.5-135888.29" switch \initial - attribute \src "libresoc.v:134107.9-134107.17" + attribute \src "libresoc.v:135888.9-135888.17" case 1'1 case end @@ -212421,14 +214916,14 @@ module \int sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:134116.3-134124.6" - process $proc$libresoc.v:134116$5541 + attribute \src "libresoc.v:135897.3-135905.6" + process $proc$libresoc.v:135897$5586 assign { } { } assign { } { } - assign $0\ren_delay$9$next[0:0]$5542 $1\ren_delay$9$next[0:0]$5543 - attribute \src "libresoc.v:134117.5-134117.29" + assign $0\ren_delay$9$next[0:0]$5587 $1\ren_delay$9$next[0:0]$5588 + attribute \src "libresoc.v:135898.5-135898.29" switch \initial - attribute \src "libresoc.v:134117.9-134117.17" + attribute \src "libresoc.v:135898.9-135898.17" case 1'1 case end @@ -212437,21 +214932,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$9$next[0:0]$5543 1'0 + assign $1\ren_delay$9$next[0:0]$5588 1'0 case - assign $1\ren_delay$9$next[0:0]$5543 \src3__ren + assign $1\ren_delay$9$next[0:0]$5588 \src3__ren end sync always - update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5542 + update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5587 end - attribute \src "libresoc.v:134125.3-134134.6" - process $proc$libresoc.v:134125$5544 + attribute \src "libresoc.v:135906.3-135915.6" + process $proc$libresoc.v:135906$5589 assign { } { } assign { } { } assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:134126.5-134126.29" + attribute \src "libresoc.v:135907.5-135907.29" switch \initial - attribute \src "libresoc.v:134126.9-134126.17" + attribute \src "libresoc.v:135907.9-135907.17" case 1'1 case end @@ -212467,10 +214962,10 @@ module \int sync always update \src3__data_o $0\src3__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:134055$5525_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:134056$5526_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:134057$5527_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:134058$5528_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:135836$5570_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:135837$5571_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:135838$5572_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:135839$5573_DATA connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr @@ -212479,925 +214974,925 @@ module \int connect \memory_r_addr$2 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:134146.1-136868.10" +attribute \src "libresoc.v:135927.1-138650.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:136298.3-136324.6" + attribute \src "libresoc.v:138080.3-138106.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:135946.3-135961.6" + attribute \src "libresoc.v:137728.3-137743.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:136459.3-136491.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$5998 - attribute \src "libresoc.v:135849.3-135850.41" + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6043 + attribute \src "libresoc.v:137631.3-137632.41" wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:136545.3-136571.6" - wire width 64 $0\dmi0__din$next[63:0]$6011 - attribute \src "libresoc.v:135845.3-135846.35" + attribute \src "libresoc.v:138327.3-138353.6" + wire width 64 $0\dmi0__din$next[63:0]$6056 + attribute \src "libresoc.v:137627.3-137628.35" wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:136148.3-136164.6" - wire $0\dmi0_addrsr__oe$next[0:0]$5935 - attribute \src "libresoc.v:135877.3-135878.47" + attribute \src "libresoc.v:137930.3-137946.6" + wire $0\dmi0_addrsr__oe$next[0:0]$5980 + attribute \src "libresoc.v:137659.3-137660.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:136165.3-136185.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5939 - attribute \src "libresoc.v:135875.3-135876.47" + attribute \src "libresoc.v:137947.3-137967.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5984 + attribute \src "libresoc.v:137657.3-137658.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:136130.3-136138.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$5929 - attribute \src "libresoc.v:135881.3-135882.63" + attribute \src "libresoc.v:137912.3-137920.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$5974 + attribute \src "libresoc.v:137663.3-137664.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:136139.3-136147.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5932 - attribute \src "libresoc.v:135879.3-135880.73" + attribute \src "libresoc.v:137921.3-137929.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 + attribute \src "libresoc.v:137661.3-137662.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:136572.3-136592.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$6016 - attribute \src "libresoc.v:135843.3-135844.45" + attribute \src "libresoc.v:138354.3-138374.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6061 + attribute \src "libresoc.v:137625.3-137626.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:136204.3-136220.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$5950 - attribute \src "libresoc.v:135869.3-135870.47" + attribute \src "libresoc.v:137986.3-138002.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$5995 + attribute \src "libresoc.v:137651.3-137652.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:136221.3-136241.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$5954 - attribute \src "libresoc.v:135867.3-135868.47" + attribute \src "libresoc.v:138003.3-138023.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$5999 + attribute \src "libresoc.v:137649.3-137650.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:136186.3-136194.6" - wire $0\dmi0_datasr_update_core$next[0:0]$5944 - attribute \src "libresoc.v:135873.3-135874.63" + attribute \src "libresoc.v:137968.3-137976.6" + wire $0\dmi0_datasr_update_core$next[0:0]$5989 + attribute \src "libresoc.v:137655.3-137656.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:136195.3-136203.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$5947 - attribute \src "libresoc.v:135871.3-135872.73" + attribute \src "libresoc.v:137977.3-137985.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$5992 + attribute \src "libresoc.v:137653.3-137654.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:136492.3-136544.6" - wire width 3 $0\fsm_state$503$next[2:0]$6004 - attribute \src "libresoc.v:135847.3-135848.45" - wire width 3 $0\fsm_state$503[2:0]$5850 - attribute \src "libresoc.v:134792.13-134792.35" - wire width 3 $0\fsm_state$503[2:0]$6053 - attribute \src "libresoc.v:136358.3-136410.6" - wire width 3 $0\fsm_state$next[2:0]$5981 - attribute \src "libresoc.v:135855.3-135856.35" + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $0\fsm_state$503$next[2:0]$6049 + attribute \src "libresoc.v:137629.3-137630.45" + wire width 3 $0\fsm_state$503[2:0]$5895 + attribute \src "libresoc.v:136573.13-136573.35" + wire width 3 $0\fsm_state$503[2:0]$6098 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $0\fsm_state$next[2:0]$6026 + attribute \src "libresoc.v:137637.3-137638.35" wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:134147.7-134147.20" + attribute \src "libresoc.v:135928.7-135928.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136642.3-136662.6" - wire width 154 $0\io_bd$next[153:0]$6036 - attribute \src "libresoc.v:135907.3-135908.27" + attribute \src "libresoc.v:138424.3-138444.6" + wire width 154 $0\io_bd$next[153:0]$6081 + attribute \src "libresoc.v:137689.3-137690.27" wire width 154 $0\io_bd[153:0] - attribute \src "libresoc.v:136624.3-136641.6" - wire width 154 $0\io_sr$next[153:0]$6032 - attribute \src "libresoc.v:135909.3-135910.27" + attribute \src "libresoc.v:138406.3-138423.6" + wire width 154 $0\io_sr$next[153:0]$6077 + attribute \src "libresoc.v:137691.3-137692.27" wire width 154 $0\io_sr[153:0] - attribute \src "libresoc.v:136325.3-136357.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$5975 - attribute \src "libresoc.v:135857.3-135858.41" + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6020 + attribute \src "libresoc.v:137639.3-137640.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:136411.3-136437.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$5988 - attribute \src "libresoc.v:135853.3-135854.45" + attribute \src "libresoc.v:138193.3-138219.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6033 + attribute \src "libresoc.v:137635.3-137636.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:136036.3-136052.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5905 - attribute \src "libresoc.v:135893.3-135894.53" + attribute \src "libresoc.v:137818.3-137834.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5950 + attribute \src "libresoc.v:137675.3-137676.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:136053.3-136073.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5909 - attribute \src "libresoc.v:135891.3-135892.53" + attribute \src "libresoc.v:137835.3-137855.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5954 + attribute \src "libresoc.v:137673.3-137674.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:136018.3-136026.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5899 - attribute \src "libresoc.v:135897.3-135898.69" + attribute \src "libresoc.v:137800.3-137808.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5944 + attribute \src "libresoc.v:137679.3-137680.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:136027.3-136035.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5902 - attribute \src "libresoc.v:135895.3-135896.79" + attribute \src "libresoc.v:137809.3-137817.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 + attribute \src "libresoc.v:137677.3-137678.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:136438.3-136458.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$5993 - attribute \src "libresoc.v:135851.3-135852.51" + attribute \src "libresoc.v:138220.3-138240.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6038 + attribute \src "libresoc.v:137633.3-137634.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:136092.3-136108.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5920 - attribute \src "libresoc.v:135885.3-135886.53" + attribute \src "libresoc.v:137874.3-137890.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5965 + attribute \src "libresoc.v:137667.3-137668.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:136109.3-136129.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5924 - attribute \src "libresoc.v:135883.3-135884.53" + attribute \src "libresoc.v:137891.3-137911.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5969 + attribute \src "libresoc.v:137665.3-137666.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:136074.3-136082.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$5914 - attribute \src "libresoc.v:135889.3-135890.69" + attribute \src "libresoc.v:137856.3-137864.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$5959 + attribute \src "libresoc.v:137671.3-137672.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:136083.3-136091.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5917 - attribute \src "libresoc.v:135887.3-135888.79" + attribute \src "libresoc.v:137865.3-137873.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 + attribute \src "libresoc.v:137669.3-137670.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:135980.3-135996.6" - wire $0\sr0__oe$next[0:0]$5890 - attribute \src "libresoc.v:135901.3-135902.31" + attribute \src "libresoc.v:137762.3-137778.6" + wire $0\sr0__oe$next[0:0]$5935 + attribute \src "libresoc.v:137683.3-137684.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:135997.3-136017.6" - wire width 3 $0\sr0_reg$next[2:0]$5894 - attribute \src "libresoc.v:135899.3-135900.31" + attribute \src "libresoc.v:137779.3-137799.6" + wire width 3 $0\sr0_reg$next[2:0]$5939 + attribute \src "libresoc.v:137681.3-137682.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:135962.3-135970.6" - wire $0\sr0_update_core$next[0:0]$5884 - attribute \src "libresoc.v:135905.3-135906.47" + attribute \src "libresoc.v:137744.3-137752.6" + wire $0\sr0_update_core$next[0:0]$5929 + attribute \src "libresoc.v:137687.3-137688.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:135971.3-135979.6" - wire $0\sr0_update_core_prev$next[0:0]$5887 - attribute \src "libresoc.v:135903.3-135904.57" + attribute \src "libresoc.v:137753.3-137761.6" + wire $0\sr0_update_core_prev$next[0:0]$5932 + attribute \src "libresoc.v:137685.3-137686.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:136614.3-136623.6" + attribute \src "libresoc.v:138396.3-138405.6" wire width 3 $0\sr5__i[2:0] - attribute \src "libresoc.v:136260.3-136276.6" - wire $0\sr5__oe$next[0:0]$5965 - attribute \src "libresoc.v:135861.3-135862.31" + attribute \src "libresoc.v:138042.3-138058.6" + wire $0\sr5__oe$next[0:0]$6010 + attribute \src "libresoc.v:137643.3-137644.31" wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:136277.3-136297.6" - wire width 3 $0\sr5_reg$next[2:0]$5969 - attribute \src "libresoc.v:135859.3-135860.31" + attribute \src "libresoc.v:138059.3-138079.6" + wire width 3 $0\sr5_reg$next[2:0]$6014 + attribute \src "libresoc.v:137641.3-137642.31" wire width 3 $0\sr5_reg[2:0] - attribute \src "libresoc.v:136242.3-136250.6" - wire $0\sr5_update_core$next[0:0]$5959 - attribute \src "libresoc.v:135865.3-135866.47" + attribute \src "libresoc.v:138024.3-138032.6" + wire $0\sr5_update_core$next[0:0]$6004 + attribute \src "libresoc.v:137647.3-137648.47" wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:136251.3-136259.6" - wire $0\sr5_update_core_prev$next[0:0]$5962 - attribute \src "libresoc.v:135863.3-135864.57" + attribute \src "libresoc.v:138033.3-138041.6" + wire $0\sr5_update_core_prev$next[0:0]$6007 + attribute \src "libresoc.v:137645.3-137646.57" wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:136593.3-136613.6" - wire $0\wb_dcache_en$next[0:0]$6021 - attribute \src "libresoc.v:135839.3-135840.41" + attribute \src "libresoc.v:138375.3-138395.6" + wire $0\wb_dcache_en$next[0:0]$6066 + attribute \src "libresoc.v:137621.3-137622.41" wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:136593.3-136613.6" - wire $0\wb_icache_en$next[0:0]$6022 - attribute \src "libresoc.v:135837.3-135838.41" + attribute \src "libresoc.v:138375.3-138395.6" + wire $0\wb_icache_en$next[0:0]$6067 + attribute \src "libresoc.v:137619.3-137620.41" wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:136593.3-136613.6" - wire $0\wb_sram_en$next[0:0]$6023 - attribute \src "libresoc.v:135841.3-135842.37" + attribute \src "libresoc.v:138375.3-138395.6" + wire $0\wb_sram_en$next[0:0]$6068 + attribute \src "libresoc.v:137623.3-137624.37" wire $0\wb_sram_en[0:0] - attribute \src "libresoc.v:136298.3-136324.6" + attribute \src "libresoc.v:138080.3-138106.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:135946.3-135961.6" + attribute \src "libresoc.v:137728.3-137743.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:136459.3-136491.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$5999 - attribute \src "libresoc.v:134705.13-134705.32" + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6044 + attribute \src "libresoc.v:136486.13-136486.32" wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:136545.3-136571.6" - wire width 64 $1\dmi0__din$next[63:0]$6012 - attribute \src "libresoc.v:134710.14-134710.46" + attribute \src "libresoc.v:138327.3-138353.6" + wire width 64 $1\dmi0__din$next[63:0]$6057 + attribute \src "libresoc.v:136491.14-136491.46" wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:136148.3-136164.6" - wire $1\dmi0_addrsr__oe$next[0:0]$5936 - attribute \src "libresoc.v:134724.7-134724.29" + attribute \src "libresoc.v:137930.3-137946.6" + wire $1\dmi0_addrsr__oe$next[0:0]$5981 + attribute \src "libresoc.v:136505.7-136505.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:136165.3-136185.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5940 - attribute \src "libresoc.v:134732.13-134732.36" + attribute \src "libresoc.v:137947.3-137967.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5985 + attribute \src "libresoc.v:136513.13-136513.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:136130.3-136138.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$5930 - attribute \src "libresoc.v:134740.7-134740.37" + attribute \src "libresoc.v:137912.3-137920.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$5975 + attribute \src "libresoc.v:136521.7-136521.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:136139.3-136147.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5933 - attribute \src "libresoc.v:134744.7-134744.42" + attribute \src "libresoc.v:137921.3-137929.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 + attribute \src "libresoc.v:136525.7-136525.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:136572.3-136592.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$6017 - attribute \src "libresoc.v:134748.14-134748.51" + attribute \src "libresoc.v:138354.3-138374.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6062 + attribute \src "libresoc.v:136529.14-136529.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:136204.3-136220.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$5951 - attribute \src "libresoc.v:134754.13-134754.35" + attribute \src "libresoc.v:137986.3-138002.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$5996 + attribute \src "libresoc.v:136535.13-136535.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:136221.3-136241.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$5955 - attribute \src "libresoc.v:134762.14-134762.52" + attribute \src "libresoc.v:138003.3-138023.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$6000 + attribute \src "libresoc.v:136543.14-136543.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:136186.3-136194.6" - wire $1\dmi0_datasr_update_core$next[0:0]$5945 - attribute \src "libresoc.v:134770.7-134770.37" + attribute \src "libresoc.v:137968.3-137976.6" + wire $1\dmi0_datasr_update_core$next[0:0]$5990 + attribute \src "libresoc.v:136551.7-136551.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:136195.3-136203.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$5948 - attribute \src "libresoc.v:134774.7-134774.42" + attribute \src "libresoc.v:137977.3-137985.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$5993 + attribute \src "libresoc.v:136555.7-136555.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:136492.3-136544.6" - wire width 3 $1\fsm_state$503$next[2:0]$6005 - attribute \src "libresoc.v:136358.3-136410.6" - wire width 3 $1\fsm_state$next[2:0]$5982 - attribute \src "libresoc.v:134790.13-134790.29" + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $1\fsm_state$503$next[2:0]$6050 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $1\fsm_state$next[2:0]$6027 + attribute \src "libresoc.v:136571.13-136571.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:136642.3-136662.6" - wire width 154 $1\io_bd$next[153:0]$6037 - attribute \src "libresoc.v:134990.15-134990.67" + attribute \src "libresoc.v:138424.3-138444.6" + wire width 154 $1\io_bd$next[153:0]$6082 + attribute \src "libresoc.v:136771.15-136771.67" wire width 154 $1\io_bd[153:0] - attribute \src "libresoc.v:136624.3-136641.6" - wire width 154 $1\io_sr$next[153:0]$6033 - attribute \src "libresoc.v:135002.15-135002.67" + attribute \src "libresoc.v:138406.3-138423.6" + wire width 154 $1\io_sr$next[153:0]$6078 + attribute \src "libresoc.v:136783.15-136783.67" wire width 154 $1\io_sr[153:0] - attribute \src "libresoc.v:136325.3-136357.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$5976 - attribute \src "libresoc.v:135011.14-135011.41" + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6021 + attribute \src "libresoc.v:136792.14-136792.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:136411.3-136437.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$5989 - attribute \src "libresoc.v:135020.14-135020.51" + attribute \src "libresoc.v:138193.3-138219.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6034 + attribute \src "libresoc.v:136801.14-136801.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:136036.3-136052.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5906 - attribute \src "libresoc.v:135034.7-135034.32" + attribute \src "libresoc.v:137818.3-137834.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5951 + attribute \src "libresoc.v:136815.7-136815.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:136053.3-136073.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5910 - attribute \src "libresoc.v:135042.14-135042.47" + attribute \src "libresoc.v:137835.3-137855.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5955 + attribute \src "libresoc.v:136823.14-136823.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:136018.3-136026.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5900 - attribute \src "libresoc.v:135050.7-135050.40" + attribute \src "libresoc.v:137800.3-137808.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5945 + attribute \src "libresoc.v:136831.7-136831.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:136027.3-136035.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5903 - attribute \src "libresoc.v:135054.7-135054.45" + attribute \src "libresoc.v:137809.3-137817.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 + attribute \src "libresoc.v:136835.7-136835.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:136438.3-136458.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$5994 - attribute \src "libresoc.v:135058.14-135058.54" + attribute \src "libresoc.v:138220.3-138240.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6039 + attribute \src "libresoc.v:136839.14-136839.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:136092.3-136108.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5921 - attribute \src "libresoc.v:135064.13-135064.38" + attribute \src "libresoc.v:137874.3-137890.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5966 + attribute \src "libresoc.v:136845.13-136845.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:136109.3-136129.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5925 - attribute \src "libresoc.v:135072.14-135072.55" + attribute \src "libresoc.v:137891.3-137911.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5970 + attribute \src "libresoc.v:136853.14-136853.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:136074.3-136082.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$5915 - attribute \src "libresoc.v:135080.7-135080.40" + attribute \src "libresoc.v:137856.3-137864.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$5960 + attribute \src "libresoc.v:136861.7-136861.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:136083.3-136091.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5918 - attribute \src "libresoc.v:135084.7-135084.45" + attribute \src "libresoc.v:137865.3-137873.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 + attribute \src "libresoc.v:136865.7-136865.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:135980.3-135996.6" - wire $1\sr0__oe$next[0:0]$5891 - attribute \src "libresoc.v:135514.7-135514.21" + attribute \src "libresoc.v:137762.3-137778.6" + wire $1\sr0__oe$next[0:0]$5936 + attribute \src "libresoc.v:137295.7-137295.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:135997.3-136017.6" - wire width 3 $1\sr0_reg$next[2:0]$5895 - attribute \src "libresoc.v:135522.13-135522.27" + attribute \src "libresoc.v:137779.3-137799.6" + wire width 3 $1\sr0_reg$next[2:0]$5940 + attribute \src "libresoc.v:137303.13-137303.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:135962.3-135970.6" - wire $1\sr0_update_core$next[0:0]$5885 - attribute \src "libresoc.v:135530.7-135530.29" + attribute \src "libresoc.v:137744.3-137752.6" + wire $1\sr0_update_core$next[0:0]$5930 + attribute \src "libresoc.v:137311.7-137311.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:135971.3-135979.6" - wire $1\sr0_update_core_prev$next[0:0]$5888 - attribute \src "libresoc.v:135534.7-135534.34" + attribute \src "libresoc.v:137753.3-137761.6" + wire $1\sr0_update_core_prev$next[0:0]$5933 + attribute \src "libresoc.v:137315.7-137315.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:136614.3-136623.6" + attribute \src "libresoc.v:138396.3-138405.6" wire width 3 $1\sr5__i[2:0] - attribute \src "libresoc.v:136260.3-136276.6" - wire $1\sr5__oe$next[0:0]$5966 - attribute \src "libresoc.v:135544.7-135544.21" + attribute \src "libresoc.v:138042.3-138058.6" + wire $1\sr5__oe$next[0:0]$6011 + attribute \src "libresoc.v:137325.7-137325.21" wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:136277.3-136297.6" - wire width 3 $1\sr5_reg$next[2:0]$5970 - attribute \src "libresoc.v:135552.13-135552.27" + attribute \src "libresoc.v:138059.3-138079.6" + wire width 3 $1\sr5_reg$next[2:0]$6015 + attribute \src "libresoc.v:137333.13-137333.27" wire width 3 $1\sr5_reg[2:0] - attribute \src "libresoc.v:136242.3-136250.6" - wire $1\sr5_update_core$next[0:0]$5960 - attribute \src "libresoc.v:135560.7-135560.29" + attribute \src "libresoc.v:138024.3-138032.6" + wire $1\sr5_update_core$next[0:0]$6005 + attribute \src "libresoc.v:137341.7-137341.29" wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:136251.3-136259.6" - wire $1\sr5_update_core_prev$next[0:0]$5963 - attribute \src "libresoc.v:135564.7-135564.34" + attribute \src "libresoc.v:138033.3-138041.6" + wire $1\sr5_update_core_prev$next[0:0]$6008 + attribute \src "libresoc.v:137345.7-137345.34" wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:136593.3-136613.6" - wire $1\wb_dcache_en$next[0:0]$6024 - attribute \src "libresoc.v:135569.7-135569.26" + attribute \src "libresoc.v:138375.3-138395.6" + wire $1\wb_dcache_en$next[0:0]$6069 + attribute \src "libresoc.v:137350.7-137350.26" wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:136593.3-136613.6" - wire $1\wb_icache_en$next[0:0]$6025 - attribute \src "libresoc.v:135574.7-135574.26" + attribute \src "libresoc.v:138375.3-138395.6" + wire $1\wb_icache_en$next[0:0]$6070 + attribute \src "libresoc.v:137355.7-137355.26" wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:136593.3-136613.6" - wire $1\wb_sram_en$next[0:0]$6026 - attribute \src "libresoc.v:135578.7-135578.24" + attribute \src "libresoc.v:138375.3-138395.6" + wire $1\wb_sram_en$next[0:0]$6071 + attribute \src "libresoc.v:137360.7-137360.24" wire $1\wb_sram_en[0:0] - attribute \src "libresoc.v:136459.3-136491.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$6000 - attribute \src "libresoc.v:136545.3-136571.6" - wire width 64 $2\dmi0__din$next[63:0]$6013 - attribute \src "libresoc.v:136148.3-136164.6" - wire $2\dmi0_addrsr__oe$next[0:0]$5937 - attribute \src "libresoc.v:136165.3-136185.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5941 - attribute \src "libresoc.v:136572.3-136592.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$6018 - attribute \src "libresoc.v:136204.3-136220.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$5952 - attribute \src "libresoc.v:136221.3-136241.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$5956 - attribute \src "libresoc.v:136492.3-136544.6" - wire width 3 $2\fsm_state$503$next[2:0]$6006 - attribute \src "libresoc.v:136358.3-136410.6" - wire width 3 $2\fsm_state$next[2:0]$5983 - attribute \src "libresoc.v:136642.3-136662.6" - wire width 154 $2\io_bd$next[153:0]$6038 - attribute \src "libresoc.v:136624.3-136641.6" - wire width 154 $2\io_sr$next[153:0]$6034 - attribute \src "libresoc.v:136325.3-136357.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$5977 - attribute \src "libresoc.v:136411.3-136437.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$5990 - attribute \src "libresoc.v:136036.3-136052.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$5907 - attribute \src "libresoc.v:136053.3-136073.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5911 - attribute \src "libresoc.v:136438.3-136458.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$5995 - attribute \src "libresoc.v:136092.3-136108.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5922 - attribute \src "libresoc.v:136109.3-136129.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5926 - attribute \src "libresoc.v:135980.3-135996.6" - wire $2\sr0__oe$next[0:0]$5892 - attribute \src "libresoc.v:135997.3-136017.6" - wire width 3 $2\sr0_reg$next[2:0]$5896 - attribute \src "libresoc.v:136260.3-136276.6" - wire $2\sr5__oe$next[0:0]$5967 - attribute \src "libresoc.v:136277.3-136297.6" - wire width 3 $2\sr5_reg$next[2:0]$5971 - attribute \src "libresoc.v:136593.3-136613.6" - wire $2\wb_dcache_en$next[0:0]$6027 - attribute \src "libresoc.v:136593.3-136613.6" - wire $2\wb_icache_en$next[0:0]$6028 - attribute \src "libresoc.v:136593.3-136613.6" - wire $2\wb_sram_en$next[0:0]$6029 - attribute \src "libresoc.v:136459.3-136491.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$6001 - attribute \src "libresoc.v:136545.3-136571.6" - wire width 64 $3\dmi0__din$next[63:0]$6014 - attribute \src "libresoc.v:136165.3-136185.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5942 - attribute \src "libresoc.v:136572.3-136592.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$6019 - attribute \src "libresoc.v:136221.3-136241.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$5957 - attribute \src "libresoc.v:136492.3-136544.6" - wire width 3 $3\fsm_state$503$next[2:0]$6007 - attribute \src "libresoc.v:136358.3-136410.6" - wire width 3 $3\fsm_state$next[2:0]$5984 - attribute \src "libresoc.v:136325.3-136357.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$5978 - attribute \src "libresoc.v:136411.3-136437.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$5991 - attribute \src "libresoc.v:136053.3-136073.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5912 - attribute \src "libresoc.v:136438.3-136458.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$5996 - attribute \src "libresoc.v:136109.3-136129.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5927 - attribute \src "libresoc.v:135997.3-136017.6" - wire width 3 $3\sr0_reg$next[2:0]$5897 - attribute \src "libresoc.v:136277.3-136297.6" - wire width 3 $3\sr5_reg$next[2:0]$5972 - attribute \src "libresoc.v:136459.3-136491.6" - wire width 4 $4\dmi0__addr_i$next[3:0]$6002 - attribute \src "libresoc.v:136492.3-136544.6" - wire width 3 $4\fsm_state$503$next[2:0]$6008 - attribute \src "libresoc.v:136358.3-136410.6" - wire width 3 $4\fsm_state$next[2:0]$5985 - attribute \src "libresoc.v:136325.3-136357.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$5979 - attribute \src "libresoc.v:136492.3-136544.6" - wire width 3 $5\fsm_state$503$next[2:0]$6009 - attribute \src "libresoc.v:136358.3-136410.6" - wire width 3 $5\fsm_state$next[2:0]$5986 - attribute \src "libresoc.v:135801.19-135801.112" - wire width 30 $add$libresoc.v:135801$5807_Y - attribute \src "libresoc.v:135803.19-135803.112" - wire width 30 $add$libresoc.v:135803$5809_Y - attribute \src "libresoc.v:135809.19-135809.112" - wire width 5 $add$libresoc.v:135809$5816_Y - attribute \src "libresoc.v:135810.19-135810.112" - wire width 5 $add$libresoc.v:135810$5817_Y - attribute \src "libresoc.v:135625.18-135625.112" - wire $and$libresoc.v:135625$5631_Y - attribute \src "libresoc.v:135692.18-135692.108" - wire $and$libresoc.v:135692$5698_Y - attribute \src "libresoc.v:135703.18-135703.110" - wire $and$libresoc.v:135703$5709_Y - attribute \src "libresoc.v:135731.19-135731.110" - wire $and$libresoc.v:135731$5737_Y - attribute \src "libresoc.v:135734.19-135734.114" - wire $and$libresoc.v:135734$5740_Y - attribute \src "libresoc.v:135737.19-135737.112" - wire $and$libresoc.v:135737$5743_Y - attribute \src "libresoc.v:135739.19-135739.113" - wire $and$libresoc.v:135739$5745_Y - attribute \src "libresoc.v:135741.19-135741.121" - wire $and$libresoc.v:135741$5747_Y - attribute \src "libresoc.v:135744.19-135744.114" - wire $and$libresoc.v:135744$5750_Y - attribute \src "libresoc.v:135746.19-135746.112" - wire $and$libresoc.v:135746$5752_Y - attribute \src "libresoc.v:135750.19-135750.113" - wire $and$libresoc.v:135750$5756_Y - attribute \src "libresoc.v:135752.19-135752.132" - wire $and$libresoc.v:135752$5758_Y - attribute \src "libresoc.v:135756.19-135756.114" - wire $and$libresoc.v:135756$5762_Y - attribute \src "libresoc.v:135758.19-135758.112" - wire $and$libresoc.v:135758$5764_Y - attribute \src "libresoc.v:135761.19-135761.113" - wire $and$libresoc.v:135761$5767_Y - attribute \src "libresoc.v:135763.19-135763.132" - wire $and$libresoc.v:135763$5769_Y - attribute \src "libresoc.v:135766.19-135766.114" - wire $and$libresoc.v:135766$5772_Y - attribute \src "libresoc.v:135768.19-135768.112" - wire $and$libresoc.v:135768$5774_Y - attribute \src "libresoc.v:135770.18-135770.108" - wire $and$libresoc.v:135770$5776_Y - attribute \src "libresoc.v:135771.19-135771.113" - wire $and$libresoc.v:135771$5777_Y - attribute \src "libresoc.v:135773.19-135773.129" - wire $and$libresoc.v:135773$5779_Y - attribute \src "libresoc.v:135777.19-135777.114" - wire $and$libresoc.v:135777$5783_Y - attribute \src "libresoc.v:135779.19-135779.112" - wire $and$libresoc.v:135779$5785_Y - attribute \src "libresoc.v:135781.18-135781.111" - wire $and$libresoc.v:135781$5787_Y - attribute \src "libresoc.v:135782.19-135782.113" - wire $and$libresoc.v:135782$5788_Y - attribute \src "libresoc.v:135784.19-135784.129" - wire $and$libresoc.v:135784$5790_Y - attribute \src "libresoc.v:135787.19-135787.114" - wire $and$libresoc.v:135787$5793_Y - attribute \src "libresoc.v:135789.19-135789.112" - wire $and$libresoc.v:135789$5795_Y - attribute \src "libresoc.v:135791.19-135791.113" - wire $and$libresoc.v:135791$5797_Y - attribute \src "libresoc.v:135794.19-135794.121" - wire $and$libresoc.v:135794$5800_Y - attribute \src "libresoc.v:135826.17-135826.106" - wire $and$libresoc.v:135826$5833_Y - attribute \src "libresoc.v:135581.17-135581.110" - wire $eq$libresoc.v:135581$5587_Y - attribute \src "libresoc.v:135592.18-135592.111" - wire $eq$libresoc.v:135592$5598_Y - attribute \src "libresoc.v:135603.18-135603.111" - wire $eq$libresoc.v:135603$5609_Y - attribute \src "libresoc.v:135636.17-135636.110" - wire $eq$libresoc.v:135636$5642_Y - attribute \src "libresoc.v:135637.18-135637.111" - wire $eq$libresoc.v:135637$5643_Y - attribute \src "libresoc.v:135648.18-135648.111" - wire $eq$libresoc.v:135648$5654_Y - attribute \src "libresoc.v:135670.18-135670.111" - wire $eq$libresoc.v:135670$5676_Y - attribute \src "libresoc.v:135714.18-135714.111" - wire $eq$libresoc.v:135714$5720_Y - attribute \src "libresoc.v:135725.18-135725.111" - wire $eq$libresoc.v:135725$5731_Y - attribute \src "libresoc.v:135726.19-135726.112" - wire $eq$libresoc.v:135726$5732_Y - attribute \src "libresoc.v:135727.19-135727.112" - wire $eq$libresoc.v:135727$5733_Y - attribute \src "libresoc.v:135729.19-135729.112" - wire $eq$libresoc.v:135729$5735_Y - attribute \src "libresoc.v:135732.19-135732.112" - wire $eq$libresoc.v:135732$5738_Y - attribute \src "libresoc.v:135742.19-135742.112" - wire $eq$libresoc.v:135742$5748_Y - attribute \src "libresoc.v:135747.17-135747.110" - wire $eq$libresoc.v:135747$5753_Y - attribute \src "libresoc.v:135748.18-135748.111" - wire $eq$libresoc.v:135748$5754_Y - attribute \src "libresoc.v:135753.19-135753.112" - wire $eq$libresoc.v:135753$5759_Y - attribute \src "libresoc.v:135754.19-135754.112" - wire $eq$libresoc.v:135754$5760_Y - attribute \src "libresoc.v:135764.19-135764.112" - wire $eq$libresoc.v:135764$5770_Y - attribute \src "libresoc.v:135774.19-135774.112" - wire $eq$libresoc.v:135774$5780_Y - attribute \src "libresoc.v:135775.19-135775.112" - wire $eq$libresoc.v:135775$5781_Y - attribute \src "libresoc.v:135785.19-135785.112" - wire $eq$libresoc.v:135785$5791_Y - attribute \src "libresoc.v:135792.18-135792.111" - wire $eq$libresoc.v:135792$5798_Y - attribute \src "libresoc.v:135795.19-135795.110" - wire $eq$libresoc.v:135795$5801_Y - attribute \src "libresoc.v:135797.19-135797.110" - wire $eq$libresoc.v:135797$5803_Y - attribute \src "libresoc.v:135798.19-135798.110" - wire $eq$libresoc.v:135798$5804_Y - attribute \src "libresoc.v:135800.19-135800.110" - wire $eq$libresoc.v:135800$5806_Y - attribute \src "libresoc.v:135802.18-135802.111" - wire $eq$libresoc.v:135802$5808_Y - attribute \src "libresoc.v:135805.19-135805.116" - wire $eq$libresoc.v:135805$5812_Y - attribute \src "libresoc.v:135806.19-135806.116" - wire $eq$libresoc.v:135806$5813_Y - attribute \src "libresoc.v:135808.19-135808.116" - wire $eq$libresoc.v:135808$5815_Y - attribute \src "libresoc.v:135804.19-135804.106" - wire width 8 $extend$libresoc.v:135804$5810_Y - attribute \src "libresoc.v:135733.19-135733.109" - wire $ne$libresoc.v:135733$5739_Y - attribute \src "libresoc.v:135735.19-135735.109" - wire $ne$libresoc.v:135735$5741_Y - attribute \src "libresoc.v:135738.19-135738.109" - wire $ne$libresoc.v:135738$5744_Y - attribute \src "libresoc.v:135743.19-135743.120" - wire $ne$libresoc.v:135743$5749_Y - attribute \src "libresoc.v:135745.19-135745.120" - wire $ne$libresoc.v:135745$5751_Y - attribute \src "libresoc.v:135749.19-135749.120" - wire $ne$libresoc.v:135749$5755_Y - attribute \src "libresoc.v:135755.19-135755.120" - wire $ne$libresoc.v:135755$5761_Y - attribute \src "libresoc.v:135757.19-135757.120" - wire $ne$libresoc.v:135757$5763_Y - attribute \src "libresoc.v:135760.19-135760.120" - wire $ne$libresoc.v:135760$5766_Y - attribute \src "libresoc.v:135765.19-135765.117" - wire $ne$libresoc.v:135765$5771_Y - attribute \src "libresoc.v:135767.19-135767.117" - wire $ne$libresoc.v:135767$5773_Y - attribute \src "libresoc.v:135769.19-135769.117" - wire $ne$libresoc.v:135769$5775_Y - attribute \src "libresoc.v:135776.19-135776.117" - wire $ne$libresoc.v:135776$5782_Y - attribute \src "libresoc.v:135778.19-135778.117" - wire $ne$libresoc.v:135778$5784_Y - attribute \src "libresoc.v:135780.19-135780.117" - wire $ne$libresoc.v:135780$5786_Y - attribute \src "libresoc.v:135786.19-135786.109" - wire $ne$libresoc.v:135786$5792_Y - attribute \src "libresoc.v:135788.19-135788.109" - wire $ne$libresoc.v:135788$5794_Y - attribute \src "libresoc.v:135790.19-135790.109" - wire $ne$libresoc.v:135790$5796_Y - attribute \src "libresoc.v:135740.19-135740.110" - wire $not$libresoc.v:135740$5746_Y - attribute \src "libresoc.v:135751.19-135751.121" - wire $not$libresoc.v:135751$5757_Y - attribute \src "libresoc.v:135762.19-135762.121" - wire $not$libresoc.v:135762$5768_Y - attribute \src "libresoc.v:135772.19-135772.118" - wire $not$libresoc.v:135772$5778_Y - attribute \src "libresoc.v:135783.19-135783.118" - wire $not$libresoc.v:135783$5789_Y - attribute \src "libresoc.v:135793.19-135793.110" - wire $not$libresoc.v:135793$5799_Y - attribute \src "libresoc.v:135796.19-135796.100" - wire $not$libresoc.v:135796$5802_Y - attribute \src "libresoc.v:135614.18-135614.104" - wire $or$libresoc.v:135614$5620_Y - attribute \src "libresoc.v:135659.18-135659.104" - wire $or$libresoc.v:135659$5665_Y - attribute \src "libresoc.v:135681.18-135681.104" - wire $or$libresoc.v:135681$5687_Y - attribute \src "libresoc.v:135728.19-135728.107" - wire $or$libresoc.v:135728$5734_Y - attribute \src "libresoc.v:135730.19-135730.107" - wire $or$libresoc.v:135730$5736_Y - attribute \src "libresoc.v:135736.18-135736.104" - wire $or$libresoc.v:135736$5742_Y - attribute \src "libresoc.v:135759.18-135759.104" - wire $or$libresoc.v:135759$5765_Y - attribute \src "libresoc.v:135799.19-135799.107" - wire $or$libresoc.v:135799$5805_Y - attribute \src "libresoc.v:135807.19-135807.107" - wire $or$libresoc.v:135807$5814_Y - attribute \src "libresoc.v:135815.17-135815.101" - wire $or$libresoc.v:135815$5822_Y - attribute \src "libresoc.v:135804.19-135804.106" - wire width 8 $pos$libresoc.v:135804$5811_Y - attribute \src "libresoc.v:135582.18-135582.133" - wire $ternary$libresoc.v:135582$5588_Y - attribute \src "libresoc.v:135583.19-135583.133" - wire $ternary$libresoc.v:135583$5589_Y - attribute \src "libresoc.v:135584.19-135584.134" - wire $ternary$libresoc.v:135584$5590_Y - attribute \src "libresoc.v:135585.19-135585.133" - wire $ternary$libresoc.v:135585$5591_Y - attribute \src "libresoc.v:135586.19-135586.132" - wire $ternary$libresoc.v:135586$5592_Y - attribute \src "libresoc.v:135587.19-135587.133" - wire $ternary$libresoc.v:135587$5593_Y - attribute \src "libresoc.v:135588.19-135588.133" - wire $ternary$libresoc.v:135588$5594_Y - attribute \src "libresoc.v:135589.19-135589.132" - wire $ternary$libresoc.v:135589$5595_Y - attribute \src "libresoc.v:135590.19-135590.133" - wire $ternary$libresoc.v:135590$5596_Y - attribute \src "libresoc.v:135591.19-135591.133" - wire $ternary$libresoc.v:135591$5597_Y - attribute \src "libresoc.v:135593.19-135593.132" - wire $ternary$libresoc.v:135593$5599_Y - attribute \src "libresoc.v:135594.19-135594.133" - wire $ternary$libresoc.v:135594$5600_Y - attribute \src "libresoc.v:135595.19-135595.133" - wire $ternary$libresoc.v:135595$5601_Y - attribute \src "libresoc.v:135596.19-135596.132" - wire $ternary$libresoc.v:135596$5602_Y - attribute \src "libresoc.v:135597.19-135597.133" - wire $ternary$libresoc.v:135597$5603_Y - attribute \src "libresoc.v:135598.19-135598.133" - wire $ternary$libresoc.v:135598$5604_Y - attribute \src "libresoc.v:135599.19-135599.132" - wire $ternary$libresoc.v:135599$5605_Y - attribute \src "libresoc.v:135600.19-135600.133" - wire $ternary$libresoc.v:135600$5606_Y - attribute \src "libresoc.v:135601.19-135601.133" - wire $ternary$libresoc.v:135601$5607_Y - attribute \src "libresoc.v:135602.19-135602.132" - wire $ternary$libresoc.v:135602$5608_Y - attribute \src "libresoc.v:135604.19-135604.133" - wire $ternary$libresoc.v:135604$5610_Y - attribute \src "libresoc.v:135605.19-135605.133" - wire $ternary$libresoc.v:135605$5611_Y - attribute \src "libresoc.v:135606.19-135606.132" - wire $ternary$libresoc.v:135606$5612_Y - attribute \src "libresoc.v:135607.19-135607.133" - wire $ternary$libresoc.v:135607$5613_Y - attribute \src "libresoc.v:135608.19-135608.133" - wire $ternary$libresoc.v:135608$5614_Y - attribute \src "libresoc.v:135609.19-135609.132" - wire $ternary$libresoc.v:135609$5615_Y - attribute \src "libresoc.v:135610.19-135610.133" - wire $ternary$libresoc.v:135610$5616_Y - attribute \src "libresoc.v:135611.19-135611.134" - wire $ternary$libresoc.v:135611$5617_Y - attribute \src "libresoc.v:135612.19-135612.135" - wire $ternary$libresoc.v:135612$5618_Y - attribute \src "libresoc.v:135613.19-135613.135" - wire $ternary$libresoc.v:135613$5619_Y - attribute \src "libresoc.v:135615.19-135615.136" - wire $ternary$libresoc.v:135615$5621_Y - attribute \src "libresoc.v:135616.19-135616.134" - wire $ternary$libresoc.v:135616$5622_Y - attribute \src "libresoc.v:135617.19-135617.135" - wire $ternary$libresoc.v:135617$5623_Y - attribute \src "libresoc.v:135618.19-135618.135" - wire $ternary$libresoc.v:135618$5624_Y - attribute \src "libresoc.v:135619.19-135619.136" - wire $ternary$libresoc.v:135619$5625_Y - attribute \src "libresoc.v:135620.19-135620.134" - wire $ternary$libresoc.v:135620$5626_Y - attribute \src "libresoc.v:135621.19-135621.133" - wire $ternary$libresoc.v:135621$5627_Y - attribute \src "libresoc.v:135622.19-135622.134" - wire $ternary$libresoc.v:135622$5628_Y - attribute \src "libresoc.v:135623.19-135623.133" - wire $ternary$libresoc.v:135623$5629_Y - attribute \src "libresoc.v:135624.19-135624.130" - wire $ternary$libresoc.v:135624$5630_Y - attribute \src "libresoc.v:135626.19-135626.130" - wire $ternary$libresoc.v:135626$5632_Y - attribute \src "libresoc.v:135627.19-135627.133" - wire $ternary$libresoc.v:135627$5633_Y - attribute \src "libresoc.v:135628.19-135628.132" - wire $ternary$libresoc.v:135628$5634_Y - attribute \src "libresoc.v:135629.19-135629.133" - wire $ternary$libresoc.v:135629$5635_Y - attribute \src "libresoc.v:135630.19-135630.132" - wire $ternary$libresoc.v:135630$5636_Y - attribute \src "libresoc.v:135631.19-135631.135" - wire $ternary$libresoc.v:135631$5637_Y - attribute \src "libresoc.v:135632.19-135632.134" - wire $ternary$libresoc.v:135632$5638_Y - attribute \src "libresoc.v:135633.19-135633.135" - wire $ternary$libresoc.v:135633$5639_Y - attribute \src "libresoc.v:135634.19-135634.135" - wire $ternary$libresoc.v:135634$5640_Y - attribute \src "libresoc.v:135635.19-135635.134" - wire $ternary$libresoc.v:135635$5641_Y - attribute \src "libresoc.v:135638.19-135638.135" - wire $ternary$libresoc.v:135638$5644_Y - attribute \src "libresoc.v:135639.19-135639.135" - wire $ternary$libresoc.v:135639$5645_Y - attribute \src "libresoc.v:135640.19-135640.134" - wire $ternary$libresoc.v:135640$5646_Y - attribute \src "libresoc.v:135641.19-135641.135" - wire $ternary$libresoc.v:135641$5647_Y - attribute \src "libresoc.v:135642.19-135642.135" - wire $ternary$libresoc.v:135642$5648_Y - attribute \src "libresoc.v:135643.19-135643.134" - wire $ternary$libresoc.v:135643$5649_Y - attribute \src "libresoc.v:135644.19-135644.135" - wire $ternary$libresoc.v:135644$5650_Y - attribute \src "libresoc.v:135645.19-135645.133" - wire $ternary$libresoc.v:135645$5651_Y - attribute \src "libresoc.v:135646.19-135646.134" - wire $ternary$libresoc.v:135646$5652_Y - attribute \src "libresoc.v:135647.19-135647.133" - wire $ternary$libresoc.v:135647$5653_Y - attribute \src "libresoc.v:135649.19-135649.134" - wire $ternary$libresoc.v:135649$5655_Y - attribute \src "libresoc.v:135650.19-135650.134" - wire $ternary$libresoc.v:135650$5656_Y - attribute \src "libresoc.v:135651.19-135651.133" - wire $ternary$libresoc.v:135651$5657_Y - attribute \src "libresoc.v:135652.19-135652.134" - wire $ternary$libresoc.v:135652$5658_Y - attribute \src "libresoc.v:135653.19-135653.134" - wire $ternary$libresoc.v:135653$5659_Y - attribute \src "libresoc.v:135654.19-135654.133" - wire $ternary$libresoc.v:135654$5660_Y - attribute \src "libresoc.v:135655.19-135655.134" - wire $ternary$libresoc.v:135655$5661_Y - attribute \src "libresoc.v:135656.19-135656.134" - wire $ternary$libresoc.v:135656$5662_Y - attribute \src "libresoc.v:135657.19-135657.133" - wire $ternary$libresoc.v:135657$5663_Y - attribute \src "libresoc.v:135658.19-135658.134" - wire $ternary$libresoc.v:135658$5664_Y - attribute \src "libresoc.v:135660.19-135660.134" - wire $ternary$libresoc.v:135660$5666_Y - attribute \src "libresoc.v:135661.19-135661.133" - wire $ternary$libresoc.v:135661$5667_Y - attribute \src "libresoc.v:135662.19-135662.134" - wire $ternary$libresoc.v:135662$5668_Y - attribute \src "libresoc.v:135663.19-135663.134" - wire $ternary$libresoc.v:135663$5669_Y - attribute \src "libresoc.v:135664.19-135664.133" - wire $ternary$libresoc.v:135664$5670_Y - attribute \src "libresoc.v:135665.19-135665.134" - wire $ternary$libresoc.v:135665$5671_Y - attribute \src "libresoc.v:135666.19-135666.135" - wire $ternary$libresoc.v:135666$5672_Y - attribute \src "libresoc.v:135667.19-135667.134" - wire $ternary$libresoc.v:135667$5673_Y - attribute \src "libresoc.v:135668.19-135668.135" - wire $ternary$libresoc.v:135668$5674_Y - attribute \src "libresoc.v:135669.19-135669.135" - wire $ternary$libresoc.v:135669$5675_Y - attribute \src "libresoc.v:135671.19-135671.134" - wire $ternary$libresoc.v:135671$5677_Y - attribute \src "libresoc.v:135672.19-135672.135" - wire $ternary$libresoc.v:135672$5678_Y - attribute \src "libresoc.v:135673.19-135673.133" - wire $ternary$libresoc.v:135673$5679_Y - attribute \src "libresoc.v:135674.19-135674.133" - wire $ternary$libresoc.v:135674$5680_Y - attribute \src "libresoc.v:135675.19-135675.133" - wire $ternary$libresoc.v:135675$5681_Y - attribute \src "libresoc.v:135676.19-135676.133" - wire $ternary$libresoc.v:135676$5682_Y - attribute \src "libresoc.v:135677.19-135677.133" - wire $ternary$libresoc.v:135677$5683_Y - attribute \src "libresoc.v:135678.19-135678.133" - wire $ternary$libresoc.v:135678$5684_Y - attribute \src "libresoc.v:135679.19-135679.133" - wire $ternary$libresoc.v:135679$5685_Y - attribute \src "libresoc.v:135680.19-135680.133" - wire $ternary$libresoc.v:135680$5686_Y - attribute \src "libresoc.v:135682.19-135682.133" - wire $ternary$libresoc.v:135682$5688_Y - attribute \src "libresoc.v:135683.19-135683.133" - wire $ternary$libresoc.v:135683$5689_Y - attribute \src "libresoc.v:135684.19-135684.134" - wire $ternary$libresoc.v:135684$5690_Y - attribute \src "libresoc.v:135685.19-135685.134" - wire $ternary$libresoc.v:135685$5691_Y - attribute \src "libresoc.v:135686.19-135686.135" - wire $ternary$libresoc.v:135686$5692_Y - attribute \src "libresoc.v:135687.19-135687.133" - wire $ternary$libresoc.v:135687$5693_Y - attribute \src "libresoc.v:135688.19-135688.135" - wire $ternary$libresoc.v:135688$5694_Y - attribute \src "libresoc.v:135689.19-135689.135" - wire $ternary$libresoc.v:135689$5695_Y - attribute \src "libresoc.v:135690.19-135690.134" - wire $ternary$libresoc.v:135690$5696_Y - attribute \src "libresoc.v:135691.19-135691.134" - wire $ternary$libresoc.v:135691$5697_Y - attribute \src "libresoc.v:135693.19-135693.134" - wire $ternary$libresoc.v:135693$5699_Y - attribute \src "libresoc.v:135694.19-135694.134" - wire $ternary$libresoc.v:135694$5700_Y - attribute \src "libresoc.v:135695.19-135695.134" - wire $ternary$libresoc.v:135695$5701_Y - attribute \src "libresoc.v:135696.19-135696.135" - wire $ternary$libresoc.v:135696$5702_Y - attribute \src "libresoc.v:135697.19-135697.134" - wire $ternary$libresoc.v:135697$5703_Y - attribute \src "libresoc.v:135698.19-135698.135" - wire $ternary$libresoc.v:135698$5704_Y - attribute \src "libresoc.v:135699.19-135699.135" - wire $ternary$libresoc.v:135699$5705_Y - attribute \src "libresoc.v:135700.19-135700.134" - wire $ternary$libresoc.v:135700$5706_Y - attribute \src "libresoc.v:135701.19-135701.135" - wire $ternary$libresoc.v:135701$5707_Y - attribute \src "libresoc.v:135702.19-135702.135" - wire $ternary$libresoc.v:135702$5708_Y - attribute \src "libresoc.v:135704.19-135704.134" - wire $ternary$libresoc.v:135704$5710_Y - attribute \src "libresoc.v:135705.19-135705.135" - wire $ternary$libresoc.v:135705$5711_Y - attribute \src "libresoc.v:135706.19-135706.136" - wire $ternary$libresoc.v:135706$5712_Y - attribute \src "libresoc.v:135707.19-135707.135" - wire $ternary$libresoc.v:135707$5713_Y - attribute \src "libresoc.v:135708.19-135708.136" - wire $ternary$libresoc.v:135708$5714_Y - attribute \src "libresoc.v:135709.19-135709.136" - wire $ternary$libresoc.v:135709$5715_Y - attribute \src "libresoc.v:135710.19-135710.135" - wire $ternary$libresoc.v:135710$5716_Y - attribute \src "libresoc.v:135711.19-135711.136" - wire $ternary$libresoc.v:135711$5717_Y - attribute \src "libresoc.v:135712.19-135712.136" - wire $ternary$libresoc.v:135712$5718_Y - attribute \src "libresoc.v:135713.19-135713.135" - wire $ternary$libresoc.v:135713$5719_Y - attribute \src "libresoc.v:135715.19-135715.136" - wire $ternary$libresoc.v:135715$5721_Y - attribute \src "libresoc.v:135716.19-135716.136" - wire $ternary$libresoc.v:135716$5722_Y - attribute \src "libresoc.v:135717.19-135717.135" - wire $ternary$libresoc.v:135717$5723_Y - attribute \src "libresoc.v:135718.19-135718.136" - wire $ternary$libresoc.v:135718$5724_Y - attribute \src "libresoc.v:135719.19-135719.136" - wire $ternary$libresoc.v:135719$5725_Y - attribute \src "libresoc.v:135720.19-135720.135" - wire $ternary$libresoc.v:135720$5726_Y - attribute \src "libresoc.v:135721.19-135721.136" - wire $ternary$libresoc.v:135721$5727_Y - attribute \src "libresoc.v:135722.19-135722.136" - wire $ternary$libresoc.v:135722$5728_Y - attribute \src "libresoc.v:135723.19-135723.135" - wire $ternary$libresoc.v:135723$5729_Y - attribute \src "libresoc.v:135724.19-135724.136" - wire $ternary$libresoc.v:135724$5730_Y - attribute \src "libresoc.v:135811.18-135811.130" - wire $ternary$libresoc.v:135811$5818_Y - attribute \src "libresoc.v:135812.18-135812.130" - wire $ternary$libresoc.v:135812$5819_Y - attribute \src "libresoc.v:135813.18-135813.130" - wire $ternary$libresoc.v:135813$5820_Y - attribute \src "libresoc.v:135814.18-135814.131" - wire $ternary$libresoc.v:135814$5821_Y - attribute \src "libresoc.v:135816.18-135816.130" - wire $ternary$libresoc.v:135816$5823_Y - attribute \src "libresoc.v:135817.18-135817.131" - wire $ternary$libresoc.v:135817$5824_Y - attribute \src "libresoc.v:135818.18-135818.131" - wire $ternary$libresoc.v:135818$5825_Y - attribute \src "libresoc.v:135819.18-135819.130" - wire $ternary$libresoc.v:135819$5826_Y - attribute \src "libresoc.v:135820.18-135820.131" - wire $ternary$libresoc.v:135820$5827_Y - attribute \src "libresoc.v:135821.18-135821.132" - wire $ternary$libresoc.v:135821$5828_Y - attribute \src "libresoc.v:135822.18-135822.132" - wire $ternary$libresoc.v:135822$5829_Y - attribute \src "libresoc.v:135823.18-135823.133" - wire $ternary$libresoc.v:135823$5830_Y - attribute \src "libresoc.v:135824.18-135824.133" - wire $ternary$libresoc.v:135824$5831_Y - attribute \src "libresoc.v:135825.18-135825.132" - wire $ternary$libresoc.v:135825$5832_Y - attribute \src "libresoc.v:135827.18-135827.133" - wire $ternary$libresoc.v:135827$5834_Y - attribute \src "libresoc.v:135828.18-135828.133" - wire $ternary$libresoc.v:135828$5835_Y - attribute \src "libresoc.v:135829.18-135829.132" - wire $ternary$libresoc.v:135829$5836_Y - attribute \src "libresoc.v:135830.18-135830.133" - wire $ternary$libresoc.v:135830$5837_Y - attribute \src "libresoc.v:135831.18-135831.133" - wire $ternary$libresoc.v:135831$5838_Y - attribute \src "libresoc.v:135832.18-135832.132" - wire $ternary$libresoc.v:135832$5839_Y - attribute \src "libresoc.v:135833.18-135833.133" - wire $ternary$libresoc.v:135833$5840_Y - attribute \src "libresoc.v:135834.18-135834.133" - wire $ternary$libresoc.v:135834$5841_Y - attribute \src "libresoc.v:135835.18-135835.132" - wire $ternary$libresoc.v:135835$5842_Y - attribute \src "libresoc.v:135836.18-135836.133" - wire $ternary$libresoc.v:135836$5843_Y + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6045 + attribute \src "libresoc.v:138327.3-138353.6" + wire width 64 $2\dmi0__din$next[63:0]$6058 + attribute \src "libresoc.v:137930.3-137946.6" + wire $2\dmi0_addrsr__oe$next[0:0]$5982 + attribute \src "libresoc.v:137947.3-137967.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5986 + attribute \src "libresoc.v:138354.3-138374.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6063 + attribute \src "libresoc.v:137986.3-138002.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$5997 + attribute \src "libresoc.v:138003.3-138023.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$6001 + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $2\fsm_state$503$next[2:0]$6051 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $2\fsm_state$next[2:0]$6028 + attribute \src "libresoc.v:138424.3-138444.6" + wire width 154 $2\io_bd$next[153:0]$6083 + attribute \src "libresoc.v:138406.3-138423.6" + wire width 154 $2\io_sr$next[153:0]$6079 + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6022 + attribute \src "libresoc.v:138193.3-138219.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6035 + attribute \src "libresoc.v:137818.3-137834.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$5952 + attribute \src "libresoc.v:137835.3-137855.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5956 + attribute \src "libresoc.v:138220.3-138240.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6040 + attribute \src "libresoc.v:137874.3-137890.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5967 + attribute \src "libresoc.v:137891.3-137911.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5971 + attribute \src "libresoc.v:137762.3-137778.6" + wire $2\sr0__oe$next[0:0]$5937 + attribute \src "libresoc.v:137779.3-137799.6" + wire width 3 $2\sr0_reg$next[2:0]$5941 + attribute \src "libresoc.v:138042.3-138058.6" + wire $2\sr5__oe$next[0:0]$6012 + attribute \src "libresoc.v:138059.3-138079.6" + wire width 3 $2\sr5_reg$next[2:0]$6016 + attribute \src "libresoc.v:138375.3-138395.6" + wire $2\wb_dcache_en$next[0:0]$6072 + attribute \src "libresoc.v:138375.3-138395.6" + wire $2\wb_icache_en$next[0:0]$6073 + attribute \src "libresoc.v:138375.3-138395.6" + wire $2\wb_sram_en$next[0:0]$6074 + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6046 + attribute \src "libresoc.v:138327.3-138353.6" + wire width 64 $3\dmi0__din$next[63:0]$6059 + attribute \src "libresoc.v:137947.3-137967.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5987 + attribute \src "libresoc.v:138354.3-138374.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6064 + attribute \src "libresoc.v:138003.3-138023.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$6002 + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $3\fsm_state$503$next[2:0]$6052 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $3\fsm_state$next[2:0]$6029 + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$6023 + attribute \src "libresoc.v:138193.3-138219.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$6036 + attribute \src "libresoc.v:137835.3-137855.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5957 + attribute \src "libresoc.v:138220.3-138240.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6041 + attribute \src "libresoc.v:137891.3-137911.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5972 + attribute \src "libresoc.v:137779.3-137799.6" + wire width 3 $3\sr0_reg$next[2:0]$5942 + attribute \src "libresoc.v:138059.3-138079.6" + wire width 3 $3\sr5_reg$next[2:0]$6017 + attribute \src "libresoc.v:138241.3-138273.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$6047 + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $4\fsm_state$503$next[2:0]$6053 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $4\fsm_state$next[2:0]$6030 + attribute \src "libresoc.v:138107.3-138139.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$6024 + attribute \src "libresoc.v:138274.3-138326.6" + wire width 3 $5\fsm_state$503$next[2:0]$6054 + attribute \src "libresoc.v:138140.3-138192.6" + wire width 3 $5\fsm_state$next[2:0]$6031 + attribute \src "libresoc.v:137583.19-137583.112" + wire width 30 $add$libresoc.v:137583$5852_Y + attribute \src "libresoc.v:137585.19-137585.112" + wire width 30 $add$libresoc.v:137585$5854_Y + attribute \src "libresoc.v:137591.19-137591.112" + wire width 5 $add$libresoc.v:137591$5861_Y + attribute \src "libresoc.v:137592.19-137592.112" + wire width 5 $add$libresoc.v:137592$5862_Y + attribute \src "libresoc.v:137407.18-137407.112" + wire $and$libresoc.v:137407$5676_Y + attribute \src "libresoc.v:137474.18-137474.108" + wire $and$libresoc.v:137474$5743_Y + attribute \src "libresoc.v:137485.18-137485.110" + wire $and$libresoc.v:137485$5754_Y + attribute \src "libresoc.v:137513.19-137513.110" + wire $and$libresoc.v:137513$5782_Y + attribute \src "libresoc.v:137516.19-137516.114" + wire $and$libresoc.v:137516$5785_Y + attribute \src "libresoc.v:137519.19-137519.112" + wire $and$libresoc.v:137519$5788_Y + attribute \src "libresoc.v:137521.19-137521.113" + wire $and$libresoc.v:137521$5790_Y + attribute \src "libresoc.v:137523.19-137523.121" + wire $and$libresoc.v:137523$5792_Y + attribute \src "libresoc.v:137526.19-137526.114" + wire $and$libresoc.v:137526$5795_Y + attribute \src "libresoc.v:137528.19-137528.112" + wire $and$libresoc.v:137528$5797_Y + attribute \src "libresoc.v:137532.19-137532.113" + wire $and$libresoc.v:137532$5801_Y + attribute \src "libresoc.v:137534.19-137534.132" + wire $and$libresoc.v:137534$5803_Y + attribute \src "libresoc.v:137538.19-137538.114" + wire $and$libresoc.v:137538$5807_Y + attribute \src "libresoc.v:137540.19-137540.112" + wire $and$libresoc.v:137540$5809_Y + attribute \src "libresoc.v:137543.19-137543.113" + wire $and$libresoc.v:137543$5812_Y + attribute \src "libresoc.v:137545.19-137545.132" + wire $and$libresoc.v:137545$5814_Y + attribute \src "libresoc.v:137548.19-137548.114" + wire $and$libresoc.v:137548$5817_Y + attribute \src "libresoc.v:137550.19-137550.112" + wire $and$libresoc.v:137550$5819_Y + attribute \src "libresoc.v:137552.18-137552.108" + wire $and$libresoc.v:137552$5821_Y + attribute \src "libresoc.v:137553.19-137553.113" + wire $and$libresoc.v:137553$5822_Y + attribute \src "libresoc.v:137555.19-137555.129" + wire $and$libresoc.v:137555$5824_Y + attribute \src "libresoc.v:137559.19-137559.114" + wire $and$libresoc.v:137559$5828_Y + attribute \src "libresoc.v:137561.19-137561.112" + wire $and$libresoc.v:137561$5830_Y + attribute \src "libresoc.v:137563.18-137563.111" + wire $and$libresoc.v:137563$5832_Y + attribute \src "libresoc.v:137564.19-137564.113" + wire $and$libresoc.v:137564$5833_Y + attribute \src "libresoc.v:137566.19-137566.129" + wire $and$libresoc.v:137566$5835_Y + attribute \src "libresoc.v:137569.19-137569.114" + wire $and$libresoc.v:137569$5838_Y + attribute \src "libresoc.v:137571.19-137571.112" + wire $and$libresoc.v:137571$5840_Y + attribute \src "libresoc.v:137573.19-137573.113" + wire $and$libresoc.v:137573$5842_Y + attribute \src "libresoc.v:137576.19-137576.121" + wire $and$libresoc.v:137576$5845_Y + attribute \src "libresoc.v:137608.17-137608.106" + wire $and$libresoc.v:137608$5878_Y + attribute \src "libresoc.v:137363.17-137363.110" + wire $eq$libresoc.v:137363$5632_Y + attribute \src "libresoc.v:137374.18-137374.111" + wire $eq$libresoc.v:137374$5643_Y + attribute \src "libresoc.v:137385.18-137385.111" + wire $eq$libresoc.v:137385$5654_Y + attribute \src "libresoc.v:137418.17-137418.110" + wire $eq$libresoc.v:137418$5687_Y + attribute \src "libresoc.v:137419.18-137419.111" + wire $eq$libresoc.v:137419$5688_Y + attribute \src "libresoc.v:137430.18-137430.111" + wire $eq$libresoc.v:137430$5699_Y + attribute \src "libresoc.v:137452.18-137452.111" + wire $eq$libresoc.v:137452$5721_Y + attribute \src "libresoc.v:137496.18-137496.111" + wire $eq$libresoc.v:137496$5765_Y + attribute \src "libresoc.v:137507.18-137507.111" + wire $eq$libresoc.v:137507$5776_Y + attribute \src "libresoc.v:137508.19-137508.112" + wire $eq$libresoc.v:137508$5777_Y + attribute \src "libresoc.v:137509.19-137509.112" + wire $eq$libresoc.v:137509$5778_Y + attribute \src "libresoc.v:137511.19-137511.112" + wire $eq$libresoc.v:137511$5780_Y + attribute \src "libresoc.v:137514.19-137514.112" + wire $eq$libresoc.v:137514$5783_Y + attribute \src "libresoc.v:137524.19-137524.112" + wire $eq$libresoc.v:137524$5793_Y + attribute \src "libresoc.v:137529.17-137529.110" + wire $eq$libresoc.v:137529$5798_Y + attribute \src "libresoc.v:137530.18-137530.111" + wire $eq$libresoc.v:137530$5799_Y + attribute \src "libresoc.v:137535.19-137535.112" + wire $eq$libresoc.v:137535$5804_Y + attribute \src "libresoc.v:137536.19-137536.112" + wire $eq$libresoc.v:137536$5805_Y + attribute \src "libresoc.v:137546.19-137546.112" + wire $eq$libresoc.v:137546$5815_Y + attribute \src "libresoc.v:137556.19-137556.112" + wire $eq$libresoc.v:137556$5825_Y + attribute \src "libresoc.v:137557.19-137557.112" + wire $eq$libresoc.v:137557$5826_Y + attribute \src "libresoc.v:137567.19-137567.112" + wire $eq$libresoc.v:137567$5836_Y + attribute \src "libresoc.v:137574.18-137574.111" + wire $eq$libresoc.v:137574$5843_Y + attribute \src "libresoc.v:137577.19-137577.110" + wire $eq$libresoc.v:137577$5846_Y + attribute \src "libresoc.v:137579.19-137579.110" + wire $eq$libresoc.v:137579$5848_Y + attribute \src "libresoc.v:137580.19-137580.110" + wire $eq$libresoc.v:137580$5849_Y + attribute \src "libresoc.v:137582.19-137582.110" + wire $eq$libresoc.v:137582$5851_Y + attribute \src "libresoc.v:137584.18-137584.111" + wire $eq$libresoc.v:137584$5853_Y + attribute \src "libresoc.v:137587.19-137587.116" + wire $eq$libresoc.v:137587$5857_Y + attribute \src "libresoc.v:137588.19-137588.116" + wire $eq$libresoc.v:137588$5858_Y + attribute \src "libresoc.v:137590.19-137590.116" + wire $eq$libresoc.v:137590$5860_Y + attribute \src "libresoc.v:137586.19-137586.106" + wire width 8 $extend$libresoc.v:137586$5855_Y + attribute \src "libresoc.v:137515.19-137515.109" + wire $ne$libresoc.v:137515$5784_Y + attribute \src "libresoc.v:137517.19-137517.109" + wire $ne$libresoc.v:137517$5786_Y + attribute \src "libresoc.v:137520.19-137520.109" + wire $ne$libresoc.v:137520$5789_Y + attribute \src "libresoc.v:137525.19-137525.120" + wire $ne$libresoc.v:137525$5794_Y + attribute \src "libresoc.v:137527.19-137527.120" + wire $ne$libresoc.v:137527$5796_Y + attribute \src "libresoc.v:137531.19-137531.120" + wire $ne$libresoc.v:137531$5800_Y + attribute \src "libresoc.v:137537.19-137537.120" + wire $ne$libresoc.v:137537$5806_Y + attribute \src "libresoc.v:137539.19-137539.120" + wire $ne$libresoc.v:137539$5808_Y + attribute \src "libresoc.v:137542.19-137542.120" + wire $ne$libresoc.v:137542$5811_Y + attribute \src "libresoc.v:137547.19-137547.117" + wire $ne$libresoc.v:137547$5816_Y + attribute \src "libresoc.v:137549.19-137549.117" + wire $ne$libresoc.v:137549$5818_Y + attribute \src "libresoc.v:137551.19-137551.117" + wire $ne$libresoc.v:137551$5820_Y + attribute \src "libresoc.v:137558.19-137558.117" + wire $ne$libresoc.v:137558$5827_Y + attribute \src "libresoc.v:137560.19-137560.117" + wire $ne$libresoc.v:137560$5829_Y + attribute \src "libresoc.v:137562.19-137562.117" + wire $ne$libresoc.v:137562$5831_Y + attribute \src "libresoc.v:137568.19-137568.109" + wire $ne$libresoc.v:137568$5837_Y + attribute \src "libresoc.v:137570.19-137570.109" + wire $ne$libresoc.v:137570$5839_Y + attribute \src "libresoc.v:137572.19-137572.109" + wire $ne$libresoc.v:137572$5841_Y + attribute \src "libresoc.v:137522.19-137522.110" + wire $not$libresoc.v:137522$5791_Y + attribute \src "libresoc.v:137533.19-137533.121" + wire $not$libresoc.v:137533$5802_Y + attribute \src "libresoc.v:137544.19-137544.121" + wire $not$libresoc.v:137544$5813_Y + attribute \src "libresoc.v:137554.19-137554.118" + wire $not$libresoc.v:137554$5823_Y + attribute \src "libresoc.v:137565.19-137565.118" + wire $not$libresoc.v:137565$5834_Y + attribute \src "libresoc.v:137575.19-137575.110" + wire $not$libresoc.v:137575$5844_Y + attribute \src "libresoc.v:137578.19-137578.100" + wire $not$libresoc.v:137578$5847_Y + attribute \src "libresoc.v:137396.18-137396.104" + wire $or$libresoc.v:137396$5665_Y + attribute \src "libresoc.v:137441.18-137441.104" + wire $or$libresoc.v:137441$5710_Y + attribute \src "libresoc.v:137463.18-137463.104" + wire $or$libresoc.v:137463$5732_Y + attribute \src "libresoc.v:137510.19-137510.107" + wire $or$libresoc.v:137510$5779_Y + attribute \src "libresoc.v:137512.19-137512.107" + wire $or$libresoc.v:137512$5781_Y + attribute \src "libresoc.v:137518.18-137518.104" + wire $or$libresoc.v:137518$5787_Y + attribute \src "libresoc.v:137541.18-137541.104" + wire $or$libresoc.v:137541$5810_Y + attribute \src "libresoc.v:137581.19-137581.107" + wire $or$libresoc.v:137581$5850_Y + attribute \src "libresoc.v:137589.19-137589.107" + wire $or$libresoc.v:137589$5859_Y + attribute \src "libresoc.v:137597.17-137597.101" + wire $or$libresoc.v:137597$5867_Y + attribute \src "libresoc.v:137586.19-137586.106" + wire width 8 $pos$libresoc.v:137586$5856_Y + attribute \src "libresoc.v:137364.18-137364.133" + wire $ternary$libresoc.v:137364$5633_Y + attribute \src "libresoc.v:137365.19-137365.133" + wire $ternary$libresoc.v:137365$5634_Y + attribute \src "libresoc.v:137366.19-137366.134" + wire $ternary$libresoc.v:137366$5635_Y + attribute \src "libresoc.v:137367.19-137367.133" + wire $ternary$libresoc.v:137367$5636_Y + attribute \src "libresoc.v:137368.19-137368.132" + wire $ternary$libresoc.v:137368$5637_Y + attribute \src "libresoc.v:137369.19-137369.133" + wire $ternary$libresoc.v:137369$5638_Y + attribute \src "libresoc.v:137370.19-137370.133" + wire $ternary$libresoc.v:137370$5639_Y + attribute \src "libresoc.v:137371.19-137371.132" + wire $ternary$libresoc.v:137371$5640_Y + attribute \src "libresoc.v:137372.19-137372.133" + wire $ternary$libresoc.v:137372$5641_Y + attribute \src "libresoc.v:137373.19-137373.133" + wire $ternary$libresoc.v:137373$5642_Y + attribute \src "libresoc.v:137375.19-137375.132" + wire $ternary$libresoc.v:137375$5644_Y + attribute \src "libresoc.v:137376.19-137376.133" + wire $ternary$libresoc.v:137376$5645_Y + attribute \src "libresoc.v:137377.19-137377.133" + wire $ternary$libresoc.v:137377$5646_Y + attribute \src "libresoc.v:137378.19-137378.132" + wire $ternary$libresoc.v:137378$5647_Y + attribute \src "libresoc.v:137379.19-137379.133" + wire $ternary$libresoc.v:137379$5648_Y + attribute \src "libresoc.v:137380.19-137380.133" + wire $ternary$libresoc.v:137380$5649_Y + attribute \src "libresoc.v:137381.19-137381.132" + wire $ternary$libresoc.v:137381$5650_Y + attribute \src "libresoc.v:137382.19-137382.133" + wire $ternary$libresoc.v:137382$5651_Y + attribute \src "libresoc.v:137383.19-137383.133" + wire $ternary$libresoc.v:137383$5652_Y + attribute \src "libresoc.v:137384.19-137384.132" + wire $ternary$libresoc.v:137384$5653_Y + attribute \src "libresoc.v:137386.19-137386.133" + wire $ternary$libresoc.v:137386$5655_Y + attribute \src "libresoc.v:137387.19-137387.133" + wire $ternary$libresoc.v:137387$5656_Y + attribute \src "libresoc.v:137388.19-137388.132" + wire $ternary$libresoc.v:137388$5657_Y + attribute \src "libresoc.v:137389.19-137389.133" + wire $ternary$libresoc.v:137389$5658_Y + attribute \src "libresoc.v:137390.19-137390.133" + wire $ternary$libresoc.v:137390$5659_Y + attribute \src "libresoc.v:137391.19-137391.132" + wire $ternary$libresoc.v:137391$5660_Y + attribute \src "libresoc.v:137392.19-137392.133" + wire $ternary$libresoc.v:137392$5661_Y + attribute \src "libresoc.v:137393.19-137393.134" + wire $ternary$libresoc.v:137393$5662_Y + attribute \src "libresoc.v:137394.19-137394.135" + wire $ternary$libresoc.v:137394$5663_Y + attribute \src "libresoc.v:137395.19-137395.135" + wire $ternary$libresoc.v:137395$5664_Y + attribute \src "libresoc.v:137397.19-137397.136" + wire $ternary$libresoc.v:137397$5666_Y + attribute \src "libresoc.v:137398.19-137398.134" + wire $ternary$libresoc.v:137398$5667_Y + attribute \src "libresoc.v:137399.19-137399.135" + wire $ternary$libresoc.v:137399$5668_Y + attribute \src "libresoc.v:137400.19-137400.135" + wire $ternary$libresoc.v:137400$5669_Y + attribute \src "libresoc.v:137401.19-137401.136" + wire $ternary$libresoc.v:137401$5670_Y + attribute \src "libresoc.v:137402.19-137402.134" + wire $ternary$libresoc.v:137402$5671_Y + attribute \src "libresoc.v:137403.19-137403.133" + wire $ternary$libresoc.v:137403$5672_Y + attribute \src "libresoc.v:137404.19-137404.134" + wire $ternary$libresoc.v:137404$5673_Y + attribute \src "libresoc.v:137405.19-137405.133" + wire $ternary$libresoc.v:137405$5674_Y + attribute \src "libresoc.v:137406.19-137406.130" + wire $ternary$libresoc.v:137406$5675_Y + attribute \src "libresoc.v:137408.19-137408.130" + wire $ternary$libresoc.v:137408$5677_Y + attribute \src "libresoc.v:137409.19-137409.133" + wire $ternary$libresoc.v:137409$5678_Y + attribute \src "libresoc.v:137410.19-137410.132" + wire $ternary$libresoc.v:137410$5679_Y + attribute \src "libresoc.v:137411.19-137411.133" + wire $ternary$libresoc.v:137411$5680_Y + attribute \src "libresoc.v:137412.19-137412.132" + wire $ternary$libresoc.v:137412$5681_Y + attribute \src "libresoc.v:137413.19-137413.135" + wire $ternary$libresoc.v:137413$5682_Y + attribute \src "libresoc.v:137414.19-137414.134" + wire $ternary$libresoc.v:137414$5683_Y + attribute \src "libresoc.v:137415.19-137415.135" + wire $ternary$libresoc.v:137415$5684_Y + attribute \src "libresoc.v:137416.19-137416.135" + wire $ternary$libresoc.v:137416$5685_Y + attribute \src "libresoc.v:137417.19-137417.134" + wire $ternary$libresoc.v:137417$5686_Y + attribute \src "libresoc.v:137420.19-137420.135" + wire $ternary$libresoc.v:137420$5689_Y + attribute \src "libresoc.v:137421.19-137421.135" + wire $ternary$libresoc.v:137421$5690_Y + attribute \src "libresoc.v:137422.19-137422.134" + wire $ternary$libresoc.v:137422$5691_Y + attribute \src "libresoc.v:137423.19-137423.135" + wire $ternary$libresoc.v:137423$5692_Y + attribute \src "libresoc.v:137424.19-137424.135" + wire $ternary$libresoc.v:137424$5693_Y + attribute \src "libresoc.v:137425.19-137425.134" + wire $ternary$libresoc.v:137425$5694_Y + attribute \src "libresoc.v:137426.19-137426.135" + wire $ternary$libresoc.v:137426$5695_Y + attribute \src "libresoc.v:137427.19-137427.133" + wire $ternary$libresoc.v:137427$5696_Y + attribute \src "libresoc.v:137428.19-137428.134" + wire $ternary$libresoc.v:137428$5697_Y + attribute \src "libresoc.v:137429.19-137429.133" + wire $ternary$libresoc.v:137429$5698_Y + attribute \src "libresoc.v:137431.19-137431.134" + wire $ternary$libresoc.v:137431$5700_Y + attribute \src "libresoc.v:137432.19-137432.134" + wire $ternary$libresoc.v:137432$5701_Y + attribute \src "libresoc.v:137433.19-137433.133" + wire $ternary$libresoc.v:137433$5702_Y + attribute \src "libresoc.v:137434.19-137434.134" + wire $ternary$libresoc.v:137434$5703_Y + attribute \src "libresoc.v:137435.19-137435.134" + wire $ternary$libresoc.v:137435$5704_Y + attribute \src "libresoc.v:137436.19-137436.133" + wire $ternary$libresoc.v:137436$5705_Y + attribute \src "libresoc.v:137437.19-137437.134" + wire $ternary$libresoc.v:137437$5706_Y + attribute \src "libresoc.v:137438.19-137438.134" + wire $ternary$libresoc.v:137438$5707_Y + attribute \src "libresoc.v:137439.19-137439.133" + wire $ternary$libresoc.v:137439$5708_Y + attribute \src "libresoc.v:137440.19-137440.134" + wire $ternary$libresoc.v:137440$5709_Y + attribute \src "libresoc.v:137442.19-137442.134" + wire $ternary$libresoc.v:137442$5711_Y + attribute \src "libresoc.v:137443.19-137443.133" + wire $ternary$libresoc.v:137443$5712_Y + attribute \src "libresoc.v:137444.19-137444.134" + wire $ternary$libresoc.v:137444$5713_Y + attribute \src "libresoc.v:137445.19-137445.134" + wire $ternary$libresoc.v:137445$5714_Y + attribute \src "libresoc.v:137446.19-137446.133" + wire $ternary$libresoc.v:137446$5715_Y + attribute \src "libresoc.v:137447.19-137447.134" + wire $ternary$libresoc.v:137447$5716_Y + attribute \src "libresoc.v:137448.19-137448.135" + wire $ternary$libresoc.v:137448$5717_Y + attribute \src "libresoc.v:137449.19-137449.134" + wire $ternary$libresoc.v:137449$5718_Y + attribute \src "libresoc.v:137450.19-137450.135" + wire $ternary$libresoc.v:137450$5719_Y + attribute \src "libresoc.v:137451.19-137451.135" + wire $ternary$libresoc.v:137451$5720_Y + attribute \src "libresoc.v:137453.19-137453.134" + wire $ternary$libresoc.v:137453$5722_Y + attribute \src "libresoc.v:137454.19-137454.135" + wire $ternary$libresoc.v:137454$5723_Y + attribute \src "libresoc.v:137455.19-137455.133" + wire $ternary$libresoc.v:137455$5724_Y + attribute \src "libresoc.v:137456.19-137456.133" + wire $ternary$libresoc.v:137456$5725_Y + attribute \src "libresoc.v:137457.19-137457.133" + wire $ternary$libresoc.v:137457$5726_Y + attribute \src "libresoc.v:137458.19-137458.133" + wire $ternary$libresoc.v:137458$5727_Y + attribute \src "libresoc.v:137459.19-137459.133" + wire $ternary$libresoc.v:137459$5728_Y + attribute \src "libresoc.v:137460.19-137460.133" + wire $ternary$libresoc.v:137460$5729_Y + attribute \src "libresoc.v:137461.19-137461.133" + wire $ternary$libresoc.v:137461$5730_Y + attribute \src "libresoc.v:137462.19-137462.133" + wire $ternary$libresoc.v:137462$5731_Y + attribute \src "libresoc.v:137464.19-137464.133" + wire $ternary$libresoc.v:137464$5733_Y + attribute \src "libresoc.v:137465.19-137465.133" + wire $ternary$libresoc.v:137465$5734_Y + attribute \src "libresoc.v:137466.19-137466.134" + wire $ternary$libresoc.v:137466$5735_Y + attribute \src "libresoc.v:137467.19-137467.134" + wire $ternary$libresoc.v:137467$5736_Y + attribute \src "libresoc.v:137468.19-137468.135" + wire $ternary$libresoc.v:137468$5737_Y + attribute \src "libresoc.v:137469.19-137469.133" + wire $ternary$libresoc.v:137469$5738_Y + attribute \src "libresoc.v:137470.19-137470.135" + wire $ternary$libresoc.v:137470$5739_Y + attribute \src "libresoc.v:137471.19-137471.135" + wire $ternary$libresoc.v:137471$5740_Y + attribute \src "libresoc.v:137472.19-137472.134" + wire $ternary$libresoc.v:137472$5741_Y + attribute \src "libresoc.v:137473.19-137473.134" + wire $ternary$libresoc.v:137473$5742_Y + attribute \src "libresoc.v:137475.19-137475.134" + wire $ternary$libresoc.v:137475$5744_Y + attribute \src "libresoc.v:137476.19-137476.134" + wire $ternary$libresoc.v:137476$5745_Y + attribute \src "libresoc.v:137477.19-137477.134" + wire $ternary$libresoc.v:137477$5746_Y + attribute \src "libresoc.v:137478.19-137478.135" + wire $ternary$libresoc.v:137478$5747_Y + attribute \src "libresoc.v:137479.19-137479.134" + wire $ternary$libresoc.v:137479$5748_Y + attribute \src "libresoc.v:137480.19-137480.135" + wire $ternary$libresoc.v:137480$5749_Y + attribute \src "libresoc.v:137481.19-137481.135" + wire $ternary$libresoc.v:137481$5750_Y + attribute \src "libresoc.v:137482.19-137482.134" + wire $ternary$libresoc.v:137482$5751_Y + attribute \src "libresoc.v:137483.19-137483.135" + wire $ternary$libresoc.v:137483$5752_Y + attribute \src "libresoc.v:137484.19-137484.135" + wire $ternary$libresoc.v:137484$5753_Y + attribute \src "libresoc.v:137486.19-137486.134" + wire $ternary$libresoc.v:137486$5755_Y + attribute \src "libresoc.v:137487.19-137487.135" + wire $ternary$libresoc.v:137487$5756_Y + attribute \src "libresoc.v:137488.19-137488.136" + wire $ternary$libresoc.v:137488$5757_Y + attribute \src "libresoc.v:137489.19-137489.135" + wire $ternary$libresoc.v:137489$5758_Y + attribute \src "libresoc.v:137490.19-137490.136" + wire $ternary$libresoc.v:137490$5759_Y + attribute \src "libresoc.v:137491.19-137491.136" + wire $ternary$libresoc.v:137491$5760_Y + attribute \src "libresoc.v:137492.19-137492.135" + wire $ternary$libresoc.v:137492$5761_Y + attribute \src "libresoc.v:137493.19-137493.136" + wire $ternary$libresoc.v:137493$5762_Y + attribute \src "libresoc.v:137494.19-137494.136" + wire $ternary$libresoc.v:137494$5763_Y + attribute \src "libresoc.v:137495.19-137495.135" + wire $ternary$libresoc.v:137495$5764_Y + attribute \src "libresoc.v:137497.19-137497.136" + wire $ternary$libresoc.v:137497$5766_Y + attribute \src "libresoc.v:137498.19-137498.136" + wire $ternary$libresoc.v:137498$5767_Y + attribute \src "libresoc.v:137499.19-137499.135" + wire $ternary$libresoc.v:137499$5768_Y + attribute \src "libresoc.v:137500.19-137500.136" + wire $ternary$libresoc.v:137500$5769_Y + attribute \src "libresoc.v:137501.19-137501.136" + wire $ternary$libresoc.v:137501$5770_Y + attribute \src "libresoc.v:137502.19-137502.135" + wire $ternary$libresoc.v:137502$5771_Y + attribute \src "libresoc.v:137503.19-137503.136" + wire $ternary$libresoc.v:137503$5772_Y + attribute \src "libresoc.v:137504.19-137504.136" + wire $ternary$libresoc.v:137504$5773_Y + attribute \src "libresoc.v:137505.19-137505.135" + wire $ternary$libresoc.v:137505$5774_Y + attribute \src "libresoc.v:137506.19-137506.136" + wire $ternary$libresoc.v:137506$5775_Y + attribute \src "libresoc.v:137593.18-137593.130" + wire $ternary$libresoc.v:137593$5863_Y + attribute \src "libresoc.v:137594.18-137594.130" + wire $ternary$libresoc.v:137594$5864_Y + attribute \src "libresoc.v:137595.18-137595.130" + wire $ternary$libresoc.v:137595$5865_Y + attribute \src "libresoc.v:137596.18-137596.131" + wire $ternary$libresoc.v:137596$5866_Y + attribute \src "libresoc.v:137598.18-137598.130" + wire $ternary$libresoc.v:137598$5868_Y + attribute \src "libresoc.v:137599.18-137599.131" + wire $ternary$libresoc.v:137599$5869_Y + attribute \src "libresoc.v:137600.18-137600.131" + wire $ternary$libresoc.v:137600$5870_Y + attribute \src "libresoc.v:137601.18-137601.130" + wire $ternary$libresoc.v:137601$5871_Y + attribute \src "libresoc.v:137602.18-137602.131" + wire $ternary$libresoc.v:137602$5872_Y + attribute \src "libresoc.v:137603.18-137603.132" + wire $ternary$libresoc.v:137603$5873_Y + attribute \src "libresoc.v:137604.18-137604.132" + wire $ternary$libresoc.v:137604$5874_Y + attribute \src "libresoc.v:137605.18-137605.133" + wire $ternary$libresoc.v:137605$5875_Y + attribute \src "libresoc.v:137606.18-137606.133" + wire $ternary$libresoc.v:137606$5876_Y + attribute \src "libresoc.v:137607.18-137607.132" + wire $ternary$libresoc.v:137607$5877_Y + attribute \src "libresoc.v:137609.18-137609.133" + wire $ternary$libresoc.v:137609$5879_Y + attribute \src "libresoc.v:137610.18-137610.133" + wire $ternary$libresoc.v:137610$5880_Y + attribute \src "libresoc.v:137611.18-137611.132" + wire $ternary$libresoc.v:137611$5881_Y + attribute \src "libresoc.v:137612.18-137612.133" + wire $ternary$libresoc.v:137612$5882_Y + attribute \src "libresoc.v:137613.18-137613.133" + wire $ternary$libresoc.v:137613$5883_Y + attribute \src "libresoc.v:137614.18-137614.132" + wire $ternary$libresoc.v:137614$5884_Y + attribute \src "libresoc.v:137615.18-137615.133" + wire $ternary$libresoc.v:137615$5885_Y + attribute \src "libresoc.v:137616.18-137616.133" + wire $ternary$libresoc.v:137616$5886_Y + attribute \src "libresoc.v:137617.18-137617.132" + wire $ternary$libresoc.v:137617$5887_Y + attribute \src "libresoc.v:137618.18-137618.133" + wire $ternary$libresoc.v:137618$5888_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" @@ -213919,13 +216414,13 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 328 \TAP_bus__tck + wire input 329 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 164 \TAP_bus__tdi + wire input 165 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 319 \TAP_bus__tdo + wire output 320 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 329 \TAP_bus__tms + wire input 330 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" @@ -213948,24 +216443,24 @@ module \jtag wire width 4 \_irblock_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 330 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 331 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire input 5 \dmi0__ack_o + wire input 6 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 output 1 \dmi0__addr_i + wire width 4 output 2 \dmi0__addr_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 4 \dmi0__addr_i$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 output 4 \dmi0__din + wire width 64 output 5 \dmi0__din attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 64 \dmi0__din$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 input 6 \dmi0__dout + wire width 64 input 7 \dmi0__dout attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 2 \dmi0__req_i + wire output 3 \dmi0__req_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 3 \dmi0__we_i + wire output 4 \dmi0__we_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire width 8 \dmi0_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" @@ -214025,17 +216520,17 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \eint_0__core__i + wire output 166 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 10 \eint_0__pad__i + wire input 11 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_1__core__i + wire output 167 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 11 \eint_1__pad__i + wire input 12 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \eint_2__core__i + wire output 168 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 12 \eint_2__pad__i + wire input 13 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" @@ -214045,198 +216540,198 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e10__core__i + wire output 175 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \gpio_e10__core__o + wire input 21 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 21 \gpio_e10__core__oe + wire input 22 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 19 \gpio_e10__pad__i + wire input 20 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__pad__o + wire output 176 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e10__pad__oe + wire output 177 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e11__core__i + wire output 178 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 23 \gpio_e11__core__o + wire input 24 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \gpio_e11__core__oe + wire input 25 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \gpio_e11__pad__i + wire input 23 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__pad__o + wire output 179 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e11__pad__oe + wire output 180 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e12__core__i + wire output 181 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e12__core__o + wire input 27 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e12__core__oe + wire input 28 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \gpio_e12__pad__i + wire input 26 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__pad__o + wire output 182 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e12__pad__oe + wire output 183 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e13__core__i + wire output 184 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e13__core__o + wire input 30 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e13__core__oe + wire input 31 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e13__pad__i + wire input 29 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__pad__o + wire output 185 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e13__pad__oe + wire output 186 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e14__core__i + wire output 187 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e14__core__o + wire input 33 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e14__core__oe + wire input 34 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e14__pad__i + wire input 32 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__pad__o + wire output 188 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e14__pad__oe + wire output 189 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e15__core__i + wire output 190 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e15__core__o + wire input 36 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e15__core__oe + wire input 37 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e15__pad__i + wire input 35 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__pad__o + wire output 191 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e15__pad__oe + wire output 192 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e8__core__i + wire output 169 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 14 \gpio_e8__core__o + wire input 15 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 15 \gpio_e8__core__oe + wire input 16 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 13 \gpio_e8__pad__i + wire input 14 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__pad__o + wire output 170 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e8__pad__oe + wire output 171 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e9__core__i + wire output 172 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 17 \gpio_e9__core__o + wire input 18 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 18 \gpio_e9__core__oe + wire input 19 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 16 \gpio_e9__pad__i + wire input 17 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__pad__o + wire output 173 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e9__pad__oe + wire output 174 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s0__core__i + wire output 193 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_s0__core__o + wire input 39 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_s0__core__oe + wire input 40 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_s0__pad__i + wire input 38 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__pad__o + wire output 194 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s0__pad__oe + wire output 195 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s1__core__i + wire output 196 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_s1__core__o + wire input 42 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_s1__core__oe + wire input 43 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_s1__pad__i + wire input 41 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__pad__o + wire output 197 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s1__pad__oe + wire output 198 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s2__core__i + wire output 199 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_s2__core__o + wire input 45 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_s2__core__oe + wire input 46 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_s2__pad__i + wire input 44 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__pad__o + wire output 200 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s2__pad__oe + wire output 201 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s3__core__i + wire output 202 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_s3__core__o + wire input 48 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_s3__core__oe + wire input 49 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_s3__pad__i + wire input 47 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__pad__o + wire output 203 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s3__pad__oe + wire output 204 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s4__core__i + wire output 205 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_s4__core__o + wire input 51 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s4__core__oe + wire input 52 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_s4__pad__i + wire input 50 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__pad__o + wire output 206 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s4__pad__oe + wire output 207 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s5__core__i + wire output 208 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s5__core__o + wire input 54 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s5__core__oe + wire input 55 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s5__pad__i + wire input 53 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__pad__o + wire output 209 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s5__pad__oe + wire output 210 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s6__core__i + wire output 211 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s6__core__o + wire input 57 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s6__core__oe + wire input 58 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s6__pad__i + wire input 56 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__pad__o + wire output 212 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s6__pad__oe + wire output 213 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s7__core__i + wire output 214 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s7__core__o + wire input 60 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s7__core__oe + wire input 61 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s7__pad__i + wire input 59 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__pad__o + wire output 215 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s7__pad__oe - attribute \src "libresoc.v:134147.7-134147.15" + wire output 216 \gpio_s7__pad__oe + attribute \src "libresoc.v:135928.7-135928.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" wire width 154 \io_bd @@ -214257,25 +216752,25 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 326 \jtag_wb__ack + wire input 327 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 320 \jtag_wb__adr + wire width 29 output 321 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 322 \jtag_wb__cyc + wire output 323 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 327 \jtag_wb__dat_r + wire width 64 input 328 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 325 \jtag_wb__dat_w + wire width 64 output 326 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 321 \jtag_wb__sel + wire output 322 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 323 \jtag_wb__stb + wire output 324 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 324 \jtag_wb__we + wire output 325 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" @@ -214335,53 +216830,53 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \mspi0_clk__core__o + wire input 62 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \mspi0_clk__pad__o + wire output 217 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \mspi0_cs_n__core__o + wire input 63 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_cs_n__pad__o + wire output 218 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi0_miso__core__i + wire output 220 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \mspi0_miso__pad__i + wire input 65 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \mspi0_mosi__core__o + wire input 64 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_mosi__pad__o + wire output 219 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \mspi1_clk__core__o + wire input 66 \mspi1_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi1_clk__pad__o + wire output 221 \mspi1_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi1_cs_n__core__o + wire input 67 \mspi1_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_cs_n__pad__o + wire output 222 \mspi1_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mspi1_miso__core__i + wire output 224 \mspi1_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mspi1_miso__pad__i + wire input 69 \mspi1_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi1_mosi__core__o + wire input 68 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_mosi__pad__o + wire output 223 \mspi1_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \mtwi_scl__core__o + wire input 73 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \mtwi_scl__pad__o + wire output 228 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mtwi_sda__core__i + wire output 225 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mtwi_sda__core__o + wire input 71 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mtwi_sda__core__oe + wire input 72 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mtwi_sda__pad__i + wire input 70 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__pad__o + wire output 226 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_sda__pad__oe + wire output 227 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" @@ -214391,371 +216886,371 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \pwm_0__core__o + wire input 74 \pwm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \pwm_0__pad__o + wire output 229 \pwm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \pwm_1__core__o + wire input 75 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 7 \rst + wire output 230 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sd0_clk__core__o + wire input 79 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_clk__pad__o + wire output 234 \sd0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sd0_cmd__core__i + wire output 231 \sd0_cmd__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sd0_cmd__core__o + wire input 77 \sd0_cmd__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sd0_cmd__core__oe + wire input 78 \sd0_cmd__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \sd0_cmd__pad__i + wire input 76 \sd0_cmd__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__pad__o + wire output 232 \sd0_cmd__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_cmd__pad__oe + wire output 233 \sd0_cmd__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_data0__core__i + wire output 235 \sd0_data0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_data0__core__o + wire input 81 \sd0_data0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_data0__core__oe + wire input 82 \sd0_data0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sd0_data0__pad__i + wire input 80 \sd0_data0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__pad__o + wire output 236 \sd0_data0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data0__pad__oe + wire output 237 \sd0_data0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data1__core__i + wire output 238 \sd0_data1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_data1__core__o + wire input 84 \sd0_data1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data1__core__oe + wire input 85 \sd0_data1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_data1__pad__i + wire input 83 \sd0_data1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__pad__o + wire output 239 \sd0_data1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data1__pad__oe + wire output 240 \sd0_data1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data2__core__i + wire output 241 \sd0_data2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data2__core__o + wire input 87 \sd0_data2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data2__core__oe + wire input 88 \sd0_data2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data2__pad__i + wire input 86 \sd0_data2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__pad__o + wire output 242 \sd0_data2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data2__pad__oe + wire output 243 \sd0_data2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data3__core__i + wire output 244 \sd0_data3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data3__core__o + wire input 90 \sd0_data3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_data3__core__oe + wire input 91 \sd0_data3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data3__pad__i + wire input 89 \sd0_data3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__pad__o + wire output 245 \sd0_data3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_data3__pad__oe + wire output 246 \sd0_data3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_a_0__core__o + wire input 117 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_a_0__pad__o + wire output 272 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_10__core__o + wire input 135 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_10__pad__o + wire output 290 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_11__core__o + wire input 136 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_11__pad__o + wire output 291 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_12__core__o + wire input 137 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_12__pad__o + wire output 292 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_1__core__o + wire input 118 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_1__pad__o + wire output 273 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_a_2__core__o + wire input 119 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_2__pad__o + wire output 274 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_a_3__core__o + wire input 120 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_3__pad__o + wire output 275 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_a_4__core__o + wire input 121 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_4__pad__o + wire output 276 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_5__core__o + wire input 122 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_5__pad__o + wire output 277 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_6__core__o + wire input 123 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_6__pad__o + wire output 278 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_7__core__o + wire input 124 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_7__pad__o + wire output 279 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_8__core__o + wire input 125 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_8__pad__o + wire output 280 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_a_9__core__o + wire input 126 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_a_9__pad__o + wire output 281 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_ba_0__core__o + wire input 127 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_ba_0__pad__o + wire output 282 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_ba_1__core__o + wire input 128 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_ba_1__pad__o + wire output 283 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_cas_n__core__o + wire input 132 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_cas_n__pad__o + wire output 287 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_cke__core__o + wire input 130 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_cke__pad__o + wire output 285 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_clock__core__o + wire input 129 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_clock__pad__o + wire output 284 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_cs_n__core__o + wire input 134 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_cs_n__pad__o + wire output 289 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sdr_dm_0__core__o + wire input 92 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dm_0__pad__o + wire output 247 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dm_1__core__i + wire output 293 \sdr_dm_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__core__o + wire input 139 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dm_1__core__oe + wire input 140 \sdr_dm_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dm_1__pad__i + wire input 138 \sdr_dm_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dm_1__pad__o + wire output 294 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dm_1__pad__oe + wire output 295 \sdr_dm_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_0__core__i + wire output 248 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_0__core__o + wire input 94 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_0__core__oe + wire input 95 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dq_0__pad__i + wire input 93 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__pad__o + wire output 249 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_0__pad__oe + wire output 250 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_10__core__i + wire output 302 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__core__o + wire input 148 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_10__core__oe + wire input 149 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_10__pad__i + wire input 147 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_10__pad__o + wire output 303 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_10__pad__oe + wire output 304 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_11__core__i + wire output 305 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__core__o + wire input 151 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_11__core__oe + wire input 152 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_11__pad__i + wire input 150 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_11__pad__o + wire output 306 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_11__pad__oe + wire output 307 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__core__i + wire output 308 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__core__o + wire input 154 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_12__core__oe + wire input 155 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_12__pad__i + wire input 153 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__o + wire output 309 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_12__pad__oe + wire output 310 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_13__core__i + wire output 311 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__core__o + wire input 157 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_13__core__oe + wire input 158 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_13__pad__i + wire input 156 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_13__pad__o + wire output 312 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_13__pad__oe + wire output 313 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_14__core__i + wire output 314 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__core__o + wire input 160 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_14__core__oe + wire input 161 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_14__pad__i + wire input 159 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_14__pad__o + wire output 315 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__pad__oe + wire output 316 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_15__core__i + wire output 317 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__core__o + wire input 163 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_15__core__oe + wire input 164 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_15__pad__i + wire input 162 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__pad__o + wire output 318 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_15__pad__oe + wire output 319 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_1__core__i + wire output 251 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_1__core__o + wire input 97 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_1__core__oe + wire input 98 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_1__pad__i + wire input 96 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__pad__o + wire output 252 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_1__pad__oe + wire output 253 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_2__core__i + wire output 254 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_2__core__o + wire input 100 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_2__core__oe + wire input 101 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_2__pad__i + wire input 99 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__pad__o + wire output 255 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_2__pad__oe + wire output 256 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_3__core__i + wire output 257 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_3__core__o + wire input 103 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_3__core__oe + wire input 104 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_3__pad__i + wire input 102 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__pad__o + wire output 258 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_3__pad__oe + wire output 259 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_4__core__i + wire output 260 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_4__core__o + wire input 106 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_4__core__oe + wire input 107 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_4__pad__i + wire input 105 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__pad__o + wire output 261 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_4__pad__oe + wire output 262 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_5__core__i + wire output 263 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_5__core__o + wire input 109 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_5__core__oe + wire input 110 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_5__pad__i + wire input 108 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__pad__o + wire output 264 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_5__pad__oe + wire output 265 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_6__core__i + wire output 266 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_6__core__o + wire input 112 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_6__core__oe + wire input 113 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_6__pad__i + wire input 111 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__pad__o + wire output 267 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_6__pad__oe + wire output 268 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_7__core__i + wire output 269 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_7__core__o + wire input 115 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_7__core__oe + wire input 116 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_7__pad__i + wire input 114 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__pad__o + wire output 270 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_7__pad__oe + wire output 271 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_8__core__i + wire output 296 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__core__o + wire input 142 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_8__core__oe + wire input 143 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_8__pad__i + wire input 141 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_8__pad__o + wire output 297 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_8__pad__oe + wire output 298 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_9__core__i + wire output 299 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__core__o + wire input 145 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_9__core__oe + wire input 146 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_9__pad__i + wire input 144 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_9__pad__o + wire output 300 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_9__pad__oe + wire output 301 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_ras_n__core__o + wire input 131 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_ras_n__pad__o + wire output 286 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_we_n__core__o + wire input 133 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_we_n__pad__o + wire output 288 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" @@ -214815,19 +217310,19 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr5_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" - wire output 8 \wb_dcache_en + wire output 9 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \wb_dcache_en$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire output 9 \wb_icache_en + wire output 10 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \wb_icache_en$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" - wire \wb_sram_en + wire output 8 \wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:135801$5807 + cell $add $add$libresoc.v:137583$5852 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -214835,10 +217330,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:135801$5807_Y + connect \Y $add$libresoc.v:137583$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:135803$5809 + cell $add $add$libresoc.v:137585$5854 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -214846,10 +217341,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:135803$5809_Y + connect \Y $add$libresoc.v:137585$5854_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:135809$5816 + cell $add $add$libresoc.v:137591$5861 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -214857,10 +217352,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:135809$5816_Y + connect \Y $add$libresoc.v:137591$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:135810$5817 + cell $add $add$libresoc.v:137592$5862 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -214868,10 +217363,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:135810$5817_Y + connect \Y $add$libresoc.v:137592$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:135625$5631 + cell $and $and$libresoc.v:137407$5676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214879,10 +217374,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture - connect \Y $and$libresoc.v:135625$5631_Y + connect \Y $and$libresoc.v:137407$5676_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:135692$5698 + cell $and $and$libresoc.v:137474$5743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214890,10 +217385,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 - connect \Y $and$libresoc.v:135692$5698_Y + connect \Y $and$libresoc.v:137474$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:135703$5709 + cell $and $and$libresoc.v:137485$5754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214901,10 +217396,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift - connect \Y $and$libresoc.v:135703$5709_Y + connect \Y $and$libresoc.v:137485$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:135731$5737 + cell $and $and$libresoc.v:137513$5782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214912,10 +217407,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$367 - connect \Y $and$libresoc.v:135731$5737_Y + connect \Y $and$libresoc.v:137513$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:135734$5740 + cell $and $and$libresoc.v:137516$5785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214923,10 +217418,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$373 connect \B \_fsm_capture - connect \Y $and$libresoc.v:135734$5740_Y + connect \Y $and$libresoc.v:137516$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:135737$5743 + cell $and $and$libresoc.v:137519$5788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214934,10 +217429,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$377 connect \B \_fsm_shift - connect \Y $and$libresoc.v:135737$5743_Y + connect \Y $and$libresoc.v:137519$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:135739$5745 + cell $and $and$libresoc.v:137521$5790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214945,10 +217440,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$381 connect \B \_fsm_update - connect \Y $and$libresoc.v:135739$5745_Y + connect \Y $and$libresoc.v:137521$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:135741$5747 + cell $and $and$libresoc.v:137523$5792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214956,10 +217451,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev connect \B \$385 - connect \Y $and$libresoc.v:135741$5747_Y + connect \Y $and$libresoc.v:137523$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:135744$5750 + cell $and $and$libresoc.v:137526$5795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214967,10 +217462,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$391 connect \B \_fsm_capture - connect \Y $and$libresoc.v:135744$5750_Y + connect \Y $and$libresoc.v:137526$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:135746$5752 + cell $and $and$libresoc.v:137528$5797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214978,10 +217473,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$395 connect \B \_fsm_shift - connect \Y $and$libresoc.v:135746$5752_Y + connect \Y $and$libresoc.v:137528$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:135750$5756 + cell $and $and$libresoc.v:137532$5801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214989,10 +217484,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$399 connect \B \_fsm_update - connect \Y $and$libresoc.v:135750$5756_Y + connect \Y $and$libresoc.v:137532$5801_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:135752$5758 + cell $and $and$libresoc.v:137534$5803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215000,10 +217495,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev connect \B \$403 - connect \Y $and$libresoc.v:135752$5758_Y + connect \Y $and$libresoc.v:137534$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:135756$5762 + cell $and $and$libresoc.v:137538$5807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215011,10 +217506,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$411 connect \B \_fsm_capture - connect \Y $and$libresoc.v:135756$5762_Y + connect \Y $and$libresoc.v:137538$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:135758$5764 + cell $and $and$libresoc.v:137540$5809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215022,10 +217517,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$415 connect \B \_fsm_shift - connect \Y $and$libresoc.v:135758$5764_Y + connect \Y $and$libresoc.v:137540$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:135761$5767 + cell $and $and$libresoc.v:137543$5812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215033,10 +217528,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$419 connect \B \_fsm_update - connect \Y $and$libresoc.v:135761$5767_Y + connect \Y $and$libresoc.v:137543$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:135763$5769 + cell $and $and$libresoc.v:137545$5814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215044,10 +217539,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev connect \B \$423 - connect \Y $and$libresoc.v:135763$5769_Y + connect \Y $and$libresoc.v:137545$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:135766$5772 + cell $and $and$libresoc.v:137548$5817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215055,10 +217550,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$429 connect \B \_fsm_capture - connect \Y $and$libresoc.v:135766$5772_Y + connect \Y $and$libresoc.v:137548$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:135768$5774 + cell $and $and$libresoc.v:137550$5819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215066,10 +217561,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$433 connect \B \_fsm_shift - connect \Y $and$libresoc.v:135768$5774_Y + connect \Y $and$libresoc.v:137550$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:135770$5776 + cell $and $and$libresoc.v:137552$5821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215077,10 +217572,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$41 - connect \Y $and$libresoc.v:135770$5776_Y + connect \Y $and$libresoc.v:137552$5821_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:135771$5777 + cell $and $and$libresoc.v:137553$5822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215088,10 +217583,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$437 connect \B \_fsm_update - connect \Y $and$libresoc.v:135771$5777_Y + connect \Y $and$libresoc.v:137553$5822_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:135773$5779 + cell $and $and$libresoc.v:137555$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215099,10 +217594,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev connect \B \$441 - connect \Y $and$libresoc.v:135773$5779_Y + connect \Y $and$libresoc.v:137555$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:135777$5783 + cell $and $and$libresoc.v:137559$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215110,10 +217605,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$449 connect \B \_fsm_capture - connect \Y $and$libresoc.v:135777$5783_Y + connect \Y $and$libresoc.v:137559$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:135779$5785 + cell $and $and$libresoc.v:137561$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215121,10 +217616,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$453 connect \B \_fsm_shift - connect \Y $and$libresoc.v:135779$5785_Y + connect \Y $and$libresoc.v:137561$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:135781$5787 + cell $and $and$libresoc.v:137563$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215132,10 +217627,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$43 connect \B \_fsm_update - connect \Y $and$libresoc.v:135781$5787_Y + connect \Y $and$libresoc.v:137563$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:135782$5788 + cell $and $and$libresoc.v:137564$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215143,10 +217638,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$457 connect \B \_fsm_update - connect \Y $and$libresoc.v:135782$5788_Y + connect \Y $and$libresoc.v:137564$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:135784$5790 + cell $and $and$libresoc.v:137566$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215154,10 +217649,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev connect \B \$461 - connect \Y $and$libresoc.v:135784$5790_Y + connect \Y $and$libresoc.v:137566$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:135787$5793 + cell $and $and$libresoc.v:137569$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215165,10 +217660,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$467 connect \B \_fsm_capture - connect \Y $and$libresoc.v:135787$5793_Y + connect \Y $and$libresoc.v:137569$5838_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:135789$5795 + cell $and $and$libresoc.v:137571$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215176,10 +217671,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$471 connect \B \_fsm_shift - connect \Y $and$libresoc.v:135789$5795_Y + connect \Y $and$libresoc.v:137571$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:135791$5797 + cell $and $and$libresoc.v:137573$5842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215187,10 +217682,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$475 connect \B \_fsm_update - connect \Y $and$libresoc.v:135791$5797_Y + connect \Y $and$libresoc.v:137573$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:135794$5800 + cell $and $and$libresoc.v:137576$5845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215198,10 +217693,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev connect \B \$479 - connect \Y $and$libresoc.v:135794$5800_Y + connect \Y $and$libresoc.v:137576$5845_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:135826$5833 + cell $and $and$libresoc.v:137608$5878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215209,10 +217704,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 - connect \Y $and$libresoc.v:135826$5833_Y + connect \Y $and$libresoc.v:137608$5878_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:135581$5587 + cell $eq $eq$libresoc.v:137363$5632 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215220,10 +217715,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:135581$5587_Y + connect \Y $eq$libresoc.v:137363$5632_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:135592$5598 + cell $eq $eq$libresoc.v:137374$5643 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215231,10 +217726,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:135592$5598_Y + connect \Y $eq$libresoc.v:137374$5643_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:135603$5609 + cell $eq $eq$libresoc.v:137385$5654 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215242,10 +217737,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:135603$5609_Y + connect \Y $eq$libresoc.v:137385$5654_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:135636$5642 + cell $eq $eq$libresoc.v:137418$5687 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215253,10 +217748,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:135636$5642_Y + connect \Y $eq$libresoc.v:137418$5687_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:135637$5643 + cell $eq $eq$libresoc.v:137419$5688 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215264,10 +217759,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:135637$5643_Y + connect \Y $eq$libresoc.v:137419$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:135648$5654 + cell $eq $eq$libresoc.v:137430$5699 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215275,10 +217770,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:135648$5654_Y + connect \Y $eq$libresoc.v:137430$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:135670$5676 + cell $eq $eq$libresoc.v:137452$5721 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215286,10 +217781,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:135670$5676_Y + connect \Y $eq$libresoc.v:137452$5721_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:135714$5720 + cell $eq $eq$libresoc.v:137496$5765 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215297,10 +217792,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:135714$5720_Y + connect \Y $eq$libresoc.v:137496$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:135725$5731 + cell $eq $eq$libresoc.v:137507$5776 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215308,10 +217803,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:135725$5731_Y + connect \Y $eq$libresoc.v:137507$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:135726$5732 + cell $eq $eq$libresoc.v:137508$5777 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215319,10 +217814,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:135726$5732_Y + connect \Y $eq$libresoc.v:137508$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:135727$5733 + cell $eq $eq$libresoc.v:137509$5778 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215330,10 +217825,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:135727$5733_Y + connect \Y $eq$libresoc.v:137509$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:135729$5735 + cell $eq $eq$libresoc.v:137511$5780 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215341,10 +217836,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:135729$5735_Y + connect \Y $eq$libresoc.v:137511$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:135732$5738 + cell $eq $eq$libresoc.v:137514$5783 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215352,10 +217847,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:135732$5738_Y + connect \Y $eq$libresoc.v:137514$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:135742$5748 + cell $eq $eq$libresoc.v:137524$5793 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215363,10 +217858,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'101 - connect \Y $eq$libresoc.v:135742$5748_Y + connect \Y $eq$libresoc.v:137524$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:135747$5753 + cell $eq $eq$libresoc.v:137529$5798 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215374,10 +217869,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:135747$5753_Y + connect \Y $eq$libresoc.v:137529$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:135748$5754 + cell $eq $eq$libresoc.v:137530$5799 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215385,10 +217880,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:135748$5754_Y + connect \Y $eq$libresoc.v:137530$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:135753$5759 + cell $eq $eq$libresoc.v:137535$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215396,10 +217891,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 - connect \Y $eq$libresoc.v:135753$5759_Y + connect \Y $eq$libresoc.v:137535$5804_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:135754$5760 + cell $eq $eq$libresoc.v:137536$5805 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215407,10 +217902,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:135754$5760_Y + connect \Y $eq$libresoc.v:137536$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:135764$5770 + cell $eq $eq$libresoc.v:137546$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215418,10 +217913,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:135764$5770_Y + connect \Y $eq$libresoc.v:137546$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:135774$5780 + cell $eq $eq$libresoc.v:137556$5825 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215429,10 +217924,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:135774$5780_Y + connect \Y $eq$libresoc.v:137556$5825_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:135775$5781 + cell $eq $eq$libresoc.v:137557$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215440,10 +217935,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1010 - connect \Y $eq$libresoc.v:135775$5781_Y + connect \Y $eq$libresoc.v:137557$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:135785$5791 + cell $eq $eq$libresoc.v:137567$5836 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215451,10 +217946,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1011 - connect \Y $eq$libresoc.v:135785$5791_Y + connect \Y $eq$libresoc.v:137567$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:135792$5798 + cell $eq $eq$libresoc.v:137574$5843 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215462,10 +217957,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:135792$5798_Y + connect \Y $eq$libresoc.v:137574$5843_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:135795$5801 + cell $eq $eq$libresoc.v:137577$5846 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215473,10 +217968,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:135795$5801_Y + connect \Y $eq$libresoc.v:137577$5846_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:135797$5803 + cell $eq $eq$libresoc.v:137579$5848 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215484,10 +217979,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:135797$5803_Y + connect \Y $eq$libresoc.v:137579$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:135798$5804 + cell $eq $eq$libresoc.v:137580$5849 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215495,10 +217990,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:135798$5804_Y + connect \Y $eq$libresoc.v:137580$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:135800$5806 + cell $eq $eq$libresoc.v:137582$5851 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215506,10 +218001,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:135800$5806_Y + connect \Y $eq$libresoc.v:137582$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:135802$5808 + cell $eq $eq$libresoc.v:137584$5853 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -215517,10 +218012,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:135802$5808_Y + connect \Y $eq$libresoc.v:137584$5853_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:135805$5812 + cell $eq $eq$libresoc.v:137587$5857 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215528,10 +218023,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$503 connect \B 1'1 - connect \Y $eq$libresoc.v:135805$5812_Y + connect \Y $eq$libresoc.v:137587$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:135806$5813 + cell $eq $eq$libresoc.v:137588$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215539,10 +218034,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$503 connect \B 2'10 - connect \Y $eq$libresoc.v:135806$5813_Y + connect \Y $eq$libresoc.v:137588$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:135808$5815 + cell $eq $eq$libresoc.v:137590$5860 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -215550,18 +218045,18 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$503 connect \B 2'10 - connect \Y $eq$libresoc.v:135808$5815_Y + connect \Y $eq$libresoc.v:137590$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:135804$5810 + cell $pos $extend$libresoc.v:137586$5855 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:135804$5810_Y + connect \Y $extend$libresoc.v:137586$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:135733$5739 + cell $ne $ne$libresoc.v:137515$5784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215569,10 +218064,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135733$5739_Y + connect \Y $ne$libresoc.v:137515$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:135735$5741 + cell $ne $ne$libresoc.v:137517$5786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215580,10 +218075,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135735$5741_Y + connect \Y $ne$libresoc.v:137517$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:135738$5744 + cell $ne $ne$libresoc.v:137520$5789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215591,10 +218086,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135738$5744_Y + connect \Y $ne$libresoc.v:137520$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:135743$5749 + cell $ne $ne$libresoc.v:137525$5794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215602,10 +218097,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135743$5749_Y + connect \Y $ne$libresoc.v:137525$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:135745$5751 + cell $ne $ne$libresoc.v:137527$5796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215613,10 +218108,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135745$5751_Y + connect \Y $ne$libresoc.v:137527$5796_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:135749$5755 + cell $ne $ne$libresoc.v:137531$5800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215624,10 +218119,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135749$5755_Y + connect \Y $ne$libresoc.v:137531$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:135755$5761 + cell $ne $ne$libresoc.v:137537$5806 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215635,10 +218130,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135755$5761_Y + connect \Y $ne$libresoc.v:137537$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:135757$5763 + cell $ne $ne$libresoc.v:137539$5808 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215646,10 +218141,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135757$5763_Y + connect \Y $ne$libresoc.v:137539$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:135760$5766 + cell $ne $ne$libresoc.v:137542$5811 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215657,10 +218152,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135760$5766_Y + connect \Y $ne$libresoc.v:137542$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:135765$5771 + cell $ne $ne$libresoc.v:137547$5816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215668,10 +218163,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135765$5771_Y + connect \Y $ne$libresoc.v:137547$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:135767$5773 + cell $ne $ne$libresoc.v:137549$5818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215679,10 +218174,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135767$5773_Y + connect \Y $ne$libresoc.v:137549$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:135769$5775 + cell $ne $ne$libresoc.v:137551$5820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215690,10 +218185,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135769$5775_Y + connect \Y $ne$libresoc.v:137551$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:135776$5782 + cell $ne $ne$libresoc.v:137558$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215701,10 +218196,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135776$5782_Y + connect \Y $ne$libresoc.v:137558$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:135778$5784 + cell $ne $ne$libresoc.v:137560$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215712,10 +218207,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135778$5784_Y + connect \Y $ne$libresoc.v:137560$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:135780$5786 + cell $ne $ne$libresoc.v:137562$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -215723,10 +218218,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135780$5786_Y + connect \Y $ne$libresoc.v:137562$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:135786$5792 + cell $ne $ne$libresoc.v:137568$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215734,10 +218229,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135786$5792_Y + connect \Y $ne$libresoc.v:137568$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:135788$5794 + cell $ne $ne$libresoc.v:137570$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215745,10 +218240,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135788$5794_Y + connect \Y $ne$libresoc.v:137570$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:135790$5796 + cell $ne $ne$libresoc.v:137572$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215756,66 +218251,66 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:135790$5796_Y + connect \Y $ne$libresoc.v:137572$5841_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:135740$5746 + cell $not $not$libresoc.v:137522$5791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:135740$5746_Y + connect \Y $not$libresoc.v:137522$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:135751$5757 + cell $not $not$libresoc.v:137533$5802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:135751$5757_Y + connect \Y $not$libresoc.v:137533$5802_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:135762$5768 + cell $not $not$libresoc.v:137544$5813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:135762$5768_Y + connect \Y $not$libresoc.v:137544$5813_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:135772$5778 + cell $not $not$libresoc.v:137554$5823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:135772$5778_Y + connect \Y $not$libresoc.v:137554$5823_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:135783$5789 + cell $not $not$libresoc.v:137565$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:135783$5789_Y + connect \Y $not$libresoc.v:137565$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:135793$5799 + cell $not $not$libresoc.v:137575$5844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core - connect \Y $not$libresoc.v:135793$5799_Y + connect \Y $not$libresoc.v:137575$5844_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:135796$5802 + cell $not $not$libresoc.v:137578$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$484 - connect \Y $not$libresoc.v:135796$5802_Y + connect \Y $not$libresoc.v:137578$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:135614$5620 + cell $or $or$libresoc.v:137396$5665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215823,10 +218318,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 - connect \Y $or$libresoc.v:135614$5620_Y + connect \Y $or$libresoc.v:137396$5665_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:135659$5665 + cell $or $or$libresoc.v:137441$5710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215834,10 +218329,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 - connect \Y $or$libresoc.v:135659$5665_Y + connect \Y $or$libresoc.v:137441$5710_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:135681$5687 + cell $or $or$libresoc.v:137463$5732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215845,10 +218340,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:135681$5687_Y + connect \Y $or$libresoc.v:137463$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:135728$5734 + cell $or $or$libresoc.v:137510$5779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215856,10 +218351,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$359 connect \B \$361 - connect \Y $or$libresoc.v:135728$5734_Y + connect \Y $or$libresoc.v:137510$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:135730$5736 + cell $or $or$libresoc.v:137512$5781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215867,10 +218362,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$363 connect \B \$365 - connect \Y $or$libresoc.v:135730$5736_Y + connect \Y $or$libresoc.v:137512$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:135736$5742 + cell $or $or$libresoc.v:137518$5787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215878,10 +218373,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:135736$5742_Y + connect \Y $or$libresoc.v:137518$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:135759$5765 + cell $or $or$libresoc.v:137541$5810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215889,10 +218384,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:135759$5765_Y + connect \Y $or$libresoc.v:137541$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:135799$5805 + cell $or $or$libresoc.v:137581$5850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215900,10 +218395,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$487 connect \B \$489 - connect \Y $or$libresoc.v:135799$5805_Y + connect \Y $or$libresoc.v:137581$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:135807$5814 + cell $or $or$libresoc.v:137589$5859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215911,10 +218406,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$504 connect \B \$506 - connect \Y $or$libresoc.v:135807$5814_Y + connect \Y $or$libresoc.v:137589$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:135815$5822 + cell $or $or$libresoc.v:137597$5867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215922,1250 +218417,1250 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:135815$5822_Y + connect \Y $or$libresoc.v:137597$5867_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:135804$5811 + cell $pos $pos$libresoc.v:137586$5856 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:135804$5810_Y - connect \Y $pos$libresoc.v:135804$5811_Y + connect \A $extend$libresoc.v:137586$5855_Y + connect \Y $pos$libresoc.v:137586$5856_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135582$5588 + cell $mux $ternary$libresoc.v:137364$5633 parameter \WIDTH 1 connect \A \gpio_e15__pad__i connect \B \io_bd [24] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135582$5588_Y + connect \Y $ternary$libresoc.v:137364$5633_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135583$5589 + cell $mux $ternary$libresoc.v:137365$5634 parameter \WIDTH 1 connect \A \gpio_e15__core__o connect \B \io_bd [25] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135583$5589_Y + connect \Y $ternary$libresoc.v:137365$5634_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135584$5590 + cell $mux $ternary$libresoc.v:137366$5635 parameter \WIDTH 1 connect \A \gpio_e15__core__oe connect \B \io_bd [26] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135584$5590_Y + connect \Y $ternary$libresoc.v:137366$5635_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135585$5591 + cell $mux $ternary$libresoc.v:137367$5636 parameter \WIDTH 1 connect \A \gpio_s0__pad__i connect \B \io_bd [27] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135585$5591_Y + connect \Y $ternary$libresoc.v:137367$5636_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135586$5592 + cell $mux $ternary$libresoc.v:137368$5637 parameter \WIDTH 1 connect \A \gpio_s0__core__o connect \B \io_bd [28] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135586$5592_Y + connect \Y $ternary$libresoc.v:137368$5637_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135587$5593 + cell $mux $ternary$libresoc.v:137369$5638 parameter \WIDTH 1 connect \A \gpio_s0__core__oe connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135587$5593_Y + connect \Y $ternary$libresoc.v:137369$5638_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135588$5594 + cell $mux $ternary$libresoc.v:137370$5639 parameter \WIDTH 1 connect \A \gpio_s1__pad__i connect \B \io_bd [30] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135588$5594_Y + connect \Y $ternary$libresoc.v:137370$5639_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135589$5595 + cell $mux $ternary$libresoc.v:137371$5640 parameter \WIDTH 1 connect \A \gpio_s1__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135589$5595_Y + connect \Y $ternary$libresoc.v:137371$5640_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135590$5596 + cell $mux $ternary$libresoc.v:137372$5641 parameter \WIDTH 1 connect \A \gpio_s1__core__oe connect \B \io_bd [32] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135590$5596_Y + connect \Y $ternary$libresoc.v:137372$5641_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135591$5597 + cell $mux $ternary$libresoc.v:137373$5642 parameter \WIDTH 1 connect \A \gpio_s2__pad__i connect \B \io_bd [33] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135591$5597_Y + connect \Y $ternary$libresoc.v:137373$5642_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135593$5599 + cell $mux $ternary$libresoc.v:137375$5644 parameter \WIDTH 1 connect \A \gpio_s2__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135593$5599_Y + connect \Y $ternary$libresoc.v:137375$5644_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135594$5600 + cell $mux $ternary$libresoc.v:137376$5645 parameter \WIDTH 1 connect \A \gpio_s2__core__oe connect \B \io_bd [35] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135594$5600_Y + connect \Y $ternary$libresoc.v:137376$5645_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135595$5601 + cell $mux $ternary$libresoc.v:137377$5646 parameter \WIDTH 1 connect \A \gpio_s3__pad__i connect \B \io_bd [36] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135595$5601_Y + connect \Y $ternary$libresoc.v:137377$5646_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135596$5602 + cell $mux $ternary$libresoc.v:137378$5647 parameter \WIDTH 1 connect \A \gpio_s3__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135596$5602_Y + connect \Y $ternary$libresoc.v:137378$5647_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135597$5603 + cell $mux $ternary$libresoc.v:137379$5648 parameter \WIDTH 1 connect \A \gpio_s3__core__oe connect \B \io_bd [38] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135597$5603_Y + connect \Y $ternary$libresoc.v:137379$5648_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135598$5604 + cell $mux $ternary$libresoc.v:137380$5649 parameter \WIDTH 1 connect \A \gpio_s4__pad__i connect \B \io_bd [39] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135598$5604_Y + connect \Y $ternary$libresoc.v:137380$5649_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135599$5605 + cell $mux $ternary$libresoc.v:137381$5650 parameter \WIDTH 1 connect \A \gpio_s4__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135599$5605_Y + connect \Y $ternary$libresoc.v:137381$5650_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135600$5606 + cell $mux $ternary$libresoc.v:137382$5651 parameter \WIDTH 1 connect \A \gpio_s4__core__oe connect \B \io_bd [41] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135600$5606_Y + connect \Y $ternary$libresoc.v:137382$5651_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135601$5607 + cell $mux $ternary$libresoc.v:137383$5652 parameter \WIDTH 1 connect \A \gpio_s5__pad__i connect \B \io_bd [42] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135601$5607_Y + connect \Y $ternary$libresoc.v:137383$5652_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135602$5608 + cell $mux $ternary$libresoc.v:137384$5653 parameter \WIDTH 1 connect \A \gpio_s5__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135602$5608_Y + connect \Y $ternary$libresoc.v:137384$5653_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135604$5610 + cell $mux $ternary$libresoc.v:137386$5655 parameter \WIDTH 1 connect \A \gpio_s5__core__oe connect \B \io_bd [44] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135604$5610_Y + connect \Y $ternary$libresoc.v:137386$5655_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135605$5611 + cell $mux $ternary$libresoc.v:137387$5656 parameter \WIDTH 1 connect \A \gpio_s6__pad__i connect \B \io_bd [45] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135605$5611_Y + connect \Y $ternary$libresoc.v:137387$5656_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135606$5612 + cell $mux $ternary$libresoc.v:137388$5657 parameter \WIDTH 1 connect \A \gpio_s6__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135606$5612_Y + connect \Y $ternary$libresoc.v:137388$5657_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135607$5613 + cell $mux $ternary$libresoc.v:137389$5658 parameter \WIDTH 1 connect \A \gpio_s6__core__oe connect \B \io_bd [47] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135607$5613_Y + connect \Y $ternary$libresoc.v:137389$5658_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135608$5614 + cell $mux $ternary$libresoc.v:137390$5659 parameter \WIDTH 1 connect \A \gpio_s7__pad__i connect \B \io_bd [48] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135608$5614_Y + connect \Y $ternary$libresoc.v:137390$5659_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135609$5615 + cell $mux $ternary$libresoc.v:137391$5660 parameter \WIDTH 1 connect \A \gpio_s7__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135609$5615_Y + connect \Y $ternary$libresoc.v:137391$5660_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135610$5616 + cell $mux $ternary$libresoc.v:137392$5661 parameter \WIDTH 1 connect \A \gpio_s7__core__oe connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135610$5616_Y + connect \Y $ternary$libresoc.v:137392$5661_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135611$5617 + cell $mux $ternary$libresoc.v:137393$5662 parameter \WIDTH 1 connect \A \mspi0_clk__core__o connect \B \io_bd [51] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135611$5617_Y + connect \Y $ternary$libresoc.v:137393$5662_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135612$5618 + cell $mux $ternary$libresoc.v:137394$5663 parameter \WIDTH 1 connect \A \mspi0_cs_n__core__o connect \B \io_bd [52] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135612$5618_Y + connect \Y $ternary$libresoc.v:137394$5663_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135613$5619 + cell $mux $ternary$libresoc.v:137395$5664 parameter \WIDTH 1 connect \A \mspi0_mosi__core__o connect \B \io_bd [53] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135613$5619_Y + connect \Y $ternary$libresoc.v:137395$5664_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:135615$5621 + cell $mux $ternary$libresoc.v:137397$5666 parameter \WIDTH 1 connect \A \mspi0_miso__pad__i connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135615$5621_Y + connect \Y $ternary$libresoc.v:137397$5666_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135616$5622 + cell $mux $ternary$libresoc.v:137398$5667 parameter \WIDTH 1 connect \A \mspi1_clk__core__o connect \B \io_bd [55] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135616$5622_Y + connect \Y $ternary$libresoc.v:137398$5667_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135617$5623 + cell $mux $ternary$libresoc.v:137399$5668 parameter \WIDTH 1 connect \A \mspi1_cs_n__core__o connect \B \io_bd [56] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135617$5623_Y + connect \Y $ternary$libresoc.v:137399$5668_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135618$5624 + cell $mux $ternary$libresoc.v:137400$5669 parameter \WIDTH 1 connect \A \mspi1_mosi__core__o connect \B \io_bd [57] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135618$5624_Y + connect \Y $ternary$libresoc.v:137400$5669_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:135619$5625 + cell $mux $ternary$libresoc.v:137401$5670 parameter \WIDTH 1 connect \A \mspi1_miso__pad__i connect \B \io_bd [58] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135619$5625_Y + connect \Y $ternary$libresoc.v:137401$5670_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135620$5626 + cell $mux $ternary$libresoc.v:137402$5671 parameter \WIDTH 1 connect \A \mtwi_sda__pad__i connect \B \io_bd [59] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135620$5626_Y + connect \Y $ternary$libresoc.v:137402$5671_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135621$5627 + cell $mux $ternary$libresoc.v:137403$5672 parameter \WIDTH 1 connect \A \mtwi_sda__core__o connect \B \io_bd [60] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135621$5627_Y + connect \Y $ternary$libresoc.v:137403$5672_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135622$5628 + cell $mux $ternary$libresoc.v:137404$5673 parameter \WIDTH 1 connect \A \mtwi_sda__core__oe connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135622$5628_Y + connect \Y $ternary$libresoc.v:137404$5673_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135623$5629 + cell $mux $ternary$libresoc.v:137405$5674 parameter \WIDTH 1 connect \A \mtwi_scl__core__o connect \B \io_bd [62] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135623$5629_Y + connect \Y $ternary$libresoc.v:137405$5674_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135624$5630 + cell $mux $ternary$libresoc.v:137406$5675 parameter \WIDTH 1 connect \A \pwm_0__core__o connect \B \io_bd [63] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135624$5630_Y + connect \Y $ternary$libresoc.v:137406$5675_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135626$5632 + cell $mux $ternary$libresoc.v:137408$5677 parameter \WIDTH 1 connect \A \pwm_1__core__o connect \B \io_bd [64] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135626$5632_Y + connect \Y $ternary$libresoc.v:137408$5677_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135627$5633 + cell $mux $ternary$libresoc.v:137409$5678 parameter \WIDTH 1 connect \A \sd0_cmd__pad__i connect \B \io_bd [65] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135627$5633_Y + connect \Y $ternary$libresoc.v:137409$5678_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135628$5634 + cell $mux $ternary$libresoc.v:137410$5679 parameter \WIDTH 1 connect \A \sd0_cmd__core__o connect \B \io_bd [66] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135628$5634_Y + connect \Y $ternary$libresoc.v:137410$5679_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135629$5635 + cell $mux $ternary$libresoc.v:137411$5680 parameter \WIDTH 1 connect \A \sd0_cmd__core__oe connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135629$5635_Y + connect \Y $ternary$libresoc.v:137411$5680_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135630$5636 + cell $mux $ternary$libresoc.v:137412$5681 parameter \WIDTH 1 connect \A \sd0_clk__core__o connect \B \io_bd [68] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135630$5636_Y + connect \Y $ternary$libresoc.v:137412$5681_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135631$5637 + cell $mux $ternary$libresoc.v:137413$5682 parameter \WIDTH 1 connect \A \sd0_data0__pad__i connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135631$5637_Y + connect \Y $ternary$libresoc.v:137413$5682_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135632$5638 + cell $mux $ternary$libresoc.v:137414$5683 parameter \WIDTH 1 connect \A \sd0_data0__core__o connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135632$5638_Y + connect \Y $ternary$libresoc.v:137414$5683_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135633$5639 + cell $mux $ternary$libresoc.v:137415$5684 parameter \WIDTH 1 connect \A \sd0_data0__core__oe connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135633$5639_Y + connect \Y $ternary$libresoc.v:137415$5684_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135634$5640 + cell $mux $ternary$libresoc.v:137416$5685 parameter \WIDTH 1 connect \A \sd0_data1__pad__i connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135634$5640_Y + connect \Y $ternary$libresoc.v:137416$5685_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135635$5641 + cell $mux $ternary$libresoc.v:137417$5686 parameter \WIDTH 1 connect \A \sd0_data1__core__o connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135635$5641_Y + connect \Y $ternary$libresoc.v:137417$5686_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135638$5644 + cell $mux $ternary$libresoc.v:137420$5689 parameter \WIDTH 1 connect \A \sd0_data1__core__oe connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135638$5644_Y + connect \Y $ternary$libresoc.v:137420$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135639$5645 + cell $mux $ternary$libresoc.v:137421$5690 parameter \WIDTH 1 connect \A \sd0_data2__pad__i connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135639$5645_Y + connect \Y $ternary$libresoc.v:137421$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135640$5646 + cell $mux $ternary$libresoc.v:137422$5691 parameter \WIDTH 1 connect \A \sd0_data2__core__o connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135640$5646_Y + connect \Y $ternary$libresoc.v:137422$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135641$5647 + cell $mux $ternary$libresoc.v:137423$5692 parameter \WIDTH 1 connect \A \sd0_data2__core__oe connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135641$5647_Y + connect \Y $ternary$libresoc.v:137423$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135642$5648 + cell $mux $ternary$libresoc.v:137424$5693 parameter \WIDTH 1 connect \A \sd0_data3__pad__i connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135642$5648_Y + connect \Y $ternary$libresoc.v:137424$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135643$5649 + cell $mux $ternary$libresoc.v:137425$5694 parameter \WIDTH 1 connect \A \sd0_data3__core__o connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135643$5649_Y + connect \Y $ternary$libresoc.v:137425$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135644$5650 + cell $mux $ternary$libresoc.v:137426$5695 parameter \WIDTH 1 connect \A \sd0_data3__core__oe connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135644$5650_Y + connect \Y $ternary$libresoc.v:137426$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135645$5651 + cell $mux $ternary$libresoc.v:137427$5696 parameter \WIDTH 1 connect \A \sdr_dm_0__core__o connect \B \io_bd [81] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135645$5651_Y + connect \Y $ternary$libresoc.v:137427$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135646$5652 + cell $mux $ternary$libresoc.v:137428$5697 parameter \WIDTH 1 connect \A \sdr_dq_0__pad__i connect \B \io_bd [82] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135646$5652_Y + connect \Y $ternary$libresoc.v:137428$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135647$5653 + cell $mux $ternary$libresoc.v:137429$5698 parameter \WIDTH 1 connect \A \sdr_dq_0__core__o connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135647$5653_Y + connect \Y $ternary$libresoc.v:137429$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135649$5655 + cell $mux $ternary$libresoc.v:137431$5700 parameter \WIDTH 1 connect \A \sdr_dq_0__core__oe connect \B \io_bd [84] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135649$5655_Y + connect \Y $ternary$libresoc.v:137431$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135650$5656 + cell $mux $ternary$libresoc.v:137432$5701 parameter \WIDTH 1 connect \A \sdr_dq_1__pad__i connect \B \io_bd [85] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135650$5656_Y + connect \Y $ternary$libresoc.v:137432$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135651$5657 + cell $mux $ternary$libresoc.v:137433$5702 parameter \WIDTH 1 connect \A \sdr_dq_1__core__o connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135651$5657_Y + connect \Y $ternary$libresoc.v:137433$5702_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135652$5658 + cell $mux $ternary$libresoc.v:137434$5703 parameter \WIDTH 1 connect \A \sdr_dq_1__core__oe connect \B \io_bd [87] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135652$5658_Y + connect \Y $ternary$libresoc.v:137434$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135653$5659 + cell $mux $ternary$libresoc.v:137435$5704 parameter \WIDTH 1 connect \A \sdr_dq_2__pad__i connect \B \io_bd [88] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135653$5659_Y + connect \Y $ternary$libresoc.v:137435$5704_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135654$5660 + cell $mux $ternary$libresoc.v:137436$5705 parameter \WIDTH 1 connect \A \sdr_dq_2__core__o connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135654$5660_Y + connect \Y $ternary$libresoc.v:137436$5705_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135655$5661 + cell $mux $ternary$libresoc.v:137437$5706 parameter \WIDTH 1 connect \A \sdr_dq_2__core__oe connect \B \io_bd [90] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135655$5661_Y + connect \Y $ternary$libresoc.v:137437$5706_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135656$5662 + cell $mux $ternary$libresoc.v:137438$5707 parameter \WIDTH 1 connect \A \sdr_dq_3__pad__i connect \B \io_bd [91] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135656$5662_Y + connect \Y $ternary$libresoc.v:137438$5707_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135657$5663 + cell $mux $ternary$libresoc.v:137439$5708 parameter \WIDTH 1 connect \A \sdr_dq_3__core__o connect \B \io_bd [92] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135657$5663_Y + connect \Y $ternary$libresoc.v:137439$5708_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135658$5664 + cell $mux $ternary$libresoc.v:137440$5709 parameter \WIDTH 1 connect \A \sdr_dq_3__core__oe connect \B \io_bd [93] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135658$5664_Y + connect \Y $ternary$libresoc.v:137440$5709_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135660$5666 + cell $mux $ternary$libresoc.v:137442$5711 parameter \WIDTH 1 connect \A \sdr_dq_4__pad__i connect \B \io_bd [94] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135660$5666_Y + connect \Y $ternary$libresoc.v:137442$5711_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135661$5667 + cell $mux $ternary$libresoc.v:137443$5712 parameter \WIDTH 1 connect \A \sdr_dq_4__core__o connect \B \io_bd [95] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135661$5667_Y + connect \Y $ternary$libresoc.v:137443$5712_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135662$5668 + cell $mux $ternary$libresoc.v:137444$5713 parameter \WIDTH 1 connect \A \sdr_dq_4__core__oe connect \B \io_bd [96] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135662$5668_Y + connect \Y $ternary$libresoc.v:137444$5713_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135663$5669 + cell $mux $ternary$libresoc.v:137445$5714 parameter \WIDTH 1 connect \A \sdr_dq_5__pad__i connect \B \io_bd [97] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135663$5669_Y + connect \Y $ternary$libresoc.v:137445$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135664$5670 + cell $mux $ternary$libresoc.v:137446$5715 parameter \WIDTH 1 connect \A \sdr_dq_5__core__o connect \B \io_bd [98] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135664$5670_Y + connect \Y $ternary$libresoc.v:137446$5715_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135665$5671 + cell $mux $ternary$libresoc.v:137447$5716 parameter \WIDTH 1 connect \A \sdr_dq_5__core__oe connect \B \io_bd [99] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135665$5671_Y + connect \Y $ternary$libresoc.v:137447$5716_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135666$5672 + cell $mux $ternary$libresoc.v:137448$5717 parameter \WIDTH 1 connect \A \sdr_dq_6__pad__i connect \B \io_bd [100] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135666$5672_Y + connect \Y $ternary$libresoc.v:137448$5717_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135667$5673 + cell $mux $ternary$libresoc.v:137449$5718 parameter \WIDTH 1 connect \A \sdr_dq_6__core__o connect \B \io_bd [101] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135667$5673_Y + connect \Y $ternary$libresoc.v:137449$5718_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135668$5674 + cell $mux $ternary$libresoc.v:137450$5719 parameter \WIDTH 1 connect \A \sdr_dq_6__core__oe connect \B \io_bd [102] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135668$5674_Y + connect \Y $ternary$libresoc.v:137450$5719_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135669$5675 + cell $mux $ternary$libresoc.v:137451$5720 parameter \WIDTH 1 connect \A \sdr_dq_7__pad__i connect \B \io_bd [103] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135669$5675_Y + connect \Y $ternary$libresoc.v:137451$5720_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135671$5677 + cell $mux $ternary$libresoc.v:137453$5722 parameter \WIDTH 1 connect \A \sdr_dq_7__core__o connect \B \io_bd [104] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135671$5677_Y + connect \Y $ternary$libresoc.v:137453$5722_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135672$5678 + cell $mux $ternary$libresoc.v:137454$5723 parameter \WIDTH 1 connect \A \sdr_dq_7__core__oe connect \B \io_bd [105] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135672$5678_Y + connect \Y $ternary$libresoc.v:137454$5723_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135673$5679 + cell $mux $ternary$libresoc.v:137455$5724 parameter \WIDTH 1 connect \A \sdr_a_0__core__o connect \B \io_bd [106] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135673$5679_Y + connect \Y $ternary$libresoc.v:137455$5724_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135674$5680 + cell $mux $ternary$libresoc.v:137456$5725 parameter \WIDTH 1 connect \A \sdr_a_1__core__o connect \B \io_bd [107] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135674$5680_Y + connect \Y $ternary$libresoc.v:137456$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135675$5681 + cell $mux $ternary$libresoc.v:137457$5726 parameter \WIDTH 1 connect \A \sdr_a_2__core__o connect \B \io_bd [108] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135675$5681_Y + connect \Y $ternary$libresoc.v:137457$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135676$5682 + cell $mux $ternary$libresoc.v:137458$5727 parameter \WIDTH 1 connect \A \sdr_a_3__core__o connect \B \io_bd [109] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135676$5682_Y + connect \Y $ternary$libresoc.v:137458$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135677$5683 + cell $mux $ternary$libresoc.v:137459$5728 parameter \WIDTH 1 connect \A \sdr_a_4__core__o connect \B \io_bd [110] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135677$5683_Y + connect \Y $ternary$libresoc.v:137459$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135678$5684 + cell $mux $ternary$libresoc.v:137460$5729 parameter \WIDTH 1 connect \A \sdr_a_5__core__o connect \B \io_bd [111] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135678$5684_Y + connect \Y $ternary$libresoc.v:137460$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135679$5685 + cell $mux $ternary$libresoc.v:137461$5730 parameter \WIDTH 1 connect \A \sdr_a_6__core__o connect \B \io_bd [112] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135679$5685_Y + connect \Y $ternary$libresoc.v:137461$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135680$5686 + cell $mux $ternary$libresoc.v:137462$5731 parameter \WIDTH 1 connect \A \sdr_a_7__core__o connect \B \io_bd [113] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135680$5686_Y + connect \Y $ternary$libresoc.v:137462$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135682$5688 + cell $mux $ternary$libresoc.v:137464$5733 parameter \WIDTH 1 connect \A \sdr_a_8__core__o connect \B \io_bd [114] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135682$5688_Y + connect \Y $ternary$libresoc.v:137464$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135683$5689 + cell $mux $ternary$libresoc.v:137465$5734 parameter \WIDTH 1 connect \A \sdr_a_9__core__o connect \B \io_bd [115] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135683$5689_Y + connect \Y $ternary$libresoc.v:137465$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135684$5690 + cell $mux $ternary$libresoc.v:137466$5735 parameter \WIDTH 1 connect \A \sdr_ba_0__core__o connect \B \io_bd [116] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135684$5690_Y + connect \Y $ternary$libresoc.v:137466$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135685$5691 + cell $mux $ternary$libresoc.v:137467$5736 parameter \WIDTH 1 connect \A \sdr_ba_1__core__o connect \B \io_bd [117] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135685$5691_Y + connect \Y $ternary$libresoc.v:137467$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135686$5692 + cell $mux $ternary$libresoc.v:137468$5737 parameter \WIDTH 1 connect \A \sdr_clock__core__o connect \B \io_bd [118] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135686$5692_Y + connect \Y $ternary$libresoc.v:137468$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135687$5693 + cell $mux $ternary$libresoc.v:137469$5738 parameter \WIDTH 1 connect \A \sdr_cke__core__o connect \B \io_bd [119] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135687$5693_Y + connect \Y $ternary$libresoc.v:137469$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135688$5694 + cell $mux $ternary$libresoc.v:137470$5739 parameter \WIDTH 1 connect \A \sdr_ras_n__core__o connect \B \io_bd [120] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135688$5694_Y + connect \Y $ternary$libresoc.v:137470$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135689$5695 + cell $mux $ternary$libresoc.v:137471$5740 parameter \WIDTH 1 connect \A \sdr_cas_n__core__o connect \B \io_bd [121] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135689$5695_Y + connect \Y $ternary$libresoc.v:137471$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135690$5696 + cell $mux $ternary$libresoc.v:137472$5741 parameter \WIDTH 1 connect \A \sdr_we_n__core__o connect \B \io_bd [122] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135690$5696_Y + connect \Y $ternary$libresoc.v:137472$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135691$5697 + cell $mux $ternary$libresoc.v:137473$5742 parameter \WIDTH 1 connect \A \sdr_cs_n__core__o connect \B \io_bd [123] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135691$5697_Y + connect \Y $ternary$libresoc.v:137473$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135693$5699 + cell $mux $ternary$libresoc.v:137475$5744 parameter \WIDTH 1 connect \A \sdr_a_10__core__o connect \B \io_bd [124] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135693$5699_Y + connect \Y $ternary$libresoc.v:137475$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135694$5700 + cell $mux $ternary$libresoc.v:137476$5745 parameter \WIDTH 1 connect \A \sdr_a_11__core__o connect \B \io_bd [125] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135694$5700_Y + connect \Y $ternary$libresoc.v:137476$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:135695$5701 + cell $mux $ternary$libresoc.v:137477$5746 parameter \WIDTH 1 connect \A \sdr_a_12__core__o connect \B \io_bd [126] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135695$5701_Y + connect \Y $ternary$libresoc.v:137477$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135696$5702 + cell $mux $ternary$libresoc.v:137478$5747 parameter \WIDTH 1 connect \A \sdr_dm_1__pad__i connect \B \io_bd [127] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135696$5702_Y + connect \Y $ternary$libresoc.v:137478$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135697$5703 + cell $mux $ternary$libresoc.v:137479$5748 parameter \WIDTH 1 connect \A \sdr_dm_1__core__o connect \B \io_bd [128] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135697$5703_Y + connect \Y $ternary$libresoc.v:137479$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135698$5704 + cell $mux $ternary$libresoc.v:137480$5749 parameter \WIDTH 1 connect \A \sdr_dm_1__core__oe connect \B \io_bd [129] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135698$5704_Y + connect \Y $ternary$libresoc.v:137480$5749_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135699$5705 + cell $mux $ternary$libresoc.v:137481$5750 parameter \WIDTH 1 connect \A \sdr_dq_8__pad__i connect \B \io_bd [130] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135699$5705_Y + connect \Y $ternary$libresoc.v:137481$5750_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135700$5706 + cell $mux $ternary$libresoc.v:137482$5751 parameter \WIDTH 1 connect \A \sdr_dq_8__core__o connect \B \io_bd [131] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135700$5706_Y + connect \Y $ternary$libresoc.v:137482$5751_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135701$5707 + cell $mux $ternary$libresoc.v:137483$5752 parameter \WIDTH 1 connect \A \sdr_dq_8__core__oe connect \B \io_bd [132] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135701$5707_Y + connect \Y $ternary$libresoc.v:137483$5752_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135702$5708 + cell $mux $ternary$libresoc.v:137484$5753 parameter \WIDTH 1 connect \A \sdr_dq_9__pad__i connect \B \io_bd [133] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135702$5708_Y + connect \Y $ternary$libresoc.v:137484$5753_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135704$5710 + cell $mux $ternary$libresoc.v:137486$5755 parameter \WIDTH 1 connect \A \sdr_dq_9__core__o connect \B \io_bd [134] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135704$5710_Y + connect \Y $ternary$libresoc.v:137486$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135705$5711 + cell $mux $ternary$libresoc.v:137487$5756 parameter \WIDTH 1 connect \A \sdr_dq_9__core__oe connect \B \io_bd [135] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135705$5711_Y + connect \Y $ternary$libresoc.v:137487$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135706$5712 + cell $mux $ternary$libresoc.v:137488$5757 parameter \WIDTH 1 connect \A \sdr_dq_10__pad__i connect \B \io_bd [136] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135706$5712_Y + connect \Y $ternary$libresoc.v:137488$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135707$5713 + cell $mux $ternary$libresoc.v:137489$5758 parameter \WIDTH 1 connect \A \sdr_dq_10__core__o connect \B \io_bd [137] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135707$5713_Y + connect \Y $ternary$libresoc.v:137489$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135708$5714 + cell $mux $ternary$libresoc.v:137490$5759 parameter \WIDTH 1 connect \A \sdr_dq_10__core__oe connect \B \io_bd [138] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135708$5714_Y + connect \Y $ternary$libresoc.v:137490$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135709$5715 + cell $mux $ternary$libresoc.v:137491$5760 parameter \WIDTH 1 connect \A \sdr_dq_11__pad__i connect \B \io_bd [139] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135709$5715_Y + connect \Y $ternary$libresoc.v:137491$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135710$5716 + cell $mux $ternary$libresoc.v:137492$5761 parameter \WIDTH 1 connect \A \sdr_dq_11__core__o connect \B \io_bd [140] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135710$5716_Y + connect \Y $ternary$libresoc.v:137492$5761_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135711$5717 + cell $mux $ternary$libresoc.v:137493$5762 parameter \WIDTH 1 connect \A \sdr_dq_11__core__oe connect \B \io_bd [141] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135711$5717_Y + connect \Y $ternary$libresoc.v:137493$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135712$5718 + cell $mux $ternary$libresoc.v:137494$5763 parameter \WIDTH 1 connect \A \sdr_dq_12__pad__i connect \B \io_bd [142] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135712$5718_Y + connect \Y $ternary$libresoc.v:137494$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135713$5719 + cell $mux $ternary$libresoc.v:137495$5764 parameter \WIDTH 1 connect \A \sdr_dq_12__core__o connect \B \io_bd [143] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135713$5719_Y + connect \Y $ternary$libresoc.v:137495$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135715$5721 + cell $mux $ternary$libresoc.v:137497$5766 parameter \WIDTH 1 connect \A \sdr_dq_12__core__oe connect \B \io_bd [144] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135715$5721_Y + connect \Y $ternary$libresoc.v:137497$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135716$5722 + cell $mux $ternary$libresoc.v:137498$5767 parameter \WIDTH 1 connect \A \sdr_dq_13__pad__i connect \B \io_bd [145] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135716$5722_Y + connect \Y $ternary$libresoc.v:137498$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135717$5723 + cell $mux $ternary$libresoc.v:137499$5768 parameter \WIDTH 1 connect \A \sdr_dq_13__core__o connect \B \io_bd [146] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135717$5723_Y + connect \Y $ternary$libresoc.v:137499$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135718$5724 + cell $mux $ternary$libresoc.v:137500$5769 parameter \WIDTH 1 connect \A \sdr_dq_13__core__oe connect \B \io_bd [147] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135718$5724_Y + connect \Y $ternary$libresoc.v:137500$5769_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135719$5725 + cell $mux $ternary$libresoc.v:137501$5770 parameter \WIDTH 1 connect \A \sdr_dq_14__pad__i connect \B \io_bd [148] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135719$5725_Y + connect \Y $ternary$libresoc.v:137501$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135720$5726 + cell $mux $ternary$libresoc.v:137502$5771 parameter \WIDTH 1 connect \A \sdr_dq_14__core__o connect \B \io_bd [149] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135720$5726_Y + connect \Y $ternary$libresoc.v:137502$5771_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135721$5727 + cell $mux $ternary$libresoc.v:137503$5772 parameter \WIDTH 1 connect \A \sdr_dq_14__core__oe connect \B \io_bd [150] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135721$5727_Y + connect \Y $ternary$libresoc.v:137503$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135722$5728 + cell $mux $ternary$libresoc.v:137504$5773 parameter \WIDTH 1 connect \A \sdr_dq_15__pad__i connect \B \io_bd [151] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135722$5728_Y + connect \Y $ternary$libresoc.v:137504$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135723$5729 + cell $mux $ternary$libresoc.v:137505$5774 parameter \WIDTH 1 connect \A \sdr_dq_15__core__o connect \B \io_bd [152] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135723$5729_Y + connect \Y $ternary$libresoc.v:137505$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135724$5730 + cell $mux $ternary$libresoc.v:137506$5775 parameter \WIDTH 1 connect \A \sdr_dq_15__core__oe connect \B \io_bd [153] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135724$5730_Y + connect \Y $ternary$libresoc.v:137506$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:135811$5818 + cell $mux $ternary$libresoc.v:137593$5863 parameter \WIDTH 1 connect \A \eint_0__pad__i connect \B \io_bd [0] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135811$5818_Y + connect \Y $ternary$libresoc.v:137593$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:135812$5819 + cell $mux $ternary$libresoc.v:137594$5864 parameter \WIDTH 1 connect \A \eint_1__pad__i connect \B \io_bd [1] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135812$5819_Y + connect \Y $ternary$libresoc.v:137594$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:135813$5820 + cell $mux $ternary$libresoc.v:137595$5865 parameter \WIDTH 1 connect \A \eint_2__pad__i connect \B \io_bd [2] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135813$5820_Y + connect \Y $ternary$libresoc.v:137595$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135814$5821 + cell $mux $ternary$libresoc.v:137596$5866 parameter \WIDTH 1 connect \A \gpio_e8__pad__i connect \B \io_bd [3] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135814$5821_Y + connect \Y $ternary$libresoc.v:137596$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135816$5823 + cell $mux $ternary$libresoc.v:137598$5868 parameter \WIDTH 1 connect \A \gpio_e8__core__o connect \B \io_bd [4] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135816$5823_Y + connect \Y $ternary$libresoc.v:137598$5868_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135817$5824 + cell $mux $ternary$libresoc.v:137599$5869 parameter \WIDTH 1 connect \A \gpio_e8__core__oe connect \B \io_bd [5] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135817$5824_Y + connect \Y $ternary$libresoc.v:137599$5869_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135818$5825 + cell $mux $ternary$libresoc.v:137600$5870 parameter \WIDTH 1 connect \A \gpio_e9__pad__i connect \B \io_bd [6] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135818$5825_Y + connect \Y $ternary$libresoc.v:137600$5870_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135819$5826 + cell $mux $ternary$libresoc.v:137601$5871 parameter \WIDTH 1 connect \A \gpio_e9__core__o connect \B \io_bd [7] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135819$5826_Y + connect \Y $ternary$libresoc.v:137601$5871_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135820$5827 + cell $mux $ternary$libresoc.v:137602$5872 parameter \WIDTH 1 connect \A \gpio_e9__core__oe connect \B \io_bd [8] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135820$5827_Y + connect \Y $ternary$libresoc.v:137602$5872_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135821$5828 + cell $mux $ternary$libresoc.v:137603$5873 parameter \WIDTH 1 connect \A \gpio_e10__pad__i connect \B \io_bd [9] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135821$5828_Y + connect \Y $ternary$libresoc.v:137603$5873_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135822$5829 + cell $mux $ternary$libresoc.v:137604$5874 parameter \WIDTH 1 connect \A \gpio_e10__core__o connect \B \io_bd [10] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135822$5829_Y + connect \Y $ternary$libresoc.v:137604$5874_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135823$5830 + cell $mux $ternary$libresoc.v:137605$5875 parameter \WIDTH 1 connect \A \gpio_e10__core__oe connect \B \io_bd [11] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135823$5830_Y + connect \Y $ternary$libresoc.v:137605$5875_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135824$5831 + cell $mux $ternary$libresoc.v:137606$5876 parameter \WIDTH 1 connect \A \gpio_e11__pad__i connect \B \io_bd [12] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135824$5831_Y + connect \Y $ternary$libresoc.v:137606$5876_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135825$5832 + cell $mux $ternary$libresoc.v:137607$5877 parameter \WIDTH 1 connect \A \gpio_e11__core__o connect \B \io_bd [13] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135825$5832_Y + connect \Y $ternary$libresoc.v:137607$5877_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135827$5834 + cell $mux $ternary$libresoc.v:137609$5879 parameter \WIDTH 1 connect \A \gpio_e11__core__oe connect \B \io_bd [14] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135827$5834_Y + connect \Y $ternary$libresoc.v:137609$5879_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135828$5835 + cell $mux $ternary$libresoc.v:137610$5880 parameter \WIDTH 1 connect \A \gpio_e12__pad__i connect \B \io_bd [15] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135828$5835_Y + connect \Y $ternary$libresoc.v:137610$5880_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135829$5836 + cell $mux $ternary$libresoc.v:137611$5881 parameter \WIDTH 1 connect \A \gpio_e12__core__o connect \B \io_bd [16] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135829$5836_Y + connect \Y $ternary$libresoc.v:137611$5881_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135830$5837 + cell $mux $ternary$libresoc.v:137612$5882 parameter \WIDTH 1 connect \A \gpio_e12__core__oe connect \B \io_bd [17] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135830$5837_Y + connect \Y $ternary$libresoc.v:137612$5882_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135831$5838 + cell $mux $ternary$libresoc.v:137613$5883 parameter \WIDTH 1 connect \A \gpio_e13__pad__i connect \B \io_bd [18] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135831$5838_Y + connect \Y $ternary$libresoc.v:137613$5883_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135832$5839 + cell $mux $ternary$libresoc.v:137614$5884 parameter \WIDTH 1 connect \A \gpio_e13__core__o connect \B \io_bd [19] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135832$5839_Y + connect \Y $ternary$libresoc.v:137614$5884_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135833$5840 + cell $mux $ternary$libresoc.v:137615$5885 parameter \WIDTH 1 connect \A \gpio_e13__core__oe connect \B \io_bd [20] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135833$5840_Y + connect \Y $ternary$libresoc.v:137615$5885_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:135834$5841 + cell $mux $ternary$libresoc.v:137616$5886 parameter \WIDTH 1 connect \A \gpio_e14__pad__i connect \B \io_bd [21] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:135834$5841_Y + connect \Y $ternary$libresoc.v:137616$5886_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:135835$5842 + cell $mux $ternary$libresoc.v:137617$5887 parameter \WIDTH 1 connect \A \gpio_e14__core__o connect \B \io_bd [22] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135835$5842_Y + connect \Y $ternary$libresoc.v:137617$5887_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:135836$5843 + cell $mux $ternary$libresoc.v:137618$5888 parameter \WIDTH 1 connect \A \gpio_e14__core__oe connect \B \io_bd [23] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:135836$5843_Y + connect \Y $ternary$libresoc.v:137618$5888_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:135911.8-135923.4" + attribute \src "libresoc.v:137693.8-137705.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -217180,7 +219675,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:135924.12-135934.4" + attribute \src "libresoc.v:137706.12-137716.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo @@ -217193,7 +219688,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:135935.12-135945.4" + attribute \src "libresoc.v:137717.12-137727.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -217205,577 +219700,577 @@ module \jtag connect \tdo \_irblock_tdo connect \update \_fsm_update end - attribute \src "libresoc.v:134147.7-134147.20" - process $proc$libresoc.v:134147$6039 + attribute \src "libresoc.v:135928.7-135928.20" + process $proc$libresoc.v:135928$6084 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134705.13-134705.32" - process $proc$libresoc.v:134705$6040 + attribute \src "libresoc.v:136486.13-136486.32" + process $proc$libresoc.v:136486$6085 assign { } { } assign $1\dmi0__addr_i[3:0] 4'0000 sync always sync init update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:134710.14-134710.46" - process $proc$libresoc.v:134710$6041 + attribute \src "libresoc.v:136491.14-136491.46" + process $proc$libresoc.v:136491$6086 assign { } { } assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:134724.7-134724.29" - process $proc$libresoc.v:134724$6042 + attribute \src "libresoc.v:136505.7-136505.29" + process $proc$libresoc.v:136505$6087 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:134732.13-134732.36" - process $proc$libresoc.v:134732$6043 + attribute \src "libresoc.v:136513.13-136513.36" + process $proc$libresoc.v:136513$6088 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:134740.7-134740.37" - process $proc$libresoc.v:134740$6044 + attribute \src "libresoc.v:136521.7-136521.37" + process $proc$libresoc.v:136521$6089 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:134744.7-134744.42" - process $proc$libresoc.v:134744$6045 + attribute \src "libresoc.v:136525.7-136525.42" + process $proc$libresoc.v:136525$6090 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:134748.14-134748.51" - process $proc$libresoc.v:134748$6046 + attribute \src "libresoc.v:136529.14-136529.51" + process $proc$libresoc.v:136529$6091 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:134754.13-134754.35" - process $proc$libresoc.v:134754$6047 + attribute \src "libresoc.v:136535.13-136535.35" + process $proc$libresoc.v:136535$6092 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:134762.14-134762.52" - process $proc$libresoc.v:134762$6048 + attribute \src "libresoc.v:136543.14-136543.52" + process $proc$libresoc.v:136543$6093 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:134770.7-134770.37" - process $proc$libresoc.v:134770$6049 + attribute \src "libresoc.v:136551.7-136551.37" + process $proc$libresoc.v:136551$6094 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:134774.7-134774.42" - process $proc$libresoc.v:134774$6050 + attribute \src "libresoc.v:136555.7-136555.42" + process $proc$libresoc.v:136555$6095 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:134790.13-134790.29" - process $proc$libresoc.v:134790$6051 + attribute \src "libresoc.v:136571.13-136571.29" + process $proc$libresoc.v:136571$6096 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:134792.13-134792.35" - process $proc$libresoc.v:134792$6052 + attribute \src "libresoc.v:136573.13-136573.35" + process $proc$libresoc.v:136573$6097 assign { } { } - assign $0\fsm_state$503[2:0]$6053 3'000 + assign $0\fsm_state$503[2:0]$6098 3'000 sync always sync init - update \fsm_state$503 $0\fsm_state$503[2:0]$6053 + update \fsm_state$503 $0\fsm_state$503[2:0]$6098 end - attribute \src "libresoc.v:134990.15-134990.67" - process $proc$libresoc.v:134990$6054 + attribute \src "libresoc.v:136771.15-136771.67" + process $proc$libresoc.v:136771$6099 assign { } { } assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \io_bd $1\io_bd[153:0] end - attribute \src "libresoc.v:135002.15-135002.67" - process $proc$libresoc.v:135002$6055 + attribute \src "libresoc.v:136783.15-136783.67" + process $proc$libresoc.v:136783$6100 assign { } { } assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \io_sr $1\io_sr[153:0] end - attribute \src "libresoc.v:135011.14-135011.41" - process $proc$libresoc.v:135011$6056 + attribute \src "libresoc.v:136792.14-136792.41" + process $proc$libresoc.v:136792$6101 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:135020.14-135020.51" - process $proc$libresoc.v:135020$6057 + attribute \src "libresoc.v:136801.14-136801.51" + process $proc$libresoc.v:136801$6102 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:135034.7-135034.32" - process $proc$libresoc.v:135034$6058 + attribute \src "libresoc.v:136815.7-136815.32" + process $proc$libresoc.v:136815$6103 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:135042.14-135042.47" - process $proc$libresoc.v:135042$6059 + attribute \src "libresoc.v:136823.14-136823.47" + process $proc$libresoc.v:136823$6104 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:135050.7-135050.40" - process $proc$libresoc.v:135050$6060 + attribute \src "libresoc.v:136831.7-136831.40" + process $proc$libresoc.v:136831$6105 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:135054.7-135054.45" - process $proc$libresoc.v:135054$6061 + attribute \src "libresoc.v:136835.7-136835.45" + process $proc$libresoc.v:136835$6106 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:135058.14-135058.54" - process $proc$libresoc.v:135058$6062 + attribute \src "libresoc.v:136839.14-136839.54" + process $proc$libresoc.v:136839$6107 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:135064.13-135064.38" - process $proc$libresoc.v:135064$6063 + attribute \src "libresoc.v:136845.13-136845.38" + process $proc$libresoc.v:136845$6108 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:135072.14-135072.55" - process $proc$libresoc.v:135072$6064 + attribute \src "libresoc.v:136853.14-136853.55" + process $proc$libresoc.v:136853$6109 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:135080.7-135080.40" - process $proc$libresoc.v:135080$6065 + attribute \src "libresoc.v:136861.7-136861.40" + process $proc$libresoc.v:136861$6110 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:135084.7-135084.45" - process $proc$libresoc.v:135084$6066 + attribute \src "libresoc.v:136865.7-136865.45" + process $proc$libresoc.v:136865$6111 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:135514.7-135514.21" - process $proc$libresoc.v:135514$6067 + attribute \src "libresoc.v:137295.7-137295.21" + process $proc$libresoc.v:137295$6112 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "libresoc.v:135522.13-135522.27" - process $proc$libresoc.v:135522$6068 + attribute \src "libresoc.v:137303.13-137303.27" + process $proc$libresoc.v:137303$6113 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:135530.7-135530.29" - process $proc$libresoc.v:135530$6069 + attribute \src "libresoc.v:137311.7-137311.29" + process $proc$libresoc.v:137311$6114 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "libresoc.v:135534.7-135534.34" - process $proc$libresoc.v:135534$6070 + attribute \src "libresoc.v:137315.7-137315.34" + process $proc$libresoc.v:137315$6115 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:135544.7-135544.21" - process $proc$libresoc.v:135544$6071 + attribute \src "libresoc.v:137325.7-137325.21" + process $proc$libresoc.v:137325$6116 assign { } { } assign $1\sr5__oe[0:0] 1'0 sync always sync init update \sr5__oe $1\sr5__oe[0:0] end - attribute \src "libresoc.v:135552.13-135552.27" - process $proc$libresoc.v:135552$6072 + attribute \src "libresoc.v:137333.13-137333.27" + process $proc$libresoc.v:137333$6117 assign { } { } assign $1\sr5_reg[2:0] 3'000 sync always sync init update \sr5_reg $1\sr5_reg[2:0] end - attribute \src "libresoc.v:135560.7-135560.29" - process $proc$libresoc.v:135560$6073 + attribute \src "libresoc.v:137341.7-137341.29" + process $proc$libresoc.v:137341$6118 assign { } { } assign $1\sr5_update_core[0:0] 1'0 sync always sync init update \sr5_update_core $1\sr5_update_core[0:0] end - attribute \src "libresoc.v:135564.7-135564.34" - process $proc$libresoc.v:135564$6074 + attribute \src "libresoc.v:137345.7-137345.34" + process $proc$libresoc.v:137345$6119 assign { } { } assign $1\sr5_update_core_prev[0:0] 1'0 sync always sync init update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:135569.7-135569.26" - process $proc$libresoc.v:135569$6075 + attribute \src "libresoc.v:137350.7-137350.26" + process $proc$libresoc.v:137350$6120 assign { } { } assign $1\wb_dcache_en[0:0] 1'1 sync always sync init update \wb_dcache_en $1\wb_dcache_en[0:0] end - attribute \src "libresoc.v:135574.7-135574.26" - process $proc$libresoc.v:135574$6076 + attribute \src "libresoc.v:137355.7-137355.26" + process $proc$libresoc.v:137355$6121 assign { } { } assign $1\wb_icache_en[0:0] 1'1 sync always sync init update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:135578.7-135578.24" - process $proc$libresoc.v:135578$6077 + attribute \src "libresoc.v:137360.7-137360.24" + process $proc$libresoc.v:137360$6122 assign { } { } assign $1\wb_sram_en[0:0] 1'1 sync always sync init update \wb_sram_en $1\wb_sram_en[0:0] end - attribute \src "libresoc.v:135837.3-135838.41" - process $proc$libresoc.v:135837$5844 + attribute \src "libresoc.v:137619.3-137620.41" + process $proc$libresoc.v:137619$5889 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "libresoc.v:135839.3-135840.41" - process $proc$libresoc.v:135839$5845 + attribute \src "libresoc.v:137621.3-137622.41" + process $proc$libresoc.v:137621$5890 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:135841.3-135842.37" - process $proc$libresoc.v:135841$5846 + attribute \src "libresoc.v:137623.3-137624.37" + process $proc$libresoc.v:137623$5891 assign { } { } assign $0\wb_sram_en[0:0] \wb_sram_en$next sync posedge \clk update \wb_sram_en $0\wb_sram_en[0:0] end - attribute \src "libresoc.v:135843.3-135844.45" - process $proc$libresoc.v:135843$5847 + attribute \src "libresoc.v:137625.3-137626.45" + process $proc$libresoc.v:137625$5892 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:135845.3-135846.35" - process $proc$libresoc.v:135845$5848 + attribute \src "libresoc.v:137627.3-137628.35" + process $proc$libresoc.v:137627$5893 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:135847.3-135848.45" - process $proc$libresoc.v:135847$5849 + attribute \src "libresoc.v:137629.3-137630.45" + process $proc$libresoc.v:137629$5894 assign { } { } - assign $0\fsm_state$503[2:0]$5850 \fsm_state$503$next + assign $0\fsm_state$503[2:0]$5895 \fsm_state$503$next sync posedge \clk - update \fsm_state$503 $0\fsm_state$503[2:0]$5850 + update \fsm_state$503 $0\fsm_state$503[2:0]$5895 end - attribute \src "libresoc.v:135849.3-135850.41" - process $proc$libresoc.v:135849$5851 + attribute \src "libresoc.v:137631.3-137632.41" + process $proc$libresoc.v:137631$5896 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:135851.3-135852.51" - process $proc$libresoc.v:135851$5852 + attribute \src "libresoc.v:137633.3-137634.51" + process $proc$libresoc.v:137633$5897 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:135853.3-135854.45" - process $proc$libresoc.v:135853$5853 + attribute \src "libresoc.v:137635.3-137636.45" + process $proc$libresoc.v:137635$5898 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:135855.3-135856.35" - process $proc$libresoc.v:135855$5854 + attribute \src "libresoc.v:137637.3-137638.35" + process $proc$libresoc.v:137637$5899 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:135857.3-135858.41" - process $proc$libresoc.v:135857$5855 + attribute \src "libresoc.v:137639.3-137640.41" + process $proc$libresoc.v:137639$5900 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:135859.3-135860.31" - process $proc$libresoc.v:135859$5856 + attribute \src "libresoc.v:137641.3-137642.31" + process $proc$libresoc.v:137641$5901 assign { } { } assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "libresoc.v:135861.3-135862.31" - process $proc$libresoc.v:135861$5857 + attribute \src "libresoc.v:137643.3-137644.31" + process $proc$libresoc.v:137643$5902 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:135863.3-135864.57" - process $proc$libresoc.v:135863$5858 + attribute \src "libresoc.v:137645.3-137646.57" + process $proc$libresoc.v:137645$5903 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:135865.3-135866.47" - process $proc$libresoc.v:135865$5859 + attribute \src "libresoc.v:137647.3-137648.47" + process $proc$libresoc.v:137647$5904 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:135867.3-135868.47" - process $proc$libresoc.v:135867$5860 + attribute \src "libresoc.v:137649.3-137650.47" + process $proc$libresoc.v:137649$5905 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:135869.3-135870.47" - process $proc$libresoc.v:135869$5861 + attribute \src "libresoc.v:137651.3-137652.47" + process $proc$libresoc.v:137651$5906 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:135871.3-135872.73" - process $proc$libresoc.v:135871$5862 + attribute \src "libresoc.v:137653.3-137654.73" + process $proc$libresoc.v:137653$5907 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:135873.3-135874.63" - process $proc$libresoc.v:135873$5863 + attribute \src "libresoc.v:137655.3-137656.63" + process $proc$libresoc.v:137655$5908 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:135875.3-135876.47" - process $proc$libresoc.v:135875$5864 + attribute \src "libresoc.v:137657.3-137658.47" + process $proc$libresoc.v:137657$5909 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:135877.3-135878.47" - process $proc$libresoc.v:135877$5865 + attribute \src "libresoc.v:137659.3-137660.47" + process $proc$libresoc.v:137659$5910 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:135879.3-135880.73" - process $proc$libresoc.v:135879$5866 + attribute \src "libresoc.v:137661.3-137662.73" + process $proc$libresoc.v:137661$5911 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:135881.3-135882.63" - process $proc$libresoc.v:135881$5867 + attribute \src "libresoc.v:137663.3-137664.63" + process $proc$libresoc.v:137663$5912 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:135883.3-135884.53" - process $proc$libresoc.v:135883$5868 + attribute \src "libresoc.v:137665.3-137666.53" + process $proc$libresoc.v:137665$5913 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:135885.3-135886.53" - process $proc$libresoc.v:135885$5869 + attribute \src "libresoc.v:137667.3-137668.53" + process $proc$libresoc.v:137667$5914 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:135887.3-135888.79" - process $proc$libresoc.v:135887$5870 + attribute \src "libresoc.v:137669.3-137670.79" + process $proc$libresoc.v:137669$5915 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:135889.3-135890.69" - process $proc$libresoc.v:135889$5871 + attribute \src "libresoc.v:137671.3-137672.69" + process $proc$libresoc.v:137671$5916 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:135891.3-135892.53" - process $proc$libresoc.v:135891$5872 + attribute \src "libresoc.v:137673.3-137674.53" + process $proc$libresoc.v:137673$5917 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:135893.3-135894.53" - process $proc$libresoc.v:135893$5873 + attribute \src "libresoc.v:137675.3-137676.53" + process $proc$libresoc.v:137675$5918 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:135895.3-135896.79" - process $proc$libresoc.v:135895$5874 + attribute \src "libresoc.v:137677.3-137678.79" + process $proc$libresoc.v:137677$5919 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:135897.3-135898.69" - process $proc$libresoc.v:135897$5875 + attribute \src "libresoc.v:137679.3-137680.69" + process $proc$libresoc.v:137679$5920 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:135899.3-135900.31" - process $proc$libresoc.v:135899$5876 + attribute \src "libresoc.v:137681.3-137682.31" + process $proc$libresoc.v:137681$5921 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:135901.3-135902.31" - process $proc$libresoc.v:135901$5877 + attribute \src "libresoc.v:137683.3-137684.31" + process $proc$libresoc.v:137683$5922 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:135903.3-135904.57" - process $proc$libresoc.v:135903$5878 + attribute \src "libresoc.v:137685.3-137686.57" + process $proc$libresoc.v:137685$5923 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:135905.3-135906.47" - process $proc$libresoc.v:135905$5879 + attribute \src "libresoc.v:137687.3-137688.47" + process $proc$libresoc.v:137687$5924 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:135907.3-135908.27" - process $proc$libresoc.v:135907$5880 + attribute \src "libresoc.v:137689.3-137690.27" + process $proc$libresoc.v:137689$5925 assign { } { } assign $0\io_bd[153:0] \io_bd$next sync negedge \negjtag_clk update \io_bd $0\io_bd[153:0] end - attribute \src "libresoc.v:135909.3-135910.27" - process $proc$libresoc.v:135909$5881 + attribute \src "libresoc.v:137691.3-137692.27" + process $proc$libresoc.v:137691$5926 assign { } { } assign $0\io_sr[153:0] \io_sr$next sync posedge \posjtag_clk update \io_sr $0\io_sr[153:0] end - attribute \src "libresoc.v:135946.3-135961.6" - process $proc$libresoc.v:135946$5882 + attribute \src "libresoc.v:137728.3-137743.6" + process $proc$libresoc.v:137728$5927 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:135947.5-135947.29" + attribute \src "libresoc.v:137729.5-137729.29" switch \initial - attribute \src "libresoc.v:135947.9-135947.17" + attribute \src "libresoc.v:137729.9-137729.17" case 1'1 case end @@ -217799,14 +220294,14 @@ module \jtag sync always update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:135962.3-135970.6" - process $proc$libresoc.v:135962$5883 + attribute \src "libresoc.v:137744.3-137752.6" + process $proc$libresoc.v:137744$5928 assign { } { } assign { } { } - assign $0\sr0_update_core$next[0:0]$5884 $1\sr0_update_core$next[0:0]$5885 - attribute \src "libresoc.v:135963.5-135963.29" + assign $0\sr0_update_core$next[0:0]$5929 $1\sr0_update_core$next[0:0]$5930 + attribute \src "libresoc.v:137745.5-137745.29" switch \initial - attribute \src "libresoc.v:135963.9-135963.17" + attribute \src "libresoc.v:137745.9-137745.17" case 1'1 case end @@ -217815,21 +220310,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$5885 1'0 + assign $1\sr0_update_core$next[0:0]$5930 1'0 case - assign $1\sr0_update_core$next[0:0]$5885 \sr0_update + assign $1\sr0_update_core$next[0:0]$5930 \sr0_update end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5884 + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5929 end - attribute \src "libresoc.v:135971.3-135979.6" - process $proc$libresoc.v:135971$5886 + attribute \src "libresoc.v:137753.3-137761.6" + process $proc$libresoc.v:137753$5931 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5887 $1\sr0_update_core_prev$next[0:0]$5888 - attribute \src "libresoc.v:135972.5-135972.29" + assign $0\sr0_update_core_prev$next[0:0]$5932 $1\sr0_update_core_prev$next[0:0]$5933 + attribute \src "libresoc.v:137754.5-137754.29" switch \initial - attribute \src "libresoc.v:135972.9-135972.17" + attribute \src "libresoc.v:137754.9-137754.17" case 1'1 case end @@ -217838,21 +220333,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5888 1'0 + assign $1\sr0_update_core_prev$next[0:0]$5933 1'0 case - assign $1\sr0_update_core_prev$next[0:0]$5888 \sr0_update_core + assign $1\sr0_update_core_prev$next[0:0]$5933 \sr0_update_core end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5887 + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5932 end - attribute \src "libresoc.v:135980.3-135996.6" - process $proc$libresoc.v:135980$5889 + attribute \src "libresoc.v:137762.3-137778.6" + process $proc$libresoc.v:137762$5934 assign { } { } assign { } { } - assign $0\sr0__oe$next[0:0]$5890 $2\sr0__oe$next[0:0]$5892 - attribute \src "libresoc.v:135981.5-135981.29" + assign $0\sr0__oe$next[0:0]$5935 $2\sr0__oe$next[0:0]$5937 + attribute \src "libresoc.v:137763.5-137763.29" switch \initial - attribute \src "libresoc.v:135981.9-135981.17" + attribute \src "libresoc.v:137763.9-137763.17" case 1'1 case end @@ -217861,34 +220356,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0__oe$next[0:0]$5891 \sr0_isir + assign $1\sr0__oe$next[0:0]$5936 \sr0_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr0__oe$next[0:0]$5891 1'0 + assign $1\sr0__oe$next[0:0]$5936 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$5892 1'0 + assign $2\sr0__oe$next[0:0]$5937 1'0 case - assign $2\sr0__oe$next[0:0]$5892 $1\sr0__oe$next[0:0]$5891 + assign $2\sr0__oe$next[0:0]$5937 $1\sr0__oe$next[0:0]$5936 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5890 + update \sr0__oe$next $0\sr0__oe$next[0:0]$5935 end - attribute \src "libresoc.v:135997.3-136017.6" - process $proc$libresoc.v:135997$5893 + attribute \src "libresoc.v:137779.3-137799.6" + process $proc$libresoc.v:137779$5938 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr0_reg$next[2:0]$5894 $3\sr0_reg$next[2:0]$5897 - attribute \src "libresoc.v:135998.5-135998.29" + assign $0\sr0_reg$next[2:0]$5939 $3\sr0_reg$next[2:0]$5942 + attribute \src "libresoc.v:137780.5-137780.29" switch \initial - attribute \src "libresoc.v:135998.9-135998.17" + attribute \src "libresoc.v:137780.9-137780.17" case 1'1 case end @@ -217897,39 +220392,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_reg$next[2:0]$5895 { \TAP_bus__tdi \sr0_reg [2:1] } + assign $1\sr0_reg$next[2:0]$5940 { \TAP_bus__tdi \sr0_reg [2:1] } case - assign $1\sr0_reg$next[2:0]$5895 \sr0_reg + assign $1\sr0_reg$next[2:0]$5940 \sr0_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr0_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0_reg$next[2:0]$5896 \sr0__i + assign $2\sr0_reg$next[2:0]$5941 \sr0__i case - assign $2\sr0_reg$next[2:0]$5896 $1\sr0_reg$next[2:0]$5895 + assign $2\sr0_reg$next[2:0]$5941 $1\sr0_reg$next[2:0]$5940 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr0_reg$next[2:0]$5897 3'000 + assign $3\sr0_reg$next[2:0]$5942 3'000 case - assign $3\sr0_reg$next[2:0]$5897 $2\sr0_reg$next[2:0]$5896 + assign $3\sr0_reg$next[2:0]$5942 $2\sr0_reg$next[2:0]$5941 end sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5894 + update \sr0_reg$next $0\sr0_reg$next[2:0]$5939 end - attribute \src "libresoc.v:136018.3-136026.6" - process $proc$libresoc.v:136018$5898 + attribute \src "libresoc.v:137800.3-137808.6" + process $proc$libresoc.v:137800$5943 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5899 $1\jtag_wb_addrsr_update_core$next[0:0]$5900 - attribute \src "libresoc.v:136019.5-136019.29" + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5944 $1\jtag_wb_addrsr_update_core$next[0:0]$5945 + attribute \src "libresoc.v:137801.5-137801.29" switch \initial - attribute \src "libresoc.v:136019.9-136019.17" + attribute \src "libresoc.v:137801.9-137801.17" case 1'1 case end @@ -217938,21 +220433,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5900 1'0 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5945 1'0 case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5900 \jtag_wb_addrsr_update + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5945 \jtag_wb_addrsr_update end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5899 + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5944 end - attribute \src "libresoc.v:136027.3-136035.6" - process $proc$libresoc.v:136027$5901 + attribute \src "libresoc.v:137809.3-137817.6" + process $proc$libresoc.v:137809$5946 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5902 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5903 - attribute \src "libresoc.v:136028.5-136028.29" + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 + attribute \src "libresoc.v:137810.5-137810.29" switch \initial - attribute \src "libresoc.v:136028.9-136028.17" + attribute \src "libresoc.v:137810.9-137810.17" case 1'1 case end @@ -217961,21 +220456,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5903 1'0 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 1'0 case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5903 \jtag_wb_addrsr_update_core + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 \jtag_wb_addrsr_update_core end sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5902 + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 end - attribute \src "libresoc.v:136036.3-136052.6" - process $proc$libresoc.v:136036$5904 + attribute \src "libresoc.v:137818.3-137834.6" + process $proc$libresoc.v:137818$5949 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5905 $2\jtag_wb_addrsr__oe$next[0:0]$5907 - attribute \src "libresoc.v:136037.5-136037.29" + assign $0\jtag_wb_addrsr__oe$next[0:0]$5950 $2\jtag_wb_addrsr__oe$next[0:0]$5952 + attribute \src "libresoc.v:137819.5-137819.29" switch \initial - attribute \src "libresoc.v:136037.9-136037.17" + attribute \src "libresoc.v:137819.9-137819.17" case 1'1 case end @@ -217984,34 +220479,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5906 \jtag_wb_addrsr_isir + assign $1\jtag_wb_addrsr__oe$next[0:0]$5951 \jtag_wb_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5906 1'0 + assign $1\jtag_wb_addrsr__oe$next[0:0]$5951 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$5907 1'0 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5952 1'0 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$5907 $1\jtag_wb_addrsr__oe$next[0:0]$5906 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5952 $1\jtag_wb_addrsr__oe$next[0:0]$5951 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5905 + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5950 end - attribute \src "libresoc.v:136053.3-136073.6" - process $proc$libresoc.v:136053$5908 + attribute \src "libresoc.v:137835.3-137855.6" + process $proc$libresoc.v:137835$5953 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$5909 $3\jtag_wb_addrsr_reg$next[28:0]$5912 - attribute \src "libresoc.v:136054.5-136054.29" + assign $0\jtag_wb_addrsr_reg$next[28:0]$5954 $3\jtag_wb_addrsr_reg$next[28:0]$5957 + attribute \src "libresoc.v:137836.5-137836.29" switch \initial - attribute \src "libresoc.v:136054.9-136054.17" + attribute \src "libresoc.v:137836.9-137836.17" case 1'1 case end @@ -218020,39 +220515,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$5910 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + assign $1\jtag_wb_addrsr_reg$next[28:0]$5955 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } case - assign $1\jtag_wb_addrsr_reg$next[28:0]$5910 \jtag_wb_addrsr_reg + assign $1\jtag_wb_addrsr_reg$next[28:0]$5955 \jtag_wb_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$5911 \jtag_wb_addrsr__i + assign $2\jtag_wb_addrsr_reg$next[28:0]$5956 \jtag_wb_addrsr__i case - assign $2\jtag_wb_addrsr_reg$next[28:0]$5911 $1\jtag_wb_addrsr_reg$next[28:0]$5910 + assign $2\jtag_wb_addrsr_reg$next[28:0]$5956 $1\jtag_wb_addrsr_reg$next[28:0]$5955 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$5912 29'00000000000000000000000000000 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5957 29'00000000000000000000000000000 case - assign $3\jtag_wb_addrsr_reg$next[28:0]$5912 $2\jtag_wb_addrsr_reg$next[28:0]$5911 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5957 $2\jtag_wb_addrsr_reg$next[28:0]$5956 end sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5909 + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5954 end - attribute \src "libresoc.v:136074.3-136082.6" - process $proc$libresoc.v:136074$5913 + attribute \src "libresoc.v:137856.3-137864.6" + process $proc$libresoc.v:137856$5958 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$5914 $1\jtag_wb_datasr_update_core$next[0:0]$5915 - attribute \src "libresoc.v:136075.5-136075.29" + assign $0\jtag_wb_datasr_update_core$next[0:0]$5959 $1\jtag_wb_datasr_update_core$next[0:0]$5960 + attribute \src "libresoc.v:137857.5-137857.29" switch \initial - attribute \src "libresoc.v:136075.9-136075.17" + attribute \src "libresoc.v:137857.9-137857.17" case 1'1 case end @@ -218061,21 +220556,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$5915 1'0 + assign $1\jtag_wb_datasr_update_core$next[0:0]$5960 1'0 case - assign $1\jtag_wb_datasr_update_core$next[0:0]$5915 \jtag_wb_datasr_update + assign $1\jtag_wb_datasr_update_core$next[0:0]$5960 \jtag_wb_datasr_update end sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5914 + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5959 end - attribute \src "libresoc.v:136083.3-136091.6" - process $proc$libresoc.v:136083$5916 + attribute \src "libresoc.v:137865.3-137873.6" + process $proc$libresoc.v:137865$5961 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5917 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5918 - attribute \src "libresoc.v:136084.5-136084.29" + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 + attribute \src "libresoc.v:137866.5-137866.29" switch \initial - attribute \src "libresoc.v:136084.9-136084.17" + attribute \src "libresoc.v:137866.9-137866.17" case 1'1 case end @@ -218084,21 +220579,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5918 1'0 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 1'0 case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5918 \jtag_wb_datasr_update_core + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 \jtag_wb_datasr_update_core end sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5917 + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 end - attribute \src "libresoc.v:136092.3-136108.6" - process $proc$libresoc.v:136092$5919 + attribute \src "libresoc.v:137874.3-137890.6" + process $proc$libresoc.v:137874$5964 assign { } { } assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$5920 $2\jtag_wb_datasr__oe$next[1:0]$5922 - attribute \src "libresoc.v:136093.5-136093.29" + assign $0\jtag_wb_datasr__oe$next[1:0]$5965 $2\jtag_wb_datasr__oe$next[1:0]$5967 + attribute \src "libresoc.v:137875.5-137875.29" switch \initial - attribute \src "libresoc.v:136093.9-136093.17" + attribute \src "libresoc.v:137875.9-137875.17" case 1'1 case end @@ -218107,34 +220602,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5921 \jtag_wb_datasr_isir + assign $1\jtag_wb_datasr__oe$next[1:0]$5966 \jtag_wb_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5921 2'00 + assign $1\jtag_wb_datasr__oe$next[1:0]$5966 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$5922 2'00 + assign $2\jtag_wb_datasr__oe$next[1:0]$5967 2'00 case - assign $2\jtag_wb_datasr__oe$next[1:0]$5922 $1\jtag_wb_datasr__oe$next[1:0]$5921 + assign $2\jtag_wb_datasr__oe$next[1:0]$5967 $1\jtag_wb_datasr__oe$next[1:0]$5966 end sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5920 + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5965 end - attribute \src "libresoc.v:136109.3-136129.6" - process $proc$libresoc.v:136109$5923 + attribute \src "libresoc.v:137891.3-137911.6" + process $proc$libresoc.v:137891$5968 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$5924 $3\jtag_wb_datasr_reg$next[63:0]$5927 - attribute \src "libresoc.v:136110.5-136110.29" + assign $0\jtag_wb_datasr_reg$next[63:0]$5969 $3\jtag_wb_datasr_reg$next[63:0]$5972 + attribute \src "libresoc.v:137892.5-137892.29" switch \initial - attribute \src "libresoc.v:136110.9-136110.17" + attribute \src "libresoc.v:137892.9-137892.17" case 1'1 case end @@ -218143,39 +220638,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$5925 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + assign $1\jtag_wb_datasr_reg$next[63:0]$5970 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case - assign $1\jtag_wb_datasr_reg$next[63:0]$5925 \jtag_wb_datasr_reg + assign $1\jtag_wb_datasr_reg$next[63:0]$5970 \jtag_wb_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$5926 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr_reg$next[63:0]$5971 \jtag_wb_datasr__i case - assign $2\jtag_wb_datasr_reg$next[63:0]$5926 $1\jtag_wb_datasr_reg$next[63:0]$5925 + assign $2\jtag_wb_datasr_reg$next[63:0]$5971 $1\jtag_wb_datasr_reg$next[63:0]$5970 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$5927 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr_reg$next[63:0]$5972 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr_reg$next[63:0]$5927 $2\jtag_wb_datasr_reg$next[63:0]$5926 + assign $3\jtag_wb_datasr_reg$next[63:0]$5972 $2\jtag_wb_datasr_reg$next[63:0]$5971 end sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5924 + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5969 end - attribute \src "libresoc.v:136130.3-136138.6" - process $proc$libresoc.v:136130$5928 + attribute \src "libresoc.v:137912.3-137920.6" + process $proc$libresoc.v:137912$5973 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$5929 $1\dmi0_addrsr_update_core$next[0:0]$5930 - attribute \src "libresoc.v:136131.5-136131.29" + assign $0\dmi0_addrsr_update_core$next[0:0]$5974 $1\dmi0_addrsr_update_core$next[0:0]$5975 + attribute \src "libresoc.v:137913.5-137913.29" switch \initial - attribute \src "libresoc.v:136131.9-136131.17" + attribute \src "libresoc.v:137913.9-137913.17" case 1'1 case end @@ -218184,21 +220679,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$5930 1'0 + assign $1\dmi0_addrsr_update_core$next[0:0]$5975 1'0 case - assign $1\dmi0_addrsr_update_core$next[0:0]$5930 \dmi0_addrsr_update + assign $1\dmi0_addrsr_update_core$next[0:0]$5975 \dmi0_addrsr_update end sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5929 + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5974 end - attribute \src "libresoc.v:136139.3-136147.6" - process $proc$libresoc.v:136139$5931 + attribute \src "libresoc.v:137921.3-137929.6" + process $proc$libresoc.v:137921$5976 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5932 $1\dmi0_addrsr_update_core_prev$next[0:0]$5933 - attribute \src "libresoc.v:136140.5-136140.29" + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 + attribute \src "libresoc.v:137922.5-137922.29" switch \initial - attribute \src "libresoc.v:136140.9-136140.17" + attribute \src "libresoc.v:137922.9-137922.17" case 1'1 case end @@ -218207,21 +220702,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5933 1'0 + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 1'0 case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5933 \dmi0_addrsr_update_core + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 \dmi0_addrsr_update_core end sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5932 + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 end - attribute \src "libresoc.v:136148.3-136164.6" - process $proc$libresoc.v:136148$5934 + attribute \src "libresoc.v:137930.3-137946.6" + process $proc$libresoc.v:137930$5979 assign { } { } assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$5935 $2\dmi0_addrsr__oe$next[0:0]$5937 - attribute \src "libresoc.v:136149.5-136149.29" + assign $0\dmi0_addrsr__oe$next[0:0]$5980 $2\dmi0_addrsr__oe$next[0:0]$5982 + attribute \src "libresoc.v:137931.5-137931.29" switch \initial - attribute \src "libresoc.v:136149.9-136149.17" + attribute \src "libresoc.v:137931.9-137931.17" case 1'1 case end @@ -218230,34 +220725,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5936 \dmi0_addrsr_isir + assign $1\dmi0_addrsr__oe$next[0:0]$5981 \dmi0_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5936 1'0 + assign $1\dmi0_addrsr__oe$next[0:0]$5981 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$5937 1'0 + assign $2\dmi0_addrsr__oe$next[0:0]$5982 1'0 case - assign $2\dmi0_addrsr__oe$next[0:0]$5937 $1\dmi0_addrsr__oe$next[0:0]$5936 + assign $2\dmi0_addrsr__oe$next[0:0]$5982 $1\dmi0_addrsr__oe$next[0:0]$5981 end sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5935 + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5980 end - attribute \src "libresoc.v:136165.3-136185.6" - process $proc$libresoc.v:136165$5938 + attribute \src "libresoc.v:137947.3-137967.6" + process $proc$libresoc.v:137947$5983 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$5939 $3\dmi0_addrsr_reg$next[7:0]$5942 - attribute \src "libresoc.v:136166.5-136166.29" + assign $0\dmi0_addrsr_reg$next[7:0]$5984 $3\dmi0_addrsr_reg$next[7:0]$5987 + attribute \src "libresoc.v:137948.5-137948.29" switch \initial - attribute \src "libresoc.v:136166.9-136166.17" + attribute \src "libresoc.v:137948.9-137948.17" case 1'1 case end @@ -218266,39 +220761,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$5940 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + assign $1\dmi0_addrsr_reg$next[7:0]$5985 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case - assign $1\dmi0_addrsr_reg$next[7:0]$5940 \dmi0_addrsr_reg + assign $1\dmi0_addrsr_reg$next[7:0]$5985 \dmi0_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$5941 \dmi0_addrsr__i + assign $2\dmi0_addrsr_reg$next[7:0]$5986 \dmi0_addrsr__i case - assign $2\dmi0_addrsr_reg$next[7:0]$5941 $1\dmi0_addrsr_reg$next[7:0]$5940 + assign $2\dmi0_addrsr_reg$next[7:0]$5986 $1\dmi0_addrsr_reg$next[7:0]$5985 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$5942 8'00000000 + assign $3\dmi0_addrsr_reg$next[7:0]$5987 8'00000000 case - assign $3\dmi0_addrsr_reg$next[7:0]$5942 $2\dmi0_addrsr_reg$next[7:0]$5941 + assign $3\dmi0_addrsr_reg$next[7:0]$5987 $2\dmi0_addrsr_reg$next[7:0]$5986 end sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5939 + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5984 end - attribute \src "libresoc.v:136186.3-136194.6" - process $proc$libresoc.v:136186$5943 + attribute \src "libresoc.v:137968.3-137976.6" + process $proc$libresoc.v:137968$5988 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$5944 $1\dmi0_datasr_update_core$next[0:0]$5945 - attribute \src "libresoc.v:136187.5-136187.29" + assign $0\dmi0_datasr_update_core$next[0:0]$5989 $1\dmi0_datasr_update_core$next[0:0]$5990 + attribute \src "libresoc.v:137969.5-137969.29" switch \initial - attribute \src "libresoc.v:136187.9-136187.17" + attribute \src "libresoc.v:137969.9-137969.17" case 1'1 case end @@ -218307,21 +220802,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$5945 1'0 + assign $1\dmi0_datasr_update_core$next[0:0]$5990 1'0 case - assign $1\dmi0_datasr_update_core$next[0:0]$5945 \dmi0_datasr_update + assign $1\dmi0_datasr_update_core$next[0:0]$5990 \dmi0_datasr_update end sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5944 + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5989 end - attribute \src "libresoc.v:136195.3-136203.6" - process $proc$libresoc.v:136195$5946 + attribute \src "libresoc.v:137977.3-137985.6" + process $proc$libresoc.v:137977$5991 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$5947 $1\dmi0_datasr_update_core_prev$next[0:0]$5948 - attribute \src "libresoc.v:136196.5-136196.29" + assign $0\dmi0_datasr_update_core_prev$next[0:0]$5992 $1\dmi0_datasr_update_core_prev$next[0:0]$5993 + attribute \src "libresoc.v:137978.5-137978.29" switch \initial - attribute \src "libresoc.v:136196.9-136196.17" + attribute \src "libresoc.v:137978.9-137978.17" case 1'1 case end @@ -218330,21 +220825,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5948 1'0 + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5993 1'0 case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5948 \dmi0_datasr_update_core + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5993 \dmi0_datasr_update_core end sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5947 + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5992 end - attribute \src "libresoc.v:136204.3-136220.6" - process $proc$libresoc.v:136204$5949 + attribute \src "libresoc.v:137986.3-138002.6" + process $proc$libresoc.v:137986$5994 assign { } { } assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$5950 $2\dmi0_datasr__oe$next[1:0]$5952 - attribute \src "libresoc.v:136205.5-136205.29" + assign $0\dmi0_datasr__oe$next[1:0]$5995 $2\dmi0_datasr__oe$next[1:0]$5997 + attribute \src "libresoc.v:137987.5-137987.29" switch \initial - attribute \src "libresoc.v:136205.9-136205.17" + attribute \src "libresoc.v:137987.9-137987.17" case 1'1 case end @@ -218353,34 +220848,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5951 \dmi0_datasr_isir + assign $1\dmi0_datasr__oe$next[1:0]$5996 \dmi0_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5951 2'00 + assign $1\dmi0_datasr__oe$next[1:0]$5996 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$5952 2'00 + assign $2\dmi0_datasr__oe$next[1:0]$5997 2'00 case - assign $2\dmi0_datasr__oe$next[1:0]$5952 $1\dmi0_datasr__oe$next[1:0]$5951 + assign $2\dmi0_datasr__oe$next[1:0]$5997 $1\dmi0_datasr__oe$next[1:0]$5996 end sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5950 + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5995 end - attribute \src "libresoc.v:136221.3-136241.6" - process $proc$libresoc.v:136221$5953 + attribute \src "libresoc.v:138003.3-138023.6" + process $proc$libresoc.v:138003$5998 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$5954 $3\dmi0_datasr_reg$next[63:0]$5957 - attribute \src "libresoc.v:136222.5-136222.29" + assign $0\dmi0_datasr_reg$next[63:0]$5999 $3\dmi0_datasr_reg$next[63:0]$6002 + attribute \src "libresoc.v:138004.5-138004.29" switch \initial - attribute \src "libresoc.v:136222.9-136222.17" + attribute \src "libresoc.v:138004.9-138004.17" case 1'1 case end @@ -218389,39 +220884,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$5955 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + assign $1\dmi0_datasr_reg$next[63:0]$6000 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\dmi0_datasr_reg$next[63:0]$5955 \dmi0_datasr_reg + assign $1\dmi0_datasr_reg$next[63:0]$6000 \dmi0_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$5956 \dmi0_datasr__i + assign $2\dmi0_datasr_reg$next[63:0]$6001 \dmi0_datasr__i case - assign $2\dmi0_datasr_reg$next[63:0]$5956 $1\dmi0_datasr_reg$next[63:0]$5955 + assign $2\dmi0_datasr_reg$next[63:0]$6001 $1\dmi0_datasr_reg$next[63:0]$6000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$5957 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr_reg$next[63:0]$6002 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr_reg$next[63:0]$5957 $2\dmi0_datasr_reg$next[63:0]$5956 + assign $3\dmi0_datasr_reg$next[63:0]$6002 $2\dmi0_datasr_reg$next[63:0]$6001 end sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5954 + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5999 end - attribute \src "libresoc.v:136242.3-136250.6" - process $proc$libresoc.v:136242$5958 + attribute \src "libresoc.v:138024.3-138032.6" + process $proc$libresoc.v:138024$6003 assign { } { } assign { } { } - assign $0\sr5_update_core$next[0:0]$5959 $1\sr5_update_core$next[0:0]$5960 - attribute \src "libresoc.v:136243.5-136243.29" + assign $0\sr5_update_core$next[0:0]$6004 $1\sr5_update_core$next[0:0]$6005 + attribute \src "libresoc.v:138025.5-138025.29" switch \initial - attribute \src "libresoc.v:136243.9-136243.17" + attribute \src "libresoc.v:138025.9-138025.17" case 1'1 case end @@ -218430,21 +220925,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core$next[0:0]$5960 1'0 + assign $1\sr5_update_core$next[0:0]$6005 1'0 case - assign $1\sr5_update_core$next[0:0]$5960 \sr5_update + assign $1\sr5_update_core$next[0:0]$6005 \sr5_update end sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5959 + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6004 end - attribute \src "libresoc.v:136251.3-136259.6" - process $proc$libresoc.v:136251$5961 + attribute \src "libresoc.v:138033.3-138041.6" + process $proc$libresoc.v:138033$6006 assign { } { } assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$5962 $1\sr5_update_core_prev$next[0:0]$5963 - attribute \src "libresoc.v:136252.5-136252.29" + assign $0\sr5_update_core_prev$next[0:0]$6007 $1\sr5_update_core_prev$next[0:0]$6008 + attribute \src "libresoc.v:138034.5-138034.29" switch \initial - attribute \src "libresoc.v:136252.9-136252.17" + attribute \src "libresoc.v:138034.9-138034.17" case 1'1 case end @@ -218453,21 +220948,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$5963 1'0 + assign $1\sr5_update_core_prev$next[0:0]$6008 1'0 case - assign $1\sr5_update_core_prev$next[0:0]$5963 \sr5_update_core + assign $1\sr5_update_core_prev$next[0:0]$6008 \sr5_update_core end sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5962 + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6007 end - attribute \src "libresoc.v:136260.3-136276.6" - process $proc$libresoc.v:136260$5964 + attribute \src "libresoc.v:138042.3-138058.6" + process $proc$libresoc.v:138042$6009 assign { } { } assign { } { } - assign $0\sr5__oe$next[0:0]$5965 $2\sr5__oe$next[0:0]$5967 - attribute \src "libresoc.v:136261.5-136261.29" + assign $0\sr5__oe$next[0:0]$6010 $2\sr5__oe$next[0:0]$6012 + attribute \src "libresoc.v:138043.5-138043.29" switch \initial - attribute \src "libresoc.v:136261.9-136261.17" + attribute \src "libresoc.v:138043.9-138043.17" case 1'1 case end @@ -218476,34 +220971,34 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__oe$next[0:0]$5966 \sr5_isir + assign $1\sr5__oe$next[0:0]$6011 \sr5_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr5__oe$next[0:0]$5966 1'0 + assign $1\sr5__oe$next[0:0]$6011 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5__oe$next[0:0]$5967 1'0 + assign $2\sr5__oe$next[0:0]$6012 1'0 case - assign $2\sr5__oe$next[0:0]$5967 $1\sr5__oe$next[0:0]$5966 + assign $2\sr5__oe$next[0:0]$6012 $1\sr5__oe$next[0:0]$6011 end sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$5965 + update \sr5__oe$next $0\sr5__oe$next[0:0]$6010 end - attribute \src "libresoc.v:136277.3-136297.6" - process $proc$libresoc.v:136277$5968 + attribute \src "libresoc.v:138059.3-138079.6" + process $proc$libresoc.v:138059$6013 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr5_reg$next[2:0]$5969 $3\sr5_reg$next[2:0]$5972 - attribute \src "libresoc.v:136278.5-136278.29" + assign $0\sr5_reg$next[2:0]$6014 $3\sr5_reg$next[2:0]$6017 + attribute \src "libresoc.v:138060.5-138060.29" switch \initial - attribute \src "libresoc.v:136278.9-136278.17" + attribute \src "libresoc.v:138060.9-138060.17" case 1'1 case end @@ -218512,38 +221007,38 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_reg$next[2:0]$5970 { \TAP_bus__tdi \sr5_reg [2:1] } + assign $1\sr5_reg$next[2:0]$6015 { \TAP_bus__tdi \sr5_reg [2:1] } case - assign $1\sr5_reg$next[2:0]$5970 \sr5_reg + assign $1\sr5_reg$next[2:0]$6015 \sr5_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr5_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5_reg$next[2:0]$5971 \sr5__i + assign $2\sr5_reg$next[2:0]$6016 \sr5__i case - assign $2\sr5_reg$next[2:0]$5971 $1\sr5_reg$next[2:0]$5970 + assign $2\sr5_reg$next[2:0]$6016 $1\sr5_reg$next[2:0]$6015 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr5_reg$next[2:0]$5972 3'000 + assign $3\sr5_reg$next[2:0]$6017 3'000 case - assign $3\sr5_reg$next[2:0]$5972 $2\sr5_reg$next[2:0]$5971 + assign $3\sr5_reg$next[2:0]$6017 $2\sr5_reg$next[2:0]$6016 end sync always - update \sr5_reg$next $0\sr5_reg$next[2:0]$5969 + update \sr5_reg$next $0\sr5_reg$next[2:0]$6014 end - attribute \src "libresoc.v:136298.3-136324.6" - process $proc$libresoc.v:136298$5973 + attribute \src "libresoc.v:138080.3-138106.6" + process $proc$libresoc.v:138080$6018 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:136299.5-136299.29" + attribute \src "libresoc.v:138081.5-138081.29" switch \initial - attribute \src "libresoc.v:136299.9-136299.17" + attribute \src "libresoc.v:138081.9-138081.17" case 1'1 case end @@ -218581,15 +221076,15 @@ module \jtag sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "libresoc.v:136325.3-136357.6" - process $proc$libresoc.v:136325$5974 + attribute \src "libresoc.v:138107.3-138139.6" + process $proc$libresoc.v:138107$6019 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__adr$next[28:0]$5975 $4\jtag_wb__adr$next[28:0]$5979 - attribute \src "libresoc.v:136326.5-136326.29" + assign $0\jtag_wb__adr$next[28:0]$6020 $4\jtag_wb__adr$next[28:0]$6024 + attribute \src "libresoc.v:138108.5-138108.29" switch \initial - attribute \src "libresoc.v:136326.9-136326.17" + attribute \src "libresoc.v:138108.9-138108.17" case 1'1 case end @@ -218598,57 +221093,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$5976 $2\jtag_wb__adr$next[28:0]$5977 + assign $1\jtag_wb__adr$next[28:0]$6021 $2\jtag_wb__adr$next[28:0]$6022 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\jtag_wb__adr$next[28:0]$5977 \jtag_wb_addrsr__o + assign $2\jtag_wb__adr$next[28:0]$6022 \jtag_wb_addrsr__o attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\jtag_wb__adr$next[28:0]$5977 \$495 [28:0] + assign $2\jtag_wb__adr$next[28:0]$6022 \$495 [28:0] case - assign $2\jtag_wb__adr$next[28:0]$5977 \jtag_wb__adr + assign $2\jtag_wb__adr$next[28:0]$6022 \jtag_wb__adr end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$5976 $3\jtag_wb__adr$next[28:0]$5978 + assign $1\jtag_wb__adr$next[28:0]$6021 $3\jtag_wb__adr$next[28:0]$6023 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__adr$next[28:0]$5978 \$498 [28:0] + assign $3\jtag_wb__adr$next[28:0]$6023 \$498 [28:0] case - assign $3\jtag_wb__adr$next[28:0]$5978 \jtag_wb__adr + assign $3\jtag_wb__adr$next[28:0]$6023 \jtag_wb__adr end case - assign $1\jtag_wb__adr$next[28:0]$5976 \jtag_wb__adr + assign $1\jtag_wb__adr$next[28:0]$6021 \jtag_wb__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\jtag_wb__adr$next[28:0]$5979 29'00000000000000000000000000000 + assign $4\jtag_wb__adr$next[28:0]$6024 29'00000000000000000000000000000 case - assign $4\jtag_wb__adr$next[28:0]$5979 $1\jtag_wb__adr$next[28:0]$5976 + assign $4\jtag_wb__adr$next[28:0]$6024 $1\jtag_wb__adr$next[28:0]$6021 end sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$5975 + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6020 end - attribute \src "libresoc.v:136358.3-136410.6" - process $proc$libresoc.v:136358$5980 + attribute \src "libresoc.v:138140.3-138192.6" + process $proc$libresoc.v:138140$6025 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[2:0]$5981 $5\fsm_state$next[2:0]$5986 - attribute \src "libresoc.v:136359.5-136359.29" + assign $0\fsm_state$next[2:0]$6026 $5\fsm_state$next[2:0]$6031 + attribute \src "libresoc.v:138141.5-138141.29" switch \initial - attribute \src "libresoc.v:136359.9-136359.17" + attribute \src "libresoc.v:138141.9-138141.17" case 1'1 case end @@ -218657,82 +221152,82 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$next[2:0]$5982 $2\fsm_state$next[2:0]$5983 + assign $1\fsm_state$next[2:0]$6027 $2\fsm_state$next[2:0]$6028 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$next[2:0]$5983 3'001 + assign $2\fsm_state$next[2:0]$6028 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$next[2:0]$5983 3'001 + assign $2\fsm_state$next[2:0]$6028 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$next[2:0]$5983 3'010 + assign $2\fsm_state$next[2:0]$6028 3'010 case - assign $2\fsm_state$next[2:0]$5983 \fsm_state + assign $2\fsm_state$next[2:0]$6028 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$next[2:0]$5982 3'011 + assign $1\fsm_state$next[2:0]$6027 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$next[2:0]$5982 $3\fsm_state$next[2:0]$5984 + assign $1\fsm_state$next[2:0]$6027 $3\fsm_state$next[2:0]$6029 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[2:0]$5984 3'000 + assign $3\fsm_state$next[2:0]$6029 3'000 case - assign $3\fsm_state$next[2:0]$5984 \fsm_state + assign $3\fsm_state$next[2:0]$6029 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$next[2:0]$5982 3'100 + assign $1\fsm_state$next[2:0]$6027 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$next[2:0]$5982 $4\fsm_state$next[2:0]$5985 + assign $1\fsm_state$next[2:0]$6027 $4\fsm_state$next[2:0]$6030 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[2:0]$5985 3'001 + assign $4\fsm_state$next[2:0]$6030 3'001 case - assign $4\fsm_state$next[2:0]$5985 \fsm_state + assign $4\fsm_state$next[2:0]$6030 \fsm_state end case - assign $1\fsm_state$next[2:0]$5982 \fsm_state + assign $1\fsm_state$next[2:0]$6027 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$5986 3'000 + assign $5\fsm_state$next[2:0]$6031 3'000 case - assign $5\fsm_state$next[2:0]$5986 $1\fsm_state$next[2:0]$5982 + assign $5\fsm_state$next[2:0]$6031 $1\fsm_state$next[2:0]$6027 end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$5981 + update \fsm_state$next $0\fsm_state$next[2:0]$6026 end - attribute \src "libresoc.v:136411.3-136437.6" - process $proc$libresoc.v:136411$5987 + attribute \src "libresoc.v:138193.3-138219.6" + process $proc$libresoc.v:138193$6032 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$5988 $3\jtag_wb__dat_w$next[63:0]$5991 - attribute \src "libresoc.v:136412.5-136412.29" + assign $0\jtag_wb__dat_w$next[63:0]$6033 $3\jtag_wb__dat_w$next[63:0]$6036 + attribute \src "libresoc.v:138194.5-138194.29" switch \initial - attribute \src "libresoc.v:136412.9-136412.17" + attribute \src "libresoc.v:138194.9-138194.17" case 1'1 case end @@ -218741,46 +221236,46 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$5989 $2\jtag_wb__dat_w$next[63:0]$5990 + assign $1\jtag_wb__dat_w$next[63:0]$6034 $2\jtag_wb__dat_w$next[63:0]$6035 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$5990 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$5990 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$5990 \jtag_wb_datasr__o + assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb_datasr__o case - assign $2\jtag_wb__dat_w$next[63:0]$5990 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w end case - assign $1\jtag_wb__dat_w$next[63:0]$5989 \jtag_wb__dat_w + assign $1\jtag_wb__dat_w$next[63:0]$6034 \jtag_wb__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$5991 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb__dat_w$next[63:0]$6036 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb__dat_w$next[63:0]$5991 $1\jtag_wb__dat_w$next[63:0]$5989 + assign $3\jtag_wb__dat_w$next[63:0]$6036 $1\jtag_wb__dat_w$next[63:0]$6034 end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$5988 + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6033 end - attribute \src "libresoc.v:136438.3-136458.6" - process $proc$libresoc.v:136438$5992 + attribute \src "libresoc.v:138220.3-138240.6" + process $proc$libresoc.v:138220$6037 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$5993 $3\jtag_wb_datasr__i$next[63:0]$5996 - attribute \src "libresoc.v:136439.5-136439.29" + assign $0\jtag_wb_datasr__i$next[63:0]$6038 $3\jtag_wb_datasr__i$next[63:0]$6041 + attribute \src "libresoc.v:138221.5-138221.29" switch \initial - attribute \src "libresoc.v:136439.9-136439.17" + attribute \src "libresoc.v:138221.9-138221.17" case 1'1 case end @@ -218789,40 +221284,40 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$5994 $2\jtag_wb_datasr__i$next[63:0]$5995 + assign $1\jtag_wb_datasr__i$next[63:0]$6039 $2\jtag_wb_datasr__i$next[63:0]$6040 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$5995 \jtag_wb__dat_r + assign $2\jtag_wb_datasr__i$next[63:0]$6040 \jtag_wb__dat_r case - assign $2\jtag_wb_datasr__i$next[63:0]$5995 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr__i$next[63:0]$6040 \jtag_wb_datasr__i end case - assign $1\jtag_wb_datasr__i$next[63:0]$5994 \jtag_wb_datasr__i + assign $1\jtag_wb_datasr__i$next[63:0]$6039 \jtag_wb_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$5996 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr__i$next[63:0]$6041 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr__i$next[63:0]$5996 $1\jtag_wb_datasr__i$next[63:0]$5994 + assign $3\jtag_wb_datasr__i$next[63:0]$6041 $1\jtag_wb_datasr__i$next[63:0]$6039 end sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$5993 + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6038 end - attribute \src "libresoc.v:136459.3-136491.6" - process $proc$libresoc.v:136459$5997 + attribute \src "libresoc.v:138241.3-138273.6" + process $proc$libresoc.v:138241$6042 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__addr_i$next[3:0]$5998 $4\dmi0__addr_i$next[3:0]$6002 - attribute \src "libresoc.v:136460.5-136460.29" + assign $0\dmi0__addr_i$next[3:0]$6043 $4\dmi0__addr_i$next[3:0]$6047 + attribute \src "libresoc.v:138242.5-138242.29" switch \initial - attribute \src "libresoc.v:136460.9-136460.17" + attribute \src "libresoc.v:138242.9-138242.17" case 1'1 case end @@ -218831,57 +221326,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$5999 $2\dmi0__addr_i$next[3:0]$6000 + assign $1\dmi0__addr_i$next[3:0]$6044 $2\dmi0__addr_i$next[3:0]$6045 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6000 \dmi0_addrsr__o [3:0] + assign $2\dmi0__addr_i$next[3:0]$6045 \dmi0_addrsr__o [3:0] attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6000 \$512 [3:0] + assign $2\dmi0__addr_i$next[3:0]$6045 \$512 [3:0] case - assign $2\dmi0__addr_i$next[3:0]$6000 \dmi0__addr_i + assign $2\dmi0__addr_i$next[3:0]$6045 \dmi0__addr_i end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$5999 $3\dmi0__addr_i$next[3:0]$6001 + assign $1\dmi0__addr_i$next[3:0]$6044 $3\dmi0__addr_i$next[3:0]$6046 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__addr_i$next[3:0]$6001 \$515 [3:0] + assign $3\dmi0__addr_i$next[3:0]$6046 \$515 [3:0] case - assign $3\dmi0__addr_i$next[3:0]$6001 \dmi0__addr_i + assign $3\dmi0__addr_i$next[3:0]$6046 \dmi0__addr_i end case - assign $1\dmi0__addr_i$next[3:0]$5999 \dmi0__addr_i + assign $1\dmi0__addr_i$next[3:0]$6044 \dmi0__addr_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dmi0__addr_i$next[3:0]$6002 4'0000 + assign $4\dmi0__addr_i$next[3:0]$6047 4'0000 case - assign $4\dmi0__addr_i$next[3:0]$6002 $1\dmi0__addr_i$next[3:0]$5999 + assign $4\dmi0__addr_i$next[3:0]$6047 $1\dmi0__addr_i$next[3:0]$6044 end sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$5998 + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6043 end - attribute \src "libresoc.v:136492.3-136544.6" - process $proc$libresoc.v:136492$6003 + attribute \src "libresoc.v:138274.3-138326.6" + process $proc$libresoc.v:138274$6048 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$503$next[2:0]$6004 $5\fsm_state$503$next[2:0]$6009 - attribute \src "libresoc.v:136493.5-136493.29" + assign $0\fsm_state$503$next[2:0]$6049 $5\fsm_state$503$next[2:0]$6054 + attribute \src "libresoc.v:138275.5-138275.29" switch \initial - attribute \src "libresoc.v:136493.9-136493.17" + attribute \src "libresoc.v:138275.9-138275.17" case 1'1 case end @@ -218890,82 +221385,82 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$503$next[2:0]$6005 $2\fsm_state$503$next[2:0]$6006 + assign $1\fsm_state$503$next[2:0]$6050 $2\fsm_state$503$next[2:0]$6051 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$503$next[2:0]$6006 3'001 + assign $2\fsm_state$503$next[2:0]$6051 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$503$next[2:0]$6006 3'001 + assign $2\fsm_state$503$next[2:0]$6051 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$503$next[2:0]$6006 3'010 + assign $2\fsm_state$503$next[2:0]$6051 3'010 case - assign $2\fsm_state$503$next[2:0]$6006 \fsm_state$503 + assign $2\fsm_state$503$next[2:0]$6051 \fsm_state$503 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$503$next[2:0]$6005 3'011 + assign $1\fsm_state$503$next[2:0]$6050 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$503$next[2:0]$6005 $3\fsm_state$503$next[2:0]$6007 + assign $1\fsm_state$503$next[2:0]$6050 $3\fsm_state$503$next[2:0]$6052 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$503$next[2:0]$6007 3'000 + assign $3\fsm_state$503$next[2:0]$6052 3'000 case - assign $3\fsm_state$503$next[2:0]$6007 \fsm_state$503 + assign $3\fsm_state$503$next[2:0]$6052 \fsm_state$503 end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$503$next[2:0]$6005 3'100 + assign $1\fsm_state$503$next[2:0]$6050 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$503$next[2:0]$6005 $4\fsm_state$503$next[2:0]$6008 + assign $1\fsm_state$503$next[2:0]$6050 $4\fsm_state$503$next[2:0]$6053 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$503$next[2:0]$6008 3'001 + assign $4\fsm_state$503$next[2:0]$6053 3'001 case - assign $4\fsm_state$503$next[2:0]$6008 \fsm_state$503 + assign $4\fsm_state$503$next[2:0]$6053 \fsm_state$503 end case - assign $1\fsm_state$503$next[2:0]$6005 \fsm_state$503 + assign $1\fsm_state$503$next[2:0]$6050 \fsm_state$503 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$503$next[2:0]$6009 3'000 + assign $5\fsm_state$503$next[2:0]$6054 3'000 case - assign $5\fsm_state$503$next[2:0]$6009 $1\fsm_state$503$next[2:0]$6005 + assign $5\fsm_state$503$next[2:0]$6054 $1\fsm_state$503$next[2:0]$6050 end sync always - update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6004 + update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6049 end - attribute \src "libresoc.v:136545.3-136571.6" - process $proc$libresoc.v:136545$6010 + attribute \src "libresoc.v:138327.3-138353.6" + process $proc$libresoc.v:138327$6055 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__din$next[63:0]$6011 $3\dmi0__din$next[63:0]$6014 - attribute \src "libresoc.v:136546.5-136546.29" + assign $0\dmi0__din$next[63:0]$6056 $3\dmi0__din$next[63:0]$6059 + attribute \src "libresoc.v:138328.5-138328.29" switch \initial - attribute \src "libresoc.v:136546.9-136546.17" + attribute \src "libresoc.v:138328.9-138328.17" case 1'1 case end @@ -218974,46 +221469,46 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__din$next[63:0]$6012 $2\dmi0__din$next[63:0]$6013 + assign $1\dmi0__din$next[63:0]$6057 $2\dmi0__din$next[63:0]$6058 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\dmi0__din$next[63:0]$6013 \dmi0__din + assign $2\dmi0__din$next[63:0]$6058 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\dmi0__din$next[63:0]$6013 \dmi0__din + assign $2\dmi0__din$next[63:0]$6058 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\dmi0__din$next[63:0]$6013 \dmi0_datasr__o + assign $2\dmi0__din$next[63:0]$6058 \dmi0_datasr__o case - assign $2\dmi0__din$next[63:0]$6013 \dmi0__din + assign $2\dmi0__din$next[63:0]$6058 \dmi0__din end case - assign $1\dmi0__din$next[63:0]$6012 \dmi0__din + assign $1\dmi0__din$next[63:0]$6057 \dmi0__din end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__din$next[63:0]$6014 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0__din$next[63:0]$6059 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0__din$next[63:0]$6014 $1\dmi0__din$next[63:0]$6012 + assign $3\dmi0__din$next[63:0]$6059 $1\dmi0__din$next[63:0]$6057 end sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$6011 + update \dmi0__din$next $0\dmi0__din$next[63:0]$6056 end - attribute \src "libresoc.v:136572.3-136592.6" - process $proc$libresoc.v:136572$6015 + attribute \src "libresoc.v:138354.3-138374.6" + process $proc$libresoc.v:138354$6060 assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$6016 $3\dmi0_datasr__i$next[63:0]$6019 - attribute \src "libresoc.v:136573.5-136573.29" + assign $0\dmi0_datasr__i$next[63:0]$6061 $3\dmi0_datasr__i$next[63:0]$6064 + attribute \src "libresoc.v:138355.5-138355.29" switch \initial - attribute \src "libresoc.v:136573.9-136573.17" + attribute \src "libresoc.v:138355.9-138355.17" case 1'1 case end @@ -219022,33 +221517,33 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$6017 $2\dmi0_datasr__i$next[63:0]$6018 + assign $1\dmi0_datasr__i$next[63:0]$6062 $2\dmi0_datasr__i$next[63:0]$6063 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$6018 \dmi0__dout + assign $2\dmi0_datasr__i$next[63:0]$6063 \dmi0__dout case - assign $2\dmi0_datasr__i$next[63:0]$6018 \dmi0_datasr__i + assign $2\dmi0_datasr__i$next[63:0]$6063 \dmi0_datasr__i end case - assign $1\dmi0_datasr__i$next[63:0]$6017 \dmi0_datasr__i + assign $1\dmi0_datasr__i$next[63:0]$6062 \dmi0_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$6019 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr__i$next[63:0]$6064 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr__i$next[63:0]$6019 $1\dmi0_datasr__i$next[63:0]$6017 + assign $3\dmi0_datasr__i$next[63:0]$6064 $1\dmi0_datasr__i$next[63:0]$6062 end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6016 + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6061 end - attribute \src "libresoc.v:136593.3-136613.6" - process $proc$libresoc.v:136593$6020 + attribute \src "libresoc.v:138375.3-138395.6" + process $proc$libresoc.v:138375$6065 assign { } { } assign { } { } assign { } { } @@ -219058,12 +221553,12 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $0\wb_dcache_en$next[0:0]$6021 $2\wb_dcache_en$next[0:0]$6027 - assign $0\wb_icache_en$next[0:0]$6022 $2\wb_icache_en$next[0:0]$6028 - assign $0\wb_sram_en$next[0:0]$6023 $2\wb_sram_en$next[0:0]$6029 - attribute \src "libresoc.v:136594.5-136594.29" + assign $0\wb_dcache_en$next[0:0]$6066 $2\wb_dcache_en$next[0:0]$6072 + assign $0\wb_icache_en$next[0:0]$6067 $2\wb_icache_en$next[0:0]$6073 + assign $0\wb_sram_en$next[0:0]$6068 $2\wb_sram_en$next[0:0]$6074 + attribute \src "libresoc.v:138376.5-138376.29" switch \initial - attribute \src "libresoc.v:136594.9-136594.17" + attribute \src "libresoc.v:138376.9-138376.17" case 1'1 case end @@ -219074,11 +221569,11 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign { $1\wb_sram_en$next[0:0]$6026 $1\wb_dcache_en$next[0:0]$6024 $1\wb_icache_en$next[0:0]$6025 } \sr5__o + assign { $1\wb_sram_en$next[0:0]$6071 $1\wb_dcache_en$next[0:0]$6069 $1\wb_icache_en$next[0:0]$6070 } \sr5__o case - assign $1\wb_dcache_en$next[0:0]$6024 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$6025 \wb_icache_en - assign $1\wb_sram_en$next[0:0]$6026 \wb_sram_en + assign $1\wb_dcache_en$next[0:0]$6069 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6070 \wb_icache_en + assign $1\wb_sram_en$next[0:0]$6071 \wb_sram_en end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -219087,27 +221582,27 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $2\wb_icache_en$next[0:0]$6028 1'1 - assign $2\wb_dcache_en$next[0:0]$6027 1'1 - assign $2\wb_sram_en$next[0:0]$6029 1'1 + assign $2\wb_icache_en$next[0:0]$6073 1'1 + assign $2\wb_dcache_en$next[0:0]$6072 1'1 + assign $2\wb_sram_en$next[0:0]$6074 1'1 case - assign $2\wb_dcache_en$next[0:0]$6027 $1\wb_dcache_en$next[0:0]$6024 - assign $2\wb_icache_en$next[0:0]$6028 $1\wb_icache_en$next[0:0]$6025 - assign $2\wb_sram_en$next[0:0]$6029 $1\wb_sram_en$next[0:0]$6026 + assign $2\wb_dcache_en$next[0:0]$6072 $1\wb_dcache_en$next[0:0]$6069 + assign $2\wb_icache_en$next[0:0]$6073 $1\wb_icache_en$next[0:0]$6070 + assign $2\wb_sram_en$next[0:0]$6074 $1\wb_sram_en$next[0:0]$6071 end sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6021 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6022 - update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6023 + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6066 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6067 + update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6068 end - attribute \src "libresoc.v:136614.3-136623.6" - process $proc$libresoc.v:136614$6030 + attribute \src "libresoc.v:138396.3-138405.6" + process $proc$libresoc.v:138396$6075 assign { } { } assign { } { } assign $0\sr5__i[2:0] $1\sr5__i[2:0] - attribute \src "libresoc.v:136615.5-136615.29" + attribute \src "libresoc.v:138397.5-138397.29" switch \initial - attribute \src "libresoc.v:136615.9-136615.17" + attribute \src "libresoc.v:138397.9-138397.17" case 1'1 case end @@ -219123,15 +221618,15 @@ module \jtag sync always update \sr5__i $0\sr5__i[2:0] end - attribute \src "libresoc.v:136624.3-136641.6" - process $proc$libresoc.v:136624$6031 + attribute \src "libresoc.v:138406.3-138423.6" + process $proc$libresoc.v:138406$6076 assign { } { } assign { } { } assign { } { } - assign $0\io_sr$next[153:0]$6032 $2\io_sr$next[153:0]$6034 - attribute \src "libresoc.v:136625.5-136625.29" + assign $0\io_sr$next[153:0]$6077 $2\io_sr$next[153:0]$6079 + attribute \src "libresoc.v:138407.5-138407.29" switch \initial - attribute \src "libresoc.v:136625.9-136625.17" + attribute \src "libresoc.v:138407.9-138407.17" case 1'1 case end @@ -219140,35 +221635,35 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $1\io_sr$next[153:0]$6033 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign $1\io_sr$next[153:0]$6078 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $1\io_sr$next[153:0]$6033 { \io_sr [152:0] \TAP_bus__tdi } + assign $1\io_sr$next[153:0]$6078 { \io_sr [152:0] \TAP_bus__tdi } case - assign $1\io_sr$next[153:0]$6033 \io_sr + assign $1\io_sr$next[153:0]$6078 \io_sr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[153:0]$6034 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\io_sr$next[153:0]$6079 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\io_sr$next[153:0]$6034 $1\io_sr$next[153:0]$6033 + assign $2\io_sr$next[153:0]$6079 $1\io_sr$next[153:0]$6078 end sync always - update \io_sr$next $0\io_sr$next[153:0]$6032 + update \io_sr$next $0\io_sr$next[153:0]$6077 end - attribute \src "libresoc.v:136642.3-136662.6" - process $proc$libresoc.v:136642$6035 + attribute \src "libresoc.v:138424.3-138444.6" + process $proc$libresoc.v:138424$6080 assign { } { } assign { } { } assign { } { } - assign $0\io_bd$next[153:0]$6036 $2\io_bd$next[153:0]$6038 - attribute \src "libresoc.v:136643.5-136643.29" + assign $0\io_bd$next[153:0]$6081 $2\io_bd$next[153:0]$6083 + attribute \src "libresoc.v:138425.5-138425.29" switch \initial - attribute \src "libresoc.v:136643.9-136643.17" + attribute \src "libresoc.v:138425.9-138425.17" case 1'1 case end @@ -219176,285 +221671,285 @@ module \jtag switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $1\io_bd$next[153:0]$6037 \io_bd + assign $1\io_bd$next[153:0]$6082 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $1\io_bd$next[153:0]$6037 \io_bd + assign $1\io_bd$next[153:0]$6082 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\io_bd$next[153:0]$6037 \io_sr + assign $1\io_bd$next[153:0]$6082 \io_sr case - assign $1\io_bd$next[153:0]$6037 \io_bd + assign $1\io_bd$next[153:0]$6082 \io_bd end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \negjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_bd$next[153:0]$6038 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[153:0]$6038 $1\io_bd$next[153:0]$6037 - end - sync always - update \io_bd$next $0\io_bd$next[153:0]$6036 - end - connect \$9 $eq$libresoc.v:135581$5587_Y - connect \$99 $ternary$libresoc.v:135582$5588_Y - connect \$101 $ternary$libresoc.v:135583$5589_Y - connect \$103 $ternary$libresoc.v:135584$5590_Y - connect \$105 $ternary$libresoc.v:135585$5591_Y - connect \$107 $ternary$libresoc.v:135586$5592_Y - connect \$109 $ternary$libresoc.v:135587$5593_Y - connect \$111 $ternary$libresoc.v:135588$5594_Y - connect \$113 $ternary$libresoc.v:135589$5595_Y - connect \$115 $ternary$libresoc.v:135590$5596_Y - connect \$117 $ternary$libresoc.v:135591$5597_Y - connect \$11 $eq$libresoc.v:135592$5598_Y - connect \$119 $ternary$libresoc.v:135593$5599_Y - connect \$121 $ternary$libresoc.v:135594$5600_Y - connect \$123 $ternary$libresoc.v:135595$5601_Y - connect \$125 $ternary$libresoc.v:135596$5602_Y - connect \$127 $ternary$libresoc.v:135597$5603_Y - connect \$129 $ternary$libresoc.v:135598$5604_Y - connect \$131 $ternary$libresoc.v:135599$5605_Y - connect \$133 $ternary$libresoc.v:135600$5606_Y - connect \$135 $ternary$libresoc.v:135601$5607_Y - connect \$137 $ternary$libresoc.v:135602$5608_Y - connect \$13 $eq$libresoc.v:135603$5609_Y - connect \$139 $ternary$libresoc.v:135604$5610_Y - connect \$141 $ternary$libresoc.v:135605$5611_Y - connect \$143 $ternary$libresoc.v:135606$5612_Y - connect \$145 $ternary$libresoc.v:135607$5613_Y - connect \$147 $ternary$libresoc.v:135608$5614_Y - connect \$149 $ternary$libresoc.v:135609$5615_Y - connect \$151 $ternary$libresoc.v:135610$5616_Y - connect \$153 $ternary$libresoc.v:135611$5617_Y - connect \$155 $ternary$libresoc.v:135612$5618_Y - connect \$157 $ternary$libresoc.v:135613$5619_Y - connect \$15 $or$libresoc.v:135614$5620_Y - connect \$159 $ternary$libresoc.v:135615$5621_Y - connect \$161 $ternary$libresoc.v:135616$5622_Y - connect \$163 $ternary$libresoc.v:135617$5623_Y - connect \$165 $ternary$libresoc.v:135618$5624_Y - connect \$167 $ternary$libresoc.v:135619$5625_Y - connect \$169 $ternary$libresoc.v:135620$5626_Y - connect \$171 $ternary$libresoc.v:135621$5627_Y - connect \$173 $ternary$libresoc.v:135622$5628_Y - connect \$175 $ternary$libresoc.v:135623$5629_Y - connect \$177 $ternary$libresoc.v:135624$5630_Y - connect \$17 $and$libresoc.v:135625$5631_Y - connect \$179 $ternary$libresoc.v:135626$5632_Y - connect \$181 $ternary$libresoc.v:135627$5633_Y - connect \$183 $ternary$libresoc.v:135628$5634_Y - connect \$185 $ternary$libresoc.v:135629$5635_Y - connect \$187 $ternary$libresoc.v:135630$5636_Y - connect \$189 $ternary$libresoc.v:135631$5637_Y - connect \$191 $ternary$libresoc.v:135632$5638_Y - connect \$193 $ternary$libresoc.v:135633$5639_Y - connect \$195 $ternary$libresoc.v:135634$5640_Y - connect \$197 $ternary$libresoc.v:135635$5641_Y - connect \$1 $eq$libresoc.v:135636$5642_Y - connect \$19 $eq$libresoc.v:135637$5643_Y - connect \$199 $ternary$libresoc.v:135638$5644_Y - connect \$201 $ternary$libresoc.v:135639$5645_Y - connect \$203 $ternary$libresoc.v:135640$5646_Y - connect \$205 $ternary$libresoc.v:135641$5647_Y - connect \$207 $ternary$libresoc.v:135642$5648_Y - connect \$209 $ternary$libresoc.v:135643$5649_Y - connect \$211 $ternary$libresoc.v:135644$5650_Y - connect \$213 $ternary$libresoc.v:135645$5651_Y - connect \$215 $ternary$libresoc.v:135646$5652_Y - connect \$217 $ternary$libresoc.v:135647$5653_Y - connect \$21 $eq$libresoc.v:135648$5654_Y - connect \$219 $ternary$libresoc.v:135649$5655_Y - connect \$221 $ternary$libresoc.v:135650$5656_Y - connect \$223 $ternary$libresoc.v:135651$5657_Y - connect \$225 $ternary$libresoc.v:135652$5658_Y - connect \$227 $ternary$libresoc.v:135653$5659_Y - connect \$229 $ternary$libresoc.v:135654$5660_Y - connect \$231 $ternary$libresoc.v:135655$5661_Y - connect \$233 $ternary$libresoc.v:135656$5662_Y - connect \$235 $ternary$libresoc.v:135657$5663_Y - connect \$237 $ternary$libresoc.v:135658$5664_Y - connect \$23 $or$libresoc.v:135659$5665_Y - connect \$239 $ternary$libresoc.v:135660$5666_Y - connect \$241 $ternary$libresoc.v:135661$5667_Y - connect \$243 $ternary$libresoc.v:135662$5668_Y - connect \$245 $ternary$libresoc.v:135663$5669_Y - connect \$247 $ternary$libresoc.v:135664$5670_Y - connect \$249 $ternary$libresoc.v:135665$5671_Y - connect \$251 $ternary$libresoc.v:135666$5672_Y - connect \$253 $ternary$libresoc.v:135667$5673_Y - connect \$255 $ternary$libresoc.v:135668$5674_Y - connect \$257 $ternary$libresoc.v:135669$5675_Y - connect \$25 $eq$libresoc.v:135670$5676_Y - connect \$259 $ternary$libresoc.v:135671$5677_Y - connect \$261 $ternary$libresoc.v:135672$5678_Y - connect \$263 $ternary$libresoc.v:135673$5679_Y - connect \$265 $ternary$libresoc.v:135674$5680_Y - connect \$267 $ternary$libresoc.v:135675$5681_Y - connect \$269 $ternary$libresoc.v:135676$5682_Y - connect \$271 $ternary$libresoc.v:135677$5683_Y - connect \$273 $ternary$libresoc.v:135678$5684_Y - connect \$275 $ternary$libresoc.v:135679$5685_Y - connect \$277 $ternary$libresoc.v:135680$5686_Y - connect \$27 $or$libresoc.v:135681$5687_Y - connect \$279 $ternary$libresoc.v:135682$5688_Y - connect \$281 $ternary$libresoc.v:135683$5689_Y - connect \$283 $ternary$libresoc.v:135684$5690_Y - connect \$285 $ternary$libresoc.v:135685$5691_Y - connect \$287 $ternary$libresoc.v:135686$5692_Y - connect \$289 $ternary$libresoc.v:135687$5693_Y - connect \$291 $ternary$libresoc.v:135688$5694_Y - connect \$293 $ternary$libresoc.v:135689$5695_Y - connect \$295 $ternary$libresoc.v:135690$5696_Y - connect \$297 $ternary$libresoc.v:135691$5697_Y - connect \$29 $and$libresoc.v:135692$5698_Y - connect \$299 $ternary$libresoc.v:135693$5699_Y - connect \$301 $ternary$libresoc.v:135694$5700_Y - connect \$303 $ternary$libresoc.v:135695$5701_Y - connect \$305 $ternary$libresoc.v:135696$5702_Y - connect \$307 $ternary$libresoc.v:135697$5703_Y - connect \$309 $ternary$libresoc.v:135698$5704_Y - connect \$311 $ternary$libresoc.v:135699$5705_Y - connect \$313 $ternary$libresoc.v:135700$5706_Y - connect \$315 $ternary$libresoc.v:135701$5707_Y - connect \$317 $ternary$libresoc.v:135702$5708_Y - connect \$31 $and$libresoc.v:135703$5709_Y - connect \$319 $ternary$libresoc.v:135704$5710_Y - connect \$321 $ternary$libresoc.v:135705$5711_Y - connect \$323 $ternary$libresoc.v:135706$5712_Y - connect \$325 $ternary$libresoc.v:135707$5713_Y - connect \$327 $ternary$libresoc.v:135708$5714_Y - connect \$329 $ternary$libresoc.v:135709$5715_Y - connect \$331 $ternary$libresoc.v:135710$5716_Y - connect \$333 $ternary$libresoc.v:135711$5717_Y - connect \$335 $ternary$libresoc.v:135712$5718_Y - connect \$337 $ternary$libresoc.v:135713$5719_Y - connect \$33 $eq$libresoc.v:135714$5720_Y - connect \$339 $ternary$libresoc.v:135715$5721_Y - connect \$341 $ternary$libresoc.v:135716$5722_Y - connect \$343 $ternary$libresoc.v:135717$5723_Y - connect \$345 $ternary$libresoc.v:135718$5724_Y - connect \$347 $ternary$libresoc.v:135719$5725_Y - connect \$349 $ternary$libresoc.v:135720$5726_Y - connect \$351 $ternary$libresoc.v:135721$5727_Y - connect \$353 $ternary$libresoc.v:135722$5728_Y - connect \$355 $ternary$libresoc.v:135723$5729_Y - connect \$357 $ternary$libresoc.v:135724$5730_Y - connect \$35 $eq$libresoc.v:135725$5731_Y - connect \$359 $eq$libresoc.v:135726$5732_Y - connect \$361 $eq$libresoc.v:135727$5733_Y - connect \$363 $or$libresoc.v:135728$5734_Y - connect \$365 $eq$libresoc.v:135729$5735_Y - connect \$367 $or$libresoc.v:135730$5736_Y - connect \$369 $and$libresoc.v:135731$5737_Y - connect \$371 $eq$libresoc.v:135732$5738_Y - connect \$373 $ne$libresoc.v:135733$5739_Y - connect \$375 $and$libresoc.v:135734$5740_Y - connect \$377 $ne$libresoc.v:135735$5741_Y - connect \$37 $or$libresoc.v:135736$5742_Y - connect \$379 $and$libresoc.v:135737$5743_Y - connect \$381 $ne$libresoc.v:135738$5744_Y - connect \$383 $and$libresoc.v:135739$5745_Y - connect \$385 $not$libresoc.v:135740$5746_Y - connect \$387 $and$libresoc.v:135741$5747_Y - connect \$389 $eq$libresoc.v:135742$5748_Y - connect \$391 $ne$libresoc.v:135743$5749_Y - connect \$393 $and$libresoc.v:135744$5750_Y - connect \$395 $ne$libresoc.v:135745$5751_Y - connect \$397 $and$libresoc.v:135746$5752_Y - connect \$3 $eq$libresoc.v:135747$5753_Y - connect \$39 $eq$libresoc.v:135748$5754_Y - connect \$399 $ne$libresoc.v:135749$5755_Y - connect \$401 $and$libresoc.v:135750$5756_Y - connect \$403 $not$libresoc.v:135751$5757_Y - connect \$405 $and$libresoc.v:135752$5758_Y - connect \$407 $eq$libresoc.v:135753$5759_Y - connect \$409 $eq$libresoc.v:135754$5760_Y - connect \$411 $ne$libresoc.v:135755$5761_Y - connect \$413 $and$libresoc.v:135756$5762_Y - connect \$415 $ne$libresoc.v:135757$5763_Y - connect \$417 $and$libresoc.v:135758$5764_Y - connect \$41 $or$libresoc.v:135759$5765_Y - connect \$419 $ne$libresoc.v:135760$5766_Y - connect \$421 $and$libresoc.v:135761$5767_Y - connect \$423 $not$libresoc.v:135762$5768_Y - connect \$425 $and$libresoc.v:135763$5769_Y - connect \$427 $eq$libresoc.v:135764$5770_Y - connect \$429 $ne$libresoc.v:135765$5771_Y - connect \$431 $and$libresoc.v:135766$5772_Y - connect \$433 $ne$libresoc.v:135767$5773_Y - connect \$435 $and$libresoc.v:135768$5774_Y - connect \$437 $ne$libresoc.v:135769$5775_Y - connect \$43 $and$libresoc.v:135770$5776_Y - connect \$439 $and$libresoc.v:135771$5777_Y - connect \$441 $not$libresoc.v:135772$5778_Y - connect \$443 $and$libresoc.v:135773$5779_Y - connect \$445 $eq$libresoc.v:135774$5780_Y - connect \$447 $eq$libresoc.v:135775$5781_Y - connect \$449 $ne$libresoc.v:135776$5782_Y - connect \$451 $and$libresoc.v:135777$5783_Y - connect \$453 $ne$libresoc.v:135778$5784_Y - connect \$455 $and$libresoc.v:135779$5785_Y - connect \$457 $ne$libresoc.v:135780$5786_Y - connect \$45 $and$libresoc.v:135781$5787_Y - connect \$459 $and$libresoc.v:135782$5788_Y - connect \$461 $not$libresoc.v:135783$5789_Y - connect \$463 $and$libresoc.v:135784$5790_Y - connect \$465 $eq$libresoc.v:135785$5791_Y - connect \$467 $ne$libresoc.v:135786$5792_Y - connect \$469 $and$libresoc.v:135787$5793_Y - connect \$471 $ne$libresoc.v:135788$5794_Y - connect \$473 $and$libresoc.v:135789$5795_Y - connect \$475 $ne$libresoc.v:135790$5796_Y - connect \$477 $and$libresoc.v:135791$5797_Y - connect \$47 $eq$libresoc.v:135792$5798_Y - connect \$479 $not$libresoc.v:135793$5799_Y - connect \$481 $and$libresoc.v:135794$5800_Y - connect \$484 $eq$libresoc.v:135795$5801_Y - connect \$483 $not$libresoc.v:135796$5802_Y - connect \$487 $eq$libresoc.v:135797$5803_Y - connect \$489 $eq$libresoc.v:135798$5804_Y - connect \$491 $or$libresoc.v:135799$5805_Y - connect \$493 $eq$libresoc.v:135800$5806_Y - connect \$496 $add$libresoc.v:135801$5807_Y - connect \$49 $eq$libresoc.v:135802$5808_Y - connect \$499 $add$libresoc.v:135803$5809_Y - connect \$501 $pos$libresoc.v:135804$5811_Y - connect \$504 $eq$libresoc.v:135805$5812_Y - connect \$506 $eq$libresoc.v:135806$5813_Y - connect \$508 $or$libresoc.v:135807$5814_Y - connect \$510 $eq$libresoc.v:135808$5815_Y - connect \$513 $add$libresoc.v:135809$5816_Y - connect \$516 $add$libresoc.v:135810$5817_Y - connect \$51 $ternary$libresoc.v:135811$5818_Y - connect \$53 $ternary$libresoc.v:135812$5819_Y - connect \$55 $ternary$libresoc.v:135813$5820_Y - connect \$57 $ternary$libresoc.v:135814$5821_Y - connect \$5 $or$libresoc.v:135815$5822_Y - connect \$59 $ternary$libresoc.v:135816$5823_Y - connect \$61 $ternary$libresoc.v:135817$5824_Y - connect \$63 $ternary$libresoc.v:135818$5825_Y - connect \$65 $ternary$libresoc.v:135819$5826_Y - connect \$67 $ternary$libresoc.v:135820$5827_Y - connect \$69 $ternary$libresoc.v:135821$5828_Y - connect \$71 $ternary$libresoc.v:135822$5829_Y - connect \$73 $ternary$libresoc.v:135823$5830_Y - connect \$75 $ternary$libresoc.v:135824$5831_Y - connect \$77 $ternary$libresoc.v:135825$5832_Y - connect \$7 $and$libresoc.v:135826$5833_Y - connect \$79 $ternary$libresoc.v:135827$5834_Y - connect \$81 $ternary$libresoc.v:135828$5835_Y - connect \$83 $ternary$libresoc.v:135829$5836_Y - connect \$85 $ternary$libresoc.v:135830$5837_Y - connect \$87 $ternary$libresoc.v:135831$5838_Y - connect \$89 $ternary$libresoc.v:135832$5839_Y - connect \$91 $ternary$libresoc.v:135833$5840_Y - connect \$93 $ternary$libresoc.v:135834$5841_Y - connect \$95 $ternary$libresoc.v:135835$5842_Y - connect \$97 $ternary$libresoc.v:135836$5843_Y + assign $2\io_bd$next[153:0]$6083 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[153:0]$6083 $1\io_bd$next[153:0]$6082 + end + sync always + update \io_bd$next $0\io_bd$next[153:0]$6081 + end + connect \$9 $eq$libresoc.v:137363$5632_Y + connect \$99 $ternary$libresoc.v:137364$5633_Y + connect \$101 $ternary$libresoc.v:137365$5634_Y + connect \$103 $ternary$libresoc.v:137366$5635_Y + connect \$105 $ternary$libresoc.v:137367$5636_Y + connect \$107 $ternary$libresoc.v:137368$5637_Y + connect \$109 $ternary$libresoc.v:137369$5638_Y + connect \$111 $ternary$libresoc.v:137370$5639_Y + connect \$113 $ternary$libresoc.v:137371$5640_Y + connect \$115 $ternary$libresoc.v:137372$5641_Y + connect \$117 $ternary$libresoc.v:137373$5642_Y + connect \$11 $eq$libresoc.v:137374$5643_Y + connect \$119 $ternary$libresoc.v:137375$5644_Y + connect \$121 $ternary$libresoc.v:137376$5645_Y + connect \$123 $ternary$libresoc.v:137377$5646_Y + connect \$125 $ternary$libresoc.v:137378$5647_Y + connect \$127 $ternary$libresoc.v:137379$5648_Y + connect \$129 $ternary$libresoc.v:137380$5649_Y + connect \$131 $ternary$libresoc.v:137381$5650_Y + connect \$133 $ternary$libresoc.v:137382$5651_Y + connect \$135 $ternary$libresoc.v:137383$5652_Y + connect \$137 $ternary$libresoc.v:137384$5653_Y + connect \$13 $eq$libresoc.v:137385$5654_Y + connect \$139 $ternary$libresoc.v:137386$5655_Y + connect \$141 $ternary$libresoc.v:137387$5656_Y + connect \$143 $ternary$libresoc.v:137388$5657_Y + connect \$145 $ternary$libresoc.v:137389$5658_Y + connect \$147 $ternary$libresoc.v:137390$5659_Y + connect \$149 $ternary$libresoc.v:137391$5660_Y + connect \$151 $ternary$libresoc.v:137392$5661_Y + connect \$153 $ternary$libresoc.v:137393$5662_Y + connect \$155 $ternary$libresoc.v:137394$5663_Y + connect \$157 $ternary$libresoc.v:137395$5664_Y + connect \$15 $or$libresoc.v:137396$5665_Y + connect \$159 $ternary$libresoc.v:137397$5666_Y + connect \$161 $ternary$libresoc.v:137398$5667_Y + connect \$163 $ternary$libresoc.v:137399$5668_Y + connect \$165 $ternary$libresoc.v:137400$5669_Y + connect \$167 $ternary$libresoc.v:137401$5670_Y + connect \$169 $ternary$libresoc.v:137402$5671_Y + connect \$171 $ternary$libresoc.v:137403$5672_Y + connect \$173 $ternary$libresoc.v:137404$5673_Y + connect \$175 $ternary$libresoc.v:137405$5674_Y + connect \$177 $ternary$libresoc.v:137406$5675_Y + connect \$17 $and$libresoc.v:137407$5676_Y + connect \$179 $ternary$libresoc.v:137408$5677_Y + connect \$181 $ternary$libresoc.v:137409$5678_Y + connect \$183 $ternary$libresoc.v:137410$5679_Y + connect \$185 $ternary$libresoc.v:137411$5680_Y + connect \$187 $ternary$libresoc.v:137412$5681_Y + connect \$189 $ternary$libresoc.v:137413$5682_Y + connect \$191 $ternary$libresoc.v:137414$5683_Y + connect \$193 $ternary$libresoc.v:137415$5684_Y + connect \$195 $ternary$libresoc.v:137416$5685_Y + connect \$197 $ternary$libresoc.v:137417$5686_Y + connect \$1 $eq$libresoc.v:137418$5687_Y + connect \$19 $eq$libresoc.v:137419$5688_Y + connect \$199 $ternary$libresoc.v:137420$5689_Y + connect \$201 $ternary$libresoc.v:137421$5690_Y + connect \$203 $ternary$libresoc.v:137422$5691_Y + connect \$205 $ternary$libresoc.v:137423$5692_Y + connect \$207 $ternary$libresoc.v:137424$5693_Y + connect \$209 $ternary$libresoc.v:137425$5694_Y + connect \$211 $ternary$libresoc.v:137426$5695_Y + connect \$213 $ternary$libresoc.v:137427$5696_Y + connect \$215 $ternary$libresoc.v:137428$5697_Y + connect \$217 $ternary$libresoc.v:137429$5698_Y + connect \$21 $eq$libresoc.v:137430$5699_Y + connect \$219 $ternary$libresoc.v:137431$5700_Y + connect \$221 $ternary$libresoc.v:137432$5701_Y + connect \$223 $ternary$libresoc.v:137433$5702_Y + connect \$225 $ternary$libresoc.v:137434$5703_Y + connect \$227 $ternary$libresoc.v:137435$5704_Y + connect \$229 $ternary$libresoc.v:137436$5705_Y + connect \$231 $ternary$libresoc.v:137437$5706_Y + connect \$233 $ternary$libresoc.v:137438$5707_Y + connect \$235 $ternary$libresoc.v:137439$5708_Y + connect \$237 $ternary$libresoc.v:137440$5709_Y + connect \$23 $or$libresoc.v:137441$5710_Y + connect \$239 $ternary$libresoc.v:137442$5711_Y + connect \$241 $ternary$libresoc.v:137443$5712_Y + connect \$243 $ternary$libresoc.v:137444$5713_Y + connect \$245 $ternary$libresoc.v:137445$5714_Y + connect \$247 $ternary$libresoc.v:137446$5715_Y + connect \$249 $ternary$libresoc.v:137447$5716_Y + connect \$251 $ternary$libresoc.v:137448$5717_Y + connect \$253 $ternary$libresoc.v:137449$5718_Y + connect \$255 $ternary$libresoc.v:137450$5719_Y + connect \$257 $ternary$libresoc.v:137451$5720_Y + connect \$25 $eq$libresoc.v:137452$5721_Y + connect \$259 $ternary$libresoc.v:137453$5722_Y + connect \$261 $ternary$libresoc.v:137454$5723_Y + connect \$263 $ternary$libresoc.v:137455$5724_Y + connect \$265 $ternary$libresoc.v:137456$5725_Y + connect \$267 $ternary$libresoc.v:137457$5726_Y + connect \$269 $ternary$libresoc.v:137458$5727_Y + connect \$271 $ternary$libresoc.v:137459$5728_Y + connect \$273 $ternary$libresoc.v:137460$5729_Y + connect \$275 $ternary$libresoc.v:137461$5730_Y + connect \$277 $ternary$libresoc.v:137462$5731_Y + connect \$27 $or$libresoc.v:137463$5732_Y + connect \$279 $ternary$libresoc.v:137464$5733_Y + connect \$281 $ternary$libresoc.v:137465$5734_Y + connect \$283 $ternary$libresoc.v:137466$5735_Y + connect \$285 $ternary$libresoc.v:137467$5736_Y + connect \$287 $ternary$libresoc.v:137468$5737_Y + connect \$289 $ternary$libresoc.v:137469$5738_Y + connect \$291 $ternary$libresoc.v:137470$5739_Y + connect \$293 $ternary$libresoc.v:137471$5740_Y + connect \$295 $ternary$libresoc.v:137472$5741_Y + connect \$297 $ternary$libresoc.v:137473$5742_Y + connect \$29 $and$libresoc.v:137474$5743_Y + connect \$299 $ternary$libresoc.v:137475$5744_Y + connect \$301 $ternary$libresoc.v:137476$5745_Y + connect \$303 $ternary$libresoc.v:137477$5746_Y + connect \$305 $ternary$libresoc.v:137478$5747_Y + connect \$307 $ternary$libresoc.v:137479$5748_Y + connect \$309 $ternary$libresoc.v:137480$5749_Y + connect \$311 $ternary$libresoc.v:137481$5750_Y + connect \$313 $ternary$libresoc.v:137482$5751_Y + connect \$315 $ternary$libresoc.v:137483$5752_Y + connect \$317 $ternary$libresoc.v:137484$5753_Y + connect \$31 $and$libresoc.v:137485$5754_Y + connect \$319 $ternary$libresoc.v:137486$5755_Y + connect \$321 $ternary$libresoc.v:137487$5756_Y + connect \$323 $ternary$libresoc.v:137488$5757_Y + connect \$325 $ternary$libresoc.v:137489$5758_Y + connect \$327 $ternary$libresoc.v:137490$5759_Y + connect \$329 $ternary$libresoc.v:137491$5760_Y + connect \$331 $ternary$libresoc.v:137492$5761_Y + connect \$333 $ternary$libresoc.v:137493$5762_Y + connect \$335 $ternary$libresoc.v:137494$5763_Y + connect \$337 $ternary$libresoc.v:137495$5764_Y + connect \$33 $eq$libresoc.v:137496$5765_Y + connect \$339 $ternary$libresoc.v:137497$5766_Y + connect \$341 $ternary$libresoc.v:137498$5767_Y + connect \$343 $ternary$libresoc.v:137499$5768_Y + connect \$345 $ternary$libresoc.v:137500$5769_Y + connect \$347 $ternary$libresoc.v:137501$5770_Y + connect \$349 $ternary$libresoc.v:137502$5771_Y + connect \$351 $ternary$libresoc.v:137503$5772_Y + connect \$353 $ternary$libresoc.v:137504$5773_Y + connect \$355 $ternary$libresoc.v:137505$5774_Y + connect \$357 $ternary$libresoc.v:137506$5775_Y + connect \$35 $eq$libresoc.v:137507$5776_Y + connect \$359 $eq$libresoc.v:137508$5777_Y + connect \$361 $eq$libresoc.v:137509$5778_Y + connect \$363 $or$libresoc.v:137510$5779_Y + connect \$365 $eq$libresoc.v:137511$5780_Y + connect \$367 $or$libresoc.v:137512$5781_Y + connect \$369 $and$libresoc.v:137513$5782_Y + connect \$371 $eq$libresoc.v:137514$5783_Y + connect \$373 $ne$libresoc.v:137515$5784_Y + connect \$375 $and$libresoc.v:137516$5785_Y + connect \$377 $ne$libresoc.v:137517$5786_Y + connect \$37 $or$libresoc.v:137518$5787_Y + connect \$379 $and$libresoc.v:137519$5788_Y + connect \$381 $ne$libresoc.v:137520$5789_Y + connect \$383 $and$libresoc.v:137521$5790_Y + connect \$385 $not$libresoc.v:137522$5791_Y + connect \$387 $and$libresoc.v:137523$5792_Y + connect \$389 $eq$libresoc.v:137524$5793_Y + connect \$391 $ne$libresoc.v:137525$5794_Y + connect \$393 $and$libresoc.v:137526$5795_Y + connect \$395 $ne$libresoc.v:137527$5796_Y + connect \$397 $and$libresoc.v:137528$5797_Y + connect \$3 $eq$libresoc.v:137529$5798_Y + connect \$39 $eq$libresoc.v:137530$5799_Y + connect \$399 $ne$libresoc.v:137531$5800_Y + connect \$401 $and$libresoc.v:137532$5801_Y + connect \$403 $not$libresoc.v:137533$5802_Y + connect \$405 $and$libresoc.v:137534$5803_Y + connect \$407 $eq$libresoc.v:137535$5804_Y + connect \$409 $eq$libresoc.v:137536$5805_Y + connect \$411 $ne$libresoc.v:137537$5806_Y + connect \$413 $and$libresoc.v:137538$5807_Y + connect \$415 $ne$libresoc.v:137539$5808_Y + connect \$417 $and$libresoc.v:137540$5809_Y + connect \$41 $or$libresoc.v:137541$5810_Y + connect \$419 $ne$libresoc.v:137542$5811_Y + connect \$421 $and$libresoc.v:137543$5812_Y + connect \$423 $not$libresoc.v:137544$5813_Y + connect \$425 $and$libresoc.v:137545$5814_Y + connect \$427 $eq$libresoc.v:137546$5815_Y + connect \$429 $ne$libresoc.v:137547$5816_Y + connect \$431 $and$libresoc.v:137548$5817_Y + connect \$433 $ne$libresoc.v:137549$5818_Y + connect \$435 $and$libresoc.v:137550$5819_Y + connect \$437 $ne$libresoc.v:137551$5820_Y + connect \$43 $and$libresoc.v:137552$5821_Y + connect \$439 $and$libresoc.v:137553$5822_Y + connect \$441 $not$libresoc.v:137554$5823_Y + connect \$443 $and$libresoc.v:137555$5824_Y + connect \$445 $eq$libresoc.v:137556$5825_Y + connect \$447 $eq$libresoc.v:137557$5826_Y + connect \$449 $ne$libresoc.v:137558$5827_Y + connect \$451 $and$libresoc.v:137559$5828_Y + connect \$453 $ne$libresoc.v:137560$5829_Y + connect \$455 $and$libresoc.v:137561$5830_Y + connect \$457 $ne$libresoc.v:137562$5831_Y + connect \$45 $and$libresoc.v:137563$5832_Y + connect \$459 $and$libresoc.v:137564$5833_Y + connect \$461 $not$libresoc.v:137565$5834_Y + connect \$463 $and$libresoc.v:137566$5835_Y + connect \$465 $eq$libresoc.v:137567$5836_Y + connect \$467 $ne$libresoc.v:137568$5837_Y + connect \$469 $and$libresoc.v:137569$5838_Y + connect \$471 $ne$libresoc.v:137570$5839_Y + connect \$473 $and$libresoc.v:137571$5840_Y + connect \$475 $ne$libresoc.v:137572$5841_Y + connect \$477 $and$libresoc.v:137573$5842_Y + connect \$47 $eq$libresoc.v:137574$5843_Y + connect \$479 $not$libresoc.v:137575$5844_Y + connect \$481 $and$libresoc.v:137576$5845_Y + connect \$484 $eq$libresoc.v:137577$5846_Y + connect \$483 $not$libresoc.v:137578$5847_Y + connect \$487 $eq$libresoc.v:137579$5848_Y + connect \$489 $eq$libresoc.v:137580$5849_Y + connect \$491 $or$libresoc.v:137581$5850_Y + connect \$493 $eq$libresoc.v:137582$5851_Y + connect \$496 $add$libresoc.v:137583$5852_Y + connect \$49 $eq$libresoc.v:137584$5853_Y + connect \$499 $add$libresoc.v:137585$5854_Y + connect \$501 $pos$libresoc.v:137586$5856_Y + connect \$504 $eq$libresoc.v:137587$5857_Y + connect \$506 $eq$libresoc.v:137588$5858_Y + connect \$508 $or$libresoc.v:137589$5859_Y + connect \$510 $eq$libresoc.v:137590$5860_Y + connect \$513 $add$libresoc.v:137591$5861_Y + connect \$516 $add$libresoc.v:137592$5862_Y + connect \$51 $ternary$libresoc.v:137593$5863_Y + connect \$53 $ternary$libresoc.v:137594$5864_Y + connect \$55 $ternary$libresoc.v:137595$5865_Y + connect \$57 $ternary$libresoc.v:137596$5866_Y + connect \$5 $or$libresoc.v:137597$5867_Y + connect \$59 $ternary$libresoc.v:137598$5868_Y + connect \$61 $ternary$libresoc.v:137599$5869_Y + connect \$63 $ternary$libresoc.v:137600$5870_Y + connect \$65 $ternary$libresoc.v:137601$5871_Y + connect \$67 $ternary$libresoc.v:137602$5872_Y + connect \$69 $ternary$libresoc.v:137603$5873_Y + connect \$71 $ternary$libresoc.v:137604$5874_Y + connect \$73 $ternary$libresoc.v:137605$5875_Y + connect \$75 $ternary$libresoc.v:137606$5876_Y + connect \$77 $ternary$libresoc.v:137607$5877_Y + connect \$7 $and$libresoc.v:137608$5878_Y + connect \$79 $ternary$libresoc.v:137609$5879_Y + connect \$81 $ternary$libresoc.v:137610$5880_Y + connect \$83 $ternary$libresoc.v:137611$5881_Y + connect \$85 $ternary$libresoc.v:137612$5882_Y + connect \$87 $ternary$libresoc.v:137613$5883_Y + connect \$89 $ternary$libresoc.v:137614$5884_Y + connect \$91 $ternary$libresoc.v:137615$5885_Y + connect \$93 $ternary$libresoc.v:137616$5886_Y + connect \$95 $ternary$libresoc.v:137617$5887_Y + connect \$97 $ternary$libresoc.v:137618$5888_Y connect \$495 \$496 connect \$498 \$499 connect \$512 \$513 @@ -219661,14 +222156,14 @@ module \jtag connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:136872.1-137061.10" +attribute \src "libresoc.v:138654.1-138843.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 23 \dbus__ack @@ -219771,7 +222266,7 @@ module \l0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:136977.12-137011.4" + attribute \src "libresoc.v:138759.12-138793.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -219808,7 +222303,7 @@ module \l0 connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:137012.9-137034.4" + attribute \src "libresoc.v:138794.9-138816.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -219833,7 +222328,7 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:137035.9-137059.4" + attribute \src "libresoc.v:138817.9-138841.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -219861,145 +222356,145 @@ module \l0 end connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:137065.1-137473.10" +attribute \src "libresoc.v:138847.1-139255.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 - attribute \src "libresoc.v:137328.3-137342.6" - wire $0\idx_l$23$next[0:0]$6117 - attribute \src "libresoc.v:137228.3-137229.35" - wire $0\idx_l$23[0:0]$6084 - attribute \src "libresoc.v:137086.7-137086.24" - wire $0\idx_l$23[0:0]$6139 - attribute \src "libresoc.v:137383.3-137392.6" + attribute \src "libresoc.v:139110.3-139124.6" + wire $0\idx_l$23$next[0:0]$6162 + attribute \src "libresoc.v:139010.3-139011.35" + wire $0\idx_l$23[0:0]$6129 + attribute \src "libresoc.v:138868.7-138868.24" + wire $0\idx_l$23[0:0]$6184 + attribute \src "libresoc.v:139165.3-139174.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:137373.3-137382.6" + attribute \src "libresoc.v:139155.3-139164.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:137066.7-137066.20" + attribute \src "libresoc.v:138848.7-138848.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137249.3-137258.6" - wire width 48 $0\ldst_port0_addr_i$12[47:0]$6086 - attribute \src "libresoc.v:137259.3-137268.6" - wire $0\ldst_port0_addr_i_ok$13[0:0]$6089 - attribute \src "libresoc.v:137301.3-137310.6" + attribute \src "libresoc.v:139031.3-139040.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6131 + attribute \src "libresoc.v:139041.3-139050.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6134 + attribute \src "libresoc.v:139083.3-139092.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:137291.3-137300.6" + attribute \src "libresoc.v:139073.3-139082.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:137363.3-137372.6" + attribute \src "libresoc.v:139145.3-139154.6" wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:137438.3-137447.6" - wire width 4 $0\ldst_port0_data_len$11[3:0]$6134 - attribute \src "libresoc.v:137311.3-137327.6" - wire $0\ldst_port0_exc_$signal$1[0:0]$6101 - attribute \src "libresoc.v:137311.3-137327.6" - wire $0\ldst_port0_exc_$signal$2[0:0]$6102 - attribute \src "libresoc.v:137311.3-137327.6" - wire $0\ldst_port0_exc_$signal$3[0:0]$6103 - attribute \src "libresoc.v:137311.3-137327.6" - wire $0\ldst_port0_exc_$signal$4[0:0]$6104 - attribute \src "libresoc.v:137311.3-137327.6" - wire $0\ldst_port0_exc_$signal$5[0:0]$6105 - attribute \src "libresoc.v:137311.3-137327.6" - wire $0\ldst_port0_exc_$signal$6[0:0]$6106 - attribute \src "libresoc.v:137311.3-137327.6" - wire $0\ldst_port0_exc_$signal$7[0:0]$6107 - attribute \src "libresoc.v:137311.3-137327.6" - wire $0\ldst_port0_exc_$signal[0:0]$6100 - attribute \src "libresoc.v:137448.3-137457.6" + attribute \src "libresoc.v:139220.3-139229.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6179 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6146 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6147 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6148 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6149 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6150 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6151 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6152 + attribute \src "libresoc.v:139093.3-139109.6" + wire $0\ldst_port0_exc_$signal[0:0]$6145 + attribute \src "libresoc.v:139230.3-139239.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:137418.3-137427.6" - wire $0\ldst_port0_is_ld_i$8[0:0]$6128 - attribute \src "libresoc.v:137428.3-137437.6" - wire $0\ldst_port0_is_st_i$9[0:0]$6131 - attribute \src "libresoc.v:137280.3-137290.6" + attribute \src "libresoc.v:139200.3-139209.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6173 + attribute \src "libresoc.v:139210.3-139219.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6176 + attribute \src "libresoc.v:139062.3-139072.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:137280.3-137290.6" + attribute \src "libresoc.v:139062.3-139072.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:137353.3-137362.6" + attribute \src "libresoc.v:139135.3-139144.6" wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:137343.3-137352.6" + attribute \src "libresoc.v:139125.3-139134.6" wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:137269.3-137279.6" - wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6092 - attribute \src "libresoc.v:137269.3-137279.6" - wire $0\ldst_port0_st_data_i_ok$17[0:0]$6093 - attribute \src "libresoc.v:137226.3-137227.36" + attribute \src "libresoc.v:139051.3-139061.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6137 + attribute \src "libresoc.v:139051.3-139061.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6138 + attribute \src "libresoc.v:139008.3-139009.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:137408.3-137417.6" + attribute \src "libresoc.v:139190.3-139199.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:137393.3-137407.6" + attribute \src "libresoc.v:139175.3-139189.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:137328.3-137342.6" - wire $1\idx_l$23$next[0:0]$6118 - attribute \src "libresoc.v:137383.3-137392.6" + attribute \src "libresoc.v:139110.3-139124.6" + wire $1\idx_l$23$next[0:0]$6163 + attribute \src "libresoc.v:139165.3-139174.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:137373.3-137382.6" + attribute \src "libresoc.v:139155.3-139164.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:137249.3-137258.6" - wire width 48 $1\ldst_port0_addr_i$12[47:0]$6087 - attribute \src "libresoc.v:137259.3-137268.6" - wire $1\ldst_port0_addr_i_ok$13[0:0]$6090 - attribute \src "libresoc.v:137301.3-137310.6" + attribute \src "libresoc.v:139031.3-139040.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6132 + attribute \src "libresoc.v:139041.3-139050.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6135 + attribute \src "libresoc.v:139083.3-139092.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:137291.3-137300.6" + attribute \src "libresoc.v:139073.3-139082.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:137363.3-137372.6" + attribute \src "libresoc.v:139145.3-139154.6" wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:137438.3-137447.6" - wire width 4 $1\ldst_port0_data_len$11[3:0]$6135 - attribute \src "libresoc.v:137311.3-137327.6" - wire $1\ldst_port0_exc_$signal$1[0:0]$6109 - attribute \src "libresoc.v:137311.3-137327.6" - wire $1\ldst_port0_exc_$signal$2[0:0]$6110 - attribute \src "libresoc.v:137311.3-137327.6" - wire $1\ldst_port0_exc_$signal$3[0:0]$6111 - attribute \src "libresoc.v:137311.3-137327.6" - wire $1\ldst_port0_exc_$signal$4[0:0]$6112 - attribute \src "libresoc.v:137311.3-137327.6" - wire $1\ldst_port0_exc_$signal$5[0:0]$6113 - attribute \src "libresoc.v:137311.3-137327.6" - wire $1\ldst_port0_exc_$signal$6[0:0]$6114 - attribute \src "libresoc.v:137311.3-137327.6" - wire $1\ldst_port0_exc_$signal$7[0:0]$6115 - attribute \src "libresoc.v:137311.3-137327.6" - wire $1\ldst_port0_exc_$signal[0:0]$6108 - attribute \src "libresoc.v:137448.3-137457.6" + attribute \src "libresoc.v:139220.3-139229.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6180 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6154 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6155 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6156 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6157 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6158 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6159 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6160 + attribute \src "libresoc.v:139093.3-139109.6" + wire $1\ldst_port0_exc_$signal[0:0]$6153 + attribute \src "libresoc.v:139230.3-139239.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:137418.3-137427.6" - wire $1\ldst_port0_is_ld_i$8[0:0]$6129 - attribute \src "libresoc.v:137428.3-137437.6" - wire $1\ldst_port0_is_st_i$9[0:0]$6132 - attribute \src "libresoc.v:137280.3-137290.6" + attribute \src "libresoc.v:139200.3-139209.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6174 + attribute \src "libresoc.v:139210.3-139219.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6177 + attribute \src "libresoc.v:139062.3-139072.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:137280.3-137290.6" + attribute \src "libresoc.v:139062.3-139072.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:137353.3-137362.6" + attribute \src "libresoc.v:139135.3-139144.6" wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:137343.3-137352.6" + attribute \src "libresoc.v:139125.3-139134.6" wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:137269.3-137279.6" - wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6094 - attribute \src "libresoc.v:137269.3-137279.6" - wire $1\ldst_port0_st_data_i_ok$17[0:0]$6095 - attribute \src "libresoc.v:137213.7-137213.25" + attribute \src "libresoc.v:139051.3-139061.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6139 + attribute \src "libresoc.v:139051.3-139061.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6140 + attribute \src "libresoc.v:138995.7-138995.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:137408.3-137417.6" + attribute \src "libresoc.v:139190.3-139199.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:137393.3-137407.6" + attribute \src "libresoc.v:139175.3-139189.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:137328.3-137342.6" - wire $2\idx_l$23$next[0:0]$6119 - attribute \src "libresoc.v:137393.3-137407.6" + attribute \src "libresoc.v:139110.3-139124.6" + wire $2\idx_l$23$next[0:0]$6164 + attribute \src "libresoc.v:139175.3-139189.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:137224.18-137224.103" - wire $not$libresoc.v:137224$6080_Y - attribute \src "libresoc.v:137225.18-137225.118" - wire $not$libresoc.v:137225$6081_Y - attribute \src "libresoc.v:137222.18-137222.134" - wire $or$libresoc.v:137222$6078_Y - attribute \src "libresoc.v:137223.18-137223.120" - wire $ternary$libresoc.v:137223$6079_Y + attribute \src "libresoc.v:139006.18-139006.103" + wire $not$libresoc.v:139006$6125_Y + attribute \src "libresoc.v:139007.18-139007.118" + wire $not$libresoc.v:139007$6126_Y + attribute \src "libresoc.v:139004.18-139004.134" + wire $or$libresoc.v:139004$6123_Y + attribute \src "libresoc.v:139005.18-139005.120" + wire $ternary$libresoc.v:139005$6124_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" @@ -220014,9 +222509,9 @@ module \l0$130 wire width 96 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23 @@ -220028,7 +222523,7 @@ module \l0$130 wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l - attribute \src "libresoc.v:137066.7-137066.15" + attribute \src "libresoc.v:138848.7-138848.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 input 6 \ldst_port0_addr_i @@ -220139,23 +222634,23 @@ module \l0$130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:137224$6080 + cell $not $not$libresoc.v:139006$6125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:137224$6080_Y + connect \Y $not$libresoc.v:139006$6125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:137225$6081 + cell $not $not$libresoc.v:139007$6126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:137225$6081_Y + connect \Y $not$libresoc.v:139007$6126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:137222$6078 + cell $or $or$libresoc.v:139004$6123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220163,18 +222658,18 @@ module \l0$130 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:137222$6078_Y + connect \Y $or$libresoc.v:139004$6123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:137223$6079 + cell $mux $ternary$libresoc.v:139005$6124 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:137223$6079_Y + connect \Y $ternary$libresoc.v:139005$6124_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:137230.9-137236.4" + attribute \src "libresoc.v:139012.9-139018.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -220183,14 +222678,14 @@ module \l0$130 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:137237.8-137241.4" + attribute \src "libresoc.v:139019.8-139023.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:137242.17-137248.4" + attribute \src "libresoc.v:139024.17-139030.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -220198,52 +222693,52 @@ module \l0$130 connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:137066.7-137066.20" - process $proc$libresoc.v:137066$6137 + attribute \src "libresoc.v:138848.7-138848.20" + process $proc$libresoc.v:138848$6182 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137086.7-137086.24" - process $proc$libresoc.v:137086$6138 + attribute \src "libresoc.v:138868.7-138868.24" + process $proc$libresoc.v:138868$6183 assign { } { } - assign $0\idx_l$23[0:0]$6139 1'0 + assign $0\idx_l$23[0:0]$6184 1'0 sync always sync init - update \idx_l$23 $0\idx_l$23[0:0]$6139 + update \idx_l$23 $0\idx_l$23[0:0]$6184 end - attribute \src "libresoc.v:137213.7-137213.25" - process $proc$libresoc.v:137213$6140 + attribute \src "libresoc.v:138995.7-138995.25" + process $proc$libresoc.v:138995$6185 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:137226.3-137227.36" - process $proc$libresoc.v:137226$6082 + attribute \src "libresoc.v:139008.3-139009.36" + process $proc$libresoc.v:139008$6127 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:137228.3-137229.35" - process $proc$libresoc.v:137228$6083 + attribute \src "libresoc.v:139010.3-139011.35" + process $proc$libresoc.v:139010$6128 assign { } { } - assign $0\idx_l$23[0:0]$6084 \idx_l$23$next + assign $0\idx_l$23[0:0]$6129 \idx_l$23$next sync posedge \coresync_clk - update \idx_l$23 $0\idx_l$23[0:0]$6084 + update \idx_l$23 $0\idx_l$23[0:0]$6129 end - attribute \src "libresoc.v:137249.3-137258.6" - process $proc$libresoc.v:137249$6085 + attribute \src "libresoc.v:139031.3-139040.6" + process $proc$libresoc.v:139031$6130 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i$12[47:0]$6086 $1\ldst_port0_addr_i$12[47:0]$6087 - attribute \src "libresoc.v:137250.5-137250.29" + assign $0\ldst_port0_addr_i$12[47:0]$6131 $1\ldst_port0_addr_i$12[47:0]$6132 + attribute \src "libresoc.v:139032.5-139032.29" switch \initial - attribute \src "libresoc.v:137250.9-137250.17" + attribute \src "libresoc.v:139032.9-139032.17" case 1'1 case end @@ -220252,21 +222747,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i$12[47:0]$6087 \$32 [47:0] + assign $1\ldst_port0_addr_i$12[47:0]$6132 \$32 [47:0] case - assign $1\ldst_port0_addr_i$12[47:0]$6087 48'000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_addr_i$12[47:0]$6132 48'000000000000000000000000000000000000000000000000 end sync always - update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6086 + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6131 end - attribute \src "libresoc.v:137259.3-137268.6" - process $proc$libresoc.v:137259$6088 + attribute \src "libresoc.v:139041.3-139050.6" + process $proc$libresoc.v:139041$6133 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$13[0:0]$6089 $1\ldst_port0_addr_i_ok$13[0:0]$6090 - attribute \src "libresoc.v:137260.5-137260.29" + assign $0\ldst_port0_addr_i_ok$13[0:0]$6134 $1\ldst_port0_addr_i_ok$13[0:0]$6135 + attribute \src "libresoc.v:139042.5-139042.29" switch \initial - attribute \src "libresoc.v:137260.9-137260.17" + attribute \src "libresoc.v:139042.9-139042.17" case 1'1 case end @@ -220275,24 +222770,24 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$13[0:0]$6090 \ldst_port0_addr_i_ok + assign $1\ldst_port0_addr_i_ok$13[0:0]$6135 \ldst_port0_addr_i_ok case - assign $1\ldst_port0_addr_i_ok$13[0:0]$6090 1'0 + assign $1\ldst_port0_addr_i_ok$13[0:0]$6135 1'0 end sync always - update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6089 + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6134 end - attribute \src "libresoc.v:137269.3-137279.6" - process $proc$libresoc.v:137269$6091 + attribute \src "libresoc.v:139051.3-139061.6" + process $proc$libresoc.v:139051$6136 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_st_data_i$18[63:0]$6092 $1\ldst_port0_st_data_i$18[63:0]$6094 - assign $0\ldst_port0_st_data_i_ok$17[0:0]$6093 $1\ldst_port0_st_data_i_ok$17[0:0]$6095 - attribute \src "libresoc.v:137270.5-137270.29" + assign $0\ldst_port0_st_data_i$18[63:0]$6137 $1\ldst_port0_st_data_i$18[63:0]$6139 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6138 $1\ldst_port0_st_data_i_ok$17[0:0]$6140 + attribute \src "libresoc.v:139052.5-139052.29" switch \initial - attribute \src "libresoc.v:137270.9-137270.17" + attribute \src "libresoc.v:139052.9-139052.17" case 1'1 case end @@ -220302,26 +222797,26 @@ module \l0$130 case 1'1 assign { } { } assign { } { } - assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6095 $1\ldst_port0_st_data_i$18[63:0]$6094 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6140 $1\ldst_port0_st_data_i$18[63:0]$6139 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case - assign $1\ldst_port0_st_data_i$18[63:0]$6094 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$17[0:0]$6095 1'0 + assign $1\ldst_port0_st_data_i$18[63:0]$6139 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6140 1'0 end sync always - update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6092 - update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6093 + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6137 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6138 end - attribute \src "libresoc.v:137280.3-137290.6" - process $proc$libresoc.v:137280$6096 + attribute \src "libresoc.v:139062.3-139072.6" + process $proc$libresoc.v:139062$6141 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:137281.5-137281.29" + attribute \src "libresoc.v:139063.5-139063.29" switch \initial - attribute \src "libresoc.v:137281.9-137281.17" + attribute \src "libresoc.v:139063.9-139063.17" case 1'1 case end @@ -220340,14 +222835,14 @@ module \l0$130 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:137291.3-137300.6" - process $proc$libresoc.v:137291$6097 + attribute \src "libresoc.v:139073.3-139082.6" + process $proc$libresoc.v:139073$6142 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:137292.5-137292.29" + attribute \src "libresoc.v:139074.5-139074.29" switch \initial - attribute \src "libresoc.v:137292.9-137292.17" + attribute \src "libresoc.v:139074.9-139074.17" case 1'1 case end @@ -220363,14 +222858,14 @@ module \l0$130 sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:137301.3-137310.6" - process $proc$libresoc.v:137301$6098 + attribute \src "libresoc.v:139083.3-139092.6" + process $proc$libresoc.v:139083$6143 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:137302.5-137302.29" + attribute \src "libresoc.v:139084.5-139084.29" switch \initial - attribute \src "libresoc.v:137302.9-137302.17" + attribute \src "libresoc.v:139084.9-139084.17" case 1'1 case end @@ -220386,8 +222881,8 @@ module \l0$130 sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:137311.3-137327.6" - process $proc$libresoc.v:137311$6099 + attribute \src "libresoc.v:139093.3-139109.6" + process $proc$libresoc.v:139093$6144 assign { } { } assign { } { } assign { } { } @@ -220404,17 +222899,17 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_exc_$signal[0:0]$6100 $1\ldst_port0_exc_$signal[0:0]$6108 - assign $0\ldst_port0_exc_$signal$1[0:0]$6101 $1\ldst_port0_exc_$signal$1[0:0]$6109 - assign $0\ldst_port0_exc_$signal$2[0:0]$6102 $1\ldst_port0_exc_$signal$2[0:0]$6110 - assign $0\ldst_port0_exc_$signal$3[0:0]$6103 $1\ldst_port0_exc_$signal$3[0:0]$6111 - assign $0\ldst_port0_exc_$signal$4[0:0]$6104 $1\ldst_port0_exc_$signal$4[0:0]$6112 - assign $0\ldst_port0_exc_$signal$5[0:0]$6105 $1\ldst_port0_exc_$signal$5[0:0]$6113 - assign $0\ldst_port0_exc_$signal$6[0:0]$6106 $1\ldst_port0_exc_$signal$6[0:0]$6114 - assign $0\ldst_port0_exc_$signal$7[0:0]$6107 $1\ldst_port0_exc_$signal$7[0:0]$6115 - attribute \src "libresoc.v:137312.5-137312.29" + assign $0\ldst_port0_exc_$signal[0:0]$6145 $1\ldst_port0_exc_$signal[0:0]$6153 + assign $0\ldst_port0_exc_$signal$1[0:0]$6146 $1\ldst_port0_exc_$signal$1[0:0]$6154 + assign $0\ldst_port0_exc_$signal$2[0:0]$6147 $1\ldst_port0_exc_$signal$2[0:0]$6155 + assign $0\ldst_port0_exc_$signal$3[0:0]$6148 $1\ldst_port0_exc_$signal$3[0:0]$6156 + assign $0\ldst_port0_exc_$signal$4[0:0]$6149 $1\ldst_port0_exc_$signal$4[0:0]$6157 + assign $0\ldst_port0_exc_$signal$5[0:0]$6150 $1\ldst_port0_exc_$signal$5[0:0]$6158 + assign $0\ldst_port0_exc_$signal$6[0:0]$6151 $1\ldst_port0_exc_$signal$6[0:0]$6159 + assign $0\ldst_port0_exc_$signal$7[0:0]$6152 $1\ldst_port0_exc_$signal$7[0:0]$6160 + attribute \src "libresoc.v:139094.5-139094.29" switch \initial - attribute \src "libresoc.v:137312.9-137312.17" + attribute \src "libresoc.v:139094.9-139094.17" case 1'1 case end @@ -220430,36 +222925,36 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign { $1\ldst_port0_exc_$signal$7[0:0]$6115 $1\ldst_port0_exc_$signal$6[0:0]$6114 $1\ldst_port0_exc_$signal$5[0:0]$6113 $1\ldst_port0_exc_$signal$4[0:0]$6112 $1\ldst_port0_exc_$signal$3[0:0]$6111 $1\ldst_port0_exc_$signal$2[0:0]$6110 $1\ldst_port0_exc_$signal$1[0:0]$6109 $1\ldst_port0_exc_$signal[0:0]$6108 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6160 $1\ldst_port0_exc_$signal$6[0:0]$6159 $1\ldst_port0_exc_$signal$5[0:0]$6158 $1\ldst_port0_exc_$signal$4[0:0]$6157 $1\ldst_port0_exc_$signal$3[0:0]$6156 $1\ldst_port0_exc_$signal$2[0:0]$6155 $1\ldst_port0_exc_$signal$1[0:0]$6154 $1\ldst_port0_exc_$signal[0:0]$6153 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case - assign $1\ldst_port0_exc_$signal[0:0]$6108 1'0 - assign $1\ldst_port0_exc_$signal$1[0:0]$6109 1'0 - assign $1\ldst_port0_exc_$signal$2[0:0]$6110 1'0 - assign $1\ldst_port0_exc_$signal$3[0:0]$6111 1'0 - assign $1\ldst_port0_exc_$signal$4[0:0]$6112 1'0 - assign $1\ldst_port0_exc_$signal$5[0:0]$6113 1'0 - assign $1\ldst_port0_exc_$signal$6[0:0]$6114 1'0 - assign $1\ldst_port0_exc_$signal$7[0:0]$6115 1'0 + assign $1\ldst_port0_exc_$signal[0:0]$6153 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6154 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6155 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6156 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6157 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6158 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6159 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6160 1'0 end sync always - update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6100 - update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6101 - update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6102 - update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6103 - update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6104 - update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6105 - update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6106 - update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6107 + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6145 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6146 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6147 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6148 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6149 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6150 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6151 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6152 end - attribute \src "libresoc.v:137328.3-137342.6" - process $proc$libresoc.v:137328$6116 + attribute \src "libresoc.v:139110.3-139124.6" + process $proc$libresoc.v:139110$6161 assign { } { } assign { } { } assign { } { } - assign $0\idx_l$23$next[0:0]$6117 $2\idx_l$23$next[0:0]$6119 - attribute \src "libresoc.v:137329.5-137329.29" + assign $0\idx_l$23$next[0:0]$6162 $2\idx_l$23$next[0:0]$6164 + attribute \src "libresoc.v:139111.5-139111.29" switch \initial - attribute \src "libresoc.v:137329.9-137329.17" + attribute \src "libresoc.v:139111.9-139111.17" case 1'1 case end @@ -220468,30 +222963,30 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l$23$next[0:0]$6118 \pick_o + assign $1\idx_l$23$next[0:0]$6163 \pick_o case - assign $1\idx_l$23$next[0:0]$6118 \idx_l$23 + assign $1\idx_l$23$next[0:0]$6163 \idx_l$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\idx_l$23$next[0:0]$6119 1'0 + assign $2\idx_l$23$next[0:0]$6164 1'0 case - assign $2\idx_l$23$next[0:0]$6119 $1\idx_l$23$next[0:0]$6118 + assign $2\idx_l$23$next[0:0]$6164 $1\idx_l$23$next[0:0]$6163 end sync always - update \idx_l$23$next $0\idx_l$23$next[0:0]$6117 + update \idx_l$23$next $0\idx_l$23$next[0:0]$6162 end - attribute \src "libresoc.v:137343.3-137352.6" - process $proc$libresoc.v:137343$6120 + attribute \src "libresoc.v:139125.3-139134.6" + process $proc$libresoc.v:139125$6165 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:137344.5-137344.29" + attribute \src "libresoc.v:139126.5-139126.29" switch \initial - attribute \src "libresoc.v:137344.9-137344.17" + attribute \src "libresoc.v:139126.9-139126.17" case 1'1 case end @@ -220507,14 +223002,14 @@ module \l0$130 sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:137353.3-137362.6" - process $proc$libresoc.v:137353$6121 + attribute \src "libresoc.v:139135.3-139144.6" + process $proc$libresoc.v:139135$6166 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:137354.5-137354.29" + attribute \src "libresoc.v:139136.5-139136.29" switch \initial - attribute \src "libresoc.v:137354.9-137354.17" + attribute \src "libresoc.v:139136.9-139136.17" case 1'1 case end @@ -220530,14 +223025,14 @@ module \l0$130 sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:137363.3-137372.6" - process $proc$libresoc.v:137363$6122 + attribute \src "libresoc.v:139145.3-139154.6" + process $proc$libresoc.v:139145$6167 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:137364.5-137364.29" + attribute \src "libresoc.v:139146.5-139146.29" switch \initial - attribute \src "libresoc.v:137364.9-137364.17" + attribute \src "libresoc.v:139146.9-139146.17" case 1'1 case end @@ -220553,14 +223048,14 @@ module \l0$130 sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:137373.3-137382.6" - process $proc$libresoc.v:137373$6123 + attribute \src "libresoc.v:139155.3-139164.6" + process $proc$libresoc.v:139155$6168 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:137374.5-137374.29" + attribute \src "libresoc.v:139156.5-139156.29" switch \initial - attribute \src "libresoc.v:137374.9-137374.17" + attribute \src "libresoc.v:139156.9-139156.17" case 1'1 case end @@ -220576,14 +223071,14 @@ module \l0$130 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:137383.3-137392.6" - process $proc$libresoc.v:137383$6124 + attribute \src "libresoc.v:139165.3-139174.6" + process $proc$libresoc.v:139165$6169 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:137384.5-137384.29" + attribute \src "libresoc.v:139166.5-139166.29" switch \initial - attribute \src "libresoc.v:137384.9-137384.17" + attribute \src "libresoc.v:139166.9-139166.17" case 1'1 case end @@ -220599,14 +223094,14 @@ module \l0$130 sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:137393.3-137407.6" - process $proc$libresoc.v:137393$6125 + attribute \src "libresoc.v:139175.3-139189.6" + process $proc$libresoc.v:139175$6170 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:137394.5-137394.29" + attribute \src "libresoc.v:139176.5-139176.29" switch \initial - attribute \src "libresoc.v:137394.9-137394.17" + attribute \src "libresoc.v:139176.9-139176.17" case 1'1 case end @@ -220631,14 +223126,14 @@ module \l0$130 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:137408.3-137417.6" - process $proc$libresoc.v:137408$6126 + attribute \src "libresoc.v:139190.3-139199.6" + process $proc$libresoc.v:139190$6171 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:137409.5-137409.29" + attribute \src "libresoc.v:139191.5-139191.29" switch \initial - attribute \src "libresoc.v:137409.9-137409.17" + attribute \src "libresoc.v:139191.9-139191.17" case 1'1 case end @@ -220654,14 +223149,14 @@ module \l0$130 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:137418.3-137427.6" - process $proc$libresoc.v:137418$6127 + attribute \src "libresoc.v:139200.3-139209.6" + process $proc$libresoc.v:139200$6172 assign { } { } assign { } { } - assign $0\ldst_port0_is_ld_i$8[0:0]$6128 $1\ldst_port0_is_ld_i$8[0:0]$6129 - attribute \src "libresoc.v:137419.5-137419.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$6173 $1\ldst_port0_is_ld_i$8[0:0]$6174 + attribute \src "libresoc.v:139201.5-139201.29" switch \initial - attribute \src "libresoc.v:137419.9-137419.17" + attribute \src "libresoc.v:139201.9-139201.17" case 1'1 case end @@ -220670,21 +223165,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_ld_i$8[0:0]$6129 \ldst_port0_is_ld_i + assign $1\ldst_port0_is_ld_i$8[0:0]$6174 \ldst_port0_is_ld_i case - assign $1\ldst_port0_is_ld_i$8[0:0]$6129 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$6174 1'0 end sync always - update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6128 + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6173 end - attribute \src "libresoc.v:137428.3-137437.6" - process $proc$libresoc.v:137428$6130 + attribute \src "libresoc.v:139210.3-139219.6" + process $proc$libresoc.v:139210$6175 assign { } { } assign { } { } - assign $0\ldst_port0_is_st_i$9[0:0]$6131 $1\ldst_port0_is_st_i$9[0:0]$6132 - attribute \src "libresoc.v:137429.5-137429.29" + assign $0\ldst_port0_is_st_i$9[0:0]$6176 $1\ldst_port0_is_st_i$9[0:0]$6177 + attribute \src "libresoc.v:139211.5-139211.29" switch \initial - attribute \src "libresoc.v:137429.9-137429.17" + attribute \src "libresoc.v:139211.9-139211.17" case 1'1 case end @@ -220693,21 +223188,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_st_i$9[0:0]$6132 \ldst_port0_is_st_i + assign $1\ldst_port0_is_st_i$9[0:0]$6177 \ldst_port0_is_st_i case - assign $1\ldst_port0_is_st_i$9[0:0]$6132 1'0 + assign $1\ldst_port0_is_st_i$9[0:0]$6177 1'0 end sync always - update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6131 + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6176 end - attribute \src "libresoc.v:137438.3-137447.6" - process $proc$libresoc.v:137438$6133 + attribute \src "libresoc.v:139220.3-139229.6" + process $proc$libresoc.v:139220$6178 assign { } { } assign { } { } - assign $0\ldst_port0_data_len$11[3:0]$6134 $1\ldst_port0_data_len$11[3:0]$6135 - attribute \src "libresoc.v:137439.5-137439.29" + assign $0\ldst_port0_data_len$11[3:0]$6179 $1\ldst_port0_data_len$11[3:0]$6180 + attribute \src "libresoc.v:139221.5-139221.29" switch \initial - attribute \src "libresoc.v:137439.9-137439.17" + attribute \src "libresoc.v:139221.9-139221.17" case 1'1 case end @@ -220716,21 +223211,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_data_len$11[3:0]$6135 \ldst_port0_data_len + assign $1\ldst_port0_data_len$11[3:0]$6180 \ldst_port0_data_len case - assign $1\ldst_port0_data_len$11[3:0]$6135 4'0000 + assign $1\ldst_port0_data_len$11[3:0]$6180 4'0000 end sync always - update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6134 + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6179 end - attribute \src "libresoc.v:137448.3-137457.6" - process $proc$libresoc.v:137448$6136 + attribute \src "libresoc.v:139230.3-139239.6" + process $proc$libresoc.v:139230$6181 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:137449.5-137449.29" + attribute \src "libresoc.v:139231.5-139231.29" switch \initial - attribute \src "libresoc.v:137449.9-137449.17" + attribute \src "libresoc.v:139231.9-139231.17" case 1'1 case end @@ -220746,10 +223241,10 @@ module \l0$130 sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$20 $or$libresoc.v:137222$6078_Y - connect \$24 $ternary$libresoc.v:137223$6079_Y - connect \$26 $not$libresoc.v:137224$6080_Y - connect \$28 $not$libresoc.v:137225$6081_Y + connect \$20 $or$libresoc.v:139004$6123_Y + connect \$24 $ternary$libresoc.v:139005$6124_Y + connect \$26 $not$libresoc.v:139006$6125_Y + connect \$28 $not$libresoc.v:139007$6126_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 @@ -220766,37 +223261,37 @@ module \l0$130 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end -attribute \src "libresoc.v:137477.1-137535.10" +attribute \src "libresoc.v:139259.1-139317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:137478.7-137478.20" + attribute \src "libresoc.v:139260.7-139260.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137523.3-137531.6" - wire $0\q_int$next[0:0]$6151 - attribute \src "libresoc.v:137521.3-137522.27" + attribute \src "libresoc.v:139305.3-139313.6" + wire $0\q_int$next[0:0]$6196 + attribute \src "libresoc.v:139303.3-139304.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:137523.3-137531.6" - wire $1\q_int$next[0:0]$6152 - attribute \src "libresoc.v:137500.7-137500.19" + attribute \src "libresoc.v:139305.3-139313.6" + wire $1\q_int$next[0:0]$6197 + attribute \src "libresoc.v:139282.7-139282.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:137513.17-137513.96" - wire $and$libresoc.v:137513$6141_Y - attribute \src "libresoc.v:137518.17-137518.96" - wire $and$libresoc.v:137518$6146_Y - attribute \src "libresoc.v:137515.18-137515.99" - wire $not$libresoc.v:137515$6143_Y - attribute \src "libresoc.v:137517.17-137517.98" - wire $not$libresoc.v:137517$6145_Y - attribute \src "libresoc.v:137520.17-137520.98" - wire $not$libresoc.v:137520$6148_Y - attribute \src "libresoc.v:137514.18-137514.104" - wire $or$libresoc.v:137514$6142_Y - attribute \src "libresoc.v:137516.18-137516.105" - wire $or$libresoc.v:137516$6144_Y - attribute \src "libresoc.v:137519.17-137519.103" - wire $or$libresoc.v:137519$6147_Y + attribute \src "libresoc.v:139295.17-139295.96" + wire $and$libresoc.v:139295$6186_Y + attribute \src "libresoc.v:139300.17-139300.96" + wire $and$libresoc.v:139300$6191_Y + attribute \src "libresoc.v:139297.18-139297.99" + wire $not$libresoc.v:139297$6188_Y + attribute \src "libresoc.v:139299.17-139299.98" + wire $not$libresoc.v:139299$6190_Y + attribute \src "libresoc.v:139302.17-139302.98" + wire $not$libresoc.v:139302$6193_Y + attribute \src "libresoc.v:139296.18-139296.104" + wire $or$libresoc.v:139296$6187_Y + attribute \src "libresoc.v:139298.18-139298.105" + wire $or$libresoc.v:139298$6189_Y + attribute \src "libresoc.v:139301.17-139301.103" + wire $or$libresoc.v:139301$6192_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -220813,11 +223308,11 @@ module \ld_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:137478.7-137478.15" + attribute \src "libresoc.v:139260.7-139260.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -220834,7 +223329,7 @@ module \ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:137513$6141 + cell $and $and$libresoc.v:139295$6186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220842,10 +223337,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:137513$6141_Y + connect \Y $and$libresoc.v:139295$6186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:137518$6146 + cell $and $and$libresoc.v:139300$6191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220853,34 +223348,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:137518$6146_Y + connect \Y $and$libresoc.v:139300$6191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:137515$6143 + cell $not $not$libresoc.v:139297$6188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:137515$6143_Y + connect \Y $not$libresoc.v:139297$6188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:137517$6145 + cell $not $not$libresoc.v:139299$6190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:137517$6145_Y + connect \Y $not$libresoc.v:139299$6190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:137520$6148 + cell $not $not$libresoc.v:139302$6193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:137520$6148_Y + connect \Y $not$libresoc.v:139302$6193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:137514$6142 + cell $or $or$libresoc.v:139296$6187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220888,10 +223383,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:137514$6142_Y + connect \Y $or$libresoc.v:139296$6187_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:137516$6144 + cell $or $or$libresoc.v:139298$6189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220899,10 +223394,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:137516$6144_Y + connect \Y $or$libresoc.v:139298$6189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:137519$6147 + cell $or $or$libresoc.v:139301$6192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220910,39 +223405,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:137519$6147_Y + connect \Y $or$libresoc.v:139301$6192_Y end - attribute \src "libresoc.v:137478.7-137478.20" - process $proc$libresoc.v:137478$6153 + attribute \src "libresoc.v:139260.7-139260.20" + process $proc$libresoc.v:139260$6198 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137500.7-137500.19" - process $proc$libresoc.v:137500$6154 + attribute \src "libresoc.v:139282.7-139282.19" + process $proc$libresoc.v:139282$6199 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:137521.3-137522.27" - process $proc$libresoc.v:137521$6149 + attribute \src "libresoc.v:139303.3-139304.27" + process $proc$libresoc.v:139303$6194 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:137523.3-137531.6" - process $proc$libresoc.v:137523$6150 + attribute \src "libresoc.v:139305.3-139313.6" + process $proc$libresoc.v:139305$6195 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6151 $1\q_int$next[0:0]$6152 - attribute \src "libresoc.v:137524.5-137524.29" + assign $0\q_int$next[0:0]$6196 $1\q_int$next[0:0]$6197 + attribute \src "libresoc.v:139306.5-139306.29" switch \initial - attribute \src "libresoc.v:137524.9-137524.17" + attribute \src "libresoc.v:139306.9-139306.17" case 1'1 case end @@ -220951,572 +223446,572 @@ module \ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6152 1'0 + assign $1\q_int$next[0:0]$6197 1'0 case - assign $1\q_int$next[0:0]$6152 \$5 + assign $1\q_int$next[0:0]$6197 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6151 + update \q_int$next $0\q_int$next[0:0]$6196 end - connect \$9 $and$libresoc.v:137513$6141_Y - connect \$11 $or$libresoc.v:137514$6142_Y - connect \$13 $not$libresoc.v:137515$6143_Y - connect \$15 $or$libresoc.v:137516$6144_Y - connect \$1 $not$libresoc.v:137517$6145_Y - connect \$3 $and$libresoc.v:137518$6146_Y - connect \$5 $or$libresoc.v:137519$6147_Y - connect \$7 $not$libresoc.v:137520$6148_Y + connect \$9 $and$libresoc.v:139295$6186_Y + connect \$11 $or$libresoc.v:139296$6187_Y + connect \$13 $not$libresoc.v:139297$6188_Y + connect \$15 $or$libresoc.v:139298$6189_Y + connect \$1 $not$libresoc.v:139299$6190_Y + connect \$3 $and$libresoc.v:139300$6191_Y + connect \$5 $or$libresoc.v:139301$6192_Y + connect \$7 $not$libresoc.v:139302$6193_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:137539.1-138898.10" +attribute \src "libresoc.v:139321.1-140684.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:138553.3-138561.6" - wire $0\adr_l_r_adr$next[0:0]$6297 - attribute \src "libresoc.v:138435.3-138436.39" + attribute \src "libresoc.v:140339.3-140347.6" + wire $0\adr_l_r_adr$next[0:0]$6342 + attribute \src "libresoc.v:140221.3-140222.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:138381.3-138382.21" + attribute \src "libresoc.v:140167.3-140168.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:138718.3-138727.6" + attribute \src "libresoc.v:140504.3-140513.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:138728.3-138737.6" + attribute \src "libresoc.v:140514.3-140523.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:138708.3-138717.6" - wire width 64 $0\ea_r$next[63:0]$6385 - attribute \src "libresoc.v:138383.3-138384.25" + attribute \src "libresoc.v:140494.3-140503.6" + wire width 64 $0\ea_r$next[63:0]$6430 + attribute \src "libresoc.v:140169.3-140170.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:137540.7-137540.20" + attribute \src "libresoc.v:139322.7-139322.20" wire $0\initial[0:0] - attribute \src "libresoc.v:138783.3-138802.6" + attribute \src "libresoc.v:140569.3-140588.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:138747.3-138770.6" + attribute \src "libresoc.v:140533.3-140556.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:138650.3-138659.6" - wire width 64 $0\ldo_r$next[63:0]$6370 - attribute \src "libresoc.v:138391.3-138392.27" + attribute \src "libresoc.v:140436.3-140445.6" + wire width 64 $0\ldo_r$next[63:0]$6415 + attribute \src "libresoc.v:140177.3-140178.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:138379.3-138380.33" + attribute \src "libresoc.v:140165.3-140166.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:138738.3-138746.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$6390 - attribute \src "libresoc.v:138377.3-138378.57" + attribute \src "libresoc.v:140524.3-140532.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6435 + attribute \src "libresoc.v:140163.3-140164.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:138827.3-138838.6" + attribute \src "libresoc.v:140613.3-140624.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:138598.3-138606.6" - wire $0\lsd_l_r_lsd$next[0:0]$6312 - attribute \src "libresoc.v:138425.3-138426.39" + attribute \src "libresoc.v:140384.3-140392.6" + wire $0\lsd_l_r_lsd$next[0:0]$6357 + attribute \src "libresoc.v:140211.3-140212.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:138526.3-138534.6" - wire $0\opc_l_r_opc$next[0:0]$6288 - attribute \src "libresoc.v:138441.3-138442.39" + attribute \src "libresoc.v:140312.3-140320.6" + wire $0\opc_l_r_opc$next[0:0]$6333 + attribute \src "libresoc.v:140227.3-140228.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:138517.3-138525.6" - wire $0\opc_l_s_opc$next[0:0]$6285 - attribute \src "libresoc.v:138443.3-138444.39" + attribute \src "libresoc.v:140303.3-140311.6" + wire $0\opc_l_s_opc$next[0:0]$6330 + attribute \src "libresoc.v:140229.3-140230.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__byte_reverse$next[0:0]$6315 - attribute \src "libresoc.v:138417.3-138418.57" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__byte_reverse$next[0:0]$6360 + attribute \src "libresoc.v:140203.3-140204.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 4 $0\oper_r__data_len$next[3:0]$6316 - attribute \src "libresoc.v:138415.3-138416.49" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6361 + attribute \src "libresoc.v:140201.3-140202.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 13 $0\oper_r__fn_unit$next[12:0]$6317 - attribute \src "libresoc.v:138395.3-138396.47" - wire width 13 $0\oper_r__fn_unit[12:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$6318 - attribute \src "libresoc.v:138397.3-138398.61" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 14 $0\oper_r__fn_unit$next[13:0]$6362 + attribute \src "libresoc.v:140181.3-140182.47" + wire width 14 $0\oper_r__fn_unit[13:0] + attribute \src "libresoc.v:140393.3-140435.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6363 + attribute \src "libresoc.v:140183.3-140184.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__imm_data__ok$next[0:0]$6319 - attribute \src "libresoc.v:138399.3-138400.57" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6364 + attribute \src "libresoc.v:140185.3-140186.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 32 $0\oper_r__insn$next[31:0]$6320 - attribute \src "libresoc.v:138423.3-138424.41" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 32 $0\oper_r__insn$next[31:0]$6365 + attribute \src "libresoc.v:140209.3-140210.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$6321 - attribute \src "libresoc.v:138393.3-138394.51" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6366 + attribute \src "libresoc.v:140179.3-140180.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__is_32bit$next[0:0]$6322 - attribute \src "libresoc.v:138411.3-138412.49" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__is_32bit$next[0:0]$6367 + attribute \src "libresoc.v:140197.3-140198.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__is_signed$next[0:0]$6323 - attribute \src "libresoc.v:138413.3-138414.51" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__is_signed$next[0:0]$6368 + attribute \src "libresoc.v:140199.3-140200.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$6324 - attribute \src "libresoc.v:138421.3-138422.51" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6369 + attribute \src "libresoc.v:140207.3-140208.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__oe__oe$next[0:0]$6325 - attribute \src "libresoc.v:138407.3-138408.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__oe__oe$next[0:0]$6370 + attribute \src "libresoc.v:140193.3-140194.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__oe__ok$next[0:0]$6326 - attribute \src "libresoc.v:138409.3-138410.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__oe__ok$next[0:0]$6371 + attribute \src "libresoc.v:140195.3-140196.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__rc__ok$next[0:0]$6327 - attribute \src "libresoc.v:138405.3-138406.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__rc__ok$next[0:0]$6372 + attribute \src "libresoc.v:140191.3-140192.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__rc__rc$next[0:0]$6328 - attribute \src "libresoc.v:138403.3-138404.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__rc__rc$next[0:0]$6373 + attribute \src "libresoc.v:140189.3-140190.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__sign_extend$next[0:0]$6329 - attribute \src "libresoc.v:138419.3-138420.55" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__sign_extend$next[0:0]$6374 + attribute \src "libresoc.v:140205.3-140206.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $0\oper_r__zero_a$next[0:0]$6330 - attribute \src "libresoc.v:138401.3-138402.45" + attribute \src "libresoc.v:140393.3-140435.6" + wire $0\oper_r__zero_a$next[0:0]$6375 + attribute \src "libresoc.v:140187.3-140188.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:138445.3-138446.28" + attribute \src "libresoc.v:140231.3-140232.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:138771.3-138782.6" + attribute \src "libresoc.v:140557.3-140568.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:138544.3-138552.6" - wire width 3 $0\src_l_r_src$next[2:0]$6294 - attribute \src "libresoc.v:138437.3-138438.39" + attribute \src "libresoc.v:140330.3-140338.6" + wire width 3 $0\src_l_r_src$next[2:0]$6339 + attribute \src "libresoc.v:140223.3-140224.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:138535.3-138543.6" - wire width 3 $0\src_l_s_src$next[2:0]$6291 - attribute \src "libresoc.v:138439.3-138440.39" + attribute \src "libresoc.v:140321.3-140329.6" + wire width 3 $0\src_l_s_src$next[2:0]$6336 + attribute \src "libresoc.v:140225.3-140226.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:138660.3-138675.6" - wire width 64 $0\src_r0$next[63:0]$6373 - attribute \src "libresoc.v:138389.3-138390.29" + attribute \src "libresoc.v:140446.3-140461.6" + wire width 64 $0\src_r0$next[63:0]$6418 + attribute \src "libresoc.v:140175.3-140176.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:138676.3-138691.6" - wire width 64 $0\src_r1$next[63:0]$6377 - attribute \src "libresoc.v:138387.3-138388.29" + attribute \src "libresoc.v:140462.3-140477.6" + wire width 64 $0\src_r1$next[63:0]$6422 + attribute \src "libresoc.v:140173.3-140174.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:138692.3-138707.6" - wire width 64 $0\src_r2$next[63:0]$6381 - attribute \src "libresoc.v:138385.3-138386.29" + attribute \src "libresoc.v:140478.3-140493.6" + wire width 64 $0\src_r2$next[63:0]$6426 + attribute \src "libresoc.v:140171.3-140172.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:138803.3-138826.6" + attribute \src "libresoc.v:140589.3-140612.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:138589.3-138597.6" - wire $0\sto_l_r_sto$next[0:0]$6309 - attribute \src "libresoc.v:138427.3-138428.39" + attribute \src "libresoc.v:140375.3-140383.6" + wire $0\sto_l_r_sto$next[0:0]$6354 + attribute \src "libresoc.v:140213.3-140214.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:138580.3-138588.6" - wire $0\upd_l_r_upd$next[0:0]$6306 - attribute \src "libresoc.v:138429.3-138430.39" + attribute \src "libresoc.v:140366.3-140374.6" + wire $0\upd_l_r_upd$next[0:0]$6351 + attribute \src "libresoc.v:140215.3-140216.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:138571.3-138579.6" - wire $0\upd_l_s_upd$next[0:0]$6303 - attribute \src "libresoc.v:138431.3-138432.39" + attribute \src "libresoc.v:140357.3-140365.6" + wire $0\upd_l_s_upd$next[0:0]$6348 + attribute \src "libresoc.v:140217.3-140218.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:138562.3-138570.6" - wire $0\wri_l_r_wri$next[0:0]$6300 - attribute \src "libresoc.v:138433.3-138434.39" + attribute \src "libresoc.v:140348.3-140356.6" + wire $0\wri_l_r_wri$next[0:0]$6345 + attribute \src "libresoc.v:140219.3-140220.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:138553.3-138561.6" - wire $1\adr_l_r_adr$next[0:0]$6298 - attribute \src "libresoc.v:137736.7-137736.25" + attribute \src "libresoc.v:140339.3-140347.6" + wire $1\adr_l_r_adr$next[0:0]$6343 + attribute \src "libresoc.v:139518.7-139518.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:137750.7-137750.20" + attribute \src "libresoc.v:139532.7-139532.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:138718.3-138727.6" + attribute \src "libresoc.v:140504.3-140513.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:138728.3-138737.6" + attribute \src "libresoc.v:140514.3-140523.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:138708.3-138717.6" - wire width 64 $1\ea_r$next[63:0]$6386 - attribute \src "libresoc.v:137796.14-137796.41" + attribute \src "libresoc.v:140494.3-140503.6" + wire width 64 $1\ea_r$next[63:0]$6431 + attribute \src "libresoc.v:139578.14-139578.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:138783.3-138802.6" + attribute \src "libresoc.v:140569.3-140588.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:138747.3-138770.6" + attribute \src "libresoc.v:140533.3-140556.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:138650.3-138659.6" - wire width 64 $1\ldo_r$next[63:0]$6371 - attribute \src "libresoc.v:137826.14-137826.42" + attribute \src "libresoc.v:140436.3-140445.6" + wire width 64 $1\ldo_r$next[63:0]$6416 + attribute \src "libresoc.v:139608.14-139608.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:137831.14-137831.62" + attribute \src "libresoc.v:139613.14-139613.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:138738.3-138746.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$6391 - attribute \src "libresoc.v:137836.7-137836.34" + attribute \src "libresoc.v:140524.3-140532.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6436 + attribute \src "libresoc.v:139618.7-139618.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:138827.3-138838.6" + attribute \src "libresoc.v:140613.3-140624.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:138598.3-138606.6" - wire $1\lsd_l_r_lsd$next[0:0]$6313 - attribute \src "libresoc.v:137885.7-137885.25" + attribute \src "libresoc.v:140384.3-140392.6" + wire $1\lsd_l_r_lsd$next[0:0]$6358 + attribute \src "libresoc.v:139667.7-139667.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:138526.3-138534.6" - wire $1\opc_l_r_opc$next[0:0]$6289 - attribute \src "libresoc.v:137899.7-137899.25" + attribute \src "libresoc.v:140312.3-140320.6" + wire $1\opc_l_r_opc$next[0:0]$6334 + attribute \src "libresoc.v:139681.7-139681.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:138517.3-138525.6" - wire $1\opc_l_s_opc$next[0:0]$6286 - attribute \src "libresoc.v:137903.7-137903.25" + attribute \src "libresoc.v:140303.3-140311.6" + wire $1\opc_l_s_opc$next[0:0]$6331 + attribute \src "libresoc.v:139685.7-139685.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__byte_reverse$next[0:0]$6331 - attribute \src "libresoc.v:138032.7-138032.34" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__byte_reverse$next[0:0]$6376 + attribute \src "libresoc.v:139816.7-139816.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 4 $1\oper_r__data_len$next[3:0]$6332 - attribute \src "libresoc.v:138036.13-138036.36" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6377 + attribute \src "libresoc.v:139820.13-139820.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 13 $1\oper_r__fn_unit$next[12:0]$6333 - attribute \src "libresoc.v:138054.14-138054.40" - wire width 13 $1\oper_r__fn_unit[12:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$6334 - attribute \src "libresoc.v:138058.14-138058.59" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 14 $1\oper_r__fn_unit$next[13:0]$6378 + attribute \src "libresoc.v:139839.14-139839.40" + wire width 14 $1\oper_r__fn_unit[13:0] + attribute \src "libresoc.v:140393.3-140435.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6379 + attribute \src "libresoc.v:139843.14-139843.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__imm_data__ok$next[0:0]$6335 - attribute \src "libresoc.v:138062.7-138062.34" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6380 + attribute \src "libresoc.v:139847.7-139847.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 32 $1\oper_r__insn$next[31:0]$6336 - attribute \src "libresoc.v:138066.14-138066.34" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 32 $1\oper_r__insn$next[31:0]$6381 + attribute \src "libresoc.v:139851.14-139851.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$6337 - attribute \src "libresoc.v:138144.13-138144.38" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6382 + attribute \src "libresoc.v:139930.13-139930.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__is_32bit$next[0:0]$6338 - attribute \src "libresoc.v:138148.7-138148.30" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__is_32bit$next[0:0]$6383 + attribute \src "libresoc.v:139934.7-139934.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__is_signed$next[0:0]$6339 - attribute \src "libresoc.v:138152.7-138152.31" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__is_signed$next[0:0]$6384 + attribute \src "libresoc.v:139938.7-139938.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$6340 - attribute \src "libresoc.v:138161.13-138161.37" + attribute \src "libresoc.v:140393.3-140435.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6385 + attribute \src "libresoc.v:139947.13-139947.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__oe__oe$next[0:0]$6341 - attribute \src "libresoc.v:138165.7-138165.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__oe__oe$next[0:0]$6386 + attribute \src "libresoc.v:139951.7-139951.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__oe__ok$next[0:0]$6342 - attribute \src "libresoc.v:138169.7-138169.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__oe__ok$next[0:0]$6387 + attribute \src "libresoc.v:139955.7-139955.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__rc__ok$next[0:0]$6343 - attribute \src "libresoc.v:138173.7-138173.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__rc__ok$next[0:0]$6388 + attribute \src "libresoc.v:139959.7-139959.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__rc__rc$next[0:0]$6344 - attribute \src "libresoc.v:138177.7-138177.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__rc__rc$next[0:0]$6389 + attribute \src "libresoc.v:139963.7-139963.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__sign_extend$next[0:0]$6345 - attribute \src "libresoc.v:138181.7-138181.33" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__sign_extend$next[0:0]$6390 + attribute \src "libresoc.v:139967.7-139967.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $1\oper_r__zero_a$next[0:0]$6346 - attribute \src "libresoc.v:138185.7-138185.28" + attribute \src "libresoc.v:140393.3-140435.6" + wire $1\oper_r__zero_a$next[0:0]$6391 + attribute \src "libresoc.v:139971.7-139971.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:138189.7-138189.21" + attribute \src "libresoc.v:139975.7-139975.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:138771.3-138782.6" + attribute \src "libresoc.v:140557.3-140568.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:138544.3-138552.6" - wire width 3 $1\src_l_r_src$next[2:0]$6295 - attribute \src "libresoc.v:138231.13-138231.31" + attribute \src "libresoc.v:140330.3-140338.6" + wire width 3 $1\src_l_r_src$next[2:0]$6340 + attribute \src "libresoc.v:140017.13-140017.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:138535.3-138543.6" - wire width 3 $1\src_l_s_src$next[2:0]$6292 - attribute \src "libresoc.v:138235.13-138235.31" + attribute \src "libresoc.v:140321.3-140329.6" + wire width 3 $1\src_l_s_src$next[2:0]$6337 + attribute \src "libresoc.v:140021.13-140021.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:138660.3-138675.6" - wire width 64 $1\src_r0$next[63:0]$6374 - attribute \src "libresoc.v:138239.14-138239.43" + attribute \src "libresoc.v:140446.3-140461.6" + wire width 64 $1\src_r0$next[63:0]$6419 + attribute \src "libresoc.v:140025.14-140025.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:138676.3-138691.6" - wire width 64 $1\src_r1$next[63:0]$6378 - attribute \src "libresoc.v:138243.14-138243.43" + attribute \src "libresoc.v:140462.3-140477.6" + wire width 64 $1\src_r1$next[63:0]$6423 + attribute \src "libresoc.v:140029.14-140029.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:138692.3-138707.6" - wire width 64 $1\src_r2$next[63:0]$6382 - attribute \src "libresoc.v:138247.14-138247.43" + attribute \src "libresoc.v:140478.3-140493.6" + wire width 64 $1\src_r2$next[63:0]$6427 + attribute \src "libresoc.v:140033.14-140033.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:138803.3-138826.6" + attribute \src "libresoc.v:140589.3-140612.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:138589.3-138597.6" - wire $1\sto_l_r_sto$next[0:0]$6310 - attribute \src "libresoc.v:138257.7-138257.25" + attribute \src "libresoc.v:140375.3-140383.6" + wire $1\sto_l_r_sto$next[0:0]$6355 + attribute \src "libresoc.v:140043.7-140043.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:138580.3-138588.6" - wire $1\upd_l_r_upd$next[0:0]$6307 - attribute \src "libresoc.v:138267.7-138267.25" + attribute \src "libresoc.v:140366.3-140374.6" + wire $1\upd_l_r_upd$next[0:0]$6352 + attribute \src "libresoc.v:140053.7-140053.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:138571.3-138579.6" - wire $1\upd_l_s_upd$next[0:0]$6304 - attribute \src "libresoc.v:138271.7-138271.25" + attribute \src "libresoc.v:140357.3-140365.6" + wire $1\upd_l_s_upd$next[0:0]$6349 + attribute \src "libresoc.v:140057.7-140057.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:138562.3-138570.6" - wire $1\wri_l_r_wri$next[0:0]$6301 - attribute \src "libresoc.v:138281.7-138281.25" + attribute \src "libresoc.v:140348.3-140356.6" + wire $1\wri_l_r_wri$next[0:0]$6346 + attribute \src "libresoc.v:140067.7-140067.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:138783.3-138802.6" + attribute \src "libresoc.v:140569.3-140588.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:138747.3-138770.6" + attribute \src "libresoc.v:140533.3-140556.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__byte_reverse$next[0:0]$6347 - attribute \src "libresoc.v:138607.3-138649.6" - wire width 4 $2\oper_r__data_len$next[3:0]$6348 - attribute \src "libresoc.v:138607.3-138649.6" - wire width 13 $2\oper_r__fn_unit$next[12:0]$6349 - attribute \src "libresoc.v:138607.3-138649.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$6350 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__imm_data__ok$next[0:0]$6351 - attribute \src "libresoc.v:138607.3-138649.6" - wire width 32 $2\oper_r__insn$next[31:0]$6352 - attribute \src "libresoc.v:138607.3-138649.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$6353 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__is_32bit$next[0:0]$6354 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__is_signed$next[0:0]$6355 - attribute \src "libresoc.v:138607.3-138649.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$6356 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__oe__oe$next[0:0]$6357 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__oe__ok$next[0:0]$6358 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__rc__ok$next[0:0]$6359 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__rc__rc$next[0:0]$6360 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__sign_extend$next[0:0]$6361 - attribute \src "libresoc.v:138607.3-138649.6" - wire $2\oper_r__zero_a$next[0:0]$6362 - attribute \src "libresoc.v:138660.3-138675.6" - wire width 64 $2\src_r0$next[63:0]$6375 - attribute \src "libresoc.v:138676.3-138691.6" - wire width 64 $2\src_r1$next[63:0]$6379 - attribute \src "libresoc.v:138692.3-138707.6" - wire width 64 $2\src_r2$next[63:0]$6383 - attribute \src "libresoc.v:138803.3-138826.6" + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__byte_reverse$next[0:0]$6392 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6393 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 14 $2\oper_r__fn_unit$next[13:0]$6394 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6395 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6396 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 32 $2\oper_r__insn$next[31:0]$6397 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6398 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__is_32bit$next[0:0]$6399 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__is_signed$next[0:0]$6400 + attribute \src "libresoc.v:140393.3-140435.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6401 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__oe__oe$next[0:0]$6402 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__oe__ok$next[0:0]$6403 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__rc__ok$next[0:0]$6404 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__rc__rc$next[0:0]$6405 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__sign_extend$next[0:0]$6406 + attribute \src "libresoc.v:140393.3-140435.6" + wire $2\oper_r__zero_a$next[0:0]$6407 + attribute \src "libresoc.v:140446.3-140461.6" + wire width 64 $2\src_r0$next[63:0]$6420 + attribute \src "libresoc.v:140462.3-140477.6" + wire width 64 $2\src_r1$next[63:0]$6424 + attribute \src "libresoc.v:140478.3-140493.6" + wire width 64 $2\src_r2$next[63:0]$6428 + attribute \src "libresoc.v:140589.3-140612.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:138607.3-138649.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$6363 - attribute \src "libresoc.v:138607.3-138649.6" - wire $3\oper_r__imm_data__ok$next[0:0]$6364 - attribute \src "libresoc.v:138607.3-138649.6" - wire $3\oper_r__oe__oe$next[0:0]$6365 - attribute \src "libresoc.v:138607.3-138649.6" - wire $3\oper_r__oe__ok$next[0:0]$6366 - attribute \src "libresoc.v:138607.3-138649.6" - wire $3\oper_r__rc__ok$next[0:0]$6367 - attribute \src "libresoc.v:138607.3-138649.6" - wire $3\oper_r__rc__rc$next[0:0]$6368 - attribute \src "libresoc.v:138363.18-138363.124" - wire width 65 $add$libresoc.v:138363$6235_Y - attribute \src "libresoc.v:138286.19-138286.118" - wire $and$libresoc.v:138286$6155_Y - attribute \src "libresoc.v:138287.19-138287.125" - wire $and$libresoc.v:138287$6156_Y - attribute \src "libresoc.v:138288.19-138288.120" - wire $and$libresoc.v:138288$6157_Y - attribute \src "libresoc.v:138289.19-138289.125" - wire $and$libresoc.v:138289$6158_Y - attribute \src "libresoc.v:138290.19-138290.118" - wire $and$libresoc.v:138290$6159_Y - attribute \src "libresoc.v:138292.19-138292.119" - wire $and$libresoc.v:138292$6161_Y - attribute \src "libresoc.v:138293.19-138293.123" - wire $and$libresoc.v:138293$6162_Y - attribute \src "libresoc.v:138294.19-138294.123" - wire $and$libresoc.v:138294$6163_Y - attribute \src "libresoc.v:138295.19-138295.120" - wire $and$libresoc.v:138295$6164_Y - attribute \src "libresoc.v:138296.19-138296.123" - wire $and$libresoc.v:138296$6165_Y - attribute \src "libresoc.v:138297.19-138297.119" - wire $and$libresoc.v:138297$6166_Y - attribute \src "libresoc.v:138298.19-138298.123" - wire $and$libresoc.v:138298$6167_Y - attribute \src "libresoc.v:138299.19-138299.125" - wire $and$libresoc.v:138299$6168_Y - attribute \src "libresoc.v:138301.19-138301.116" - wire $and$libresoc.v:138301$6170_Y - attribute \src "libresoc.v:138303.19-138303.120" - wire $and$libresoc.v:138303$6172_Y - attribute \src "libresoc.v:138304.19-138304.123" - wire $and$libresoc.v:138304$6173_Y - attribute \src "libresoc.v:138308.19-138308.125" - wire $and$libresoc.v:138308$6177_Y - attribute \src "libresoc.v:138309.19-138309.123" - wire $and$libresoc.v:138309$6178_Y - attribute \src "libresoc.v:138314.19-138314.116" - wire $and$libresoc.v:138314$6183_Y - attribute \src "libresoc.v:138316.19-138316.116" - wire $and$libresoc.v:138316$6185_Y - attribute \src "libresoc.v:138319.19-138319.118" - wire $and$libresoc.v:138319$6188_Y - attribute \src "libresoc.v:138321.19-138321.125" - wire $and$libresoc.v:138321$6190_Y - attribute \src "libresoc.v:138324.19-138324.160" - wire width 3 $and$libresoc.v:138324$6193_Y - attribute \src "libresoc.v:138325.19-138325.122" - wire $and$libresoc.v:138325$6194_Y - attribute \src "libresoc.v:138326.19-138326.122" - wire $and$libresoc.v:138326$6195_Y - attribute \src "libresoc.v:138328.19-138328.122" - wire $and$libresoc.v:138328$6198_Y - attribute \src "libresoc.v:138340.18-138340.123" - wire $and$libresoc.v:138340$6212_Y - attribute \src "libresoc.v:138341.18-138341.123" - wire $and$libresoc.v:138341$6213_Y - attribute \src "libresoc.v:138343.18-138343.114" - wire $and$libresoc.v:138343$6215_Y - attribute \src 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$pos$libresoc.v:140115$6245_Y + attribute \src "libresoc.v:140116.19-140116.148" + wire width 64 $pos$libresoc.v:140116$6246_Y + attribute \src "libresoc.v:140118.19-140118.206" + wire width 64 $pos$libresoc.v:140118$6248_Y + attribute \src "libresoc.v:140120.19-140120.102" + wire width 64 $pos$libresoc.v:140120$6251_Y + attribute \src "libresoc.v:140121.19-140121.120" + wire width 64 $pos$libresoc.v:140121$6252_Y + attribute \src "libresoc.v:140122.19-140122.150" + wire width 64 $pos$libresoc.v:140122$6253_Y + attribute \src "libresoc.v:140145.18-140145.107" + wire width 64 $ternary$libresoc.v:140145$6276_Y + attribute \src "libresoc.v:140146.18-140146.112" + wire width 64 $ternary$libresoc.v:140146$6277_Y + attribute \src "libresoc.v:140147.18-140147.147" + wire width 64 $ternary$libresoc.v:140147$6278_Y + attribute \src "libresoc.v:140148.18-140148.155" + wire width 64 $ternary$libresoc.v:140148$6279_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" @@ -221731,9 +224226,9 @@ module \ldst0 wire \alu_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i @@ -221791,7 +224286,7 @@ module \ldst0 wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 - attribute \src "libresoc.v:137540.7-137540.15" + attribute \src "libresoc.v:139322.7-139322.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o @@ -221886,21 +224381,22 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 7 \oper_i_ldst_ldst0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -221981,6 +224477,7 @@ module \ldst0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -222015,23 +224512,24 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \oper_r__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \oper_r__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \oper_r__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \oper_r__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -222118,6 +224616,7 @@ module \ldst0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \oper_r__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -222262,7 +224761,7 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:138363$6235 + cell $add $add$libresoc.v:140149$6280 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -222270,10 +224769,10 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:138363$6235_Y + connect \Y $add$libresoc.v:140149$6280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:138286$6155 + cell $and $and$libresoc.v:140072$6200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222281,10 +224780,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 - connect \Y $and$libresoc.v:138286$6155_Y + connect \Y $and$libresoc.v:140072$6200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:138287$6156 + cell $and $and$libresoc.v:140073$6201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222292,10 +224791,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:138287$6156_Y + connect \Y $and$libresoc.v:140073$6201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:138288$6157 + cell $and $and$libresoc.v:140074$6202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222303,10 +224802,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o - connect \Y $and$libresoc.v:138288$6157_Y + connect \Y $and$libresoc.v:140074$6202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:138289$6158 + cell $and $and$libresoc.v:140075$6203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222314,10 +224813,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:138289$6158_Y + connect \Y $and$libresoc.v:140075$6203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:138290$6159 + cell $and $and$libresoc.v:140076$6204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222325,10 +224824,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:138290$6159_Y + connect \Y $and$libresoc.v:140076$6204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:138292$6161 + cell $and $and$libresoc.v:140078$6206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222336,10 +224835,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:138292$6161_Y + connect \Y $and$libresoc.v:140078$6206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:138293$6162 + cell $and $and$libresoc.v:140079$6207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222347,10 +224846,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:138293$6162_Y + connect \Y $and$libresoc.v:140079$6207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:138294$6163 + cell $and $and$libresoc.v:140080$6208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222358,10 +224857,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:138294$6163_Y + connect \Y $and$libresoc.v:140080$6208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:138295$6164 + cell $and $and$libresoc.v:140081$6209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222369,10 +224868,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:138295$6164_Y + connect \Y $and$libresoc.v:140081$6209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:138296$6165 + cell $and $and$libresoc.v:140082$6210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222380,10 +224879,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:138296$6165_Y + connect \Y $and$libresoc.v:140082$6210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:138297$6166 + cell $and $and$libresoc.v:140083$6211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222391,10 +224890,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:138297$6166_Y + connect \Y $and$libresoc.v:140083$6211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:138298$6167 + cell $and $and$libresoc.v:140084$6212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222402,10 +224901,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:138298$6167_Y + connect \Y $and$libresoc.v:140084$6212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:138299$6168 + cell $and $and$libresoc.v:140085$6213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222413,10 +224912,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:138299$6168_Y + connect \Y $and$libresoc.v:140085$6213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:138301$6170 + cell $and $and$libresoc.v:140087$6215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222424,10 +224923,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:138301$6170_Y + connect \Y $and$libresoc.v:140087$6215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:138303$6172 + cell $and $and$libresoc.v:140089$6217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222435,10 +224934,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:138303$6172_Y + connect \Y $and$libresoc.v:140089$6217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:138304$6173 + cell $and $and$libresoc.v:140090$6218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222446,10 +224945,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:138304$6173_Y + connect \Y $and$libresoc.v:140090$6218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:138308$6177 + cell $and $and$libresoc.v:140094$6222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222457,10 +224956,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:138308$6177_Y + connect \Y $and$libresoc.v:140094$6222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:138309$6178 + cell $and $and$libresoc.v:140095$6223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222468,10 +224967,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:138309$6178_Y + connect \Y $and$libresoc.v:140095$6223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:138314$6183 + cell $and $and$libresoc.v:140100$6228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222479,10 +224978,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 - connect \Y $and$libresoc.v:138314$6183_Y + connect \Y $and$libresoc.v:140100$6228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:138316$6185 + cell $and $and$libresoc.v:140102$6230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222490,10 +224989,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 - connect \Y $and$libresoc.v:138316$6185_Y + connect \Y $and$libresoc.v:140102$6230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:138319$6188 + cell $and $and$libresoc.v:140105$6233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222501,10 +225000,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 - connect \Y $and$libresoc.v:138319$6188_Y + connect \Y $and$libresoc.v:140105$6233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:138321$6190 + cell $and $and$libresoc.v:140107$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222512,10 +225011,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:138321$6190_Y + connect \Y $and$libresoc.v:140107$6235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:138324$6193 + cell $and $and$libresoc.v:140110$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -222523,10 +225022,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:138324$6193_Y + connect \Y $and$libresoc.v:140110$6238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:138325$6194 + cell $and $and$libresoc.v:140111$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222534,10 +225033,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:138325$6194_Y + connect \Y $and$libresoc.v:140111$6239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:138326$6195 + cell $and $and$libresoc.v:140112$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222545,10 +225044,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:138326$6195_Y + connect \Y $and$libresoc.v:140112$6240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - cell $and $and$libresoc.v:138328$6198 + cell $and $and$libresoc.v:140114$6243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222556,10 +225055,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:138328$6198_Y + connect \Y $and$libresoc.v:140114$6243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:138340$6212 + cell $and $and$libresoc.v:140126$6257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222567,10 +225066,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:138340$6212_Y + connect \Y $and$libresoc.v:140126$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:138341$6213 + cell $and $and$libresoc.v:140127$6258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222578,10 +225077,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:138341$6213_Y + connect \Y $and$libresoc.v:140127$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:138343$6215 + cell $and $and$libresoc.v:140129$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222589,10 +225088,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 - connect \Y $and$libresoc.v:138343$6215_Y + connect \Y $and$libresoc.v:140129$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:138345$6217 + cell $and $and$libresoc.v:140131$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222600,10 +225099,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $and$libresoc.v:138345$6217_Y + connect \Y $and$libresoc.v:140131$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:138348$6220 + cell $and $and$libresoc.v:140134$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222611,10 +225110,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:138348$6220_Y + connect \Y $and$libresoc.v:140134$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:138352$6224 + cell $and $and$libresoc.v:140138$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222622,10 +225121,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 - connect \Y $and$libresoc.v:138352$6224_Y + connect \Y $and$libresoc.v:140138$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:138355$6227 + cell $and $and$libresoc.v:140141$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222633,10 +225132,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:138355$6227_Y + connect \Y $and$libresoc.v:140141$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:138364$6236 + cell $and $and$libresoc.v:140150$6281 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -222644,10 +225143,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:138364$6236_Y + connect \Y $and$libresoc.v:140150$6281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:138366$6238 + cell $and $and$libresoc.v:140152$6283 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -222655,10 +225154,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:138366$6238_Y + connect \Y $and$libresoc.v:140152$6283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:138368$6240 + cell $and $and$libresoc.v:140154$6285 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -222666,10 +225165,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 - connect \Y $and$libresoc.v:138368$6240_Y + connect \Y $and$libresoc.v:140154$6285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:138369$6241 + cell $and $and$libresoc.v:140155$6286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222677,10 +225176,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:138369$6241_Y + connect \Y $and$libresoc.v:140155$6286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:138370$6242 + cell $and $and$libresoc.v:140156$6287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222688,10 +225187,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:138370$6242_Y + connect \Y $and$libresoc.v:140156$6287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:138375$6247 + cell $and $and$libresoc.v:140161$6292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222699,10 +225198,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 - connect \Y $and$libresoc.v:138375$6247_Y + connect \Y $and$libresoc.v:140161$6292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:138300$6169 + cell $eq $eq$libresoc.v:140086$6214 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -222710,10 +225209,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:138300$6169_Y + connect \Y $eq$libresoc.v:140086$6214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:138320$6189 + cell $eq $eq$libresoc.v:140106$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -222721,10 +225220,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:138320$6189_Y + connect \Y $eq$libresoc.v:140106$6234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:138322$6191 + cell $eq $eq$libresoc.v:140108$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -222732,10 +225231,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:138322$6191_Y + connect \Y $eq$libresoc.v:140108$6236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:138333$6204 + cell $eq $eq$libresoc.v:140119$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -222743,10 +225242,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:138333$6204_Y + connect \Y $eq$libresoc.v:140119$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:138338$6210 + cell $eq $eq$libresoc.v:140124$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -222754,10 +225253,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $eq$libresoc.v:138338$6210_Y + connect \Y $eq$libresoc.v:140124$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:138339$6211 + cell $eq $eq$libresoc.v:140125$6256 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -222765,10 +225264,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $eq$libresoc.v:138339$6211_Y + connect \Y $eq$libresoc.v:140125$6256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:138347$6219 + cell $eq $eq$libresoc.v:140133$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -222776,10 +225275,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:138347$6219_Y + connect \Y $eq$libresoc.v:140133$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:138351$6223 + cell $eq $eq$libresoc.v:140137$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -222787,114 +225286,114 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:138351$6223_Y + connect \Y $eq$libresoc.v:140137$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:138327$6196 + cell $pos $extend$libresoc.v:140113$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:138327$6196_Y + connect \Y $extend$libresoc.v:140113$6241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:138329$6199 + cell $pos $extend$libresoc.v:140115$6244 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:138329$6199_Y + connect \Y $extend$libresoc.v:140115$6244_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:138334$6205 + cell $pos $extend$libresoc.v:140120$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:138334$6205_Y + connect \Y $extend$libresoc.v:140120$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:138312$6181 + cell $not $not$libresoc.v:140098$6226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 - connect \Y $not$libresoc.v:138312$6181_Y + connect \Y $not$libresoc.v:140098$6226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:138317$6186 + cell $not $not$libresoc.v:140103$6231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:138317$6186_Y + connect \Y $not$libresoc.v:140103$6231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:138342$6214 + cell $not $not$libresoc.v:140128$6259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:138342$6214_Y + connect \Y $not$libresoc.v:140128$6259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:138344$6216 + cell $not $not$libresoc.v:140130$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:138344$6216_Y + connect \Y $not$libresoc.v:140130$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:138346$6218 + cell $not $not$libresoc.v:140132$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:138346$6218_Y + connect \Y $not$libresoc.v:140132$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:138350$6222 + cell $not $not$libresoc.v:140136$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:138350$6222_Y + connect \Y $not$libresoc.v:140136$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:138365$6237 + cell $not $not$libresoc.v:140151$6282 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:138365$6237_Y + connect \Y $not$libresoc.v:140151$6282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:138367$6239 + cell $not $not$libresoc.v:140153$6284 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:138367$6239_Y + connect \Y $not$libresoc.v:140153$6284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:138374$6246 + cell $not $not$libresoc.v:140160$6291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 - connect \Y $not$libresoc.v:138374$6246_Y + connect \Y $not$libresoc.v:140160$6291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:138376$6248 + cell $not $not$libresoc.v:140162$6293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:138376$6248_Y + connect \Y $not$libresoc.v:140162$6293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:138291$6160 + cell $or $or$libresoc.v:140077$6205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222902,10 +225401,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:138291$6160_Y + connect \Y $or$libresoc.v:140077$6205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:138302$6171 + cell $or $or$libresoc.v:140088$6216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222913,10 +225412,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:138302$6171_Y + connect \Y $or$libresoc.v:140088$6216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:138305$6174 + cell $or $or$libresoc.v:140091$6219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222924,10 +225423,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:138305$6174_Y + connect \Y $or$libresoc.v:140091$6219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:138306$6175 + cell $or $or$libresoc.v:140092$6220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222935,10 +225434,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:138306$6175_Y + connect \Y $or$libresoc.v:140092$6220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:138307$6176 + cell $or $or$libresoc.v:140093$6221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222946,10 +225445,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:138307$6176_Y + connect \Y $or$libresoc.v:140093$6221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:138310$6179 + cell $or $or$libresoc.v:140096$6224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222957,10 +225456,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:138310$6179_Y + connect \Y $or$libresoc.v:140096$6224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:138311$6180 + cell $or $or$libresoc.v:140097$6225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222968,10 +225467,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:138311$6180_Y + connect \Y $or$libresoc.v:140097$6225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:138313$6182 + cell $or $or$libresoc.v:140099$6227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222979,10 +225478,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:138313$6182_Y + connect \Y $or$libresoc.v:140099$6227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:138315$6184 + cell $or $or$libresoc.v:140101$6229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222990,10 +225489,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:138315$6184_Y + connect \Y $or$libresoc.v:140101$6229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:138318$6187 + cell $or $or$libresoc.v:140104$6232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223001,10 +225500,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:138318$6187_Y + connect \Y $or$libresoc.v:140104$6232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:138323$6192 + cell $or $or$libresoc.v:140109$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223012,10 +225511,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:138323$6192_Y + connect \Y $or$libresoc.v:140109$6237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:138331$6202 + cell $or $or$libresoc.v:140117$6247 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -223023,10 +225522,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:138331$6202_Y + connect \Y $or$libresoc.v:140117$6247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:138337$6209 + cell $or $or$libresoc.v:140123$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223034,10 +225533,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:138337$6209_Y + connect \Y $or$libresoc.v:140123$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:138349$6221 + cell $or $or$libresoc.v:140135$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223045,10 +225544,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 - connect \Y $or$libresoc.v:138349$6221_Y + connect \Y $or$libresoc.v:140135$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:138353$6225 + cell $or $or$libresoc.v:140139$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223056,10 +225555,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 - connect \Y $or$libresoc.v:138353$6225_Y + connect \Y $or$libresoc.v:140139$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:138354$6226 + cell $or $or$libresoc.v:140140$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223067,10 +225566,10 @@ module \ldst0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:138354$6226_Y + connect \Y $or$libresoc.v:140140$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:138356$6228 + cell $or $or$libresoc.v:140142$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223078,10 +225577,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:138356$6228_Y + connect \Y $or$libresoc.v:140142$6273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:138357$6229 + cell $or $or$libresoc.v:140143$6274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223089,10 +225588,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:138357$6229_Y + connect \Y $or$libresoc.v:140143$6274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:138358$6230 + cell $or $or$libresoc.v:140144$6275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223100,10 +225599,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:138358$6230_Y + connect \Y $or$libresoc.v:140144$6275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:138371$6243 + cell $or $or$libresoc.v:140157$6288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223111,10 +225610,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:138371$6243_Y + connect \Y $or$libresoc.v:140157$6288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:138372$6244 + cell $or $or$libresoc.v:140158$6289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223122,10 +225621,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:138372$6244_Y + connect \Y $or$libresoc.v:140158$6289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:138373$6245 + cell $or $or$libresoc.v:140159$6290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223133,98 +225632,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:138373$6245_Y + connect \Y $or$libresoc.v:140159$6290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:138327$6197 + cell $pos $pos$libresoc.v:140113$6242 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:138327$6196_Y - connect \Y $pos$libresoc.v:138327$6197_Y + connect \A $extend$libresoc.v:140113$6241_Y + connect \Y $pos$libresoc.v:140113$6242_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:138329$6200 + cell $pos $pos$libresoc.v:140115$6245 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:138329$6199_Y - connect \Y $pos$libresoc.v:138329$6200_Y + connect \A $extend$libresoc.v:140115$6244_Y + connect \Y $pos$libresoc.v:140115$6245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:138330$6201 + cell $pos $pos$libresoc.v:140116$6246 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:138330$6201_Y + connect \Y $pos$libresoc.v:140116$6246_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:138332$6203 + cell $pos $pos$libresoc.v:140118$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:138332$6203_Y + connect \Y $pos$libresoc.v:140118$6248_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:138334$6206 + cell $pos $pos$libresoc.v:140120$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:138334$6205_Y - connect \Y $pos$libresoc.v:138334$6206_Y + connect \A $extend$libresoc.v:140120$6250_Y + connect \Y $pos$libresoc.v:140120$6251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:138335$6207 + cell $pos $pos$libresoc.v:140121$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:138335$6207_Y + connect \Y $pos$libresoc.v:140121$6252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:138336$6208 + cell $pos $pos$libresoc.v:140122$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:138336$6208_Y + connect \Y $pos$libresoc.v:140122$6253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:138359$6231 + cell $mux $ternary$libresoc.v:140145$6276 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:138359$6231_Y + connect \Y $ternary$libresoc.v:140145$6276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:138360$6232 + cell $mux $ternary$libresoc.v:140146$6277 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:138360$6232_Y + connect \Y $ternary$libresoc.v:140146$6277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:138361$6233 + cell $mux $ternary$libresoc.v:140147$6278 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:138361$6233_Y + connect \Y $ternary$libresoc.v:140147$6278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:138362$6234 + cell $mux $ternary$libresoc.v:140148$6279 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:138362$6234_Y + connect \Y $ternary$libresoc.v:140148$6279_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:138447.9-138453.4" + attribute \src "libresoc.v:140233.9-140239.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223233,7 +225732,7 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:138454.15-138460.4" + attribute \src "libresoc.v:140240.15-140246.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223242,7 +225741,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:138461.9-138467.4" + attribute \src "libresoc.v:140247.9-140253.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223251,7 +225750,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:138468.9-138474.4" + attribute \src "libresoc.v:140254.9-140260.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223260,7 +225759,7 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:138475.15-138481.4" + attribute \src "libresoc.v:140261.15-140267.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223269,7 +225768,7 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:138482.15-138488.4" + attribute \src "libresoc.v:140268.15-140274.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223278,7 +225777,7 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:138489.15-138495.4" + attribute \src "libresoc.v:140275.15-140281.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223287,7 +225786,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:138496.9-138502.4" + attribute \src "libresoc.v:140282.9-140288.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223296,7 +225795,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:138503.9-138509.4" + attribute \src "libresoc.v:140289.9-140295.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223305,7 +225804,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:138510.9-138516.4" + attribute \src "libresoc.v:140296.9-140302.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -223313,547 +225812,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:137540.7-137540.20" - process $proc$libresoc.v:137540$6397 + attribute \src "libresoc.v:139322.7-139322.20" + process $proc$libresoc.v:139322$6442 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137736.7-137736.25" - process $proc$libresoc.v:137736$6398 + attribute \src "libresoc.v:139518.7-139518.25" + process $proc$libresoc.v:139518$6443 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:137750.7-137750.20" - process $proc$libresoc.v:137750$6399 + attribute \src "libresoc.v:139532.7-139532.20" + process $proc$libresoc.v:139532$6444 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:137796.14-137796.41" - process $proc$libresoc.v:137796$6400 + attribute \src "libresoc.v:139578.14-139578.41" + process $proc$libresoc.v:139578$6445 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:137826.14-137826.42" - process $proc$libresoc.v:137826$6401 + attribute \src "libresoc.v:139608.14-139608.42" + process $proc$libresoc.v:139608$6446 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:137831.14-137831.62" - process $proc$libresoc.v:137831$6402 + attribute \src "libresoc.v:139613.14-139613.62" + process $proc$libresoc.v:139613$6447 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:137836.7-137836.34" - process $proc$libresoc.v:137836$6403 + attribute \src "libresoc.v:139618.7-139618.34" + process $proc$libresoc.v:139618$6448 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:137885.7-137885.25" - process $proc$libresoc.v:137885$6404 + attribute \src "libresoc.v:139667.7-139667.25" + process $proc$libresoc.v:139667$6449 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:137899.7-137899.25" - process $proc$libresoc.v:137899$6405 + attribute \src "libresoc.v:139681.7-139681.25" + process $proc$libresoc.v:139681$6450 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:137903.7-137903.25" - process $proc$libresoc.v:137903$6406 + attribute \src "libresoc.v:139685.7-139685.25" + process $proc$libresoc.v:139685$6451 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:138032.7-138032.34" - process $proc$libresoc.v:138032$6407 + attribute \src "libresoc.v:139816.7-139816.34" + process $proc$libresoc.v:139816$6452 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:138036.13-138036.36" - process $proc$libresoc.v:138036$6408 + attribute \src "libresoc.v:139820.13-139820.36" + process $proc$libresoc.v:139820$6453 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:138054.14-138054.40" - process $proc$libresoc.v:138054$6409 + attribute \src "libresoc.v:139839.14-139839.40" + process $proc$libresoc.v:139839$6454 assign { } { } - assign $1\oper_r__fn_unit[12:0] 13'0000000000000 + assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init - update \oper_r__fn_unit $1\oper_r__fn_unit[12:0] + update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:138058.14-138058.59" - process $proc$libresoc.v:138058$6410 + attribute \src "libresoc.v:139843.14-139843.59" + process $proc$libresoc.v:139843$6455 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:138062.7-138062.34" - process $proc$libresoc.v:138062$6411 + attribute \src "libresoc.v:139847.7-139847.34" + process $proc$libresoc.v:139847$6456 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:138066.14-138066.34" - process $proc$libresoc.v:138066$6412 + attribute \src "libresoc.v:139851.14-139851.34" + process $proc$libresoc.v:139851$6457 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:138144.13-138144.38" - process $proc$libresoc.v:138144$6413 + attribute \src "libresoc.v:139930.13-139930.38" + process $proc$libresoc.v:139930$6458 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:138148.7-138148.30" - process $proc$libresoc.v:138148$6414 + attribute \src "libresoc.v:139934.7-139934.30" + process $proc$libresoc.v:139934$6459 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:138152.7-138152.31" - process $proc$libresoc.v:138152$6415 + attribute \src "libresoc.v:139938.7-139938.31" + process $proc$libresoc.v:139938$6460 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:138161.13-138161.37" - process $proc$libresoc.v:138161$6416 + attribute \src "libresoc.v:139947.13-139947.37" + process $proc$libresoc.v:139947$6461 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:138165.7-138165.28" - process $proc$libresoc.v:138165$6417 + attribute \src "libresoc.v:139951.7-139951.28" + process $proc$libresoc.v:139951$6462 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:138169.7-138169.28" - process $proc$libresoc.v:138169$6418 + attribute \src "libresoc.v:139955.7-139955.28" + process $proc$libresoc.v:139955$6463 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:138173.7-138173.28" - process $proc$libresoc.v:138173$6419 + attribute \src "libresoc.v:139959.7-139959.28" + process $proc$libresoc.v:139959$6464 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:138177.7-138177.28" - process $proc$libresoc.v:138177$6420 + attribute \src "libresoc.v:139963.7-139963.28" + process $proc$libresoc.v:139963$6465 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:138181.7-138181.33" - process $proc$libresoc.v:138181$6421 + attribute \src "libresoc.v:139967.7-139967.33" + process $proc$libresoc.v:139967$6466 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:138185.7-138185.28" - process $proc$libresoc.v:138185$6422 + attribute \src "libresoc.v:139971.7-139971.28" + process $proc$libresoc.v:139971$6467 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:138189.7-138189.21" - process $proc$libresoc.v:138189$6423 + attribute \src "libresoc.v:139975.7-139975.21" + process $proc$libresoc.v:139975$6468 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:138231.13-138231.31" - process $proc$libresoc.v:138231$6424 + attribute \src "libresoc.v:140017.13-140017.31" + process $proc$libresoc.v:140017$6469 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:138235.13-138235.31" - process $proc$libresoc.v:138235$6425 + attribute \src "libresoc.v:140021.13-140021.31" + process $proc$libresoc.v:140021$6470 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:138239.14-138239.43" - process $proc$libresoc.v:138239$6426 + attribute \src "libresoc.v:140025.14-140025.43" + process $proc$libresoc.v:140025$6471 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:138243.14-138243.43" - process $proc$libresoc.v:138243$6427 + attribute \src "libresoc.v:140029.14-140029.43" + process $proc$libresoc.v:140029$6472 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:138247.14-138247.43" - process $proc$libresoc.v:138247$6428 + attribute \src "libresoc.v:140033.14-140033.43" + process $proc$libresoc.v:140033$6473 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:138257.7-138257.25" - process $proc$libresoc.v:138257$6429 + attribute \src "libresoc.v:140043.7-140043.25" + process $proc$libresoc.v:140043$6474 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:138267.7-138267.25" - process $proc$libresoc.v:138267$6430 + attribute \src "libresoc.v:140053.7-140053.25" + process $proc$libresoc.v:140053$6475 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:138271.7-138271.25" - process $proc$libresoc.v:138271$6431 + attribute \src "libresoc.v:140057.7-140057.25" + process $proc$libresoc.v:140057$6476 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:138281.7-138281.25" - process $proc$libresoc.v:138281$6432 + attribute \src "libresoc.v:140067.7-140067.25" + process $proc$libresoc.v:140067$6477 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:138377.3-138378.57" - process $proc$libresoc.v:138377$6249 + attribute \src "libresoc.v:140163.3-140164.57" + process $proc$libresoc.v:140163$6294 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:138379.3-138380.33" - process $proc$libresoc.v:138379$6250 + attribute \src "libresoc.v:140165.3-140166.33" + process $proc$libresoc.v:140165$6295 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:138381.3-138382.21" - process $proc$libresoc.v:138381$6251 + attribute \src "libresoc.v:140167.3-140168.21" + process $proc$libresoc.v:140167$6296 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:138383.3-138384.25" - process $proc$libresoc.v:138383$6252 + attribute \src "libresoc.v:140169.3-140170.25" + process $proc$libresoc.v:140169$6297 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:138385.3-138386.29" - process $proc$libresoc.v:138385$6253 + attribute \src "libresoc.v:140171.3-140172.29" + process $proc$libresoc.v:140171$6298 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:138387.3-138388.29" - process $proc$libresoc.v:138387$6254 + attribute \src "libresoc.v:140173.3-140174.29" + process $proc$libresoc.v:140173$6299 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:138389.3-138390.29" - process $proc$libresoc.v:138389$6255 + attribute \src "libresoc.v:140175.3-140176.29" + process $proc$libresoc.v:140175$6300 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:138391.3-138392.27" - process $proc$libresoc.v:138391$6256 + attribute \src "libresoc.v:140177.3-140178.27" + process $proc$libresoc.v:140177$6301 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:138393.3-138394.51" - process $proc$libresoc.v:138393$6257 + attribute \src "libresoc.v:140179.3-140180.51" + process $proc$libresoc.v:140179$6302 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:138395.3-138396.47" - process $proc$libresoc.v:138395$6258 + attribute \src "libresoc.v:140181.3-140182.47" + process $proc$libresoc.v:140181$6303 assign { } { } - assign $0\oper_r__fn_unit[12:0] \oper_r__fn_unit$next + assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk - update \oper_r__fn_unit $0\oper_r__fn_unit[12:0] + update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:138397.3-138398.61" - process $proc$libresoc.v:138397$6259 + attribute \src "libresoc.v:140183.3-140184.61" + process $proc$libresoc.v:140183$6304 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:138399.3-138400.57" - process $proc$libresoc.v:138399$6260 + attribute \src "libresoc.v:140185.3-140186.57" + process $proc$libresoc.v:140185$6305 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:138401.3-138402.45" - process $proc$libresoc.v:138401$6261 + attribute \src "libresoc.v:140187.3-140188.45" + process $proc$libresoc.v:140187$6306 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:138403.3-138404.45" - process $proc$libresoc.v:138403$6262 + attribute \src "libresoc.v:140189.3-140190.45" + process $proc$libresoc.v:140189$6307 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:138405.3-138406.45" - process $proc$libresoc.v:138405$6263 + attribute \src "libresoc.v:140191.3-140192.45" + process $proc$libresoc.v:140191$6308 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:138407.3-138408.45" - process $proc$libresoc.v:138407$6264 + attribute \src "libresoc.v:140193.3-140194.45" + process $proc$libresoc.v:140193$6309 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:138409.3-138410.45" - process $proc$libresoc.v:138409$6265 + attribute \src "libresoc.v:140195.3-140196.45" + process $proc$libresoc.v:140195$6310 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:138411.3-138412.49" - process $proc$libresoc.v:138411$6266 + attribute \src "libresoc.v:140197.3-140198.49" + process $proc$libresoc.v:140197$6311 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:138413.3-138414.51" - process $proc$libresoc.v:138413$6267 + attribute \src "libresoc.v:140199.3-140200.51" + process $proc$libresoc.v:140199$6312 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:138415.3-138416.49" - process $proc$libresoc.v:138415$6268 + attribute \src "libresoc.v:140201.3-140202.49" + process $proc$libresoc.v:140201$6313 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:138417.3-138418.57" - process $proc$libresoc.v:138417$6269 + attribute \src "libresoc.v:140203.3-140204.57" + process $proc$libresoc.v:140203$6314 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:138419.3-138420.55" - process $proc$libresoc.v:138419$6270 + attribute \src "libresoc.v:140205.3-140206.55" + process $proc$libresoc.v:140205$6315 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:138421.3-138422.51" - process $proc$libresoc.v:138421$6271 + attribute \src "libresoc.v:140207.3-140208.51" + process $proc$libresoc.v:140207$6316 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:138423.3-138424.41" - process $proc$libresoc.v:138423$6272 + attribute \src "libresoc.v:140209.3-140210.41" + process $proc$libresoc.v:140209$6317 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:138425.3-138426.39" - process $proc$libresoc.v:138425$6273 + attribute \src "libresoc.v:140211.3-140212.39" + process $proc$libresoc.v:140211$6318 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:138427.3-138428.39" - process $proc$libresoc.v:138427$6274 + attribute \src "libresoc.v:140213.3-140214.39" + process $proc$libresoc.v:140213$6319 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:138429.3-138430.39" - process $proc$libresoc.v:138429$6275 + attribute \src "libresoc.v:140215.3-140216.39" + process $proc$libresoc.v:140215$6320 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:138431.3-138432.39" - process $proc$libresoc.v:138431$6276 + attribute \src "libresoc.v:140217.3-140218.39" + process $proc$libresoc.v:140217$6321 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:138433.3-138434.39" - process $proc$libresoc.v:138433$6277 + attribute \src "libresoc.v:140219.3-140220.39" + process $proc$libresoc.v:140219$6322 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:138435.3-138436.39" - process $proc$libresoc.v:138435$6278 + attribute \src "libresoc.v:140221.3-140222.39" + process $proc$libresoc.v:140221$6323 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:138437.3-138438.39" - process $proc$libresoc.v:138437$6279 + attribute \src "libresoc.v:140223.3-140224.39" + process $proc$libresoc.v:140223$6324 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:138439.3-138440.39" - process $proc$libresoc.v:138439$6280 + attribute \src "libresoc.v:140225.3-140226.39" + process $proc$libresoc.v:140225$6325 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:138441.3-138442.39" - process $proc$libresoc.v:138441$6281 + attribute \src "libresoc.v:140227.3-140228.39" + process $proc$libresoc.v:140227$6326 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:138443.3-138444.39" - process $proc$libresoc.v:138443$6282 + attribute \src "libresoc.v:140229.3-140230.39" + process $proc$libresoc.v:140229$6327 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:138445.3-138446.28" - process $proc$libresoc.v:138445$6283 + attribute \src "libresoc.v:140231.3-140232.28" + process $proc$libresoc.v:140231$6328 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:138517.3-138525.6" - process $proc$libresoc.v:138517$6284 + attribute \src "libresoc.v:140303.3-140311.6" + process $proc$libresoc.v:140303$6329 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6285 $1\opc_l_s_opc$next[0:0]$6286 - attribute \src "libresoc.v:138518.5-138518.29" + assign $0\opc_l_s_opc$next[0:0]$6330 $1\opc_l_s_opc$next[0:0]$6331 + attribute \src "libresoc.v:140304.5-140304.29" switch \initial - attribute \src "libresoc.v:138518.9-138518.17" + attribute \src "libresoc.v:140304.9-140304.17" case 1'1 case end @@ -223862,21 +226361,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6286 1'0 + assign $1\opc_l_s_opc$next[0:0]$6331 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6286 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6331 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6285 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6330 end - attribute \src "libresoc.v:138526.3-138534.6" - process $proc$libresoc.v:138526$6287 + attribute \src "libresoc.v:140312.3-140320.6" + process $proc$libresoc.v:140312$6332 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6288 $1\opc_l_r_opc$next[0:0]$6289 - attribute \src "libresoc.v:138527.5-138527.29" + assign $0\opc_l_r_opc$next[0:0]$6333 $1\opc_l_r_opc$next[0:0]$6334 + attribute \src "libresoc.v:140313.5-140313.29" switch \initial - attribute \src "libresoc.v:138527.9-138527.17" + attribute \src "libresoc.v:140313.9-140313.17" case 1'1 case end @@ -223885,21 +226384,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6289 1'1 + assign $1\opc_l_r_opc$next[0:0]$6334 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6289 \reset_o + assign $1\opc_l_r_opc$next[0:0]$6334 \reset_o end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6288 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6333 end - attribute \src "libresoc.v:138535.3-138543.6" - process $proc$libresoc.v:138535$6290 + attribute \src "libresoc.v:140321.3-140329.6" + process $proc$libresoc.v:140321$6335 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6291 $1\src_l_s_src$next[2:0]$6292 - attribute \src "libresoc.v:138536.5-138536.29" + assign $0\src_l_s_src$next[2:0]$6336 $1\src_l_s_src$next[2:0]$6337 + attribute \src "libresoc.v:140322.5-140322.29" switch \initial - attribute \src "libresoc.v:138536.9-138536.17" + attribute \src "libresoc.v:140322.9-140322.17" case 1'1 case end @@ -223908,21 +226407,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6292 3'000 + assign $1\src_l_s_src$next[2:0]$6337 3'000 case - assign $1\src_l_s_src$next[2:0]$6292 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6337 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6291 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6336 end - attribute \src "libresoc.v:138544.3-138552.6" - process $proc$libresoc.v:138544$6293 + attribute \src "libresoc.v:140330.3-140338.6" + process $proc$libresoc.v:140330$6338 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6294 $1\src_l_r_src$next[2:0]$6295 - attribute \src "libresoc.v:138545.5-138545.29" + assign $0\src_l_r_src$next[2:0]$6339 $1\src_l_r_src$next[2:0]$6340 + attribute \src "libresoc.v:140331.5-140331.29" switch \initial - attribute \src "libresoc.v:138545.9-138545.17" + attribute \src "libresoc.v:140331.9-140331.17" case 1'1 case end @@ -223931,21 +226430,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6295 3'111 + assign $1\src_l_r_src$next[2:0]$6340 3'111 case - assign $1\src_l_r_src$next[2:0]$6295 \reset_r + assign $1\src_l_r_src$next[2:0]$6340 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6294 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6339 end - attribute \src "libresoc.v:138553.3-138561.6" - process $proc$libresoc.v:138553$6296 + attribute \src "libresoc.v:140339.3-140347.6" + process $proc$libresoc.v:140339$6341 assign { } { } assign { } { } - assign $0\adr_l_r_adr$next[0:0]$6297 $1\adr_l_r_adr$next[0:0]$6298 - attribute \src "libresoc.v:138554.5-138554.29" + assign $0\adr_l_r_adr$next[0:0]$6342 $1\adr_l_r_adr$next[0:0]$6343 + attribute \src "libresoc.v:140340.5-140340.29" switch \initial - attribute \src "libresoc.v:138554.9-138554.17" + attribute \src "libresoc.v:140340.9-140340.17" case 1'1 case end @@ -223954,21 +226453,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adr_l_r_adr$next[0:0]$6298 1'1 + assign $1\adr_l_r_adr$next[0:0]$6343 1'1 case - assign $1\adr_l_r_adr$next[0:0]$6298 \reset_a + assign $1\adr_l_r_adr$next[0:0]$6343 \reset_a end sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6297 + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6342 end - attribute \src "libresoc.v:138562.3-138570.6" - process $proc$libresoc.v:138562$6299 + attribute \src "libresoc.v:140348.3-140356.6" + process $proc$libresoc.v:140348$6344 assign { } { } assign { } { } - assign $0\wri_l_r_wri$next[0:0]$6300 $1\wri_l_r_wri$next[0:0]$6301 - attribute \src "libresoc.v:138563.5-138563.29" + assign $0\wri_l_r_wri$next[0:0]$6345 $1\wri_l_r_wri$next[0:0]$6346 + attribute \src "libresoc.v:140349.5-140349.29" switch \initial - attribute \src "libresoc.v:138563.9-138563.17" + attribute \src "libresoc.v:140349.9-140349.17" case 1'1 case end @@ -223977,21 +226476,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wri_l_r_wri$next[0:0]$6301 1'1 + assign $1\wri_l_r_wri$next[0:0]$6346 1'1 case - assign $1\wri_l_r_wri$next[0:0]$6301 \$38 [0] + assign $1\wri_l_r_wri$next[0:0]$6346 \$38 [0] end sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6300 + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6345 end - attribute \src "libresoc.v:138571.3-138579.6" - process $proc$libresoc.v:138571$6302 + attribute \src "libresoc.v:140357.3-140365.6" + process $proc$libresoc.v:140357$6347 assign { } { } assign { } { } - assign $0\upd_l_s_upd$next[0:0]$6303 $1\upd_l_s_upd$next[0:0]$6304 - attribute \src "libresoc.v:138572.5-138572.29" + assign $0\upd_l_s_upd$next[0:0]$6348 $1\upd_l_s_upd$next[0:0]$6349 + attribute \src "libresoc.v:140358.5-140358.29" switch \initial - attribute \src "libresoc.v:138572.9-138572.17" + attribute \src "libresoc.v:140358.9-140358.17" case 1'1 case end @@ -224000,21 +226499,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_s_upd$next[0:0]$6304 1'0 + assign $1\upd_l_s_upd$next[0:0]$6349 1'0 case - assign $1\upd_l_s_upd$next[0:0]$6304 \reset_i + assign $1\upd_l_s_upd$next[0:0]$6349 \reset_i end sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6303 + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6348 end - attribute \src "libresoc.v:138580.3-138588.6" - process $proc$libresoc.v:138580$6305 + attribute \src "libresoc.v:140366.3-140374.6" + process $proc$libresoc.v:140366$6350 assign { } { } assign { } { } - assign $0\upd_l_r_upd$next[0:0]$6306 $1\upd_l_r_upd$next[0:0]$6307 - attribute \src "libresoc.v:138581.5-138581.29" + assign $0\upd_l_r_upd$next[0:0]$6351 $1\upd_l_r_upd$next[0:0]$6352 + attribute \src "libresoc.v:140367.5-140367.29" switch \initial - attribute \src "libresoc.v:138581.9-138581.17" + attribute \src "libresoc.v:140367.9-140367.17" case 1'1 case end @@ -224023,21 +226522,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_r_upd$next[0:0]$6307 1'1 + assign $1\upd_l_r_upd$next[0:0]$6352 1'1 case - assign $1\upd_l_r_upd$next[0:0]$6307 \reset_u + assign $1\upd_l_r_upd$next[0:0]$6352 \reset_u end sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6306 + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6351 end - attribute \src "libresoc.v:138589.3-138597.6" - process $proc$libresoc.v:138589$6308 + attribute \src "libresoc.v:140375.3-140383.6" + process $proc$libresoc.v:140375$6353 assign { } { } assign { } { } - assign $0\sto_l_r_sto$next[0:0]$6309 $1\sto_l_r_sto$next[0:0]$6310 - attribute \src "libresoc.v:138590.5-138590.29" + assign $0\sto_l_r_sto$next[0:0]$6354 $1\sto_l_r_sto$next[0:0]$6355 + attribute \src "libresoc.v:140376.5-140376.29" switch \initial - attribute \src "libresoc.v:138590.9-138590.17" + attribute \src "libresoc.v:140376.9-140376.17" case 1'1 case end @@ -224046,21 +226545,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sto_l_r_sto$next[0:0]$6310 1'1 + assign $1\sto_l_r_sto$next[0:0]$6355 1'1 case - assign $1\sto_l_r_sto$next[0:0]$6310 \$59 + assign $1\sto_l_r_sto$next[0:0]$6355 \$59 end sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6309 + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6354 end - attribute \src "libresoc.v:138598.3-138606.6" - process $proc$libresoc.v:138598$6311 + attribute \src "libresoc.v:140384.3-140392.6" + process $proc$libresoc.v:140384$6356 assign { } { } assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$6312 $1\lsd_l_r_lsd$next[0:0]$6313 - attribute \src "libresoc.v:138599.5-138599.29" + assign $0\lsd_l_r_lsd$next[0:0]$6357 $1\lsd_l_r_lsd$next[0:0]$6358 + attribute \src "libresoc.v:140385.5-140385.29" switch \initial - attribute \src "libresoc.v:138599.9-138599.17" + attribute \src "libresoc.v:140385.9-140385.17" case 1'1 case end @@ -224069,15 +226568,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$6313 1'1 + assign $1\lsd_l_r_lsd$next[0:0]$6358 1'1 case - assign $1\lsd_l_r_lsd$next[0:0]$6313 \$63 + assign $1\lsd_l_r_lsd$next[0:0]$6358 \$63 end sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6312 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6357 end - attribute \src "libresoc.v:138607.3-138649.6" - process $proc$libresoc.v:138607$6314 + attribute \src "libresoc.v:140393.3-140435.6" + process $proc$libresoc.v:140393$6359 assign { } { } assign { } { } assign { } { } @@ -224126,31 +226625,31 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$6315 $2\oper_r__byte_reverse$next[0:0]$6347 - assign $0\oper_r__data_len$next[3:0]$6316 $2\oper_r__data_len$next[3:0]$6348 - assign $0\oper_r__fn_unit$next[12:0]$6317 $2\oper_r__fn_unit$next[12:0]$6349 + assign $0\oper_r__byte_reverse$next[0:0]$6360 $2\oper_r__byte_reverse$next[0:0]$6392 + assign $0\oper_r__data_len$next[3:0]$6361 $2\oper_r__data_len$next[3:0]$6393 + assign $0\oper_r__fn_unit$next[13:0]$6362 $2\oper_r__fn_unit$next[13:0]$6394 assign { } { } assign { } { } - assign $0\oper_r__insn$next[31:0]$6320 $2\oper_r__insn$next[31:0]$6352 - assign $0\oper_r__insn_type$next[6:0]$6321 $2\oper_r__insn_type$next[6:0]$6353 - assign $0\oper_r__is_32bit$next[0:0]$6322 $2\oper_r__is_32bit$next[0:0]$6354 - assign $0\oper_r__is_signed$next[0:0]$6323 $2\oper_r__is_signed$next[0:0]$6355 - assign $0\oper_r__ldst_mode$next[1:0]$6324 $2\oper_r__ldst_mode$next[1:0]$6356 + assign $0\oper_r__insn$next[31:0]$6365 $2\oper_r__insn$next[31:0]$6397 + assign $0\oper_r__insn_type$next[6:0]$6366 $2\oper_r__insn_type$next[6:0]$6398 + assign $0\oper_r__is_32bit$next[0:0]$6367 $2\oper_r__is_32bit$next[0:0]$6399 + assign $0\oper_r__is_signed$next[0:0]$6368 $2\oper_r__is_signed$next[0:0]$6400 + assign $0\oper_r__ldst_mode$next[1:0]$6369 $2\oper_r__ldst_mode$next[1:0]$6401 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$6329 $2\oper_r__sign_extend$next[0:0]$6361 - assign $0\oper_r__zero_a$next[0:0]$6330 $2\oper_r__zero_a$next[0:0]$6362 - assign $0\oper_r__imm_data__data$next[63:0]$6318 $3\oper_r__imm_data__data$next[63:0]$6363 - assign $0\oper_r__imm_data__ok$next[0:0]$6319 $3\oper_r__imm_data__ok$next[0:0]$6364 - assign $0\oper_r__oe__oe$next[0:0]$6325 $3\oper_r__oe__oe$next[0:0]$6365 - assign $0\oper_r__oe__ok$next[0:0]$6326 $3\oper_r__oe__ok$next[0:0]$6366 - assign $0\oper_r__rc__ok$next[0:0]$6327 $3\oper_r__rc__ok$next[0:0]$6367 - assign $0\oper_r__rc__rc$next[0:0]$6328 $3\oper_r__rc__rc$next[0:0]$6368 - attribute \src "libresoc.v:138608.5-138608.29" + assign $0\oper_r__sign_extend$next[0:0]$6374 $2\oper_r__sign_extend$next[0:0]$6406 + assign $0\oper_r__zero_a$next[0:0]$6375 $2\oper_r__zero_a$next[0:0]$6407 + assign $0\oper_r__imm_data__data$next[63:0]$6363 $3\oper_r__imm_data__data$next[63:0]$6408 + assign $0\oper_r__imm_data__ok$next[0:0]$6364 $3\oper_r__imm_data__ok$next[0:0]$6409 + assign $0\oper_r__oe__oe$next[0:0]$6370 $3\oper_r__oe__oe$next[0:0]$6410 + assign $0\oper_r__oe__ok$next[0:0]$6371 $3\oper_r__oe__ok$next[0:0]$6411 + assign $0\oper_r__rc__ok$next[0:0]$6372 $3\oper_r__rc__ok$next[0:0]$6412 + assign $0\oper_r__rc__rc$next[0:0]$6373 $3\oper_r__rc__rc$next[0:0]$6413 + attribute \src "libresoc.v:140394.5-140394.29" switch \initial - attribute \src "libresoc.v:138608.9-138608.17" + attribute \src "libresoc.v:140394.9-140394.17" case 1'1 case end @@ -224174,24 +226673,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $1\oper_r__insn$next[31:0]$6336 $1\oper_r__ldst_mode$next[1:0]$6340 $1\oper_r__sign_extend$next[0:0]$6345 $1\oper_r__byte_reverse$next[0:0]$6331 $1\oper_r__data_len$next[3:0]$6332 $1\oper_r__is_signed$next[0:0]$6339 $1\oper_r__is_32bit$next[0:0]$6338 $1\oper_r__oe__ok$next[0:0]$6342 $1\oper_r__oe__oe$next[0:0]$6341 $1\oper_r__rc__ok$next[0:0]$6343 $1\oper_r__rc__rc$next[0:0]$6344 $1\oper_r__zero_a$next[0:0]$6346 $1\oper_r__imm_data__ok$next[0:0]$6335 $1\oper_r__imm_data__data$next[63:0]$6334 $1\oper_r__fn_unit$next[12:0]$6333 $1\oper_r__insn_type$next[6:0]$6337 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + assign { $1\oper_r__insn$next[31:0]$6381 $1\oper_r__ldst_mode$next[1:0]$6385 $1\oper_r__sign_extend$next[0:0]$6390 $1\oper_r__byte_reverse$next[0:0]$6376 $1\oper_r__data_len$next[3:0]$6377 $1\oper_r__is_signed$next[0:0]$6384 $1\oper_r__is_32bit$next[0:0]$6383 $1\oper_r__oe__ok$next[0:0]$6387 $1\oper_r__oe__oe$next[0:0]$6386 $1\oper_r__rc__ok$next[0:0]$6388 $1\oper_r__rc__rc$next[0:0]$6389 $1\oper_r__zero_a$next[0:0]$6391 $1\oper_r__imm_data__ok$next[0:0]$6380 $1\oper_r__imm_data__data$next[63:0]$6379 $1\oper_r__fn_unit$next[13:0]$6378 $1\oper_r__insn_type$next[6:0]$6382 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } case - assign $1\oper_r__byte_reverse$next[0:0]$6331 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$6332 \oper_r__data_len - assign $1\oper_r__fn_unit$next[12:0]$6333 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$6334 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$6335 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$6336 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$6337 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$6338 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$6339 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$6340 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$6341 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$6342 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$6343 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$6344 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$6345 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$6346 \oper_r__zero_a + assign $1\oper_r__byte_reverse$next[0:0]$6376 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6377 \oper_r__data_len + assign $1\oper_r__fn_unit$next[13:0]$6378 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6379 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6380 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6381 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6382 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6383 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6384 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6385 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6386 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6387 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6388 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6389 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6390 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6391 \oper_r__zero_a end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" switch \cu_done_o @@ -224213,24 +226712,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $2\oper_r__insn$next[31:0]$6352 $2\oper_r__ldst_mode$next[1:0]$6356 $2\oper_r__sign_extend$next[0:0]$6361 $2\oper_r__byte_reverse$next[0:0]$6347 $2\oper_r__data_len$next[3:0]$6348 $2\oper_r__is_signed$next[0:0]$6355 $2\oper_r__is_32bit$next[0:0]$6354 $2\oper_r__oe__ok$next[0:0]$6358 $2\oper_r__oe__oe$next[0:0]$6357 $2\oper_r__rc__ok$next[0:0]$6359 $2\oper_r__rc__rc$next[0:0]$6360 $2\oper_r__zero_a$next[0:0]$6362 $2\oper_r__imm_data__ok$next[0:0]$6351 $2\oper_r__imm_data__data$next[63:0]$6350 $2\oper_r__fn_unit$next[12:0]$6349 $2\oper_r__insn_type$next[6:0]$6353 } 132'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\oper_r__insn$next[31:0]$6397 $2\oper_r__ldst_mode$next[1:0]$6401 $2\oper_r__sign_extend$next[0:0]$6406 $2\oper_r__byte_reverse$next[0:0]$6392 $2\oper_r__data_len$next[3:0]$6393 $2\oper_r__is_signed$next[0:0]$6400 $2\oper_r__is_32bit$next[0:0]$6399 $2\oper_r__oe__ok$next[0:0]$6403 $2\oper_r__oe__oe$next[0:0]$6402 $2\oper_r__rc__ok$next[0:0]$6404 $2\oper_r__rc__rc$next[0:0]$6405 $2\oper_r__zero_a$next[0:0]$6407 $2\oper_r__imm_data__ok$next[0:0]$6396 $2\oper_r__imm_data__data$next[63:0]$6395 $2\oper_r__fn_unit$next[13:0]$6394 $2\oper_r__insn_type$next[6:0]$6398 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\oper_r__byte_reverse$next[0:0]$6347 $1\oper_r__byte_reverse$next[0:0]$6331 - assign $2\oper_r__data_len$next[3:0]$6348 $1\oper_r__data_len$next[3:0]$6332 - assign $2\oper_r__fn_unit$next[12:0]$6349 $1\oper_r__fn_unit$next[12:0]$6333 - assign $2\oper_r__imm_data__data$next[63:0]$6350 $1\oper_r__imm_data__data$next[63:0]$6334 - assign $2\oper_r__imm_data__ok$next[0:0]$6351 $1\oper_r__imm_data__ok$next[0:0]$6335 - assign $2\oper_r__insn$next[31:0]$6352 $1\oper_r__insn$next[31:0]$6336 - assign $2\oper_r__insn_type$next[6:0]$6353 $1\oper_r__insn_type$next[6:0]$6337 - assign $2\oper_r__is_32bit$next[0:0]$6354 $1\oper_r__is_32bit$next[0:0]$6338 - assign $2\oper_r__is_signed$next[0:0]$6355 $1\oper_r__is_signed$next[0:0]$6339 - assign $2\oper_r__ldst_mode$next[1:0]$6356 $1\oper_r__ldst_mode$next[1:0]$6340 - assign $2\oper_r__oe__oe$next[0:0]$6357 $1\oper_r__oe__oe$next[0:0]$6341 - assign $2\oper_r__oe__ok$next[0:0]$6358 $1\oper_r__oe__ok$next[0:0]$6342 - assign $2\oper_r__rc__ok$next[0:0]$6359 $1\oper_r__rc__ok$next[0:0]$6343 - assign $2\oper_r__rc__rc$next[0:0]$6360 $1\oper_r__rc__rc$next[0:0]$6344 - assign $2\oper_r__sign_extend$next[0:0]$6361 $1\oper_r__sign_extend$next[0:0]$6345 - assign $2\oper_r__zero_a$next[0:0]$6362 $1\oper_r__zero_a$next[0:0]$6346 + assign $2\oper_r__byte_reverse$next[0:0]$6392 $1\oper_r__byte_reverse$next[0:0]$6376 + assign $2\oper_r__data_len$next[3:0]$6393 $1\oper_r__data_len$next[3:0]$6377 + assign $2\oper_r__fn_unit$next[13:0]$6394 $1\oper_r__fn_unit$next[13:0]$6378 + assign $2\oper_r__imm_data__data$next[63:0]$6395 $1\oper_r__imm_data__data$next[63:0]$6379 + assign $2\oper_r__imm_data__ok$next[0:0]$6396 $1\oper_r__imm_data__ok$next[0:0]$6380 + assign $2\oper_r__insn$next[31:0]$6397 $1\oper_r__insn$next[31:0]$6381 + assign $2\oper_r__insn_type$next[6:0]$6398 $1\oper_r__insn_type$next[6:0]$6382 + assign $2\oper_r__is_32bit$next[0:0]$6399 $1\oper_r__is_32bit$next[0:0]$6383 + assign $2\oper_r__is_signed$next[0:0]$6400 $1\oper_r__is_signed$next[0:0]$6384 + assign $2\oper_r__ldst_mode$next[1:0]$6401 $1\oper_r__ldst_mode$next[1:0]$6385 + assign $2\oper_r__oe__oe$next[0:0]$6402 $1\oper_r__oe__oe$next[0:0]$6386 + assign $2\oper_r__oe__ok$next[0:0]$6403 $1\oper_r__oe__ok$next[0:0]$6387 + assign $2\oper_r__rc__ok$next[0:0]$6404 $1\oper_r__rc__ok$next[0:0]$6388 + assign $2\oper_r__rc__rc$next[0:0]$6405 $1\oper_r__rc__rc$next[0:0]$6389 + assign $2\oper_r__sign_extend$next[0:0]$6406 $1\oper_r__sign_extend$next[0:0]$6390 + assign $2\oper_r__zero_a$next[0:0]$6407 $1\oper_r__zero_a$next[0:0]$6391 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -224242,46 +226741,46 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$6363 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$6364 1'0 - assign $3\oper_r__rc__rc$next[0:0]$6368 1'0 - assign $3\oper_r__rc__ok$next[0:0]$6367 1'0 - assign $3\oper_r__oe__oe$next[0:0]$6365 1'0 - assign $3\oper_r__oe__ok$next[0:0]$6366 1'0 + assign $3\oper_r__imm_data__data$next[63:0]$6408 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6409 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6413 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6412 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6410 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6411 1'0 case - assign $3\oper_r__imm_data__data$next[63:0]$6363 $2\oper_r__imm_data__data$next[63:0]$6350 - assign $3\oper_r__imm_data__ok$next[0:0]$6364 $2\oper_r__imm_data__ok$next[0:0]$6351 - assign $3\oper_r__oe__oe$next[0:0]$6365 $2\oper_r__oe__oe$next[0:0]$6357 - assign $3\oper_r__oe__ok$next[0:0]$6366 $2\oper_r__oe__ok$next[0:0]$6358 - assign $3\oper_r__rc__ok$next[0:0]$6367 $2\oper_r__rc__ok$next[0:0]$6359 - assign $3\oper_r__rc__rc$next[0:0]$6368 $2\oper_r__rc__rc$next[0:0]$6360 + assign $3\oper_r__imm_data__data$next[63:0]$6408 $2\oper_r__imm_data__data$next[63:0]$6395 + assign $3\oper_r__imm_data__ok$next[0:0]$6409 $2\oper_r__imm_data__ok$next[0:0]$6396 + assign $3\oper_r__oe__oe$next[0:0]$6410 $2\oper_r__oe__oe$next[0:0]$6402 + assign $3\oper_r__oe__ok$next[0:0]$6411 $2\oper_r__oe__ok$next[0:0]$6403 + assign $3\oper_r__rc__ok$next[0:0]$6412 $2\oper_r__rc__ok$next[0:0]$6404 + assign $3\oper_r__rc__rc$next[0:0]$6413 $2\oper_r__rc__rc$next[0:0]$6405 end sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6315 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6316 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[12:0]$6317 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6318 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6319 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6320 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6321 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6322 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6323 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6324 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6325 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6326 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6327 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6328 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6329 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6330 + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6360 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6361 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6362 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6363 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6364 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6365 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6366 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6367 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6368 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6369 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6370 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6371 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6372 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6373 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6374 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6375 end - attribute \src "libresoc.v:138650.3-138659.6" - process $proc$libresoc.v:138650$6369 + attribute \src "libresoc.v:140436.3-140445.6" + process $proc$libresoc.v:140436$6414 assign { } { } assign { } { } - assign $0\ldo_r$next[63:0]$6370 $1\ldo_r$next[63:0]$6371 - attribute \src "libresoc.v:138651.5-138651.29" + assign $0\ldo_r$next[63:0]$6415 $1\ldo_r$next[63:0]$6416 + attribute \src "libresoc.v:140437.5-140437.29" switch \initial - attribute \src "libresoc.v:138651.9-138651.17" + attribute \src "libresoc.v:140437.9-140437.17" case 1'1 case end @@ -224290,22 +226789,22 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldo_r$next[63:0]$6371 \ldd_o + assign $1\ldo_r$next[63:0]$6416 \ldd_o case - assign $1\ldo_r$next[63:0]$6371 \ldo_r + assign $1\ldo_r$next[63:0]$6416 \ldo_r end sync always - update \ldo_r$next $0\ldo_r$next[63:0]$6370 + update \ldo_r$next $0\ldo_r$next[63:0]$6415 end - attribute \src "libresoc.v:138660.3-138675.6" - process $proc$libresoc.v:138660$6372 + attribute \src "libresoc.v:140446.3-140461.6" + process $proc$libresoc.v:140446$6417 assign { } { } assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6373 $2\src_r0$next[63:0]$6375 - attribute \src "libresoc.v:138661.5-138661.29" + assign $0\src_r0$next[63:0]$6418 $2\src_r0$next[63:0]$6420 + attribute \src "libresoc.v:140447.5-140447.29" switch \initial - attribute \src "libresoc.v:138661.9-138661.17" + attribute \src "libresoc.v:140447.9-140447.17" case 1'1 case end @@ -224314,31 +226813,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6374 \src1_i + assign $1\src_r0$next[63:0]$6419 \src1_i case - assign $1\src_r0$next[63:0]$6374 \src_r0 + assign $1\src_r0$next[63:0]$6419 \src_r0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r0$next[63:0]$6375 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r0$next[63:0]$6420 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r0$next[63:0]$6375 $1\src_r0$next[63:0]$6374 + assign $2\src_r0$next[63:0]$6420 $1\src_r0$next[63:0]$6419 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6373 + update \src_r0$next $0\src_r0$next[63:0]$6418 end - attribute \src "libresoc.v:138676.3-138691.6" - process $proc$libresoc.v:138676$6376 + attribute \src "libresoc.v:140462.3-140477.6" + process $proc$libresoc.v:140462$6421 assign { } { } assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6377 $2\src_r1$next[63:0]$6379 - attribute \src "libresoc.v:138677.5-138677.29" + assign $0\src_r1$next[63:0]$6422 $2\src_r1$next[63:0]$6424 + attribute \src "libresoc.v:140463.5-140463.29" switch \initial - attribute \src "libresoc.v:138677.9-138677.17" + attribute \src "libresoc.v:140463.9-140463.17" case 1'1 case end @@ -224347,31 +226846,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6378 \src2_i + assign $1\src_r1$next[63:0]$6423 \src2_i case - assign $1\src_r1$next[63:0]$6378 \src_r1 + assign $1\src_r1$next[63:0]$6423 \src_r1 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r1$next[63:0]$6379 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r1$next[63:0]$6424 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r1$next[63:0]$6379 $1\src_r1$next[63:0]$6378 + assign $2\src_r1$next[63:0]$6424 $1\src_r1$next[63:0]$6423 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6377 + update \src_r1$next $0\src_r1$next[63:0]$6422 end - attribute \src "libresoc.v:138692.3-138707.6" - process $proc$libresoc.v:138692$6380 + attribute \src "libresoc.v:140478.3-140493.6" + process $proc$libresoc.v:140478$6425 assign { } { } assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$6381 $2\src_r2$next[63:0]$6383 - attribute \src "libresoc.v:138693.5-138693.29" + assign $0\src_r2$next[63:0]$6426 $2\src_r2$next[63:0]$6428 + attribute \src "libresoc.v:140479.5-140479.29" switch \initial - attribute \src "libresoc.v:138693.9-138693.17" + attribute \src "libresoc.v:140479.9-140479.17" case 1'1 case end @@ -224380,30 +226879,30 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$6382 \src3_i + assign $1\src_r2$next[63:0]$6427 \src3_i case - assign $1\src_r2$next[63:0]$6382 \src_r2 + assign $1\src_r2$next[63:0]$6427 \src_r2 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r2$next[63:0]$6383 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r2$next[63:0]$6428 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r2$next[63:0]$6383 $1\src_r2$next[63:0]$6382 + assign $2\src_r2$next[63:0]$6428 $1\src_r2$next[63:0]$6427 end sync always - update \src_r2$next $0\src_r2$next[63:0]$6381 + update \src_r2$next $0\src_r2$next[63:0]$6426 end - attribute \src "libresoc.v:138708.3-138717.6" - process $proc$libresoc.v:138708$6384 + attribute \src "libresoc.v:140494.3-140503.6" + process $proc$libresoc.v:140494$6429 assign { } { } assign { } { } - assign $0\ea_r$next[63:0]$6385 $1\ea_r$next[63:0]$6386 - attribute \src "libresoc.v:138709.5-138709.29" + assign $0\ea_r$next[63:0]$6430 $1\ea_r$next[63:0]$6431 + attribute \src "libresoc.v:140495.5-140495.29" switch \initial - attribute \src "libresoc.v:138709.9-138709.17" + attribute \src "libresoc.v:140495.9-140495.17" case 1'1 case end @@ -224412,21 +226911,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ea_r$next[63:0]$6386 \alu_o + assign $1\ea_r$next[63:0]$6431 \alu_o case - assign $1\ea_r$next[63:0]$6386 \ea_r + assign $1\ea_r$next[63:0]$6431 \ea_r end sync always - update \ea_r$next $0\ea_r$next[63:0]$6385 + update \ea_r$next $0\ea_r$next[63:0]$6430 end - attribute \src "libresoc.v:138718.3-138727.6" - process $proc$libresoc.v:138718$6387 + attribute \src "libresoc.v:140504.3-140513.6" + process $proc$libresoc.v:140504$6432 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:138719.5-138719.29" + attribute \src "libresoc.v:140505.5-140505.29" switch \initial - attribute \src "libresoc.v:138719.9-138719.17" + attribute \src "libresoc.v:140505.9-140505.17" case 1'1 case end @@ -224442,14 +226941,14 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:138728.3-138737.6" - process $proc$libresoc.v:138728$6388 + attribute \src "libresoc.v:140514.3-140523.6" + process $proc$libresoc.v:140514$6433 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:138729.5-138729.29" + attribute \src "libresoc.v:140515.5-140515.29" switch \initial - attribute \src "libresoc.v:138729.9-138729.17" + attribute \src "libresoc.v:140515.9-140515.17" case 1'1 case end @@ -224465,14 +226964,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:138738.3-138746.6" - process $proc$libresoc.v:138738$6389 + attribute \src "libresoc.v:140524.3-140532.6" + process $proc$libresoc.v:140524$6434 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$6390 $1\ldst_port0_addr_i_ok$next[0:0]$6391 - attribute \src "libresoc.v:138739.5-138739.29" + assign $0\ldst_port0_addr_i_ok$next[0:0]$6435 $1\ldst_port0_addr_i_ok$next[0:0]$6436 + attribute \src "libresoc.v:140525.5-140525.29" switch \initial - attribute \src "libresoc.v:138739.9-138739.17" + attribute \src "libresoc.v:140525.9-140525.17" case 1'1 case end @@ -224481,21 +226980,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$6391 1'0 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6436 1'0 case - assign $1\ldst_port0_addr_i_ok$next[0:0]$6391 \$177 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6436 \$177 end sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6390 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6435 end - attribute \src "libresoc.v:138747.3-138770.6" - process $proc$libresoc.v:138747$6392 + attribute \src "libresoc.v:140533.3-140556.6" + process $proc$libresoc.v:140533$6437 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:138748.5-138748.29" + attribute \src "libresoc.v:140534.5-140534.29" switch \initial - attribute \src "libresoc.v:138748.9-138748.17" + attribute \src "libresoc.v:140534.9-140534.17" case 1'1 case end @@ -224532,13 +227031,13 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:138771.3-138782.6" - process $proc$libresoc.v:138771$6393 + attribute \src "libresoc.v:140557.3-140568.6" + process $proc$libresoc.v:140557$6438 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:138772.5-138772.29" + attribute \src "libresoc.v:140558.5-140558.29" switch \initial - attribute \src "libresoc.v:138772.9-138772.17" + attribute \src "libresoc.v:140558.9-140558.17" case 1'1 case end @@ -224556,13 +227055,13 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:138783.3-138802.6" - process $proc$libresoc.v:138783$6394 + attribute \src "libresoc.v:140569.3-140588.6" + process $proc$libresoc.v:140569$6439 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:138784.5-138784.29" + attribute \src "libresoc.v:140570.5-140570.29" switch \initial - attribute \src "libresoc.v:138784.9-138784.17" + attribute \src "libresoc.v:140570.9-140570.17" case 1'1 case end @@ -224591,14 +227090,14 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:138803.3-138826.6" - process $proc$libresoc.v:138803$6395 + attribute \src "libresoc.v:140589.3-140612.6" + process $proc$libresoc.v:140589$6440 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:138804.5-138804.29" + attribute \src "libresoc.v:140590.5-140590.29" switch \initial - attribute \src "libresoc.v:138804.9-138804.17" + attribute \src "libresoc.v:140590.9-140590.17" case 1'1 case end @@ -224635,13 +227134,13 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:138827.3-138838.6" - process $proc$libresoc.v:138827$6396 + attribute \src "libresoc.v:140613.3-140624.6" + process $proc$libresoc.v:140613$6441 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:138828.5-138828.29" + attribute \src "libresoc.v:140614.5-140614.29" switch \initial - attribute \src "libresoc.v:138828.9-138828.17" + attribute \src "libresoc.v:140614.9-140614.17" case 1'1 case end @@ -224659,97 +227158,97 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$100 $and$libresoc.v:138286$6155_Y - connect \$102 $and$libresoc.v:138287$6156_Y - connect \$104 $and$libresoc.v:138288$6157_Y - connect \$106 $and$libresoc.v:138289$6158_Y - connect \$108 $and$libresoc.v:138290$6159_Y - connect \$10 $or$libresoc.v:138291$6160_Y - connect \$110 $and$libresoc.v:138292$6161_Y - connect \$112 $and$libresoc.v:138293$6162_Y - connect \$114 $and$libresoc.v:138294$6163_Y - connect \$116 $and$libresoc.v:138295$6164_Y - connect \$118 $and$libresoc.v:138296$6165_Y - connect \$120 $and$libresoc.v:138297$6166_Y - connect \$122 $and$libresoc.v:138298$6167_Y - connect \$124 $and$libresoc.v:138299$6168_Y - connect \$126 $eq$libresoc.v:138300$6169_Y - connect \$128 $and$libresoc.v:138301$6170_Y - connect \$12 $or$libresoc.v:138302$6171_Y - connect \$130 $and$libresoc.v:138303$6172_Y - connect \$132 $and$libresoc.v:138304$6173_Y - connect \$134 $or$libresoc.v:138305$6174_Y - connect \$136 $or$libresoc.v:138306$6175_Y - connect \$138 $or$libresoc.v:138307$6176_Y - connect \$140 $and$libresoc.v:138308$6177_Y - connect \$142 $and$libresoc.v:138309$6178_Y - connect \$145 $or$libresoc.v:138310$6179_Y - connect \$147 $or$libresoc.v:138311$6180_Y - connect \$144 $not$libresoc.v:138312$6181_Y - connect \$14 $or$libresoc.v:138313$6182_Y - connect \$150 $and$libresoc.v:138314$6183_Y - connect \$152 $or$libresoc.v:138315$6184_Y - connect \$154 $and$libresoc.v:138316$6185_Y - connect \$156 $not$libresoc.v:138317$6186_Y - connect \$158 $or$libresoc.v:138318$6187_Y - connect \$160 $and$libresoc.v:138319$6188_Y - connect \$162 $eq$libresoc.v:138320$6189_Y - connect \$164 $and$libresoc.v:138321$6190_Y - connect \$167 $eq$libresoc.v:138322$6191_Y - connect \$16 $or$libresoc.v:138323$6192_Y - connect \$169 $and$libresoc.v:138324$6193_Y - connect \$171 $and$libresoc.v:138325$6194_Y - connect \$173 $and$libresoc.v:138326$6195_Y - connect \$175 $pos$libresoc.v:138327$6197_Y - connect \$177 $and$libresoc.v:138328$6198_Y - connect \$186 $pos$libresoc.v:138329$6200_Y - connect \$188 $pos$libresoc.v:138330$6201_Y - connect \$18 $or$libresoc.v:138331$6202_Y - connect \$190 $pos$libresoc.v:138332$6203_Y - connect \$192 $eq$libresoc.v:138333$6204_Y - connect \$194 $pos$libresoc.v:138334$6206_Y - connect \$196 $pos$libresoc.v:138335$6207_Y - connect \$198 $pos$libresoc.v:138336$6208_Y - connect \$20 $or$libresoc.v:138337$6209_Y - connect \$22 $eq$libresoc.v:138338$6210_Y - connect \$24 $eq$libresoc.v:138339$6211_Y - connect \$26 $and$libresoc.v:138340$6212_Y - connect \$28 $and$libresoc.v:138341$6213_Y - connect \$30 $not$libresoc.v:138342$6214_Y - connect \$32 $and$libresoc.v:138343$6215_Y - connect \$34 $not$libresoc.v:138344$6216_Y - connect \$36 $and$libresoc.v:138345$6217_Y - connect \$39 $not$libresoc.v:138346$6218_Y - connect \$41 $eq$libresoc.v:138347$6219_Y - connect \$43 $and$libresoc.v:138348$6220_Y - connect \$45 $or$libresoc.v:138349$6221_Y - connect \$47 $not$libresoc.v:138350$6222_Y - connect \$49 $eq$libresoc.v:138351$6223_Y - connect \$51 $and$libresoc.v:138352$6224_Y - connect \$53 $or$libresoc.v:138353$6225_Y - connect \$55 $or$libresoc.v:138354$6226_Y - connect \$57 $and$libresoc.v:138355$6227_Y - connect \$59 $or$libresoc.v:138356$6228_Y - connect \$61 $or$libresoc.v:138357$6229_Y - connect \$63 $or$libresoc.v:138358$6230_Y - connect \$65 $ternary$libresoc.v:138359$6231_Y - connect \$67 $ternary$libresoc.v:138360$6232_Y - connect \$69 $ternary$libresoc.v:138361$6233_Y - connect \$71 $ternary$libresoc.v:138362$6234_Y - connect \$74 $add$libresoc.v:138363$6235_Y - connect \$76 $and$libresoc.v:138364$6236_Y - connect \$78 $not$libresoc.v:138365$6237_Y - connect \$80 $and$libresoc.v:138366$6238_Y - connect \$82 $not$libresoc.v:138367$6239_Y - connect \$84 $and$libresoc.v:138368$6240_Y - connect \$86 $and$libresoc.v:138369$6241_Y - connect \$88 $and$libresoc.v:138370$6242_Y - connect \$8 $or$libresoc.v:138371$6243_Y - connect \$90 $or$libresoc.v:138372$6244_Y - connect \$93 $or$libresoc.v:138373$6245_Y - connect \$92 $not$libresoc.v:138374$6246_Y - connect \$96 $and$libresoc.v:138375$6247_Y - connect \$98 $not$libresoc.v:138376$6248_Y + connect \$100 $and$libresoc.v:140072$6200_Y + connect \$102 $and$libresoc.v:140073$6201_Y + connect \$104 $and$libresoc.v:140074$6202_Y + connect \$106 $and$libresoc.v:140075$6203_Y + connect \$108 $and$libresoc.v:140076$6204_Y + connect \$10 $or$libresoc.v:140077$6205_Y + connect \$110 $and$libresoc.v:140078$6206_Y + connect \$112 $and$libresoc.v:140079$6207_Y + connect \$114 $and$libresoc.v:140080$6208_Y + connect \$116 $and$libresoc.v:140081$6209_Y + connect \$118 $and$libresoc.v:140082$6210_Y + connect \$120 $and$libresoc.v:140083$6211_Y + connect \$122 $and$libresoc.v:140084$6212_Y + connect \$124 $and$libresoc.v:140085$6213_Y + connect \$126 $eq$libresoc.v:140086$6214_Y + connect \$128 $and$libresoc.v:140087$6215_Y + connect \$12 $or$libresoc.v:140088$6216_Y + connect \$130 $and$libresoc.v:140089$6217_Y + connect \$132 $and$libresoc.v:140090$6218_Y + connect \$134 $or$libresoc.v:140091$6219_Y + connect \$136 $or$libresoc.v:140092$6220_Y + connect \$138 $or$libresoc.v:140093$6221_Y + connect \$140 $and$libresoc.v:140094$6222_Y + connect \$142 $and$libresoc.v:140095$6223_Y + connect \$145 $or$libresoc.v:140096$6224_Y + connect \$147 $or$libresoc.v:140097$6225_Y + connect \$144 $not$libresoc.v:140098$6226_Y + connect \$14 $or$libresoc.v:140099$6227_Y + connect \$150 $and$libresoc.v:140100$6228_Y + connect \$152 $or$libresoc.v:140101$6229_Y + connect \$154 $and$libresoc.v:140102$6230_Y + connect \$156 $not$libresoc.v:140103$6231_Y + connect \$158 $or$libresoc.v:140104$6232_Y + connect \$160 $and$libresoc.v:140105$6233_Y + connect \$162 $eq$libresoc.v:140106$6234_Y + connect \$164 $and$libresoc.v:140107$6235_Y + connect \$167 $eq$libresoc.v:140108$6236_Y + connect \$16 $or$libresoc.v:140109$6237_Y + connect \$169 $and$libresoc.v:140110$6238_Y + connect \$171 $and$libresoc.v:140111$6239_Y + connect \$173 $and$libresoc.v:140112$6240_Y + connect \$175 $pos$libresoc.v:140113$6242_Y + connect \$177 $and$libresoc.v:140114$6243_Y + connect \$186 $pos$libresoc.v:140115$6245_Y + connect \$188 $pos$libresoc.v:140116$6246_Y + connect \$18 $or$libresoc.v:140117$6247_Y + connect \$190 $pos$libresoc.v:140118$6248_Y + connect \$192 $eq$libresoc.v:140119$6249_Y + connect \$194 $pos$libresoc.v:140120$6251_Y + connect \$196 $pos$libresoc.v:140121$6252_Y + connect \$198 $pos$libresoc.v:140122$6253_Y + connect \$20 $or$libresoc.v:140123$6254_Y + connect \$22 $eq$libresoc.v:140124$6255_Y + connect \$24 $eq$libresoc.v:140125$6256_Y + connect \$26 $and$libresoc.v:140126$6257_Y + connect \$28 $and$libresoc.v:140127$6258_Y + connect \$30 $not$libresoc.v:140128$6259_Y + connect \$32 $and$libresoc.v:140129$6260_Y + connect \$34 $not$libresoc.v:140130$6261_Y + connect \$36 $and$libresoc.v:140131$6262_Y + connect \$39 $not$libresoc.v:140132$6263_Y + connect \$41 $eq$libresoc.v:140133$6264_Y + connect \$43 $and$libresoc.v:140134$6265_Y + connect \$45 $or$libresoc.v:140135$6266_Y + connect \$47 $not$libresoc.v:140136$6267_Y + connect \$49 $eq$libresoc.v:140137$6268_Y + connect \$51 $and$libresoc.v:140138$6269_Y + connect \$53 $or$libresoc.v:140139$6270_Y + connect \$55 $or$libresoc.v:140140$6271_Y + connect \$57 $and$libresoc.v:140141$6272_Y + connect \$59 $or$libresoc.v:140142$6273_Y + connect \$61 $or$libresoc.v:140143$6274_Y + connect \$63 $or$libresoc.v:140144$6275_Y + connect \$65 $ternary$libresoc.v:140145$6276_Y + connect \$67 $ternary$libresoc.v:140146$6277_Y + connect \$69 $ternary$libresoc.v:140147$6278_Y + connect \$71 $ternary$libresoc.v:140148$6279_Y + connect \$74 $add$libresoc.v:140149$6280_Y + connect \$76 $and$libresoc.v:140150$6281_Y + connect \$78 $not$libresoc.v:140151$6282_Y + connect \$80 $and$libresoc.v:140152$6283_Y + connect \$82 $not$libresoc.v:140153$6284_Y + connect \$84 $and$libresoc.v:140154$6285_Y + connect \$86 $and$libresoc.v:140155$6286_Y + connect \$88 $and$libresoc.v:140156$6287_Y + connect \$8 $or$libresoc.v:140157$6288_Y + connect \$90 $or$libresoc.v:140158$6289_Y + connect \$93 $or$libresoc.v:140159$6290_Y + connect \$92 $not$libresoc.v:140160$6291_Y + connect \$96 $and$libresoc.v:140161$6292_Y + connect \$98 $not$libresoc.v:140162$6293_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 @@ -224810,271 +227309,271 @@ module \ldst0 connect \reset_o \$10 connect \reset_i \$8 end -attribute \src "libresoc.v:138902.1-139489.10" +attribute \src "libresoc.v:140688.1-141275.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:138903.7-138903.20" + attribute \src "libresoc.v:140689.7-140689.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $10\mask[9:9] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $11\mask[10:10] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $12\mask[11:11] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $13\mask[12:12] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $14\mask[13:13] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $15\mask[14:14] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $16\mask[15:15] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $17\mask[16:16] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $18\mask[17:17] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $19\mask[18:18] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $1\mask[0:0] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $20\mask[19:19] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $21\mask[20:20] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $22\mask[21:21] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $23\mask[22:22] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $24\mask[23:23] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $25\mask[24:24] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $26\mask[25:25] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $27\mask[26:26] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $28\mask[27:27] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $29\mask[28:28] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $2\mask[1:1] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $30\mask[29:29] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $31\mask[30:30] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $32\mask[31:31] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $33\mask[32:32] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $34\mask[33:33] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $35\mask[34:34] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $36\mask[35:35] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $37\mask[36:36] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $38\mask[37:37] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $39\mask[38:38] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $3\mask[2:2] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $40\mask[39:39] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $41\mask[40:40] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $42\mask[41:41] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $43\mask[42:42] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $44\mask[43:43] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $45\mask[44:44] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $46\mask[45:45] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $47\mask[46:46] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $48\mask[47:47] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $49\mask[48:48] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $4\mask[3:3] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $50\mask[49:49] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $51\mask[50:50] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $52\mask[51:51] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $53\mask[52:52] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $54\mask[53:53] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $55\mask[54:54] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $56\mask[55:55] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $57\mask[56:56] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $58\mask[57:57] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $59\mask[58:58] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $5\mask[4:4] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $60\mask[59:59] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $61\mask[60:60] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $62\mask[61:61] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $63\mask[62:62] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $64\mask[63:63] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $6\mask[5:5] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $7\mask[6:6] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $8\mask[7:7] - attribute \src "libresoc.v:139101.3-139488.6" + attribute \src "libresoc.v:140887.3-141274.6" wire $9\mask[8:8] - attribute \src "libresoc.v:139037.17-139037.96" - wire $gt$libresoc.v:139037$6433_Y - attribute \src "libresoc.v:139038.18-139038.98" - wire $gt$libresoc.v:139038$6434_Y - attribute \src "libresoc.v:139039.19-139039.99" - wire $gt$libresoc.v:139039$6435_Y - attribute \src "libresoc.v:139040.19-139040.99" - wire $gt$libresoc.v:139040$6436_Y - attribute \src "libresoc.v:139041.19-139041.99" - wire $gt$libresoc.v:139041$6437_Y - attribute \src "libresoc.v:139042.19-139042.99" - wire $gt$libresoc.v:139042$6438_Y - attribute \src "libresoc.v:139043.19-139043.99" - wire $gt$libresoc.v:139043$6439_Y - attribute \src "libresoc.v:139044.19-139044.99" - wire $gt$libresoc.v:139044$6440_Y - attribute \src "libresoc.v:139045.19-139045.99" - wire $gt$libresoc.v:139045$6441_Y - attribute \src "libresoc.v:139046.19-139046.99" - wire $gt$libresoc.v:139046$6442_Y - attribute \src "libresoc.v:139047.19-139047.99" - wire $gt$libresoc.v:139047$6443_Y - attribute \src "libresoc.v:139048.18-139048.97" - wire $gt$libresoc.v:139048$6444_Y - attribute \src "libresoc.v:139049.19-139049.99" - wire $gt$libresoc.v:139049$6445_Y - attribute \src "libresoc.v:139050.19-139050.99" - wire $gt$libresoc.v:139050$6446_Y - attribute \src "libresoc.v:139051.19-139051.99" - wire $gt$libresoc.v:139051$6447_Y - attribute \src "libresoc.v:139052.19-139052.99" - wire $gt$libresoc.v:139052$6448_Y - attribute \src "libresoc.v:139053.19-139053.99" - wire $gt$libresoc.v:139053$6449_Y - attribute \src "libresoc.v:139054.18-139054.97" - wire $gt$libresoc.v:139054$6450_Y - attribute \src "libresoc.v:139055.18-139055.97" - wire $gt$libresoc.v:139055$6451_Y - attribute \src "libresoc.v:139056.18-139056.97" - wire $gt$libresoc.v:139056$6452_Y - attribute \src "libresoc.v:139057.17-139057.96" - wire $gt$libresoc.v:139057$6453_Y - attribute \src "libresoc.v:139058.18-139058.97" - wire $gt$libresoc.v:139058$6454_Y - attribute \src "libresoc.v:139059.18-139059.97" - wire $gt$libresoc.v:139059$6455_Y - attribute \src "libresoc.v:139060.18-139060.97" - wire $gt$libresoc.v:139060$6456_Y - attribute \src "libresoc.v:139061.18-139061.97" - wire $gt$libresoc.v:139061$6457_Y - attribute \src "libresoc.v:139062.18-139062.97" - wire $gt$libresoc.v:139062$6458_Y - attribute \src "libresoc.v:139063.18-139063.97" - wire $gt$libresoc.v:139063$6459_Y - attribute \src "libresoc.v:139064.18-139064.97" - wire $gt$libresoc.v:139064$6460_Y - attribute \src "libresoc.v:139065.18-139065.98" - wire $gt$libresoc.v:139065$6461_Y - attribute \src "libresoc.v:139066.18-139066.98" - wire $gt$libresoc.v:139066$6462_Y - attribute \src "libresoc.v:139067.18-139067.98" - wire $gt$libresoc.v:139067$6463_Y - attribute \src "libresoc.v:139068.17-139068.96" - wire $gt$libresoc.v:139068$6464_Y - attribute \src "libresoc.v:139069.18-139069.98" - wire $gt$libresoc.v:139069$6465_Y - attribute \src "libresoc.v:139070.18-139070.98" - wire $gt$libresoc.v:139070$6466_Y - attribute \src "libresoc.v:139071.18-139071.98" - wire $gt$libresoc.v:139071$6467_Y - attribute \src "libresoc.v:139072.18-139072.98" - wire $gt$libresoc.v:139072$6468_Y - attribute \src "libresoc.v:139073.18-139073.98" - wire $gt$libresoc.v:139073$6469_Y - attribute \src "libresoc.v:139074.18-139074.98" - wire $gt$libresoc.v:139074$6470_Y - attribute \src "libresoc.v:139075.18-139075.98" - wire $gt$libresoc.v:139075$6471_Y - attribute \src "libresoc.v:139076.18-139076.98" - wire $gt$libresoc.v:139076$6472_Y - attribute \src "libresoc.v:139077.18-139077.98" - wire $gt$libresoc.v:139077$6473_Y - attribute \src "libresoc.v:139078.18-139078.98" - wire $gt$libresoc.v:139078$6474_Y - attribute \src "libresoc.v:139079.17-139079.96" - wire $gt$libresoc.v:139079$6475_Y - attribute \src "libresoc.v:139080.18-139080.98" - wire $gt$libresoc.v:139080$6476_Y - attribute \src "libresoc.v:139081.18-139081.98" - wire $gt$libresoc.v:139081$6477_Y - attribute \src "libresoc.v:139082.18-139082.98" - wire $gt$libresoc.v:139082$6478_Y - attribute \src "libresoc.v:139083.18-139083.98" - wire $gt$libresoc.v:139083$6479_Y - attribute \src "libresoc.v:139084.18-139084.98" - wire $gt$libresoc.v:139084$6480_Y - attribute \src "libresoc.v:139085.18-139085.98" - wire $gt$libresoc.v:139085$6481_Y - attribute \src "libresoc.v:139086.18-139086.98" - wire $gt$libresoc.v:139086$6482_Y - attribute \src "libresoc.v:139087.18-139087.98" - wire $gt$libresoc.v:139087$6483_Y - attribute \src "libresoc.v:139088.18-139088.98" - wire $gt$libresoc.v:139088$6484_Y - attribute \src "libresoc.v:139089.18-139089.98" - wire $gt$libresoc.v:139089$6485_Y - attribute \src "libresoc.v:139090.17-139090.96" - wire $gt$libresoc.v:139090$6486_Y - attribute \src "libresoc.v:139091.18-139091.98" - wire $gt$libresoc.v:139091$6487_Y - attribute \src "libresoc.v:139092.18-139092.98" - wire $gt$libresoc.v:139092$6488_Y - attribute \src "libresoc.v:139093.18-139093.98" - wire $gt$libresoc.v:139093$6489_Y - attribute \src "libresoc.v:139094.18-139094.98" - wire $gt$libresoc.v:139094$6490_Y - attribute \src "libresoc.v:139095.18-139095.98" - wire $gt$libresoc.v:139095$6491_Y - attribute \src "libresoc.v:139096.18-139096.98" - wire $gt$libresoc.v:139096$6492_Y - attribute \src "libresoc.v:139097.18-139097.98" - wire $gt$libresoc.v:139097$6493_Y - attribute \src "libresoc.v:139098.18-139098.98" - wire $gt$libresoc.v:139098$6494_Y - attribute \src "libresoc.v:139099.18-139099.98" - wire $gt$libresoc.v:139099$6495_Y - attribute \src "libresoc.v:139100.18-139100.98" - wire $gt$libresoc.v:139100$6496_Y + attribute \src "libresoc.v:140823.17-140823.96" + wire $gt$libresoc.v:140823$6478_Y + attribute \src "libresoc.v:140824.18-140824.98" + wire $gt$libresoc.v:140824$6479_Y + attribute \src "libresoc.v:140825.19-140825.99" + wire $gt$libresoc.v:140825$6480_Y + attribute \src "libresoc.v:140826.19-140826.99" + wire $gt$libresoc.v:140826$6481_Y + attribute \src "libresoc.v:140827.19-140827.99" + wire $gt$libresoc.v:140827$6482_Y + attribute \src "libresoc.v:140828.19-140828.99" + wire $gt$libresoc.v:140828$6483_Y + attribute \src "libresoc.v:140829.19-140829.99" + wire $gt$libresoc.v:140829$6484_Y + attribute \src "libresoc.v:140830.19-140830.99" + wire $gt$libresoc.v:140830$6485_Y + attribute \src "libresoc.v:140831.19-140831.99" + wire $gt$libresoc.v:140831$6486_Y + attribute \src "libresoc.v:140832.19-140832.99" + wire $gt$libresoc.v:140832$6487_Y + attribute \src "libresoc.v:140833.19-140833.99" + wire $gt$libresoc.v:140833$6488_Y + attribute \src "libresoc.v:140834.18-140834.97" + wire $gt$libresoc.v:140834$6489_Y + attribute \src "libresoc.v:140835.19-140835.99" + wire $gt$libresoc.v:140835$6490_Y + attribute \src "libresoc.v:140836.19-140836.99" + wire $gt$libresoc.v:140836$6491_Y + attribute \src "libresoc.v:140837.19-140837.99" + wire $gt$libresoc.v:140837$6492_Y + attribute \src "libresoc.v:140838.19-140838.99" + wire $gt$libresoc.v:140838$6493_Y + attribute \src "libresoc.v:140839.19-140839.99" + wire $gt$libresoc.v:140839$6494_Y + attribute \src "libresoc.v:140840.18-140840.97" + wire $gt$libresoc.v:140840$6495_Y + attribute \src "libresoc.v:140841.18-140841.97" + wire $gt$libresoc.v:140841$6496_Y + attribute \src "libresoc.v:140842.18-140842.97" + wire $gt$libresoc.v:140842$6497_Y + attribute \src "libresoc.v:140843.17-140843.96" + wire $gt$libresoc.v:140843$6498_Y + attribute \src "libresoc.v:140844.18-140844.97" + wire $gt$libresoc.v:140844$6499_Y + attribute \src "libresoc.v:140845.18-140845.97" + wire $gt$libresoc.v:140845$6500_Y + attribute \src "libresoc.v:140846.18-140846.97" + wire $gt$libresoc.v:140846$6501_Y + attribute \src "libresoc.v:140847.18-140847.97" + wire $gt$libresoc.v:140847$6502_Y + attribute \src "libresoc.v:140848.18-140848.97" + wire $gt$libresoc.v:140848$6503_Y + attribute \src "libresoc.v:140849.18-140849.97" + wire $gt$libresoc.v:140849$6504_Y + attribute \src "libresoc.v:140850.18-140850.97" + wire $gt$libresoc.v:140850$6505_Y + attribute \src "libresoc.v:140851.18-140851.98" + wire $gt$libresoc.v:140851$6506_Y + attribute \src "libresoc.v:140852.18-140852.98" + wire $gt$libresoc.v:140852$6507_Y + attribute \src "libresoc.v:140853.18-140853.98" + wire $gt$libresoc.v:140853$6508_Y + attribute \src "libresoc.v:140854.17-140854.96" + wire $gt$libresoc.v:140854$6509_Y + attribute \src "libresoc.v:140855.18-140855.98" + wire $gt$libresoc.v:140855$6510_Y + attribute \src "libresoc.v:140856.18-140856.98" + wire $gt$libresoc.v:140856$6511_Y + attribute \src "libresoc.v:140857.18-140857.98" + wire $gt$libresoc.v:140857$6512_Y + attribute \src "libresoc.v:140858.18-140858.98" + wire $gt$libresoc.v:140858$6513_Y + attribute \src "libresoc.v:140859.18-140859.98" + wire $gt$libresoc.v:140859$6514_Y + attribute \src "libresoc.v:140860.18-140860.98" + wire $gt$libresoc.v:140860$6515_Y + attribute \src "libresoc.v:140861.18-140861.98" + wire $gt$libresoc.v:140861$6516_Y + attribute \src "libresoc.v:140862.18-140862.98" + wire $gt$libresoc.v:140862$6517_Y + attribute \src "libresoc.v:140863.18-140863.98" + wire $gt$libresoc.v:140863$6518_Y + attribute \src "libresoc.v:140864.18-140864.98" + wire $gt$libresoc.v:140864$6519_Y + attribute \src "libresoc.v:140865.17-140865.96" + wire $gt$libresoc.v:140865$6520_Y + attribute \src "libresoc.v:140866.18-140866.98" + wire $gt$libresoc.v:140866$6521_Y + attribute \src "libresoc.v:140867.18-140867.98" + wire $gt$libresoc.v:140867$6522_Y + attribute \src "libresoc.v:140868.18-140868.98" + wire $gt$libresoc.v:140868$6523_Y + attribute \src "libresoc.v:140869.18-140869.98" + wire $gt$libresoc.v:140869$6524_Y + attribute \src "libresoc.v:140870.18-140870.98" + wire $gt$libresoc.v:140870$6525_Y + attribute \src "libresoc.v:140871.18-140871.98" + wire $gt$libresoc.v:140871$6526_Y + attribute \src "libresoc.v:140872.18-140872.98" + wire $gt$libresoc.v:140872$6527_Y + attribute \src "libresoc.v:140873.18-140873.98" + wire $gt$libresoc.v:140873$6528_Y + attribute \src "libresoc.v:140874.18-140874.98" + wire $gt$libresoc.v:140874$6529_Y + attribute \src "libresoc.v:140875.18-140875.98" + wire $gt$libresoc.v:140875$6530_Y + attribute \src "libresoc.v:140876.17-140876.96" + wire $gt$libresoc.v:140876$6531_Y + attribute \src "libresoc.v:140877.18-140877.98" + wire $gt$libresoc.v:140877$6532_Y + attribute \src "libresoc.v:140878.18-140878.98" + wire $gt$libresoc.v:140878$6533_Y + attribute \src "libresoc.v:140879.18-140879.98" + wire $gt$libresoc.v:140879$6534_Y + attribute \src "libresoc.v:140880.18-140880.98" + wire $gt$libresoc.v:140880$6535_Y + attribute \src "libresoc.v:140881.18-140881.98" + wire $gt$libresoc.v:140881$6536_Y + attribute \src "libresoc.v:140882.18-140882.98" + wire $gt$libresoc.v:140882$6537_Y + attribute \src "libresoc.v:140883.18-140883.98" + wire $gt$libresoc.v:140883$6538_Y + attribute \src "libresoc.v:140884.18-140884.98" + wire $gt$libresoc.v:140884$6539_Y + attribute \src "libresoc.v:140885.18-140885.98" + wire $gt$libresoc.v:140885$6540_Y + attribute \src "libresoc.v:140886.18-140886.98" + wire $gt$libresoc.v:140886$6541_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -225203,14 +227702,14 @@ module \left_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:138903.7-138903.15" + attribute \src "libresoc.v:140689.7-140689.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139037$6433 + cell $gt $gt$libresoc.v:140823$6478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225218,10 +227717,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:139037$6433_Y + connect \Y $gt$libresoc.v:140823$6478_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139038$6434 + cell $gt $gt$libresoc.v:140824$6479 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225229,10 +227728,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:139038$6434_Y + connect \Y $gt$libresoc.v:140824$6479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139039$6435 + cell $gt $gt$libresoc.v:140825$6480 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225240,10 +227739,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:139039$6435_Y + connect \Y $gt$libresoc.v:140825$6480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139040$6436 + cell $gt $gt$libresoc.v:140826$6481 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225251,10 +227750,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:139040$6436_Y + connect \Y $gt$libresoc.v:140826$6481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139041$6437 + cell $gt $gt$libresoc.v:140827$6482 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225262,10 +227761,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:139041$6437_Y + connect \Y $gt$libresoc.v:140827$6482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139042$6438 + cell $gt $gt$libresoc.v:140828$6483 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225273,10 +227772,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:139042$6438_Y + connect \Y $gt$libresoc.v:140828$6483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139043$6439 + cell $gt $gt$libresoc.v:140829$6484 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225284,10 +227783,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:139043$6439_Y + connect \Y $gt$libresoc.v:140829$6484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139044$6440 + cell $gt $gt$libresoc.v:140830$6485 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225295,10 +227794,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:139044$6440_Y + connect \Y $gt$libresoc.v:140830$6485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139045$6441 + cell $gt $gt$libresoc.v:140831$6486 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225306,10 +227805,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:139045$6441_Y + connect \Y $gt$libresoc.v:140831$6486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139046$6442 + cell $gt $gt$libresoc.v:140832$6487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225317,10 +227816,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:139046$6442_Y + connect \Y $gt$libresoc.v:140832$6487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139047$6443 + cell $gt $gt$libresoc.v:140833$6488 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225328,10 +227827,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:139047$6443_Y + connect \Y $gt$libresoc.v:140833$6488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139048$6444 + cell $gt $gt$libresoc.v:140834$6489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225339,10 +227838,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:139048$6444_Y + connect \Y $gt$libresoc.v:140834$6489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139049$6445 + cell $gt $gt$libresoc.v:140835$6490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225350,10 +227849,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:139049$6445_Y + connect \Y $gt$libresoc.v:140835$6490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139050$6446 + cell $gt $gt$libresoc.v:140836$6491 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225361,10 +227860,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:139050$6446_Y + connect \Y $gt$libresoc.v:140836$6491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139051$6447 + cell $gt $gt$libresoc.v:140837$6492 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225372,10 +227871,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:139051$6447_Y + connect \Y $gt$libresoc.v:140837$6492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139052$6448 + cell $gt $gt$libresoc.v:140838$6493 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225383,10 +227882,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:139052$6448_Y + connect \Y $gt$libresoc.v:140838$6493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139053$6449 + cell $gt $gt$libresoc.v:140839$6494 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225394,10 +227893,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:139053$6449_Y + connect \Y $gt$libresoc.v:140839$6494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139054$6450 + cell $gt $gt$libresoc.v:140840$6495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225405,10 +227904,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:139054$6450_Y + connect \Y $gt$libresoc.v:140840$6495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139055$6451 + cell $gt $gt$libresoc.v:140841$6496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225416,10 +227915,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:139055$6451_Y + connect \Y $gt$libresoc.v:140841$6496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139056$6452 + cell $gt $gt$libresoc.v:140842$6497 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225427,10 +227926,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:139056$6452_Y + connect \Y $gt$libresoc.v:140842$6497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139057$6453 + cell $gt $gt$libresoc.v:140843$6498 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225438,10 +227937,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:139057$6453_Y + connect \Y $gt$libresoc.v:140843$6498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139058$6454 + cell $gt $gt$libresoc.v:140844$6499 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225449,10 +227948,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:139058$6454_Y + connect \Y $gt$libresoc.v:140844$6499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139059$6455 + cell $gt $gt$libresoc.v:140845$6500 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225460,10 +227959,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:139059$6455_Y + connect \Y $gt$libresoc.v:140845$6500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139060$6456 + cell $gt $gt$libresoc.v:140846$6501 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225471,10 +227970,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:139060$6456_Y + connect \Y $gt$libresoc.v:140846$6501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139061$6457 + cell $gt $gt$libresoc.v:140847$6502 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225482,10 +227981,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:139061$6457_Y + connect \Y $gt$libresoc.v:140847$6502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139062$6458 + cell $gt $gt$libresoc.v:140848$6503 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225493,10 +227992,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:139062$6458_Y + connect \Y $gt$libresoc.v:140848$6503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139063$6459 + cell $gt $gt$libresoc.v:140849$6504 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225504,10 +228003,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:139063$6459_Y + connect \Y $gt$libresoc.v:140849$6504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139064$6460 + cell $gt $gt$libresoc.v:140850$6505 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225515,10 +228014,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:139064$6460_Y + connect \Y $gt$libresoc.v:140850$6505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139065$6461 + cell $gt $gt$libresoc.v:140851$6506 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225526,10 +228025,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:139065$6461_Y + connect \Y $gt$libresoc.v:140851$6506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139066$6462 + cell $gt $gt$libresoc.v:140852$6507 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225537,10 +228036,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:139066$6462_Y + connect \Y $gt$libresoc.v:140852$6507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139067$6463 + cell $gt $gt$libresoc.v:140853$6508 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225548,10 +228047,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:139067$6463_Y + connect \Y $gt$libresoc.v:140853$6508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139068$6464 + cell $gt $gt$libresoc.v:140854$6509 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225559,10 +228058,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:139068$6464_Y + connect \Y $gt$libresoc.v:140854$6509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139069$6465 + cell $gt $gt$libresoc.v:140855$6510 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225570,10 +228069,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:139069$6465_Y + connect \Y $gt$libresoc.v:140855$6510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139070$6466 + cell $gt $gt$libresoc.v:140856$6511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225581,10 +228080,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:139070$6466_Y + connect \Y $gt$libresoc.v:140856$6511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139071$6467 + cell $gt $gt$libresoc.v:140857$6512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225592,10 +228091,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:139071$6467_Y + connect \Y $gt$libresoc.v:140857$6512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139072$6468 + cell $gt $gt$libresoc.v:140858$6513 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225603,10 +228102,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:139072$6468_Y + connect \Y $gt$libresoc.v:140858$6513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139073$6469 + cell $gt $gt$libresoc.v:140859$6514 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225614,10 +228113,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:139073$6469_Y + connect \Y $gt$libresoc.v:140859$6514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139074$6470 + cell $gt $gt$libresoc.v:140860$6515 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225625,10 +228124,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:139074$6470_Y + connect \Y $gt$libresoc.v:140860$6515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139075$6471 + cell $gt $gt$libresoc.v:140861$6516 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225636,10 +228135,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:139075$6471_Y + connect \Y $gt$libresoc.v:140861$6516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139076$6472 + cell $gt $gt$libresoc.v:140862$6517 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225647,10 +228146,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:139076$6472_Y + connect \Y $gt$libresoc.v:140862$6517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139077$6473 + cell $gt $gt$libresoc.v:140863$6518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225658,10 +228157,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:139077$6473_Y + connect \Y $gt$libresoc.v:140863$6518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139078$6474 + cell $gt $gt$libresoc.v:140864$6519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225669,10 +228168,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:139078$6474_Y + connect \Y $gt$libresoc.v:140864$6519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139079$6475 + cell $gt $gt$libresoc.v:140865$6520 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225680,10 +228179,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:139079$6475_Y + connect \Y $gt$libresoc.v:140865$6520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139080$6476 + cell $gt $gt$libresoc.v:140866$6521 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225691,10 +228190,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:139080$6476_Y + connect \Y $gt$libresoc.v:140866$6521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139081$6477 + cell $gt $gt$libresoc.v:140867$6522 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225702,10 +228201,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:139081$6477_Y + connect \Y $gt$libresoc.v:140867$6522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139082$6478 + cell $gt $gt$libresoc.v:140868$6523 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225713,10 +228212,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:139082$6478_Y + connect \Y $gt$libresoc.v:140868$6523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139083$6479 + cell $gt $gt$libresoc.v:140869$6524 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225724,10 +228223,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:139083$6479_Y + connect \Y $gt$libresoc.v:140869$6524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139084$6480 + cell $gt $gt$libresoc.v:140870$6525 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225735,10 +228234,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:139084$6480_Y + connect \Y $gt$libresoc.v:140870$6525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139085$6481 + cell $gt $gt$libresoc.v:140871$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225746,10 +228245,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:139085$6481_Y + connect \Y $gt$libresoc.v:140871$6526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139086$6482 + cell $gt $gt$libresoc.v:140872$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225757,10 +228256,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:139086$6482_Y + connect \Y $gt$libresoc.v:140872$6527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139087$6483 + cell $gt $gt$libresoc.v:140873$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225768,10 +228267,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:139087$6483_Y + connect \Y $gt$libresoc.v:140873$6528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139088$6484 + cell $gt $gt$libresoc.v:140874$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225779,10 +228278,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:139088$6484_Y + connect \Y $gt$libresoc.v:140874$6529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139089$6485 + cell $gt $gt$libresoc.v:140875$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225790,10 +228289,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:139089$6485_Y + connect \Y $gt$libresoc.v:140875$6530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139090$6486 + cell $gt $gt$libresoc.v:140876$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225801,10 +228300,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:139090$6486_Y + connect \Y $gt$libresoc.v:140876$6531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139091$6487 + cell $gt $gt$libresoc.v:140877$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225812,10 +228311,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:139091$6487_Y + connect \Y $gt$libresoc.v:140877$6532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139092$6488 + cell $gt $gt$libresoc.v:140878$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225823,10 +228322,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:139092$6488_Y + connect \Y $gt$libresoc.v:140878$6533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139093$6489 + cell $gt $gt$libresoc.v:140879$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225834,10 +228333,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:139093$6489_Y + connect \Y $gt$libresoc.v:140879$6534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139094$6490 + cell $gt $gt$libresoc.v:140880$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225845,10 +228344,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:139094$6490_Y + connect \Y $gt$libresoc.v:140880$6535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139095$6491 + cell $gt $gt$libresoc.v:140881$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225856,10 +228355,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:139095$6491_Y + connect \Y $gt$libresoc.v:140881$6536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139096$6492 + cell $gt $gt$libresoc.v:140882$6537 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225867,10 +228366,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:139096$6492_Y + connect \Y $gt$libresoc.v:140882$6537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139097$6493 + cell $gt $gt$libresoc.v:140883$6538 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225878,10 +228377,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:139097$6493_Y + connect \Y $gt$libresoc.v:140883$6538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139098$6494 + cell $gt $gt$libresoc.v:140884$6539 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225889,10 +228388,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:139098$6494_Y + connect \Y $gt$libresoc.v:140884$6539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139099$6495 + cell $gt $gt$libresoc.v:140885$6540 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225900,10 +228399,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:139099$6495_Y + connect \Y $gt$libresoc.v:140885$6540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:139100$6496 + cell $gt $gt$libresoc.v:140886$6541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225911,18 +228410,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:139100$6496_Y + connect \Y $gt$libresoc.v:140886$6541_Y end - attribute \src "libresoc.v:138903.7-138903.20" - process $proc$libresoc.v:138903$6498 + attribute \src "libresoc.v:140689.7-140689.20" + process $proc$libresoc.v:140689$6543 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139101.3-139488.6" - process $proc$libresoc.v:139101$6497 + attribute \src "libresoc.v:140887.3-141274.6" + process $proc$libresoc.v:140887$6542 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -225989,9 +228488,9 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:139102.5-139102.29" + attribute \src "libresoc.v:140888.5-140888.29" switch \initial - attribute \src "libresoc.v:139102.9-139102.17" + attribute \src "libresoc.v:140888.9-140888.17" case 1'1 case end @@ -226574,86 +229073,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:139037$6433_Y - connect \$99 $gt$libresoc.v:139038$6434_Y - connect \$101 $gt$libresoc.v:139039$6435_Y - connect \$103 $gt$libresoc.v:139040$6436_Y - connect \$105 $gt$libresoc.v:139041$6437_Y - connect \$107 $gt$libresoc.v:139042$6438_Y - connect \$109 $gt$libresoc.v:139043$6439_Y - connect \$111 $gt$libresoc.v:139044$6440_Y - connect \$113 $gt$libresoc.v:139045$6441_Y - connect \$115 $gt$libresoc.v:139046$6442_Y - connect \$117 $gt$libresoc.v:139047$6443_Y - connect \$11 $gt$libresoc.v:139048$6444_Y - connect \$119 $gt$libresoc.v:139049$6445_Y - connect \$121 $gt$libresoc.v:139050$6446_Y - connect \$123 $gt$libresoc.v:139051$6447_Y - connect \$125 $gt$libresoc.v:139052$6448_Y - connect \$127 $gt$libresoc.v:139053$6449_Y - connect \$13 $gt$libresoc.v:139054$6450_Y - connect \$15 $gt$libresoc.v:139055$6451_Y - connect \$17 $gt$libresoc.v:139056$6452_Y - connect \$1 $gt$libresoc.v:139057$6453_Y - connect \$19 $gt$libresoc.v:139058$6454_Y - connect \$21 $gt$libresoc.v:139059$6455_Y - connect \$23 $gt$libresoc.v:139060$6456_Y - connect \$25 $gt$libresoc.v:139061$6457_Y - connect \$27 $gt$libresoc.v:139062$6458_Y - connect \$29 $gt$libresoc.v:139063$6459_Y - connect \$31 $gt$libresoc.v:139064$6460_Y - connect \$33 $gt$libresoc.v:139065$6461_Y - connect \$35 $gt$libresoc.v:139066$6462_Y - connect \$37 $gt$libresoc.v:139067$6463_Y - connect \$3 $gt$libresoc.v:139068$6464_Y - connect \$39 $gt$libresoc.v:139069$6465_Y - connect \$41 $gt$libresoc.v:139070$6466_Y - connect \$43 $gt$libresoc.v:139071$6467_Y - connect \$45 $gt$libresoc.v:139072$6468_Y - connect \$47 $gt$libresoc.v:139073$6469_Y - connect \$49 $gt$libresoc.v:139074$6470_Y - connect \$51 $gt$libresoc.v:139075$6471_Y - connect \$53 $gt$libresoc.v:139076$6472_Y - connect \$55 $gt$libresoc.v:139077$6473_Y - connect \$57 $gt$libresoc.v:139078$6474_Y - connect \$5 $gt$libresoc.v:139079$6475_Y - connect \$59 $gt$libresoc.v:139080$6476_Y - connect \$61 $gt$libresoc.v:139081$6477_Y - connect \$63 $gt$libresoc.v:139082$6478_Y - connect \$65 $gt$libresoc.v:139083$6479_Y - connect \$67 $gt$libresoc.v:139084$6480_Y - connect \$69 $gt$libresoc.v:139085$6481_Y - connect \$71 $gt$libresoc.v:139086$6482_Y - connect \$73 $gt$libresoc.v:139087$6483_Y - connect \$75 $gt$libresoc.v:139088$6484_Y - connect \$77 $gt$libresoc.v:139089$6485_Y - connect \$7 $gt$libresoc.v:139090$6486_Y - connect \$79 $gt$libresoc.v:139091$6487_Y - connect \$81 $gt$libresoc.v:139092$6488_Y - connect \$83 $gt$libresoc.v:139093$6489_Y - connect \$85 $gt$libresoc.v:139094$6490_Y - connect \$87 $gt$libresoc.v:139095$6491_Y - connect \$89 $gt$libresoc.v:139096$6492_Y - connect \$91 $gt$libresoc.v:139097$6493_Y - connect \$93 $gt$libresoc.v:139098$6494_Y - connect \$95 $gt$libresoc.v:139099$6495_Y - connect \$97 $gt$libresoc.v:139100$6496_Y + connect \$9 $gt$libresoc.v:140823$6478_Y + connect \$99 $gt$libresoc.v:140824$6479_Y + connect \$101 $gt$libresoc.v:140825$6480_Y + connect \$103 $gt$libresoc.v:140826$6481_Y + connect \$105 $gt$libresoc.v:140827$6482_Y + connect \$107 $gt$libresoc.v:140828$6483_Y + connect \$109 $gt$libresoc.v:140829$6484_Y + connect \$111 $gt$libresoc.v:140830$6485_Y + connect \$113 $gt$libresoc.v:140831$6486_Y + connect \$115 $gt$libresoc.v:140832$6487_Y + connect \$117 $gt$libresoc.v:140833$6488_Y + connect \$11 $gt$libresoc.v:140834$6489_Y + connect \$119 $gt$libresoc.v:140835$6490_Y + connect \$121 $gt$libresoc.v:140836$6491_Y + connect \$123 $gt$libresoc.v:140837$6492_Y + connect \$125 $gt$libresoc.v:140838$6493_Y + connect \$127 $gt$libresoc.v:140839$6494_Y + connect \$13 $gt$libresoc.v:140840$6495_Y + connect \$15 $gt$libresoc.v:140841$6496_Y + connect \$17 $gt$libresoc.v:140842$6497_Y + connect \$1 $gt$libresoc.v:140843$6498_Y + connect \$19 $gt$libresoc.v:140844$6499_Y + connect \$21 $gt$libresoc.v:140845$6500_Y + connect \$23 $gt$libresoc.v:140846$6501_Y + connect \$25 $gt$libresoc.v:140847$6502_Y + connect \$27 $gt$libresoc.v:140848$6503_Y + connect \$29 $gt$libresoc.v:140849$6504_Y + connect \$31 $gt$libresoc.v:140850$6505_Y + connect \$33 $gt$libresoc.v:140851$6506_Y + connect \$35 $gt$libresoc.v:140852$6507_Y + connect \$37 $gt$libresoc.v:140853$6508_Y + connect \$3 $gt$libresoc.v:140854$6509_Y + connect \$39 $gt$libresoc.v:140855$6510_Y + connect \$41 $gt$libresoc.v:140856$6511_Y + connect \$43 $gt$libresoc.v:140857$6512_Y + connect \$45 $gt$libresoc.v:140858$6513_Y + connect \$47 $gt$libresoc.v:140859$6514_Y + connect \$49 $gt$libresoc.v:140860$6515_Y + connect \$51 $gt$libresoc.v:140861$6516_Y + connect \$53 $gt$libresoc.v:140862$6517_Y + connect \$55 $gt$libresoc.v:140863$6518_Y + connect \$57 $gt$libresoc.v:140864$6519_Y + connect \$5 $gt$libresoc.v:140865$6520_Y + connect \$59 $gt$libresoc.v:140866$6521_Y + connect \$61 $gt$libresoc.v:140867$6522_Y + connect \$63 $gt$libresoc.v:140868$6523_Y + connect \$65 $gt$libresoc.v:140869$6524_Y + connect \$67 $gt$libresoc.v:140870$6525_Y + connect \$69 $gt$libresoc.v:140871$6526_Y + connect \$71 $gt$libresoc.v:140872$6527_Y + connect \$73 $gt$libresoc.v:140873$6528_Y + connect \$75 $gt$libresoc.v:140874$6529_Y + connect \$77 $gt$libresoc.v:140875$6530_Y + connect \$7 $gt$libresoc.v:140876$6531_Y + connect \$79 $gt$libresoc.v:140877$6532_Y + connect \$81 $gt$libresoc.v:140878$6533_Y + connect \$83 $gt$libresoc.v:140879$6534_Y + connect \$85 $gt$libresoc.v:140880$6535_Y + connect \$87 $gt$libresoc.v:140881$6536_Y + connect \$89 $gt$libresoc.v:140882$6537_Y + connect \$91 $gt$libresoc.v:140883$6538_Y + connect \$93 $gt$libresoc.v:140884$6539_Y + connect \$95 $gt$libresoc.v:140885$6540_Y + connect \$97 $gt$libresoc.v:140886$6541_Y end -attribute \src "libresoc.v:139493.1-139522.10" +attribute \src "libresoc.v:141279.1-141308.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:139517.17-139517.101" - wire width 64 $extend$libresoc.v:139517$6502_Y - attribute \src "libresoc.v:139517.17-139517.101" - wire width 64 $pos$libresoc.v:139517$6503_Y - attribute \src "libresoc.v:139514.17-139514.111" - wire width 20 $sshl$libresoc.v:139514$6499_Y - attribute \src "libresoc.v:139516.17-139516.113" - wire width 32 $sshl$libresoc.v:139516$6501_Y - attribute \src "libresoc.v:139515.17-139515.107" - wire width 21 $sub$libresoc.v:139515$6500_Y + attribute \src "libresoc.v:141303.17-141303.101" + wire width 64 $extend$libresoc.v:141303$6547_Y + attribute \src "libresoc.v:141303.17-141303.101" + wire width 64 $pos$libresoc.v:141303$6548_Y + attribute \src "libresoc.v:141300.17-141300.111" + wire width 20 $sshl$libresoc.v:141300$6544_Y + attribute \src "libresoc.v:141302.17-141302.113" + wire width 32 $sshl$libresoc.v:141302$6546_Y + attribute \src "libresoc.v:141301.17-141301.107" + wire width 21 $sub$libresoc.v:141301$6545_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -226675,23 +229174,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:139517$6502 + cell $pos $extend$libresoc.v:141303$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:139517$6502_Y + connect \Y $extend$libresoc.v:141303$6547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:139517$6503 + cell $pos $pos$libresoc.v:141303$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139517$6502_Y - connect \Y $pos$libresoc.v:139517$6503_Y + connect \A $extend$libresoc.v:141303$6547_Y + connect \Y $pos$libresoc.v:141303$6548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:139514$6499 + cell $sshl $sshl$libresoc.v:141300$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -226699,10 +229198,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:139514$6499_Y + connect \Y $sshl$libresoc.v:141300$6544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:139516$6501 + cell $sshl $sshl$libresoc.v:141302$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -226710,10 +229209,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:139516$6501_Y + connect \Y $sshl$libresoc.v:141302$6546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:139515$6500 + cell $sub $sub$libresoc.v:141301$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -226721,48 +229220,48 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:139515$6500_Y + connect \Y $sub$libresoc.v:141301$6545_Y end - connect \$2 $sshl$libresoc.v:139514$6499_Y - connect \$4 $sub$libresoc.v:139515$6500_Y - connect \$7 $sshl$libresoc.v:139516$6501_Y - connect \$6 $pos$libresoc.v:139517$6503_Y + connect \$2 $sshl$libresoc.v:141300$6544_Y + connect \$4 $sub$libresoc.v:141301$6545_Y + connect \$7 $sshl$libresoc.v:141302$6546_Y + connect \$6 $pos$libresoc.v:141303$6548_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:139526.1-139584.10" +attribute \src "libresoc.v:141312.1-141370.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:139527.7-139527.20" + attribute \src "libresoc.v:141313.7-141313.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139572.3-139580.6" - wire $0\q_int$next[0:0]$6514 - attribute \src "libresoc.v:139570.3-139571.27" + attribute \src "libresoc.v:141358.3-141366.6" + wire $0\q_int$next[0:0]$6559 + attribute \src "libresoc.v:141356.3-141357.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:139572.3-139580.6" - wire $1\q_int$next[0:0]$6515 - attribute \src "libresoc.v:139549.7-139549.19" + attribute \src "libresoc.v:141358.3-141366.6" + wire $1\q_int$next[0:0]$6560 + attribute \src "libresoc.v:141335.7-141335.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:139562.17-139562.96" - wire $and$libresoc.v:139562$6504_Y - attribute \src "libresoc.v:139567.17-139567.96" - wire $and$libresoc.v:139567$6509_Y - attribute \src "libresoc.v:139564.18-139564.93" - wire $not$libresoc.v:139564$6506_Y - attribute \src "libresoc.v:139566.17-139566.92" - wire $not$libresoc.v:139566$6508_Y - attribute \src "libresoc.v:139569.17-139569.92" - wire $not$libresoc.v:139569$6511_Y - attribute \src "libresoc.v:139563.18-139563.98" - wire $or$libresoc.v:139563$6505_Y - attribute \src "libresoc.v:139565.18-139565.99" - wire $or$libresoc.v:139565$6507_Y - attribute \src "libresoc.v:139568.17-139568.97" - wire $or$libresoc.v:139568$6510_Y + attribute \src "libresoc.v:141348.17-141348.96" + wire $and$libresoc.v:141348$6549_Y + attribute \src "libresoc.v:141353.17-141353.96" + wire $and$libresoc.v:141353$6554_Y + attribute \src "libresoc.v:141350.18-141350.93" + wire $not$libresoc.v:141350$6551_Y + attribute \src "libresoc.v:141352.17-141352.92" + wire $not$libresoc.v:141352$6553_Y + attribute \src "libresoc.v:141355.17-141355.92" + wire $not$libresoc.v:141355$6556_Y + attribute \src "libresoc.v:141349.18-141349.98" + wire $or$libresoc.v:141349$6550_Y + attribute \src "libresoc.v:141351.18-141351.99" + wire $or$libresoc.v:141351$6552_Y + attribute \src "libresoc.v:141354.17-141354.97" + wire $or$libresoc.v:141354$6555_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -226779,11 +229278,11 @@ module \lod_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:139527.7-139527.15" + attribute \src "libresoc.v:141313.7-141313.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -226800,7 +229299,7 @@ module \lod_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:139562$6504 + cell $and $and$libresoc.v:141348$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226808,10 +229307,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:139562$6504_Y + connect \Y $and$libresoc.v:141348$6549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:139567$6509 + cell $and $and$libresoc.v:141353$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226819,34 +229318,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:139567$6509_Y + connect \Y $and$libresoc.v:141353$6554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:139564$6506 + cell $not $not$libresoc.v:141350$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:139564$6506_Y + connect \Y $not$libresoc.v:141350$6551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:139566$6508 + cell $not $not$libresoc.v:141352$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:139566$6508_Y + connect \Y $not$libresoc.v:141352$6553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:139569$6511 + cell $not $not$libresoc.v:141355$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:139569$6511_Y + connect \Y $not$libresoc.v:141355$6556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:139563$6505 + cell $or $or$libresoc.v:141349$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226854,10 +229353,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:139563$6505_Y + connect \Y $or$libresoc.v:141349$6550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:139565$6507 + cell $or $or$libresoc.v:141351$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226865,10 +229364,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:139565$6507_Y + connect \Y $or$libresoc.v:141351$6552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:139568$6510 + cell $or $or$libresoc.v:141354$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -226876,39 +229375,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:139568$6510_Y + connect \Y $or$libresoc.v:141354$6555_Y end - attribute \src "libresoc.v:139527.7-139527.20" - process $proc$libresoc.v:139527$6516 + attribute \src "libresoc.v:141313.7-141313.20" + process $proc$libresoc.v:141313$6561 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139549.7-139549.19" - process $proc$libresoc.v:139549$6517 + attribute \src "libresoc.v:141335.7-141335.19" + process $proc$libresoc.v:141335$6562 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:139570.3-139571.27" - process $proc$libresoc.v:139570$6512 + attribute \src "libresoc.v:141356.3-141357.27" + process $proc$libresoc.v:141356$6557 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:139572.3-139580.6" - process $proc$libresoc.v:139572$6513 + attribute \src "libresoc.v:141358.3-141366.6" + process $proc$libresoc.v:141358$6558 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6514 $1\q_int$next[0:0]$6515 - attribute \src "libresoc.v:139573.5-139573.29" + assign $0\q_int$next[0:0]$6559 $1\q_int$next[0:0]$6560 + attribute \src "libresoc.v:141359.5-141359.29" switch \initial - attribute \src "libresoc.v:139573.9-139573.17" + attribute \src "libresoc.v:141359.9-141359.17" case 1'1 case end @@ -226917,494 +229416,494 @@ module \lod_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6515 1'0 + assign $1\q_int$next[0:0]$6560 1'0 case - assign $1\q_int$next[0:0]$6515 \$5 + assign $1\q_int$next[0:0]$6560 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6514 + update \q_int$next $0\q_int$next[0:0]$6559 end - connect \$9 $and$libresoc.v:139562$6504_Y - connect \$11 $or$libresoc.v:139563$6505_Y - connect \$13 $not$libresoc.v:139564$6506_Y - connect \$15 $or$libresoc.v:139565$6507_Y - connect \$1 $not$libresoc.v:139566$6508_Y - connect \$3 $and$libresoc.v:139567$6509_Y - connect \$5 $or$libresoc.v:139568$6510_Y - connect \$7 $not$libresoc.v:139569$6511_Y + connect \$9 $and$libresoc.v:141348$6549_Y + connect \$11 $or$libresoc.v:141349$6550_Y + connect \$13 $not$libresoc.v:141350$6551_Y + connect \$15 $or$libresoc.v:141351$6552_Y + connect \$1 $not$libresoc.v:141352$6553_Y + connect \$3 $and$libresoc.v:141353$6554_Y + connect \$5 $or$libresoc.v:141354$6555_Y + connect \$7 $not$libresoc.v:141355$6556_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:139588.1-140704.10" +attribute \src "libresoc.v:141374.1-142494.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:140329.3-140330.24" + attribute \src "libresoc.v:142119.3-142120.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:140327.3-140328.44" + attribute \src "libresoc.v:142117.3-142118.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:140634.3-140642.6" - wire $0\alu_l_r_alu$next[0:0]$6718 - attribute \src "libresoc.v:140251.3-140252.39" + attribute \src "libresoc.v:142424.3-142432.6" + wire $0\alu_l_r_alu$next[0:0]$6763 + attribute \src "libresoc.v:142041.3-142042.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6647 - attribute \src "libresoc.v:140301.3-140302.83" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6692 + attribute \src "libresoc.v:142091.3-142092.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 13 $0\alu_logical0_logical_op__fn_unit$next[12:0]$6648 - attribute \src "libresoc.v:140271.3-140272.81" - wire width 13 $0\alu_logical0_logical_op__fn_unit[12:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6649 - attribute \src "libresoc.v:140273.3-140274.95" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 + attribute \src "libresoc.v:142061.3-142062.81" + wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:142302.3-142340.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 + attribute \src "libresoc.v:142063.3-142064.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6650 - attribute \src "libresoc.v:140275.3-140276.91" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 + attribute \src "libresoc.v:142065.3-142066.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6651 - attribute \src "libresoc.v:140289.3-140290.89" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 + attribute \src "libresoc.v:142079.3-142080.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6652 - attribute \src "libresoc.v:140303.3-140304.75" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6697 + attribute \src "libresoc.v:142093.3-142094.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6653 - attribute \src "libresoc.v:140269.3-140270.85" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 + attribute \src "libresoc.v:142059.3-142060.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6654 - attribute \src "libresoc.v:140285.3-140286.85" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 + attribute \src "libresoc.v:142075.3-142076.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6655 - attribute \src "libresoc.v:140291.3-140292.87" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 + attribute \src "libresoc.v:142081.3-142082.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6656 - attribute \src "libresoc.v:140297.3-140298.83" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 + attribute \src "libresoc.v:142087.3-142088.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6657 - attribute \src "libresoc.v:140299.3-140300.85" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 + attribute \src "libresoc.v:142089.3-142090.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6658 - attribute \src "libresoc.v:140281.3-140282.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 + attribute \src "libresoc.v:142071.3-142072.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6659 - attribute \src "libresoc.v:140283.3-140284.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 + attribute \src "libresoc.v:142073.3-142074.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6660 - attribute \src "libresoc.v:140295.3-140296.91" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 + attribute \src "libresoc.v:142085.3-142086.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6661 - attribute \src "libresoc.v:140279.3-140280.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 + attribute \src "libresoc.v:142069.3-142070.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6662 - attribute \src "libresoc.v:140277.3-140278.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 + attribute \src "libresoc.v:142067.3-142068.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6663 - attribute \src "libresoc.v:140293.3-140294.85" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 + attribute \src "libresoc.v:142083.3-142084.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6664 - attribute \src "libresoc.v:140287.3-140288.79" + attribute \src "libresoc.v:142302.3-142340.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 + attribute \src "libresoc.v:142077.3-142078.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:140625.3-140633.6" - wire $0\alui_l_r_alui$next[0:0]$6715 - attribute \src "libresoc.v:140253.3-140254.43" + attribute \src "libresoc.v:142415.3-142423.6" + wire $0\alui_l_r_alui$next[0:0]$6760 + attribute \src "libresoc.v:142043.3-142044.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:140551.3-140572.6" - wire width 64 $0\data_r0__o$next[63:0]$6690 - attribute \src "libresoc.v:140265.3-140266.37" + attribute \src "libresoc.v:142341.3-142362.6" + wire width 64 $0\data_r0__o$next[63:0]$6735 + attribute \src "libresoc.v:142055.3-142056.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:140551.3-140572.6" - wire $0\data_r0__o_ok$next[0:0]$6691 - attribute \src "libresoc.v:140267.3-140268.43" + attribute \src "libresoc.v:142341.3-142362.6" + wire $0\data_r0__o_ok$next[0:0]$6736 + attribute \src "libresoc.v:142057.3-142058.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:140573.3-140594.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6698 - attribute \src "libresoc.v:140261.3-140262.43" + attribute \src "libresoc.v:142363.3-142384.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6743 + attribute \src "libresoc.v:142051.3-142052.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:140573.3-140594.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6699 - attribute \src "libresoc.v:140263.3-140264.49" + attribute \src "libresoc.v:142363.3-142384.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6744 + attribute \src "libresoc.v:142053.3-142054.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:140643.3-140652.6" + attribute \src "libresoc.v:142433.3-142442.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:140653.3-140662.6" + attribute \src "libresoc.v:142443.3-142452.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:139589.7-139589.20" + attribute \src "libresoc.v:141375.7-141375.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140467.3-140475.6" - wire $0\opc_l_r_opc$next[0:0]$6632 - attribute \src "libresoc.v:140313.3-140314.39" + attribute \src "libresoc.v:142257.3-142265.6" + wire $0\opc_l_r_opc$next[0:0]$6677 + attribute \src "libresoc.v:142103.3-142104.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140458.3-140466.6" - wire $0\opc_l_s_opc$next[0:0]$6629 - attribute \src "libresoc.v:140315.3-140316.39" + attribute \src "libresoc.v:142248.3-142256.6" + wire $0\opc_l_s_opc$next[0:0]$6674 + attribute \src "libresoc.v:142105.3-142106.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:140663.3-140671.6" - wire width 2 $0\prev_wr_go$next[1:0]$6723 - attribute \src "libresoc.v:140325.3-140326.37" + attribute \src "libresoc.v:142453.3-142461.6" + wire width 2 $0\prev_wr_go$next[1:0]$6768 + attribute \src "libresoc.v:142115.3-142116.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:140412.3-140421.6" + attribute \src "libresoc.v:142202.3-142211.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:140503.3-140511.6" - wire width 2 $0\req_l_r_req$next[1:0]$6644 - attribute \src "libresoc.v:140305.3-140306.39" + attribute \src "libresoc.v:142293.3-142301.6" + wire width 2 $0\req_l_r_req$next[1:0]$6689 + attribute \src "libresoc.v:142095.3-142096.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:140494.3-140502.6" - wire width 2 $0\req_l_s_req$next[1:0]$6641 - attribute \src "libresoc.v:140307.3-140308.39" + attribute \src "libresoc.v:142284.3-142292.6" + wire width 2 $0\req_l_s_req$next[1:0]$6686 + attribute \src "libresoc.v:142097.3-142098.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:140431.3-140439.6" - wire $0\rok_l_r_rdok$next[0:0]$6620 - attribute \src "libresoc.v:140321.3-140322.41" + attribute \src "libresoc.v:142221.3-142229.6" + wire $0\rok_l_r_rdok$next[0:0]$6665 + attribute \src "libresoc.v:142111.3-142112.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:140422.3-140430.6" - wire $0\rok_l_s_rdok$next[0:0]$6617 - attribute \src "libresoc.v:140323.3-140324.41" + attribute \src "libresoc.v:142212.3-142220.6" + wire $0\rok_l_s_rdok$next[0:0]$6662 + attribute \src "libresoc.v:142113.3-142114.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:140449.3-140457.6" - wire $0\rst_l_r_rst$next[0:0]$6626 - attribute \src "libresoc.v:140317.3-140318.39" + attribute \src "libresoc.v:142239.3-142247.6" + wire $0\rst_l_r_rst$next[0:0]$6671 + attribute \src "libresoc.v:142107.3-142108.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:140440.3-140448.6" - wire $0\rst_l_s_rst$next[0:0]$6623 - attribute \src "libresoc.v:140319.3-140320.39" + attribute \src "libresoc.v:142230.3-142238.6" + wire $0\rst_l_s_rst$next[0:0]$6668 + attribute \src "libresoc.v:142109.3-142110.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:140485.3-140493.6" - wire width 3 $0\src_l_r_src$next[2:0]$6638 - attribute \src "libresoc.v:140309.3-140310.39" + attribute \src "libresoc.v:142275.3-142283.6" + wire width 3 $0\src_l_r_src$next[2:0]$6683 + attribute \src "libresoc.v:142099.3-142100.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:140476.3-140484.6" - wire width 3 $0\src_l_s_src$next[2:0]$6635 - attribute \src "libresoc.v:140311.3-140312.39" + attribute \src "libresoc.v:142266.3-142274.6" + wire width 3 $0\src_l_s_src$next[2:0]$6680 + attribute \src "libresoc.v:142101.3-142102.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:140595.3-140604.6" - wire width 64 $0\src_r0$next[63:0]$6706 - attribute \src "libresoc.v:140259.3-140260.29" + attribute \src "libresoc.v:142385.3-142394.6" + wire width 64 $0\src_r0$next[63:0]$6751 + attribute \src "libresoc.v:142049.3-142050.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:140605.3-140614.6" - wire width 64 $0\src_r1$next[63:0]$6709 - attribute \src "libresoc.v:140257.3-140258.29" + attribute \src "libresoc.v:142395.3-142404.6" + wire width 64 $0\src_r1$next[63:0]$6754 + attribute \src "libresoc.v:142047.3-142048.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:140615.3-140624.6" - wire $0\src_r2$next[0:0]$6712 - attribute \src "libresoc.v:140255.3-140256.29" + attribute \src "libresoc.v:142405.3-142414.6" + wire $0\src_r2$next[0:0]$6757 + attribute \src "libresoc.v:142045.3-142046.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:139707.7-139707.24" + attribute \src "libresoc.v:141493.7-141493.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:139717.7-139717.26" + attribute \src "libresoc.v:141503.7-141503.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:140634.3-140642.6" - wire $1\alu_l_r_alu$next[0:0]$6719 - attribute \src "libresoc.v:139725.7-139725.25" + attribute \src "libresoc.v:142424.3-142432.6" + wire $1\alu_l_r_alu$next[0:0]$6764 + attribute \src "libresoc.v:141511.7-141511.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6665 - attribute \src "libresoc.v:139733.13-139733.53" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 + attribute \src "libresoc.v:141519.13-141519.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 13 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6666 - attribute \src "libresoc.v:139751.14-139751.57" - wire width 13 $1\alu_logical0_logical_op__fn_unit[12:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6667 - attribute \src "libresoc.v:139755.14-139755.76" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 + attribute \src "libresoc.v:141538.14-141538.57" + wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] + attribute \src "libresoc.v:142302.3-142340.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 + attribute \src "libresoc.v:141542.14-141542.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6668 - attribute \src "libresoc.v:139759.7-139759.51" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 + attribute \src "libresoc.v:141546.7-141546.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6669 - attribute \src "libresoc.v:139767.13-139767.56" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 + attribute \src "libresoc.v:141554.13-141554.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6670 - attribute \src "libresoc.v:139771.14-139771.51" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6715 + attribute \src "libresoc.v:141558.14-141558.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6671 - attribute \src "libresoc.v:139849.13-139849.55" + attribute \src "libresoc.v:142302.3-142340.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 + attribute \src "libresoc.v:141637.13-141637.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6672 - attribute \src "libresoc.v:139853.7-139853.48" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 + attribute \src "libresoc.v:141641.7-141641.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6673 - attribute \src "libresoc.v:139857.7-139857.49" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 + attribute \src "libresoc.v:141645.7-141645.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6674 - attribute \src "libresoc.v:139861.7-139861.47" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 + attribute \src "libresoc.v:141649.7-141649.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6675 - attribute \src "libresoc.v:139865.7-139865.48" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 + attribute \src "libresoc.v:141653.7-141653.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6676 - attribute \src "libresoc.v:139869.7-139869.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 + attribute \src "libresoc.v:141657.7-141657.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6677 - attribute \src "libresoc.v:139873.7-139873.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 + attribute \src "libresoc.v:141661.7-141661.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6678 - attribute \src "libresoc.v:139877.7-139877.51" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 + attribute \src "libresoc.v:141665.7-141665.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6679 - attribute \src "libresoc.v:139881.7-139881.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 + attribute \src "libresoc.v:141669.7-141669.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6680 - attribute \src "libresoc.v:139885.7-139885.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 + attribute \src "libresoc.v:141673.7-141673.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6681 - attribute \src "libresoc.v:139889.7-139889.48" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 + attribute \src "libresoc.v:141677.7-141677.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6682 - attribute \src "libresoc.v:139893.7-139893.45" + attribute \src "libresoc.v:142302.3-142340.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 + attribute \src "libresoc.v:141681.7-141681.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:140625.3-140633.6" - wire $1\alui_l_r_alui$next[0:0]$6716 - attribute \src "libresoc.v:139919.7-139919.27" + attribute \src "libresoc.v:142415.3-142423.6" + wire $1\alui_l_r_alui$next[0:0]$6761 + attribute \src "libresoc.v:141707.7-141707.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:140551.3-140572.6" - wire width 64 $1\data_r0__o$next[63:0]$6692 - attribute \src "libresoc.v:139953.14-139953.47" + attribute \src "libresoc.v:142341.3-142362.6" + wire width 64 $1\data_r0__o$next[63:0]$6737 + attribute \src "libresoc.v:141741.14-141741.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:140551.3-140572.6" - wire $1\data_r0__o_ok$next[0:0]$6693 - attribute \src "libresoc.v:139957.7-139957.27" + attribute \src "libresoc.v:142341.3-142362.6" + wire $1\data_r0__o_ok$next[0:0]$6738 + attribute \src "libresoc.v:141745.7-141745.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:140573.3-140594.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6700 - attribute \src "libresoc.v:139961.13-139961.33" + attribute \src "libresoc.v:142363.3-142384.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6745 + attribute \src "libresoc.v:141749.13-141749.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:140573.3-140594.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6701 - attribute \src "libresoc.v:139965.7-139965.30" + attribute \src "libresoc.v:142363.3-142384.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6746 + attribute \src "libresoc.v:141753.7-141753.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:140643.3-140652.6" + attribute \src "libresoc.v:142433.3-142442.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:140653.3-140662.6" + attribute \src "libresoc.v:142443.3-142452.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:140467.3-140475.6" - wire $1\opc_l_r_opc$next[0:0]$6633 - attribute \src "libresoc.v:139979.7-139979.25" + attribute \src "libresoc.v:142257.3-142265.6" + wire $1\opc_l_r_opc$next[0:0]$6678 + attribute \src "libresoc.v:141767.7-141767.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140458.3-140466.6" - wire $1\opc_l_s_opc$next[0:0]$6630 - attribute \src "libresoc.v:139983.7-139983.25" + attribute \src "libresoc.v:142248.3-142256.6" + wire $1\opc_l_s_opc$next[0:0]$6675 + attribute \src "libresoc.v:141771.7-141771.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:140663.3-140671.6" - wire width 2 $1\prev_wr_go$next[1:0]$6724 - attribute \src "libresoc.v:140115.13-140115.30" + attribute \src "libresoc.v:142453.3-142461.6" + wire width 2 $1\prev_wr_go$next[1:0]$6769 + attribute \src "libresoc.v:141905.13-141905.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:140412.3-140421.6" + attribute \src "libresoc.v:142202.3-142211.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:140503.3-140511.6" - wire width 2 $1\req_l_r_req$next[1:0]$6645 - attribute \src "libresoc.v:140123.13-140123.31" + attribute \src "libresoc.v:142293.3-142301.6" + wire width 2 $1\req_l_r_req$next[1:0]$6690 + attribute \src "libresoc.v:141913.13-141913.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:140494.3-140502.6" - wire width 2 $1\req_l_s_req$next[1:0]$6642 - attribute \src "libresoc.v:140127.13-140127.31" + attribute \src "libresoc.v:142284.3-142292.6" + wire width 2 $1\req_l_s_req$next[1:0]$6687 + attribute \src "libresoc.v:141917.13-141917.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:140431.3-140439.6" - wire $1\rok_l_r_rdok$next[0:0]$6621 - attribute \src "libresoc.v:140139.7-140139.26" + attribute \src "libresoc.v:142221.3-142229.6" + wire $1\rok_l_r_rdok$next[0:0]$6666 + attribute \src "libresoc.v:141929.7-141929.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:140422.3-140430.6" - wire $1\rok_l_s_rdok$next[0:0]$6618 - attribute \src "libresoc.v:140143.7-140143.26" + attribute \src "libresoc.v:142212.3-142220.6" + wire $1\rok_l_s_rdok$next[0:0]$6663 + attribute \src "libresoc.v:141933.7-141933.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:140449.3-140457.6" - wire $1\rst_l_r_rst$next[0:0]$6627 - attribute \src "libresoc.v:140147.7-140147.25" + attribute \src "libresoc.v:142239.3-142247.6" + wire $1\rst_l_r_rst$next[0:0]$6672 + attribute \src "libresoc.v:141937.7-141937.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:140440.3-140448.6" - wire $1\rst_l_s_rst$next[0:0]$6624 - attribute \src "libresoc.v:140151.7-140151.25" + attribute \src "libresoc.v:142230.3-142238.6" + wire $1\rst_l_s_rst$next[0:0]$6669 + attribute \src "libresoc.v:141941.7-141941.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:140485.3-140493.6" - wire width 3 $1\src_l_r_src$next[2:0]$6639 - attribute \src "libresoc.v:140165.13-140165.31" + attribute \src "libresoc.v:142275.3-142283.6" + wire width 3 $1\src_l_r_src$next[2:0]$6684 + attribute \src "libresoc.v:141955.13-141955.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:140476.3-140484.6" - wire width 3 $1\src_l_s_src$next[2:0]$6636 - attribute \src "libresoc.v:140169.13-140169.31" + attribute \src "libresoc.v:142266.3-142274.6" + wire width 3 $1\src_l_s_src$next[2:0]$6681 + attribute \src "libresoc.v:141959.13-141959.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:140595.3-140604.6" - wire width 64 $1\src_r0$next[63:0]$6707 - attribute \src "libresoc.v:140177.14-140177.43" + attribute \src "libresoc.v:142385.3-142394.6" + wire width 64 $1\src_r0$next[63:0]$6752 + attribute \src "libresoc.v:141967.14-141967.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:140605.3-140614.6" - wire width 64 $1\src_r1$next[63:0]$6710 - attribute \src "libresoc.v:140181.14-140181.43" + attribute \src "libresoc.v:142395.3-142404.6" + wire width 64 $1\src_r1$next[63:0]$6755 + attribute \src "libresoc.v:141971.14-141971.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:140615.3-140624.6" - wire $1\src_r2$next[0:0]$6713 - attribute \src "libresoc.v:140185.7-140185.20" + attribute \src "libresoc.v:142405.3-142414.6" + wire $1\src_r2$next[0:0]$6758 + attribute \src "libresoc.v:141975.7-141975.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:140512.3-140550.6" - wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6683 - attribute \src "libresoc.v:140512.3-140550.6" - wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6684 - attribute \src "libresoc.v:140512.3-140550.6" - wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6685 - attribute \src "libresoc.v:140512.3-140550.6" - wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6686 - attribute \src "libresoc.v:140512.3-140550.6" - wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6687 - attribute \src "libresoc.v:140512.3-140550.6" - wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6688 - attribute \src "libresoc.v:140551.3-140572.6" - wire width 64 $2\data_r0__o$next[63:0]$6694 - attribute \src "libresoc.v:140551.3-140572.6" - wire $2\data_r0__o_ok$next[0:0]$6695 - attribute \src "libresoc.v:140573.3-140594.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$6702 - attribute \src "libresoc.v:140573.3-140594.6" - wire $2\data_r1__cr_a_ok$next[0:0]$6703 - attribute \src "libresoc.v:140551.3-140572.6" - wire $3\data_r0__o_ok$next[0:0]$6696 - attribute \src "libresoc.v:140573.3-140594.6" - wire $3\data_r1__cr_a_ok$next[0:0]$6704 - attribute \src "libresoc.v:140194.17-140194.109" - wire $and$libresoc.v:140194$6518_Y - attribute \src "libresoc.v:140195.18-140195.130" - wire width 3 $and$libresoc.v:140195$6519_Y - attribute \src "libresoc.v:140197.19-140197.114" - wire width 3 $and$libresoc.v:140197$6521_Y - attribute \src "libresoc.v:140198.19-140198.125" - wire $and$libresoc.v:140198$6522_Y - attribute \src "libresoc.v:140199.19-140199.125" - wire $and$libresoc.v:140199$6523_Y - attribute \src "libresoc.v:140200.19-140200.133" - wire width 2 $and$libresoc.v:140200$6524_Y - attribute \src "libresoc.v:140201.19-140201.121" - wire width 2 $and$libresoc.v:140201$6525_Y - attribute \src "libresoc.v:140202.19-140202.127" - wire $and$libresoc.v:140202$6526_Y - attribute \src "libresoc.v:140203.19-140203.127" - wire $and$libresoc.v:140203$6527_Y - attribute \src "libresoc.v:140205.18-140205.98" - wire $and$libresoc.v:140205$6529_Y - attribute \src "libresoc.v:140207.18-140207.100" - wire $and$libresoc.v:140207$6531_Y - attribute \src "libresoc.v:140208.17-140208.123" - wire $and$libresoc.v:140208$6532_Y - attribute \src "libresoc.v:140209.18-140209.138" - wire width 2 $and$libresoc.v:140209$6533_Y - attribute \src "libresoc.v:140211.18-140211.119" - wire width 2 $and$libresoc.v:140211$6535_Y - attribute \src "libresoc.v:140214.18-140214.116" - wire $and$libresoc.v:140214$6538_Y - attribute \src "libresoc.v:140219.18-140219.113" - wire $and$libresoc.v:140219$6543_Y - attribute \src "libresoc.v:140220.18-140220.125" - wire width 2 $and$libresoc.v:140220$6544_Y - attribute \src "libresoc.v:140222.18-140222.112" - wire $and$libresoc.v:140222$6546_Y - attribute \src "libresoc.v:140225.18-140225.130" - wire $and$libresoc.v:140225$6549_Y - attribute \src "libresoc.v:140226.18-140226.130" - wire $and$libresoc.v:140226$6550_Y - attribute \src "libresoc.v:140227.18-140227.117" - wire $and$libresoc.v:140227$6551_Y - attribute \src "libresoc.v:140232.18-140232.134" - wire $and$libresoc.v:140232$6556_Y - attribute \src "libresoc.v:140233.18-140233.124" - wire width 2 $and$libresoc.v:140233$6557_Y - attribute \src "libresoc.v:140236.18-140236.116" - wire $and$libresoc.v:140236$6560_Y - attribute \src "libresoc.v:140237.18-140237.119" - wire $and$libresoc.v:140237$6561_Y - attribute \src "libresoc.v:140246.18-140246.138" - wire $and$libresoc.v:140246$6570_Y - attribute \src "libresoc.v:140247.18-140247.136" - wire $and$libresoc.v:140247$6571_Y - attribute \src "libresoc.v:140248.18-140248.149" - wire width 3 $and$libresoc.v:140248$6572_Y - attribute \src "libresoc.v:140221.18-140221.113" - wire $eq$libresoc.v:140221$6545_Y - attribute \src "libresoc.v:140223.18-140223.119" - wire $eq$libresoc.v:140223$6547_Y - attribute \src "libresoc.v:140196.19-140196.115" - wire width 3 $not$libresoc.v:140196$6520_Y - attribute \src "libresoc.v:140204.18-140204.97" - wire $not$libresoc.v:140204$6528_Y - attribute \src "libresoc.v:140206.18-140206.99" - wire $not$libresoc.v:140206$6530_Y - attribute \src "libresoc.v:140210.18-140210.113" - wire width 2 $not$libresoc.v:140210$6534_Y - attribute \src "libresoc.v:140213.18-140213.106" - wire $not$libresoc.v:140213$6537_Y - attribute \src "libresoc.v:140218.18-140218.124" - wire $not$libresoc.v:140218$6542_Y - attribute \src "libresoc.v:140224.17-140224.113" - wire width 3 $not$libresoc.v:140224$6548_Y - attribute \src "libresoc.v:140249.18-140249.133" - wire $not$libresoc.v:140249$6573_Y - attribute \src "libresoc.v:140250.18-140250.139" - wire $not$libresoc.v:140250$6574_Y - attribute \src "libresoc.v:140217.18-140217.112" - wire $or$libresoc.v:140217$6541_Y - attribute \src "libresoc.v:140228.18-140228.122" - wire $or$libresoc.v:140228$6552_Y - attribute \src "libresoc.v:140229.18-140229.124" - wire $or$libresoc.v:140229$6553_Y - attribute \src "libresoc.v:140230.18-140230.142" - wire width 2 $or$libresoc.v:140230$6554_Y - attribute \src "libresoc.v:140231.18-140231.155" - wire width 3 $or$libresoc.v:140231$6555_Y - attribute \src "libresoc.v:140234.18-140234.120" - wire width 2 $or$libresoc.v:140234$6558_Y - attribute \src "libresoc.v:140235.17-140235.117" - wire width 3 $or$libresoc.v:140235$6559_Y - attribute \src "libresoc.v:140241.17-140241.104" - wire $reduce_and$libresoc.v:140241$6565_Y - attribute \src "libresoc.v:140212.18-140212.106" - wire $reduce_or$libresoc.v:140212$6536_Y - attribute \src "libresoc.v:140215.18-140215.113" - wire $reduce_or$libresoc.v:140215$6539_Y - attribute \src "libresoc.v:140216.18-140216.112" - wire $reduce_or$libresoc.v:140216$6540_Y - attribute \src "libresoc.v:140238.18-140238.162" - wire $ternary$libresoc.v:140238$6562_Y - attribute \src "libresoc.v:140239.18-140239.163" - wire width 64 $ternary$libresoc.v:140239$6563_Y - attribute \src "libresoc.v:140240.18-140240.168" - wire $ternary$libresoc.v:140240$6564_Y - attribute \src "libresoc.v:140242.18-140242.188" - wire width 64 $ternary$libresoc.v:140242$6566_Y - attribute \src "libresoc.v:140243.18-140243.115" - wire width 64 $ternary$libresoc.v:140243$6567_Y - attribute \src "libresoc.v:140244.18-140244.125" - wire width 64 $ternary$libresoc.v:140244$6568_Y - attribute \src "libresoc.v:140245.18-140245.118" - wire $ternary$libresoc.v:140245$6569_Y + attribute \src "libresoc.v:142302.3-142340.6" + wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 + attribute \src "libresoc.v:142302.3-142340.6" + wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 + attribute \src "libresoc.v:142302.3-142340.6" + wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 + attribute \src "libresoc.v:142302.3-142340.6" + wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 + attribute \src "libresoc.v:142302.3-142340.6" + wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 + attribute \src "libresoc.v:142302.3-142340.6" + wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 + attribute \src "libresoc.v:142341.3-142362.6" + wire width 64 $2\data_r0__o$next[63:0]$6739 + attribute \src "libresoc.v:142341.3-142362.6" + wire $2\data_r0__o_ok$next[0:0]$6740 + attribute \src "libresoc.v:142363.3-142384.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$6747 + attribute \src "libresoc.v:142363.3-142384.6" + wire $2\data_r1__cr_a_ok$next[0:0]$6748 + attribute \src "libresoc.v:142341.3-142362.6" + wire $3\data_r0__o_ok$next[0:0]$6741 + attribute \src "libresoc.v:142363.3-142384.6" + wire $3\data_r1__cr_a_ok$next[0:0]$6749 + attribute \src "libresoc.v:141984.17-141984.109" + wire $and$libresoc.v:141984$6563_Y + attribute \src "libresoc.v:141985.18-141985.130" + wire width 3 $and$libresoc.v:141985$6564_Y + attribute \src "libresoc.v:141987.19-141987.114" + wire width 3 $and$libresoc.v:141987$6566_Y + attribute \src "libresoc.v:141988.19-141988.125" + wire $and$libresoc.v:141988$6567_Y + attribute \src "libresoc.v:141989.19-141989.125" + wire $and$libresoc.v:141989$6568_Y + attribute \src "libresoc.v:141990.19-141990.133" + wire width 2 $and$libresoc.v:141990$6569_Y + attribute \src "libresoc.v:141991.19-141991.121" + wire width 2 $and$libresoc.v:141991$6570_Y + attribute \src "libresoc.v:141992.19-141992.127" + wire $and$libresoc.v:141992$6571_Y + attribute \src "libresoc.v:141993.19-141993.127" + wire $and$libresoc.v:141993$6572_Y + attribute \src "libresoc.v:141995.18-141995.98" + wire $and$libresoc.v:141995$6574_Y + attribute \src "libresoc.v:141997.18-141997.100" + wire $and$libresoc.v:141997$6576_Y + attribute \src "libresoc.v:141998.17-141998.123" + wire $and$libresoc.v:141998$6577_Y + attribute \src "libresoc.v:141999.18-141999.138" + wire width 2 $and$libresoc.v:141999$6578_Y + attribute \src "libresoc.v:142001.18-142001.119" + wire width 2 $and$libresoc.v:142001$6580_Y + attribute \src "libresoc.v:142004.18-142004.116" + wire $and$libresoc.v:142004$6583_Y + attribute \src "libresoc.v:142009.18-142009.113" + wire $and$libresoc.v:142009$6588_Y + attribute \src "libresoc.v:142010.18-142010.125" + wire width 2 $and$libresoc.v:142010$6589_Y + attribute \src "libresoc.v:142012.18-142012.112" + wire $and$libresoc.v:142012$6591_Y + attribute \src "libresoc.v:142015.18-142015.130" + wire $and$libresoc.v:142015$6594_Y + attribute \src "libresoc.v:142016.18-142016.130" + wire $and$libresoc.v:142016$6595_Y + attribute \src "libresoc.v:142017.18-142017.117" + wire $and$libresoc.v:142017$6596_Y + attribute \src "libresoc.v:142022.18-142022.134" + wire $and$libresoc.v:142022$6601_Y + attribute \src "libresoc.v:142023.18-142023.124" + wire width 2 $and$libresoc.v:142023$6602_Y + attribute \src "libresoc.v:142026.18-142026.116" + wire $and$libresoc.v:142026$6605_Y + attribute \src "libresoc.v:142027.18-142027.119" + wire $and$libresoc.v:142027$6606_Y + attribute \src "libresoc.v:142036.18-142036.138" + wire $and$libresoc.v:142036$6615_Y + attribute \src "libresoc.v:142037.18-142037.136" + wire $and$libresoc.v:142037$6616_Y + attribute \src "libresoc.v:142038.18-142038.149" + wire width 3 $and$libresoc.v:142038$6617_Y + attribute \src "libresoc.v:142011.18-142011.113" + wire $eq$libresoc.v:142011$6590_Y + attribute \src "libresoc.v:142013.18-142013.119" + wire $eq$libresoc.v:142013$6592_Y + attribute \src "libresoc.v:141986.19-141986.115" + wire width 3 $not$libresoc.v:141986$6565_Y + attribute \src "libresoc.v:141994.18-141994.97" + wire $not$libresoc.v:141994$6573_Y + attribute \src "libresoc.v:141996.18-141996.99" + wire $not$libresoc.v:141996$6575_Y + attribute \src "libresoc.v:142000.18-142000.113" + wire width 2 $not$libresoc.v:142000$6579_Y + attribute \src "libresoc.v:142003.18-142003.106" + wire $not$libresoc.v:142003$6582_Y + attribute \src "libresoc.v:142008.18-142008.124" + wire $not$libresoc.v:142008$6587_Y + attribute \src "libresoc.v:142014.17-142014.113" + wire width 3 $not$libresoc.v:142014$6593_Y + attribute \src "libresoc.v:142039.18-142039.133" + wire $not$libresoc.v:142039$6618_Y + attribute \src "libresoc.v:142040.18-142040.139" + wire $not$libresoc.v:142040$6619_Y + attribute \src "libresoc.v:142007.18-142007.112" + wire $or$libresoc.v:142007$6586_Y + attribute \src "libresoc.v:142018.18-142018.122" + wire $or$libresoc.v:142018$6597_Y + attribute \src "libresoc.v:142019.18-142019.124" + wire $or$libresoc.v:142019$6598_Y + attribute \src "libresoc.v:142020.18-142020.142" + wire width 2 $or$libresoc.v:142020$6599_Y + attribute \src "libresoc.v:142021.18-142021.155" + wire width 3 $or$libresoc.v:142021$6600_Y + attribute \src "libresoc.v:142024.18-142024.120" + wire width 2 $or$libresoc.v:142024$6603_Y + attribute \src "libresoc.v:142025.17-142025.117" + wire width 3 $or$libresoc.v:142025$6604_Y + attribute \src "libresoc.v:142031.17-142031.104" + wire $reduce_and$libresoc.v:142031$6610_Y + attribute \src "libresoc.v:142002.18-142002.106" + wire $reduce_or$libresoc.v:142002$6581_Y + attribute \src "libresoc.v:142005.18-142005.113" + wire $reduce_or$libresoc.v:142005$6584_Y + attribute \src "libresoc.v:142006.18-142006.112" + wire $reduce_or$libresoc.v:142006$6585_Y + attribute \src "libresoc.v:142028.18-142028.162" + wire $ternary$libresoc.v:142028$6607_Y + attribute \src "libresoc.v:142029.18-142029.163" + wire width 64 $ternary$libresoc.v:142029$6608_Y + attribute \src "libresoc.v:142030.18-142030.168" + wire $ternary$libresoc.v:142030$6609_Y + attribute \src "libresoc.v:142032.18-142032.188" + wire width 64 $ternary$libresoc.v:142032$6611_Y + attribute \src "libresoc.v:142033.18-142033.115" + wire width 64 $ternary$libresoc.v:142033$6612_Y + attribute \src "libresoc.v:142034.18-142034.125" + wire width 64 $ternary$libresoc.v:142034$6613_Y + attribute \src "libresoc.v:142035.18-142035.118" + wire $ternary$libresoc.v:142035$6614_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -227552,23 +230051,24 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_logical0_logical_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_logical0_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_logical0_logical_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_logical0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_logical0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_logical0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -227663,6 +230163,7 @@ module \logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_logical0_logical_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -227739,9 +230240,9 @@ module \logical0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -227787,7 +230288,7 @@ module \logical0 wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:139589.7-139589.15" + attribute \src "libresoc.v:141375.7-141375.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -227804,21 +230305,22 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_logical0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -227905,6 +230407,7 @@ module \logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -228010,7 +230513,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:140194$6518 + cell $and $and$libresoc.v:141984$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228018,10 +230521,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:140194$6518_Y + connect \Y $and$libresoc.v:141984$6563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:140195$6519 + cell $and $and$libresoc.v:141985$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -228029,10 +230532,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:140195$6519_Y + connect \Y $and$libresoc.v:141985$6564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:140197$6521 + cell $and $and$libresoc.v:141987$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -228040,10 +230543,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:140197$6521_Y + connect \Y $and$libresoc.v:141987$6566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:140198$6522 + cell $and $and$libresoc.v:141988$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228051,10 +230554,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140198$6522_Y + connect \Y $and$libresoc.v:141988$6567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:140199$6523 + cell $and $and$libresoc.v:141989$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228062,10 +230565,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140199$6523_Y + connect \Y $and$libresoc.v:141989$6568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:140200$6524 + cell $and $and$libresoc.v:141990$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228073,10 +230576,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:140200$6524_Y + connect \Y $and$libresoc.v:141990$6569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:140201$6525 + cell $and $and$libresoc.v:141991$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228084,10 +230587,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:140201$6525_Y + connect \Y $and$libresoc.v:141991$6570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:140202$6526 + cell $and $and$libresoc.v:141992$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228095,10 +230598,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:140202$6526_Y + connect \Y $and$libresoc.v:141992$6571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:140203$6527 + cell $and $and$libresoc.v:141993$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228106,10 +230609,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:140203$6527_Y + connect \Y $and$libresoc.v:141993$6572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:140205$6529 + cell $and $and$libresoc.v:141995$6574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228117,10 +230620,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:140205$6529_Y + connect \Y $and$libresoc.v:141995$6574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:140207$6531 + cell $and $and$libresoc.v:141997$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228128,10 +230631,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:140207$6531_Y + connect \Y $and$libresoc.v:141997$6576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:140208$6532 + cell $and $and$libresoc.v:141998$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228139,10 +230642,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:140208$6532_Y + connect \Y $and$libresoc.v:141998$6577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:140209$6533 + cell $and $and$libresoc.v:141999$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228150,10 +230653,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:140209$6533_Y + connect \Y $and$libresoc.v:141999$6578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:140211$6535 + cell $and $and$libresoc.v:142001$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228161,10 +230664,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:140211$6535_Y + connect \Y $and$libresoc.v:142001$6580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:140214$6538 + cell $and $and$libresoc.v:142004$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228172,10 +230675,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:140214$6538_Y + connect \Y $and$libresoc.v:142004$6583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:140219$6543 + cell $and $and$libresoc.v:142009$6588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228183,10 +230686,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:140219$6543_Y + connect \Y $and$libresoc.v:142009$6588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:140220$6544 + cell $and $and$libresoc.v:142010$6589 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228194,10 +230697,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:140220$6544_Y + connect \Y $and$libresoc.v:142010$6589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:140222$6546 + cell $and $and$libresoc.v:142012$6591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228205,10 +230708,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:140222$6546_Y + connect \Y $and$libresoc.v:142012$6591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:140225$6549 + cell $and $and$libresoc.v:142015$6594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228216,10 +230719,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:140225$6549_Y + connect \Y $and$libresoc.v:142015$6594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:140226$6550 + cell $and $and$libresoc.v:142016$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228227,10 +230730,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:140226$6550_Y + connect \Y $and$libresoc.v:142016$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:140227$6551 + cell $and $and$libresoc.v:142017$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228238,10 +230741,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:140227$6551_Y + connect \Y $and$libresoc.v:142017$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:140232$6556 + cell $and $and$libresoc.v:142022$6601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228249,10 +230752,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:140232$6556_Y + connect \Y $and$libresoc.v:142022$6601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:140233$6557 + cell $and $and$libresoc.v:142023$6602 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228260,10 +230763,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:140233$6557_Y + connect \Y $and$libresoc.v:142023$6602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:140236$6560 + cell $and $and$libresoc.v:142026$6605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228271,10 +230774,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:140236$6560_Y + connect \Y $and$libresoc.v:142026$6605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:140237$6561 + cell $and $and$libresoc.v:142027$6606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228282,10 +230785,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:140237$6561_Y + connect \Y $and$libresoc.v:142027$6606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:140246$6570 + cell $and $and$libresoc.v:142036$6615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228293,10 +230796,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:140246$6570_Y + connect \Y $and$libresoc.v:142036$6615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:140247$6571 + cell $and $and$libresoc.v:142037$6616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228304,10 +230807,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:140247$6571_Y + connect \Y $and$libresoc.v:142037$6616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:140248$6572 + cell $and $and$libresoc.v:142038$6617 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -228315,10 +230818,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:140248$6572_Y + connect \Y $and$libresoc.v:142038$6617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:140221$6545 + cell $eq $eq$libresoc.v:142011$6590 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228326,10 +230829,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:140221$6545_Y + connect \Y $eq$libresoc.v:142011$6590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:140223$6547 + cell $eq $eq$libresoc.v:142013$6592 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228337,82 +230840,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:140223$6547_Y + connect \Y $eq$libresoc.v:142013$6592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:140196$6520 + cell $not $not$libresoc.v:141986$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:140196$6520_Y + connect \Y $not$libresoc.v:141986$6565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:140204$6528 + cell $not $not$libresoc.v:141994$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:140204$6528_Y + connect \Y $not$libresoc.v:141994$6573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:140206$6530 + cell $not $not$libresoc.v:141996$6575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:140206$6530_Y + connect \Y $not$libresoc.v:141996$6575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:140210$6534 + cell $not $not$libresoc.v:142000$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:140210$6534_Y + connect \Y $not$libresoc.v:142000$6579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:140213$6537 + cell $not $not$libresoc.v:142003$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:140213$6537_Y + connect \Y $not$libresoc.v:142003$6582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:140218$6542 + cell $not $not$libresoc.v:142008$6587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:140218$6542_Y + connect \Y $not$libresoc.v:142008$6587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:140224$6548 + cell $not $not$libresoc.v:142014$6593 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:140224$6548_Y + connect \Y $not$libresoc.v:142014$6593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:140249$6573 + cell $not $not$libresoc.v:142039$6618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:140249$6573_Y + connect \Y $not$libresoc.v:142039$6618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:140250$6574 + cell $not $not$libresoc.v:142040$6619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:140250$6574_Y + connect \Y $not$libresoc.v:142040$6619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:140217$6541 + cell $or $or$libresoc.v:142007$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228420,10 +230923,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:140217$6541_Y + connect \Y $or$libresoc.v:142007$6586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:140228$6552 + cell $or $or$libresoc.v:142018$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228431,10 +230934,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140228$6552_Y + connect \Y $or$libresoc.v:142018$6597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:140229$6553 + cell $or $or$libresoc.v:142019$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228442,10 +230945,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140229$6553_Y + connect \Y $or$libresoc.v:142019$6598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:140230$6554 + cell $or $or$libresoc.v:142020$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228453,10 +230956,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:140230$6554_Y + connect \Y $or$libresoc.v:142020$6599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:140231$6555 + cell $or $or$libresoc.v:142021$6600 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -228464,10 +230967,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:140231$6555_Y + connect \Y $or$libresoc.v:142021$6600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:140234$6558 + cell $or $or$libresoc.v:142024$6603 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -228475,10 +230978,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:140234$6558_Y + connect \Y $or$libresoc.v:142024$6603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:140235$6559 + cell $or $or$libresoc.v:142025$6604 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -228486,98 +230989,98 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:140235$6559_Y + connect \Y $or$libresoc.v:142025$6604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:140241$6565 + cell $reduce_and $reduce_and$libresoc.v:142031$6610 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:140241$6565_Y + connect \Y $reduce_and$libresoc.v:142031$6610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:140212$6536 + cell $reduce_or $reduce_or$libresoc.v:142002$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:140212$6536_Y + connect \Y $reduce_or$libresoc.v:142002$6581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:140215$6539 + cell $reduce_or $reduce_or$libresoc.v:142005$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:140215$6539_Y + connect \Y $reduce_or$libresoc.v:142005$6584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:140216$6540 + cell $reduce_or $reduce_or$libresoc.v:142006$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:140216$6540_Y + connect \Y $reduce_or$libresoc.v:142006$6585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:140238$6562 + cell $mux $ternary$libresoc.v:142028$6607 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:140238$6562_Y + connect \Y $ternary$libresoc.v:142028$6607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:140239$6563 + cell $mux $ternary$libresoc.v:142029$6608 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:140239$6563_Y + connect \Y $ternary$libresoc.v:142029$6608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:140240$6564 + cell $mux $ternary$libresoc.v:142030$6609 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:140240$6564_Y + connect \Y $ternary$libresoc.v:142030$6609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:140242$6566 + cell $mux $ternary$libresoc.v:142032$6611 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:140242$6566_Y + connect \Y $ternary$libresoc.v:142032$6611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140243$6567 + cell $mux $ternary$libresoc.v:142033$6612 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:140243$6567_Y + connect \Y $ternary$libresoc.v:142033$6612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140244$6568 + cell $mux $ternary$libresoc.v:142034$6613 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:140244$6568_Y + connect \Y $ternary$libresoc.v:142034$6613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140245$6569 + cell $mux $ternary$libresoc.v:142035$6614 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:140245$6569_Y + connect \Y $ternary$libresoc.v:142035$6614_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:140331.14-140337.4" + attribute \src "libresoc.v:142121.14-142127.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228586,7 +231089,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:140338.16-140370.4" + attribute \src "libresoc.v:142128.16-142160.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228621,7 +231124,7 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:140371.15-140377.4" + attribute \src "libresoc.v:142161.15-142167.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228630,7 +231133,7 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:140378.14-140384.4" + attribute \src "libresoc.v:142168.14-142174.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228639,7 +231142,7 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:140385.14-140391.4" + attribute \src "libresoc.v:142175.14-142181.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228648,7 +231151,7 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:140392.14-140398.4" + attribute \src "libresoc.v:142182.14-142188.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228657,7 +231160,7 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:140399.14-140404.4" + attribute \src "libresoc.v:142189.14-142194.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228665,7 +231168,7 @@ module \logical0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:140405.14-140411.4" + attribute \src "libresoc.v:142195.14-142201.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228673,622 +231176,622 @@ module \logical0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:139589.7-139589.20" - process $proc$libresoc.v:139589$6725 + attribute \src "libresoc.v:141375.7-141375.20" + process $proc$libresoc.v:141375$6770 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139707.7-139707.24" - process $proc$libresoc.v:139707$6726 + attribute \src "libresoc.v:141493.7-141493.24" + process $proc$libresoc.v:141493$6771 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:139717.7-139717.26" - process $proc$libresoc.v:139717$6727 + attribute \src "libresoc.v:141503.7-141503.26" + process $proc$libresoc.v:141503$6772 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:139725.7-139725.25" - process $proc$libresoc.v:139725$6728 + attribute \src "libresoc.v:141511.7-141511.25" + process $proc$libresoc.v:141511$6773 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:139733.13-139733.53" - process $proc$libresoc.v:139733$6729 + attribute \src "libresoc.v:141519.13-141519.53" + process $proc$libresoc.v:141519$6774 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:139751.14-139751.57" - process $proc$libresoc.v:139751$6730 + attribute \src "libresoc.v:141538.14-141538.57" + process $proc$libresoc.v:141538$6775 assign { } { } - assign $1\alu_logical0_logical_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[12:0] + update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:139755.14-139755.76" - process $proc$libresoc.v:139755$6731 + attribute \src "libresoc.v:141542.14-141542.76" + process $proc$libresoc.v:141542$6776 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:139759.7-139759.51" - process $proc$libresoc.v:139759$6732 + attribute \src "libresoc.v:141546.7-141546.51" + process $proc$libresoc.v:141546$6777 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:139767.13-139767.56" - process $proc$libresoc.v:139767$6733 + attribute \src "libresoc.v:141554.13-141554.56" + process $proc$libresoc.v:141554$6778 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:139771.14-139771.51" - process $proc$libresoc.v:139771$6734 + attribute \src "libresoc.v:141558.14-141558.51" + process $proc$libresoc.v:141558$6779 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:139849.13-139849.55" - process $proc$libresoc.v:139849$6735 + attribute \src "libresoc.v:141637.13-141637.55" + process $proc$libresoc.v:141637$6780 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:139853.7-139853.48" - process $proc$libresoc.v:139853$6736 + attribute \src "libresoc.v:141641.7-141641.48" + process $proc$libresoc.v:141641$6781 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:139857.7-139857.49" - process $proc$libresoc.v:139857$6737 + attribute \src "libresoc.v:141645.7-141645.49" + process $proc$libresoc.v:141645$6782 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:139861.7-139861.47" - process $proc$libresoc.v:139861$6738 + attribute \src "libresoc.v:141649.7-141649.47" + process $proc$libresoc.v:141649$6783 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:139865.7-139865.48" - process $proc$libresoc.v:139865$6739 + attribute \src "libresoc.v:141653.7-141653.48" + process $proc$libresoc.v:141653$6784 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:139869.7-139869.45" - process $proc$libresoc.v:139869$6740 + attribute \src "libresoc.v:141657.7-141657.45" + process $proc$libresoc.v:141657$6785 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:139873.7-139873.45" - process $proc$libresoc.v:139873$6741 + attribute \src "libresoc.v:141661.7-141661.45" + process $proc$libresoc.v:141661$6786 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:139877.7-139877.51" - process $proc$libresoc.v:139877$6742 + attribute \src "libresoc.v:141665.7-141665.51" + process $proc$libresoc.v:141665$6787 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:139881.7-139881.45" - process $proc$libresoc.v:139881$6743 + attribute \src "libresoc.v:141669.7-141669.45" + process $proc$libresoc.v:141669$6788 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:139885.7-139885.45" - process $proc$libresoc.v:139885$6744 + attribute \src "libresoc.v:141673.7-141673.45" + process $proc$libresoc.v:141673$6789 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:139889.7-139889.48" - process $proc$libresoc.v:139889$6745 + attribute \src "libresoc.v:141677.7-141677.48" + process $proc$libresoc.v:141677$6790 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:139893.7-139893.45" - process $proc$libresoc.v:139893$6746 + attribute \src "libresoc.v:141681.7-141681.45" + process $proc$libresoc.v:141681$6791 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:139919.7-139919.27" - process $proc$libresoc.v:139919$6747 + attribute \src "libresoc.v:141707.7-141707.27" + process $proc$libresoc.v:141707$6792 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:139953.14-139953.47" - process $proc$libresoc.v:139953$6748 + attribute \src "libresoc.v:141741.14-141741.47" + process $proc$libresoc.v:141741$6793 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:139957.7-139957.27" - process $proc$libresoc.v:139957$6749 + attribute \src "libresoc.v:141745.7-141745.27" + process $proc$libresoc.v:141745$6794 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:139961.13-139961.33" - process $proc$libresoc.v:139961$6750 + attribute \src "libresoc.v:141749.13-141749.33" + process $proc$libresoc.v:141749$6795 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:139965.7-139965.30" - process $proc$libresoc.v:139965$6751 + attribute \src "libresoc.v:141753.7-141753.30" + process $proc$libresoc.v:141753$6796 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:139979.7-139979.25" - process $proc$libresoc.v:139979$6752 + attribute \src "libresoc.v:141767.7-141767.25" + process $proc$libresoc.v:141767$6797 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:139983.7-139983.25" - process $proc$libresoc.v:139983$6753 + attribute \src "libresoc.v:141771.7-141771.25" + process $proc$libresoc.v:141771$6798 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:140115.13-140115.30" - process $proc$libresoc.v:140115$6754 + attribute \src "libresoc.v:141905.13-141905.30" + process $proc$libresoc.v:141905$6799 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:140123.13-140123.31" - process $proc$libresoc.v:140123$6755 + attribute \src "libresoc.v:141913.13-141913.31" + process $proc$libresoc.v:141913$6800 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:140127.13-140127.31" - process $proc$libresoc.v:140127$6756 + attribute \src "libresoc.v:141917.13-141917.31" + process $proc$libresoc.v:141917$6801 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:140139.7-140139.26" - process $proc$libresoc.v:140139$6757 + attribute \src "libresoc.v:141929.7-141929.26" + process $proc$libresoc.v:141929$6802 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:140143.7-140143.26" - process $proc$libresoc.v:140143$6758 + attribute \src "libresoc.v:141933.7-141933.26" + process $proc$libresoc.v:141933$6803 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:140147.7-140147.25" - process $proc$libresoc.v:140147$6759 + attribute \src "libresoc.v:141937.7-141937.25" + process $proc$libresoc.v:141937$6804 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:140151.7-140151.25" - process $proc$libresoc.v:140151$6760 + attribute \src "libresoc.v:141941.7-141941.25" + process $proc$libresoc.v:141941$6805 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:140165.13-140165.31" - process $proc$libresoc.v:140165$6761 + attribute \src "libresoc.v:141955.13-141955.31" + process $proc$libresoc.v:141955$6806 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:140169.13-140169.31" - process $proc$libresoc.v:140169$6762 + attribute \src "libresoc.v:141959.13-141959.31" + process $proc$libresoc.v:141959$6807 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:140177.14-140177.43" - process $proc$libresoc.v:140177$6763 + attribute \src "libresoc.v:141967.14-141967.43" + process $proc$libresoc.v:141967$6808 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:140181.14-140181.43" - process $proc$libresoc.v:140181$6764 + attribute \src "libresoc.v:141971.14-141971.43" + process $proc$libresoc.v:141971$6809 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:140185.7-140185.20" - process $proc$libresoc.v:140185$6765 + attribute \src "libresoc.v:141975.7-141975.20" + process $proc$libresoc.v:141975$6810 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:140251.3-140252.39" - process $proc$libresoc.v:140251$6575 + attribute \src "libresoc.v:142041.3-142042.39" + process $proc$libresoc.v:142041$6620 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:140253.3-140254.43" - process $proc$libresoc.v:140253$6576 + attribute \src "libresoc.v:142043.3-142044.43" + process $proc$libresoc.v:142043$6621 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:140255.3-140256.29" - process $proc$libresoc.v:140255$6577 + attribute \src "libresoc.v:142045.3-142046.29" + process $proc$libresoc.v:142045$6622 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:140257.3-140258.29" - process $proc$libresoc.v:140257$6578 + attribute \src "libresoc.v:142047.3-142048.29" + process $proc$libresoc.v:142047$6623 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:140259.3-140260.29" - process $proc$libresoc.v:140259$6579 + attribute \src "libresoc.v:142049.3-142050.29" + process $proc$libresoc.v:142049$6624 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:140261.3-140262.43" - process $proc$libresoc.v:140261$6580 + attribute \src "libresoc.v:142051.3-142052.43" + process $proc$libresoc.v:142051$6625 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:140263.3-140264.49" - process $proc$libresoc.v:140263$6581 + attribute \src "libresoc.v:142053.3-142054.49" + process $proc$libresoc.v:142053$6626 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:140265.3-140266.37" - process $proc$libresoc.v:140265$6582 + attribute \src "libresoc.v:142055.3-142056.37" + process $proc$libresoc.v:142055$6627 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:140267.3-140268.43" - process $proc$libresoc.v:140267$6583 + attribute \src "libresoc.v:142057.3-142058.43" + process $proc$libresoc.v:142057$6628 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:140269.3-140270.85" - process $proc$libresoc.v:140269$6584 + attribute \src "libresoc.v:142059.3-142060.85" + process $proc$libresoc.v:142059$6629 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:140271.3-140272.81" - process $proc$libresoc.v:140271$6585 + attribute \src "libresoc.v:142061.3-142062.81" + process $proc$libresoc.v:142061$6630 assign { } { } - assign $0\alu_logical0_logical_op__fn_unit[12:0] \alu_logical0_logical_op__fn_unit$next + assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk - update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[12:0] + update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:140273.3-140274.95" - process $proc$libresoc.v:140273$6586 + attribute \src "libresoc.v:142063.3-142064.95" + process $proc$libresoc.v:142063$6631 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:140275.3-140276.91" - process $proc$libresoc.v:140275$6587 + attribute \src "libresoc.v:142065.3-142066.91" + process $proc$libresoc.v:142065$6632 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:140277.3-140278.79" - process $proc$libresoc.v:140277$6588 + attribute \src "libresoc.v:142067.3-142068.79" + process $proc$libresoc.v:142067$6633 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:140279.3-140280.79" - process $proc$libresoc.v:140279$6589 + attribute \src "libresoc.v:142069.3-142070.79" + process $proc$libresoc.v:142069$6634 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:140281.3-140282.79" - process $proc$libresoc.v:140281$6590 + attribute \src "libresoc.v:142071.3-142072.79" + process $proc$libresoc.v:142071$6635 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:140283.3-140284.79" - process $proc$libresoc.v:140283$6591 + attribute \src "libresoc.v:142073.3-142074.79" + process $proc$libresoc.v:142073$6636 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:140285.3-140286.85" - process $proc$libresoc.v:140285$6592 + attribute \src "libresoc.v:142075.3-142076.85" + process $proc$libresoc.v:142075$6637 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:140287.3-140288.79" - process $proc$libresoc.v:140287$6593 + attribute \src "libresoc.v:142077.3-142078.79" + process $proc$libresoc.v:142077$6638 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:140289.3-140290.89" - process $proc$libresoc.v:140289$6594 + attribute \src "libresoc.v:142079.3-142080.89" + process $proc$libresoc.v:142079$6639 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:140291.3-140292.87" - process $proc$libresoc.v:140291$6595 + attribute \src "libresoc.v:142081.3-142082.87" + process $proc$libresoc.v:142081$6640 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:140293.3-140294.85" - process $proc$libresoc.v:140293$6596 + attribute \src "libresoc.v:142083.3-142084.85" + process $proc$libresoc.v:142083$6641 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:140295.3-140296.91" - process $proc$libresoc.v:140295$6597 + attribute \src "libresoc.v:142085.3-142086.91" + process $proc$libresoc.v:142085$6642 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:140297.3-140298.83" - process $proc$libresoc.v:140297$6598 + attribute \src "libresoc.v:142087.3-142088.83" + process $proc$libresoc.v:142087$6643 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:140299.3-140300.85" - process $proc$libresoc.v:140299$6599 + attribute \src "libresoc.v:142089.3-142090.85" + process $proc$libresoc.v:142089$6644 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:140301.3-140302.83" - process $proc$libresoc.v:140301$6600 + attribute \src "libresoc.v:142091.3-142092.83" + process $proc$libresoc.v:142091$6645 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:140303.3-140304.75" - process $proc$libresoc.v:140303$6601 + attribute \src "libresoc.v:142093.3-142094.75" + process $proc$libresoc.v:142093$6646 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:140305.3-140306.39" - process $proc$libresoc.v:140305$6602 + attribute \src "libresoc.v:142095.3-142096.39" + process $proc$libresoc.v:142095$6647 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:140307.3-140308.39" - process $proc$libresoc.v:140307$6603 + attribute \src "libresoc.v:142097.3-142098.39" + process $proc$libresoc.v:142097$6648 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:140309.3-140310.39" - process $proc$libresoc.v:140309$6604 + attribute \src "libresoc.v:142099.3-142100.39" + process $proc$libresoc.v:142099$6649 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:140311.3-140312.39" - process $proc$libresoc.v:140311$6605 + attribute \src "libresoc.v:142101.3-142102.39" + process $proc$libresoc.v:142101$6650 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:140313.3-140314.39" - process $proc$libresoc.v:140313$6606 + attribute \src "libresoc.v:142103.3-142104.39" + process $proc$libresoc.v:142103$6651 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:140315.3-140316.39" - process $proc$libresoc.v:140315$6607 + attribute \src "libresoc.v:142105.3-142106.39" + process $proc$libresoc.v:142105$6652 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:140317.3-140318.39" - process $proc$libresoc.v:140317$6608 + attribute \src "libresoc.v:142107.3-142108.39" + process $proc$libresoc.v:142107$6653 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:140319.3-140320.39" - process $proc$libresoc.v:140319$6609 + attribute \src "libresoc.v:142109.3-142110.39" + process $proc$libresoc.v:142109$6654 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:140321.3-140322.41" - process $proc$libresoc.v:140321$6610 + attribute \src "libresoc.v:142111.3-142112.41" + process $proc$libresoc.v:142111$6655 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:140323.3-140324.41" - process $proc$libresoc.v:140323$6611 + attribute \src "libresoc.v:142113.3-142114.41" + process $proc$libresoc.v:142113$6656 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:140325.3-140326.37" - process $proc$libresoc.v:140325$6612 + attribute \src "libresoc.v:142115.3-142116.37" + process $proc$libresoc.v:142115$6657 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:140327.3-140328.44" - process $proc$libresoc.v:140327$6613 + attribute \src "libresoc.v:142117.3-142118.44" + process $proc$libresoc.v:142117$6658 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:140329.3-140330.24" - process $proc$libresoc.v:140329$6614 + attribute \src "libresoc.v:142119.3-142120.24" + process $proc$libresoc.v:142119$6659 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:140412.3-140421.6" - process $proc$libresoc.v:140412$6615 + attribute \src "libresoc.v:142202.3-142211.6" + process $proc$libresoc.v:142202$6660 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:140413.5-140413.29" + attribute \src "libresoc.v:142203.5-142203.29" switch \initial - attribute \src "libresoc.v:140413.9-140413.17" + attribute \src "libresoc.v:142203.9-142203.17" case 1'1 case end @@ -229304,14 +231807,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:140422.3-140430.6" - process $proc$libresoc.v:140422$6616 + attribute \src "libresoc.v:142212.3-142220.6" + process $proc$libresoc.v:142212$6661 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6617 $1\rok_l_s_rdok$next[0:0]$6618 - attribute \src "libresoc.v:140423.5-140423.29" + assign $0\rok_l_s_rdok$next[0:0]$6662 $1\rok_l_s_rdok$next[0:0]$6663 + attribute \src "libresoc.v:142213.5-142213.29" switch \initial - attribute \src "libresoc.v:140423.9-140423.17" + attribute \src "libresoc.v:142213.9-142213.17" case 1'1 case end @@ -229320,21 +231823,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6618 1'0 + assign $1\rok_l_s_rdok$next[0:0]$6663 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$6618 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$6663 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6617 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6662 end - attribute \src "libresoc.v:140431.3-140439.6" - process $proc$libresoc.v:140431$6619 + attribute \src "libresoc.v:142221.3-142229.6" + process $proc$libresoc.v:142221$6664 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6620 $1\rok_l_r_rdok$next[0:0]$6621 - attribute \src "libresoc.v:140432.5-140432.29" + assign $0\rok_l_r_rdok$next[0:0]$6665 $1\rok_l_r_rdok$next[0:0]$6666 + attribute \src "libresoc.v:142222.5-142222.29" switch \initial - attribute \src "libresoc.v:140432.9-140432.17" + attribute \src "libresoc.v:142222.9-142222.17" case 1'1 case end @@ -229343,21 +231846,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6621 1'1 + assign $1\rok_l_r_rdok$next[0:0]$6666 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$6621 \$63 + assign $1\rok_l_r_rdok$next[0:0]$6666 \$63 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6620 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6665 end - attribute \src "libresoc.v:140440.3-140448.6" - process $proc$libresoc.v:140440$6622 + attribute \src "libresoc.v:142230.3-142238.6" + process $proc$libresoc.v:142230$6667 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6623 $1\rst_l_s_rst$next[0:0]$6624 - attribute \src "libresoc.v:140441.5-140441.29" + assign $0\rst_l_s_rst$next[0:0]$6668 $1\rst_l_s_rst$next[0:0]$6669 + attribute \src "libresoc.v:142231.5-142231.29" switch \initial - attribute \src "libresoc.v:140441.9-140441.17" + attribute \src "libresoc.v:142231.9-142231.17" case 1'1 case end @@ -229366,21 +231869,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6624 1'0 + assign $1\rst_l_s_rst$next[0:0]$6669 1'0 case - assign $1\rst_l_s_rst$next[0:0]$6624 \all_rd + assign $1\rst_l_s_rst$next[0:0]$6669 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6623 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6668 end - attribute \src "libresoc.v:140449.3-140457.6" - process $proc$libresoc.v:140449$6625 + attribute \src "libresoc.v:142239.3-142247.6" + process $proc$libresoc.v:142239$6670 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6626 $1\rst_l_r_rst$next[0:0]$6627 - attribute \src "libresoc.v:140450.5-140450.29" + assign $0\rst_l_r_rst$next[0:0]$6671 $1\rst_l_r_rst$next[0:0]$6672 + attribute \src "libresoc.v:142240.5-142240.29" switch \initial - attribute \src "libresoc.v:140450.9-140450.17" + attribute \src "libresoc.v:142240.9-142240.17" case 1'1 case end @@ -229389,21 +231892,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6627 1'1 + assign $1\rst_l_r_rst$next[0:0]$6672 1'1 case - assign $1\rst_l_r_rst$next[0:0]$6627 \rst_r + assign $1\rst_l_r_rst$next[0:0]$6672 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6626 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6671 end - attribute \src "libresoc.v:140458.3-140466.6" - process $proc$libresoc.v:140458$6628 + attribute \src "libresoc.v:142248.3-142256.6" + process $proc$libresoc.v:142248$6673 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6629 $1\opc_l_s_opc$next[0:0]$6630 - attribute \src "libresoc.v:140459.5-140459.29" + assign $0\opc_l_s_opc$next[0:0]$6674 $1\opc_l_s_opc$next[0:0]$6675 + attribute \src "libresoc.v:142249.5-142249.29" switch \initial - attribute \src "libresoc.v:140459.9-140459.17" + attribute \src "libresoc.v:142249.9-142249.17" case 1'1 case end @@ -229412,21 +231915,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6630 1'0 + assign $1\opc_l_s_opc$next[0:0]$6675 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6630 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6675 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6629 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6674 end - attribute \src "libresoc.v:140467.3-140475.6" - process $proc$libresoc.v:140467$6631 + attribute \src "libresoc.v:142257.3-142265.6" + process $proc$libresoc.v:142257$6676 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6632 $1\opc_l_r_opc$next[0:0]$6633 - attribute \src "libresoc.v:140468.5-140468.29" + assign $0\opc_l_r_opc$next[0:0]$6677 $1\opc_l_r_opc$next[0:0]$6678 + attribute \src "libresoc.v:142258.5-142258.29" switch \initial - attribute \src "libresoc.v:140468.9-140468.17" + attribute \src "libresoc.v:142258.9-142258.17" case 1'1 case end @@ -229435,21 +231938,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6633 1'1 + assign $1\opc_l_r_opc$next[0:0]$6678 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6633 \req_done + assign $1\opc_l_r_opc$next[0:0]$6678 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6632 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6677 end - attribute \src "libresoc.v:140476.3-140484.6" - process $proc$libresoc.v:140476$6634 + attribute \src "libresoc.v:142266.3-142274.6" + process $proc$libresoc.v:142266$6679 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6635 $1\src_l_s_src$next[2:0]$6636 - attribute \src "libresoc.v:140477.5-140477.29" + assign $0\src_l_s_src$next[2:0]$6680 $1\src_l_s_src$next[2:0]$6681 + attribute \src "libresoc.v:142267.5-142267.29" switch \initial - attribute \src "libresoc.v:140477.9-140477.17" + attribute \src "libresoc.v:142267.9-142267.17" case 1'1 case end @@ -229458,21 +231961,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6636 3'000 + assign $1\src_l_s_src$next[2:0]$6681 3'000 case - assign $1\src_l_s_src$next[2:0]$6636 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6681 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6635 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6680 end - attribute \src "libresoc.v:140485.3-140493.6" - process $proc$libresoc.v:140485$6637 + attribute \src "libresoc.v:142275.3-142283.6" + process $proc$libresoc.v:142275$6682 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6638 $1\src_l_r_src$next[2:0]$6639 - attribute \src "libresoc.v:140486.5-140486.29" + assign $0\src_l_r_src$next[2:0]$6683 $1\src_l_r_src$next[2:0]$6684 + attribute \src "libresoc.v:142276.5-142276.29" switch \initial - attribute \src "libresoc.v:140486.9-140486.17" + attribute \src "libresoc.v:142276.9-142276.17" case 1'1 case end @@ -229481,21 +231984,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6639 3'111 + assign $1\src_l_r_src$next[2:0]$6684 3'111 case - assign $1\src_l_r_src$next[2:0]$6639 \reset_r + assign $1\src_l_r_src$next[2:0]$6684 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6638 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6683 end - attribute \src "libresoc.v:140494.3-140502.6" - process $proc$libresoc.v:140494$6640 + attribute \src "libresoc.v:142284.3-142292.6" + process $proc$libresoc.v:142284$6685 assign { } { } assign { } { } - assign $0\req_l_s_req$next[1:0]$6641 $1\req_l_s_req$next[1:0]$6642 - attribute \src "libresoc.v:140495.5-140495.29" + assign $0\req_l_s_req$next[1:0]$6686 $1\req_l_s_req$next[1:0]$6687 + attribute \src "libresoc.v:142285.5-142285.29" switch \initial - attribute \src "libresoc.v:140495.9-140495.17" + attribute \src "libresoc.v:142285.9-142285.17" case 1'1 case end @@ -229504,21 +232007,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[1:0]$6642 2'00 + assign $1\req_l_s_req$next[1:0]$6687 2'00 case - assign $1\req_l_s_req$next[1:0]$6642 \$65 + assign $1\req_l_s_req$next[1:0]$6687 \$65 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6641 + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6686 end - attribute \src "libresoc.v:140503.3-140511.6" - process $proc$libresoc.v:140503$6643 + attribute \src "libresoc.v:142293.3-142301.6" + process $proc$libresoc.v:142293$6688 assign { } { } assign { } { } - assign $0\req_l_r_req$next[1:0]$6644 $1\req_l_r_req$next[1:0]$6645 - attribute \src "libresoc.v:140504.5-140504.29" + assign $0\req_l_r_req$next[1:0]$6689 $1\req_l_r_req$next[1:0]$6690 + attribute \src "libresoc.v:142294.5-142294.29" switch \initial - attribute \src "libresoc.v:140504.9-140504.17" + attribute \src "libresoc.v:142294.9-142294.17" case 1'1 case end @@ -229527,15 +232030,15 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[1:0]$6645 2'11 + assign $1\req_l_r_req$next[1:0]$6690 2'11 case - assign $1\req_l_r_req$next[1:0]$6645 \$67 + assign $1\req_l_r_req$next[1:0]$6690 \$67 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6644 + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6689 end - attribute \src "libresoc.v:140512.3-140550.6" - process $proc$libresoc.v:140512$6646 + attribute \src "libresoc.v:142302.3-142340.6" + process $proc$libresoc.v:142302$6691 assign { } { } assign { } { } assign { } { } @@ -229572,33 +232075,33 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6647 $1\alu_logical0_logical_op__data_len$next[3:0]$6665 - assign $0\alu_logical0_logical_op__fn_unit$next[12:0]$6648 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6666 + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6692 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 + assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6651 $1\alu_logical0_logical_op__input_carry$next[1:0]$6669 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6652 $1\alu_logical0_logical_op__insn$next[31:0]$6670 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6653 $1\alu_logical0_logical_op__insn_type$next[6:0]$6671 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6654 $1\alu_logical0_logical_op__invert_in$next[0:0]$6672 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6655 $1\alu_logical0_logical_op__invert_out$next[0:0]$6673 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6656 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6674 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6657 $1\alu_logical0_logical_op__is_signed$next[0:0]$6675 + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6697 $1\alu_logical0_logical_op__insn$next[31:0]$6715 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6660 $1\alu_logical0_logical_op__output_carry$next[0:0]$6678 + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6663 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6681 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6664 $1\alu_logical0_logical_op__zero_a$next[0:0]$6682 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6649 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6683 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6650 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6684 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6658 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6685 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6659 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6686 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6661 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6687 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6662 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6688 - attribute \src "libresoc.v:140513.5-140513.29" + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 + attribute \src "libresoc.v:142303.5-142303.29" switch \initial - attribute \src "libresoc.v:140513.9-140513.17" + attribute \src "libresoc.v:142303.9-142303.17" case 1'1 case end @@ -229624,26 +232127,26 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6670 $1\alu_logical0_logical_op__data_len$next[3:0]$6665 $1\alu_logical0_logical_op__is_signed$next[0:0]$6675 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6674 $1\alu_logical0_logical_op__output_carry$next[0:0]$6678 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6681 $1\alu_logical0_logical_op__invert_out$next[0:0]$6673 $1\alu_logical0_logical_op__input_carry$next[1:0]$6669 $1\alu_logical0_logical_op__zero_a$next[0:0]$6682 $1\alu_logical0_logical_op__invert_in$next[0:0]$6672 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6677 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6676 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6679 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6680 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6668 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6667 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6666 $1\alu_logical0_logical_op__insn_type$next[6:0]$6671 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6715 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6665 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[12:0]$6666 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6667 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6668 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6669 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6670 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6671 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6672 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6673 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6674 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6675 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6676 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6677 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6678 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6679 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6680 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6681 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6682 \alu_logical0_logical_op__zero_a + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6710 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6715 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -229655,54 +232158,54 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6683 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6684 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6688 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6687 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6685 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6686 1'0 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 1'0 case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6683 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6667 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6684 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6668 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6685 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6676 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6686 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6677 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6687 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6679 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6688 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6680 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 end sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6647 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[12:0]$6648 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6649 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6650 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6651 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6652 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6653 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6654 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6655 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6656 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6657 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6658 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6659 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6660 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6661 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6662 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6663 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6664 + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6692 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6697 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 end - attribute \src "libresoc.v:140551.3-140572.6" - process $proc$libresoc.v:140551$6689 + attribute \src "libresoc.v:142341.3-142362.6" + process $proc$libresoc.v:142341$6734 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$6690 $2\data_r0__o$next[63:0]$6694 + assign $0\data_r0__o$next[63:0]$6735 $2\data_r0__o$next[63:0]$6739 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6691 $3\data_r0__o_ok$next[0:0]$6696 - attribute \src "libresoc.v:140552.5-140552.29" + assign $0\data_r0__o_ok$next[0:0]$6736 $3\data_r0__o_ok$next[0:0]$6741 + attribute \src "libresoc.v:142342.5-142342.29" switch \initial - attribute \src "libresoc.v:140552.9-140552.17" + attribute \src "libresoc.v:142342.9-142342.17" case 1'1 case end @@ -229712,10 +232215,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6693 $1\data_r0__o$next[63:0]$6692 } { \o_ok \alu_logical0_o } + assign { $1\data_r0__o_ok$next[0:0]$6738 $1\data_r0__o$next[63:0]$6737 } { \o_ok \alu_logical0_o } case - assign $1\data_r0__o$next[63:0]$6692 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6693 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$6737 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6738 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -229723,38 +232226,38 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6695 $2\data_r0__o$next[63:0]$6694 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$6740 $2\data_r0__o$next[63:0]$6739 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$6694 $1\data_r0__o$next[63:0]$6692 - assign $2\data_r0__o_ok$next[0:0]$6695 $1\data_r0__o_ok$next[0:0]$6693 + assign $2\data_r0__o$next[63:0]$6739 $1\data_r0__o$next[63:0]$6737 + assign $2\data_r0__o_ok$next[0:0]$6740 $1\data_r0__o_ok$next[0:0]$6738 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6696 1'0 + assign $3\data_r0__o_ok$next[0:0]$6741 1'0 case - assign $3\data_r0__o_ok$next[0:0]$6696 $2\data_r0__o_ok$next[0:0]$6695 + assign $3\data_r0__o_ok$next[0:0]$6741 $2\data_r0__o_ok$next[0:0]$6740 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6690 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6691 + update \data_r0__o$next $0\data_r0__o$next[63:0]$6735 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6736 end - attribute \src "libresoc.v:140573.3-140594.6" - process $proc$libresoc.v:140573$6697 + attribute \src "libresoc.v:142363.3-142384.6" + process $proc$libresoc.v:142363$6742 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6698 $2\data_r1__cr_a$next[3:0]$6702 + assign $0\data_r1__cr_a$next[3:0]$6743 $2\data_r1__cr_a$next[3:0]$6747 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6699 $3\data_r1__cr_a_ok$next[0:0]$6704 - attribute \src "libresoc.v:140574.5-140574.29" + assign $0\data_r1__cr_a_ok$next[0:0]$6744 $3\data_r1__cr_a_ok$next[0:0]$6749 + attribute \src "libresoc.v:142364.5-142364.29" switch \initial - attribute \src "libresoc.v:140574.9-140574.17" + attribute \src "libresoc.v:142364.9-142364.17" case 1'1 case end @@ -229764,10 +232267,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6701 $1\data_r1__cr_a$next[3:0]$6700 } { \cr_a_ok \alu_logical0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$6746 $1\data_r1__cr_a$next[3:0]$6745 } { \cr_a_ok \alu_logical0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$6700 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6701 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$6745 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6746 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -229775,32 +232278,32 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6703 $2\data_r1__cr_a$next[3:0]$6702 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$6748 $2\data_r1__cr_a$next[3:0]$6747 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$6702 $1\data_r1__cr_a$next[3:0]$6700 - assign $2\data_r1__cr_a_ok$next[0:0]$6703 $1\data_r1__cr_a_ok$next[0:0]$6701 + assign $2\data_r1__cr_a$next[3:0]$6747 $1\data_r1__cr_a$next[3:0]$6745 + assign $2\data_r1__cr_a_ok$next[0:0]$6748 $1\data_r1__cr_a_ok$next[0:0]$6746 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6704 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$6749 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$6704 $2\data_r1__cr_a_ok$next[0:0]$6703 + assign $3\data_r1__cr_a_ok$next[0:0]$6749 $2\data_r1__cr_a_ok$next[0:0]$6748 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6698 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6699 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6743 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6744 end - attribute \src "libresoc.v:140595.3-140604.6" - process $proc$libresoc.v:140595$6705 + attribute \src "libresoc.v:142385.3-142394.6" + process $proc$libresoc.v:142385$6750 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6706 $1\src_r0$next[63:0]$6707 - attribute \src "libresoc.v:140596.5-140596.29" + assign $0\src_r0$next[63:0]$6751 $1\src_r0$next[63:0]$6752 + attribute \src "libresoc.v:142386.5-142386.29" switch \initial - attribute \src "libresoc.v:140596.9-140596.17" + attribute \src "libresoc.v:142386.9-142386.17" case 1'1 case end @@ -229809,21 +232312,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6707 \src_or_imm + assign $1\src_r0$next[63:0]$6752 \src_or_imm case - assign $1\src_r0$next[63:0]$6707 \src_r0 + assign $1\src_r0$next[63:0]$6752 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6706 + update \src_r0$next $0\src_r0$next[63:0]$6751 end - attribute \src "libresoc.v:140605.3-140614.6" - process $proc$libresoc.v:140605$6708 + attribute \src "libresoc.v:142395.3-142404.6" + process $proc$libresoc.v:142395$6753 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6709 $1\src_r1$next[63:0]$6710 - attribute \src "libresoc.v:140606.5-140606.29" + assign $0\src_r1$next[63:0]$6754 $1\src_r1$next[63:0]$6755 + attribute \src "libresoc.v:142396.5-142396.29" switch \initial - attribute \src "libresoc.v:140606.9-140606.17" + attribute \src "libresoc.v:142396.9-142396.17" case 1'1 case end @@ -229832,21 +232335,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6710 \src_or_imm$80 + assign $1\src_r1$next[63:0]$6755 \src_or_imm$80 case - assign $1\src_r1$next[63:0]$6710 \src_r1 + assign $1\src_r1$next[63:0]$6755 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6709 + update \src_r1$next $0\src_r1$next[63:0]$6754 end - attribute \src "libresoc.v:140615.3-140624.6" - process $proc$libresoc.v:140615$6711 + attribute \src "libresoc.v:142405.3-142414.6" + process $proc$libresoc.v:142405$6756 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$6712 $1\src_r2$next[0:0]$6713 - attribute \src "libresoc.v:140616.5-140616.29" + assign $0\src_r2$next[0:0]$6757 $1\src_r2$next[0:0]$6758 + attribute \src "libresoc.v:142406.5-142406.29" switch \initial - attribute \src "libresoc.v:140616.9-140616.17" + attribute \src "libresoc.v:142406.9-142406.17" case 1'1 case end @@ -229855,21 +232358,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$6713 \src3_i + assign $1\src_r2$next[0:0]$6758 \src3_i case - assign $1\src_r2$next[0:0]$6713 \src_r2 + assign $1\src_r2$next[0:0]$6758 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$6712 + update \src_r2$next $0\src_r2$next[0:0]$6757 end - attribute \src "libresoc.v:140625.3-140633.6" - process $proc$libresoc.v:140625$6714 + attribute \src "libresoc.v:142415.3-142423.6" + process $proc$libresoc.v:142415$6759 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6715 $1\alui_l_r_alui$next[0:0]$6716 - attribute \src "libresoc.v:140626.5-140626.29" + assign $0\alui_l_r_alui$next[0:0]$6760 $1\alui_l_r_alui$next[0:0]$6761 + attribute \src "libresoc.v:142416.5-142416.29" switch \initial - attribute \src "libresoc.v:140626.9-140626.17" + attribute \src "libresoc.v:142416.9-142416.17" case 1'1 case end @@ -229878,21 +232381,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6716 1'1 + assign $1\alui_l_r_alui$next[0:0]$6761 1'1 case - assign $1\alui_l_r_alui$next[0:0]$6716 \$89 + assign $1\alui_l_r_alui$next[0:0]$6761 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6715 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6760 end - attribute \src "libresoc.v:140634.3-140642.6" - process $proc$libresoc.v:140634$6717 + attribute \src "libresoc.v:142424.3-142432.6" + process $proc$libresoc.v:142424$6762 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6718 $1\alu_l_r_alu$next[0:0]$6719 - attribute \src "libresoc.v:140635.5-140635.29" + assign $0\alu_l_r_alu$next[0:0]$6763 $1\alu_l_r_alu$next[0:0]$6764 + attribute \src "libresoc.v:142425.5-142425.29" switch \initial - attribute \src "libresoc.v:140635.9-140635.17" + attribute \src "libresoc.v:142425.9-142425.17" case 1'1 case end @@ -229901,21 +232404,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6719 1'1 + assign $1\alu_l_r_alu$next[0:0]$6764 1'1 case - assign $1\alu_l_r_alu$next[0:0]$6719 \$91 + assign $1\alu_l_r_alu$next[0:0]$6764 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6718 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6763 end - attribute \src "libresoc.v:140643.3-140652.6" - process $proc$libresoc.v:140643$6720 + attribute \src "libresoc.v:142433.3-142442.6" + process $proc$libresoc.v:142433$6765 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:140644.5-140644.29" + attribute \src "libresoc.v:142434.5-142434.29" switch \initial - attribute \src "libresoc.v:140644.9-140644.17" + attribute \src "libresoc.v:142434.9-142434.17" case 1'1 case end @@ -229931,14 +232434,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:140653.3-140662.6" - process $proc$libresoc.v:140653$6721 + attribute \src "libresoc.v:142443.3-142452.6" + process $proc$libresoc.v:142443$6766 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:140654.5-140654.29" + attribute \src "libresoc.v:142444.5-142444.29" switch \initial - attribute \src "libresoc.v:140654.9-140654.17" + attribute \src "libresoc.v:142444.9-142444.17" case 1'1 case end @@ -229954,14 +232457,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:140663.3-140671.6" - process $proc$libresoc.v:140663$6722 + attribute \src "libresoc.v:142453.3-142461.6" + process $proc$libresoc.v:142453$6767 assign { } { } assign { } { } - assign $0\prev_wr_go$next[1:0]$6723 $1\prev_wr_go$next[1:0]$6724 - attribute \src "libresoc.v:140664.5-140664.29" + assign $0\prev_wr_go$next[1:0]$6768 $1\prev_wr_go$next[1:0]$6769 + attribute \src "libresoc.v:142454.5-142454.29" switch \initial - attribute \src "libresoc.v:140664.9-140664.17" + attribute \src "libresoc.v:142454.9-142454.17" case 1'1 case end @@ -229970,70 +232473,70 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[1:0]$6724 2'00 - case - assign $1\prev_wr_go$next[1:0]$6724 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6723 - end - connect \$9 $and$libresoc.v:140194$6518_Y - connect \$99 $and$libresoc.v:140195$6519_Y - connect \$101 $not$libresoc.v:140196$6520_Y - connect \$103 $and$libresoc.v:140197$6521_Y - connect \$105 $and$libresoc.v:140198$6522_Y - connect \$107 $and$libresoc.v:140199$6523_Y - connect \$109 $and$libresoc.v:140200$6524_Y - connect \$111 $and$libresoc.v:140201$6525_Y - connect \$113 $and$libresoc.v:140202$6526_Y - connect \$115 $and$libresoc.v:140203$6527_Y - connect \$11 $not$libresoc.v:140204$6528_Y - connect \$13 $and$libresoc.v:140205$6529_Y - connect \$15 $not$libresoc.v:140206$6530_Y - connect \$17 $and$libresoc.v:140207$6531_Y - connect \$1 $and$libresoc.v:140208$6532_Y - connect \$19 $and$libresoc.v:140209$6533_Y - connect \$23 $not$libresoc.v:140210$6534_Y - connect \$25 $and$libresoc.v:140211$6535_Y - connect \$22 $reduce_or$libresoc.v:140212$6536_Y - connect \$21 $not$libresoc.v:140213$6537_Y - connect \$29 $and$libresoc.v:140214$6538_Y - connect \$31 $reduce_or$libresoc.v:140215$6539_Y - connect \$33 $reduce_or$libresoc.v:140216$6540_Y - connect \$35 $or$libresoc.v:140217$6541_Y - connect \$37 $not$libresoc.v:140218$6542_Y - connect \$39 $and$libresoc.v:140219$6543_Y - connect \$41 $and$libresoc.v:140220$6544_Y - connect \$43 $eq$libresoc.v:140221$6545_Y - connect \$45 $and$libresoc.v:140222$6546_Y - connect \$47 $eq$libresoc.v:140223$6547_Y - connect \$4 $not$libresoc.v:140224$6548_Y - connect \$49 $and$libresoc.v:140225$6549_Y - connect \$51 $and$libresoc.v:140226$6550_Y - connect \$53 $and$libresoc.v:140227$6551_Y - connect \$55 $or$libresoc.v:140228$6552_Y - connect \$57 $or$libresoc.v:140229$6553_Y - connect \$59 $or$libresoc.v:140230$6554_Y - connect \$61 $or$libresoc.v:140231$6555_Y - connect \$63 $and$libresoc.v:140232$6556_Y - connect \$65 $and$libresoc.v:140233$6557_Y - connect \$67 $or$libresoc.v:140234$6558_Y - connect \$6 $or$libresoc.v:140235$6559_Y - connect \$69 $and$libresoc.v:140236$6560_Y - connect \$71 $and$libresoc.v:140237$6561_Y - connect \$73 $ternary$libresoc.v:140238$6562_Y - connect \$75 $ternary$libresoc.v:140239$6563_Y - connect \$78 $ternary$libresoc.v:140240$6564_Y - connect \$3 $reduce_and$libresoc.v:140241$6565_Y - connect \$81 $ternary$libresoc.v:140242$6566_Y - connect \$83 $ternary$libresoc.v:140243$6567_Y - connect \$85 $ternary$libresoc.v:140244$6568_Y - connect \$87 $ternary$libresoc.v:140245$6569_Y - connect \$89 $and$libresoc.v:140246$6570_Y - connect \$91 $and$libresoc.v:140247$6571_Y - connect \$93 $and$libresoc.v:140248$6572_Y - connect \$95 $not$libresoc.v:140249$6573_Y - connect \$97 $not$libresoc.v:140250$6574_Y + assign $1\prev_wr_go$next[1:0]$6769 2'00 + case + assign $1\prev_wr_go$next[1:0]$6769 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6768 + end + connect \$9 $and$libresoc.v:141984$6563_Y + connect \$99 $and$libresoc.v:141985$6564_Y + connect \$101 $not$libresoc.v:141986$6565_Y + connect \$103 $and$libresoc.v:141987$6566_Y + connect \$105 $and$libresoc.v:141988$6567_Y + connect \$107 $and$libresoc.v:141989$6568_Y + connect \$109 $and$libresoc.v:141990$6569_Y + connect \$111 $and$libresoc.v:141991$6570_Y + connect \$113 $and$libresoc.v:141992$6571_Y + connect \$115 $and$libresoc.v:141993$6572_Y + connect \$11 $not$libresoc.v:141994$6573_Y + connect \$13 $and$libresoc.v:141995$6574_Y + connect \$15 $not$libresoc.v:141996$6575_Y + connect \$17 $and$libresoc.v:141997$6576_Y + connect \$1 $and$libresoc.v:141998$6577_Y + connect \$19 $and$libresoc.v:141999$6578_Y + connect \$23 $not$libresoc.v:142000$6579_Y + connect \$25 $and$libresoc.v:142001$6580_Y + connect \$22 $reduce_or$libresoc.v:142002$6581_Y + connect \$21 $not$libresoc.v:142003$6582_Y + connect \$29 $and$libresoc.v:142004$6583_Y + connect \$31 $reduce_or$libresoc.v:142005$6584_Y + connect \$33 $reduce_or$libresoc.v:142006$6585_Y + connect \$35 $or$libresoc.v:142007$6586_Y + connect \$37 $not$libresoc.v:142008$6587_Y + connect \$39 $and$libresoc.v:142009$6588_Y + connect \$41 $and$libresoc.v:142010$6589_Y + connect \$43 $eq$libresoc.v:142011$6590_Y + connect \$45 $and$libresoc.v:142012$6591_Y + connect \$47 $eq$libresoc.v:142013$6592_Y + connect \$4 $not$libresoc.v:142014$6593_Y + connect \$49 $and$libresoc.v:142015$6594_Y + connect \$51 $and$libresoc.v:142016$6595_Y + connect \$53 $and$libresoc.v:142017$6596_Y + connect \$55 $or$libresoc.v:142018$6597_Y + connect \$57 $or$libresoc.v:142019$6598_Y + connect \$59 $or$libresoc.v:142020$6599_Y + connect \$61 $or$libresoc.v:142021$6600_Y + connect \$63 $and$libresoc.v:142022$6601_Y + connect \$65 $and$libresoc.v:142023$6602_Y + connect \$67 $or$libresoc.v:142024$6603_Y + connect \$6 $or$libresoc.v:142025$6604_Y + connect \$69 $and$libresoc.v:142026$6605_Y + connect \$71 $and$libresoc.v:142027$6606_Y + connect \$73 $ternary$libresoc.v:142028$6607_Y + connect \$75 $ternary$libresoc.v:142029$6608_Y + connect \$78 $ternary$libresoc.v:142030$6609_Y + connect \$3 $reduce_and$libresoc.v:142031$6610_Y + connect \$81 $ternary$libresoc.v:142032$6611_Y + connect \$83 $ternary$libresoc.v:142033$6612_Y + connect \$85 $ternary$libresoc.v:142034$6613_Y + connect \$87 $ternary$libresoc.v:142035$6614_Y + connect \$89 $and$libresoc.v:142036$6615_Y + connect \$91 $and$libresoc.v:142037$6616_Y + connect \$93 $and$libresoc.v:142038$6617_Y + connect \$95 $not$libresoc.v:142039$6618_Y + connect \$97 $not$libresoc.v:142040$6619_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -230067,248 +232570,248 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:140708.1-142085.10" +attribute \src "libresoc.v:142498.1-143889.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:142024.3-142042.6" - wire width 4 $0\cr_a$next[3:0]$6850 - attribute \src "libresoc.v:141784.3-141785.25" + attribute \src "libresoc.v:143828.3-143846.6" + wire width 4 $0\cr_a$next[3:0]$6895 + attribute \src "libresoc.v:143588.3-143589.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:142024.3-142042.6" - wire $0\cr_a_ok$next[0:0]$6851 - attribute \src "libresoc.v:141786.3-141787.31" + attribute \src "libresoc.v:143828.3-143846.6" + wire $0\cr_a_ok$next[0:0]$6896 + attribute \src "libresoc.v:143590.3-143591.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:140709.7-140709.20" + attribute \src "libresoc.v:142499.7-142499.20" wire $0\initial[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 4 $0\logical_op__data_len$next[3:0]$6801 - attribute \src "libresoc.v:141824.3-141825.57" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6846 + attribute \src "libresoc.v:143628.3-143629.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 13 $0\logical_op__fn_unit$next[12:0]$6802 - attribute \src "libresoc.v:141794.3-141795.55" - wire width 13 $0\logical_op__fn_unit[12:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$6803 - attribute \src "libresoc.v:141796.3-141797.69" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$6847 + attribute \src "libresoc.v:143598.3-143599.55" + wire width 14 $0\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:143767.3-143808.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6848 + attribute \src "libresoc.v:143600.3-143601.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__imm_data__ok$next[0:0]$6804 - attribute \src "libresoc.v:141798.3-141799.65" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6849 + attribute \src "libresoc.v:143602.3-143603.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$6805 - attribute \src "libresoc.v:141812.3-141813.63" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6850 + attribute \src "libresoc.v:143616.3-143617.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 32 $0\logical_op__insn$next[31:0]$6806 - attribute \src "libresoc.v:141826.3-141827.49" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 32 $0\logical_op__insn$next[31:0]$6851 + attribute \src "libresoc.v:143630.3-143631.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$6807 - attribute \src "libresoc.v:141792.3-141793.59" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6852 + attribute \src "libresoc.v:143596.3-143597.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__invert_in$next[0:0]$6808 - attribute \src "libresoc.v:141808.3-141809.59" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__invert_in$next[0:0]$6853 + attribute \src "libresoc.v:143612.3-143613.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__invert_out$next[0:0]$6809 - attribute \src "libresoc.v:141814.3-141815.61" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__invert_out$next[0:0]$6854 + attribute \src "libresoc.v:143618.3-143619.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__is_32bit$next[0:0]$6810 - attribute \src "libresoc.v:141820.3-141821.57" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__is_32bit$next[0:0]$6855 + attribute \src "libresoc.v:143624.3-143625.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__is_signed$next[0:0]$6811 - attribute \src "libresoc.v:141822.3-141823.59" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__is_signed$next[0:0]$6856 + attribute \src "libresoc.v:143626.3-143627.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__oe__oe$next[0:0]$6812 - attribute \src "libresoc.v:141804.3-141805.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__oe__oe$next[0:0]$6857 + attribute \src "libresoc.v:143608.3-143609.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__oe__ok$next[0:0]$6813 - attribute \src "libresoc.v:141806.3-141807.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__oe__ok$next[0:0]$6858 + attribute \src "libresoc.v:143610.3-143611.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__output_carry$next[0:0]$6814 - attribute \src "libresoc.v:141818.3-141819.65" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__output_carry$next[0:0]$6859 + attribute \src "libresoc.v:143622.3-143623.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__rc__ok$next[0:0]$6815 - attribute \src "libresoc.v:141802.3-141803.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__rc__ok$next[0:0]$6860 + attribute \src "libresoc.v:143606.3-143607.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__rc__rc$next[0:0]$6816 - attribute \src "libresoc.v:141800.3-141801.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__rc__rc$next[0:0]$6861 + attribute \src "libresoc.v:143604.3-143605.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__write_cr0$next[0:0]$6817 - attribute \src "libresoc.v:141816.3-141817.59" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__write_cr0$next[0:0]$6862 + attribute \src "libresoc.v:143620.3-143621.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $0\logical_op__zero_a$next[0:0]$6818 - attribute \src "libresoc.v:141810.3-141811.53" + attribute \src "libresoc.v:143767.3-143808.6" + wire $0\logical_op__zero_a$next[0:0]$6863 + attribute \src "libresoc.v:143614.3-143615.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:141950.3-141962.6" - wire width 2 $0\muxid$next[1:0]$6798 - attribute \src "libresoc.v:141828.3-141829.27" + attribute \src "libresoc.v:143754.3-143766.6" + wire width 2 $0\muxid$next[1:0]$6843 + attribute \src "libresoc.v:143632.3-143633.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:142005.3-142023.6" - wire width 64 $0\o$next[63:0]$6844 - attribute \src "libresoc.v:141788.3-141789.19" + attribute \src "libresoc.v:143809.3-143827.6" + wire width 64 $0\o$next[63:0]$6889 + attribute \src "libresoc.v:143592.3-143593.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:142005.3-142023.6" - wire $0\o_ok$next[0:0]$6845 - attribute \src "libresoc.v:141790.3-141791.25" + attribute \src "libresoc.v:143809.3-143827.6" + wire $0\o_ok$next[0:0]$6890 + attribute \src "libresoc.v:143594.3-143595.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:141932.3-141949.6" - wire $0\r_busy$next[0:0]$6794 - attribute \src "libresoc.v:141830.3-141831.29" + attribute \src "libresoc.v:143736.3-143753.6" + wire $0\r_busy$next[0:0]$6839 + attribute \src "libresoc.v:143634.3-143635.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:142043.3-142061.6" - wire $0\xer_so$next[0:0]$6856 - attribute \src "libresoc.v:141780.3-141781.29" + attribute \src "libresoc.v:143847.3-143865.6" + wire $0\xer_so$next[0:0]$6901 + attribute \src "libresoc.v:143584.3-143585.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:142043.3-142061.6" - wire $0\xer_so_ok$next[0:0]$6857 - attribute \src "libresoc.v:141782.3-141783.35" + attribute \src "libresoc.v:143847.3-143865.6" + wire $0\xer_so_ok$next[0:0]$6902 + attribute \src "libresoc.v:143586.3-143587.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:142024.3-142042.6" - wire width 4 $1\cr_a$next[3:0]$6852 - attribute \src "libresoc.v:140718.13-140718.24" + attribute \src "libresoc.v:143828.3-143846.6" + wire width 4 $1\cr_a$next[3:0]$6897 + attribute \src "libresoc.v:142508.13-142508.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:142024.3-142042.6" - wire $1\cr_a_ok$next[0:0]$6853 - attribute \src "libresoc.v:140727.7-140727.21" + attribute \src "libresoc.v:143828.3-143846.6" + wire $1\cr_a_ok$next[0:0]$6898 + attribute \src "libresoc.v:142517.7-142517.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 4 $1\logical_op__data_len$next[3:0]$6819 - attribute \src "libresoc.v:141008.13-141008.40" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6864 + attribute \src "libresoc.v:142802.13-142802.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 13 $1\logical_op__fn_unit$next[12:0]$6820 - attribute \src "libresoc.v:141031.14-141031.44" - wire width 13 $1\logical_op__fn_unit[12:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$6821 - attribute \src "libresoc.v:141068.14-141068.63" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$6865 + attribute \src "libresoc.v:142826.14-142826.44" + wire width 14 $1\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:143767.3-143808.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6866 + attribute \src "libresoc.v:142865.14-142865.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__imm_data__ok$next[0:0]$6822 - attribute \src "libresoc.v:141077.7-141077.38" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6867 + attribute \src "libresoc.v:142874.7-142874.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$6823 - attribute \src "libresoc.v:141090.13-141090.43" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6868 + attribute \src "libresoc.v:142887.13-142887.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 32 $1\logical_op__insn$next[31:0]$6824 - attribute \src "libresoc.v:141107.14-141107.38" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 32 $1\logical_op__insn$next[31:0]$6869 + attribute \src "libresoc.v:142904.14-142904.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$6825 - attribute \src "libresoc.v:141190.13-141190.42" + attribute \src "libresoc.v:143767.3-143808.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6870 + attribute \src "libresoc.v:142988.13-142988.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__invert_in$next[0:0]$6826 - attribute \src "libresoc.v:141347.7-141347.35" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__invert_in$next[0:0]$6871 + attribute \src "libresoc.v:143147.7-143147.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__invert_out$next[0:0]$6827 - attribute \src "libresoc.v:141356.7-141356.36" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__invert_out$next[0:0]$6872 + attribute \src "libresoc.v:143156.7-143156.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__is_32bit$next[0:0]$6828 - attribute \src "libresoc.v:141365.7-141365.34" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__is_32bit$next[0:0]$6873 + attribute \src "libresoc.v:143165.7-143165.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__is_signed$next[0:0]$6829 - attribute \src "libresoc.v:141374.7-141374.35" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__is_signed$next[0:0]$6874 + attribute \src "libresoc.v:143174.7-143174.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__oe__oe$next[0:0]$6830 - attribute \src "libresoc.v:141383.7-141383.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__oe__oe$next[0:0]$6875 + attribute \src "libresoc.v:143183.7-143183.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__oe__ok$next[0:0]$6831 - attribute \src "libresoc.v:141392.7-141392.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__oe__ok$next[0:0]$6876 + attribute \src "libresoc.v:143192.7-143192.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__output_carry$next[0:0]$6832 - attribute \src "libresoc.v:141401.7-141401.38" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__output_carry$next[0:0]$6877 + attribute \src "libresoc.v:143201.7-143201.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__rc__ok$next[0:0]$6833 - attribute \src "libresoc.v:141410.7-141410.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__rc__ok$next[0:0]$6878 + attribute \src "libresoc.v:143210.7-143210.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__rc__rc$next[0:0]$6834 - attribute \src "libresoc.v:141419.7-141419.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__rc__rc$next[0:0]$6879 + attribute \src "libresoc.v:143219.7-143219.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__write_cr0$next[0:0]$6835 - attribute \src "libresoc.v:141428.7-141428.35" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__write_cr0$next[0:0]$6880 + attribute \src "libresoc.v:143228.7-143228.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:141963.3-142004.6" - wire $1\logical_op__zero_a$next[0:0]$6836 - attribute \src "libresoc.v:141437.7-141437.32" + attribute \src "libresoc.v:143767.3-143808.6" + wire $1\logical_op__zero_a$next[0:0]$6881 + attribute \src "libresoc.v:143237.7-143237.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:141950.3-141962.6" - wire width 2 $1\muxid$next[1:0]$6799 - attribute \src "libresoc.v:141718.13-141718.25" + attribute \src "libresoc.v:143754.3-143766.6" + wire width 2 $1\muxid$next[1:0]$6844 + attribute \src "libresoc.v:143522.13-143522.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:142005.3-142023.6" - wire width 64 $1\o$next[63:0]$6846 - attribute \src "libresoc.v:141733.14-141733.38" + attribute \src "libresoc.v:143809.3-143827.6" + wire width 64 $1\o$next[63:0]$6891 + attribute \src "libresoc.v:143537.14-143537.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:142005.3-142023.6" - wire $1\o_ok$next[0:0]$6847 - attribute \src "libresoc.v:141740.7-141740.18" + attribute \src "libresoc.v:143809.3-143827.6" + wire $1\o_ok$next[0:0]$6892 + attribute \src "libresoc.v:143544.7-143544.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:141932.3-141949.6" - wire $1\r_busy$next[0:0]$6795 - attribute \src "libresoc.v:141754.7-141754.20" + attribute \src "libresoc.v:143736.3-143753.6" + wire $1\r_busy$next[0:0]$6840 + attribute \src "libresoc.v:143558.7-143558.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:142043.3-142061.6" - wire $1\xer_so$next[0:0]$6858 - attribute \src "libresoc.v:141763.7-141763.20" + attribute \src "libresoc.v:143847.3-143865.6" + wire $1\xer_so$next[0:0]$6903 + attribute \src "libresoc.v:143567.7-143567.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:142043.3-142061.6" - wire $1\xer_so_ok$next[0:0]$6859 - attribute \src "libresoc.v:141772.7-141772.23" + attribute \src "libresoc.v:143847.3-143865.6" + wire $1\xer_so_ok$next[0:0]$6904 + attribute \src "libresoc.v:143576.7-143576.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:142024.3-142042.6" - wire $2\cr_a_ok$next[0:0]$6854 - attribute \src "libresoc.v:141963.3-142004.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$6837 - attribute \src "libresoc.v:141963.3-142004.6" - wire $2\logical_op__imm_data__ok$next[0:0]$6838 - attribute \src "libresoc.v:141963.3-142004.6" - wire $2\logical_op__oe__oe$next[0:0]$6839 - attribute \src "libresoc.v:141963.3-142004.6" - wire $2\logical_op__oe__ok$next[0:0]$6840 - attribute \src "libresoc.v:141963.3-142004.6" - wire $2\logical_op__rc__ok$next[0:0]$6841 - attribute \src "libresoc.v:141963.3-142004.6" - wire $2\logical_op__rc__rc$next[0:0]$6842 - attribute \src "libresoc.v:142005.3-142023.6" - wire $2\o_ok$next[0:0]$6848 - attribute \src "libresoc.v:141932.3-141949.6" - wire $2\r_busy$next[0:0]$6796 - attribute \src "libresoc.v:142043.3-142061.6" - wire $2\xer_so_ok$next[0:0]$6860 - attribute \src "libresoc.v:141779.18-141779.118" - wire $and$libresoc.v:141779$6766_Y + attribute \src "libresoc.v:143828.3-143846.6" + wire $2\cr_a_ok$next[0:0]$6899 + attribute \src "libresoc.v:143767.3-143808.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$6882 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__imm_data__ok$next[0:0]$6883 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__oe__oe$next[0:0]$6884 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__oe__ok$next[0:0]$6885 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__rc__ok$next[0:0]$6886 + attribute \src "libresoc.v:143767.3-143808.6" + wire $2\logical_op__rc__rc$next[0:0]$6887 + attribute \src "libresoc.v:143809.3-143827.6" + wire $2\o_ok$next[0:0]$6893 + attribute \src "libresoc.v:143736.3-143753.6" + wire $2\r_busy$next[0:0]$6841 + attribute \src "libresoc.v:143847.3-143865.6" + wire $2\xer_so_ok$next[0:0]$6905 + attribute \src "libresoc.v:143583.18-143583.118" + wire $and$libresoc.v:143583$6811_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -230326,44 +232829,46 @@ module \logical_pipe1 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:140709.7-140709.15" + attribute \src "libresoc.v:142499.7-142499.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len$38 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_logical_op__fn_unit$23 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -230462,6 +232967,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -230538,6 +233044,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -230609,55 +233116,58 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 33 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 33 \logical_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -230776,6 +233286,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -230852,6 +233363,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 32 \logical_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -230928,6 +233440,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -231025,37 +233538,39 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \main_logical_op__data_len$60 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_logical_op__fn_unit$45 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_logical_op__fn_unit$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -231154,6 +233669,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -231230,6 +233746,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_logical_op__insn_type$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -231351,7 +233868,7 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:141779$6766 + cell $and $and$libresoc.v:143583$6811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231359,10 +233876,10 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:141779$6766_Y + connect \Y $and$libresoc.v:143583$6811_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:141832.14-141877.4" + attribute \src "libresoc.v:143636.14-143681.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 @@ -231410,7 +233927,7 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:141878.13-141923.4" + attribute \src "libresoc.v:143682.13-143727.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 @@ -231458,424 +233975,424 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:141924.10-141927.4" + attribute \src "libresoc.v:143728.10-143731.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:141928.10-141931.4" + attribute \src "libresoc.v:143732.10-143735.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:140709.7-140709.20" - process $proc$libresoc.v:140709$6861 + attribute \src "libresoc.v:142499.7-142499.20" + process $proc$libresoc.v:142499$6906 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140718.13-140718.24" - process $proc$libresoc.v:140718$6862 + attribute \src "libresoc.v:142508.13-142508.24" + process $proc$libresoc.v:142508$6907 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:140727.7-140727.21" - process $proc$libresoc.v:140727$6863 + attribute \src "libresoc.v:142517.7-142517.21" + process $proc$libresoc.v:142517$6908 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:141008.13-141008.40" - process $proc$libresoc.v:141008$6864 + attribute \src "libresoc.v:142802.13-142802.40" + process $proc$libresoc.v:142802$6909 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:141031.14-141031.44" - process $proc$libresoc.v:141031$6865 + attribute \src "libresoc.v:142826.14-142826.44" + process $proc$libresoc.v:142826$6910 assign { } { } - assign $1\logical_op__fn_unit[12:0] 13'0000000000000 + assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[12:0] + update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:141068.14-141068.63" - process $proc$libresoc.v:141068$6866 + attribute \src "libresoc.v:142865.14-142865.63" + process $proc$libresoc.v:142865$6911 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:141077.7-141077.38" - process $proc$libresoc.v:141077$6867 + attribute \src "libresoc.v:142874.7-142874.38" + process $proc$libresoc.v:142874$6912 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:141090.13-141090.43" - process $proc$libresoc.v:141090$6868 + attribute \src "libresoc.v:142887.13-142887.43" + process $proc$libresoc.v:142887$6913 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:141107.14-141107.38" - process $proc$libresoc.v:141107$6869 + attribute \src "libresoc.v:142904.14-142904.38" + process $proc$libresoc.v:142904$6914 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:141190.13-141190.42" - process $proc$libresoc.v:141190$6870 + attribute \src "libresoc.v:142988.13-142988.42" + process $proc$libresoc.v:142988$6915 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:141347.7-141347.35" - process $proc$libresoc.v:141347$6871 + attribute \src "libresoc.v:143147.7-143147.35" + process $proc$libresoc.v:143147$6916 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:141356.7-141356.36" - process $proc$libresoc.v:141356$6872 + attribute \src "libresoc.v:143156.7-143156.36" + process $proc$libresoc.v:143156$6917 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:141365.7-141365.34" - process $proc$libresoc.v:141365$6873 + attribute \src "libresoc.v:143165.7-143165.34" + process $proc$libresoc.v:143165$6918 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:141374.7-141374.35" - process $proc$libresoc.v:141374$6874 + attribute \src "libresoc.v:143174.7-143174.35" + process $proc$libresoc.v:143174$6919 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:141383.7-141383.32" - process $proc$libresoc.v:141383$6875 + attribute \src "libresoc.v:143183.7-143183.32" + process $proc$libresoc.v:143183$6920 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:141392.7-141392.32" - process $proc$libresoc.v:141392$6876 + attribute \src "libresoc.v:143192.7-143192.32" + process $proc$libresoc.v:143192$6921 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:141401.7-141401.38" - process $proc$libresoc.v:141401$6877 + attribute \src "libresoc.v:143201.7-143201.38" + process $proc$libresoc.v:143201$6922 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:141410.7-141410.32" - process $proc$libresoc.v:141410$6878 + attribute \src "libresoc.v:143210.7-143210.32" + process $proc$libresoc.v:143210$6923 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:141419.7-141419.32" - process $proc$libresoc.v:141419$6879 + attribute \src "libresoc.v:143219.7-143219.32" + process $proc$libresoc.v:143219$6924 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:141428.7-141428.35" - process $proc$libresoc.v:141428$6880 + attribute \src "libresoc.v:143228.7-143228.35" + process $proc$libresoc.v:143228$6925 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:141437.7-141437.32" - process $proc$libresoc.v:141437$6881 + attribute \src "libresoc.v:143237.7-143237.32" + process $proc$libresoc.v:143237$6926 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:141718.13-141718.25" - process $proc$libresoc.v:141718$6882 + attribute \src "libresoc.v:143522.13-143522.25" + process $proc$libresoc.v:143522$6927 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:141733.14-141733.38" - process $proc$libresoc.v:141733$6883 + attribute \src "libresoc.v:143537.14-143537.38" + process $proc$libresoc.v:143537$6928 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:141740.7-141740.18" - process $proc$libresoc.v:141740$6884 + attribute \src "libresoc.v:143544.7-143544.18" + process $proc$libresoc.v:143544$6929 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:141754.7-141754.20" - process $proc$libresoc.v:141754$6885 + attribute \src "libresoc.v:143558.7-143558.20" + process $proc$libresoc.v:143558$6930 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:141763.7-141763.20" - process $proc$libresoc.v:141763$6886 + attribute \src "libresoc.v:143567.7-143567.20" + process $proc$libresoc.v:143567$6931 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:141772.7-141772.23" - process $proc$libresoc.v:141772$6887 + attribute \src "libresoc.v:143576.7-143576.23" + process $proc$libresoc.v:143576$6932 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:141780.3-141781.29" - process $proc$libresoc.v:141780$6767 + attribute \src "libresoc.v:143584.3-143585.29" + process $proc$libresoc.v:143584$6812 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:141782.3-141783.35" - process $proc$libresoc.v:141782$6768 + attribute \src "libresoc.v:143586.3-143587.35" + process $proc$libresoc.v:143586$6813 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:141784.3-141785.25" - process $proc$libresoc.v:141784$6769 + attribute \src "libresoc.v:143588.3-143589.25" + process $proc$libresoc.v:143588$6814 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:141786.3-141787.31" - process $proc$libresoc.v:141786$6770 + attribute \src "libresoc.v:143590.3-143591.31" + process $proc$libresoc.v:143590$6815 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:141788.3-141789.19" - process $proc$libresoc.v:141788$6771 + attribute \src "libresoc.v:143592.3-143593.19" + process $proc$libresoc.v:143592$6816 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:141790.3-141791.25" - process $proc$libresoc.v:141790$6772 + attribute \src "libresoc.v:143594.3-143595.25" + process $proc$libresoc.v:143594$6817 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:141792.3-141793.59" - process $proc$libresoc.v:141792$6773 + attribute \src "libresoc.v:143596.3-143597.59" + process $proc$libresoc.v:143596$6818 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:141794.3-141795.55" - process $proc$libresoc.v:141794$6774 + attribute \src "libresoc.v:143598.3-143599.55" + process $proc$libresoc.v:143598$6819 assign { } { } - assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next + assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[12:0] + update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:141796.3-141797.69" - process $proc$libresoc.v:141796$6775 + attribute \src "libresoc.v:143600.3-143601.69" + process $proc$libresoc.v:143600$6820 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:141798.3-141799.65" - process $proc$libresoc.v:141798$6776 + attribute \src "libresoc.v:143602.3-143603.65" + process $proc$libresoc.v:143602$6821 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:141800.3-141801.53" - process $proc$libresoc.v:141800$6777 + attribute \src "libresoc.v:143604.3-143605.53" + process $proc$libresoc.v:143604$6822 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:141802.3-141803.53" - process $proc$libresoc.v:141802$6778 + attribute \src "libresoc.v:143606.3-143607.53" + process $proc$libresoc.v:143606$6823 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:141804.3-141805.53" - process $proc$libresoc.v:141804$6779 + attribute \src "libresoc.v:143608.3-143609.53" + process $proc$libresoc.v:143608$6824 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:141806.3-141807.53" - process $proc$libresoc.v:141806$6780 + attribute \src "libresoc.v:143610.3-143611.53" + process $proc$libresoc.v:143610$6825 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:141808.3-141809.59" - process $proc$libresoc.v:141808$6781 + attribute \src "libresoc.v:143612.3-143613.59" + process $proc$libresoc.v:143612$6826 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:141810.3-141811.53" - process $proc$libresoc.v:141810$6782 + attribute \src "libresoc.v:143614.3-143615.53" + process $proc$libresoc.v:143614$6827 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:141812.3-141813.63" - process $proc$libresoc.v:141812$6783 + attribute \src "libresoc.v:143616.3-143617.63" + process $proc$libresoc.v:143616$6828 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:141814.3-141815.61" - process $proc$libresoc.v:141814$6784 + attribute \src "libresoc.v:143618.3-143619.61" + process $proc$libresoc.v:143618$6829 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:141816.3-141817.59" - process $proc$libresoc.v:141816$6785 + attribute \src "libresoc.v:143620.3-143621.59" + process $proc$libresoc.v:143620$6830 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:141818.3-141819.65" - process $proc$libresoc.v:141818$6786 + attribute \src "libresoc.v:143622.3-143623.65" + process $proc$libresoc.v:143622$6831 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:141820.3-141821.57" - process $proc$libresoc.v:141820$6787 + attribute \src "libresoc.v:143624.3-143625.57" + process $proc$libresoc.v:143624$6832 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:141822.3-141823.59" - process $proc$libresoc.v:141822$6788 + attribute \src "libresoc.v:143626.3-143627.59" + process $proc$libresoc.v:143626$6833 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:141824.3-141825.57" - process $proc$libresoc.v:141824$6789 + attribute \src "libresoc.v:143628.3-143629.57" + process $proc$libresoc.v:143628$6834 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:141826.3-141827.49" - process $proc$libresoc.v:141826$6790 + attribute \src "libresoc.v:143630.3-143631.49" + process $proc$libresoc.v:143630$6835 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:141828.3-141829.27" - process $proc$libresoc.v:141828$6791 + attribute \src "libresoc.v:143632.3-143633.27" + process $proc$libresoc.v:143632$6836 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:141830.3-141831.29" - process $proc$libresoc.v:141830$6792 + attribute \src "libresoc.v:143634.3-143635.29" + process $proc$libresoc.v:143634$6837 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:141932.3-141949.6" - process $proc$libresoc.v:141932$6793 + attribute \src "libresoc.v:143736.3-143753.6" + process $proc$libresoc.v:143736$6838 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6794 $2\r_busy$next[0:0]$6796 - attribute \src "libresoc.v:141933.5-141933.29" + assign $0\r_busy$next[0:0]$6839 $2\r_busy$next[0:0]$6841 + attribute \src "libresoc.v:143737.5-143737.29" switch \initial - attribute \src "libresoc.v:141933.9-141933.17" + attribute \src "libresoc.v:143737.9-143737.17" case 1'1 case end @@ -231884,34 +234401,34 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6795 1'1 + assign $1\r_busy$next[0:0]$6840 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6795 1'0 + assign $1\r_busy$next[0:0]$6840 1'0 case - assign $1\r_busy$next[0:0]$6795 \r_busy + assign $1\r_busy$next[0:0]$6840 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6796 1'0 + assign $2\r_busy$next[0:0]$6841 1'0 case - assign $2\r_busy$next[0:0]$6796 $1\r_busy$next[0:0]$6795 + assign $2\r_busy$next[0:0]$6841 $1\r_busy$next[0:0]$6840 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6794 + update \r_busy$next $0\r_busy$next[0:0]$6839 end - attribute \src "libresoc.v:141950.3-141962.6" - process $proc$libresoc.v:141950$6797 + attribute \src "libresoc.v:143754.3-143766.6" + process $proc$libresoc.v:143754$6842 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$6798 $1\muxid$next[1:0]$6799 - attribute \src "libresoc.v:141951.5-141951.29" + assign $0\muxid$next[1:0]$6843 $1\muxid$next[1:0]$6844 + attribute \src "libresoc.v:143755.5-143755.29" switch \initial - attribute \src "libresoc.v:141951.9-141951.17" + attribute \src "libresoc.v:143755.9-143755.17" case 1'1 case end @@ -231920,19 +234437,19 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$6799 \muxid$66 + assign $1\muxid$next[1:0]$6844 \muxid$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$6799 \muxid$66 + assign $1\muxid$next[1:0]$6844 \muxid$66 case - assign $1\muxid$next[1:0]$6799 \muxid + assign $1\muxid$next[1:0]$6844 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$6798 + update \muxid$next $0\muxid$next[1:0]$6843 end - attribute \src "libresoc.v:141963.3-142004.6" - process $proc$libresoc.v:141963$6800 + attribute \src "libresoc.v:143767.3-143808.6" + process $proc$libresoc.v:143767$6845 assign { } { } assign { } { } assign { } { } @@ -231969,33 +234486,33 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$6801 $1\logical_op__data_len$next[3:0]$6819 - assign $0\logical_op__fn_unit$next[12:0]$6802 $1\logical_op__fn_unit$next[12:0]$6820 + assign $0\logical_op__data_len$next[3:0]$6846 $1\logical_op__data_len$next[3:0]$6864 + assign $0\logical_op__fn_unit$next[13:0]$6847 $1\logical_op__fn_unit$next[13:0]$6865 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6805 $1\logical_op__input_carry$next[1:0]$6823 - assign $0\logical_op__insn$next[31:0]$6806 $1\logical_op__insn$next[31:0]$6824 - assign $0\logical_op__insn_type$next[6:0]$6807 $1\logical_op__insn_type$next[6:0]$6825 - assign $0\logical_op__invert_in$next[0:0]$6808 $1\logical_op__invert_in$next[0:0]$6826 - assign $0\logical_op__invert_out$next[0:0]$6809 $1\logical_op__invert_out$next[0:0]$6827 - assign $0\logical_op__is_32bit$next[0:0]$6810 $1\logical_op__is_32bit$next[0:0]$6828 - assign $0\logical_op__is_signed$next[0:0]$6811 $1\logical_op__is_signed$next[0:0]$6829 + assign $0\logical_op__input_carry$next[1:0]$6850 $1\logical_op__input_carry$next[1:0]$6868 + assign $0\logical_op__insn$next[31:0]$6851 $1\logical_op__insn$next[31:0]$6869 + assign $0\logical_op__insn_type$next[6:0]$6852 $1\logical_op__insn_type$next[6:0]$6870 + assign $0\logical_op__invert_in$next[0:0]$6853 $1\logical_op__invert_in$next[0:0]$6871 + assign $0\logical_op__invert_out$next[0:0]$6854 $1\logical_op__invert_out$next[0:0]$6872 + assign $0\logical_op__is_32bit$next[0:0]$6855 $1\logical_op__is_32bit$next[0:0]$6873 + assign $0\logical_op__is_signed$next[0:0]$6856 $1\logical_op__is_signed$next[0:0]$6874 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6814 $1\logical_op__output_carry$next[0:0]$6832 + assign $0\logical_op__output_carry$next[0:0]$6859 $1\logical_op__output_carry$next[0:0]$6877 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6817 $1\logical_op__write_cr0$next[0:0]$6835 - assign $0\logical_op__zero_a$next[0:0]$6818 $1\logical_op__zero_a$next[0:0]$6836 - assign $0\logical_op__imm_data__data$next[63:0]$6803 $2\logical_op__imm_data__data$next[63:0]$6837 - assign $0\logical_op__imm_data__ok$next[0:0]$6804 $2\logical_op__imm_data__ok$next[0:0]$6838 - assign $0\logical_op__oe__oe$next[0:0]$6812 $2\logical_op__oe__oe$next[0:0]$6839 - assign $0\logical_op__oe__ok$next[0:0]$6813 $2\logical_op__oe__ok$next[0:0]$6840 - assign $0\logical_op__rc__ok$next[0:0]$6815 $2\logical_op__rc__ok$next[0:0]$6841 - assign $0\logical_op__rc__rc$next[0:0]$6816 $2\logical_op__rc__rc$next[0:0]$6842 - attribute \src "libresoc.v:141964.5-141964.29" + assign $0\logical_op__write_cr0$next[0:0]$6862 $1\logical_op__write_cr0$next[0:0]$6880 + assign $0\logical_op__zero_a$next[0:0]$6863 $1\logical_op__zero_a$next[0:0]$6881 + assign $0\logical_op__imm_data__data$next[63:0]$6848 $2\logical_op__imm_data__data$next[63:0]$6882 + assign $0\logical_op__imm_data__ok$next[0:0]$6849 $2\logical_op__imm_data__ok$next[0:0]$6883 + assign $0\logical_op__oe__oe$next[0:0]$6857 $2\logical_op__oe__oe$next[0:0]$6884 + assign $0\logical_op__oe__ok$next[0:0]$6858 $2\logical_op__oe__ok$next[0:0]$6885 + assign $0\logical_op__rc__ok$next[0:0]$6860 $2\logical_op__rc__ok$next[0:0]$6886 + assign $0\logical_op__rc__rc$next[0:0]$6861 $2\logical_op__rc__rc$next[0:0]$6887 + attribute \src "libresoc.v:143768.5-143768.29" switch \initial - attribute \src "libresoc.v:141964.9-141964.17" + attribute \src "libresoc.v:143768.9-143768.17" case 1'1 case end @@ -232021,7 +234538,7 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6824 $1\logical_op__data_len$next[3:0]$6819 $1\logical_op__is_signed$next[0:0]$6829 $1\logical_op__is_32bit$next[0:0]$6828 $1\logical_op__output_carry$next[0:0]$6832 $1\logical_op__write_cr0$next[0:0]$6835 $1\logical_op__invert_out$next[0:0]$6827 $1\logical_op__input_carry$next[1:0]$6823 $1\logical_op__zero_a$next[0:0]$6836 $1\logical_op__invert_in$next[0:0]$6826 $1\logical_op__oe__ok$next[0:0]$6831 $1\logical_op__oe__oe$next[0:0]$6830 $1\logical_op__rc__ok$next[0:0]$6833 $1\logical_op__rc__rc$next[0:0]$6834 $1\logical_op__imm_data__ok$next[0:0]$6822 $1\logical_op__imm_data__data$next[63:0]$6821 $1\logical_op__fn_unit$next[12:0]$6820 $1\logical_op__insn_type$next[6:0]$6825 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6869 $1\logical_op__data_len$next[3:0]$6864 $1\logical_op__is_signed$next[0:0]$6874 $1\logical_op__is_32bit$next[0:0]$6873 $1\logical_op__output_carry$next[0:0]$6877 $1\logical_op__write_cr0$next[0:0]$6880 $1\logical_op__invert_out$next[0:0]$6872 $1\logical_op__input_carry$next[1:0]$6868 $1\logical_op__zero_a$next[0:0]$6881 $1\logical_op__invert_in$next[0:0]$6871 $1\logical_op__oe__ok$next[0:0]$6876 $1\logical_op__oe__oe$next[0:0]$6875 $1\logical_op__rc__ok$next[0:0]$6878 $1\logical_op__rc__rc$next[0:0]$6879 $1\logical_op__imm_data__ok$next[0:0]$6867 $1\logical_op__imm_data__data$next[63:0]$6866 $1\logical_op__fn_unit$next[13:0]$6865 $1\logical_op__insn_type$next[6:0]$6870 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -232042,26 +234559,26 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6824 $1\logical_op__data_len$next[3:0]$6819 $1\logical_op__is_signed$next[0:0]$6829 $1\logical_op__is_32bit$next[0:0]$6828 $1\logical_op__output_carry$next[0:0]$6832 $1\logical_op__write_cr0$next[0:0]$6835 $1\logical_op__invert_out$next[0:0]$6827 $1\logical_op__input_carry$next[1:0]$6823 $1\logical_op__zero_a$next[0:0]$6836 $1\logical_op__invert_in$next[0:0]$6826 $1\logical_op__oe__ok$next[0:0]$6831 $1\logical_op__oe__oe$next[0:0]$6830 $1\logical_op__rc__ok$next[0:0]$6833 $1\logical_op__rc__rc$next[0:0]$6834 $1\logical_op__imm_data__ok$next[0:0]$6822 $1\logical_op__imm_data__data$next[63:0]$6821 $1\logical_op__fn_unit$next[12:0]$6820 $1\logical_op__insn_type$next[6:0]$6825 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6869 $1\logical_op__data_len$next[3:0]$6864 $1\logical_op__is_signed$next[0:0]$6874 $1\logical_op__is_32bit$next[0:0]$6873 $1\logical_op__output_carry$next[0:0]$6877 $1\logical_op__write_cr0$next[0:0]$6880 $1\logical_op__invert_out$next[0:0]$6872 $1\logical_op__input_carry$next[1:0]$6868 $1\logical_op__zero_a$next[0:0]$6881 $1\logical_op__invert_in$next[0:0]$6871 $1\logical_op__oe__ok$next[0:0]$6876 $1\logical_op__oe__oe$next[0:0]$6875 $1\logical_op__rc__ok$next[0:0]$6878 $1\logical_op__rc__rc$next[0:0]$6879 $1\logical_op__imm_data__ok$next[0:0]$6867 $1\logical_op__imm_data__data$next[63:0]$6866 $1\logical_op__fn_unit$next[13:0]$6865 $1\logical_op__insn_type$next[6:0]$6870 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } case - assign $1\logical_op__data_len$next[3:0]$6819 \logical_op__data_len - assign $1\logical_op__fn_unit$next[12:0]$6820 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6821 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6822 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6823 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6824 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6825 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6826 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6827 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6828 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6829 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6830 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6831 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6832 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6833 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6834 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6835 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6836 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$6864 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$6865 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6866 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6867 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6868 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6869 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6870 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6871 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6872 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6873 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6874 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6875 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6876 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6877 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6878 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6879 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6880 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6881 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -232073,52 +234590,52 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6837 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6838 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6842 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6841 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6839 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6840 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$6882 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6883 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6887 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6886 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6884 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6885 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$6837 $1\logical_op__imm_data__data$next[63:0]$6821 - assign $2\logical_op__imm_data__ok$next[0:0]$6838 $1\logical_op__imm_data__ok$next[0:0]$6822 - assign $2\logical_op__oe__oe$next[0:0]$6839 $1\logical_op__oe__oe$next[0:0]$6830 - assign $2\logical_op__oe__ok$next[0:0]$6840 $1\logical_op__oe__ok$next[0:0]$6831 - assign $2\logical_op__rc__ok$next[0:0]$6841 $1\logical_op__rc__ok$next[0:0]$6833 - assign $2\logical_op__rc__rc$next[0:0]$6842 $1\logical_op__rc__rc$next[0:0]$6834 + assign $2\logical_op__imm_data__data$next[63:0]$6882 $1\logical_op__imm_data__data$next[63:0]$6866 + assign $2\logical_op__imm_data__ok$next[0:0]$6883 $1\logical_op__imm_data__ok$next[0:0]$6867 + assign $2\logical_op__oe__oe$next[0:0]$6884 $1\logical_op__oe__oe$next[0:0]$6875 + assign $2\logical_op__oe__ok$next[0:0]$6885 $1\logical_op__oe__ok$next[0:0]$6876 + assign $2\logical_op__rc__ok$next[0:0]$6886 $1\logical_op__rc__ok$next[0:0]$6878 + assign $2\logical_op__rc__rc$next[0:0]$6887 $1\logical_op__rc__rc$next[0:0]$6879 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6801 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$6802 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6803 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6804 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6805 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6806 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6807 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6808 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6809 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6810 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6811 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6812 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6813 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6814 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6815 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6816 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6817 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6818 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6846 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6847 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6848 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6849 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6850 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6851 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6852 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6853 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6854 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6855 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6856 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6857 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6858 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6859 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6860 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6861 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6862 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6863 end - attribute \src "libresoc.v:142005.3-142023.6" - process $proc$libresoc.v:142005$6843 + attribute \src "libresoc.v:143809.3-143827.6" + process $proc$libresoc.v:143809$6888 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$6844 $1\o$next[63:0]$6846 + assign $0\o$next[63:0]$6889 $1\o$next[63:0]$6891 assign { } { } - assign $0\o_ok$next[0:0]$6845 $2\o_ok$next[0:0]$6848 - attribute \src "libresoc.v:142006.5-142006.29" + assign $0\o_ok$next[0:0]$6890 $2\o_ok$next[0:0]$6893 + attribute \src "libresoc.v:143810.5-143810.29" switch \initial - attribute \src "libresoc.v:142006.9-142006.17" + attribute \src "libresoc.v:143810.9-143810.17" case 1'1 case end @@ -232128,41 +234645,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6847 $1\o$next[63:0]$6846 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6892 $1\o$next[63:0]$6891 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6847 $1\o$next[63:0]$6846 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6892 $1\o$next[63:0]$6891 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$6846 \o - assign $1\o_ok$next[0:0]$6847 \o_ok + assign $1\o$next[63:0]$6891 \o + assign $1\o_ok$next[0:0]$6892 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$6848 1'0 + assign $2\o_ok$next[0:0]$6893 1'0 case - assign $2\o_ok$next[0:0]$6848 $1\o_ok$next[0:0]$6847 + assign $2\o_ok$next[0:0]$6893 $1\o_ok$next[0:0]$6892 end sync always - update \o$next $0\o$next[63:0]$6844 - update \o_ok$next $0\o_ok$next[0:0]$6845 + update \o$next $0\o$next[63:0]$6889 + update \o_ok$next $0\o_ok$next[0:0]$6890 end - attribute \src "libresoc.v:142024.3-142042.6" - process $proc$libresoc.v:142024$6849 + attribute \src "libresoc.v:143828.3-143846.6" + process $proc$libresoc.v:143828$6894 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$6850 $1\cr_a$next[3:0]$6852 + assign $0\cr_a$next[3:0]$6895 $1\cr_a$next[3:0]$6897 assign { } { } - assign $0\cr_a_ok$next[0:0]$6851 $2\cr_a_ok$next[0:0]$6854 - attribute \src "libresoc.v:142025.5-142025.29" + assign $0\cr_a_ok$next[0:0]$6896 $2\cr_a_ok$next[0:0]$6899 + attribute \src "libresoc.v:143829.5-143829.29" switch \initial - attribute \src "libresoc.v:142025.9-142025.17" + attribute \src "libresoc.v:143829.9-143829.17" case 1'1 case end @@ -232172,41 +234689,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6853 $1\cr_a$next[3:0]$6852 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6898 $1\cr_a$next[3:0]$6897 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6853 $1\cr_a$next[3:0]$6852 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6898 $1\cr_a$next[3:0]$6897 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$6852 \cr_a - assign $1\cr_a_ok$next[0:0]$6853 \cr_a_ok + assign $1\cr_a$next[3:0]$6897 \cr_a + assign $1\cr_a_ok$next[0:0]$6898 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$6854 1'0 + assign $2\cr_a_ok$next[0:0]$6899 1'0 case - assign $2\cr_a_ok$next[0:0]$6854 $1\cr_a_ok$next[0:0]$6853 + assign $2\cr_a_ok$next[0:0]$6899 $1\cr_a_ok$next[0:0]$6898 end sync always - update \cr_a$next $0\cr_a$next[3:0]$6850 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6851 + update \cr_a$next $0\cr_a$next[3:0]$6895 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6896 end - attribute \src "libresoc.v:142043.3-142061.6" - process $proc$libresoc.v:142043$6855 + attribute \src "libresoc.v:143847.3-143865.6" + process $proc$libresoc.v:143847$6900 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$6856 $1\xer_so$next[0:0]$6858 + assign $0\xer_so$next[0:0]$6901 $1\xer_so$next[0:0]$6903 assign { } { } - assign $0\xer_so_ok$next[0:0]$6857 $2\xer_so_ok$next[0:0]$6860 - attribute \src "libresoc.v:142044.5-142044.29" + assign $0\xer_so_ok$next[0:0]$6902 $2\xer_so_ok$next[0:0]$6905 + attribute \src "libresoc.v:143848.5-143848.29" switch \initial - attribute \src "libresoc.v:142044.9-142044.17" + attribute \src "libresoc.v:143848.9-143848.17" case 1'1 case end @@ -232216,30 +234733,30 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6859 $1\xer_so$next[0:0]$6858 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6904 $1\xer_so$next[0:0]$6903 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6859 $1\xer_so$next[0:0]$6858 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6904 $1\xer_so$next[0:0]$6903 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$6858 \xer_so - assign $1\xer_so_ok$next[0:0]$6859 \xer_so_ok + assign $1\xer_so$next[0:0]$6903 \xer_so + assign $1\xer_so_ok$next[0:0]$6904 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$6860 1'0 + assign $2\xer_so_ok$next[0:0]$6905 1'0 case - assign $2\xer_so_ok$next[0:0]$6860 $1\xer_so_ok$next[0:0]$6859 + assign $2\xer_so_ok$next[0:0]$6905 $1\xer_so_ok$next[0:0]$6904 end sync always - update \xer_so$next $0\xer_so$next[0:0]$6856 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6857 + update \xer_so$next $0\xer_so$next[0:0]$6901 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6902 end - connect \$64 $and$libresoc.v:141779$6766_Y + connect \$64 $and$libresoc.v:143583$6811_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -232264,230 +234781,230 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:142089.1-143112.10" +attribute \src "libresoc.v:143893.1-144926.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:143079.3-143097.6" - wire width 4 $0\cr_a$22$next[3:0]$6993 - attribute \src "libresoc.v:142883.3-142884.33" - wire width 4 $0\cr_a$22[3:0]$6890 - attribute \src "libresoc.v:142101.13-142101.29" - wire width 4 $0\cr_a$22[3:0]$7000 - attribute \src "libresoc.v:143079.3-143097.6" - wire $0\cr_a_ok$23$next[0:0]$6994 - attribute \src "libresoc.v:142885.3-142886.39" - wire $0\cr_a_ok$23[0:0]$6892 - attribute \src "libresoc.v:142110.7-142110.26" - wire $0\cr_a_ok$23[0:0]$7002 - attribute \src "libresoc.v:142090.7-142090.20" + attribute \src "libresoc.v:144893.3-144911.6" + wire width 4 $0\cr_a$22$next[3:0]$7038 + attribute \src "libresoc.v:144697.3-144698.33" + wire width 4 $0\cr_a$22[3:0]$6935 + attribute \src "libresoc.v:143905.13-143905.29" + wire width 4 $0\cr_a$22[3:0]$7045 + attribute \src "libresoc.v:144893.3-144911.6" + wire $0\cr_a_ok$23$next[0:0]$7039 + attribute \src "libresoc.v:144699.3-144700.39" + wire $0\cr_a_ok$23[0:0]$6937 + attribute \src "libresoc.v:143914.7-143914.26" + wire $0\cr_a_ok$23[0:0]$7047 + attribute \src "libresoc.v:143894.7-143894.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143018.3-143059.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$6944 - attribute \src "libresoc.v:142923.3-142924.65" - wire width 4 $0\logical_op__data_len$18[3:0]$6930 - attribute \src "libresoc.v:142121.13-142121.45" - wire width 4 $0\logical_op__data_len$18[3:0]$7004 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 13 $0\logical_op__fn_unit$3$next[12:0]$6945 - attribute \src "libresoc.v:142893.3-142894.61" - wire width 13 $0\logical_op__fn_unit$3[12:0]$6900 - attribute \src "libresoc.v:142158.14-142158.48" - wire width 13 $0\logical_op__fn_unit$3[12:0]$7006 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6946 - attribute \src "libresoc.v:142895.3-142896.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6902 - attribute \src "libresoc.v:142181.14-142181.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$7008 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$6947 - attribute \src "libresoc.v:142897.3-142898.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6904 - attribute \src "libresoc.v:142190.7-142190.42" - wire $0\logical_op__imm_data__ok$5[0:0]$7010 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$6948 - attribute \src "libresoc.v:142911.3-142912.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$6918 - attribute \src "libresoc.v:142207.13-142207.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$7012 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$6949 - attribute \src "libresoc.v:142925.3-142926.57" - wire width 32 $0\logical_op__insn$19[31:0]$6932 - attribute \src "libresoc.v:142220.14-142220.43" - wire width 32 $0\logical_op__insn$19[31:0]$7014 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$6950 - attribute \src "libresoc.v:142891.3-142892.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6898 - attribute \src "libresoc.v:142377.13-142377.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$7016 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__invert_in$10$next[0:0]$6951 - attribute \src "libresoc.v:142907.3-142908.67" - wire $0\logical_op__invert_in$10[0:0]$6914 - attribute \src "libresoc.v:142460.7-142460.40" - wire $0\logical_op__invert_in$10[0:0]$7018 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__invert_out$13$next[0:0]$6952 - attribute \src "libresoc.v:142913.3-142914.69" - wire $0\logical_op__invert_out$13[0:0]$6920 - attribute \src "libresoc.v:142469.7-142469.41" - wire $0\logical_op__invert_out$13[0:0]$7020 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__is_32bit$16$next[0:0]$6953 - attribute \src "libresoc.v:142919.3-142920.65" - wire $0\logical_op__is_32bit$16[0:0]$6926 - attribute \src "libresoc.v:142478.7-142478.39" - wire $0\logical_op__is_32bit$16[0:0]$7022 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__is_signed$17$next[0:0]$6954 - attribute \src "libresoc.v:142921.3-142922.67" - wire $0\logical_op__is_signed$17[0:0]$6928 - attribute \src "libresoc.v:142487.7-142487.40" - wire $0\logical_op__is_signed$17[0:0]$7024 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__oe__oe$8$next[0:0]$6955 - attribute \src "libresoc.v:142903.3-142904.59" - wire $0\logical_op__oe__oe$8[0:0]$6910 - attribute \src "libresoc.v:142498.7-142498.36" - wire $0\logical_op__oe__oe$8[0:0]$7026 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__oe__ok$9$next[0:0]$6956 - attribute \src "libresoc.v:142905.3-142906.59" - wire $0\logical_op__oe__ok$9[0:0]$6912 - attribute \src "libresoc.v:142507.7-142507.36" - wire $0\logical_op__oe__ok$9[0:0]$7028 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__output_carry$15$next[0:0]$6957 - attribute \src "libresoc.v:142917.3-142918.73" - wire $0\logical_op__output_carry$15[0:0]$6924 - attribute \src "libresoc.v:142514.7-142514.43" - wire $0\logical_op__output_carry$15[0:0]$7030 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__rc__ok$7$next[0:0]$6958 - attribute \src "libresoc.v:142901.3-142902.59" - wire $0\logical_op__rc__ok$7[0:0]$6908 - attribute \src "libresoc.v:142525.7-142525.36" - wire $0\logical_op__rc__ok$7[0:0]$7032 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__rc__rc$6$next[0:0]$6959 - attribute \src "libresoc.v:142899.3-142900.59" - wire $0\logical_op__rc__rc$6[0:0]$6906 - attribute \src "libresoc.v:142534.7-142534.36" - wire $0\logical_op__rc__rc$6[0:0]$7034 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__write_cr0$14$next[0:0]$6960 - attribute \src "libresoc.v:142915.3-142916.67" - wire $0\logical_op__write_cr0$14[0:0]$6922 - attribute \src "libresoc.v:142541.7-142541.40" - wire $0\logical_op__write_cr0$14[0:0]$7036 - attribute \src "libresoc.v:143018.3-143059.6" - wire $0\logical_op__zero_a$11$next[0:0]$6961 - attribute \src "libresoc.v:142909.3-142910.61" - wire $0\logical_op__zero_a$11[0:0]$6916 - attribute \src "libresoc.v:142550.7-142550.37" - wire $0\logical_op__zero_a$11[0:0]$7038 - attribute \src "libresoc.v:143005.3-143017.6" - wire width 2 $0\muxid$1$next[1:0]$6941 - attribute \src "libresoc.v:142927.3-142928.33" - wire width 2 $0\muxid$1[1:0]$6934 - attribute \src "libresoc.v:142559.13-142559.29" - wire width 2 $0\muxid$1[1:0]$7040 - attribute \src "libresoc.v:143060.3-143078.6" - wire width 64 $0\o$20$next[63:0]$6987 - attribute \src "libresoc.v:142887.3-142888.27" - wire width 64 $0\o$20[63:0]$6894 - attribute \src "libresoc.v:142574.14-142574.43" - wire width 64 $0\o$20[63:0]$7042 - attribute \src "libresoc.v:143060.3-143078.6" - wire $0\o_ok$21$next[0:0]$6988 - attribute \src "libresoc.v:142889.3-142890.33" - wire $0\o_ok$21[0:0]$6896 - attribute \src "libresoc.v:142583.7-142583.23" - wire $0\o_ok$21[0:0]$7044 - attribute \src "libresoc.v:142987.3-143004.6" - wire $0\r_busy$next[0:0]$6937 - attribute \src "libresoc.v:142929.3-142930.29" + attribute \src "libresoc.v:144832.3-144873.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$6989 + attribute \src "libresoc.v:144737.3-144738.65" + wire width 4 $0\logical_op__data_len$18[3:0]$6975 + attribute \src "libresoc.v:143925.13-143925.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7049 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$6990 + attribute \src "libresoc.v:144707.3-144708.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$6945 + attribute \src "libresoc.v:143964.14-143964.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$7051 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6991 + attribute \src "libresoc.v:144709.3-144710.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6947 + attribute \src "libresoc.v:143988.14-143988.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7053 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$6992 + attribute \src "libresoc.v:144711.3-144712.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6949 + attribute \src "libresoc.v:143997.7-143997.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7055 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$6993 + attribute \src "libresoc.v:144725.3-144726.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6963 + attribute \src "libresoc.v:144014.13-144014.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7057 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$6994 + attribute \src "libresoc.v:144739.3-144740.57" + wire width 32 $0\logical_op__insn$19[31:0]$6977 + attribute \src "libresoc.v:144027.14-144027.43" + wire width 32 $0\logical_op__insn$19[31:0]$7059 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$6995 + attribute \src "libresoc.v:144705.3-144706.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6943 + attribute \src "libresoc.v:144186.13-144186.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7061 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__invert_in$10$next[0:0]$6996 + attribute \src "libresoc.v:144721.3-144722.67" + wire $0\logical_op__invert_in$10[0:0]$6959 + attribute \src "libresoc.v:144270.7-144270.40" + wire $0\logical_op__invert_in$10[0:0]$7063 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__invert_out$13$next[0:0]$6997 + attribute \src "libresoc.v:144727.3-144728.69" + wire $0\logical_op__invert_out$13[0:0]$6965 + attribute \src "libresoc.v:144279.7-144279.41" + wire $0\logical_op__invert_out$13[0:0]$7065 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__is_32bit$16$next[0:0]$6998 + attribute \src "libresoc.v:144733.3-144734.65" + wire $0\logical_op__is_32bit$16[0:0]$6971 + attribute \src "libresoc.v:144288.7-144288.39" + wire $0\logical_op__is_32bit$16[0:0]$7067 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__is_signed$17$next[0:0]$6999 + attribute \src "libresoc.v:144735.3-144736.67" + wire $0\logical_op__is_signed$17[0:0]$6973 + attribute \src "libresoc.v:144297.7-144297.40" + wire $0\logical_op__is_signed$17[0:0]$7069 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__oe__oe$8$next[0:0]$7000 + attribute \src "libresoc.v:144717.3-144718.59" + wire $0\logical_op__oe__oe$8[0:0]$6955 + attribute \src "libresoc.v:144308.7-144308.36" + wire $0\logical_op__oe__oe$8[0:0]$7071 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__oe__ok$9$next[0:0]$7001 + attribute \src "libresoc.v:144719.3-144720.59" + wire $0\logical_op__oe__ok$9[0:0]$6957 + attribute \src "libresoc.v:144317.7-144317.36" + wire $0\logical_op__oe__ok$9[0:0]$7073 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__output_carry$15$next[0:0]$7002 + attribute \src "libresoc.v:144731.3-144732.73" + wire $0\logical_op__output_carry$15[0:0]$6969 + attribute \src "libresoc.v:144324.7-144324.43" + wire $0\logical_op__output_carry$15[0:0]$7075 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__rc__ok$7$next[0:0]$7003 + attribute \src "libresoc.v:144715.3-144716.59" + wire $0\logical_op__rc__ok$7[0:0]$6953 + attribute \src "libresoc.v:144335.7-144335.36" + wire $0\logical_op__rc__ok$7[0:0]$7077 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__rc__rc$6$next[0:0]$7004 + attribute \src "libresoc.v:144713.3-144714.59" + wire $0\logical_op__rc__rc$6[0:0]$6951 + attribute \src "libresoc.v:144344.7-144344.36" + wire $0\logical_op__rc__rc$6[0:0]$7079 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__write_cr0$14$next[0:0]$7005 + attribute \src "libresoc.v:144729.3-144730.67" + wire $0\logical_op__write_cr0$14[0:0]$6967 + attribute \src "libresoc.v:144351.7-144351.40" + wire $0\logical_op__write_cr0$14[0:0]$7081 + attribute \src "libresoc.v:144832.3-144873.6" + wire $0\logical_op__zero_a$11$next[0:0]$7006 + attribute \src "libresoc.v:144723.3-144724.61" + wire $0\logical_op__zero_a$11[0:0]$6961 + attribute \src "libresoc.v:144360.7-144360.37" + wire $0\logical_op__zero_a$11[0:0]$7083 + attribute \src "libresoc.v:144819.3-144831.6" + wire width 2 $0\muxid$1$next[1:0]$6986 + attribute \src "libresoc.v:144741.3-144742.33" + wire width 2 $0\muxid$1[1:0]$6979 + attribute \src "libresoc.v:144369.13-144369.29" + wire width 2 $0\muxid$1[1:0]$7085 + attribute \src "libresoc.v:144874.3-144892.6" + wire width 64 $0\o$20$next[63:0]$7032 + attribute \src "libresoc.v:144701.3-144702.27" + wire width 64 $0\o$20[63:0]$6939 + attribute \src "libresoc.v:144384.14-144384.43" + wire width 64 $0\o$20[63:0]$7087 + attribute \src "libresoc.v:144874.3-144892.6" + wire $0\o_ok$21$next[0:0]$7033 + attribute \src "libresoc.v:144703.3-144704.33" + wire $0\o_ok$21[0:0]$6941 + attribute \src "libresoc.v:144393.7-144393.23" + wire $0\o_ok$21[0:0]$7089 + attribute \src "libresoc.v:144801.3-144818.6" + wire $0\r_busy$next[0:0]$6982 + attribute \src "libresoc.v:144743.3-144744.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:143079.3-143097.6" - wire width 4 $1\cr_a$22$next[3:0]$6995 - attribute \src "libresoc.v:143079.3-143097.6" - wire $1\cr_a_ok$23$next[0:0]$6996 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$6962 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 13 $1\logical_op__fn_unit$3$next[12:0]$6963 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6964 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$6965 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$6966 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$6967 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$6968 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__invert_in$10$next[0:0]$6969 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__invert_out$13$next[0:0]$6970 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__is_32bit$16$next[0:0]$6971 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__is_signed$17$next[0:0]$6972 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__oe__oe$8$next[0:0]$6973 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__oe__ok$9$next[0:0]$6974 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__output_carry$15$next[0:0]$6975 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__rc__ok$7$next[0:0]$6976 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__rc__rc$6$next[0:0]$6977 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__write_cr0$14$next[0:0]$6978 - attribute \src "libresoc.v:143018.3-143059.6" - wire $1\logical_op__zero_a$11$next[0:0]$6979 - attribute \src "libresoc.v:143005.3-143017.6" - wire width 2 $1\muxid$1$next[1:0]$6942 - attribute \src "libresoc.v:143060.3-143078.6" - wire width 64 $1\o$20$next[63:0]$6989 - attribute \src "libresoc.v:143060.3-143078.6" - wire $1\o_ok$21$next[0:0]$6990 - attribute \src "libresoc.v:142987.3-143004.6" - wire $1\r_busy$next[0:0]$6938 - attribute \src "libresoc.v:142873.7-142873.20" + attribute \src "libresoc.v:144893.3-144911.6" + wire width 4 $1\cr_a$22$next[3:0]$7040 + attribute \src "libresoc.v:144893.3-144911.6" + wire $1\cr_a_ok$23$next[0:0]$7041 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$7007 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7008 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7009 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$7010 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$7011 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$7012 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$7013 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__invert_in$10$next[0:0]$7014 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__invert_out$13$next[0:0]$7015 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__is_32bit$16$next[0:0]$7016 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__is_signed$17$next[0:0]$7017 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__oe__oe$8$next[0:0]$7018 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__oe__ok$9$next[0:0]$7019 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__output_carry$15$next[0:0]$7020 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7021 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7022 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7023 + attribute \src "libresoc.v:144832.3-144873.6" + wire $1\logical_op__zero_a$11$next[0:0]$7024 + attribute \src "libresoc.v:144819.3-144831.6" + wire width 2 $1\muxid$1$next[1:0]$6987 + attribute \src "libresoc.v:144874.3-144892.6" + wire width 64 $1\o$20$next[63:0]$7034 + attribute \src "libresoc.v:144874.3-144892.6" + wire $1\o_ok$21$next[0:0]$7035 + attribute \src "libresoc.v:144801.3-144818.6" + wire $1\r_busy$next[0:0]$6983 + attribute \src "libresoc.v:144687.7-144687.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:143079.3-143097.6" - wire $2\cr_a_ok$23$next[0:0]$6997 - attribute \src "libresoc.v:143018.3-143059.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6980 - attribute \src "libresoc.v:143018.3-143059.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$6981 - attribute \src "libresoc.v:143018.3-143059.6" - wire $2\logical_op__oe__oe$8$next[0:0]$6982 - attribute \src "libresoc.v:143018.3-143059.6" - wire $2\logical_op__oe__ok$9$next[0:0]$6983 - attribute \src "libresoc.v:143018.3-143059.6" - wire $2\logical_op__rc__ok$7$next[0:0]$6984 - attribute \src "libresoc.v:143018.3-143059.6" - wire $2\logical_op__rc__rc$6$next[0:0]$6985 - attribute \src "libresoc.v:143060.3-143078.6" - wire $2\o_ok$21$next[0:0]$6991 - attribute \src "libresoc.v:142987.3-143004.6" - wire $2\r_busy$next[0:0]$6939 - attribute \src "libresoc.v:142882.18-142882.118" - wire $and$libresoc.v:142882$6888_Y + attribute \src "libresoc.v:144893.3-144911.6" + wire $2\cr_a_ok$23$next[0:0]$7042 + attribute \src "libresoc.v:144832.3-144873.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7025 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7026 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7027 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7028 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7029 + attribute \src "libresoc.v:144832.3-144873.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7030 + attribute \src "libresoc.v:144874.3-144892.6" + wire $2\o_ok$21$next[0:0]$7036 + attribute \src "libresoc.v:144801.3-144818.6" + wire $2\r_busy$next[0:0]$6984 + attribute \src "libresoc.v:144696.18-144696.118" + wire $and$libresoc.v:144696$6933_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -232507,7 +235024,7 @@ module \logical_pipe2 wire \cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$73 - attribute \src "libresoc.v:142090.7-142090.15" + attribute \src "libresoc.v:143894.7-143894.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -232518,55 +235035,58 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$68 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 33 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 33 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$53 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -232685,6 +235205,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -232761,6 +235282,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 32 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -232839,6 +235361,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -232970,37 +235493,39 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len$41 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_logical_op__fn_unit$26 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -233099,6 +235624,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -233175,6 +235701,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -233254,7 +235781,7 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:142882$6888 + cell $and $and$libresoc.v:144696$6933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233262,16 +235789,16 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:142882$6888_Y + connect \Y $and$libresoc.v:144696$6933_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:142931.10-142934.4" + attribute \src "libresoc.v:144745.10-144748.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:142935.15-142982.4" + attribute \src "libresoc.v:144749.15-144796.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 @@ -233321,388 +235848,388 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:142983.10-142986.4" + attribute \src "libresoc.v:144797.10-144800.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:142090.7-142090.20" - process $proc$libresoc.v:142090$6998 + attribute \src "libresoc.v:143894.7-143894.20" + process $proc$libresoc.v:143894$7043 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142101.13-142101.29" - process $proc$libresoc.v:142101$6999 + attribute \src "libresoc.v:143905.13-143905.29" + process $proc$libresoc.v:143905$7044 assign { } { } - assign $0\cr_a$22[3:0]$7000 4'0000 + assign $0\cr_a$22[3:0]$7045 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$7000 + update \cr_a$22 $0\cr_a$22[3:0]$7045 end - attribute \src "libresoc.v:142110.7-142110.26" - process $proc$libresoc.v:142110$7001 + attribute \src "libresoc.v:143914.7-143914.26" + process $proc$libresoc.v:143914$7046 assign { } { } - assign $0\cr_a_ok$23[0:0]$7002 1'0 + assign $0\cr_a_ok$23[0:0]$7047 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7002 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7047 end - attribute \src "libresoc.v:142121.13-142121.45" - process $proc$libresoc.v:142121$7003 + attribute \src "libresoc.v:143925.13-143925.45" + process $proc$libresoc.v:143925$7048 assign { } { } - assign $0\logical_op__data_len$18[3:0]$7004 4'0000 + assign $0\logical_op__data_len$18[3:0]$7049 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7004 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7049 end - attribute \src "libresoc.v:142158.14-142158.48" - process $proc$libresoc.v:142158$7005 + attribute \src "libresoc.v:143964.14-143964.48" + process $proc$libresoc.v:143964$7050 assign { } { } - assign $0\logical_op__fn_unit$3[12:0]$7006 13'0000000000000 + assign $0\logical_op__fn_unit$3[13:0]$7051 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$7006 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7051 end - attribute \src "libresoc.v:142181.14-142181.67" - process $proc$libresoc.v:142181$7007 + attribute \src "libresoc.v:143988.14-143988.67" + process $proc$libresoc.v:143988$7052 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$7008 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$7053 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7008 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7053 end - attribute \src "libresoc.v:142190.7-142190.42" - process $proc$libresoc.v:142190$7009 + attribute \src "libresoc.v:143997.7-143997.42" + process $proc$libresoc.v:143997$7054 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$7010 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$7055 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7010 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7055 end - attribute \src "libresoc.v:142207.13-142207.48" - process $proc$libresoc.v:142207$7011 + attribute \src "libresoc.v:144014.13-144014.48" + process $proc$libresoc.v:144014$7056 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7012 2'00 + assign $0\logical_op__input_carry$12[1:0]$7057 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7012 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7057 end - attribute \src "libresoc.v:142220.14-142220.43" - process $proc$libresoc.v:142220$7013 + attribute \src "libresoc.v:144027.14-144027.43" + process $proc$libresoc.v:144027$7058 assign { } { } - assign $0\logical_op__insn$19[31:0]$7014 0 + assign $0\logical_op__insn$19[31:0]$7059 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7014 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7059 end - attribute \src "libresoc.v:142377.13-142377.46" - process $proc$libresoc.v:142377$7015 + attribute \src "libresoc.v:144186.13-144186.46" + process $proc$libresoc.v:144186$7060 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$7016 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$7061 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7016 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7061 end - attribute \src "libresoc.v:142460.7-142460.40" - process $proc$libresoc.v:142460$7017 + attribute \src "libresoc.v:144270.7-144270.40" + process $proc$libresoc.v:144270$7062 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7018 1'0 + assign $0\logical_op__invert_in$10[0:0]$7063 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7018 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7063 end - attribute \src "libresoc.v:142469.7-142469.41" - process $proc$libresoc.v:142469$7019 + attribute \src "libresoc.v:144279.7-144279.41" + process $proc$libresoc.v:144279$7064 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7020 1'0 + assign $0\logical_op__invert_out$13[0:0]$7065 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7020 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7065 end - attribute \src "libresoc.v:142478.7-142478.39" - process $proc$libresoc.v:142478$7021 + attribute \src "libresoc.v:144288.7-144288.39" + process $proc$libresoc.v:144288$7066 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7022 1'0 + assign $0\logical_op__is_32bit$16[0:0]$7067 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7022 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7067 end - attribute \src "libresoc.v:142487.7-142487.40" - process $proc$libresoc.v:142487$7023 + attribute \src "libresoc.v:144297.7-144297.40" + process $proc$libresoc.v:144297$7068 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7024 1'0 + assign $0\logical_op__is_signed$17[0:0]$7069 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7024 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7069 end - attribute \src "libresoc.v:142498.7-142498.36" - process $proc$libresoc.v:142498$7025 + attribute \src "libresoc.v:144308.7-144308.36" + process $proc$libresoc.v:144308$7070 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$7026 1'0 + assign $0\logical_op__oe__oe$8[0:0]$7071 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7026 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7071 end - attribute \src "libresoc.v:142507.7-142507.36" - process $proc$libresoc.v:142507$7027 + attribute \src "libresoc.v:144317.7-144317.36" + process $proc$libresoc.v:144317$7072 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7028 1'0 + assign $0\logical_op__oe__ok$9[0:0]$7073 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7028 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7073 end - attribute \src "libresoc.v:142514.7-142514.43" - process $proc$libresoc.v:142514$7029 + attribute \src "libresoc.v:144324.7-144324.43" + process $proc$libresoc.v:144324$7074 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7030 1'0 + assign $0\logical_op__output_carry$15[0:0]$7075 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7030 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7075 end - attribute \src "libresoc.v:142525.7-142525.36" - process $proc$libresoc.v:142525$7031 + attribute \src "libresoc.v:144335.7-144335.36" + process $proc$libresoc.v:144335$7076 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$7032 1'0 + assign $0\logical_op__rc__ok$7[0:0]$7077 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7032 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7077 end - attribute \src "libresoc.v:142534.7-142534.36" - process $proc$libresoc.v:142534$7033 + attribute \src "libresoc.v:144344.7-144344.36" + process $proc$libresoc.v:144344$7078 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$7034 1'0 + assign $0\logical_op__rc__rc$6[0:0]$7079 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7034 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7079 end - attribute \src "libresoc.v:142541.7-142541.40" - process $proc$libresoc.v:142541$7035 + attribute \src "libresoc.v:144351.7-144351.40" + process $proc$libresoc.v:144351$7080 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7036 1'0 + assign $0\logical_op__write_cr0$14[0:0]$7081 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7036 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7081 end - attribute \src "libresoc.v:142550.7-142550.37" - process $proc$libresoc.v:142550$7037 + attribute \src "libresoc.v:144360.7-144360.37" + process $proc$libresoc.v:144360$7082 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7038 1'0 + assign $0\logical_op__zero_a$11[0:0]$7083 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7038 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7083 end - attribute \src "libresoc.v:142559.13-142559.29" - process $proc$libresoc.v:142559$7039 + attribute \src "libresoc.v:144369.13-144369.29" + process $proc$libresoc.v:144369$7084 assign { } { } - assign $0\muxid$1[1:0]$7040 2'00 + assign $0\muxid$1[1:0]$7085 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7040 + update \muxid$1 $0\muxid$1[1:0]$7085 end - attribute \src "libresoc.v:142574.14-142574.43" - process $proc$libresoc.v:142574$7041 + attribute \src "libresoc.v:144384.14-144384.43" + process $proc$libresoc.v:144384$7086 assign { } { } - assign $0\o$20[63:0]$7042 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$7087 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$7042 + update \o$20 $0\o$20[63:0]$7087 end - attribute \src "libresoc.v:142583.7-142583.23" - process $proc$libresoc.v:142583$7043 + attribute \src "libresoc.v:144393.7-144393.23" + process $proc$libresoc.v:144393$7088 assign { } { } - assign $0\o_ok$21[0:0]$7044 1'0 + assign $0\o_ok$21[0:0]$7089 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$7044 + update \o_ok$21 $0\o_ok$21[0:0]$7089 end - attribute \src "libresoc.v:142873.7-142873.20" - process $proc$libresoc.v:142873$7045 + attribute \src "libresoc.v:144687.7-144687.20" + process $proc$libresoc.v:144687$7090 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:142883.3-142884.33" - process $proc$libresoc.v:142883$6889 + attribute \src "libresoc.v:144697.3-144698.33" + process $proc$libresoc.v:144697$6934 assign { } { } - assign $0\cr_a$22[3:0]$6890 \cr_a$22$next + assign $0\cr_a$22[3:0]$6935 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6890 + update \cr_a$22 $0\cr_a$22[3:0]$6935 end - attribute \src "libresoc.v:142885.3-142886.39" - process $proc$libresoc.v:142885$6891 + attribute \src "libresoc.v:144699.3-144700.39" + process $proc$libresoc.v:144699$6936 assign { } { } - assign $0\cr_a_ok$23[0:0]$6892 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$6937 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6892 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6937 end - attribute \src "libresoc.v:142887.3-142888.27" - process $proc$libresoc.v:142887$6893 + attribute \src "libresoc.v:144701.3-144702.27" + process $proc$libresoc.v:144701$6938 assign { } { } - assign $0\o$20[63:0]$6894 \o$20$next + assign $0\o$20[63:0]$6939 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6894 + update \o$20 $0\o$20[63:0]$6939 end - attribute \src "libresoc.v:142889.3-142890.33" - process $proc$libresoc.v:142889$6895 + attribute \src "libresoc.v:144703.3-144704.33" + process $proc$libresoc.v:144703$6940 assign { } { } - assign $0\o_ok$21[0:0]$6896 \o_ok$21$next + assign $0\o_ok$21[0:0]$6941 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6896 + update \o_ok$21 $0\o_ok$21[0:0]$6941 end - attribute \src "libresoc.v:142891.3-142892.65" - process $proc$libresoc.v:142891$6897 + attribute \src "libresoc.v:144705.3-144706.65" + process $proc$libresoc.v:144705$6942 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6898 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$6943 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6898 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6943 end - attribute \src "libresoc.v:142893.3-142894.61" - process $proc$libresoc.v:142893$6899 + attribute \src "libresoc.v:144707.3-144708.61" + process $proc$libresoc.v:144707$6944 assign { } { } - assign $0\logical_op__fn_unit$3[12:0]$6900 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$6945 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$6900 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6945 end - attribute \src "libresoc.v:142895.3-142896.75" - process $proc$libresoc.v:142895$6901 + attribute \src "libresoc.v:144709.3-144710.75" + process $proc$libresoc.v:144709$6946 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6902 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$6947 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6902 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6947 end - attribute \src "libresoc.v:142897.3-142898.71" - process $proc$libresoc.v:142897$6903 + attribute \src "libresoc.v:144711.3-144712.71" + process $proc$libresoc.v:144711$6948 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6904 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$6949 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6904 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6949 end - attribute \src "libresoc.v:142899.3-142900.59" - process $proc$libresoc.v:142899$6905 + attribute \src "libresoc.v:144713.3-144714.59" + process $proc$libresoc.v:144713$6950 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6906 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$6951 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6906 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6951 end - attribute \src "libresoc.v:142901.3-142902.59" - process $proc$libresoc.v:142901$6907 + attribute \src "libresoc.v:144715.3-144716.59" + process $proc$libresoc.v:144715$6952 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6908 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$6953 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6908 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6953 end - attribute \src "libresoc.v:142903.3-142904.59" - process $proc$libresoc.v:142903$6909 + attribute \src "libresoc.v:144717.3-144718.59" + process $proc$libresoc.v:144717$6954 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6910 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$6955 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6910 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6955 end - attribute \src "libresoc.v:142905.3-142906.59" - process $proc$libresoc.v:142905$6911 + attribute \src "libresoc.v:144719.3-144720.59" + process $proc$libresoc.v:144719$6956 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6912 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$6957 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6912 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6957 end - attribute \src "libresoc.v:142907.3-142908.67" - process $proc$libresoc.v:142907$6913 + attribute \src "libresoc.v:144721.3-144722.67" + process $proc$libresoc.v:144721$6958 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6914 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$6959 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6914 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6959 end - attribute \src "libresoc.v:142909.3-142910.61" - process $proc$libresoc.v:142909$6915 + attribute \src "libresoc.v:144723.3-144724.61" + process $proc$libresoc.v:144723$6960 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6916 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$6961 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6916 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6961 end - attribute \src "libresoc.v:142911.3-142912.71" - process $proc$libresoc.v:142911$6917 + attribute \src "libresoc.v:144725.3-144726.71" + process $proc$libresoc.v:144725$6962 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6918 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$6963 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6918 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6963 end - attribute \src "libresoc.v:142913.3-142914.69" - process $proc$libresoc.v:142913$6919 + attribute \src "libresoc.v:144727.3-144728.69" + process $proc$libresoc.v:144727$6964 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6920 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$6965 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6920 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6965 end - attribute \src "libresoc.v:142915.3-142916.67" - process $proc$libresoc.v:142915$6921 + attribute \src "libresoc.v:144729.3-144730.67" + process $proc$libresoc.v:144729$6966 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6922 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$6967 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6922 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6967 end - attribute \src "libresoc.v:142917.3-142918.73" - process $proc$libresoc.v:142917$6923 + attribute \src "libresoc.v:144731.3-144732.73" + process $proc$libresoc.v:144731$6968 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6924 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$6969 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6924 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6969 end - attribute \src "libresoc.v:142919.3-142920.65" - process $proc$libresoc.v:142919$6925 + attribute \src "libresoc.v:144733.3-144734.65" + process $proc$libresoc.v:144733$6970 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6926 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$6971 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6926 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6971 end - attribute \src "libresoc.v:142921.3-142922.67" - process $proc$libresoc.v:142921$6927 + attribute \src "libresoc.v:144735.3-144736.67" + process $proc$libresoc.v:144735$6972 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6928 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$6973 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6928 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6973 end - attribute \src "libresoc.v:142923.3-142924.65" - process $proc$libresoc.v:142923$6929 + attribute \src "libresoc.v:144737.3-144738.65" + process $proc$libresoc.v:144737$6974 assign { } { } - assign $0\logical_op__data_len$18[3:0]$6930 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$6975 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6930 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6975 end - attribute \src "libresoc.v:142925.3-142926.57" - process $proc$libresoc.v:142925$6931 + attribute \src "libresoc.v:144739.3-144740.57" + process $proc$libresoc.v:144739$6976 assign { } { } - assign $0\logical_op__insn$19[31:0]$6932 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$6977 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6932 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6977 end - attribute \src "libresoc.v:142927.3-142928.33" - process $proc$libresoc.v:142927$6933 + attribute \src "libresoc.v:144741.3-144742.33" + process $proc$libresoc.v:144741$6978 assign { } { } - assign $0\muxid$1[1:0]$6934 \muxid$1$next + assign $0\muxid$1[1:0]$6979 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$6934 + update \muxid$1 $0\muxid$1[1:0]$6979 end - attribute \src "libresoc.v:142929.3-142930.29" - process $proc$libresoc.v:142929$6935 + attribute \src "libresoc.v:144743.3-144744.29" + process $proc$libresoc.v:144743$6980 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:142987.3-143004.6" - process $proc$libresoc.v:142987$6936 + attribute \src "libresoc.v:144801.3-144818.6" + process $proc$libresoc.v:144801$6981 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6937 $2\r_busy$next[0:0]$6939 - attribute \src "libresoc.v:142988.5-142988.29" + assign $0\r_busy$next[0:0]$6982 $2\r_busy$next[0:0]$6984 + attribute \src "libresoc.v:144802.5-144802.29" switch \initial - attribute \src "libresoc.v:142988.9-142988.17" + attribute \src "libresoc.v:144802.9-144802.17" case 1'1 case end @@ -233711,34 +236238,34 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6938 1'1 + assign $1\r_busy$next[0:0]$6983 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6938 1'0 + assign $1\r_busy$next[0:0]$6983 1'0 case - assign $1\r_busy$next[0:0]$6938 \r_busy + assign $1\r_busy$next[0:0]$6983 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6939 1'0 + assign $2\r_busy$next[0:0]$6984 1'0 case - assign $2\r_busy$next[0:0]$6939 $1\r_busy$next[0:0]$6938 + assign $2\r_busy$next[0:0]$6984 $1\r_busy$next[0:0]$6983 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6937 + update \r_busy$next $0\r_busy$next[0:0]$6982 end - attribute \src "libresoc.v:143005.3-143017.6" - process $proc$libresoc.v:143005$6940 + attribute \src "libresoc.v:144819.3-144831.6" + process $proc$libresoc.v:144819$6985 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$6941 $1\muxid$1$next[1:0]$6942 - attribute \src "libresoc.v:143006.5-143006.29" + assign $0\muxid$1$next[1:0]$6986 $1\muxid$1$next[1:0]$6987 + attribute \src "libresoc.v:144820.5-144820.29" switch \initial - attribute \src "libresoc.v:143006.9-143006.17" + attribute \src "libresoc.v:144820.9-144820.17" case 1'1 case end @@ -233747,19 +236274,19 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$6942 \muxid$51 + assign $1\muxid$1$next[1:0]$6987 \muxid$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$6942 \muxid$51 + assign $1\muxid$1$next[1:0]$6987 \muxid$51 case - assign $1\muxid$1$next[1:0]$6942 \muxid$1 + assign $1\muxid$1$next[1:0]$6987 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$6941 + update \muxid$1$next $0\muxid$1$next[1:0]$6986 end - attribute \src "libresoc.v:143018.3-143059.6" - process $proc$libresoc.v:143018$6943 + attribute \src "libresoc.v:144832.3-144873.6" + process $proc$libresoc.v:144832$6988 assign { } { } assign { } { } assign { } { } @@ -233796,33 +236323,33 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$6944 $1\logical_op__data_len$18$next[3:0]$6962 - assign $0\logical_op__fn_unit$3$next[12:0]$6945 $1\logical_op__fn_unit$3$next[12:0]$6963 + assign $0\logical_op__data_len$18$next[3:0]$6989 $1\logical_op__data_len$18$next[3:0]$7007 + assign $0\logical_op__fn_unit$3$next[13:0]$6990 $1\logical_op__fn_unit$3$next[13:0]$7008 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$6948 $1\logical_op__input_carry$12$next[1:0]$6966 - assign $0\logical_op__insn$19$next[31:0]$6949 $1\logical_op__insn$19$next[31:0]$6967 - assign $0\logical_op__insn_type$2$next[6:0]$6950 $1\logical_op__insn_type$2$next[6:0]$6968 - assign $0\logical_op__invert_in$10$next[0:0]$6951 $1\logical_op__invert_in$10$next[0:0]$6969 - assign $0\logical_op__invert_out$13$next[0:0]$6952 $1\logical_op__invert_out$13$next[0:0]$6970 - assign $0\logical_op__is_32bit$16$next[0:0]$6953 $1\logical_op__is_32bit$16$next[0:0]$6971 - assign $0\logical_op__is_signed$17$next[0:0]$6954 $1\logical_op__is_signed$17$next[0:0]$6972 + assign $0\logical_op__input_carry$12$next[1:0]$6993 $1\logical_op__input_carry$12$next[1:0]$7011 + assign $0\logical_op__insn$19$next[31:0]$6994 $1\logical_op__insn$19$next[31:0]$7012 + assign $0\logical_op__insn_type$2$next[6:0]$6995 $1\logical_op__insn_type$2$next[6:0]$7013 + assign $0\logical_op__invert_in$10$next[0:0]$6996 $1\logical_op__invert_in$10$next[0:0]$7014 + assign $0\logical_op__invert_out$13$next[0:0]$6997 $1\logical_op__invert_out$13$next[0:0]$7015 + assign $0\logical_op__is_32bit$16$next[0:0]$6998 $1\logical_op__is_32bit$16$next[0:0]$7016 + assign $0\logical_op__is_signed$17$next[0:0]$6999 $1\logical_op__is_signed$17$next[0:0]$7017 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$6957 $1\logical_op__output_carry$15$next[0:0]$6975 + assign $0\logical_op__output_carry$15$next[0:0]$7002 $1\logical_op__output_carry$15$next[0:0]$7020 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$6960 $1\logical_op__write_cr0$14$next[0:0]$6978 - assign $0\logical_op__zero_a$11$next[0:0]$6961 $1\logical_op__zero_a$11$next[0:0]$6979 - assign $0\logical_op__imm_data__data$4$next[63:0]$6946 $2\logical_op__imm_data__data$4$next[63:0]$6980 - assign $0\logical_op__imm_data__ok$5$next[0:0]$6947 $2\logical_op__imm_data__ok$5$next[0:0]$6981 - assign $0\logical_op__oe__oe$8$next[0:0]$6955 $2\logical_op__oe__oe$8$next[0:0]$6982 - assign $0\logical_op__oe__ok$9$next[0:0]$6956 $2\logical_op__oe__ok$9$next[0:0]$6983 - assign $0\logical_op__rc__ok$7$next[0:0]$6958 $2\logical_op__rc__ok$7$next[0:0]$6984 - assign $0\logical_op__rc__rc$6$next[0:0]$6959 $2\logical_op__rc__rc$6$next[0:0]$6985 - attribute \src "libresoc.v:143019.5-143019.29" + assign $0\logical_op__write_cr0$14$next[0:0]$7005 $1\logical_op__write_cr0$14$next[0:0]$7023 + assign $0\logical_op__zero_a$11$next[0:0]$7006 $1\logical_op__zero_a$11$next[0:0]$7024 + assign $0\logical_op__imm_data__data$4$next[63:0]$6991 $2\logical_op__imm_data__data$4$next[63:0]$7025 + assign $0\logical_op__imm_data__ok$5$next[0:0]$6992 $2\logical_op__imm_data__ok$5$next[0:0]$7026 + assign $0\logical_op__oe__oe$8$next[0:0]$7000 $2\logical_op__oe__oe$8$next[0:0]$7027 + assign $0\logical_op__oe__ok$9$next[0:0]$7001 $2\logical_op__oe__ok$9$next[0:0]$7028 + assign $0\logical_op__rc__ok$7$next[0:0]$7003 $2\logical_op__rc__ok$7$next[0:0]$7029 + assign $0\logical_op__rc__rc$6$next[0:0]$7004 $2\logical_op__rc__rc$6$next[0:0]$7030 + attribute \src "libresoc.v:144833.5-144833.29" switch \initial - attribute \src "libresoc.v:143019.9-143019.17" + attribute \src "libresoc.v:144833.9-144833.17" case 1'1 case end @@ -233848,7 +236375,7 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6967 $1\logical_op__data_len$18$next[3:0]$6962 $1\logical_op__is_signed$17$next[0:0]$6972 $1\logical_op__is_32bit$16$next[0:0]$6971 $1\logical_op__output_carry$15$next[0:0]$6975 $1\logical_op__write_cr0$14$next[0:0]$6978 $1\logical_op__invert_out$13$next[0:0]$6970 $1\logical_op__input_carry$12$next[1:0]$6966 $1\logical_op__zero_a$11$next[0:0]$6979 $1\logical_op__invert_in$10$next[0:0]$6969 $1\logical_op__oe__ok$9$next[0:0]$6974 $1\logical_op__oe__oe$8$next[0:0]$6973 $1\logical_op__rc__ok$7$next[0:0]$6976 $1\logical_op__rc__rc$6$next[0:0]$6977 $1\logical_op__imm_data__ok$5$next[0:0]$6965 $1\logical_op__imm_data__data$4$next[63:0]$6964 $1\logical_op__fn_unit$3$next[12:0]$6963 $1\logical_op__insn_type$2$next[6:0]$6968 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7012 $1\logical_op__data_len$18$next[3:0]$7007 $1\logical_op__is_signed$17$next[0:0]$7017 $1\logical_op__is_32bit$16$next[0:0]$7016 $1\logical_op__output_carry$15$next[0:0]$7020 $1\logical_op__write_cr0$14$next[0:0]$7023 $1\logical_op__invert_out$13$next[0:0]$7015 $1\logical_op__input_carry$12$next[1:0]$7011 $1\logical_op__zero_a$11$next[0:0]$7024 $1\logical_op__invert_in$10$next[0:0]$7014 $1\logical_op__oe__ok$9$next[0:0]$7019 $1\logical_op__oe__oe$8$next[0:0]$7018 $1\logical_op__rc__ok$7$next[0:0]$7021 $1\logical_op__rc__rc$6$next[0:0]$7022 $1\logical_op__imm_data__ok$5$next[0:0]$7010 $1\logical_op__imm_data__data$4$next[63:0]$7009 $1\logical_op__fn_unit$3$next[13:0]$7008 $1\logical_op__insn_type$2$next[6:0]$7013 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -233869,26 +236396,26 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6967 $1\logical_op__data_len$18$next[3:0]$6962 $1\logical_op__is_signed$17$next[0:0]$6972 $1\logical_op__is_32bit$16$next[0:0]$6971 $1\logical_op__output_carry$15$next[0:0]$6975 $1\logical_op__write_cr0$14$next[0:0]$6978 $1\logical_op__invert_out$13$next[0:0]$6970 $1\logical_op__input_carry$12$next[1:0]$6966 $1\logical_op__zero_a$11$next[0:0]$6979 $1\logical_op__invert_in$10$next[0:0]$6969 $1\logical_op__oe__ok$9$next[0:0]$6974 $1\logical_op__oe__oe$8$next[0:0]$6973 $1\logical_op__rc__ok$7$next[0:0]$6976 $1\logical_op__rc__rc$6$next[0:0]$6977 $1\logical_op__imm_data__ok$5$next[0:0]$6965 $1\logical_op__imm_data__data$4$next[63:0]$6964 $1\logical_op__fn_unit$3$next[12:0]$6963 $1\logical_op__insn_type$2$next[6:0]$6968 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7012 $1\logical_op__data_len$18$next[3:0]$7007 $1\logical_op__is_signed$17$next[0:0]$7017 $1\logical_op__is_32bit$16$next[0:0]$7016 $1\logical_op__output_carry$15$next[0:0]$7020 $1\logical_op__write_cr0$14$next[0:0]$7023 $1\logical_op__invert_out$13$next[0:0]$7015 $1\logical_op__input_carry$12$next[1:0]$7011 $1\logical_op__zero_a$11$next[0:0]$7024 $1\logical_op__invert_in$10$next[0:0]$7014 $1\logical_op__oe__ok$9$next[0:0]$7019 $1\logical_op__oe__oe$8$next[0:0]$7018 $1\logical_op__rc__ok$7$next[0:0]$7021 $1\logical_op__rc__rc$6$next[0:0]$7022 $1\logical_op__imm_data__ok$5$next[0:0]$7010 $1\logical_op__imm_data__data$4$next[63:0]$7009 $1\logical_op__fn_unit$3$next[13:0]$7008 $1\logical_op__insn_type$2$next[6:0]$7013 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case - assign $1\logical_op__data_len$18$next[3:0]$6962 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[12:0]$6963 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$6964 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$6965 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$6966 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$6967 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$6968 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$6969 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$6970 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$6971 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$6972 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$6973 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$6974 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$6975 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$6976 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$6977 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$6978 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$6979 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$7007 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$7008 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$7009 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$7010 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$7011 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$7012 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$7013 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$7014 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$7015 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$7016 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$7017 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$7018 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$7019 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7020 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7021 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7022 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7023 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7024 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -233900,52 +236427,52 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$6980 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6981 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$6985 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$6984 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$6982 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$6983 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$7025 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7026 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7030 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7029 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7027 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7028 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$6980 $1\logical_op__imm_data__data$4$next[63:0]$6964 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6981 $1\logical_op__imm_data__ok$5$next[0:0]$6965 - assign $2\logical_op__oe__oe$8$next[0:0]$6982 $1\logical_op__oe__oe$8$next[0:0]$6973 - assign $2\logical_op__oe__ok$9$next[0:0]$6983 $1\logical_op__oe__ok$9$next[0:0]$6974 - assign $2\logical_op__rc__ok$7$next[0:0]$6984 $1\logical_op__rc__ok$7$next[0:0]$6976 - assign $2\logical_op__rc__rc$6$next[0:0]$6985 $1\logical_op__rc__rc$6$next[0:0]$6977 + assign $2\logical_op__imm_data__data$4$next[63:0]$7025 $1\logical_op__imm_data__data$4$next[63:0]$7009 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7026 $1\logical_op__imm_data__ok$5$next[0:0]$7010 + assign $2\logical_op__oe__oe$8$next[0:0]$7027 $1\logical_op__oe__oe$8$next[0:0]$7018 + assign $2\logical_op__oe__ok$9$next[0:0]$7028 $1\logical_op__oe__ok$9$next[0:0]$7019 + assign $2\logical_op__rc__ok$7$next[0:0]$7029 $1\logical_op__rc__ok$7$next[0:0]$7021 + assign $2\logical_op__rc__rc$6$next[0:0]$7030 $1\logical_op__rc__rc$6$next[0:0]$7022 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6944 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$6945 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6946 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6947 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6948 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6949 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6950 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6951 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6952 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6953 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6954 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6955 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6956 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6957 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6958 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6959 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6960 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6961 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6989 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$6990 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6991 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6992 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6993 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6994 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6995 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6996 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6997 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6998 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6999 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7000 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7001 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7002 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7003 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7004 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7005 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7006 end - attribute \src "libresoc.v:143060.3-143078.6" - process $proc$libresoc.v:143060$6986 + attribute \src "libresoc.v:144874.3-144892.6" + process $proc$libresoc.v:144874$7031 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$6987 $1\o$20$next[63:0]$6989 + assign $0\o$20$next[63:0]$7032 $1\o$20$next[63:0]$7034 assign { } { } - assign $0\o_ok$21$next[0:0]$6988 $2\o_ok$21$next[0:0]$6991 - attribute \src "libresoc.v:143061.5-143061.29" + assign $0\o_ok$21$next[0:0]$7033 $2\o_ok$21$next[0:0]$7036 + attribute \src "libresoc.v:144875.5-144875.29" switch \initial - attribute \src "libresoc.v:143061.9-143061.17" + attribute \src "libresoc.v:144875.9-144875.17" case 1'1 case end @@ -233955,41 +236482,41 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$6990 $1\o$20$next[63:0]$6989 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7035 $1\o$20$next[63:0]$7034 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$6990 $1\o$20$next[63:0]$6989 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7035 $1\o$20$next[63:0]$7034 } { \o_ok$71 \o$70 } case - assign $1\o$20$next[63:0]$6989 \o$20 - assign $1\o_ok$21$next[0:0]$6990 \o_ok$21 + assign $1\o$20$next[63:0]$7034 \o$20 + assign $1\o_ok$21$next[0:0]$7035 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$6991 1'0 + assign $2\o_ok$21$next[0:0]$7036 1'0 case - assign $2\o_ok$21$next[0:0]$6991 $1\o_ok$21$next[0:0]$6990 + assign $2\o_ok$21$next[0:0]$7036 $1\o_ok$21$next[0:0]$7035 end sync always - update \o$20$next $0\o$20$next[63:0]$6987 - update \o_ok$21$next $0\o_ok$21$next[0:0]$6988 + update \o$20$next $0\o$20$next[63:0]$7032 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7033 end - attribute \src "libresoc.v:143079.3-143097.6" - process $proc$libresoc.v:143079$6992 + attribute \src "libresoc.v:144893.3-144911.6" + process $proc$libresoc.v:144893$7037 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$6993 $1\cr_a$22$next[3:0]$6995 + assign $0\cr_a$22$next[3:0]$7038 $1\cr_a$22$next[3:0]$7040 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$6994 $2\cr_a_ok$23$next[0:0]$6997 - attribute \src "libresoc.v:143080.5-143080.29" + assign $0\cr_a_ok$23$next[0:0]$7039 $2\cr_a_ok$23$next[0:0]$7042 + attribute \src "libresoc.v:144894.5-144894.29" switch \initial - attribute \src "libresoc.v:143080.9-143080.17" + attribute \src "libresoc.v:144894.9-144894.17" case 1'1 case end @@ -233999,30 +236526,30 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6996 $1\cr_a$22$next[3:0]$6995 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7041 $1\cr_a$22$next[3:0]$7040 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6996 $1\cr_a$22$next[3:0]$6995 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7041 $1\cr_a$22$next[3:0]$7040 } { \cr_a_ok$73 \cr_a$72 } case - assign $1\cr_a$22$next[3:0]$6995 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$6996 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$7040 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7041 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$6997 1'0 + assign $2\cr_a_ok$23$next[0:0]$7042 1'0 case - assign $2\cr_a_ok$23$next[0:0]$6997 $1\cr_a_ok$23$next[0:0]$6996 + assign $2\cr_a_ok$23$next[0:0]$7042 $1\cr_a_ok$23$next[0:0]$7041 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$6993 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6994 + update \cr_a$22$next $0\cr_a$22$next[3:0]$7038 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7039 end - connect \$49 $and$libresoc.v:142882$6888_Y + connect \$49 $and$libresoc.v:144696$6933_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -234038,789 +236565,785 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-11018.10" +attribute \src "ls180.v:4.1-11017.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 - attribute \src "ls180.v:10490.1-10494.4" - wire width 3 $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 - attribute \src "ls180.v:10490.1-10494.4" - wire width 25 $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 - attribute \src "ls180.v:10490.1-10494.4" - wire width 25 $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 - attribute \src "ls180.v:10504.1-10508.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 - attribute \src "ls180.v:10504.1-10508.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 - attribute \src "ls180.v:10504.1-10508.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 - attribute \src "ls180.v:10518.1-10522.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 - attribute \src "ls180.v:10518.1-10522.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 - attribute \src "ls180.v:10518.1-10522.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 - attribute \src "ls180.v:10532.1-10536.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 - attribute \src "ls180.v:10532.1-10536.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 - attribute \src "ls180.v:10532.1-10536.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 - attribute \src "ls180.v:10547.1-10551.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 - attribute \src "ls180.v:10547.1-10551.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 - attribute \src "ls180.v:10547.1-10551.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 - attribute \src "ls180.v:10564.1-10568.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 - attribute \src "ls180.v:10564.1-10568.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 - attribute \src "ls180.v:10564.1-10568.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 - attribute \src "ls180.v:10580.1-10584.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 - attribute \src "ls180.v:10580.1-10584.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 - attribute \src "ls180.v:10580.1-10584.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 - attribute \src "ls180.v:10594.1-10598.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 - attribute \src "ls180.v:10594.1-10598.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 - attribute \src "ls180.v:10594.1-10598.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 + attribute \src "ls180.v:10353.1-10371.4" + wire width 6 $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 + attribute \src "ls180.v:10353.1-10371.4" + wire width 64 $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 + attribute \src "ls180.v:10381.1-10399.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 + attribute \src "ls180.v:10381.1-10399.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 + attribute \src "ls180.v:10409.1-10427.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 + attribute \src "ls180.v:10409.1-10427.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 + attribute \src "ls180.v:10437.1-10455.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 + attribute \src "ls180.v:10437.1-10455.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 + attribute \src "ls180.v:10465.1-10483.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 + attribute \src "ls180.v:10465.1-10483.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 + attribute \src "ls180.v:10493.1-10497.4" + wire width 3 $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 + attribute \src "ls180.v:10493.1-10497.4" + wire width 25 $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 + attribute \src "ls180.v:10493.1-10497.4" + wire width 25 $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 + attribute \src "ls180.v:10507.1-10511.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 + attribute \src "ls180.v:10507.1-10511.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 + attribute \src "ls180.v:10507.1-10511.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 + attribute \src "ls180.v:10521.1-10525.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 + attribute \src "ls180.v:10521.1-10525.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 + attribute \src "ls180.v:10521.1-10525.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 + attribute \src "ls180.v:10535.1-10539.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 + attribute \src "ls180.v:10535.1-10539.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 + attribute \src "ls180.v:10535.1-10539.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 + attribute \src "ls180.v:10550.1-10554.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 + attribute \src "ls180.v:10550.1-10554.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 + attribute \src "ls180.v:10550.1-10554.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 + attribute \src "ls180.v:10567.1-10571.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 + attribute \src "ls180.v:10567.1-10571.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 + attribute \src "ls180.v:10567.1-10571.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 + attribute \src "ls180.v:10583.1-10587.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 + attribute \src "ls180.v:10583.1-10587.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 + attribute \src "ls180.v:10583.1-10587.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 + attribute \src "ls180.v:10597.1-10601.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 + attribute \src "ls180.v:10597.1-10601.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 + attribute \src "ls180.v:10597.1-10601.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 + attribute \src "ls180.v:3402.1-3495.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6788.1-6804.4" + attribute \src "ls180.v:6791.1-6807.4" wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:7009.1-7025.4" + attribute \src "ls180.v:7012.1-7028.4" wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:7026.1-7042.4" + attribute \src "ls180.v:7029.1-7045.4" wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:7094.1-7101.4" + attribute \src "ls180.v:7097.1-7104.4" wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:7102.1-7109.4" + attribute \src "ls180.v:7105.1-7112.4" wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:7110.1-7117.4" + attribute \src "ls180.v:7113.1-7120.4" wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:7118.1-7125.4" + attribute \src "ls180.v:7121.1-7128.4" wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:7126.1-7133.4" + attribute \src "ls180.v:7129.1-7136.4" wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:7134.1-7141.4" + attribute \src "ls180.v:7137.1-7144.4" wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:7142.1-7149.4" + attribute \src "ls180.v:7145.1-7152.4" wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:7150.1-7157.4" + attribute \src "ls180.v:7153.1-7160.4" wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6805.1-6821.4" + attribute \src "ls180.v:6808.1-6824.4" wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7158.1-7165.4" + attribute \src "ls180.v:7161.1-7168.4" wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:7166.1-7173.4" + attribute \src "ls180.v:7169.1-7176.4" wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:7174.1-7181.4" + attribute \src "ls180.v:7177.1-7184.4" wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:7182.1-7189.4" + attribute \src "ls180.v:7185.1-7192.4" wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:7190.1-7209.4" + attribute \src "ls180.v:7193.1-7212.4" wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:7210.1-7229.4" + attribute \src "ls180.v:7213.1-7232.4" wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:7230.1-7249.4" + attribute \src "ls180.v:7233.1-7252.4" wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:7250.1-7269.4" + attribute \src "ls180.v:7253.1-7272.4" wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:7270.1-7289.4" + attribute \src "ls180.v:7273.1-7292.4" wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7290.1-7309.4" + attribute \src "ls180.v:7293.1-7312.4" wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6822.1-6838.4" + attribute \src "ls180.v:6825.1-6841.4" wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7310.1-7329.4" + attribute \src "ls180.v:7313.1-7332.4" wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7330.1-7349.4" + attribute \src "ls180.v:7333.1-7352.4" wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6839.1-6855.4" + attribute \src "ls180.v:6842.1-6858.4" wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6856.1-6872.4" + attribute \src "ls180.v:6859.1-6875.4" wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6873.1-6889.4" + attribute \src "ls180.v:6876.1-6892.4" wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6941.1-6957.4" + attribute \src "ls180.v:6944.1-6960.4" wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6958.1-6974.4" + attribute \src "ls180.v:6961.1-6977.4" wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6975.1-6991.4" + attribute \src "ls180.v:6978.1-6994.4" wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6992.1-7008.4" + attribute \src "ls180.v:6995.1-7011.4" wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6890.1-6906.4" + attribute \src "ls180.v:6893.1-6909.4" wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6907.1-6923.4" + attribute \src "ls180.v:6910.1-6926.4" wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6924.1-6940.4" + attribute \src "ls180.v:6927.1-6943.4" wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:7043.1-7059.4" + attribute \src "ls180.v:7046.1-7062.4" wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:7060.1-7076.4" + attribute \src "ls180.v:7063.1-7079.4" wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:7077.1-7093.4" + attribute \src "ls180.v:7080.1-7096.4" wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:6028.1-6039.4" + attribute \src "ls180.v:6031.1-6042.4" wire $0\builder_error[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1990.5-1990.55" + attribute \src "ls180.v:1993.5-1993.55" wire $0\builder_libresocsim_converted_interface_ack[0:0] - attribute \src "ls180.v:1986.12-1986.65" + attribute \src "ls180.v:1989.12-1989.65" wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] - attribute \src "ls180.v:1994.5-1994.55" + attribute \src "ls180.v:1997.5-1997.55" wire $0\builder_libresocsim_converted_interface_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1976.12-1976.52" + attribute \src "ls180.v:1979.12-1979.52" wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] - attribute \src "ls180.v:1980.5-1980.44" + attribute \src "ls180.v:1983.5-1983.44" wire $0\builder_libresocsim_wishbone_cyc[0:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1977.12-1977.54" + attribute \src "ls180.v:1980.12-1980.54" wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] - attribute \src "ls180.v:1979.11-1979.50" + attribute \src "ls180.v:1982.11-1982.50" wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] - attribute \src "ls180.v:1981.5-1981.44" + attribute \src "ls180.v:1984.5-1984.44" wire $0\builder_libresocsim_wishbone_stb[0:0] - attribute \src "ls180.v:1983.5-1983.43" + attribute \src "ls180.v:1986.5-1986.43" wire $0\builder_libresocsim_wishbone_we[0:0] - attribute \src "ls180.v:1875.5-1875.27" + attribute \src "ls180.v:1878.5-1878.27" wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1876.5-1876.27" + attribute \src "ls180.v:1879.5-1879.27" wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1877.5-1877.27" + attribute \src "ls180.v:1880.5-1880.27" wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1878.5-1878.27" + attribute \src "ls180.v:1881.5-1881.27" wire $0\builder_locked3[0:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5845.1-5881.4" + attribute \src "ls180.v:5848.1-5884.4" wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3305.1-3335.4" + attribute \src "ls180.v:3308.1-3338.4" wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5643.1-5682.4" + attribute \src "ls180.v:5646.1-5685.4" wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5740.1-5776.4" + attribute \src "ls180.v:5743.1-5779.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4620.1-4696.4" + attribute \src "ls180.v:4623.1-4699.4" wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4857.1-4884.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4586.1-4619.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:6028.1-6039.4" + attribute \src "ls180.v:6031.1-6042.4" wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:6028.1-6039.4" + attribute \src "ls180.v:6031.1-6042.4" wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5906.1-5921.4" + attribute \src "ls180.v:5909.1-5924.4" wire width 13 $0\builder_slave_sel[12:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\builder_slave_sel_r[12:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7469.1-7497.4" + attribute \src "ls180.v:7472.1-7500.4" wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7498.1-7526.4" + attribute \src "ls180.v:7501.1-7529.4" wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7350.1-7366.4" + attribute \src "ls180.v:7353.1-7369.4" wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7367.1-7383.4" + attribute \src "ls180.v:7370.1-7386.4" wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7384.1-7400.4" + attribute \src "ls180.v:7387.1-7403.4" wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7401.1-7417.4" + attribute \src "ls180.v:7404.1-7420.4" wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7418.1-7434.4" + attribute \src "ls180.v:7421.1-7437.4" wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7435.1-7451.4" + attribute \src "ls180.v:7438.1-7454.4" wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7452.1-7468.4" + attribute \src "ls180.v:7455.1-7471.4" wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:198.11-198.24" - wire width 3 $0\eint_1[2:0] - attribute \src "ls180.v:4396.1-4400.4" + attribute \src "ls180.v:4399.1-4403.4" wire width 16 $0\gpio_o[15:0] - attribute \src "ls180.v:4401.1-4405.4" + attribute \src "ls180.v:4404.1-4408.4" wire width 16 $0\gpio_oe[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_converter0_counter[0:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_converter0_dat_r[63:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\main_converter0_skip[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_converter1_counter[0:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_converter1_dat_r[63:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\main_converter1_skip[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 24 $0\main_dummy[23:0] - attribute \src "ls180.v:1082.12-1082.53" + attribute \src "ls180.v:1085.12-1085.53" wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] - attribute \src "ls180.v:1084.12-1084.54" + attribute \src "ls180.v:1087.12-1087.54" wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] - attribute \src "ls180.v:7584.1-7594.4" + attribute \src "ls180.v:7587.1-7597.4" wire width 16 $0\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:7595.1-7605.4" + attribute \src "ls180.v:7598.1-7608.4" wire width 16 $0\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7626.1-7628.4" + attribute \src "ls180.v:7629.1-7631.4" wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1663.11-1663.41" + attribute \src "ls180.v:1666.11-1666.41" wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1662.11-1662.41" + attribute \src "ls180.v:1665.11-1665.41" wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:316.5-316.51" + attribute \src "ls180.v:319.5-319.51" wire $0\main_interface0_converted_interface_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:256.5-256.39" + attribute \src "ls180.v:259.5-259.39" wire $0\main_interface0_ram_bus_err[0:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1754.11-1754.41" + attribute \src "ls180.v:1757.11-1757.41" wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1753.11-1753.41" + attribute \src "ls180.v:1756.11-1756.41" wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1746.12-1746.45" + attribute \src "ls180.v:1749.12-1749.45" wire width 64 $0\main_interface1_bus_dat_w[63:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire width 8 $0\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:331.5-331.51" + attribute \src "ls180.v:334.5-334.51" wire $0\main_interface1_converted_interface_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:271.5-271.39" + attribute \src "ls180.v:274.5-274.39" wire $0\main_interface1_ram_bus_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:286.5-286.39" + attribute \src "ls180.v:289.5-289.39" wire $0\main_interface2_ram_bus_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_interface3_ram_bus_ack[0:0] - attribute \src "ls180.v:301.5-301.39" + attribute \src "ls180.v:304.5-304.39" wire $0\main_interface3_ram_bus_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:179.12-179.74" + attribute \src "ls180.v:182.12-182.74" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:172.5-172.69" + attribute \src "ls180.v:179.5-179.69" wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:176.5-176.72" + attribute \src "ls180.v:172.5-172.72" wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:183.12-183.78" + attribute \src "ls180.v:175.11-175.79" + wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + attribute \src "ls180.v:195.12-195.78" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - attribute \src "ls180.v:197.5-197.74" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] - attribute \src "ls180.v:202.5-202.74" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] attribute \src "ls180.v:75.11-75.52" wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] attribute \src "ls180.v:74.11-74.52" @@ -234829,1943 +237352,1943 @@ module \ls180 wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] attribute \src "ls180.v:85.11-85.52" wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] - attribute \src "ls180.v:2884.1-2889.4" + attribute \src "ls180.v:2887.1-2892.4" wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] attribute \src "ls180.v:115.11-115.55" wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] attribute \src "ls180.v:114.11-114.55" wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] - attribute \src "ls180.v:2891.1-2901.4" + attribute \src "ls180.v:2894.1-2904.4" wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] - attribute \src "ls180.v:2903.1-2949.4" + attribute \src "ls180.v:2906.1-2952.4" wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] - attribute \src "ls180.v:2951.1-2961.4" + attribute \src "ls180.v:2954.1-2964.4" wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] - attribute \src "ls180.v:2963.1-3009.4" + attribute \src "ls180.v:2966.1-3012.4" wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:214.5-214.40" + attribute \src "ls180.v:217.5-217.40" wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:3072.1-3082.4" + attribute \src "ls180.v:3075.1-3085.4" wire width 8 $0\main_libresocsim_we[7:0] - attribute \src "ls180.v:3088.1-3093.4" + attribute \src "ls180.v:3091.1-3096.4" wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4204.1-4214.4" + attribute \src "ls180.v:4207.1-4217.4" wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1687.5-1687.41" + attribute \src "ls180.v:1690.5-1690.41" wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5610.1-5617.4" + attribute \src "ls180.v:5613.1-5620.4" wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5643.1-5682.4" + attribute \src "ls180.v:5646.1-5685.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5643.1-5682.4" + attribute \src "ls180.v:5646.1-5685.4" wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:5643.1-5682.4" + attribute \src "ls180.v:5646.1-5685.4" wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5643.1-5682.4" + attribute \src "ls180.v:5646.1-5685.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5643.1-5682.4" + attribute \src "ls180.v:5646.1-5685.4" wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5643.1-5682.4" + attribute \src "ls180.v:5646.1-5685.4" wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5643.1-5682.4" + attribute \src "ls180.v:5646.1-5685.4" wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1496.5-1496.34" + attribute \src "ls180.v:1499.5-1499.34" wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5298.1-5305.4" + attribute \src "ls180.v:5301.1-5308.4" wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5354.1-5361.4" + attribute \src "ls180.v:5357.1-5364.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5308.1-5315.4" + attribute \src "ls180.v:5311.1-5318.4" wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5364.1-5371.4" + attribute \src "ls180.v:5367.1-5374.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5318.1-5325.4" + attribute \src "ls180.v:5321.1-5328.4" wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5374.1-5381.4" + attribute \src "ls180.v:5377.1-5384.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5328.1-5335.4" + attribute \src "ls180.v:5331.1-5338.4" wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5384.1-5391.4" + attribute \src "ls180.v:5387.1-5394.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5343.1-5350.4" + attribute \src "ls180.v:5346.1-5353.4" wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1602.5-1602.50" + attribute \src "ls180.v:1605.5-1605.50" wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5337.1-5342.4" + attribute \src "ls180.v:5340.1-5345.4" wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5290.1-5295.4" + attribute \src "ls180.v:5293.1-5298.4" wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:5172.1-5179.4" + attribute \src "ls180.v:5175.1-5182.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:5182.1-5189.4" + attribute \src "ls180.v:5185.1-5192.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5192.1-5199.4" + attribute \src "ls180.v:5195.1-5202.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5202.1-5209.4" + attribute \src "ls180.v:5205.1-5212.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1559.5-1559.51" + attribute \src "ls180.v:1562.5-1562.51" wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5210.1-5289.4" + attribute \src "ls180.v:5213.1-5292.4" wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:5150.1-5157.4" + attribute \src "ls180.v:5153.1-5160.4" wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:5788.1-5816.4" + attribute \src "ls180.v:5791.1-5819.4" wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5740.1-5776.4" + attribute \src "ls180.v:5743.1-5779.4" wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5740.1-5776.4" + attribute \src "ls180.v:5743.1-5779.4" wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5740.1-5776.4" + attribute \src "ls180.v:5743.1-5779.4" wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5740.1-5776.4" + attribute \src "ls180.v:5743.1-5779.4" wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5740.1-5776.4" + attribute \src "ls180.v:5743.1-5779.4" wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5740.1-5776.4" + attribute \src "ls180.v:5743.1-5779.4" wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1767.5-1767.45" + attribute \src "ls180.v:1770.5-1770.45" wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:5702.1-5739.4" + attribute \src "ls180.v:5705.1-5742.4" wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1823.5-1823.41" + attribute \src "ls180.v:1826.5-1826.41" wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5830.1-5837.4" + attribute \src "ls180.v:5833.1-5840.4" wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4556.1-4584.4" + attribute \src "ls180.v:4559.1-4587.4" wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1288.5-1288.53" + attribute \src "ls180.v:1291.5-1291.53" wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1289.5-1289.52" + attribute \src "ls180.v:1292.5-1292.52" wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1269.5-1269.46" + attribute \src "ls180.v:1272.5-1272.46" wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1242.5-1242.49" + attribute \src "ls180.v:1245.5-1245.49" wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1243.5-1243.48" + attribute \src "ls180.v:1246.5-1246.48" wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1244.5-1244.55" + attribute \src "ls180.v:1247.5-1247.55" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1246.5-1246.57" + attribute \src "ls180.v:1249.5-1249.57" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1247.5-1247.58" + attribute \src "ls180.v:1250.5-1250.58" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1249.11-1249.64" + attribute \src "ls180.v:1252.11-1252.64" wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1250.5-1250.59" + attribute \src "ls180.v:1253.5-1253.59" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1255.11-1255.57" + attribute \src "ls180.v:1258.11-1258.57" wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1256.5-1256.52" + attribute \src "ls180.v:1259.5-1259.52" wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4730.1-4823.4" + attribute \src "ls180.v:4733.1-4826.4" wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4620.1-4696.4" + attribute \src "ls180.v:4623.1-4699.4" wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4620.1-4696.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4620.1-4696.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4620.1-4696.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4620.1-4696.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4620.1-4696.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1232.11-1232.57" + attribute \src "ls180.v:1235.11-1235.57" wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1233.5-1233.52" + attribute \src "ls180.v:1236.5-1236.52" wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4620.1-4696.4" + attribute \src "ls180.v:4623.1-4699.4" wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1444.5-1444.55" + attribute \src "ls180.v:1447.5-1447.55" wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1445.5-1445.54" + attribute \src "ls180.v:1448.5-1448.54" wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1425.5-1425.48" + attribute \src "ls180.v:1428.5-1428.48" wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1396.5-1396.50" + attribute \src "ls180.v:1399.5-1399.50" wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1397.5-1397.49" + attribute \src "ls180.v:1400.5-1400.49" wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1398.5-1398.56" + attribute \src "ls180.v:1401.5-1401.56" wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1400.5-1400.58" + attribute \src "ls180.v:1403.5-1403.58" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1401.5-1401.59" + attribute \src "ls180.v:1404.5-1404.59" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1403.11-1403.65" + attribute \src "ls180.v:1406.11-1406.65" wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1404.5-1404.60" + attribute \src "ls180.v:1407.5-1407.60" wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1407.5-1407.51" + attribute \src "ls180.v:1410.5-1410.51" wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1408.5-1408.52" + attribute \src "ls180.v:1411.5-1411.52" wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1409.11-1409.58" + attribute \src "ls180.v:1412.11-1412.58" wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1410.5-1410.53" + attribute \src "ls180.v:1413.5-1413.53" wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1417.5-1417.41" + attribute \src "ls180.v:1420.5-1420.41" wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4991.1-5092.4" + attribute \src "ls180.v:4994.1-5095.4" wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1366.5-1366.54" + attribute \src "ls180.v:1369.5-1369.54" wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1367.5-1367.53" + attribute \src "ls180.v:1370.5-1370.53" wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1347.5-1347.47" + attribute \src "ls180.v:1350.5-1350.47" wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4857.1-4884.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4857.1-4884.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4857.1-4884.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4857.1-4884.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1334.5-1334.50" + attribute \src "ls180.v:1337.5-1337.50" wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1335.5-1335.49" + attribute \src "ls180.v:1338.5-1338.49" wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1336.5-1336.56" + attribute \src "ls180.v:1339.5-1339.56" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1337.5-1337.58" + attribute \src "ls180.v:1340.5-1340.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1338.5-1338.58" + attribute \src "ls180.v:1341.5-1341.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1339.5-1339.59" + attribute \src "ls180.v:1342.5-1342.59" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1340.11-1340.65" + attribute \src "ls180.v:1343.11-1343.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1341.11-1341.65" + attribute \src "ls180.v:1344.11-1344.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1342.5-1342.60" + attribute \src "ls180.v:1345.5-1345.60" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1332.5-1332.50" + attribute \src "ls180.v:1335.5-1335.50" wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1321.5-1321.51" + attribute \src "ls180.v:1324.5-1324.51" wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1322.5-1322.52" + attribute \src "ls180.v:1325.5-1325.52" wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" + attribute \src "ls180.v:5395.1-5585.4" wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4885.1-4957.4" + attribute \src "ls180.v:4888.1-4960.4" wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4857.1-4884.4" + attribute \src "ls180.v:4860.1-4887.4" wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4586.1-4619.4" + attribute \src "ls180.v:4589.1-4622.4" wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4586.1-4619.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1214.5-1214.40" + attribute \src "ls180.v:1217.5-1217.40" wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4586.1-4619.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4586.1-4619.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4586.1-4619.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4586.1-4619.4" + attribute \src "ls180.v:4589.1-4622.4" wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4586.1-4619.4" + attribute \src "ls180.v:4589.1-4622.4" wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3361.1-3368.4" + attribute \src "ls180.v:3364.1-3371.4" wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:536.5-536.64" + attribute \src "ls180.v:539.5-539.64" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:519.5-519.67" + attribute \src "ls180.v:522.5-522.67" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:520.5-520.66" + attribute \src "ls180.v:523.5-523.66" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3383.1-3390.4" + attribute \src "ls180.v:3386.1-3393.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3350.1-3357.4" + attribute \src "ls180.v:3353.1-3360.4" wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:4048.1-4056.4" + attribute \src "ls180.v:4051.1-4059.4" wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3399.1-3492.4" + attribute \src "ls180.v:3402.1-3495.4" wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:578.32-578.76" + attribute \src "ls180.v:581.32-581.76" wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:576.32-576.75" + attribute \src "ls180.v:579.32-579.75" wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3518.1-3525.4" + attribute \src "ls180.v:3521.1-3528.4" wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:618.5-618.64" + attribute \src "ls180.v:621.5-621.64" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:601.5-601.67" + attribute \src "ls180.v:604.5-604.67" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:602.5-602.66" + attribute \src "ls180.v:605.5-605.66" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3540.1-3547.4" + attribute \src "ls180.v:3543.1-3550.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3507.1-3514.4" + attribute \src "ls180.v:3510.1-3517.4" wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:4057.1-4065.4" + attribute \src "ls180.v:4060.1-4068.4" wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3556.1-3649.4" + attribute \src "ls180.v:3559.1-3652.4" wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:660.32-660.76" + attribute \src "ls180.v:663.32-663.76" wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:658.32-658.75" + attribute \src "ls180.v:661.32-661.75" wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3675.1-3682.4" + attribute \src "ls180.v:3678.1-3685.4" wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:700.5-700.64" + attribute \src "ls180.v:703.5-703.64" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:683.5-683.67" + attribute \src "ls180.v:686.5-686.67" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:684.5-684.66" + attribute \src "ls180.v:687.5-687.66" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3697.1-3704.4" + attribute \src "ls180.v:3700.1-3707.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3664.1-3671.4" + attribute \src "ls180.v:3667.1-3674.4" wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:4066.1-4074.4" + attribute \src "ls180.v:4069.1-4077.4" wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3713.1-3806.4" + attribute \src "ls180.v:3716.1-3809.4" wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:742.32-742.76" + attribute \src "ls180.v:745.32-745.76" wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:740.32-740.75" + attribute \src "ls180.v:743.32-743.75" wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3832.1-3839.4" + attribute \src "ls180.v:3835.1-3842.4" wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:782.5-782.64" + attribute \src "ls180.v:785.5-785.64" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:765.5-765.67" + attribute \src "ls180.v:768.5-768.67" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:766.5-766.66" + attribute \src "ls180.v:769.5-769.66" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3854.1-3861.4" + attribute \src "ls180.v:3857.1-3864.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3821.1-3828.4" + attribute \src "ls180.v:3824.1-3831.4" wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:4075.1-4083.4" + attribute \src "ls180.v:4078.1-4086.4" wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3870.1-3963.4" + attribute \src "ls180.v:3873.1-3966.4" wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:824.32-824.76" + attribute \src "ls180.v:827.32-827.76" wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:822.32-822.75" + attribute \src "ls180.v:825.32-825.75" wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3997.1-4002.4" + attribute \src "ls180.v:4000.1-4005.4" wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:4003.1-4008.4" + attribute \src "ls180.v:4006.1-4011.4" wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:4009.1-4014.4" + attribute \src "ls180.v:4012.1-4017.4" wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:832.5-832.43" + attribute \src "ls180.v:835.5-835.43" wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3983.1-3989.4" + attribute \src "ls180.v:3986.1-3992.4" wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:830.5-830.48" + attribute \src "ls180.v:833.5-833.48" wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:829.5-829.43" + attribute \src "ls180.v:832.5-832.43" wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:827.5-827.44" + attribute \src "ls180.v:830.5-830.44" wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:828.5-828.45" + attribute \src "ls180.v:831.5-831.45" wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:4030.1-4035.4" + attribute \src "ls180.v:4033.1-4038.4" wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:4036.1-4041.4" + attribute \src "ls180.v:4039.1-4044.4" wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:4042.1-4047.4" + attribute \src "ls180.v:4045.1-4050.4" wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:4016.1-4022.4" + attribute \src "ls180.v:4019.1-4025.4" wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3305.1-3335.4" + attribute \src "ls180.v:3308.1-3338.4" wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:480.5-480.42" + attribute \src "ls180.v:483.5-483.42" wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:481.5-481.43" + attribute \src "ls180.v:484.5-484.43" wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3305.1-3335.4" + attribute \src "ls180.v:3308.1-3338.4" wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:416.5-416.38" + attribute \src "ls180.v:419.5-419.38" wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:465.5-465.35" + attribute \src "ls180.v:468.5-468.35" wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4184.1-4197.4" + attribute \src "ls180.v:4187.1-4200.4" wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4184.1-4197.4" + attribute \src "ls180.v:4187.1-4200.4" wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:366.5-366.36" + attribute \src "ls180.v:369.5-369.36" wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3246.1-3262.4" + attribute \src "ls180.v:3249.1-3265.4" wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3246.1-3262.4" + attribute \src "ls180.v:3249.1-3265.4" wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3246.1-3262.4" + attribute \src "ls180.v:3249.1-3265.4" wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3246.1-3262.4" + attribute \src "ls180.v:3249.1-3265.4" wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:863.12-863.36" + attribute \src "ls180.v:866.12-866.36" wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:864.11-864.35" + attribute \src "ls180.v:867.11-867.35" wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3305.1-3335.4" + attribute \src "ls180.v:3308.1-3338.4" wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3188.1-3242.4" + attribute \src "ls180.v:3191.1-3245.4" wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:866.5-866.31" + attribute \src "ls180.v:869.5-869.31" wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:867.5-867.31" + attribute \src "ls180.v:870.5-870.31" wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:4088.1-4160.4" + attribute \src "ls180.v:4091.1-4163.4" wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:871.32-871.63" + attribute \src "ls180.v:874.32-874.63" wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:869.32-869.63" + attribute \src "ls180.v:872.32-872.63" wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:918.5-918.54" + attribute \src "ls180.v:921.5-921.54" wire $0\main_socbushandler_converted_interface_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_socbushandler_counter[0:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 64 $0\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\main_socbushandler_skip[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4417.1-4465.4" + attribute \src "ls180.v:4420.1-4468.4" wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1105.12-1105.47" + attribute \src "ls180.v:1108.12-1108.47" wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6553.1-6558.4" + attribute \src "ls180.v:6556.1-6561.4" wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4476.1-4524.4" + attribute \src "ls180.v:4479.1-4527.4" wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6599.1-6604.4" + attribute \src "ls180.v:6602.1-6607.4" wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:3097.1-3107.4" + attribute \src "ls180.v:3100.1-3110.4" wire width 8 $0\main_sram0_we[7:0] - attribute \src "ls180.v:3111.1-3121.4" + attribute \src "ls180.v:3114.1-3124.4" wire width 8 $0\main_sram1_we[7:0] - attribute \src "ls180.v:3125.1-3135.4" + attribute \src "ls180.v:3128.1-3138.4" wire width 8 $0\main_sram2_we[7:0] - attribute \src "ls180.v:3139.1-3149.4" + attribute \src "ls180.v:3142.1-3152.4" wire width 8 $0\main_sram3_we[7:0] - attribute \src "ls180.v:4324.1-4328.4" + attribute \src "ls180.v:4327.1-4331.4" wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4313.1-4317.4" + attribute \src "ls180.v:4316.1-4320.4" wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:954.5-954.38" + attribute \src "ls180.v:957.5-957.38" wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:955.5-955.37" + attribute \src "ls180.v:958.5-958.37" wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:1081.5-1081.27" + attribute \src "ls180.v:1084.5-1084.27" wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4318.1-4323.4" + attribute \src "ls180.v:4321.1-4326.4" wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1063.5-1063.37" + attribute \src "ls180.v:1066.5-1066.37" wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4376.1-4383.4" + attribute \src "ls180.v:4379.1-4386.4" wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4307.1-4312.4" + attribute \src "ls180.v:4310.1-4315.4" wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:1026.5-1026.37" + attribute \src "ls180.v:1029.5-1029.37" wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:1009.5-1009.40" + attribute \src "ls180.v:1012.5-1012.40" wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:1010.5-1010.39" + attribute \src "ls180.v:1013.5-1013.39" wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4346.1-4353.4" + attribute \src "ls180.v:4349.1-4356.4" wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4216.1-4262.4" + attribute \src "ls180.v:4219.1-4265.4" wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire width 30 $0\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:3011.1-3021.4" + attribute \src "ls180.v:3014.1-3024.4" wire width 32 $0\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire width 4 $0\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:3023.1-3069.4" + attribute \src "ls180.v:3026.1-3072.4" wire $0\main_wb_sdram_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10350.1-10368.4" + attribute \src "ls180.v:10353.1-10371.4" wire width 6 $0\memadr[5:0] - attribute \src "ls180.v:10378.1-10396.4" + attribute \src "ls180.v:10381.1-10399.4" wire width 6 $0\memadr_1[5:0] - attribute \src "ls180.v:10406.1-10424.4" + attribute \src "ls180.v:10409.1-10427.4" wire width 6 $0\memadr_2[5:0] - attribute \src "ls180.v:10434.1-10452.4" + attribute \src "ls180.v:10437.1-10455.4" wire width 6 $0\memadr_3[5:0] - attribute \src "ls180.v:10462.1-10480.4" + attribute \src "ls180.v:10465.1-10483.4" wire width 6 $0\memadr_4[5:0] - attribute \src "ls180.v:10490.1-10494.4" + attribute \src "ls180.v:10493.1-10497.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10504.1-10508.4" + attribute \src "ls180.v:10507.1-10511.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10518.1-10522.4" + attribute \src "ls180.v:10521.1-10525.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10532.1-10536.4" + attribute \src "ls180.v:10535.1-10539.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10547.1-10551.4" + attribute \src "ls180.v:10550.1-10554.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10553.1-10556.4" + attribute \src "ls180.v:10556.1-10559.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10564.1-10568.4" + attribute \src "ls180.v:10567.1-10571.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10570.1-10573.4" + attribute \src "ls180.v:10573.1-10576.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10580.1-10584.4" + attribute \src "ls180.v:10583.1-10587.4" wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10594.1-10598.4" + attribute \src "ls180.v:10597.1-10601.4" wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7630.1-7700.4" + attribute \src "ls180.v:7633.1-7703.4" wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7702.1-10346.4" + attribute \src "ls180.v:7705.1-10349.4" wire $0\uart_tx[0:0] - attribute \src "ls180.v:1854.11-1854.49" + attribute \src "ls180.v:1857.11-1857.49" wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1853.11-1853.44" + attribute \src "ls180.v:1856.11-1856.44" wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1856.11-1856.49" + attribute \src "ls180.v:1859.11-1859.49" wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1855.11-1855.44" + attribute \src "ls180.v:1858.11-1858.44" wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1858.11-1858.49" + attribute \src "ls180.v:1861.11-1861.49" wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1857.11-1857.44" + attribute \src "ls180.v:1860.11-1860.44" wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1860.11-1860.49" + attribute \src "ls180.v:1863.11-1863.49" wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1859.11-1859.44" + attribute \src "ls180.v:1862.11-1862.44" wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2713.5-2713.41" + attribute \src "ls180.v:2716.5-2716.41" wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2726.5-2726.42" + attribute \src "ls180.v:2729.5-2729.42" wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2727.5-2727.42" + attribute \src "ls180.v:2730.5-2730.42" wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2731.12-2731.50" + attribute \src "ls180.v:2734.12-2734.50" wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2732.5-2732.42" + attribute \src "ls180.v:2735.5-2735.42" wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2733.5-2733.42" + attribute \src "ls180.v:2736.5-2736.42" wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2734.12-2734.50" + attribute \src "ls180.v:2737.12-2737.50" wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2735.5-2735.42" + attribute \src "ls180.v:2738.5-2738.42" wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2736.5-2736.42" + attribute \src "ls180.v:2739.5-2739.42" wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2737.12-2737.50" + attribute \src "ls180.v:2740.12-2740.50" wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2738.5-2738.42" + attribute \src "ls180.v:2741.5-2741.42" wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2714.12-2714.49" + attribute \src "ls180.v:2717.12-2717.49" wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2739.5-2739.42" + attribute \src "ls180.v:2742.5-2742.42" wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2740.12-2740.50" + attribute \src "ls180.v:2743.12-2743.50" wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2741.5-2741.42" + attribute \src "ls180.v:2744.5-2744.42" wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2742.5-2742.42" + attribute \src "ls180.v:2745.5-2745.42" wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2743.12-2743.50" + attribute \src "ls180.v:2746.12-2746.50" wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2744.12-2744.50" + attribute \src "ls180.v:2747.12-2747.50" wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:2745.11-2745.48" + attribute \src "ls180.v:2748.11-2748.48" wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:2746.5-2746.42" + attribute \src "ls180.v:2749.5-2749.42" wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2747.5-2747.42" + attribute \src "ls180.v:2750.5-2750.42" wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2748.5-2748.42" + attribute \src "ls180.v:2751.5-2751.42" wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2715.11-2715.47" + attribute \src "ls180.v:2718.11-2718.47" wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2749.11-2749.48" + attribute \src "ls180.v:2752.11-2752.48" wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2750.11-2750.48" + attribute \src "ls180.v:2753.11-2753.48" wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2716.5-2716.41" + attribute \src "ls180.v:2719.5-2719.41" wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2717.5-2717.41" + attribute \src "ls180.v:2720.5-2720.41" wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2718.5-2718.41" + attribute \src "ls180.v:2721.5-2721.41" wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2722.5-2722.41" + attribute \src "ls180.v:2725.5-2725.41" wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2723.12-2723.49" + attribute \src "ls180.v:2726.12-2726.49" wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2724.11-2724.47" + attribute \src "ls180.v:2727.11-2727.47" wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2725.5-2725.41" + attribute \src "ls180.v:2728.5-2728.41" wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2719.5-2719.39" + attribute \src "ls180.v:2722.5-2722.39" wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2720.5-2720.39" + attribute \src "ls180.v:2723.5-2723.39" wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2721.5-2721.39" + attribute \src "ls180.v:2724.5-2724.39" wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2728.5-2728.39" + attribute \src "ls180.v:2731.5-2731.39" wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2729.5-2729.39" + attribute \src "ls180.v:2732.5-2732.39" wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2730.5-2730.39" + attribute \src "ls180.v:2733.5-2733.39" wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1840.5-1840.41" + attribute \src "ls180.v:1843.5-1843.41" wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1839.5-1839.36" + attribute \src "ls180.v:1842.5-1842.36" wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1844.5-1844.41" + attribute \src "ls180.v:1847.5-1847.41" wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1843.5-1843.36" + attribute \src "ls180.v:1846.5-1846.36" wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1848.5-1848.41" + attribute \src "ls180.v:1851.5-1851.41" wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1847.5-1847.36" + attribute \src "ls180.v:1850.5-1850.36" wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1885.5-1885.40" + attribute \src "ls180.v:1888.5-1888.40" wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1884.5-1884.35" + attribute \src "ls180.v:1887.5-1887.35" wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:2013.12-2013.39" + attribute \src "ls180.v:2016.12-2016.39" wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:2010.5-2010.25" + attribute \src "ls180.v:2013.5-2013.25" wire $1\builder_error[0:0] - attribute \src "ls180.v:2007.11-2007.31" + attribute \src "ls180.v:2010.11-2010.31" wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:2017.11-2017.51" + attribute \src "ls180.v:2020.11-2020.51" wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2519.11-2519.52" + attribute \src "ls180.v:2522.11-2522.52" wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2552.11-2552.52" + attribute \src "ls180.v:2555.11-2555.52" wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2593.11-2593.52" + attribute \src "ls180.v:2596.11-2596.52" wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2658.11-2658.52" + attribute \src "ls180.v:2661.11-2661.52" wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2683.11-2683.52" + attribute \src "ls180.v:2686.11-2686.52" wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2058.11-2058.51" + attribute \src "ls180.v:2061.11-2061.51" wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2087.11-2087.51" + attribute \src "ls180.v:2090.11-2090.51" wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2100.11-2100.51" + attribute \src "ls180.v:2103.11-2103.51" wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2141.11-2141.51" + attribute \src "ls180.v:2144.11-2144.51" wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2182.11-2182.51" + attribute \src "ls180.v:2185.11-2185.51" wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2247.11-2247.51" + attribute \src "ls180.v:2250.11-2250.51" wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2380.11-2380.51" + attribute \src "ls180.v:2383.11-2383.51" wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2461.11-2461.51" + attribute \src "ls180.v:2464.11-2464.51" wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2478.11-2478.51" + attribute \src "ls180.v:2481.11-2481.51" wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1972.12-1972.43" + attribute \src "ls180.v:1975.12-1975.43" wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2709.12-2709.55" + attribute \src "ls180.v:2712.12-2712.55" wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2710.5-2710.50" + attribute \src "ls180.v:2713.5-2713.50" wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1974.11-1974.43" + attribute \src "ls180.v:1977.11-1977.43" wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2707.11-2707.55" + attribute \src "ls180.v:2710.11-2710.55" wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2708.5-2708.52" + attribute \src "ls180.v:2711.5-2711.52" wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1973.5-1973.34" + attribute \src "ls180.v:1976.5-1976.34" wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2711.5-2711.46" + attribute \src "ls180.v:2714.5-2714.46" wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2712.5-2712.49" + attribute \src "ls180.v:2715.5-2715.49" wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1982.5-1982.44" + attribute \src "ls180.v:1985.5-1985.44" wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1978.12-1978.54" + attribute \src "ls180.v:1981.12-1981.54" wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1862.11-1862.48" + attribute \src "ls180.v:1865.11-1865.48" wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1861.11-1861.43" + attribute \src "ls180.v:1864.11-1864.43" wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2816.32-2816.66" + attribute \src "ls180.v:2819.32-2819.66" wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2817.32-2817.66" + attribute \src "ls180.v:2820.32-2820.66" wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2836.32-2836.67" + attribute \src "ls180.v:2839.32-2839.67" wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2837.32-2837.67" + attribute \src "ls180.v:2840.32-2840.67" wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2838.32-2838.67" + attribute \src "ls180.v:2841.32-2841.67" wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2839.32-2839.67" + attribute \src "ls180.v:2842.32-2842.67" wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2840.32-2840.67" + attribute \src "ls180.v:2843.32-2843.67" wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2841.32-2841.67" + attribute \src "ls180.v:2844.32-2844.67" wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2842.32-2842.67" + attribute \src "ls180.v:2845.32-2845.67" wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2843.32-2843.67" + attribute \src "ls180.v:2846.32-2846.67" wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2844.32-2844.67" + attribute \src "ls180.v:2847.32-2847.67" wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2845.32-2845.67" + attribute \src "ls180.v:2848.32-2848.67" wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2846.32-2846.67" + attribute \src "ls180.v:2849.32-2849.67" wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2847.32-2847.67" + attribute \src "ls180.v:2850.32-2850.67" wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2848.32-2848.67" + attribute \src "ls180.v:2851.32-2851.67" wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2849.32-2849.67" + attribute \src "ls180.v:2852.32-2852.67" wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2818.32-2818.66" + attribute \src "ls180.v:2821.32-2821.66" wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2819.32-2819.66" + attribute \src "ls180.v:2822.32-2822.66" wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2820.32-2820.66" + attribute \src "ls180.v:2823.32-2823.66" wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2821.32-2821.66" + attribute \src "ls180.v:2824.32-2824.66" wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2822.32-2822.66" + attribute \src "ls180.v:2825.32-2825.66" wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2823.32-2823.66" + attribute \src "ls180.v:2826.32-2826.66" wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2824.32-2824.66" + attribute \src "ls180.v:2827.32-2827.66" wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2825.32-2825.66" + attribute \src "ls180.v:2828.32-2828.66" wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2826.32-2826.66" + attribute \src "ls180.v:2829.32-2829.66" wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2827.32-2827.66" + attribute \src "ls180.v:2830.32-2830.66" wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2828.32-2828.66" + attribute \src "ls180.v:2831.32-2831.66" wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2829.32-2829.66" + attribute \src "ls180.v:2832.32-2832.66" wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2830.32-2830.66" + attribute \src "ls180.v:2833.32-2833.66" wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2831.32-2831.66" + attribute \src "ls180.v:2834.32-2834.66" wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2832.32-2832.66" + attribute \src "ls180.v:2835.32-2835.66" wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2833.32-2833.66" + attribute \src "ls180.v:2836.32-2836.66" wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2834.32-2834.66" + attribute \src "ls180.v:2837.32-2837.66" wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2835.32-2835.66" + attribute \src "ls180.v:2838.32-2838.66" wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1880.5-1880.43" + attribute \src "ls180.v:1883.5-1883.43" wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1881.5-1881.43" + attribute \src "ls180.v:1884.5-1884.43" wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1882.5-1882.43" + attribute \src "ls180.v:1885.5-1885.43" wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1883.5-1883.43" + attribute \src "ls180.v:1886.5-1886.43" wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1879.5-1879.42" + attribute \src "ls180.v:1882.5-1882.42" wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2706.11-2706.36" + attribute \src "ls180.v:2709.11-2709.36" wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1852.11-1852.46" + attribute \src "ls180.v:1855.11-1855.46" wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1851.11-1851.41" + attribute \src "ls180.v:1854.11-1854.41" wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1961.11-1961.51" + attribute \src "ls180.v:1964.11-1964.51" wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1960.11-1960.46" + attribute \src "ls180.v:1963.11-1963.46" wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1929.5-1929.57" + attribute \src "ls180.v:1932.5-1932.57" wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1928.5-1928.52" + attribute \src "ls180.v:1931.5-1931.52" wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1941.11-1941.47" + attribute \src "ls180.v:1944.11-1944.47" wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1940.11-1940.42" + attribute \src "ls180.v:1943.11-1943.42" wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1965.5-1965.49" + attribute \src "ls180.v:1968.5-1968.49" wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1964.5-1964.44" + attribute \src "ls180.v:1967.5-1967.44" wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1969.11-1969.65" + attribute \src "ls180.v:1972.11-1972.65" wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1968.11-1968.60" + attribute \src "ls180.v:1971.11-1971.60" wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1917.11-1917.46" + attribute \src "ls180.v:1920.11-1920.46" wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1916.11-1916.41" + attribute \src "ls180.v:1919.11-1919.41" wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1905.11-1905.52" + attribute \src "ls180.v:1908.11-1908.52" wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1904.11-1904.47" + attribute \src "ls180.v:1907.11-1907.47" wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1901.11-1901.52" + attribute \src "ls180.v:1904.11-1904.52" wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1900.11-1900.47" + attribute \src "ls180.v:1903.11-1903.47" wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1913.5-1913.46" + attribute \src "ls180.v:1916.5-1916.46" wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1912.5-1912.41" + attribute \src "ls180.v:1915.5-1915.41" wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1921.11-1921.53" + attribute \src "ls180.v:1924.11-1924.53" wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1920.11-1920.48" + attribute \src "ls180.v:1923.11-1923.48" wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1897.5-1897.46" + attribute \src "ls180.v:1900.5-1900.46" wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1896.5-1896.41" + attribute \src "ls180.v:1899.5-1899.41" wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:2001.5-2001.30" + attribute \src "ls180.v:2004.5-2004.30" wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1997.12-1997.40" + attribute \src "ls180.v:2000.12-2000.40" wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:2008.12-2008.37" + attribute \src "ls180.v:2011.12-2011.37" wire width 13 $1\builder_slave_sel[12:0] - attribute \src "ls180.v:2009.12-2009.39" + attribute \src "ls180.v:2012.12-2012.39" wire width 13 $1\builder_slave_sel_r[12:0] - attribute \src "ls180.v:1889.11-1889.47" + attribute \src "ls180.v:1892.11-1892.47" wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1888.11-1888.42" + attribute \src "ls180.v:1891.11-1891.42" wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1893.11-1893.47" + attribute \src "ls180.v:1896.11-1896.47" wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1892.11-1892.42" + attribute \src "ls180.v:1895.11-1895.42" wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2705.11-2705.31" + attribute \src "ls180.v:2708.11-2708.31" wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2758.5-2758.39" + attribute \src "ls180.v:2761.5-2761.39" wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2759.5-2759.39" + attribute \src "ls180.v:2762.5-2762.39" wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2751.11-2751.47" + attribute \src "ls180.v:2754.11-2754.47" wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2752.12-2752.49" + attribute \src "ls180.v:2755.12-2755.49" wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2753.5-2753.41" + attribute \src "ls180.v:2756.5-2756.41" wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2754.5-2754.41" + attribute \src "ls180.v:2757.5-2757.41" wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2755.5-2755.41" + attribute \src "ls180.v:2758.5-2758.41" wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2756.5-2756.41" + attribute \src "ls180.v:2759.5-2759.41" wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2757.5-2757.41" + attribute \src "ls180.v:2760.5-2760.41" wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:935.5-935.29" + attribute \src "ls180.v:938.5-938.29" wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:318.5-318.35" + attribute \src "ls180.v:321.5-321.35" wire $1\main_converter0_counter[0:0] - attribute \src "ls180.v:1841.5-1841.57" + attribute \src "ls180.v:1844.5-1844.57" wire $1\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1842.5-1842.60" + attribute \src "ls180.v:1845.5-1845.60" wire $1\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:320.12-320.41" + attribute \src "ls180.v:323.12-323.41" wire width 64 $1\main_converter0_dat_r[63:0] - attribute \src "ls180.v:317.5-317.32" + attribute \src "ls180.v:320.5-320.32" wire $1\main_converter0_skip[0:0] - attribute \src "ls180.v:333.5-333.35" + attribute \src "ls180.v:336.5-336.35" wire $1\main_converter1_counter[0:0] - attribute \src "ls180.v:1845.5-1845.57" + attribute \src "ls180.v:1848.5-1848.57" wire $1\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1846.5-1846.60" + attribute \src "ls180.v:1849.5-1849.60" wire $1\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:335.12-335.41" + attribute \src "ls180.v:338.12-338.41" wire width 64 $1\main_converter1_dat_r[63:0] - attribute \src "ls180.v:332.5-332.32" + attribute \src "ls180.v:335.5-335.32" wire $1\main_converter1_skip[0:0] - attribute \src "ls180.v:932.5-932.34" + attribute \src "ls180.v:935.5-935.34" wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1886.5-1886.55" + attribute \src "ls180.v:1889.5-1889.55" wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1887.5-1887.58" + attribute \src "ls180.v:1890.5-1890.58" wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:934.12-934.40" + attribute \src "ls180.v:937.12-937.40" wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:931.5-931.31" + attribute \src "ls180.v:934.5-934.31" wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:354.12-354.38" + attribute \src "ls180.v:357.12-357.38" wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:355.5-355.36" + attribute \src "ls180.v:358.5-358.36" wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1172.12-1172.30" + attribute \src "ls180.v:1175.12-1175.30" wire width 24 $1\main_dummy[23:0] - attribute \src "ls180.v:1083.12-1083.49" + attribute \src "ls180.v:1086.12-1086.49" wire width 16 $1\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:1089.5-1089.40" + attribute \src "ls180.v:1092.5-1092.40" wire $1\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:1088.12-1088.53" + attribute \src "ls180.v:1091.12-1091.53" wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:1093.5-1093.41" + attribute \src "ls180.v:1096.5-1096.41" wire $1\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:1092.12-1092.54" + attribute \src "ls180.v:1095.12-1095.54" wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:1090.12-1090.49" + attribute \src "ls180.v:1093.12-1093.49" wire width 16 $1\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:1197.5-1197.23" + attribute \src "ls180.v:1200.5-1200.23" wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1196.11-1196.34" + attribute \src "ls180.v:1199.11-1199.34" wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:339.5-339.24" + attribute \src "ls180.v:342.5-342.24" wire $1\main_int_rst[0:0] - attribute \src "ls180.v:312.5-312.51" + attribute \src "ls180.v:315.5-315.51" wire $1\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:252.5-252.39" + attribute \src "ls180.v:255.5-255.39" wire $1\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:1745.12-1745.43" + attribute \src "ls180.v:1748.12-1748.43" wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1749.5-1749.35" + attribute \src "ls180.v:1752.5-1752.35" wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1748.11-1748.41" + attribute \src "ls180.v:1751.11-1751.41" wire width 8 $1\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:1750.5-1750.35" + attribute \src "ls180.v:1753.5-1753.35" wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1752.5-1752.34" + attribute \src "ls180.v:1755.5-1755.34" wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:327.5-327.51" + attribute \src "ls180.v:330.5-330.51" wire $1\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:267.5-267.39" + attribute \src "ls180.v:270.5-270.39" wire $1\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:282.5-282.39" + attribute \src "ls180.v:285.5-285.39" wire $1\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:297.5-297.39" + attribute \src "ls180.v:300.5-300.39" wire $1\main_interface3_ram_bus_ack[0:0] attribute \src "ls180.v:63.12-63.47" wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:224.5-224.34" + attribute \src "ls180.v:227.5-227.34" wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:223.5-223.39" + attribute \src "ls180.v:226.5-226.39" wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:244.5-244.44" + attribute \src "ls180.v:247.5-247.44" wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:243.5-243.49" + attribute \src "ls180.v:246.5-246.49" wire $1\main_libresocsim_eventmanager_storage[0:0] attribute \src "ls180.v:65.12-65.55" wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] @@ -236793,15 +239316,15 @@ module \ls180 wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] attribute \src "ls180.v:104.5-104.49" wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:220.5-220.36" + attribute \src "ls180.v:223.5-223.36" wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:219.12-219.49" + attribute \src "ls180.v:222.12-222.49" wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:210.5-210.40" + attribute \src "ls180.v:213.5-213.40" wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:222.5-222.38" + attribute \src "ls180.v:225.5-225.38" wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:221.12-221.51" + attribute \src "ls180.v:224.12-224.51" wire width 32 $1\main_libresocsim_reload_storage[31:0] attribute \src "ls180.v:56.5-56.37" wire $1\main_libresocsim_reset_re[0:0] @@ -236811,8756 +239334,8756 @@ module \ls180 wire $1\main_libresocsim_scratch_re[0:0] attribute \src "ls180.v:57.12-57.60" wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:226.5-226.44" + attribute \src "ls180.v:229.5-229.44" wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:225.5-225.49" + attribute \src "ls180.v:228.5-228.49" wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:245.12-245.42" + attribute \src "ls180.v:248.12-248.42" wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:227.12-227.49" + attribute \src "ls180.v:230.12-230.49" wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:217.11-217.37" + attribute \src "ls180.v:220.11-220.37" wire width 8 $1\main_libresocsim_we[7:0] - attribute \src "ls180.v:233.5-233.39" + attribute \src "ls180.v:236.5-236.39" wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:234.5-234.45" + attribute \src "ls180.v:237.5-237.45" wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:231.5-231.41" + attribute \src "ls180.v:234.5-234.41" wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:923.12-923.40" + attribute \src "ls180.v:926.12-926.40" wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:927.5-927.32" + attribute \src "ls180.v:930.5-930.32" wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:924.12-924.42" + attribute \src "ls180.v:927.12-927.42" wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:926.11-926.38" + attribute \src "ls180.v:929.11-929.38" wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:928.5-928.32" + attribute \src "ls180.v:931.5-931.32" wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:930.5-930.31" + attribute \src "ls180.v:933.5-933.31" wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1176.12-1176.37" + attribute \src "ls180.v:1179.12-1179.37" wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1178.5-1178.31" + attribute \src "ls180.v:1181.5-1181.31" wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1177.5-1177.36" + attribute \src "ls180.v:1180.5-1180.36" wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1182.5-1182.31" + attribute \src "ls180.v:1185.5-1185.31" wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1181.12-1181.44" + attribute \src "ls180.v:1184.12-1184.44" wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1180.5-1180.30" + attribute \src "ls180.v:1183.5-1183.30" wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1179.12-1179.43" + attribute \src "ls180.v:1182.12-1182.43" wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1186.12-1186.37" + attribute \src "ls180.v:1189.12-1189.37" wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1188.5-1188.31" + attribute \src "ls180.v:1191.5-1191.31" wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1187.5-1187.36" + attribute \src "ls180.v:1190.5-1190.36" wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1192.5-1192.31" + attribute \src "ls180.v:1195.5-1195.31" wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1191.12-1191.44" + attribute \src "ls180.v:1194.12-1194.44" wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1190.5-1190.30" + attribute \src "ls180.v:1193.5-1193.30" wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1189.12-1189.43" + attribute \src "ls180.v:1192.12-1192.43" wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:356.11-356.32" + attribute \src "ls180.v:359.11-359.32" wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1714.11-1714.50" + attribute \src "ls180.v:1717.11-1717.50" wire width 3 $1\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:1710.5-1710.51" + attribute \src "ls180.v:1713.5-1713.51" wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1711.5-1711.50" + attribute \src "ls180.v:1714.5-1714.50" wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1712.12-1712.66" + attribute \src "ls180.v:1715.12-1715.66" wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:1713.11-1713.77" + attribute \src "ls180.v:1716.11-1716.77" wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1716.5-1716.49" + attribute \src "ls180.v:1719.5-1719.49" wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1689.11-1689.47" + attribute \src "ls180.v:1692.11-1692.47" wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1686.11-1686.45" + attribute \src "ls180.v:1689.11-1689.45" wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1688.11-1688.47" + attribute \src "ls180.v:1691.11-1691.47" wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1690.11-1690.50" + attribute \src "ls180.v:1693.11-1693.50" wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1724.12-1724.62" + attribute \src "ls180.v:1727.12-1727.62" wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1725.12-1725.60" + attribute \src "ls180.v:1728.12-1728.60" wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:1722.5-1722.45" + attribute \src "ls180.v:1725.5-1725.45" wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1732.5-1732.54" + attribute \src "ls180.v:1735.5-1735.54" wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1731.12-1731.67" + attribute \src "ls180.v:1734.12-1734.67" wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1736.5-1736.56" + attribute \src "ls180.v:1739.5-1739.56" wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1735.5-1735.61" + attribute \src "ls180.v:1738.5-1738.61" wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1734.5-1734.56" + attribute \src "ls180.v:1737.5-1737.56" wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1733.12-1733.69" + attribute \src "ls180.v:1736.12-1736.69" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1740.5-1740.54" + attribute \src "ls180.v:1743.5-1743.54" wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1739.5-1739.59" + attribute \src "ls180.v:1742.5-1742.59" wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1742.12-1742.61" + attribute \src "ls180.v:1745.12-1745.61" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1962.12-1962.87" + attribute \src "ls180.v:1965.12-1965.87" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1963.5-1963.82" + attribute \src "ls180.v:1966.5-1966.82" wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1727.5-1727.57" + attribute \src "ls180.v:1730.5-1730.57" wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1737.5-1737.53" + attribute \src "ls180.v:1740.5-1740.53" wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1506.5-1506.38" + attribute \src "ls180.v:1509.5-1509.38" wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1505.12-1505.51" + attribute \src "ls180.v:1508.12-1508.51" wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1504.5-1504.39" + attribute \src "ls180.v:1507.5-1507.39" wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1503.11-1503.51" + attribute \src "ls180.v:1506.11-1506.51" wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1490.5-1490.39" + attribute \src "ls180.v:1493.5-1493.39" wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1489.12-1489.52" + attribute \src "ls180.v:1492.12-1492.52" wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1492.5-1492.38" + attribute \src "ls180.v:1495.5-1495.38" wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1491.12-1491.51" + attribute \src "ls180.v:1494.12-1494.51" wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1645.11-1645.39" + attribute \src "ls180.v:1648.11-1648.39" wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1946.11-1946.62" + attribute \src "ls180.v:1949.11-1949.62" wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1947.5-1947.59" + attribute \src "ls180.v:1950.5-1950.59" wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1646.5-1646.32" + attribute \src "ls180.v:1649.5-1649.32" wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1942.5-1942.55" + attribute \src "ls180.v:1945.5-1945.55" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1943.5-1943.58" + attribute \src "ls180.v:1946.5-1946.58" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1647.5-1647.33" + attribute \src "ls180.v:1650.5-1650.33" wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1950.5-1950.56" + attribute \src "ls180.v:1953.5-1953.56" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1951.5-1951.59" + attribute \src "ls180.v:1954.5-1954.59" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1497.13-1497.53" + attribute \src "ls180.v:1500.13-1500.53" wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1958.13-1958.76" + attribute \src "ls180.v:1961.13-1961.76" wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1959.5-1959.69" + attribute \src "ls180.v:1962.5-1962.69" wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1648.5-1648.35" + attribute \src "ls180.v:1651.5-1651.35" wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1952.5-1952.58" + attribute \src "ls180.v:1955.5-1955.58" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1953.5-1953.61" + attribute \src "ls180.v:1956.5-1956.61" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1606.11-1606.47" + attribute \src "ls180.v:1609.11-1609.47" wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1612.5-1612.46" + attribute \src "ls180.v:1615.5-1615.46" wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1611.12-1611.54" + attribute \src "ls180.v:1614.12-1614.54" wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1607.12-1607.58" + attribute \src "ls180.v:1610.12-1610.58" wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1619.5-1619.46" + attribute \src "ls180.v:1622.5-1622.46" wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1618.12-1618.54" + attribute \src "ls180.v:1621.12-1621.54" wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1614.12-1614.58" + attribute \src "ls180.v:1617.12-1617.58" wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1626.5-1626.46" + attribute \src "ls180.v:1629.5-1629.46" wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1625.12-1625.54" + attribute \src "ls180.v:1628.12-1628.54" wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1621.12-1621.58" + attribute \src "ls180.v:1624.12-1624.58" wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1633.5-1633.46" + attribute \src "ls180.v:1636.5-1636.46" wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1632.12-1632.54" + attribute \src "ls180.v:1635.12-1635.54" wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1628.12-1628.58" + attribute \src "ls180.v:1631.12-1631.58" wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1635.12-1635.53" + attribute \src "ls180.v:1638.12-1638.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1636.12-1636.53" + attribute \src "ls180.v:1639.12-1639.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1637.12-1637.53" + attribute \src "ls180.v:1640.12-1640.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1638.12-1638.53" + attribute \src "ls180.v:1641.12-1641.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1640.12-1640.51" + attribute \src "ls180.v:1643.12-1643.51" wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1641.12-1641.51" + attribute \src "ls180.v:1644.12-1644.51" wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1642.12-1642.51" + attribute \src "ls180.v:1645.12-1645.51" wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1643.12-1643.51" + attribute \src "ls180.v:1646.12-1646.51" wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1597.5-1597.48" + attribute \src "ls180.v:1600.5-1600.48" wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1598.5-1598.47" + attribute \src "ls180.v:1601.5-1601.47" wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1599.11-1599.61" + attribute \src "ls180.v:1602.11-1602.61" wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1596.5-1596.48" + attribute \src "ls180.v:1599.5-1599.48" wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1595.5-1595.48" + attribute \src "ls180.v:1598.5-1598.48" wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1600.5-1600.50" + attribute \src "ls180.v:1603.5-1603.50" wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1605.11-1605.47" + attribute \src "ls180.v:1608.11-1608.47" wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1639.5-1639.43" + attribute \src "ls180.v:1642.5-1642.43" wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1562.11-1562.48" + attribute \src "ls180.v:1565.11-1565.48" wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1938.11-1938.87" + attribute \src "ls180.v:1941.11-1941.87" wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1939.5-1939.84" + attribute \src "ls180.v:1942.5-1942.84" wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1567.12-1567.55" + attribute \src "ls180.v:1570.12-1570.55" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1563.12-1563.59" + attribute \src "ls180.v:1566.12-1566.59" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1574.12-1574.55" + attribute \src "ls180.v:1577.12-1577.55" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1570.12-1570.59" + attribute \src "ls180.v:1573.12-1573.59" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1581.12-1581.55" + attribute \src "ls180.v:1584.12-1584.55" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1577.12-1577.59" + attribute \src "ls180.v:1580.12-1580.59" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1588.12-1588.55" + attribute \src "ls180.v:1591.12-1591.55" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1584.12-1584.59" + attribute \src "ls180.v:1587.12-1587.59" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1591.12-1591.54" + attribute \src "ls180.v:1594.12-1594.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1930.12-1930.93" + attribute \src "ls180.v:1933.12-1933.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1931.5-1931.88" + attribute \src "ls180.v:1934.5-1934.88" wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1592.12-1592.54" + attribute \src "ls180.v:1595.12-1595.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1932.12-1932.93" + attribute \src "ls180.v:1935.12-1935.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1933.5-1933.88" + attribute \src "ls180.v:1936.5-1936.88" wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1593.12-1593.54" + attribute \src "ls180.v:1596.12-1596.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1934.12-1934.93" + attribute \src "ls180.v:1937.12-1937.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1935.5-1935.88" + attribute \src "ls180.v:1938.5-1938.88" wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1594.12-1594.54" + attribute \src "ls180.v:1597.12-1597.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1936.12-1936.93" + attribute \src "ls180.v:1939.12-1939.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1937.5-1937.88" + attribute \src "ls180.v:1940.5-1940.88" wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1553.5-1553.49" + attribute \src "ls180.v:1556.5-1556.49" wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1560.5-1560.50" + attribute \src "ls180.v:1563.5-1563.50" wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1561.11-1561.64" + attribute \src "ls180.v:1564.11-1564.64" wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1558.5-1558.51" + attribute \src "ls180.v:1561.5-1561.51" wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1557.5-1557.51" + attribute \src "ls180.v:1560.5-1560.51" wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1549.11-1549.47" + attribute \src "ls180.v:1552.11-1552.47" wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1507.11-1507.51" + attribute \src "ls180.v:1510.11-1510.51" wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1650.12-1650.42" + attribute \src "ls180.v:1653.12-1653.42" wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1948.12-1948.65" + attribute \src "ls180.v:1951.12-1951.65" wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1949.5-1949.60" + attribute \src "ls180.v:1952.5-1952.60" wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1651.5-1651.33" + attribute \src "ls180.v:1654.5-1654.33" wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1944.5-1944.56" + attribute \src "ls180.v:1947.5-1947.56" wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1945.5-1945.59" + attribute \src "ls180.v:1948.5-1948.59" wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1652.5-1652.34" + attribute \src "ls180.v:1655.5-1655.34" wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1954.5-1954.57" + attribute \src "ls180.v:1957.5-1957.57" wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1955.5-1955.60" + attribute \src "ls180.v:1958.5-1958.60" wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1653.5-1653.36" + attribute \src "ls180.v:1656.5-1656.36" wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1956.5-1956.59" + attribute \src "ls180.v:1959.5-1959.59" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1957.5-1957.62" + attribute \src "ls180.v:1960.5-1960.62" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1798.11-1798.48" + attribute \src "ls180.v:1801.11-1801.48" wire width 3 $1\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:1796.11-1796.64" + attribute \src "ls180.v:1799.11-1799.64" wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1772.5-1772.40" + attribute \src "ls180.v:1775.5-1775.40" wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1771.12-1771.53" + attribute \src "ls180.v:1774.12-1774.53" wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1770.12-1770.45" + attribute \src "ls180.v:1773.12-1773.45" wire width 64 $1\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:1966.12-1966.75" + attribute \src "ls180.v:1969.12-1969.75" wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:1967.5-1967.70" + attribute \src "ls180.v:1970.5-1970.70" wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1777.5-1777.44" + attribute \src "ls180.v:1780.5-1780.44" wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1776.5-1776.42" + attribute \src "ls180.v:1779.5-1779.42" wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1775.5-1775.47" + attribute \src "ls180.v:1778.5-1778.47" wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1774.5-1774.42" + attribute \src "ls180.v:1777.5-1777.42" wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1773.12-1773.55" + attribute \src "ls180.v:1776.12-1776.55" wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1780.5-1780.40" + attribute \src "ls180.v:1783.5-1783.40" wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1779.5-1779.45" + attribute \src "ls180.v:1782.5-1782.45" wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1784.12-1784.47" + attribute \src "ls180.v:1787.12-1787.47" wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1970.12-1970.87" + attribute \src "ls180.v:1973.12-1973.87" wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1971.5-1971.82" + attribute \src "ls180.v:1974.5-1974.82" wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1763.5-1763.42" + attribute \src "ls180.v:1766.5-1766.42" wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1764.12-1764.61" + attribute \src "ls180.v:1767.12-1767.61" wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1762.5-1762.43" + attribute \src "ls180.v:1765.5-1765.43" wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1761.5-1761.43" + attribute \src "ls180.v:1764.5-1764.43" wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1768.5-1768.44" + attribute \src "ls180.v:1771.5-1771.44" wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1769.12-1769.60" + attribute \src "ls180.v:1772.12-1772.60" wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:1765.5-1765.45" + attribute \src "ls180.v:1768.5-1768.45" wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1825.11-1825.47" + attribute \src "ls180.v:1828.11-1828.47" wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1822.11-1822.45" + attribute \src "ls180.v:1825.11-1825.45" wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1824.11-1824.47" + attribute \src "ls180.v:1827.11-1827.47" wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1826.11-1826.50" + attribute \src "ls180.v:1829.11-1829.50" wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1206.5-1206.35" - wire $1\main_sdphy_clocker_clk0[0:0] attribute \src "ls180.v:1209.5-1209.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1212.5-1212.35" wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1210.5-1210.36" + attribute \src "ls180.v:1213.5-1213.36" wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1208.11-1208.41" + attribute \src "ls180.v:1211.11-1211.41" wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1204.5-1204.33" + attribute \src "ls180.v:1207.5-1207.33" wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1203.11-1203.46" + attribute \src "ls180.v:1206.11-1206.46" wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1312.5-1312.49" + attribute \src "ls180.v:1315.5-1315.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1313.5-1313.48" + attribute \src "ls180.v:1316.5-1316.48" wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1314.11-1314.62" + attribute \src "ls180.v:1317.11-1317.62" wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1310.5-1310.49" + attribute \src "ls180.v:1313.5-1313.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1297.11-1297.54" + attribute \src "ls180.v:1300.11-1300.54" wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1293.5-1293.55" + attribute \src "ls180.v:1296.5-1296.55" wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1294.5-1294.54" + attribute \src "ls180.v:1297.5-1297.54" wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1295.11-1295.68" + attribute \src "ls180.v:1298.11-1298.68" wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1296.11-1296.81" + attribute \src "ls180.v:1299.11-1299.81" wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1299.5-1299.53" + attribute \src "ls180.v:1302.5-1302.53" wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1315.5-1315.38" + attribute \src "ls180.v:1318.5-1318.38" wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1910.5-1910.66" + attribute \src "ls180.v:1913.5-1913.66" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1911.5-1911.69" + attribute \src "ls180.v:1914.5-1914.69" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1285.5-1285.36" + attribute \src "ls180.v:1288.5-1288.36" wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1280.5-1280.53" + attribute \src "ls180.v:1283.5-1283.53" wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1267.11-1267.39" + attribute \src "ls180.v:1270.11-1270.39" wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1906.11-1906.67" + attribute \src "ls180.v:1909.11-1909.67" wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1907.5-1907.64" + attribute \src "ls180.v:1910.5-1910.64" wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1252.5-1252.48" + attribute \src "ls180.v:1255.5-1255.48" wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1253.5-1253.50" + attribute \src "ls180.v:1256.5-1256.50" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1254.5-1254.51" + attribute \src "ls180.v:1257.5-1257.51" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1259.5-1259.37" + attribute \src "ls180.v:1262.5-1262.37" wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1260.11-1260.53" + attribute \src "ls180.v:1263.11-1263.53" wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1258.5-1258.38" + attribute \src "ls180.v:1261.5-1261.38" wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1257.5-1257.38" + attribute \src "ls180.v:1260.5-1260.38" wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1263.5-1263.39" + attribute \src "ls180.v:1266.5-1266.39" wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1264.11-1264.53" + attribute \src "ls180.v:1267.11-1267.53" wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1265.11-1265.55" + attribute \src "ls180.v:1268.11-1268.55" wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1262.5-1262.40" + attribute \src "ls180.v:1265.5-1265.40" wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1261.5-1261.40" + attribute \src "ls180.v:1264.5-1264.40" wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1266.12-1266.48" + attribute \src "ls180.v:1269.12-1269.48" wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1908.12-1908.71" + attribute \src "ls180.v:1911.12-1911.71" wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1909.5-1909.66" + attribute \src "ls180.v:1912.5-1912.66" wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1239.11-1239.39" + attribute \src "ls180.v:1242.11-1242.39" wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1902.11-1902.66" + attribute \src "ls180.v:1905.11-1905.66" wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1903.5-1903.63" + attribute \src "ls180.v:1906.5-1906.63" wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1238.5-1238.32" + attribute \src "ls180.v:1241.5-1241.32" wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1229.5-1229.48" + attribute \src "ls180.v:1232.5-1232.48" wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1230.5-1230.50" + attribute \src "ls180.v:1233.5-1233.50" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1231.5-1231.51" + attribute \src "ls180.v:1234.5-1234.51" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1236.5-1236.37" + attribute \src "ls180.v:1239.5-1239.37" wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1237.11-1237.51" + attribute \src "ls180.v:1240.11-1240.51" wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1235.5-1235.38" + attribute \src "ls180.v:1238.5-1238.38" wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1234.5-1234.38" + attribute \src "ls180.v:1237.5-1237.38" wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1423.11-1423.41" + attribute \src "ls180.v:1426.11-1426.41" wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1922.11-1922.70" + attribute \src "ls180.v:1925.11-1925.70" wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1923.5-1923.66" + attribute \src "ls180.v:1926.5-1926.66" wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1468.5-1468.51" + attribute \src "ls180.v:1471.5-1471.51" wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1469.5-1469.50" + attribute \src "ls180.v:1472.5-1472.50" wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1470.11-1470.64" + attribute \src "ls180.v:1473.11-1473.64" wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1466.5-1466.51" + attribute \src "ls180.v:1469.5-1469.51" wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1453.5-1453.50" + attribute \src "ls180.v:1456.5-1456.50" wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1449.5-1449.57" + attribute \src "ls180.v:1452.5-1452.57" wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1450.5-1450.56" + attribute \src "ls180.v:1453.5-1453.56" wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1451.11-1451.70" + attribute \src "ls180.v:1454.11-1454.70" wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1452.11-1452.83" + attribute \src "ls180.v:1455.11-1455.83" wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1455.5-1455.55" + attribute \src "ls180.v:1458.5-1458.55" wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1471.5-1471.40" + attribute \src "ls180.v:1474.5-1474.40" wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1926.5-1926.69" + attribute \src "ls180.v:1929.5-1929.69" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1927.5-1927.72" + attribute \src "ls180.v:1930.5-1930.72" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1441.5-1441.38" + attribute \src "ls180.v:1444.5-1444.38" wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1436.5-1436.55" + attribute \src "ls180.v:1439.5-1439.55" wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1406.5-1406.49" + attribute \src "ls180.v:1409.5-1409.49" wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1413.5-1413.38" + attribute \src "ls180.v:1416.5-1416.38" wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1414.11-1414.61" + attribute \src "ls180.v:1417.11-1417.61" wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1412.5-1412.39" + attribute \src "ls180.v:1415.5-1415.39" wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1411.5-1411.39" + attribute \src "ls180.v:1414.5-1414.39" wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1418.5-1418.40" + attribute \src "ls180.v:1421.5-1421.40" wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1419.11-1419.54" + attribute \src "ls180.v:1422.11-1422.54" wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1420.11-1420.56" + attribute \src "ls180.v:1423.11-1423.56" wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1416.5-1416.41" + attribute \src "ls180.v:1419.5-1419.41" wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1415.5-1415.41" + attribute \src "ls180.v:1418.5-1418.41" wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1421.5-1421.33" + attribute \src "ls180.v:1424.5-1424.33" wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1422.12-1422.49" + attribute \src "ls180.v:1425.12-1425.49" wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1924.12-1924.73" + attribute \src "ls180.v:1927.12-1927.73" wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1925.5-1925.68" + attribute \src "ls180.v:1928.5-1928.68" wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1331.11-1331.40" + attribute \src "ls180.v:1334.11-1334.40" wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1918.11-1918.61" + attribute \src "ls180.v:1921.11-1921.61" wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1919.5-1919.58" + attribute \src "ls180.v:1922.5-1922.58" wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1390.5-1390.50" + attribute \src "ls180.v:1393.5-1393.50" wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1391.5-1391.49" + attribute \src "ls180.v:1394.5-1394.49" wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1392.11-1392.63" + attribute \src "ls180.v:1395.11-1395.63" wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1388.5-1388.50" + attribute \src "ls180.v:1391.5-1391.50" wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1375.11-1375.55" + attribute \src "ls180.v:1378.11-1378.55" wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1371.5-1371.56" + attribute \src "ls180.v:1374.5-1374.56" wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1372.5-1372.55" + attribute \src "ls180.v:1375.5-1375.55" wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1373.11-1373.69" + attribute \src "ls180.v:1376.11-1376.69" wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1374.11-1374.82" + attribute \src "ls180.v:1377.11-1377.82" wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1377.5-1377.54" + attribute \src "ls180.v:1380.5-1380.54" wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1393.5-1393.39" + attribute \src "ls180.v:1396.5-1396.39" wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1914.5-1914.66" + attribute \src "ls180.v:1917.5-1917.66" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1915.5-1915.69" + attribute \src "ls180.v:1918.5-1918.69" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1363.5-1363.37" + attribute \src "ls180.v:1366.5-1366.37" wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1358.5-1358.54" + attribute \src "ls180.v:1361.5-1361.54" wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1345.5-1345.34" + attribute \src "ls180.v:1348.5-1348.34" wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1320.5-1320.49" + attribute \src "ls180.v:1323.5-1323.49" wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1323.11-1323.58" + attribute \src "ls180.v:1326.11-1326.58" wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1324.5-1324.53" + attribute \src "ls180.v:1327.5-1327.53" wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1327.5-1327.39" + attribute \src "ls180.v:1330.5-1330.39" wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1328.5-1328.38" + attribute \src "ls180.v:1331.5-1331.38" wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1329.11-1329.52" + attribute \src "ls180.v:1332.11-1332.52" wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1326.5-1326.39" + attribute \src "ls180.v:1329.5-1329.39" wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1325.5-1325.39" + attribute \src "ls180.v:1328.5-1328.39" wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1343.5-1343.34" + attribute \src "ls180.v:1346.5-1346.34" wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1330.5-1330.33" + attribute \src "ls180.v:1333.5-1333.33" wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1344.5-1344.34" + attribute \src "ls180.v:1347.5-1347.34" wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1224.11-1224.39" + attribute \src "ls180.v:1227.11-1227.39" wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1898.11-1898.66" + attribute \src "ls180.v:1901.11-1901.66" wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1899.5-1899.63" + attribute \src "ls180.v:1902.5-1902.63" wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1219.5-1219.48" + attribute \src "ls180.v:1222.5-1222.48" wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1220.5-1220.50" + attribute \src "ls180.v:1223.5-1223.50" wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1221.5-1221.51" + attribute \src "ls180.v:1224.5-1224.51" wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1222.11-1222.57" + attribute \src "ls180.v:1225.11-1225.57" wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1223.5-1223.52" + attribute \src "ls180.v:1226.5-1226.52" wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1473.5-1473.35" + attribute \src "ls180.v:1476.5-1476.35" wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1476.11-1476.42" + attribute \src "ls180.v:1479.11-1479.42" wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:418.5-418.33" + attribute \src "ls180.v:421.5-421.33" wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:417.12-417.46" + attribute \src "ls180.v:420.12-420.46" wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:420.5-420.34" + attribute \src "ls180.v:423.5-423.34" wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:419.11-419.45" + attribute \src "ls180.v:422.11-422.45" wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:516.5-516.50" + attribute \src "ls180.v:519.5-519.50" wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:538.11-538.70" + attribute \src "ls180.v:541.11-541.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:535.11-535.68" + attribute \src "ls180.v:538.11-538.68" wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:537.11-537.70" + attribute \src "ls180.v:540.11-540.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:539.11-539.73" + attribute \src "ls180.v:542.11-542.73" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:562.5-562.59" + attribute \src "ls180.v:565.5-565.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:563.5-563.58" + attribute \src "ls180.v:566.5-566.58" wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:565.12-565.74" + attribute \src "ls180.v:568.12-568.74" wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:564.5-564.64" + attribute \src "ls180.v:567.5-567.64" wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:560.5-560.59" + attribute \src "ls180.v:563.5-563.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:508.12-508.57" + attribute \src "ls180.v:511.12-511.57" wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:510.5-510.51" + attribute \src "ls180.v:513.5-513.51" wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:513.5-513.54" + attribute \src "ls180.v:516.5-516.54" wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:514.5-514.55" + attribute \src "ls180.v:517.5-517.55" wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:515.5-515.56" + attribute \src "ls180.v:518.5-518.56" wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:511.5-511.51" + attribute \src "ls180.v:514.5-514.51" wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:512.5-512.50" + attribute \src "ls180.v:515.5-515.50" wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:507.5-507.45" + attribute \src "ls180.v:510.5-510.45" wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:506.5-506.45" + attribute \src "ls180.v:509.5-509.45" wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:505.5-505.47" + attribute \src "ls180.v:508.5-508.47" wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:503.5-503.51" + attribute \src "ls180.v:506.5-506.51" wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:502.5-502.51" + attribute \src "ls180.v:505.5-505.51" wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:566.12-566.47" + attribute \src "ls180.v:569.12-569.47" wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:570.5-570.45" + attribute \src "ls180.v:573.5-573.45" wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:571.5-571.54" + attribute \src "ls180.v:574.5-574.54" wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:569.5-569.44" + attribute \src "ls180.v:572.5-572.44" wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:567.5-567.46" + attribute \src "ls180.v:570.5-570.46" wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:574.11-574.55" + attribute \src "ls180.v:577.11-577.55" wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:573.32-573.76" + attribute \src "ls180.v:576.32-576.76" wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:598.5-598.50" + attribute \src "ls180.v:601.5-601.50" wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:620.11-620.70" + attribute \src "ls180.v:623.11-623.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:617.11-617.68" + attribute \src "ls180.v:620.11-620.68" wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:619.11-619.70" + attribute \src "ls180.v:622.11-622.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:621.11-621.73" + attribute \src "ls180.v:624.11-624.73" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:644.5-644.59" + attribute \src "ls180.v:647.5-647.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:645.5-645.58" + attribute \src "ls180.v:648.5-648.58" wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:647.12-647.74" + attribute \src "ls180.v:650.12-650.74" wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:646.5-646.64" + attribute \src "ls180.v:649.5-649.64" wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:642.5-642.59" + attribute \src "ls180.v:645.5-645.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:590.12-590.57" + attribute \src "ls180.v:593.12-593.57" wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:592.5-592.51" + attribute \src "ls180.v:595.5-595.51" wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:595.5-595.54" + attribute \src "ls180.v:598.5-598.54" wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:596.5-596.55" + attribute \src "ls180.v:599.5-599.55" wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:597.5-597.56" + attribute \src "ls180.v:600.5-600.56" wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:593.5-593.51" + attribute \src "ls180.v:596.5-596.51" wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:594.5-594.50" + attribute \src "ls180.v:597.5-597.50" wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:589.5-589.45" + attribute \src "ls180.v:592.5-592.45" wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:588.5-588.45" + attribute \src "ls180.v:591.5-591.45" wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:587.5-587.47" + attribute \src "ls180.v:590.5-590.47" wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:585.5-585.51" + attribute \src "ls180.v:588.5-588.51" wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:584.5-584.51" + attribute \src "ls180.v:587.5-587.51" wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:648.12-648.47" + attribute \src "ls180.v:651.12-651.47" wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:652.5-652.45" + attribute \src "ls180.v:655.5-655.45" wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:653.5-653.54" + attribute \src "ls180.v:656.5-656.54" wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:651.5-651.44" + attribute \src "ls180.v:654.5-654.44" wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:649.5-649.46" + attribute \src "ls180.v:652.5-652.46" wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:656.11-656.55" + attribute \src "ls180.v:659.11-659.55" wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:655.32-655.76" + attribute \src "ls180.v:658.32-658.76" wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:680.5-680.50" + attribute \src "ls180.v:683.5-683.50" wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:702.11-702.70" + attribute \src "ls180.v:705.11-705.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:699.11-699.68" + attribute \src "ls180.v:702.11-702.68" wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:701.11-701.70" + attribute \src "ls180.v:704.11-704.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:703.11-703.73" + attribute \src "ls180.v:706.11-706.73" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:726.5-726.59" + attribute \src "ls180.v:729.5-729.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:727.5-727.58" + attribute \src "ls180.v:730.5-730.58" wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:729.12-729.74" + attribute \src "ls180.v:732.12-732.74" wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:728.5-728.64" + attribute \src "ls180.v:731.5-731.64" wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:724.5-724.59" + attribute \src "ls180.v:727.5-727.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:672.12-672.57" + attribute \src "ls180.v:675.12-675.57" wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:674.5-674.51" + attribute \src "ls180.v:677.5-677.51" wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:677.5-677.54" + attribute \src "ls180.v:680.5-680.54" wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:678.5-678.55" + attribute \src "ls180.v:681.5-681.55" wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:679.5-679.56" + attribute \src "ls180.v:682.5-682.56" wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:675.5-675.51" + attribute \src "ls180.v:678.5-678.51" wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:676.5-676.50" + attribute \src "ls180.v:679.5-679.50" wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:671.5-671.45" + attribute \src "ls180.v:674.5-674.45" wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:670.5-670.45" + attribute \src "ls180.v:673.5-673.45" wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:669.5-669.47" + attribute \src "ls180.v:672.5-672.47" wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:667.5-667.51" + attribute \src "ls180.v:670.5-670.51" wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:666.5-666.51" + attribute \src "ls180.v:669.5-669.51" wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:730.12-730.47" + attribute \src "ls180.v:733.12-733.47" wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:734.5-734.45" + attribute \src "ls180.v:737.5-737.45" wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:735.5-735.54" + attribute \src "ls180.v:738.5-738.54" wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:733.5-733.44" + attribute \src "ls180.v:736.5-736.44" wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:731.5-731.46" + attribute \src "ls180.v:734.5-734.46" wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:738.11-738.55" + attribute \src "ls180.v:741.11-741.55" wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:737.32-737.76" + attribute \src "ls180.v:740.32-740.76" wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:762.5-762.50" + attribute \src "ls180.v:765.5-765.50" wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:784.11-784.70" + attribute \src "ls180.v:787.11-787.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:781.11-781.68" + attribute \src "ls180.v:784.11-784.68" wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:783.11-783.70" + attribute \src "ls180.v:786.11-786.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:785.11-785.73" + attribute \src "ls180.v:788.11-788.73" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:808.5-808.59" + attribute \src "ls180.v:811.5-811.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:809.5-809.58" + attribute \src "ls180.v:812.5-812.58" wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:811.12-811.74" + attribute \src "ls180.v:814.12-814.74" wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:810.5-810.64" + attribute \src "ls180.v:813.5-813.64" wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:806.5-806.59" + attribute \src "ls180.v:809.5-809.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:754.12-754.57" + attribute \src "ls180.v:757.12-757.57" wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:756.5-756.51" + attribute \src "ls180.v:759.5-759.51" wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:759.5-759.54" + attribute \src "ls180.v:762.5-762.54" wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:760.5-760.55" + attribute \src "ls180.v:763.5-763.55" wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:761.5-761.56" + attribute \src "ls180.v:764.5-764.56" wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:757.5-757.51" + attribute \src "ls180.v:760.5-760.51" wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:758.5-758.50" + attribute \src "ls180.v:761.5-761.50" wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:753.5-753.45" + attribute \src "ls180.v:756.5-756.45" wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:752.5-752.45" + attribute \src "ls180.v:755.5-755.45" wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:751.5-751.47" + attribute \src "ls180.v:754.5-754.47" wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:749.5-749.51" + attribute \src "ls180.v:752.5-752.51" wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:748.5-748.51" + attribute \src "ls180.v:751.5-751.51" wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:812.12-812.47" + attribute \src "ls180.v:815.12-815.47" wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:816.5-816.45" + attribute \src "ls180.v:819.5-819.45" wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:817.5-817.54" + attribute \src "ls180.v:820.5-820.54" wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:815.5-815.44" + attribute \src "ls180.v:818.5-818.44" wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:813.5-813.46" + attribute \src "ls180.v:816.5-816.46" wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:820.11-820.55" + attribute \src "ls180.v:823.11-823.55" wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:819.32-819.76" + attribute \src "ls180.v:822.32-822.76" wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:835.5-835.49" + attribute \src "ls180.v:838.5-838.49" wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:836.5-836.49" + attribute \src "ls180.v:839.5-839.49" wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:837.5-837.48" + attribute \src "ls180.v:840.5-840.48" wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:843.11-843.45" + attribute \src "ls180.v:846.11-846.45" wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:841.11-841.46" + attribute \src "ls180.v:844.11-844.46" wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:853.5-853.49" + attribute \src "ls180.v:856.5-856.49" wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:854.5-854.49" + attribute \src "ls180.v:857.5-857.49" wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:855.5-855.48" + attribute \src "ls180.v:858.5-858.48" wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:850.5-850.43" + attribute \src "ls180.v:853.5-853.43" wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:861.11-861.45" + attribute \src "ls180.v:864.11-864.45" wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:859.11-859.46" + attribute \src "ls180.v:862.11-862.46" wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:848.5-848.48" + attribute \src "ls180.v:851.5-851.48" wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:845.5-845.44" + attribute \src "ls180.v:848.5-848.44" wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:846.5-846.45" + attribute \src "ls180.v:849.5-849.45" wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:474.5-474.31" + attribute \src "ls180.v:477.5-477.31" wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:475.12-475.44" + attribute \src "ls180.v:478.12-478.44" wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:476.11-476.43" + attribute \src "ls180.v:479.11-479.43" wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:477.5-477.38" + attribute \src "ls180.v:480.5-480.38" wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:478.5-478.38" + attribute \src "ls180.v:481.5-481.38" wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:479.5-479.37" + attribute \src "ls180.v:482.5-482.37" wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:473.5-473.32" + attribute \src "ls180.v:476.5-476.32" wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:472.5-472.32" + attribute \src "ls180.v:475.5-475.32" wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:412.5-412.33" + attribute \src "ls180.v:415.5-415.33" wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:411.11-411.44" + attribute \src "ls180.v:414.11-414.44" wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:456.12-456.45" + attribute \src "ls180.v:459.12-459.45" wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:457.11-457.40" + attribute \src "ls180.v:460.11-460.40" wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:458.5-458.35" + attribute \src "ls180.v:461.5-461.35" wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:459.5-459.34" + attribute \src "ls180.v:462.5-462.34" wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:460.5-460.35" + attribute \src "ls180.v:463.5-463.35" wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:469.5-469.39" + attribute \src "ls180.v:472.5-472.39" wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:461.5-461.34" + attribute \src "ls180.v:464.5-464.34" wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:467.5-467.39" + attribute \src "ls180.v:470.5-470.39" wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:880.5-880.26" - wire $1\main_sdram_en0[0:0] attribute \src "ls180.v:883.5-883.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:886.5-886.26" wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:453.12-453.46" + attribute \src "ls180.v:456.12-456.46" wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:454.11-454.47" + attribute \src "ls180.v:457.11-457.47" wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:359.5-359.36" + attribute \src "ls180.v:362.5-362.36" wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:360.5-360.35" + attribute \src "ls180.v:363.5-363.35" wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:361.5-361.36" + attribute \src "ls180.v:364.5-364.36" wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:371.12-371.45" + attribute \src "ls180.v:374.12-374.45" wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:372.5-372.43" + attribute \src "ls180.v:375.5-375.43" wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:362.5-362.35" + attribute \src "ls180.v:365.5-365.35" wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:398.5-398.38" + attribute \src "ls180.v:401.5-401.38" wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:389.12-389.48" + attribute \src "ls180.v:392.12-392.48" wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:390.11-390.43" + attribute \src "ls180.v:393.11-393.43" wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:391.5-391.38" + attribute \src "ls180.v:394.5-394.38" wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:395.5-395.36" + attribute \src "ls180.v:398.5-398.36" wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:392.5-392.37" + attribute \src "ls180.v:395.5-395.37" wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:396.5-396.36" + attribute \src "ls180.v:399.5-399.36" wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:393.5-393.38" + attribute \src "ls180.v:396.5-396.38" wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:402.5-402.42" + attribute \src "ls180.v:405.5-405.42" wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:397.5-397.40" + attribute \src "ls180.v:400.5-400.40" wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:394.5-394.37" + attribute \src "ls180.v:397.5-397.37" wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:399.12-399.47" + attribute \src "ls180.v:402.12-402.47" wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:400.5-400.42" + attribute \src "ls180.v:403.5-403.42" wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:401.11-401.50" + attribute \src "ls180.v:404.11-404.50" wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:490.5-490.38" + attribute \src "ls180.v:493.5-493.38" wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:489.5-489.38" + attribute \src "ls180.v:492.5-492.38" wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:410.5-410.25" + attribute \src "ls180.v:413.5-413.25" wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:496.5-496.38" + attribute \src "ls180.v:499.5-499.38" wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:495.11-495.46" + attribute \src "ls180.v:498.11-498.46" wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:494.5-494.38" + attribute \src "ls180.v:497.5-497.38" wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:491.5-491.39" + attribute \src "ls180.v:494.5-494.39" wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:387.12-387.46" + attribute \src "ls180.v:390.12-390.46" wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:388.5-388.44" + attribute \src "ls180.v:391.5-391.44" wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:423.12-423.37" + attribute \src "ls180.v:426.12-426.37" wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:865.11-865.40" + attribute \src "ls180.v:868.11-868.40" wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:409.11-409.36" + attribute \src "ls180.v:412.11-412.36" wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:874.5-874.36" + attribute \src "ls180.v:877.5-877.36" wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:873.32-873.63" + attribute \src "ls180.v:876.32-876.63" wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:882.11-882.34" - wire width 5 $1\main_sdram_time0[4:0] attribute \src "ls180.v:885.11-885.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:888.11-888.34" wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:487.11-487.44" + attribute \src "ls180.v:490.11-490.44" wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:877.11-877.42" + attribute \src "ls180.v:880.11-880.42" wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:876.32-876.63" + attribute \src "ls180.v:879.32-879.63" wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:422.5-422.32" + attribute \src "ls180.v:425.5-425.32" wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:421.12-421.45" + attribute \src "ls180.v:424.12-424.45" wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:914.5-914.54" + attribute \src "ls180.v:917.5-917.54" wire $1\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:920.5-920.38" + attribute \src "ls180.v:923.5-923.38" wire $1\main_socbushandler_counter[0:0] - attribute \src "ls180.v:1849.5-1849.60" + attribute \src "ls180.v:1852.5-1852.60" wire $1\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1850.5-1850.63" + attribute \src "ls180.v:1853.5-1853.63" wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:922.12-922.44" + attribute \src "ls180.v:925.12-925.44" wire width 64 $1\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:919.5-919.35" + attribute \src "ls180.v:922.5-922.35" wire $1\main_socbushandler_skip[0:0] - attribute \src "ls180.v:1108.12-1108.44" + attribute \src "ls180.v:1111.12-1111.44" wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1109.5-1109.31" + attribute \src "ls180.v:1112.5-1112.31" wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1113.11-1113.42" + attribute \src "ls180.v:1116.11-1116.42" wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1114.5-1114.31" + attribute \src "ls180.v:1117.5-1117.31" wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1170.5-1170.30" + attribute \src "ls180.v:1173.5-1173.30" wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1169.12-1169.45" + attribute \src "ls180.v:1172.12-1172.45" wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1118.5-1118.36" + attribute \src "ls180.v:1121.5-1121.36" wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1119.5-1119.31" + attribute \src "ls180.v:1122.5-1122.31" wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1120.5-1120.36" + attribute \src "ls180.v:1123.5-1123.36" wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1121.5-1121.31" + attribute \src "ls180.v:1124.5-1124.31" wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1122.5-1122.39" + attribute \src "ls180.v:1125.5-1125.39" wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1123.5-1123.38" + attribute \src "ls180.v:1126.5-1126.38" wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1124.11-1124.40" + attribute \src "ls180.v:1127.11-1127.40" wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1890.11-1890.62" + attribute \src "ls180.v:1893.11-1893.62" wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1891.5-1891.59" + attribute \src "ls180.v:1894.5-1894.59" wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1125.5-1125.39" + attribute \src "ls180.v:1128.5-1128.39" wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1126.5-1126.39" + attribute \src "ls180.v:1129.5-1129.39" wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:1099.5-1099.32" + attribute \src "ls180.v:1102.5-1102.32" wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1127.12-1127.48" + attribute \src "ls180.v:1130.12-1130.48" wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1130.11-1130.44" + attribute \src "ls180.v:1133.11-1133.44" wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1131.11-1131.43" + attribute \src "ls180.v:1134.11-1134.43" wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1132.11-1132.44" + attribute \src "ls180.v:1135.11-1135.44" wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:1100.5-1100.31" + attribute \src "ls180.v:1103.5-1103.31" wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:1102.11-1102.38" + attribute \src "ls180.v:1105.11-1105.38" wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1106.5-1106.33" + attribute \src "ls180.v:1109.5-1109.33" wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1163.12-1163.47" + attribute \src "ls180.v:1166.12-1166.47" wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1158.5-1158.37" + attribute \src "ls180.v:1161.5-1161.37" wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1145.5-1145.37" + attribute \src "ls180.v:1148.5-1148.37" wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1144.12-1144.50" + attribute \src "ls180.v:1147.12-1147.50" wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1160.11-1160.38" + attribute \src "ls180.v:1163.11-1163.38" wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1894.11-1894.60" + attribute \src "ls180.v:1897.11-1897.60" wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1895.5-1895.57" + attribute \src "ls180.v:1898.5-1898.57" wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1159.5-1159.36" + attribute \src "ls180.v:1162.5-1162.36" wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1155.5-1155.32" + attribute \src "ls180.v:1158.5-1158.32" wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1154.5-1154.37" + attribute \src "ls180.v:1157.5-1157.37" wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1135.5-1135.32" + attribute \src "ls180.v:1138.5-1138.32" wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1136.5-1136.30" + attribute \src "ls180.v:1139.5-1139.30" wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1157.5-1157.38" + attribute \src "ls180.v:1160.5-1160.38" wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1156.5-1156.43" + attribute \src "ls180.v:1159.5-1159.43" wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1138.11-1138.37" + attribute \src "ls180.v:1141.11-1141.37" wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1168.11-1168.42" + attribute \src "ls180.v:1171.11-1171.42" wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1162.5-1162.37" + attribute \src "ls180.v:1165.5-1165.37" wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1166.11-1166.42" + attribute \src "ls180.v:1169.11-1169.42" wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1161.5-1161.37" + attribute \src "ls180.v:1164.5-1164.37" wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1150.5-1150.34" + attribute \src "ls180.v:1153.5-1153.34" wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1167.11-1167.41" + attribute \src "ls180.v:1170.11-1170.41" wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1149.11-1149.45" + attribute \src "ls180.v:1152.11-1152.45" wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1142.5-1142.33" + attribute \src "ls180.v:1145.5-1145.33" wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:259.11-259.31" + attribute \src "ls180.v:262.11-262.31" wire width 8 $1\main_sram0_we[7:0] - attribute \src "ls180.v:274.11-274.31" + attribute \src "ls180.v:277.11-277.31" wire width 8 $1\main_sram1_we[7:0] - attribute \src "ls180.v:289.11-289.31" + attribute \src "ls180.v:292.11-292.31" wire width 8 $1\main_sram2_we[7:0] - attribute \src "ls180.v:304.11-304.31" + attribute \src "ls180.v:307.11-307.31" wire width 8 $1\main_sram3_we[7:0] - attribute \src "ls180.v:990.11-990.50" + attribute \src "ls180.v:993.11-993.50" wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:992.5-992.37" + attribute \src "ls180.v:995.5-995.37" wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:986.11-986.49" + attribute \src "ls180.v:989.11-989.49" wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:991.11-991.48" + attribute \src "ls180.v:994.11-994.48" wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:958.12-958.54" + attribute \src "ls180.v:961.12-961.54" wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:948.12-948.54" + attribute \src "ls180.v:951.12-951.54" wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:941.5-941.28" + attribute \src "ls180.v:944.5-944.28" wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:962.11-962.43" + attribute \src "ls180.v:965.11-965.43" wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:963.5-963.33" + attribute \src "ls180.v:966.5-966.33" wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:960.5-960.30" + attribute \src "ls180.v:963.5-963.30" wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:961.11-961.38" + attribute \src "ls180.v:964.11-964.38" wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:943.5-943.36" + attribute \src "ls180.v:946.5-946.36" wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:956.11-956.51" + attribute \src "ls180.v:959.11-959.51" wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:952.5-952.38" + attribute \src "ls180.v:955.5-955.38" wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:940.12-940.47" + attribute \src "ls180.v:943.12-943.47" wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:950.11-950.43" + attribute \src "ls180.v:953.11-953.43" wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:951.5-951.33" + attribute \src "ls180.v:954.5-954.33" wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:949.11-949.38" + attribute \src "ls180.v:952.11-952.38" wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:957.5-957.39" + attribute \src "ls180.v:960.5-960.39" wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:947.5-947.39" + attribute \src "ls180.v:950.5-950.39" wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:981.5-981.30" + attribute \src "ls180.v:984.5-984.30" wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:1065.11-1065.43" + attribute \src "ls180.v:1068.11-1068.43" wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:1062.11-1062.42" + attribute \src "ls180.v:1065.11-1065.42" wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:1064.11-1064.43" + attribute \src "ls180.v:1067.11-1067.43" wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:1055.5-1055.38" + attribute \src "ls180.v:1058.5-1058.38" wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1066.11-1066.46" + attribute \src "ls180.v:1069.11-1069.46" wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:982.5-982.36" + attribute \src "ls180.v:985.5-985.36" wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:979.5-979.32" + attribute \src "ls180.v:982.5-982.32" wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:976.5-976.30" + attribute \src "ls180.v:979.5-979.30" wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:1028.11-1028.43" + attribute \src "ls180.v:1031.11-1031.43" wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:1025.11-1025.42" + attribute \src "ls180.v:1028.11-1028.42" wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:1027.11-1027.43" + attribute \src "ls180.v:1030.11-1030.43" wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:1018.5-1018.38" + attribute \src "ls180.v:1021.5-1021.38" wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:1029.11-1029.46" + attribute \src "ls180.v:1032.11-1032.46" wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:977.5-977.36" + attribute \src "ls180.v:980.5-980.36" wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:974.5-974.32" + attribute \src "ls180.v:977.5-977.32" wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:906.5-906.29" + attribute \src "ls180.v:909.5-909.29" wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:900.12-900.37" + attribute \src "ls180.v:903.12-903.37" wire width 30 $1\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:904.5-904.29" + attribute \src "ls180.v:907.5-907.29" wire $1\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:901.12-901.39" + attribute \src "ls180.v:904.12-904.39" wire width 32 $1\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:903.11-903.35" + attribute \src "ls180.v:906.11-906.35" wire width 4 $1\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:905.5-905.29" + attribute \src "ls180.v:908.5-908.29" wire $1\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:907.5-907.28" + attribute \src "ls180.v:910.5-910.28" wire $1\main_wb_sdram_we[0:0] - attribute \src "ls180.v:936.5-936.31" + attribute \src "ls180.v:939.5-939.31" wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2932.56-2932.86" - wire $add$ls180.v:2932$58_Y - attribute \src "ls180.v:2992.56-2992.86" - wire $add$ls180.v:2992$69_Y - attribute \src "ls180.v:3052.59-3052.92" - wire $add$ls180.v:3052$80_Y - attribute \src "ls180.v:4245.54-4245.83" - wire $add$ls180.v:4245$685_Y - attribute \src "ls180.v:4345.36-4345.89" - wire width 5 $add$ls180.v:4345$731_Y - attribute \src "ls180.v:4375.36-4375.89" - wire width 5 $add$ls180.v:4375$742_Y - attribute \src "ls180.v:4441.54-4441.83" - wire width 3 $add$ls180.v:4441$757_Y - attribute \src "ls180.v:4500.52-4500.79" - wire width 3 $add$ls180.v:4500$765_Y - attribute \src "ls180.v:4604.58-4604.86" - wire width 8 $add$ls180.v:4604$793_Y - attribute \src "ls180.v:4661.58-4661.86" - wire width 8 $add$ls180.v:4661$796_Y - attribute \src "ls180.v:4678.58-4678.86" - wire width 8 $add$ls180.v:4678$798_Y - attribute \src "ls180.v:4771.59-4771.87" - wire width 8 $add$ls180.v:4771$815_Y - attribute \src "ls180.v:4796.59-4796.87" - wire width 8 $add$ls180.v:4796$818_Y - attribute \src "ls180.v:4918.53-4918.82" - wire width 8 $add$ls180.v:4918$835_Y - attribute \src "ls180.v:5029.65-5029.114" - wire width 10 $add$ls180.v:5029$849_Y - attribute \src "ls180.v:5034.62-5034.91" - wire width 10 $add$ls180.v:5034$852_Y - attribute \src "ls180.v:5060.61-5060.90" - wire width 10 $add$ls180.v:5060$855_Y - attribute \src "ls180.v:5264.80-5264.117" - wire width 3 $add$ls180.v:5264$1040_Y - attribute \src "ls180.v:5458.54-5458.82" - wire width 3 $add$ls180.v:5458$1115_Y - attribute \src "ls180.v:5510.55-5510.84" - wire width 32 $add$ls180.v:5510$1125_Y - attribute \src "ls180.v:5536.57-5536.86" - wire width 32 $add$ls180.v:5536$1133_Y - attribute \src "ls180.v:5657.51-5657.134" - wire width 32 $add$ls180.v:5657$1149_Y - attribute \src "ls180.v:5660.77-5660.125" - wire width 32 $add$ls180.v:5660$1151_Y - attribute \src "ls180.v:5753.50-5753.105" - wire width 32 $add$ls180.v:5753$1160_Y - attribute \src "ls180.v:5755.77-5755.111" - wire width 32 $add$ls180.v:5755$1161_Y - attribute \src "ls180.v:7762.36-7762.70" - wire width 32 $add$ls180.v:7762$2602_Y - attribute \src "ls180.v:7863.37-7863.72" - wire width 4 $add$ls180.v:7863$2635_Y - attribute \src "ls180.v:7880.60-7880.119" - wire width 3 $add$ls180.v:7880$2639_Y + attribute \src "ls180.v:2935.56-2935.86" + wire $add$ls180.v:2935$58_Y + attribute \src "ls180.v:2995.56-2995.86" + wire $add$ls180.v:2995$69_Y + attribute \src "ls180.v:3055.59-3055.92" + wire $add$ls180.v:3055$80_Y + attribute \src "ls180.v:4248.54-4248.83" + wire $add$ls180.v:4248$685_Y + attribute \src "ls180.v:4348.36-4348.89" + wire width 5 $add$ls180.v:4348$731_Y + attribute \src "ls180.v:4378.36-4378.89" + wire width 5 $add$ls180.v:4378$742_Y + attribute \src "ls180.v:4444.54-4444.83" + wire width 3 $add$ls180.v:4444$757_Y + attribute \src "ls180.v:4503.52-4503.79" + wire width 3 $add$ls180.v:4503$765_Y + attribute \src "ls180.v:4607.58-4607.86" + wire width 8 $add$ls180.v:4607$793_Y + attribute \src "ls180.v:4664.58-4664.86" + wire width 8 $add$ls180.v:4664$796_Y + attribute \src "ls180.v:4681.58-4681.86" + wire width 8 $add$ls180.v:4681$798_Y + attribute \src "ls180.v:4774.59-4774.87" + wire width 8 $add$ls180.v:4774$815_Y + attribute \src "ls180.v:4799.59-4799.87" + wire width 8 $add$ls180.v:4799$818_Y + attribute \src "ls180.v:4921.53-4921.82" + wire width 8 $add$ls180.v:4921$835_Y + attribute \src "ls180.v:5032.65-5032.114" + wire width 10 $add$ls180.v:5032$849_Y + attribute \src "ls180.v:5037.62-5037.91" + wire width 10 $add$ls180.v:5037$852_Y + attribute \src "ls180.v:5063.61-5063.90" + wire width 10 $add$ls180.v:5063$855_Y + attribute \src "ls180.v:5267.80-5267.117" + wire width 3 $add$ls180.v:5267$1040_Y + attribute \src "ls180.v:5461.54-5461.82" + wire width 3 $add$ls180.v:5461$1115_Y + attribute \src "ls180.v:5513.55-5513.84" + wire width 32 $add$ls180.v:5513$1125_Y + attribute \src "ls180.v:5539.57-5539.86" + wire width 32 $add$ls180.v:5539$1133_Y + attribute \src "ls180.v:5660.51-5660.134" + wire width 32 $add$ls180.v:5660$1149_Y + attribute \src "ls180.v:5663.77-5663.125" + wire width 32 $add$ls180.v:5663$1151_Y + attribute \src "ls180.v:5756.50-5756.105" + wire width 32 $add$ls180.v:5756$1160_Y + attribute \src "ls180.v:5758.77-5758.111" + wire width 32 $add$ls180.v:5758$1161_Y + attribute \src "ls180.v:7765.36-7765.70" + wire width 32 $add$ls180.v:7765$2602_Y + attribute \src "ls180.v:7866.37-7866.72" + wire width 4 $add$ls180.v:7866$2635_Y attribute \src "ls180.v:7883.60-7883.119" - wire width 3 $add$ls180.v:7883$2640_Y - attribute \src "ls180.v:7887.59-7887.116" - wire width 4 $add$ls180.v:7887$2645_Y - attribute \src "ls180.v:7926.60-7926.119" - wire width 3 $add$ls180.v:7926$2655_Y + wire width 3 $add$ls180.v:7883$2639_Y + attribute \src "ls180.v:7886.60-7886.119" + wire width 3 $add$ls180.v:7886$2640_Y + attribute \src "ls180.v:7890.59-7890.116" + wire width 4 $add$ls180.v:7890$2645_Y attribute \src "ls180.v:7929.60-7929.119" - wire width 3 $add$ls180.v:7929$2656_Y - attribute \src "ls180.v:7933.59-7933.116" - wire width 4 $add$ls180.v:7933$2661_Y - attribute \src "ls180.v:7972.60-7972.119" - wire width 3 $add$ls180.v:7972$2671_Y + wire width 3 $add$ls180.v:7929$2655_Y + attribute \src "ls180.v:7932.60-7932.119" + wire width 3 $add$ls180.v:7932$2656_Y + attribute \src "ls180.v:7936.59-7936.116" + wire width 4 $add$ls180.v:7936$2661_Y attribute \src "ls180.v:7975.60-7975.119" - wire width 3 $add$ls180.v:7975$2672_Y - attribute \src "ls180.v:7979.59-7979.116" - wire width 4 $add$ls180.v:7979$2677_Y - attribute \src "ls180.v:8018.60-8018.119" - wire width 3 $add$ls180.v:8018$2687_Y + wire width 3 $add$ls180.v:7975$2671_Y + attribute \src "ls180.v:7978.60-7978.119" + wire width 3 $add$ls180.v:7978$2672_Y + attribute \src "ls180.v:7982.59-7982.116" + wire width 4 $add$ls180.v:7982$2677_Y attribute \src "ls180.v:8021.60-8021.119" - wire width 3 $add$ls180.v:8021$2688_Y - attribute \src "ls180.v:8025.59-8025.116" - wire width 4 $add$ls180.v:8025$2693_Y - attribute \src "ls180.v:8255.34-8255.66" - wire width 4 $add$ls180.v:8255$2747_Y - attribute \src "ls180.v:8271.73-8271.131" - wire width 33 $add$ls180.v:8271$2750_Y - attribute \src "ls180.v:8284.34-8284.66" - wire width 4 $add$ls180.v:8284$2754_Y - attribute \src "ls180.v:8303.73-8303.131" - wire width 33 $add$ls180.v:8303$2757_Y - attribute \src "ls180.v:8329.33-8329.65" - wire width 4 $add$ls180.v:8329$2765_Y + wire width 3 $add$ls180.v:8021$2687_Y + attribute \src "ls180.v:8024.60-8024.119" + wire width 3 $add$ls180.v:8024$2688_Y + attribute \src "ls180.v:8028.59-8028.116" + wire width 4 $add$ls180.v:8028$2693_Y + attribute \src "ls180.v:8258.34-8258.66" + wire width 4 $add$ls180.v:8258$2747_Y + attribute \src "ls180.v:8274.73-8274.131" + wire width 33 $add$ls180.v:8274$2750_Y + attribute \src "ls180.v:8287.34-8287.66" + wire width 4 $add$ls180.v:8287$2754_Y + attribute \src "ls180.v:8306.73-8306.131" + wire width 33 $add$ls180.v:8306$2757_Y attribute \src "ls180.v:8332.33-8332.65" - wire width 4 $add$ls180.v:8332$2766_Y - attribute \src "ls180.v:8336.33-8336.64" - wire width 5 $add$ls180.v:8336$2771_Y - attribute \src "ls180.v:8351.33-8351.65" - wire width 4 $add$ls180.v:8351$2776_Y + wire width 4 $add$ls180.v:8332$2765_Y + attribute \src "ls180.v:8335.33-8335.65" + wire width 4 $add$ls180.v:8335$2766_Y + attribute \src "ls180.v:8339.33-8339.64" + wire width 5 $add$ls180.v:8339$2771_Y attribute \src "ls180.v:8354.33-8354.65" - wire width 4 $add$ls180.v:8354$2777_Y - attribute \src "ls180.v:8358.33-8358.64" - wire width 5 $add$ls180.v:8358$2782_Y - attribute \src "ls180.v:8379.35-8379.70" - wire width 16 $add$ls180.v:8379$2784_Y - attribute \src "ls180.v:8414.34-8414.68" - wire width 16 $add$ls180.v:8414$2789_Y - attribute \src "ls180.v:8450.25-8450.49" - wire width 32 $add$ls180.v:8450$2794_Y - attribute \src "ls180.v:8464.25-8464.49" - wire width 32 $add$ls180.v:8464$2798_Y - attribute \src "ls180.v:8478.31-8478.61" - wire width 9 $add$ls180.v:8478$2803_Y - attribute \src "ls180.v:8501.45-8501.88" - wire width 3 $add$ls180.v:8501$2807_Y - attribute \src "ls180.v:8547.71-8547.114" - wire width 4 $add$ls180.v:8547$2813_Y - attribute \src "ls180.v:8582.46-8582.90" - wire width 3 $add$ls180.v:8582$2819_Y - attribute \src "ls180.v:8628.72-8628.116" - wire width 4 $add$ls180.v:8628$2825_Y - attribute \src "ls180.v:8661.47-8661.92" - wire $add$ls180.v:8661$2831_Y - attribute \src "ls180.v:8689.73-8689.118" - wire width 2 $add$ls180.v:8689$2837_Y - attribute \src "ls180.v:8801.39-8801.75" - wire width 4 $add$ls180.v:8801$2850_Y - attribute \src "ls180.v:8862.37-8862.73" - wire width 5 $add$ls180.v:8862$2854_Y + wire width 4 $add$ls180.v:8354$2776_Y + attribute \src "ls180.v:8357.33-8357.65" + wire width 4 $add$ls180.v:8357$2777_Y + attribute \src "ls180.v:8361.33-8361.64" + wire width 5 $add$ls180.v:8361$2782_Y + attribute \src "ls180.v:8382.35-8382.70" + wire width 16 $add$ls180.v:8382$2784_Y + attribute \src "ls180.v:8417.34-8417.68" + wire width 16 $add$ls180.v:8417$2789_Y + attribute \src "ls180.v:8453.25-8453.49" + wire width 32 $add$ls180.v:8453$2794_Y + attribute \src "ls180.v:8467.25-8467.49" + wire width 32 $add$ls180.v:8467$2798_Y + attribute \src "ls180.v:8481.31-8481.61" + wire width 9 $add$ls180.v:8481$2803_Y + attribute \src "ls180.v:8504.45-8504.88" + wire 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attribute \src "ls180.v:6414.103-6414.147" - wire $eq$ls180.v:6414$1923_Y - attribute \src "ls180.v:6416.102-6416.146" - wire $eq$ls180.v:6416$1926_Y - attribute \src "ls180.v:6417.105-6417.149" - wire $eq$ls180.v:6417$1930_Y + wire $eq$ls180.v:6414$1916_Y + attribute \src "ls180.v:6416.100-6416.144" + wire $eq$ls180.v:6416$1919_Y + attribute \src "ls180.v:6417.103-6417.147" + wire $eq$ls180.v:6417$1923_Y attribute \src "ls180.v:6419.102-6419.146" - wire $eq$ls180.v:6419$1933_Y + wire $eq$ls180.v:6419$1926_Y attribute \src "ls180.v:6420.105-6420.149" - wire $eq$ls180.v:6420$1937_Y - attribute \src "ls180.v:6422.102-6422.147" - wire $eq$ls180.v:6422$1940_Y - attribute \src "ls180.v:6423.105-6423.150" - wire $eq$ls180.v:6423$1944_Y + wire $eq$ls180.v:6420$1930_Y + attribute \src "ls180.v:6422.102-6422.146" + wire $eq$ls180.v:6422$1933_Y + attribute \src "ls180.v:6423.105-6423.149" + wire $eq$ls180.v:6423$1937_Y attribute \src "ls180.v:6425.102-6425.147" - wire $eq$ls180.v:6425$1947_Y + wire $eq$ls180.v:6425$1940_Y attribute \src "ls180.v:6426.105-6426.150" - wire $eq$ls180.v:6426$1951_Y + wire $eq$ls180.v:6426$1944_Y attribute \src "ls180.v:6428.102-6428.147" - wire $eq$ls180.v:6428$1954_Y + wire $eq$ls180.v:6428$1947_Y attribute \src "ls180.v:6429.105-6429.150" - wire $eq$ls180.v:6429$1958_Y - attribute \src "ls180.v:6431.99-6431.144" - wire $eq$ls180.v:6431$1961_Y - attribute \src "ls180.v:6432.102-6432.147" - wire $eq$ls180.v:6432$1965_Y - attribute \src "ls180.v:6434.100-6434.145" - wire $eq$ls180.v:6434$1968_Y - attribute \src "ls180.v:6435.103-6435.148" - wire $eq$ls180.v:6435$1972_Y - attribute \src "ls180.v:6437.102-6437.147" - wire $eq$ls180.v:6437$1975_Y - attribute \src "ls180.v:6438.105-6438.150" - wire $eq$ls180.v:6438$1979_Y + wire $eq$ls180.v:6429$1951_Y + attribute \src "ls180.v:6431.102-6431.147" + wire $eq$ls180.v:6431$1954_Y + attribute \src "ls180.v:6432.105-6432.150" + wire $eq$ls180.v:6432$1958_Y + attribute \src "ls180.v:6434.99-6434.144" + wire $eq$ls180.v:6434$1961_Y + attribute \src "ls180.v:6435.102-6435.147" + wire $eq$ls180.v:6435$1965_Y + attribute \src "ls180.v:6437.100-6437.145" + wire $eq$ls180.v:6437$1968_Y + attribute \src "ls180.v:6438.103-6438.148" + wire $eq$ls180.v:6438$1972_Y attribute \src "ls180.v:6440.102-6440.147" - wire $eq$ls180.v:6440$1982_Y + wire $eq$ls180.v:6440$1975_Y attribute \src "ls180.v:6441.105-6441.150" - wire $eq$ls180.v:6441$1986_Y + wire $eq$ls180.v:6441$1979_Y attribute \src "ls180.v:6443.102-6443.147" - wire $eq$ls180.v:6443$1989_Y + wire $eq$ls180.v:6443$1982_Y attribute \src "ls180.v:6444.105-6444.150" - wire $eq$ls180.v:6444$1993_Y + wire $eq$ls180.v:6444$1986_Y attribute \src "ls180.v:6446.102-6446.147" - wire $eq$ls180.v:6446$1996_Y + wire $eq$ls180.v:6446$1989_Y attribute \src "ls180.v:6447.105-6447.150" - wire $eq$ls180.v:6447$2000_Y - attribute \src "ls180.v:6469.32-6469.78" - wire $eq$ls180.v:6469$2002_Y - attribute \src "ls180.v:6471.102-6471.146" - wire $eq$ls180.v:6471$2004_Y - attribute \src "ls180.v:6472.105-6472.149" - wire $eq$ls180.v:6472$2008_Y - attribute \src "ls180.v:6474.107-6474.151" - wire $eq$ls180.v:6474$2011_Y - attribute \src "ls180.v:6475.110-6475.154" - wire $eq$ls180.v:6475$2015_Y + wire $eq$ls180.v:6447$1993_Y + attribute \src "ls180.v:6449.102-6449.147" + wire $eq$ls180.v:6449$1996_Y + attribute \src "ls180.v:6450.105-6450.150" + wire $eq$ls180.v:6450$2000_Y + attribute \src "ls180.v:6472.32-6472.78" + wire $eq$ls180.v:6472$2002_Y + attribute \src "ls180.v:6474.102-6474.146" + wire $eq$ls180.v:6474$2004_Y + attribute \src "ls180.v:6475.105-6475.149" + wire $eq$ls180.v:6475$2008_Y attribute \src "ls180.v:6477.107-6477.151" - wire $eq$ls180.v:6477$2018_Y + wire $eq$ls180.v:6477$2011_Y attribute \src "ls180.v:6478.110-6478.154" - wire $eq$ls180.v:6478$2022_Y - attribute \src "ls180.v:6480.100-6480.144" - wire $eq$ls180.v:6480$2025_Y - attribute \src "ls180.v:6481.103-6481.147" - wire $eq$ls180.v:6481$2029_Y - attribute \src "ls180.v:6486.32-6486.77" - wire $eq$ls180.v:6486$2031_Y - attribute \src "ls180.v:6488.104-6488.148" - wire $eq$ls180.v:6488$2033_Y - attribute \src "ls180.v:6489.107-6489.151" - wire $eq$ls180.v:6489$2037_Y - attribute \src "ls180.v:6491.108-6491.152" - wire $eq$ls180.v:6491$2040_Y - attribute \src "ls180.v:6492.111-6492.155" - wire $eq$ls180.v:6492$2044_Y - attribute \src "ls180.v:6494.98-6494.142" - wire $eq$ls180.v:6494$2047_Y - attribute \src "ls180.v:6495.101-6495.145" - wire $eq$ls180.v:6495$2051_Y - attribute \src "ls180.v:6497.108-6497.152" - wire $eq$ls180.v:6497$2054_Y - attribute \src "ls180.v:6498.111-6498.155" - wire $eq$ls180.v:6498$2058_Y + wire $eq$ls180.v:6478$2015_Y + attribute \src "ls180.v:6480.107-6480.151" + wire $eq$ls180.v:6480$2018_Y + attribute \src "ls180.v:6481.110-6481.154" + wire $eq$ls180.v:6481$2022_Y + attribute \src "ls180.v:6483.100-6483.144" + wire $eq$ls180.v:6483$2025_Y + attribute \src "ls180.v:6484.103-6484.147" + wire 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"ls180.v:10531.68-10531.77" + wire width 25 $memrd$\storage_2$ls180.v:10531$3041_DATA + attribute \src "ls180.v:10538.14-10538.23" + wire width 25 $memrd$\storage_3$ls180.v:10538$3046_DATA + attribute \src "ls180.v:10545.68-10545.77" + wire width 25 $memrd$\storage_3$ls180.v:10545$3048_DATA + attribute \src "ls180.v:10553.14-10553.23" + wire width 10 $memrd$\storage_4$ls180.v:10553$3053_DATA + attribute \src "ls180.v:10558.15-10558.24" + wire width 10 $memrd$\storage_4$ls180.v:10558$3055_DATA + attribute \src "ls180.v:10570.14-10570.23" + wire width 10 $memrd$\storage_5$ls180.v:10570$3060_DATA + attribute \src "ls180.v:10575.15-10575.24" + wire width 10 $memrd$\storage_5$ls180.v:10575$3062_DATA + attribute \src "ls180.v:10586.14-10586.23" + wire width 10 $memrd$\storage_6$ls180.v:10586$3067_DATA + attribute \src "ls180.v:10593.45-10593.54" + wire width 10 $memrd$\storage_6$ls180.v:10593$3069_DATA + attribute \src "ls180.v:10600.14-10600.23" + wire width 10 $memrd$\storage_7$ls180.v:10600$3074_DATA + attribute \src "ls180.v:10607.45-10607.54" + wire width 10 $memrd$\storage_7$ls180.v:10607$3076_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10352$1_ADDR + wire width 6 $memwr$\mem$ls180.v:10355$1_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10352$1_DATA + wire width 64 $memwr$\mem$ls180.v:10355$1_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10352$1_EN + wire width 64 $memwr$\mem$ls180.v:10355$1_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10354$2_ADDR + wire width 6 $memwr$\mem$ls180.v:10357$2_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10354$2_DATA + wire width 64 $memwr$\mem$ls180.v:10357$2_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10354$2_EN + wire width 64 $memwr$\mem$ls180.v:10357$2_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10356$3_ADDR + wire width 6 $memwr$\mem$ls180.v:10359$3_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10356$3_DATA + wire width 64 $memwr$\mem$ls180.v:10359$3_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10356$3_EN + wire width 64 $memwr$\mem$ls180.v:10359$3_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10358$4_ADDR + wire width 6 $memwr$\mem$ls180.v:10361$4_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10358$4_DATA + wire width 64 $memwr$\mem$ls180.v:10361$4_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10358$4_EN + wire width 64 $memwr$\mem$ls180.v:10361$4_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10360$5_ADDR + wire width 6 $memwr$\mem$ls180.v:10363$5_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10360$5_DATA + wire width 64 $memwr$\mem$ls180.v:10363$5_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10360$5_EN + wire width 64 $memwr$\mem$ls180.v:10363$5_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10362$6_ADDR + wire width 6 $memwr$\mem$ls180.v:10365$6_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10362$6_DATA + wire width 64 $memwr$\mem$ls180.v:10365$6_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10362$6_EN + wire width 64 $memwr$\mem$ls180.v:10365$6_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10364$7_ADDR + wire width 6 $memwr$\mem$ls180.v:10367$7_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10364$7_DATA + wire width 64 $memwr$\mem$ls180.v:10367$7_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10364$7_EN + wire width 64 $memwr$\mem$ls180.v:10367$7_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10366$8_ADDR + wire width 6 $memwr$\mem$ls180.v:10369$8_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10366$8_DATA + wire width 64 $memwr$\mem$ls180.v:10369$8_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10366$8_EN + wire width 64 $memwr$\mem$ls180.v:10369$8_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_1$ls180.v:10380$9_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10383$9_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10380$9_DATA + wire width 64 $memwr$\mem_1$ls180.v:10383$9_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10380$9_EN + wire width 64 $memwr$\mem_1$ls180.v:10383$9_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_1$ls180.v:10382$10_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10385$10_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10382$10_DATA + wire width 64 $memwr$\mem_1$ls180.v:10385$10_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10382$10_EN + wire width 64 $memwr$\mem_1$ls180.v:10385$10_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_1$ls180.v:10384$11_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10387$11_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10384$11_DATA + wire width 64 $memwr$\mem_1$ls180.v:10387$11_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10384$11_EN + wire width 64 $memwr$\mem_1$ls180.v:10387$11_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_1$ls180.v:10386$12_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10389$12_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10386$12_DATA + wire width 64 $memwr$\mem_1$ls180.v:10389$12_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10386$12_EN + wire width 64 $memwr$\mem_1$ls180.v:10389$12_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_1$ls180.v:10388$13_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10391$13_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10388$13_DATA + wire width 64 $memwr$\mem_1$ls180.v:10391$13_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10388$13_EN + wire width 64 $memwr$\mem_1$ls180.v:10391$13_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_1$ls180.v:10390$14_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10393$14_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10390$14_DATA + wire width 64 $memwr$\mem_1$ls180.v:10393$14_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10390$14_EN + wire width 64 $memwr$\mem_1$ls180.v:10393$14_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_1$ls180.v:10392$15_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10395$15_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10392$15_DATA + wire width 64 $memwr$\mem_1$ls180.v:10395$15_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10392$15_EN + wire width 64 $memwr$\mem_1$ls180.v:10395$15_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_1$ls180.v:10394$16_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10397$16_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10394$16_DATA + wire width 64 $memwr$\mem_1$ls180.v:10397$16_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10394$16_EN + wire width 64 $memwr$\mem_1$ls180.v:10397$16_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10408$17_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10411$17_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10408$17_DATA + wire width 64 $memwr$\mem_2$ls180.v:10411$17_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10408$17_EN + wire width 64 $memwr$\mem_2$ls180.v:10411$17_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10410$18_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10413$18_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10410$18_DATA + wire width 64 $memwr$\mem_2$ls180.v:10413$18_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10410$18_EN + wire width 64 $memwr$\mem_2$ls180.v:10413$18_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10412$19_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10415$19_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10412$19_DATA + wire width 64 $memwr$\mem_2$ls180.v:10415$19_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10412$19_EN + wire width 64 $memwr$\mem_2$ls180.v:10415$19_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10414$20_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10417$20_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10414$20_DATA + wire width 64 $memwr$\mem_2$ls180.v:10417$20_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10414$20_EN + wire width 64 $memwr$\mem_2$ls180.v:10417$20_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10416$21_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10419$21_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10416$21_DATA + wire width 64 $memwr$\mem_2$ls180.v:10419$21_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10416$21_EN + wire width 64 $memwr$\mem_2$ls180.v:10419$21_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10418$22_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10421$22_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10418$22_DATA + wire width 64 $memwr$\mem_2$ls180.v:10421$22_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10418$22_EN + wire width 64 $memwr$\mem_2$ls180.v:10421$22_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10420$23_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10423$23_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10420$23_DATA + wire width 64 $memwr$\mem_2$ls180.v:10423$23_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10420$23_EN + wire width 64 $memwr$\mem_2$ls180.v:10423$23_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10422$24_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10425$24_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10422$24_DATA + wire width 64 $memwr$\mem_2$ls180.v:10425$24_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10422$24_EN + wire width 64 $memwr$\mem_2$ls180.v:10425$24_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10436$25_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10439$25_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10436$25_DATA + wire width 64 $memwr$\mem_3$ls180.v:10439$25_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10436$25_EN + wire width 64 $memwr$\mem_3$ls180.v:10439$25_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10438$26_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10441$26_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10438$26_DATA + wire width 64 $memwr$\mem_3$ls180.v:10441$26_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10438$26_EN + wire width 64 $memwr$\mem_3$ls180.v:10441$26_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10440$27_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10443$27_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10440$27_DATA + wire width 64 $memwr$\mem_3$ls180.v:10443$27_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10440$27_EN + wire width 64 $memwr$\mem_3$ls180.v:10443$27_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10442$28_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10445$28_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10442$28_DATA + wire width 64 $memwr$\mem_3$ls180.v:10445$28_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10442$28_EN + wire width 64 $memwr$\mem_3$ls180.v:10445$28_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10444$29_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10447$29_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10444$29_DATA + wire width 64 $memwr$\mem_3$ls180.v:10447$29_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10444$29_EN + wire width 64 $memwr$\mem_3$ls180.v:10447$29_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10446$30_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10449$30_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10446$30_DATA + wire width 64 $memwr$\mem_3$ls180.v:10449$30_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10446$30_EN + wire width 64 $memwr$\mem_3$ls180.v:10449$30_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10448$31_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10451$31_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10448$31_DATA + wire width 64 $memwr$\mem_3$ls180.v:10451$31_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10448$31_EN + wire width 64 $memwr$\mem_3$ls180.v:10451$31_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10450$32_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10453$32_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10450$32_DATA + wire width 64 $memwr$\mem_3$ls180.v:10453$32_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10450$32_EN + wire width 64 $memwr$\mem_3$ls180.v:10453$32_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10464$33_ADDR + wire width 6 $memwr$\mem_4$ls180.v:10467$33_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10464$33_DATA + wire width 64 $memwr$\mem_4$ls180.v:10467$33_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10464$33_EN + wire width 64 $memwr$\mem_4$ls180.v:10467$33_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10466$34_ADDR + wire width 6 $memwr$\mem_4$ls180.v:10469$34_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10466$34_DATA + wire width 64 $memwr$\mem_4$ls180.v:10469$34_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10466$34_EN + wire width 64 $memwr$\mem_4$ls180.v:10469$34_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10468$35_ADDR + wire width 6 $memwr$\mem_4$ls180.v:10471$35_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10468$35_DATA + wire width 64 $memwr$\mem_4$ls180.v:10471$35_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10468$35_EN + wire width 64 $memwr$\mem_4$ls180.v:10471$35_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10470$36_ADDR + wire width 6 $memwr$\mem_4$ls180.v:10473$36_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10470$36_DATA + wire width 64 $memwr$\mem_4$ls180.v:10473$36_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10470$36_EN + wire width 64 $memwr$\mem_4$ls180.v:10473$36_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10472$37_ADDR + wire width 6 $memwr$\mem_4$ls180.v:10475$37_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10472$37_DATA + wire width 64 $memwr$\mem_4$ls180.v:10475$37_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10472$37_EN + wire width 64 $memwr$\mem_4$ls180.v:10475$37_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10474$38_ADDR + wire width 6 $memwr$\mem_4$ls180.v:10477$38_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10474$38_DATA + wire width 64 $memwr$\mem_4$ls180.v:10477$38_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10474$38_EN + wire width 64 $memwr$\mem_4$ls180.v:10477$38_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10476$39_ADDR + wire width 6 $memwr$\mem_4$ls180.v:10479$39_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10476$39_DATA + wire width 64 $memwr$\mem_4$ls180.v:10479$39_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10476$39_EN + wire width 64 $memwr$\mem_4$ls180.v:10479$39_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10478$40_ADDR + wire width 6 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$or$ls180.v:7704$2575_Y - attribute \src "ls180.v:7705.20-7705.71" - wire $or$ls180.v:7705$2576_Y + wire $or$ls180.v:4534$775_Y + attribute \src "ls180.v:4535.38-4535.117" + wire $or$ls180.v:4535$776_Y + attribute \src "ls180.v:4535.37-4535.159" + wire $or$ls180.v:4535$777_Y + attribute \src "ls180.v:4535.36-4535.202" + wire $or$ls180.v:4535$778_Y + attribute \src "ls180.v:4535.35-4535.245" + wire $or$ls180.v:4535$779_Y + attribute \src "ls180.v:4536.40-4536.123" + wire $or$ls180.v:4536$780_Y + attribute \src "ls180.v:4536.39-4536.167" + wire $or$ls180.v:4536$781_Y + attribute \src "ls180.v:4536.38-4536.212" + wire $or$ls180.v:4536$782_Y + attribute \src "ls180.v:4536.37-4536.257" + wire $or$ls180.v:4536$783_Y + attribute \src "ls180.v:4537.39-4537.120" + wire width 4 $or$ls180.v:4537$784_Y + attribute \src "ls180.v:4537.38-4537.163" + wire width 4 $or$ls180.v:4537$785_Y + attribute \src "ls180.v:4537.37-4537.207" + wire width 4 $or$ls180.v:4537$786_Y + attribute \src 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"ls180.v:5141.164-5141.279" + wire $xor$ls180.v:5141$946_Y + attribute \src "ls180.v:5142.361-5142.434" + wire $xor$ls180.v:5142$947_Y + attribute \src "ls180.v:5142.205-5142.278" + wire $xor$ls180.v:5142$948_Y + attribute \src "ls180.v:5142.164-5142.279" + wire $xor$ls180.v:5142$949_Y attribute \src "ls180.v:5143.360-5143.432" - wire $xor$ls180.v:5143$959_Y + wire $xor$ls180.v:5143$950_Y attribute \src "ls180.v:5143.205-5143.277" - wire $xor$ls180.v:5143$960_Y + wire $xor$ls180.v:5143$951_Y attribute \src "ls180.v:5143.164-5143.278" - wire $xor$ls180.v:5143$961_Y + wire $xor$ls180.v:5143$952_Y attribute \src "ls180.v:5144.360-5144.432" - wire $xor$ls180.v:5144$962_Y + wire $xor$ls180.v:5144$953_Y attribute \src "ls180.v:5144.205-5144.277" - wire $xor$ls180.v:5144$963_Y + wire $xor$ls180.v:5144$954_Y attribute \src "ls180.v:5144.164-5144.278" - wire $xor$ls180.v:5144$964_Y + wire $xor$ls180.v:5144$955_Y attribute \src "ls180.v:5145.360-5145.432" - wire $xor$ls180.v:5145$965_Y + wire $xor$ls180.v:5145$956_Y attribute \src "ls180.v:5145.205-5145.277" - wire $xor$ls180.v:5145$966_Y + wire $xor$ls180.v:5145$957_Y attribute \src "ls180.v:5145.164-5145.278" - wire $xor$ls180.v:5145$967_Y + wire $xor$ls180.v:5145$958_Y attribute \src "ls180.v:5146.360-5146.432" - wire $xor$ls180.v:5146$968_Y + wire $xor$ls180.v:5146$959_Y attribute \src "ls180.v:5146.205-5146.277" - wire $xor$ls180.v:5146$969_Y + wire $xor$ls180.v:5146$960_Y attribute \src "ls180.v:5146.164-5146.278" - wire $xor$ls180.v:5146$970_Y + wire $xor$ls180.v:5146$961_Y attribute \src "ls180.v:5147.360-5147.432" - wire $xor$ls180.v:5147$971_Y + wire $xor$ls180.v:5147$962_Y attribute \src "ls180.v:5147.205-5147.277" - wire $xor$ls180.v:5147$972_Y + wire $xor$ls180.v:5147$963_Y attribute \src "ls180.v:5147.164-5147.278" - wire $xor$ls180.v:5147$973_Y + wire $xor$ls180.v:5147$964_Y attribute \src "ls180.v:5148.360-5148.432" - wire $xor$ls180.v:5148$974_Y + wire $xor$ls180.v:5148$965_Y attribute \src "ls180.v:5148.205-5148.277" - wire $xor$ls180.v:5148$975_Y + wire $xor$ls180.v:5148$966_Y attribute \src "ls180.v:5148.164-5148.278" - wire $xor$ls180.v:5148$976_Y + wire $xor$ls180.v:5148$967_Y attribute \src "ls180.v:5149.360-5149.432" - wire $xor$ls180.v:5149$977_Y + wire $xor$ls180.v:5149$968_Y attribute \src "ls180.v:5149.205-5149.277" - wire $xor$ls180.v:5149$978_Y + wire $xor$ls180.v:5149$969_Y attribute \src "ls180.v:5149.164-5149.278" - wire $xor$ls180.v:5149$979_Y - attribute \src "ls180.v:5170.899-5170.983" - wire $xor$ls180.v:5170$993_Y - attribute \src "ls180.v:5170.634-5170.718" - wire $xor$ls180.v:5170$994_Y - attribute \src "ls180.v:5170.588-5170.719" - wire $xor$ls180.v:5170$995_Y - attribute \src "ls180.v:5170.234-5170.318" - wire $xor$ls180.v:5170$996_Y - attribute \src "ls180.v:5170.187-5170.319" - wire $xor$ls180.v:5170$997_Y - attribute \src "ls180.v:5171.588-5171.719" - wire $xor$ls180.v:5171$1000_Y - attribute \src "ls180.v:5171.234-5171.318" - wire $xor$ls180.v:5171$1001_Y - attribute \src "ls180.v:5171.187-5171.319" - wire $xor$ls180.v:5171$1002_Y - attribute \src "ls180.v:5171.899-5171.983" - wire $xor$ls180.v:5171$998_Y - attribute \src "ls180.v:5171.634-5171.718" - wire $xor$ls180.v:5171$999_Y - attribute \src "ls180.v:5180.899-5180.983" - wire $xor$ls180.v:5180$1004_Y - attribute \src "ls180.v:5180.634-5180.718" - wire $xor$ls180.v:5180$1005_Y - attribute \src "ls180.v:5180.588-5180.719" - wire $xor$ls180.v:5180$1006_Y - attribute \src "ls180.v:5180.234-5180.318" - wire $xor$ls180.v:5180$1007_Y - attribute \src "ls180.v:5180.187-5180.319" - wire $xor$ls180.v:5180$1008_Y - attribute \src "ls180.v:5181.899-5181.983" - wire $xor$ls180.v:5181$1009_Y - attribute \src "ls180.v:5181.634-5181.718" - wire $xor$ls180.v:5181$1010_Y - attribute \src "ls180.v:5181.588-5181.719" - wire $xor$ls180.v:5181$1011_Y - attribute \src "ls180.v:5181.234-5181.318" - wire $xor$ls180.v:5181$1012_Y - attribute \src "ls180.v:5181.187-5181.319" - wire $xor$ls180.v:5181$1013_Y - attribute \src "ls180.v:5190.899-5190.983" - wire $xor$ls180.v:5190$1015_Y - attribute \src "ls180.v:5190.634-5190.718" - wire $xor$ls180.v:5190$1016_Y - attribute \src "ls180.v:5190.588-5190.719" - wire $xor$ls180.v:5190$1017_Y - attribute \src "ls180.v:5190.234-5190.318" - wire $xor$ls180.v:5190$1018_Y - attribute \src "ls180.v:5190.187-5190.319" - wire $xor$ls180.v:5190$1019_Y - attribute \src "ls180.v:5191.899-5191.983" - wire $xor$ls180.v:5191$1020_Y - attribute \src "ls180.v:5191.634-5191.718" - wire $xor$ls180.v:5191$1021_Y - attribute \src "ls180.v:5191.588-5191.719" - wire $xor$ls180.v:5191$1022_Y - attribute \src "ls180.v:5191.234-5191.318" - wire $xor$ls180.v:5191$1023_Y - attribute \src "ls180.v:5191.187-5191.319" - wire $xor$ls180.v:5191$1024_Y - attribute \src "ls180.v:5200.899-5200.983" - wire $xor$ls180.v:5200$1026_Y - attribute \src "ls180.v:5200.634-5200.718" - wire $xor$ls180.v:5200$1027_Y - attribute \src "ls180.v:5200.588-5200.719" - wire $xor$ls180.v:5200$1028_Y - attribute \src "ls180.v:5200.234-5200.318" - wire $xor$ls180.v:5200$1029_Y - attribute \src "ls180.v:5200.187-5200.319" - wire $xor$ls180.v:5200$1030_Y - attribute \src "ls180.v:5201.899-5201.983" - wire $xor$ls180.v:5201$1031_Y - attribute \src "ls180.v:5201.634-5201.718" - wire $xor$ls180.v:5201$1032_Y - attribute \src "ls180.v:5201.588-5201.719" - wire $xor$ls180.v:5201$1033_Y - attribute \src "ls180.v:5201.234-5201.318" - wire $xor$ls180.v:5201$1034_Y - attribute \src "ls180.v:5201.187-5201.319" - wire $xor$ls180.v:5201$1035_Y - attribute \src "ls180.v:5352.879-5352.961" - wire $xor$ls180.v:5352$1068_Y - attribute \src "ls180.v:5352.620-5352.702" - wire $xor$ls180.v:5352$1069_Y - attribute \src "ls180.v:5352.575-5352.703" - wire $xor$ls180.v:5352$1070_Y - attribute \src "ls180.v:5352.229-5352.311" - wire $xor$ls180.v:5352$1071_Y - attribute \src "ls180.v:5352.183-5352.312" - wire $xor$ls180.v:5352$1072_Y - attribute \src "ls180.v:5353.879-5353.961" - wire $xor$ls180.v:5353$1073_Y - attribute \src "ls180.v:5353.620-5353.702" - wire $xor$ls180.v:5353$1074_Y - attribute \src "ls180.v:5353.575-5353.703" - wire $xor$ls180.v:5353$1075_Y - attribute \src "ls180.v:5353.229-5353.311" - wire $xor$ls180.v:5353$1076_Y - attribute \src "ls180.v:5353.183-5353.312" - wire $xor$ls180.v:5353$1077_Y - attribute \src "ls180.v:5362.879-5362.961" - wire $xor$ls180.v:5362$1079_Y - attribute \src "ls180.v:5362.620-5362.702" - wire $xor$ls180.v:5362$1080_Y - attribute \src "ls180.v:5362.575-5362.703" - wire $xor$ls180.v:5362$1081_Y - attribute \src "ls180.v:5362.229-5362.311" - wire $xor$ls180.v:5362$1082_Y - attribute \src "ls180.v:5362.183-5362.312" - wire $xor$ls180.v:5362$1083_Y - attribute \src "ls180.v:5363.879-5363.961" - wire $xor$ls180.v:5363$1084_Y - attribute \src "ls180.v:5363.620-5363.702" - wire $xor$ls180.v:5363$1085_Y - attribute \src "ls180.v:5363.575-5363.703" - wire $xor$ls180.v:5363$1086_Y - attribute \src "ls180.v:5363.229-5363.311" - wire $xor$ls180.v:5363$1087_Y - attribute \src "ls180.v:5363.183-5363.312" - wire $xor$ls180.v:5363$1088_Y - attribute \src "ls180.v:5372.879-5372.961" - wire $xor$ls180.v:5372$1090_Y - attribute \src "ls180.v:5372.620-5372.702" - wire $xor$ls180.v:5372$1091_Y - attribute \src "ls180.v:5372.575-5372.703" - wire $xor$ls180.v:5372$1092_Y - attribute \src "ls180.v:5372.229-5372.311" - wire $xor$ls180.v:5372$1093_Y - attribute \src "ls180.v:5372.183-5372.312" - wire $xor$ls180.v:5372$1094_Y - attribute \src "ls180.v:5373.879-5373.961" - wire $xor$ls180.v:5373$1095_Y - attribute \src "ls180.v:5373.620-5373.702" - wire $xor$ls180.v:5373$1096_Y - attribute \src "ls180.v:5373.575-5373.703" - wire $xor$ls180.v:5373$1097_Y - attribute \src "ls180.v:5373.229-5373.311" - wire $xor$ls180.v:5373$1098_Y - attribute \src "ls180.v:5373.183-5373.312" - wire $xor$ls180.v:5373$1099_Y - attribute \src "ls180.v:5382.879-5382.961" - wire $xor$ls180.v:5382$1101_Y - attribute \src "ls180.v:5382.620-5382.702" - wire $xor$ls180.v:5382$1102_Y - attribute \src "ls180.v:5382.575-5382.703" - wire $xor$ls180.v:5382$1103_Y - attribute \src "ls180.v:5382.229-5382.311" - wire $xor$ls180.v:5382$1104_Y - attribute \src "ls180.v:5382.183-5382.312" - wire $xor$ls180.v:5382$1105_Y - attribute \src "ls180.v:5383.879-5383.961" - wire $xor$ls180.v:5383$1106_Y - attribute \src "ls180.v:5383.620-5383.702" - wire $xor$ls180.v:5383$1107_Y - attribute \src "ls180.v:5383.575-5383.703" - wire $xor$ls180.v:5383$1108_Y - attribute \src "ls180.v:5383.229-5383.311" - wire $xor$ls180.v:5383$1109_Y - attribute \src "ls180.v:5383.183-5383.312" - wire $xor$ls180.v:5383$1110_Y - attribute \src "ls180.v:1854.11-1854.42" + wire $xor$ls180.v:5149$970_Y + attribute \src "ls180.v:5150.360-5150.432" + wire $xor$ls180.v:5150$971_Y + attribute \src "ls180.v:5150.205-5150.277" + wire $xor$ls180.v:5150$972_Y + attribute \src "ls180.v:5150.164-5150.278" + wire $xor$ls180.v:5150$973_Y + attribute \src "ls180.v:5151.360-5151.432" + wire $xor$ls180.v:5151$974_Y + attribute \src "ls180.v:5151.205-5151.277" + wire $xor$ls180.v:5151$975_Y + attribute \src "ls180.v:5151.164-5151.278" + wire $xor$ls180.v:5151$976_Y + attribute \src "ls180.v:5152.360-5152.432" + wire $xor$ls180.v:5152$977_Y + attribute \src "ls180.v:5152.205-5152.277" + wire $xor$ls180.v:5152$978_Y + attribute \src "ls180.v:5152.164-5152.278" + wire $xor$ls180.v:5152$979_Y + attribute \src "ls180.v:5173.899-5173.983" + wire $xor$ls180.v:5173$993_Y + attribute \src "ls180.v:5173.634-5173.718" + wire $xor$ls180.v:5173$994_Y + attribute \src "ls180.v:5173.588-5173.719" + wire $xor$ls180.v:5173$995_Y + attribute \src "ls180.v:5173.234-5173.318" + wire $xor$ls180.v:5173$996_Y + attribute \src "ls180.v:5173.187-5173.319" + wire $xor$ls180.v:5173$997_Y + attribute \src "ls180.v:5174.588-5174.719" + wire $xor$ls180.v:5174$1000_Y + attribute \src "ls180.v:5174.234-5174.318" + wire $xor$ls180.v:5174$1001_Y + attribute \src "ls180.v:5174.187-5174.319" + wire $xor$ls180.v:5174$1002_Y + attribute \src "ls180.v:5174.899-5174.983" + wire $xor$ls180.v:5174$998_Y + attribute \src "ls180.v:5174.634-5174.718" + wire $xor$ls180.v:5174$999_Y + attribute \src "ls180.v:5183.899-5183.983" + wire $xor$ls180.v:5183$1004_Y + attribute \src "ls180.v:5183.634-5183.718" + wire $xor$ls180.v:5183$1005_Y + attribute \src "ls180.v:5183.588-5183.719" + wire $xor$ls180.v:5183$1006_Y + attribute \src "ls180.v:5183.234-5183.318" + wire $xor$ls180.v:5183$1007_Y + attribute \src "ls180.v:5183.187-5183.319" + wire $xor$ls180.v:5183$1008_Y + attribute \src "ls180.v:5184.899-5184.983" + wire $xor$ls180.v:5184$1009_Y + attribute \src "ls180.v:5184.634-5184.718" + wire $xor$ls180.v:5184$1010_Y + attribute \src "ls180.v:5184.588-5184.719" + wire $xor$ls180.v:5184$1011_Y + attribute \src "ls180.v:5184.234-5184.318" + wire $xor$ls180.v:5184$1012_Y + attribute \src "ls180.v:5184.187-5184.319" + wire $xor$ls180.v:5184$1013_Y + attribute \src "ls180.v:5193.899-5193.983" + wire $xor$ls180.v:5193$1015_Y + attribute \src "ls180.v:5193.634-5193.718" + wire $xor$ls180.v:5193$1016_Y + attribute \src "ls180.v:5193.588-5193.719" + wire $xor$ls180.v:5193$1017_Y + attribute \src "ls180.v:5193.234-5193.318" + wire $xor$ls180.v:5193$1018_Y + attribute \src "ls180.v:5193.187-5193.319" + wire $xor$ls180.v:5193$1019_Y + attribute \src "ls180.v:5194.899-5194.983" + wire $xor$ls180.v:5194$1020_Y + attribute \src "ls180.v:5194.634-5194.718" + wire $xor$ls180.v:5194$1021_Y + attribute \src "ls180.v:5194.588-5194.719" + wire $xor$ls180.v:5194$1022_Y + attribute \src "ls180.v:5194.234-5194.318" + wire $xor$ls180.v:5194$1023_Y + attribute \src "ls180.v:5194.187-5194.319" + wire $xor$ls180.v:5194$1024_Y + attribute \src "ls180.v:5203.899-5203.983" + wire $xor$ls180.v:5203$1026_Y + attribute \src "ls180.v:5203.634-5203.718" + wire $xor$ls180.v:5203$1027_Y + attribute \src "ls180.v:5203.588-5203.719" + wire $xor$ls180.v:5203$1028_Y + attribute \src "ls180.v:5203.234-5203.318" + wire $xor$ls180.v:5203$1029_Y + attribute \src "ls180.v:5203.187-5203.319" + wire $xor$ls180.v:5203$1030_Y + attribute \src "ls180.v:5204.899-5204.983" + wire $xor$ls180.v:5204$1031_Y + attribute \src "ls180.v:5204.634-5204.718" + wire $xor$ls180.v:5204$1032_Y + attribute \src "ls180.v:5204.588-5204.719" + wire $xor$ls180.v:5204$1033_Y + attribute \src "ls180.v:5204.234-5204.318" + wire $xor$ls180.v:5204$1034_Y + attribute \src "ls180.v:5204.187-5204.319" + wire $xor$ls180.v:5204$1035_Y + attribute \src "ls180.v:5355.879-5355.961" + wire $xor$ls180.v:5355$1068_Y + attribute \src "ls180.v:5355.620-5355.702" + wire $xor$ls180.v:5355$1069_Y + attribute \src "ls180.v:5355.575-5355.703" + wire $xor$ls180.v:5355$1070_Y + attribute \src "ls180.v:5355.229-5355.311" + wire $xor$ls180.v:5355$1071_Y + attribute \src "ls180.v:5355.183-5355.312" + wire $xor$ls180.v:5355$1072_Y + attribute \src "ls180.v:5356.879-5356.961" + wire $xor$ls180.v:5356$1073_Y + attribute \src "ls180.v:5356.620-5356.702" + wire $xor$ls180.v:5356$1074_Y + attribute \src "ls180.v:5356.575-5356.703" + wire $xor$ls180.v:5356$1075_Y + attribute \src "ls180.v:5356.229-5356.311" + wire $xor$ls180.v:5356$1076_Y + attribute \src "ls180.v:5356.183-5356.312" + wire $xor$ls180.v:5356$1077_Y + attribute \src "ls180.v:5365.879-5365.961" + wire $xor$ls180.v:5365$1079_Y + attribute \src "ls180.v:5365.620-5365.702" + wire $xor$ls180.v:5365$1080_Y + attribute \src "ls180.v:5365.575-5365.703" + wire $xor$ls180.v:5365$1081_Y + attribute \src "ls180.v:5365.229-5365.311" + wire $xor$ls180.v:5365$1082_Y + attribute \src "ls180.v:5365.183-5365.312" + wire $xor$ls180.v:5365$1083_Y + attribute \src "ls180.v:5366.879-5366.961" + wire $xor$ls180.v:5366$1084_Y + attribute \src "ls180.v:5366.620-5366.702" + wire $xor$ls180.v:5366$1085_Y + attribute \src "ls180.v:5366.575-5366.703" + wire $xor$ls180.v:5366$1086_Y + attribute \src "ls180.v:5366.229-5366.311" + wire $xor$ls180.v:5366$1087_Y + attribute \src "ls180.v:5366.183-5366.312" + wire $xor$ls180.v:5366$1088_Y + attribute \src "ls180.v:5375.879-5375.961" + wire $xor$ls180.v:5375$1090_Y + attribute \src "ls180.v:5375.620-5375.702" + wire $xor$ls180.v:5375$1091_Y + attribute \src "ls180.v:5375.575-5375.703" + wire $xor$ls180.v:5375$1092_Y + attribute \src "ls180.v:5375.229-5375.311" + wire $xor$ls180.v:5375$1093_Y + attribute \src "ls180.v:5375.183-5375.312" + wire $xor$ls180.v:5375$1094_Y + attribute \src "ls180.v:5376.879-5376.961" + wire $xor$ls180.v:5376$1095_Y + attribute \src "ls180.v:5376.620-5376.702" + wire $xor$ls180.v:5376$1096_Y + attribute \src "ls180.v:5376.575-5376.703" + wire $xor$ls180.v:5376$1097_Y + attribute \src "ls180.v:5376.229-5376.311" + wire $xor$ls180.v:5376$1098_Y + attribute \src "ls180.v:5376.183-5376.312" + wire $xor$ls180.v:5376$1099_Y + attribute \src "ls180.v:5385.879-5385.961" + wire $xor$ls180.v:5385$1101_Y + attribute \src "ls180.v:5385.620-5385.702" + wire $xor$ls180.v:5385$1102_Y + attribute \src "ls180.v:5385.575-5385.703" + wire $xor$ls180.v:5385$1103_Y + attribute \src "ls180.v:5385.229-5385.311" + wire $xor$ls180.v:5385$1104_Y + attribute \src "ls180.v:5385.183-5385.312" + wire $xor$ls180.v:5385$1105_Y + attribute \src "ls180.v:5386.879-5386.961" + wire $xor$ls180.v:5386$1106_Y + attribute \src "ls180.v:5386.620-5386.702" + wire $xor$ls180.v:5386$1107_Y + attribute \src "ls180.v:5386.575-5386.703" + wire $xor$ls180.v:5386$1108_Y + attribute \src "ls180.v:5386.229-5386.311" + wire $xor$ls180.v:5386$1109_Y + attribute \src "ls180.v:5386.183-5386.312" + wire $xor$ls180.v:5386$1110_Y + attribute \src "ls180.v:1857.11-1857.42" wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1853.11-1853.37" + attribute \src "ls180.v:1856.11-1856.37" wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1856.11-1856.42" + attribute \src "ls180.v:1859.11-1859.42" wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1855.11-1855.37" + attribute \src "ls180.v:1858.11-1858.37" wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1858.11-1858.42" + attribute \src "ls180.v:1861.11-1861.42" wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1857.11-1857.37" + attribute \src "ls180.v:1860.11-1860.37" wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1860.11-1860.42" + attribute \src "ls180.v:1863.11-1863.42" wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1859.11-1859.37" + attribute \src "ls180.v:1862.11-1862.37" wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2713.5-2713.34" + attribute \src "ls180.v:2716.5-2716.34" wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2714.12-2714.41" + attribute \src "ls180.v:2717.12-2717.41" wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2726.5-2726.35" + attribute \src "ls180.v:2729.5-2729.35" wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2727.5-2727.35" + attribute \src "ls180.v:2730.5-2730.35" wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2731.12-2731.42" + attribute \src "ls180.v:2734.12-2734.42" wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2732.5-2732.35" + attribute \src "ls180.v:2735.5-2735.35" wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2733.5-2733.35" + attribute \src "ls180.v:2736.5-2736.35" wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2734.12-2734.42" + attribute \src "ls180.v:2737.12-2737.42" wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2735.5-2735.35" + attribute \src "ls180.v:2738.5-2738.35" wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2736.5-2736.35" + attribute \src "ls180.v:2739.5-2739.35" wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2737.12-2737.42" + attribute \src "ls180.v:2740.12-2740.42" wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2738.5-2738.35" + attribute \src "ls180.v:2741.5-2741.35" wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2715.11-2715.40" + attribute \src "ls180.v:2718.11-2718.40" wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2739.5-2739.35" + attribute \src "ls180.v:2742.5-2742.35" wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2740.12-2740.42" + attribute \src "ls180.v:2743.12-2743.42" wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2741.5-2741.35" + attribute \src "ls180.v:2744.5-2744.35" wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2742.5-2742.35" + attribute \src "ls180.v:2745.5-2745.35" wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2743.12-2743.42" + attribute \src "ls180.v:2746.12-2746.42" wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2744.12-2744.42" + attribute \src "ls180.v:2747.12-2747.42" wire width 64 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2745.11-2745.41" + attribute \src "ls180.v:2748.11-2748.41" wire width 8 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2746.5-2746.35" + attribute \src "ls180.v:2749.5-2749.35" wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2747.5-2747.35" + attribute \src "ls180.v:2750.5-2750.35" wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2748.5-2748.35" + attribute \src "ls180.v:2751.5-2751.35" wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2716.5-2716.34" + attribute \src "ls180.v:2719.5-2719.34" wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2749.11-2749.41" + attribute \src "ls180.v:2752.11-2752.41" wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2750.11-2750.41" + attribute \src "ls180.v:2753.11-2753.41" wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2717.5-2717.34" + attribute \src "ls180.v:2720.5-2720.34" wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2718.5-2718.34" + attribute \src "ls180.v:2721.5-2721.34" wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2722.5-2722.34" + attribute \src "ls180.v:2725.5-2725.34" wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2723.12-2723.41" + attribute \src "ls180.v:2726.12-2726.41" wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2724.11-2724.40" + attribute \src "ls180.v:2727.11-2727.40" wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2725.5-2725.34" + attribute \src "ls180.v:2728.5-2728.34" wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2719.5-2719.32" + attribute \src "ls180.v:2722.5-2722.32" wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2720.5-2720.32" + attribute \src "ls180.v:2723.5-2723.32" wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2721.5-2721.32" + attribute \src "ls180.v:2724.5-2724.32" wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2728.5-2728.32" + attribute \src "ls180.v:2731.5-2731.32" wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2729.5-2729.32" + attribute \src "ls180.v:2732.5-2732.32" wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2730.5-2730.32" + attribute \src "ls180.v:2733.5-2733.32" wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1840.5-1840.34" + attribute \src "ls180.v:1843.5-1843.34" wire \builder_converter0_next_state - attribute \src "ls180.v:1839.5-1839.29" + attribute \src "ls180.v:1842.5-1842.29" wire \builder_converter0_state - attribute \src "ls180.v:1844.5-1844.34" + attribute \src "ls180.v:1847.5-1847.34" wire \builder_converter1_next_state - attribute \src "ls180.v:1843.5-1843.29" + attribute \src "ls180.v:1846.5-1846.29" wire \builder_converter1_state - attribute \src "ls180.v:1848.5-1848.34" + attribute \src "ls180.v:1851.5-1851.34" wire \builder_converter2_next_state - attribute \src "ls180.v:1847.5-1847.29" + attribute \src "ls180.v:1850.5-1850.29" wire \builder_converter2_state - attribute \src "ls180.v:1885.5-1885.33" + attribute \src "ls180.v:1888.5-1888.33" wire \builder_converter_next_state - attribute \src "ls180.v:1884.5-1884.28" + attribute \src "ls180.v:1887.5-1887.28" wire \builder_converter_state - attribute \src "ls180.v:2013.12-2013.25" + attribute \src "ls180.v:2016.12-2016.25" wire width 20 \builder_count - attribute \src "ls180.v:2701.13-2701.41" + attribute \src "ls180.v:2704.13-2704.41" wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2704.12-2704.42" + attribute \src "ls180.v:2707.12-2707.42" wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2703.12-2703.42" + attribute \src "ls180.v:2706.12-2706.42" wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2702.6-2702.33" + attribute \src "ls180.v:2705.6-2705.33" wire \builder_csr_interconnect_we - attribute \src "ls180.v:2051.12-2051.42" + attribute \src "ls180.v:2054.12-2054.42" wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:2050.6-2050.37" + attribute \src "ls180.v:2053.6-2053.37" wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:2053.12-2053.42" + attribute \src "ls180.v:2056.12-2056.42" wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:2052.6-2052.37" + attribute \src "ls180.v:2055.6-2055.37" wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:2047.12-2047.42" + attribute \src "ls180.v:2050.12-2050.42" wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:2046.6-2046.37" + attribute \src "ls180.v:2049.6-2049.37" wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:2049.12-2049.42" + attribute \src "ls180.v:2052.12-2052.42" wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:2048.6-2048.37" + attribute \src "ls180.v:2051.6-2051.37" wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:2043.12-2043.42" + attribute \src "ls180.v:2046.12-2046.42" wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:2042.6-2042.37" + attribute \src "ls180.v:2045.6-2045.37" wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:2045.12-2045.42" + attribute \src "ls180.v:2048.12-2048.42" wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:2044.6-2044.37" + attribute \src "ls180.v:2047.6-2047.37" wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:2039.12-2039.42" + attribute \src "ls180.v:2042.12-2042.42" wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:2038.6-2038.37" + attribute \src "ls180.v:2041.6-2041.37" wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:2041.12-2041.42" + attribute \src "ls180.v:2044.12-2044.42" wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:2040.6-2040.37" + attribute \src "ls180.v:2043.6-2043.37" wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:2019.6-2019.31" + attribute \src "ls180.v:2022.6-2022.31" wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:2018.6-2018.32" + attribute \src "ls180.v:2021.6-2021.32" wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:2021.6-2021.31" + attribute \src "ls180.v:2024.6-2024.31" wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:2020.6-2020.32" + attribute \src "ls180.v:2023.6-2023.32" wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:2035.12-2035.39" + attribute \src "ls180.v:2038.12-2038.39" wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:2034.6-2034.34" + attribute \src "ls180.v:2037.6-2037.34" wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:2037.12-2037.39" + attribute \src "ls180.v:2040.12-2040.39" wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:2036.6-2036.34" + attribute \src "ls180.v:2039.6-2039.34" wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:2031.12-2031.39" + attribute \src "ls180.v:2034.12-2034.39" wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:2030.6-2030.34" + attribute \src "ls180.v:2033.6-2033.34" wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:2033.12-2033.39" + attribute \src "ls180.v:2036.12-2036.39" wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:2032.6-2032.34" + attribute \src "ls180.v:2035.6-2035.34" wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:2027.12-2027.39" + attribute \src "ls180.v:2030.12-2030.39" wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:2026.6-2026.34" + attribute \src "ls180.v:2029.6-2029.34" wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:2029.12-2029.39" + attribute \src "ls180.v:2032.12-2032.39" wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:2028.6-2028.34" + attribute \src "ls180.v:2031.6-2031.34" wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:2023.12-2023.39" + attribute \src "ls180.v:2026.12-2026.39" wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:2022.6-2022.34" + attribute \src "ls180.v:2025.6-2025.34" wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:2025.12-2025.39" + attribute \src "ls180.v:2028.12-2028.39" wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:2024.6-2024.34" + attribute \src "ls180.v:2027.6-2027.34" wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:2054.6-2054.26" + attribute \src "ls180.v:2057.6-2057.26" wire \builder_csrbank0_sel - attribute \src "ls180.v:2525.12-2525.40" + attribute \src "ls180.v:2528.12-2528.40" wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2524.6-2524.35" + attribute \src "ls180.v:2527.6-2527.35" wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2527.12-2527.40" + attribute \src "ls180.v:2530.12-2530.40" wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2526.6-2526.35" + attribute \src "ls180.v:2529.6-2529.35" wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2521.12-2521.40" + attribute \src "ls180.v:2524.12-2524.40" wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2520.6-2520.35" + attribute \src "ls180.v:2523.6-2523.35" wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2523.12-2523.40" + attribute \src "ls180.v:2526.12-2526.40" wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2522.6-2522.35" + attribute \src "ls180.v:2525.6-2525.35" wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2541.6-2541.29" + attribute \src "ls180.v:2544.6-2544.29" wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2540.6-2540.30" + attribute \src "ls180.v:2543.6-2543.30" wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2543.6-2543.29" + attribute \src "ls180.v:2546.6-2546.29" wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2542.6-2542.30" + attribute \src "ls180.v:2545.6-2545.30" wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2545.6-2545.35" + attribute \src "ls180.v:2548.6-2548.35" wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2544.6-2544.36" + attribute \src "ls180.v:2547.6-2547.36" wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2547.6-2547.35" + attribute \src "ls180.v:2550.6-2550.35" wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2546.6-2546.36" + attribute \src "ls180.v:2549.6-2549.36" wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2537.12-2537.36" + attribute \src "ls180.v:2540.12-2540.36" wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2536.6-2536.31" + attribute \src "ls180.v:2539.6-2539.31" wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2539.12-2539.36" + attribute \src "ls180.v:2542.12-2542.36" wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2538.6-2538.31" + attribute \src "ls180.v:2541.6-2541.31" wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2533.12-2533.37" + attribute \src "ls180.v:2536.12-2536.37" wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2532.6-2532.32" + attribute \src "ls180.v:2535.6-2535.32" wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2535.12-2535.37" + attribute \src "ls180.v:2538.12-2538.37" wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2534.6-2534.32" + attribute \src "ls180.v:2537.6-2537.32" wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2548.6-2548.27" + attribute \src "ls180.v:2551.6-2551.27" wire \builder_csrbank10_sel - attribute \src "ls180.v:2529.6-2529.32" + attribute \src "ls180.v:2532.6-2532.32" wire \builder_csrbank10_status_r - attribute \src "ls180.v:2528.6-2528.33" + attribute \src "ls180.v:2531.6-2531.33" wire \builder_csrbank10_status_re - attribute \src "ls180.v:2531.6-2531.32" + attribute \src "ls180.v:2534.6-2534.32" wire \builder_csrbank10_status_w - attribute \src "ls180.v:2530.6-2530.33" + attribute \src "ls180.v:2533.6-2533.33" wire \builder_csrbank10_status_we - attribute \src "ls180.v:2586.12-2586.44" + attribute \src "ls180.v:2589.12-2589.44" wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2585.6-2585.39" + attribute \src "ls180.v:2588.6-2588.39" wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2588.12-2588.44" + attribute \src "ls180.v:2591.12-2591.44" wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2587.6-2587.39" + attribute \src "ls180.v:2590.6-2590.39" wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2582.12-2582.44" + attribute \src "ls180.v:2585.12-2585.44" wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2581.6-2581.39" + attribute \src "ls180.v:2584.6-2584.39" wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2584.12-2584.44" + attribute \src "ls180.v:2587.12-2587.44" wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2583.6-2583.39" + attribute \src "ls180.v:2586.6-2586.39" wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2558.12-2558.40" + attribute \src "ls180.v:2561.12-2561.40" wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2557.6-2557.35" + attribute \src "ls180.v:2560.6-2560.35" wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2560.12-2560.40" + attribute \src "ls180.v:2563.12-2563.40" wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2559.6-2559.35" + attribute \src "ls180.v:2562.6-2562.35" wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2554.12-2554.40" + attribute \src "ls180.v:2557.12-2557.40" wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2553.6-2553.35" + attribute \src "ls180.v:2556.6-2556.35" wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2556.12-2556.40" + attribute \src "ls180.v:2559.12-2559.40" wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2555.6-2555.35" + attribute \src "ls180.v:2558.6-2558.35" wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2574.6-2574.29" + attribute \src "ls180.v:2577.6-2577.29" wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2573.6-2573.30" + attribute \src "ls180.v:2576.6-2576.30" wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2576.6-2576.29" + attribute \src "ls180.v:2579.6-2579.29" wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2575.6-2575.30" + attribute \src "ls180.v:2578.6-2578.30" wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2578.6-2578.35" + attribute \src "ls180.v:2581.6-2581.35" wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2577.6-2577.36" + attribute \src "ls180.v:2580.6-2580.36" wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2580.6-2580.35" + attribute \src "ls180.v:2583.6-2583.35" wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2579.6-2579.36" + attribute \src "ls180.v:2582.6-2582.36" wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2570.12-2570.36" + attribute \src "ls180.v:2573.12-2573.36" wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2569.6-2569.31" + attribute \src "ls180.v:2572.6-2572.31" wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2572.12-2572.36" + attribute \src "ls180.v:2575.12-2575.36" wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2571.6-2571.31" + attribute \src "ls180.v:2574.6-2574.31" wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2566.12-2566.37" + attribute \src "ls180.v:2569.12-2569.37" wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2565.6-2565.32" + attribute \src "ls180.v:2568.6-2568.32" wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2568.12-2568.37" + attribute \src "ls180.v:2571.12-2571.37" wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2567.6-2567.32" + attribute \src "ls180.v:2570.6-2570.32" wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2589.6-2589.27" + attribute \src "ls180.v:2592.6-2592.27" wire \builder_csrbank11_sel - attribute \src "ls180.v:2562.6-2562.32" + attribute \src "ls180.v:2565.6-2565.32" wire \builder_csrbank11_status_r - attribute \src "ls180.v:2561.6-2561.33" + attribute \src "ls180.v:2564.6-2564.33" wire \builder_csrbank11_status_re - attribute \src "ls180.v:2564.6-2564.32" + attribute \src "ls180.v:2567.6-2567.32" wire \builder_csrbank11_status_w - attribute \src "ls180.v:2563.6-2563.33" + attribute \src "ls180.v:2566.6-2566.33" wire \builder_csrbank11_status_we - attribute \src "ls180.v:2627.6-2627.29" + attribute \src "ls180.v:2630.6-2630.29" wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2626.6-2626.30" + attribute \src "ls180.v:2629.6-2629.30" wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2629.6-2629.29" + attribute \src "ls180.v:2632.6-2632.29" wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2628.6-2628.30" + attribute \src "ls180.v:2631.6-2631.30" wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2651.6-2651.36" + attribute \src "ls180.v:2654.6-2654.36" wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2650.6-2650.37" + attribute \src "ls180.v:2653.6-2653.37" wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2653.6-2653.36" + attribute \src "ls180.v:2656.6-2656.36" wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2652.6-2652.37" + attribute \src "ls180.v:2655.6-2655.37" wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2607.12-2607.37" + attribute \src "ls180.v:2610.12-2610.37" wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2606.6-2606.32" + attribute \src "ls180.v:2609.6-2609.32" wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2609.12-2609.37" + attribute \src "ls180.v:2612.12-2612.37" wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2608.6-2608.32" + attribute \src "ls180.v:2611.6-2611.32" wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2603.12-2603.37" + attribute \src "ls180.v:2606.12-2606.37" wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2602.6-2602.32" + attribute \src "ls180.v:2605.6-2605.32" wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2605.12-2605.37" + attribute \src "ls180.v:2608.12-2608.37" wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2604.6-2604.32" + attribute \src "ls180.v:2607.6-2607.32" wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2599.12-2599.37" + attribute \src "ls180.v:2602.12-2602.37" wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2598.6-2598.32" + attribute \src "ls180.v:2601.6-2601.32" wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2601.12-2601.37" + attribute \src "ls180.v:2604.12-2604.37" wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2600.6-2600.32" + attribute \src "ls180.v:2603.6-2603.32" wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2595.12-2595.37" + attribute \src "ls180.v:2598.12-2598.37" wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2594.6-2594.32" + attribute \src "ls180.v:2597.6-2597.32" wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2597.12-2597.37" + attribute \src "ls180.v:2600.12-2600.37" wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2596.6-2596.32" + attribute \src "ls180.v:2599.6-2599.32" wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2623.12-2623.39" + attribute \src "ls180.v:2626.12-2626.39" wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2622.6-2622.34" + attribute \src "ls180.v:2625.6-2625.34" wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2625.12-2625.39" + attribute \src "ls180.v:2628.12-2628.39" wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2624.6-2624.34" + attribute \src "ls180.v:2627.6-2627.34" wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2619.12-2619.39" + attribute \src "ls180.v:2622.12-2622.39" wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2618.6-2618.34" + attribute \src "ls180.v:2621.6-2621.34" wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2621.12-2621.39" + attribute \src "ls180.v:2624.12-2624.39" wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2620.6-2620.34" + attribute \src "ls180.v:2623.6-2623.34" wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2615.12-2615.39" + attribute \src "ls180.v:2618.12-2618.39" wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2614.6-2614.34" + attribute \src "ls180.v:2617.6-2617.34" wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2617.12-2617.39" + attribute \src "ls180.v:2620.12-2620.39" wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2616.6-2616.34" + attribute \src "ls180.v:2619.6-2619.34" wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2611.12-2611.39" + attribute \src "ls180.v:2614.12-2614.39" wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2610.6-2610.34" + attribute \src "ls180.v:2613.6-2613.34" wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2613.12-2613.39" + attribute \src "ls180.v:2616.12-2616.39" wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2612.6-2612.34" + attribute \src "ls180.v:2615.6-2615.34" wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2654.6-2654.27" + attribute \src "ls180.v:2657.6-2657.27" wire \builder_csrbank12_sel - attribute \src "ls180.v:2631.6-2631.39" + attribute \src "ls180.v:2634.6-2634.39" wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2630.6-2630.40" + attribute \src "ls180.v:2633.6-2633.40" wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2633.6-2633.39" + attribute \src "ls180.v:2636.6-2636.39" wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2632.6-2632.40" + attribute \src "ls180.v:2635.6-2635.40" wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2647.12-2647.38" + attribute \src "ls180.v:2650.12-2650.38" wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2646.6-2646.33" + attribute \src "ls180.v:2649.6-2649.33" wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2649.12-2649.38" + attribute \src "ls180.v:2652.12-2652.38" wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2648.6-2648.33" + attribute \src "ls180.v:2651.6-2651.33" wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2643.12-2643.38" + attribute \src "ls180.v:2646.12-2646.38" wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2642.6-2642.33" + attribute \src "ls180.v:2645.6-2645.33" wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2645.12-2645.38" + attribute \src "ls180.v:2648.12-2648.38" wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2644.6-2644.33" + attribute \src "ls180.v:2647.6-2647.33" wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2639.12-2639.38" + attribute \src "ls180.v:2642.12-2642.38" wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2638.6-2638.33" + attribute \src "ls180.v:2641.6-2641.33" wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2641.12-2641.38" + attribute \src "ls180.v:2644.12-2644.38" wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2640.6-2640.33" + attribute \src "ls180.v:2643.6-2643.33" wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2635.12-2635.38" + attribute \src "ls180.v:2638.12-2638.38" wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2634.6-2634.33" + attribute \src "ls180.v:2637.6-2637.33" wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2637.12-2637.38" + attribute \src "ls180.v:2640.12-2640.38" wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2636.6-2636.33" + attribute \src "ls180.v:2639.6-2639.33" wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2668.12-2668.42" + attribute \src "ls180.v:2671.12-2671.42" wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2667.6-2667.37" + attribute \src "ls180.v:2670.6-2670.37" wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2670.12-2670.42" + attribute \src "ls180.v:2673.12-2673.42" wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2669.6-2669.37" + attribute \src "ls180.v:2672.6-2672.37" wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2664.6-2664.33" + attribute \src "ls180.v:2667.6-2667.33" wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2663.6-2663.34" + attribute \src "ls180.v:2666.6-2666.34" wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2666.6-2666.33" + attribute \src "ls180.v:2669.6-2669.33" wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2665.6-2665.34" + attribute \src "ls180.v:2668.6-2668.34" wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2676.6-2676.32" + attribute \src "ls180.v:2679.6-2679.32" wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2675.6-2675.33" + attribute \src "ls180.v:2678.6-2678.33" wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2678.6-2678.32" + attribute \src "ls180.v:2681.6-2681.32" wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2677.6-2677.33" + attribute \src "ls180.v:2680.6-2680.33" wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2679.6-2679.27" + attribute \src "ls180.v:2682.6-2682.27" wire \builder_csrbank13_sel - attribute \src "ls180.v:2672.6-2672.33" + attribute \src "ls180.v:2675.6-2675.33" wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2671.6-2671.34" + attribute \src "ls180.v:2674.6-2674.34" wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2674.6-2674.33" + attribute \src "ls180.v:2677.6-2677.33" wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2673.6-2673.34" + attribute \src "ls180.v:2676.6-2676.34" wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2660.6-2660.32" + attribute \src "ls180.v:2663.6-2663.32" wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2659.6-2659.33" + attribute \src "ls180.v:2662.6-2662.33" wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2662.6-2662.32" + attribute \src "ls180.v:2665.6-2665.32" wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2661.6-2661.33" + attribute \src "ls180.v:2664.6-2664.33" wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2700.6-2700.27" + attribute \src "ls180.v:2703.6-2703.27" wire \builder_csrbank14_sel - attribute \src "ls180.v:2697.12-2697.44" + attribute \src "ls180.v:2700.12-2700.44" wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2696.6-2696.39" + attribute \src "ls180.v:2699.6-2699.39" wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2699.12-2699.44" + attribute \src "ls180.v:2702.12-2702.44" wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2698.6-2698.39" + attribute \src "ls180.v:2701.6-2701.39" wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2693.12-2693.44" + attribute \src "ls180.v:2696.12-2696.44" wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2692.6-2692.39" + attribute \src "ls180.v:2695.6-2695.39" wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2695.12-2695.44" + attribute \src "ls180.v:2698.12-2698.44" wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2694.6-2694.39" + attribute \src "ls180.v:2697.6-2697.39" wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2689.12-2689.44" + attribute \src "ls180.v:2692.12-2692.44" wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2688.6-2688.39" + attribute \src "ls180.v:2691.6-2691.39" wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2691.12-2691.44" + attribute \src "ls180.v:2694.12-2694.44" wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2690.6-2690.39" + attribute \src "ls180.v:2693.6-2693.39" wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2685.12-2685.44" + attribute \src "ls180.v:2688.12-2688.44" wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2684.6-2684.39" + attribute \src "ls180.v:2687.6-2687.39" wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2687.12-2687.44" + attribute \src "ls180.v:2690.12-2690.44" wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2686.6-2686.39" + attribute \src "ls180.v:2689.6-2689.39" wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:2072.12-2072.34" + attribute \src "ls180.v:2075.12-2075.34" wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:2071.6-2071.29" + attribute \src "ls180.v:2074.6-2074.29" wire \builder_csrbank1_in0_re - attribute \src "ls180.v:2074.12-2074.34" + attribute \src "ls180.v:2077.12-2077.34" wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:2073.6-2073.29" + attribute \src "ls180.v:2076.6-2076.29" wire \builder_csrbank1_in0_we - attribute \src "ls180.v:2068.12-2068.34" + attribute \src "ls180.v:2071.12-2071.34" wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:2067.6-2067.29" + attribute \src "ls180.v:2070.6-2070.29" wire \builder_csrbank1_in1_re - attribute \src "ls180.v:2070.12-2070.34" + attribute \src "ls180.v:2073.12-2073.34" wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:2069.6-2069.29" + attribute \src "ls180.v:2072.6-2072.29" wire \builder_csrbank1_in1_we - attribute \src "ls180.v:2064.12-2064.34" + attribute \src "ls180.v:2067.12-2067.34" wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:2063.6-2063.29" + attribute \src "ls180.v:2066.6-2066.29" wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:2066.12-2066.34" + attribute \src "ls180.v:2069.12-2069.34" wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:2065.6-2065.29" + attribute \src "ls180.v:2068.6-2068.29" wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:2060.12-2060.34" + attribute \src "ls180.v:2063.12-2063.34" wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:2059.6-2059.29" + attribute \src "ls180.v:2062.6-2062.29" wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:2062.12-2062.34" + attribute \src "ls180.v:2065.12-2065.34" wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:2061.6-2061.29" + attribute \src "ls180.v:2064.6-2064.29" wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:2080.12-2080.35" + attribute \src "ls180.v:2083.12-2083.35" wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:2079.6-2079.30" + attribute \src "ls180.v:2082.6-2082.30" wire \builder_csrbank1_out0_re - attribute \src "ls180.v:2082.12-2082.35" + attribute \src "ls180.v:2085.12-2085.35" wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:2081.6-2081.30" + attribute \src "ls180.v:2084.6-2084.30" wire \builder_csrbank1_out0_we - attribute \src "ls180.v:2076.12-2076.35" + attribute \src "ls180.v:2079.12-2079.35" wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:2075.6-2075.30" + attribute \src "ls180.v:2078.6-2078.30" wire \builder_csrbank1_out1_re - attribute \src "ls180.v:2078.12-2078.35" + attribute \src "ls180.v:2081.12-2081.35" wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:2077.6-2077.30" + attribute \src "ls180.v:2080.6-2080.30" wire \builder_csrbank1_out1_we - attribute \src "ls180.v:2083.6-2083.26" + attribute \src "ls180.v:2086.6-2086.26" wire \builder_csrbank1_sel - attribute \src "ls180.v:2093.6-2093.26" + attribute \src "ls180.v:2096.6-2096.26" wire \builder_csrbank2_r_r - attribute \src "ls180.v:2092.6-2092.27" + attribute \src "ls180.v:2095.6-2095.27" wire \builder_csrbank2_r_re - attribute \src "ls180.v:2095.6-2095.26" + attribute \src "ls180.v:2098.6-2098.26" wire \builder_csrbank2_r_w - attribute \src "ls180.v:2094.6-2094.27" + attribute \src "ls180.v:2097.6-2097.27" wire \builder_csrbank2_r_we - attribute \src "ls180.v:2096.6-2096.26" + attribute \src "ls180.v:2099.6-2099.26" wire \builder_csrbank2_sel - attribute \src "ls180.v:2089.12-2089.33" + attribute \src "ls180.v:2092.12-2092.33" wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:2088.6-2088.28" + attribute \src "ls180.v:2091.6-2091.28" wire \builder_csrbank2_w0_re - attribute \src "ls180.v:2091.12-2091.33" + attribute \src "ls180.v:2094.12-2094.33" wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:2090.6-2090.28" + attribute \src "ls180.v:2093.6-2093.28" wire \builder_csrbank2_w0_we - attribute \src "ls180.v:2102.6-2102.32" + attribute \src "ls180.v:2105.6-2105.32" wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:2101.6-2101.33" + attribute \src "ls180.v:2104.6-2104.33" wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:2104.6-2104.32" + attribute \src "ls180.v:2107.6-2107.32" wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:2103.6-2103.33" + attribute \src "ls180.v:2106.6-2106.33" wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2134.12-2134.38" + attribute \src "ls180.v:2137.12-2137.38" wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2133.6-2133.33" + attribute \src "ls180.v:2136.6-2136.33" wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2136.12-2136.38" + attribute \src "ls180.v:2139.12-2139.38" wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2135.6-2135.33" + attribute \src "ls180.v:2138.6-2138.33" wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2130.12-2130.38" + attribute \src "ls180.v:2133.12-2133.38" wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2129.6-2129.33" + attribute \src "ls180.v:2132.6-2132.33" wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2132.12-2132.38" + attribute \src "ls180.v:2135.12-2135.38" wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2131.6-2131.33" + attribute \src "ls180.v:2134.6-2134.33" wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2126.12-2126.38" + attribute \src "ls180.v:2129.12-2129.38" wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2125.6-2125.33" + attribute \src "ls180.v:2128.6-2128.33" wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2128.12-2128.38" + attribute \src "ls180.v:2131.12-2131.38" wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2127.6-2127.33" + attribute \src "ls180.v:2130.6-2130.33" wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2122.12-2122.38" + attribute \src "ls180.v:2125.12-2125.38" wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2121.6-2121.33" + attribute \src "ls180.v:2124.6-2124.33" wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2124.12-2124.38" + attribute \src "ls180.v:2127.12-2127.38" wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2123.6-2123.33" + attribute \src "ls180.v:2126.6-2126.33" wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2137.6-2137.26" + attribute \src "ls180.v:2140.6-2140.26" wire \builder_csrbank3_sel - attribute \src "ls180.v:2118.12-2118.37" + attribute \src "ls180.v:2121.12-2121.37" wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2117.6-2117.32" + attribute \src "ls180.v:2120.6-2120.32" wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2120.12-2120.37" + attribute \src "ls180.v:2123.12-2123.37" wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2119.6-2119.32" + attribute \src "ls180.v:2122.6-2122.32" wire \builder_csrbank3_width0_we - attribute \src "ls180.v:2114.12-2114.37" + attribute \src "ls180.v:2117.12-2117.37" wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:2113.6-2113.32" + attribute \src "ls180.v:2116.6-2116.32" wire \builder_csrbank3_width1_re - attribute \src "ls180.v:2116.12-2116.37" + attribute \src "ls180.v:2119.12-2119.37" wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:2115.6-2115.32" + attribute \src "ls180.v:2118.6-2118.32" wire \builder_csrbank3_width1_we - attribute \src "ls180.v:2110.12-2110.37" + attribute \src "ls180.v:2113.12-2113.37" wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:2109.6-2109.32" + attribute \src "ls180.v:2112.6-2112.32" wire \builder_csrbank3_width2_re - attribute \src "ls180.v:2112.12-2112.37" + attribute \src "ls180.v:2115.12-2115.37" wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:2111.6-2111.32" + attribute \src "ls180.v:2114.6-2114.32" wire \builder_csrbank3_width2_we - attribute \src "ls180.v:2106.12-2106.37" + attribute \src "ls180.v:2109.12-2109.37" wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:2105.6-2105.32" + attribute \src "ls180.v:2108.6-2108.32" wire \builder_csrbank3_width3_re - attribute \src "ls180.v:2108.12-2108.37" + attribute \src "ls180.v:2111.12-2111.37" wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:2107.6-2107.32" + attribute \src "ls180.v:2110.6-2110.32" wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2143.6-2143.32" + attribute \src "ls180.v:2146.6-2146.32" wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2142.6-2142.33" + attribute \src "ls180.v:2145.6-2145.33" wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2145.6-2145.32" + attribute \src "ls180.v:2148.6-2148.32" wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2144.6-2144.33" + attribute \src "ls180.v:2147.6-2147.33" wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2175.12-2175.38" + attribute \src "ls180.v:2178.12-2178.38" wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2174.6-2174.33" + attribute \src "ls180.v:2177.6-2177.33" wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2177.12-2177.38" + attribute \src "ls180.v:2180.12-2180.38" wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2176.6-2176.33" + attribute \src "ls180.v:2179.6-2179.33" wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2171.12-2171.38" + attribute \src "ls180.v:2174.12-2174.38" wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2170.6-2170.33" + attribute \src "ls180.v:2173.6-2173.33" wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2173.12-2173.38" + attribute \src "ls180.v:2176.12-2176.38" wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2172.6-2172.33" + attribute \src "ls180.v:2175.6-2175.33" wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2167.12-2167.38" + attribute \src "ls180.v:2170.12-2170.38" wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2166.6-2166.33" + attribute \src "ls180.v:2169.6-2169.33" wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2169.12-2169.38" + attribute \src "ls180.v:2172.12-2172.38" wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2168.6-2168.33" + attribute \src "ls180.v:2171.6-2171.33" wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2163.12-2163.38" + attribute \src "ls180.v:2166.12-2166.38" wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2162.6-2162.33" + attribute \src "ls180.v:2165.6-2165.33" wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2165.12-2165.38" + attribute \src "ls180.v:2168.12-2168.38" wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2164.6-2164.33" + attribute \src "ls180.v:2167.6-2167.33" wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2178.6-2178.26" + attribute \src "ls180.v:2181.6-2181.26" wire \builder_csrbank4_sel - attribute \src "ls180.v:2159.12-2159.37" + attribute \src "ls180.v:2162.12-2162.37" wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2158.6-2158.32" + attribute \src "ls180.v:2161.6-2161.32" wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2161.12-2161.37" + attribute \src "ls180.v:2164.12-2164.37" wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2160.6-2160.32" + attribute \src "ls180.v:2163.6-2163.32" wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2155.12-2155.37" + attribute \src "ls180.v:2158.12-2158.37" wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2154.6-2154.32" + attribute \src "ls180.v:2157.6-2157.32" wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2157.12-2157.37" + attribute \src "ls180.v:2160.12-2160.37" wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2156.6-2156.32" + attribute \src "ls180.v:2159.6-2159.32" wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2151.12-2151.37" + attribute \src "ls180.v:2154.12-2154.37" wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2150.6-2150.32" + attribute \src "ls180.v:2153.6-2153.32" wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2153.12-2153.37" + attribute \src "ls180.v:2156.12-2156.37" wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2152.6-2152.32" + attribute \src "ls180.v:2155.6-2155.32" wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2147.12-2147.37" + attribute \src "ls180.v:2150.12-2150.37" wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2146.6-2146.32" + attribute \src "ls180.v:2149.6-2149.32" wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2149.12-2149.37" + attribute \src "ls180.v:2152.12-2152.37" wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2148.6-2148.32" + attribute \src "ls180.v:2151.6-2151.32" wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2212.12-2212.40" + attribute \src "ls180.v:2215.12-2215.40" wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2211.6-2211.35" + attribute \src "ls180.v:2214.6-2214.35" wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2214.12-2214.40" + attribute \src "ls180.v:2217.12-2217.40" wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2213.6-2213.35" + attribute \src "ls180.v:2216.6-2216.35" wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2208.12-2208.40" + attribute \src "ls180.v:2211.12-2211.40" wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2207.6-2207.35" + attribute \src "ls180.v:2210.6-2210.35" wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2210.12-2210.40" + attribute \src "ls180.v:2213.12-2213.40" wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2209.6-2209.35" + attribute \src "ls180.v:2212.6-2212.35" wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2204.12-2204.40" + attribute \src "ls180.v:2207.12-2207.40" wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2203.6-2203.35" + attribute \src "ls180.v:2206.6-2206.35" wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2206.12-2206.40" + attribute \src "ls180.v:2209.12-2209.40" wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2205.6-2205.35" + attribute \src "ls180.v:2208.6-2208.35" wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2200.12-2200.40" + attribute \src "ls180.v:2203.12-2203.40" wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2199.6-2199.35" + attribute \src "ls180.v:2202.6-2202.35" wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2202.12-2202.40" + attribute \src "ls180.v:2205.12-2205.40" wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2201.6-2201.35" + attribute \src "ls180.v:2204.6-2204.35" wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2196.12-2196.40" + attribute \src "ls180.v:2199.12-2199.40" wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2195.6-2195.35" + attribute \src "ls180.v:2198.6-2198.35" wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2198.12-2198.40" + attribute \src "ls180.v:2201.12-2201.40" wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2197.6-2197.35" + attribute \src "ls180.v:2200.6-2200.35" wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2192.12-2192.40" + attribute \src "ls180.v:2195.12-2195.40" wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2191.6-2191.35" + attribute \src "ls180.v:2194.6-2194.35" wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2194.12-2194.40" + attribute \src "ls180.v:2197.12-2197.40" wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2193.6-2193.35" + attribute \src "ls180.v:2196.6-2196.35" wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2188.12-2188.40" + attribute \src "ls180.v:2191.12-2191.40" wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2187.6-2187.35" + attribute \src "ls180.v:2190.6-2190.35" wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2190.12-2190.40" + attribute \src "ls180.v:2193.12-2193.40" wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2189.6-2189.35" + attribute \src "ls180.v:2192.6-2192.35" wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2184.12-2184.40" + attribute \src "ls180.v:2187.12-2187.40" wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2183.6-2183.35" + attribute \src "ls180.v:2186.6-2186.35" wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2186.12-2186.40" + attribute \src "ls180.v:2189.12-2189.40" wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2185.6-2185.35" + attribute \src "ls180.v:2188.6-2188.35" wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2236.6-2236.33" + attribute \src "ls180.v:2239.6-2239.33" wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2235.6-2235.34" + attribute \src "ls180.v:2238.6-2238.34" wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2238.6-2238.33" + attribute \src "ls180.v:2241.6-2241.33" wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2237.6-2237.34" + attribute \src "ls180.v:2240.6-2240.34" wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2232.6-2232.36" + attribute \src "ls180.v:2235.6-2235.36" wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2231.6-2231.37" + attribute \src "ls180.v:2234.6-2234.37" wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2234.6-2234.36" + attribute \src "ls180.v:2237.6-2237.36" wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2233.6-2233.37" + attribute \src "ls180.v:2236.6-2236.37" wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2228.12-2228.42" + attribute \src "ls180.v:2231.12-2231.42" wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2227.6-2227.37" + attribute \src "ls180.v:2230.6-2230.37" wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2230.12-2230.42" + attribute \src "ls180.v:2233.12-2233.42" wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2229.6-2229.37" + attribute \src "ls180.v:2232.6-2232.37" wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2224.12-2224.42" + attribute \src "ls180.v:2227.12-2227.42" wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2223.6-2223.37" + attribute \src "ls180.v:2226.6-2226.37" wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2226.12-2226.42" + attribute \src "ls180.v:2229.12-2229.42" wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2225.6-2225.37" + attribute \src "ls180.v:2228.6-2228.37" wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2220.12-2220.42" + attribute \src "ls180.v:2223.12-2223.42" wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2219.6-2219.37" + attribute \src "ls180.v:2222.6-2222.37" wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2222.12-2222.42" + attribute \src "ls180.v:2225.12-2225.42" wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2221.6-2221.37" + attribute \src "ls180.v:2224.6-2224.37" wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2216.12-2216.42" + attribute \src "ls180.v:2219.12-2219.42" wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2215.6-2215.37" + attribute \src "ls180.v:2218.6-2218.37" wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2218.12-2218.42" + attribute \src "ls180.v:2221.12-2221.42" wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2217.6-2217.37" + attribute \src "ls180.v:2220.6-2220.37" wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2240.6-2240.34" + attribute \src "ls180.v:2243.6-2243.34" wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2239.6-2239.35" + attribute \src "ls180.v:2242.6-2242.35" wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2242.6-2242.34" + attribute \src "ls180.v:2245.6-2245.34" wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2241.6-2241.35" + attribute \src "ls180.v:2244.6-2244.35" wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2243.6-2243.26" + attribute \src "ls180.v:2246.6-2246.26" wire \builder_csrbank5_sel - attribute \src "ls180.v:2373.12-2373.43" + attribute \src "ls180.v:2376.12-2376.43" wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2372.6-2372.38" + attribute \src "ls180.v:2375.6-2375.38" wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2375.12-2375.43" + attribute \src "ls180.v:2378.12-2378.43" wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2374.6-2374.38" + attribute \src "ls180.v:2377.6-2377.38" wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2369.12-2369.43" + attribute \src "ls180.v:2372.12-2372.43" wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2368.6-2368.38" + attribute \src "ls180.v:2371.6-2371.38" wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2371.12-2371.43" + attribute \src "ls180.v:2374.12-2374.43" wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2370.6-2370.38" + attribute \src "ls180.v:2373.6-2373.38" wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2365.12-2365.43" + attribute \src "ls180.v:2368.12-2368.43" wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2364.6-2364.38" + attribute \src "ls180.v:2367.6-2367.38" wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2367.12-2367.43" + attribute \src "ls180.v:2370.12-2370.43" wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2366.6-2366.38" + attribute \src "ls180.v:2369.6-2369.38" wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2361.12-2361.43" + attribute \src "ls180.v:2364.12-2364.43" wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2360.6-2360.38" + attribute \src "ls180.v:2363.6-2363.38" wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2363.12-2363.43" + attribute \src "ls180.v:2366.12-2366.43" wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2362.6-2362.38" + attribute \src "ls180.v:2365.6-2365.38" wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2357.12-2357.44" + attribute \src "ls180.v:2360.12-2360.44" wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2356.6-2356.39" + attribute \src "ls180.v:2359.6-2359.39" wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2359.12-2359.44" + attribute \src "ls180.v:2362.12-2362.44" wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2358.6-2358.39" + attribute \src "ls180.v:2361.6-2361.39" wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2353.12-2353.44" + attribute \src "ls180.v:2356.12-2356.44" wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2352.6-2352.39" + attribute \src "ls180.v:2355.6-2355.39" wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2355.12-2355.44" + attribute \src "ls180.v:2358.12-2358.44" wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2354.6-2354.39" + attribute \src "ls180.v:2357.6-2357.39" wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2261.12-2261.44" + attribute \src "ls180.v:2264.12-2264.44" wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2260.6-2260.39" + attribute \src "ls180.v:2263.6-2263.39" wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2263.12-2263.44" + attribute \src "ls180.v:2266.12-2266.44" wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2262.6-2262.39" + attribute \src "ls180.v:2265.6-2265.39" wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2257.12-2257.44" + attribute \src "ls180.v:2260.12-2260.44" wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2256.6-2256.39" + attribute \src "ls180.v:2259.6-2259.39" wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2259.12-2259.44" + attribute \src "ls180.v:2262.12-2262.44" wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2258.6-2258.39" + attribute \src "ls180.v:2261.6-2261.39" wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2253.12-2253.44" + attribute \src "ls180.v:2256.12-2256.44" wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2252.6-2252.39" + attribute \src "ls180.v:2255.6-2255.39" wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2255.12-2255.44" + attribute \src "ls180.v:2258.12-2258.44" wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2254.6-2254.39" + attribute \src "ls180.v:2257.6-2257.39" wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2249.12-2249.44" + attribute \src "ls180.v:2252.12-2252.44" wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2248.6-2248.39" + attribute \src "ls180.v:2251.6-2251.39" wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2251.12-2251.44" + attribute \src "ls180.v:2254.12-2254.44" wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2250.6-2250.39" + attribute \src "ls180.v:2253.6-2253.39" wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2277.12-2277.43" + attribute \src "ls180.v:2280.12-2280.43" wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2276.6-2276.38" + attribute \src "ls180.v:2279.6-2279.38" wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2279.12-2279.43" + attribute \src "ls180.v:2282.12-2282.43" wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2278.6-2278.38" + attribute \src "ls180.v:2281.6-2281.38" wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2273.12-2273.43" + attribute \src "ls180.v:2276.12-2276.43" wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2272.6-2272.38" + attribute \src "ls180.v:2275.6-2275.38" wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2275.12-2275.43" + attribute \src "ls180.v:2278.12-2278.43" wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2274.6-2274.38" + attribute \src "ls180.v:2277.6-2277.38" wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2269.12-2269.43" + attribute \src "ls180.v:2272.12-2272.43" wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2268.6-2268.38" + attribute \src "ls180.v:2271.6-2271.38" wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2271.12-2271.43" + attribute \src "ls180.v:2274.12-2274.43" wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2270.6-2270.38" + attribute \src "ls180.v:2273.6-2273.38" wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2265.12-2265.43" + attribute \src "ls180.v:2268.12-2268.43" wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2264.6-2264.38" + attribute \src "ls180.v:2267.6-2267.38" wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2267.12-2267.43" + attribute \src "ls180.v:2270.12-2270.43" wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2266.6-2266.38" + attribute \src "ls180.v:2269.6-2269.38" wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2345.12-2345.40" + attribute \src "ls180.v:2348.12-2348.40" wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2344.6-2344.35" + attribute \src "ls180.v:2347.6-2347.35" wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2347.12-2347.40" + attribute \src "ls180.v:2350.12-2350.40" wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2346.6-2346.35" + attribute \src "ls180.v:2349.6-2349.35" wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2341.12-2341.44" + attribute \src "ls180.v:2344.12-2344.44" wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2340.6-2340.39" + attribute \src "ls180.v:2343.6-2343.39" wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2343.12-2343.44" + attribute \src "ls180.v:2346.12-2346.44" wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2342.6-2342.39" + attribute \src "ls180.v:2345.6-2345.39" wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2301.12-2301.45" + attribute \src "ls180.v:2304.12-2304.45" wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2300.6-2300.40" + attribute \src "ls180.v:2303.6-2303.40" wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2303.12-2303.45" + attribute \src "ls180.v:2306.12-2306.45" wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2302.6-2302.40" + attribute \src "ls180.v:2305.6-2305.40" wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2297.12-2297.45" + attribute \src "ls180.v:2300.12-2300.45" wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2296.6-2296.40" + attribute \src "ls180.v:2299.6-2299.40" wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2299.12-2299.45" + attribute \src "ls180.v:2302.12-2302.45" wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2298.6-2298.40" + attribute \src "ls180.v:2301.6-2301.40" wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2293.12-2293.45" + attribute \src "ls180.v:2296.12-2296.45" wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2292.6-2292.40" + attribute \src "ls180.v:2295.6-2295.40" wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2295.12-2295.45" + attribute \src "ls180.v:2298.12-2298.45" wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2294.6-2294.40" + attribute \src "ls180.v:2297.6-2297.40" wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2289.12-2289.45" + attribute \src "ls180.v:2292.12-2292.45" wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2288.6-2288.40" + attribute \src "ls180.v:2291.6-2291.40" wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2291.12-2291.45" + attribute \src "ls180.v:2294.12-2294.45" wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2290.6-2290.40" + attribute \src "ls180.v:2293.6-2293.40" wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2285.12-2285.45" + attribute \src "ls180.v:2288.12-2288.45" wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2284.6-2284.40" + attribute \src "ls180.v:2287.6-2287.40" wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2287.12-2287.45" + attribute \src "ls180.v:2290.12-2290.45" wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2286.6-2286.40" + attribute \src "ls180.v:2289.6-2289.40" wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2281.12-2281.45" + attribute \src "ls180.v:2284.12-2284.45" wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2280.6-2280.40" + attribute \src "ls180.v:2283.6-2283.40" wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2283.12-2283.45" + attribute \src "ls180.v:2286.12-2286.45" wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2282.6-2282.40" + attribute \src "ls180.v:2285.6-2285.40" wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2337.12-2337.44" + attribute \src "ls180.v:2340.12-2340.44" wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2336.6-2336.39" + attribute \src "ls180.v:2339.6-2339.39" wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2339.12-2339.44" + attribute \src "ls180.v:2342.12-2342.44" wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2338.6-2338.39" + attribute \src "ls180.v:2341.6-2341.39" wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2333.12-2333.44" + attribute \src "ls180.v:2336.12-2336.44" wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2332.6-2332.39" + attribute \src "ls180.v:2335.6-2335.39" wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2335.12-2335.44" + attribute \src "ls180.v:2338.12-2338.44" wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2334.6-2334.39" + attribute \src "ls180.v:2337.6-2337.39" wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2329.12-2329.44" + attribute \src "ls180.v:2332.12-2332.44" wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2328.6-2328.39" + attribute \src "ls180.v:2331.6-2331.39" wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2331.12-2331.44" + attribute \src "ls180.v:2334.12-2334.44" wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2330.6-2330.39" + attribute \src "ls180.v:2333.6-2333.39" wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2325.12-2325.44" + attribute \src "ls180.v:2328.12-2328.44" wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2324.6-2324.39" + attribute \src "ls180.v:2327.6-2327.39" wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2327.12-2327.44" + attribute \src "ls180.v:2330.12-2330.44" wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2326.6-2326.39" + attribute \src "ls180.v:2329.6-2329.39" wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2321.12-2321.44" + attribute \src "ls180.v:2324.12-2324.44" wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2320.6-2320.39" + attribute \src "ls180.v:2323.6-2323.39" wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2323.12-2323.44" + attribute \src "ls180.v:2326.12-2326.44" wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2322.6-2322.39" + attribute \src "ls180.v:2325.6-2325.39" wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2317.12-2317.44" + attribute \src "ls180.v:2320.12-2320.44" wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2316.6-2316.39" + attribute \src "ls180.v:2319.6-2319.39" wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2319.12-2319.44" + attribute \src "ls180.v:2322.12-2322.44" wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2318.6-2318.39" + attribute \src "ls180.v:2321.6-2321.39" wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2313.12-2313.44" + attribute \src "ls180.v:2316.12-2316.44" wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2312.6-2312.39" + attribute \src "ls180.v:2315.6-2315.39" wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2315.12-2315.44" + attribute \src "ls180.v:2318.12-2318.44" wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2314.6-2314.39" + attribute \src "ls180.v:2317.6-2317.39" wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2309.12-2309.44" + attribute \src "ls180.v:2312.12-2312.44" wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2308.6-2308.39" + attribute \src "ls180.v:2311.6-2311.39" wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2311.12-2311.44" + attribute \src "ls180.v:2314.12-2314.44" wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2310.6-2310.39" + attribute \src "ls180.v:2313.6-2313.39" wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2305.12-2305.44" + attribute \src "ls180.v:2308.12-2308.44" wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2304.6-2304.39" + attribute \src "ls180.v:2307.6-2307.39" wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2307.12-2307.44" + attribute \src "ls180.v:2310.12-2310.44" wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2306.6-2306.39" + attribute \src "ls180.v:2309.6-2309.39" wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2349.12-2349.41" + attribute \src "ls180.v:2352.12-2352.41" wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2348.6-2348.36" + attribute \src "ls180.v:2351.6-2351.36" wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2351.12-2351.41" + attribute \src "ls180.v:2354.12-2354.41" wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2350.6-2350.36" + attribute \src "ls180.v:2353.6-2353.36" wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2376.6-2376.26" + attribute \src "ls180.v:2379.6-2379.26" wire \builder_csrbank6_sel - attribute \src "ls180.v:2410.12-2410.40" + attribute \src "ls180.v:2413.12-2413.40" wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2409.6-2409.35" + attribute \src "ls180.v:2412.6-2412.35" wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2412.12-2412.40" + attribute \src "ls180.v:2415.12-2415.40" wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2411.6-2411.35" + attribute \src "ls180.v:2414.6-2414.35" wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2406.12-2406.40" + attribute \src "ls180.v:2409.12-2409.40" wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2405.6-2405.35" + attribute \src "ls180.v:2408.6-2408.35" wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2408.12-2408.40" + attribute \src "ls180.v:2411.12-2411.40" wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2407.6-2407.35" + attribute \src "ls180.v:2410.6-2410.35" wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2402.12-2402.40" + attribute \src "ls180.v:2405.12-2405.40" wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2401.6-2401.35" + attribute \src "ls180.v:2404.6-2404.35" wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2404.12-2404.40" + attribute \src "ls180.v:2407.12-2407.40" wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2403.6-2403.35" + attribute \src "ls180.v:2406.6-2406.35" wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2398.12-2398.40" + attribute \src "ls180.v:2401.12-2401.40" wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2397.6-2397.35" + attribute \src "ls180.v:2400.6-2400.35" wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2400.12-2400.40" + attribute \src "ls180.v:2403.12-2403.40" wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2399.6-2399.35" + attribute \src "ls180.v:2402.6-2402.35" wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2394.12-2394.40" + attribute \src "ls180.v:2397.12-2397.40" wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2393.6-2393.35" + attribute \src "ls180.v:2396.6-2396.35" wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2396.12-2396.40" + attribute \src "ls180.v:2399.12-2399.40" wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2395.6-2395.35" + attribute \src "ls180.v:2398.6-2398.35" wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2390.12-2390.40" + attribute \src "ls180.v:2393.12-2393.40" wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2389.6-2389.35" + attribute \src "ls180.v:2392.6-2392.35" wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2392.12-2392.40" + attribute \src "ls180.v:2395.12-2395.40" wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2391.6-2391.35" + attribute \src "ls180.v:2394.6-2394.35" wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2386.12-2386.40" + attribute \src "ls180.v:2389.12-2389.40" wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2385.6-2385.35" + attribute \src "ls180.v:2388.6-2388.35" wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2388.12-2388.40" + attribute \src "ls180.v:2391.12-2391.40" wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2387.6-2387.35" + attribute \src "ls180.v:2390.6-2390.35" wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2382.12-2382.40" + attribute \src "ls180.v:2385.12-2385.40" wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2381.6-2381.35" + attribute \src "ls180.v:2384.6-2384.35" wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2384.12-2384.40" + attribute \src "ls180.v:2387.12-2387.40" wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2383.6-2383.35" + attribute \src "ls180.v:2386.6-2386.35" wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2434.6-2434.33" + attribute \src "ls180.v:2437.6-2437.33" wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2433.6-2433.34" + attribute \src "ls180.v:2436.6-2436.34" wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2436.6-2436.33" + attribute \src "ls180.v:2439.6-2439.33" wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2435.6-2435.34" + attribute \src "ls180.v:2438.6-2438.34" wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2430.6-2430.36" + attribute \src "ls180.v:2433.6-2433.36" wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2429.6-2429.37" + attribute \src "ls180.v:2432.6-2432.37" wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2432.6-2432.36" + attribute \src "ls180.v:2435.6-2435.36" wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2431.6-2431.37" + attribute \src "ls180.v:2434.6-2434.37" wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2426.12-2426.42" + attribute \src "ls180.v:2429.12-2429.42" wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2425.6-2425.37" + attribute \src "ls180.v:2428.6-2428.37" wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2428.12-2428.42" + attribute \src "ls180.v:2431.12-2431.42" wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2427.6-2427.37" + attribute \src "ls180.v:2430.6-2430.37" wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2422.12-2422.42" + attribute \src "ls180.v:2425.12-2425.42" wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2421.6-2421.37" + attribute \src "ls180.v:2424.6-2424.37" wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2424.12-2424.42" + attribute \src "ls180.v:2427.12-2427.42" wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2423.6-2423.37" + attribute \src "ls180.v:2426.6-2426.37" wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2418.12-2418.42" + attribute \src "ls180.v:2421.12-2421.42" wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2417.6-2417.37" + attribute \src "ls180.v:2420.6-2420.37" wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2420.12-2420.42" + attribute \src "ls180.v:2423.12-2423.42" wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2419.6-2419.37" + attribute \src "ls180.v:2422.6-2422.37" wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2414.12-2414.42" + attribute \src "ls180.v:2417.12-2417.42" wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2413.6-2413.37" + attribute \src "ls180.v:2416.6-2416.37" wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2416.12-2416.42" + attribute \src "ls180.v:2419.12-2419.42" wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2415.6-2415.37" + attribute \src "ls180.v:2418.6-2418.37" wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2438.6-2438.34" + attribute \src "ls180.v:2441.6-2441.34" wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2437.6-2437.35" + attribute \src "ls180.v:2440.6-2440.35" wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2440.6-2440.34" + attribute \src "ls180.v:2443.6-2443.34" wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2439.6-2439.35" + attribute \src "ls180.v:2442.6-2442.35" wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2454.12-2454.42" + attribute \src "ls180.v:2457.12-2457.42" wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2453.6-2453.37" + attribute \src "ls180.v:2456.6-2456.37" wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2456.12-2456.42" + attribute \src "ls180.v:2459.12-2459.42" wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2455.6-2455.37" + attribute \src "ls180.v:2458.6-2458.37" wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2450.12-2450.42" + attribute \src "ls180.v:2453.12-2453.42" wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2449.6-2449.37" + attribute \src "ls180.v:2452.6-2452.37" wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2452.12-2452.42" + attribute \src "ls180.v:2455.12-2455.42" wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2451.6-2451.37" + attribute \src "ls180.v:2454.6-2454.37" wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2446.12-2446.42" + attribute \src "ls180.v:2449.12-2449.42" wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2445.6-2445.37" + attribute \src "ls180.v:2448.6-2448.37" wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2448.12-2448.42" + attribute \src "ls180.v:2451.12-2451.42" wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2447.6-2447.37" + attribute \src "ls180.v:2450.6-2450.37" wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2442.12-2442.42" + attribute \src "ls180.v:2445.12-2445.42" wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2441.6-2441.37" + attribute \src "ls180.v:2444.6-2444.37" wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2444.12-2444.42" + attribute \src "ls180.v:2447.12-2447.42" wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2443.6-2443.37" + attribute \src "ls180.v:2446.6-2446.37" wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2457.6-2457.26" + attribute \src "ls180.v:2460.6-2460.26" wire \builder_csrbank7_sel - attribute \src "ls180.v:2463.6-2463.36" + attribute \src "ls180.v:2466.6-2466.36" wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2462.6-2462.37" + attribute \src "ls180.v:2465.6-2465.37" wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2465.6-2465.36" + attribute \src "ls180.v:2468.6-2468.36" wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2464.6-2464.37" + attribute \src "ls180.v:2467.6-2467.37" wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2471.12-2471.47" + attribute \src "ls180.v:2474.12-2474.47" wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2470.6-2470.42" + attribute \src "ls180.v:2473.6-2473.42" wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2473.12-2473.47" + attribute \src "ls180.v:2476.12-2476.47" wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2472.6-2472.42" + attribute \src "ls180.v:2475.6-2475.42" wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2467.6-2467.41" + attribute \src "ls180.v:2470.6-2470.41" wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2466.6-2466.42" + attribute \src "ls180.v:2469.6-2469.42" wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2469.6-2469.41" + attribute \src "ls180.v:2472.6-2472.41" wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2468.6-2468.42" + attribute \src "ls180.v:2471.6-2471.42" wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2474.6-2474.26" + attribute \src "ls180.v:2477.6-2477.26" wire \builder_csrbank8_sel - attribute \src "ls180.v:2480.12-2480.44" + attribute \src "ls180.v:2483.12-2483.44" wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2479.6-2479.39" + attribute \src "ls180.v:2482.6-2482.39" wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2482.12-2482.44" + attribute \src "ls180.v:2485.12-2485.44" wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2481.6-2481.39" + attribute \src "ls180.v:2484.6-2484.39" wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2492.12-2492.48" + attribute \src "ls180.v:2495.12-2495.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2491.6-2491.43" + attribute \src "ls180.v:2494.6-2494.43" wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2494.12-2494.48" + attribute \src "ls180.v:2497.12-2497.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2493.6-2493.43" + attribute \src "ls180.v:2496.6-2496.43" wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2488.12-2488.48" + attribute \src "ls180.v:2491.12-2491.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2487.6-2487.43" + attribute \src "ls180.v:2490.6-2490.43" wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2490.12-2490.48" + attribute \src "ls180.v:2493.12-2493.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2489.6-2489.43" + attribute \src "ls180.v:2492.6-2492.43" wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2496.12-2496.49" + attribute \src "ls180.v:2499.12-2499.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2495.6-2495.44" + attribute \src "ls180.v:2498.6-2498.44" wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2498.12-2498.49" + attribute \src "ls180.v:2501.12-2501.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2497.6-2497.44" + attribute \src "ls180.v:2500.6-2500.44" wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2484.12-2484.48" + attribute \src "ls180.v:2487.12-2487.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2483.6-2483.43" + attribute \src "ls180.v:2486.6-2486.43" wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2486.12-2486.48" + attribute \src "ls180.v:2489.12-2489.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2485.6-2485.43" + attribute \src "ls180.v:2488.6-2488.43" wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2512.12-2512.47" + attribute \src "ls180.v:2515.12-2515.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2511.6-2511.42" + attribute \src "ls180.v:2514.6-2514.42" wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2514.12-2514.47" + attribute \src "ls180.v:2517.12-2517.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2513.6-2513.42" + attribute \src "ls180.v:2516.6-2516.42" wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2508.12-2508.47" + attribute \src "ls180.v:2511.12-2511.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2507.6-2507.42" + attribute \src "ls180.v:2510.6-2510.42" wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2510.12-2510.47" + attribute \src "ls180.v:2513.12-2513.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2509.6-2509.42" + attribute \src "ls180.v:2512.6-2512.42" wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2504.12-2504.47" + attribute \src "ls180.v:2507.12-2507.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2503.6-2503.42" + attribute \src "ls180.v:2506.6-2506.42" wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2506.12-2506.47" + attribute \src "ls180.v:2509.12-2509.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2505.6-2505.42" + attribute \src "ls180.v:2508.6-2508.42" wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2500.12-2500.47" + attribute \src "ls180.v:2503.12-2503.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2499.6-2499.42" + attribute \src "ls180.v:2502.6-2502.42" wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2502.12-2502.47" + attribute \src "ls180.v:2505.12-2505.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2501.6-2501.42" + attribute \src "ls180.v:2504.6-2504.42" wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2515.6-2515.26" + attribute \src "ls180.v:2518.6-2518.26" wire \builder_csrbank9_sel - attribute \src "ls180.v:2012.6-2012.18" + attribute \src "ls180.v:2015.6-2015.18" wire \builder_done - attribute \src "ls180.v:2010.5-2010.18" + attribute \src "ls180.v:2013.5-2013.18" wire \builder_error - attribute \src "ls180.v:2007.11-2007.24" + attribute \src "ls180.v:2010.11-2010.24" wire width 3 \builder_grant - attribute \src "ls180.v:2014.13-2014.44" + attribute \src "ls180.v:2017.13-2017.44" wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:2017.11-2017.44" + attribute \src "ls180.v:2020.11-2020.44" wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:2016.12-2016.45" + attribute \src "ls180.v:2019.12-2019.45" wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:2015.6-2015.36" + attribute \src "ls180.v:2018.6-2018.36" wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2516.13-2516.45" + attribute \src "ls180.v:2519.13-2519.45" wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2519.11-2519.45" + attribute \src "ls180.v:2522.11-2522.45" wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2518.12-2518.46" + attribute \src "ls180.v:2521.12-2521.46" wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2517.6-2517.37" + attribute \src "ls180.v:2520.6-2520.37" wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2549.13-2549.45" + attribute \src "ls180.v:2552.13-2552.45" wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2552.11-2552.45" + attribute \src "ls180.v:2555.11-2555.45" wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2551.12-2551.46" + attribute \src "ls180.v:2554.12-2554.46" wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2550.6-2550.37" + attribute \src "ls180.v:2553.6-2553.37" wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2590.13-2590.45" + attribute \src "ls180.v:2593.13-2593.45" wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2593.11-2593.45" + attribute \src "ls180.v:2596.11-2596.45" wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2592.12-2592.46" + attribute \src "ls180.v:2595.12-2595.46" wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2591.6-2591.37" + attribute \src "ls180.v:2594.6-2594.37" wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2655.13-2655.45" + attribute \src "ls180.v:2658.13-2658.45" wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2658.11-2658.45" + attribute \src "ls180.v:2661.11-2661.45" wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2657.12-2657.46" + attribute \src "ls180.v:2660.12-2660.46" wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2656.6-2656.37" + attribute \src "ls180.v:2659.6-2659.37" wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2680.13-2680.45" + attribute \src "ls180.v:2683.13-2683.45" wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2683.11-2683.45" + attribute \src "ls180.v:2686.11-2686.45" wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2682.12-2682.46" + attribute \src "ls180.v:2685.12-2685.46" wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2681.6-2681.37" + attribute \src "ls180.v:2684.6-2684.37" wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:2055.13-2055.44" + attribute \src "ls180.v:2058.13-2058.44" wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:2058.11-2058.44" + attribute \src "ls180.v:2061.11-2061.44" wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:2057.12-2057.45" + attribute \src "ls180.v:2060.12-2060.45" wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:2056.6-2056.36" + attribute \src "ls180.v:2059.6-2059.36" wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:2084.13-2084.44" + attribute \src "ls180.v:2087.13-2087.44" wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:2087.11-2087.44" + attribute \src "ls180.v:2090.11-2090.44" wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:2086.12-2086.45" + attribute \src "ls180.v:2089.12-2089.45" wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:2085.6-2085.36" + attribute \src "ls180.v:2088.6-2088.36" wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:2097.13-2097.44" + attribute \src "ls180.v:2100.13-2100.44" wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:2100.11-2100.44" + attribute \src "ls180.v:2103.11-2103.44" wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:2099.12-2099.45" + attribute \src "ls180.v:2102.12-2102.45" wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:2098.6-2098.36" + attribute \src "ls180.v:2101.6-2101.36" wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2138.13-2138.44" + attribute \src "ls180.v:2141.13-2141.44" wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2141.11-2141.44" + attribute \src "ls180.v:2144.11-2144.44" wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2140.12-2140.45" + attribute \src "ls180.v:2143.12-2143.45" wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2139.6-2139.36" + attribute \src "ls180.v:2142.6-2142.36" wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2179.13-2179.44" + attribute \src "ls180.v:2182.13-2182.44" wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2182.11-2182.44" + attribute \src "ls180.v:2185.11-2185.44" wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2181.12-2181.45" + attribute \src "ls180.v:2184.12-2184.45" wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2180.6-2180.36" + attribute \src "ls180.v:2183.6-2183.36" wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2244.13-2244.44" + attribute \src "ls180.v:2247.13-2247.44" wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2247.11-2247.44" + attribute \src "ls180.v:2250.11-2250.44" wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2246.12-2246.45" + attribute \src "ls180.v:2249.12-2249.45" wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2245.6-2245.36" + attribute \src "ls180.v:2248.6-2248.36" wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2377.13-2377.44" + attribute \src "ls180.v:2380.13-2380.44" wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2380.11-2380.44" + attribute \src "ls180.v:2383.11-2383.44" wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2379.12-2379.45" + attribute \src "ls180.v:2382.12-2382.45" wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2378.6-2378.36" + attribute \src "ls180.v:2381.6-2381.36" wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2458.13-2458.44" + attribute \src "ls180.v:2461.13-2461.44" wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2461.11-2461.44" + attribute \src "ls180.v:2464.11-2464.44" wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2460.12-2460.45" + attribute \src "ls180.v:2463.12-2463.45" wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2459.6-2459.36" + attribute \src "ls180.v:2462.6-2462.36" wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2475.13-2475.44" + attribute \src "ls180.v:2478.13-2478.44" wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2478.11-2478.44" + attribute \src "ls180.v:2481.11-2481.44" wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2477.12-2477.45" + attribute \src "ls180.v:2480.12-2480.45" wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2476.6-2476.36" + attribute \src "ls180.v:2479.6-2479.36" wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1972.12-1972.35" + attribute \src "ls180.v:1975.12-1975.35" wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2709.12-2709.47" + attribute \src "ls180.v:2712.12-2712.47" wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2710.5-2710.43" + attribute \src "ls180.v:2713.5-2713.43" wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1990.5-1990.48" + attribute \src "ls180.v:1993.5-1993.48" wire \builder_libresocsim_converted_interface_ack - attribute \src "ls180.v:1984.13-1984.56" + attribute \src "ls180.v:1987.13-1987.56" wire width 30 \builder_libresocsim_converted_interface_adr - attribute \src "ls180.v:1993.12-1993.55" + attribute \src "ls180.v:1996.12-1996.55" wire width 2 \builder_libresocsim_converted_interface_bte - attribute \src "ls180.v:1992.12-1992.55" + attribute \src "ls180.v:1995.12-1995.55" wire width 3 \builder_libresocsim_converted_interface_cti - attribute \src "ls180.v:1988.6-1988.49" + attribute \src "ls180.v:1991.6-1991.49" wire \builder_libresocsim_converted_interface_cyc - attribute \src "ls180.v:1986.12-1986.57" + attribute \src "ls180.v:1989.12-1989.57" wire width 64 \builder_libresocsim_converted_interface_dat_r - attribute \src "ls180.v:1985.13-1985.58" + attribute \src "ls180.v:1988.13-1988.58" wire width 64 \builder_libresocsim_converted_interface_dat_w - attribute \src "ls180.v:1994.5-1994.48" + attribute \src "ls180.v:1997.5-1997.48" wire \builder_libresocsim_converted_interface_err - attribute \src "ls180.v:1987.12-1987.55" + attribute \src "ls180.v:1990.12-1990.55" wire width 8 \builder_libresocsim_converted_interface_sel - attribute \src "ls180.v:1989.6-1989.49" + attribute \src "ls180.v:1992.6-1992.49" wire \builder_libresocsim_converted_interface_stb - attribute \src "ls180.v:1991.6-1991.48" + attribute \src "ls180.v:1994.6-1994.48" wire \builder_libresocsim_converted_interface_we - attribute \src "ls180.v:1975.12-1975.37" + attribute \src "ls180.v:1978.12-1978.37" wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1974.11-1974.36" + attribute \src "ls180.v:1977.11-1977.36" wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2707.11-2707.48" + attribute \src "ls180.v:2710.11-2710.48" wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2708.5-2708.45" + attribute \src "ls180.v:2711.5-2711.45" wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1973.5-1973.27" + attribute \src "ls180.v:1976.5-1976.27" wire \builder_libresocsim_we - attribute \src "ls180.v:2711.5-2711.39" + attribute \src "ls180.v:2714.5-2714.39" wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2712.5-2712.42" + attribute \src "ls180.v:2715.5-2715.42" wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1982.5-1982.37" + attribute \src "ls180.v:1985.5-1985.37" wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1976.12-1976.44" + attribute \src "ls180.v:1979.12-1979.44" wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1980.5-1980.37" + attribute \src "ls180.v:1983.5-1983.37" wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1978.12-1978.46" + attribute \src "ls180.v:1981.12-1981.46" wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1977.12-1977.46" + attribute \src "ls180.v:1980.12-1980.46" wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1979.11-1979.43" + attribute \src "ls180.v:1982.11-1982.43" wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1981.5-1981.37" + attribute \src "ls180.v:1984.5-1984.37" wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1983.5-1983.36" + attribute \src "ls180.v:1986.5-1986.36" wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1875.5-1875.20" + attribute \src "ls180.v:1878.5-1878.20" wire \builder_locked0 - attribute \src "ls180.v:1876.5-1876.20" + attribute \src "ls180.v:1879.5-1879.20" wire \builder_locked1 - attribute \src "ls180.v:1877.5-1877.20" + attribute \src "ls180.v:1880.5-1880.20" wire \builder_locked2 - attribute \src "ls180.v:1878.5-1878.20" + attribute \src "ls180.v:1881.5-1881.20" wire \builder_locked3 - attribute \src "ls180.v:1862.11-1862.41" + attribute \src "ls180.v:1865.11-1865.41" wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1861.11-1861.36" + attribute \src "ls180.v:1864.11-1864.36" wire width 3 \builder_multiplexer_state attribute \no_retiming "true" - attribute \src "ls180.v:2816.32-2816.59" + attribute \src "ls180.v:2819.32-2819.59" wire \builder_multiregimpl0_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2817.32-2817.59" + attribute \src "ls180.v:2820.32-2820.59" wire \builder_multiregimpl0_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2836.32-2836.60" + attribute \src "ls180.v:2839.32-2839.60" wire \builder_multiregimpl10_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2837.32-2837.60" + attribute \src "ls180.v:2840.32-2840.60" wire \builder_multiregimpl10_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2838.32-2838.60" + attribute \src "ls180.v:2841.32-2841.60" wire \builder_multiregimpl11_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2839.32-2839.60" + attribute \src "ls180.v:2842.32-2842.60" wire \builder_multiregimpl11_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2840.32-2840.60" + attribute \src "ls180.v:2843.32-2843.60" wire \builder_multiregimpl12_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2841.32-2841.60" + attribute \src "ls180.v:2844.32-2844.60" wire \builder_multiregimpl12_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2842.32-2842.60" + attribute \src "ls180.v:2845.32-2845.60" wire \builder_multiregimpl13_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2843.32-2843.60" + attribute \src "ls180.v:2846.32-2846.60" wire \builder_multiregimpl13_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2844.32-2844.60" + attribute \src "ls180.v:2847.32-2847.60" wire \builder_multiregimpl14_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2845.32-2845.60" + attribute \src "ls180.v:2848.32-2848.60" wire \builder_multiregimpl14_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2846.32-2846.60" + attribute \src "ls180.v:2849.32-2849.60" wire \builder_multiregimpl15_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2847.32-2847.60" + attribute \src "ls180.v:2850.32-2850.60" wire \builder_multiregimpl15_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2848.32-2848.60" + attribute \src "ls180.v:2851.32-2851.60" wire \builder_multiregimpl16_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2849.32-2849.60" + attribute \src "ls180.v:2852.32-2852.60" wire \builder_multiregimpl16_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2818.32-2818.59" + attribute \src "ls180.v:2821.32-2821.59" wire \builder_multiregimpl1_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2819.32-2819.59" + attribute \src "ls180.v:2822.32-2822.59" wire \builder_multiregimpl1_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2820.32-2820.59" + attribute \src "ls180.v:2823.32-2823.59" wire \builder_multiregimpl2_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2821.32-2821.59" + attribute \src "ls180.v:2824.32-2824.59" wire \builder_multiregimpl2_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2822.32-2822.59" + attribute \src "ls180.v:2825.32-2825.59" wire \builder_multiregimpl3_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2823.32-2823.59" + attribute \src "ls180.v:2826.32-2826.59" wire \builder_multiregimpl3_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2824.32-2824.59" + attribute \src "ls180.v:2827.32-2827.59" wire \builder_multiregimpl4_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2825.32-2825.59" + attribute \src "ls180.v:2828.32-2828.59" wire \builder_multiregimpl4_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2826.32-2826.59" + attribute \src "ls180.v:2829.32-2829.59" wire \builder_multiregimpl5_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2827.32-2827.59" + attribute \src "ls180.v:2830.32-2830.59" wire \builder_multiregimpl5_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2828.32-2828.59" + attribute \src "ls180.v:2831.32-2831.59" wire \builder_multiregimpl6_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2829.32-2829.59" + attribute \src "ls180.v:2832.32-2832.59" wire \builder_multiregimpl6_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2830.32-2830.59" + attribute \src "ls180.v:2833.32-2833.59" wire \builder_multiregimpl7_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2831.32-2831.59" + attribute \src "ls180.v:2834.32-2834.59" wire \builder_multiregimpl7_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2832.32-2832.59" + attribute \src "ls180.v:2835.32-2835.59" wire \builder_multiregimpl8_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2833.32-2833.59" + attribute \src "ls180.v:2836.32-2836.59" wire \builder_multiregimpl8_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2834.32-2834.59" + attribute \src "ls180.v:2837.32-2837.59" wire \builder_multiregimpl9_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2835.32-2835.59" + attribute \src "ls180.v:2838.32-2838.59" wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1880.5-1880.36" + attribute \src "ls180.v:1883.5-1883.36" wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1881.5-1881.36" + attribute \src "ls180.v:1884.5-1884.36" wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1882.5-1882.36" + attribute \src "ls180.v:1885.5-1885.36" wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1883.5-1883.36" + attribute \src "ls180.v:1886.5-1886.36" wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1879.5-1879.35" + attribute \src "ls180.v:1882.5-1882.35" wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2706.11-2706.29" + attribute \src "ls180.v:2709.11-2709.29" wire width 2 \builder_next_state - attribute \src "ls180.v:1852.11-1852.39" + attribute \src "ls180.v:1855.11-1855.39" wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1851.11-1851.34" + attribute \src "ls180.v:1854.11-1854.34" wire width 2 \builder_refresher_state - attribute \src "ls180.v:2006.12-2006.27" + attribute \src "ls180.v:2009.12-2009.27" wire width 5 \builder_request - attribute \src "ls180.v:1865.6-1865.28" + attribute \src "ls180.v:1868.6-1868.28" wire \builder_roundrobin0_ce - attribute \src "ls180.v:1864.6-1864.31" + attribute \src "ls180.v:1867.6-1867.31" wire \builder_roundrobin0_grant - attribute \src "ls180.v:1863.6-1863.33" + attribute \src "ls180.v:1866.6-1866.33" wire \builder_roundrobin0_request - attribute \src "ls180.v:1868.6-1868.28" + attribute \src "ls180.v:1871.6-1871.28" wire \builder_roundrobin1_ce - attribute \src "ls180.v:1867.6-1867.31" + attribute \src "ls180.v:1870.6-1870.31" wire \builder_roundrobin1_grant - attribute \src "ls180.v:1866.6-1866.33" + attribute \src "ls180.v:1869.6-1869.33" wire \builder_roundrobin1_request - attribute \src "ls180.v:1871.6-1871.28" + attribute \src "ls180.v:1874.6-1874.28" wire \builder_roundrobin2_ce - attribute \src "ls180.v:1870.6-1870.31" + attribute \src "ls180.v:1873.6-1873.31" wire \builder_roundrobin2_grant - attribute \src "ls180.v:1869.6-1869.33" + attribute \src "ls180.v:1872.6-1872.33" wire \builder_roundrobin2_request - attribute \src "ls180.v:1874.6-1874.28" + attribute \src "ls180.v:1877.6-1877.28" wire \builder_roundrobin3_ce - attribute \src "ls180.v:1873.6-1873.31" + attribute \src "ls180.v:1876.6-1876.31" wire \builder_roundrobin3_grant - attribute \src "ls180.v:1872.6-1872.33" + attribute \src "ls180.v:1875.6-1875.33" wire \builder_roundrobin3_request - attribute \src "ls180.v:1961.11-1961.44" + attribute \src "ls180.v:1964.11-1964.44" wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1960.11-1960.39" + attribute \src "ls180.v:1963.11-1963.39" wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1929.5-1929.50" + attribute \src "ls180.v:1932.5-1932.50" wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1928.5-1928.45" + attribute \src "ls180.v:1931.5-1931.45" wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1941.11-1941.40" + attribute \src "ls180.v:1944.11-1944.40" wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1940.11-1940.35" + attribute \src "ls180.v:1943.11-1943.35" wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1965.5-1965.42" + attribute \src "ls180.v:1968.5-1968.42" wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1964.5-1964.37" + attribute \src "ls180.v:1967.5-1967.37" wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1969.11-1969.58" + attribute \src "ls180.v:1972.11-1972.58" wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1968.11-1968.53" + attribute \src "ls180.v:1971.11-1971.53" wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1917.11-1917.39" + attribute \src "ls180.v:1920.11-1920.39" wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1916.11-1916.34" + attribute \src "ls180.v:1919.11-1919.34" wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1905.11-1905.45" + attribute \src "ls180.v:1908.11-1908.45" wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1904.11-1904.40" + attribute \src "ls180.v:1907.11-1907.40" wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1901.11-1901.45" + attribute \src "ls180.v:1904.11-1904.45" wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1900.11-1900.40" + attribute \src "ls180.v:1903.11-1903.40" wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1913.5-1913.39" + attribute \src "ls180.v:1916.5-1916.39" wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1912.5-1912.34" + attribute \src "ls180.v:1915.5-1915.34" wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1921.11-1921.46" + attribute \src "ls180.v:1924.11-1924.46" wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1920.11-1920.41" + attribute \src "ls180.v:1923.11-1923.41" wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1897.5-1897.39" + attribute \src "ls180.v:1900.5-1900.39" wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1896.5-1896.34" + attribute \src "ls180.v:1899.5-1899.34" wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:2001.5-2001.23" + attribute \src "ls180.v:2004.5-2004.23" wire \builder_shared_ack - attribute \src "ls180.v:1995.13-1995.31" + attribute \src "ls180.v:1998.13-1998.31" wire width 30 \builder_shared_adr - attribute \src "ls180.v:2004.12-2004.30" + attribute \src "ls180.v:2007.12-2007.30" wire width 2 \builder_shared_bte - attribute \src "ls180.v:2003.12-2003.30" + attribute \src "ls180.v:2006.12-2006.30" wire width 3 \builder_shared_cti - attribute \src "ls180.v:1999.6-1999.24" + attribute \src "ls180.v:2002.6-2002.24" wire \builder_shared_cyc - attribute \src "ls180.v:1997.12-1997.32" + attribute \src "ls180.v:2000.12-2000.32" wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1996.13-1996.33" + attribute \src "ls180.v:1999.13-1999.33" wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:2005.6-2005.24" + attribute \src "ls180.v:2008.6-2008.24" wire \builder_shared_err - attribute \src "ls180.v:1998.12-1998.30" + attribute \src "ls180.v:2001.12-2001.30" wire width 4 \builder_shared_sel - attribute \src "ls180.v:2000.6-2000.24" + attribute \src "ls180.v:2003.6-2003.24" wire \builder_shared_stb - attribute \src "ls180.v:2002.6-2002.23" + attribute \src "ls180.v:2005.6-2005.23" wire \builder_shared_we - attribute \src "ls180.v:2008.12-2008.29" + attribute \src "ls180.v:2011.12-2011.29" wire width 13 \builder_slave_sel - attribute \src "ls180.v:2009.12-2009.31" + attribute \src "ls180.v:2012.12-2012.31" wire width 13 \builder_slave_sel_r - attribute \src "ls180.v:1889.11-1889.40" + attribute \src "ls180.v:1892.11-1892.40" wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1888.11-1888.35" + attribute \src "ls180.v:1891.11-1891.35" wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1893.11-1893.40" + attribute \src "ls180.v:1896.11-1896.40" wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1892.11-1892.35" + attribute \src "ls180.v:1895.11-1895.35" wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2705.11-2705.24" + attribute \src "ls180.v:2708.11-2708.24" wire width 2 \builder_state - attribute \src "ls180.v:2758.5-2758.32" + attribute \src "ls180.v:2761.5-2761.32" wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2759.5-2759.32" + attribute \src "ls180.v:2762.5-2762.32" wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2751.11-2751.40" + attribute \src "ls180.v:2754.11-2754.40" wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2752.12-2752.41" + attribute \src "ls180.v:2755.12-2755.41" wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2753.5-2753.34" + attribute \src "ls180.v:2756.5-2756.34" wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2754.5-2754.34" + attribute \src "ls180.v:2757.5-2757.34" wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2755.5-2755.34" + attribute \src "ls180.v:2758.5-2758.34" wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2756.5-2756.34" + attribute \src "ls180.v:2759.5-2759.34" wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2757.5-2757.34" + attribute \src "ls180.v:2760.5-2760.34" wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:2011.6-2011.18" + attribute \src "ls180.v:2014.6-2014.18" wire \builder_wait - attribute \src "ls180.v:37.19-37.23" - wire width 3 input 33 \eint - attribute \src "ls180.v:198.11-198.17" + attribute \src "ls180.v:42.19-42.23" + wire width 3 input 38 \eint + attribute \src "ls180.v:206.12-206.18" wire width 3 \eint_1 - attribute \src "ls180.v:18.20-18.26" - wire width 16 input 14 \gpio_i - attribute \src "ls180.v:19.21-19.27" + attribute \src "ls180.v:18.21-18.27" + wire width 16 output 14 \gpio_i + attribute \src "ls180.v:19.20-19.26" wire width 16 output 15 \gpio_o - attribute \src "ls180.v:20.21-20.28" + attribute \src "ls180.v:20.20-20.27" wire width 16 output 16 \gpio_oe - attribute \src "ls180.v:7.14-7.21" - wire output 3 \i2c_scl - attribute \src "ls180.v:8.13-8.22" - wire input 4 \i2c_sda_i - attribute \src "ls180.v:9.14-9.23" - wire output 5 \i2c_sda_o - attribute \src "ls180.v:10.14-10.24" - wire output 6 \i2c_sda_oe + attribute \src "ls180.v:14.14-14.21" + wire output 10 \i2c_scl + attribute \src "ls180.v:15.14-15.23" + wire output 11 \i2c_sda_i + attribute \src "ls180.v:16.14-16.23" + wire output 12 \i2c_sda_o + attribute \src "ls180.v:17.14-17.24" + wire output 13 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -245569,309 +248092,309 @@ module \ls180 wire output 47 \jtag_tdo attribute \src "ls180.v:48.13-48.21" wire input 44 \jtag_tms - attribute \src "ls180.v:937.6-937.18" + attribute \src "ls180.v:940.6-940.18" wire \main_ack_cmd - attribute \src "ls180.v:939.6-939.20" + attribute \src "ls180.v:942.6-942.20" wire \main_ack_rdata - attribute \src "ls180.v:938.6-938.20" + attribute \src "ls180.v:941.6-941.20" wire \main_ack_wdata - attribute \src "ls180.v:935.5-935.22" + attribute \src "ls180.v:938.5-938.22" wire \main_cmd_consumed - attribute \src "ls180.v:318.5-318.28" + attribute \src "ls180.v:321.5-321.28" wire \main_converter0_counter - attribute \src "ls180.v:1841.5-1841.50" + attribute \src "ls180.v:1844.5-1844.50" wire \main_converter0_counter_converter0_next_value - attribute \src "ls180.v:1842.5-1842.53" + attribute \src "ls180.v:1845.5-1845.53" wire \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:320.12-320.33" + attribute \src "ls180.v:323.12-323.33" wire width 64 \main_converter0_dat_r - attribute \src "ls180.v:319.6-319.27" + attribute \src "ls180.v:322.6-322.27" wire \main_converter0_reset - attribute \src "ls180.v:317.5-317.25" + attribute \src "ls180.v:320.5-320.25" wire \main_converter0_skip - attribute \src "ls180.v:333.5-333.28" + attribute \src "ls180.v:336.5-336.28" wire \main_converter1_counter - attribute \src "ls180.v:1845.5-1845.50" + attribute \src "ls180.v:1848.5-1848.50" wire \main_converter1_counter_converter1_next_value - attribute \src "ls180.v:1846.5-1846.53" + attribute \src "ls180.v:1849.5-1849.53" wire \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:335.12-335.33" + attribute \src "ls180.v:338.12-338.33" wire width 64 \main_converter1_dat_r - attribute \src "ls180.v:334.6-334.27" + attribute \src "ls180.v:337.6-337.27" wire \main_converter1_reset - attribute \src "ls180.v:332.5-332.25" + attribute \src "ls180.v:335.5-335.25" wire \main_converter1_skip - attribute \src "ls180.v:932.5-932.27" + attribute \src "ls180.v:935.5-935.27" wire \main_converter_counter - attribute \src "ls180.v:1886.5-1886.48" + attribute \src "ls180.v:1889.5-1889.48" wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1887.5-1887.51" + attribute \src "ls180.v:1890.5-1890.51" wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:934.12-934.32" + attribute \src "ls180.v:937.12-937.32" wire width 32 \main_converter_dat_r - attribute \src "ls180.v:933.6-933.26" + attribute \src "ls180.v:936.6-936.26" wire \main_converter_reset - attribute \src "ls180.v:931.5-931.24" + attribute \src "ls180.v:934.5-934.24" wire \main_converter_skip - attribute \src "ls180.v:349.6-349.23" + attribute \src "ls180.v:352.6-352.23" wire \main_dfi_p0_act_n - attribute \src "ls180.v:340.13-340.32" + attribute \src "ls180.v:343.13-343.32" wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:341.12-341.28" + attribute \src "ls180.v:344.12-344.28" wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:342.6-342.23" + attribute \src "ls180.v:345.6-345.23" wire \main_dfi_p0_cas_n - attribute \src "ls180.v:346.6-346.21" + attribute \src "ls180.v:349.6-349.21" wire \main_dfi_p0_cke - attribute \src "ls180.v:343.6-343.22" + attribute \src "ls180.v:346.6-346.22" wire \main_dfi_p0_cs_n - attribute \src "ls180.v:347.6-347.21" + attribute \src "ls180.v:350.6-350.21" wire \main_dfi_p0_odt - attribute \src "ls180.v:344.6-344.23" + attribute \src "ls180.v:347.6-347.23" wire \main_dfi_p0_ras_n - attribute \src "ls180.v:354.12-354.30" + attribute \src "ls180.v:357.12-357.30" wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:353.6-353.27" + attribute \src "ls180.v:356.6-356.27" wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:355.5-355.29" + attribute \src "ls180.v:358.5-358.29" wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:348.6-348.25" + attribute \src "ls180.v:351.6-351.25" wire \main_dfi_p0_reset_n - attribute \src "ls180.v:345.6-345.22" + attribute \src "ls180.v:348.6-348.22" wire \main_dfi_p0_we_n - attribute \src "ls180.v:350.13-350.31" + attribute \src "ls180.v:353.13-353.31" wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:351.6-351.27" + attribute \src "ls180.v:354.6-354.27" wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:352.12-352.35" + attribute \src "ls180.v:355.12-355.35" wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1172.12-1172.22" + attribute \src "ls180.v:1175.12-1175.22" wire width 24 \main_dummy - attribute \src "ls180.v:1082.12-1082.45" + attribute \src "ls180.v:1085.12-1085.45" wire width 16 \main_gpiotristateasic0_oe_storage - attribute \src "ls180.v:1084.12-1084.46" + attribute \src "ls180.v:1087.12-1087.46" wire width 16 \main_gpiotristateasic0_out_storage - attribute \src "ls180.v:1085.13-1085.42" + attribute \src "ls180.v:1088.13-1088.42" wire width 16 \main_gpiotristateasic0_pads_i - attribute \src "ls180.v:1086.13-1086.42" + attribute \src "ls180.v:1089.13-1089.42" wire width 16 \main_gpiotristateasic0_pads_o - attribute \src "ls180.v:1087.13-1087.43" + attribute \src "ls180.v:1090.13-1090.43" wire width 16 \main_gpiotristateasic0_pads_oe - attribute \src "ls180.v:1083.12-1083.41" + attribute \src "ls180.v:1086.12-1086.41" wire width 16 \main_gpiotristateasic0_status - attribute \src "ls180.v:1089.5-1089.33" + attribute \src "ls180.v:1092.5-1092.33" wire \main_gpiotristateasic1_oe_re - attribute \src "ls180.v:1088.12-1088.45" + attribute \src "ls180.v:1091.12-1091.45" wire width 16 \main_gpiotristateasic1_oe_storage - attribute \src "ls180.v:1093.5-1093.34" + attribute \src "ls180.v:1096.5-1096.34" wire \main_gpiotristateasic1_out_re - attribute \src "ls180.v:1092.12-1092.46" + attribute \src "ls180.v:1095.12-1095.46" wire width 16 \main_gpiotristateasic1_out_storage - attribute \src "ls180.v:1094.13-1094.42" + attribute \src "ls180.v:1097.13-1097.42" wire width 16 \main_gpiotristateasic1_pads_i - attribute \src "ls180.v:1095.13-1095.42" + attribute \src "ls180.v:1098.13-1098.42" wire width 16 \main_gpiotristateasic1_pads_o - attribute \src "ls180.v:1096.13-1096.43" + attribute \src "ls180.v:1099.13-1099.43" wire width 16 \main_gpiotristateasic1_pads_oe - attribute \src "ls180.v:1090.12-1090.41" + attribute \src "ls180.v:1093.12-1093.41" wire width 16 \main_gpiotristateasic1_status - attribute \src "ls180.v:1091.6-1091.31" + attribute \src "ls180.v:1094.6-1094.31" wire \main_gpiotristateasic1_we - attribute \src "ls180.v:1194.6-1194.17" + attribute \src "ls180.v:1197.6-1197.17" wire \main_i2c_oe - attribute \src "ls180.v:1197.5-1197.16" + attribute \src "ls180.v:1200.5-1200.16" wire \main_i2c_re - attribute \src "ls180.v:1193.6-1193.18" + attribute \src "ls180.v:1196.6-1196.18" wire \main_i2c_scl - attribute \src "ls180.v:1195.6-1195.19" - wire \main_i2c_sda0 attribute \src "ls180.v:1198.6-1198.19" + wire \main_i2c_sda0 + attribute \src "ls180.v:1201.6-1201.19" wire \main_i2c_sda1 - attribute \src "ls180.v:1199.6-1199.21" + attribute \src "ls180.v:1202.6-1202.21" wire \main_i2c_status - attribute \src "ls180.v:1196.11-1196.27" + attribute \src "ls180.v:1199.11-1199.27" wire width 3 \main_i2c_storage - attribute \src "ls180.v:1200.6-1200.17" + attribute \src "ls180.v:1203.6-1203.17" wire \main_i2c_we - attribute \src "ls180.v:339.5-339.17" + attribute \src "ls180.v:342.5-342.17" wire \main_int_rst - attribute \src "ls180.v:1660.6-1660.29" + attribute \src "ls180.v:1663.6-1663.29" wire \main_interface0_bus_ack - attribute \src "ls180.v:1654.13-1654.36" + attribute \src "ls180.v:1657.13-1657.36" wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1663.11-1663.34" + attribute \src "ls180.v:1666.11-1666.34" wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1662.11-1662.34" + attribute \src "ls180.v:1665.11-1665.34" wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1658.6-1658.29" + attribute \src "ls180.v:1661.6-1661.29" wire \main_interface0_bus_cyc - attribute \src "ls180.v:1656.13-1656.38" + attribute \src "ls180.v:1659.13-1659.38" wire width 64 \main_interface0_bus_dat_r - attribute \src "ls180.v:1655.13-1655.38" + attribute \src "ls180.v:1658.13-1658.38" wire width 64 \main_interface0_bus_dat_w - attribute \src "ls180.v:1664.6-1664.29" + attribute \src "ls180.v:1667.6-1667.29" wire \main_interface0_bus_err - attribute \src "ls180.v:1657.12-1657.35" + attribute \src "ls180.v:1660.12-1660.35" wire width 8 \main_interface0_bus_sel - attribute \src "ls180.v:1659.6-1659.29" + attribute \src "ls180.v:1662.6-1662.29" wire \main_interface0_bus_stb - attribute \src "ls180.v:1661.6-1661.28" + attribute \src "ls180.v:1664.6-1664.28" wire \main_interface0_bus_we - attribute \src "ls180.v:312.5-312.44" + attribute \src "ls180.v:315.5-315.44" wire \main_interface0_converted_interface_ack - attribute \src "ls180.v:306.13-306.52" + attribute \src "ls180.v:309.13-309.52" wire width 30 \main_interface0_converted_interface_adr - attribute \src "ls180.v:315.12-315.51" + attribute \src "ls180.v:318.12-318.51" wire width 2 \main_interface0_converted_interface_bte - attribute \src "ls180.v:314.12-314.51" + attribute \src "ls180.v:317.12-317.51" wire width 3 \main_interface0_converted_interface_cti - attribute \src "ls180.v:310.6-310.45" + attribute \src "ls180.v:313.6-313.45" wire \main_interface0_converted_interface_cyc - attribute \src "ls180.v:308.13-308.54" + attribute \src "ls180.v:311.13-311.54" wire width 64 \main_interface0_converted_interface_dat_r - attribute \src "ls180.v:307.13-307.54" + attribute \src "ls180.v:310.13-310.54" wire width 64 \main_interface0_converted_interface_dat_w - attribute \src "ls180.v:316.5-316.44" + attribute \src "ls180.v:319.5-319.44" wire \main_interface0_converted_interface_err - attribute \src "ls180.v:309.12-309.51" + attribute \src "ls180.v:312.12-312.51" wire width 8 \main_interface0_converted_interface_sel - attribute \src "ls180.v:311.6-311.45" + attribute \src "ls180.v:314.6-314.45" wire \main_interface0_converted_interface_stb - attribute \src "ls180.v:313.6-313.44" + attribute \src "ls180.v:316.6-316.44" wire \main_interface0_converted_interface_we - attribute \src "ls180.v:252.5-252.32" + attribute \src "ls180.v:255.5-255.32" wire \main_interface0_ram_bus_ack - attribute \src "ls180.v:246.13-246.40" + attribute \src "ls180.v:249.13-249.40" wire width 30 \main_interface0_ram_bus_adr - attribute \src "ls180.v:255.12-255.39" + attribute \src "ls180.v:258.12-258.39" wire width 2 \main_interface0_ram_bus_bte - attribute \src "ls180.v:254.12-254.39" + attribute \src "ls180.v:257.12-257.39" wire width 3 \main_interface0_ram_bus_cti - attribute \src "ls180.v:250.6-250.33" + attribute \src "ls180.v:253.6-253.33" wire \main_interface0_ram_bus_cyc - attribute \src "ls180.v:248.13-248.42" + attribute \src "ls180.v:251.13-251.42" wire width 64 \main_interface0_ram_bus_dat_r - attribute \src "ls180.v:247.13-247.42" + attribute \src "ls180.v:250.13-250.42" wire width 64 \main_interface0_ram_bus_dat_w - attribute \src "ls180.v:256.5-256.32" + attribute \src "ls180.v:259.5-259.32" wire \main_interface0_ram_bus_err - attribute \src "ls180.v:249.12-249.39" + attribute \src "ls180.v:252.12-252.39" wire width 8 \main_interface0_ram_bus_sel - attribute \src "ls180.v:251.6-251.33" + attribute \src "ls180.v:254.6-254.33" wire \main_interface0_ram_bus_stb - attribute \src "ls180.v:253.6-253.32" + attribute \src "ls180.v:256.6-256.32" wire \main_interface0_ram_bus_we - attribute \src "ls180.v:1751.6-1751.29" + attribute \src "ls180.v:1754.6-1754.29" wire \main_interface1_bus_ack - attribute \src "ls180.v:1745.12-1745.35" + attribute \src "ls180.v:1748.12-1748.35" wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1754.11-1754.34" + attribute \src "ls180.v:1757.11-1757.34" wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1753.11-1753.34" + attribute \src "ls180.v:1756.11-1756.34" wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1749.5-1749.28" + attribute \src "ls180.v:1752.5-1752.28" wire \main_interface1_bus_cyc - attribute \src "ls180.v:1747.13-1747.38" + attribute \src "ls180.v:1750.13-1750.38" wire width 64 \main_interface1_bus_dat_r - attribute \src "ls180.v:1746.12-1746.37" + attribute \src "ls180.v:1749.12-1749.37" wire width 64 \main_interface1_bus_dat_w - attribute \src "ls180.v:1755.6-1755.29" + attribute \src "ls180.v:1758.6-1758.29" wire \main_interface1_bus_err - attribute \src "ls180.v:1748.11-1748.34" + attribute \src "ls180.v:1751.11-1751.34" wire width 8 \main_interface1_bus_sel - attribute \src "ls180.v:1750.5-1750.28" + attribute \src "ls180.v:1753.5-1753.28" wire \main_interface1_bus_stb - attribute \src "ls180.v:1752.5-1752.27" + attribute \src "ls180.v:1755.5-1755.27" wire \main_interface1_bus_we - attribute \src "ls180.v:327.5-327.44" + attribute \src "ls180.v:330.5-330.44" wire \main_interface1_converted_interface_ack - attribute \src "ls180.v:321.13-321.52" + attribute \src "ls180.v:324.13-324.52" wire width 30 \main_interface1_converted_interface_adr - attribute \src "ls180.v:330.12-330.51" + attribute \src "ls180.v:333.12-333.51" wire width 2 \main_interface1_converted_interface_bte - attribute \src "ls180.v:329.12-329.51" + attribute \src "ls180.v:332.12-332.51" wire width 3 \main_interface1_converted_interface_cti - attribute \src "ls180.v:325.6-325.45" + attribute \src "ls180.v:328.6-328.45" wire \main_interface1_converted_interface_cyc - attribute \src "ls180.v:323.13-323.54" + attribute \src "ls180.v:326.13-326.54" wire width 64 \main_interface1_converted_interface_dat_r - attribute \src "ls180.v:322.13-322.54" + attribute \src "ls180.v:325.13-325.54" wire width 64 \main_interface1_converted_interface_dat_w - attribute \src "ls180.v:331.5-331.44" + attribute \src "ls180.v:334.5-334.44" wire \main_interface1_converted_interface_err - attribute \src "ls180.v:324.12-324.51" + attribute \src "ls180.v:327.12-327.51" wire width 8 \main_interface1_converted_interface_sel - attribute \src "ls180.v:326.6-326.45" + attribute \src "ls180.v:329.6-329.45" wire \main_interface1_converted_interface_stb - attribute \src "ls180.v:328.6-328.44" + attribute \src "ls180.v:331.6-331.44" wire \main_interface1_converted_interface_we - attribute \src "ls180.v:267.5-267.32" + attribute \src "ls180.v:270.5-270.32" wire \main_interface1_ram_bus_ack - attribute \src "ls180.v:261.13-261.40" + attribute \src "ls180.v:264.13-264.40" wire width 30 \main_interface1_ram_bus_adr - attribute \src "ls180.v:270.12-270.39" + attribute \src "ls180.v:273.12-273.39" wire width 2 \main_interface1_ram_bus_bte - attribute \src "ls180.v:269.12-269.39" + attribute \src "ls180.v:272.12-272.39" wire width 3 \main_interface1_ram_bus_cti - attribute \src "ls180.v:265.6-265.33" + attribute \src "ls180.v:268.6-268.33" wire \main_interface1_ram_bus_cyc - attribute \src "ls180.v:263.13-263.42" + attribute \src "ls180.v:266.13-266.42" wire width 64 \main_interface1_ram_bus_dat_r - attribute \src "ls180.v:262.13-262.42" + attribute \src "ls180.v:265.13-265.42" wire width 64 \main_interface1_ram_bus_dat_w - attribute \src "ls180.v:271.5-271.32" + attribute \src "ls180.v:274.5-274.32" wire \main_interface1_ram_bus_err - attribute \src "ls180.v:264.12-264.39" + attribute \src "ls180.v:267.12-267.39" wire width 8 \main_interface1_ram_bus_sel - attribute \src "ls180.v:266.6-266.33" + attribute \src "ls180.v:269.6-269.33" wire \main_interface1_ram_bus_stb - attribute \src "ls180.v:268.6-268.32" + attribute \src "ls180.v:271.6-271.32" wire \main_interface1_ram_bus_we - attribute \src "ls180.v:282.5-282.32" + attribute \src "ls180.v:285.5-285.32" wire \main_interface2_ram_bus_ack - attribute \src "ls180.v:276.13-276.40" + attribute \src "ls180.v:279.13-279.40" wire width 30 \main_interface2_ram_bus_adr - attribute \src "ls180.v:285.12-285.39" + attribute \src "ls180.v:288.12-288.39" wire width 2 \main_interface2_ram_bus_bte - attribute \src "ls180.v:284.12-284.39" + attribute \src "ls180.v:287.12-287.39" wire width 3 \main_interface2_ram_bus_cti - attribute \src "ls180.v:280.6-280.33" + attribute \src "ls180.v:283.6-283.33" wire \main_interface2_ram_bus_cyc - attribute \src "ls180.v:278.13-278.42" + attribute \src "ls180.v:281.13-281.42" wire width 64 \main_interface2_ram_bus_dat_r - attribute \src "ls180.v:277.13-277.42" + attribute \src "ls180.v:280.13-280.42" wire width 64 \main_interface2_ram_bus_dat_w - attribute \src "ls180.v:286.5-286.32" + attribute \src "ls180.v:289.5-289.32" wire \main_interface2_ram_bus_err - attribute \src "ls180.v:279.12-279.39" + attribute \src "ls180.v:282.12-282.39" wire width 8 \main_interface2_ram_bus_sel - attribute \src "ls180.v:281.6-281.33" + attribute \src "ls180.v:284.6-284.33" wire \main_interface2_ram_bus_stb - attribute \src "ls180.v:283.6-283.32" + attribute \src "ls180.v:286.6-286.32" wire \main_interface2_ram_bus_we - attribute \src "ls180.v:297.5-297.32" + attribute \src "ls180.v:300.5-300.32" wire \main_interface3_ram_bus_ack - attribute \src "ls180.v:291.13-291.40" + attribute \src "ls180.v:294.13-294.40" wire width 30 \main_interface3_ram_bus_adr - attribute \src "ls180.v:300.12-300.39" + attribute \src "ls180.v:303.12-303.39" wire width 2 \main_interface3_ram_bus_bte - attribute \src "ls180.v:299.12-299.39" + attribute \src "ls180.v:302.12-302.39" wire width 3 \main_interface3_ram_bus_cti - attribute \src "ls180.v:295.6-295.33" + attribute \src "ls180.v:298.6-298.33" wire \main_interface3_ram_bus_cyc - attribute \src "ls180.v:293.13-293.42" + attribute \src "ls180.v:296.13-296.42" wire width 64 \main_interface3_ram_bus_dat_r - attribute \src "ls180.v:292.13-292.42" + attribute \src "ls180.v:295.13-295.42" wire width 64 \main_interface3_ram_bus_dat_w - attribute \src "ls180.v:301.5-301.32" + attribute \src "ls180.v:304.5-304.32" wire \main_interface3_ram_bus_err - attribute \src "ls180.v:294.12-294.39" + attribute \src "ls180.v:297.12-297.39" wire width 8 \main_interface3_ram_bus_sel - attribute \src "ls180.v:296.6-296.33" + attribute \src "ls180.v:299.6-299.33" wire \main_interface3_ram_bus_stb - attribute \src "ls180.v:298.6-298.32" + attribute \src "ls180.v:301.6-301.32" wire \main_interface3_ram_bus_we - attribute \src "ls180.v:215.12-215.32" + attribute \src "ls180.v:218.12-218.32" wire width 6 \main_libresocsim_adr attribute \src "ls180.v:62.6-62.32" wire \main_libresocsim_bus_error @@ -245881,35 +248404,35 @@ module \ls180 wire width 32 \main_libresocsim_bus_errors_status attribute \src "ls180.v:60.6-60.36" wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:216.13-216.35" + attribute \src "ls180.v:219.13-219.35" wire width 64 \main_libresocsim_dat_r - attribute \src "ls180.v:218.13-218.35" + attribute \src "ls180.v:221.13-221.35" wire width 64 \main_libresocsim_dat_w - attribute \src "ls180.v:224.5-224.27" + attribute \src "ls180.v:227.5-227.27" wire \main_libresocsim_en_re - attribute \src "ls180.v:223.5-223.32" + attribute \src "ls180.v:226.5-226.32" wire \main_libresocsim_en_storage - attribute \src "ls180.v:240.6-240.45" + attribute \src "ls180.v:243.6-243.45" wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:239.6-239.46" + attribute \src "ls180.v:242.6-242.46" wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:242.6-242.45" + attribute \src "ls180.v:245.6-245.45" wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:241.6-241.46" + attribute \src "ls180.v:244.6-244.46" wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:244.5-244.37" + attribute \src "ls180.v:247.5-247.37" wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:236.6-236.44" + attribute \src "ls180.v:239.6-239.44" wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:235.6-235.45" + attribute \src "ls180.v:238.6-238.45" wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:238.6-238.44" + attribute \src "ls180.v:241.6-241.44" wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:237.6-237.45" + attribute \src "ls180.v:240.6-240.45" wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:243.5-243.42" + attribute \src "ls180.v:246.5-246.42" wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:229.6-229.26" + attribute \src "ls180.v:232.6-232.26" wire \main_libresocsim_irq attribute \src "ls180.v:165.6-165.32" wire \main_libresocsim_libresoc0 @@ -245919,65 +248442,71 @@ module \ls180 wire width 64 \main_libresocsim_libresoc2 attribute \src "ls180.v:169.12-169.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:179.12-179.66" + attribute \src "ls180.v:182.12-182.66" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:180.13-180.67" + attribute \src "ls180.v:183.13-183.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:181.13-181.68" + attribute \src "ls180.v:184.13-184.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:171.6-171.61" + attribute \src "ls180.v:178.6-178.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:172.5-172.62" + attribute \src "ls180.v:179.5-179.62" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:173.6-173.63" + attribute \src "ls180.v:180.6-180.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:174.6-174.64" + attribute \src "ls180.v:181.6-181.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:175.6-175.64" + attribute \src "ls180.v:171.6-171.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:176.5-176.65" + attribute \src "ls180.v:172.5-172.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:177.6-177.66" + attribute \src "ls180.v:173.6-173.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:178.6-178.67" + attribute \src "ls180.v:174.6-174.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:182.13-182.68" + attribute \src "ls180.v:175.11-175.72" + wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i + attribute \src "ls180.v:176.12-176.73" + wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o + attribute \src "ls180.v:177.6-177.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + attribute \src "ls180.v:194.13-194.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:191.12-191.68" + attribute \src "ls180.v:203.12-203.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:188.6-188.65" + attribute \src "ls180.v:200.6-200.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:190.6-190.63" + attribute \src "ls180.v:202.6-202.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:189.6-189.64" + attribute \src "ls180.v:201.6-201.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:192.12-192.68" + attribute \src "ls180.v:204.12-204.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:183.12-183.70" + attribute \src "ls180.v:195.12-195.70" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:184.13-184.71" + attribute \src "ls180.v:196.13-196.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:185.6-185.65" + attribute \src "ls180.v:197.6-197.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:187.6-187.65" + attribute \src "ls180.v:199.6-199.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:186.6-186.64" + attribute \src "ls180.v:198.6-198.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:194.6-194.67" + attribute \src "ls180.v:185.6-185.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:196.6-196.68" + attribute \src "ls180.v:187.6-187.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:197.5-197.67" + attribute \src "ls180.v:188.6-188.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:195.6-195.68" + attribute \src "ls180.v:186.6-186.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:199.6-199.67" + attribute \src "ls180.v:189.6-189.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:201.6-201.68" + attribute \src "ls180.v:191.6-191.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:202.5-202.67" + attribute \src "ls180.v:192.6-192.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:200.6-200.68" + attribute \src "ls180.v:190.6-190.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack @@ -246185,35 +248714,35 @@ module \ls180 wire \main_libresocsim_libresoc_xics_ics_stb attribute \src "ls180.v:104.5-104.42" wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:220.5-220.29" + attribute \src "ls180.v:223.5-223.29" wire \main_libresocsim_load_re - attribute \src "ls180.v:219.12-219.41" + attribute \src "ls180.v:222.12-222.41" wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:210.5-210.33" + attribute \src "ls180.v:213.5-213.33" wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:204.13-204.41" + attribute \src "ls180.v:207.13-207.41" wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:213.12-213.40" + attribute \src "ls180.v:216.12-216.40" wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:212.12-212.40" + attribute \src "ls180.v:215.12-215.40" wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:208.6-208.34" + attribute \src "ls180.v:211.6-211.34" wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:206.13-206.43" + attribute \src "ls180.v:209.13-209.43" wire width 64 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:205.13-205.43" + attribute \src "ls180.v:208.13-208.43" wire width 64 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:214.5-214.33" + attribute \src "ls180.v:217.5-217.33" wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:207.12-207.40" + attribute \src "ls180.v:210.12-210.40" wire width 8 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:209.6-209.34" + attribute \src "ls180.v:212.6-212.34" wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:211.6-211.33" + attribute \src "ls180.v:214.6-214.33" wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:222.5-222.31" + attribute \src "ls180.v:225.5-225.31" wire \main_libresocsim_reload_re - attribute \src "ls180.v:221.12-221.43" + attribute \src "ls180.v:224.12-224.43" wire width 32 \main_libresocsim_reload_storage attribute \src "ls180.v:61.6-61.28" wire \main_libresocsim_reset @@ -246225,3289 +248754,3289 @@ module \ls180 wire \main_libresocsim_scratch_re attribute \src "ls180.v:57.12-57.44" wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:226.5-226.37" + attribute \src "ls180.v:229.5-229.37" wire \main_libresocsim_update_value_re - attribute \src "ls180.v:225.5-225.42" + attribute \src "ls180.v:228.5-228.42" wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:245.12-245.34" + attribute \src "ls180.v:248.12-248.34" wire width 32 \main_libresocsim_value - attribute \src "ls180.v:227.12-227.41" + attribute \src "ls180.v:230.12-230.41" wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:228.6-228.31" + attribute \src "ls180.v:231.6-231.31" wire \main_libresocsim_value_we - attribute \src "ls180.v:217.11-217.30" + attribute \src "ls180.v:220.11-220.30" wire width 8 \main_libresocsim_we - attribute \src "ls180.v:233.5-233.32" + attribute \src "ls180.v:236.5-236.32" wire \main_libresocsim_zero_clear - attribute \src "ls180.v:234.5-234.38" + attribute \src "ls180.v:237.5-237.38" wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:231.5-231.34" + attribute \src "ls180.v:234.5-234.34" wire \main_libresocsim_zero_pending - attribute \src "ls180.v:230.6-230.34" + attribute \src "ls180.v:233.6-233.34" wire \main_libresocsim_zero_status - attribute \src "ls180.v:232.6-232.35" + attribute \src "ls180.v:235.6-235.35" wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:929.6-929.26" + attribute \src "ls180.v:932.6-932.26" wire \main_litedram_wb_ack - attribute \src "ls180.v:923.12-923.32" + attribute \src "ls180.v:926.12-926.32" wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:927.5-927.25" + attribute \src "ls180.v:930.5-930.25" wire \main_litedram_wb_cyc - attribute \src "ls180.v:925.13-925.35" + attribute \src "ls180.v:928.13-928.35" wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:924.12-924.34" + attribute \src "ls180.v:927.12-927.34" wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:926.11-926.31" + attribute \src "ls180.v:929.11-929.31" wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:928.5-928.25" + attribute \src "ls180.v:931.5-931.25" wire \main_litedram_wb_stb - attribute \src "ls180.v:930.5-930.24" + attribute \src "ls180.v:933.5-933.24" wire \main_litedram_wb_we - attribute \src "ls180.v:1171.13-1171.20" + attribute \src "ls180.v:1174.13-1174.20" wire width 24 \main_nc - attribute \src "ls180.v:890.6-890.24" + attribute \src "ls180.v:893.6-893.24" wire \main_port_cmd_last - attribute \src "ls180.v:892.13-892.39" + attribute \src "ls180.v:895.13-895.39" wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:891.6-891.30" + attribute \src "ls180.v:894.6-894.30" wire \main_port_cmd_payload_we - attribute \src "ls180.v:889.6-889.25" + attribute \src "ls180.v:892.6-892.25" wire \main_port_cmd_ready - attribute \src "ls180.v:888.6-888.25" + attribute \src "ls180.v:891.6-891.25" wire \main_port_cmd_valid - attribute \src "ls180.v:887.6-887.21" + attribute \src "ls180.v:890.6-890.21" wire \main_port_flush - attribute \src "ls180.v:899.13-899.41" + attribute \src "ls180.v:902.13-902.41" wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:898.6-898.27" + attribute \src "ls180.v:901.6-901.27" wire \main_port_rdata_ready - attribute \src "ls180.v:897.6-897.27" + attribute \src "ls180.v:900.6-900.27" wire \main_port_rdata_valid - attribute \src "ls180.v:895.13-895.41" + attribute \src "ls180.v:898.13-898.41" wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:896.12-896.38" + attribute \src "ls180.v:899.12-899.38" wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:894.6-894.27" + attribute \src "ls180.v:897.6-897.27" wire \main_port_wdata_ready - attribute \src "ls180.v:893.6-893.27" + attribute \src "ls180.v:896.6-896.27" wire \main_port_wdata_valid - attribute \src "ls180.v:1176.12-1176.29" + attribute \src "ls180.v:1179.12-1179.29" wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1173.6-1173.22" + attribute \src "ls180.v:1176.6-1176.22" wire \main_pwm0_enable - attribute \src "ls180.v:1178.5-1178.24" + attribute \src "ls180.v:1181.5-1181.24" wire \main_pwm0_enable_re - attribute \src "ls180.v:1177.5-1177.29" + attribute \src "ls180.v:1180.5-1180.29" wire \main_pwm0_enable_storage - attribute \src "ls180.v:1175.13-1175.29" + attribute \src "ls180.v:1178.13-1178.29" wire width 32 \main_pwm0_period - attribute \src "ls180.v:1182.5-1182.24" + attribute \src "ls180.v:1185.5-1185.24" wire \main_pwm0_period_re - attribute \src "ls180.v:1181.12-1181.36" + attribute \src "ls180.v:1184.12-1184.36" wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1174.13-1174.28" + attribute \src "ls180.v:1177.13-1177.28" wire width 32 \main_pwm0_width - attribute \src "ls180.v:1180.5-1180.23" + attribute \src "ls180.v:1183.5-1183.23" wire \main_pwm0_width_re - attribute \src "ls180.v:1179.12-1179.35" + attribute \src "ls180.v:1182.12-1182.35" wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1186.12-1186.29" + attribute \src "ls180.v:1189.12-1189.29" wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1183.6-1183.22" + attribute \src "ls180.v:1186.6-1186.22" wire \main_pwm1_enable - attribute \src "ls180.v:1188.5-1188.24" + attribute \src "ls180.v:1191.5-1191.24" wire \main_pwm1_enable_re - attribute \src "ls180.v:1187.5-1187.29" + attribute \src "ls180.v:1190.5-1190.29" wire \main_pwm1_enable_storage - attribute \src "ls180.v:1185.13-1185.29" + attribute \src "ls180.v:1188.13-1188.29" wire width 32 \main_pwm1_period - attribute \src "ls180.v:1192.5-1192.24" + attribute \src "ls180.v:1195.5-1195.24" wire \main_pwm1_period_re - attribute \src "ls180.v:1191.12-1191.36" + attribute \src "ls180.v:1194.12-1194.36" wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1184.13-1184.28" + attribute \src "ls180.v:1187.13-1187.28" wire width 32 \main_pwm1_width - attribute \src "ls180.v:1190.5-1190.23" + attribute \src "ls180.v:1193.5-1193.23" wire \main_pwm1_width_re - attribute \src "ls180.v:1189.12-1189.35" + attribute \src "ls180.v:1192.12-1192.35" wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:356.11-356.25" + attribute \src "ls180.v:359.11-359.25" wire width 3 \main_rddata_en - attribute \src "ls180.v:1714.11-1714.43" + attribute \src "ls180.v:1717.11-1717.43" wire width 3 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1715.6-1715.42" + attribute \src "ls180.v:1718.6-1718.42" wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1705.6-1705.43" + attribute \src "ls180.v:1708.6-1708.43" wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1706.6-1706.42" + attribute \src "ls180.v:1709.6-1709.42" wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1707.12-1707.56" + attribute \src "ls180.v:1710.12-1710.56" wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1704.6-1704.43" + attribute \src "ls180.v:1707.6-1707.43" wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1703.6-1703.43" + attribute \src "ls180.v:1706.6-1706.43" wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1710.5-1710.44" + attribute \src "ls180.v:1713.5-1713.44" wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1711.5-1711.43" + attribute \src "ls180.v:1714.5-1714.43" wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1712.12-1712.58" + attribute \src "ls180.v:1715.12-1715.58" wire width 64 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1713.11-1713.70" + attribute \src "ls180.v:1716.11-1716.70" wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1709.6-1709.45" + attribute \src "ls180.v:1712.6-1712.45" wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1708.6-1708.45" + attribute \src "ls180.v:1711.6-1711.45" wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1716.5-1716.42" + attribute \src "ls180.v:1719.5-1719.42" wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1689.11-1689.40" + attribute \src "ls180.v:1692.11-1692.40" wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1694.6-1694.35" + attribute \src "ls180.v:1697.6-1697.35" wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1698.6-1698.41" + attribute \src "ls180.v:1701.6-1701.41" wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1699.6-1699.40" + attribute \src "ls180.v:1702.6-1702.40" wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1697.12-1697.54" + attribute \src "ls180.v:1700.12-1700.54" wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1701.6-1701.42" + attribute \src "ls180.v:1704.6-1704.42" wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1702.6-1702.41" + attribute \src "ls180.v:1705.6-1705.41" wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1700.12-1700.55" + attribute \src "ls180.v:1703.12-1703.55" wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1686.11-1686.38" + attribute \src "ls180.v:1689.11-1689.38" wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1688.11-1688.40" + attribute \src "ls180.v:1691.11-1691.40" wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1695.12-1695.44" + attribute \src "ls180.v:1698.12-1698.44" wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1696.12-1696.46" + attribute \src "ls180.v:1699.12-1699.46" wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1687.5-1687.34" + attribute \src "ls180.v:1690.5-1690.34" wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1672.6-1672.38" + attribute \src "ls180.v:1675.6-1675.38" wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1673.6-1673.37" + attribute \src "ls180.v:1676.6-1676.37" wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1674.12-1674.51" + attribute \src "ls180.v:1677.12-1677.51" wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1671.6-1671.38" + attribute \src "ls180.v:1674.6-1674.38" wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1670.6-1670.38" + attribute \src "ls180.v:1673.6-1673.38" wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1677.6-1677.40" + attribute \src "ls180.v:1680.6-1680.40" wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1678.6-1678.39" + attribute \src "ls180.v:1681.6-1681.39" wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1679.12-1679.53" + attribute \src "ls180.v:1682.12-1682.53" wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1676.6-1676.40" + attribute \src "ls180.v:1679.6-1679.40" wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1675.6-1675.40" + attribute \src "ls180.v:1678.6-1678.40" wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1684.12-1684.46" + attribute \src "ls180.v:1687.12-1687.46" wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1685.12-1685.47" + attribute \src "ls180.v:1688.12-1688.47" wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1682.6-1682.39" + attribute \src "ls180.v:1685.6-1685.39" wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1683.6-1683.45" + attribute \src "ls180.v:1686.6-1686.45" wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1680.6-1680.39" + attribute \src "ls180.v:1683.6-1683.39" wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1681.6-1681.45" + attribute \src "ls180.v:1684.6-1684.45" wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1690.11-1690.43" + attribute \src "ls180.v:1693.11-1693.43" wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1691.12-1691.46" + attribute \src "ls180.v:1694.12-1694.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1693.12-1693.46" + attribute \src "ls180.v:1696.12-1696.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1692.6-1692.37" + attribute \src "ls180.v:1695.6-1695.37" wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1667.6-1667.38" + attribute \src "ls180.v:1670.6-1670.38" wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1668.6-1668.37" + attribute \src "ls180.v:1671.6-1671.37" wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1724.12-1724.54" + attribute \src "ls180.v:1727.12-1727.54" wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1669.12-1669.52" + attribute \src "ls180.v:1672.12-1672.52" wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1725.12-1725.52" + attribute \src "ls180.v:1728.12-1728.52" wire width 64 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1666.6-1666.39" + attribute \src "ls180.v:1669.6-1669.39" wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1723.6-1723.39" + attribute \src "ls180.v:1726.6-1726.39" wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1665.6-1665.39" + attribute \src "ls180.v:1668.6-1668.39" wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1722.5-1722.38" + attribute \src "ls180.v:1725.5-1725.38" wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1719.6-1719.42" + attribute \src "ls180.v:1722.6-1722.42" wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1720.6-1720.41" + attribute \src "ls180.v:1723.6-1723.41" wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1721.13-1721.56" + attribute \src "ls180.v:1724.13-1724.56" wire width 64 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1718.6-1718.42" + attribute \src "ls180.v:1721.6-1721.42" wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1717.6-1717.42" + attribute \src "ls180.v:1720.6-1720.42" wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1741.13-1741.52" + attribute \src "ls180.v:1744.13-1744.52" wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1732.5-1732.47" + attribute \src "ls180.v:1735.5-1735.47" wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1731.12-1731.59" + attribute \src "ls180.v:1734.12-1734.59" wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1736.5-1736.49" + attribute \src "ls180.v:1739.5-1739.49" wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1735.5-1735.54" + attribute \src "ls180.v:1738.5-1738.54" wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1743.13-1743.54" + attribute \src "ls180.v:1746.13-1746.54" wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1734.5-1734.49" + attribute \src "ls180.v:1737.5-1737.49" wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1733.12-1733.61" + attribute \src "ls180.v:1736.12-1736.61" wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1740.5-1740.47" + attribute \src "ls180.v:1743.5-1743.47" wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1739.5-1739.52" + attribute \src "ls180.v:1742.5-1742.52" wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1742.12-1742.53" + attribute \src "ls180.v:1745.12-1745.53" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1962.12-1962.79" + attribute \src "ls180.v:1965.12-1965.79" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1963.5-1963.75" + attribute \src "ls180.v:1966.5-1966.75" wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1744.6-1744.46" + attribute \src "ls180.v:1747.6-1747.46" wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1728.6-1728.51" + attribute \src "ls180.v:1731.6-1731.51" wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1729.6-1729.50" + attribute \src "ls180.v:1732.6-1732.50" wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1730.13-1730.65" + attribute \src "ls180.v:1733.13-1733.65" wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1727.5-1727.50" + attribute \src "ls180.v:1730.5-1730.50" wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1726.6-1726.51" + attribute \src "ls180.v:1729.6-1729.51" wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1737.5-1737.46" + attribute \src "ls180.v:1740.5-1740.46" wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1738.6-1738.43" + attribute \src "ls180.v:1741.6-1741.43" wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1506.5-1506.31" + attribute \src "ls180.v:1509.5-1509.31" wire \main_sdcore_block_count_re - attribute \src "ls180.v:1505.12-1505.43" + attribute \src "ls180.v:1508.12-1508.43" wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1504.5-1504.32" + attribute \src "ls180.v:1507.5-1507.32" wire \main_sdcore_block_length_re - attribute \src "ls180.v:1503.11-1503.43" + attribute \src "ls180.v:1506.11-1506.43" wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1490.5-1490.32" + attribute \src "ls180.v:1493.5-1493.32" wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1489.12-1489.44" + attribute \src "ls180.v:1492.12-1492.44" wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1492.5-1492.31" + attribute \src "ls180.v:1495.5-1495.31" wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1491.12-1491.43" + attribute \src "ls180.v:1494.12-1494.43" wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1645.11-1645.32" + attribute \src "ls180.v:1648.11-1648.32" wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1946.11-1946.55" + attribute \src "ls180.v:1949.11-1949.55" wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1947.5-1947.52" + attribute \src "ls180.v:1950.5-1950.52" wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1646.5-1646.25" + attribute \src "ls180.v:1649.5-1649.25" wire \main_sdcore_cmd_done - attribute \src "ls180.v:1942.5-1942.48" + attribute \src "ls180.v:1945.5-1945.48" wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1943.5-1943.51" + attribute \src "ls180.v:1946.5-1946.51" wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1647.5-1647.26" + attribute \src "ls180.v:1650.5-1650.26" wire \main_sdcore_cmd_error - attribute \src "ls180.v:1950.5-1950.49" + attribute \src "ls180.v:1953.5-1953.49" wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1951.5-1951.52" + attribute \src "ls180.v:1954.5-1954.52" wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1499.12-1499.40" + attribute \src "ls180.v:1502.12-1502.40" wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1500.6-1500.30" + attribute \src "ls180.v:1503.6-1503.30" wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1497.13-1497.44" + attribute \src "ls180.v:1500.13-1500.44" wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1958.13-1958.67" + attribute \src "ls180.v:1961.13-1961.67" wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1959.5-1959.62" + attribute \src "ls180.v:1962.5-1962.62" wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1498.6-1498.33" + attribute \src "ls180.v:1501.6-1501.33" wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1494.6-1494.28" + attribute \src "ls180.v:1497.6-1497.28" wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1493.6-1493.29" + attribute \src "ls180.v:1496.6-1496.29" wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1496.5-1496.27" + attribute \src "ls180.v:1499.5-1499.27" wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1495.6-1495.29" + attribute \src "ls180.v:1498.6-1498.29" wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1648.5-1648.28" + attribute \src "ls180.v:1651.5-1651.28" wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1952.5-1952.51" + attribute \src "ls180.v:1955.5-1955.51" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1953.5-1953.54" + attribute \src "ls180.v:1956.5-1956.54" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1644.12-1644.32" + attribute \src "ls180.v:1647.12-1647.32" wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1606.11-1606.40" + attribute \src "ls180.v:1609.11-1609.40" wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1612.5-1612.39" + attribute \src "ls180.v:1615.5-1615.39" wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1611.12-1611.46" + attribute \src "ls180.v:1614.12-1614.46" wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1607.12-1607.50" + attribute \src "ls180.v:1610.12-1610.50" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1608.13-1608.51" + attribute \src "ls180.v:1611.13-1611.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1609.13-1609.51" + attribute \src "ls180.v:1612.13-1612.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1613.6-1613.43" + attribute \src "ls180.v:1616.6-1616.43" wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1610.12-1610.46" + attribute \src "ls180.v:1613.12-1613.46" wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1619.5-1619.39" + attribute \src "ls180.v:1622.5-1622.39" wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1618.12-1618.46" + attribute \src "ls180.v:1621.12-1621.46" wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1614.12-1614.50" + attribute \src "ls180.v:1617.12-1617.50" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1615.13-1615.51" + attribute \src "ls180.v:1618.13-1618.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1616.13-1616.51" + attribute \src "ls180.v:1619.13-1619.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1620.6-1620.43" + attribute \src "ls180.v:1623.6-1623.43" wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1617.12-1617.46" + attribute \src "ls180.v:1620.12-1620.46" wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1626.5-1626.39" + attribute \src "ls180.v:1629.5-1629.39" wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1625.12-1625.46" + attribute \src "ls180.v:1628.12-1628.46" wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1621.12-1621.50" + attribute \src "ls180.v:1624.12-1624.50" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1622.13-1622.51" + attribute \src "ls180.v:1625.13-1625.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1623.13-1623.51" + attribute \src "ls180.v:1626.13-1626.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1627.6-1627.43" + attribute \src "ls180.v:1630.6-1630.43" wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1624.12-1624.46" + attribute \src "ls180.v:1627.12-1627.46" wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1633.5-1633.39" + attribute \src "ls180.v:1636.5-1636.39" wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1632.12-1632.46" + attribute \src "ls180.v:1635.12-1635.46" wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1628.12-1628.50" + attribute \src "ls180.v:1631.12-1631.50" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1629.13-1629.51" + attribute \src "ls180.v:1632.13-1632.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1630.13-1630.51" + attribute \src "ls180.v:1633.13-1633.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1634.6-1634.43" + attribute \src "ls180.v:1637.6-1637.43" wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1631.12-1631.46" + attribute \src "ls180.v:1634.12-1634.46" wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1635.12-1635.45" + attribute \src "ls180.v:1638.12-1638.45" wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1636.12-1636.45" + attribute \src "ls180.v:1639.12-1639.45" wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1637.12-1637.45" + attribute \src "ls180.v:1640.12-1640.45" wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1638.12-1638.45" + attribute \src "ls180.v:1641.12-1641.45" wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1640.12-1640.43" + attribute \src "ls180.v:1643.12-1643.43" wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1641.12-1641.43" + attribute \src "ls180.v:1644.12-1644.43" wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1642.12-1642.43" + attribute \src "ls180.v:1645.12-1645.43" wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1643.12-1643.43" + attribute \src "ls180.v:1646.12-1646.43" wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1597.5-1597.41" + attribute \src "ls180.v:1600.5-1600.41" wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1598.5-1598.40" + attribute \src "ls180.v:1601.5-1601.40" wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1599.11-1599.54" + attribute \src "ls180.v:1602.11-1602.54" wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1596.5-1596.41" + attribute \src "ls180.v:1599.5-1599.41" wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1595.5-1595.41" + attribute \src "ls180.v:1598.5-1598.41" wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1602.5-1602.43" + attribute \src "ls180.v:1605.5-1605.43" wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1603.6-1603.43" + attribute \src "ls180.v:1606.6-1606.43" wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1604.12-1604.57" + attribute \src "ls180.v:1607.12-1607.57" wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1601.6-1601.44" + attribute \src "ls180.v:1604.6-1604.44" wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1600.5-1600.43" + attribute \src "ls180.v:1603.5-1603.43" wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1605.11-1605.40" + attribute \src "ls180.v:1608.11-1608.40" wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1639.5-1639.36" + attribute \src "ls180.v:1642.5-1642.36" wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1562.11-1562.41" + attribute \src "ls180.v:1565.11-1565.41" wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1938.11-1938.80" + attribute \src "ls180.v:1941.11-1941.80" wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1939.5-1939.77" + attribute \src "ls180.v:1942.5-1942.77" wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1568.6-1568.41" + attribute \src "ls180.v:1571.6-1571.41" wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1567.12-1567.47" + attribute \src "ls180.v:1570.12-1570.47" wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1563.12-1563.51" + attribute \src "ls180.v:1566.12-1566.51" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1564.13-1564.52" + attribute \src "ls180.v:1567.13-1567.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1565.13-1565.52" + attribute \src "ls180.v:1568.13-1568.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1569.6-1569.44" + attribute \src "ls180.v:1572.6-1572.44" wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1566.12-1566.47" + attribute \src "ls180.v:1569.12-1569.47" wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1575.6-1575.41" + attribute \src "ls180.v:1578.6-1578.41" wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1574.12-1574.47" + attribute \src "ls180.v:1577.12-1577.47" wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1570.12-1570.51" + attribute \src "ls180.v:1573.12-1573.51" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1571.13-1571.52" + attribute \src "ls180.v:1574.13-1574.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1572.13-1572.52" + attribute \src "ls180.v:1575.13-1575.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1576.6-1576.44" + attribute \src "ls180.v:1579.6-1579.44" wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1573.12-1573.47" + attribute \src "ls180.v:1576.12-1576.47" wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1582.6-1582.41" + attribute \src "ls180.v:1585.6-1585.41" wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1581.12-1581.47" + attribute \src "ls180.v:1584.12-1584.47" wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1577.12-1577.51" + attribute \src "ls180.v:1580.12-1580.51" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1578.13-1578.52" + attribute \src "ls180.v:1581.13-1581.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1579.13-1579.52" + attribute \src "ls180.v:1582.13-1582.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1583.6-1583.44" + attribute \src "ls180.v:1586.6-1586.44" wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1580.12-1580.47" + attribute \src "ls180.v:1583.12-1583.47" wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1589.6-1589.41" + attribute \src "ls180.v:1592.6-1592.41" wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1588.12-1588.47" + attribute \src "ls180.v:1591.12-1591.47" wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1584.12-1584.51" + attribute \src "ls180.v:1587.12-1587.51" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1585.13-1585.52" + attribute \src "ls180.v:1588.13-1588.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1586.13-1586.52" + attribute \src "ls180.v:1589.13-1589.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1590.6-1590.44" + attribute \src "ls180.v:1593.6-1593.44" wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1587.12-1587.47" + attribute \src "ls180.v:1590.12-1590.47" wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1591.12-1591.46" + attribute \src "ls180.v:1594.12-1594.46" wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1930.12-1930.85" + attribute \src "ls180.v:1933.12-1933.85" wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1931.5-1931.81" + attribute \src "ls180.v:1934.5-1934.81" wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1592.12-1592.46" + attribute \src "ls180.v:1595.12-1595.46" wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1932.12-1932.85" + attribute \src "ls180.v:1935.12-1935.85" wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1933.5-1933.81" + attribute \src "ls180.v:1936.5-1936.81" wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1593.12-1593.46" + attribute \src "ls180.v:1596.12-1596.46" wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1934.12-1934.85" + attribute \src "ls180.v:1937.12-1937.85" wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1935.5-1935.81" + attribute \src "ls180.v:1938.5-1938.81" wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1594.12-1594.46" + attribute \src "ls180.v:1597.12-1597.46" wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1936.12-1936.85" + attribute \src "ls180.v:1939.12-1939.85" wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1937.5-1937.81" + attribute \src "ls180.v:1940.5-1940.81" wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1554.6-1554.43" + attribute \src "ls180.v:1557.6-1557.43" wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1555.6-1555.42" + attribute \src "ls180.v:1558.6-1558.42" wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1556.12-1556.56" + attribute \src "ls180.v:1559.12-1559.56" wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1553.5-1553.42" + attribute \src "ls180.v:1556.5-1556.42" wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1552.6-1552.43" + attribute \src "ls180.v:1555.6-1555.43" wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1559.5-1559.44" + attribute \src "ls180.v:1562.5-1562.44" wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1560.5-1560.43" + attribute \src "ls180.v:1563.5-1563.43" wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1561.11-1561.57" + attribute \src "ls180.v:1564.11-1564.57" wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1558.5-1558.44" + attribute \src "ls180.v:1561.5-1561.44" wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1557.5-1557.44" + attribute \src "ls180.v:1560.5-1560.44" wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1550.6-1550.35" + attribute \src "ls180.v:1553.6-1553.35" wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1549.11-1549.40" + attribute \src "ls180.v:1552.11-1552.40" wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1507.11-1507.44" + attribute \src "ls180.v:1510.11-1510.44" wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1508.12-1508.45" + attribute \src "ls180.v:1511.12-1511.45" wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1517.12-1517.46" + attribute \src "ls180.v:1520.12-1520.46" wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1518.12-1518.46" + attribute \src "ls180.v:1521.12-1521.46" wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1519.12-1519.46" + attribute \src "ls180.v:1522.12-1522.46" wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1520.12-1520.46" + attribute \src "ls180.v:1523.12-1523.46" wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1521.12-1521.46" + attribute \src "ls180.v:1524.12-1524.46" wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1522.12-1522.46" + attribute \src "ls180.v:1525.12-1525.46" wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1523.12-1523.46" + attribute \src "ls180.v:1526.12-1526.46" wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1524.12-1524.46" + attribute \src "ls180.v:1527.12-1527.46" wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1525.12-1525.46" + attribute \src "ls180.v:1528.12-1528.46" wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1526.12-1526.46" + attribute \src "ls180.v:1529.12-1529.46" wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1509.12-1509.45" + attribute \src "ls180.v:1512.12-1512.45" wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1527.12-1527.46" + attribute \src "ls180.v:1530.12-1530.46" wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1528.12-1528.46" + attribute \src "ls180.v:1531.12-1531.46" wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1529.12-1529.46" + attribute \src "ls180.v:1532.12-1532.46" wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1530.12-1530.46" + attribute \src "ls180.v:1533.12-1533.46" wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1531.12-1531.46" + attribute \src "ls180.v:1534.12-1534.46" wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1532.12-1532.46" + attribute \src "ls180.v:1535.12-1535.46" wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1533.12-1533.46" + attribute \src "ls180.v:1536.12-1536.46" wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1534.12-1534.46" + attribute \src "ls180.v:1537.12-1537.46" wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1535.12-1535.46" + attribute \src "ls180.v:1538.12-1538.46" wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1536.12-1536.46" + attribute \src "ls180.v:1539.12-1539.46" wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1510.12-1510.45" + attribute \src "ls180.v:1513.12-1513.45" wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1537.12-1537.46" + attribute \src "ls180.v:1540.12-1540.46" wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1538.12-1538.46" + attribute \src "ls180.v:1541.12-1541.46" wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1539.12-1539.46" + attribute \src "ls180.v:1542.12-1542.46" wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1540.12-1540.46" + attribute \src "ls180.v:1543.12-1543.46" wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1541.12-1541.46" + attribute \src "ls180.v:1544.12-1544.46" wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1542.12-1542.46" + attribute \src "ls180.v:1545.12-1545.46" wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1543.12-1543.46" + attribute \src "ls180.v:1546.12-1546.46" wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1544.12-1544.46" + attribute \src "ls180.v:1547.12-1547.46" wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1545.12-1545.46" + attribute \src "ls180.v:1548.12-1548.46" wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1546.12-1546.46" + attribute \src "ls180.v:1549.12-1549.46" wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1511.12-1511.45" + attribute \src "ls180.v:1514.12-1514.45" wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1547.12-1547.46" + attribute \src "ls180.v:1550.12-1550.46" wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1512.12-1512.45" + attribute \src "ls180.v:1515.12-1515.45" wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1513.12-1513.45" + attribute \src "ls180.v:1516.12-1516.45" wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1514.12-1514.45" + attribute \src "ls180.v:1517.12-1517.45" wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1515.12-1515.45" + attribute \src "ls180.v:1518.12-1518.45" wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1516.12-1516.45" + attribute \src "ls180.v:1519.12-1519.45" wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1551.6-1551.38" + attribute \src "ls180.v:1554.6-1554.38" wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1548.13-1548.42" + attribute \src "ls180.v:1551.13-1551.42" wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1650.12-1650.34" + attribute \src "ls180.v:1653.12-1653.34" wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1948.12-1948.57" + attribute \src "ls180.v:1951.12-1951.57" wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1949.5-1949.53" + attribute \src "ls180.v:1952.5-1952.53" wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1651.5-1651.26" + attribute \src "ls180.v:1654.5-1654.26" wire \main_sdcore_data_done - attribute \src "ls180.v:1944.5-1944.49" + attribute \src "ls180.v:1947.5-1947.49" wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1945.5-1945.52" + attribute \src "ls180.v:1948.5-1948.52" wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1652.5-1652.27" + attribute \src "ls180.v:1655.5-1655.27" wire \main_sdcore_data_error - attribute \src "ls180.v:1954.5-1954.50" + attribute \src "ls180.v:1957.5-1957.50" wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1955.5-1955.53" + attribute \src "ls180.v:1958.5-1958.53" wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1501.12-1501.41" + attribute \src "ls180.v:1504.12-1504.41" wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1502.6-1502.31" + attribute \src "ls180.v:1505.6-1505.31" wire \main_sdcore_data_event_we - attribute \src "ls180.v:1653.5-1653.29" + attribute \src "ls180.v:1656.5-1656.29" wire \main_sdcore_data_timeout - attribute \src "ls180.v:1956.5-1956.52" + attribute \src "ls180.v:1959.5-1959.52" wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1957.5-1957.55" + attribute \src "ls180.v:1960.5-1960.55" wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1649.12-1649.33" + attribute \src "ls180.v:1652.12-1652.33" wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1481.6-1481.33" + attribute \src "ls180.v:1484.6-1484.33" wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1482.6-1482.32" + attribute \src "ls180.v:1485.6-1485.32" wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1483.12-1483.46" + attribute \src "ls180.v:1486.12-1486.46" wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1480.6-1480.33" + attribute \src "ls180.v:1483.6-1483.33" wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1479.6-1479.33" + attribute \src "ls180.v:1482.6-1482.33" wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1486.6-1486.37" + attribute \src "ls180.v:1489.6-1489.37" wire \main_sdcore_source_source_first - attribute \src "ls180.v:1487.6-1487.36" + attribute \src "ls180.v:1490.6-1490.36" wire \main_sdcore_source_source_last - attribute \src "ls180.v:1488.12-1488.50" + attribute \src "ls180.v:1491.12-1491.50" wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1485.6-1485.37" + attribute \src "ls180.v:1488.6-1488.37" wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1484.6-1484.37" + attribute \src "ls180.v:1487.6-1487.37" wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1799.6-1799.38" + attribute \src "ls180.v:1802.6-1802.38" wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1800.6-1800.37" + attribute \src "ls180.v:1803.6-1803.37" wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1798.11-1798.41" + attribute \src "ls180.v:1801.11-1801.41" wire width 3 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1789.6-1789.43" + attribute \src "ls180.v:1792.6-1792.43" wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1790.6-1790.42" + attribute \src "ls180.v:1793.6-1793.42" wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1791.13-1791.57" + attribute \src "ls180.v:1794.13-1794.57" wire width 64 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1788.6-1788.43" + attribute \src "ls180.v:1791.6-1791.43" wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1787.6-1787.43" + attribute \src "ls180.v:1790.6-1790.43" wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1794.6-1794.45" + attribute \src "ls180.v:1797.6-1797.45" wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1795.6-1795.44" + attribute \src "ls180.v:1798.6-1798.44" wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1796.11-1796.57" + attribute \src "ls180.v:1799.11-1799.57" wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1797.6-1797.65" + attribute \src "ls180.v:1800.6-1800.65" wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1793.6-1793.45" + attribute \src "ls180.v:1796.6-1796.45" wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1792.6-1792.45" + attribute \src "ls180.v:1795.6-1795.45" wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1783.13-1783.38" + attribute \src "ls180.v:1786.13-1786.38" wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1772.5-1772.33" + attribute \src "ls180.v:1775.5-1775.33" wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1771.12-1771.45" + attribute \src "ls180.v:1774.12-1774.45" wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1770.12-1770.37" + attribute \src "ls180.v:1773.12-1773.37" wire width 64 \main_sdmem2block_dma_data - attribute \src "ls180.v:1966.12-1966.67" + attribute \src "ls180.v:1969.12-1969.67" wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1967.5-1967.63" + attribute \src "ls180.v:1970.5-1970.63" wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1777.5-1777.37" + attribute \src "ls180.v:1780.5-1780.37" wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1778.6-1778.34" + attribute \src "ls180.v:1781.6-1781.34" wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1776.5-1776.35" + attribute \src "ls180.v:1779.5-1779.35" wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1775.5-1775.40" + attribute \src "ls180.v:1778.5-1778.40" wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1785.13-1785.40" + attribute \src "ls180.v:1788.13-1788.40" wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1774.5-1774.35" + attribute \src "ls180.v:1777.5-1777.35" wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1773.12-1773.47" + attribute \src "ls180.v:1776.12-1776.47" wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1780.5-1780.33" + attribute \src "ls180.v:1783.5-1783.33" wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1779.5-1779.38" + attribute \src "ls180.v:1782.5-1782.38" wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1784.12-1784.39" + attribute \src "ls180.v:1787.12-1787.39" wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1970.12-1970.79" + attribute \src "ls180.v:1973.12-1973.79" wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1971.5-1971.75" + attribute \src "ls180.v:1974.5-1974.75" wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1781.13-1781.47" + attribute \src "ls180.v:1784.13-1784.47" wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1782.6-1782.36" + attribute \src "ls180.v:1785.6-1785.36" wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1786.6-1786.32" + attribute \src "ls180.v:1789.6-1789.32" wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1763.5-1763.35" + attribute \src "ls180.v:1766.5-1766.35" wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1764.12-1764.53" + attribute \src "ls180.v:1767.12-1767.53" wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1762.5-1762.36" + attribute \src "ls180.v:1765.5-1765.36" wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1761.5-1761.36" + attribute \src "ls180.v:1764.5-1764.36" wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1767.5-1767.38" + attribute \src "ls180.v:1770.5-1770.38" wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1768.5-1768.37" + attribute \src "ls180.v:1771.5-1771.37" wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1769.12-1769.52" + attribute \src "ls180.v:1772.12-1772.52" wire width 64 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1766.6-1766.39" + attribute \src "ls180.v:1769.6-1769.39" wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1765.5-1765.38" + attribute \src "ls180.v:1768.5-1768.38" wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1825.11-1825.40" + attribute \src "ls180.v:1828.11-1828.40" wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1830.6-1830.35" + attribute \src "ls180.v:1833.6-1833.35" wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1834.6-1834.41" + attribute \src "ls180.v:1837.6-1837.41" wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1835.6-1835.40" + attribute \src "ls180.v:1838.6-1838.40" wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1833.12-1833.54" + attribute \src "ls180.v:1836.12-1836.54" wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1837.6-1837.42" + attribute \src "ls180.v:1840.6-1840.42" wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1838.6-1838.41" + attribute \src "ls180.v:1841.6-1841.41" wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1836.12-1836.55" + attribute \src "ls180.v:1839.12-1839.55" wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1822.11-1822.38" + attribute \src "ls180.v:1825.11-1825.38" wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1824.11-1824.40" + attribute \src "ls180.v:1827.11-1827.40" wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1831.12-1831.44" + attribute \src "ls180.v:1834.12-1834.44" wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1832.12-1832.46" + attribute \src "ls180.v:1835.12-1835.46" wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1823.5-1823.34" + attribute \src "ls180.v:1826.5-1826.34" wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1808.6-1808.38" + attribute \src "ls180.v:1811.6-1811.38" wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1809.6-1809.37" + attribute \src "ls180.v:1812.6-1812.37" wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1810.12-1810.51" + attribute \src "ls180.v:1813.12-1813.51" wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1807.6-1807.38" + attribute \src "ls180.v:1810.6-1810.38" wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1806.6-1806.38" + attribute \src "ls180.v:1809.6-1809.38" wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1813.6-1813.40" + attribute \src "ls180.v:1816.6-1816.40" wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1814.6-1814.39" + attribute \src "ls180.v:1817.6-1817.39" wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1815.12-1815.53" + attribute \src "ls180.v:1818.12-1818.53" wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1812.6-1812.40" + attribute \src "ls180.v:1815.6-1815.40" wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1811.6-1811.40" + attribute \src "ls180.v:1814.6-1814.40" wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1820.12-1820.46" + attribute \src "ls180.v:1823.12-1823.46" wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1821.12-1821.47" + attribute \src "ls180.v:1824.12-1824.47" wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1818.6-1818.39" + attribute \src "ls180.v:1821.6-1821.39" wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1819.6-1819.45" + attribute \src "ls180.v:1822.6-1822.45" wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1816.6-1816.39" + attribute \src "ls180.v:1819.6-1819.39" wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1817.6-1817.45" + attribute \src "ls180.v:1820.6-1820.45" wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1826.11-1826.43" + attribute \src "ls180.v:1829.11-1829.43" wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1827.12-1827.46" + attribute \src "ls180.v:1830.12-1830.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1829.12-1829.46" + attribute \src "ls180.v:1832.12-1832.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1828.6-1828.37" + attribute \src "ls180.v:1831.6-1831.37" wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1758.6-1758.43" + attribute \src "ls180.v:1761.6-1761.43" wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1803.6-1803.43" + attribute \src "ls180.v:1806.6-1806.43" wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1759.6-1759.42" + attribute \src "ls180.v:1762.6-1762.42" wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1804.6-1804.42" + attribute \src "ls180.v:1807.6-1807.42" wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1760.12-1760.56" + attribute \src "ls180.v:1763.12-1763.56" wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1805.12-1805.56" + attribute \src "ls180.v:1808.12-1808.56" wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1757.6-1757.43" + attribute \src "ls180.v:1760.6-1760.43" wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1802.6-1802.43" + attribute \src "ls180.v:1805.6-1805.43" wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1756.6-1756.43" + attribute \src "ls180.v:1759.6-1759.43" wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1801.6-1801.43" + attribute \src "ls180.v:1804.6-1804.43" wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1207.6-1207.27" + attribute \src "ls180.v:1210.6-1210.27" wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1206.5-1206.28" - wire \main_sdphy_clocker_clk0 attribute \src "ls180.v:1209.5-1209.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1212.5-1212.28" wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1210.5-1210.29" + attribute \src "ls180.v:1213.5-1213.29" wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1208.11-1208.34" + attribute \src "ls180.v:1211.11-1211.34" wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1204.5-1204.26" + attribute \src "ls180.v:1207.5-1207.26" wire \main_sdphy_clocker_re - attribute \src "ls180.v:1205.6-1205.29" + attribute \src "ls180.v:1208.6-1208.29" wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1203.11-1203.37" + attribute \src "ls180.v:1206.11-1206.37" wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1307.6-1307.41" + attribute \src "ls180.v:1310.6-1310.41" wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1308.6-1308.40" + attribute \src "ls180.v:1311.6-1311.40" wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1309.12-1309.54" + attribute \src "ls180.v:1312.12-1312.54" wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1306.6-1306.41" + attribute \src "ls180.v:1309.6-1309.41" wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1305.6-1305.41" + attribute \src "ls180.v:1308.6-1308.41" wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1312.5-1312.42" + attribute \src "ls180.v:1315.5-1315.42" wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1313.5-1313.41" + attribute \src "ls180.v:1316.5-1316.41" wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1314.11-1314.55" + attribute \src "ls180.v:1317.11-1317.55" wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1311.6-1311.43" + attribute \src "ls180.v:1314.6-1314.43" wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1310.5-1310.42" + attribute \src "ls180.v:1313.5-1313.42" wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1297.11-1297.47" + attribute \src "ls180.v:1300.11-1300.47" wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1298.6-1298.46" + attribute \src "ls180.v:1301.6-1301.46" wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1288.5-1288.46" + attribute \src "ls180.v:1291.5-1291.46" wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1289.5-1289.45" + attribute \src "ls180.v:1292.5-1292.45" wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1290.6-1290.54" + attribute \src "ls180.v:1293.6-1293.54" wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1287.6-1287.47" + attribute \src "ls180.v:1290.6-1290.47" wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1286.6-1286.47" + attribute \src "ls180.v:1289.6-1289.47" wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1293.5-1293.48" + attribute \src "ls180.v:1296.5-1296.48" wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1294.5-1294.47" + attribute \src "ls180.v:1297.5-1297.47" wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1295.11-1295.61" + attribute \src "ls180.v:1298.11-1298.61" wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1296.11-1296.74" + attribute \src "ls180.v:1299.11-1299.74" wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1292.6-1292.49" + attribute \src "ls180.v:1295.6-1295.49" wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1291.6-1291.49" + attribute \src "ls180.v:1294.6-1294.49" wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1299.5-1299.46" + attribute \src "ls180.v:1302.5-1302.46" wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1270.6-1270.40" + attribute \src "ls180.v:1273.6-1273.40" wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1271.6-1271.39" + attribute \src "ls180.v:1274.6-1274.39" wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1272.6-1272.46" + attribute \src "ls180.v:1275.6-1275.46" wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1273.6-1273.48" + attribute \src "ls180.v:1276.6-1276.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1274.6-1274.48" + attribute \src "ls180.v:1277.6-1277.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1275.6-1275.49" + attribute \src "ls180.v:1278.6-1278.49" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1276.12-1276.55" + attribute \src "ls180.v:1279.12-1279.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1277.12-1277.55" + attribute \src "ls180.v:1280.12-1280.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1278.6-1278.50" + attribute \src "ls180.v:1281.6-1281.50" wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1269.5-1269.39" + attribute \src "ls180.v:1272.5-1272.39" wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1268.6-1268.40" + attribute \src "ls180.v:1271.6-1271.40" wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1315.5-1315.31" + attribute \src "ls180.v:1318.5-1318.31" wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1910.5-1910.59" + attribute \src "ls180.v:1913.5-1913.59" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1911.5-1911.62" + attribute \src "ls180.v:1914.5-1914.62" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1285.5-1285.29" + attribute \src "ls180.v:1288.5-1288.29" wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1281.6-1281.47" + attribute \src "ls180.v:1284.6-1284.47" wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1302.6-1302.47" + attribute \src "ls180.v:1305.6-1305.47" wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1282.6-1282.46" + attribute \src "ls180.v:1285.6-1285.46" wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1303.6-1303.46" + attribute \src "ls180.v:1306.6-1306.46" wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1283.12-1283.60" + attribute \src "ls180.v:1286.12-1286.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1304.12-1304.60" + attribute \src "ls180.v:1307.12-1307.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1280.5-1280.46" + attribute \src "ls180.v:1283.5-1283.46" wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1301.6-1301.47" + attribute \src "ls180.v:1304.6-1304.47" wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1279.6-1279.47" + attribute \src "ls180.v:1282.6-1282.47" wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1300.6-1300.47" + attribute \src "ls180.v:1303.6-1303.47" wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1284.6-1284.32" + attribute \src "ls180.v:1287.6-1287.32" wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1267.11-1267.32" + attribute \src "ls180.v:1270.11-1270.32" wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1906.11-1906.60" + attribute \src "ls180.v:1909.11-1909.60" wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1907.5-1907.57" + attribute \src "ls180.v:1910.5-1910.57" wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1242.5-1242.42" + attribute \src "ls180.v:1245.5-1245.42" wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1243.5-1243.41" + attribute \src "ls180.v:1246.5-1246.41" wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1244.5-1244.48" + attribute \src "ls180.v:1247.5-1247.48" wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1245.6-1245.51" + attribute \src "ls180.v:1248.6-1248.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1246.5-1246.50" + attribute \src "ls180.v:1249.5-1249.50" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1247.5-1247.51" + attribute \src "ls180.v:1250.5-1250.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1248.12-1248.58" + attribute \src "ls180.v:1251.12-1251.58" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1249.11-1249.57" + attribute \src "ls180.v:1252.11-1252.57" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1250.5-1250.52" + attribute \src "ls180.v:1253.5-1253.52" wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1241.6-1241.43" + attribute \src "ls180.v:1244.6-1244.43" wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1240.6-1240.43" + attribute \src "ls180.v:1243.6-1243.43" wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1252.5-1252.41" + attribute \src "ls180.v:1255.5-1255.41" wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1253.5-1253.43" + attribute \src "ls180.v:1256.5-1256.43" wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1254.5-1254.44" + attribute \src "ls180.v:1257.5-1257.44" wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1255.11-1255.50" + attribute \src "ls180.v:1258.11-1258.50" wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1256.5-1256.45" + attribute \src "ls180.v:1259.5-1259.45" wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1251.6-1251.36" + attribute \src "ls180.v:1254.6-1254.36" wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1259.5-1259.30" + attribute \src "ls180.v:1262.5-1262.30" wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1260.11-1260.46" + attribute \src "ls180.v:1263.11-1263.46" wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1258.5-1258.31" + attribute \src "ls180.v:1261.5-1261.31" wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1257.5-1257.31" + attribute \src "ls180.v:1260.5-1260.31" wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1263.5-1263.32" + attribute \src "ls180.v:1266.5-1266.32" wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1264.11-1264.46" + attribute \src "ls180.v:1267.11-1267.46" wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1265.11-1265.48" + attribute \src "ls180.v:1268.11-1268.48" wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1262.5-1262.33" + attribute \src "ls180.v:1265.5-1265.33" wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1261.5-1261.33" + attribute \src "ls180.v:1264.5-1264.33" wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1266.12-1266.35" + attribute \src "ls180.v:1269.12-1269.35" wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1908.12-1908.63" + attribute \src "ls180.v:1911.12-1911.63" wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1909.5-1909.59" + attribute \src "ls180.v:1912.5-1912.59" wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1239.11-1239.32" + attribute \src "ls180.v:1242.11-1242.32" wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1902.11-1902.59" + attribute \src "ls180.v:1905.11-1905.59" wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1903.5-1903.56" + attribute \src "ls180.v:1906.5-1906.56" wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1238.5-1238.25" + attribute \src "ls180.v:1241.5-1241.25" wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1226.6-1226.43" + attribute \src "ls180.v:1229.6-1229.43" wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1227.12-1227.50" + attribute \src "ls180.v:1230.12-1230.50" wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1225.6-1225.35" + attribute \src "ls180.v:1228.6-1228.35" wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1229.5-1229.41" + attribute \src "ls180.v:1232.5-1232.41" wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1230.5-1230.43" + attribute \src "ls180.v:1233.5-1233.43" wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1231.5-1231.44" + attribute \src "ls180.v:1234.5-1234.44" wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1232.11-1232.50" + attribute \src "ls180.v:1235.11-1235.50" wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1233.5-1233.45" + attribute \src "ls180.v:1236.5-1236.45" wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1228.6-1228.36" + attribute \src "ls180.v:1231.6-1231.36" wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1236.5-1236.30" + attribute \src "ls180.v:1239.5-1239.30" wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1237.11-1237.44" + attribute \src "ls180.v:1240.11-1240.44" wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1235.5-1235.31" + attribute \src "ls180.v:1238.5-1238.31" wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1234.5-1234.31" + attribute \src "ls180.v:1237.5-1237.31" wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1423.11-1423.33" + attribute \src "ls180.v:1426.11-1426.33" wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1922.11-1922.62" + attribute \src "ls180.v:1925.11-1925.62" wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1923.5-1923.59" + attribute \src "ls180.v:1926.5-1926.59" wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1463.6-1463.43" + attribute \src "ls180.v:1466.6-1466.43" wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1464.6-1464.42" + attribute \src "ls180.v:1467.6-1467.42" wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1465.12-1465.56" + attribute \src "ls180.v:1468.12-1468.56" wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1462.6-1462.43" + attribute \src "ls180.v:1465.6-1465.43" wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1461.6-1461.43" + attribute \src "ls180.v:1464.6-1464.43" wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1468.5-1468.44" + attribute \src "ls180.v:1471.5-1471.44" wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1469.5-1469.43" + attribute \src "ls180.v:1472.5-1472.43" wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1470.11-1470.57" + attribute \src "ls180.v:1473.11-1473.57" wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1467.6-1467.45" + attribute \src "ls180.v:1470.6-1470.45" wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1466.5-1466.44" + attribute \src "ls180.v:1469.5-1469.44" wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1453.5-1453.43" + attribute \src "ls180.v:1456.5-1456.43" wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1454.6-1454.48" + attribute \src "ls180.v:1457.6-1457.48" wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1444.5-1444.48" + attribute \src "ls180.v:1447.5-1447.48" wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1445.5-1445.47" + attribute \src "ls180.v:1448.5-1448.47" wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1446.12-1446.62" + attribute \src "ls180.v:1449.12-1449.62" wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1443.6-1443.49" + attribute \src "ls180.v:1446.6-1446.49" wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1442.6-1442.49" + attribute \src "ls180.v:1445.6-1445.49" wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1449.5-1449.50" + attribute \src "ls180.v:1452.5-1452.50" wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1450.5-1450.49" + attribute \src "ls180.v:1453.5-1453.49" wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1451.11-1451.63" + attribute \src "ls180.v:1454.11-1454.63" wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1452.11-1452.76" + attribute \src "ls180.v:1455.11-1455.76" wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1448.6-1448.51" + attribute \src "ls180.v:1451.6-1451.51" wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1447.6-1447.51" + attribute \src "ls180.v:1450.6-1450.51" wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1455.5-1455.48" + attribute \src "ls180.v:1458.5-1458.48" wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1426.6-1426.42" + attribute \src "ls180.v:1429.6-1429.42" wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1427.6-1427.41" + attribute \src "ls180.v:1430.6-1430.41" wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1428.6-1428.48" + attribute \src "ls180.v:1431.6-1431.48" wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1429.6-1429.50" + attribute \src "ls180.v:1432.6-1432.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1430.6-1430.50" + attribute \src "ls180.v:1433.6-1433.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1431.6-1431.51" + attribute \src "ls180.v:1434.6-1434.51" wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1432.12-1432.57" + attribute \src "ls180.v:1435.12-1435.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1433.12-1433.57" + attribute \src "ls180.v:1436.12-1436.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1434.6-1434.52" + attribute \src "ls180.v:1437.6-1437.52" wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1425.5-1425.41" + attribute \src "ls180.v:1428.5-1428.41" wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1424.6-1424.42" + attribute \src "ls180.v:1427.6-1427.42" wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1471.5-1471.33" + attribute \src "ls180.v:1474.5-1474.33" wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1926.5-1926.62" + attribute \src "ls180.v:1929.5-1929.62" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1927.5-1927.65" + attribute \src "ls180.v:1930.5-1930.65" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1441.5-1441.31" + attribute \src "ls180.v:1444.5-1444.31" wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1437.6-1437.49" + attribute \src "ls180.v:1440.6-1440.49" wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1458.6-1458.49" + attribute \src "ls180.v:1461.6-1461.49" wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1438.6-1438.48" + attribute \src "ls180.v:1441.6-1441.48" wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1459.6-1459.48" + attribute \src "ls180.v:1462.6-1462.48" wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1439.12-1439.62" + attribute \src "ls180.v:1442.12-1442.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1460.12-1460.62" + attribute \src "ls180.v:1463.12-1463.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1436.5-1436.48" + attribute \src "ls180.v:1439.5-1439.48" wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1457.6-1457.49" + attribute \src "ls180.v:1460.6-1460.49" wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1435.6-1435.49" + attribute \src "ls180.v:1438.6-1438.49" wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1456.6-1456.49" + attribute \src "ls180.v:1459.6-1459.49" wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1440.6-1440.34" + attribute \src "ls180.v:1443.6-1443.34" wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1396.5-1396.43" + attribute \src "ls180.v:1399.5-1399.43" wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1397.5-1397.42" + attribute \src "ls180.v:1400.5-1400.42" wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1398.5-1398.49" + attribute \src "ls180.v:1401.5-1401.49" wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1399.6-1399.52" + attribute \src "ls180.v:1402.6-1402.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1400.5-1400.51" + attribute \src "ls180.v:1403.5-1403.51" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1401.5-1401.52" + attribute \src "ls180.v:1404.5-1404.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1402.12-1402.59" + attribute \src "ls180.v:1405.12-1405.59" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1403.11-1403.58" + attribute \src "ls180.v:1406.11-1406.58" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1404.5-1404.53" + attribute \src "ls180.v:1407.5-1407.53" wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1395.6-1395.44" + attribute \src "ls180.v:1398.6-1398.44" wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1394.6-1394.44" + attribute \src "ls180.v:1397.6-1397.44" wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1406.5-1406.42" + attribute \src "ls180.v:1409.5-1409.42" wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1407.5-1407.44" + attribute \src "ls180.v:1410.5-1410.44" wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1408.5-1408.45" + attribute \src "ls180.v:1411.5-1411.45" wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1409.11-1409.51" + attribute \src "ls180.v:1412.11-1412.51" wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1410.5-1410.46" + attribute \src "ls180.v:1413.5-1413.46" wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1405.6-1405.37" + attribute \src "ls180.v:1408.6-1408.37" wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1413.5-1413.31" + attribute \src "ls180.v:1416.5-1416.31" wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1414.11-1414.53" + attribute \src "ls180.v:1417.11-1417.53" wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1412.5-1412.32" + attribute \src "ls180.v:1415.5-1415.32" wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1411.5-1411.32" + attribute \src "ls180.v:1414.5-1414.32" wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1417.5-1417.34" + attribute \src "ls180.v:1420.5-1420.34" wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1418.5-1418.33" + attribute \src "ls180.v:1421.5-1421.33" wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1419.11-1419.47" + attribute \src "ls180.v:1422.11-1422.47" wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1420.11-1420.49" + attribute \src "ls180.v:1423.11-1423.49" wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1416.5-1416.34" + attribute \src "ls180.v:1419.5-1419.34" wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1415.5-1415.34" + attribute \src "ls180.v:1418.5-1418.34" wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1421.5-1421.26" + attribute \src "ls180.v:1424.5-1424.26" wire \main_sdphy_datar_stop - attribute \src "ls180.v:1422.12-1422.36" + attribute \src "ls180.v:1425.12-1425.36" wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1924.12-1924.65" + attribute \src "ls180.v:1927.12-1927.65" wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1925.5-1925.61" + attribute \src "ls180.v:1928.5-1928.61" wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1331.11-1331.33" + attribute \src "ls180.v:1334.11-1334.33" wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1918.11-1918.54" + attribute \src "ls180.v:1921.11-1921.54" wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1919.5-1919.51" + attribute \src "ls180.v:1922.5-1922.51" wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1385.6-1385.42" + attribute \src "ls180.v:1388.6-1388.42" wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1386.6-1386.41" + attribute \src "ls180.v:1389.6-1389.41" wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1387.12-1387.55" + attribute \src "ls180.v:1390.12-1390.55" wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1384.6-1384.42" + attribute \src "ls180.v:1387.6-1387.42" wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1383.6-1383.42" + attribute \src "ls180.v:1386.6-1386.42" wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1390.5-1390.43" + attribute \src "ls180.v:1393.5-1393.43" wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1391.5-1391.42" + attribute \src "ls180.v:1394.5-1394.42" wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1392.11-1392.56" + attribute \src "ls180.v:1395.11-1395.56" wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1389.6-1389.44" + attribute \src "ls180.v:1392.6-1392.44" wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1388.5-1388.43" + attribute \src "ls180.v:1391.5-1391.43" wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1375.11-1375.48" + attribute \src "ls180.v:1378.11-1378.48" wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1376.6-1376.47" + attribute \src "ls180.v:1379.6-1379.47" wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1366.5-1366.47" + attribute \src "ls180.v:1369.5-1369.47" wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1367.5-1367.46" + attribute \src "ls180.v:1370.5-1370.46" wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1368.6-1368.55" + attribute \src "ls180.v:1371.6-1371.55" wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1365.6-1365.48" + attribute \src "ls180.v:1368.6-1368.48" wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1364.6-1364.48" + attribute \src "ls180.v:1367.6-1367.48" wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1371.5-1371.49" + attribute \src "ls180.v:1374.5-1374.49" wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1372.5-1372.48" + attribute \src "ls180.v:1375.5-1375.48" wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1373.11-1373.62" + attribute \src "ls180.v:1376.11-1376.62" wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1374.11-1374.75" + attribute \src "ls180.v:1377.11-1377.75" wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1370.6-1370.50" + attribute \src "ls180.v:1373.6-1373.50" wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1369.6-1369.50" + attribute \src "ls180.v:1372.6-1372.50" wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1377.5-1377.47" + attribute \src "ls180.v:1380.5-1380.47" wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1348.6-1348.41" + attribute \src "ls180.v:1351.6-1351.41" wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1349.6-1349.40" + attribute \src "ls180.v:1352.6-1352.40" wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1350.6-1350.47" + attribute \src "ls180.v:1353.6-1353.47" wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1351.6-1351.49" + attribute \src "ls180.v:1354.6-1354.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1352.6-1352.49" + attribute \src "ls180.v:1355.6-1355.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1353.6-1353.50" + attribute \src "ls180.v:1356.6-1356.50" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1354.12-1354.56" + attribute \src "ls180.v:1357.12-1357.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1355.12-1355.56" + attribute \src "ls180.v:1358.12-1358.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1356.6-1356.51" + attribute \src "ls180.v:1359.6-1359.51" wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1347.5-1347.40" + attribute \src "ls180.v:1350.5-1350.40" wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1346.6-1346.41" + attribute \src "ls180.v:1349.6-1349.41" wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1393.5-1393.32" + attribute \src "ls180.v:1396.5-1396.32" wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1914.5-1914.59" + attribute \src "ls180.v:1917.5-1917.59" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1915.5-1915.62" + attribute \src "ls180.v:1918.5-1918.62" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1363.5-1363.30" + attribute \src "ls180.v:1366.5-1366.30" wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1359.6-1359.48" + attribute \src "ls180.v:1362.6-1362.48" wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1380.6-1380.48" + attribute \src "ls180.v:1383.6-1383.48" wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1360.6-1360.47" + attribute \src "ls180.v:1363.6-1363.47" wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1381.6-1381.47" + attribute \src "ls180.v:1384.6-1384.47" wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1361.12-1361.61" + attribute \src "ls180.v:1364.12-1364.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1382.12-1382.61" + attribute \src "ls180.v:1385.12-1385.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1358.5-1358.47" + attribute \src "ls180.v:1361.5-1361.47" wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1379.6-1379.48" + attribute \src "ls180.v:1382.6-1382.48" wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1357.6-1357.48" + attribute \src "ls180.v:1360.6-1360.48" wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1378.6-1378.48" + attribute \src "ls180.v:1381.6-1381.48" wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1362.6-1362.33" + attribute \src "ls180.v:1365.6-1365.33" wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1345.5-1345.27" + attribute \src "ls180.v:1348.5-1348.27" wire \main_sdphy_dataw_error - attribute \src "ls180.v:1334.5-1334.43" + attribute \src "ls180.v:1337.5-1337.43" wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1335.5-1335.42" + attribute \src "ls180.v:1338.5-1338.42" wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1336.5-1336.49" + attribute \src "ls180.v:1339.5-1339.49" wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1337.5-1337.51" + attribute \src "ls180.v:1340.5-1340.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1338.5-1338.51" + attribute \src "ls180.v:1341.5-1341.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1339.5-1339.52" + attribute \src "ls180.v:1342.5-1342.52" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1340.11-1340.58" + attribute \src "ls180.v:1343.11-1343.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1341.11-1341.58" + attribute \src "ls180.v:1344.11-1344.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1342.5-1342.53" + attribute \src "ls180.v:1345.5-1345.53" wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1333.6-1333.44" + attribute \src "ls180.v:1336.6-1336.44" wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1332.5-1332.43" + attribute \src "ls180.v:1335.5-1335.43" wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1317.6-1317.44" + attribute \src "ls180.v:1320.6-1320.44" wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1318.12-1318.51" + attribute \src "ls180.v:1321.12-1321.51" wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1316.6-1316.36" + attribute \src "ls180.v:1319.6-1319.36" wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1320.5-1320.42" + attribute \src "ls180.v:1323.5-1323.42" wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1321.5-1321.44" + attribute \src "ls180.v:1324.5-1324.44" wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1322.5-1322.45" + attribute \src "ls180.v:1325.5-1325.45" wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1323.11-1323.51" + attribute \src "ls180.v:1326.11-1326.51" wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1324.5-1324.46" + attribute \src "ls180.v:1327.5-1327.46" wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1319.6-1319.37" + attribute \src "ls180.v:1322.6-1322.37" wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1327.5-1327.32" + attribute \src "ls180.v:1330.5-1330.32" wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1328.5-1328.31" + attribute \src "ls180.v:1331.5-1331.31" wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1329.11-1329.45" + attribute \src "ls180.v:1332.11-1332.45" wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1326.5-1326.32" + attribute \src "ls180.v:1329.5-1329.32" wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1325.5-1325.32" + attribute \src "ls180.v:1328.5-1328.32" wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1343.5-1343.27" + attribute \src "ls180.v:1346.5-1346.27" wire \main_sdphy_dataw_start - attribute \src "ls180.v:1330.5-1330.26" + attribute \src "ls180.v:1333.5-1333.26" wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1344.5-1344.27" + attribute \src "ls180.v:1347.5-1347.27" wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1224.11-1224.32" + attribute \src "ls180.v:1227.11-1227.32" wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1898.11-1898.59" + attribute \src "ls180.v:1901.11-1901.59" wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1899.5-1899.56" + attribute \src "ls180.v:1902.5-1902.56" wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1212.6-1212.34" + attribute \src "ls180.v:1215.6-1215.34" wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1211.6-1211.35" + attribute \src "ls180.v:1214.6-1214.35" wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1214.5-1214.33" + attribute \src "ls180.v:1217.5-1217.33" wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1213.6-1213.35" + attribute \src "ls180.v:1216.6-1216.35" wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1216.6-1216.43" + attribute \src "ls180.v:1219.6-1219.43" wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1217.12-1217.50" + attribute \src "ls180.v:1220.12-1220.50" wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1215.6-1215.35" + attribute \src "ls180.v:1218.6-1218.35" wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1219.5-1219.41" + attribute \src "ls180.v:1222.5-1222.41" wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1220.5-1220.43" + attribute \src "ls180.v:1223.5-1223.43" wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1221.5-1221.44" + attribute \src "ls180.v:1224.5-1224.44" wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1222.11-1222.50" + attribute \src "ls180.v:1225.11-1225.50" wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1223.5-1223.45" + attribute \src "ls180.v:1226.5-1226.45" wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1218.6-1218.36" + attribute \src "ls180.v:1221.6-1221.36" wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1472.6-1472.27" + attribute \src "ls180.v:1475.6-1475.27" wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1473.5-1473.28" + attribute \src "ls180.v:1476.5-1476.28" wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1474.6-1474.29" + attribute \src "ls180.v:1477.6-1477.29" wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1475.6-1475.30" + attribute \src "ls180.v:1478.6-1478.30" wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1476.11-1476.35" + attribute \src "ls180.v:1479.11-1479.35" wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1477.12-1477.36" + attribute \src "ls180.v:1480.12-1480.36" wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1478.6-1478.31" + attribute \src "ls180.v:1481.6-1481.31" wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1201.6-1201.23" + attribute \src "ls180.v:1204.6-1204.23" wire \main_sdphy_status - attribute \src "ls180.v:1202.6-1202.19" + attribute \src "ls180.v:1205.6-1205.19" wire \main_sdphy_we - attribute \src "ls180.v:418.5-418.26" + attribute \src "ls180.v:421.5-421.26" wire \main_sdram_address_re - attribute \src "ls180.v:417.12-417.38" + attribute \src "ls180.v:420.12-420.38" wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:420.5-420.27" + attribute \src "ls180.v:423.5-423.27" wire \main_sdram_baddress_re - attribute \src "ls180.v:419.11-419.38" + attribute \src "ls180.v:422.11-422.38" wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:516.5-516.43" + attribute \src "ls180.v:519.5-519.43" wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:538.11-538.63" + attribute \src "ls180.v:541.11-541.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:543.6-543.58" + attribute \src "ls180.v:546.6-546.58" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:548.6-548.64" + attribute \src "ls180.v:551.6-551.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:549.6-549.63" + attribute \src "ls180.v:552.6-552.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:547.13-547.78" + attribute \src "ls180.v:550.13-550.78" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:546.6-546.69" + attribute \src "ls180.v:549.6-549.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:552.6-552.65" + attribute \src "ls180.v:555.6-555.65" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:553.6-553.64" + attribute \src "ls180.v:556.6-556.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:551.13-551.79" + attribute \src "ls180.v:554.13-554.79" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:550.6-550.70" + attribute \src "ls180.v:553.6-553.70" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:535.11-535.61" + attribute \src "ls180.v:538.11-538.61" wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:537.11-537.63" + attribute \src "ls180.v:540.11-540.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:544.12-544.67" + attribute \src "ls180.v:547.12-547.67" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:545.13-545.70" + attribute \src "ls180.v:548.13-548.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:536.5-536.57" + attribute \src "ls180.v:539.5-539.57" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:519.5-519.60" + attribute \src "ls180.v:522.5-522.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:520.5-520.59" + attribute \src "ls180.v:523.5-523.59" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:522.13-522.75" + attribute \src "ls180.v:525.13-525.75" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:521.6-521.66" + attribute \src "ls180.v:524.6-524.66" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:518.6-518.61" + attribute \src "ls180.v:521.6-521.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:517.6-517.61" + attribute \src "ls180.v:520.6-520.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:525.6-525.63" + attribute \src "ls180.v:528.6-528.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:526.6-526.62" + attribute \src "ls180.v:529.6-529.62" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:528.13-528.77" + attribute \src "ls180.v:531.13-531.77" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:527.6-527.68" + attribute \src "ls180.v:530.6-530.68" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:524.6-524.63" + attribute \src "ls180.v:527.6-527.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:523.6-523.63" + attribute \src "ls180.v:526.6-526.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:533.13-533.71" + attribute \src "ls180.v:536.13-536.71" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:534.13-534.72" + attribute \src "ls180.v:537.13-537.72" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:531.6-531.63" + attribute \src "ls180.v:534.6-534.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:532.6-532.69" + attribute \src "ls180.v:535.6-535.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:529.6-529.63" + attribute \src "ls180.v:532.6-532.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:530.6-530.69" + attribute \src "ls180.v:533.6-533.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:539.11-539.66" + attribute \src "ls180.v:542.11-542.66" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:540.13-540.70" + attribute \src "ls180.v:543.13-543.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:542.13-542.70" + attribute \src "ls180.v:545.13-545.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:541.6-541.60" + attribute \src "ls180.v:544.6-544.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:556.6-556.51" + attribute \src "ls180.v:559.6-559.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:557.6-557.50" + attribute \src "ls180.v:560.6-560.50" wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:559.13-559.65" + attribute \src "ls180.v:562.13-562.65" wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:558.6-558.56" + attribute \src "ls180.v:561.6-561.56" wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:555.6-555.51" + attribute \src "ls180.v:558.6-558.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:554.6-554.51" + attribute \src "ls180.v:557.6-557.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:562.5-562.52" + attribute \src "ls180.v:565.5-565.52" wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:563.5-563.51" + attribute \src "ls180.v:566.5-566.51" wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:565.12-565.66" + attribute \src "ls180.v:568.12-568.66" wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:564.5-564.57" + attribute \src "ls180.v:567.5-567.57" wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:561.6-561.53" + attribute \src "ls180.v:564.6-564.53" wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:560.5-560.52" + attribute \src "ls180.v:563.5-563.52" wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:508.12-508.49" + attribute \src "ls180.v:511.12-511.49" wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:509.12-509.50" + attribute \src "ls180.v:512.12-512.50" wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:510.5-510.44" + attribute \src "ls180.v:513.5-513.44" wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:513.5-513.47" + attribute \src "ls180.v:516.5-516.47" wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:514.5-514.48" + attribute \src "ls180.v:517.5-517.48" wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:515.5-515.49" + attribute \src "ls180.v:518.5-518.49" wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:511.5-511.44" + attribute \src "ls180.v:514.5-514.44" wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:512.5-512.43" + attribute \src "ls180.v:515.5-515.43" wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:507.5-507.38" + attribute \src "ls180.v:510.5-510.38" wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:506.5-506.38" + attribute \src "ls180.v:509.5-509.38" wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:505.5-505.40" + attribute \src "ls180.v:508.5-508.40" wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:504.6-504.41" + attribute \src "ls180.v:507.6-507.41" wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:500.13-500.45" + attribute \src "ls180.v:503.13-503.45" wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:501.6-501.38" + attribute \src "ls180.v:504.6-504.38" wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:503.5-503.44" + attribute \src "ls180.v:506.5-506.44" wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:498.6-498.39" + attribute \src "ls180.v:501.6-501.39" wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:497.6-497.39" + attribute \src "ls180.v:500.6-500.39" wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:502.5-502.44" + attribute \src "ls180.v:505.5-505.44" wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:499.6-499.36" + attribute \src "ls180.v:502.6-502.36" wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:566.12-566.39" + attribute \src "ls180.v:569.12-569.39" wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:570.5-570.38" + attribute \src "ls180.v:573.5-573.38" wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:571.5-571.47" + attribute \src "ls180.v:574.5-574.47" wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:568.6-568.37" + attribute \src "ls180.v:571.6-571.37" wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:569.5-569.37" + attribute \src "ls180.v:572.5-572.37" wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:567.5-567.39" + attribute \src "ls180.v:570.5-570.39" wire \main_sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:578.32-578.69" + attribute \src "ls180.v:581.32-581.69" wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:577.6-577.43" + attribute \src "ls180.v:580.6-580.43" wire \main_sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:576.32-576.68" + attribute \src "ls180.v:579.32-579.68" wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:575.6-575.42" + attribute \src "ls180.v:578.6-578.42" wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:574.11-574.48" + attribute \src "ls180.v:577.11-577.48" wire width 3 \main_sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:573.32-573.69" + attribute \src "ls180.v:576.32-576.69" wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:572.6-572.43" + attribute \src "ls180.v:575.6-575.43" wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:598.5-598.43" + attribute \src "ls180.v:601.5-601.43" wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:620.11-620.63" + attribute \src "ls180.v:623.11-623.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:625.6-625.58" + attribute \src "ls180.v:628.6-628.58" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:630.6-630.64" + attribute \src "ls180.v:633.6-633.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:631.6-631.63" + attribute \src "ls180.v:634.6-634.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:629.13-629.78" + attribute \src "ls180.v:632.13-632.78" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:628.6-628.69" + attribute \src "ls180.v:631.6-631.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:634.6-634.65" + attribute \src "ls180.v:637.6-637.65" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:635.6-635.64" + attribute \src "ls180.v:638.6-638.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:633.13-633.79" + attribute \src "ls180.v:636.13-636.79" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:632.6-632.70" + attribute \src "ls180.v:635.6-635.70" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:617.11-617.61" + attribute \src "ls180.v:620.11-620.61" wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:619.11-619.63" + attribute \src "ls180.v:622.11-622.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:626.12-626.67" + attribute \src "ls180.v:629.12-629.67" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:627.13-627.70" + attribute \src "ls180.v:630.13-630.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:618.5-618.57" + attribute \src "ls180.v:621.5-621.57" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:601.5-601.60" + attribute \src "ls180.v:604.5-604.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:602.5-602.59" + attribute \src "ls180.v:605.5-605.59" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:604.13-604.75" + attribute \src "ls180.v:607.13-607.75" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:603.6-603.66" + attribute \src "ls180.v:606.6-606.66" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:600.6-600.61" + attribute \src "ls180.v:603.6-603.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:599.6-599.61" + attribute \src "ls180.v:602.6-602.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:607.6-607.63" + attribute \src "ls180.v:610.6-610.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:608.6-608.62" + attribute \src "ls180.v:611.6-611.62" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:610.13-610.77" + attribute \src "ls180.v:613.13-613.77" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:609.6-609.68" + attribute \src "ls180.v:612.6-612.68" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:606.6-606.63" + attribute \src "ls180.v:609.6-609.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:605.6-605.63" + attribute \src "ls180.v:608.6-608.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:615.13-615.71" + attribute \src "ls180.v:618.13-618.71" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:616.13-616.72" + attribute \src "ls180.v:619.13-619.72" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:613.6-613.63" + attribute \src "ls180.v:616.6-616.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:614.6-614.69" + attribute \src "ls180.v:617.6-617.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:611.6-611.63" + attribute \src "ls180.v:614.6-614.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:612.6-612.69" + attribute \src "ls180.v:615.6-615.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:621.11-621.66" + attribute \src "ls180.v:624.11-624.66" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:622.13-622.70" + attribute \src "ls180.v:625.13-625.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:624.13-624.70" + attribute \src "ls180.v:627.13-627.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:623.6-623.60" + attribute \src "ls180.v:626.6-626.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:638.6-638.51" + attribute \src "ls180.v:641.6-641.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:639.6-639.50" + attribute \src "ls180.v:642.6-642.50" wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:641.13-641.65" + attribute \src "ls180.v:644.13-644.65" wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:640.6-640.56" + attribute \src "ls180.v:643.6-643.56" wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:637.6-637.51" + attribute \src "ls180.v:640.6-640.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:636.6-636.51" + attribute \src "ls180.v:639.6-639.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:644.5-644.52" + attribute \src "ls180.v:647.5-647.52" wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:645.5-645.51" + attribute \src "ls180.v:648.5-648.51" wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:647.12-647.66" + attribute \src "ls180.v:650.12-650.66" wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:646.5-646.57" + attribute \src "ls180.v:649.5-649.57" wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:643.6-643.53" + attribute \src "ls180.v:646.6-646.53" wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:642.5-642.52" + attribute \src "ls180.v:645.5-645.52" wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:590.12-590.49" + attribute \src "ls180.v:593.12-593.49" wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:591.12-591.50" + attribute \src "ls180.v:594.12-594.50" wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:592.5-592.44" + attribute \src "ls180.v:595.5-595.44" wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:595.5-595.47" + attribute \src "ls180.v:598.5-598.47" wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:596.5-596.48" + attribute \src "ls180.v:599.5-599.48" wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:597.5-597.49" + attribute \src "ls180.v:600.5-600.49" wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:593.5-593.44" + attribute \src "ls180.v:596.5-596.44" wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:594.5-594.43" + attribute \src "ls180.v:597.5-597.43" wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:589.5-589.38" + attribute \src "ls180.v:592.5-592.38" wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:588.5-588.38" + attribute \src "ls180.v:591.5-591.38" wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:587.5-587.40" + attribute \src "ls180.v:590.5-590.40" wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:586.6-586.41" + attribute \src "ls180.v:589.6-589.41" wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:582.13-582.45" + attribute \src "ls180.v:585.13-585.45" wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:583.6-583.38" + attribute \src "ls180.v:586.6-586.38" wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:585.5-585.44" + attribute \src "ls180.v:588.5-588.44" wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:580.6-580.39" + attribute \src "ls180.v:583.6-583.39" wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:579.6-579.39" + attribute \src "ls180.v:582.6-582.39" wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:584.5-584.44" + attribute \src "ls180.v:587.5-587.44" wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:581.6-581.36" + attribute \src "ls180.v:584.6-584.36" wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:648.12-648.39" + attribute \src "ls180.v:651.12-651.39" wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:652.5-652.38" + attribute \src "ls180.v:655.5-655.38" wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:653.5-653.47" + attribute \src "ls180.v:656.5-656.47" wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:650.6-650.37" + attribute \src "ls180.v:653.6-653.37" wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:651.5-651.37" + attribute \src "ls180.v:654.5-654.37" wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:649.5-649.39" + attribute \src "ls180.v:652.5-652.39" wire \main_sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:660.32-660.69" + attribute \src "ls180.v:663.32-663.69" wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:659.6-659.43" + attribute \src "ls180.v:662.6-662.43" wire \main_sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:658.32-658.68" + attribute \src "ls180.v:661.32-661.68" wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:657.6-657.42" + attribute \src "ls180.v:660.6-660.42" wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:656.11-656.48" + attribute \src "ls180.v:659.11-659.48" wire width 3 \main_sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:655.32-655.69" + attribute \src "ls180.v:658.32-658.69" wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:654.6-654.43" + attribute \src "ls180.v:657.6-657.43" wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:680.5-680.43" + attribute \src "ls180.v:683.5-683.43" wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:702.11-702.63" + attribute \src "ls180.v:705.11-705.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:707.6-707.58" + attribute \src "ls180.v:710.6-710.58" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:712.6-712.64" + attribute \src "ls180.v:715.6-715.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:713.6-713.63" + attribute \src "ls180.v:716.6-716.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:711.13-711.78" + attribute \src "ls180.v:714.13-714.78" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:710.6-710.69" + attribute \src "ls180.v:713.6-713.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:716.6-716.65" + attribute \src "ls180.v:719.6-719.65" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:717.6-717.64" + attribute \src "ls180.v:720.6-720.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:715.13-715.79" + attribute \src "ls180.v:718.13-718.79" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:714.6-714.70" + attribute \src "ls180.v:717.6-717.70" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:699.11-699.61" + attribute \src "ls180.v:702.11-702.61" wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:701.11-701.63" + attribute \src "ls180.v:704.11-704.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:708.12-708.67" + attribute \src "ls180.v:711.12-711.67" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:709.13-709.70" + attribute \src "ls180.v:712.13-712.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:700.5-700.57" + attribute \src "ls180.v:703.5-703.57" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:683.5-683.60" + attribute \src "ls180.v:686.5-686.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:684.5-684.59" + attribute \src "ls180.v:687.5-687.59" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:686.13-686.75" + attribute \src "ls180.v:689.13-689.75" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:685.6-685.66" + attribute \src "ls180.v:688.6-688.66" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:682.6-682.61" + attribute \src "ls180.v:685.6-685.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:681.6-681.61" + attribute \src "ls180.v:684.6-684.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:689.6-689.63" + attribute \src "ls180.v:692.6-692.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:690.6-690.62" + attribute \src "ls180.v:693.6-693.62" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:692.13-692.77" + attribute \src "ls180.v:695.13-695.77" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:691.6-691.68" + attribute \src "ls180.v:694.6-694.68" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:688.6-688.63" + attribute \src "ls180.v:691.6-691.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:687.6-687.63" + attribute \src "ls180.v:690.6-690.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:697.13-697.71" + attribute \src "ls180.v:700.13-700.71" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:698.13-698.72" + attribute \src "ls180.v:701.13-701.72" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:695.6-695.63" + attribute \src "ls180.v:698.6-698.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:696.6-696.69" + attribute \src "ls180.v:699.6-699.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:693.6-693.63" + attribute \src "ls180.v:696.6-696.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:694.6-694.69" + attribute \src "ls180.v:697.6-697.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:703.11-703.66" + attribute \src "ls180.v:706.11-706.66" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:704.13-704.70" + attribute \src "ls180.v:707.13-707.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:706.13-706.70" + attribute \src "ls180.v:709.13-709.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:705.6-705.60" + attribute \src "ls180.v:708.6-708.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:720.6-720.51" + attribute \src "ls180.v:723.6-723.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:721.6-721.50" + attribute \src "ls180.v:724.6-724.50" wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:723.13-723.65" + attribute \src "ls180.v:726.13-726.65" wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:722.6-722.56" + attribute \src "ls180.v:725.6-725.56" wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:719.6-719.51" + attribute \src "ls180.v:722.6-722.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:718.6-718.51" + attribute \src "ls180.v:721.6-721.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:726.5-726.52" + attribute \src "ls180.v:729.5-729.52" wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:727.5-727.51" + attribute \src "ls180.v:730.5-730.51" wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:729.12-729.66" + attribute \src "ls180.v:732.12-732.66" wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:728.5-728.57" + attribute \src "ls180.v:731.5-731.57" wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:725.6-725.53" + attribute \src "ls180.v:728.6-728.53" wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:724.5-724.52" + attribute \src "ls180.v:727.5-727.52" wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:672.12-672.49" + attribute \src "ls180.v:675.12-675.49" wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:673.12-673.50" + attribute \src "ls180.v:676.12-676.50" wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:674.5-674.44" + attribute \src "ls180.v:677.5-677.44" wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:677.5-677.47" + attribute \src "ls180.v:680.5-680.47" wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:678.5-678.48" + attribute \src "ls180.v:681.5-681.48" wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:679.5-679.49" + attribute \src "ls180.v:682.5-682.49" wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:675.5-675.44" + attribute \src "ls180.v:678.5-678.44" wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:676.5-676.43" + attribute \src "ls180.v:679.5-679.43" wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:671.5-671.38" + attribute \src "ls180.v:674.5-674.38" wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:670.5-670.38" + attribute \src "ls180.v:673.5-673.38" wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:669.5-669.40" + attribute \src "ls180.v:672.5-672.40" wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:668.6-668.41" + attribute \src "ls180.v:671.6-671.41" wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:664.13-664.45" + attribute \src "ls180.v:667.13-667.45" wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:665.6-665.38" + attribute \src "ls180.v:668.6-668.38" wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:667.5-667.44" + attribute \src "ls180.v:670.5-670.44" wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:662.6-662.39" + attribute \src "ls180.v:665.6-665.39" wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:661.6-661.39" + attribute \src "ls180.v:664.6-664.39" wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:666.5-666.44" + attribute \src "ls180.v:669.5-669.44" wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:663.6-663.36" + attribute \src "ls180.v:666.6-666.36" wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:730.12-730.39" + attribute \src "ls180.v:733.12-733.39" wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:734.5-734.38" + attribute \src "ls180.v:737.5-737.38" wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:735.5-735.47" + attribute \src "ls180.v:738.5-738.47" wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:732.6-732.37" + attribute \src "ls180.v:735.6-735.37" wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:733.5-733.37" + attribute \src "ls180.v:736.5-736.37" wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:731.5-731.39" + attribute \src "ls180.v:734.5-734.39" wire \main_sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:742.32-742.69" + attribute \src "ls180.v:745.32-745.69" wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:741.6-741.43" + attribute \src "ls180.v:744.6-744.43" wire \main_sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:740.32-740.68" + attribute \src "ls180.v:743.32-743.68" wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:739.6-739.42" + attribute \src "ls180.v:742.6-742.42" wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:738.11-738.48" + attribute \src "ls180.v:741.11-741.48" wire width 3 \main_sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:737.32-737.69" + attribute \src "ls180.v:740.32-740.69" wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:736.6-736.43" + attribute \src "ls180.v:739.6-739.43" wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:762.5-762.43" + attribute \src "ls180.v:765.5-765.43" wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:784.11-784.63" + attribute \src "ls180.v:787.11-787.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:789.6-789.58" + attribute \src "ls180.v:792.6-792.58" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:794.6-794.64" + attribute \src "ls180.v:797.6-797.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:795.6-795.63" + attribute \src "ls180.v:798.6-798.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:793.13-793.78" + attribute \src "ls180.v:796.13-796.78" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:792.6-792.69" + attribute \src "ls180.v:795.6-795.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:798.6-798.65" + attribute \src "ls180.v:801.6-801.65" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:799.6-799.64" + attribute \src "ls180.v:802.6-802.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:797.13-797.79" + attribute \src "ls180.v:800.13-800.79" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:796.6-796.70" + attribute \src "ls180.v:799.6-799.70" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:781.11-781.61" + attribute \src "ls180.v:784.11-784.61" wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:783.11-783.63" + attribute \src "ls180.v:786.11-786.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:790.12-790.67" + attribute \src "ls180.v:793.12-793.67" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:791.13-791.70" + attribute \src "ls180.v:794.13-794.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:782.5-782.57" + attribute \src "ls180.v:785.5-785.57" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:765.5-765.60" + attribute \src "ls180.v:768.5-768.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:766.5-766.59" + attribute \src "ls180.v:769.5-769.59" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:768.13-768.75" + attribute \src "ls180.v:771.13-771.75" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:767.6-767.66" + attribute \src "ls180.v:770.6-770.66" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:764.6-764.61" + attribute \src "ls180.v:767.6-767.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:763.6-763.61" + attribute \src "ls180.v:766.6-766.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:771.6-771.63" + attribute \src "ls180.v:774.6-774.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:772.6-772.62" + attribute \src "ls180.v:775.6-775.62" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:774.13-774.77" + attribute \src "ls180.v:777.13-777.77" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:773.6-773.68" + attribute \src "ls180.v:776.6-776.68" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:770.6-770.63" + attribute \src "ls180.v:773.6-773.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:769.6-769.63" + attribute \src "ls180.v:772.6-772.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:779.13-779.71" + attribute \src "ls180.v:782.13-782.71" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:780.13-780.72" + attribute \src "ls180.v:783.13-783.72" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:777.6-777.63" + attribute \src "ls180.v:780.6-780.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:778.6-778.69" + attribute \src "ls180.v:781.6-781.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:775.6-775.63" + attribute \src "ls180.v:778.6-778.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:776.6-776.69" + attribute \src "ls180.v:779.6-779.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:785.11-785.66" + attribute \src "ls180.v:788.11-788.66" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:786.13-786.70" + attribute \src "ls180.v:789.13-789.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:788.13-788.70" + attribute \src "ls180.v:791.13-791.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:787.6-787.60" + attribute \src "ls180.v:790.6-790.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:802.6-802.51" + attribute \src "ls180.v:805.6-805.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:803.6-803.50" + attribute \src "ls180.v:806.6-806.50" wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:805.13-805.65" + attribute \src "ls180.v:808.13-808.65" wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:804.6-804.56" + attribute \src "ls180.v:807.6-807.56" wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:801.6-801.51" + attribute \src "ls180.v:804.6-804.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:800.6-800.51" + attribute \src "ls180.v:803.6-803.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:808.5-808.52" + attribute \src "ls180.v:811.5-811.52" wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:809.5-809.51" + attribute \src "ls180.v:812.5-812.51" wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:811.12-811.66" + attribute \src "ls180.v:814.12-814.66" wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:810.5-810.57" + attribute \src "ls180.v:813.5-813.57" wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:807.6-807.53" + attribute \src "ls180.v:810.6-810.53" wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:806.5-806.52" + attribute \src "ls180.v:809.5-809.52" wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:754.12-754.49" + attribute \src "ls180.v:757.12-757.49" wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:755.12-755.50" + attribute \src "ls180.v:758.12-758.50" wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:756.5-756.44" + attribute \src "ls180.v:759.5-759.44" wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:759.5-759.47" + attribute \src "ls180.v:762.5-762.47" wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:760.5-760.48" + attribute \src "ls180.v:763.5-763.48" wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:761.5-761.49" + attribute \src "ls180.v:764.5-764.49" wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:757.5-757.44" + attribute \src "ls180.v:760.5-760.44" wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:758.5-758.43" + attribute \src "ls180.v:761.5-761.43" wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:753.5-753.38" + attribute \src "ls180.v:756.5-756.38" wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:752.5-752.38" + attribute \src "ls180.v:755.5-755.38" wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:751.5-751.40" + attribute \src "ls180.v:754.5-754.40" wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:750.6-750.41" + attribute \src "ls180.v:753.6-753.41" wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:746.13-746.45" + attribute \src "ls180.v:749.13-749.45" wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:747.6-747.38" + attribute \src "ls180.v:750.6-750.38" wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:749.5-749.44" + attribute \src "ls180.v:752.5-752.44" wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:744.6-744.39" + attribute \src "ls180.v:747.6-747.39" wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:743.6-743.39" + attribute \src "ls180.v:746.6-746.39" wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:748.5-748.44" + attribute \src "ls180.v:751.5-751.44" wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:745.6-745.36" + attribute \src "ls180.v:748.6-748.36" wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:812.12-812.39" + attribute \src "ls180.v:815.12-815.39" wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:816.5-816.38" + attribute \src "ls180.v:819.5-819.38" wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:817.5-817.47" + attribute \src "ls180.v:820.5-820.47" wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:814.6-814.37" + attribute \src "ls180.v:817.6-817.37" wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:815.5-815.37" + attribute \src "ls180.v:818.5-818.37" wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:813.5-813.39" + attribute \src "ls180.v:816.5-816.39" wire \main_sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:824.32-824.69" + attribute \src "ls180.v:827.32-827.69" wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:823.6-823.43" + attribute \src "ls180.v:826.6-826.43" wire \main_sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:822.32-822.68" + attribute \src "ls180.v:825.32-825.68" wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:821.6-821.42" + attribute \src "ls180.v:824.6-824.42" wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:820.11-820.48" + attribute \src "ls180.v:823.11-823.48" wire width 3 \main_sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:819.32-819.69" + attribute \src "ls180.v:822.32-822.69" wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:818.6-818.43" + attribute \src "ls180.v:821.6-821.43" wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:826.6-826.28" + attribute \src "ls180.v:829.6-829.28" wire \main_sdram_cas_allowed - attribute \src "ls180.v:844.6-844.30" + attribute \src "ls180.v:847.6-847.30" wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:833.13-833.48" + attribute \src "ls180.v:836.13-836.48" wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:834.12-834.48" + attribute \src "ls180.v:837.12-837.48" wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:835.5-835.42" + attribute \src "ls180.v:838.5-838.42" wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:838.6-838.46" + attribute \src "ls180.v:841.6-841.46" wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:839.6-839.47" + attribute \src "ls180.v:842.6-842.47" wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:840.6-840.48" + attribute \src "ls180.v:843.6-843.48" wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:836.5-836.42" + attribute \src "ls180.v:839.5-839.42" wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:837.5-837.41" + attribute \src "ls180.v:840.5-840.41" wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:832.5-832.36" + attribute \src "ls180.v:835.5-835.36" wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:831.6-831.37" + attribute \src "ls180.v:834.6-834.37" wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:843.11-843.38" + attribute \src "ls180.v:846.11-846.38" wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:842.12-842.41" + attribute \src "ls180.v:845.12-845.41" wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:841.11-841.39" + attribute \src "ls180.v:844.11-844.39" wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:830.5-830.41" + attribute \src "ls180.v:833.5-833.41" wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:829.5-829.36" + attribute \src "ls180.v:832.5-832.36" wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:827.5-827.37" + attribute \src "ls180.v:830.5-830.37" wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:828.5-828.38" + attribute \src "ls180.v:831.5-831.38" wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:862.6-862.30" + attribute \src "ls180.v:865.6-865.30" wire \main_sdram_choose_req_ce - attribute \src "ls180.v:851.13-851.48" + attribute \src "ls180.v:854.13-854.48" wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:852.12-852.48" + attribute \src "ls180.v:855.12-855.48" wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:853.5-853.42" + attribute \src "ls180.v:856.5-856.42" wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:856.6-856.46" + attribute \src "ls180.v:859.6-859.46" wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:857.6-857.47" + attribute \src "ls180.v:860.6-860.47" wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:858.6-858.48" + attribute \src "ls180.v:861.6-861.48" wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:854.5-854.42" + attribute \src "ls180.v:857.5-857.42" wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:855.5-855.41" + attribute \src "ls180.v:858.5-858.41" wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:850.5-850.36" + attribute \src "ls180.v:853.5-853.36" wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:849.6-849.37" + attribute \src "ls180.v:852.6-852.37" wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:861.11-861.38" + attribute \src "ls180.v:864.11-864.38" wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:860.12-860.41" + attribute \src "ls180.v:863.12-863.41" wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:859.11-859.39" + attribute \src "ls180.v:862.11-862.39" wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:848.5-848.41" + attribute \src "ls180.v:851.5-851.41" wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:847.6-847.37" + attribute \src "ls180.v:850.6-850.37" wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:845.5-845.37" + attribute \src "ls180.v:848.5-848.37" wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:846.5-846.38" + attribute \src "ls180.v:849.5-849.38" wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:406.6-406.20" + attribute \src "ls180.v:409.6-409.20" wire \main_sdram_cke - attribute \src "ls180.v:474.5-474.24" + attribute \src "ls180.v:477.5-477.24" wire \main_sdram_cmd_last - attribute \src "ls180.v:475.12-475.36" + attribute \src "ls180.v:478.12-478.36" wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:476.11-476.36" + attribute \src "ls180.v:479.11-479.36" wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:477.5-477.31" + attribute \src "ls180.v:480.5-480.31" wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:480.5-480.35" + attribute \src "ls180.v:483.5-483.35" wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:481.5-481.36" + attribute \src "ls180.v:484.5-484.36" wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:478.5-478.31" + attribute \src "ls180.v:481.5-481.31" wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:479.5-479.30" + attribute \src "ls180.v:482.5-482.30" wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:473.5-473.25" + attribute \src "ls180.v:476.5-476.25" wire \main_sdram_cmd_ready - attribute \src "ls180.v:472.5-472.25" + attribute \src "ls180.v:475.5-475.25" wire \main_sdram_cmd_valid - attribute \src "ls180.v:414.6-414.32" + attribute \src "ls180.v:417.6-417.32" wire \main_sdram_command_issue_r - attribute \src "ls180.v:413.6-413.33" + attribute \src "ls180.v:416.6-416.33" wire \main_sdram_command_issue_re - attribute \src "ls180.v:416.5-416.31" + attribute \src "ls180.v:419.5-419.31" wire \main_sdram_command_issue_w - attribute \src "ls180.v:415.6-415.33" + attribute \src "ls180.v:418.6-418.33" wire \main_sdram_command_issue_we - attribute \src "ls180.v:412.5-412.26" + attribute \src "ls180.v:415.5-415.26" wire \main_sdram_command_re - attribute \src "ls180.v:411.11-411.37" + attribute \src "ls180.v:414.11-414.37" wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:465.5-465.28" + attribute \src "ls180.v:468.5-468.28" wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:456.12-456.37" + attribute \src "ls180.v:459.12-459.37" wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:457.11-457.33" + attribute \src "ls180.v:460.11-460.33" wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:458.5-458.28" + attribute \src "ls180.v:461.5-461.28" wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:462.6-462.27" + attribute \src "ls180.v:465.6-465.27" wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:459.5-459.27" + attribute \src "ls180.v:462.5-462.27" wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:463.6-463.27" + attribute \src "ls180.v:466.6-466.27" wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:460.5-460.28" + attribute \src "ls180.v:463.5-463.28" wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:470.13-470.37" + attribute \src "ls180.v:473.13-473.37" wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:469.5-469.32" + attribute \src "ls180.v:472.5-472.32" wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:471.6-471.36" + attribute \src "ls180.v:474.6-474.36" wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:464.6-464.31" + attribute \src "ls180.v:467.6-467.31" wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:461.5-461.27" + attribute \src "ls180.v:464.5-464.27" wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:466.13-466.37" + attribute \src "ls180.v:469.13-469.37" wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:467.5-467.32" + attribute \src "ls180.v:470.5-470.32" wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:468.12-468.41" + attribute \src "ls180.v:471.12-471.41" wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:880.5-880.19" - wire \main_sdram_en0 attribute \src "ls180.v:883.5-883.19" + wire \main_sdram_en0 + attribute \src "ls180.v:886.5-886.19" wire \main_sdram_en1 - attribute \src "ls180.v:886.6-886.30" + attribute \src "ls180.v:889.6-889.30" wire \main_sdram_go_to_refresh - attribute \src "ls180.v:428.13-428.44" + attribute \src "ls180.v:431.13-431.44" wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:429.6-429.37" + attribute \src "ls180.v:432.6-432.37" wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:431.6-431.44" + attribute \src "ls180.v:434.6-434.44" wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:426.6-426.38" + attribute \src "ls180.v:429.6-429.38" wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:425.6-425.38" + attribute \src "ls180.v:428.6-428.38" wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:430.6-430.44" + attribute \src "ls180.v:433.6-433.44" wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:427.6-427.35" + attribute \src "ls180.v:430.6-430.35" wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:435.13-435.44" + attribute \src "ls180.v:438.13-438.44" wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:436.6-436.37" + attribute \src "ls180.v:439.6-439.37" wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:438.6-438.44" + attribute \src "ls180.v:441.6-441.44" wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:433.6-433.38" + attribute \src "ls180.v:436.6-436.38" wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:432.6-432.38" + attribute \src "ls180.v:435.6-435.38" wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:437.6-437.44" + attribute \src "ls180.v:440.6-440.44" wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:434.6-434.35" + attribute \src "ls180.v:437.6-437.35" wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:442.13-442.44" + attribute \src "ls180.v:445.13-445.44" wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:443.6-443.37" + attribute \src "ls180.v:446.6-446.37" wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:445.6-445.44" + attribute \src "ls180.v:448.6-448.44" wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:440.6-440.38" + attribute \src "ls180.v:443.6-443.38" wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:439.6-439.38" + attribute \src "ls180.v:442.6-442.38" wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:444.6-444.44" + attribute \src "ls180.v:447.6-447.44" wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:441.6-441.35" + attribute \src "ls180.v:444.6-444.35" wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:449.13-449.44" + attribute \src "ls180.v:452.13-452.44" wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:450.6-450.37" + attribute \src "ls180.v:453.6-453.37" wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:452.6-452.44" + attribute \src "ls180.v:455.6-455.44" wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:447.6-447.38" + attribute \src "ls180.v:450.6-450.38" wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:446.6-446.38" + attribute \src "ls180.v:449.6-449.38" wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:451.6-451.44" + attribute \src "ls180.v:454.6-454.44" wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:448.6-448.35" + attribute \src "ls180.v:451.6-451.35" wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:455.13-455.39" + attribute \src "ls180.v:458.13-458.39" wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:453.12-453.38" + attribute \src "ls180.v:456.12-456.38" wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:454.11-454.40" + attribute \src "ls180.v:457.11-457.40" wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:366.5-366.29" + attribute \src "ls180.v:369.5-369.29" wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:357.13-357.39" + attribute \src "ls180.v:360.13-360.39" wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:358.12-358.35" + attribute \src "ls180.v:361.12-361.35" wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:359.5-359.29" + attribute \src "ls180.v:362.5-362.29" wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:363.6-363.28" + attribute \src "ls180.v:366.6-366.28" wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:360.5-360.28" + attribute \src "ls180.v:363.5-363.28" wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:364.6-364.28" + attribute \src "ls180.v:367.6-367.28" wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:361.5-361.29" + attribute \src "ls180.v:364.5-364.29" wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:371.12-371.37" + attribute \src "ls180.v:374.12-374.37" wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:370.6-370.34" + attribute \src "ls180.v:373.6-373.34" wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:372.5-372.36" + attribute \src "ls180.v:375.5-375.36" wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:365.6-365.32" + attribute \src "ls180.v:368.6-368.32" wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:362.5-362.28" + attribute \src "ls180.v:365.5-365.28" wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:367.13-367.38" + attribute \src "ls180.v:370.13-370.38" wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:368.6-368.34" + attribute \src "ls180.v:371.6-371.34" wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:369.12-369.42" + attribute \src "ls180.v:372.12-372.42" wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:398.5-398.31" + attribute \src "ls180.v:401.5-401.31" wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:389.12-389.40" + attribute \src "ls180.v:392.12-392.40" wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:390.11-390.36" + attribute \src "ls180.v:393.11-393.36" wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:391.5-391.31" + attribute \src "ls180.v:394.5-394.31" wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:395.5-395.29" + attribute \src "ls180.v:398.5-398.29" wire \main_sdram_master_p0_cke - attribute \src "ls180.v:392.5-392.30" + attribute \src "ls180.v:395.5-395.30" wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:396.5-396.29" + attribute \src "ls180.v:399.5-399.29" wire \main_sdram_master_p0_odt - attribute \src "ls180.v:393.5-393.31" + attribute \src "ls180.v:396.5-396.31" wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:403.13-403.40" + attribute \src "ls180.v:406.13-406.40" wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:402.5-402.35" + attribute \src "ls180.v:405.5-405.35" wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:404.6-404.39" + attribute \src "ls180.v:407.6-407.39" wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:397.5-397.33" + attribute \src "ls180.v:400.5-400.33" wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:394.5-394.30" + attribute \src "ls180.v:397.5-397.30" wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:399.12-399.39" + attribute \src "ls180.v:402.12-402.39" wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:400.5-400.35" + attribute \src "ls180.v:403.5-403.35" wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:401.11-401.43" + attribute \src "ls180.v:404.11-404.43" wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:881.6-881.26" - wire \main_sdram_max_time0 attribute \src "ls180.v:884.6-884.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:887.6-887.26" wire \main_sdram_max_time1 - attribute \src "ls180.v:863.12-863.28" + attribute \src "ls180.v:866.12-866.28" wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:864.11-864.28" + attribute \src "ls180.v:867.11-867.28" wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:407.6-407.20" + attribute \src "ls180.v:410.6-410.20" wire \main_sdram_odt - attribute \src "ls180.v:490.5-490.31" + attribute \src "ls180.v:493.5-493.31" wire \main_sdram_postponer_count - attribute \src "ls180.v:488.6-488.32" + attribute \src "ls180.v:491.6-491.32" wire \main_sdram_postponer_req_i - attribute \src "ls180.v:489.5-489.31" + attribute \src "ls180.v:492.5-492.31" wire \main_sdram_postponer_req_o - attribute \src "ls180.v:825.6-825.28" + attribute \src "ls180.v:828.6-828.28" wire \main_sdram_ras_allowed - attribute \src "ls180.v:410.5-410.18" + attribute \src "ls180.v:413.5-413.18" wire \main_sdram_re - attribute \src "ls180.v:878.6-878.31" + attribute \src "ls180.v:881.6-881.31" wire \main_sdram_read_available - attribute \src "ls180.v:408.6-408.24" + attribute \src "ls180.v:411.6-411.24" wire \main_sdram_reset_n - attribute \src "ls180.v:405.6-405.20" + attribute \src "ls180.v:408.6-408.20" wire \main_sdram_sel - attribute \src "ls180.v:496.5-496.31" + attribute \src "ls180.v:499.5-499.31" wire \main_sdram_sequencer_count - attribute \src "ls180.v:495.11-495.39" + attribute \src "ls180.v:498.11-498.39" wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:492.6-492.32" + attribute \src "ls180.v:495.6-495.32" wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:494.5-494.31" + attribute \src "ls180.v:497.5-497.31" wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:491.5-491.32" + attribute \src "ls180.v:494.5-494.32" wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:493.6-493.33" + attribute \src "ls180.v:496.6-496.33" wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:382.6-382.31" + attribute \src "ls180.v:385.6-385.31" wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:373.13-373.40" + attribute \src "ls180.v:376.13-376.40" wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:374.12-374.36" + attribute \src "ls180.v:377.12-377.36" wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:375.6-375.31" + attribute \src "ls180.v:378.6-378.31" wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:379.6-379.29" + attribute \src "ls180.v:382.6-382.29" wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:376.6-376.30" + attribute \src "ls180.v:379.6-379.30" wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:380.6-380.29" + attribute \src "ls180.v:383.6-383.29" wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:377.6-377.31" + attribute \src "ls180.v:380.6-380.31" wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:387.12-387.38" + attribute \src "ls180.v:390.12-390.38" wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:386.6-386.35" + attribute \src "ls180.v:389.6-389.35" wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:388.5-388.37" + attribute \src "ls180.v:391.5-391.37" wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:381.6-381.33" + attribute \src "ls180.v:384.6-384.33" wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:378.6-378.30" + attribute \src "ls180.v:381.6-381.30" wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:383.13-383.39" + attribute \src "ls180.v:386.13-386.39" wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:384.6-384.35" + attribute \src "ls180.v:387.6-387.35" wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:385.12-385.43" + attribute \src "ls180.v:388.12-388.43" wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:423.12-423.29" + attribute \src "ls180.v:426.12-426.29" wire width 16 \main_sdram_status - attribute \src "ls180.v:866.5-866.24" + attribute \src "ls180.v:869.5-869.24" wire \main_sdram_steerer0 - attribute \src "ls180.v:867.5-867.24" + attribute \src "ls180.v:870.5-870.24" wire \main_sdram_steerer1 - attribute \src "ls180.v:865.11-865.33" + attribute \src "ls180.v:868.11-868.33" wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:409.11-409.29" + attribute \src "ls180.v:412.11-412.29" wire width 4 \main_sdram_storage - attribute \src "ls180.v:874.5-874.29" + attribute \src "ls180.v:877.5-877.29" wire \main_sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:873.32-873.56" + attribute \src "ls180.v:876.32-876.56" wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:872.6-872.30" + attribute \src "ls180.v:875.6-875.30" wire \main_sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:871.32-871.56" + attribute \src "ls180.v:874.32-874.56" wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:870.6-870.30" + attribute \src "ls180.v:873.6-873.30" wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:882.11-882.27" - wire width 5 \main_sdram_time0 attribute \src "ls180.v:885.11-885.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:888.11-888.27" wire width 4 \main_sdram_time1 - attribute \src "ls180.v:485.12-485.35" + attribute \src "ls180.v:488.12-488.35" wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:487.11-487.34" + attribute \src "ls180.v:490.11-490.34" wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:484.6-484.28" + attribute \src "ls180.v:487.6-487.28" wire \main_sdram_timer_done0 - attribute \src "ls180.v:486.6-486.28" + attribute \src "ls180.v:489.6-489.28" wire \main_sdram_timer_done1 - attribute \src "ls180.v:483.6-483.27" + attribute \src "ls180.v:486.6-486.27" wire \main_sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:869.32-869.56" + attribute \src "ls180.v:872.32-872.56" wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:868.6-868.30" + attribute \src "ls180.v:871.6-871.30" wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:877.11-877.35" + attribute \src "ls180.v:880.11-880.35" wire width 3 \main_sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:876.32-876.56" + attribute \src "ls180.v:879.32-879.56" wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:875.6-875.30" + attribute \src "ls180.v:878.6-878.30" wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:482.6-482.30" + attribute \src "ls180.v:485.6-485.30" wire \main_sdram_wants_refresh - attribute \src "ls180.v:424.6-424.19" + attribute \src "ls180.v:427.6-427.19" wire \main_sdram_we - attribute \src "ls180.v:422.5-422.25" + attribute \src "ls180.v:425.5-425.25" wire \main_sdram_wrdata_re - attribute \src "ls180.v:421.12-421.37" + attribute \src "ls180.v:424.12-424.37" wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:879.6-879.32" + attribute \src "ls180.v:882.6-882.32" wire \main_sdram_write_available - attribute \src "ls180.v:914.5-914.47" + attribute \src "ls180.v:917.5-917.47" wire \main_socbushandler_converted_interface_ack - attribute \src "ls180.v:908.13-908.55" + attribute \src "ls180.v:911.13-911.55" wire width 30 \main_socbushandler_converted_interface_adr - attribute \src "ls180.v:917.12-917.54" + attribute \src "ls180.v:920.12-920.54" wire width 2 \main_socbushandler_converted_interface_bte - attribute \src "ls180.v:916.12-916.54" + attribute \src "ls180.v:919.12-919.54" wire width 3 \main_socbushandler_converted_interface_cti - attribute \src "ls180.v:912.6-912.48" + attribute \src "ls180.v:915.6-915.48" wire \main_socbushandler_converted_interface_cyc - attribute \src "ls180.v:910.13-910.57" + attribute \src "ls180.v:913.13-913.57" wire width 64 \main_socbushandler_converted_interface_dat_r - attribute \src "ls180.v:909.13-909.57" + attribute \src "ls180.v:912.13-912.57" wire width 64 \main_socbushandler_converted_interface_dat_w - attribute \src "ls180.v:918.5-918.47" + attribute \src "ls180.v:921.5-921.47" wire \main_socbushandler_converted_interface_err - attribute \src "ls180.v:911.12-911.54" + attribute \src "ls180.v:914.12-914.54" wire width 8 \main_socbushandler_converted_interface_sel - attribute \src "ls180.v:913.6-913.48" + attribute \src "ls180.v:916.6-916.48" wire \main_socbushandler_converted_interface_stb - attribute \src "ls180.v:915.6-915.47" + attribute \src "ls180.v:918.6-918.47" wire \main_socbushandler_converted_interface_we - attribute \src "ls180.v:920.5-920.31" + attribute \src "ls180.v:923.5-923.31" wire \main_socbushandler_counter - attribute \src "ls180.v:1849.5-1849.53" + attribute \src "ls180.v:1852.5-1852.53" wire \main_socbushandler_counter_converter2_next_value - attribute \src "ls180.v:1850.5-1850.56" + attribute \src "ls180.v:1853.5-1853.56" wire \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:922.12-922.36" + attribute \src "ls180.v:925.12-925.36" wire width 64 \main_socbushandler_dat_r - attribute \src "ls180.v:921.6-921.30" + attribute \src "ls180.v:924.6-924.30" wire \main_socbushandler_reset - attribute \src "ls180.v:919.5-919.28" + attribute \src "ls180.v:922.5-922.28" wire \main_socbushandler_skip - attribute \src "ls180.v:1097.6-1097.27" + attribute \src "ls180.v:1100.6-1100.27" wire \main_spimaster0_start - attribute \src "ls180.v:1107.12-1107.35" + attribute \src "ls180.v:1110.12-1110.35" wire width 8 \main_spimaster10_length - attribute \src "ls180.v:1108.12-1108.36" + attribute \src "ls180.v:1111.12-1111.36" wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1109.5-1109.24" + attribute \src "ls180.v:1112.5-1112.24" wire \main_spimaster12_re - attribute \src "ls180.v:1110.6-1110.27" + attribute \src "ls180.v:1113.6-1113.27" wire \main_spimaster13_done - attribute \src "ls180.v:1111.6-1111.29" + attribute \src "ls180.v:1114.6-1114.29" wire \main_spimaster14_status - attribute \src "ls180.v:1112.6-1112.25" + attribute \src "ls180.v:1115.6-1115.25" wire \main_spimaster15_we - attribute \src "ls180.v:1113.11-1113.35" + attribute \src "ls180.v:1116.11-1116.35" wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1114.5-1114.24" + attribute \src "ls180.v:1117.5-1117.24" wire \main_spimaster17_re - attribute \src "ls180.v:1115.12-1115.35" + attribute \src "ls180.v:1118.12-1118.35" wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1116.6-1116.25" + attribute \src "ls180.v:1119.6-1119.25" wire \main_spimaster19_we - attribute \src "ls180.v:1098.12-1098.34" + attribute \src "ls180.v:1101.12-1101.34" wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1170.5-1170.23" + attribute \src "ls180.v:1173.5-1173.23" wire \main_spimaster1_re - attribute \src "ls180.v:1169.12-1169.35" + attribute \src "ls180.v:1172.12-1172.35" wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1117.6-1117.26" + attribute \src "ls180.v:1120.6-1120.26" wire \main_spimaster20_sel - attribute \src "ls180.v:1118.5-1118.29" + attribute \src "ls180.v:1121.5-1121.29" wire \main_spimaster21_storage - attribute \src "ls180.v:1119.5-1119.24" + attribute \src "ls180.v:1122.5-1122.24" wire \main_spimaster22_re - attribute \src "ls180.v:1120.5-1120.29" + attribute \src "ls180.v:1123.5-1123.29" wire \main_spimaster23_storage - attribute \src "ls180.v:1121.5-1121.24" + attribute \src "ls180.v:1124.5-1124.24" wire \main_spimaster24_re - attribute \src "ls180.v:1122.5-1122.32" + attribute \src "ls180.v:1125.5-1125.32" wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1123.5-1123.31" + attribute \src "ls180.v:1126.5-1126.31" wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1124.11-1124.33" + attribute \src "ls180.v:1127.11-1127.33" wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1890.11-1890.55" + attribute \src "ls180.v:1893.11-1893.55" wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1891.5-1891.52" + attribute \src "ls180.v:1894.5-1894.52" wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1125.5-1125.32" + attribute \src "ls180.v:1128.5-1128.32" wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1126.5-1126.32" + attribute \src "ls180.v:1129.5-1129.32" wire \main_spimaster29_miso_latch - attribute \src "ls180.v:1099.5-1099.25" + attribute \src "ls180.v:1102.5-1102.25" wire \main_spimaster2_done - attribute \src "ls180.v:1127.12-1127.40" + attribute \src "ls180.v:1130.12-1130.40" wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1128.6-1128.31" + attribute \src "ls180.v:1131.6-1131.31" wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1129.6-1129.31" + attribute \src "ls180.v:1132.6-1132.31" wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1130.11-1130.37" + attribute \src "ls180.v:1133.11-1133.37" wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1131.11-1131.36" + attribute \src "ls180.v:1134.11-1134.36" wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1132.11-1132.37" + attribute \src "ls180.v:1135.11-1135.37" wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:1100.5-1100.24" + attribute \src "ls180.v:1103.5-1103.24" wire \main_spimaster3_irq - attribute \src "ls180.v:1101.12-1101.32" + attribute \src "ls180.v:1104.12-1104.32" wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:1102.11-1102.31" + attribute \src "ls180.v:1105.11-1105.31" wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:1103.6-1103.24" + attribute \src "ls180.v:1106.6-1106.24" wire \main_spimaster6_cs - attribute \src "ls180.v:1104.6-1104.30" + attribute \src "ls180.v:1107.6-1107.30" wire \main_spimaster7_loopback - attribute \src "ls180.v:1105.12-1105.39" + attribute \src "ls180.v:1108.12-1108.39" wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:1106.5-1106.26" + attribute \src "ls180.v:1109.5-1109.26" wire \main_spimaster9_start - attribute \src "ls180.v:1141.13-1141.40" + attribute \src "ls180.v:1144.13-1144.40" wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1163.12-1163.39" + attribute \src "ls180.v:1166.12-1166.39" wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1158.5-1158.30" + attribute \src "ls180.v:1161.5-1161.30" wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1165.6-1165.29" + attribute \src "ls180.v:1168.6-1168.29" wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1164.6-1164.29" + attribute \src "ls180.v:1167.6-1167.29" wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1145.5-1145.30" + attribute \src "ls180.v:1148.5-1148.30" wire \main_spisdcard_control_re - attribute \src "ls180.v:1144.12-1144.42" + attribute \src "ls180.v:1147.12-1147.42" wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1160.11-1160.31" + attribute \src "ls180.v:1163.11-1163.31" wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1894.11-1894.53" + attribute \src "ls180.v:1897.11-1897.53" wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1895.5-1895.50" + attribute \src "ls180.v:1898.5-1898.50" wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1139.6-1139.23" + attribute \src "ls180.v:1142.6-1142.23" wire \main_spisdcard_cs - attribute \src "ls180.v:1159.5-1159.29" + attribute \src "ls180.v:1162.5-1162.29" wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1155.5-1155.25" + attribute \src "ls180.v:1158.5-1158.25" wire \main_spisdcard_cs_re - attribute \src "ls180.v:1154.5-1154.30" + attribute \src "ls180.v:1157.5-1157.30" wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1135.5-1135.25" + attribute \src "ls180.v:1138.5-1138.25" wire \main_spisdcard_done0 - attribute \src "ls180.v:1146.6-1146.26" + attribute \src "ls180.v:1149.6-1149.26" wire \main_spisdcard_done1 - attribute \src "ls180.v:1136.5-1136.23" + attribute \src "ls180.v:1139.5-1139.23" wire \main_spisdcard_irq - attribute \src "ls180.v:1134.12-1134.34" + attribute \src "ls180.v:1137.12-1137.34" wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1143.12-1143.34" + attribute \src "ls180.v:1146.12-1146.34" wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1140.6-1140.29" + attribute \src "ls180.v:1143.6-1143.29" wire \main_spisdcard_loopback - attribute \src "ls180.v:1157.5-1157.31" + attribute \src "ls180.v:1160.5-1160.31" wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1156.5-1156.36" + attribute \src "ls180.v:1159.5-1159.36" wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1138.11-1138.30" + attribute \src "ls180.v:1141.11-1141.30" wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1168.11-1168.35" + attribute \src "ls180.v:1171.11-1171.35" wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1162.5-1162.30" + attribute \src "ls180.v:1165.5-1165.30" wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1151.12-1151.38" + attribute \src "ls180.v:1154.12-1154.38" wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1152.6-1152.28" + attribute \src "ls180.v:1155.6-1155.28" wire \main_spisdcard_miso_we - attribute \src "ls180.v:1137.12-1137.31" + attribute \src "ls180.v:1140.12-1140.31" wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1166.11-1166.35" + attribute \src "ls180.v:1169.11-1169.35" wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1161.5-1161.30" + attribute \src "ls180.v:1164.5-1164.30" wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1150.5-1150.27" + attribute \src "ls180.v:1153.5-1153.27" wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1167.11-1167.34" + attribute \src "ls180.v:1170.11-1170.34" wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1149.11-1149.38" + attribute \src "ls180.v:1152.11-1152.38" wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1153.6-1153.24" + attribute \src "ls180.v:1156.6-1156.24" wire \main_spisdcard_sel - attribute \src "ls180.v:1133.6-1133.27" + attribute \src "ls180.v:1136.6-1136.27" wire \main_spisdcard_start0 - attribute \src "ls180.v:1142.5-1142.26" + attribute \src "ls180.v:1145.5-1145.26" wire \main_spisdcard_start1 - attribute \src "ls180.v:1147.6-1147.34" + attribute \src "ls180.v:1150.6-1150.34" wire \main_spisdcard_status_status - attribute \src "ls180.v:1148.6-1148.30" + attribute \src "ls180.v:1151.6-1151.30" wire \main_spisdcard_status_we - attribute \src "ls180.v:257.12-257.26" + attribute \src "ls180.v:260.12-260.26" wire width 6 \main_sram0_adr - attribute \src "ls180.v:258.13-258.29" + attribute \src "ls180.v:261.13-261.29" wire width 64 \main_sram0_dat_r - attribute \src "ls180.v:260.13-260.29" + attribute \src "ls180.v:263.13-263.29" wire width 64 \main_sram0_dat_w - attribute \src "ls180.v:259.11-259.24" + attribute \src "ls180.v:262.11-262.24" wire width 8 \main_sram0_we - attribute \src "ls180.v:272.12-272.26" + attribute \src "ls180.v:275.12-275.26" wire width 6 \main_sram1_adr - attribute \src "ls180.v:273.13-273.29" + attribute \src "ls180.v:276.13-276.29" wire width 64 \main_sram1_dat_r - attribute \src "ls180.v:275.13-275.29" + attribute \src "ls180.v:278.13-278.29" wire width 64 \main_sram1_dat_w - attribute \src "ls180.v:274.11-274.24" + attribute \src "ls180.v:277.11-277.24" wire width 8 \main_sram1_we - attribute \src "ls180.v:287.12-287.26" + attribute \src "ls180.v:290.12-290.26" wire width 6 \main_sram2_adr - attribute \src "ls180.v:288.13-288.29" + attribute \src "ls180.v:291.13-291.29" wire width 64 \main_sram2_dat_r - attribute \src "ls180.v:290.13-290.29" + attribute \src "ls180.v:293.13-293.29" wire width 64 \main_sram2_dat_w - attribute \src "ls180.v:289.11-289.24" + attribute \src "ls180.v:292.11-292.24" wire width 8 \main_sram2_we - attribute \src "ls180.v:302.12-302.26" + attribute \src "ls180.v:305.12-305.26" wire width 6 \main_sram3_adr - attribute \src "ls180.v:303.13-303.29" + attribute \src "ls180.v:306.13-306.29" wire width 64 \main_sram3_dat_r - attribute \src "ls180.v:305.13-305.29" + attribute \src "ls180.v:308.13-308.29" wire width 64 \main_sram3_dat_w - attribute \src "ls180.v:304.11-304.24" + attribute \src "ls180.v:307.11-307.24" wire width 8 \main_sram3_we - attribute \src "ls180.v:988.12-988.44" + attribute \src "ls180.v:991.12-991.44" wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:987.6-987.39" + attribute \src "ls180.v:990.6-990.39" wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:990.11-990.43" + attribute \src "ls180.v:993.11-993.43" wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:989.6-989.39" + attribute \src "ls180.v:992.6-992.39" wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:992.5-992.30" + attribute \src "ls180.v:995.5-995.30" wire \main_uart_eventmanager_re - attribute \src "ls180.v:984.12-984.43" + attribute \src "ls180.v:987.12-987.43" wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:983.6-983.38" + attribute \src "ls180.v:986.6-986.38" wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:986.11-986.42" + attribute \src "ls180.v:989.11-989.42" wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:985.6-985.38" + attribute \src "ls180.v:988.6-988.38" wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:991.11-991.41" + attribute \src "ls180.v:994.11-994.41" wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:972.6-972.19" + attribute \src "ls180.v:975.6-975.19" wire \main_uart_irq - attribute \src "ls180.v:958.12-958.46" + attribute \src "ls180.v:961.12-961.46" wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:948.12-948.46" + attribute \src "ls180.v:951.12-951.46" wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:941.5-941.21" + attribute \src "ls180.v:944.5-944.21" wire \main_uart_phy_re - attribute \src "ls180.v:959.6-959.22" + attribute \src "ls180.v:962.6-962.22" wire \main_uart_phy_rx - attribute \src "ls180.v:962.11-962.36" + attribute \src "ls180.v:965.11-965.36" wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:963.5-963.26" + attribute \src "ls180.v:966.5-966.26" wire \main_uart_phy_rx_busy - attribute \src "ls180.v:960.5-960.23" + attribute \src "ls180.v:963.5-963.23" wire \main_uart_phy_rx_r - attribute \src "ls180.v:961.11-961.31" + attribute \src "ls180.v:964.11-964.31" wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:944.6-944.30" + attribute \src "ls180.v:947.6-947.30" wire \main_uart_phy_sink_first - attribute \src "ls180.v:945.6-945.29" + attribute \src "ls180.v:948.6-948.29" wire \main_uart_phy_sink_last - attribute \src "ls180.v:946.12-946.43" + attribute \src "ls180.v:949.12-949.43" wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:943.5-943.29" + attribute \src "ls180.v:946.5-946.29" wire \main_uart_phy_sink_ready - attribute \src "ls180.v:942.6-942.30" + attribute \src "ls180.v:945.6-945.30" wire \main_uart_phy_sink_valid - attribute \src "ls180.v:954.5-954.31" + attribute \src "ls180.v:957.5-957.31" wire \main_uart_phy_source_first - attribute \src "ls180.v:955.5-955.30" + attribute \src "ls180.v:958.5-958.30" wire \main_uart_phy_source_last - attribute \src "ls180.v:956.11-956.44" + attribute \src "ls180.v:959.11-959.44" wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:953.6-953.32" + attribute \src "ls180.v:956.6-956.32" wire \main_uart_phy_source_ready - attribute \src "ls180.v:952.5-952.31" + attribute \src "ls180.v:955.5-955.31" wire \main_uart_phy_source_valid - attribute \src "ls180.v:940.12-940.33" + attribute \src "ls180.v:943.12-943.33" wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:950.11-950.36" + attribute \src "ls180.v:953.11-953.36" wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:951.5-951.26" + attribute \src "ls180.v:954.5-954.26" wire \main_uart_phy_tx_busy - attribute \src "ls180.v:949.11-949.31" + attribute \src "ls180.v:952.11-952.31" wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:957.5-957.32" + attribute \src "ls180.v:960.5-960.32" wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:947.5-947.32" + attribute \src "ls180.v:950.5-950.32" wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:1081.5-1081.20" + attribute \src "ls180.v:1084.5-1084.20" wire \main_uart_reset - attribute \src "ls180.v:981.5-981.23" + attribute \src "ls180.v:984.5-984.23" wire \main_uart_rx_clear - attribute \src "ls180.v:1065.11-1065.36" + attribute \src "ls180.v:1068.11-1068.36" wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:1070.6-1070.31" + attribute \src "ls180.v:1073.6-1073.31" wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:1076.6-1076.37" + attribute \src "ls180.v:1079.6-1079.37" wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:1077.6-1077.36" + attribute \src "ls180.v:1080.6-1080.36" wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:1075.12-1075.50" + attribute \src "ls180.v:1078.12-1078.50" wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1079.6-1079.38" + attribute \src "ls180.v:1082.6-1082.38" wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:1080.6-1080.37" + attribute \src "ls180.v:1083.6-1083.37" wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:1078.12-1078.51" + attribute \src "ls180.v:1081.12-1081.51" wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1062.11-1062.35" + attribute \src "ls180.v:1065.11-1065.35" wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:1074.12-1074.36" + attribute \src "ls180.v:1077.12-1077.36" wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:1064.11-1064.36" + attribute \src "ls180.v:1067.11-1067.36" wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:1071.12-1071.40" + attribute \src "ls180.v:1074.12-1074.40" wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:1072.12-1072.42" + attribute \src "ls180.v:1075.12-1075.42" wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:1073.6-1073.33" + attribute \src "ls180.v:1076.6-1076.33" wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:1054.6-1054.26" + attribute \src "ls180.v:1057.6-1057.26" wire \main_uart_rx_fifo_re - attribute \src "ls180.v:1055.5-1055.31" + attribute \src "ls180.v:1058.5-1058.31" wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:1063.5-1063.30" + attribute \src "ls180.v:1066.5-1066.30" wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:1046.6-1046.34" + attribute \src "ls180.v:1049.6-1049.34" wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:1047.6-1047.33" + attribute \src "ls180.v:1050.6-1050.33" wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:1048.12-1048.47" + attribute \src "ls180.v:1051.12-1051.47" wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:1045.6-1045.34" + attribute \src "ls180.v:1048.6-1048.34" wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:1044.6-1044.34" + attribute \src "ls180.v:1047.6-1047.34" wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:1051.6-1051.36" + attribute \src "ls180.v:1054.6-1054.36" wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:1052.6-1052.35" + attribute \src "ls180.v:1055.6-1055.35" wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:1053.12-1053.49" + attribute \src "ls180.v:1056.12-1056.49" wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:1050.6-1050.36" + attribute \src "ls180.v:1053.6-1053.36" wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:1049.6-1049.36" + attribute \src "ls180.v:1052.6-1052.36" wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:1060.12-1060.42" + attribute \src "ls180.v:1063.12-1063.42" wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:1061.12-1061.43" + attribute \src "ls180.v:1064.12-1064.43" wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:1058.6-1058.35" + attribute \src "ls180.v:1061.6-1061.35" wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:1059.6-1059.41" + attribute \src "ls180.v:1062.6-1062.41" wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:1056.6-1056.35" + attribute \src "ls180.v:1059.6-1059.35" wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:1057.6-1057.41" + attribute \src "ls180.v:1060.6-1060.41" wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:1066.11-1066.39" + attribute \src "ls180.v:1069.11-1069.39" wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:1067.12-1067.42" + attribute \src "ls180.v:1070.12-1070.42" wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:1069.12-1069.42" + attribute \src "ls180.v:1072.12-1072.42" wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:1068.6-1068.33" + attribute \src "ls180.v:1071.6-1071.33" wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:982.5-982.29" + attribute \src "ls180.v:985.5-985.29" wire \main_uart_rx_old_trigger - attribute \src "ls180.v:979.5-979.25" + attribute \src "ls180.v:982.5-982.25" wire \main_uart_rx_pending - attribute \src "ls180.v:978.6-978.25" + attribute \src "ls180.v:981.6-981.25" wire \main_uart_rx_status - attribute \src "ls180.v:980.6-980.26" + attribute \src "ls180.v:983.6-983.26" wire \main_uart_rx_trigger - attribute \src "ls180.v:970.6-970.30" + attribute \src "ls180.v:973.6-973.30" wire \main_uart_rxempty_status - attribute \src "ls180.v:971.6-971.26" + attribute \src "ls180.v:974.6-974.26" wire \main_uart_rxempty_we - attribute \src "ls180.v:995.6-995.29" + attribute \src "ls180.v:998.6-998.29" wire \main_uart_rxfull_status - attribute \src "ls180.v:996.6-996.25" + attribute \src "ls180.v:999.6-999.25" wire \main_uart_rxfull_we - attribute \src "ls180.v:965.12-965.28" + attribute \src "ls180.v:968.12-968.28" wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:964.6-964.23" + attribute \src "ls180.v:967.6-967.23" wire \main_uart_rxtx_re - attribute \src "ls180.v:967.12-967.28" + attribute \src "ls180.v:970.12-970.28" wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:966.6-966.23" + attribute \src "ls180.v:969.6-969.23" wire \main_uart_rxtx_we - attribute \src "ls180.v:976.5-976.23" + attribute \src "ls180.v:979.5-979.23" wire \main_uart_tx_clear - attribute \src "ls180.v:1028.11-1028.36" + attribute \src "ls180.v:1031.11-1031.36" wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:1033.6-1033.31" + attribute \src "ls180.v:1036.6-1036.31" wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:1039.6-1039.37" + attribute \src "ls180.v:1042.6-1042.37" wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:1040.6-1040.36" + attribute \src "ls180.v:1043.6-1043.36" wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:1038.12-1038.50" + attribute \src "ls180.v:1041.12-1041.50" wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1042.6-1042.38" + attribute \src "ls180.v:1045.6-1045.38" wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:1043.6-1043.37" + attribute \src "ls180.v:1046.6-1046.37" wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:1041.12-1041.51" + attribute \src "ls180.v:1044.12-1044.51" wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1025.11-1025.35" + attribute \src "ls180.v:1028.11-1028.35" wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:1037.12-1037.36" + attribute \src "ls180.v:1040.12-1040.36" wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:1027.11-1027.36" + attribute \src "ls180.v:1030.11-1030.36" wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:1034.12-1034.40" + attribute \src "ls180.v:1037.12-1037.40" wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:1035.12-1035.42" + attribute \src "ls180.v:1038.12-1038.42" wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:1036.6-1036.33" + attribute \src "ls180.v:1039.6-1039.33" wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:1017.6-1017.26" + attribute \src "ls180.v:1020.6-1020.26" wire \main_uart_tx_fifo_re - attribute \src "ls180.v:1018.5-1018.31" + attribute \src "ls180.v:1021.5-1021.31" wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:1026.5-1026.30" + attribute \src "ls180.v:1029.5-1029.30" wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:1009.5-1009.33" + attribute \src "ls180.v:1012.5-1012.33" wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:1010.5-1010.32" + attribute \src "ls180.v:1013.5-1013.32" wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:1011.12-1011.47" + attribute \src "ls180.v:1014.12-1014.47" wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:1008.6-1008.34" + attribute \src "ls180.v:1011.6-1011.34" wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:1007.6-1007.34" + attribute \src "ls180.v:1010.6-1010.34" wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:1014.6-1014.36" + attribute \src "ls180.v:1017.6-1017.36" wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:1015.6-1015.35" + attribute \src "ls180.v:1018.6-1018.35" wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:1016.12-1016.49" + attribute \src "ls180.v:1019.12-1019.49" wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:1013.6-1013.36" + attribute \src "ls180.v:1016.6-1016.36" wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:1012.6-1012.36" + attribute \src "ls180.v:1015.6-1015.36" wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:1023.12-1023.42" + attribute \src "ls180.v:1026.12-1026.42" wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:1024.12-1024.43" + attribute \src "ls180.v:1027.12-1027.43" wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:1021.6-1021.35" + attribute \src "ls180.v:1024.6-1024.35" wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:1022.6-1022.41" + attribute \src "ls180.v:1025.6-1025.41" wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:1019.6-1019.35" + attribute \src "ls180.v:1022.6-1022.35" wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:1020.6-1020.41" + attribute \src "ls180.v:1023.6-1023.41" wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:1029.11-1029.39" + attribute \src "ls180.v:1032.11-1032.39" wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:1030.12-1030.42" + attribute \src "ls180.v:1033.12-1033.42" wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:1032.12-1032.42" + attribute \src "ls180.v:1035.12-1035.42" wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:1031.6-1031.33" + attribute \src "ls180.v:1034.6-1034.33" wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:977.5-977.29" + attribute \src "ls180.v:980.5-980.29" wire \main_uart_tx_old_trigger - attribute \src "ls180.v:974.5-974.25" + attribute \src "ls180.v:977.5-977.25" wire \main_uart_tx_pending - attribute \src "ls180.v:973.6-973.25" + attribute \src "ls180.v:976.6-976.25" wire \main_uart_tx_status - attribute \src "ls180.v:975.6-975.26" + attribute \src "ls180.v:978.6-978.26" wire \main_uart_tx_trigger - attribute \src "ls180.v:993.6-993.30" + attribute \src "ls180.v:996.6-996.30" wire \main_uart_txempty_status - attribute \src "ls180.v:994.6-994.26" + attribute \src "ls180.v:997.6-997.26" wire \main_uart_txempty_we - attribute \src "ls180.v:968.6-968.29" + attribute \src "ls180.v:971.6-971.29" wire \main_uart_txfull_status - attribute \src "ls180.v:969.6-969.25" + attribute \src "ls180.v:972.6-972.25" wire \main_uart_txfull_we - attribute \src "ls180.v:999.6-999.31" + attribute \src "ls180.v:1002.6-1002.31" wire \main_uart_uart_sink_first - attribute \src "ls180.v:1000.6-1000.30" + attribute \src "ls180.v:1003.6-1003.30" wire \main_uart_uart_sink_last - attribute \src "ls180.v:1001.12-1001.44" + attribute \src "ls180.v:1004.12-1004.44" wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:998.6-998.31" + attribute \src "ls180.v:1001.6-1001.31" wire \main_uart_uart_sink_ready - attribute \src "ls180.v:997.6-997.31" + attribute \src "ls180.v:1000.6-1000.31" wire \main_uart_uart_sink_valid - attribute \src "ls180.v:1004.6-1004.33" + attribute \src "ls180.v:1007.6-1007.33" wire \main_uart_uart_source_first - attribute \src "ls180.v:1005.6-1005.32" + attribute \src "ls180.v:1008.6-1008.32" wire \main_uart_uart_source_last - attribute \src "ls180.v:1006.12-1006.46" + attribute \src "ls180.v:1009.12-1009.46" wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:1003.6-1003.33" + attribute \src "ls180.v:1006.6-1006.33" wire \main_uart_uart_source_ready - attribute \src "ls180.v:1002.6-1002.33" + attribute \src "ls180.v:1005.6-1005.33" wire \main_uart_uart_source_valid - attribute \src "ls180.v:906.5-906.22" + attribute \src "ls180.v:909.5-909.22" wire \main_wb_sdram_ack - attribute \src "ls180.v:900.12-900.29" + attribute \src "ls180.v:903.12-903.29" wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:904.5-904.22" + attribute \src "ls180.v:907.5-907.22" wire \main_wb_sdram_cyc - attribute \src "ls180.v:902.13-902.32" + attribute \src "ls180.v:905.13-905.32" wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:901.12-901.31" + attribute \src "ls180.v:904.12-904.31" wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:903.11-903.28" + attribute \src "ls180.v:906.11-906.28" wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:905.5-905.22" + attribute \src "ls180.v:908.5-908.22" wire \main_wb_sdram_stb - attribute \src "ls180.v:907.5-907.21" + attribute \src "ls180.v:910.5-910.21" wire \main_wb_sdram_we - attribute \src "ls180.v:936.5-936.24" + attribute \src "ls180.v:939.5-939.24" wire \main_wdata_consumed - attribute \src "ls180.v:10349.11-10349.17" + attribute \src "ls180.v:10352.11-10352.17" wire width 6 \memadr - attribute \src "ls180.v:10377.11-10377.19" + attribute \src "ls180.v:10380.11-10380.19" wire width 6 \memadr_1 - attribute \src "ls180.v:10405.11-10405.19" + attribute \src "ls180.v:10408.11-10408.19" wire width 6 \memadr_2 - attribute \src "ls180.v:10433.11-10433.19" + attribute \src "ls180.v:10436.11-10436.19" wire width 6 \memadr_3 - attribute \src "ls180.v:10461.11-10461.19" + attribute \src "ls180.v:10464.11-10464.19" wire width 6 \memadr_4 - attribute \src "ls180.v:10489.12-10489.18" + attribute \src "ls180.v:10492.12-10492.18" wire width 25 \memdat - attribute \src "ls180.v:10503.12-10503.20" + attribute \src "ls180.v:10506.12-10506.20" wire width 25 \memdat_1 - attribute \src "ls180.v:10517.12-10517.20" + attribute \src "ls180.v:10520.12-10520.20" wire width 25 \memdat_2 - attribute \src "ls180.v:10531.12-10531.20" + attribute \src "ls180.v:10534.12-10534.20" wire width 25 \memdat_3 - attribute \src "ls180.v:10545.11-10545.19" + attribute \src "ls180.v:10548.11-10548.19" wire width 10 \memdat_4 - attribute \src "ls180.v:10546.11-10546.19" + attribute \src "ls180.v:10549.11-10549.19" wire width 10 \memdat_5 - attribute \src "ls180.v:10562.11-10562.19" + attribute \src "ls180.v:10565.11-10565.19" wire width 10 \memdat_6 - attribute \src "ls180.v:10563.11-10563.19" + attribute \src "ls180.v:10566.11-10566.19" wire width 10 \memdat_7 - attribute \src "ls180.v:10579.11-10579.19" + attribute \src "ls180.v:10582.11-10582.19" wire width 10 \memdat_8 - attribute \src "ls180.v:10593.11-10593.19" + attribute \src "ls180.v:10596.11-10596.19" wire width 10 \memdat_9 attribute \src "ls180.v:52.20-52.22" wire width 24 input 48 \nc - attribute \src "ls180.v:338.6-338.13" + attribute \src "ls180.v:341.6-341.13" wire \por_clk - attribute \src "ls180.v:42.20-42.23" - wire width 2 output 38 \pwm - attribute \src "ls180.v:203.12-203.17" + attribute \src "ls180.v:29.19-29.22" + wire width 2 output 25 \pwm + attribute \src "ls180.v:193.12-193.17" wire width 2 \pwm_1 - attribute \src "ls180.v:11.14-11.24" - wire output 7 \sdcard_clk - attribute \src "ls180.v:12.13-12.25" - wire input 8 \sdcard_cmd_i - attribute \src "ls180.v:13.14-13.26" - wire output 9 \sdcard_cmd_o - attribute \src "ls180.v:14.14-14.27" - wire output 10 \sdcard_cmd_oe - attribute \src "ls180.v:15.19-15.32" - wire width 4 input 11 \sdcard_data_i - attribute \src "ls180.v:16.19-16.32" - wire width 4 output 12 \sdcard_data_o - attribute \src "ls180.v:17.13-17.27" - wire output 13 \sdcard_data_oe - attribute \src "ls180.v:21.21-21.28" - wire width 13 output 17 \sdram_a - attribute \src "ls180.v:30.20-30.28" - wire width 2 output 26 \sdram_ba - attribute \src "ls180.v:27.14-27.25" - wire output 23 \sdram_cas_n - attribute \src "ls180.v:29.14-29.23" - wire output 25 \sdram_cke - attribute \src "ls180.v:32.14-32.25" - wire output 28 \sdram_clock - attribute \src "ls180.v:193.6-193.19" + attribute \src "ls180.v:5.13-5.23" + wire output 1 \sdcard_clk + attribute \src "ls180.v:6.14-6.26" + wire output 2 \sdcard_cmd_i + attribute \src "ls180.v:7.13-7.25" + wire output 3 \sdcard_cmd_o + attribute \src "ls180.v:8.13-8.26" + wire output 4 \sdcard_cmd_oe + attribute \src "ls180.v:9.20-9.33" + wire width 4 output 5 \sdcard_data_i + attribute \src "ls180.v:10.19-10.32" + wire width 4 output 6 \sdcard_data_o + attribute \src "ls180.v:11.13-11.27" + wire output 7 \sdcard_data_oe + attribute \src "ls180.v:30.20-30.27" + wire width 13 output 26 \sdram_a + attribute \src "ls180.v:39.19-39.27" + wire width 2 output 35 \sdram_ba + attribute \src "ls180.v:36.13-36.24" + wire output 32 \sdram_cas_n + attribute \src "ls180.v:38.13-38.22" + wire output 34 \sdram_cke + attribute \src "ls180.v:41.13-41.24" + wire output 37 \sdram_clock + attribute \src "ls180.v:205.6-205.19" wire \sdram_clock_1 - attribute \src "ls180.v:28.14-28.24" - wire output 24 \sdram_cs_n - attribute \src "ls180.v:31.20-31.28" - wire width 2 output 27 \sdram_dm - attribute \src "ls180.v:22.20-22.30" - wire width 16 input 18 \sdram_dq_i - attribute \src "ls180.v:23.21-23.31" - wire width 16 output 19 \sdram_dq_o - attribute \src "ls180.v:24.14-24.25" - wire output 20 \sdram_dq_oe - attribute \src "ls180.v:26.14-26.25" - wire output 22 \sdram_ras_n - attribute \src "ls180.v:25.14-25.24" - wire output 21 \sdram_we_n - attribute \src "ls180.v:2760.6-2760.15" + attribute \src "ls180.v:37.13-37.23" + wire output 33 \sdram_cs_n + attribute \src "ls180.v:40.19-40.27" + wire width 2 output 36 \sdram_dm + attribute \src "ls180.v:31.21-31.31" + wire width 16 output 27 \sdram_dq_i + attribute \src "ls180.v:32.20-32.30" + wire width 16 output 28 \sdram_dq_o + attribute \src "ls180.v:33.13-33.24" + wire output 29 \sdram_dq_oe + attribute \src "ls180.v:35.13-35.24" + wire output 31 \sdram_ras_n + attribute \src "ls180.v:34.13-34.23" + wire output 30 \sdram_we_n + attribute \src "ls180.v:2763.6-2763.15" wire \sdrio_clk - attribute \src "ls180.v:2761.6-2761.17" + attribute \src "ls180.v:2764.6-2764.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2770.6-2770.18" + attribute \src "ls180.v:2773.6-2773.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2771.6-2771.18" + attribute \src "ls180.v:2774.6-2774.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2772.6-2772.18" + attribute \src "ls180.v:2775.6-2775.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2773.6-2773.18" + attribute \src "ls180.v:2776.6-2776.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2774.6-2774.18" + attribute \src "ls180.v:2777.6-2777.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2775.6-2775.18" + attribute \src "ls180.v:2778.6-2778.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2776.6-2776.18" + attribute \src "ls180.v:2779.6-2779.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2777.6-2777.18" + attribute \src "ls180.v:2780.6-2780.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2778.6-2778.18" + attribute \src "ls180.v:2781.6-2781.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2779.6-2779.18" + attribute \src "ls180.v:2782.6-2782.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2762.6-2762.17" + attribute \src "ls180.v:2765.6-2765.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2780.6-2780.18" + attribute \src "ls180.v:2783.6-2783.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2781.6-2781.18" + attribute \src "ls180.v:2784.6-2784.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2782.6-2782.18" + attribute \src "ls180.v:2785.6-2785.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2783.6-2783.18" + attribute \src "ls180.v:2786.6-2786.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2784.6-2784.18" + attribute \src "ls180.v:2787.6-2787.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2785.6-2785.18" + attribute \src "ls180.v:2788.6-2788.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2786.6-2786.18" + attribute \src "ls180.v:2789.6-2789.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2787.6-2787.18" + attribute \src "ls180.v:2790.6-2790.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2788.6-2788.18" + attribute \src "ls180.v:2791.6-2791.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2789.6-2789.18" + attribute \src "ls180.v:2792.6-2792.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2763.6-2763.17" + attribute \src "ls180.v:2766.6-2766.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2790.6-2790.18" + attribute \src "ls180.v:2793.6-2793.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2791.6-2791.18" + attribute \src "ls180.v:2794.6-2794.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2792.6-2792.18" + attribute \src "ls180.v:2795.6-2795.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2793.6-2793.18" + attribute \src "ls180.v:2796.6-2796.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2794.6-2794.18" + attribute \src "ls180.v:2797.6-2797.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2795.6-2795.18" + attribute \src "ls180.v:2798.6-2798.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2796.6-2796.18" + attribute \src "ls180.v:2799.6-2799.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2797.6-2797.18" + attribute \src "ls180.v:2800.6-2800.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2798.6-2798.18" + attribute \src "ls180.v:2801.6-2801.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2799.6-2799.18" + attribute \src "ls180.v:2802.6-2802.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2764.6-2764.17" + attribute \src "ls180.v:2767.6-2767.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2800.6-2800.18" + attribute \src "ls180.v:2803.6-2803.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2801.6-2801.18" + attribute \src "ls180.v:2804.6-2804.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2802.6-2802.18" + attribute \src "ls180.v:2805.6-2805.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2803.6-2803.18" + attribute \src "ls180.v:2806.6-2806.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2804.6-2804.18" + attribute \src "ls180.v:2807.6-2807.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2805.6-2805.18" + attribute \src "ls180.v:2808.6-2808.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2806.6-2806.18" + attribute \src "ls180.v:2809.6-2809.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2807.6-2807.18" + attribute \src "ls180.v:2810.6-2810.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2808.6-2808.18" + attribute \src "ls180.v:2811.6-2811.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2809.6-2809.18" + attribute \src "ls180.v:2812.6-2812.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2765.6-2765.17" + attribute \src "ls180.v:2768.6-2768.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2810.6-2810.18" + attribute \src "ls180.v:2813.6-2813.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2811.6-2811.18" + attribute \src "ls180.v:2814.6-2814.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2812.6-2812.18" + attribute \src "ls180.v:2815.6-2815.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2813.6-2813.18" + attribute \src "ls180.v:2816.6-2816.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2814.6-2814.18" + attribute \src "ls180.v:2817.6-2817.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2815.6-2815.18" + attribute \src "ls180.v:2818.6-2818.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2850.6-2850.18" + attribute \src "ls180.v:2853.6-2853.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2851.6-2851.18" + attribute \src "ls180.v:2854.6-2854.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2852.6-2852.18" + attribute \src "ls180.v:2855.6-2855.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2853.6-2853.18" + attribute \src "ls180.v:2856.6-2856.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2766.6-2766.17" + attribute \src "ls180.v:2769.6-2769.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2854.6-2854.18" + attribute \src "ls180.v:2857.6-2857.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2855.6-2855.18" + attribute \src "ls180.v:2858.6-2858.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2856.6-2856.18" + attribute \src "ls180.v:2859.6-2859.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2857.6-2857.18" + attribute \src "ls180.v:2860.6-2860.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2858.6-2858.18" + attribute \src "ls180.v:2861.6-2861.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2859.6-2859.18" + attribute \src "ls180.v:2862.6-2862.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2860.6-2860.18" + attribute \src "ls180.v:2863.6-2863.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2861.6-2861.18" + attribute \src "ls180.v:2864.6-2864.18" wire \sdrio_clk_67 - attribute \src "ls180.v:2862.6-2862.18" + attribute \src "ls180.v:2865.6-2865.18" wire \sdrio_clk_68 - attribute \src "ls180.v:2767.6-2767.17" + attribute \src "ls180.v:2770.6-2770.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2768.6-2768.17" + attribute \src "ls180.v:2771.6-2771.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2769.6-2769.17" + attribute \src "ls180.v:2772.6-2772.17" wire \sdrio_clk_9 - attribute \src "ls180.v:33.14-33.27" - wire output 29 \spimaster_clk - attribute \src "ls180.v:35.14-35.28" - wire output 31 \spimaster_cs_n - attribute \src "ls180.v:36.13-36.27" - wire input 32 \spimaster_miso - attribute \src "ls180.v:34.14-34.28" - wire output 30 \spimaster_mosi - attribute \src "ls180.v:38.14-38.27" - wire output 34 \spisdcard_clk - attribute \src "ls180.v:40.14-40.28" - wire output 36 \spisdcard_cs_n - attribute \src "ls180.v:41.13-41.27" - wire input 37 \spisdcard_miso - attribute \src "ls180.v:39.14-39.28" - wire output 35 \spisdcard_mosi + attribute \src "ls180.v:21.13-21.26" + wire output 17 \spimaster_clk + attribute \src "ls180.v:23.13-23.27" + wire output 19 \spimaster_cs_n + attribute \src "ls180.v:24.13-24.27" + wire input 20 \spimaster_miso + attribute \src "ls180.v:22.13-22.27" + wire output 18 \spimaster_mosi + attribute \src "ls180.v:25.13-25.26" + wire output 21 \spisdcard_clk + attribute \src "ls180.v:27.13-27.27" + wire output 23 \spisdcard_cs_n + attribute \src "ls180.v:28.13-28.27" + wire input 24 \spisdcard_miso + attribute \src "ls180.v:26.13-26.27" + wire output 22 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk - attribute \src "ls180.v:336.6-336.15" + attribute \src "ls180.v:339.6-339.15" wire \sys_clk_1 attribute \src "ls180.v:45.19-45.31" wire width 2 input 41 \sys_clksel_i @@ -249517,40 +252046,40 @@ module \ls180 wire output 43 \sys_pll_lck_o attribute \src "ls180.v:44.13-44.20" wire input 40 \sys_rst - attribute \src "ls180.v:337.6-337.15" + attribute \src "ls180.v:340.6-340.15" wire \sys_rst_1 - attribute \src "ls180.v:6.13-6.20" - wire input 2 \uart_rx - attribute \src "ls180.v:5.13-5.20" - wire output 1 \uart_tx - attribute \src "ls180.v:10348.12-10348.15" + attribute \src "ls180.v:13.13-13.20" + wire input 9 \uart_rx + attribute \src "ls180.v:12.13-12.20" + wire output 8 \uart_tx + attribute \src "ls180.v:10351.12-10351.15" memory width 64 size 64 \mem - attribute \src "ls180.v:10376.12-10376.17" + attribute \src "ls180.v:10379.12-10379.17" memory width 64 size 64 \mem_1 - attribute \src "ls180.v:10404.12-10404.17" + attribute \src "ls180.v:10407.12-10407.17" memory width 64 size 64 \mem_2 - attribute \src "ls180.v:10432.12-10432.17" + attribute \src "ls180.v:10435.12-10435.17" memory width 64 size 64 \mem_3 - attribute \src "ls180.v:10460.12-10460.17" + attribute \src "ls180.v:10463.12-10463.17" memory width 64 size 64 \mem_4 - attribute \src "ls180.v:10488.12-10488.19" + attribute \src "ls180.v:10491.12-10491.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10502.12-10502.21" + attribute \src "ls180.v:10505.12-10505.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10516.12-10516.21" + attribute \src "ls180.v:10519.12-10519.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10530.12-10530.21" + attribute \src "ls180.v:10533.12-10533.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10544.11-10544.20" + attribute \src "ls180.v:10547.11-10547.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10561.11-10561.20" + attribute \src "ls180.v:10564.11-10564.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10578.11-10578.20" + attribute \src "ls180.v:10581.11-10581.20" memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10592.11-10592.20" + attribute \src "ls180.v:10595.11-10595.20" memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2932.56-2932.86" - cell $add $add$ls180.v:2932$58 + attribute \src "ls180.v:2935.56-2935.86" + cell $add $add$ls180.v:2935$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249558,10 +252087,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2932$58_Y + connect \Y $add$ls180.v:2935$58_Y end - attribute \src "ls180.v:2992.56-2992.86" - cell $add $add$ls180.v:2992$69 + attribute \src "ls180.v:2995.56-2995.86" + cell $add $add$ls180.v:2995$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249569,10 +252098,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2992$69_Y + connect \Y $add$ls180.v:2995$69_Y end - attribute \src "ls180.v:3052.59-3052.92" - cell $add $add$ls180.v:3052$80 + attribute \src "ls180.v:3055.59-3055.92" + cell $add $add$ls180.v:3055$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249580,10 +252109,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $add$ls180.v:3052$80_Y + connect \Y $add$ls180.v:3055$80_Y end - attribute \src "ls180.v:4245.54-4245.83" - cell $add $add$ls180.v:4245$685 + attribute \src "ls180.v:4248.54-4248.83" + cell $add $add$ls180.v:4248$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249591,10 +252120,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4245$685_Y + connect \Y $add$ls180.v:4248$685_Y end - attribute \src "ls180.v:4345.36-4345.89" - cell $add $add$ls180.v:4345$731 + attribute \src "ls180.v:4348.36-4348.89" + cell $add $add$ls180.v:4348$731 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -249602,10 +252131,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4345$731_Y + connect \Y $add$ls180.v:4348$731_Y end - attribute \src "ls180.v:4375.36-4375.89" - cell $add $add$ls180.v:4375$742 + attribute \src "ls180.v:4378.36-4378.89" + cell $add $add$ls180.v:4378$742 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -249613,10 +252142,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4375$742_Y + connect \Y $add$ls180.v:4378$742_Y end - attribute \src "ls180.v:4441.54-4441.83" - cell $add $add$ls180.v:4441$757 + attribute \src "ls180.v:4444.54-4444.83" + cell $add $add$ls180.v:4444$757 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249624,10 +252153,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster27_count connect \B 1'1 - connect \Y $add$ls180.v:4441$757_Y + connect \Y $add$ls180.v:4444$757_Y end - attribute \src "ls180.v:4500.52-4500.79" - cell $add $add$ls180.v:4500$765 + attribute \src "ls180.v:4503.52-4503.79" + cell $add $add$ls180.v:4503$765 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249635,10 +252164,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_count connect \B 1'1 - connect \Y $add$ls180.v:4500$765_Y + connect \Y $add$ls180.v:4503$765_Y end - attribute \src "ls180.v:4604.58-4604.86" - cell $add $add$ls180.v:4604$793 + attribute \src "ls180.v:4607.58-4607.86" + cell $add $add$ls180.v:4607$793 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249646,10 +252175,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_init_count connect \B 1'1 - connect \Y $add$ls180.v:4604$793_Y + connect \Y $add$ls180.v:4607$793_Y end - attribute \src "ls180.v:4661.58-4661.86" - cell $add $add$ls180.v:4661$796 + attribute \src "ls180.v:4664.58-4664.86" + cell $add $add$ls180.v:4664$796 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249657,10 +252186,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4661$796_Y + connect \Y $add$ls180.v:4664$796_Y end - attribute \src "ls180.v:4678.58-4678.86" - cell $add $add$ls180.v:4678$798 + attribute \src "ls180.v:4681.58-4681.86" + cell $add $add$ls180.v:4681$798 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249668,10 +252197,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4678$798_Y + connect \Y $add$ls180.v:4681$798_Y end - attribute \src "ls180.v:4771.59-4771.87" - cell $add $add$ls180.v:4771$815 + attribute \src "ls180.v:4774.59-4774.87" + cell $add $add$ls180.v:4774$815 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249679,10 +252208,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4771$815_Y + connect \Y $add$ls180.v:4774$815_Y end - attribute \src "ls180.v:4796.59-4796.87" - cell $add $add$ls180.v:4796$818 + attribute \src "ls180.v:4799.59-4799.87" + cell $add $add$ls180.v:4799$818 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249690,10 +252219,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4796$818_Y + connect \Y $add$ls180.v:4799$818_Y end - attribute \src "ls180.v:4918.53-4918.82" - cell $add $add$ls180.v:4918$835 + attribute \src "ls180.v:4921.53-4921.82" + cell $add $add$ls180.v:4921$835 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249701,10 +252230,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $add$ls180.v:4918$835_Y + connect \Y $add$ls180.v:4921$835_Y end - attribute \src "ls180.v:5029.65-5029.114" - cell $add $add$ls180.v:5029$849 + attribute \src "ls180.v:5032.65-5032.114" + cell $add $add$ls180.v:5032$849 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -249712,10 +252241,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_sink_payload_block_length connect \B 4'1000 - connect \Y $add$ls180.v:5029$849_Y + connect \Y $add$ls180.v:5032$849_Y end - attribute \src "ls180.v:5034.62-5034.91" - cell $add $add$ls180.v:5034$852 + attribute \src "ls180.v:5037.62-5037.91" + cell $add $add$ls180.v:5037$852 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -249723,10 +252252,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:5034$852_Y + connect \Y $add$ls180.v:5037$852_Y end - attribute \src "ls180.v:5060.61-5060.90" - cell $add $add$ls180.v:5060$855 + attribute \src "ls180.v:5063.61-5063.90" + cell $add $add$ls180.v:5063$855 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -249734,10 +252263,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:5060$855_Y + connect \Y $add$ls180.v:5063$855_Y end - attribute \src "ls180.v:5264.80-5264.117" - cell $add $add$ls180.v:5264$1040 + attribute \src "ls180.v:5267.80-5267.117" + cell $add $add$ls180.v:5267$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249745,10 +252274,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_crc16_inserter_cnt connect \B 1'1 - connect \Y $add$ls180.v:5264$1040_Y + connect \Y $add$ls180.v:5267$1040_Y end - attribute \src "ls180.v:5458.54-5458.82" - cell $add $add$ls180.v:5458$1115 + attribute \src "ls180.v:5461.54-5461.82" + cell $add $add$ls180.v:5461$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249756,10 +252285,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_cmd_count connect \B 1'1 - connect \Y $add$ls180.v:5458$1115_Y + connect \Y $add$ls180.v:5461$1115_Y end - attribute \src "ls180.v:5510.55-5510.84" - cell $add $add$ls180.v:5510$1125 + attribute \src "ls180.v:5513.55-5513.84" + cell $add $add$ls180.v:5513$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249767,10 +252296,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5510$1125_Y + connect \Y $add$ls180.v:5513$1125_Y end - attribute \src "ls180.v:5536.57-5536.86" - cell $add $add$ls180.v:5536$1133 + attribute \src "ls180.v:5539.57-5539.86" + cell $add $add$ls180.v:5539$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249778,10 +252307,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5536$1133_Y + connect \Y $add$ls180.v:5539$1133_Y end - attribute \src "ls180.v:5657.51-5657.134" - cell $add $add$ls180.v:5657$1149 + attribute \src "ls180.v:5660.51-5660.134" + cell $add $add$ls180.v:5660$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249789,10 +252318,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_base connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5657$1149_Y + connect \Y $add$ls180.v:5660$1149_Y end - attribute \src "ls180.v:5660.77-5660.125" - cell $add $add$ls180.v:5660$1151 + attribute \src "ls180.v:5663.77-5663.125" + cell $add $add$ls180.v:5663$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249800,10 +252329,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_offset connect \B 1'1 - connect \Y $add$ls180.v:5660$1151_Y + connect \Y $add$ls180.v:5663$1151_Y end - attribute \src "ls180.v:5753.50-5753.105" - cell $add $add$ls180.v:5753$1160 + attribute \src "ls180.v:5756.50-5756.105" + cell $add $add$ls180.v:5756$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249811,10 +252340,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_base connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5753$1160_Y + connect \Y $add$ls180.v:5756$1160_Y end - attribute \src "ls180.v:5755.77-5755.111" - cell $add $add$ls180.v:5755$1161 + attribute \src "ls180.v:5758.77-5758.111" + cell $add $add$ls180.v:5758$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249822,10 +252351,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_offset connect \B 1'1 - connect \Y $add$ls180.v:5755$1161_Y + connect \Y $add$ls180.v:5758$1161_Y end - attribute \src "ls180.v:7762.36-7762.70" - cell $add $add$ls180.v:7762$2602 + attribute \src "ls180.v:7765.36-7765.70" + cell $add $add$ls180.v:7765$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249833,10 +252362,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7762$2602_Y + connect \Y $add$ls180.v:7765$2602_Y end - attribute \src "ls180.v:7863.37-7863.72" - cell $add $add$ls180.v:7863$2635 + attribute \src "ls180.v:7866.37-7866.72" + cell $add $add$ls180.v:7866$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249844,10 +252373,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7863$2635_Y + connect \Y $add$ls180.v:7866$2635_Y end - attribute \src "ls180.v:7880.60-7880.119" - cell $add $add$ls180.v:7880$2639 + attribute \src "ls180.v:7883.60-7883.119" + cell $add $add$ls180.v:7883$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249855,10 +252384,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7880$2639_Y + connect \Y $add$ls180.v:7883$2639_Y end - attribute \src "ls180.v:7883.60-7883.119" - cell $add $add$ls180.v:7883$2640 + attribute \src "ls180.v:7886.60-7886.119" + cell $add $add$ls180.v:7886$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249866,10 +252395,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7883$2640_Y + connect \Y $add$ls180.v:7886$2640_Y end - attribute \src "ls180.v:7887.59-7887.116" - cell $add $add$ls180.v:7887$2645 + attribute \src "ls180.v:7890.59-7890.116" + cell $add $add$ls180.v:7890$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249877,10 +252406,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7887$2645_Y + connect \Y $add$ls180.v:7890$2645_Y end - attribute \src "ls180.v:7926.60-7926.119" - cell $add $add$ls180.v:7926$2655 + attribute \src "ls180.v:7929.60-7929.119" + cell $add $add$ls180.v:7929$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249888,10 +252417,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7926$2655_Y + connect \Y $add$ls180.v:7929$2655_Y end - attribute \src "ls180.v:7929.60-7929.119" - cell $add $add$ls180.v:7929$2656 + attribute \src "ls180.v:7932.60-7932.119" + cell $add $add$ls180.v:7932$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249899,10 +252428,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7929$2656_Y + connect \Y $add$ls180.v:7932$2656_Y end - attribute \src "ls180.v:7933.59-7933.116" - cell $add $add$ls180.v:7933$2661 + attribute \src "ls180.v:7936.59-7936.116" + cell $add $add$ls180.v:7936$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249910,10 +252439,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7933$2661_Y + connect \Y $add$ls180.v:7936$2661_Y end - attribute \src "ls180.v:7972.60-7972.119" - cell $add $add$ls180.v:7972$2671 + attribute \src "ls180.v:7975.60-7975.119" + cell $add $add$ls180.v:7975$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249921,10 +252450,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7972$2671_Y + connect \Y $add$ls180.v:7975$2671_Y end - attribute \src "ls180.v:7975.60-7975.119" - cell $add $add$ls180.v:7975$2672 + attribute \src "ls180.v:7978.60-7978.119" + cell $add $add$ls180.v:7978$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249932,10 +252461,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7975$2672_Y + connect \Y $add$ls180.v:7978$2672_Y end - attribute \src "ls180.v:7979.59-7979.116" - cell $add $add$ls180.v:7979$2677 + attribute \src "ls180.v:7982.59-7982.116" + cell $add $add$ls180.v:7982$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249943,10 +252472,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7979$2677_Y + connect \Y $add$ls180.v:7982$2677_Y end - attribute \src "ls180.v:8018.60-8018.119" - cell $add $add$ls180.v:8018$2687 + attribute \src "ls180.v:8021.60-8021.119" + cell $add $add$ls180.v:8021$2687 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249954,10 +252483,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:8018$2687_Y + connect \Y $add$ls180.v:8021$2687_Y end - attribute \src "ls180.v:8021.60-8021.119" - cell $add $add$ls180.v:8021$2688 + attribute \src "ls180.v:8024.60-8024.119" + cell $add $add$ls180.v:8024$2688 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249965,10 +252494,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:8021$2688_Y + connect \Y $add$ls180.v:8024$2688_Y end - attribute \src "ls180.v:8025.59-8025.116" - cell $add $add$ls180.v:8025$2693 + attribute \src "ls180.v:8028.59-8028.116" + cell $add $add$ls180.v:8028$2693 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249976,10 +252505,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:8025$2693_Y + connect \Y $add$ls180.v:8028$2693_Y end - attribute \src "ls180.v:8255.34-8255.66" - cell $add $add$ls180.v:8255$2747 + attribute \src "ls180.v:8258.34-8258.66" + cell $add $add$ls180.v:8258$2747 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249987,10 +252516,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8255$2747_Y + connect \Y $add$ls180.v:8258$2747_Y end - attribute \src "ls180.v:8271.73-8271.131" - cell $add $add$ls180.v:8271$2750 + attribute \src "ls180.v:8274.73-8274.131" + cell $add $add$ls180.v:8274$2750 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249998,10 +252527,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_tx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8271$2750_Y + connect \Y $add$ls180.v:8274$2750_Y end - attribute \src "ls180.v:8284.34-8284.66" - cell $add $add$ls180.v:8284$2754 + attribute \src "ls180.v:8287.34-8287.66" + cell $add $add$ls180.v:8287$2754 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250009,10 +252538,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8284$2754_Y + connect \Y $add$ls180.v:8287$2754_Y end - attribute \src "ls180.v:8303.73-8303.131" - cell $add $add$ls180.v:8303$2757 + attribute \src "ls180.v:8306.73-8306.131" + cell $add $add$ls180.v:8306$2757 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -250020,10 +252549,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_rx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8303$2757_Y + connect \Y $add$ls180.v:8306$2757_Y end - attribute \src "ls180.v:8329.33-8329.65" - cell $add $add$ls180.v:8329$2765 + attribute \src "ls180.v:8332.33-8332.65" + cell $add $add$ls180.v:8332$2765 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250031,10 +252560,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8329$2765_Y + connect \Y $add$ls180.v:8332$2765_Y end - attribute \src "ls180.v:8332.33-8332.65" - cell $add $add$ls180.v:8332$2766 + attribute \src "ls180.v:8335.33-8335.65" + cell $add $add$ls180.v:8335$2766 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250042,10 +252571,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8332$2766_Y + connect \Y $add$ls180.v:8335$2766_Y end - attribute \src "ls180.v:8336.33-8336.64" - cell $add $add$ls180.v:8336$2771 + attribute \src "ls180.v:8339.33-8339.64" + cell $add $add$ls180.v:8339$2771 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -250053,10 +252582,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8336$2771_Y + connect \Y $add$ls180.v:8339$2771_Y end - attribute \src "ls180.v:8351.33-8351.65" - cell $add $add$ls180.v:8351$2776 + attribute \src "ls180.v:8354.33-8354.65" + cell $add $add$ls180.v:8354$2776 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250064,10 +252593,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8351$2776_Y + connect \Y $add$ls180.v:8354$2776_Y end - attribute \src "ls180.v:8354.33-8354.65" - cell $add $add$ls180.v:8354$2777 + attribute \src "ls180.v:8357.33-8357.65" + cell $add $add$ls180.v:8357$2777 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250075,10 +252604,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8354$2777_Y + connect \Y $add$ls180.v:8357$2777_Y end - attribute \src "ls180.v:8358.33-8358.64" - cell $add $add$ls180.v:8358$2782 + attribute \src "ls180.v:8361.33-8361.64" + cell $add $add$ls180.v:8361$2782 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -250086,10 +252615,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8358$2782_Y + connect \Y $add$ls180.v:8361$2782_Y end - attribute \src "ls180.v:8379.35-8379.70" - cell $add $add$ls180.v:8379$2784 + attribute \src "ls180.v:8382.35-8382.70" + cell $add $add$ls180.v:8382$2784 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -250097,10 +252626,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster30_clk_divider connect \B 1'1 - connect \Y $add$ls180.v:8379$2784_Y + connect \Y $add$ls180.v:8382$2784_Y end - attribute \src "ls180.v:8414.34-8414.68" - cell $add $add$ls180.v:8414$2789 + attribute \src "ls180.v:8417.34-8417.68" + cell $add $add$ls180.v:8417$2789 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -250108,10 +252637,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8414$2789_Y + connect \Y $add$ls180.v:8417$2789_Y end - attribute \src "ls180.v:8450.25-8450.49" - cell $add $add$ls180.v:8450$2794 + attribute \src "ls180.v:8453.25-8453.49" + cell $add $add$ls180.v:8453$2794 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -250119,10 +252648,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8450$2794_Y + connect \Y $add$ls180.v:8453$2794_Y end - attribute \src "ls180.v:8464.25-8464.49" - cell $add $add$ls180.v:8464$2798 + attribute \src "ls180.v:8467.25-8467.49" + cell $add $add$ls180.v:8467$2798 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -250130,10 +252659,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8464$2798_Y + connect \Y $add$ls180.v:8467$2798_Y end - attribute \src "ls180.v:8478.31-8478.61" - cell $add $add$ls180.v:8478$2803 + attribute \src "ls180.v:8481.31-8481.61" + cell $add $add$ls180.v:8481$2803 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -250141,10 +252670,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8478$2803_Y + connect \Y $add$ls180.v:8481$2803_Y end - attribute \src "ls180.v:8501.45-8501.88" - cell $add $add$ls180.v:8501$2807 + attribute \src "ls180.v:8504.45-8504.88" + cell $add $add$ls180.v:8504$2807 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250152,10 +252681,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8501$2807_Y + connect \Y $add$ls180.v:8504$2807_Y end - attribute \src "ls180.v:8547.71-8547.114" - cell $add $add$ls180.v:8547$2813 + attribute \src "ls180.v:8550.71-8550.114" + cell $add $add$ls180.v:8550$2813 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250163,10 +252692,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8547$2813_Y + connect \Y $add$ls180.v:8550$2813_Y end - attribute \src "ls180.v:8582.46-8582.90" - cell $add $add$ls180.v:8582$2819 + attribute \src "ls180.v:8585.46-8585.90" + cell $add $add$ls180.v:8585$2819 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250174,10 +252703,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8582$2819_Y + connect \Y $add$ls180.v:8585$2819_Y end - attribute \src "ls180.v:8628.72-8628.116" - cell $add $add$ls180.v:8628$2825 + attribute \src "ls180.v:8631.72-8631.116" + cell $add $add$ls180.v:8631$2825 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250185,10 +252714,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8628$2825_Y + connect \Y $add$ls180.v:8631$2825_Y end - attribute \src "ls180.v:8661.47-8661.92" - cell $add $add$ls180.v:8661$2831 + attribute \src "ls180.v:8664.47-8664.92" + cell $add $add$ls180.v:8664$2831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250196,10 +252725,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8661$2831_Y + connect \Y $add$ls180.v:8664$2831_Y end - attribute \src "ls180.v:8689.73-8689.118" - cell $add $add$ls180.v:8689$2837 + attribute \src "ls180.v:8692.73-8692.118" + cell $add $add$ls180.v:8692$2837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250207,10 +252736,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8689$2837_Y + connect \Y $add$ls180.v:8692$2837_Y end - attribute \src "ls180.v:8801.39-8801.75" - cell $add $add$ls180.v:8801$2850 + attribute \src "ls180.v:8804.39-8804.75" + cell $add $add$ls180.v:8804$2850 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250218,10 +252747,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8801$2850_Y + connect \Y $add$ls180.v:8804$2850_Y end - attribute \src "ls180.v:8862.37-8862.73" - cell $add $add$ls180.v:8862$2854 + attribute \src "ls180.v:8865.37-8865.73" + cell $add $add$ls180.v:8865$2854 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -250229,10 +252758,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8862$2854_Y + connect \Y $add$ls180.v:8865$2854_Y end - attribute \src "ls180.v:8865.37-8865.73" - cell $add $add$ls180.v:8865$2855 + attribute \src "ls180.v:8868.37-8868.73" + cell $add $add$ls180.v:8868$2855 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -250240,10 +252769,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8865$2855_Y + connect \Y $add$ls180.v:8868$2855_Y end - attribute \src "ls180.v:8869.36-8869.70" - cell $add $add$ls180.v:8869$2860 + attribute \src "ls180.v:8872.36-8872.70" + cell $add $add$ls180.v:8872$2860 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250251,10 +252780,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8869$2860_Y + connect \Y $add$ls180.v:8872$2860_Y end - attribute \src "ls180.v:8884.41-8884.80" - cell $add $add$ls180.v:8884$2864 + attribute \src "ls180.v:8887.41-8887.80" + cell $add $add$ls180.v:8887$2864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250262,10 +252791,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8884$2864_Y + connect \Y $add$ls180.v:8887$2864_Y end - attribute \src "ls180.v:8930.67-8930.106" - cell $add $add$ls180.v:8930$2870 + attribute \src "ls180.v:8933.67-8933.106" + cell $add $add$ls180.v:8933$2870 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250273,10 +252802,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8930$2870_Y + connect \Y $add$ls180.v:8933$2870_Y end - attribute \src "ls180.v:8956.39-8956.76" - cell $add $add$ls180.v:8956$2872 + attribute \src "ls180.v:8959.39-8959.76" + cell $add $add$ls180.v:8959$2872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250284,10 +252813,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8956$2872_Y + connect \Y $add$ls180.v:8959$2872_Y end - attribute \src "ls180.v:8960.37-8960.73" - cell $add $add$ls180.v:8960$2876 + attribute \src "ls180.v:8963.37-8963.73" + cell $add $add$ls180.v:8963$2876 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -250295,10 +252824,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8960$2876_Y + connect \Y $add$ls180.v:8963$2876_Y end - attribute \src "ls180.v:8963.37-8963.73" - cell $add $add$ls180.v:8963$2877 + attribute \src "ls180.v:8966.37-8966.73" + cell $add $add$ls180.v:8966$2877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -250306,10 +252835,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8963$2877_Y + connect \Y $add$ls180.v:8966$2877_Y end - attribute \src "ls180.v:8967.36-8967.70" - cell $add $add$ls180.v:8967$2882 + attribute \src "ls180.v:8970.36-8970.70" + cell $add $add$ls180.v:8970$2882 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -250317,10 +252846,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8967$2882_Y + connect \Y $add$ls180.v:8970$2882_Y end - attribute \src "ls180.v:2926.9-2926.90" - cell $and $and$ls180.v:2926$53 + attribute \src "ls180.v:2929.9-2929.90" + cell $and $and$ls180.v:2929$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250328,10 +252857,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_converted_interface_stb connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2926$53_Y + connect \Y $and$ls180.v:2929$53_Y end - attribute \src "ls180.v:2944.9-2944.90" - cell $and $and$ls180.v:2944$60 + attribute \src "ls180.v:2947.9-2947.90" + cell $and $and$ls180.v:2947$60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250339,10 +252868,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_converted_interface_stb connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2944$60_Y + connect \Y $and$ls180.v:2947$60_Y end - attribute \src "ls180.v:2986.9-2986.90" - cell $and $and$ls180.v:2986$64 + attribute \src "ls180.v:2989.9-2989.90" + cell $and $and$ls180.v:2989$64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250350,10 +252879,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_converted_interface_stb connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:2986$64_Y + connect \Y $and$ls180.v:2989$64_Y end - attribute \src "ls180.v:3004.9-3004.90" - cell $and $and$ls180.v:3004$71 + attribute \src "ls180.v:3007.9-3007.90" + cell $and $and$ls180.v:3007$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250361,10 +252890,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_converted_interface_stb connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:3004$71_Y + connect \Y $and$ls180.v:3007$71_Y end - attribute \src "ls180.v:3046.9-3046.96" - cell $and $and$ls180.v:3046$75 + attribute \src "ls180.v:3049.9-3049.96" + cell $and $and$ls180.v:3049$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250372,10 +252901,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_socbushandler_converted_interface_stb connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:3046$75_Y + connect \Y $and$ls180.v:3049$75_Y end - attribute \src "ls180.v:3064.9-3064.96" - cell $and $and$ls180.v:3064$82 + attribute \src "ls180.v:3067.9-3067.96" + cell $and $and$ls180.v:3067$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250383,10 +252912,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_socbushandler_converted_interface_stb connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:3064$82_Y + connect \Y $and$ls180.v:3067$82_Y end - attribute \src "ls180.v:3074.31-3074.90" - cell $and $and$ls180.v:3074$84 + attribute \src "ls180.v:3077.31-3077.90" + cell $and $and$ls180.v:3077$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250394,32 +252923,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3074$84_Y + connect \Y $and$ls180.v:3077$84_Y end - attribute \src "ls180.v:3074.30-3074.121" - cell $and $and$ls180.v:3074$85 + attribute \src "ls180.v:3077.30-3077.121" + cell $and $and$ls180.v:3077$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3074$84_Y + connect \A $and$ls180.v:3077$84_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3074$85_Y + connect \Y $and$ls180.v:3077$85_Y end - attribute \src "ls180.v:3074.29-3074.156" - cell $and $and$ls180.v:3074$86 + attribute \src "ls180.v:3077.29-3077.156" + cell $and $and$ls180.v:3077$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3074$85_Y + connect \A $and$ls180.v:3077$85_Y connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:3074$86_Y + connect \Y $and$ls180.v:3077$86_Y end - attribute \src "ls180.v:3075.31-3075.90" - cell $and $and$ls180.v:3075$87 + attribute \src "ls180.v:3078.31-3078.90" + cell $and $and$ls180.v:3078$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250427,32 +252956,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3075$87_Y + connect \Y $and$ls180.v:3078$87_Y end - attribute \src "ls180.v:3075.30-3075.121" - cell $and $and$ls180.v:3075$88 + attribute \src "ls180.v:3078.30-3078.121" + cell $and $and$ls180.v:3078$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3075$87_Y + connect \A $and$ls180.v:3078$87_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3075$88_Y + connect \Y $and$ls180.v:3078$88_Y end - attribute \src "ls180.v:3075.29-3075.156" - cell $and $and$ls180.v:3075$89 + attribute \src "ls180.v:3078.29-3078.156" + cell $and $and$ls180.v:3078$89 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3075$88_Y + connect \A $and$ls180.v:3078$88_Y connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:3075$89_Y + connect \Y $and$ls180.v:3078$89_Y end - attribute \src "ls180.v:3076.31-3076.90" - cell $and $and$ls180.v:3076$90 + attribute \src "ls180.v:3079.31-3079.90" + cell $and $and$ls180.v:3079$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250460,32 +252989,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3076$90_Y + connect \Y $and$ls180.v:3079$90_Y end - attribute \src "ls180.v:3076.30-3076.121" - cell $and $and$ls180.v:3076$91 + attribute \src "ls180.v:3079.30-3079.121" + cell $and $and$ls180.v:3079$91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3076$90_Y + connect \A $and$ls180.v:3079$90_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3076$91_Y + connect \Y $and$ls180.v:3079$91_Y end - attribute \src "ls180.v:3076.29-3076.156" - cell $and $and$ls180.v:3076$92 + attribute \src "ls180.v:3079.29-3079.156" + cell $and $and$ls180.v:3079$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3076$91_Y + connect \A $and$ls180.v:3079$91_Y connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:3076$92_Y + connect \Y $and$ls180.v:3079$92_Y end - attribute \src "ls180.v:3077.31-3077.90" - cell $and $and$ls180.v:3077$93 + attribute \src "ls180.v:3080.31-3080.90" + cell $and $and$ls180.v:3080$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250493,32 +253022,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3077$93_Y + connect \Y $and$ls180.v:3080$93_Y end - attribute \src "ls180.v:3077.30-3077.121" - cell $and $and$ls180.v:3077$94 + attribute \src "ls180.v:3080.30-3080.121" + cell $and $and$ls180.v:3080$94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3077$93_Y + connect \A $and$ls180.v:3080$93_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3077$94_Y + connect \Y $and$ls180.v:3080$94_Y end - attribute \src "ls180.v:3077.29-3077.156" - cell $and $and$ls180.v:3077$95 + attribute \src "ls180.v:3080.29-3080.156" + cell $and $and$ls180.v:3080$95 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3077$94_Y + connect \A $and$ls180.v:3080$94_Y connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:3077$95_Y + connect \Y $and$ls180.v:3080$95_Y end - attribute \src "ls180.v:3078.31-3078.90" - cell $and $and$ls180.v:3078$96 + attribute \src "ls180.v:3081.31-3081.90" + cell $and $and$ls180.v:3081$96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250526,54 +253055,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3078$96_Y + connect \Y $and$ls180.v:3081$96_Y end - attribute \src "ls180.v:3078.30-3078.121" - cell $and $and$ls180.v:3078$97 + attribute \src "ls180.v:3081.30-3081.121" + cell $and $and$ls180.v:3081$97 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3078$96_Y + connect \A $and$ls180.v:3081$96_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3078$97_Y + connect \Y $and$ls180.v:3081$97_Y end - attribute \src "ls180.v:3078.29-3078.156" - cell $and $and$ls180.v:3078$98 + attribute \src "ls180.v:3081.29-3081.156" + cell $and $and$ls180.v:3081$98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3078$97_Y + connect \A $and$ls180.v:3081$97_Y connect \B \main_libresocsim_ram_bus_sel [4] - connect \Y $and$ls180.v:3078$98_Y + connect \Y $and$ls180.v:3081$98_Y end - attribute \src "ls180.v:3079.30-3079.121" - cell $and $and$ls180.v:3079$100 + attribute \src "ls180.v:3082.30-3082.121" + cell $and $and$ls180.v:3082$100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3079$99_Y + connect \A $and$ls180.v:3082$99_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3079$100_Y + connect \Y $and$ls180.v:3082$100_Y end - attribute \src "ls180.v:3079.29-3079.156" - cell $and $and$ls180.v:3079$101 + attribute \src "ls180.v:3082.29-3082.156" + cell $and $and$ls180.v:3082$101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3079$100_Y + connect \A $and$ls180.v:3082$100_Y connect \B \main_libresocsim_ram_bus_sel [5] - connect \Y $and$ls180.v:3079$101_Y + connect \Y $and$ls180.v:3082$101_Y end - attribute \src "ls180.v:3079.31-3079.90" - cell $and $and$ls180.v:3079$99 + attribute \src "ls180.v:3082.31-3082.90" + cell $and $and$ls180.v:3082$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250581,10 +253110,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3079$99_Y + connect \Y $and$ls180.v:3082$99_Y end - attribute \src "ls180.v:3080.31-3080.90" - cell $and $and$ls180.v:3080$102 + attribute \src "ls180.v:3083.31-3083.90" + cell $and $and$ls180.v:3083$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250592,32 +253121,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3080$102_Y + connect \Y $and$ls180.v:3083$102_Y end - attribute \src "ls180.v:3080.30-3080.121" - cell $and $and$ls180.v:3080$103 + attribute \src "ls180.v:3083.30-3083.121" + cell $and $and$ls180.v:3083$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3080$102_Y + connect \A $and$ls180.v:3083$102_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3080$103_Y + connect \Y $and$ls180.v:3083$103_Y end - attribute \src "ls180.v:3080.29-3080.156" - cell $and $and$ls180.v:3080$104 + attribute \src "ls180.v:3083.29-3083.156" + cell $and $and$ls180.v:3083$104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3080$103_Y + connect \A $and$ls180.v:3083$103_Y connect \B \main_libresocsim_ram_bus_sel [6] - connect \Y $and$ls180.v:3080$104_Y + connect \Y $and$ls180.v:3083$104_Y end - attribute \src "ls180.v:3081.31-3081.90" - cell $and $and$ls180.v:3081$105 + attribute \src "ls180.v:3084.31-3084.90" + cell $and $and$ls180.v:3084$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250625,32 +253154,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3081$105_Y + connect \Y $and$ls180.v:3084$105_Y end - attribute \src "ls180.v:3081.30-3081.121" - cell $and $and$ls180.v:3081$106 + attribute \src "ls180.v:3084.30-3084.121" + cell $and $and$ls180.v:3084$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3081$105_Y + connect \A $and$ls180.v:3084$105_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3081$106_Y + connect \Y $and$ls180.v:3084$106_Y end - attribute \src "ls180.v:3081.29-3081.156" - cell $and $and$ls180.v:3081$107 + attribute \src "ls180.v:3084.29-3084.156" + cell $and $and$ls180.v:3084$107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3081$106_Y + connect \A $and$ls180.v:3084$106_Y connect \B \main_libresocsim_ram_bus_sel [7] - connect \Y $and$ls180.v:3081$107_Y + connect \Y $and$ls180.v:3084$107_Y end - attribute \src "ls180.v:3090.7-3090.89" - cell $and $and$ls180.v:3090$110 + attribute \src "ls180.v:3093.7-3093.89" + cell $and $and$ls180.v:3093$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250658,10 +253187,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_re connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:3090$110_Y + connect \Y $and$ls180.v:3093$110_Y end - attribute \src "ls180.v:3095.32-3095.111" - cell $and $and$ls180.v:3095$111 + attribute \src "ls180.v:3098.32-3098.111" + cell $and $and$ls180.v:3098$111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250669,10 +253198,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_w connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:3095$111_Y + connect \Y $and$ls180.v:3098$111_Y end - attribute \src "ls180.v:3099.25-3099.82" - cell $and $and$ls180.v:3099$113 + attribute \src "ls180.v:3102.25-3102.82" + cell $and $and$ls180.v:3102$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250680,32 +253209,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3099$113_Y + connect \Y $and$ls180.v:3102$113_Y end - attribute \src "ls180.v:3099.24-3099.112" - cell $and $and$ls180.v:3099$114 + attribute \src "ls180.v:3102.24-3102.112" + cell $and $and$ls180.v:3102$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3099$113_Y + connect \A $and$ls180.v:3102$113_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3099$114_Y + connect \Y $and$ls180.v:3102$114_Y end - attribute \src "ls180.v:3099.23-3099.146" - cell $and $and$ls180.v:3099$115 + attribute \src "ls180.v:3102.23-3102.146" + cell $and $and$ls180.v:3102$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3099$114_Y + connect \A $and$ls180.v:3102$114_Y connect \B \main_interface0_ram_bus_sel [0] - connect \Y $and$ls180.v:3099$115_Y + connect \Y $and$ls180.v:3102$115_Y end - attribute \src "ls180.v:3100.25-3100.82" - cell $and $and$ls180.v:3100$116 + attribute \src "ls180.v:3103.25-3103.82" + cell $and $and$ls180.v:3103$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250713,32 +253242,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3100$116_Y + connect \Y $and$ls180.v:3103$116_Y end - attribute \src "ls180.v:3100.24-3100.112" - cell $and $and$ls180.v:3100$117 + attribute \src "ls180.v:3103.24-3103.112" + cell $and $and$ls180.v:3103$117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3100$116_Y + connect \A $and$ls180.v:3103$116_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3100$117_Y + connect \Y $and$ls180.v:3103$117_Y end - attribute \src "ls180.v:3100.23-3100.146" - cell $and $and$ls180.v:3100$118 + attribute \src "ls180.v:3103.23-3103.146" + cell $and $and$ls180.v:3103$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3100$117_Y + connect \A $and$ls180.v:3103$117_Y connect \B \main_interface0_ram_bus_sel [1] - connect \Y $and$ls180.v:3100$118_Y + connect \Y $and$ls180.v:3103$118_Y end - attribute \src "ls180.v:3101.25-3101.82" - cell $and $and$ls180.v:3101$119 + attribute \src "ls180.v:3104.25-3104.82" + cell $and $and$ls180.v:3104$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250746,32 +253275,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3101$119_Y + connect \Y $and$ls180.v:3104$119_Y end - attribute \src "ls180.v:3101.24-3101.112" - cell $and $and$ls180.v:3101$120 + attribute \src "ls180.v:3104.24-3104.112" + cell $and $and$ls180.v:3104$120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3101$119_Y + connect \A $and$ls180.v:3104$119_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3101$120_Y + connect \Y $and$ls180.v:3104$120_Y end - attribute \src "ls180.v:3101.23-3101.146" - cell $and $and$ls180.v:3101$121 + attribute \src "ls180.v:3104.23-3104.146" + cell $and $and$ls180.v:3104$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3101$120_Y + connect \A $and$ls180.v:3104$120_Y connect \B \main_interface0_ram_bus_sel [2] - connect \Y $and$ls180.v:3101$121_Y + connect \Y $and$ls180.v:3104$121_Y end - attribute \src "ls180.v:3102.25-3102.82" - cell $and $and$ls180.v:3102$122 + attribute \src "ls180.v:3105.25-3105.82" + cell $and $and$ls180.v:3105$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250779,32 +253308,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3102$122_Y + connect \Y $and$ls180.v:3105$122_Y end - attribute \src "ls180.v:3102.24-3102.112" - cell $and $and$ls180.v:3102$123 + attribute \src "ls180.v:3105.24-3105.112" + cell $and $and$ls180.v:3105$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3102$122_Y + connect \A $and$ls180.v:3105$122_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3102$123_Y + connect \Y $and$ls180.v:3105$123_Y end - attribute \src "ls180.v:3102.23-3102.146" - cell $and $and$ls180.v:3102$124 + attribute \src "ls180.v:3105.23-3105.146" + cell $and $and$ls180.v:3105$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3102$123_Y + connect \A $and$ls180.v:3105$123_Y connect \B \main_interface0_ram_bus_sel [3] - connect \Y $and$ls180.v:3102$124_Y + connect \Y $and$ls180.v:3105$124_Y end - attribute \src "ls180.v:3103.25-3103.82" - cell $and $and$ls180.v:3103$125 + attribute \src "ls180.v:3106.25-3106.82" + cell $and $and$ls180.v:3106$125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250812,32 +253341,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3103$125_Y + connect \Y $and$ls180.v:3106$125_Y end - attribute \src "ls180.v:3103.24-3103.112" - cell $and $and$ls180.v:3103$126 + attribute \src "ls180.v:3106.24-3106.112" + cell $and $and$ls180.v:3106$126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3103$125_Y + connect \A $and$ls180.v:3106$125_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3103$126_Y + connect \Y $and$ls180.v:3106$126_Y end - attribute \src "ls180.v:3103.23-3103.146" - cell $and $and$ls180.v:3103$127 + attribute \src "ls180.v:3106.23-3106.146" + cell $and $and$ls180.v:3106$127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3103$126_Y + connect \A $and$ls180.v:3106$126_Y connect \B \main_interface0_ram_bus_sel [4] - connect \Y $and$ls180.v:3103$127_Y + connect \Y $and$ls180.v:3106$127_Y end - attribute \src "ls180.v:3104.25-3104.82" - cell $and $and$ls180.v:3104$128 + attribute \src "ls180.v:3107.25-3107.82" + cell $and $and$ls180.v:3107$128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250845,32 +253374,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3104$128_Y + connect \Y $and$ls180.v:3107$128_Y end - attribute \src "ls180.v:3104.24-3104.112" - cell $and $and$ls180.v:3104$129 + attribute \src "ls180.v:3107.24-3107.112" + cell $and $and$ls180.v:3107$129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3104$128_Y + connect \A $and$ls180.v:3107$128_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3104$129_Y + connect \Y $and$ls180.v:3107$129_Y end - attribute \src "ls180.v:3104.23-3104.146" - cell $and $and$ls180.v:3104$130 + attribute \src "ls180.v:3107.23-3107.146" + cell $and $and$ls180.v:3107$130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3104$129_Y + connect \A $and$ls180.v:3107$129_Y connect \B \main_interface0_ram_bus_sel [5] - connect \Y $and$ls180.v:3104$130_Y + connect \Y $and$ls180.v:3107$130_Y end - attribute \src "ls180.v:3105.25-3105.82" - cell $and $and$ls180.v:3105$131 + attribute \src "ls180.v:3108.25-3108.82" + cell $and $and$ls180.v:3108$131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250878,32 +253407,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3105$131_Y + connect \Y $and$ls180.v:3108$131_Y end - attribute \src "ls180.v:3105.24-3105.112" - cell $and $and$ls180.v:3105$132 + attribute \src "ls180.v:3108.24-3108.112" + cell $and $and$ls180.v:3108$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3105$131_Y + connect \A $and$ls180.v:3108$131_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3105$132_Y + connect \Y $and$ls180.v:3108$132_Y end - attribute \src "ls180.v:3105.23-3105.146" - cell $and $and$ls180.v:3105$133 + attribute \src "ls180.v:3108.23-3108.146" + cell $and $and$ls180.v:3108$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3105$132_Y + connect \A $and$ls180.v:3108$132_Y connect \B \main_interface0_ram_bus_sel [6] - connect \Y $and$ls180.v:3105$133_Y + connect \Y $and$ls180.v:3108$133_Y end - attribute \src "ls180.v:3106.25-3106.82" - cell $and $and$ls180.v:3106$134 + attribute \src "ls180.v:3109.25-3109.82" + cell $and $and$ls180.v:3109$134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250911,32 +253440,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3106$134_Y + connect \Y $and$ls180.v:3109$134_Y end - attribute \src "ls180.v:3106.24-3106.112" - cell $and $and$ls180.v:3106$135 + attribute \src "ls180.v:3109.24-3109.112" + cell $and $and$ls180.v:3109$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3106$134_Y + connect \A $and$ls180.v:3109$134_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3106$135_Y + connect \Y $and$ls180.v:3109$135_Y end - attribute \src "ls180.v:3106.23-3106.146" - cell $and $and$ls180.v:3106$136 + attribute \src "ls180.v:3109.23-3109.146" + cell $and $and$ls180.v:3109$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3106$135_Y + connect \A $and$ls180.v:3109$135_Y connect \B \main_interface0_ram_bus_sel [7] - connect \Y $and$ls180.v:3106$136_Y + connect \Y $and$ls180.v:3109$136_Y end - attribute \src "ls180.v:3113.25-3113.82" - cell $and $and$ls180.v:3113$138 + attribute \src "ls180.v:3116.25-3116.82" + cell $and $and$ls180.v:3116$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250944,32 +253473,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3113$138_Y + connect \Y $and$ls180.v:3116$138_Y end - attribute \src "ls180.v:3113.24-3113.112" - cell $and $and$ls180.v:3113$139 + attribute \src "ls180.v:3116.24-3116.112" + cell $and $and$ls180.v:3116$139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3113$138_Y + connect \A $and$ls180.v:3116$138_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3113$139_Y + connect \Y $and$ls180.v:3116$139_Y end - attribute \src "ls180.v:3113.23-3113.146" - cell $and $and$ls180.v:3113$140 + attribute \src "ls180.v:3116.23-3116.146" + cell $and $and$ls180.v:3116$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3113$139_Y + connect \A $and$ls180.v:3116$139_Y connect \B \main_interface1_ram_bus_sel [0] - connect \Y $and$ls180.v:3113$140_Y + connect \Y $and$ls180.v:3116$140_Y end - attribute \src "ls180.v:3114.25-3114.82" - cell $and $and$ls180.v:3114$141 + attribute \src "ls180.v:3117.25-3117.82" + cell $and $and$ls180.v:3117$141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250977,32 +253506,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3114$141_Y + connect \Y $and$ls180.v:3117$141_Y end - attribute \src "ls180.v:3114.24-3114.112" - cell $and $and$ls180.v:3114$142 + attribute \src "ls180.v:3117.24-3117.112" + cell $and $and$ls180.v:3117$142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3114$141_Y + connect \A $and$ls180.v:3117$141_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3114$142_Y + connect \Y $and$ls180.v:3117$142_Y end - attribute \src "ls180.v:3114.23-3114.146" - cell $and $and$ls180.v:3114$143 + attribute \src "ls180.v:3117.23-3117.146" + cell $and $and$ls180.v:3117$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3114$142_Y + connect \A $and$ls180.v:3117$142_Y connect \B \main_interface1_ram_bus_sel [1] - connect \Y $and$ls180.v:3114$143_Y + connect \Y $and$ls180.v:3117$143_Y end - attribute \src "ls180.v:3115.25-3115.82" - cell $and $and$ls180.v:3115$144 + attribute \src "ls180.v:3118.25-3118.82" + cell $and $and$ls180.v:3118$144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251010,32 +253539,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3115$144_Y + connect \Y $and$ls180.v:3118$144_Y end - attribute \src "ls180.v:3115.24-3115.112" - cell $and $and$ls180.v:3115$145 + attribute \src "ls180.v:3118.24-3118.112" + cell $and $and$ls180.v:3118$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3115$144_Y + connect \A $and$ls180.v:3118$144_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3115$145_Y + connect \Y $and$ls180.v:3118$145_Y end - attribute \src "ls180.v:3115.23-3115.146" - cell $and $and$ls180.v:3115$146 + attribute \src "ls180.v:3118.23-3118.146" + cell $and $and$ls180.v:3118$146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3115$145_Y + connect \A $and$ls180.v:3118$145_Y connect \B \main_interface1_ram_bus_sel [2] - connect \Y $and$ls180.v:3115$146_Y + connect \Y $and$ls180.v:3118$146_Y end - attribute \src "ls180.v:3116.25-3116.82" - cell $and $and$ls180.v:3116$147 + attribute \src "ls180.v:3119.25-3119.82" + cell $and $and$ls180.v:3119$147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251043,32 +253572,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3116$147_Y + connect \Y $and$ls180.v:3119$147_Y end - attribute \src "ls180.v:3116.24-3116.112" - cell $and $and$ls180.v:3116$148 + attribute \src "ls180.v:3119.24-3119.112" + cell $and $and$ls180.v:3119$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3116$147_Y + connect \A $and$ls180.v:3119$147_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3116$148_Y + connect \Y $and$ls180.v:3119$148_Y end - attribute \src "ls180.v:3116.23-3116.146" - cell $and $and$ls180.v:3116$149 + attribute \src "ls180.v:3119.23-3119.146" + cell $and $and$ls180.v:3119$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3116$148_Y + connect \A $and$ls180.v:3119$148_Y connect \B \main_interface1_ram_bus_sel [3] - connect \Y $and$ls180.v:3116$149_Y + connect \Y $and$ls180.v:3119$149_Y end - attribute \src "ls180.v:3117.25-3117.82" - cell $and $and$ls180.v:3117$150 + attribute \src "ls180.v:3120.25-3120.82" + cell $and $and$ls180.v:3120$150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251076,32 +253605,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3117$150_Y + connect \Y $and$ls180.v:3120$150_Y end - attribute \src "ls180.v:3117.24-3117.112" - cell $and $and$ls180.v:3117$151 + attribute \src "ls180.v:3120.24-3120.112" + cell $and $and$ls180.v:3120$151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3117$150_Y + connect \A $and$ls180.v:3120$150_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3117$151_Y + connect \Y $and$ls180.v:3120$151_Y end - attribute \src "ls180.v:3117.23-3117.146" - cell $and $and$ls180.v:3117$152 + attribute \src "ls180.v:3120.23-3120.146" + cell $and $and$ls180.v:3120$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3117$151_Y + connect \A $and$ls180.v:3120$151_Y connect \B \main_interface1_ram_bus_sel [4] - connect \Y $and$ls180.v:3117$152_Y + connect \Y $and$ls180.v:3120$152_Y end - attribute \src "ls180.v:3118.25-3118.82" - cell $and $and$ls180.v:3118$153 + attribute \src "ls180.v:3121.25-3121.82" + cell $and $and$ls180.v:3121$153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251109,32 +253638,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3118$153_Y + connect \Y $and$ls180.v:3121$153_Y end - attribute \src "ls180.v:3118.24-3118.112" - cell $and $and$ls180.v:3118$154 + attribute \src "ls180.v:3121.24-3121.112" + cell $and $and$ls180.v:3121$154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3118$153_Y + connect \A $and$ls180.v:3121$153_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3118$154_Y + connect \Y $and$ls180.v:3121$154_Y end - attribute \src "ls180.v:3118.23-3118.146" - cell $and $and$ls180.v:3118$155 + attribute \src "ls180.v:3121.23-3121.146" + cell $and $and$ls180.v:3121$155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3118$154_Y + connect \A $and$ls180.v:3121$154_Y connect \B \main_interface1_ram_bus_sel [5] - connect \Y $and$ls180.v:3118$155_Y + connect \Y $and$ls180.v:3121$155_Y end - attribute \src "ls180.v:3119.25-3119.82" - cell $and $and$ls180.v:3119$156 + attribute \src "ls180.v:3122.25-3122.82" + cell $and $and$ls180.v:3122$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251142,32 +253671,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3119$156_Y + connect \Y $and$ls180.v:3122$156_Y end - attribute \src "ls180.v:3119.24-3119.112" - cell $and $and$ls180.v:3119$157 + attribute \src "ls180.v:3122.24-3122.112" + cell $and $and$ls180.v:3122$157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3119$156_Y + connect \A $and$ls180.v:3122$156_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3119$157_Y + connect \Y $and$ls180.v:3122$157_Y end - attribute \src "ls180.v:3119.23-3119.146" - cell $and $and$ls180.v:3119$158 + attribute \src "ls180.v:3122.23-3122.146" + cell $and $and$ls180.v:3122$158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3119$157_Y + connect \A $and$ls180.v:3122$157_Y connect \B \main_interface1_ram_bus_sel [6] - connect \Y $and$ls180.v:3119$158_Y + connect \Y $and$ls180.v:3122$158_Y end - attribute \src "ls180.v:3120.25-3120.82" - cell $and $and$ls180.v:3120$159 + attribute \src "ls180.v:3123.25-3123.82" + cell $and $and$ls180.v:3123$159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251175,32 +253704,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3120$159_Y + connect \Y $and$ls180.v:3123$159_Y end - attribute \src "ls180.v:3120.24-3120.112" - cell $and $and$ls180.v:3120$160 + attribute \src "ls180.v:3123.24-3123.112" + cell $and $and$ls180.v:3123$160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3120$159_Y + connect \A $and$ls180.v:3123$159_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3120$160_Y + connect \Y $and$ls180.v:3123$160_Y end - attribute \src "ls180.v:3120.23-3120.146" - cell $and $and$ls180.v:3120$161 + attribute \src "ls180.v:3123.23-3123.146" + cell $and $and$ls180.v:3123$161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3120$160_Y + connect \A $and$ls180.v:3123$160_Y connect \B \main_interface1_ram_bus_sel [7] - connect \Y $and$ls180.v:3120$161_Y + connect \Y $and$ls180.v:3123$161_Y end - attribute \src "ls180.v:3127.25-3127.82" - cell $and $and$ls180.v:3127$163 + attribute \src "ls180.v:3130.25-3130.82" + cell $and $and$ls180.v:3130$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251208,32 +253737,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3127$163_Y + connect \Y $and$ls180.v:3130$163_Y end - attribute \src "ls180.v:3127.24-3127.112" - cell $and $and$ls180.v:3127$164 + attribute \src "ls180.v:3130.24-3130.112" + cell $and $and$ls180.v:3130$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3127$163_Y + connect \A $and$ls180.v:3130$163_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3127$164_Y + connect \Y $and$ls180.v:3130$164_Y end - attribute \src "ls180.v:3127.23-3127.146" - cell $and $and$ls180.v:3127$165 + attribute \src "ls180.v:3130.23-3130.146" + cell $and $and$ls180.v:3130$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3127$164_Y + connect \A $and$ls180.v:3130$164_Y connect \B \main_interface2_ram_bus_sel [0] - connect \Y $and$ls180.v:3127$165_Y + connect \Y $and$ls180.v:3130$165_Y end - attribute \src "ls180.v:3128.25-3128.82" - cell $and $and$ls180.v:3128$166 + attribute \src "ls180.v:3131.25-3131.82" + cell $and $and$ls180.v:3131$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251241,32 +253770,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3128$166_Y + connect \Y $and$ls180.v:3131$166_Y end - attribute \src "ls180.v:3128.24-3128.112" - cell $and $and$ls180.v:3128$167 + attribute \src "ls180.v:3131.24-3131.112" + cell $and $and$ls180.v:3131$167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3128$166_Y + connect \A $and$ls180.v:3131$166_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3128$167_Y + connect \Y $and$ls180.v:3131$167_Y end - attribute \src "ls180.v:3128.23-3128.146" - cell $and $and$ls180.v:3128$168 + attribute \src "ls180.v:3131.23-3131.146" + cell $and $and$ls180.v:3131$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3128$167_Y + connect \A $and$ls180.v:3131$167_Y connect \B \main_interface2_ram_bus_sel [1] - connect \Y $and$ls180.v:3128$168_Y + connect \Y $and$ls180.v:3131$168_Y end - attribute \src "ls180.v:3129.25-3129.82" - cell $and $and$ls180.v:3129$169 + attribute \src "ls180.v:3132.25-3132.82" + cell $and $and$ls180.v:3132$169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251274,32 +253803,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3129$169_Y + connect \Y $and$ls180.v:3132$169_Y end - attribute \src "ls180.v:3129.24-3129.112" - cell $and $and$ls180.v:3129$170 + attribute \src "ls180.v:3132.24-3132.112" + cell $and $and$ls180.v:3132$170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3129$169_Y + connect \A $and$ls180.v:3132$169_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3129$170_Y + connect \Y $and$ls180.v:3132$170_Y end - attribute \src "ls180.v:3129.23-3129.146" - cell $and $and$ls180.v:3129$171 + attribute \src "ls180.v:3132.23-3132.146" + cell $and $and$ls180.v:3132$171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3129$170_Y + connect \A $and$ls180.v:3132$170_Y connect \B \main_interface2_ram_bus_sel [2] - connect \Y $and$ls180.v:3129$171_Y + connect \Y $and$ls180.v:3132$171_Y end - attribute \src "ls180.v:3130.25-3130.82" - cell $and $and$ls180.v:3130$172 + attribute \src "ls180.v:3133.25-3133.82" + cell $and $and$ls180.v:3133$172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251307,32 +253836,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3130$172_Y + connect \Y $and$ls180.v:3133$172_Y end - attribute \src "ls180.v:3130.24-3130.112" - cell $and $and$ls180.v:3130$173 + attribute \src "ls180.v:3133.24-3133.112" + cell $and $and$ls180.v:3133$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3130$172_Y + connect \A $and$ls180.v:3133$172_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3130$173_Y + connect \Y $and$ls180.v:3133$173_Y end - attribute \src "ls180.v:3130.23-3130.146" - cell $and $and$ls180.v:3130$174 + attribute \src "ls180.v:3133.23-3133.146" + cell $and $and$ls180.v:3133$174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3130$173_Y + connect \A $and$ls180.v:3133$173_Y connect \B \main_interface2_ram_bus_sel [3] - connect \Y $and$ls180.v:3130$174_Y + connect \Y $and$ls180.v:3133$174_Y end - attribute \src "ls180.v:3131.25-3131.82" - cell $and $and$ls180.v:3131$175 + attribute \src "ls180.v:3134.25-3134.82" + cell $and $and$ls180.v:3134$175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251340,32 +253869,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3131$175_Y + connect \Y $and$ls180.v:3134$175_Y end - attribute \src "ls180.v:3131.24-3131.112" - cell $and $and$ls180.v:3131$176 + attribute \src "ls180.v:3134.24-3134.112" + cell $and $and$ls180.v:3134$176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3131$175_Y + connect \A $and$ls180.v:3134$175_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3131$176_Y + connect \Y $and$ls180.v:3134$176_Y end - attribute \src "ls180.v:3131.23-3131.146" - cell $and $and$ls180.v:3131$177 + attribute \src "ls180.v:3134.23-3134.146" + cell $and $and$ls180.v:3134$177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3131$176_Y + connect \A $and$ls180.v:3134$176_Y connect \B \main_interface2_ram_bus_sel [4] - connect \Y $and$ls180.v:3131$177_Y + connect \Y $and$ls180.v:3134$177_Y end - attribute \src "ls180.v:3132.25-3132.82" - cell $and $and$ls180.v:3132$178 + attribute \src "ls180.v:3135.25-3135.82" + cell $and $and$ls180.v:3135$178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251373,32 +253902,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3132$178_Y + connect \Y $and$ls180.v:3135$178_Y end - attribute \src "ls180.v:3132.24-3132.112" - cell $and $and$ls180.v:3132$179 + attribute \src "ls180.v:3135.24-3135.112" + cell $and $and$ls180.v:3135$179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3132$178_Y + connect \A $and$ls180.v:3135$178_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3132$179_Y + connect \Y $and$ls180.v:3135$179_Y end - attribute \src "ls180.v:3132.23-3132.146" - cell $and $and$ls180.v:3132$180 + attribute \src "ls180.v:3135.23-3135.146" + cell $and $and$ls180.v:3135$180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3132$179_Y + connect \A $and$ls180.v:3135$179_Y connect \B \main_interface2_ram_bus_sel [5] - connect \Y $and$ls180.v:3132$180_Y + connect \Y $and$ls180.v:3135$180_Y end - attribute \src "ls180.v:3133.25-3133.82" - cell $and $and$ls180.v:3133$181 + attribute \src "ls180.v:3136.25-3136.82" + cell $and $and$ls180.v:3136$181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251406,32 +253935,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3133$181_Y + connect \Y $and$ls180.v:3136$181_Y end - attribute \src "ls180.v:3133.24-3133.112" - cell $and $and$ls180.v:3133$182 + attribute \src "ls180.v:3136.24-3136.112" + cell $and $and$ls180.v:3136$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3133$181_Y + connect \A $and$ls180.v:3136$181_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3133$182_Y + connect \Y $and$ls180.v:3136$182_Y end - attribute \src "ls180.v:3133.23-3133.146" - cell $and $and$ls180.v:3133$183 + attribute \src "ls180.v:3136.23-3136.146" + cell $and $and$ls180.v:3136$183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3133$182_Y + connect \A $and$ls180.v:3136$182_Y connect \B \main_interface2_ram_bus_sel [6] - connect \Y $and$ls180.v:3133$183_Y + connect \Y $and$ls180.v:3136$183_Y end - attribute \src "ls180.v:3134.25-3134.82" - cell $and $and$ls180.v:3134$184 + attribute \src "ls180.v:3137.25-3137.82" + cell $and $and$ls180.v:3137$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251439,131 +253968,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3134$184_Y + connect \Y $and$ls180.v:3137$184_Y end - attribute \src "ls180.v:3134.24-3134.112" - cell $and $and$ls180.v:3134$185 + attribute \src "ls180.v:3137.24-3137.112" + cell $and $and$ls180.v:3137$185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$184_Y + connect \A $and$ls180.v:3137$184_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3134$185_Y + connect \Y $and$ls180.v:3137$185_Y end - attribute \src "ls180.v:3134.23-3134.146" - cell $and $and$ls180.v:3134$186 + attribute \src "ls180.v:3137.23-3137.146" + cell $and $and$ls180.v:3137$186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$185_Y + connect \A $and$ls180.v:3137$185_Y connect \B \main_interface2_ram_bus_sel [7] - connect \Y $and$ls180.v:3134$186_Y - end - attribute \src "ls180.v:3141.25-3141.82" - cell $and $and$ls180.v:3141$188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3141$188_Y - end - attribute \src "ls180.v:3141.24-3141.112" - cell $and $and$ls180.v:3141$189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3141$188_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3141$189_Y - end - attribute \src "ls180.v:3141.23-3141.146" - cell $and $and$ls180.v:3141$190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3141$189_Y - connect \B \main_interface3_ram_bus_sel [0] - connect \Y $and$ls180.v:3141$190_Y - end - attribute \src "ls180.v:3142.25-3142.82" - cell $and $and$ls180.v:3142$191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3142$191_Y - end - attribute \src "ls180.v:3142.24-3142.112" - cell $and $and$ls180.v:3142$192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3142$191_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3142$192_Y - end - attribute \src "ls180.v:3142.23-3142.146" - cell $and $and$ls180.v:3142$193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3142$192_Y - connect \B \main_interface3_ram_bus_sel [1] - connect \Y $and$ls180.v:3142$193_Y - end - attribute \src "ls180.v:3143.25-3143.82" - cell $and $and$ls180.v:3143$194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3143$194_Y - end - attribute \src "ls180.v:3143.24-3143.112" - cell $and $and$ls180.v:3143$195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3143$194_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3143$195_Y - end - attribute \src "ls180.v:3143.23-3143.146" - cell $and $and$ls180.v:3143$196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3143$195_Y - connect \B \main_interface3_ram_bus_sel [2] - connect \Y $and$ls180.v:3143$196_Y + connect \Y $and$ls180.v:3137$186_Y end attribute \src "ls180.v:3144.25-3144.82" - cell $and $and$ls180.v:3144$197 + cell $and $and$ls180.v:3144$188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251571,32 +254001,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_cyc connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3144$197_Y + connect \Y $and$ls180.v:3144$188_Y end attribute \src "ls180.v:3144.24-3144.112" - cell $and $and$ls180.v:3144$198 + cell $and $and$ls180.v:3144$189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3144$197_Y + connect \A $and$ls180.v:3144$188_Y connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3144$198_Y + connect \Y $and$ls180.v:3144$189_Y end attribute \src "ls180.v:3144.23-3144.146" - cell $and $and$ls180.v:3144$199 + cell $and $and$ls180.v:3144$190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3144$198_Y - connect \B \main_interface3_ram_bus_sel [3] - connect \Y $and$ls180.v:3144$199_Y + connect \A $and$ls180.v:3144$189_Y + connect \B \main_interface3_ram_bus_sel [0] + connect \Y $and$ls180.v:3144$190_Y end attribute \src "ls180.v:3145.25-3145.82" - cell $and $and$ls180.v:3145$200 + cell $and $and$ls180.v:3145$191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251604,32 +254034,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_cyc connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3145$200_Y + connect \Y $and$ls180.v:3145$191_Y end attribute \src "ls180.v:3145.24-3145.112" - cell $and $and$ls180.v:3145$201 + cell $and $and$ls180.v:3145$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3145$200_Y + connect \A $and$ls180.v:3145$191_Y connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3145$201_Y + connect \Y $and$ls180.v:3145$192_Y end attribute \src "ls180.v:3145.23-3145.146" - cell $and $and$ls180.v:3145$202 + cell $and $and$ls180.v:3145$193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3145$201_Y - connect \B \main_interface3_ram_bus_sel [4] - connect \Y $and$ls180.v:3145$202_Y + connect \A $and$ls180.v:3145$192_Y + connect \B \main_interface3_ram_bus_sel [1] + connect \Y $and$ls180.v:3145$193_Y end attribute \src "ls180.v:3146.25-3146.82" - cell $and $and$ls180.v:3146$203 + cell $and $and$ls180.v:3146$194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251637,32 +254067,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_cyc connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3146$203_Y + connect \Y $and$ls180.v:3146$194_Y end attribute \src "ls180.v:3146.24-3146.112" - cell $and $and$ls180.v:3146$204 + cell $and $and$ls180.v:3146$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3146$203_Y + connect \A $and$ls180.v:3146$194_Y connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3146$204_Y + connect \Y $and$ls180.v:3146$195_Y end attribute \src "ls180.v:3146.23-3146.146" - cell $and $and$ls180.v:3146$205 + cell $and $and$ls180.v:3146$196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3146$204_Y - connect \B \main_interface3_ram_bus_sel [5] - connect \Y $and$ls180.v:3146$205_Y + connect \A $and$ls180.v:3146$195_Y + connect \B \main_interface3_ram_bus_sel [2] + connect \Y $and$ls180.v:3146$196_Y end attribute \src "ls180.v:3147.25-3147.82" - cell $and $and$ls180.v:3147$206 + cell $and $and$ls180.v:3147$197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251670,32 +254100,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_cyc connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3147$206_Y + connect \Y $and$ls180.v:3147$197_Y end attribute \src "ls180.v:3147.24-3147.112" - cell $and $and$ls180.v:3147$207 + cell $and $and$ls180.v:3147$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3147$206_Y + connect \A $and$ls180.v:3147$197_Y connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3147$207_Y + connect \Y $and$ls180.v:3147$198_Y end attribute \src "ls180.v:3147.23-3147.146" - cell $and $and$ls180.v:3147$208 + cell $and $and$ls180.v:3147$199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3147$207_Y - connect \B \main_interface3_ram_bus_sel [6] - connect \Y $and$ls180.v:3147$208_Y + connect \A $and$ls180.v:3147$198_Y + connect \B \main_interface3_ram_bus_sel [3] + connect \Y $and$ls180.v:3147$199_Y end attribute \src "ls180.v:3148.25-3148.82" - cell $and $and$ls180.v:3148$209 + cell $and $and$ls180.v:3148$200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251703,32 +254133,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_cyc connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3148$209_Y + connect \Y $and$ls180.v:3148$200_Y end attribute \src "ls180.v:3148.24-3148.112" - cell $and $and$ls180.v:3148$210 + cell $and $and$ls180.v:3148$201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$209_Y + connect \A $and$ls180.v:3148$200_Y connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3148$210_Y + connect \Y $and$ls180.v:3148$201_Y end attribute \src "ls180.v:3148.23-3148.146" - cell $and $and$ls180.v:3148$211 + cell $and $and$ls180.v:3148$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3148$201_Y + connect \B \main_interface3_ram_bus_sel [4] + connect \Y $and$ls180.v:3148$202_Y + end + attribute \src "ls180.v:3149.25-3149.82" + cell $and $and$ls180.v:3149$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3149$203_Y + end + attribute \src "ls180.v:3149.24-3149.112" + cell $and $and$ls180.v:3149$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3149$203_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3149$204_Y + end + attribute \src "ls180.v:3149.23-3149.146" + cell $and $and$ls180.v:3149$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3149$204_Y + connect \B \main_interface3_ram_bus_sel [5] + connect \Y $and$ls180.v:3149$205_Y + end + attribute \src "ls180.v:3150.25-3150.82" + cell $and $and$ls180.v:3150$206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$210_Y + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3150$206_Y + end + attribute \src "ls180.v:3150.24-3150.112" + cell $and $and$ls180.v:3150$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3150$206_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3150$207_Y + end + attribute \src "ls180.v:3150.23-3150.146" + cell $and $and$ls180.v:3150$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3150$207_Y + connect \B \main_interface3_ram_bus_sel [6] + connect \Y $and$ls180.v:3150$208_Y + end + attribute \src "ls180.v:3151.25-3151.82" + cell $and $and$ls180.v:3151$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3151$209_Y + end + attribute \src "ls180.v:3151.24-3151.112" + cell $and $and$ls180.v:3151$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3151$209_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3151$210_Y + end + attribute \src "ls180.v:3151.23-3151.146" + cell $and $and$ls180.v:3151$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3151$210_Y connect \B \main_interface3_ram_bus_sel [7] - connect \Y $and$ls180.v:3148$211_Y + connect \Y $and$ls180.v:3151$211_Y end - attribute \src "ls180.v:3265.40-3265.99" - cell $and $and$ls180.v:3265$218 + attribute \src "ls180.v:3268.40-3268.99" + cell $and $and$ls180.v:3268$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251736,10 +254265,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3265$218_Y + connect \Y $and$ls180.v:3268$218_Y end - attribute \src "ls180.v:3266.40-3266.99" - cell $and $and$ls180.v:3266$219 + attribute \src "ls180.v:3269.40-3269.99" + cell $and $and$ls180.v:3269$219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251747,21 +254276,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3266$219_Y + connect \Y $and$ls180.v:3269$219_Y end - attribute \src "ls180.v:3304.38-3304.103" - cell $and $and$ls180.v:3304$225 + attribute \src "ls180.v:3307.38-3307.103" + cell $and $and$ls180.v:3307$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3304$224_Y - connect \Y $and$ls180.v:3304$225_Y + connect \B $eq$ls180.v:3307$224_Y + connect \Y $and$ls180.v:3307$225_Y end - attribute \src "ls180.v:3358.50-3358.119" - cell $and $and$ls180.v:3358$233 + attribute \src "ls180.v:3361.50-3361.119" + cell $and $and$ls180.v:3361$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251769,21 +254298,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3358$233_Y + connect \Y $and$ls180.v:3361$233_Y end - attribute \src "ls180.v:3358.49-3358.167" - cell $and $and$ls180.v:3358$234 + attribute \src "ls180.v:3361.49-3361.167" + cell $and $and$ls180.v:3361$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3358$233_Y + connect \A $and$ls180.v:3361$233_Y connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3358$234_Y + connect \Y $and$ls180.v:3361$234_Y end - attribute \src "ls180.v:3359.49-3359.118" - cell $and $and$ls180.v:3359$235 + attribute \src "ls180.v:3362.49-3362.118" + cell $and $and$ls180.v:3362$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251791,21 +254320,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3359$235_Y + connect \Y $and$ls180.v:3362$235_Y end - attribute \src "ls180.v:3359.48-3359.154" - cell $and $and$ls180.v:3359$236 + attribute \src "ls180.v:3362.48-3362.154" + cell $and $and$ls180.v:3362$236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3359$235_Y + connect \A $and$ls180.v:3362$235_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3359$236_Y + connect \Y $and$ls180.v:3362$236_Y end - attribute \src "ls180.v:3360.50-3360.119" - cell $and $and$ls180.v:3360$237 + attribute \src "ls180.v:3363.50-3363.119" + cell $and $and$ls180.v:3363$237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251813,21 +254342,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3360$237_Y + connect \Y $and$ls180.v:3363$237_Y end - attribute \src "ls180.v:3360.49-3360.155" - cell $and $and$ls180.v:3360$238 + attribute \src "ls180.v:3363.49-3363.155" + cell $and $and$ls180.v:3363$238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3360$237_Y + connect \A $and$ls180.v:3363$237_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3360$238_Y + connect \Y $and$ls180.v:3363$238_Y end - attribute \src "ls180.v:3363.7-3363.114" - cell $and $and$ls180.v:3363$240 + attribute \src "ls180.v:3366.7-3366.114" + cell $and $and$ls180.v:3366$240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251835,21 +254364,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3363$240_Y + connect \Y $and$ls180.v:3366$240_Y end - attribute \src "ls180.v:3392.66-3392.246" - cell $and $and$ls180.v:3392$246 + attribute \src "ls180.v:3395.66-3395.246" + cell $and $and$ls180.v:3395$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3392$245_Y - connect \Y $and$ls180.v:3392$246_Y + connect \B $or$ls180.v:3395$245_Y + connect \Y $and$ls180.v:3395$246_Y end - attribute \src "ls180.v:3393.64-3393.187" - cell $and $and$ls180.v:3393$247 + attribute \src "ls180.v:3396.64-3396.187" + cell $and $and$ls180.v:3396$247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251857,10 +254386,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3393$247_Y + connect \Y $and$ls180.v:3396$247_Y end - attribute \src "ls180.v:3417.9-3417.86" - cell $and $and$ls180.v:3417$253 + attribute \src "ls180.v:3420.9-3420.86" + cell $and $and$ls180.v:3420$253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251868,10 +254397,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3417$253_Y + connect \Y $and$ls180.v:3420$253_Y end - attribute \src "ls180.v:3429.9-3429.86" - cell $and $and$ls180.v:3429$254 + attribute \src "ls180.v:3432.9-3432.86" + cell $and $and$ls180.v:3432$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251879,10 +254408,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3429$254_Y + connect \Y $and$ls180.v:3432$254_Y end - attribute \src "ls180.v:3479.13-3479.87" - cell $and $and$ls180.v:3479$256 + attribute \src "ls180.v:3482.13-3482.87" + cell $and $and$ls180.v:3482$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251890,10 +254419,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_ready connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3479$256_Y + connect \Y $and$ls180.v:3482$256_Y end - attribute \src "ls180.v:3515.50-3515.119" - cell $and $and$ls180.v:3515$263 + attribute \src "ls180.v:3518.50-3518.119" + cell $and $and$ls180.v:3518$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251901,21 +254430,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3515$263_Y + connect \Y $and$ls180.v:3518$263_Y end - attribute \src "ls180.v:3515.49-3515.167" - cell $and $and$ls180.v:3515$264 + attribute \src "ls180.v:3518.49-3518.167" + cell $and $and$ls180.v:3518$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3515$263_Y + connect \A $and$ls180.v:3518$263_Y connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3515$264_Y + connect \Y $and$ls180.v:3518$264_Y end - attribute \src "ls180.v:3516.49-3516.118" - cell $and $and$ls180.v:3516$265 + attribute \src "ls180.v:3519.49-3519.118" + cell $and $and$ls180.v:3519$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251923,21 +254452,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3516$265_Y + connect \Y $and$ls180.v:3519$265_Y end - attribute \src "ls180.v:3516.48-3516.154" - cell $and $and$ls180.v:3516$266 + attribute \src "ls180.v:3519.48-3519.154" + cell $and $and$ls180.v:3519$266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3516$265_Y + connect \A $and$ls180.v:3519$265_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3516$266_Y + connect \Y $and$ls180.v:3519$266_Y end - attribute \src "ls180.v:3517.50-3517.119" - cell $and $and$ls180.v:3517$267 + attribute \src "ls180.v:3520.50-3520.119" + cell $and $and$ls180.v:3520$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251945,21 +254474,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3517$267_Y + connect \Y $and$ls180.v:3520$267_Y end - attribute \src "ls180.v:3517.49-3517.155" - cell $and $and$ls180.v:3517$268 + attribute \src "ls180.v:3520.49-3520.155" + cell $and $and$ls180.v:3520$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3517$267_Y + connect \A $and$ls180.v:3520$267_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3517$268_Y + connect \Y $and$ls180.v:3520$268_Y end - attribute \src "ls180.v:3520.7-3520.114" - cell $and $and$ls180.v:3520$270 + attribute \src "ls180.v:3523.7-3523.114" + cell $and $and$ls180.v:3523$270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251967,21 +254496,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3520$270_Y + connect \Y $and$ls180.v:3523$270_Y end - attribute \src "ls180.v:3549.66-3549.246" - cell $and $and$ls180.v:3549$276 + attribute \src "ls180.v:3552.66-3552.246" + cell $and $and$ls180.v:3552$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3549$275_Y - connect \Y $and$ls180.v:3549$276_Y + connect \B $or$ls180.v:3552$275_Y + connect \Y $and$ls180.v:3552$276_Y end - attribute \src "ls180.v:3550.64-3550.187" - cell $and $and$ls180.v:3550$277 + attribute \src "ls180.v:3553.64-3553.187" + cell $and $and$ls180.v:3553$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251989,10 +254518,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3550$277_Y + connect \Y $and$ls180.v:3553$277_Y end - attribute \src "ls180.v:3574.9-3574.86" - cell $and $and$ls180.v:3574$283 + attribute \src "ls180.v:3577.9-3577.86" + cell $and $and$ls180.v:3577$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252000,10 +254529,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3574$283_Y + connect \Y $and$ls180.v:3577$283_Y end - attribute \src "ls180.v:3586.9-3586.86" - cell $and $and$ls180.v:3586$284 + attribute \src "ls180.v:3589.9-3589.86" + cell $and $and$ls180.v:3589$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252011,10 +254540,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3586$284_Y + connect \Y $and$ls180.v:3589$284_Y end - attribute \src "ls180.v:3636.13-3636.87" - cell $and $and$ls180.v:3636$286 + attribute \src "ls180.v:3639.13-3639.87" + cell $and $and$ls180.v:3639$286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252022,10 +254551,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_ready connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3636$286_Y + connect \Y $and$ls180.v:3639$286_Y end - attribute \src "ls180.v:3672.50-3672.119" - cell $and $and$ls180.v:3672$293 + attribute \src "ls180.v:3675.50-3675.119" + cell $and $and$ls180.v:3675$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252033,21 +254562,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3672$293_Y + connect \Y $and$ls180.v:3675$293_Y end - attribute \src "ls180.v:3672.49-3672.167" - cell $and $and$ls180.v:3672$294 + attribute \src "ls180.v:3675.49-3675.167" + cell $and $and$ls180.v:3675$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3672$293_Y + connect \A $and$ls180.v:3675$293_Y connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3672$294_Y + connect \Y $and$ls180.v:3675$294_Y end - attribute \src "ls180.v:3673.49-3673.118" - cell $and $and$ls180.v:3673$295 + attribute \src "ls180.v:3676.49-3676.118" + cell $and $and$ls180.v:3676$295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252055,21 +254584,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3673$295_Y + connect \Y $and$ls180.v:3676$295_Y end - attribute \src "ls180.v:3673.48-3673.154" - cell $and $and$ls180.v:3673$296 + attribute \src "ls180.v:3676.48-3676.154" + cell $and $and$ls180.v:3676$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3673$295_Y + connect \A $and$ls180.v:3676$295_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3673$296_Y + connect \Y $and$ls180.v:3676$296_Y end - attribute \src "ls180.v:3674.50-3674.119" - cell $and $and$ls180.v:3674$297 + attribute \src "ls180.v:3677.50-3677.119" + cell $and $and$ls180.v:3677$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252077,21 +254606,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3674$297_Y + connect \Y $and$ls180.v:3677$297_Y end - attribute \src "ls180.v:3674.49-3674.155" - cell $and $and$ls180.v:3674$298 + attribute \src "ls180.v:3677.49-3677.155" + cell $and $and$ls180.v:3677$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3674$297_Y + connect \A $and$ls180.v:3677$297_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3674$298_Y + connect \Y $and$ls180.v:3677$298_Y end - attribute \src "ls180.v:3677.7-3677.114" - cell $and $and$ls180.v:3677$300 + attribute \src "ls180.v:3680.7-3680.114" + cell $and $and$ls180.v:3680$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252099,21 +254628,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3677$300_Y + connect \Y $and$ls180.v:3680$300_Y end - attribute \src "ls180.v:3706.66-3706.246" - cell $and $and$ls180.v:3706$306 + attribute \src "ls180.v:3709.66-3709.246" + cell $and $and$ls180.v:3709$306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3706$305_Y - connect \Y $and$ls180.v:3706$306_Y + connect \B $or$ls180.v:3709$305_Y + connect \Y $and$ls180.v:3709$306_Y end - attribute \src "ls180.v:3707.64-3707.187" - cell $and $and$ls180.v:3707$307 + attribute \src "ls180.v:3710.64-3710.187" + cell $and $and$ls180.v:3710$307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252121,10 +254650,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3707$307_Y + connect \Y $and$ls180.v:3710$307_Y end - attribute \src "ls180.v:3731.9-3731.86" - cell $and $and$ls180.v:3731$313 + attribute \src "ls180.v:3734.9-3734.86" + cell $and $and$ls180.v:3734$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252132,10 +254661,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3731$313_Y + connect \Y $and$ls180.v:3734$313_Y end - attribute \src "ls180.v:3743.9-3743.86" - cell $and $and$ls180.v:3743$314 + attribute \src "ls180.v:3746.9-3746.86" + cell $and $and$ls180.v:3746$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252143,10 +254672,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3743$314_Y + connect \Y $and$ls180.v:3746$314_Y end - attribute \src "ls180.v:3793.13-3793.87" - cell $and $and$ls180.v:3793$316 + attribute \src "ls180.v:3796.13-3796.87" + cell $and $and$ls180.v:3796$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252154,10 +254683,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_ready connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3793$316_Y + connect \Y $and$ls180.v:3796$316_Y end - attribute \src "ls180.v:3829.50-3829.119" - cell $and $and$ls180.v:3829$323 + attribute \src "ls180.v:3832.50-3832.119" + cell $and $and$ls180.v:3832$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252165,21 +254694,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3829$323_Y + connect \Y $and$ls180.v:3832$323_Y end - attribute \src "ls180.v:3829.49-3829.167" - cell $and $and$ls180.v:3829$324 + attribute \src "ls180.v:3832.49-3832.167" + cell $and $and$ls180.v:3832$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3829$323_Y + connect \A $and$ls180.v:3832$323_Y connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3829$324_Y + connect \Y $and$ls180.v:3832$324_Y end - attribute \src "ls180.v:3830.49-3830.118" - cell $and $and$ls180.v:3830$325 + attribute \src "ls180.v:3833.49-3833.118" + cell $and $and$ls180.v:3833$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252187,21 +254716,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3830$325_Y + connect \Y $and$ls180.v:3833$325_Y end - attribute \src "ls180.v:3830.48-3830.154" - cell $and $and$ls180.v:3830$326 + attribute \src "ls180.v:3833.48-3833.154" + cell $and $and$ls180.v:3833$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3830$325_Y + connect \A $and$ls180.v:3833$325_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3830$326_Y + connect \Y $and$ls180.v:3833$326_Y end - attribute \src "ls180.v:3831.50-3831.119" - cell $and $and$ls180.v:3831$327 + attribute \src "ls180.v:3834.50-3834.119" + cell $and $and$ls180.v:3834$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252209,21 +254738,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3831$327_Y + connect \Y $and$ls180.v:3834$327_Y end - attribute \src "ls180.v:3831.49-3831.155" - cell $and $and$ls180.v:3831$328 + attribute \src "ls180.v:3834.49-3834.155" + cell $and $and$ls180.v:3834$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3831$327_Y + connect \A $and$ls180.v:3834$327_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3831$328_Y + connect \Y $and$ls180.v:3834$328_Y end - attribute \src "ls180.v:3834.7-3834.114" - cell $and $and$ls180.v:3834$330 + attribute \src "ls180.v:3837.7-3837.114" + cell $and $and$ls180.v:3837$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252231,21 +254760,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3834$330_Y + connect \Y $and$ls180.v:3837$330_Y end - attribute \src "ls180.v:3863.66-3863.246" - cell $and $and$ls180.v:3863$336 + attribute \src "ls180.v:3866.66-3866.246" + cell $and $and$ls180.v:3866$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3863$335_Y - connect \Y $and$ls180.v:3863$336_Y + connect \B $or$ls180.v:3866$335_Y + connect \Y $and$ls180.v:3866$336_Y end - attribute \src "ls180.v:3864.64-3864.187" - cell $and $and$ls180.v:3864$337 + attribute \src "ls180.v:3867.64-3867.187" + cell $and $and$ls180.v:3867$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252253,10 +254782,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3864$337_Y + connect \Y $and$ls180.v:3867$337_Y end - attribute \src "ls180.v:3888.9-3888.86" - cell $and $and$ls180.v:3888$343 + attribute \src "ls180.v:3891.9-3891.86" + cell $and $and$ls180.v:3891$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252264,10 +254793,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3888$343_Y + connect \Y $and$ls180.v:3891$343_Y end - attribute \src "ls180.v:3900.9-3900.86" - cell $and $and$ls180.v:3900$344 + attribute \src "ls180.v:3903.9-3903.86" + cell $and $and$ls180.v:3903$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252275,10 +254804,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3900$344_Y + connect \Y $and$ls180.v:3903$344_Y end - attribute \src "ls180.v:3950.13-3950.87" - cell $and $and$ls180.v:3950$346 + attribute \src "ls180.v:3953.13-3953.87" + cell $and $and$ls180.v:3953$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252286,10 +254815,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_ready connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3950$346_Y + connect \Y $and$ls180.v:3953$346_Y end - attribute \src "ls180.v:3965.37-3965.102" - cell $and $and$ls180.v:3965$347 + attribute \src "ls180.v:3968.37-3968.102" + cell $and $and$ls180.v:3968$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252297,43 +254826,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3965$347_Y + connect \Y $and$ls180.v:3968$347_Y end - attribute \src "ls180.v:3965.108-3965.188" - cell $and $and$ls180.v:3965$349 + attribute \src "ls180.v:3968.108-3968.188" + cell $and $and$ls180.v:3968$349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3965$348_Y - connect \Y $and$ls180.v:3965$349_Y + connect \B $not$ls180.v:3968$348_Y + connect \Y $and$ls180.v:3968$349_Y end - attribute \src "ls180.v:3965.107-3965.231" - cell $and $and$ls180.v:3965$351 + attribute \src "ls180.v:3968.107-3968.231" + cell $and $and$ls180.v:3968$351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3965$349_Y - connect \B $not$ls180.v:3965$350_Y - connect \Y $and$ls180.v:3965$351_Y + connect \A $and$ls180.v:3968$349_Y + connect \B $not$ls180.v:3968$350_Y + connect \Y $and$ls180.v:3968$351_Y end - attribute \src "ls180.v:3965.36-3965.232" - cell $and $and$ls180.v:3965$352 + attribute \src "ls180.v:3968.36-3968.232" + cell $and $and$ls180.v:3968$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3965$347_Y - connect \B $and$ls180.v:3965$351_Y - connect \Y $and$ls180.v:3965$352_Y + connect \A $and$ls180.v:3968$347_Y + connect \B $and$ls180.v:3968$351_Y + connect \Y $and$ls180.v:3968$352_Y end - attribute \src "ls180.v:3966.37-3966.102" - cell $and $and$ls180.v:3966$353 + attribute \src "ls180.v:3969.37-3969.102" + cell $and $and$ls180.v:3969$353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252341,43 +254870,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3966$353_Y + connect \Y $and$ls180.v:3969$353_Y end - attribute \src "ls180.v:3966.108-3966.188" - cell $and $and$ls180.v:3966$355 + attribute \src "ls180.v:3969.108-3969.188" + cell $and $and$ls180.v:3969$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3966$354_Y - connect \Y $and$ls180.v:3966$355_Y + connect \B $not$ls180.v:3969$354_Y + connect \Y $and$ls180.v:3969$355_Y end - attribute \src "ls180.v:3966.107-3966.231" - cell $and $and$ls180.v:3966$357 + attribute \src "ls180.v:3969.107-3969.231" + cell $and $and$ls180.v:3969$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3966$355_Y - connect \B $not$ls180.v:3966$356_Y - connect \Y $and$ls180.v:3966$357_Y + connect \A $and$ls180.v:3969$355_Y + connect \B $not$ls180.v:3969$356_Y + connect \Y $and$ls180.v:3969$357_Y end - attribute \src "ls180.v:3966.36-3966.232" - cell $and $and$ls180.v:3966$358 + attribute \src "ls180.v:3969.36-3969.232" + cell $and $and$ls180.v:3969$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3966$353_Y - connect \B $and$ls180.v:3966$357_Y - connect \Y $and$ls180.v:3966$358_Y + connect \A $and$ls180.v:3969$353_Y + connect \B $and$ls180.v:3969$357_Y + connect \Y $and$ls180.v:3969$358_Y end - attribute \src "ls180.v:3967.34-3967.85" - cell $and $and$ls180.v:3967$359 + attribute \src "ls180.v:3970.34-3970.85" + cell $and $and$ls180.v:3970$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252385,10 +254914,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_trrdcon_ready connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3967$359_Y + connect \Y $and$ls180.v:3970$359_Y end - attribute \src "ls180.v:3968.37-3968.102" - cell $and $and$ls180.v:3968$360 + attribute \src "ls180.v:3971.37-3971.102" + cell $and $and$ls180.v:3971$360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252396,21 +254925,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3968$360_Y + connect \Y $and$ls180.v:3971$360_Y end - attribute \src "ls180.v:3968.36-3968.194" - cell $and $and$ls180.v:3968$362 + attribute \src "ls180.v:3971.36-3971.194" + cell $and $and$ls180.v:3971$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3968$360_Y - connect \B $or$ls180.v:3968$361_Y - connect \Y $and$ls180.v:3968$362_Y + connect \A $and$ls180.v:3971$360_Y + connect \B $or$ls180.v:3971$361_Y + connect \Y $and$ls180.v:3971$362_Y end - attribute \src "ls180.v:3970.37-3970.102" - cell $and $and$ls180.v:3970$363 + attribute \src "ls180.v:3973.37-3973.102" + cell $and $and$ls180.v:3973$363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252418,21 +254947,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3970$363_Y + connect \Y $and$ls180.v:3973$363_Y end - attribute \src "ls180.v:3970.36-3970.148" - cell $and $and$ls180.v:3970$364 + attribute \src "ls180.v:3973.36-3973.148" + cell $and $and$ls180.v:3973$364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3970$363_Y + connect \A $and$ls180.v:3973$363_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3970$364_Y + connect \Y $and$ls180.v:3973$364_Y end - attribute \src "ls180.v:3971.40-3971.119" - cell $and $and$ls180.v:3971$365 + attribute \src "ls180.v:3974.40-3974.119" + cell $and $and$ls180.v:3974$365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252440,10 +254969,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3971$365_Y + connect \Y $and$ls180.v:3974$365_Y end - attribute \src "ls180.v:3971.124-3971.203" - cell $and $and$ls180.v:3971$366 + attribute \src "ls180.v:3974.124-3974.203" + cell $and $and$ls180.v:3974$366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252451,10 +254980,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3971$366_Y + connect \Y $and$ls180.v:3974$366_Y end - attribute \src "ls180.v:3971.209-3971.288" - cell $and $and$ls180.v:3971$368 + attribute \src "ls180.v:3974.209-3974.288" + cell $and $and$ls180.v:3974$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252462,10 +254991,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3971$368_Y + connect \Y $and$ls180.v:3974$368_Y end - attribute \src "ls180.v:3971.294-3971.373" - cell $and $and$ls180.v:3971$370 + attribute \src "ls180.v:3974.294-3974.373" + cell $and $and$ls180.v:3974$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252473,10 +255002,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3971$370_Y + connect \Y $and$ls180.v:3974$370_Y end - attribute \src "ls180.v:3972.41-3972.121" - cell $and $and$ls180.v:3972$372 + attribute \src "ls180.v:3975.41-3975.121" + cell $and $and$ls180.v:3975$372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252484,10 +255013,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3972$372_Y + connect \Y $and$ls180.v:3975$372_Y end - attribute \src "ls180.v:3972.126-3972.206" - cell $and $and$ls180.v:3972$373 + attribute \src "ls180.v:3975.126-3975.206" + cell $and $and$ls180.v:3975$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252495,10 +255024,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3972$373_Y + connect \Y $and$ls180.v:3975$373_Y end - attribute \src "ls180.v:3972.212-3972.292" - cell $and $and$ls180.v:3972$375 + attribute \src "ls180.v:3975.212-3975.292" + cell $and $and$ls180.v:3975$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252506,10 +255035,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3972$375_Y + connect \Y $and$ls180.v:3975$375_Y end - attribute \src "ls180.v:3972.298-3972.378" - cell $and $and$ls180.v:3972$377 + attribute \src "ls180.v:3975.298-3975.378" + cell $and $and$ls180.v:3975$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252517,10 +255046,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3972$377_Y + connect \Y $and$ls180.v:3975$377_Y end - attribute \src "ls180.v:3979.38-3979.111" - cell $and $and$ls180.v:3979$381 + attribute \src "ls180.v:3982.38-3982.111" + cell $and $and$ls180.v:3982$381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252528,32 +255057,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_gnt connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3979$381_Y + connect \Y $and$ls180.v:3982$381_Y end - attribute \src "ls180.v:3979.37-3979.150" - cell $and $and$ls180.v:3979$382 + attribute \src "ls180.v:3982.37-3982.150" + cell $and $and$ls180.v:3982$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3979$381_Y + connect \A $and$ls180.v:3982$381_Y connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3979$382_Y + connect \Y $and$ls180.v:3982$382_Y end - attribute \src "ls180.v:3979.36-3979.189" - cell $and $and$ls180.v:3979$383 + attribute \src "ls180.v:3982.36-3982.189" + cell $and $and$ls180.v:3982$383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3979$382_Y + connect \A $and$ls180.v:3982$382_Y connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3979$383_Y + connect \Y $and$ls180.v:3982$383_Y end - attribute \src "ls180.v:3985.77-3985.153" - cell $and $and$ls180.v:3985$386 + attribute \src "ls180.v:3988.77-3988.153" + cell $and $and$ls180.v:3988$386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252561,65 +255090,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3985$386_Y + connect \Y $and$ls180.v:3988$386_Y end - attribute \src "ls180.v:3985.162-3985.246" - cell $and $and$ls180.v:3985$388 + attribute \src "ls180.v:3988.162-3988.246" + cell $and $and$ls180.v:3988$388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3985$387_Y - connect \Y $and$ls180.v:3985$388_Y + connect \B $not$ls180.v:3988$387_Y + connect \Y $and$ls180.v:3988$388_Y end - attribute \src "ls180.v:3985.161-3985.291" - cell $and $and$ls180.v:3985$390 + attribute \src "ls180.v:3988.161-3988.291" + cell $and $and$ls180.v:3988$390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$388_Y - connect \B $not$ls180.v:3985$389_Y - connect \Y $and$ls180.v:3985$390_Y + connect \A $and$ls180.v:3988$388_Y + connect \B $not$ls180.v:3988$389_Y + connect \Y $and$ls180.v:3988$390_Y end - attribute \src "ls180.v:3985.76-3985.333" - cell $and $and$ls180.v:3985$393 + attribute \src "ls180.v:3988.76-3988.333" + cell $and $and$ls180.v:3988$393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$386_Y - connect \B $or$ls180.v:3985$392_Y - connect \Y $and$ls180.v:3985$393_Y + connect \A $and$ls180.v:3988$386_Y + connect \B $or$ls180.v:3988$392_Y + connect \Y $and$ls180.v:3988$393_Y end - attribute \src "ls180.v:3985.338-3985.505" - cell $and $and$ls180.v:3985$396 + attribute \src "ls180.v:3988.338-3988.505" + cell $and $and$ls180.v:3988$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3985$394_Y - connect \B $eq$ls180.v:3985$395_Y - connect \Y $and$ls180.v:3985$396_Y + connect \A $eq$ls180.v:3988$394_Y + connect \B $eq$ls180.v:3988$395_Y + connect \Y $and$ls180.v:3988$396_Y end - attribute \src "ls180.v:3985.38-3985.507" - cell $and $and$ls180.v:3985$398 + attribute \src "ls180.v:3988.38-3988.507" + cell $and $and$ls180.v:3988$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3985$397_Y - connect \Y $and$ls180.v:3985$398_Y + connect \B $or$ls180.v:3988$397_Y + connect \Y $and$ls180.v:3988$398_Y end - attribute \src "ls180.v:3986.77-3986.153" - cell $and $and$ls180.v:3986$399 + attribute \src "ls180.v:3989.77-3989.153" + cell $and $and$ls180.v:3989$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252627,65 +255156,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3986$399_Y + connect \Y $and$ls180.v:3989$399_Y end - attribute \src "ls180.v:3986.162-3986.246" - cell $and $and$ls180.v:3986$401 + attribute \src "ls180.v:3989.162-3989.246" + cell $and $and$ls180.v:3989$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3986$400_Y - connect \Y $and$ls180.v:3986$401_Y + connect \B $not$ls180.v:3989$400_Y + connect \Y $and$ls180.v:3989$401_Y end - attribute \src "ls180.v:3986.161-3986.291" - cell $and $and$ls180.v:3986$403 + attribute \src "ls180.v:3989.161-3989.291" + cell $and $and$ls180.v:3989$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3986$401_Y - connect \B $not$ls180.v:3986$402_Y - connect \Y $and$ls180.v:3986$403_Y + connect \A $and$ls180.v:3989$401_Y + connect \B $not$ls180.v:3989$402_Y + connect \Y $and$ls180.v:3989$403_Y end - attribute \src "ls180.v:3986.76-3986.333" - cell $and $and$ls180.v:3986$406 + attribute \src "ls180.v:3989.76-3989.333" + cell $and $and$ls180.v:3989$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3986$399_Y - connect \B $or$ls180.v:3986$405_Y - connect \Y $and$ls180.v:3986$406_Y + connect \A $and$ls180.v:3989$399_Y + connect \B $or$ls180.v:3989$405_Y + connect \Y $and$ls180.v:3989$406_Y end - attribute \src "ls180.v:3986.338-3986.505" - cell $and $and$ls180.v:3986$409 + attribute \src "ls180.v:3989.338-3989.505" + cell $and $and$ls180.v:3989$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3986$407_Y - connect \B $eq$ls180.v:3986$408_Y - connect \Y $and$ls180.v:3986$409_Y + connect \A $eq$ls180.v:3989$407_Y + connect \B $eq$ls180.v:3989$408_Y + connect \Y $and$ls180.v:3989$409_Y end - attribute \src "ls180.v:3986.38-3986.507" - cell $and $and$ls180.v:3986$411 + attribute \src "ls180.v:3989.38-3989.507" + cell $and $and$ls180.v:3989$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3986$410_Y - connect \Y $and$ls180.v:3986$411_Y + connect \B $or$ls180.v:3989$410_Y + connect \Y $and$ls180.v:3989$411_Y end - attribute \src "ls180.v:3987.77-3987.153" - cell $and $and$ls180.v:3987$412 + attribute \src "ls180.v:3990.77-3990.153" + cell $and $and$ls180.v:3990$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252693,65 +255222,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3987$412_Y + connect \Y $and$ls180.v:3990$412_Y end - attribute \src "ls180.v:3987.162-3987.246" - cell $and $and$ls180.v:3987$414 + attribute \src "ls180.v:3990.162-3990.246" + cell $and $and$ls180.v:3990$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3987$413_Y - connect \Y $and$ls180.v:3987$414_Y + connect \B $not$ls180.v:3990$413_Y + connect \Y $and$ls180.v:3990$414_Y end - attribute \src "ls180.v:3987.161-3987.291" - cell $and $and$ls180.v:3987$416 + attribute \src "ls180.v:3990.161-3990.291" + cell $and $and$ls180.v:3990$416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3987$414_Y - connect \B $not$ls180.v:3987$415_Y - connect \Y $and$ls180.v:3987$416_Y + connect \A $and$ls180.v:3990$414_Y + connect \B $not$ls180.v:3990$415_Y + connect \Y $and$ls180.v:3990$416_Y end - attribute \src "ls180.v:3987.76-3987.333" - cell $and $and$ls180.v:3987$419 + attribute \src "ls180.v:3990.76-3990.333" + cell $and $and$ls180.v:3990$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3987$412_Y - connect \B $or$ls180.v:3987$418_Y - connect \Y $and$ls180.v:3987$419_Y + connect \A $and$ls180.v:3990$412_Y + connect \B $or$ls180.v:3990$418_Y + connect \Y $and$ls180.v:3990$419_Y end - attribute \src "ls180.v:3987.338-3987.505" - cell $and $and$ls180.v:3987$422 + attribute \src "ls180.v:3990.338-3990.505" + cell $and $and$ls180.v:3990$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3987$420_Y - connect \B $eq$ls180.v:3987$421_Y - connect \Y $and$ls180.v:3987$422_Y + connect \A $eq$ls180.v:3990$420_Y + connect \B $eq$ls180.v:3990$421_Y + connect \Y $and$ls180.v:3990$422_Y end - attribute \src "ls180.v:3987.38-3987.507" - cell $and $and$ls180.v:3987$424 + attribute \src "ls180.v:3990.38-3990.507" + cell $and $and$ls180.v:3990$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3987$423_Y - connect \Y $and$ls180.v:3987$424_Y + connect \B $or$ls180.v:3990$423_Y + connect \Y $and$ls180.v:3990$424_Y end - attribute \src "ls180.v:3988.77-3988.153" - cell $and $and$ls180.v:3988$425 + attribute \src "ls180.v:3991.77-3991.153" + cell $and $and$ls180.v:3991$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252759,65 +255288,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3988$425_Y + connect \Y $and$ls180.v:3991$425_Y end - attribute \src "ls180.v:3988.162-3988.246" - cell $and $and$ls180.v:3988$427 + attribute \src "ls180.v:3991.162-3991.246" + cell $and $and$ls180.v:3991$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3988$426_Y - connect \Y $and$ls180.v:3988$427_Y + connect \B $not$ls180.v:3991$426_Y + connect \Y $and$ls180.v:3991$427_Y end - attribute \src "ls180.v:3988.161-3988.291" - cell $and $and$ls180.v:3988$429 + attribute \src "ls180.v:3991.161-3991.291" + cell $and $and$ls180.v:3991$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$427_Y - connect \B $not$ls180.v:3988$428_Y - connect \Y $and$ls180.v:3988$429_Y + connect \A $and$ls180.v:3991$427_Y + connect \B $not$ls180.v:3991$428_Y + connect \Y $and$ls180.v:3991$429_Y end - attribute \src "ls180.v:3988.76-3988.333" - cell $and $and$ls180.v:3988$432 + attribute \src "ls180.v:3991.76-3991.333" + cell $and $and$ls180.v:3991$432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$425_Y - connect \B $or$ls180.v:3988$431_Y - connect \Y $and$ls180.v:3988$432_Y + connect \A $and$ls180.v:3991$425_Y + connect \B $or$ls180.v:3991$431_Y + connect \Y $and$ls180.v:3991$432_Y end - attribute \src "ls180.v:3988.338-3988.505" - cell $and $and$ls180.v:3988$435 + attribute \src "ls180.v:3991.338-3991.505" + cell $and $and$ls180.v:3991$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$433_Y - connect \B $eq$ls180.v:3988$434_Y - connect \Y $and$ls180.v:3988$435_Y + connect \A $eq$ls180.v:3991$433_Y + connect \B $eq$ls180.v:3991$434_Y + connect \Y $and$ls180.v:3991$435_Y end - attribute \src "ls180.v:3988.38-3988.507" - cell $and $and$ls180.v:3988$437 + attribute \src "ls180.v:3991.38-3991.507" + cell $and $and$ls180.v:3991$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3988$436_Y - connect \Y $and$ls180.v:3988$437_Y + connect \B $or$ls180.v:3991$436_Y + connect \Y $and$ls180.v:3991$437_Y end - attribute \src "ls180.v:4018.77-4018.153" - cell $and $and$ls180.v:4018$444 + attribute \src "ls180.v:4021.77-4021.153" + cell $and $and$ls180.v:4021$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252825,65 +255354,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4018$444_Y + connect \Y $and$ls180.v:4021$444_Y end - attribute \src "ls180.v:4018.162-4018.246" - cell $and $and$ls180.v:4018$446 + attribute \src "ls180.v:4021.162-4021.246" + cell $and $and$ls180.v:4021$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:4018$445_Y - connect \Y $and$ls180.v:4018$446_Y + connect \B $not$ls180.v:4021$445_Y + connect \Y $and$ls180.v:4021$446_Y end - attribute \src "ls180.v:4018.161-4018.291" - cell $and $and$ls180.v:4018$448 + attribute \src "ls180.v:4021.161-4021.291" + cell $and $and$ls180.v:4021$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4018$446_Y - connect \B $not$ls180.v:4018$447_Y - connect \Y $and$ls180.v:4018$448_Y + connect \A $and$ls180.v:4021$446_Y + connect \B $not$ls180.v:4021$447_Y + connect \Y $and$ls180.v:4021$448_Y end - attribute \src "ls180.v:4018.76-4018.333" - cell $and $and$ls180.v:4018$451 + attribute \src "ls180.v:4021.76-4021.333" + cell $and $and$ls180.v:4021$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4018$444_Y - connect \B $or$ls180.v:4018$450_Y - connect \Y $and$ls180.v:4018$451_Y + connect \A $and$ls180.v:4021$444_Y + connect \B $or$ls180.v:4021$450_Y + connect \Y $and$ls180.v:4021$451_Y end - attribute \src "ls180.v:4018.338-4018.505" - cell $and $and$ls180.v:4018$454 + attribute \src "ls180.v:4021.338-4021.505" + cell $and $and$ls180.v:4021$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4018$452_Y - connect \B $eq$ls180.v:4018$453_Y - connect \Y $and$ls180.v:4018$454_Y + connect \A $eq$ls180.v:4021$452_Y + connect \B $eq$ls180.v:4021$453_Y + connect \Y $and$ls180.v:4021$454_Y end - attribute \src "ls180.v:4018.38-4018.507" - cell $and $and$ls180.v:4018$456 + attribute \src "ls180.v:4021.38-4021.507" + cell $and $and$ls180.v:4021$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:4018$455_Y - connect \Y $and$ls180.v:4018$456_Y + connect \B $or$ls180.v:4021$455_Y + connect \Y $and$ls180.v:4021$456_Y end - attribute \src "ls180.v:4019.77-4019.153" - cell $and $and$ls180.v:4019$457 + attribute \src "ls180.v:4022.77-4022.153" + cell $and $and$ls180.v:4022$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252891,65 +255420,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4019$457_Y + connect \Y $and$ls180.v:4022$457_Y end - attribute \src "ls180.v:4019.162-4019.246" - cell $and $and$ls180.v:4019$459 + attribute \src "ls180.v:4022.162-4022.246" + cell $and $and$ls180.v:4022$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:4019$458_Y - connect \Y $and$ls180.v:4019$459_Y + connect \B $not$ls180.v:4022$458_Y + connect \Y $and$ls180.v:4022$459_Y end - attribute \src "ls180.v:4019.161-4019.291" - cell $and $and$ls180.v:4019$461 + attribute \src "ls180.v:4022.161-4022.291" + cell $and $and$ls180.v:4022$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4019$459_Y - connect \B $not$ls180.v:4019$460_Y - connect \Y $and$ls180.v:4019$461_Y + connect \A $and$ls180.v:4022$459_Y + connect \B $not$ls180.v:4022$460_Y + connect \Y $and$ls180.v:4022$461_Y end - attribute \src "ls180.v:4019.76-4019.333" - cell $and $and$ls180.v:4019$464 + attribute \src "ls180.v:4022.76-4022.333" + cell $and $and$ls180.v:4022$464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4019$457_Y - connect \B $or$ls180.v:4019$463_Y - connect \Y $and$ls180.v:4019$464_Y + connect \A $and$ls180.v:4022$457_Y + connect \B $or$ls180.v:4022$463_Y + connect \Y $and$ls180.v:4022$464_Y end - attribute \src "ls180.v:4019.338-4019.505" - cell $and $and$ls180.v:4019$467 + attribute \src "ls180.v:4022.338-4022.505" + cell $and $and$ls180.v:4022$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4019$465_Y - connect \B $eq$ls180.v:4019$466_Y - connect \Y $and$ls180.v:4019$467_Y + connect \A $eq$ls180.v:4022$465_Y + connect \B $eq$ls180.v:4022$466_Y + connect \Y $and$ls180.v:4022$467_Y end - attribute \src "ls180.v:4019.38-4019.507" - cell $and $and$ls180.v:4019$469 + attribute \src "ls180.v:4022.38-4022.507" + cell $and $and$ls180.v:4022$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:4019$468_Y - connect \Y $and$ls180.v:4019$469_Y + connect \B $or$ls180.v:4022$468_Y + connect \Y $and$ls180.v:4022$469_Y end - attribute \src "ls180.v:4020.77-4020.153" - cell $and $and$ls180.v:4020$470 + attribute \src "ls180.v:4023.77-4023.153" + cell $and $and$ls180.v:4023$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252957,65 +255486,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4020$470_Y + connect \Y $and$ls180.v:4023$470_Y end - attribute \src "ls180.v:4020.162-4020.246" - cell $and $and$ls180.v:4020$472 + attribute \src "ls180.v:4023.162-4023.246" + cell $and $and$ls180.v:4023$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:4020$471_Y - connect \Y $and$ls180.v:4020$472_Y + connect \B $not$ls180.v:4023$471_Y + connect \Y $and$ls180.v:4023$472_Y end - attribute \src "ls180.v:4020.161-4020.291" - cell $and $and$ls180.v:4020$474 + attribute \src "ls180.v:4023.161-4023.291" + cell $and $and$ls180.v:4023$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4020$472_Y - connect \B $not$ls180.v:4020$473_Y - connect \Y $and$ls180.v:4020$474_Y + connect \A $and$ls180.v:4023$472_Y + connect \B $not$ls180.v:4023$473_Y + connect \Y $and$ls180.v:4023$474_Y end - attribute \src "ls180.v:4020.76-4020.333" - cell $and $and$ls180.v:4020$477 + attribute \src "ls180.v:4023.76-4023.333" + cell $and $and$ls180.v:4023$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4020$470_Y - connect \B $or$ls180.v:4020$476_Y - connect \Y $and$ls180.v:4020$477_Y + connect \A $and$ls180.v:4023$470_Y + connect \B $or$ls180.v:4023$476_Y + connect \Y $and$ls180.v:4023$477_Y end - attribute \src "ls180.v:4020.338-4020.505" - cell $and $and$ls180.v:4020$480 + attribute \src "ls180.v:4023.338-4023.505" + cell $and $and$ls180.v:4023$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4020$478_Y - connect \B $eq$ls180.v:4020$479_Y - connect \Y $and$ls180.v:4020$480_Y + connect \A $eq$ls180.v:4023$478_Y + connect \B $eq$ls180.v:4023$479_Y + connect \Y $and$ls180.v:4023$480_Y end - attribute \src "ls180.v:4020.38-4020.507" - cell $and $and$ls180.v:4020$482 + attribute \src "ls180.v:4023.38-4023.507" + cell $and $and$ls180.v:4023$482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:4020$481_Y - connect \Y $and$ls180.v:4020$482_Y + connect \B $or$ls180.v:4023$481_Y + connect \Y $and$ls180.v:4023$482_Y end - attribute \src "ls180.v:4021.77-4021.153" - cell $and $and$ls180.v:4021$483 + attribute \src "ls180.v:4024.77-4024.153" + cell $and $and$ls180.v:4024$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253023,65 +255552,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4021$483_Y + connect \Y $and$ls180.v:4024$483_Y end - attribute \src "ls180.v:4021.162-4021.246" - cell $and $and$ls180.v:4021$485 + attribute \src "ls180.v:4024.162-4024.246" + cell $and $and$ls180.v:4024$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:4021$484_Y - connect \Y $and$ls180.v:4021$485_Y + connect \B $not$ls180.v:4024$484_Y + connect \Y $and$ls180.v:4024$485_Y end - attribute \src "ls180.v:4021.161-4021.291" - cell $and $and$ls180.v:4021$487 + attribute \src "ls180.v:4024.161-4024.291" + cell $and $and$ls180.v:4024$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$485_Y - connect \B $not$ls180.v:4021$486_Y - connect \Y $and$ls180.v:4021$487_Y + connect \A $and$ls180.v:4024$485_Y + connect \B $not$ls180.v:4024$486_Y + connect \Y $and$ls180.v:4024$487_Y end - attribute \src "ls180.v:4021.76-4021.333" - cell $and $and$ls180.v:4021$490 + attribute \src "ls180.v:4024.76-4024.333" + cell $and $and$ls180.v:4024$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$483_Y - connect \B $or$ls180.v:4021$489_Y - connect \Y $and$ls180.v:4021$490_Y + connect \A $and$ls180.v:4024$483_Y + connect \B $or$ls180.v:4024$489_Y + connect \Y $and$ls180.v:4024$490_Y end - attribute \src "ls180.v:4021.338-4021.505" - cell $and $and$ls180.v:4021$493 + attribute \src "ls180.v:4024.338-4024.505" + cell $and $and$ls180.v:4024$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4021$491_Y - connect \B $eq$ls180.v:4021$492_Y - connect \Y $and$ls180.v:4021$493_Y + connect \A $eq$ls180.v:4024$491_Y + connect \B $eq$ls180.v:4024$492_Y + connect \Y $and$ls180.v:4024$493_Y end - attribute \src "ls180.v:4021.38-4021.507" - cell $and $and$ls180.v:4021$495 + attribute \src "ls180.v:4024.38-4024.507" + cell $and $and$ls180.v:4024$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:4021$494_Y - connect \Y $and$ls180.v:4021$495_Y + connect \B $or$ls180.v:4024$494_Y + connect \Y $and$ls180.v:4024$495_Y end - attribute \src "ls180.v:4050.8-4050.73" - cell $and $and$ls180.v:4050$500 + attribute \src "ls180.v:4053.8-4053.73" + cell $and $and$ls180.v:4053$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253089,21 +255618,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4050$500_Y + connect \Y $and$ls180.v:4053$500_Y end - attribute \src "ls180.v:4050.7-4050.114" - cell $and $and$ls180.v:4050$502 + attribute \src "ls180.v:4053.7-4053.114" + cell $and $and$ls180.v:4053$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4050$500_Y - connect \B $eq$ls180.v:4050$501_Y - connect \Y $and$ls180.v:4050$502_Y + connect \A $and$ls180.v:4053$500_Y + connect \B $eq$ls180.v:4053$501_Y + connect \Y $and$ls180.v:4053$502_Y end - attribute \src "ls180.v:4053.8-4053.73" - cell $and $and$ls180.v:4053$503 + attribute \src "ls180.v:4056.8-4056.73" + cell $and $and$ls180.v:4056$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253111,21 +255640,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4053$503_Y + connect \Y $and$ls180.v:4056$503_Y end - attribute \src "ls180.v:4053.7-4053.114" - cell $and $and$ls180.v:4053$505 + attribute \src "ls180.v:4056.7-4056.114" + cell $and $and$ls180.v:4056$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$503_Y - connect \B $eq$ls180.v:4053$504_Y - connect \Y $and$ls180.v:4053$505_Y + connect \A $and$ls180.v:4056$503_Y + connect \B $eq$ls180.v:4056$504_Y + connect \Y $and$ls180.v:4056$505_Y end - attribute \src "ls180.v:4059.8-4059.73" - cell $and $and$ls180.v:4059$507 + attribute \src "ls180.v:4062.8-4062.73" + cell $and $and$ls180.v:4062$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253133,21 +255662,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4059$507_Y + connect \Y $and$ls180.v:4062$507_Y end - attribute \src "ls180.v:4059.7-4059.114" - cell $and $and$ls180.v:4059$509 + attribute \src "ls180.v:4062.7-4062.114" + cell $and $and$ls180.v:4062$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4059$507_Y - connect \B $eq$ls180.v:4059$508_Y - connect \Y $and$ls180.v:4059$509_Y + connect \A $and$ls180.v:4062$507_Y + connect \B $eq$ls180.v:4062$508_Y + connect \Y $and$ls180.v:4062$509_Y end - attribute \src "ls180.v:4062.8-4062.73" - cell $and $and$ls180.v:4062$510 + attribute \src "ls180.v:4065.8-4065.73" + cell $and $and$ls180.v:4065$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253155,21 +255684,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4062$510_Y + connect \Y $and$ls180.v:4065$510_Y end - attribute \src "ls180.v:4062.7-4062.114" - cell $and $and$ls180.v:4062$512 + attribute \src "ls180.v:4065.7-4065.114" + cell $and $and$ls180.v:4065$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4062$510_Y - connect \B $eq$ls180.v:4062$511_Y - connect \Y $and$ls180.v:4062$512_Y + connect \A $and$ls180.v:4065$510_Y + connect \B $eq$ls180.v:4065$511_Y + connect \Y $and$ls180.v:4065$512_Y end - attribute \src "ls180.v:4068.8-4068.73" - cell $and $and$ls180.v:4068$514 + attribute \src "ls180.v:4071.8-4071.73" + cell $and $and$ls180.v:4071$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253177,21 +255706,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4068$514_Y + connect \Y $and$ls180.v:4071$514_Y end - attribute \src "ls180.v:4068.7-4068.114" - cell $and $and$ls180.v:4068$516 + attribute \src "ls180.v:4071.7-4071.114" + cell $and $and$ls180.v:4071$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4068$514_Y - connect \B $eq$ls180.v:4068$515_Y - connect \Y $and$ls180.v:4068$516_Y + connect \A $and$ls180.v:4071$514_Y + connect \B $eq$ls180.v:4071$515_Y + connect \Y $and$ls180.v:4071$516_Y end - attribute \src "ls180.v:4071.8-4071.73" - cell $and $and$ls180.v:4071$517 + attribute \src "ls180.v:4074.8-4074.73" + cell $and $and$ls180.v:4074$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253199,21 +255728,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4071$517_Y + connect \Y $and$ls180.v:4074$517_Y end - attribute \src "ls180.v:4071.7-4071.114" - cell $and $and$ls180.v:4071$519 + attribute \src "ls180.v:4074.7-4074.114" + cell $and $and$ls180.v:4074$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4071$517_Y - connect \B $eq$ls180.v:4071$518_Y - connect \Y $and$ls180.v:4071$519_Y + connect \A $and$ls180.v:4074$517_Y + connect \B $eq$ls180.v:4074$518_Y + connect \Y $and$ls180.v:4074$519_Y end - attribute \src "ls180.v:4077.8-4077.73" - cell $and $and$ls180.v:4077$521 + attribute \src "ls180.v:4080.8-4080.73" + cell $and $and$ls180.v:4080$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253221,21 +255750,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4077$521_Y + connect \Y $and$ls180.v:4080$521_Y end - attribute \src "ls180.v:4077.7-4077.114" - cell $and $and$ls180.v:4077$523 + attribute \src "ls180.v:4080.7-4080.114" + cell $and $and$ls180.v:4080$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4077$521_Y - connect \B $eq$ls180.v:4077$522_Y - connect \Y $and$ls180.v:4077$523_Y + connect \A $and$ls180.v:4080$521_Y + connect \B $eq$ls180.v:4080$522_Y + connect \Y $and$ls180.v:4080$523_Y end - attribute \src "ls180.v:4080.8-4080.73" - cell $and $and$ls180.v:4080$524 + attribute \src "ls180.v:4083.8-4083.73" + cell $and $and$ls180.v:4083$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253243,615 +255772,615 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4080$524_Y + connect \Y $and$ls180.v:4083$524_Y end - attribute \src "ls180.v:4080.7-4080.114" - cell $and $and$ls180.v:4080$526 + attribute \src "ls180.v:4083.7-4083.114" + cell $and $and$ls180.v:4083$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4080$524_Y - connect \B $eq$ls180.v:4080$525_Y - connect \Y $and$ls180.v:4080$526_Y + connect \A $and$ls180.v:4083$524_Y + connect \B $eq$ls180.v:4083$525_Y + connect \Y $and$ls180.v:4083$526_Y end - attribute \src "ls180.v:4105.71-4105.151" - cell $and $and$ls180.v:4105$531 + attribute \src "ls180.v:4108.71-4108.151" + cell $and $and$ls180.v:4108$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4105$530_Y - connect \Y $and$ls180.v:4105$531_Y + connect \B $not$ls180.v:4108$530_Y + connect \Y $and$ls180.v:4108$531_Y end - attribute \src "ls180.v:4105.70-4105.194" - cell $and $and$ls180.v:4105$533 + attribute \src "ls180.v:4108.70-4108.194" + cell $and $and$ls180.v:4108$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4105$531_Y - connect \B $not$ls180.v:4105$532_Y - connect \Y $and$ls180.v:4105$533_Y + connect \A $and$ls180.v:4108$531_Y + connect \B $not$ls180.v:4108$532_Y + connect \Y $and$ls180.v:4108$533_Y end - attribute \src "ls180.v:4105.41-4105.222" - cell $and $and$ls180.v:4105$536 + attribute \src "ls180.v:4108.41-4108.222" + cell $and $and$ls180.v:4108$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4105$535_Y - connect \Y $and$ls180.v:4105$536_Y + connect \B $or$ls180.v:4108$535_Y + connect \Y $and$ls180.v:4108$536_Y end - attribute \src "ls180.v:4143.71-4143.151" - cell $and $and$ls180.v:4143$540 + attribute \src "ls180.v:4146.71-4146.151" + cell $and $and$ls180.v:4146$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4143$539_Y - connect \Y $and$ls180.v:4143$540_Y + connect \B $not$ls180.v:4146$539_Y + connect \Y $and$ls180.v:4146$540_Y end - attribute \src "ls180.v:4143.70-4143.194" - cell $and $and$ls180.v:4143$542 + attribute \src "ls180.v:4146.70-4146.194" + cell $and $and$ls180.v:4146$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4143$540_Y - connect \B $not$ls180.v:4143$541_Y - connect \Y $and$ls180.v:4143$542_Y + connect \A $and$ls180.v:4146$540_Y + connect \B $not$ls180.v:4146$541_Y + connect \Y $and$ls180.v:4146$542_Y end - attribute \src "ls180.v:4143.41-4143.222" - cell $and $and$ls180.v:4143$545 + attribute \src "ls180.v:4146.41-4146.222" + cell $and $and$ls180.v:4146$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4143$544_Y - connect \Y $and$ls180.v:4143$545_Y + connect \B $or$ls180.v:4146$544_Y + connect \Y $and$ls180.v:4146$545_Y end - attribute \src "ls180.v:4161.110-4161.179" - cell $and $and$ls180.v:4161$550 + attribute \src "ls180.v:4164.110-4164.179" + cell $and $and$ls180.v:4164$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4161$549_Y - connect \Y $and$ls180.v:4161$550_Y + connect \B $eq$ls180.v:4164$549_Y + connect \Y $and$ls180.v:4164$550_Y end - attribute \src "ls180.v:4161.185-4161.254" - cell $and $and$ls180.v:4161$553 + attribute \src "ls180.v:4164.185-4164.254" + cell $and $and$ls180.v:4164$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4161$552_Y - connect \Y $and$ls180.v:4161$553_Y + connect \B $eq$ls180.v:4164$552_Y + connect \Y $and$ls180.v:4164$553_Y end - attribute \src "ls180.v:4161.260-4161.329" - cell $and $and$ls180.v:4161$556 + attribute \src "ls180.v:4164.260-4164.329" + cell $and $and$ls180.v:4164$556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4161$555_Y - connect \Y $and$ls180.v:4161$556_Y + connect \B $eq$ls180.v:4164$555_Y + connect \Y $and$ls180.v:4164$556_Y end - attribute \src "ls180.v:4161.41-4161.332" - cell $and $and$ls180.v:4161$559 + attribute \src "ls180.v:4164.41-4164.332" + cell $and $and$ls180.v:4164$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4161$548_Y - connect \B $not$ls180.v:4161$558_Y - connect \Y $and$ls180.v:4161$559_Y + connect \A $eq$ls180.v:4164$548_Y + connect \B $not$ls180.v:4164$558_Y + connect \Y $and$ls180.v:4164$559_Y end - attribute \src "ls180.v:4161.40-4161.355" - cell $and $and$ls180.v:4161$560 + attribute \src "ls180.v:4164.40-4164.355" + cell $and $and$ls180.v:4164$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4161$559_Y + connect \A $and$ls180.v:4164$559_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4161$560_Y + connect \Y $and$ls180.v:4164$560_Y end - attribute \src "ls180.v:4162.34-4162.106" - cell $and $and$ls180.v:4162$563 + attribute \src "ls180.v:4165.34-4165.106" + cell $and $and$ls180.v:4165$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4162$561_Y - connect \B $not$ls180.v:4162$562_Y - connect \Y $and$ls180.v:4162$563_Y + connect \A $not$ls180.v:4165$561_Y + connect \B $not$ls180.v:4165$562_Y + connect \Y $and$ls180.v:4165$563_Y end - attribute \src "ls180.v:4166.110-4166.179" - cell $and $and$ls180.v:4166$566 + attribute \src "ls180.v:4169.110-4169.179" + cell $and $and$ls180.v:4169$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4166$565_Y - connect \Y $and$ls180.v:4166$566_Y + connect \B $eq$ls180.v:4169$565_Y + connect \Y $and$ls180.v:4169$566_Y end - attribute \src "ls180.v:4166.185-4166.254" - cell $and $and$ls180.v:4166$569 + attribute \src "ls180.v:4169.185-4169.254" + cell $and $and$ls180.v:4169$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4166$568_Y - connect \Y $and$ls180.v:4166$569_Y + connect \B $eq$ls180.v:4169$568_Y + connect \Y $and$ls180.v:4169$569_Y end - attribute \src "ls180.v:4166.260-4166.329" - cell $and $and$ls180.v:4166$572 + attribute \src "ls180.v:4169.260-4169.329" + cell $and $and$ls180.v:4169$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4166$571_Y - connect \Y $and$ls180.v:4166$572_Y + connect \B $eq$ls180.v:4169$571_Y + connect \Y $and$ls180.v:4169$572_Y end - attribute \src "ls180.v:4166.41-4166.332" - cell $and $and$ls180.v:4166$575 + attribute \src "ls180.v:4169.41-4169.332" + cell $and $and$ls180.v:4169$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4166$564_Y - connect \B $not$ls180.v:4166$574_Y - connect \Y $and$ls180.v:4166$575_Y + connect \A $eq$ls180.v:4169$564_Y + connect \B $not$ls180.v:4169$574_Y + connect \Y $and$ls180.v:4169$575_Y end - attribute \src "ls180.v:4166.40-4166.355" - cell $and $and$ls180.v:4166$576 + attribute \src "ls180.v:4169.40-4169.355" + cell $and $and$ls180.v:4169$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4166$575_Y + connect \A $and$ls180.v:4169$575_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4166$576_Y + connect \Y $and$ls180.v:4169$576_Y end - attribute \src "ls180.v:4167.34-4167.106" - cell $and $and$ls180.v:4167$579 + attribute \src "ls180.v:4170.34-4170.106" + cell $and $and$ls180.v:4170$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4167$577_Y - connect \B $not$ls180.v:4167$578_Y - connect \Y $and$ls180.v:4167$579_Y + connect \A $not$ls180.v:4170$577_Y + connect \B $not$ls180.v:4170$578_Y + connect \Y $and$ls180.v:4170$579_Y end - attribute \src "ls180.v:4171.110-4171.179" - cell $and $and$ls180.v:4171$582 + attribute \src "ls180.v:4174.110-4174.179" + cell $and $and$ls180.v:4174$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4171$581_Y - connect \Y $and$ls180.v:4171$582_Y + connect \B $eq$ls180.v:4174$581_Y + connect \Y $and$ls180.v:4174$582_Y end - attribute \src "ls180.v:4171.185-4171.254" - cell $and $and$ls180.v:4171$585 + attribute \src "ls180.v:4174.185-4174.254" + cell $and $and$ls180.v:4174$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4171$584_Y - connect \Y $and$ls180.v:4171$585_Y + connect \B $eq$ls180.v:4174$584_Y + connect \Y $and$ls180.v:4174$585_Y end - attribute \src "ls180.v:4171.260-4171.329" - cell $and $and$ls180.v:4171$588 + attribute \src "ls180.v:4174.260-4174.329" + cell $and $and$ls180.v:4174$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4171$587_Y - connect \Y $and$ls180.v:4171$588_Y + connect \B $eq$ls180.v:4174$587_Y + connect \Y $and$ls180.v:4174$588_Y end - attribute \src "ls180.v:4171.41-4171.332" - cell $and $and$ls180.v:4171$591 + attribute \src "ls180.v:4174.41-4174.332" + cell $and $and$ls180.v:4174$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4171$580_Y - connect \B $not$ls180.v:4171$590_Y - connect \Y $and$ls180.v:4171$591_Y + connect \A $eq$ls180.v:4174$580_Y + connect \B $not$ls180.v:4174$590_Y + connect \Y $and$ls180.v:4174$591_Y end - attribute \src "ls180.v:4171.40-4171.355" - cell $and $and$ls180.v:4171$592 + attribute \src "ls180.v:4174.40-4174.355" + cell $and $and$ls180.v:4174$592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4171$591_Y + connect \A $and$ls180.v:4174$591_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4171$592_Y + connect \Y $and$ls180.v:4174$592_Y end - attribute \src "ls180.v:4172.34-4172.106" - cell $and $and$ls180.v:4172$595 + attribute \src "ls180.v:4175.34-4175.106" + cell $and $and$ls180.v:4175$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4172$593_Y - connect \B $not$ls180.v:4172$594_Y - connect \Y $and$ls180.v:4172$595_Y + connect \A $not$ls180.v:4175$593_Y + connect \B $not$ls180.v:4175$594_Y + connect \Y $and$ls180.v:4175$595_Y end - attribute \src "ls180.v:4176.110-4176.179" - cell $and $and$ls180.v:4176$598 + attribute \src "ls180.v:4179.110-4179.179" + cell $and $and$ls180.v:4179$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4176$597_Y - connect \Y $and$ls180.v:4176$598_Y + connect \B $eq$ls180.v:4179$597_Y + connect \Y $and$ls180.v:4179$598_Y end - attribute \src "ls180.v:4176.185-4176.254" - cell $and $and$ls180.v:4176$601 + attribute \src "ls180.v:4179.185-4179.254" + cell $and $and$ls180.v:4179$601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4176$600_Y - connect \Y $and$ls180.v:4176$601_Y + connect \B $eq$ls180.v:4179$600_Y + connect \Y $and$ls180.v:4179$601_Y end - attribute \src "ls180.v:4176.260-4176.329" - cell $and $and$ls180.v:4176$604 + attribute \src "ls180.v:4179.260-4179.329" + cell $and $and$ls180.v:4179$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4176$603_Y - connect \Y $and$ls180.v:4176$604_Y + connect \B $eq$ls180.v:4179$603_Y + connect \Y $and$ls180.v:4179$604_Y end - attribute \src "ls180.v:4176.41-4176.332" - cell $and $and$ls180.v:4176$607 + attribute \src "ls180.v:4179.41-4179.332" + cell $and $and$ls180.v:4179$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4176$596_Y - connect \B $not$ls180.v:4176$606_Y - connect \Y $and$ls180.v:4176$607_Y + connect \A $eq$ls180.v:4179$596_Y + connect \B $not$ls180.v:4179$606_Y + connect \Y $and$ls180.v:4179$607_Y end - attribute \src "ls180.v:4176.40-4176.355" - cell $and $and$ls180.v:4176$608 + attribute \src "ls180.v:4179.40-4179.355" + cell $and $and$ls180.v:4179$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4176$607_Y + connect \A $and$ls180.v:4179$607_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4176$608_Y + connect \Y $and$ls180.v:4179$608_Y end - attribute \src "ls180.v:4177.34-4177.106" - cell $and $and$ls180.v:4177$611 + attribute \src "ls180.v:4180.34-4180.106" + cell $and $and$ls180.v:4180$611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4177$609_Y - connect \B $not$ls180.v:4177$610_Y - connect \Y $and$ls180.v:4177$611_Y + connect \A $not$ls180.v:4180$609_Y + connect \B $not$ls180.v:4180$610_Y + connect \Y $and$ls180.v:4180$611_Y end - attribute \src "ls180.v:4181.151-4181.220" - cell $and $and$ls180.v:4181$615 + attribute \src "ls180.v:4184.151-4184.220" + cell $and $and$ls180.v:4184$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4181$614_Y - connect \Y $and$ls180.v:4181$615_Y + connect \B $eq$ls180.v:4184$614_Y + connect \Y $and$ls180.v:4184$615_Y end - attribute \src "ls180.v:4181.226-4181.295" - cell $and $and$ls180.v:4181$618 + attribute \src "ls180.v:4184.226-4184.295" + cell $and $and$ls180.v:4184$618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4181$617_Y - connect \Y $and$ls180.v:4181$618_Y + connect \B $eq$ls180.v:4184$617_Y + connect \Y $and$ls180.v:4184$618_Y end - attribute \src "ls180.v:4181.301-4181.370" - cell $and $and$ls180.v:4181$621 + attribute \src "ls180.v:4184.301-4184.370" + cell $and $and$ls180.v:4184$621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4181$620_Y - connect \Y $and$ls180.v:4181$621_Y + connect \B $eq$ls180.v:4184$620_Y + connect \Y $and$ls180.v:4184$621_Y end - attribute \src "ls180.v:4181.82-4181.373" - cell $and $and$ls180.v:4181$624 + attribute \src "ls180.v:4184.82-4184.373" + cell $and $and$ls180.v:4184$624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$613_Y - connect \B $not$ls180.v:4181$623_Y - connect \Y $and$ls180.v:4181$624_Y + connect \A $eq$ls180.v:4184$613_Y + connect \B $not$ls180.v:4184$623_Y + connect \Y $and$ls180.v:4184$624_Y end - attribute \src "ls180.v:4181.43-4181.374" - cell $and $and$ls180.v:4181$625 + attribute \src "ls180.v:4184.43-4184.374" + cell $and $and$ls180.v:4184$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$612_Y - connect \B $and$ls180.v:4181$624_Y - connect \Y $and$ls180.v:4181$625_Y + connect \A $eq$ls180.v:4184$612_Y + connect \B $and$ls180.v:4184$624_Y + connect \Y $and$ls180.v:4184$625_Y end - attribute \src "ls180.v:4181.42-4181.410" - cell $and $and$ls180.v:4181$626 + attribute \src "ls180.v:4184.42-4184.410" + cell $and $and$ls180.v:4184$626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4181$625_Y + connect \A $and$ls180.v:4184$625_Y connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4181$626_Y + connect \Y $and$ls180.v:4184$626_Y end - attribute \src "ls180.v:4181.525-4181.594" - cell $and $and$ls180.v:4181$631 + attribute \src "ls180.v:4184.525-4184.594" + cell $and $and$ls180.v:4184$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4181$630_Y - connect \Y $and$ls180.v:4181$631_Y + connect \B $eq$ls180.v:4184$630_Y + connect \Y $and$ls180.v:4184$631_Y end - attribute \src "ls180.v:4181.600-4181.669" - cell $and $and$ls180.v:4181$634 + attribute \src "ls180.v:4184.600-4184.669" + cell $and $and$ls180.v:4184$634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4181$633_Y - connect \Y $and$ls180.v:4181$634_Y + connect \B $eq$ls180.v:4184$633_Y + connect \Y $and$ls180.v:4184$634_Y end - attribute \src "ls180.v:4181.675-4181.744" - cell $and $and$ls180.v:4181$637 + attribute \src "ls180.v:4184.675-4184.744" + cell $and $and$ls180.v:4184$637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4181$636_Y - connect \Y $and$ls180.v:4181$637_Y + connect \B $eq$ls180.v:4184$636_Y + connect \Y $and$ls180.v:4184$637_Y end - attribute \src "ls180.v:4181.456-4181.747" - cell $and $and$ls180.v:4181$640 + attribute \src "ls180.v:4184.456-4184.747" + cell $and $and$ls180.v:4184$640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$629_Y - connect \B $not$ls180.v:4181$639_Y - connect \Y $and$ls180.v:4181$640_Y + connect \A $eq$ls180.v:4184$629_Y + connect \B $not$ls180.v:4184$639_Y + connect \Y $and$ls180.v:4184$640_Y end - attribute \src "ls180.v:4181.417-4181.748" - cell $and $and$ls180.v:4181$641 + attribute \src "ls180.v:4184.417-4184.748" + cell $and $and$ls180.v:4184$641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$628_Y - connect \B $and$ls180.v:4181$640_Y - connect \Y $and$ls180.v:4181$641_Y + connect \A $eq$ls180.v:4184$628_Y + connect \B $and$ls180.v:4184$640_Y + connect \Y $and$ls180.v:4184$641_Y end - attribute \src "ls180.v:4181.416-4181.784" - cell $and $and$ls180.v:4181$642 + attribute \src "ls180.v:4184.416-4184.784" + cell $and $and$ls180.v:4184$642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4181$641_Y + connect \A $and$ls180.v:4184$641_Y connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4181$642_Y + connect \Y $and$ls180.v:4184$642_Y end - attribute \src "ls180.v:4181.899-4181.968" - cell $and $and$ls180.v:4181$647 + attribute \src "ls180.v:4184.899-4184.968" + cell $and $and$ls180.v:4184$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4181$646_Y - connect \Y $and$ls180.v:4181$647_Y + connect \B $eq$ls180.v:4184$646_Y + connect \Y $and$ls180.v:4184$647_Y end - attribute \src "ls180.v:4181.974-4181.1043" - cell $and $and$ls180.v:4181$650 + attribute \src "ls180.v:4184.974-4184.1043" + cell $and $and$ls180.v:4184$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4181$649_Y - connect \Y $and$ls180.v:4181$650_Y + connect \B $eq$ls180.v:4184$649_Y + connect \Y $and$ls180.v:4184$650_Y end - attribute \src "ls180.v:4181.1049-4181.1118" - cell $and $and$ls180.v:4181$653 + attribute \src "ls180.v:4184.1049-4184.1118" + cell $and $and$ls180.v:4184$653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4181$652_Y - connect \Y $and$ls180.v:4181$653_Y + connect \B $eq$ls180.v:4184$652_Y + connect \Y $and$ls180.v:4184$653_Y end - attribute \src "ls180.v:4181.830-4181.1121" - cell $and $and$ls180.v:4181$656 + attribute \src "ls180.v:4184.830-4184.1121" + cell $and $and$ls180.v:4184$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$645_Y - connect \B $not$ls180.v:4181$655_Y - connect \Y $and$ls180.v:4181$656_Y + connect \A $eq$ls180.v:4184$645_Y + connect \B $not$ls180.v:4184$655_Y + connect \Y $and$ls180.v:4184$656_Y end - attribute \src "ls180.v:4181.791-4181.1122" - cell $and $and$ls180.v:4181$657 + attribute \src "ls180.v:4184.791-4184.1122" + cell $and $and$ls180.v:4184$657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$644_Y - connect \B $and$ls180.v:4181$656_Y - connect \Y $and$ls180.v:4181$657_Y + connect \A $eq$ls180.v:4184$644_Y + connect \B $and$ls180.v:4184$656_Y + connect \Y $and$ls180.v:4184$657_Y end - attribute \src "ls180.v:4181.790-4181.1158" - cell $and $and$ls180.v:4181$658 + attribute \src "ls180.v:4184.790-4184.1158" + cell $and $and$ls180.v:4184$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4181$657_Y + connect \A $and$ls180.v:4184$657_Y connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4181$658_Y + connect \Y $and$ls180.v:4184$658_Y end - attribute \src "ls180.v:4181.1273-4181.1342" - cell $and $and$ls180.v:4181$663 + attribute \src "ls180.v:4184.1273-4184.1342" + cell $and $and$ls180.v:4184$663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4181$662_Y - connect \Y $and$ls180.v:4181$663_Y + connect \B $eq$ls180.v:4184$662_Y + connect \Y $and$ls180.v:4184$663_Y end - attribute \src "ls180.v:4181.1348-4181.1417" - cell $and $and$ls180.v:4181$666 + attribute \src "ls180.v:4184.1348-4184.1417" + cell $and $and$ls180.v:4184$666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4181$665_Y - connect \Y $and$ls180.v:4181$666_Y + connect \B $eq$ls180.v:4184$665_Y + connect \Y $and$ls180.v:4184$666_Y end - attribute \src "ls180.v:4181.1423-4181.1492" - cell $and $and$ls180.v:4181$669 + attribute \src "ls180.v:4184.1423-4184.1492" + cell $and $and$ls180.v:4184$669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4181$668_Y - connect \Y $and$ls180.v:4181$669_Y + connect \B $eq$ls180.v:4184$668_Y + connect \Y $and$ls180.v:4184$669_Y end - attribute \src "ls180.v:4181.1204-4181.1495" - cell $and $and$ls180.v:4181$672 + attribute \src "ls180.v:4184.1204-4184.1495" + cell $and $and$ls180.v:4184$672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$661_Y - connect \B $not$ls180.v:4181$671_Y - connect \Y $and$ls180.v:4181$672_Y + connect \A $eq$ls180.v:4184$661_Y + connect \B $not$ls180.v:4184$671_Y + connect \Y $and$ls180.v:4184$672_Y end - attribute \src "ls180.v:4181.1165-4181.1496" - cell $and $and$ls180.v:4181$673 + attribute \src "ls180.v:4184.1165-4184.1496" + cell $and $and$ls180.v:4184$673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$660_Y - connect \B $and$ls180.v:4181$672_Y - connect \Y $and$ls180.v:4181$673_Y + connect \A $eq$ls180.v:4184$660_Y + connect \B $and$ls180.v:4184$672_Y + connect \Y $and$ls180.v:4184$673_Y end - attribute \src "ls180.v:4181.1164-4181.1532" - cell $and $and$ls180.v:4181$674 + attribute \src "ls180.v:4184.1164-4184.1532" + cell $and $and$ls180.v:4184$674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4181$673_Y + connect \A $and$ls180.v:4184$673_Y connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4181$674_Y + connect \Y $and$ls180.v:4184$674_Y end - attribute \src "ls180.v:4239.9-4239.46" - cell $and $and$ls180.v:4239$680 + attribute \src "ls180.v:4242.9-4242.46" + cell $and $and$ls180.v:4242$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253859,10 +256388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4239$680_Y + connect \Y $and$ls180.v:4242$680_Y end - attribute \src "ls180.v:4257.9-4257.46" - cell $and $and$ls180.v:4257$687 + attribute \src "ls180.v:4260.9-4260.46" + cell $and $and$ls180.v:4260$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253870,10 +256399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4257$687_Y + connect \Y $and$ls180.v:4260$687_Y end - attribute \src "ls180.v:4270.32-4270.75" - cell $and $and$ls180.v:4270$691 + attribute \src "ls180.v:4273.32-4273.75" + cell $and $and$ls180.v:4273$691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253881,54 +256410,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4270$691_Y + connect \Y $and$ls180.v:4273$691_Y end - attribute \src "ls180.v:4270.31-4270.99" - cell $and $and$ls180.v:4270$693 + attribute \src "ls180.v:4273.31-4273.99" + cell $and $and$ls180.v:4273$693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4270$691_Y - connect \B $not$ls180.v:4270$692_Y - connect \Y $and$ls180.v:4270$693_Y + connect \A $and$ls180.v:4273$691_Y + connect \B $not$ls180.v:4273$692_Y + connect \Y $and$ls180.v:4273$693_Y end - attribute \src "ls180.v:4271.34-4271.102" - cell $and $and$ls180.v:4271$695 + attribute \src "ls180.v:4274.34-4274.102" + cell $and $and$ls180.v:4274$695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4271$694_Y + connect \A $or$ls180.v:4274$694_Y connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4271$695_Y + connect \Y $and$ls180.v:4274$695_Y end - attribute \src "ls180.v:4271.33-4271.128" - cell $and $and$ls180.v:4271$697 + attribute \src "ls180.v:4274.33-4274.128" + cell $and $and$ls180.v:4274$697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4271$695_Y - connect \B $not$ls180.v:4271$696_Y - connect \Y $and$ls180.v:4271$697_Y + connect \A $and$ls180.v:4274$695_Y + connect \B $not$ls180.v:4274$696_Y + connect \Y $and$ls180.v:4274$697_Y end - attribute \src "ls180.v:4272.33-4272.104" - cell $and $and$ls180.v:4272$700 + attribute \src "ls180.v:4275.33-4275.104" + cell $and $and$ls180.v:4275$700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4272$698_Y - connect \B $not$ls180.v:4272$699_Y - connect \Y $and$ls180.v:4272$700_Y + connect \A $or$ls180.v:4275$698_Y + connect \B $not$ls180.v:4275$699_Y + connect \Y $and$ls180.v:4275$700_Y end - attribute \src "ls180.v:4273.49-4273.85" - cell $and $and$ls180.v:4273$701 + attribute \src "ls180.v:4276.49-4276.85" + cell $and $and$ls180.v:4276$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253936,32 +256465,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we connect \B \main_ack_wdata - connect \Y $and$ls180.v:4273$701_Y + connect \Y $and$ls180.v:4276$701_Y end - attribute \src "ls180.v:4273.90-4273.129" - cell $and $and$ls180.v:4273$703 + attribute \src "ls180.v:4276.90-4276.129" + cell $and $and$ls180.v:4276$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4273$702_Y + connect \A $not$ls180.v:4276$702_Y connect \B \main_ack_rdata - connect \Y $and$ls180.v:4273$703_Y + connect \Y $and$ls180.v:4276$703_Y end - attribute \src "ls180.v:4273.32-4273.131" - cell $and $and$ls180.v:4273$705 + attribute \src "ls180.v:4276.32-4276.131" + cell $and $and$ls180.v:4276$705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_ack_cmd - connect \B $or$ls180.v:4273$704_Y - connect \Y $and$ls180.v:4273$705_Y + connect \B $or$ls180.v:4276$704_Y + connect \Y $and$ls180.v:4276$705_Y end - attribute \src "ls180.v:4274.25-4274.66" - cell $and $and$ls180.v:4274$706 + attribute \src "ls180.v:4277.25-4277.66" + cell $and $and$ls180.v:4277$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253969,10 +256498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4274$706_Y + connect \Y $and$ls180.v:4277$706_Y end - attribute \src "ls180.v:4275.27-4275.72" - cell $and $and$ls180.v:4275$708 + attribute \src "ls180.v:4278.27-4278.72" + cell $and $and$ls180.v:4278$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253980,10 +256509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4275$708_Y + connect \Y $and$ls180.v:4278$708_Y end - attribute \src "ls180.v:4276.26-4276.71" - cell $and $and$ls180.v:4276$710 + attribute \src "ls180.v:4279.26-4279.71" + cell $and $and$ls180.v:4279$710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253991,10 +256520,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_rdata_valid connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4276$710_Y + connect \Y $and$ls180.v:4279$710_Y end - attribute \src "ls180.v:4305.64-4305.88" - cell $and $and$ls180.v:4305$716 + attribute \src "ls180.v:4308.64-4308.88" + cell $and $and$ls180.v:4308$716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254002,10 +256531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4305$716_Y + connect \Y $and$ls180.v:4308$716_Y end - attribute \src "ls180.v:4309.7-4309.78" - cell $and $and$ls180.v:4309$720 + attribute \src "ls180.v:4312.7-4312.78" + cell $and $and$ls180.v:4312$720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254013,10 +256542,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4309$720_Y + connect \Y $and$ls180.v:4312$720_Y end - attribute \src "ls180.v:4320.7-4320.78" - cell $and $and$ls180.v:4320$723 + attribute \src "ls180.v:4323.7-4323.78" + cell $and $and$ls180.v:4323$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254024,10 +256553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4320$723_Y + connect \Y $and$ls180.v:4323$723_Y end - attribute \src "ls180.v:4329.26-4329.97" - cell $and $and$ls180.v:4329$725 + attribute \src "ls180.v:4332.26-4332.97" + cell $and $and$ls180.v:4332$725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254035,10 +256564,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [0] connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4329$725_Y + connect \Y $and$ls180.v:4332$725_Y end - attribute \src "ls180.v:4329.102-4329.173" - cell $and $and$ls180.v:4329$726 + attribute \src "ls180.v:4332.102-4332.173" + cell $and $and$ls180.v:4332$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254046,32 +256575,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [1] connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4329$726_Y + connect \Y $and$ls180.v:4332$726_Y end - attribute \src "ls180.v:4344.41-4344.133" - cell $and $and$ls180.v:4344$730 + attribute \src "ls180.v:4347.41-4347.133" + cell $and $and$ls180.v:4347$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4344$729_Y - connect \Y $and$ls180.v:4344$730_Y + connect \B $or$ls180.v:4347$729_Y + connect \Y $and$ls180.v:4347$730_Y end - attribute \src "ls180.v:4355.39-4355.136" - cell $and $and$ls180.v:4355$735 + attribute \src "ls180.v:4358.39-4358.136" + cell $and $and$ls180.v:4358$735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4355$734_Y - connect \Y $and$ls180.v:4355$735_Y + connect \B $or$ls180.v:4358$734_Y + connect \Y $and$ls180.v:4358$735_Y end - attribute \src "ls180.v:4356.37-4356.104" - cell $and $and$ls180.v:4356$736 + attribute \src "ls180.v:4359.37-4359.104" + cell $and $and$ls180.v:4359$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254079,32 +256608,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4356$736_Y + connect \Y $and$ls180.v:4359$736_Y end - attribute \src "ls180.v:4374.41-4374.133" - cell $and $and$ls180.v:4374$741 + attribute \src "ls180.v:4377.41-4377.133" + cell $and $and$ls180.v:4377$741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4374$740_Y - connect \Y $and$ls180.v:4374$741_Y + connect \B $or$ls180.v:4377$740_Y + connect \Y $and$ls180.v:4377$741_Y end - attribute \src "ls180.v:4385.39-4385.136" - cell $and $and$ls180.v:4385$746 + attribute \src "ls180.v:4388.39-4388.136" + cell $and $and$ls180.v:4388$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4385$745_Y - connect \Y $and$ls180.v:4385$746_Y + connect \B $or$ls180.v:4388$745_Y + connect \Y $and$ls180.v:4388$746_Y end - attribute \src "ls180.v:4386.37-4386.104" - cell $and $and$ls180.v:4386$747 + attribute \src "ls180.v:4389.37-4389.104" + cell $and $and$ls180.v:4389$747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254112,21 +256641,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4386$747_Y + connect \Y $and$ls180.v:4389$747_Y end - attribute \src "ls180.v:4585.33-4585.86" - cell $and $and$ls180.v:4585$791 + attribute \src "ls180.v:4588.33-4588.86" + cell $and $and$ls180.v:4588$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4585$790_Y - connect \Y $and$ls180.v:4585$791_Y + connect \B $not$ls180.v:4588$790_Y + connect \Y $and$ls180.v:4588$791_Y end - attribute \src "ls180.v:4689.9-4689.68" - cell $and $and$ls180.v:4689$800 + attribute \src "ls180.v:4692.9-4692.68" + cell $and $and$ls180.v:4692$800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254134,21 +256663,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4689$800_Y + connect \Y $and$ls180.v:4692$800_Y end - attribute \src "ls180.v:4709.53-4709.145" - cell $and $and$ls180.v:4709$803 + attribute \src "ls180.v:4712.53-4712.145" + cell $and $and$ls180.v:4712$803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4709$802_Y - connect \Y $and$ls180.v:4709$803_Y + connect \B $or$ls180.v:4712$802_Y + connect \Y $and$ls180.v:4712$803_Y end - attribute \src "ls180.v:4728.52-4728.137" - cell $and $and$ls180.v:4728$806 + attribute \src "ls180.v:4731.52-4731.137" + cell $and $and$ls180.v:4731$806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254156,10 +256685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4728$806_Y + connect \Y $and$ls180.v:4731$806_Y end - attribute \src "ls180.v:4769.9-4769.68" - cell $and $and$ls180.v:4769$814 + attribute \src "ls180.v:4772.9-4772.68" + cell $and $and$ls180.v:4772$814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254167,10 +256696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4769$814_Y + connect \Y $and$ls180.v:4772$814_Y end - attribute \src "ls180.v:4807.9-4807.68" - cell $and $and$ls180.v:4807$820 + attribute \src "ls180.v:4810.9-4810.68" + cell $and $and$ls180.v:4810$820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254178,10 +256707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4807$820_Y + connect \Y $and$ls180.v:4810$820_Y end - attribute \src "ls180.v:4816.10-4816.69" - cell $and $and$ls180.v:4816$821 + attribute \src "ls180.v:4819.10-4819.69" + cell $and $and$ls180.v:4819$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254189,21 +256718,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_sink_valid connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4816$821_Y + connect \Y $and$ls180.v:4819$821_Y end - attribute \src "ls180.v:4816.9-4816.93" - cell $and $and$ls180.v:4816$822 + attribute \src "ls180.v:4819.9-4819.93" + cell $and $and$ls180.v:4819$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4816$821_Y + connect \A $and$ls180.v:4819$821_Y connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4816$822_Y + connect \Y $and$ls180.v:4819$822_Y end - attribute \src "ls180.v:4836.54-4836.117" - cell $and $and$ls180.v:4836$824 + attribute \src "ls180.v:4839.54-4839.117" + cell $and $and$ls180.v:4839$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254211,10 +256740,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_valid connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4836$824_Y + connect \Y $and$ls180.v:4839$824_Y end - attribute \src "ls180.v:4855.53-4855.140" - cell $and $and$ls180.v:4855$827 + attribute \src "ls180.v:4858.53-4858.140" + cell $and $and$ls180.v:4858$827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254222,10 +256751,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4855$827_Y + connect \Y $and$ls180.v:4858$827_Y end - attribute \src "ls180.v:4952.9-4952.70" - cell $and $and$ls180.v:4952$837 + attribute \src "ls180.v:4955.9-4955.70" + cell $and $and$ls180.v:4955$837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254233,10 +256762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4952$837_Y + connect \Y $and$ls180.v:4955$837_Y end - attribute \src "ls180.v:4970.55-4970.120" - cell $and $and$ls180.v:4970$839 + attribute \src "ls180.v:4973.55-4973.120" + cell $and $and$ls180.v:4973$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254244,10 +256773,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_valid connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4970$839_Y + connect \Y $and$ls180.v:4973$839_Y end - attribute \src "ls180.v:4989.54-4989.143" - cell $and $and$ls180.v:4989$842 + attribute \src "ls180.v:4992.54-4992.143" + cell $and $and$ls180.v:4992$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254255,10 +256784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4989$842_Y + connect \Y $and$ls180.v:4992$842_Y end - attribute \src "ls180.v:5071.9-5071.70" - cell $and $and$ls180.v:5071$857 + attribute \src "ls180.v:5074.9-5074.70" + cell $and $and$ls180.v:5074$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254266,10 +256795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_valid connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5071$857_Y + connect \Y $and$ls180.v:5074$857_Y end - attribute \src "ls180.v:5078.9-5078.70" - cell $and $and$ls180.v:5078$858 + attribute \src "ls180.v:5081.9-5081.70" + cell $and $and$ls180.v:5081$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254277,10 +256806,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_sink_valid connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:5078$858_Y + connect \Y $and$ls180.v:5081$858_Y end - attribute \src "ls180.v:5159.48-5159.124" - cell $and $and$ls180.v:5159$981 + attribute \src "ls180.v:5162.48-5162.124" + cell $and $and$ls180.v:5162$981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254288,21 +256817,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5159$981_Y + connect \Y $and$ls180.v:5162$981_Y end - attribute \src "ls180.v:5159.47-5159.165" - cell $and $and$ls180.v:5159$982 + attribute \src "ls180.v:5162.47-5162.165" + cell $and $and$ls180.v:5162$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5159$981_Y + connect \A $and$ls180.v:5162$981_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5159$982_Y + connect \Y $and$ls180.v:5162$982_Y end - attribute \src "ls180.v:5160.50-5160.127" - cell $and $and$ls180.v:5160$983 + attribute \src "ls180.v:5163.50-5163.127" + cell $and $and$ls180.v:5163$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254310,10 +256839,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5160$983_Y + connect \Y $and$ls180.v:5163$983_Y end - attribute \src "ls180.v:5162.48-5162.124" - cell $and $and$ls180.v:5162$984 + attribute \src "ls180.v:5165.48-5165.124" + cell $and $and$ls180.v:5165$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254321,21 +256850,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5162$984_Y + connect \Y $and$ls180.v:5165$984_Y end - attribute \src "ls180.v:5162.47-5162.165" - cell $and $and$ls180.v:5162$985 + attribute \src "ls180.v:5165.47-5165.165" + cell $and $and$ls180.v:5165$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5162$984_Y + connect \A $and$ls180.v:5165$984_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5162$985_Y + connect \Y $and$ls180.v:5165$985_Y end - attribute \src "ls180.v:5163.50-5163.127" - cell $and $and$ls180.v:5163$986 + attribute \src "ls180.v:5166.50-5166.127" + cell $and $and$ls180.v:5166$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254343,10 +256872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5163$986_Y + connect \Y $and$ls180.v:5166$986_Y end - attribute \src "ls180.v:5165.48-5165.124" - cell $and $and$ls180.v:5165$987 + attribute \src "ls180.v:5168.48-5168.124" + cell $and $and$ls180.v:5168$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254354,21 +256883,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5165$987_Y + connect \Y $and$ls180.v:5168$987_Y end - attribute \src "ls180.v:5165.47-5165.165" - cell $and $and$ls180.v:5165$988 + attribute \src "ls180.v:5168.47-5168.165" + cell $and $and$ls180.v:5168$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5165$987_Y + connect \A $and$ls180.v:5168$987_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5165$988_Y + connect \Y $and$ls180.v:5168$988_Y end - attribute \src "ls180.v:5166.50-5166.127" - cell $and $and$ls180.v:5166$989 + attribute \src "ls180.v:5169.50-5169.127" + cell $and $and$ls180.v:5169$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254376,10 +256905,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5166$989_Y + connect \Y $and$ls180.v:5169$989_Y end - attribute \src "ls180.v:5168.48-5168.124" - cell $and $and$ls180.v:5168$990 + attribute \src "ls180.v:5171.48-5171.124" + cell $and $and$ls180.v:5171$990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254387,21 +256916,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5168$990_Y + connect \Y $and$ls180.v:5171$990_Y end - attribute \src "ls180.v:5168.47-5168.165" - cell $and $and$ls180.v:5168$991 + attribute \src "ls180.v:5171.47-5171.165" + cell $and $and$ls180.v:5171$991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5168$990_Y + connect \A $and$ls180.v:5171$990_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5168$991_Y + connect \Y $and$ls180.v:5171$991_Y end - attribute \src "ls180.v:5169.50-5169.127" - cell $and $and$ls180.v:5169$992 + attribute \src "ls180.v:5172.50-5172.127" + cell $and $and$ls180.v:5172$992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254409,10 +256938,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5169$992_Y + connect \Y $and$ls180.v:5172$992_Y end - attribute \src "ls180.v:5282.10-5282.86" - cell $and $and$ls180.v:5282$1041 + attribute \src "ls180.v:5285.10-5285.86" + cell $and $and$ls180.v:5285$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254420,54 +256949,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5282$1041_Y + connect \Y $and$ls180.v:5285$1041_Y end - attribute \src "ls180.v:5282.9-5282.127" - cell $and $and$ls180.v:5282$1042 + attribute \src "ls180.v:5285.9-5285.127" + cell $and $and$ls180.v:5285$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5282$1041_Y + connect \A $and$ls180.v:5285$1041_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5282$1042_Y + connect \Y $and$ls180.v:5285$1042_Y end - attribute \src "ls180.v:5292.9-5292.152" - cell $and $and$ls180.v:5292$1046 + attribute \src "ls180.v:5295.9-5295.152" + cell $and $and$ls180.v:5295$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5292$1044_Y - connect \B $eq$ls180.v:5292$1045_Y - connect \Y $and$ls180.v:5292$1046_Y + connect \A $eq$ls180.v:5295$1044_Y + connect \B $eq$ls180.v:5295$1045_Y + connect \Y $and$ls180.v:5295$1046_Y end - attribute \src "ls180.v:5292.8-5292.226" - cell $and $and$ls180.v:5292$1048 + attribute \src "ls180.v:5295.8-5295.226" + cell $and $and$ls180.v:5295$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5292$1046_Y - connect \B $eq$ls180.v:5292$1047_Y - connect \Y $and$ls180.v:5292$1048_Y + connect \A $and$ls180.v:5295$1046_Y + connect \B $eq$ls180.v:5295$1047_Y + connect \Y $and$ls180.v:5295$1048_Y end - attribute \src "ls180.v:5292.7-5292.300" - cell $and $and$ls180.v:5292$1050 + attribute \src "ls180.v:5295.7-5295.300" + cell $and $and$ls180.v:5295$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5292$1048_Y - connect \B $eq$ls180.v:5292$1049_Y - connect \Y $and$ls180.v:5292$1050_Y + connect \A $and$ls180.v:5295$1048_Y + connect \B $eq$ls180.v:5295$1049_Y + connect \Y $and$ls180.v:5295$1050_Y end - attribute \src "ls180.v:5297.49-5297.124" - cell $and $and$ls180.v:5297$1051 + attribute \src "ls180.v:5300.49-5300.124" + cell $and $and$ls180.v:5300$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254475,10 +257004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5297$1051_Y + connect \Y $and$ls180.v:5300$1051_Y end - attribute \src "ls180.v:5307.49-5307.124" - cell $and $and$ls180.v:5307$1054 + attribute \src "ls180.v:5310.49-5310.124" + cell $and $and$ls180.v:5310$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254486,10 +257015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5307$1054_Y + connect \Y $and$ls180.v:5310$1054_Y end - attribute \src "ls180.v:5317.49-5317.124" - cell $and $and$ls180.v:5317$1057 + attribute \src "ls180.v:5320.49-5320.124" + cell $and $and$ls180.v:5320$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254497,10 +257026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5317$1057_Y + connect \Y $and$ls180.v:5320$1057_Y end - attribute \src "ls180.v:5327.49-5327.124" - cell $and $and$ls180.v:5327$1060 + attribute \src "ls180.v:5330.49-5330.124" + cell $and $and$ls180.v:5330$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254508,21 +257037,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5327$1060_Y + connect \Y $and$ls180.v:5330$1060_Y end - attribute \src "ls180.v:5339.7-5339.84" - cell $and $and$ls180.v:5339$1065 + attribute \src "ls180.v:5342.7-5342.84" + cell $and $and$ls180.v:5342$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5339$1064_Y - connect \Y $and$ls180.v:5339$1065_Y + connect \B $gt$ls180.v:5342$1064_Y + connect \Y $and$ls180.v:5342$1065_Y end - attribute \src "ls180.v:5457.9-5457.64" - cell $and $and$ls180.v:5457$1114 + attribute \src "ls180.v:5460.9-5460.64" + cell $and $and$ls180.v:5460$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254530,10 +257059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5457$1114_Y + connect \Y $and$ls180.v:5460$1114_Y end - attribute \src "ls180.v:5509.10-5509.66" - cell $and $and$ls180.v:5509$1123 + attribute \src "ls180.v:5512.10-5512.66" + cell $and $and$ls180.v:5512$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254541,21 +257070,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5509$1123_Y + connect \Y $and$ls180.v:5512$1123_Y end - attribute \src "ls180.v:5509.9-5509.97" - cell $and $and$ls180.v:5509$1124 + attribute \src "ls180.v:5512.9-5512.97" + cell $and $and$ls180.v:5512$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5509$1123_Y + connect \A $and$ls180.v:5512$1123_Y connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5509$1124_Y + connect \Y $and$ls180.v:5512$1124_Y end - attribute \src "ls180.v:5535.11-5535.71" - cell $and $and$ls180.v:5535$1132 + attribute \src "ls180.v:5538.11-5538.71" + cell $and $and$ls180.v:5538$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254563,21 +257092,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_last connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5535$1132_Y + connect \Y $and$ls180.v:5538$1132_Y end - attribute \src "ls180.v:5619.43-5619.152" - cell $and $and$ls180.v:5619$1140 + attribute \src "ls180.v:5622.43-5622.152" + cell $and $and$ls180.v:5622$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5619$1139_Y - connect \Y $and$ls180.v:5619$1140_Y + connect \B $or$ls180.v:5622$1139_Y + connect \Y $and$ls180.v:5622$1140_Y end - attribute \src "ls180.v:5620.41-5620.116" - cell $and $and$ls180.v:5620$1141 + attribute \src "ls180.v:5623.41-5623.116" + cell $and $and$ls180.v:5623$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254585,10 +257114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_readable connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5620$1141_Y + connect \Y $and$ls180.v:5623$1141_Y end - attribute \src "ls180.v:5632.48-5632.125" - cell $and $and$ls180.v:5632$1146 + attribute \src "ls180.v:5635.48-5635.125" + cell $and $and$ls180.v:5635$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254596,10 +257125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5632$1146_Y + connect \Y $and$ls180.v:5635$1146_Y end - attribute \src "ls180.v:5659.9-5659.102" - cell $and $and$ls180.v:5659$1150 + attribute \src "ls180.v:5662.9-5662.102" + cell $and $and$ls180.v:5662$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254607,10 +257136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5659$1150_Y + connect \Y $and$ls180.v:5662$1150_Y end - attribute \src "ls180.v:5732.9-5732.58" - cell $and $and$ls180.v:5732$1156 + attribute \src "ls180.v:5735.9-5735.58" + cell $and $and$ls180.v:5735$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254618,10 +257147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_bus_stb connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5732$1156_Y + connect \Y $and$ls180.v:5735$1156_Y end - attribute \src "ls180.v:5785.51-5785.123" - cell $and $and$ls180.v:5785$1164 + attribute \src "ls180.v:5788.51-5788.123" + cell $and $and$ls180.v:5788$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254629,10 +257158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_first connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5785$1164_Y + connect \Y $and$ls180.v:5788$1164_Y end - attribute \src "ls180.v:5786.50-5786.120" - cell $and $and$ls180.v:5786$1165 + attribute \src "ls180.v:5789.50-5789.120" + cell $and $and$ls180.v:5789$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254640,10 +257169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_last connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5786$1165_Y + connect \Y $and$ls180.v:5789$1165_Y end - attribute \src "ls180.v:5787.49-5787.122" - cell $and $and$ls180.v:5787$1166 + attribute \src "ls180.v:5790.49-5790.122" + cell $and $and$ls180.v:5790$1166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254651,21 +257180,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_last connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5787$1166_Y + connect \Y $and$ls180.v:5790$1166_Y end - attribute \src "ls180.v:5839.43-5839.152" - cell $and $and$ls180.v:5839$1171 + attribute \src "ls180.v:5842.43-5842.152" + cell $and $and$ls180.v:5842$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5839$1170_Y - connect \Y $and$ls180.v:5839$1171_Y + connect \B $or$ls180.v:5842$1170_Y + connect \Y $and$ls180.v:5842$1171_Y end - attribute \src "ls180.v:5840.41-5840.116" - cell $and $and$ls180.v:5840$1172 + attribute \src "ls180.v:5843.41-5843.116" + cell $and $and$ls180.v:5843$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254673,10 +257202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_readable connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5840$1172_Y + connect \Y $and$ls180.v:5843$1172_Y end - attribute \src "ls180.v:5872.9-5872.76" - cell $and $and$ls180.v:5872$1176 + attribute \src "ls180.v:5875.9-5875.76" + cell $and $and$ls180.v:5875$1176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254684,131 +257213,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_cyc connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5872$1176_Y + connect \Y $and$ls180.v:5875$1176_Y end - attribute \src "ls180.v:5875.44-5875.120" - cell $and $and$ls180.v:5875$1178 + attribute \src "ls180.v:5878.44-5878.120" + cell $and $and$ls180.v:5878$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5875$1177_Y - connect \Y $and$ls180.v:5875$1178_Y + connect \B $ne$ls180.v:5878$1177_Y + connect \Y $and$ls180.v:5878$1178_Y end - attribute \src "ls180.v:5895.46-5895.90" - cell $and $and$ls180.v:5895$1180 + attribute \src "ls180.v:5898.46-5898.90" + cell $and $and$ls180.v:5898$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5895$1179_Y - connect \Y $and$ls180.v:5895$1180_Y + connect \B $eq$ls180.v:5898$1179_Y + connect \Y $and$ls180.v:5898$1180_Y end - attribute \src "ls180.v:5896.46-5896.90" - cell $and $and$ls180.v:5896$1182 + attribute \src "ls180.v:5899.46-5899.90" + cell $and $and$ls180.v:5899$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5896$1181_Y - connect \Y $and$ls180.v:5896$1182_Y + connect \B $eq$ls180.v:5899$1181_Y + connect \Y $and$ls180.v:5899$1182_Y end - attribute \src "ls180.v:5897.49-5897.93" - cell $and $and$ls180.v:5897$1184 + attribute \src "ls180.v:5900.49-5900.93" + cell $and $and$ls180.v:5900$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5897$1183_Y - connect \Y $and$ls180.v:5897$1184_Y + connect \B $eq$ls180.v:5900$1183_Y + connect \Y $and$ls180.v:5900$1184_Y end - attribute \src "ls180.v:5898.35-5898.79" - cell $and $and$ls180.v:5898$1186 + attribute \src "ls180.v:5901.35-5901.79" + cell $and $and$ls180.v:5901$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5898$1185_Y - connect \Y $and$ls180.v:5898$1186_Y + connect \B $eq$ls180.v:5901$1185_Y + connect \Y $and$ls180.v:5901$1186_Y end - attribute \src "ls180.v:5899.35-5899.79" - cell $and $and$ls180.v:5899$1188 + attribute \src "ls180.v:5902.35-5902.79" + cell $and $and$ls180.v:5902$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5899$1187_Y - connect \Y $and$ls180.v:5899$1188_Y + connect \B $eq$ls180.v:5902$1187_Y + connect \Y $and$ls180.v:5902$1188_Y end - attribute \src "ls180.v:5900.46-5900.90" - cell $and $and$ls180.v:5900$1190 + attribute \src "ls180.v:5903.46-5903.90" + cell $and $and$ls180.v:5903$1190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5900$1189_Y - connect \Y $and$ls180.v:5900$1190_Y + connect \B $eq$ls180.v:5903$1189_Y + connect \Y $and$ls180.v:5903$1190_Y end - attribute \src "ls180.v:5901.46-5901.90" - cell $and $and$ls180.v:5901$1192 + attribute \src "ls180.v:5904.46-5904.90" + cell $and $and$ls180.v:5904$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5901$1191_Y - connect \Y $and$ls180.v:5901$1192_Y + connect \B $eq$ls180.v:5904$1191_Y + connect \Y $and$ls180.v:5904$1192_Y end - attribute \src "ls180.v:5902.49-5902.93" - cell $and $and$ls180.v:5902$1194 + attribute \src "ls180.v:5905.49-5905.93" + cell $and $and$ls180.v:5905$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5902$1193_Y - connect \Y $and$ls180.v:5902$1194_Y + connect \B $eq$ls180.v:5905$1193_Y + connect \Y $and$ls180.v:5905$1194_Y end - attribute \src "ls180.v:5903.35-5903.79" - cell $and $and$ls180.v:5903$1196 + attribute \src "ls180.v:5906.35-5906.79" + cell $and $and$ls180.v:5906$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5903$1195_Y - connect \Y $and$ls180.v:5903$1196_Y + connect \B $eq$ls180.v:5906$1195_Y + connect \Y $and$ls180.v:5906$1196_Y end - attribute \src "ls180.v:5904.35-5904.79" - cell $and $and$ls180.v:5904$1198 + attribute \src "ls180.v:5907.35-5907.79" + cell $and $and$ls180.v:5907$1198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5904$1197_Y - connect \Y $and$ls180.v:5904$1198_Y + connect \B $eq$ls180.v:5907$1197_Y + connect \Y $and$ls180.v:5907$1198_Y end - attribute \src "ls180.v:6013.40-6013.81" - cell $and $and$ls180.v:6013$1213 + attribute \src "ls180.v:6016.40-6016.81" + cell $and $and$ls180.v:6016$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254816,10 +257345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:6013$1213_Y + connect \Y $and$ls180.v:6016$1213_Y end - attribute \src "ls180.v:6014.39-6014.80" - cell $and $and$ls180.v:6014$1214 + attribute \src "ls180.v:6017.39-6017.80" + cell $and $and$ls180.v:6017$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254827,10 +257356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:6014$1214_Y + connect \Y $and$ls180.v:6017$1214_Y end - attribute \src "ls180.v:6015.39-6015.80" - cell $and $and$ls180.v:6015$1215 + attribute \src "ls180.v:6018.39-6018.80" + cell $and $and$ls180.v:6018$1215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254838,10 +257367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:6015$1215_Y + connect \Y $and$ls180.v:6018$1215_Y end - attribute \src "ls180.v:6016.39-6016.80" - cell $and $and$ls180.v:6016$1216 + attribute \src "ls180.v:6019.39-6019.80" + cell $and $and$ls180.v:6019$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254849,10 +257378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:6016$1216_Y + connect \Y $and$ls180.v:6019$1216_Y end - attribute \src "ls180.v:6017.39-6017.80" - cell $and $and$ls180.v:6017$1217 + attribute \src "ls180.v:6020.39-6020.80" + cell $and $and$ls180.v:6020$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254860,10 +257389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:6017$1217_Y + connect \Y $and$ls180.v:6020$1217_Y end - attribute \src "ls180.v:6018.51-6018.92" - cell $and $and$ls180.v:6018$1218 + attribute \src "ls180.v:6021.51-6021.92" + cell $and $and$ls180.v:6021$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254871,10 +257400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [5] - connect \Y $and$ls180.v:6018$1218_Y + connect \Y $and$ls180.v:6021$1218_Y end - attribute \src "ls180.v:6019.51-6019.92" - cell $and $and$ls180.v:6019$1219 + attribute \src "ls180.v:6022.51-6022.92" + cell $and $and$ls180.v:6022$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254882,10 +257411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [6] - connect \Y $and$ls180.v:6019$1219_Y + connect \Y $and$ls180.v:6022$1219_Y end - attribute \src "ls180.v:6020.52-6020.93" - cell $and $and$ls180.v:6020$1220 + attribute \src "ls180.v:6023.52-6023.93" + cell $and $and$ls180.v:6023$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254893,10 +257422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [7] - connect \Y $and$ls180.v:6020$1220_Y + connect \Y $and$ls180.v:6023$1220_Y end - attribute \src "ls180.v:6021.52-6021.93" - cell $and $and$ls180.v:6021$1221 + attribute \src "ls180.v:6024.52-6024.93" + cell $and $and$ls180.v:6024$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254904,10 +257433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [8] - connect \Y $and$ls180.v:6021$1221_Y + connect \Y $and$ls180.v:6024$1221_Y end - attribute \src "ls180.v:6022.52-6022.93" - cell $and $and$ls180.v:6022$1222 + attribute \src "ls180.v:6025.52-6025.93" + cell $and $and$ls180.v:6025$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254915,10 +257444,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [9] - connect \Y $and$ls180.v:6022$1222_Y + connect \Y $and$ls180.v:6025$1222_Y end - attribute \src "ls180.v:6023.52-6023.94" - cell $and $and$ls180.v:6023$1223 + attribute \src "ls180.v:6026.52-6026.94" + cell $and $and$ls180.v:6026$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254926,10 +257455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [10] - connect \Y $and$ls180.v:6023$1223_Y + connect \Y $and$ls180.v:6026$1223_Y end - attribute \src "ls180.v:6024.54-6024.96" - cell $and $and$ls180.v:6024$1224 + attribute \src "ls180.v:6027.54-6027.96" + cell $and $and$ls180.v:6027$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254937,10 +257466,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [11] - connect \Y $and$ls180.v:6024$1224_Y + connect \Y $and$ls180.v:6027$1224_Y end - attribute \src "ls180.v:6025.55-6025.97" - cell $and $and$ls180.v:6025$1225 + attribute \src "ls180.v:6028.55-6028.97" + cell $and $and$ls180.v:6028$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254948,10 +257477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [12] - connect \Y $and$ls180.v:6025$1225_Y + connect \Y $and$ls180.v:6028$1225_Y end - attribute \src "ls180.v:6027.25-6027.64" - cell $and $and$ls180.v:6027$1238 + attribute \src "ls180.v:6030.25-6030.64" + cell $and $and$ls180.v:6030$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254959,21 +257488,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_stb connect \B \builder_shared_cyc - connect \Y $and$ls180.v:6027$1238_Y + connect \Y $and$ls180.v:6030$1238_Y end - attribute \src "ls180.v:6027.24-6027.89" - cell $and $and$ls180.v:6027$1240 + attribute \src "ls180.v:6030.24-6030.89" + cell $and $and$ls180.v:6030$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6027$1238_Y - connect \B $not$ls180.v:6027$1239_Y - connect \Y $and$ls180.v:6027$1240_Y + connect \A $and$ls180.v:6030$1238_Y + connect \B $not$ls180.v:6030$1239_Y + connect \Y $and$ls180.v:6030$1240_Y end - attribute \src "ls180.v:6033.39-6033.100" - cell $and $and$ls180.v:6033$1254 + attribute \src "ls180.v:6036.39-6036.100" + cell $and $and$ls180.v:6036$1254 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -254981,10 +257510,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1254_Y + connect \Y $and$ls180.v:6036$1254_Y end - attribute \src "ls180.v:6033.105-6033.165" - cell $and $and$ls180.v:6033$1255 + attribute \src "ls180.v:6036.105-6036.165" + cell $and $and$ls180.v:6036$1255 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -254992,10 +257521,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } connect \B \main_interface0_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1255_Y + connect \Y $and$ls180.v:6036$1255_Y end - attribute \src "ls180.v:6033.171-6033.231" - cell $and $and$ls180.v:6033$1257 + attribute \src "ls180.v:6036.171-6036.231" + cell $and $and$ls180.v:6036$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255003,10 +257532,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } connect \B \main_interface1_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1257_Y + connect \Y $and$ls180.v:6036$1257_Y end - attribute \src "ls180.v:6033.237-6033.297" - cell $and $and$ls180.v:6033$1259 + attribute \src "ls180.v:6036.237-6036.297" + cell $and $and$ls180.v:6036$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255014,10 +257543,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } connect \B \main_interface2_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1259_Y + connect \Y $and$ls180.v:6036$1259_Y end - attribute \src "ls180.v:6033.303-6033.363" - cell $and $and$ls180.v:6033$1261 + attribute \src "ls180.v:6036.303-6036.363" + cell $and $and$ls180.v:6036$1261 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255025,10 +257554,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } connect \B \main_interface3_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1261_Y + connect \Y $and$ls180.v:6036$1261_Y end - attribute \src "ls180.v:6033.369-6033.441" - cell $and $and$ls180.v:6033$1263 + attribute \src "ls180.v:6036.369-6036.441" + cell $and $and$ls180.v:6036$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255036,10 +257565,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } connect \B \main_interface0_converted_interface_dat_r - connect \Y $and$ls180.v:6033$1263_Y + connect \Y $and$ls180.v:6036$1263_Y end - attribute \src "ls180.v:6033.447-6033.519" - cell $and $and$ls180.v:6033$1265 + attribute \src "ls180.v:6036.447-6036.519" + cell $and $and$ls180.v:6036$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255047,10 +257576,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } connect \B \main_interface1_converted_interface_dat_r - connect \Y $and$ls180.v:6033$1265_Y + connect \Y $and$ls180.v:6036$1265_Y end - attribute \src "ls180.v:6033.525-6033.598" - cell $and $and$ls180.v:6033$1267 + attribute \src "ls180.v:6036.525-6036.598" + cell $and $and$ls180.v:6036$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255058,10 +257587,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } connect \B \main_libresocsim_libresoc_interface0_dat_r - connect \Y $and$ls180.v:6033$1267_Y + connect \Y $and$ls180.v:6036$1267_Y end - attribute \src "ls180.v:6033.604-6033.677" - cell $and $and$ls180.v:6033$1269 + attribute \src "ls180.v:6036.604-6036.677" + cell $and $and$ls180.v:6036$1269 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255069,10 +257598,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] } connect \B \main_libresocsim_libresoc_interface1_dat_r - connect \Y $and$ls180.v:6033$1269_Y + connect \Y $and$ls180.v:6036$1269_Y end - attribute \src "ls180.v:6033.683-6033.756" - cell $and $and$ls180.v:6033$1271 + attribute \src "ls180.v:6036.683-6036.756" + cell $and $and$ls180.v:6036$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255080,10 +257609,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] } connect \B \main_libresocsim_libresoc_interface2_dat_r - connect \Y $and$ls180.v:6033$1271_Y + connect \Y $and$ls180.v:6036$1271_Y end - attribute \src "ls180.v:6033.762-6033.836" - cell $and $and$ls180.v:6033$1273 + attribute \src "ls180.v:6036.762-6036.836" + cell $and $and$ls180.v:6036$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255091,10 +257620,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] } connect \B \main_libresocsim_libresoc_interface3_dat_r - connect \Y $and$ls180.v:6033$1273_Y + connect \Y $and$ls180.v:6036$1273_Y end - attribute \src "ls180.v:6033.842-6033.918" - cell $and $and$ls180.v:6033$1275 + attribute \src "ls180.v:6036.842-6036.918" + cell $and $and$ls180.v:6036$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255102,10 +257631,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] } connect \B \main_socbushandler_converted_interface_dat_r - connect \Y $and$ls180.v:6033$1275_Y + connect \Y $and$ls180.v:6036$1275_Y end - attribute \src "ls180.v:6033.924-6033.1001" - cell $and $and$ls180.v:6033$1277 + attribute \src "ls180.v:6036.924-6036.1001" + cell $and $and$ls180.v:6036$1277 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -255113,10 +257642,10 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] } connect \B \builder_libresocsim_converted_interface_dat_r - connect \Y $and$ls180.v:6033$1277_Y + connect \Y $and$ls180.v:6036$1277_Y end - attribute \src "ls180.v:6043.39-6043.92" - cell $and $and$ls180.v:6043$1281 + attribute \src "ls180.v:6046.39-6046.92" + cell $and $and$ls180.v:6046$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255124,87 +257653,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6043$1281_Y + connect \Y $and$ls180.v:6046$1281_Y end - attribute \src "ls180.v:6043.38-6043.142" - cell $and $and$ls180.v:6043$1283 + attribute \src "ls180.v:6046.38-6046.142" + cell $and $and$ls180.v:6046$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6043$1281_Y - connect \B $eq$ls180.v:6043$1282_Y - connect \Y $and$ls180.v:6043$1283_Y + connect \A $and$ls180.v:6046$1281_Y + connect \B $eq$ls180.v:6046$1282_Y + connect \Y $and$ls180.v:6046$1283_Y end - attribute \src "ls180.v:6044.39-6044.95" - cell $and $and$ls180.v:6044$1285 + attribute \src "ls180.v:6047.39-6047.95" + cell $and $and$ls180.v:6047$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6044$1284_Y - connect \Y $and$ls180.v:6044$1285_Y - end - attribute \src "ls180.v:6044.38-6044.145" - cell $and $and$ls180.v:6044$1287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6044$1285_Y - connect \B $eq$ls180.v:6044$1286_Y - connect \Y $and$ls180.v:6044$1287_Y - end - attribute \src "ls180.v:6046.41-6046.94" - cell $and $and$ls180.v:6046$1288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6046$1288_Y + connect \B $not$ls180.v:6047$1284_Y + connect \Y $and$ls180.v:6047$1285_Y end - attribute \src "ls180.v:6046.40-6046.144" - cell $and $and$ls180.v:6046$1290 + attribute \src "ls180.v:6047.38-6047.145" + cell $and $and$ls180.v:6047$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1288_Y - connect \B $eq$ls180.v:6046$1289_Y - connect \Y $and$ls180.v:6046$1290_Y - end - attribute \src "ls180.v:6047.41-6047.97" - cell $and $and$ls180.v:6047$1292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6047$1291_Y - connect \Y $and$ls180.v:6047$1292_Y - end - attribute \src "ls180.v:6047.40-6047.147" - cell $and $and$ls180.v:6047$1294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1292_Y - connect \B $eq$ls180.v:6047$1293_Y - connect \Y $and$ls180.v:6047$1294_Y + connect \A $and$ls180.v:6047$1285_Y + connect \B $eq$ls180.v:6047$1286_Y + connect \Y $and$ls180.v:6047$1287_Y end attribute \src "ls180.v:6049.41-6049.94" - cell $and $and$ls180.v:6049$1295 + cell $and $and$ls180.v:6049$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255212,43 +257697,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6049$1295_Y + connect \Y $and$ls180.v:6049$1288_Y end attribute \src "ls180.v:6049.40-6049.144" - cell $and $and$ls180.v:6049$1297 + cell $and $and$ls180.v:6049$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1295_Y - connect \B $eq$ls180.v:6049$1296_Y - connect \Y $and$ls180.v:6049$1297_Y + connect \A $and$ls180.v:6049$1288_Y + connect \B $eq$ls180.v:6049$1289_Y + connect \Y $and$ls180.v:6049$1290_Y end attribute \src "ls180.v:6050.41-6050.97" - cell $and $and$ls180.v:6050$1299 + cell $and $and$ls180.v:6050$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6050$1298_Y - connect \Y $and$ls180.v:6050$1299_Y + connect \B $not$ls180.v:6050$1291_Y + connect \Y $and$ls180.v:6050$1292_Y end attribute \src "ls180.v:6050.40-6050.147" - cell $and $and$ls180.v:6050$1301 + cell $and $and$ls180.v:6050$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1299_Y - connect \B $eq$ls180.v:6050$1300_Y - connect \Y $and$ls180.v:6050$1301_Y + connect \A $and$ls180.v:6050$1292_Y + connect \B $eq$ls180.v:6050$1293_Y + connect \Y $and$ls180.v:6050$1294_Y end attribute \src "ls180.v:6052.41-6052.94" - cell $and $and$ls180.v:6052$1302 + cell $and $and$ls180.v:6052$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255256,43 +257741,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6052$1302_Y + connect \Y $and$ls180.v:6052$1295_Y end attribute \src "ls180.v:6052.40-6052.144" - cell $and $and$ls180.v:6052$1304 + cell $and $and$ls180.v:6052$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6052$1302_Y - connect \B $eq$ls180.v:6052$1303_Y - connect \Y $and$ls180.v:6052$1304_Y + connect \A $and$ls180.v:6052$1295_Y + connect \B $eq$ls180.v:6052$1296_Y + connect \Y $and$ls180.v:6052$1297_Y end attribute \src "ls180.v:6053.41-6053.97" - cell $and $and$ls180.v:6053$1306 + cell $and $and$ls180.v:6053$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6053$1305_Y - connect \Y $and$ls180.v:6053$1306_Y + connect \B $not$ls180.v:6053$1298_Y + connect \Y $and$ls180.v:6053$1299_Y end attribute \src "ls180.v:6053.40-6053.147" - cell $and $and$ls180.v:6053$1308 + cell $and $and$ls180.v:6053$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6053$1306_Y - connect \B $eq$ls180.v:6053$1307_Y - connect \Y $and$ls180.v:6053$1308_Y + connect \A $and$ls180.v:6053$1299_Y + connect \B $eq$ls180.v:6053$1300_Y + connect \Y $and$ls180.v:6053$1301_Y end attribute \src "ls180.v:6055.41-6055.94" - cell $and $and$ls180.v:6055$1309 + cell $and $and$ls180.v:6055$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255300,43 +257785,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6055$1309_Y + connect \Y $and$ls180.v:6055$1302_Y end attribute \src "ls180.v:6055.40-6055.144" - cell $and $and$ls180.v:6055$1311 + cell $and $and$ls180.v:6055$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1309_Y - connect \B $eq$ls180.v:6055$1310_Y - connect \Y $and$ls180.v:6055$1311_Y + connect \A $and$ls180.v:6055$1302_Y + connect \B $eq$ls180.v:6055$1303_Y + connect \Y $and$ls180.v:6055$1304_Y end attribute \src "ls180.v:6056.41-6056.97" - cell $and $and$ls180.v:6056$1313 + cell $and $and$ls180.v:6056$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6056$1312_Y - connect \Y $and$ls180.v:6056$1313_Y + connect \B $not$ls180.v:6056$1305_Y + connect \Y $and$ls180.v:6056$1306_Y end attribute \src "ls180.v:6056.40-6056.147" - cell $and $and$ls180.v:6056$1315 + cell $and $and$ls180.v:6056$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1313_Y - connect \B $eq$ls180.v:6056$1314_Y - connect \Y $and$ls180.v:6056$1315_Y + connect \A $and$ls180.v:6056$1306_Y + connect \B $eq$ls180.v:6056$1307_Y + connect \Y $and$ls180.v:6056$1308_Y end - attribute \src "ls180.v:6058.44-6058.97" - cell $and $and$ls180.v:6058$1316 + attribute \src "ls180.v:6058.41-6058.94" + cell $and $and$ls180.v:6058$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255344,43 +257829,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6058$1316_Y + connect \Y $and$ls180.v:6058$1309_Y end - attribute \src "ls180.v:6058.43-6058.147" - cell $and $and$ls180.v:6058$1318 + attribute \src "ls180.v:6058.40-6058.144" + cell $and $and$ls180.v:6058$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1316_Y - connect \B $eq$ls180.v:6058$1317_Y - connect \Y $and$ls180.v:6058$1318_Y + connect \A $and$ls180.v:6058$1309_Y + connect \B $eq$ls180.v:6058$1310_Y + connect \Y $and$ls180.v:6058$1311_Y end - attribute \src "ls180.v:6059.44-6059.100" - cell $and $and$ls180.v:6059$1320 + attribute \src "ls180.v:6059.41-6059.97" + cell $and $and$ls180.v:6059$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6059$1319_Y - connect \Y $and$ls180.v:6059$1320_Y + connect \B $not$ls180.v:6059$1312_Y + connect \Y $and$ls180.v:6059$1313_Y end - attribute \src "ls180.v:6059.43-6059.150" - cell $and $and$ls180.v:6059$1322 + attribute \src "ls180.v:6059.40-6059.147" + cell $and $and$ls180.v:6059$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1320_Y - connect \B $eq$ls180.v:6059$1321_Y - connect \Y $and$ls180.v:6059$1322_Y + connect \A $and$ls180.v:6059$1313_Y + connect \B $eq$ls180.v:6059$1314_Y + connect \Y $and$ls180.v:6059$1315_Y end attribute \src "ls180.v:6061.44-6061.97" - cell $and $and$ls180.v:6061$1323 + cell $and $and$ls180.v:6061$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255388,43 +257873,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6061$1323_Y + connect \Y $and$ls180.v:6061$1316_Y end attribute \src "ls180.v:6061.43-6061.147" - cell $and $and$ls180.v:6061$1325 + cell $and $and$ls180.v:6061$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1323_Y - connect \B $eq$ls180.v:6061$1324_Y - connect \Y $and$ls180.v:6061$1325_Y + connect \A $and$ls180.v:6061$1316_Y + connect \B $eq$ls180.v:6061$1317_Y + connect \Y $and$ls180.v:6061$1318_Y end attribute \src "ls180.v:6062.44-6062.100" - cell $and $and$ls180.v:6062$1327 + cell $and $and$ls180.v:6062$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6062$1326_Y - connect \Y $and$ls180.v:6062$1327_Y + connect \B $not$ls180.v:6062$1319_Y + connect \Y $and$ls180.v:6062$1320_Y end attribute \src "ls180.v:6062.43-6062.150" - cell $and $and$ls180.v:6062$1329 + cell $and $and$ls180.v:6062$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1327_Y - connect \B $eq$ls180.v:6062$1328_Y - connect \Y $and$ls180.v:6062$1329_Y + connect \A $and$ls180.v:6062$1320_Y + connect \B $eq$ls180.v:6062$1321_Y + connect \Y $and$ls180.v:6062$1322_Y end attribute \src "ls180.v:6064.44-6064.97" - cell $and $and$ls180.v:6064$1330 + cell $and $and$ls180.v:6064$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255432,43 +257917,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6064$1330_Y + connect \Y $and$ls180.v:6064$1323_Y end attribute \src "ls180.v:6064.43-6064.147" - cell $and $and$ls180.v:6064$1332 + cell $and $and$ls180.v:6064$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1330_Y - connect \B $eq$ls180.v:6064$1331_Y - connect \Y $and$ls180.v:6064$1332_Y + connect \A $and$ls180.v:6064$1323_Y + connect \B $eq$ls180.v:6064$1324_Y + connect \Y $and$ls180.v:6064$1325_Y end attribute \src "ls180.v:6065.44-6065.100" - cell $and $and$ls180.v:6065$1334 + cell $and $and$ls180.v:6065$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6065$1333_Y - connect \Y $and$ls180.v:6065$1334_Y + connect \B $not$ls180.v:6065$1326_Y + connect \Y $and$ls180.v:6065$1327_Y end attribute \src "ls180.v:6065.43-6065.150" - cell $and $and$ls180.v:6065$1336 + cell $and $and$ls180.v:6065$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1334_Y - connect \B $eq$ls180.v:6065$1335_Y - connect \Y $and$ls180.v:6065$1336_Y + connect \A $and$ls180.v:6065$1327_Y + connect \B $eq$ls180.v:6065$1328_Y + connect \Y $and$ls180.v:6065$1329_Y end attribute \src "ls180.v:6067.44-6067.97" - cell $and $and$ls180.v:6067$1337 + cell $and $and$ls180.v:6067$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255476,87 +257961,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6067$1337_Y + connect \Y $and$ls180.v:6067$1330_Y end attribute \src "ls180.v:6067.43-6067.147" - cell $and $and$ls180.v:6067$1339 + cell $and $and$ls180.v:6067$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1337_Y - connect \B $eq$ls180.v:6067$1338_Y - connect \Y $and$ls180.v:6067$1339_Y + connect \A $and$ls180.v:6067$1330_Y + connect \B $eq$ls180.v:6067$1331_Y + connect \Y $and$ls180.v:6067$1332_Y end attribute \src "ls180.v:6068.44-6068.100" - cell $and $and$ls180.v:6068$1341 + cell $and $and$ls180.v:6068$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6068$1340_Y - connect \Y $and$ls180.v:6068$1341_Y + connect \B $not$ls180.v:6068$1333_Y + connect \Y $and$ls180.v:6068$1334_Y end attribute \src "ls180.v:6068.43-6068.150" - cell $and $and$ls180.v:6068$1343 + cell $and $and$ls180.v:6068$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1341_Y - connect \B $eq$ls180.v:6068$1342_Y - connect \Y $and$ls180.v:6068$1343_Y + connect \A $and$ls180.v:6068$1334_Y + connect \B $eq$ls180.v:6068$1335_Y + connect \Y $and$ls180.v:6068$1336_Y end - attribute \src "ls180.v:6081.36-6081.89" - cell $and $and$ls180.v:6081$1345 + attribute \src "ls180.v:6070.44-6070.97" + cell $and $and$ls180.v:6070$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6081$1345_Y + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6070$1337_Y end - attribute \src "ls180.v:6081.35-6081.139" - cell $and $and$ls180.v:6081$1347 + attribute \src "ls180.v:6070.43-6070.147" + cell $and $and$ls180.v:6070$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6081$1345_Y - connect \B $eq$ls180.v:6081$1346_Y - connect \Y $and$ls180.v:6081$1347_Y + connect \A $and$ls180.v:6070$1337_Y + connect \B $eq$ls180.v:6070$1338_Y + connect \Y $and$ls180.v:6070$1339_Y end - attribute \src "ls180.v:6082.36-6082.92" - cell $and $and$ls180.v:6082$1349 + attribute \src "ls180.v:6071.44-6071.100" + cell $and $and$ls180.v:6071$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6082$1348_Y - connect \Y $and$ls180.v:6082$1349_Y + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6071$1340_Y + connect \Y $and$ls180.v:6071$1341_Y end - attribute \src "ls180.v:6082.35-6082.142" - cell $and $and$ls180.v:6082$1351 + attribute \src "ls180.v:6071.43-6071.150" + cell $and $and$ls180.v:6071$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6082$1349_Y - connect \B $eq$ls180.v:6082$1350_Y - connect \Y $and$ls180.v:6082$1351_Y + connect \A $and$ls180.v:6071$1341_Y + connect \B $eq$ls180.v:6071$1342_Y + connect \Y $and$ls180.v:6071$1343_Y end attribute \src "ls180.v:6084.36-6084.89" - cell $and $and$ls180.v:6084$1352 + cell $and $and$ls180.v:6084$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255564,43 +258049,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6084$1352_Y + connect \Y $and$ls180.v:6084$1345_Y end attribute \src "ls180.v:6084.35-6084.139" - cell $and $and$ls180.v:6084$1354 + cell $and $and$ls180.v:6084$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6084$1352_Y - connect \B $eq$ls180.v:6084$1353_Y - connect \Y $and$ls180.v:6084$1354_Y + connect \A $and$ls180.v:6084$1345_Y + connect \B $eq$ls180.v:6084$1346_Y + connect \Y $and$ls180.v:6084$1347_Y end attribute \src "ls180.v:6085.36-6085.92" - cell $and $and$ls180.v:6085$1356 + cell $and $and$ls180.v:6085$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6085$1355_Y - connect \Y $and$ls180.v:6085$1356_Y + connect \B $not$ls180.v:6085$1348_Y + connect \Y $and$ls180.v:6085$1349_Y end attribute \src "ls180.v:6085.35-6085.142" - cell $and $and$ls180.v:6085$1358 + cell $and $and$ls180.v:6085$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6085$1356_Y - connect \B $eq$ls180.v:6085$1357_Y - connect \Y $and$ls180.v:6085$1358_Y + connect \A $and$ls180.v:6085$1349_Y + connect \B $eq$ls180.v:6085$1350_Y + connect \Y $and$ls180.v:6085$1351_Y end attribute \src "ls180.v:6087.36-6087.89" - cell $and $and$ls180.v:6087$1359 + cell $and $and$ls180.v:6087$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255608,43 +258093,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6087$1359_Y + connect \Y $and$ls180.v:6087$1352_Y end attribute \src "ls180.v:6087.35-6087.139" - cell $and $and$ls180.v:6087$1361 + cell $and $and$ls180.v:6087$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1359_Y - connect \B $eq$ls180.v:6087$1360_Y - connect \Y $and$ls180.v:6087$1361_Y + connect \A $and$ls180.v:6087$1352_Y + connect \B $eq$ls180.v:6087$1353_Y + connect \Y $and$ls180.v:6087$1354_Y end attribute \src "ls180.v:6088.36-6088.92" - cell $and $and$ls180.v:6088$1363 + cell $and $and$ls180.v:6088$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6088$1362_Y - connect \Y $and$ls180.v:6088$1363_Y + connect \B $not$ls180.v:6088$1355_Y + connect \Y $and$ls180.v:6088$1356_Y end attribute \src "ls180.v:6088.35-6088.142" - cell $and $and$ls180.v:6088$1365 + cell $and $and$ls180.v:6088$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$1363_Y - connect \B $eq$ls180.v:6088$1364_Y - connect \Y $and$ls180.v:6088$1365_Y + connect \A $and$ls180.v:6088$1356_Y + connect \B $eq$ls180.v:6088$1357_Y + connect \Y $and$ls180.v:6088$1358_Y end attribute \src "ls180.v:6090.36-6090.89" - cell $and $and$ls180.v:6090$1366 + cell $and $and$ls180.v:6090$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255652,43 +258137,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6090$1366_Y + connect \Y $and$ls180.v:6090$1359_Y end attribute \src "ls180.v:6090.35-6090.139" - cell $and $and$ls180.v:6090$1368 + cell $and $and$ls180.v:6090$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$1366_Y - connect \B $eq$ls180.v:6090$1367_Y - connect \Y $and$ls180.v:6090$1368_Y + connect \A $and$ls180.v:6090$1359_Y + connect \B $eq$ls180.v:6090$1360_Y + connect \Y $and$ls180.v:6090$1361_Y end attribute \src "ls180.v:6091.36-6091.92" - cell $and $and$ls180.v:6091$1370 + cell $and $and$ls180.v:6091$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6091$1369_Y - connect \Y $and$ls180.v:6091$1370_Y + connect \B $not$ls180.v:6091$1362_Y + connect \Y $and$ls180.v:6091$1363_Y end attribute \src "ls180.v:6091.35-6091.142" - cell $and $and$ls180.v:6091$1372 + cell $and $and$ls180.v:6091$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$1370_Y - connect \B $eq$ls180.v:6091$1371_Y - connect \Y $and$ls180.v:6091$1372_Y + connect \A $and$ls180.v:6091$1363_Y + connect \B $eq$ls180.v:6091$1364_Y + connect \Y $and$ls180.v:6091$1365_Y end - attribute \src "ls180.v:6093.37-6093.90" - cell $and $and$ls180.v:6093$1373 + attribute \src "ls180.v:6093.36-6093.89" + cell $and $and$ls180.v:6093$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255696,43 +258181,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6093$1373_Y + connect \Y $and$ls180.v:6093$1366_Y end - attribute \src "ls180.v:6093.36-6093.140" - cell $and $and$ls180.v:6093$1375 + attribute \src "ls180.v:6093.35-6093.139" + cell $and $and$ls180.v:6093$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6093$1373_Y - connect \B $eq$ls180.v:6093$1374_Y - connect \Y $and$ls180.v:6093$1375_Y + connect \A $and$ls180.v:6093$1366_Y + connect \B $eq$ls180.v:6093$1367_Y + connect \Y $and$ls180.v:6093$1368_Y end - attribute \src "ls180.v:6094.37-6094.93" - cell $and $and$ls180.v:6094$1377 + attribute \src "ls180.v:6094.36-6094.92" + cell $and $and$ls180.v:6094$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6094$1376_Y - connect \Y $and$ls180.v:6094$1377_Y + connect \B $not$ls180.v:6094$1369_Y + connect \Y $and$ls180.v:6094$1370_Y end - attribute \src "ls180.v:6094.36-6094.143" - cell $and $and$ls180.v:6094$1379 + attribute \src "ls180.v:6094.35-6094.142" + cell $and $and$ls180.v:6094$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6094$1377_Y - connect \B $eq$ls180.v:6094$1378_Y - connect \Y $and$ls180.v:6094$1379_Y + connect \A $and$ls180.v:6094$1370_Y + connect \B $eq$ls180.v:6094$1371_Y + connect \Y $and$ls180.v:6094$1372_Y end attribute \src "ls180.v:6096.37-6096.90" - cell $and $and$ls180.v:6096$1380 + cell $and $and$ls180.v:6096$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255740,87 +258225,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6096$1380_Y + connect \Y $and$ls180.v:6096$1373_Y end attribute \src "ls180.v:6096.36-6096.140" - cell $and $and$ls180.v:6096$1382 + cell $and $and$ls180.v:6096$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6096$1380_Y - connect \B $eq$ls180.v:6096$1381_Y - connect \Y $and$ls180.v:6096$1382_Y + connect \A $and$ls180.v:6096$1373_Y + connect \B $eq$ls180.v:6096$1374_Y + connect \Y $and$ls180.v:6096$1375_Y end attribute \src "ls180.v:6097.37-6097.93" - cell $and $and$ls180.v:6097$1384 + cell $and $and$ls180.v:6097$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6097$1383_Y - connect \Y $and$ls180.v:6097$1384_Y + connect \B $not$ls180.v:6097$1376_Y + connect \Y $and$ls180.v:6097$1377_Y end attribute \src "ls180.v:6097.36-6097.143" - cell $and $and$ls180.v:6097$1386 + cell $and $and$ls180.v:6097$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6097$1384_Y - connect \B $eq$ls180.v:6097$1385_Y - connect \Y $and$ls180.v:6097$1386_Y + connect \A $and$ls180.v:6097$1377_Y + connect \B $eq$ls180.v:6097$1378_Y + connect \Y $and$ls180.v:6097$1379_Y end - attribute \src "ls180.v:6107.35-6107.88" - cell $and $and$ls180.v:6107$1388 + attribute \src "ls180.v:6099.37-6099.90" + cell $and $and$ls180.v:6099$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:6107$1388_Y + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6099$1380_Y end - attribute \src "ls180.v:6107.34-6107.136" - cell $and $and$ls180.v:6107$1390 + attribute \src "ls180.v:6099.36-6099.140" + cell $and $and$ls180.v:6099$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6107$1388_Y - connect \B $eq$ls180.v:6107$1389_Y - connect \Y $and$ls180.v:6107$1390_Y + connect \A $and$ls180.v:6099$1380_Y + connect \B $eq$ls180.v:6099$1381_Y + connect \Y $and$ls180.v:6099$1382_Y end - attribute \src "ls180.v:6108.35-6108.91" - cell $and $and$ls180.v:6108$1392 + attribute \src "ls180.v:6100.37-6100.93" + cell $and $and$ls180.v:6100$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:6108$1391_Y - connect \Y $and$ls180.v:6108$1392_Y + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6100$1383_Y + connect \Y $and$ls180.v:6100$1384_Y end - attribute \src "ls180.v:6108.34-6108.139" - cell $and $and$ls180.v:6108$1394 + attribute \src "ls180.v:6100.36-6100.143" + cell $and $and$ls180.v:6100$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6108$1392_Y - connect \B $eq$ls180.v:6108$1393_Y - connect \Y $and$ls180.v:6108$1394_Y + connect \A $and$ls180.v:6100$1384_Y + connect \B $eq$ls180.v:6100$1385_Y + connect \Y $and$ls180.v:6100$1386_Y end - attribute \src "ls180.v:6110.34-6110.87" - cell $and $and$ls180.v:6110$1395 + attribute \src "ls180.v:6110.35-6110.88" + cell $and $and$ls180.v:6110$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255828,87 +258313,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:6110$1395_Y + connect \Y $and$ls180.v:6110$1388_Y end - attribute \src "ls180.v:6110.33-6110.135" - cell $and $and$ls180.v:6110$1397 + attribute \src "ls180.v:6110.34-6110.136" + cell $and $and$ls180.v:6110$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6110$1395_Y - connect \B $eq$ls180.v:6110$1396_Y - connect \Y $and$ls180.v:6110$1397_Y + connect \A $and$ls180.v:6110$1388_Y + connect \B $eq$ls180.v:6110$1389_Y + connect \Y $and$ls180.v:6110$1390_Y end - attribute \src "ls180.v:6111.34-6111.90" - cell $and $and$ls180.v:6111$1399 + attribute \src "ls180.v:6111.35-6111.91" + cell $and $and$ls180.v:6111$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:6111$1398_Y - connect \Y $and$ls180.v:6111$1399_Y + connect \B $not$ls180.v:6111$1391_Y + connect \Y $and$ls180.v:6111$1392_Y end - attribute \src "ls180.v:6111.33-6111.138" - cell $and $and$ls180.v:6111$1401 + attribute \src "ls180.v:6111.34-6111.139" + cell $and $and$ls180.v:6111$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1399_Y - connect \B $eq$ls180.v:6111$1400_Y - connect \Y $and$ls180.v:6111$1401_Y + connect \A $and$ls180.v:6111$1392_Y + connect \B $eq$ls180.v:6111$1393_Y + connect \Y $and$ls180.v:6111$1394_Y end - attribute \src "ls180.v:6121.40-6121.93" - cell $and $and$ls180.v:6121$1403 + attribute \src "ls180.v:6113.34-6113.87" + cell $and $and$ls180.v:6113$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6121$1403_Y + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:6113$1395_Y end - attribute \src "ls180.v:6121.39-6121.143" - cell $and $and$ls180.v:6121$1405 + attribute \src "ls180.v:6113.33-6113.135" + cell $and $and$ls180.v:6113$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6121$1403_Y - connect \B $eq$ls180.v:6121$1404_Y - connect \Y $and$ls180.v:6121$1405_Y + connect \A $and$ls180.v:6113$1395_Y + connect \B $eq$ls180.v:6113$1396_Y + connect \Y $and$ls180.v:6113$1397_Y end - attribute \src "ls180.v:6122.40-6122.96" - cell $and $and$ls180.v:6122$1407 + attribute \src "ls180.v:6114.34-6114.90" + cell $and $and$ls180.v:6114$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6122$1406_Y - connect \Y $and$ls180.v:6122$1407_Y + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:6114$1398_Y + connect \Y $and$ls180.v:6114$1399_Y end - attribute \src "ls180.v:6122.39-6122.146" - cell $and $and$ls180.v:6122$1409 + attribute \src "ls180.v:6114.33-6114.138" + cell $and $and$ls180.v:6114$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6122$1407_Y - connect \B $eq$ls180.v:6122$1408_Y - connect \Y $and$ls180.v:6122$1409_Y + connect \A $and$ls180.v:6114$1399_Y + connect \B $eq$ls180.v:6114$1400_Y + connect \Y $and$ls180.v:6114$1401_Y end - attribute \src "ls180.v:6124.39-6124.92" - cell $and $and$ls180.v:6124$1410 + attribute \src "ls180.v:6124.40-6124.93" + cell $and $and$ls180.v:6124$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255916,43 +258401,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6124$1410_Y + connect \Y $and$ls180.v:6124$1403_Y end - attribute \src "ls180.v:6124.38-6124.142" - cell $and $and$ls180.v:6124$1412 + attribute \src "ls180.v:6124.39-6124.143" + cell $and $and$ls180.v:6124$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1410_Y - connect \B $eq$ls180.v:6124$1411_Y - connect \Y $and$ls180.v:6124$1412_Y + connect \A $and$ls180.v:6124$1403_Y + connect \B $eq$ls180.v:6124$1404_Y + connect \Y $and$ls180.v:6124$1405_Y end - attribute \src "ls180.v:6125.39-6125.95" - cell $and $and$ls180.v:6125$1414 + attribute \src "ls180.v:6125.40-6125.96" + cell $and $and$ls180.v:6125$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6125$1413_Y - connect \Y $and$ls180.v:6125$1414_Y + connect \B $not$ls180.v:6125$1406_Y + connect \Y $and$ls180.v:6125$1407_Y end - attribute \src "ls180.v:6125.38-6125.145" - cell $and $and$ls180.v:6125$1416 + attribute \src "ls180.v:6125.39-6125.146" + cell $and $and$ls180.v:6125$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6125$1414_Y - connect \B $eq$ls180.v:6125$1415_Y - connect \Y $and$ls180.v:6125$1416_Y + connect \A $and$ls180.v:6125$1407_Y + connect \B $eq$ls180.v:6125$1408_Y + connect \Y $and$ls180.v:6125$1409_Y end attribute \src "ls180.v:6127.39-6127.92" - cell $and $and$ls180.v:6127$1417 + cell $and $and$ls180.v:6127$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255960,43 +258445,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6127$1417_Y + connect \Y $and$ls180.v:6127$1410_Y end attribute \src "ls180.v:6127.38-6127.142" - cell $and $and$ls180.v:6127$1419 + cell $and $and$ls180.v:6127$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1417_Y - connect \B $eq$ls180.v:6127$1418_Y - connect \Y $and$ls180.v:6127$1419_Y + connect \A $and$ls180.v:6127$1410_Y + connect \B $eq$ls180.v:6127$1411_Y + connect \Y $and$ls180.v:6127$1412_Y end attribute \src "ls180.v:6128.39-6128.95" - cell $and $and$ls180.v:6128$1421 + cell $and $and$ls180.v:6128$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6128$1420_Y - connect \Y $and$ls180.v:6128$1421_Y + connect \B $not$ls180.v:6128$1413_Y + connect \Y $and$ls180.v:6128$1414_Y end attribute \src "ls180.v:6128.38-6128.145" - cell $and $and$ls180.v:6128$1423 + cell $and $and$ls180.v:6128$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6128$1421_Y - connect \B $eq$ls180.v:6128$1422_Y - connect \Y $and$ls180.v:6128$1423_Y + connect \A $and$ls180.v:6128$1414_Y + connect \B $eq$ls180.v:6128$1415_Y + connect \Y $and$ls180.v:6128$1416_Y end attribute \src "ls180.v:6130.39-6130.92" - cell $and $and$ls180.v:6130$1424 + cell $and $and$ls180.v:6130$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256004,43 +258489,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6130$1424_Y + connect \Y $and$ls180.v:6130$1417_Y end attribute \src "ls180.v:6130.38-6130.142" - cell $and $and$ls180.v:6130$1426 + cell $and $and$ls180.v:6130$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1424_Y - connect \B $eq$ls180.v:6130$1425_Y - connect \Y $and$ls180.v:6130$1426_Y + connect \A $and$ls180.v:6130$1417_Y + connect \B $eq$ls180.v:6130$1418_Y + connect \Y $and$ls180.v:6130$1419_Y end attribute \src "ls180.v:6131.39-6131.95" - cell $and $and$ls180.v:6131$1428 + cell $and $and$ls180.v:6131$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6131$1427_Y - connect \Y $and$ls180.v:6131$1428_Y + connect \B $not$ls180.v:6131$1420_Y + connect \Y $and$ls180.v:6131$1421_Y end attribute \src "ls180.v:6131.38-6131.145" - cell $and $and$ls180.v:6131$1430 + cell $and $and$ls180.v:6131$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6131$1428_Y - connect \B $eq$ls180.v:6131$1429_Y - connect \Y $and$ls180.v:6131$1430_Y + connect \A $and$ls180.v:6131$1421_Y + connect \B $eq$ls180.v:6131$1422_Y + connect \Y $and$ls180.v:6131$1423_Y end attribute \src "ls180.v:6133.39-6133.92" - cell $and $and$ls180.v:6133$1431 + cell $and $and$ls180.v:6133$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256048,43 +258533,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6133$1431_Y + connect \Y $and$ls180.v:6133$1424_Y end attribute \src "ls180.v:6133.38-6133.142" - cell $and $and$ls180.v:6133$1433 + cell $and $and$ls180.v:6133$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1431_Y - connect \B $eq$ls180.v:6133$1432_Y - connect \Y $and$ls180.v:6133$1433_Y + connect \A $and$ls180.v:6133$1424_Y + connect \B $eq$ls180.v:6133$1425_Y + connect \Y $and$ls180.v:6133$1426_Y end attribute \src "ls180.v:6134.39-6134.95" - cell $and $and$ls180.v:6134$1435 + cell $and $and$ls180.v:6134$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6134$1434_Y - connect \Y $and$ls180.v:6134$1435_Y + connect \B $not$ls180.v:6134$1427_Y + connect \Y $and$ls180.v:6134$1428_Y end attribute \src "ls180.v:6134.38-6134.145" - cell $and $and$ls180.v:6134$1437 + cell $and $and$ls180.v:6134$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6134$1435_Y - connect \B $eq$ls180.v:6134$1436_Y - connect \Y $and$ls180.v:6134$1437_Y + connect \A $and$ls180.v:6134$1428_Y + connect \B $eq$ls180.v:6134$1429_Y + connect \Y $and$ls180.v:6134$1430_Y end - attribute \src "ls180.v:6136.40-6136.93" - cell $and $and$ls180.v:6136$1438 + attribute \src "ls180.v:6136.39-6136.92" + cell $and $and$ls180.v:6136$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256092,43 +258577,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6136$1438_Y + connect \Y $and$ls180.v:6136$1431_Y end - attribute \src "ls180.v:6136.39-6136.143" - cell $and $and$ls180.v:6136$1440 + attribute \src "ls180.v:6136.38-6136.142" + cell $and $and$ls180.v:6136$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1438_Y - connect \B $eq$ls180.v:6136$1439_Y - connect \Y $and$ls180.v:6136$1440_Y + connect \A $and$ls180.v:6136$1431_Y + connect \B $eq$ls180.v:6136$1432_Y + connect \Y $and$ls180.v:6136$1433_Y end - attribute \src "ls180.v:6137.40-6137.96" - cell $and $and$ls180.v:6137$1442 + attribute \src "ls180.v:6137.39-6137.95" + cell $and $and$ls180.v:6137$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6137$1441_Y - connect \Y $and$ls180.v:6137$1442_Y + connect \B $not$ls180.v:6137$1434_Y + connect \Y $and$ls180.v:6137$1435_Y end - attribute \src "ls180.v:6137.39-6137.146" - cell $and $and$ls180.v:6137$1444 + attribute \src "ls180.v:6137.38-6137.145" + cell $and $and$ls180.v:6137$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6137$1442_Y - connect \B $eq$ls180.v:6137$1443_Y - connect \Y $and$ls180.v:6137$1444_Y + connect \A $and$ls180.v:6137$1435_Y + connect \B $eq$ls180.v:6137$1436_Y + connect \Y $and$ls180.v:6137$1437_Y end attribute \src "ls180.v:6139.40-6139.93" - cell $and $and$ls180.v:6139$1445 + cell $and $and$ls180.v:6139$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256136,43 +258621,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6139$1445_Y + connect \Y $and$ls180.v:6139$1438_Y end attribute \src "ls180.v:6139.39-6139.143" - cell $and $and$ls180.v:6139$1447 + cell $and $and$ls180.v:6139$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1445_Y - connect \B $eq$ls180.v:6139$1446_Y - connect \Y $and$ls180.v:6139$1447_Y + connect \A $and$ls180.v:6139$1438_Y + connect \B $eq$ls180.v:6139$1439_Y + connect \Y $and$ls180.v:6139$1440_Y end attribute \src "ls180.v:6140.40-6140.96" - cell $and $and$ls180.v:6140$1449 + cell $and $and$ls180.v:6140$1442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6140$1448_Y - connect \Y $and$ls180.v:6140$1449_Y + connect \B $not$ls180.v:6140$1441_Y + connect \Y $and$ls180.v:6140$1442_Y end attribute \src "ls180.v:6140.39-6140.146" - cell $and $and$ls180.v:6140$1451 + cell $and $and$ls180.v:6140$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6140$1449_Y - connect \B $eq$ls180.v:6140$1450_Y - connect \Y $and$ls180.v:6140$1451_Y + connect \A $and$ls180.v:6140$1442_Y + connect \B $eq$ls180.v:6140$1443_Y + connect \Y $and$ls180.v:6140$1444_Y end attribute \src "ls180.v:6142.40-6142.93" - cell $and $and$ls180.v:6142$1452 + cell $and $and$ls180.v:6142$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256180,43 +258665,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6142$1452_Y + connect \Y $and$ls180.v:6142$1445_Y end attribute \src "ls180.v:6142.39-6142.143" - cell $and $and$ls180.v:6142$1454 + cell $and $and$ls180.v:6142$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1452_Y - connect \B $eq$ls180.v:6142$1453_Y - connect \Y $and$ls180.v:6142$1454_Y + connect \A $and$ls180.v:6142$1445_Y + connect \B $eq$ls180.v:6142$1446_Y + connect \Y $and$ls180.v:6142$1447_Y end attribute \src "ls180.v:6143.40-6143.96" - cell $and $and$ls180.v:6143$1456 + cell $and $and$ls180.v:6143$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6143$1455_Y - connect \Y $and$ls180.v:6143$1456_Y + connect \B $not$ls180.v:6143$1448_Y + connect \Y $and$ls180.v:6143$1449_Y end attribute \src "ls180.v:6143.39-6143.146" - cell $and $and$ls180.v:6143$1458 + cell $and $and$ls180.v:6143$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6143$1456_Y - connect \B $eq$ls180.v:6143$1457_Y - connect \Y $and$ls180.v:6143$1458_Y + connect \A $and$ls180.v:6143$1449_Y + connect \B $eq$ls180.v:6143$1450_Y + connect \Y $and$ls180.v:6143$1451_Y end attribute \src "ls180.v:6145.40-6145.93" - cell $and $and$ls180.v:6145$1459 + cell $and $and$ls180.v:6145$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256224,87 +258709,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6145$1459_Y + connect \Y $and$ls180.v:6145$1452_Y end attribute \src "ls180.v:6145.39-6145.143" - cell $and $and$ls180.v:6145$1461 + cell $and $and$ls180.v:6145$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1459_Y - connect \B $eq$ls180.v:6145$1460_Y - connect \Y $and$ls180.v:6145$1461_Y + connect \A $and$ls180.v:6145$1452_Y + connect \B $eq$ls180.v:6145$1453_Y + connect \Y $and$ls180.v:6145$1454_Y end attribute \src "ls180.v:6146.40-6146.96" - cell $and $and$ls180.v:6146$1463 + cell $and $and$ls180.v:6146$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6146$1462_Y - connect \Y $and$ls180.v:6146$1463_Y + connect \B $not$ls180.v:6146$1455_Y + connect \Y $and$ls180.v:6146$1456_Y end attribute \src "ls180.v:6146.39-6146.146" - cell $and $and$ls180.v:6146$1465 + cell $and $and$ls180.v:6146$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6146$1463_Y - connect \B $eq$ls180.v:6146$1464_Y - connect \Y $and$ls180.v:6146$1465_Y + connect \A $and$ls180.v:6146$1456_Y + connect \B $eq$ls180.v:6146$1457_Y + connect \Y $and$ls180.v:6146$1458_Y end - attribute \src "ls180.v:6158.40-6158.93" - cell $and $and$ls180.v:6158$1467 + attribute \src "ls180.v:6148.40-6148.93" + cell $and $and$ls180.v:6148$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6158$1467_Y + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6148$1459_Y end - attribute \src "ls180.v:6158.39-6158.143" - cell $and $and$ls180.v:6158$1469 + attribute \src "ls180.v:6148.39-6148.143" + cell $and $and$ls180.v:6148$1461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6158$1467_Y - connect \B $eq$ls180.v:6158$1468_Y - connect \Y $and$ls180.v:6158$1469_Y + connect \A $and$ls180.v:6148$1459_Y + connect \B $eq$ls180.v:6148$1460_Y + connect \Y $and$ls180.v:6148$1461_Y end - attribute \src "ls180.v:6159.40-6159.96" - cell $and $and$ls180.v:6159$1471 + attribute \src "ls180.v:6149.40-6149.96" + cell $and $and$ls180.v:6149$1463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6159$1470_Y - connect \Y $and$ls180.v:6159$1471_Y + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6149$1462_Y + connect \Y $and$ls180.v:6149$1463_Y end - attribute \src "ls180.v:6159.39-6159.146" - cell $and $and$ls180.v:6159$1473 + attribute \src "ls180.v:6149.39-6149.146" + cell $and $and$ls180.v:6149$1465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6159$1471_Y - connect \B $eq$ls180.v:6159$1472_Y - connect \Y $and$ls180.v:6159$1473_Y + connect \A $and$ls180.v:6149$1463_Y + connect \B $eq$ls180.v:6149$1464_Y + connect \Y $and$ls180.v:6149$1465_Y end - attribute \src "ls180.v:6161.39-6161.92" - cell $and $and$ls180.v:6161$1474 + attribute \src "ls180.v:6161.40-6161.93" + cell $and $and$ls180.v:6161$1467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256312,43 +258797,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6161$1474_Y + connect \Y $and$ls180.v:6161$1467_Y end - attribute \src "ls180.v:6161.38-6161.142" - cell $and $and$ls180.v:6161$1476 + attribute \src "ls180.v:6161.39-6161.143" + cell $and $and$ls180.v:6161$1469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6161$1474_Y - connect \B $eq$ls180.v:6161$1475_Y - connect \Y $and$ls180.v:6161$1476_Y + connect \A $and$ls180.v:6161$1467_Y + connect \B $eq$ls180.v:6161$1468_Y + connect \Y $and$ls180.v:6161$1469_Y end - attribute \src "ls180.v:6162.39-6162.95" - cell $and $and$ls180.v:6162$1478 + attribute \src "ls180.v:6162.40-6162.96" + cell $and $and$ls180.v:6162$1471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6162$1477_Y - connect \Y $and$ls180.v:6162$1478_Y + connect \B $not$ls180.v:6162$1470_Y + connect \Y $and$ls180.v:6162$1471_Y end - attribute \src "ls180.v:6162.38-6162.145" - cell $and $and$ls180.v:6162$1480 + attribute \src "ls180.v:6162.39-6162.146" + cell $and $and$ls180.v:6162$1473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1478_Y - connect \B $eq$ls180.v:6162$1479_Y - connect \Y $and$ls180.v:6162$1480_Y + connect \A $and$ls180.v:6162$1471_Y + connect \B $eq$ls180.v:6162$1472_Y + connect \Y $and$ls180.v:6162$1473_Y end attribute \src "ls180.v:6164.39-6164.92" - cell $and $and$ls180.v:6164$1481 + cell $and $and$ls180.v:6164$1474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256356,43 +258841,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6164$1481_Y + connect \Y $and$ls180.v:6164$1474_Y end attribute \src "ls180.v:6164.38-6164.142" - cell $and $and$ls180.v:6164$1483 + cell $and $and$ls180.v:6164$1476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6164$1481_Y - connect \B $eq$ls180.v:6164$1482_Y - connect \Y $and$ls180.v:6164$1483_Y + connect \A $and$ls180.v:6164$1474_Y + connect \B $eq$ls180.v:6164$1475_Y + connect \Y $and$ls180.v:6164$1476_Y end attribute \src "ls180.v:6165.39-6165.95" - cell $and $and$ls180.v:6165$1485 + cell $and $and$ls180.v:6165$1478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6165$1484_Y - connect \Y $and$ls180.v:6165$1485_Y + connect \B $not$ls180.v:6165$1477_Y + connect \Y $and$ls180.v:6165$1478_Y end attribute \src "ls180.v:6165.38-6165.145" - cell $and $and$ls180.v:6165$1487 + cell $and $and$ls180.v:6165$1480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6165$1485_Y - connect \B $eq$ls180.v:6165$1486_Y - connect \Y $and$ls180.v:6165$1487_Y + connect \A $and$ls180.v:6165$1478_Y + connect \B $eq$ls180.v:6165$1479_Y + connect \Y $and$ls180.v:6165$1480_Y end attribute \src "ls180.v:6167.39-6167.92" - cell $and $and$ls180.v:6167$1488 + cell $and $and$ls180.v:6167$1481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256400,43 +258885,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6167$1488_Y + connect \Y $and$ls180.v:6167$1481_Y end attribute \src "ls180.v:6167.38-6167.142" - cell $and $and$ls180.v:6167$1490 + cell $and $and$ls180.v:6167$1483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6167$1488_Y - connect \B $eq$ls180.v:6167$1489_Y - connect \Y $and$ls180.v:6167$1490_Y + connect \A $and$ls180.v:6167$1481_Y + connect \B $eq$ls180.v:6167$1482_Y + connect \Y $and$ls180.v:6167$1483_Y end attribute \src "ls180.v:6168.39-6168.95" - cell $and $and$ls180.v:6168$1492 + cell $and $and$ls180.v:6168$1485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6168$1491_Y - connect \Y $and$ls180.v:6168$1492_Y + connect \B $not$ls180.v:6168$1484_Y + connect \Y $and$ls180.v:6168$1485_Y end attribute \src "ls180.v:6168.38-6168.145" - cell $and $and$ls180.v:6168$1494 + cell $and $and$ls180.v:6168$1487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6168$1492_Y - connect \B $eq$ls180.v:6168$1493_Y - connect \Y $and$ls180.v:6168$1494_Y + connect \A $and$ls180.v:6168$1485_Y + connect \B $eq$ls180.v:6168$1486_Y + connect \Y $and$ls180.v:6168$1487_Y end attribute \src "ls180.v:6170.39-6170.92" - cell $and $and$ls180.v:6170$1495 + cell $and $and$ls180.v:6170$1488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256444,43 +258929,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6170$1495_Y + connect \Y $and$ls180.v:6170$1488_Y end attribute \src "ls180.v:6170.38-6170.142" - cell $and $and$ls180.v:6170$1497 + cell $and $and$ls180.v:6170$1490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6170$1495_Y - connect \B $eq$ls180.v:6170$1496_Y - connect \Y $and$ls180.v:6170$1497_Y + connect \A $and$ls180.v:6170$1488_Y + connect \B $eq$ls180.v:6170$1489_Y + connect \Y $and$ls180.v:6170$1490_Y end attribute \src "ls180.v:6171.39-6171.95" - cell $and $and$ls180.v:6171$1499 + cell $and $and$ls180.v:6171$1492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6171$1498_Y - connect \Y $and$ls180.v:6171$1499_Y + connect \B $not$ls180.v:6171$1491_Y + connect \Y $and$ls180.v:6171$1492_Y end attribute \src "ls180.v:6171.38-6171.145" - cell $and $and$ls180.v:6171$1501 + cell $and $and$ls180.v:6171$1494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6171$1499_Y - connect \B $eq$ls180.v:6171$1500_Y - connect \Y $and$ls180.v:6171$1501_Y + connect \A $and$ls180.v:6171$1492_Y + connect \B $eq$ls180.v:6171$1493_Y + connect \Y $and$ls180.v:6171$1494_Y end - attribute \src "ls180.v:6173.40-6173.93" - cell $and $and$ls180.v:6173$1502 + attribute \src "ls180.v:6173.39-6173.92" + cell $and $and$ls180.v:6173$1495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256488,43 +258973,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6173$1502_Y + connect \Y $and$ls180.v:6173$1495_Y end - attribute \src "ls180.v:6173.39-6173.143" - cell $and $and$ls180.v:6173$1504 + attribute \src "ls180.v:6173.38-6173.142" + cell $and $and$ls180.v:6173$1497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6173$1502_Y - connect \B $eq$ls180.v:6173$1503_Y - connect \Y $and$ls180.v:6173$1504_Y + connect \A $and$ls180.v:6173$1495_Y + connect \B $eq$ls180.v:6173$1496_Y + connect \Y $and$ls180.v:6173$1497_Y end - attribute \src "ls180.v:6174.40-6174.96" - cell $and $and$ls180.v:6174$1506 + attribute \src "ls180.v:6174.39-6174.95" + cell $and $and$ls180.v:6174$1499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6174$1505_Y - connect \Y $and$ls180.v:6174$1506_Y + connect \B $not$ls180.v:6174$1498_Y + connect \Y $and$ls180.v:6174$1499_Y end - attribute \src "ls180.v:6174.39-6174.146" - cell $and $and$ls180.v:6174$1508 + attribute \src "ls180.v:6174.38-6174.145" + cell $and $and$ls180.v:6174$1501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6174$1506_Y - connect \B $eq$ls180.v:6174$1507_Y - connect \Y $and$ls180.v:6174$1508_Y + connect \A $and$ls180.v:6174$1499_Y + connect \B $eq$ls180.v:6174$1500_Y + connect \Y $and$ls180.v:6174$1501_Y end attribute \src "ls180.v:6176.40-6176.93" - cell $and $and$ls180.v:6176$1509 + cell $and $and$ls180.v:6176$1502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256532,43 +259017,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6176$1509_Y + connect \Y $and$ls180.v:6176$1502_Y end attribute \src "ls180.v:6176.39-6176.143" - cell $and $and$ls180.v:6176$1511 + cell $and $and$ls180.v:6176$1504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6176$1509_Y - connect \B $eq$ls180.v:6176$1510_Y - connect \Y $and$ls180.v:6176$1511_Y + connect \A $and$ls180.v:6176$1502_Y + connect \B $eq$ls180.v:6176$1503_Y + connect \Y $and$ls180.v:6176$1504_Y end attribute \src "ls180.v:6177.40-6177.96" - cell $and $and$ls180.v:6177$1513 + cell $and $and$ls180.v:6177$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6177$1512_Y - connect \Y $and$ls180.v:6177$1513_Y + connect \B $not$ls180.v:6177$1505_Y + connect \Y $and$ls180.v:6177$1506_Y end attribute \src "ls180.v:6177.39-6177.146" - cell $and $and$ls180.v:6177$1515 + cell $and $and$ls180.v:6177$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6177$1513_Y - connect \B $eq$ls180.v:6177$1514_Y - connect \Y $and$ls180.v:6177$1515_Y + connect \A $and$ls180.v:6177$1506_Y + connect \B $eq$ls180.v:6177$1507_Y + connect \Y $and$ls180.v:6177$1508_Y end attribute \src "ls180.v:6179.40-6179.93" - cell $and $and$ls180.v:6179$1516 + cell $and $and$ls180.v:6179$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256576,43 +259061,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6179$1516_Y + connect \Y $and$ls180.v:6179$1509_Y end attribute \src "ls180.v:6179.39-6179.143" - cell $and $and$ls180.v:6179$1518 + cell $and $and$ls180.v:6179$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6179$1516_Y - connect \B $eq$ls180.v:6179$1517_Y - connect \Y $and$ls180.v:6179$1518_Y + connect \A $and$ls180.v:6179$1509_Y + connect \B $eq$ls180.v:6179$1510_Y + connect \Y $and$ls180.v:6179$1511_Y end attribute \src "ls180.v:6180.40-6180.96" - cell $and $and$ls180.v:6180$1520 + cell $and $and$ls180.v:6180$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6180$1519_Y - connect \Y $and$ls180.v:6180$1520_Y + connect \B $not$ls180.v:6180$1512_Y + connect \Y $and$ls180.v:6180$1513_Y end attribute \src "ls180.v:6180.39-6180.146" - cell $and $and$ls180.v:6180$1522 + cell $and $and$ls180.v:6180$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6180$1520_Y - connect \B $eq$ls180.v:6180$1521_Y - connect \Y $and$ls180.v:6180$1522_Y + connect \A $and$ls180.v:6180$1513_Y + connect \B $eq$ls180.v:6180$1514_Y + connect \Y $and$ls180.v:6180$1515_Y end attribute \src "ls180.v:6182.40-6182.93" - cell $and $and$ls180.v:6182$1523 + cell $and $and$ls180.v:6182$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256620,87 +259105,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6182$1523_Y + connect \Y $and$ls180.v:6182$1516_Y end attribute \src "ls180.v:6182.39-6182.143" - cell $and $and$ls180.v:6182$1525 + cell $and $and$ls180.v:6182$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6182$1523_Y - connect \B $eq$ls180.v:6182$1524_Y - connect \Y $and$ls180.v:6182$1525_Y + connect \A $and$ls180.v:6182$1516_Y + connect \B $eq$ls180.v:6182$1517_Y + connect \Y $and$ls180.v:6182$1518_Y end attribute \src "ls180.v:6183.40-6183.96" - cell $and $and$ls180.v:6183$1527 + cell $and $and$ls180.v:6183$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6183$1526_Y - connect \Y $and$ls180.v:6183$1527_Y + connect \B $not$ls180.v:6183$1519_Y + connect \Y $and$ls180.v:6183$1520_Y end attribute \src "ls180.v:6183.39-6183.146" - cell $and $and$ls180.v:6183$1529 + cell $and $and$ls180.v:6183$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6183$1527_Y - connect \B $eq$ls180.v:6183$1528_Y - connect \Y $and$ls180.v:6183$1529_Y + connect \A $and$ls180.v:6183$1520_Y + connect \B $eq$ls180.v:6183$1521_Y + connect \Y $and$ls180.v:6183$1522_Y end - attribute \src "ls180.v:6195.42-6195.95" - cell $and $and$ls180.v:6195$1531 + attribute \src "ls180.v:6185.40-6185.93" + cell $and $and$ls180.v:6185$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6195$1531_Y + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6185$1523_Y end - attribute \src "ls180.v:6195.41-6195.145" - cell $and $and$ls180.v:6195$1533 + attribute \src "ls180.v:6185.39-6185.143" + cell $and $and$ls180.v:6185$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6195$1531_Y - connect \B $eq$ls180.v:6195$1532_Y - connect \Y $and$ls180.v:6195$1533_Y + connect \A $and$ls180.v:6185$1523_Y + connect \B $eq$ls180.v:6185$1524_Y + connect \Y $and$ls180.v:6185$1525_Y end - attribute \src "ls180.v:6196.42-6196.98" - cell $and $and$ls180.v:6196$1535 + attribute \src "ls180.v:6186.40-6186.96" + cell $and $and$ls180.v:6186$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6196$1534_Y - connect \Y $and$ls180.v:6196$1535_Y + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6186$1526_Y + connect \Y $and$ls180.v:6186$1527_Y end - attribute \src "ls180.v:6196.41-6196.148" - cell $and $and$ls180.v:6196$1537 + attribute \src "ls180.v:6186.39-6186.146" + cell $and $and$ls180.v:6186$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6196$1535_Y - connect \B $eq$ls180.v:6196$1536_Y - connect \Y $and$ls180.v:6196$1537_Y + connect \A $and$ls180.v:6186$1527_Y + connect \B $eq$ls180.v:6186$1528_Y + connect \Y $and$ls180.v:6186$1529_Y end attribute \src "ls180.v:6198.42-6198.95" - cell $and $and$ls180.v:6198$1538 + cell $and $and$ls180.v:6198$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256708,43 +259193,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6198$1538_Y + connect \Y $and$ls180.v:6198$1531_Y end attribute \src "ls180.v:6198.41-6198.145" - cell $and $and$ls180.v:6198$1540 + cell $and $and$ls180.v:6198$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6198$1538_Y - connect \B $eq$ls180.v:6198$1539_Y - connect \Y $and$ls180.v:6198$1540_Y + connect \A $and$ls180.v:6198$1531_Y + connect \B $eq$ls180.v:6198$1532_Y + connect \Y $and$ls180.v:6198$1533_Y end attribute \src "ls180.v:6199.42-6199.98" - cell $and $and$ls180.v:6199$1542 + cell $and $and$ls180.v:6199$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6199$1541_Y - connect \Y $and$ls180.v:6199$1542_Y + connect \B $not$ls180.v:6199$1534_Y + connect \Y $and$ls180.v:6199$1535_Y end attribute \src "ls180.v:6199.41-6199.148" - cell $and $and$ls180.v:6199$1544 + cell $and $and$ls180.v:6199$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6199$1542_Y - connect \B $eq$ls180.v:6199$1543_Y - connect \Y $and$ls180.v:6199$1544_Y + connect \A $and$ls180.v:6199$1535_Y + connect \B $eq$ls180.v:6199$1536_Y + connect \Y $and$ls180.v:6199$1537_Y end attribute \src "ls180.v:6201.42-6201.95" - cell $and $and$ls180.v:6201$1545 + cell $and $and$ls180.v:6201$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256752,43 +259237,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6201$1545_Y + connect \Y $and$ls180.v:6201$1538_Y end attribute \src "ls180.v:6201.41-6201.145" - cell $and $and$ls180.v:6201$1547 + cell $and $and$ls180.v:6201$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6201$1545_Y - connect \B $eq$ls180.v:6201$1546_Y - connect \Y $and$ls180.v:6201$1547_Y + connect \A $and$ls180.v:6201$1538_Y + connect \B $eq$ls180.v:6201$1539_Y + connect \Y $and$ls180.v:6201$1540_Y end attribute \src "ls180.v:6202.42-6202.98" - cell $and $and$ls180.v:6202$1549 + cell $and $and$ls180.v:6202$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6202$1548_Y - connect \Y $and$ls180.v:6202$1549_Y + connect \B $not$ls180.v:6202$1541_Y + connect \Y $and$ls180.v:6202$1542_Y end attribute \src "ls180.v:6202.41-6202.148" - cell $and $and$ls180.v:6202$1551 + cell $and $and$ls180.v:6202$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6202$1549_Y - connect \B $eq$ls180.v:6202$1550_Y - connect \Y $and$ls180.v:6202$1551_Y + connect \A $and$ls180.v:6202$1542_Y + connect \B $eq$ls180.v:6202$1543_Y + connect \Y $and$ls180.v:6202$1544_Y end attribute \src "ls180.v:6204.42-6204.95" - cell $and $and$ls180.v:6204$1552 + cell $and $and$ls180.v:6204$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256796,43 +259281,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6204$1552_Y + connect \Y $and$ls180.v:6204$1545_Y end attribute \src "ls180.v:6204.41-6204.145" - cell $and $and$ls180.v:6204$1554 + cell $and $and$ls180.v:6204$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6204$1552_Y - connect \B $eq$ls180.v:6204$1553_Y - connect \Y $and$ls180.v:6204$1554_Y + connect \A $and$ls180.v:6204$1545_Y + connect \B $eq$ls180.v:6204$1546_Y + connect \Y $and$ls180.v:6204$1547_Y end attribute \src "ls180.v:6205.42-6205.98" - cell $and $and$ls180.v:6205$1556 + cell $and $and$ls180.v:6205$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6205$1555_Y - connect \Y $and$ls180.v:6205$1556_Y + connect \B $not$ls180.v:6205$1548_Y + connect \Y $and$ls180.v:6205$1549_Y end attribute \src "ls180.v:6205.41-6205.148" - cell $and $and$ls180.v:6205$1558 + cell $and $and$ls180.v:6205$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6205$1556_Y - connect \B $eq$ls180.v:6205$1557_Y - connect \Y $and$ls180.v:6205$1558_Y + connect \A $and$ls180.v:6205$1549_Y + connect \B $eq$ls180.v:6205$1550_Y + connect \Y $and$ls180.v:6205$1551_Y end attribute \src "ls180.v:6207.42-6207.95" - cell $and $and$ls180.v:6207$1559 + cell $and $and$ls180.v:6207$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256840,43 +259325,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6207$1559_Y + connect \Y $and$ls180.v:6207$1552_Y end attribute \src "ls180.v:6207.41-6207.145" - cell $and $and$ls180.v:6207$1561 + cell $and $and$ls180.v:6207$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6207$1559_Y - connect \B $eq$ls180.v:6207$1560_Y - connect \Y $and$ls180.v:6207$1561_Y + connect \A $and$ls180.v:6207$1552_Y + connect \B $eq$ls180.v:6207$1553_Y + connect \Y $and$ls180.v:6207$1554_Y end attribute \src "ls180.v:6208.42-6208.98" - cell $and $and$ls180.v:6208$1563 + cell $and $and$ls180.v:6208$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6208$1562_Y - connect \Y $and$ls180.v:6208$1563_Y + connect \B $not$ls180.v:6208$1555_Y + connect \Y $and$ls180.v:6208$1556_Y end attribute \src "ls180.v:6208.41-6208.148" - cell $and $and$ls180.v:6208$1565 + cell $and $and$ls180.v:6208$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6208$1563_Y - connect \B $eq$ls180.v:6208$1564_Y - connect \Y $and$ls180.v:6208$1565_Y + connect \A $and$ls180.v:6208$1556_Y + connect \B $eq$ls180.v:6208$1557_Y + connect \Y $and$ls180.v:6208$1558_Y end attribute \src "ls180.v:6210.42-6210.95" - cell $and $and$ls180.v:6210$1566 + cell $and $and$ls180.v:6210$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256884,43 +259369,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6210$1566_Y + connect \Y $and$ls180.v:6210$1559_Y end attribute \src "ls180.v:6210.41-6210.145" - cell $and $and$ls180.v:6210$1568 + cell $and $and$ls180.v:6210$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6210$1566_Y - connect \B $eq$ls180.v:6210$1567_Y - connect \Y $and$ls180.v:6210$1568_Y + connect \A $and$ls180.v:6210$1559_Y + connect \B $eq$ls180.v:6210$1560_Y + connect \Y $and$ls180.v:6210$1561_Y end attribute \src "ls180.v:6211.42-6211.98" - cell $and $and$ls180.v:6211$1570 + cell $and $and$ls180.v:6211$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6211$1569_Y - connect \Y $and$ls180.v:6211$1570_Y + connect \B $not$ls180.v:6211$1562_Y + connect \Y $and$ls180.v:6211$1563_Y end attribute \src "ls180.v:6211.41-6211.148" - cell $and $and$ls180.v:6211$1572 + cell $and $and$ls180.v:6211$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6211$1570_Y - connect \B $eq$ls180.v:6211$1571_Y - connect \Y $and$ls180.v:6211$1572_Y + connect \A $and$ls180.v:6211$1563_Y + connect \B $eq$ls180.v:6211$1564_Y + connect \Y $and$ls180.v:6211$1565_Y end attribute \src "ls180.v:6213.42-6213.95" - cell $and $and$ls180.v:6213$1573 + cell $and $and$ls180.v:6213$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256928,43 +259413,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6213$1573_Y + connect \Y $and$ls180.v:6213$1566_Y end attribute \src "ls180.v:6213.41-6213.145" - cell $and $and$ls180.v:6213$1575 + cell $and $and$ls180.v:6213$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6213$1573_Y - connect \B $eq$ls180.v:6213$1574_Y - connect \Y $and$ls180.v:6213$1575_Y + connect \A $and$ls180.v:6213$1566_Y + connect \B $eq$ls180.v:6213$1567_Y + connect \Y $and$ls180.v:6213$1568_Y end attribute \src "ls180.v:6214.42-6214.98" - cell $and $and$ls180.v:6214$1577 + cell $and $and$ls180.v:6214$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6214$1576_Y - connect \Y $and$ls180.v:6214$1577_Y + connect \B $not$ls180.v:6214$1569_Y + connect \Y $and$ls180.v:6214$1570_Y end attribute \src "ls180.v:6214.41-6214.148" - cell $and $and$ls180.v:6214$1579 + cell $and $and$ls180.v:6214$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6214$1577_Y - connect \B $eq$ls180.v:6214$1578_Y - connect \Y $and$ls180.v:6214$1579_Y + connect \A $and$ls180.v:6214$1570_Y + connect \B $eq$ls180.v:6214$1571_Y + connect \Y $and$ls180.v:6214$1572_Y end attribute \src "ls180.v:6216.42-6216.95" - cell $and $and$ls180.v:6216$1580 + cell $and $and$ls180.v:6216$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256972,43 +259457,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6216$1580_Y + connect \Y $and$ls180.v:6216$1573_Y end attribute \src "ls180.v:6216.41-6216.145" - cell $and $and$ls180.v:6216$1582 + cell $and $and$ls180.v:6216$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6216$1580_Y - connect \B $eq$ls180.v:6216$1581_Y - connect \Y $and$ls180.v:6216$1582_Y + connect \A $and$ls180.v:6216$1573_Y + connect \B $eq$ls180.v:6216$1574_Y + connect \Y $and$ls180.v:6216$1575_Y end attribute \src "ls180.v:6217.42-6217.98" - cell $and $and$ls180.v:6217$1584 + cell $and $and$ls180.v:6217$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6217$1583_Y - connect \Y $and$ls180.v:6217$1584_Y + connect \B $not$ls180.v:6217$1576_Y + connect \Y $and$ls180.v:6217$1577_Y end attribute \src "ls180.v:6217.41-6217.148" - cell $and $and$ls180.v:6217$1586 + cell $and $and$ls180.v:6217$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6217$1584_Y - connect \B $eq$ls180.v:6217$1585_Y - connect \Y $and$ls180.v:6217$1586_Y + connect \A $and$ls180.v:6217$1577_Y + connect \B $eq$ls180.v:6217$1578_Y + connect \Y $and$ls180.v:6217$1579_Y end - attribute \src "ls180.v:6219.44-6219.97" - cell $and $and$ls180.v:6219$1587 + attribute \src "ls180.v:6219.42-6219.95" + cell $and $and$ls180.v:6219$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257016,43 +259501,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6219$1587_Y + connect \Y $and$ls180.v:6219$1580_Y end - attribute \src "ls180.v:6219.43-6219.147" - cell $and $and$ls180.v:6219$1589 + attribute \src "ls180.v:6219.41-6219.145" + cell $and $and$ls180.v:6219$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6219$1587_Y - connect \B $eq$ls180.v:6219$1588_Y - connect \Y $and$ls180.v:6219$1589_Y + connect \A $and$ls180.v:6219$1580_Y + connect \B $eq$ls180.v:6219$1581_Y + connect \Y $and$ls180.v:6219$1582_Y end - attribute \src "ls180.v:6220.44-6220.100" - cell $and $and$ls180.v:6220$1591 + attribute \src "ls180.v:6220.42-6220.98" + cell $and $and$ls180.v:6220$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6220$1590_Y - connect \Y $and$ls180.v:6220$1591_Y + connect \B $not$ls180.v:6220$1583_Y + connect \Y $and$ls180.v:6220$1584_Y end - attribute \src "ls180.v:6220.43-6220.150" - cell $and $and$ls180.v:6220$1593 + attribute \src "ls180.v:6220.41-6220.148" + cell $and $and$ls180.v:6220$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6220$1591_Y - connect \B $eq$ls180.v:6220$1592_Y - connect \Y $and$ls180.v:6220$1593_Y + connect \A $and$ls180.v:6220$1584_Y + connect \B $eq$ls180.v:6220$1585_Y + connect \Y $and$ls180.v:6220$1586_Y end attribute \src "ls180.v:6222.44-6222.97" - cell $and $and$ls180.v:6222$1594 + cell $and $and$ls180.v:6222$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257060,43 +259545,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6222$1594_Y + connect \Y $and$ls180.v:6222$1587_Y end attribute \src "ls180.v:6222.43-6222.147" - cell $and $and$ls180.v:6222$1596 + cell $and $and$ls180.v:6222$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1594_Y - connect \B $eq$ls180.v:6222$1595_Y - connect \Y $and$ls180.v:6222$1596_Y + connect \A $and$ls180.v:6222$1587_Y + connect \B $eq$ls180.v:6222$1588_Y + connect \Y $and$ls180.v:6222$1589_Y end attribute \src "ls180.v:6223.44-6223.100" - cell $and $and$ls180.v:6223$1598 + cell $and $and$ls180.v:6223$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6223$1597_Y - connect \Y $and$ls180.v:6223$1598_Y + connect \B $not$ls180.v:6223$1590_Y + connect \Y $and$ls180.v:6223$1591_Y end attribute \src "ls180.v:6223.43-6223.150" - cell $and $and$ls180.v:6223$1600 + cell $and $and$ls180.v:6223$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1598_Y - connect \B $eq$ls180.v:6223$1599_Y - connect \Y $and$ls180.v:6223$1600_Y + connect \A $and$ls180.v:6223$1591_Y + connect \B $eq$ls180.v:6223$1592_Y + connect \Y $and$ls180.v:6223$1593_Y end attribute \src "ls180.v:6225.44-6225.97" - cell $and $and$ls180.v:6225$1601 + cell $and $and$ls180.v:6225$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257104,43 +259589,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6225$1601_Y + connect \Y $and$ls180.v:6225$1594_Y end - attribute \src "ls180.v:6225.43-6225.148" - cell $and $and$ls180.v:6225$1603 + attribute \src "ls180.v:6225.43-6225.147" + cell $and $and$ls180.v:6225$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1601_Y - connect \B $eq$ls180.v:6225$1602_Y - connect \Y $and$ls180.v:6225$1603_Y + connect \A $and$ls180.v:6225$1594_Y + connect \B $eq$ls180.v:6225$1595_Y + connect \Y $and$ls180.v:6225$1596_Y end attribute \src "ls180.v:6226.44-6226.100" - cell $and $and$ls180.v:6226$1605 + cell $and $and$ls180.v:6226$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6226$1604_Y - connect \Y $and$ls180.v:6226$1605_Y + connect \B $not$ls180.v:6226$1597_Y + connect \Y $and$ls180.v:6226$1598_Y end - attribute \src "ls180.v:6226.43-6226.151" - cell $and $and$ls180.v:6226$1607 + attribute \src "ls180.v:6226.43-6226.150" + cell $and $and$ls180.v:6226$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1605_Y - connect \B $eq$ls180.v:6226$1606_Y - connect \Y $and$ls180.v:6226$1607_Y + connect \A $and$ls180.v:6226$1598_Y + connect \B $eq$ls180.v:6226$1599_Y + connect \Y $and$ls180.v:6226$1600_Y end attribute \src "ls180.v:6228.44-6228.97" - cell $and $and$ls180.v:6228$1608 + cell $and $and$ls180.v:6228$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257148,43 +259633,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6228$1608_Y + connect \Y $and$ls180.v:6228$1601_Y end attribute \src "ls180.v:6228.43-6228.148" - cell $and $and$ls180.v:6228$1610 + cell $and $and$ls180.v:6228$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1608_Y - connect \B $eq$ls180.v:6228$1609_Y - connect \Y $and$ls180.v:6228$1610_Y + connect \A $and$ls180.v:6228$1601_Y + connect \B $eq$ls180.v:6228$1602_Y + connect \Y $and$ls180.v:6228$1603_Y end attribute \src "ls180.v:6229.44-6229.100" - cell $and $and$ls180.v:6229$1612 + cell $and $and$ls180.v:6229$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6229$1611_Y - connect \Y $and$ls180.v:6229$1612_Y + connect \B $not$ls180.v:6229$1604_Y + connect \Y $and$ls180.v:6229$1605_Y end attribute \src "ls180.v:6229.43-6229.151" - cell $and $and$ls180.v:6229$1614 + cell $and $and$ls180.v:6229$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1612_Y - connect \B $eq$ls180.v:6229$1613_Y - connect \Y $and$ls180.v:6229$1614_Y + connect \A $and$ls180.v:6229$1605_Y + connect \B $eq$ls180.v:6229$1606_Y + connect \Y $and$ls180.v:6229$1607_Y end attribute \src "ls180.v:6231.44-6231.97" - cell $and $and$ls180.v:6231$1615 + cell $and $and$ls180.v:6231$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257192,43 +259677,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6231$1615_Y + connect \Y $and$ls180.v:6231$1608_Y end attribute \src "ls180.v:6231.43-6231.148" - cell $and $and$ls180.v:6231$1617 + cell $and $and$ls180.v:6231$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6231$1615_Y - connect \B $eq$ls180.v:6231$1616_Y - connect \Y $and$ls180.v:6231$1617_Y + connect \A $and$ls180.v:6231$1608_Y + connect \B $eq$ls180.v:6231$1609_Y + connect \Y $and$ls180.v:6231$1610_Y end attribute \src "ls180.v:6232.44-6232.100" - cell $and $and$ls180.v:6232$1619 + cell $and $and$ls180.v:6232$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6232$1618_Y - connect \Y $and$ls180.v:6232$1619_Y + connect \B $not$ls180.v:6232$1611_Y + connect \Y $and$ls180.v:6232$1612_Y end attribute \src "ls180.v:6232.43-6232.151" - cell $and $and$ls180.v:6232$1621 + cell $and $and$ls180.v:6232$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1619_Y - connect \B $eq$ls180.v:6232$1620_Y - connect \Y $and$ls180.v:6232$1621_Y + connect \A $and$ls180.v:6232$1612_Y + connect \B $eq$ls180.v:6232$1613_Y + connect \Y $and$ls180.v:6232$1614_Y end - attribute \src "ls180.v:6234.41-6234.94" - cell $and $and$ls180.v:6234$1622 + attribute \src "ls180.v:6234.44-6234.97" + cell $and $and$ls180.v:6234$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257236,43 +259721,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6234$1622_Y + connect \Y $and$ls180.v:6234$1615_Y end - attribute \src "ls180.v:6234.40-6234.145" - cell $and $and$ls180.v:6234$1624 + attribute \src "ls180.v:6234.43-6234.148" + cell $and $and$ls180.v:6234$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6234$1622_Y - connect \B $eq$ls180.v:6234$1623_Y - connect \Y $and$ls180.v:6234$1624_Y + connect \A $and$ls180.v:6234$1615_Y + connect \B $eq$ls180.v:6234$1616_Y + connect \Y $and$ls180.v:6234$1617_Y end - attribute \src "ls180.v:6235.41-6235.97" - cell $and $and$ls180.v:6235$1626 + attribute \src "ls180.v:6235.44-6235.100" + cell $and $and$ls180.v:6235$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6235$1625_Y - connect \Y $and$ls180.v:6235$1626_Y + connect \B $not$ls180.v:6235$1618_Y + connect \Y $and$ls180.v:6235$1619_Y end - attribute \src "ls180.v:6235.40-6235.148" - cell $and $and$ls180.v:6235$1628 + attribute \src "ls180.v:6235.43-6235.151" + cell $and $and$ls180.v:6235$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1626_Y - connect \B $eq$ls180.v:6235$1627_Y - connect \Y $and$ls180.v:6235$1628_Y + connect \A $and$ls180.v:6235$1619_Y + connect \B $eq$ls180.v:6235$1620_Y + connect \Y $and$ls180.v:6235$1621_Y end - attribute \src "ls180.v:6237.42-6237.95" - cell $and $and$ls180.v:6237$1629 + attribute \src "ls180.v:6237.41-6237.94" + cell $and $and$ls180.v:6237$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257280,87 +259765,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6237$1629_Y + connect \Y $and$ls180.v:6237$1622_Y end - attribute \src "ls180.v:6237.41-6237.146" - cell $and $and$ls180.v:6237$1631 + attribute \src "ls180.v:6237.40-6237.145" + cell $and $and$ls180.v:6237$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1629_Y - connect \B $eq$ls180.v:6237$1630_Y - connect \Y $and$ls180.v:6237$1631_Y + connect \A $and$ls180.v:6237$1622_Y + connect \B $eq$ls180.v:6237$1623_Y + connect \Y $and$ls180.v:6237$1624_Y end - attribute \src "ls180.v:6238.42-6238.98" - cell $and $and$ls180.v:6238$1633 + attribute \src "ls180.v:6238.41-6238.97" + cell $and $and$ls180.v:6238$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6238$1632_Y - connect \Y $and$ls180.v:6238$1633_Y + connect \B $not$ls180.v:6238$1625_Y + connect \Y $and$ls180.v:6238$1626_Y end - attribute \src "ls180.v:6238.41-6238.149" - cell $and $and$ls180.v:6238$1635 + attribute \src "ls180.v:6238.40-6238.148" + cell $and $and$ls180.v:6238$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1633_Y - connect \B $eq$ls180.v:6238$1634_Y - connect \Y $and$ls180.v:6238$1635_Y + connect \A $and$ls180.v:6238$1626_Y + connect \B $eq$ls180.v:6238$1627_Y + connect \Y $and$ls180.v:6238$1628_Y end - attribute \src "ls180.v:6257.46-6257.99" - cell $and $and$ls180.v:6257$1637 + attribute \src "ls180.v:6240.42-6240.95" + cell $and $and$ls180.v:6240$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6257$1637_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6240$1629_Y end - attribute \src "ls180.v:6257.45-6257.149" - cell $and $and$ls180.v:6257$1639 + attribute \src "ls180.v:6240.41-6240.146" + cell $and $and$ls180.v:6240$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6257$1637_Y - connect \B $eq$ls180.v:6257$1638_Y - connect \Y $and$ls180.v:6257$1639_Y + connect \A $and$ls180.v:6240$1629_Y + connect \B $eq$ls180.v:6240$1630_Y + connect \Y $and$ls180.v:6240$1631_Y end - attribute \src "ls180.v:6258.46-6258.102" - cell $and $and$ls180.v:6258$1641 + attribute \src "ls180.v:6241.42-6241.98" + cell $and $and$ls180.v:6241$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6258$1640_Y - connect \Y $and$ls180.v:6258$1641_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6241$1632_Y + connect \Y $and$ls180.v:6241$1633_Y end - attribute \src "ls180.v:6258.45-6258.152" - cell $and $and$ls180.v:6258$1643 + attribute \src "ls180.v:6241.41-6241.149" + cell $and $and$ls180.v:6241$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6258$1641_Y - connect \B $eq$ls180.v:6258$1642_Y - connect \Y $and$ls180.v:6258$1643_Y + connect \A $and$ls180.v:6241$1633_Y + connect \B $eq$ls180.v:6241$1634_Y + connect \Y $and$ls180.v:6241$1635_Y end attribute \src "ls180.v:6260.46-6260.99" - cell $and $and$ls180.v:6260$1644 + cell $and $and$ls180.v:6260$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257368,43 +259853,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6260$1644_Y + connect \Y $and$ls180.v:6260$1637_Y end attribute \src "ls180.v:6260.45-6260.149" - cell $and $and$ls180.v:6260$1646 + cell $and $and$ls180.v:6260$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6260$1644_Y - connect \B $eq$ls180.v:6260$1645_Y - connect \Y $and$ls180.v:6260$1646_Y + connect \A $and$ls180.v:6260$1637_Y + connect \B $eq$ls180.v:6260$1638_Y + connect \Y $and$ls180.v:6260$1639_Y end attribute \src "ls180.v:6261.46-6261.102" - cell $and $and$ls180.v:6261$1648 + cell $and $and$ls180.v:6261$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6261$1647_Y - connect \Y $and$ls180.v:6261$1648_Y + connect \B $not$ls180.v:6261$1640_Y + connect \Y $and$ls180.v:6261$1641_Y end attribute \src "ls180.v:6261.45-6261.152" - cell $and $and$ls180.v:6261$1650 + cell $and $and$ls180.v:6261$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1648_Y - connect \B $eq$ls180.v:6261$1649_Y - connect \Y $and$ls180.v:6261$1650_Y + connect \A $and$ls180.v:6261$1641_Y + connect \B $eq$ls180.v:6261$1642_Y + connect \Y $and$ls180.v:6261$1643_Y end attribute \src "ls180.v:6263.46-6263.99" - cell $and $and$ls180.v:6263$1651 + cell $and $and$ls180.v:6263$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257412,43 +259897,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6263$1651_Y + connect \Y $and$ls180.v:6263$1644_Y end attribute \src "ls180.v:6263.45-6263.149" - cell $and $and$ls180.v:6263$1653 + cell $and $and$ls180.v:6263$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6263$1651_Y - connect \B $eq$ls180.v:6263$1652_Y - connect \Y $and$ls180.v:6263$1653_Y + connect \A $and$ls180.v:6263$1644_Y + connect \B $eq$ls180.v:6263$1645_Y + connect \Y $and$ls180.v:6263$1646_Y end attribute \src "ls180.v:6264.46-6264.102" - cell $and $and$ls180.v:6264$1655 + cell $and $and$ls180.v:6264$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6264$1654_Y - connect \Y $and$ls180.v:6264$1655_Y + connect \B $not$ls180.v:6264$1647_Y + connect \Y $and$ls180.v:6264$1648_Y end attribute \src "ls180.v:6264.45-6264.152" - cell $and $and$ls180.v:6264$1657 + cell $and $and$ls180.v:6264$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1655_Y - connect \B $eq$ls180.v:6264$1656_Y - connect \Y $and$ls180.v:6264$1657_Y + connect \A $and$ls180.v:6264$1648_Y + connect \B $eq$ls180.v:6264$1649_Y + connect \Y $and$ls180.v:6264$1650_Y end attribute \src "ls180.v:6266.46-6266.99" - cell $and $and$ls180.v:6266$1658 + cell $and $and$ls180.v:6266$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257456,43 +259941,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6266$1658_Y + connect \Y $and$ls180.v:6266$1651_Y end attribute \src "ls180.v:6266.45-6266.149" - cell $and $and$ls180.v:6266$1660 + cell $and $and$ls180.v:6266$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6266$1658_Y - connect \B $eq$ls180.v:6266$1659_Y - connect \Y $and$ls180.v:6266$1660_Y + connect \A $and$ls180.v:6266$1651_Y + connect \B $eq$ls180.v:6266$1652_Y + connect \Y $and$ls180.v:6266$1653_Y end attribute \src "ls180.v:6267.46-6267.102" - cell $and $and$ls180.v:6267$1662 + cell $and $and$ls180.v:6267$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6267$1661_Y - connect \Y $and$ls180.v:6267$1662_Y + connect \B $not$ls180.v:6267$1654_Y + connect \Y $and$ls180.v:6267$1655_Y end attribute \src "ls180.v:6267.45-6267.152" - cell $and $and$ls180.v:6267$1664 + cell $and $and$ls180.v:6267$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6267$1662_Y - connect \B $eq$ls180.v:6267$1663_Y - connect \Y $and$ls180.v:6267$1664_Y + connect \A $and$ls180.v:6267$1655_Y + connect \B $eq$ls180.v:6267$1656_Y + connect \Y $and$ls180.v:6267$1657_Y end - attribute \src "ls180.v:6269.45-6269.98" - cell $and $and$ls180.v:6269$1665 + attribute \src "ls180.v:6269.46-6269.99" + cell $and $and$ls180.v:6269$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257500,43 +259985,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6269$1665_Y + connect \Y $and$ls180.v:6269$1658_Y end - attribute \src "ls180.v:6269.44-6269.148" - cell $and $and$ls180.v:6269$1667 + attribute \src "ls180.v:6269.45-6269.149" + cell $and $and$ls180.v:6269$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6269$1665_Y - connect \B $eq$ls180.v:6269$1666_Y - connect \Y $and$ls180.v:6269$1667_Y + connect \A $and$ls180.v:6269$1658_Y + connect \B $eq$ls180.v:6269$1659_Y + connect \Y $and$ls180.v:6269$1660_Y end - attribute \src "ls180.v:6270.45-6270.101" - cell $and $and$ls180.v:6270$1669 + attribute \src "ls180.v:6270.46-6270.102" + cell $and $and$ls180.v:6270$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6270$1668_Y - connect \Y $and$ls180.v:6270$1669_Y + connect \B $not$ls180.v:6270$1661_Y + connect \Y $and$ls180.v:6270$1662_Y end - attribute \src "ls180.v:6270.44-6270.151" - cell $and $and$ls180.v:6270$1671 + attribute \src "ls180.v:6270.45-6270.152" + cell $and $and$ls180.v:6270$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6270$1669_Y - connect \B $eq$ls180.v:6270$1670_Y - connect \Y $and$ls180.v:6270$1671_Y + connect \A $and$ls180.v:6270$1662_Y + connect \B $eq$ls180.v:6270$1663_Y + connect \Y $and$ls180.v:6270$1664_Y end attribute \src "ls180.v:6272.45-6272.98" - cell $and $and$ls180.v:6272$1672 + cell $and $and$ls180.v:6272$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257544,43 +260029,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6272$1672_Y + connect \Y $and$ls180.v:6272$1665_Y end attribute \src "ls180.v:6272.44-6272.148" - cell $and $and$ls180.v:6272$1674 + cell $and $and$ls180.v:6272$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6272$1672_Y - connect \B $eq$ls180.v:6272$1673_Y - connect \Y $and$ls180.v:6272$1674_Y + connect \A $and$ls180.v:6272$1665_Y + connect \B $eq$ls180.v:6272$1666_Y + connect \Y $and$ls180.v:6272$1667_Y end attribute \src "ls180.v:6273.45-6273.101" - cell $and $and$ls180.v:6273$1676 + cell $and $and$ls180.v:6273$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6273$1675_Y - connect \Y $and$ls180.v:6273$1676_Y + connect \B $not$ls180.v:6273$1668_Y + connect \Y $and$ls180.v:6273$1669_Y end attribute \src "ls180.v:6273.44-6273.151" - cell $and $and$ls180.v:6273$1678 + cell $and $and$ls180.v:6273$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6273$1676_Y - connect \B $eq$ls180.v:6273$1677_Y - connect \Y $and$ls180.v:6273$1678_Y + connect \A $and$ls180.v:6273$1669_Y + connect \B $eq$ls180.v:6273$1670_Y + connect \Y $and$ls180.v:6273$1671_Y end attribute \src "ls180.v:6275.45-6275.98" - cell $and $and$ls180.v:6275$1679 + cell $and $and$ls180.v:6275$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257588,43 +260073,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6275$1679_Y + connect \Y $and$ls180.v:6275$1672_Y end attribute \src "ls180.v:6275.44-6275.148" - cell $and $and$ls180.v:6275$1681 + cell $and $and$ls180.v:6275$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6275$1679_Y - connect \B $eq$ls180.v:6275$1680_Y - connect \Y $and$ls180.v:6275$1681_Y + connect \A $and$ls180.v:6275$1672_Y + connect \B $eq$ls180.v:6275$1673_Y + connect \Y $and$ls180.v:6275$1674_Y end attribute \src "ls180.v:6276.45-6276.101" - cell $and $and$ls180.v:6276$1683 + cell $and $and$ls180.v:6276$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6276$1682_Y - connect \Y $and$ls180.v:6276$1683_Y + connect \B $not$ls180.v:6276$1675_Y + connect \Y $and$ls180.v:6276$1676_Y end attribute \src "ls180.v:6276.44-6276.151" - cell $and $and$ls180.v:6276$1685 + cell $and $and$ls180.v:6276$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6276$1683_Y - connect \B $eq$ls180.v:6276$1684_Y - connect \Y $and$ls180.v:6276$1685_Y + connect \A $and$ls180.v:6276$1676_Y + connect \B $eq$ls180.v:6276$1677_Y + connect \Y $and$ls180.v:6276$1678_Y end attribute \src "ls180.v:6278.45-6278.98" - cell $and $and$ls180.v:6278$1686 + cell $and $and$ls180.v:6278$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257632,43 +260117,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6278$1686_Y + connect \Y $and$ls180.v:6278$1679_Y end attribute \src "ls180.v:6278.44-6278.148" - cell $and $and$ls180.v:6278$1688 + cell $and $and$ls180.v:6278$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6278$1686_Y - connect \B $eq$ls180.v:6278$1687_Y - connect \Y $and$ls180.v:6278$1688_Y + connect \A $and$ls180.v:6278$1679_Y + connect \B $eq$ls180.v:6278$1680_Y + connect \Y $and$ls180.v:6278$1681_Y end attribute \src "ls180.v:6279.45-6279.101" - cell $and $and$ls180.v:6279$1690 + cell $and $and$ls180.v:6279$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6279$1689_Y - connect \Y $and$ls180.v:6279$1690_Y + connect \B $not$ls180.v:6279$1682_Y + connect \Y $and$ls180.v:6279$1683_Y end attribute \src "ls180.v:6279.44-6279.151" - cell $and $and$ls180.v:6279$1692 + cell $and $and$ls180.v:6279$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6279$1690_Y - connect \B $eq$ls180.v:6279$1691_Y - connect \Y $and$ls180.v:6279$1692_Y + connect \A $and$ls180.v:6279$1683_Y + connect \B $eq$ls180.v:6279$1684_Y + connect \Y $and$ls180.v:6279$1685_Y end - attribute \src "ls180.v:6281.36-6281.89" - cell $and $and$ls180.v:6281$1693 + attribute \src "ls180.v:6281.45-6281.98" + cell $and $and$ls180.v:6281$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257676,43 +260161,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6281$1693_Y + connect \Y $and$ls180.v:6281$1686_Y end - attribute \src "ls180.v:6281.35-6281.139" - cell $and $and$ls180.v:6281$1695 + attribute \src "ls180.v:6281.44-6281.148" + cell $and $and$ls180.v:6281$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6281$1693_Y - connect \B $eq$ls180.v:6281$1694_Y - connect \Y $and$ls180.v:6281$1695_Y + connect \A $and$ls180.v:6281$1686_Y + connect \B $eq$ls180.v:6281$1687_Y + connect \Y $and$ls180.v:6281$1688_Y end - attribute \src "ls180.v:6282.36-6282.92" - cell $and $and$ls180.v:6282$1697 + attribute \src "ls180.v:6282.45-6282.101" + cell $and $and$ls180.v:6282$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6282$1696_Y - connect \Y $and$ls180.v:6282$1697_Y + connect \B $not$ls180.v:6282$1689_Y + connect \Y $and$ls180.v:6282$1690_Y end - attribute \src "ls180.v:6282.35-6282.142" - cell $and $and$ls180.v:6282$1699 + attribute \src "ls180.v:6282.44-6282.151" + cell $and $and$ls180.v:6282$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6282$1697_Y - connect \B $eq$ls180.v:6282$1698_Y - connect \Y $and$ls180.v:6282$1699_Y + connect \A $and$ls180.v:6282$1690_Y + connect \B $eq$ls180.v:6282$1691_Y + connect \Y $and$ls180.v:6282$1692_Y end - attribute \src "ls180.v:6284.47-6284.100" - cell $and $and$ls180.v:6284$1700 + attribute \src "ls180.v:6284.36-6284.89" + cell $and $and$ls180.v:6284$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257720,43 +260205,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6284$1700_Y + connect \Y $and$ls180.v:6284$1693_Y end - attribute \src "ls180.v:6284.46-6284.150" - cell $and $and$ls180.v:6284$1702 + attribute \src "ls180.v:6284.35-6284.139" + cell $and $and$ls180.v:6284$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6284$1700_Y - connect \B $eq$ls180.v:6284$1701_Y - connect \Y $and$ls180.v:6284$1702_Y + connect \A $and$ls180.v:6284$1693_Y + connect \B $eq$ls180.v:6284$1694_Y + connect \Y $and$ls180.v:6284$1695_Y end - attribute \src "ls180.v:6285.47-6285.103" - cell $and $and$ls180.v:6285$1704 + attribute \src "ls180.v:6285.36-6285.92" + cell $and $and$ls180.v:6285$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6285$1703_Y - connect \Y $and$ls180.v:6285$1704_Y + connect \B $not$ls180.v:6285$1696_Y + connect \Y $and$ls180.v:6285$1697_Y end - attribute \src "ls180.v:6285.46-6285.153" - cell $and $and$ls180.v:6285$1706 + attribute \src "ls180.v:6285.35-6285.142" + cell $and $and$ls180.v:6285$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6285$1704_Y - connect \B $eq$ls180.v:6285$1705_Y - connect \Y $and$ls180.v:6285$1706_Y + connect \A $and$ls180.v:6285$1697_Y + connect \B $eq$ls180.v:6285$1698_Y + connect \Y $and$ls180.v:6285$1699_Y end attribute \src "ls180.v:6287.47-6287.100" - cell $and $and$ls180.v:6287$1707 + cell $and $and$ls180.v:6287$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257764,43 +260249,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6287$1707_Y + connect \Y $and$ls180.v:6287$1700_Y end - attribute \src "ls180.v:6287.46-6287.151" - cell $and $and$ls180.v:6287$1709 + attribute \src "ls180.v:6287.46-6287.150" + cell $and $and$ls180.v:6287$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6287$1707_Y - connect \B $eq$ls180.v:6287$1708_Y - connect \Y $and$ls180.v:6287$1709_Y + connect \A $and$ls180.v:6287$1700_Y + connect \B $eq$ls180.v:6287$1701_Y + connect \Y $and$ls180.v:6287$1702_Y end attribute \src "ls180.v:6288.47-6288.103" - cell $and $and$ls180.v:6288$1711 + cell $and $and$ls180.v:6288$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6288$1710_Y - connect \Y $and$ls180.v:6288$1711_Y + connect \B $not$ls180.v:6288$1703_Y + connect \Y $and$ls180.v:6288$1704_Y end - attribute \src "ls180.v:6288.46-6288.154" - cell $and $and$ls180.v:6288$1713 + attribute \src "ls180.v:6288.46-6288.153" + cell $and $and$ls180.v:6288$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6288$1711_Y - connect \B $eq$ls180.v:6288$1712_Y - connect \Y $and$ls180.v:6288$1713_Y + connect \A $and$ls180.v:6288$1704_Y + connect \B $eq$ls180.v:6288$1705_Y + connect \Y $and$ls180.v:6288$1706_Y end attribute \src "ls180.v:6290.47-6290.100" - cell $and $and$ls180.v:6290$1714 + cell $and $and$ls180.v:6290$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257808,43 +260293,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6290$1714_Y + connect \Y $and$ls180.v:6290$1707_Y end attribute \src "ls180.v:6290.46-6290.151" - cell $and $and$ls180.v:6290$1716 + cell $and $and$ls180.v:6290$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6290$1714_Y - connect \B $eq$ls180.v:6290$1715_Y - connect \Y $and$ls180.v:6290$1716_Y + connect \A $and$ls180.v:6290$1707_Y + connect \B $eq$ls180.v:6290$1708_Y + connect \Y $and$ls180.v:6290$1709_Y end attribute \src "ls180.v:6291.47-6291.103" - cell $and $and$ls180.v:6291$1718 + cell $and $and$ls180.v:6291$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6291$1717_Y - connect \Y $and$ls180.v:6291$1718_Y + connect \B $not$ls180.v:6291$1710_Y + connect \Y $and$ls180.v:6291$1711_Y end attribute \src "ls180.v:6291.46-6291.154" - cell $and $and$ls180.v:6291$1720 + cell $and $and$ls180.v:6291$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6291$1718_Y - connect \B $eq$ls180.v:6291$1719_Y - connect \Y $and$ls180.v:6291$1720_Y + connect \A $and$ls180.v:6291$1711_Y + connect \B $eq$ls180.v:6291$1712_Y + connect \Y $and$ls180.v:6291$1713_Y end attribute \src "ls180.v:6293.47-6293.100" - cell $and $and$ls180.v:6293$1721 + cell $and $and$ls180.v:6293$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257852,43 +260337,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6293$1721_Y + connect \Y $and$ls180.v:6293$1714_Y end attribute \src "ls180.v:6293.46-6293.151" - cell $and $and$ls180.v:6293$1723 + cell $and $and$ls180.v:6293$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6293$1721_Y - connect \B $eq$ls180.v:6293$1722_Y - connect \Y $and$ls180.v:6293$1723_Y + connect \A $and$ls180.v:6293$1714_Y + connect \B $eq$ls180.v:6293$1715_Y + connect \Y $and$ls180.v:6293$1716_Y end attribute \src "ls180.v:6294.47-6294.103" - cell $and $and$ls180.v:6294$1725 + cell $and $and$ls180.v:6294$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6294$1724_Y - connect \Y $and$ls180.v:6294$1725_Y + connect \B $not$ls180.v:6294$1717_Y + connect \Y $and$ls180.v:6294$1718_Y end attribute \src "ls180.v:6294.46-6294.154" - cell $and $and$ls180.v:6294$1727 + cell $and $and$ls180.v:6294$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6294$1725_Y - connect \B $eq$ls180.v:6294$1726_Y - connect \Y $and$ls180.v:6294$1727_Y + connect \A $and$ls180.v:6294$1718_Y + connect \B $eq$ls180.v:6294$1719_Y + connect \Y $and$ls180.v:6294$1720_Y end attribute \src "ls180.v:6296.47-6296.100" - cell $and $and$ls180.v:6296$1728 + cell $and $and$ls180.v:6296$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257896,43 +260381,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6296$1728_Y + connect \Y $and$ls180.v:6296$1721_Y end attribute \src "ls180.v:6296.46-6296.151" - cell $and $and$ls180.v:6296$1730 + cell $and $and$ls180.v:6296$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6296$1728_Y - connect \B $eq$ls180.v:6296$1729_Y - connect \Y $and$ls180.v:6296$1730_Y + connect \A $and$ls180.v:6296$1721_Y + connect \B $eq$ls180.v:6296$1722_Y + connect \Y $and$ls180.v:6296$1723_Y end attribute \src "ls180.v:6297.47-6297.103" - cell $and $and$ls180.v:6297$1732 + cell $and $and$ls180.v:6297$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6297$1731_Y - connect \Y $and$ls180.v:6297$1732_Y + connect \B $not$ls180.v:6297$1724_Y + connect \Y $and$ls180.v:6297$1725_Y end attribute \src "ls180.v:6297.46-6297.154" - cell $and $and$ls180.v:6297$1734 + cell $and $and$ls180.v:6297$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6297$1732_Y - connect \B $eq$ls180.v:6297$1733_Y - connect \Y $and$ls180.v:6297$1734_Y + connect \A $and$ls180.v:6297$1725_Y + connect \B $eq$ls180.v:6297$1726_Y + connect \Y $and$ls180.v:6297$1727_Y end attribute \src "ls180.v:6299.47-6299.100" - cell $and $and$ls180.v:6299$1735 + cell $and $and$ls180.v:6299$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257940,43 +260425,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6299$1735_Y + connect \Y $and$ls180.v:6299$1728_Y end attribute \src "ls180.v:6299.46-6299.151" - cell $and $and$ls180.v:6299$1737 + cell $and $and$ls180.v:6299$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6299$1735_Y - connect \B $eq$ls180.v:6299$1736_Y - connect \Y $and$ls180.v:6299$1737_Y + connect \A $and$ls180.v:6299$1728_Y + connect \B $eq$ls180.v:6299$1729_Y + connect \Y $and$ls180.v:6299$1730_Y end attribute \src "ls180.v:6300.47-6300.103" - cell $and $and$ls180.v:6300$1739 + cell $and $and$ls180.v:6300$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6300$1738_Y - connect \Y $and$ls180.v:6300$1739_Y + connect \B $not$ls180.v:6300$1731_Y + connect \Y $and$ls180.v:6300$1732_Y end attribute \src "ls180.v:6300.46-6300.154" - cell $and $and$ls180.v:6300$1741 + cell $and $and$ls180.v:6300$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6300$1739_Y - connect \B $eq$ls180.v:6300$1740_Y - connect \Y $and$ls180.v:6300$1741_Y + connect \A $and$ls180.v:6300$1732_Y + connect \B $eq$ls180.v:6300$1733_Y + connect \Y $and$ls180.v:6300$1734_Y end - attribute \src "ls180.v:6302.46-6302.99" - cell $and $and$ls180.v:6302$1742 + attribute \src "ls180.v:6302.47-6302.100" + cell $and $and$ls180.v:6302$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257984,43 +260469,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6302$1742_Y + connect \Y $and$ls180.v:6302$1735_Y end - attribute \src "ls180.v:6302.45-6302.150" - cell $and $and$ls180.v:6302$1744 + attribute \src "ls180.v:6302.46-6302.151" + cell $and $and$ls180.v:6302$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$1742_Y - connect \B $eq$ls180.v:6302$1743_Y - connect \Y $and$ls180.v:6302$1744_Y + connect \A $and$ls180.v:6302$1735_Y + connect \B $eq$ls180.v:6302$1736_Y + connect \Y $and$ls180.v:6302$1737_Y end - attribute \src "ls180.v:6303.46-6303.102" - cell $and $and$ls180.v:6303$1746 + attribute \src "ls180.v:6303.47-6303.103" + cell $and $and$ls180.v:6303$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6303$1745_Y - connect \Y $and$ls180.v:6303$1746_Y + connect \B $not$ls180.v:6303$1738_Y + connect \Y $and$ls180.v:6303$1739_Y end - attribute \src "ls180.v:6303.45-6303.153" - cell $and $and$ls180.v:6303$1748 + attribute \src "ls180.v:6303.46-6303.154" + cell $and $and$ls180.v:6303$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$1746_Y - connect \B $eq$ls180.v:6303$1747_Y - connect \Y $and$ls180.v:6303$1748_Y + connect \A $and$ls180.v:6303$1739_Y + connect \B $eq$ls180.v:6303$1740_Y + connect \Y $and$ls180.v:6303$1741_Y end attribute \src "ls180.v:6305.46-6305.99" - cell $and $and$ls180.v:6305$1749 + cell $and $and$ls180.v:6305$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258028,43 +260513,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6305$1749_Y + connect \Y $and$ls180.v:6305$1742_Y end attribute \src "ls180.v:6305.45-6305.150" - cell $and $and$ls180.v:6305$1751 + cell $and $and$ls180.v:6305$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$1749_Y - connect \B $eq$ls180.v:6305$1750_Y - connect \Y $and$ls180.v:6305$1751_Y + connect \A $and$ls180.v:6305$1742_Y + connect \B $eq$ls180.v:6305$1743_Y + connect \Y $and$ls180.v:6305$1744_Y end attribute \src "ls180.v:6306.46-6306.102" - cell $and $and$ls180.v:6306$1753 + cell $and $and$ls180.v:6306$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6306$1752_Y - connect \Y $and$ls180.v:6306$1753_Y + connect \B $not$ls180.v:6306$1745_Y + connect \Y $and$ls180.v:6306$1746_Y end attribute \src "ls180.v:6306.45-6306.153" - cell $and $and$ls180.v:6306$1755 + cell $and $and$ls180.v:6306$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$1753_Y - connect \B $eq$ls180.v:6306$1754_Y - connect \Y $and$ls180.v:6306$1755_Y + connect \A $and$ls180.v:6306$1746_Y + connect \B $eq$ls180.v:6306$1747_Y + connect \Y $and$ls180.v:6306$1748_Y end attribute \src "ls180.v:6308.46-6308.99" - cell $and $and$ls180.v:6308$1756 + cell $and $and$ls180.v:6308$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258072,43 +260557,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6308$1756_Y + connect \Y $and$ls180.v:6308$1749_Y end attribute \src "ls180.v:6308.45-6308.150" - cell $and $and$ls180.v:6308$1758 + cell $and $and$ls180.v:6308$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$1756_Y - connect \B $eq$ls180.v:6308$1757_Y - connect \Y $and$ls180.v:6308$1758_Y + connect \A $and$ls180.v:6308$1749_Y + connect \B $eq$ls180.v:6308$1750_Y + connect \Y $and$ls180.v:6308$1751_Y end attribute \src "ls180.v:6309.46-6309.102" - cell $and $and$ls180.v:6309$1760 + cell $and $and$ls180.v:6309$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6309$1759_Y - connect \Y $and$ls180.v:6309$1760_Y + connect \B $not$ls180.v:6309$1752_Y + connect \Y $and$ls180.v:6309$1753_Y end attribute \src "ls180.v:6309.45-6309.153" - cell $and $and$ls180.v:6309$1762 + cell $and $and$ls180.v:6309$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$1760_Y - connect \B $eq$ls180.v:6309$1761_Y - connect \Y $and$ls180.v:6309$1762_Y + connect \A $and$ls180.v:6309$1753_Y + connect \B $eq$ls180.v:6309$1754_Y + connect \Y $and$ls180.v:6309$1755_Y end attribute \src "ls180.v:6311.46-6311.99" - cell $and $and$ls180.v:6311$1763 + cell $and $and$ls180.v:6311$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258116,43 +260601,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6311$1763_Y + connect \Y $and$ls180.v:6311$1756_Y end attribute \src "ls180.v:6311.45-6311.150" - cell $and $and$ls180.v:6311$1765 + cell $and $and$ls180.v:6311$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$1763_Y - connect \B $eq$ls180.v:6311$1764_Y - connect \Y $and$ls180.v:6311$1765_Y + connect \A $and$ls180.v:6311$1756_Y + connect \B $eq$ls180.v:6311$1757_Y + connect \Y $and$ls180.v:6311$1758_Y end attribute \src "ls180.v:6312.46-6312.102" - cell $and $and$ls180.v:6312$1767 + cell $and $and$ls180.v:6312$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6312$1766_Y - connect \Y $and$ls180.v:6312$1767_Y + connect \B $not$ls180.v:6312$1759_Y + connect \Y $and$ls180.v:6312$1760_Y end attribute \src "ls180.v:6312.45-6312.153" - cell $and $and$ls180.v:6312$1769 + cell $and $and$ls180.v:6312$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6312$1767_Y - connect \B $eq$ls180.v:6312$1768_Y - connect \Y $and$ls180.v:6312$1769_Y + connect \A $and$ls180.v:6312$1760_Y + connect \B $eq$ls180.v:6312$1761_Y + connect \Y $and$ls180.v:6312$1762_Y end attribute \src "ls180.v:6314.46-6314.99" - cell $and $and$ls180.v:6314$1770 + cell $and $and$ls180.v:6314$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258160,43 +260645,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6314$1770_Y + connect \Y $and$ls180.v:6314$1763_Y end attribute \src "ls180.v:6314.45-6314.150" - cell $and $and$ls180.v:6314$1772 + cell $and $and$ls180.v:6314$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6314$1770_Y - connect \B $eq$ls180.v:6314$1771_Y - connect \Y $and$ls180.v:6314$1772_Y + connect \A $and$ls180.v:6314$1763_Y + connect \B $eq$ls180.v:6314$1764_Y + connect \Y $and$ls180.v:6314$1765_Y end attribute \src "ls180.v:6315.46-6315.102" - cell $and $and$ls180.v:6315$1774 + cell $and $and$ls180.v:6315$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6315$1773_Y - connect \Y $and$ls180.v:6315$1774_Y + connect \B $not$ls180.v:6315$1766_Y + connect \Y $and$ls180.v:6315$1767_Y end attribute \src "ls180.v:6315.45-6315.153" - cell $and $and$ls180.v:6315$1776 + cell $and $and$ls180.v:6315$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6315$1774_Y - connect \B $eq$ls180.v:6315$1775_Y - connect \Y $and$ls180.v:6315$1776_Y + connect \A $and$ls180.v:6315$1767_Y + connect \B $eq$ls180.v:6315$1768_Y + connect \Y $and$ls180.v:6315$1769_Y end attribute \src "ls180.v:6317.46-6317.99" - cell $and $and$ls180.v:6317$1777 + cell $and $and$ls180.v:6317$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258204,43 +260689,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6317$1777_Y + connect \Y $and$ls180.v:6317$1770_Y end attribute \src "ls180.v:6317.45-6317.150" - cell $and $and$ls180.v:6317$1779 + cell $and $and$ls180.v:6317$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6317$1777_Y - connect \B $eq$ls180.v:6317$1778_Y - connect \Y $and$ls180.v:6317$1779_Y + connect \A $and$ls180.v:6317$1770_Y + connect \B $eq$ls180.v:6317$1771_Y + connect \Y $and$ls180.v:6317$1772_Y end attribute \src "ls180.v:6318.46-6318.102" - cell $and $and$ls180.v:6318$1781 + cell $and $and$ls180.v:6318$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6318$1780_Y - connect \Y $and$ls180.v:6318$1781_Y + connect \B $not$ls180.v:6318$1773_Y + connect \Y $and$ls180.v:6318$1774_Y end attribute \src "ls180.v:6318.45-6318.153" - cell $and $and$ls180.v:6318$1783 + cell $and $and$ls180.v:6318$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$1781_Y - connect \B $eq$ls180.v:6318$1782_Y - connect \Y $and$ls180.v:6318$1783_Y + connect \A $and$ls180.v:6318$1774_Y + connect \B $eq$ls180.v:6318$1775_Y + connect \Y $and$ls180.v:6318$1776_Y end attribute \src "ls180.v:6320.46-6320.99" - cell $and $and$ls180.v:6320$1784 + cell $and $and$ls180.v:6320$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258248,43 +260733,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6320$1784_Y + connect \Y $and$ls180.v:6320$1777_Y end attribute \src "ls180.v:6320.45-6320.150" - cell $and $and$ls180.v:6320$1786 + cell $and $and$ls180.v:6320$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6320$1784_Y - connect \B $eq$ls180.v:6320$1785_Y - connect \Y $and$ls180.v:6320$1786_Y + connect \A $and$ls180.v:6320$1777_Y + connect \B $eq$ls180.v:6320$1778_Y + connect \Y $and$ls180.v:6320$1779_Y end attribute \src "ls180.v:6321.46-6321.102" - cell $and $and$ls180.v:6321$1788 + cell $and $and$ls180.v:6321$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6321$1787_Y - connect \Y $and$ls180.v:6321$1788_Y + connect \B $not$ls180.v:6321$1780_Y + connect \Y $and$ls180.v:6321$1781_Y end attribute \src "ls180.v:6321.45-6321.153" - cell $and $and$ls180.v:6321$1790 + cell $and $and$ls180.v:6321$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$1788_Y - connect \B $eq$ls180.v:6321$1789_Y - connect \Y $and$ls180.v:6321$1790_Y + connect \A $and$ls180.v:6321$1781_Y + connect \B $eq$ls180.v:6321$1782_Y + connect \Y $and$ls180.v:6321$1783_Y end attribute \src "ls180.v:6323.46-6323.99" - cell $and $and$ls180.v:6323$1791 + cell $and $and$ls180.v:6323$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258292,43 +260777,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6323$1791_Y + connect \Y $and$ls180.v:6323$1784_Y end attribute \src "ls180.v:6323.45-6323.150" - cell $and $and$ls180.v:6323$1793 + cell $and $and$ls180.v:6323$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6323$1791_Y - connect \B $eq$ls180.v:6323$1792_Y - connect \Y $and$ls180.v:6323$1793_Y + connect \A $and$ls180.v:6323$1784_Y + connect \B $eq$ls180.v:6323$1785_Y + connect \Y $and$ls180.v:6323$1786_Y end attribute \src "ls180.v:6324.46-6324.102" - cell $and $and$ls180.v:6324$1795 + cell $and $and$ls180.v:6324$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6324$1794_Y - connect \Y $and$ls180.v:6324$1795_Y + connect \B $not$ls180.v:6324$1787_Y + connect \Y $and$ls180.v:6324$1788_Y end attribute \src "ls180.v:6324.45-6324.153" - cell $and $and$ls180.v:6324$1797 + cell $and $and$ls180.v:6324$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$1795_Y - connect \B $eq$ls180.v:6324$1796_Y - connect \Y $and$ls180.v:6324$1797_Y + connect \A $and$ls180.v:6324$1788_Y + connect \B $eq$ls180.v:6324$1789_Y + connect \Y $and$ls180.v:6324$1790_Y end attribute \src "ls180.v:6326.46-6326.99" - cell $and $and$ls180.v:6326$1798 + cell $and $and$ls180.v:6326$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258336,43 +260821,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6326$1798_Y + connect \Y $and$ls180.v:6326$1791_Y end attribute \src "ls180.v:6326.45-6326.150" - cell $and $and$ls180.v:6326$1800 + cell $and $and$ls180.v:6326$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6326$1798_Y - connect \B $eq$ls180.v:6326$1799_Y - connect \Y $and$ls180.v:6326$1800_Y + connect \A $and$ls180.v:6326$1791_Y + connect \B $eq$ls180.v:6326$1792_Y + connect \Y $and$ls180.v:6326$1793_Y end attribute \src "ls180.v:6327.46-6327.102" - cell $and $and$ls180.v:6327$1802 + cell $and $and$ls180.v:6327$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6327$1801_Y - connect \Y $and$ls180.v:6327$1802_Y + connect \B $not$ls180.v:6327$1794_Y + connect \Y $and$ls180.v:6327$1795_Y end attribute \src "ls180.v:6327.45-6327.153" - cell $and $and$ls180.v:6327$1804 + cell $and $and$ls180.v:6327$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$1802_Y - connect \B $eq$ls180.v:6327$1803_Y - connect \Y $and$ls180.v:6327$1804_Y + connect \A $and$ls180.v:6327$1795_Y + connect \B $eq$ls180.v:6327$1796_Y + connect \Y $and$ls180.v:6327$1797_Y end attribute \src "ls180.v:6329.46-6329.99" - cell $and $and$ls180.v:6329$1805 + cell $and $and$ls180.v:6329$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258380,43 +260865,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6329$1805_Y + connect \Y $and$ls180.v:6329$1798_Y end attribute \src "ls180.v:6329.45-6329.150" - cell $and $and$ls180.v:6329$1807 + cell $and $and$ls180.v:6329$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6329$1805_Y - connect \B $eq$ls180.v:6329$1806_Y - connect \Y $and$ls180.v:6329$1807_Y + connect \A $and$ls180.v:6329$1798_Y + connect \B $eq$ls180.v:6329$1799_Y + connect \Y $and$ls180.v:6329$1800_Y end attribute \src "ls180.v:6330.46-6330.102" - cell $and $and$ls180.v:6330$1809 + cell $and $and$ls180.v:6330$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6330$1808_Y - connect \Y $and$ls180.v:6330$1809_Y + connect \B $not$ls180.v:6330$1801_Y + connect \Y $and$ls180.v:6330$1802_Y end attribute \src "ls180.v:6330.45-6330.153" - cell $and $and$ls180.v:6330$1811 + cell $and $and$ls180.v:6330$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6330$1809_Y - connect \B $eq$ls180.v:6330$1810_Y - connect \Y $and$ls180.v:6330$1811_Y + connect \A $and$ls180.v:6330$1802_Y + connect \B $eq$ls180.v:6330$1803_Y + connect \Y $and$ls180.v:6330$1804_Y end - attribute \src "ls180.v:6332.42-6332.95" - cell $and $and$ls180.v:6332$1812 + attribute \src "ls180.v:6332.46-6332.99" + cell $and $and$ls180.v:6332$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258424,43 +260909,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6332$1812_Y + connect \Y $and$ls180.v:6332$1805_Y end - attribute \src "ls180.v:6332.41-6332.146" - cell $and $and$ls180.v:6332$1814 + attribute \src "ls180.v:6332.45-6332.150" + cell $and $and$ls180.v:6332$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6332$1812_Y - connect \B $eq$ls180.v:6332$1813_Y - connect \Y $and$ls180.v:6332$1814_Y + connect \A $and$ls180.v:6332$1805_Y + connect \B $eq$ls180.v:6332$1806_Y + connect \Y $and$ls180.v:6332$1807_Y end - attribute \src "ls180.v:6333.42-6333.98" - cell $and $and$ls180.v:6333$1816 + attribute \src "ls180.v:6333.46-6333.102" + cell $and $and$ls180.v:6333$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6333$1815_Y - connect \Y $and$ls180.v:6333$1816_Y + connect \B $not$ls180.v:6333$1808_Y + connect \Y $and$ls180.v:6333$1809_Y end - attribute \src "ls180.v:6333.41-6333.149" - cell $and $and$ls180.v:6333$1818 + attribute \src "ls180.v:6333.45-6333.153" + cell $and $and$ls180.v:6333$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$1816_Y - connect \B $eq$ls180.v:6333$1817_Y - connect \Y $and$ls180.v:6333$1818_Y + connect \A $and$ls180.v:6333$1809_Y + connect \B $eq$ls180.v:6333$1810_Y + connect \Y $and$ls180.v:6333$1811_Y end - attribute \src "ls180.v:6335.43-6335.96" - cell $and $and$ls180.v:6335$1819 + attribute \src "ls180.v:6335.42-6335.95" + cell $and $and$ls180.v:6335$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258468,43 +260953,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6335$1819_Y + connect \Y $and$ls180.v:6335$1812_Y end - attribute \src "ls180.v:6335.42-6335.147" - cell $and $and$ls180.v:6335$1821 + attribute \src "ls180.v:6335.41-6335.146" + cell $and $and$ls180.v:6335$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6335$1819_Y - connect \B $eq$ls180.v:6335$1820_Y - connect \Y $and$ls180.v:6335$1821_Y + connect \A $and$ls180.v:6335$1812_Y + connect \B $eq$ls180.v:6335$1813_Y + connect \Y $and$ls180.v:6335$1814_Y end - attribute \src "ls180.v:6336.43-6336.99" - cell $and $and$ls180.v:6336$1823 + attribute \src "ls180.v:6336.42-6336.98" + cell $and $and$ls180.v:6336$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6336$1822_Y - connect \Y $and$ls180.v:6336$1823_Y + connect \B $not$ls180.v:6336$1815_Y + connect \Y $and$ls180.v:6336$1816_Y end - attribute \src "ls180.v:6336.42-6336.150" - cell $and $and$ls180.v:6336$1825 + attribute \src "ls180.v:6336.41-6336.149" + cell $and $and$ls180.v:6336$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6336$1823_Y - connect \B $eq$ls180.v:6336$1824_Y - connect \Y $and$ls180.v:6336$1825_Y + connect \A $and$ls180.v:6336$1816_Y + connect \B $eq$ls180.v:6336$1817_Y + connect \Y $and$ls180.v:6336$1818_Y end - attribute \src "ls180.v:6338.46-6338.99" - cell $and $and$ls180.v:6338$1826 + attribute \src "ls180.v:6338.43-6338.96" + cell $and $and$ls180.v:6338$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258512,43 +260997,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6338$1826_Y + connect \Y $and$ls180.v:6338$1819_Y end - attribute \src "ls180.v:6338.45-6338.150" - cell $and $and$ls180.v:6338$1828 + attribute \src "ls180.v:6338.42-6338.147" + cell $and $and$ls180.v:6338$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6338$1826_Y - connect \B $eq$ls180.v:6338$1827_Y - connect \Y $and$ls180.v:6338$1828_Y + connect \A $and$ls180.v:6338$1819_Y + connect \B $eq$ls180.v:6338$1820_Y + connect \Y $and$ls180.v:6338$1821_Y end - attribute \src "ls180.v:6339.46-6339.102" - cell $and $and$ls180.v:6339$1830 + attribute \src "ls180.v:6339.43-6339.99" + cell $and $and$ls180.v:6339$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6339$1829_Y - connect \Y $and$ls180.v:6339$1830_Y + connect \B $not$ls180.v:6339$1822_Y + connect \Y $and$ls180.v:6339$1823_Y end - attribute \src "ls180.v:6339.45-6339.153" - cell $and $and$ls180.v:6339$1832 + attribute \src "ls180.v:6339.42-6339.150" + cell $and $and$ls180.v:6339$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6339$1830_Y - connect \B $eq$ls180.v:6339$1831_Y - connect \Y $and$ls180.v:6339$1832_Y + connect \A $and$ls180.v:6339$1823_Y + connect \B $eq$ls180.v:6339$1824_Y + connect \Y $and$ls180.v:6339$1825_Y end attribute \src "ls180.v:6341.46-6341.99" - cell $and $and$ls180.v:6341$1833 + cell $and $and$ls180.v:6341$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258556,43 +261041,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6341$1833_Y + connect \Y $and$ls180.v:6341$1826_Y end attribute \src "ls180.v:6341.45-6341.150" - cell $and $and$ls180.v:6341$1835 + cell $and $and$ls180.v:6341$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6341$1833_Y - connect \B $eq$ls180.v:6341$1834_Y - connect \Y $and$ls180.v:6341$1835_Y + connect \A $and$ls180.v:6341$1826_Y + connect \B $eq$ls180.v:6341$1827_Y + connect \Y $and$ls180.v:6341$1828_Y end attribute \src "ls180.v:6342.46-6342.102" - cell $and $and$ls180.v:6342$1837 + cell $and $and$ls180.v:6342$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6342$1836_Y - connect \Y $and$ls180.v:6342$1837_Y + connect \B $not$ls180.v:6342$1829_Y + connect \Y $and$ls180.v:6342$1830_Y end attribute \src "ls180.v:6342.45-6342.153" - cell $and $and$ls180.v:6342$1839 + cell $and $and$ls180.v:6342$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6342$1837_Y - connect \B $eq$ls180.v:6342$1838_Y - connect \Y $and$ls180.v:6342$1839_Y + connect \A $and$ls180.v:6342$1830_Y + connect \B $eq$ls180.v:6342$1831_Y + connect \Y $and$ls180.v:6342$1832_Y end - attribute \src "ls180.v:6344.45-6344.98" - cell $and $and$ls180.v:6344$1840 + attribute \src "ls180.v:6344.46-6344.99" + cell $and $and$ls180.v:6344$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258600,43 +261085,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6344$1840_Y + connect \Y $and$ls180.v:6344$1833_Y end - attribute \src "ls180.v:6344.44-6344.149" - cell $and $and$ls180.v:6344$1842 + attribute \src "ls180.v:6344.45-6344.150" + cell $and $and$ls180.v:6344$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6344$1840_Y - connect \B $eq$ls180.v:6344$1841_Y - connect \Y $and$ls180.v:6344$1842_Y + connect \A $and$ls180.v:6344$1833_Y + connect \B $eq$ls180.v:6344$1834_Y + connect \Y $and$ls180.v:6344$1835_Y end - attribute \src "ls180.v:6345.45-6345.101" - cell $and $and$ls180.v:6345$1844 + attribute \src "ls180.v:6345.46-6345.102" + cell $and $and$ls180.v:6345$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6345$1843_Y - connect \Y $and$ls180.v:6345$1844_Y + connect \B $not$ls180.v:6345$1836_Y + connect \Y $and$ls180.v:6345$1837_Y end - attribute \src "ls180.v:6345.44-6345.152" - cell $and $and$ls180.v:6345$1846 + attribute \src "ls180.v:6345.45-6345.153" + cell $and $and$ls180.v:6345$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6345$1844_Y - connect \B $eq$ls180.v:6345$1845_Y - connect \Y $and$ls180.v:6345$1846_Y + connect \A $and$ls180.v:6345$1837_Y + connect \B $eq$ls180.v:6345$1838_Y + connect \Y $and$ls180.v:6345$1839_Y end attribute \src "ls180.v:6347.45-6347.98" - cell $and $and$ls180.v:6347$1847 + cell $and $and$ls180.v:6347$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258644,43 +261129,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6347$1847_Y + connect \Y $and$ls180.v:6347$1840_Y end attribute \src "ls180.v:6347.44-6347.149" - cell $and $and$ls180.v:6347$1849 + cell $and $and$ls180.v:6347$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6347$1847_Y - connect \B $eq$ls180.v:6347$1848_Y - connect \Y $and$ls180.v:6347$1849_Y + connect \A $and$ls180.v:6347$1840_Y + connect \B $eq$ls180.v:6347$1841_Y + connect \Y $and$ls180.v:6347$1842_Y end attribute \src "ls180.v:6348.45-6348.101" - cell $and $and$ls180.v:6348$1851 + cell $and $and$ls180.v:6348$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6348$1850_Y - connect \Y $and$ls180.v:6348$1851_Y + connect \B $not$ls180.v:6348$1843_Y + connect \Y $and$ls180.v:6348$1844_Y end attribute \src "ls180.v:6348.44-6348.152" - cell $and $and$ls180.v:6348$1853 + cell $and $and$ls180.v:6348$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6348$1851_Y - connect \B $eq$ls180.v:6348$1852_Y - connect \Y $and$ls180.v:6348$1853_Y + connect \A $and$ls180.v:6348$1844_Y + connect \B $eq$ls180.v:6348$1845_Y + connect \Y $and$ls180.v:6348$1846_Y end attribute \src "ls180.v:6350.45-6350.98" - cell $and $and$ls180.v:6350$1854 + cell $and $and$ls180.v:6350$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258688,43 +261173,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6350$1854_Y + connect \Y $and$ls180.v:6350$1847_Y end attribute \src "ls180.v:6350.44-6350.149" - cell $and $and$ls180.v:6350$1856 + cell $and $and$ls180.v:6350$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6350$1854_Y - connect \B $eq$ls180.v:6350$1855_Y - connect \Y $and$ls180.v:6350$1856_Y + connect \A $and$ls180.v:6350$1847_Y + connect \B $eq$ls180.v:6350$1848_Y + connect \Y $and$ls180.v:6350$1849_Y end attribute \src "ls180.v:6351.45-6351.101" - cell $and $and$ls180.v:6351$1858 + cell $and $and$ls180.v:6351$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6351$1857_Y - connect \Y $and$ls180.v:6351$1858_Y + connect \B $not$ls180.v:6351$1850_Y + connect \Y $and$ls180.v:6351$1851_Y end attribute \src "ls180.v:6351.44-6351.152" - cell $and $and$ls180.v:6351$1860 + cell $and $and$ls180.v:6351$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6351$1858_Y - connect \B $eq$ls180.v:6351$1859_Y - connect \Y $and$ls180.v:6351$1860_Y + connect \A $and$ls180.v:6351$1851_Y + connect \B $eq$ls180.v:6351$1852_Y + connect \Y $and$ls180.v:6351$1853_Y end attribute \src "ls180.v:6353.45-6353.98" - cell $and $and$ls180.v:6353$1861 + cell $and $and$ls180.v:6353$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258732,87 +261217,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6353$1861_Y + connect \Y $and$ls180.v:6353$1854_Y end attribute \src "ls180.v:6353.44-6353.149" - cell $and $and$ls180.v:6353$1863 + cell $and $and$ls180.v:6353$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6353$1861_Y - connect \B $eq$ls180.v:6353$1862_Y - connect \Y $and$ls180.v:6353$1863_Y + connect \A $and$ls180.v:6353$1854_Y + connect \B $eq$ls180.v:6353$1855_Y + connect \Y $and$ls180.v:6353$1856_Y end attribute \src "ls180.v:6354.45-6354.101" - cell $and $and$ls180.v:6354$1865 + cell $and $and$ls180.v:6354$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6354$1864_Y - connect \Y $and$ls180.v:6354$1865_Y + connect \B $not$ls180.v:6354$1857_Y + connect \Y $and$ls180.v:6354$1858_Y end attribute \src "ls180.v:6354.44-6354.152" - cell $and $and$ls180.v:6354$1867 + cell $and $and$ls180.v:6354$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6354$1865_Y - connect \B $eq$ls180.v:6354$1866_Y - connect \Y $and$ls180.v:6354$1867_Y + connect \A $and$ls180.v:6354$1858_Y + connect \B $eq$ls180.v:6354$1859_Y + connect \Y $and$ls180.v:6354$1860_Y end - attribute \src "ls180.v:6392.42-6392.95" - cell $and $and$ls180.v:6392$1869 + attribute \src "ls180.v:6356.45-6356.98" + cell $and $and$ls180.v:6356$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6392$1869_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6356$1861_Y end - attribute \src "ls180.v:6392.41-6392.145" - cell $and $and$ls180.v:6392$1871 + attribute \src "ls180.v:6356.44-6356.149" + cell $and $and$ls180.v:6356$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6392$1869_Y - connect \B $eq$ls180.v:6392$1870_Y - connect \Y $and$ls180.v:6392$1871_Y + connect \A $and$ls180.v:6356$1861_Y + connect \B $eq$ls180.v:6356$1862_Y + connect \Y $and$ls180.v:6356$1863_Y end - attribute \src "ls180.v:6393.42-6393.98" - cell $and $and$ls180.v:6393$1873 + attribute \src "ls180.v:6357.45-6357.101" + cell $and $and$ls180.v:6357$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6393$1872_Y - connect \Y $and$ls180.v:6393$1873_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6357$1864_Y + connect \Y $and$ls180.v:6357$1865_Y end - attribute \src "ls180.v:6393.41-6393.148" - cell $and $and$ls180.v:6393$1875 + attribute \src "ls180.v:6357.44-6357.152" + cell $and $and$ls180.v:6357$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6393$1873_Y - connect \B $eq$ls180.v:6393$1874_Y - connect \Y $and$ls180.v:6393$1875_Y + connect \A $and$ls180.v:6357$1865_Y + connect \B $eq$ls180.v:6357$1866_Y + connect \Y $and$ls180.v:6357$1867_Y end attribute \src "ls180.v:6395.42-6395.95" - cell $and $and$ls180.v:6395$1876 + cell $and $and$ls180.v:6395$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258820,43 +261305,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6395$1876_Y + connect \Y $and$ls180.v:6395$1869_Y end attribute \src "ls180.v:6395.41-6395.145" - cell $and $and$ls180.v:6395$1878 + cell $and $and$ls180.v:6395$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6395$1876_Y - connect \B $eq$ls180.v:6395$1877_Y - connect \Y $and$ls180.v:6395$1878_Y + connect \A $and$ls180.v:6395$1869_Y + connect \B $eq$ls180.v:6395$1870_Y + connect \Y $and$ls180.v:6395$1871_Y end attribute \src "ls180.v:6396.42-6396.98" - cell $and $and$ls180.v:6396$1880 + cell $and $and$ls180.v:6396$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6396$1879_Y - connect \Y $and$ls180.v:6396$1880_Y + connect \B $not$ls180.v:6396$1872_Y + connect \Y $and$ls180.v:6396$1873_Y end attribute \src "ls180.v:6396.41-6396.148" - cell $and $and$ls180.v:6396$1882 + cell $and $and$ls180.v:6396$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6396$1880_Y - connect \B $eq$ls180.v:6396$1881_Y - connect \Y $and$ls180.v:6396$1882_Y + connect \A $and$ls180.v:6396$1873_Y + connect \B $eq$ls180.v:6396$1874_Y + connect \Y $and$ls180.v:6396$1875_Y end attribute \src "ls180.v:6398.42-6398.95" - cell $and $and$ls180.v:6398$1883 + cell $and $and$ls180.v:6398$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258864,43 +261349,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6398$1883_Y + connect \Y $and$ls180.v:6398$1876_Y end attribute \src "ls180.v:6398.41-6398.145" - cell $and $and$ls180.v:6398$1885 + cell $and $and$ls180.v:6398$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6398$1883_Y - connect \B $eq$ls180.v:6398$1884_Y - connect \Y $and$ls180.v:6398$1885_Y + connect \A $and$ls180.v:6398$1876_Y + connect \B $eq$ls180.v:6398$1877_Y + connect \Y $and$ls180.v:6398$1878_Y end attribute \src "ls180.v:6399.42-6399.98" - cell $and $and$ls180.v:6399$1887 + cell $and $and$ls180.v:6399$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6399$1886_Y - connect \Y $and$ls180.v:6399$1887_Y + connect \B $not$ls180.v:6399$1879_Y + connect \Y $and$ls180.v:6399$1880_Y end attribute \src "ls180.v:6399.41-6399.148" - cell $and $and$ls180.v:6399$1889 + cell $and $and$ls180.v:6399$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6399$1887_Y - connect \B $eq$ls180.v:6399$1888_Y - connect \Y $and$ls180.v:6399$1889_Y + connect \A $and$ls180.v:6399$1880_Y + connect \B $eq$ls180.v:6399$1881_Y + connect \Y $and$ls180.v:6399$1882_Y end attribute \src "ls180.v:6401.42-6401.95" - cell $and $and$ls180.v:6401$1890 + cell $and $and$ls180.v:6401$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258908,43 +261393,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6401$1890_Y + connect \Y $and$ls180.v:6401$1883_Y end attribute \src "ls180.v:6401.41-6401.145" - cell $and $and$ls180.v:6401$1892 + cell $and $and$ls180.v:6401$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6401$1890_Y - connect \B $eq$ls180.v:6401$1891_Y - connect \Y $and$ls180.v:6401$1892_Y + connect \A $and$ls180.v:6401$1883_Y + connect \B $eq$ls180.v:6401$1884_Y + connect \Y $and$ls180.v:6401$1885_Y end attribute \src "ls180.v:6402.42-6402.98" - cell $and $and$ls180.v:6402$1894 + cell $and $and$ls180.v:6402$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6402$1893_Y - connect \Y $and$ls180.v:6402$1894_Y + connect \B $not$ls180.v:6402$1886_Y + connect \Y $and$ls180.v:6402$1887_Y end attribute \src "ls180.v:6402.41-6402.148" - cell $and $and$ls180.v:6402$1896 + cell $and $and$ls180.v:6402$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6402$1894_Y - connect \B $eq$ls180.v:6402$1895_Y - connect \Y $and$ls180.v:6402$1896_Y + connect \A $and$ls180.v:6402$1887_Y + connect \B $eq$ls180.v:6402$1888_Y + connect \Y $and$ls180.v:6402$1889_Y end attribute \src "ls180.v:6404.42-6404.95" - cell $and $and$ls180.v:6404$1897 + cell $and $and$ls180.v:6404$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258952,43 +261437,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6404$1897_Y + connect \Y $and$ls180.v:6404$1890_Y end attribute \src "ls180.v:6404.41-6404.145" - cell $and $and$ls180.v:6404$1899 + cell $and $and$ls180.v:6404$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6404$1897_Y - connect \B $eq$ls180.v:6404$1898_Y - connect \Y $and$ls180.v:6404$1899_Y + connect \A $and$ls180.v:6404$1890_Y + connect \B $eq$ls180.v:6404$1891_Y + connect \Y $and$ls180.v:6404$1892_Y end attribute \src "ls180.v:6405.42-6405.98" - cell $and $and$ls180.v:6405$1901 + cell $and $and$ls180.v:6405$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6405$1900_Y - connect \Y $and$ls180.v:6405$1901_Y + connect \B $not$ls180.v:6405$1893_Y + connect \Y $and$ls180.v:6405$1894_Y end attribute \src "ls180.v:6405.41-6405.148" - cell $and $and$ls180.v:6405$1903 + cell $and $and$ls180.v:6405$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6405$1901_Y - connect \B $eq$ls180.v:6405$1902_Y - connect \Y $and$ls180.v:6405$1903_Y + connect \A $and$ls180.v:6405$1894_Y + connect \B $eq$ls180.v:6405$1895_Y + connect \Y $and$ls180.v:6405$1896_Y end attribute \src "ls180.v:6407.42-6407.95" - cell $and $and$ls180.v:6407$1904 + cell $and $and$ls180.v:6407$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258996,43 +261481,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6407$1904_Y + connect \Y $and$ls180.v:6407$1897_Y end attribute \src "ls180.v:6407.41-6407.145" - cell $and $and$ls180.v:6407$1906 + cell $and $and$ls180.v:6407$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6407$1904_Y - connect \B $eq$ls180.v:6407$1905_Y - connect \Y $and$ls180.v:6407$1906_Y + connect \A $and$ls180.v:6407$1897_Y + connect \B $eq$ls180.v:6407$1898_Y + connect \Y $and$ls180.v:6407$1899_Y end attribute \src "ls180.v:6408.42-6408.98" - cell $and $and$ls180.v:6408$1908 + cell $and $and$ls180.v:6408$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6408$1907_Y - connect \Y $and$ls180.v:6408$1908_Y + connect \B $not$ls180.v:6408$1900_Y + connect \Y $and$ls180.v:6408$1901_Y end attribute \src "ls180.v:6408.41-6408.148" - cell $and $and$ls180.v:6408$1910 + cell $and $and$ls180.v:6408$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6408$1908_Y - connect \B $eq$ls180.v:6408$1909_Y - connect \Y $and$ls180.v:6408$1910_Y + connect \A $and$ls180.v:6408$1901_Y + connect \B $eq$ls180.v:6408$1902_Y + connect \Y $and$ls180.v:6408$1903_Y end attribute \src "ls180.v:6410.42-6410.95" - cell $and $and$ls180.v:6410$1911 + cell $and $and$ls180.v:6410$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259040,43 +261525,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6410$1911_Y + connect \Y $and$ls180.v:6410$1904_Y end attribute \src "ls180.v:6410.41-6410.145" - cell $and $and$ls180.v:6410$1913 + cell $and $and$ls180.v:6410$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6410$1911_Y - connect \B $eq$ls180.v:6410$1912_Y - connect \Y $and$ls180.v:6410$1913_Y + connect \A $and$ls180.v:6410$1904_Y + connect \B $eq$ls180.v:6410$1905_Y + connect \Y $and$ls180.v:6410$1906_Y end attribute \src "ls180.v:6411.42-6411.98" - cell $and $and$ls180.v:6411$1915 + cell $and $and$ls180.v:6411$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6411$1914_Y - connect \Y $and$ls180.v:6411$1915_Y + connect \B $not$ls180.v:6411$1907_Y + connect \Y $and$ls180.v:6411$1908_Y end attribute \src "ls180.v:6411.41-6411.148" - cell $and $and$ls180.v:6411$1917 + cell $and $and$ls180.v:6411$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6411$1915_Y - connect \B $eq$ls180.v:6411$1916_Y - connect \Y $and$ls180.v:6411$1917_Y + connect \A $and$ls180.v:6411$1908_Y + connect \B $eq$ls180.v:6411$1909_Y + connect \Y $and$ls180.v:6411$1910_Y end attribute \src "ls180.v:6413.42-6413.95" - cell $and $and$ls180.v:6413$1918 + cell $and $and$ls180.v:6413$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259084,43 +261569,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6413$1918_Y + connect \Y $and$ls180.v:6413$1911_Y end attribute \src "ls180.v:6413.41-6413.145" - cell $and $and$ls180.v:6413$1920 + cell $and $and$ls180.v:6413$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6413$1918_Y - connect \B $eq$ls180.v:6413$1919_Y - connect \Y $and$ls180.v:6413$1920_Y + connect \A $and$ls180.v:6413$1911_Y + connect \B $eq$ls180.v:6413$1912_Y + connect \Y $and$ls180.v:6413$1913_Y end attribute \src "ls180.v:6414.42-6414.98" - cell $and $and$ls180.v:6414$1922 + cell $and $and$ls180.v:6414$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6414$1921_Y - connect \Y $and$ls180.v:6414$1922_Y + connect \B $not$ls180.v:6414$1914_Y + connect \Y $and$ls180.v:6414$1915_Y end attribute \src "ls180.v:6414.41-6414.148" - cell $and $and$ls180.v:6414$1924 + cell $and $and$ls180.v:6414$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6414$1922_Y - connect \B $eq$ls180.v:6414$1923_Y - connect \Y $and$ls180.v:6414$1924_Y + connect \A $and$ls180.v:6414$1915_Y + connect \B $eq$ls180.v:6414$1916_Y + connect \Y $and$ls180.v:6414$1917_Y end - attribute \src "ls180.v:6416.44-6416.97" - cell $and $and$ls180.v:6416$1925 + attribute \src "ls180.v:6416.42-6416.95" + cell $and $and$ls180.v:6416$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259128,43 +261613,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6416$1925_Y + connect \Y $and$ls180.v:6416$1918_Y end - attribute \src "ls180.v:6416.43-6416.147" - cell $and $and$ls180.v:6416$1927 + attribute \src "ls180.v:6416.41-6416.145" + cell $and $and$ls180.v:6416$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6416$1925_Y - connect \B $eq$ls180.v:6416$1926_Y - connect \Y $and$ls180.v:6416$1927_Y + connect \A $and$ls180.v:6416$1918_Y + connect \B $eq$ls180.v:6416$1919_Y + connect \Y $and$ls180.v:6416$1920_Y end - attribute \src "ls180.v:6417.44-6417.100" - cell $and $and$ls180.v:6417$1929 + attribute \src "ls180.v:6417.42-6417.98" + cell $and $and$ls180.v:6417$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6417$1928_Y - connect \Y $and$ls180.v:6417$1929_Y + connect \B $not$ls180.v:6417$1921_Y + connect \Y $and$ls180.v:6417$1922_Y end - attribute \src "ls180.v:6417.43-6417.150" - cell $and $and$ls180.v:6417$1931 + attribute \src "ls180.v:6417.41-6417.148" + cell $and $and$ls180.v:6417$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6417$1929_Y - connect \B $eq$ls180.v:6417$1930_Y - connect \Y $and$ls180.v:6417$1931_Y + connect \A $and$ls180.v:6417$1922_Y + connect \B $eq$ls180.v:6417$1923_Y + connect \Y $and$ls180.v:6417$1924_Y end attribute \src "ls180.v:6419.44-6419.97" - cell $and $and$ls180.v:6419$1932 + cell $and $and$ls180.v:6419$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259172,43 +261657,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6419$1932_Y + connect \Y $and$ls180.v:6419$1925_Y end attribute \src "ls180.v:6419.43-6419.147" - cell $and $and$ls180.v:6419$1934 + cell $and $and$ls180.v:6419$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6419$1932_Y - connect \B $eq$ls180.v:6419$1933_Y - connect \Y $and$ls180.v:6419$1934_Y + connect \A $and$ls180.v:6419$1925_Y + connect \B $eq$ls180.v:6419$1926_Y + connect \Y $and$ls180.v:6419$1927_Y end attribute \src "ls180.v:6420.44-6420.100" - cell $and $and$ls180.v:6420$1936 + cell $and $and$ls180.v:6420$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6420$1935_Y - connect \Y $and$ls180.v:6420$1936_Y + connect \B $not$ls180.v:6420$1928_Y + connect \Y $and$ls180.v:6420$1929_Y end attribute \src "ls180.v:6420.43-6420.150" - cell $and $and$ls180.v:6420$1938 + cell $and $and$ls180.v:6420$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6420$1936_Y - connect \B $eq$ls180.v:6420$1937_Y - connect \Y $and$ls180.v:6420$1938_Y + connect \A $and$ls180.v:6420$1929_Y + connect \B $eq$ls180.v:6420$1930_Y + connect \Y $and$ls180.v:6420$1931_Y end attribute \src "ls180.v:6422.44-6422.97" - cell $and $and$ls180.v:6422$1939 + cell $and $and$ls180.v:6422$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259216,43 +261701,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6422$1939_Y + connect \Y $and$ls180.v:6422$1932_Y end - attribute \src "ls180.v:6422.43-6422.148" - cell $and $and$ls180.v:6422$1941 + attribute \src "ls180.v:6422.43-6422.147" + cell $and $and$ls180.v:6422$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6422$1939_Y - connect \B $eq$ls180.v:6422$1940_Y - connect \Y $and$ls180.v:6422$1941_Y + connect \A $and$ls180.v:6422$1932_Y + connect \B $eq$ls180.v:6422$1933_Y + connect \Y $and$ls180.v:6422$1934_Y end attribute \src "ls180.v:6423.44-6423.100" - cell $and $and$ls180.v:6423$1943 + cell $and $and$ls180.v:6423$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6423$1942_Y - connect \Y $and$ls180.v:6423$1943_Y + connect \B $not$ls180.v:6423$1935_Y + connect \Y $and$ls180.v:6423$1936_Y end - attribute \src "ls180.v:6423.43-6423.151" - cell $and $and$ls180.v:6423$1945 + attribute \src "ls180.v:6423.43-6423.150" + cell $and $and$ls180.v:6423$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6423$1943_Y - connect \B $eq$ls180.v:6423$1944_Y - connect \Y $and$ls180.v:6423$1945_Y + connect \A $and$ls180.v:6423$1936_Y + connect \B $eq$ls180.v:6423$1937_Y + connect \Y $and$ls180.v:6423$1938_Y end attribute \src "ls180.v:6425.44-6425.97" - cell $and $and$ls180.v:6425$1946 + cell $and $and$ls180.v:6425$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259260,43 +261745,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6425$1946_Y + connect \Y $and$ls180.v:6425$1939_Y end attribute \src "ls180.v:6425.43-6425.148" - cell $and $and$ls180.v:6425$1948 + cell $and $and$ls180.v:6425$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6425$1946_Y - connect \B $eq$ls180.v:6425$1947_Y - connect \Y $and$ls180.v:6425$1948_Y + connect \A $and$ls180.v:6425$1939_Y + connect \B $eq$ls180.v:6425$1940_Y + connect \Y $and$ls180.v:6425$1941_Y end attribute \src "ls180.v:6426.44-6426.100" - cell $and $and$ls180.v:6426$1950 + cell $and $and$ls180.v:6426$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6426$1949_Y - connect \Y $and$ls180.v:6426$1950_Y + connect \B $not$ls180.v:6426$1942_Y + connect \Y $and$ls180.v:6426$1943_Y end attribute \src "ls180.v:6426.43-6426.151" - cell $and $and$ls180.v:6426$1952 + cell $and $and$ls180.v:6426$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6426$1950_Y - connect \B $eq$ls180.v:6426$1951_Y - connect \Y $and$ls180.v:6426$1952_Y + connect \A $and$ls180.v:6426$1943_Y + connect \B $eq$ls180.v:6426$1944_Y + connect \Y $and$ls180.v:6426$1945_Y end attribute \src "ls180.v:6428.44-6428.97" - cell $and $and$ls180.v:6428$1953 + cell $and $and$ls180.v:6428$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259304,43 +261789,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6428$1953_Y + connect \Y $and$ls180.v:6428$1946_Y end attribute \src "ls180.v:6428.43-6428.148" - cell $and $and$ls180.v:6428$1955 + cell $and $and$ls180.v:6428$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6428$1953_Y - connect \B $eq$ls180.v:6428$1954_Y - connect \Y $and$ls180.v:6428$1955_Y + connect \A $and$ls180.v:6428$1946_Y + connect \B $eq$ls180.v:6428$1947_Y + connect \Y $and$ls180.v:6428$1948_Y end attribute \src "ls180.v:6429.44-6429.100" - cell $and $and$ls180.v:6429$1957 + cell $and $and$ls180.v:6429$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6429$1956_Y - connect \Y $and$ls180.v:6429$1957_Y + connect \B $not$ls180.v:6429$1949_Y + connect \Y $and$ls180.v:6429$1950_Y end attribute \src "ls180.v:6429.43-6429.151" - cell $and $and$ls180.v:6429$1959 + cell $and $and$ls180.v:6429$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6429$1957_Y - connect \B $eq$ls180.v:6429$1958_Y - connect \Y $and$ls180.v:6429$1959_Y + connect \A $and$ls180.v:6429$1950_Y + connect \B $eq$ls180.v:6429$1951_Y + connect \Y $and$ls180.v:6429$1952_Y end - attribute \src "ls180.v:6431.41-6431.94" - cell $and $and$ls180.v:6431$1960 + attribute \src "ls180.v:6431.44-6431.97" + cell $and $and$ls180.v:6431$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259348,43 +261833,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6431$1960_Y + connect \Y $and$ls180.v:6431$1953_Y end - attribute \src "ls180.v:6431.40-6431.145" - cell $and $and$ls180.v:6431$1962 + attribute \src "ls180.v:6431.43-6431.148" + cell $and $and$ls180.v:6431$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6431$1960_Y - connect \B $eq$ls180.v:6431$1961_Y - connect \Y $and$ls180.v:6431$1962_Y + connect \A $and$ls180.v:6431$1953_Y + connect \B $eq$ls180.v:6431$1954_Y + connect \Y $and$ls180.v:6431$1955_Y end - attribute \src "ls180.v:6432.41-6432.97" - cell $and $and$ls180.v:6432$1964 + attribute \src "ls180.v:6432.44-6432.100" + cell $and $and$ls180.v:6432$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6432$1963_Y - connect \Y $and$ls180.v:6432$1964_Y + connect \B $not$ls180.v:6432$1956_Y + connect \Y $and$ls180.v:6432$1957_Y end - attribute \src "ls180.v:6432.40-6432.148" - cell $and $and$ls180.v:6432$1966 + attribute \src "ls180.v:6432.43-6432.151" + cell $and $and$ls180.v:6432$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6432$1964_Y - connect \B $eq$ls180.v:6432$1965_Y - connect \Y $and$ls180.v:6432$1966_Y + connect \A $and$ls180.v:6432$1957_Y + connect \B $eq$ls180.v:6432$1958_Y + connect \Y $and$ls180.v:6432$1959_Y end - attribute \src "ls180.v:6434.42-6434.95" - cell $and $and$ls180.v:6434$1967 + attribute \src "ls180.v:6434.41-6434.94" + cell $and $and$ls180.v:6434$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259392,43 +261877,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6434$1967_Y + connect \Y $and$ls180.v:6434$1960_Y end - attribute \src "ls180.v:6434.41-6434.146" - cell $and $and$ls180.v:6434$1969 + attribute \src "ls180.v:6434.40-6434.145" + cell $and $and$ls180.v:6434$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6434$1967_Y - connect \B $eq$ls180.v:6434$1968_Y - connect \Y $and$ls180.v:6434$1969_Y + connect \A $and$ls180.v:6434$1960_Y + connect \B $eq$ls180.v:6434$1961_Y + connect \Y $and$ls180.v:6434$1962_Y end - attribute \src "ls180.v:6435.42-6435.98" - cell $and $and$ls180.v:6435$1971 + attribute \src "ls180.v:6435.41-6435.97" + cell $and $and$ls180.v:6435$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6435$1970_Y - connect \Y $and$ls180.v:6435$1971_Y + connect \B $not$ls180.v:6435$1963_Y + connect \Y $and$ls180.v:6435$1964_Y end - attribute \src "ls180.v:6435.41-6435.149" - cell $and $and$ls180.v:6435$1973 + attribute \src "ls180.v:6435.40-6435.148" + cell $and $and$ls180.v:6435$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6435$1971_Y - connect \B $eq$ls180.v:6435$1972_Y - connect \Y $and$ls180.v:6435$1973_Y + connect \A $and$ls180.v:6435$1964_Y + connect \B $eq$ls180.v:6435$1965_Y + connect \Y $and$ls180.v:6435$1966_Y end - attribute \src "ls180.v:6437.44-6437.97" - cell $and $and$ls180.v:6437$1974 + attribute \src "ls180.v:6437.42-6437.95" + cell $and $and$ls180.v:6437$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259436,43 +261921,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6437$1974_Y + connect \Y $and$ls180.v:6437$1967_Y end - attribute \src "ls180.v:6437.43-6437.148" - cell $and $and$ls180.v:6437$1976 + attribute \src "ls180.v:6437.41-6437.146" + cell $and $and$ls180.v:6437$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6437$1974_Y - connect \B $eq$ls180.v:6437$1975_Y - connect \Y $and$ls180.v:6437$1976_Y + connect \A $and$ls180.v:6437$1967_Y + connect \B $eq$ls180.v:6437$1968_Y + connect \Y $and$ls180.v:6437$1969_Y end - attribute \src "ls180.v:6438.44-6438.100" - cell $and $and$ls180.v:6438$1978 + attribute \src "ls180.v:6438.42-6438.98" + cell $and $and$ls180.v:6438$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6438$1977_Y - connect \Y $and$ls180.v:6438$1978_Y + connect \B $not$ls180.v:6438$1970_Y + connect \Y $and$ls180.v:6438$1971_Y end - attribute \src "ls180.v:6438.43-6438.151" - cell $and $and$ls180.v:6438$1980 + attribute \src "ls180.v:6438.41-6438.149" + cell $and $and$ls180.v:6438$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6438$1978_Y - connect \B $eq$ls180.v:6438$1979_Y - connect \Y $and$ls180.v:6438$1980_Y + connect \A $and$ls180.v:6438$1971_Y + connect \B $eq$ls180.v:6438$1972_Y + connect \Y $and$ls180.v:6438$1973_Y end attribute \src "ls180.v:6440.44-6440.97" - cell $and $and$ls180.v:6440$1981 + cell $and $and$ls180.v:6440$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259480,43 +261965,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6440$1981_Y + connect \Y $and$ls180.v:6440$1974_Y end attribute \src "ls180.v:6440.43-6440.148" - cell $and $and$ls180.v:6440$1983 + cell $and $and$ls180.v:6440$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6440$1981_Y - connect \B $eq$ls180.v:6440$1982_Y - connect \Y $and$ls180.v:6440$1983_Y + connect \A $and$ls180.v:6440$1974_Y + connect \B $eq$ls180.v:6440$1975_Y + connect \Y $and$ls180.v:6440$1976_Y end attribute \src "ls180.v:6441.44-6441.100" - cell $and $and$ls180.v:6441$1985 + cell $and $and$ls180.v:6441$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6441$1984_Y - connect \Y $and$ls180.v:6441$1985_Y + connect \B $not$ls180.v:6441$1977_Y + connect \Y $and$ls180.v:6441$1978_Y end attribute \src "ls180.v:6441.43-6441.151" - cell $and $and$ls180.v:6441$1987 + cell $and $and$ls180.v:6441$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6441$1985_Y - connect \B $eq$ls180.v:6441$1986_Y - connect \Y $and$ls180.v:6441$1987_Y + connect \A $and$ls180.v:6441$1978_Y + connect \B $eq$ls180.v:6441$1979_Y + connect \Y $and$ls180.v:6441$1980_Y end attribute \src "ls180.v:6443.44-6443.97" - cell $and $and$ls180.v:6443$1988 + cell $and $and$ls180.v:6443$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259524,43 +262009,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6443$1988_Y + connect \Y $and$ls180.v:6443$1981_Y end attribute \src "ls180.v:6443.43-6443.148" - cell $and $and$ls180.v:6443$1990 + cell $and $and$ls180.v:6443$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6443$1988_Y - connect \B $eq$ls180.v:6443$1989_Y - connect \Y $and$ls180.v:6443$1990_Y + connect \A $and$ls180.v:6443$1981_Y + connect \B $eq$ls180.v:6443$1982_Y + connect \Y $and$ls180.v:6443$1983_Y end attribute \src "ls180.v:6444.44-6444.100" - cell $and $and$ls180.v:6444$1992 + cell $and $and$ls180.v:6444$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6444$1991_Y - connect \Y $and$ls180.v:6444$1992_Y + connect \B $not$ls180.v:6444$1984_Y + connect \Y $and$ls180.v:6444$1985_Y end attribute \src "ls180.v:6444.43-6444.151" - cell $and $and$ls180.v:6444$1994 + cell $and $and$ls180.v:6444$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6444$1992_Y - connect \B $eq$ls180.v:6444$1993_Y - connect \Y $and$ls180.v:6444$1994_Y + connect \A $and$ls180.v:6444$1985_Y + connect \B $eq$ls180.v:6444$1986_Y + connect \Y $and$ls180.v:6444$1987_Y end attribute \src "ls180.v:6446.44-6446.97" - cell $and $and$ls180.v:6446$1995 + cell $and $and$ls180.v:6446$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259568,87 +262053,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6446$1995_Y + connect \Y $and$ls180.v:6446$1988_Y end attribute \src "ls180.v:6446.43-6446.148" - cell $and $and$ls180.v:6446$1997 + cell $and $and$ls180.v:6446$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6446$1995_Y - connect \B $eq$ls180.v:6446$1996_Y - connect \Y $and$ls180.v:6446$1997_Y + connect \A $and$ls180.v:6446$1988_Y + connect \B $eq$ls180.v:6446$1989_Y + connect \Y $and$ls180.v:6446$1990_Y end attribute \src "ls180.v:6447.44-6447.100" - cell $and $and$ls180.v:6447$1999 + cell $and $and$ls180.v:6447$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6447$1998_Y - connect \Y $and$ls180.v:6447$1999_Y + connect \B $not$ls180.v:6447$1991_Y + connect \Y $and$ls180.v:6447$1992_Y end attribute \src "ls180.v:6447.43-6447.151" - cell $and $and$ls180.v:6447$2001 + cell $and $and$ls180.v:6447$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6447$1999_Y - connect \B $eq$ls180.v:6447$2000_Y - connect \Y $and$ls180.v:6447$2001_Y + connect \A $and$ls180.v:6447$1992_Y + connect \B $eq$ls180.v:6447$1993_Y + connect \Y $and$ls180.v:6447$1994_Y end - attribute \src "ls180.v:6471.44-6471.97" - cell $and $and$ls180.v:6471$2003 + attribute \src "ls180.v:6449.44-6449.97" + cell $and $and$ls180.v:6449$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6471$2003_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6449$1995_Y end - attribute \src "ls180.v:6471.43-6471.147" - cell $and $and$ls180.v:6471$2005 + attribute \src "ls180.v:6449.43-6449.148" + cell $and $and$ls180.v:6449$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6471$2003_Y - connect \B $eq$ls180.v:6471$2004_Y - connect \Y $and$ls180.v:6471$2005_Y + connect \A $and$ls180.v:6449$1995_Y + connect \B $eq$ls180.v:6449$1996_Y + connect \Y $and$ls180.v:6449$1997_Y end - attribute \src "ls180.v:6472.44-6472.100" - cell $and $and$ls180.v:6472$2007 + attribute \src "ls180.v:6450.44-6450.100" + cell $and $and$ls180.v:6450$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6472$2006_Y - connect \Y $and$ls180.v:6472$2007_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6450$1998_Y + connect \Y $and$ls180.v:6450$1999_Y end - attribute \src "ls180.v:6472.43-6472.150" - cell $and $and$ls180.v:6472$2009 + attribute \src "ls180.v:6450.43-6450.151" + cell $and $and$ls180.v:6450$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6472$2007_Y - connect \B $eq$ls180.v:6472$2008_Y - connect \Y $and$ls180.v:6472$2009_Y + connect \A $and$ls180.v:6450$1999_Y + connect \B $eq$ls180.v:6450$2000_Y + connect \Y $and$ls180.v:6450$2001_Y end - attribute \src "ls180.v:6474.49-6474.102" - cell $and $and$ls180.v:6474$2010 + attribute \src "ls180.v:6474.44-6474.97" + cell $and $and$ls180.v:6474$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259656,43 +262141,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6474$2010_Y + connect \Y $and$ls180.v:6474$2003_Y end - attribute \src "ls180.v:6474.48-6474.152" - cell $and $and$ls180.v:6474$2012 + attribute \src "ls180.v:6474.43-6474.147" + cell $and $and$ls180.v:6474$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6474$2010_Y - connect \B $eq$ls180.v:6474$2011_Y - connect \Y $and$ls180.v:6474$2012_Y + connect \A $and$ls180.v:6474$2003_Y + connect \B $eq$ls180.v:6474$2004_Y + connect \Y $and$ls180.v:6474$2005_Y end - attribute \src "ls180.v:6475.49-6475.105" - cell $and $and$ls180.v:6475$2014 + attribute \src "ls180.v:6475.44-6475.100" + cell $and $and$ls180.v:6475$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6475$2013_Y - connect \Y $and$ls180.v:6475$2014_Y + connect \B $not$ls180.v:6475$2006_Y + connect \Y $and$ls180.v:6475$2007_Y end - attribute \src "ls180.v:6475.48-6475.155" - cell $and $and$ls180.v:6475$2016 + attribute \src "ls180.v:6475.43-6475.150" + cell $and $and$ls180.v:6475$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6475$2014_Y - connect \B $eq$ls180.v:6475$2015_Y - connect \Y $and$ls180.v:6475$2016_Y + connect \A $and$ls180.v:6475$2007_Y + connect \B $eq$ls180.v:6475$2008_Y + connect \Y $and$ls180.v:6475$2009_Y end attribute \src "ls180.v:6477.49-6477.102" - cell $and $and$ls180.v:6477$2017 + cell $and $and$ls180.v:6477$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259700,43 +262185,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6477$2017_Y + connect \Y $and$ls180.v:6477$2010_Y end attribute \src "ls180.v:6477.48-6477.152" - cell $and $and$ls180.v:6477$2019 + cell $and $and$ls180.v:6477$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6477$2017_Y - connect \B $eq$ls180.v:6477$2018_Y - connect \Y $and$ls180.v:6477$2019_Y + connect \A $and$ls180.v:6477$2010_Y + connect \B $eq$ls180.v:6477$2011_Y + connect \Y $and$ls180.v:6477$2012_Y end attribute \src "ls180.v:6478.49-6478.105" - cell $and $and$ls180.v:6478$2021 + cell $and $and$ls180.v:6478$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6478$2020_Y - connect \Y $and$ls180.v:6478$2021_Y + connect \B $not$ls180.v:6478$2013_Y + connect \Y $and$ls180.v:6478$2014_Y end attribute \src "ls180.v:6478.48-6478.155" - cell $and $and$ls180.v:6478$2023 + cell $and $and$ls180.v:6478$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6478$2021_Y - connect \B $eq$ls180.v:6478$2022_Y - connect \Y $and$ls180.v:6478$2023_Y + connect \A $and$ls180.v:6478$2014_Y + connect \B $eq$ls180.v:6478$2015_Y + connect \Y $and$ls180.v:6478$2016_Y end - attribute \src "ls180.v:6480.42-6480.95" - cell $and $and$ls180.v:6480$2024 + attribute \src "ls180.v:6480.49-6480.102" + cell $and $and$ls180.v:6480$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259744,87 +262229,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6480$2024_Y + connect \Y $and$ls180.v:6480$2017_Y end - attribute \src "ls180.v:6480.41-6480.145" - cell $and $and$ls180.v:6480$2026 + attribute \src "ls180.v:6480.48-6480.152" + cell $and $and$ls180.v:6480$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6480$2024_Y - connect \B $eq$ls180.v:6480$2025_Y - connect \Y $and$ls180.v:6480$2026_Y + connect \A $and$ls180.v:6480$2017_Y + connect \B $eq$ls180.v:6480$2018_Y + connect \Y $and$ls180.v:6480$2019_Y end - attribute \src "ls180.v:6481.42-6481.98" - cell $and $and$ls180.v:6481$2028 + attribute \src "ls180.v:6481.49-6481.105" + cell $and $and$ls180.v:6481$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6481$2027_Y - connect \Y $and$ls180.v:6481$2028_Y + connect \B $not$ls180.v:6481$2020_Y + connect \Y $and$ls180.v:6481$2021_Y end - attribute \src "ls180.v:6481.41-6481.148" - cell $and $and$ls180.v:6481$2030 + attribute \src "ls180.v:6481.48-6481.155" + cell $and $and$ls180.v:6481$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6481$2028_Y - connect \B $eq$ls180.v:6481$2029_Y - connect \Y $and$ls180.v:6481$2030_Y + connect \A $and$ls180.v:6481$2021_Y + connect \B $eq$ls180.v:6481$2022_Y + connect \Y $and$ls180.v:6481$2023_Y end - attribute \src "ls180.v:6488.46-6488.99" - cell $and $and$ls180.v:6488$2032 + attribute \src "ls180.v:6483.42-6483.95" + cell $and $and$ls180.v:6483$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6488$2032_Y + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6483$2024_Y end - attribute \src "ls180.v:6488.45-6488.149" - cell $and $and$ls180.v:6488$2034 + attribute \src "ls180.v:6483.41-6483.145" + cell $and $and$ls180.v:6483$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6488$2032_Y - connect \B $eq$ls180.v:6488$2033_Y - connect \Y $and$ls180.v:6488$2034_Y + connect \A $and$ls180.v:6483$2024_Y + connect \B $eq$ls180.v:6483$2025_Y + connect \Y $and$ls180.v:6483$2026_Y end - attribute \src "ls180.v:6489.46-6489.102" - cell $and $and$ls180.v:6489$2036 + attribute \src "ls180.v:6484.42-6484.98" + cell $and $and$ls180.v:6484$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6489$2035_Y - connect \Y $and$ls180.v:6489$2036_Y + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6484$2027_Y + connect \Y $and$ls180.v:6484$2028_Y end - attribute \src "ls180.v:6489.45-6489.152" - cell $and $and$ls180.v:6489$2038 + attribute \src "ls180.v:6484.41-6484.148" + cell $and $and$ls180.v:6484$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6489$2036_Y - connect \B $eq$ls180.v:6489$2037_Y - connect \Y $and$ls180.v:6489$2038_Y + connect \A $and$ls180.v:6484$2028_Y + connect \B $eq$ls180.v:6484$2029_Y + connect \Y $and$ls180.v:6484$2030_Y end - attribute \src "ls180.v:6491.50-6491.103" - cell $and $and$ls180.v:6491$2039 + attribute \src "ls180.v:6491.46-6491.99" + cell $and $and$ls180.v:6491$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259832,43 +262317,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6491$2039_Y + connect \Y $and$ls180.v:6491$2032_Y end - attribute \src "ls180.v:6491.49-6491.153" - cell $and $and$ls180.v:6491$2041 + attribute \src "ls180.v:6491.45-6491.149" + cell $and $and$ls180.v:6491$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6491$2039_Y - connect \B $eq$ls180.v:6491$2040_Y - connect \Y $and$ls180.v:6491$2041_Y + connect \A $and$ls180.v:6491$2032_Y + connect \B $eq$ls180.v:6491$2033_Y + connect \Y $and$ls180.v:6491$2034_Y end - attribute \src "ls180.v:6492.50-6492.106" - cell $and $and$ls180.v:6492$2043 + attribute \src "ls180.v:6492.46-6492.102" + cell $and $and$ls180.v:6492$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6492$2042_Y - connect \Y $and$ls180.v:6492$2043_Y + connect \B $not$ls180.v:6492$2035_Y + connect \Y $and$ls180.v:6492$2036_Y end - attribute \src "ls180.v:6492.49-6492.156" - cell $and $and$ls180.v:6492$2045 + attribute \src "ls180.v:6492.45-6492.152" + cell $and $and$ls180.v:6492$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6492$2043_Y - connect \B $eq$ls180.v:6492$2044_Y - connect \Y $and$ls180.v:6492$2045_Y + connect \A $and$ls180.v:6492$2036_Y + connect \B $eq$ls180.v:6492$2037_Y + connect \Y $and$ls180.v:6492$2038_Y end - attribute \src "ls180.v:6494.40-6494.93" - cell $and $and$ls180.v:6494$2046 + attribute \src "ls180.v:6494.50-6494.103" + cell $and $and$ls180.v:6494$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259876,43 +262361,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6494$2046_Y + connect \Y $and$ls180.v:6494$2039_Y end - attribute \src "ls180.v:6494.39-6494.143" - cell $and $and$ls180.v:6494$2048 + attribute \src "ls180.v:6494.49-6494.153" + cell $and $and$ls180.v:6494$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6494$2046_Y - connect \B $eq$ls180.v:6494$2047_Y - connect \Y $and$ls180.v:6494$2048_Y + connect \A $and$ls180.v:6494$2039_Y + connect \B $eq$ls180.v:6494$2040_Y + connect \Y $and$ls180.v:6494$2041_Y end - attribute \src "ls180.v:6495.40-6495.96" - cell $and $and$ls180.v:6495$2050 + attribute \src "ls180.v:6495.50-6495.106" + cell $and $and$ls180.v:6495$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6495$2049_Y - connect \Y $and$ls180.v:6495$2050_Y + connect \B $not$ls180.v:6495$2042_Y + connect \Y $and$ls180.v:6495$2043_Y end - attribute \src "ls180.v:6495.39-6495.146" - cell $and $and$ls180.v:6495$2052 + attribute \src "ls180.v:6495.49-6495.156" + cell $and $and$ls180.v:6495$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6495$2050_Y - connect \B $eq$ls180.v:6495$2051_Y - connect \Y $and$ls180.v:6495$2052_Y + connect \A $and$ls180.v:6495$2043_Y + connect \B $eq$ls180.v:6495$2044_Y + connect \Y $and$ls180.v:6495$2045_Y end - attribute \src "ls180.v:6497.50-6497.103" - cell $and $and$ls180.v:6497$2053 + attribute \src "ls180.v:6497.40-6497.93" + cell $and $and$ls180.v:6497$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259920,43 +262405,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6497$2053_Y + connect \Y $and$ls180.v:6497$2046_Y end - attribute \src "ls180.v:6497.49-6497.153" - cell $and $and$ls180.v:6497$2055 + attribute \src "ls180.v:6497.39-6497.143" + cell $and $and$ls180.v:6497$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6497$2053_Y - connect \B $eq$ls180.v:6497$2054_Y - connect \Y $and$ls180.v:6497$2055_Y + connect \A $and$ls180.v:6497$2046_Y + connect \B $eq$ls180.v:6497$2047_Y + connect \Y $and$ls180.v:6497$2048_Y end - attribute \src "ls180.v:6498.50-6498.106" - cell $and $and$ls180.v:6498$2057 + attribute \src "ls180.v:6498.40-6498.96" + cell $and $and$ls180.v:6498$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6498$2056_Y - connect \Y $and$ls180.v:6498$2057_Y + connect \B $not$ls180.v:6498$2049_Y + connect \Y $and$ls180.v:6498$2050_Y end - attribute \src "ls180.v:6498.49-6498.156" - cell $and $and$ls180.v:6498$2059 + attribute \src "ls180.v:6498.39-6498.146" + cell $and $and$ls180.v:6498$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6498$2057_Y - connect \B $eq$ls180.v:6498$2058_Y - connect \Y $and$ls180.v:6498$2059_Y + connect \A $and$ls180.v:6498$2050_Y + connect \B $eq$ls180.v:6498$2051_Y + connect \Y $and$ls180.v:6498$2052_Y end attribute \src "ls180.v:6500.50-6500.103" - cell $and $and$ls180.v:6500$2060 + cell $and $and$ls180.v:6500$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259964,43 +262449,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6500$2060_Y + connect \Y $and$ls180.v:6500$2053_Y end attribute \src "ls180.v:6500.49-6500.153" - cell $and $and$ls180.v:6500$2062 + cell $and $and$ls180.v:6500$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6500$2060_Y - connect \B $eq$ls180.v:6500$2061_Y - connect \Y $and$ls180.v:6500$2062_Y + connect \A $and$ls180.v:6500$2053_Y + connect \B $eq$ls180.v:6500$2054_Y + connect \Y $and$ls180.v:6500$2055_Y end attribute \src "ls180.v:6501.50-6501.106" - cell $and $and$ls180.v:6501$2064 + cell $and $and$ls180.v:6501$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6501$2063_Y - connect \Y $and$ls180.v:6501$2064_Y + connect \B $not$ls180.v:6501$2056_Y + connect \Y $and$ls180.v:6501$2057_Y end attribute \src "ls180.v:6501.49-6501.156" - cell $and $and$ls180.v:6501$2066 + cell $and $and$ls180.v:6501$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6501$2064_Y - connect \B $eq$ls180.v:6501$2065_Y - connect \Y $and$ls180.v:6501$2066_Y + connect \A $and$ls180.v:6501$2057_Y + connect \B $eq$ls180.v:6501$2058_Y + connect \Y $and$ls180.v:6501$2059_Y end - attribute \src "ls180.v:6503.51-6503.104" - cell $and $and$ls180.v:6503$2067 + attribute \src "ls180.v:6503.50-6503.103" + cell $and $and$ls180.v:6503$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260008,43 +262493,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6503$2067_Y + connect \Y $and$ls180.v:6503$2060_Y end - attribute \src "ls180.v:6503.50-6503.154" - cell $and $and$ls180.v:6503$2069 + attribute \src "ls180.v:6503.49-6503.153" + cell $and $and$ls180.v:6503$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6503$2067_Y - connect \B $eq$ls180.v:6503$2068_Y - connect \Y $and$ls180.v:6503$2069_Y + connect \A $and$ls180.v:6503$2060_Y + connect \B $eq$ls180.v:6503$2061_Y + connect \Y $and$ls180.v:6503$2062_Y end - attribute \src "ls180.v:6504.51-6504.107" - cell $and $and$ls180.v:6504$2071 + attribute \src "ls180.v:6504.50-6504.106" + cell $and $and$ls180.v:6504$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6504$2070_Y - connect \Y $and$ls180.v:6504$2071_Y + connect \B $not$ls180.v:6504$2063_Y + connect \Y $and$ls180.v:6504$2064_Y end - attribute \src "ls180.v:6504.50-6504.157" - cell $and $and$ls180.v:6504$2073 + attribute \src "ls180.v:6504.49-6504.156" + cell $and $and$ls180.v:6504$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6504$2071_Y - connect \B $eq$ls180.v:6504$2072_Y - connect \Y $and$ls180.v:6504$2073_Y + connect \A $and$ls180.v:6504$2064_Y + connect \B $eq$ls180.v:6504$2065_Y + connect \Y $and$ls180.v:6504$2066_Y end - attribute \src "ls180.v:6506.49-6506.102" - cell $and $and$ls180.v:6506$2074 + attribute \src "ls180.v:6506.51-6506.104" + cell $and $and$ls180.v:6506$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260052,43 +262537,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6506$2074_Y + connect \Y $and$ls180.v:6506$2067_Y end - attribute \src "ls180.v:6506.48-6506.152" - cell $and $and$ls180.v:6506$2076 + attribute \src "ls180.v:6506.50-6506.154" + cell $and $and$ls180.v:6506$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6506$2074_Y - connect \B $eq$ls180.v:6506$2075_Y - connect \Y $and$ls180.v:6506$2076_Y + connect \A $and$ls180.v:6506$2067_Y + connect \B $eq$ls180.v:6506$2068_Y + connect \Y $and$ls180.v:6506$2069_Y end - attribute \src "ls180.v:6507.49-6507.105" - cell $and $and$ls180.v:6507$2078 + attribute \src "ls180.v:6507.51-6507.107" + cell $and $and$ls180.v:6507$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6507$2077_Y - connect \Y $and$ls180.v:6507$2078_Y + connect \B $not$ls180.v:6507$2070_Y + connect \Y $and$ls180.v:6507$2071_Y end - attribute \src "ls180.v:6507.48-6507.155" - cell $and $and$ls180.v:6507$2080 + attribute \src "ls180.v:6507.50-6507.157" + cell $and $and$ls180.v:6507$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6507$2078_Y - connect \B $eq$ls180.v:6507$2079_Y - connect \Y $and$ls180.v:6507$2080_Y + connect \A $and$ls180.v:6507$2071_Y + connect \B $eq$ls180.v:6507$2072_Y + connect \Y $and$ls180.v:6507$2073_Y end attribute \src "ls180.v:6509.49-6509.102" - cell $and $and$ls180.v:6509$2081 + cell $and $and$ls180.v:6509$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260096,43 +262581,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6509$2081_Y + connect \Y $and$ls180.v:6509$2074_Y end attribute \src "ls180.v:6509.48-6509.152" - cell $and $and$ls180.v:6509$2083 + cell $and $and$ls180.v:6509$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6509$2081_Y - connect \B $eq$ls180.v:6509$2082_Y - connect \Y $and$ls180.v:6509$2083_Y + connect \A $and$ls180.v:6509$2074_Y + connect \B $eq$ls180.v:6509$2075_Y + connect \Y $and$ls180.v:6509$2076_Y end attribute \src "ls180.v:6510.49-6510.105" - cell $and $and$ls180.v:6510$2085 + cell $and $and$ls180.v:6510$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6510$2084_Y - connect \Y $and$ls180.v:6510$2085_Y + connect \B $not$ls180.v:6510$2077_Y + connect \Y $and$ls180.v:6510$2078_Y end attribute \src "ls180.v:6510.48-6510.155" - cell $and $and$ls180.v:6510$2087 + cell $and $and$ls180.v:6510$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6510$2085_Y - connect \B $eq$ls180.v:6510$2086_Y - connect \Y $and$ls180.v:6510$2087_Y + connect \A $and$ls180.v:6510$2078_Y + connect \B $eq$ls180.v:6510$2079_Y + connect \Y $and$ls180.v:6510$2080_Y end attribute \src "ls180.v:6512.49-6512.102" - cell $and $and$ls180.v:6512$2088 + cell $and $and$ls180.v:6512$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260140,43 +262625,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6512$2088_Y + connect \Y $and$ls180.v:6512$2081_Y end attribute \src "ls180.v:6512.48-6512.152" - cell $and $and$ls180.v:6512$2090 + cell $and $and$ls180.v:6512$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6512$2088_Y - connect \B $eq$ls180.v:6512$2089_Y - connect \Y $and$ls180.v:6512$2090_Y + connect \A $and$ls180.v:6512$2081_Y + connect \B $eq$ls180.v:6512$2082_Y + connect \Y $and$ls180.v:6512$2083_Y end attribute \src "ls180.v:6513.49-6513.105" - cell $and $and$ls180.v:6513$2092 + cell $and $and$ls180.v:6513$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6513$2091_Y - connect \Y $and$ls180.v:6513$2092_Y + connect \B $not$ls180.v:6513$2084_Y + connect \Y $and$ls180.v:6513$2085_Y end attribute \src "ls180.v:6513.48-6513.155" - cell $and $and$ls180.v:6513$2094 + cell $and $and$ls180.v:6513$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6513$2092_Y - connect \B $eq$ls180.v:6513$2093_Y - connect \Y $and$ls180.v:6513$2094_Y + connect \A $and$ls180.v:6513$2085_Y + connect \B $eq$ls180.v:6513$2086_Y + connect \Y $and$ls180.v:6513$2087_Y end attribute \src "ls180.v:6515.49-6515.102" - cell $and $and$ls180.v:6515$2095 + cell $and $and$ls180.v:6515$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260184,87 +262669,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6515$2095_Y + connect \Y $and$ls180.v:6515$2088_Y end attribute \src "ls180.v:6515.48-6515.152" - cell $and $and$ls180.v:6515$2097 + cell $and $and$ls180.v:6515$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6515$2095_Y - connect \B $eq$ls180.v:6515$2096_Y - connect \Y $and$ls180.v:6515$2097_Y + connect \A $and$ls180.v:6515$2088_Y + connect \B $eq$ls180.v:6515$2089_Y + connect \Y $and$ls180.v:6515$2090_Y end attribute \src "ls180.v:6516.49-6516.105" - cell $and $and$ls180.v:6516$2099 + cell $and $and$ls180.v:6516$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6516$2098_Y - connect \Y $and$ls180.v:6516$2099_Y + connect \B $not$ls180.v:6516$2091_Y + connect \Y $and$ls180.v:6516$2092_Y end attribute \src "ls180.v:6516.48-6516.155" - cell $and $and$ls180.v:6516$2101 + cell $and $and$ls180.v:6516$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6516$2099_Y - connect \B $eq$ls180.v:6516$2100_Y - connect \Y $and$ls180.v:6516$2101_Y + connect \A $and$ls180.v:6516$2092_Y + connect \B $eq$ls180.v:6516$2093_Y + connect \Y $and$ls180.v:6516$2094_Y end - attribute \src "ls180.v:6533.42-6533.97" - cell $and $and$ls180.v:6533$2103 + attribute \src "ls180.v:6518.49-6518.102" + cell $and $and$ls180.v:6518$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6533$2103_Y + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6518$2095_Y end - attribute \src "ls180.v:6533.41-6533.148" - cell $and $and$ls180.v:6533$2105 + attribute \src "ls180.v:6518.48-6518.152" + cell $and $and$ls180.v:6518$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6533$2103_Y - connect \B $eq$ls180.v:6533$2104_Y - connect \Y $and$ls180.v:6533$2105_Y + connect \A $and$ls180.v:6518$2095_Y + connect \B $eq$ls180.v:6518$2096_Y + connect \Y $and$ls180.v:6518$2097_Y end - attribute \src "ls180.v:6534.42-6534.100" - cell $and $and$ls180.v:6534$2107 + attribute \src "ls180.v:6519.49-6519.105" + cell $and $and$ls180.v:6519$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6534$2106_Y - connect \Y $and$ls180.v:6534$2107_Y + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6519$2098_Y + connect \Y $and$ls180.v:6519$2099_Y end - attribute \src "ls180.v:6534.41-6534.151" - cell $and $and$ls180.v:6534$2109 + attribute \src "ls180.v:6519.48-6519.155" + cell $and $and$ls180.v:6519$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6534$2107_Y - connect \B $eq$ls180.v:6534$2108_Y - connect \Y $and$ls180.v:6534$2109_Y + connect \A $and$ls180.v:6519$2099_Y + connect \B $eq$ls180.v:6519$2100_Y + connect \Y $and$ls180.v:6519$2101_Y end attribute \src "ls180.v:6536.42-6536.97" - cell $and $and$ls180.v:6536$2110 + cell $and $and$ls180.v:6536$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260272,43 +262757,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6536$2110_Y + connect \Y $and$ls180.v:6536$2103_Y end attribute \src "ls180.v:6536.41-6536.148" - cell $and $and$ls180.v:6536$2112 + cell $and $and$ls180.v:6536$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6536$2110_Y - connect \B $eq$ls180.v:6536$2111_Y - connect \Y $and$ls180.v:6536$2112_Y + connect \A $and$ls180.v:6536$2103_Y + connect \B $eq$ls180.v:6536$2104_Y + connect \Y $and$ls180.v:6536$2105_Y end attribute \src "ls180.v:6537.42-6537.100" - cell $and $and$ls180.v:6537$2114 + cell $and $and$ls180.v:6537$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6537$2113_Y - connect \Y $and$ls180.v:6537$2114_Y + connect \B $not$ls180.v:6537$2106_Y + connect \Y $and$ls180.v:6537$2107_Y end attribute \src "ls180.v:6537.41-6537.151" - cell $and $and$ls180.v:6537$2116 + cell $and $and$ls180.v:6537$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6537$2114_Y - connect \B $eq$ls180.v:6537$2115_Y - connect \Y $and$ls180.v:6537$2116_Y + connect \A $and$ls180.v:6537$2107_Y + connect \B $eq$ls180.v:6537$2108_Y + connect \Y $and$ls180.v:6537$2109_Y end - attribute \src "ls180.v:6539.40-6539.95" - cell $and $and$ls180.v:6539$2117 + attribute \src "ls180.v:6539.42-6539.97" + cell $and $and$ls180.v:6539$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260316,43 +262801,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6539$2117_Y + connect \Y $and$ls180.v:6539$2110_Y end - attribute \src "ls180.v:6539.39-6539.146" - cell $and $and$ls180.v:6539$2119 + attribute \src "ls180.v:6539.41-6539.148" + cell $and $and$ls180.v:6539$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6539$2117_Y - connect \B $eq$ls180.v:6539$2118_Y - connect \Y $and$ls180.v:6539$2119_Y + connect \A $and$ls180.v:6539$2110_Y + connect \B $eq$ls180.v:6539$2111_Y + connect \Y $and$ls180.v:6539$2112_Y end - attribute \src "ls180.v:6540.40-6540.98" - cell $and $and$ls180.v:6540$2121 + attribute \src "ls180.v:6540.42-6540.100" + cell $and $and$ls180.v:6540$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6540$2120_Y - connect \Y $and$ls180.v:6540$2121_Y + connect \B $not$ls180.v:6540$2113_Y + connect \Y $and$ls180.v:6540$2114_Y end - attribute \src "ls180.v:6540.39-6540.149" - cell $and $and$ls180.v:6540$2123 + attribute \src "ls180.v:6540.41-6540.151" + cell $and $and$ls180.v:6540$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6540$2121_Y - connect \B $eq$ls180.v:6540$2122_Y - connect \Y $and$ls180.v:6540$2123_Y + connect \A $and$ls180.v:6540$2114_Y + connect \B $eq$ls180.v:6540$2115_Y + connect \Y $and$ls180.v:6540$2116_Y end - attribute \src "ls180.v:6542.39-6542.94" - cell $and $and$ls180.v:6542$2124 + attribute \src "ls180.v:6542.40-6542.95" + cell $and $and$ls180.v:6542$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260360,43 +262845,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6542$2124_Y + connect \Y $and$ls180.v:6542$2117_Y end - attribute \src "ls180.v:6542.38-6542.145" - cell $and $and$ls180.v:6542$2126 + attribute \src "ls180.v:6542.39-6542.146" + cell $and $and$ls180.v:6542$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6542$2124_Y - connect \B $eq$ls180.v:6542$2125_Y - connect \Y $and$ls180.v:6542$2126_Y + connect \A $and$ls180.v:6542$2117_Y + connect \B $eq$ls180.v:6542$2118_Y + connect \Y $and$ls180.v:6542$2119_Y end - attribute \src "ls180.v:6543.39-6543.97" - cell $and $and$ls180.v:6543$2128 + attribute \src "ls180.v:6543.40-6543.98" + cell $and $and$ls180.v:6543$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6543$2127_Y - connect \Y $and$ls180.v:6543$2128_Y + connect \B $not$ls180.v:6543$2120_Y + connect \Y $and$ls180.v:6543$2121_Y end - attribute \src "ls180.v:6543.38-6543.148" - cell $and $and$ls180.v:6543$2130 + attribute \src "ls180.v:6543.39-6543.149" + cell $and $and$ls180.v:6543$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6543$2128_Y - connect \B $eq$ls180.v:6543$2129_Y - connect \Y $and$ls180.v:6543$2130_Y + connect \A $and$ls180.v:6543$2121_Y + connect \B $eq$ls180.v:6543$2122_Y + connect \Y $and$ls180.v:6543$2123_Y end - attribute \src "ls180.v:6545.38-6545.93" - cell $and $and$ls180.v:6545$2131 + attribute \src "ls180.v:6545.39-6545.94" + cell $and $and$ls180.v:6545$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260404,43 +262889,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6545$2131_Y + connect \Y $and$ls180.v:6545$2124_Y end - attribute \src "ls180.v:6545.37-6545.144" - cell $and $and$ls180.v:6545$2133 + attribute \src "ls180.v:6545.38-6545.145" + cell $and $and$ls180.v:6545$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6545$2131_Y - connect \B $eq$ls180.v:6545$2132_Y - connect \Y $and$ls180.v:6545$2133_Y + connect \A $and$ls180.v:6545$2124_Y + connect \B $eq$ls180.v:6545$2125_Y + connect \Y $and$ls180.v:6545$2126_Y end - attribute \src "ls180.v:6546.38-6546.96" - cell $and $and$ls180.v:6546$2135 + attribute \src "ls180.v:6546.39-6546.97" + cell $and $and$ls180.v:6546$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6546$2134_Y - connect \Y $and$ls180.v:6546$2135_Y + connect \B $not$ls180.v:6546$2127_Y + connect \Y $and$ls180.v:6546$2128_Y end - attribute \src "ls180.v:6546.37-6546.147" - cell $and $and$ls180.v:6546$2137 + attribute \src "ls180.v:6546.38-6546.148" + cell $and $and$ls180.v:6546$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6546$2135_Y - connect \B $eq$ls180.v:6546$2136_Y - connect \Y $and$ls180.v:6546$2137_Y + connect \A $and$ls180.v:6546$2128_Y + connect \B $eq$ls180.v:6546$2129_Y + connect \Y $and$ls180.v:6546$2130_Y end - attribute \src "ls180.v:6548.37-6548.92" - cell $and $and$ls180.v:6548$2138 + attribute \src "ls180.v:6548.38-6548.93" + cell $and $and$ls180.v:6548$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260448,43 +262933,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6548$2138_Y + connect \Y $and$ls180.v:6548$2131_Y end - attribute \src "ls180.v:6548.36-6548.143" - cell $and $and$ls180.v:6548$2140 + attribute \src "ls180.v:6548.37-6548.144" + cell $and $and$ls180.v:6548$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6548$2138_Y - connect \B $eq$ls180.v:6548$2139_Y - connect \Y $and$ls180.v:6548$2140_Y + connect \A $and$ls180.v:6548$2131_Y + connect \B $eq$ls180.v:6548$2132_Y + connect \Y $and$ls180.v:6548$2133_Y end - attribute \src "ls180.v:6549.37-6549.95" - cell $and $and$ls180.v:6549$2142 + attribute \src "ls180.v:6549.38-6549.96" + cell $and $and$ls180.v:6549$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6549$2141_Y - connect \Y $and$ls180.v:6549$2142_Y + connect \B $not$ls180.v:6549$2134_Y + connect \Y $and$ls180.v:6549$2135_Y end - attribute \src "ls180.v:6549.36-6549.146" - cell $and $and$ls180.v:6549$2144 + attribute \src "ls180.v:6549.37-6549.147" + cell $and $and$ls180.v:6549$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6549$2142_Y - connect \B $eq$ls180.v:6549$2143_Y - connect \Y $and$ls180.v:6549$2144_Y + connect \A $and$ls180.v:6549$2135_Y + connect \B $eq$ls180.v:6549$2136_Y + connect \Y $and$ls180.v:6549$2137_Y end - attribute \src "ls180.v:6551.43-6551.98" - cell $and $and$ls180.v:6551$2145 + attribute \src "ls180.v:6551.37-6551.92" + cell $and $and$ls180.v:6551$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260492,87 +262977,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6551$2145_Y + connect \Y $and$ls180.v:6551$2138_Y end - attribute \src "ls180.v:6551.42-6551.149" - cell $and $and$ls180.v:6551$2147 + attribute \src "ls180.v:6551.36-6551.143" + cell $and $and$ls180.v:6551$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6551$2145_Y - connect \B $eq$ls180.v:6551$2146_Y - connect \Y $and$ls180.v:6551$2147_Y + connect \A $and$ls180.v:6551$2138_Y + connect \B $eq$ls180.v:6551$2139_Y + connect \Y $and$ls180.v:6551$2140_Y end - attribute \src "ls180.v:6552.43-6552.101" - cell $and $and$ls180.v:6552$2149 + attribute \src "ls180.v:6552.37-6552.95" + cell $and $and$ls180.v:6552$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6552$2148_Y - connect \Y $and$ls180.v:6552$2149_Y + connect \B $not$ls180.v:6552$2141_Y + connect \Y $and$ls180.v:6552$2142_Y end - attribute \src "ls180.v:6552.42-6552.152" - cell $and $and$ls180.v:6552$2151 + attribute \src "ls180.v:6552.36-6552.146" + cell $and $and$ls180.v:6552$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6552$2149_Y - connect \B $eq$ls180.v:6552$2150_Y - connect \Y $and$ls180.v:6552$2151_Y + connect \A $and$ls180.v:6552$2142_Y + connect \B $eq$ls180.v:6552$2143_Y + connect \Y $and$ls180.v:6552$2144_Y end - attribute \src "ls180.v:6573.42-6573.97" - cell $and $and$ls180.v:6573$2154 + attribute \src "ls180.v:6554.43-6554.98" + cell $and $and$ls180.v:6554$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6573$2154_Y + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6554$2145_Y end - attribute \src "ls180.v:6573.41-6573.148" - cell $and $and$ls180.v:6573$2156 + attribute \src "ls180.v:6554.42-6554.149" + cell $and $and$ls180.v:6554$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6573$2154_Y - connect \B $eq$ls180.v:6573$2155_Y - connect \Y $and$ls180.v:6573$2156_Y + connect \A $and$ls180.v:6554$2145_Y + connect \B $eq$ls180.v:6554$2146_Y + connect \Y $and$ls180.v:6554$2147_Y end - attribute \src "ls180.v:6574.42-6574.100" - cell $and $and$ls180.v:6574$2158 + attribute \src "ls180.v:6555.43-6555.101" + cell $and $and$ls180.v:6555$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6574$2157_Y - connect \Y $and$ls180.v:6574$2158_Y + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6555$2148_Y + connect \Y $and$ls180.v:6555$2149_Y end - attribute \src "ls180.v:6574.41-6574.151" - cell $and $and$ls180.v:6574$2160 + attribute \src "ls180.v:6555.42-6555.152" + cell $and $and$ls180.v:6555$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6574$2158_Y - connect \B $eq$ls180.v:6574$2159_Y - connect \Y $and$ls180.v:6574$2160_Y + connect \A $and$ls180.v:6555$2149_Y + connect \B $eq$ls180.v:6555$2150_Y + connect \Y $and$ls180.v:6555$2151_Y end attribute \src "ls180.v:6576.42-6576.97" - cell $and $and$ls180.v:6576$2161 + cell $and $and$ls180.v:6576$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260580,43 +263065,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6576$2161_Y + connect \Y $and$ls180.v:6576$2154_Y end attribute \src "ls180.v:6576.41-6576.148" - cell $and $and$ls180.v:6576$2163 + cell $and $and$ls180.v:6576$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6576$2161_Y - connect \B $eq$ls180.v:6576$2162_Y - connect \Y $and$ls180.v:6576$2163_Y + connect \A $and$ls180.v:6576$2154_Y + connect \B $eq$ls180.v:6576$2155_Y + connect \Y $and$ls180.v:6576$2156_Y end attribute \src "ls180.v:6577.42-6577.100" - cell $and $and$ls180.v:6577$2165 + cell $and $and$ls180.v:6577$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6577$2164_Y - connect \Y $and$ls180.v:6577$2165_Y + connect \B $not$ls180.v:6577$2157_Y + connect \Y $and$ls180.v:6577$2158_Y end attribute \src "ls180.v:6577.41-6577.151" - cell $and $and$ls180.v:6577$2167 + cell $and $and$ls180.v:6577$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6577$2165_Y - connect \B $eq$ls180.v:6577$2166_Y - connect \Y $and$ls180.v:6577$2167_Y + connect \A $and$ls180.v:6577$2158_Y + connect \B $eq$ls180.v:6577$2159_Y + connect \Y $and$ls180.v:6577$2160_Y end - attribute \src "ls180.v:6579.40-6579.95" - cell $and $and$ls180.v:6579$2168 + attribute \src "ls180.v:6579.42-6579.97" + cell $and $and$ls180.v:6579$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260624,43 +263109,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6579$2168_Y + connect \Y $and$ls180.v:6579$2161_Y end - attribute \src "ls180.v:6579.39-6579.146" - cell $and $and$ls180.v:6579$2170 + attribute \src "ls180.v:6579.41-6579.148" + cell $and $and$ls180.v:6579$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6579$2168_Y - connect \B $eq$ls180.v:6579$2169_Y - connect \Y $and$ls180.v:6579$2170_Y + connect \A $and$ls180.v:6579$2161_Y + connect \B $eq$ls180.v:6579$2162_Y + connect \Y $and$ls180.v:6579$2163_Y end - attribute \src "ls180.v:6580.40-6580.98" - cell $and $and$ls180.v:6580$2172 + attribute \src "ls180.v:6580.42-6580.100" + cell $and $and$ls180.v:6580$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6580$2171_Y - connect \Y $and$ls180.v:6580$2172_Y + connect \B $not$ls180.v:6580$2164_Y + connect \Y $and$ls180.v:6580$2165_Y end - attribute \src "ls180.v:6580.39-6580.149" - cell $and $and$ls180.v:6580$2174 + attribute \src "ls180.v:6580.41-6580.151" + cell $and $and$ls180.v:6580$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6580$2172_Y - connect \B $eq$ls180.v:6580$2173_Y - connect \Y $and$ls180.v:6580$2174_Y + connect \A $and$ls180.v:6580$2165_Y + connect \B $eq$ls180.v:6580$2166_Y + connect \Y $and$ls180.v:6580$2167_Y end - attribute \src "ls180.v:6582.39-6582.94" - cell $and $and$ls180.v:6582$2175 + attribute \src "ls180.v:6582.40-6582.95" + cell $and $and$ls180.v:6582$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260668,43 +263153,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6582$2175_Y + connect \Y $and$ls180.v:6582$2168_Y end - attribute \src "ls180.v:6582.38-6582.145" - cell $and $and$ls180.v:6582$2177 + attribute \src "ls180.v:6582.39-6582.146" + cell $and $and$ls180.v:6582$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6582$2175_Y - connect \B $eq$ls180.v:6582$2176_Y - connect \Y $and$ls180.v:6582$2177_Y + connect \A $and$ls180.v:6582$2168_Y + connect \B $eq$ls180.v:6582$2169_Y + connect \Y $and$ls180.v:6582$2170_Y end - attribute \src "ls180.v:6583.39-6583.97" - cell $and $and$ls180.v:6583$2179 + attribute \src "ls180.v:6583.40-6583.98" + cell $and $and$ls180.v:6583$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6583$2178_Y - connect \Y $and$ls180.v:6583$2179_Y + connect \B $not$ls180.v:6583$2171_Y + connect \Y $and$ls180.v:6583$2172_Y end - attribute \src "ls180.v:6583.38-6583.148" - cell $and $and$ls180.v:6583$2181 + attribute \src "ls180.v:6583.39-6583.149" + cell $and $and$ls180.v:6583$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6583$2179_Y - connect \B $eq$ls180.v:6583$2180_Y - connect \Y $and$ls180.v:6583$2181_Y + connect \A $and$ls180.v:6583$2172_Y + connect \B $eq$ls180.v:6583$2173_Y + connect \Y $and$ls180.v:6583$2174_Y end - attribute \src "ls180.v:6585.38-6585.93" - cell $and $and$ls180.v:6585$2182 + attribute \src "ls180.v:6585.39-6585.94" + cell $and $and$ls180.v:6585$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260712,43 +263197,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6585$2182_Y + connect \Y $and$ls180.v:6585$2175_Y end - attribute \src "ls180.v:6585.37-6585.144" - cell $and $and$ls180.v:6585$2184 + attribute \src "ls180.v:6585.38-6585.145" + cell $and $and$ls180.v:6585$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6585$2182_Y - connect \B $eq$ls180.v:6585$2183_Y - connect \Y $and$ls180.v:6585$2184_Y + connect \A $and$ls180.v:6585$2175_Y + connect \B $eq$ls180.v:6585$2176_Y + connect \Y $and$ls180.v:6585$2177_Y end - attribute \src "ls180.v:6586.38-6586.96" - cell $and $and$ls180.v:6586$2186 + attribute \src "ls180.v:6586.39-6586.97" + cell $and $and$ls180.v:6586$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6586$2185_Y - connect \Y $and$ls180.v:6586$2186_Y + connect \B $not$ls180.v:6586$2178_Y + connect \Y $and$ls180.v:6586$2179_Y end - attribute \src "ls180.v:6586.37-6586.147" - cell $and $and$ls180.v:6586$2188 + attribute \src "ls180.v:6586.38-6586.148" + cell $and $and$ls180.v:6586$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6586$2186_Y - connect \B $eq$ls180.v:6586$2187_Y - connect \Y $and$ls180.v:6586$2188_Y + connect \A $and$ls180.v:6586$2179_Y + connect \B $eq$ls180.v:6586$2180_Y + connect \Y $and$ls180.v:6586$2181_Y end - attribute \src "ls180.v:6588.37-6588.92" - cell $and $and$ls180.v:6588$2189 + attribute \src "ls180.v:6588.38-6588.93" + cell $and $and$ls180.v:6588$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260756,43 +263241,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6588$2189_Y + connect \Y $and$ls180.v:6588$2182_Y end - attribute \src "ls180.v:6588.36-6588.143" - cell $and $and$ls180.v:6588$2191 + attribute \src "ls180.v:6588.37-6588.144" + cell $and $and$ls180.v:6588$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6588$2189_Y - connect \B $eq$ls180.v:6588$2190_Y - connect \Y $and$ls180.v:6588$2191_Y + connect \A $and$ls180.v:6588$2182_Y + connect \B $eq$ls180.v:6588$2183_Y + connect \Y $and$ls180.v:6588$2184_Y end - attribute \src "ls180.v:6589.37-6589.95" - cell $and $and$ls180.v:6589$2193 + attribute \src "ls180.v:6589.38-6589.96" + cell $and $and$ls180.v:6589$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6589$2192_Y - connect \Y $and$ls180.v:6589$2193_Y + connect \B $not$ls180.v:6589$2185_Y + connect \Y $and$ls180.v:6589$2186_Y end - attribute \src "ls180.v:6589.36-6589.146" - cell $and $and$ls180.v:6589$2195 + attribute \src "ls180.v:6589.37-6589.147" + cell $and $and$ls180.v:6589$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6589$2193_Y - connect \B $eq$ls180.v:6589$2194_Y - connect \Y $and$ls180.v:6589$2195_Y + connect \A $and$ls180.v:6589$2186_Y + connect \B $eq$ls180.v:6589$2187_Y + connect \Y $and$ls180.v:6589$2188_Y end - attribute \src "ls180.v:6591.43-6591.98" - cell $and $and$ls180.v:6591$2196 + attribute \src "ls180.v:6591.37-6591.92" + cell $and $and$ls180.v:6591$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260800,43 +263285,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6591$2196_Y + connect \Y $and$ls180.v:6591$2189_Y end - attribute \src "ls180.v:6591.42-6591.149" - cell $and $and$ls180.v:6591$2198 + attribute \src "ls180.v:6591.36-6591.143" + cell $and $and$ls180.v:6591$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6591$2196_Y - connect \B $eq$ls180.v:6591$2197_Y - connect \Y $and$ls180.v:6591$2198_Y + connect \A $and$ls180.v:6591$2189_Y + connect \B $eq$ls180.v:6591$2190_Y + connect \Y $and$ls180.v:6591$2191_Y end - attribute \src "ls180.v:6592.43-6592.101" - cell $and $and$ls180.v:6592$2200 + attribute \src "ls180.v:6592.37-6592.95" + cell $and $and$ls180.v:6592$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6592$2199_Y - connect \Y $and$ls180.v:6592$2200_Y + connect \B $not$ls180.v:6592$2192_Y + connect \Y $and$ls180.v:6592$2193_Y end - attribute \src "ls180.v:6592.42-6592.152" - cell $and $and$ls180.v:6592$2202 + attribute \src "ls180.v:6592.36-6592.146" + cell $and $and$ls180.v:6592$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6592$2200_Y - connect \B $eq$ls180.v:6592$2201_Y - connect \Y $and$ls180.v:6592$2202_Y + connect \A $and$ls180.v:6592$2193_Y + connect \B $eq$ls180.v:6592$2194_Y + connect \Y $and$ls180.v:6592$2195_Y end - attribute \src "ls180.v:6594.46-6594.101" - cell $and $and$ls180.v:6594$2203 + attribute \src "ls180.v:6594.43-6594.98" + cell $and $and$ls180.v:6594$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260844,43 +263329,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6594$2203_Y + connect \Y $and$ls180.v:6594$2196_Y end - attribute \src "ls180.v:6594.45-6594.152" - cell $and $and$ls180.v:6594$2205 + attribute \src "ls180.v:6594.42-6594.149" + cell $and $and$ls180.v:6594$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6594$2203_Y - connect \B $eq$ls180.v:6594$2204_Y - connect \Y $and$ls180.v:6594$2205_Y + connect \A $and$ls180.v:6594$2196_Y + connect \B $eq$ls180.v:6594$2197_Y + connect \Y $and$ls180.v:6594$2198_Y end - attribute \src "ls180.v:6595.46-6595.104" - cell $and $and$ls180.v:6595$2207 + attribute \src "ls180.v:6595.43-6595.101" + cell $and $and$ls180.v:6595$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6595$2206_Y - connect \Y $and$ls180.v:6595$2207_Y + connect \B $not$ls180.v:6595$2199_Y + connect \Y $and$ls180.v:6595$2200_Y end - attribute \src "ls180.v:6595.45-6595.155" - cell $and $and$ls180.v:6595$2209 + attribute \src "ls180.v:6595.42-6595.152" + cell $and $and$ls180.v:6595$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6595$2207_Y - connect \B $eq$ls180.v:6595$2208_Y - connect \Y $and$ls180.v:6595$2209_Y + connect \A $and$ls180.v:6595$2200_Y + connect \B $eq$ls180.v:6595$2201_Y + connect \Y $and$ls180.v:6595$2202_Y end attribute \src "ls180.v:6597.46-6597.101" - cell $and $and$ls180.v:6597$2210 + cell $and $and$ls180.v:6597$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260888,87 +263373,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6597$2210_Y + connect \Y $and$ls180.v:6597$2203_Y end attribute \src "ls180.v:6597.45-6597.152" - cell $and $and$ls180.v:6597$2212 + cell $and $and$ls180.v:6597$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6597$2210_Y - connect \B $eq$ls180.v:6597$2211_Y - connect \Y $and$ls180.v:6597$2212_Y + connect \A $and$ls180.v:6597$2203_Y + connect \B $eq$ls180.v:6597$2204_Y + connect \Y $and$ls180.v:6597$2205_Y end attribute \src "ls180.v:6598.46-6598.104" - cell $and $and$ls180.v:6598$2214 + cell $and $and$ls180.v:6598$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6598$2213_Y - connect \Y $and$ls180.v:6598$2214_Y + connect \B $not$ls180.v:6598$2206_Y + connect \Y $and$ls180.v:6598$2207_Y end attribute \src "ls180.v:6598.45-6598.155" - cell $and $and$ls180.v:6598$2216 + cell $and $and$ls180.v:6598$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6598$2214_Y - connect \B $eq$ls180.v:6598$2215_Y - connect \Y $and$ls180.v:6598$2216_Y + connect \A $and$ls180.v:6598$2207_Y + connect \B $eq$ls180.v:6598$2208_Y + connect \Y $and$ls180.v:6598$2209_Y end - attribute \src "ls180.v:6621.39-6621.94" - cell $and $and$ls180.v:6621$2219 + attribute \src "ls180.v:6600.46-6600.101" + cell $and $and$ls180.v:6600$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6621$2219_Y + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6600$2210_Y end - attribute \src "ls180.v:6621.38-6621.145" - cell $and $and$ls180.v:6621$2221 + attribute \src "ls180.v:6600.45-6600.152" + cell $and $and$ls180.v:6600$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6621$2219_Y - connect \B $eq$ls180.v:6621$2220_Y - connect \Y $and$ls180.v:6621$2221_Y + connect \A $and$ls180.v:6600$2210_Y + connect \B $eq$ls180.v:6600$2211_Y + connect \Y $and$ls180.v:6600$2212_Y end - attribute \src "ls180.v:6622.39-6622.97" - cell $and $and$ls180.v:6622$2223 + attribute \src "ls180.v:6601.46-6601.104" + cell $and $and$ls180.v:6601$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6622$2222_Y - connect \Y $and$ls180.v:6622$2223_Y + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6601$2213_Y + connect \Y $and$ls180.v:6601$2214_Y end - attribute \src "ls180.v:6622.38-6622.148" - cell $and $and$ls180.v:6622$2225 + attribute \src "ls180.v:6601.45-6601.155" + cell $and $and$ls180.v:6601$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6622$2223_Y - connect \B $eq$ls180.v:6622$2224_Y - connect \Y $and$ls180.v:6622$2225_Y + connect \A $and$ls180.v:6601$2214_Y + connect \B $eq$ls180.v:6601$2215_Y + connect \Y $and$ls180.v:6601$2216_Y end attribute \src "ls180.v:6624.39-6624.94" - cell $and $and$ls180.v:6624$2226 + cell $and $and$ls180.v:6624$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260976,43 +263461,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6624$2226_Y + connect \Y $and$ls180.v:6624$2219_Y end attribute \src "ls180.v:6624.38-6624.145" - cell $and $and$ls180.v:6624$2228 + cell $and $and$ls180.v:6624$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6624$2226_Y - connect \B $eq$ls180.v:6624$2227_Y - connect \Y $and$ls180.v:6624$2228_Y + connect \A $and$ls180.v:6624$2219_Y + connect \B $eq$ls180.v:6624$2220_Y + connect \Y $and$ls180.v:6624$2221_Y end attribute \src "ls180.v:6625.39-6625.97" - cell $and $and$ls180.v:6625$2230 + cell $and $and$ls180.v:6625$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6625$2229_Y - connect \Y $and$ls180.v:6625$2230_Y + connect \B $not$ls180.v:6625$2222_Y + connect \Y $and$ls180.v:6625$2223_Y end attribute \src "ls180.v:6625.38-6625.148" - cell $and $and$ls180.v:6625$2232 + cell $and $and$ls180.v:6625$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6625$2230_Y - connect \B $eq$ls180.v:6625$2231_Y - connect \Y $and$ls180.v:6625$2232_Y + connect \A $and$ls180.v:6625$2223_Y + connect \B $eq$ls180.v:6625$2224_Y + connect \Y $and$ls180.v:6625$2225_Y end attribute \src "ls180.v:6627.39-6627.94" - cell $and $and$ls180.v:6627$2233 + cell $and $and$ls180.v:6627$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261020,43 +263505,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6627$2233_Y + connect \Y $and$ls180.v:6627$2226_Y end attribute \src "ls180.v:6627.38-6627.145" - cell $and $and$ls180.v:6627$2235 + cell $and $and$ls180.v:6627$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6627$2233_Y - connect \B $eq$ls180.v:6627$2234_Y - connect \Y $and$ls180.v:6627$2235_Y + connect \A $and$ls180.v:6627$2226_Y + connect \B $eq$ls180.v:6627$2227_Y + connect \Y $and$ls180.v:6627$2228_Y end attribute \src "ls180.v:6628.39-6628.97" - cell $and $and$ls180.v:6628$2237 + cell $and $and$ls180.v:6628$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6628$2236_Y - connect \Y $and$ls180.v:6628$2237_Y + connect \B $not$ls180.v:6628$2229_Y + connect \Y $and$ls180.v:6628$2230_Y end attribute \src "ls180.v:6628.38-6628.148" - cell $and $and$ls180.v:6628$2239 + cell $and $and$ls180.v:6628$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6628$2237_Y - connect \B $eq$ls180.v:6628$2238_Y - connect \Y $and$ls180.v:6628$2239_Y + connect \A $and$ls180.v:6628$2230_Y + connect \B $eq$ls180.v:6628$2231_Y + connect \Y $and$ls180.v:6628$2232_Y end attribute \src "ls180.v:6630.39-6630.94" - cell $and $and$ls180.v:6630$2240 + cell $and $and$ls180.v:6630$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261064,43 +263549,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6630$2240_Y + connect \Y $and$ls180.v:6630$2233_Y end attribute \src "ls180.v:6630.38-6630.145" - cell $and $and$ls180.v:6630$2242 + cell $and $and$ls180.v:6630$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6630$2240_Y - connect \B $eq$ls180.v:6630$2241_Y - connect \Y $and$ls180.v:6630$2242_Y + connect \A $and$ls180.v:6630$2233_Y + connect \B $eq$ls180.v:6630$2234_Y + connect \Y $and$ls180.v:6630$2235_Y end attribute \src "ls180.v:6631.39-6631.97" - cell $and $and$ls180.v:6631$2244 + cell $and $and$ls180.v:6631$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6631$2243_Y - connect \Y $and$ls180.v:6631$2244_Y + connect \B $not$ls180.v:6631$2236_Y + connect \Y $and$ls180.v:6631$2237_Y end attribute \src "ls180.v:6631.38-6631.148" - cell $and $and$ls180.v:6631$2246 + cell $and $and$ls180.v:6631$2239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6631$2244_Y - connect \B $eq$ls180.v:6631$2245_Y - connect \Y $and$ls180.v:6631$2246_Y + connect \A $and$ls180.v:6631$2237_Y + connect \B $eq$ls180.v:6631$2238_Y + connect \Y $and$ls180.v:6631$2239_Y end - attribute \src "ls180.v:6633.41-6633.96" - cell $and $and$ls180.v:6633$2247 + attribute \src "ls180.v:6633.39-6633.94" + cell $and $and$ls180.v:6633$2240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261108,43 +263593,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6633$2247_Y + connect \Y $and$ls180.v:6633$2240_Y end - attribute \src "ls180.v:6633.40-6633.147" - cell $and $and$ls180.v:6633$2249 + attribute \src "ls180.v:6633.38-6633.145" + cell $and $and$ls180.v:6633$2242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6633$2247_Y - connect \B $eq$ls180.v:6633$2248_Y - connect \Y $and$ls180.v:6633$2249_Y + connect \A $and$ls180.v:6633$2240_Y + connect \B $eq$ls180.v:6633$2241_Y + connect \Y $and$ls180.v:6633$2242_Y end - attribute \src "ls180.v:6634.41-6634.99" - cell $and $and$ls180.v:6634$2251 + attribute \src "ls180.v:6634.39-6634.97" + cell $and $and$ls180.v:6634$2244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6634$2250_Y - connect \Y $and$ls180.v:6634$2251_Y + connect \B $not$ls180.v:6634$2243_Y + connect \Y $and$ls180.v:6634$2244_Y end - attribute \src "ls180.v:6634.40-6634.150" - cell $and $and$ls180.v:6634$2253 + attribute \src "ls180.v:6634.38-6634.148" + cell $and $and$ls180.v:6634$2246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6634$2251_Y - connect \B $eq$ls180.v:6634$2252_Y - connect \Y $and$ls180.v:6634$2253_Y + connect \A $and$ls180.v:6634$2244_Y + connect \B $eq$ls180.v:6634$2245_Y + connect \Y $and$ls180.v:6634$2246_Y end attribute \src "ls180.v:6636.41-6636.96" - cell $and $and$ls180.v:6636$2254 + cell $and $and$ls180.v:6636$2247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261152,43 +263637,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6636$2254_Y + connect \Y $and$ls180.v:6636$2247_Y end attribute \src "ls180.v:6636.40-6636.147" - cell $and $and$ls180.v:6636$2256 + cell $and $and$ls180.v:6636$2249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6636$2254_Y - connect \B $eq$ls180.v:6636$2255_Y - connect \Y $and$ls180.v:6636$2256_Y + connect \A $and$ls180.v:6636$2247_Y + connect \B $eq$ls180.v:6636$2248_Y + connect \Y $and$ls180.v:6636$2249_Y end attribute \src "ls180.v:6637.41-6637.99" - cell $and $and$ls180.v:6637$2258 + cell $and $and$ls180.v:6637$2251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6637$2257_Y - connect \Y $and$ls180.v:6637$2258_Y + connect \B $not$ls180.v:6637$2250_Y + connect \Y $and$ls180.v:6637$2251_Y end attribute \src "ls180.v:6637.40-6637.150" - cell $and $and$ls180.v:6637$2260 + cell $and $and$ls180.v:6637$2253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6637$2258_Y - connect \B $eq$ls180.v:6637$2259_Y - connect \Y $and$ls180.v:6637$2260_Y + connect \A $and$ls180.v:6637$2251_Y + connect \B $eq$ls180.v:6637$2252_Y + connect \Y $and$ls180.v:6637$2253_Y end attribute \src "ls180.v:6639.41-6639.96" - cell $and $and$ls180.v:6639$2261 + cell $and $and$ls180.v:6639$2254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261196,43 +263681,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6639$2261_Y + connect \Y $and$ls180.v:6639$2254_Y end attribute \src "ls180.v:6639.40-6639.147" - cell $and $and$ls180.v:6639$2263 + cell $and $and$ls180.v:6639$2256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6639$2261_Y - connect \B $eq$ls180.v:6639$2262_Y - connect \Y $and$ls180.v:6639$2263_Y + connect \A $and$ls180.v:6639$2254_Y + connect \B $eq$ls180.v:6639$2255_Y + connect \Y $and$ls180.v:6639$2256_Y end attribute \src "ls180.v:6640.41-6640.99" - cell $and $and$ls180.v:6640$2265 + cell $and $and$ls180.v:6640$2258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6640$2264_Y - connect \Y $and$ls180.v:6640$2265_Y + connect \B $not$ls180.v:6640$2257_Y + connect \Y $and$ls180.v:6640$2258_Y end attribute \src "ls180.v:6640.40-6640.150" - cell $and $and$ls180.v:6640$2267 + cell $and $and$ls180.v:6640$2260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6640$2265_Y - connect \B $eq$ls180.v:6640$2266_Y - connect \Y $and$ls180.v:6640$2267_Y + connect \A $and$ls180.v:6640$2258_Y + connect \B $eq$ls180.v:6640$2259_Y + connect \Y $and$ls180.v:6640$2260_Y end attribute \src "ls180.v:6642.41-6642.96" - cell $and $and$ls180.v:6642$2268 + cell $and $and$ls180.v:6642$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261240,43 +263725,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6642$2268_Y + connect \Y $and$ls180.v:6642$2261_Y end attribute \src "ls180.v:6642.40-6642.147" - cell $and $and$ls180.v:6642$2270 + cell $and $and$ls180.v:6642$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6642$2268_Y - connect \B $eq$ls180.v:6642$2269_Y - connect \Y $and$ls180.v:6642$2270_Y + connect \A $and$ls180.v:6642$2261_Y + connect \B $eq$ls180.v:6642$2262_Y + connect \Y $and$ls180.v:6642$2263_Y end attribute \src "ls180.v:6643.41-6643.99" - cell $and $and$ls180.v:6643$2272 + cell $and $and$ls180.v:6643$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6643$2271_Y - connect \Y $and$ls180.v:6643$2272_Y + connect \B $not$ls180.v:6643$2264_Y + connect \Y $and$ls180.v:6643$2265_Y end attribute \src "ls180.v:6643.40-6643.150" - cell $and $and$ls180.v:6643$2274 + cell $and $and$ls180.v:6643$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6643$2272_Y - connect \B $eq$ls180.v:6643$2273_Y - connect \Y $and$ls180.v:6643$2274_Y + connect \A $and$ls180.v:6643$2265_Y + connect \B $eq$ls180.v:6643$2266_Y + connect \Y $and$ls180.v:6643$2267_Y end - attribute \src "ls180.v:6645.37-6645.92" - cell $and $and$ls180.v:6645$2275 + attribute \src "ls180.v:6645.41-6645.96" + cell $and $and$ls180.v:6645$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261284,43 +263769,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6645$2275_Y + connect \Y $and$ls180.v:6645$2268_Y end - attribute \src "ls180.v:6645.36-6645.143" - cell $and $and$ls180.v:6645$2277 + attribute \src "ls180.v:6645.40-6645.147" + cell $and $and$ls180.v:6645$2270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6645$2275_Y - connect \B $eq$ls180.v:6645$2276_Y - connect \Y $and$ls180.v:6645$2277_Y + connect \A $and$ls180.v:6645$2268_Y + connect \B $eq$ls180.v:6645$2269_Y + connect \Y $and$ls180.v:6645$2270_Y end - attribute \src "ls180.v:6646.37-6646.95" - cell $and $and$ls180.v:6646$2279 + attribute \src "ls180.v:6646.41-6646.99" + cell $and $and$ls180.v:6646$2272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6646$2278_Y - connect \Y $and$ls180.v:6646$2279_Y + connect \B $not$ls180.v:6646$2271_Y + connect \Y $and$ls180.v:6646$2272_Y end - attribute \src "ls180.v:6646.36-6646.146" - cell $and $and$ls180.v:6646$2281 + attribute \src "ls180.v:6646.40-6646.150" + cell $and $and$ls180.v:6646$2274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6646$2279_Y - connect \B $eq$ls180.v:6646$2280_Y - connect \Y $and$ls180.v:6646$2281_Y + connect \A $and$ls180.v:6646$2272_Y + connect \B $eq$ls180.v:6646$2273_Y + connect \Y $and$ls180.v:6646$2274_Y end - attribute \src "ls180.v:6648.47-6648.102" - cell $and $and$ls180.v:6648$2282 + attribute \src "ls180.v:6648.37-6648.92" + cell $and $and$ls180.v:6648$2275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261328,43 +263813,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6648$2282_Y + connect \Y $and$ls180.v:6648$2275_Y end - attribute \src "ls180.v:6648.46-6648.153" - cell $and $and$ls180.v:6648$2284 + attribute \src "ls180.v:6648.36-6648.143" + cell $and $and$ls180.v:6648$2277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6648$2282_Y - connect \B $eq$ls180.v:6648$2283_Y - connect \Y $and$ls180.v:6648$2284_Y + connect \A $and$ls180.v:6648$2275_Y + connect \B $eq$ls180.v:6648$2276_Y + connect \Y $and$ls180.v:6648$2277_Y end - attribute \src "ls180.v:6649.47-6649.105" - cell $and $and$ls180.v:6649$2286 + attribute \src "ls180.v:6649.37-6649.95" + cell $and $and$ls180.v:6649$2279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6649$2285_Y - connect \Y $and$ls180.v:6649$2286_Y + connect \B $not$ls180.v:6649$2278_Y + connect \Y $and$ls180.v:6649$2279_Y end - attribute \src "ls180.v:6649.46-6649.156" - cell $and $and$ls180.v:6649$2288 + attribute \src "ls180.v:6649.36-6649.146" + cell $and $and$ls180.v:6649$2281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6649$2286_Y - connect \B $eq$ls180.v:6649$2287_Y - connect \Y $and$ls180.v:6649$2288_Y + connect \A $and$ls180.v:6649$2279_Y + connect \B $eq$ls180.v:6649$2280_Y + connect \Y $and$ls180.v:6649$2281_Y end - attribute \src "ls180.v:6651.40-6651.95" - cell $and $and$ls180.v:6651$2289 + attribute \src "ls180.v:6651.47-6651.102" + cell $and $and$ls180.v:6651$2282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261372,43 +263857,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6651$2289_Y + connect \Y $and$ls180.v:6651$2282_Y end - attribute \src "ls180.v:6651.39-6651.147" - cell $and $and$ls180.v:6651$2291 + attribute \src "ls180.v:6651.46-6651.153" + cell $and $and$ls180.v:6651$2284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6651$2289_Y - connect \B $eq$ls180.v:6651$2290_Y - connect \Y $and$ls180.v:6651$2291_Y + connect \A $and$ls180.v:6651$2282_Y + connect \B $eq$ls180.v:6651$2283_Y + connect \Y $and$ls180.v:6651$2284_Y end - attribute \src "ls180.v:6652.40-6652.98" - cell $and $and$ls180.v:6652$2293 + attribute \src "ls180.v:6652.47-6652.105" + cell $and $and$ls180.v:6652$2286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6652$2292_Y - connect \Y $and$ls180.v:6652$2293_Y + connect \B $not$ls180.v:6652$2285_Y + connect \Y $and$ls180.v:6652$2286_Y end - attribute \src "ls180.v:6652.39-6652.150" - cell $and $and$ls180.v:6652$2295 + attribute \src "ls180.v:6652.46-6652.156" + cell $and $and$ls180.v:6652$2288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6652$2293_Y - connect \B $eq$ls180.v:6652$2294_Y - connect \Y $and$ls180.v:6652$2295_Y + connect \A $and$ls180.v:6652$2286_Y + connect \B $eq$ls180.v:6652$2287_Y + connect \Y $and$ls180.v:6652$2288_Y end attribute \src "ls180.v:6654.40-6654.95" - cell $and $and$ls180.v:6654$2296 + cell $and $and$ls180.v:6654$2289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261416,43 +263901,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6654$2296_Y + connect \Y $and$ls180.v:6654$2289_Y end attribute \src "ls180.v:6654.39-6654.147" - cell $and $and$ls180.v:6654$2298 + cell $and $and$ls180.v:6654$2291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6654$2296_Y - connect \B $eq$ls180.v:6654$2297_Y - connect \Y $and$ls180.v:6654$2298_Y + connect \A $and$ls180.v:6654$2289_Y + connect \B $eq$ls180.v:6654$2290_Y + connect \Y $and$ls180.v:6654$2291_Y end attribute \src "ls180.v:6655.40-6655.98" - cell $and $and$ls180.v:6655$2300 + cell $and $and$ls180.v:6655$2293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6655$2299_Y - connect \Y $and$ls180.v:6655$2300_Y + connect \B $not$ls180.v:6655$2292_Y + connect \Y $and$ls180.v:6655$2293_Y end attribute \src "ls180.v:6655.39-6655.150" - cell $and $and$ls180.v:6655$2302 + cell $and $and$ls180.v:6655$2295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6655$2300_Y - connect \B $eq$ls180.v:6655$2301_Y - connect \Y $and$ls180.v:6655$2302_Y + connect \A $and$ls180.v:6655$2293_Y + connect \B $eq$ls180.v:6655$2294_Y + connect \Y $and$ls180.v:6655$2295_Y end attribute \src "ls180.v:6657.40-6657.95" - cell $and $and$ls180.v:6657$2303 + cell $and $and$ls180.v:6657$2296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261460,43 +263945,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6657$2303_Y + connect \Y $and$ls180.v:6657$2296_Y end attribute \src "ls180.v:6657.39-6657.147" - cell $and $and$ls180.v:6657$2305 + cell $and $and$ls180.v:6657$2298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6657$2303_Y - connect \B $eq$ls180.v:6657$2304_Y - connect \Y $and$ls180.v:6657$2305_Y + connect \A $and$ls180.v:6657$2296_Y + connect \B $eq$ls180.v:6657$2297_Y + connect \Y $and$ls180.v:6657$2298_Y end attribute \src "ls180.v:6658.40-6658.98" - cell $and $and$ls180.v:6658$2307 + cell $and $and$ls180.v:6658$2300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6658$2306_Y - connect \Y $and$ls180.v:6658$2307_Y + connect \B $not$ls180.v:6658$2299_Y + connect \Y $and$ls180.v:6658$2300_Y end attribute \src "ls180.v:6658.39-6658.150" - cell $and $and$ls180.v:6658$2309 + cell $and $and$ls180.v:6658$2302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6658$2307_Y - connect \B $eq$ls180.v:6658$2308_Y - connect \Y $and$ls180.v:6658$2309_Y + connect \A $and$ls180.v:6658$2300_Y + connect \B $eq$ls180.v:6658$2301_Y + connect \Y $and$ls180.v:6658$2302_Y end attribute \src "ls180.v:6660.40-6660.95" - cell $and $and$ls180.v:6660$2310 + cell $and $and$ls180.v:6660$2303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261504,43 +263989,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6660$2310_Y + connect \Y $and$ls180.v:6660$2303_Y end attribute \src "ls180.v:6660.39-6660.147" - cell $and $and$ls180.v:6660$2312 + cell $and $and$ls180.v:6660$2305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6660$2310_Y - connect \B $eq$ls180.v:6660$2311_Y - connect \Y $and$ls180.v:6660$2312_Y + connect \A $and$ls180.v:6660$2303_Y + connect \B $eq$ls180.v:6660$2304_Y + connect \Y $and$ls180.v:6660$2305_Y end attribute \src "ls180.v:6661.40-6661.98" - cell $and $and$ls180.v:6661$2314 + cell $and $and$ls180.v:6661$2307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6661$2313_Y - connect \Y $and$ls180.v:6661$2314_Y + connect \B $not$ls180.v:6661$2306_Y + connect \Y $and$ls180.v:6661$2307_Y end attribute \src "ls180.v:6661.39-6661.150" - cell $and $and$ls180.v:6661$2316 + cell $and $and$ls180.v:6661$2309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6661$2307_Y + connect \B $eq$ls180.v:6661$2308_Y + connect \Y $and$ls180.v:6661$2309_Y + end + attribute \src "ls180.v:6663.40-6663.95" + cell $and $and$ls180.v:6663$2310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6663$2310_Y + end + attribute \src "ls180.v:6663.39-6663.147" + cell $and $and$ls180.v:6663$2312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6663$2310_Y + connect \B $eq$ls180.v:6663$2311_Y + connect \Y $and$ls180.v:6663$2312_Y + end + attribute \src "ls180.v:6664.40-6664.98" + cell $and $and$ls180.v:6664$2314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6664$2313_Y + connect \Y $and$ls180.v:6664$2314_Y + end + attribute \src "ls180.v:6664.39-6664.150" + cell $and $and$ls180.v:6664$2316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6661$2314_Y - connect \B $eq$ls180.v:6661$2315_Y - connect \Y $and$ls180.v:6661$2316_Y + connect \A $and$ls180.v:6664$2314_Y + connect \B $eq$ls180.v:6664$2315_Y + connect \Y $and$ls180.v:6664$2316_Y end - attribute \src "ls180.v:6663.52-6663.107" - cell $and $and$ls180.v:6663$2317 + attribute \src "ls180.v:6666.52-6666.107" + cell $and $and$ls180.v:6666$2317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261548,43 +264077,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6663$2317_Y + connect \Y $and$ls180.v:6666$2317_Y end - attribute \src "ls180.v:6663.51-6663.159" - cell $and $and$ls180.v:6663$2319 + attribute \src "ls180.v:6666.51-6666.159" + cell $and $and$ls180.v:6666$2319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6663$2317_Y - connect \B $eq$ls180.v:6663$2318_Y - connect \Y $and$ls180.v:6663$2319_Y + connect \A $and$ls180.v:6666$2317_Y + connect \B $eq$ls180.v:6666$2318_Y + connect \Y $and$ls180.v:6666$2319_Y end - attribute \src "ls180.v:6664.52-6664.110" - cell $and $and$ls180.v:6664$2321 + attribute \src "ls180.v:6667.52-6667.110" + cell $and $and$ls180.v:6667$2321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6664$2320_Y - connect \Y $and$ls180.v:6664$2321_Y + connect \B $not$ls180.v:6667$2320_Y + connect \Y $and$ls180.v:6667$2321_Y end - attribute \src "ls180.v:6664.51-6664.162" - cell $and $and$ls180.v:6664$2323 + attribute \src "ls180.v:6667.51-6667.162" + cell $and $and$ls180.v:6667$2323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6664$2321_Y - connect \B $eq$ls180.v:6664$2322_Y - connect \Y $and$ls180.v:6664$2323_Y + connect \A $and$ls180.v:6667$2321_Y + connect \B $eq$ls180.v:6667$2322_Y + connect \Y $and$ls180.v:6667$2323_Y end - attribute \src "ls180.v:6666.53-6666.108" - cell $and $and$ls180.v:6666$2324 + attribute \src "ls180.v:6669.53-6669.108" + cell $and $and$ls180.v:6669$2324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261592,43 +264121,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6666$2324_Y + connect \Y $and$ls180.v:6669$2324_Y end - attribute \src "ls180.v:6666.52-6666.160" - cell $and $and$ls180.v:6666$2326 + attribute \src "ls180.v:6669.52-6669.160" + cell $and $and$ls180.v:6669$2326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6666$2324_Y - connect \B $eq$ls180.v:6666$2325_Y - connect \Y $and$ls180.v:6666$2326_Y + connect \A $and$ls180.v:6669$2324_Y + connect \B $eq$ls180.v:6669$2325_Y + connect \Y $and$ls180.v:6669$2326_Y end - attribute \src "ls180.v:6667.53-6667.111" - cell $and $and$ls180.v:6667$2328 + attribute \src "ls180.v:6670.53-6670.111" + cell $and $and$ls180.v:6670$2328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6667$2327_Y - connect \Y $and$ls180.v:6667$2328_Y + connect \B $not$ls180.v:6670$2327_Y + connect \Y $and$ls180.v:6670$2328_Y end - attribute \src "ls180.v:6667.52-6667.163" - cell $and $and$ls180.v:6667$2330 + attribute \src "ls180.v:6670.52-6670.163" + cell $and $and$ls180.v:6670$2330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6667$2328_Y - connect \B $eq$ls180.v:6667$2329_Y - connect \Y $and$ls180.v:6667$2330_Y + connect \A $and$ls180.v:6670$2328_Y + connect \B $eq$ls180.v:6670$2329_Y + connect \Y $and$ls180.v:6670$2330_Y end - attribute \src "ls180.v:6669.44-6669.99" - cell $and $and$ls180.v:6669$2331 + attribute \src "ls180.v:6672.44-6672.99" + cell $and $and$ls180.v:6672$2331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261636,43 +264165,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6669$2331_Y + connect \Y $and$ls180.v:6672$2331_Y end - attribute \src "ls180.v:6669.43-6669.151" - cell $and $and$ls180.v:6669$2333 + attribute \src "ls180.v:6672.43-6672.151" + cell $and $and$ls180.v:6672$2333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6669$2331_Y - connect \B $eq$ls180.v:6669$2332_Y - connect \Y $and$ls180.v:6669$2333_Y + connect \A $and$ls180.v:6672$2331_Y + connect \B $eq$ls180.v:6672$2332_Y + connect \Y $and$ls180.v:6672$2333_Y end - attribute \src "ls180.v:6670.44-6670.102" - cell $and $and$ls180.v:6670$2335 + attribute \src "ls180.v:6673.44-6673.102" + cell $and $and$ls180.v:6673$2335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6670$2334_Y - connect \Y $and$ls180.v:6670$2335_Y + connect \B $not$ls180.v:6673$2334_Y + connect \Y $and$ls180.v:6673$2335_Y end - attribute \src "ls180.v:6670.43-6670.154" - cell $and $and$ls180.v:6670$2337 + attribute \src "ls180.v:6673.43-6673.154" + cell $and $and$ls180.v:6673$2337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6670$2335_Y - connect \B $eq$ls180.v:6670$2336_Y - connect \Y $and$ls180.v:6670$2337_Y + connect \A $and$ls180.v:6673$2335_Y + connect \B $eq$ls180.v:6673$2336_Y + connect \Y $and$ls180.v:6673$2337_Y end - attribute \src "ls180.v:6689.30-6689.85" - cell $and $and$ls180.v:6689$2339 + attribute \src "ls180.v:6692.30-6692.85" + cell $and $and$ls180.v:6692$2339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261680,43 +264209,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6689$2339_Y + connect \Y $and$ls180.v:6692$2339_Y end - attribute \src "ls180.v:6689.29-6689.136" - cell $and $and$ls180.v:6689$2341 + attribute \src "ls180.v:6692.29-6692.136" + cell $and $and$ls180.v:6692$2341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6689$2339_Y - connect \B $eq$ls180.v:6689$2340_Y - connect \Y $and$ls180.v:6689$2341_Y + connect \A $and$ls180.v:6692$2339_Y + connect \B $eq$ls180.v:6692$2340_Y + connect \Y $and$ls180.v:6692$2341_Y end - attribute \src "ls180.v:6690.30-6690.88" - cell $and $and$ls180.v:6690$2343 + attribute \src "ls180.v:6693.30-6693.88" + cell $and $and$ls180.v:6693$2343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6690$2342_Y - connect \Y $and$ls180.v:6690$2343_Y + connect \B $not$ls180.v:6693$2342_Y + connect \Y $and$ls180.v:6693$2343_Y end - attribute \src "ls180.v:6690.29-6690.139" - cell $and $and$ls180.v:6690$2345 + attribute \src "ls180.v:6693.29-6693.139" + cell $and $and$ls180.v:6693$2345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6690$2343_Y - connect \B $eq$ls180.v:6690$2344_Y - connect \Y $and$ls180.v:6690$2345_Y + connect \A $and$ls180.v:6693$2343_Y + connect \B $eq$ls180.v:6693$2344_Y + connect \Y $and$ls180.v:6693$2345_Y end - attribute \src "ls180.v:6692.40-6692.95" - cell $and $and$ls180.v:6692$2346 + attribute \src "ls180.v:6695.40-6695.95" + cell $and $and$ls180.v:6695$2346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261724,43 +264253,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6692$2346_Y + connect \Y $and$ls180.v:6695$2346_Y end - attribute \src "ls180.v:6692.39-6692.146" - cell $and $and$ls180.v:6692$2348 + attribute \src "ls180.v:6695.39-6695.146" + cell $and $and$ls180.v:6695$2348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6692$2346_Y - connect \B $eq$ls180.v:6692$2347_Y - connect \Y $and$ls180.v:6692$2348_Y + connect \A $and$ls180.v:6695$2346_Y + connect \B $eq$ls180.v:6695$2347_Y + connect \Y $and$ls180.v:6695$2348_Y end - attribute \src "ls180.v:6693.40-6693.98" - cell $and $and$ls180.v:6693$2350 + attribute \src "ls180.v:6696.40-6696.98" + cell $and $and$ls180.v:6696$2350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6693$2349_Y - connect \Y $and$ls180.v:6693$2350_Y + connect \B $not$ls180.v:6696$2349_Y + connect \Y $and$ls180.v:6696$2350_Y end - attribute \src "ls180.v:6693.39-6693.149" - cell $and $and$ls180.v:6693$2352 + attribute \src "ls180.v:6696.39-6696.149" + cell $and $and$ls180.v:6696$2352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6693$2350_Y - connect \B $eq$ls180.v:6693$2351_Y - connect \Y $and$ls180.v:6693$2352_Y + connect \A $and$ls180.v:6696$2350_Y + connect \B $eq$ls180.v:6696$2351_Y + connect \Y $and$ls180.v:6696$2352_Y end - attribute \src "ls180.v:6695.41-6695.96" - cell $and $and$ls180.v:6695$2353 + attribute \src "ls180.v:6698.41-6698.96" + cell $and $and$ls180.v:6698$2353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261768,43 +264297,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6695$2353_Y + connect \Y $and$ls180.v:6698$2353_Y end - attribute \src "ls180.v:6695.40-6695.147" - cell $and $and$ls180.v:6695$2355 + attribute \src "ls180.v:6698.40-6698.147" + cell $and $and$ls180.v:6698$2355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6695$2353_Y - connect \B $eq$ls180.v:6695$2354_Y - connect \Y $and$ls180.v:6695$2355_Y + connect \A $and$ls180.v:6698$2353_Y + connect \B $eq$ls180.v:6698$2354_Y + connect \Y $and$ls180.v:6698$2355_Y end - attribute \src "ls180.v:6696.41-6696.99" - cell $and $and$ls180.v:6696$2357 + attribute \src "ls180.v:6699.41-6699.99" + cell $and $and$ls180.v:6699$2357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6696$2356_Y - connect \Y $and$ls180.v:6696$2357_Y + connect \B $not$ls180.v:6699$2356_Y + connect \Y $and$ls180.v:6699$2357_Y end - attribute \src "ls180.v:6696.40-6696.150" - cell $and $and$ls180.v:6696$2359 + attribute \src "ls180.v:6699.40-6699.150" + cell $and $and$ls180.v:6699$2359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6696$2357_Y - connect \B $eq$ls180.v:6696$2358_Y - connect \Y $and$ls180.v:6696$2359_Y + connect \A $and$ls180.v:6699$2357_Y + connect \B $eq$ls180.v:6699$2358_Y + connect \Y $and$ls180.v:6699$2359_Y end - attribute \src "ls180.v:6698.45-6698.100" - cell $and $and$ls180.v:6698$2360 + attribute \src "ls180.v:6701.45-6701.100" + cell $and $and$ls180.v:6701$2360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261812,43 +264341,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6698$2360_Y + connect \Y $and$ls180.v:6701$2360_Y end - attribute \src "ls180.v:6698.44-6698.151" - cell $and $and$ls180.v:6698$2362 + attribute \src "ls180.v:6701.44-6701.151" + cell $and $and$ls180.v:6701$2362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6698$2360_Y - connect \B $eq$ls180.v:6698$2361_Y - connect \Y $and$ls180.v:6698$2362_Y + connect \A $and$ls180.v:6701$2360_Y + connect \B $eq$ls180.v:6701$2361_Y + connect \Y $and$ls180.v:6701$2362_Y end - attribute \src "ls180.v:6699.45-6699.103" - cell $and $and$ls180.v:6699$2364 + attribute \src "ls180.v:6702.45-6702.103" + cell $and $and$ls180.v:6702$2364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6699$2363_Y - connect \Y $and$ls180.v:6699$2364_Y + connect \B $not$ls180.v:6702$2363_Y + connect \Y $and$ls180.v:6702$2364_Y end - attribute \src "ls180.v:6699.44-6699.154" - cell $and $and$ls180.v:6699$2366 + attribute \src "ls180.v:6702.44-6702.154" + cell $and $and$ls180.v:6702$2366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6699$2364_Y - connect \B $eq$ls180.v:6699$2365_Y - connect \Y $and$ls180.v:6699$2366_Y + connect \A $and$ls180.v:6702$2364_Y + connect \B $eq$ls180.v:6702$2365_Y + connect \Y $and$ls180.v:6702$2366_Y end - attribute \src "ls180.v:6701.46-6701.101" - cell $and $and$ls180.v:6701$2367 + attribute \src "ls180.v:6704.46-6704.101" + cell $and $and$ls180.v:6704$2367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261856,43 +264385,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6701$2367_Y + connect \Y $and$ls180.v:6704$2367_Y end - attribute \src "ls180.v:6701.45-6701.152" - cell $and $and$ls180.v:6701$2369 + attribute \src "ls180.v:6704.45-6704.152" + cell $and $and$ls180.v:6704$2369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6701$2367_Y - connect \B $eq$ls180.v:6701$2368_Y - connect \Y $and$ls180.v:6701$2369_Y + connect \A $and$ls180.v:6704$2367_Y + connect \B $eq$ls180.v:6704$2368_Y + connect \Y $and$ls180.v:6704$2369_Y end - attribute \src "ls180.v:6702.46-6702.104" - cell $and $and$ls180.v:6702$2371 + attribute \src "ls180.v:6705.46-6705.104" + cell $and $and$ls180.v:6705$2371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6702$2370_Y - connect \Y $and$ls180.v:6702$2371_Y + connect \B $not$ls180.v:6705$2370_Y + connect \Y $and$ls180.v:6705$2371_Y end - attribute \src "ls180.v:6702.45-6702.155" - cell $and $and$ls180.v:6702$2373 + attribute \src "ls180.v:6705.45-6705.155" + cell $and $and$ls180.v:6705$2373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6702$2371_Y - connect \B $eq$ls180.v:6702$2372_Y - connect \Y $and$ls180.v:6702$2373_Y + connect \A $and$ls180.v:6705$2371_Y + connect \B $eq$ls180.v:6705$2372_Y + connect \Y $and$ls180.v:6705$2373_Y end - attribute \src "ls180.v:6704.44-6704.99" - cell $and $and$ls180.v:6704$2374 + attribute \src "ls180.v:6707.44-6707.99" + cell $and $and$ls180.v:6707$2374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261900,43 +264429,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6704$2374_Y + connect \Y $and$ls180.v:6707$2374_Y end - attribute \src "ls180.v:6704.43-6704.150" - cell $and $and$ls180.v:6704$2376 + attribute \src "ls180.v:6707.43-6707.150" + cell $and $and$ls180.v:6707$2376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6704$2374_Y - connect \B $eq$ls180.v:6704$2375_Y - connect \Y $and$ls180.v:6704$2376_Y + connect \A $and$ls180.v:6707$2374_Y + connect \B $eq$ls180.v:6707$2375_Y + connect \Y $and$ls180.v:6707$2376_Y end - attribute \src "ls180.v:6705.44-6705.102" - cell $and $and$ls180.v:6705$2378 + attribute \src "ls180.v:6708.44-6708.102" + cell $and $and$ls180.v:6708$2378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6705$2377_Y - connect \Y $and$ls180.v:6705$2378_Y + connect \B $not$ls180.v:6708$2377_Y + connect \Y $and$ls180.v:6708$2378_Y end - attribute \src "ls180.v:6705.43-6705.153" - cell $and $and$ls180.v:6705$2380 + attribute \src "ls180.v:6708.43-6708.153" + cell $and $and$ls180.v:6708$2380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6705$2378_Y - connect \B $eq$ls180.v:6705$2379_Y - connect \Y $and$ls180.v:6705$2380_Y + connect \A $and$ls180.v:6708$2378_Y + connect \B $eq$ls180.v:6708$2379_Y + connect \Y $and$ls180.v:6708$2380_Y end - attribute \src "ls180.v:6707.41-6707.96" - cell $and $and$ls180.v:6707$2381 + attribute \src "ls180.v:6710.41-6710.96" + cell $and $and$ls180.v:6710$2381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261944,43 +264473,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6707$2381_Y + connect \Y $and$ls180.v:6710$2381_Y end - attribute \src "ls180.v:6707.40-6707.147" - cell $and $and$ls180.v:6707$2383 + attribute \src "ls180.v:6710.40-6710.147" + cell $and $and$ls180.v:6710$2383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6707$2381_Y - connect \B $eq$ls180.v:6707$2382_Y - connect \Y $and$ls180.v:6707$2383_Y + connect \A $and$ls180.v:6710$2381_Y + connect \B $eq$ls180.v:6710$2382_Y + connect \Y $and$ls180.v:6710$2383_Y end - attribute \src "ls180.v:6708.41-6708.99" - cell $and $and$ls180.v:6708$2385 + attribute \src "ls180.v:6711.41-6711.99" + cell $and $and$ls180.v:6711$2385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6708$2384_Y - connect \Y $and$ls180.v:6708$2385_Y + connect \B $not$ls180.v:6711$2384_Y + connect \Y $and$ls180.v:6711$2385_Y end - attribute \src "ls180.v:6708.40-6708.150" - cell $and $and$ls180.v:6708$2387 + attribute \src "ls180.v:6711.40-6711.150" + cell $and $and$ls180.v:6711$2387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6708$2385_Y - connect \B $eq$ls180.v:6708$2386_Y - connect \Y $and$ls180.v:6708$2387_Y + connect \A $and$ls180.v:6711$2385_Y + connect \B $eq$ls180.v:6711$2386_Y + connect \Y $and$ls180.v:6711$2387_Y end - attribute \src "ls180.v:6710.40-6710.95" - cell $and $and$ls180.v:6710$2388 + attribute \src "ls180.v:6713.40-6713.95" + cell $and $and$ls180.v:6713$2388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261988,43 +264517,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6710$2388_Y + connect \Y $and$ls180.v:6713$2388_Y end - attribute \src "ls180.v:6710.39-6710.146" - cell $and $and$ls180.v:6710$2390 + attribute \src "ls180.v:6713.39-6713.146" + cell $and $and$ls180.v:6713$2390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6710$2388_Y - connect \B $eq$ls180.v:6710$2389_Y - connect \Y $and$ls180.v:6710$2390_Y + connect \A $and$ls180.v:6713$2388_Y + connect \B $eq$ls180.v:6713$2389_Y + connect \Y $and$ls180.v:6713$2390_Y end - attribute \src "ls180.v:6711.40-6711.98" - cell $and $and$ls180.v:6711$2392 + attribute \src "ls180.v:6714.40-6714.98" + cell $and $and$ls180.v:6714$2392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6711$2391_Y - connect \Y $and$ls180.v:6711$2392_Y + connect \B $not$ls180.v:6714$2391_Y + connect \Y $and$ls180.v:6714$2392_Y end - attribute \src "ls180.v:6711.39-6711.149" - cell $and $and$ls180.v:6711$2394 + attribute \src "ls180.v:6714.39-6714.149" + cell $and $and$ls180.v:6714$2394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6711$2392_Y - connect \B $eq$ls180.v:6711$2393_Y - connect \Y $and$ls180.v:6711$2394_Y + connect \A $and$ls180.v:6714$2392_Y + connect \B $eq$ls180.v:6714$2393_Y + connect \Y $and$ls180.v:6714$2394_Y end - attribute \src "ls180.v:6723.46-6723.101" - cell $and $and$ls180.v:6723$2396 + attribute \src "ls180.v:6726.46-6726.101" + cell $and $and$ls180.v:6726$2396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262032,43 +264561,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6723$2396_Y + connect \Y $and$ls180.v:6726$2396_Y end - attribute \src "ls180.v:6723.45-6723.152" - cell $and $and$ls180.v:6723$2398 + attribute \src "ls180.v:6726.45-6726.152" + cell $and $and$ls180.v:6726$2398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6723$2396_Y - connect \B $eq$ls180.v:6723$2397_Y - connect \Y $and$ls180.v:6723$2398_Y + connect \A $and$ls180.v:6726$2396_Y + connect \B $eq$ls180.v:6726$2397_Y + connect \Y $and$ls180.v:6726$2398_Y end - attribute \src "ls180.v:6724.46-6724.104" - cell $and $and$ls180.v:6724$2400 + attribute \src "ls180.v:6727.46-6727.104" + cell $and $and$ls180.v:6727$2400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6724$2399_Y - connect \Y $and$ls180.v:6724$2400_Y + connect \B $not$ls180.v:6727$2399_Y + connect \Y $and$ls180.v:6727$2400_Y end - attribute \src "ls180.v:6724.45-6724.155" - cell $and $and$ls180.v:6724$2402 + attribute \src "ls180.v:6727.45-6727.155" + cell $and $and$ls180.v:6727$2402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6724$2400_Y - connect \B $eq$ls180.v:6724$2401_Y - connect \Y $and$ls180.v:6724$2402_Y + connect \A $and$ls180.v:6727$2400_Y + connect \B $eq$ls180.v:6727$2401_Y + connect \Y $and$ls180.v:6727$2402_Y end - attribute \src "ls180.v:6726.46-6726.101" - cell $and $and$ls180.v:6726$2403 + attribute \src "ls180.v:6729.46-6729.101" + cell $and $and$ls180.v:6729$2403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262076,43 +264605,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6726$2403_Y + connect \Y $and$ls180.v:6729$2403_Y end - attribute \src "ls180.v:6726.45-6726.152" - cell $and $and$ls180.v:6726$2405 + attribute \src "ls180.v:6729.45-6729.152" + cell $and $and$ls180.v:6729$2405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6726$2403_Y - connect \B $eq$ls180.v:6726$2404_Y - connect \Y $and$ls180.v:6726$2405_Y + connect \A $and$ls180.v:6729$2403_Y + connect \B $eq$ls180.v:6729$2404_Y + connect \Y $and$ls180.v:6729$2405_Y end - attribute \src "ls180.v:6727.46-6727.104" - cell $and $and$ls180.v:6727$2407 + attribute \src "ls180.v:6730.46-6730.104" + cell $and $and$ls180.v:6730$2407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6727$2406_Y - connect \Y $and$ls180.v:6727$2407_Y + connect \B $not$ls180.v:6730$2406_Y + connect \Y $and$ls180.v:6730$2407_Y end - attribute \src "ls180.v:6727.45-6727.155" - cell $and $and$ls180.v:6727$2409 + attribute \src "ls180.v:6730.45-6730.155" + cell $and $and$ls180.v:6730$2409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6727$2407_Y - connect \B $eq$ls180.v:6727$2408_Y - connect \Y $and$ls180.v:6727$2409_Y + connect \A $and$ls180.v:6730$2407_Y + connect \B $eq$ls180.v:6730$2408_Y + connect \Y $and$ls180.v:6730$2409_Y end - attribute \src "ls180.v:6729.46-6729.101" - cell $and $and$ls180.v:6729$2410 + attribute \src "ls180.v:6732.46-6732.101" + cell $and $and$ls180.v:6732$2410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262120,43 +264649,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6729$2410_Y + connect \Y $and$ls180.v:6732$2410_Y end - attribute \src "ls180.v:6729.45-6729.152" - cell $and $and$ls180.v:6729$2412 + attribute \src "ls180.v:6732.45-6732.152" + cell $and $and$ls180.v:6732$2412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6729$2410_Y - connect \B $eq$ls180.v:6729$2411_Y - connect \Y $and$ls180.v:6729$2412_Y + connect \A $and$ls180.v:6732$2410_Y + connect \B $eq$ls180.v:6732$2411_Y + connect \Y $and$ls180.v:6732$2412_Y end - attribute \src "ls180.v:6730.46-6730.104" - cell $and $and$ls180.v:6730$2414 + attribute \src "ls180.v:6733.46-6733.104" + cell $and $and$ls180.v:6733$2414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6730$2413_Y - connect \Y $and$ls180.v:6730$2414_Y + connect \B $not$ls180.v:6733$2413_Y + connect \Y $and$ls180.v:6733$2414_Y end - attribute \src "ls180.v:6730.45-6730.155" - cell $and $and$ls180.v:6730$2416 + attribute \src "ls180.v:6733.45-6733.155" + cell $and $and$ls180.v:6733$2416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6730$2414_Y - connect \B $eq$ls180.v:6730$2415_Y - connect \Y $and$ls180.v:6730$2416_Y + connect \A $and$ls180.v:6733$2414_Y + connect \B $eq$ls180.v:6733$2415_Y + connect \Y $and$ls180.v:6733$2416_Y end - attribute \src "ls180.v:6732.46-6732.101" - cell $and $and$ls180.v:6732$2417 + attribute \src "ls180.v:6735.46-6735.101" + cell $and $and$ls180.v:6735$2417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262164,263 +264693,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6732$2417_Y + connect \Y $and$ls180.v:6735$2417_Y end - attribute \src "ls180.v:6732.45-6732.152" - cell $and $and$ls180.v:6732$2419 + attribute \src "ls180.v:6735.45-6735.152" + cell $and $and$ls180.v:6735$2419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6732$2417_Y - connect \B $eq$ls180.v:6732$2418_Y - connect \Y $and$ls180.v:6732$2419_Y + connect \A $and$ls180.v:6735$2417_Y + connect \B $eq$ls180.v:6735$2418_Y + connect \Y $and$ls180.v:6735$2419_Y end - attribute \src "ls180.v:6733.46-6733.104" - cell $and $and$ls180.v:6733$2421 + attribute \src "ls180.v:6736.46-6736.104" + cell $and $and$ls180.v:6736$2421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6733$2420_Y - connect \Y $and$ls180.v:6733$2421_Y + connect \B $not$ls180.v:6736$2420_Y + connect \Y $and$ls180.v:6736$2421_Y end - attribute \src "ls180.v:6733.45-6733.155" - cell $and $and$ls180.v:6733$2423 + attribute \src "ls180.v:6736.45-6736.155" + cell $and $and$ls180.v:6736$2423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6733$2421_Y - connect \B $eq$ls180.v:6733$2422_Y - connect \Y $and$ls180.v:6733$2423_Y + connect \A $and$ls180.v:6736$2421_Y + connect \B $eq$ls180.v:6736$2422_Y + connect \Y $and$ls180.v:6736$2423_Y end - attribute \src "ls180.v:7114.109-7114.178" - cell $and $and$ls180.v:7114$2461 + attribute \src "ls180.v:7117.109-7117.178" + cell $and $and$ls180.v:7117$2461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7114$2460_Y - connect \Y $and$ls180.v:7114$2461_Y + connect \B $eq$ls180.v:7117$2460_Y + connect \Y $and$ls180.v:7117$2461_Y end - attribute \src "ls180.v:7114.184-7114.253" - cell $and $and$ls180.v:7114$2464 + attribute \src "ls180.v:7117.184-7117.253" + cell $and $and$ls180.v:7117$2464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7114$2463_Y - connect \Y $and$ls180.v:7114$2464_Y + connect \B $eq$ls180.v:7117$2463_Y + connect \Y $and$ls180.v:7117$2464_Y end - attribute \src "ls180.v:7114.259-7114.328" - cell $and $and$ls180.v:7114$2467 + attribute \src "ls180.v:7117.259-7117.328" + cell $and $and$ls180.v:7117$2467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7114$2466_Y - connect \Y $and$ls180.v:7114$2467_Y + connect \B $eq$ls180.v:7117$2466_Y + connect \Y $and$ls180.v:7117$2467_Y end - attribute \src "ls180.v:7114.40-7114.331" - cell $and $and$ls180.v:7114$2470 + attribute \src "ls180.v:7117.40-7117.331" + cell $and $and$ls180.v:7117$2470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7114$2459_Y - connect \B $not$ls180.v:7114$2469_Y - connect \Y $and$ls180.v:7114$2470_Y + connect \A $eq$ls180.v:7117$2459_Y + connect \B $not$ls180.v:7117$2469_Y + connect \Y $and$ls180.v:7117$2470_Y end - attribute \src "ls180.v:7114.39-7114.354" - cell $and $and$ls180.v:7114$2471 + attribute \src "ls180.v:7117.39-7117.354" + cell $and $and$ls180.v:7117$2471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7114$2470_Y + connect \A $and$ls180.v:7117$2470_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7114$2471_Y + connect \Y $and$ls180.v:7117$2471_Y end - attribute \src "ls180.v:7138.109-7138.178" - cell $and $and$ls180.v:7138$2477 + attribute \src "ls180.v:7141.109-7141.178" + cell $and $and$ls180.v:7141$2477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7138$2476_Y - connect \Y $and$ls180.v:7138$2477_Y + connect \B $eq$ls180.v:7141$2476_Y + connect \Y $and$ls180.v:7141$2477_Y end - attribute \src "ls180.v:7138.184-7138.253" - cell $and $and$ls180.v:7138$2480 + attribute \src "ls180.v:7141.184-7141.253" + cell $and $and$ls180.v:7141$2480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7138$2479_Y - connect \Y $and$ls180.v:7138$2480_Y + connect \B $eq$ls180.v:7141$2479_Y + connect \Y $and$ls180.v:7141$2480_Y end - attribute \src "ls180.v:7138.259-7138.328" - cell $and $and$ls180.v:7138$2483 + attribute \src "ls180.v:7141.259-7141.328" + cell $and $and$ls180.v:7141$2483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7138$2482_Y - connect \Y $and$ls180.v:7138$2483_Y + connect \B $eq$ls180.v:7141$2482_Y + connect \Y $and$ls180.v:7141$2483_Y end - attribute \src "ls180.v:7138.40-7138.331" - cell $and $and$ls180.v:7138$2486 + attribute \src "ls180.v:7141.40-7141.331" + cell $and $and$ls180.v:7141$2486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7138$2475_Y - connect \B $not$ls180.v:7138$2485_Y - connect \Y $and$ls180.v:7138$2486_Y + connect \A $eq$ls180.v:7141$2475_Y + connect \B $not$ls180.v:7141$2485_Y + connect \Y $and$ls180.v:7141$2486_Y end - attribute \src "ls180.v:7138.39-7138.354" - cell $and $and$ls180.v:7138$2487 + attribute \src "ls180.v:7141.39-7141.354" + cell $and $and$ls180.v:7141$2487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7138$2486_Y + connect \A $and$ls180.v:7141$2486_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7138$2487_Y + connect \Y $and$ls180.v:7141$2487_Y end - attribute \src "ls180.v:7162.109-7162.178" - cell $and $and$ls180.v:7162$2493 + attribute \src "ls180.v:7165.109-7165.178" + cell $and $and$ls180.v:7165$2493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7162$2492_Y - connect \Y $and$ls180.v:7162$2493_Y + connect \B $eq$ls180.v:7165$2492_Y + connect \Y $and$ls180.v:7165$2493_Y end - attribute \src "ls180.v:7162.184-7162.253" - cell $and $and$ls180.v:7162$2496 + attribute \src "ls180.v:7165.184-7165.253" + cell $and $and$ls180.v:7165$2496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7162$2495_Y - connect \Y $and$ls180.v:7162$2496_Y + connect \B $eq$ls180.v:7165$2495_Y + connect \Y $and$ls180.v:7165$2496_Y end - attribute \src "ls180.v:7162.259-7162.328" - cell $and $and$ls180.v:7162$2499 + attribute \src "ls180.v:7165.259-7165.328" + cell $and $and$ls180.v:7165$2499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7162$2498_Y - connect \Y $and$ls180.v:7162$2499_Y + connect \B $eq$ls180.v:7165$2498_Y + connect \Y $and$ls180.v:7165$2499_Y end - attribute \src "ls180.v:7162.40-7162.331" - cell $and $and$ls180.v:7162$2502 + attribute \src "ls180.v:7165.40-7165.331" + cell $and $and$ls180.v:7165$2502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7162$2491_Y - connect \B $not$ls180.v:7162$2501_Y - connect \Y $and$ls180.v:7162$2502_Y + connect \A $eq$ls180.v:7165$2491_Y + connect \B $not$ls180.v:7165$2501_Y + connect \Y $and$ls180.v:7165$2502_Y end - attribute \src "ls180.v:7162.39-7162.354" - cell $and $and$ls180.v:7162$2503 + attribute \src "ls180.v:7165.39-7165.354" + cell $and $and$ls180.v:7165$2503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7162$2502_Y + connect \A $and$ls180.v:7165$2502_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7162$2503_Y + connect \Y $and$ls180.v:7165$2503_Y end - attribute \src "ls180.v:7186.109-7186.178" - cell $and $and$ls180.v:7186$2509 + attribute \src "ls180.v:7189.109-7189.178" + cell $and $and$ls180.v:7189$2509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7186$2508_Y - connect \Y $and$ls180.v:7186$2509_Y + connect \B $eq$ls180.v:7189$2508_Y + connect \Y $and$ls180.v:7189$2509_Y end - attribute \src "ls180.v:7186.184-7186.253" - cell $and $and$ls180.v:7186$2512 + attribute \src "ls180.v:7189.184-7189.253" + cell $and $and$ls180.v:7189$2512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7186$2511_Y - connect \Y $and$ls180.v:7186$2512_Y + connect \B $eq$ls180.v:7189$2511_Y + connect \Y $and$ls180.v:7189$2512_Y end - attribute \src "ls180.v:7186.259-7186.328" - cell $and $and$ls180.v:7186$2515 + attribute \src "ls180.v:7189.259-7189.328" + cell $and $and$ls180.v:7189$2515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7186$2514_Y - connect \Y $and$ls180.v:7186$2515_Y + connect \B $eq$ls180.v:7189$2514_Y + connect \Y $and$ls180.v:7189$2515_Y end - attribute \src "ls180.v:7186.40-7186.331" - cell $and $and$ls180.v:7186$2518 + attribute \src "ls180.v:7189.40-7189.331" + cell $and $and$ls180.v:7189$2518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7186$2507_Y - connect \B $not$ls180.v:7186$2517_Y - connect \Y $and$ls180.v:7186$2518_Y + connect \A $eq$ls180.v:7189$2507_Y + connect \B $not$ls180.v:7189$2517_Y + connect \Y $and$ls180.v:7189$2518_Y end - attribute \src "ls180.v:7186.39-7186.354" - cell $and $and$ls180.v:7186$2519 + attribute \src "ls180.v:7189.39-7189.354" + cell $and $and$ls180.v:7189$2519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7186$2518_Y + connect \A $and$ls180.v:7189$2518_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7186$2519_Y + connect \Y $and$ls180.v:7189$2519_Y end - attribute \src "ls180.v:7391.39-7391.104" - cell $and $and$ls180.v:7391$2531 + attribute \src "ls180.v:7394.39-7394.104" + cell $and $and$ls180.v:7394$2531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262428,21 +264957,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7391$2531_Y + connect \Y $and$ls180.v:7394$2531_Y end - attribute \src "ls180.v:7391.38-7391.145" - cell $and $and$ls180.v:7391$2532 + attribute \src "ls180.v:7394.38-7394.145" + cell $and $and$ls180.v:7394$2532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7391$2531_Y + connect \A $and$ls180.v:7394$2531_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7391$2532_Y + connect \Y $and$ls180.v:7394$2532_Y end - attribute \src "ls180.v:7394.39-7394.104" - cell $and $and$ls180.v:7394$2533 + attribute \src "ls180.v:7397.39-7397.104" + cell $and $and$ls180.v:7397$2533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262450,21 +264979,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7394$2533_Y + connect \Y $and$ls180.v:7397$2533_Y end - attribute \src "ls180.v:7394.38-7394.145" - cell $and $and$ls180.v:7394$2534 + attribute \src "ls180.v:7397.38-7397.145" + cell $and $and$ls180.v:7397$2534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7394$2533_Y + connect \A $and$ls180.v:7397$2533_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7394$2534_Y + connect \Y $and$ls180.v:7397$2534_Y end - attribute \src "ls180.v:7397.39-7397.82" - cell $and $and$ls180.v:7397$2535 + attribute \src "ls180.v:7400.39-7400.82" + cell $and $and$ls180.v:7400$2535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262472,21 +265001,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7397$2535_Y + connect \Y $and$ls180.v:7400$2535_Y end - attribute \src "ls180.v:7397.38-7397.112" - cell $and $and$ls180.v:7397$2536 + attribute \src "ls180.v:7400.38-7400.112" + cell $and $and$ls180.v:7400$2536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7397$2535_Y + connect \A $and$ls180.v:7400$2535_Y connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7397$2536_Y + connect \Y $and$ls180.v:7400$2536_Y end - attribute \src "ls180.v:7408.39-7408.104" - cell $and $and$ls180.v:7408$2538 + attribute \src "ls180.v:7411.39-7411.104" + cell $and $and$ls180.v:7411$2538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262494,21 +265023,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7408$2538_Y + connect \Y $and$ls180.v:7411$2538_Y end - attribute \src "ls180.v:7408.38-7408.145" - cell $and $and$ls180.v:7408$2539 + attribute \src "ls180.v:7411.38-7411.145" + cell $and $and$ls180.v:7411$2539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7408$2538_Y + connect \A $and$ls180.v:7411$2538_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7408$2539_Y + connect \Y $and$ls180.v:7411$2539_Y end - attribute \src "ls180.v:7411.39-7411.104" - cell $and $and$ls180.v:7411$2540 + attribute \src "ls180.v:7414.39-7414.104" + cell $and $and$ls180.v:7414$2540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262516,21 +265045,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7411$2540_Y + connect \Y $and$ls180.v:7414$2540_Y end - attribute \src "ls180.v:7411.38-7411.145" - cell $and $and$ls180.v:7411$2541 + attribute \src "ls180.v:7414.38-7414.145" + cell $and $and$ls180.v:7414$2541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7411$2540_Y + connect \A $and$ls180.v:7414$2540_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7411$2541_Y + connect \Y $and$ls180.v:7414$2541_Y end - attribute \src "ls180.v:7414.39-7414.82" - cell $and $and$ls180.v:7414$2542 + attribute \src "ls180.v:7417.39-7417.82" + cell $and $and$ls180.v:7417$2542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262538,21 +265067,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7414$2542_Y + connect \Y $and$ls180.v:7417$2542_Y end - attribute \src "ls180.v:7414.38-7414.112" - cell $and $and$ls180.v:7414$2543 + attribute \src "ls180.v:7417.38-7417.112" + cell $and $and$ls180.v:7417$2543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7414$2542_Y + connect \A $and$ls180.v:7417$2542_Y connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7414$2543_Y + connect \Y $and$ls180.v:7417$2543_Y end - attribute \src "ls180.v:7425.39-7425.104" - cell $and $and$ls180.v:7425$2545 + attribute \src "ls180.v:7428.39-7428.104" + cell $and $and$ls180.v:7428$2545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262560,21 +265089,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7425$2545_Y + connect \Y $and$ls180.v:7428$2545_Y end - attribute \src "ls180.v:7425.38-7425.144" - cell $and $and$ls180.v:7425$2546 + attribute \src "ls180.v:7428.38-7428.144" + cell $and $and$ls180.v:7428$2546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7425$2545_Y + connect \A $and$ls180.v:7428$2545_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7425$2546_Y + connect \Y $and$ls180.v:7428$2546_Y end - attribute \src "ls180.v:7428.39-7428.104" - cell $and $and$ls180.v:7428$2547 + attribute \src "ls180.v:7431.39-7431.104" + cell $and $and$ls180.v:7431$2547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262582,21 +265111,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7428$2547_Y + connect \Y $and$ls180.v:7431$2547_Y end - attribute \src "ls180.v:7428.38-7428.144" - cell $and $and$ls180.v:7428$2548 + attribute \src "ls180.v:7431.38-7431.144" + cell $and $and$ls180.v:7431$2548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7428$2547_Y + connect \A $and$ls180.v:7431$2547_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7428$2548_Y + connect \Y $and$ls180.v:7431$2548_Y end - attribute \src "ls180.v:7431.39-7431.82" - cell $and $and$ls180.v:7431$2549 + attribute \src "ls180.v:7434.39-7434.82" + cell $and $and$ls180.v:7434$2549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262604,21 +265133,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7431$2549_Y + connect \Y $and$ls180.v:7434$2549_Y end - attribute \src "ls180.v:7431.38-7431.111" - cell $and $and$ls180.v:7431$2550 + attribute \src "ls180.v:7434.38-7434.111" + cell $and $and$ls180.v:7434$2550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7431$2549_Y + connect \A $and$ls180.v:7434$2549_Y connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7431$2550_Y + connect \Y $and$ls180.v:7434$2550_Y end - attribute \src "ls180.v:7442.39-7442.104" - cell $and $and$ls180.v:7442$2552 + attribute \src "ls180.v:7445.39-7445.104" + cell $and $and$ls180.v:7445$2552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262626,21 +265155,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7442$2552_Y + connect \Y $and$ls180.v:7445$2552_Y end - attribute \src "ls180.v:7442.38-7442.149" - cell $and $and$ls180.v:7442$2553 + attribute \src "ls180.v:7445.38-7445.149" + cell $and $and$ls180.v:7445$2553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7442$2552_Y + connect \A $and$ls180.v:7445$2552_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7442$2553_Y + connect \Y $and$ls180.v:7445$2553_Y end - attribute \src "ls180.v:7445.39-7445.104" - cell $and $and$ls180.v:7445$2554 + attribute \src "ls180.v:7448.39-7448.104" + cell $and $and$ls180.v:7448$2554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262648,21 +265177,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7445$2554_Y + connect \Y $and$ls180.v:7448$2554_Y end - attribute \src "ls180.v:7445.38-7445.149" - cell $and $and$ls180.v:7445$2555 + attribute \src "ls180.v:7448.38-7448.149" + cell $and $and$ls180.v:7448$2555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7445$2554_Y + connect \A $and$ls180.v:7448$2554_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7445$2555_Y + connect \Y $and$ls180.v:7448$2555_Y end - attribute \src "ls180.v:7448.39-7448.82" - cell $and $and$ls180.v:7448$2556 + attribute \src "ls180.v:7451.39-7451.82" + cell $and $and$ls180.v:7451$2556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262670,21 +265199,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7448$2556_Y + connect \Y $and$ls180.v:7451$2556_Y end - attribute \src "ls180.v:7448.38-7448.116" - cell $and $and$ls180.v:7448$2557 + attribute \src "ls180.v:7451.38-7451.116" + cell $and $and$ls180.v:7451$2557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7448$2556_Y + connect \A $and$ls180.v:7451$2556_Y connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7448$2557_Y + connect \Y $and$ls180.v:7451$2557_Y end - attribute \src "ls180.v:7459.39-7459.104" - cell $and $and$ls180.v:7459$2559 + attribute \src "ls180.v:7462.39-7462.104" + cell $and $and$ls180.v:7462$2559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262692,21 +265221,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7459$2559_Y + connect \Y $and$ls180.v:7462$2559_Y end - attribute \src "ls180.v:7459.38-7459.150" - cell $and $and$ls180.v:7459$2560 + attribute \src "ls180.v:7462.38-7462.150" + cell $and $and$ls180.v:7462$2560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7459$2559_Y + connect \A $and$ls180.v:7462$2559_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7459$2560_Y + connect \Y $and$ls180.v:7462$2560_Y end - attribute \src "ls180.v:7462.39-7462.104" - cell $and $and$ls180.v:7462$2561 + attribute \src "ls180.v:7465.39-7465.104" + cell $and $and$ls180.v:7465$2561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262714,21 +265243,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7462$2561_Y + connect \Y $and$ls180.v:7465$2561_Y end - attribute \src "ls180.v:7462.38-7462.150" - cell $and $and$ls180.v:7462$2562 + attribute \src "ls180.v:7465.38-7465.150" + cell $and $and$ls180.v:7465$2562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7462$2561_Y + connect \A $and$ls180.v:7465$2561_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7462$2562_Y + connect \Y $and$ls180.v:7465$2562_Y end - attribute \src "ls180.v:7465.39-7465.82" - cell $and $and$ls180.v:7465$2563 + attribute \src "ls180.v:7468.39-7468.82" + cell $and $and$ls180.v:7468$2563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262736,32 +265265,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7465$2563_Y + connect \Y $and$ls180.v:7468$2563_Y end - attribute \src "ls180.v:7465.38-7465.117" - cell $and $and$ls180.v:7465$2564 + attribute \src "ls180.v:7468.38-7468.117" + cell $and $and$ls180.v:7468$2564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7465$2563_Y + connect \A $and$ls180.v:7468$2563_Y connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7465$2564_Y + connect \Y $and$ls180.v:7468$2564_Y end - attribute \src "ls180.v:7687.17-7687.67" - cell $and $and$ls180.v:7687$2572 + attribute \src "ls180.v:7690.17-7690.67" + cell $and $and$ls180.v:7690$2572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7687$2571_Y + connect \A $not$ls180.v:7690$2571_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7687$2572_Y + connect \Y $and$ls180.v:7690$2572_Y end - attribute \src "ls180.v:7766.8-7766.67" - cell $and $and$ls180.v:7766$2603 + attribute \src "ls180.v:7769.8-7769.67" + cell $and $and$ls180.v:7769$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262769,32 +265298,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7766$2603_Y + connect \Y $and$ls180.v:7769$2603_Y end - attribute \src "ls180.v:7766.7-7766.102" - cell $and $and$ls180.v:7766$2605 + attribute \src "ls180.v:7769.7-7769.102" + cell $and $and$ls180.v:7769$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7766$2603_Y - connect \B $not$ls180.v:7766$2604_Y - connect \Y $and$ls180.v:7766$2605_Y + connect \A $and$ls180.v:7769$2603_Y + connect \B $not$ls180.v:7769$2604_Y + connect \Y $and$ls180.v:7769$2605_Y end - attribute \src "ls180.v:7785.7-7785.75" - cell $and $and$ls180.v:7785$2609 + attribute \src "ls180.v:7788.7-7788.75" + cell $and $and$ls180.v:7788$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7785$2608_Y + connect \A $not$ls180.v:7788$2608_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7785$2609_Y + connect \Y $and$ls180.v:7788$2609_Y end - attribute \src "ls180.v:7789.8-7789.65" - cell $and $and$ls180.v:7789$2610 + attribute \src "ls180.v:7792.8-7792.65" + cell $and $and$ls180.v:7792$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262802,21 +265331,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:7789$2610_Y + connect \Y $and$ls180.v:7792$2610_Y end - attribute \src "ls180.v:7789.7-7789.99" - cell $and $and$ls180.v:7789$2612 + attribute \src "ls180.v:7792.7-7792.99" + cell $and $and$ls180.v:7792$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7789$2610_Y - connect \B $not$ls180.v:7789$2611_Y - connect \Y $and$ls180.v:7789$2612_Y + connect \A $and$ls180.v:7792$2610_Y + connect \B $not$ls180.v:7792$2611_Y + connect \Y $and$ls180.v:7792$2612_Y end - attribute \src "ls180.v:7793.8-7793.65" - cell $and $and$ls180.v:7793$2613 + attribute \src "ls180.v:7796.8-7796.65" + cell $and $and$ls180.v:7796$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262824,21 +265353,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:7793$2613_Y + connect \Y $and$ls180.v:7796$2613_Y end - attribute \src "ls180.v:7793.7-7793.99" - cell $and $and$ls180.v:7793$2615 + attribute \src "ls180.v:7796.7-7796.99" + cell $and $and$ls180.v:7796$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7793$2613_Y - connect \B $not$ls180.v:7793$2614_Y - connect \Y $and$ls180.v:7793$2615_Y + connect \A $and$ls180.v:7796$2613_Y + connect \B $not$ls180.v:7796$2614_Y + connect \Y $and$ls180.v:7796$2615_Y end - attribute \src "ls180.v:7797.8-7797.65" - cell $and $and$ls180.v:7797$2616 + attribute \src "ls180.v:7800.8-7800.65" + cell $and $and$ls180.v:7800$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262846,21 +265375,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:7797$2616_Y + connect \Y $and$ls180.v:7800$2616_Y end - attribute \src "ls180.v:7797.7-7797.99" - cell $and $and$ls180.v:7797$2618 + attribute \src "ls180.v:7800.7-7800.99" + cell $and $and$ls180.v:7800$2618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7797$2616_Y - connect \B $not$ls180.v:7797$2617_Y - connect \Y $and$ls180.v:7797$2618_Y + connect \A $and$ls180.v:7800$2616_Y + connect \B $not$ls180.v:7800$2617_Y + connect \Y $and$ls180.v:7800$2618_Y end - attribute \src "ls180.v:7801.8-7801.65" - cell $and $and$ls180.v:7801$2619 + attribute \src "ls180.v:7804.8-7804.65" + cell $and $and$ls180.v:7804$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262868,43 +265397,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_cyc connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:7801$2619_Y + connect \Y $and$ls180.v:7804$2619_Y end - attribute \src "ls180.v:7801.7-7801.99" - cell $and $and$ls180.v:7801$2621 + attribute \src "ls180.v:7804.7-7804.99" + cell $and $and$ls180.v:7804$2621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7801$2619_Y - connect \B $not$ls180.v:7801$2620_Y - connect \Y $and$ls180.v:7801$2621_Y + connect \A $and$ls180.v:7804$2619_Y + connect \B $not$ls180.v:7804$2620_Y + connect \Y $and$ls180.v:7804$2621_Y end - attribute \src "ls180.v:7809.7-7809.56" - cell $and $and$ls180.v:7809$2623 + attribute \src "ls180.v:7812.7-7812.56" + cell $and $and$ls180.v:7812$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7809$2622_Y - connect \Y $and$ls180.v:7809$2623_Y + connect \B $not$ls180.v:7812$2622_Y + connect \Y $and$ls180.v:7812$2623_Y end - attribute \src "ls180.v:7837.7-7837.75" - cell $and $and$ls180.v:7837$2630 + attribute \src "ls180.v:7840.7-7840.75" + cell $and $and$ls180.v:7840$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7837$2629_Y - connect \Y $and$ls180.v:7837$2630_Y + connect \B $eq$ls180.v:7840$2629_Y + connect \Y $and$ls180.v:7840$2630_Y end - attribute \src "ls180.v:7879.8-7879.131" - cell $and $and$ls180.v:7879$2636 + attribute \src "ls180.v:7882.8-7882.131" + cell $and $and$ls180.v:7882$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262912,21 +265441,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7879$2636_Y + connect \Y $and$ls180.v:7882$2636_Y end - attribute \src "ls180.v:7879.7-7879.190" - cell $and $and$ls180.v:7879$2638 + attribute \src "ls180.v:7882.7-7882.190" + cell $and $and$ls180.v:7882$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7879$2636_Y - connect \B $not$ls180.v:7879$2637_Y - connect \Y $and$ls180.v:7879$2638_Y + connect \A $and$ls180.v:7882$2636_Y + connect \B $not$ls180.v:7882$2637_Y + connect \Y $and$ls180.v:7882$2638_Y end - attribute \src "ls180.v:7885.8-7885.131" - cell $and $and$ls180.v:7885$2641 + attribute \src "ls180.v:7888.8-7888.131" + cell $and $and$ls180.v:7888$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262934,21 +265463,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7885$2641_Y + connect \Y $and$ls180.v:7888$2641_Y end - attribute \src "ls180.v:7885.7-7885.190" - cell $and $and$ls180.v:7885$2643 + attribute \src "ls180.v:7888.7-7888.190" + cell $and $and$ls180.v:7888$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7885$2641_Y - connect \B $not$ls180.v:7885$2642_Y - connect \Y $and$ls180.v:7885$2643_Y + connect \A $and$ls180.v:7888$2641_Y + connect \B $not$ls180.v:7888$2642_Y + connect \Y $and$ls180.v:7888$2643_Y end - attribute \src "ls180.v:7925.8-7925.131" - cell $and $and$ls180.v:7925$2652 + attribute \src "ls180.v:7928.8-7928.131" + cell $and $and$ls180.v:7928$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262956,21 +265485,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7925$2652_Y + connect \Y $and$ls180.v:7928$2652_Y end - attribute \src "ls180.v:7925.7-7925.190" - cell $and $and$ls180.v:7925$2654 + attribute \src "ls180.v:7928.7-7928.190" + cell $and $and$ls180.v:7928$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7925$2652_Y - connect \B $not$ls180.v:7925$2653_Y - connect \Y $and$ls180.v:7925$2654_Y + connect \A $and$ls180.v:7928$2652_Y + connect \B $not$ls180.v:7928$2653_Y + connect \Y $and$ls180.v:7928$2654_Y end - attribute \src "ls180.v:7931.8-7931.131" - cell $and $and$ls180.v:7931$2657 + attribute \src "ls180.v:7934.8-7934.131" + cell $and $and$ls180.v:7934$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262978,21 +265507,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7931$2657_Y + connect \Y $and$ls180.v:7934$2657_Y end - attribute \src "ls180.v:7931.7-7931.190" - cell $and $and$ls180.v:7931$2659 + attribute \src "ls180.v:7934.7-7934.190" + cell $and $and$ls180.v:7934$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7931$2657_Y - connect \B $not$ls180.v:7931$2658_Y - connect \Y $and$ls180.v:7931$2659_Y + connect \A $and$ls180.v:7934$2657_Y + connect \B $not$ls180.v:7934$2658_Y + connect \Y $and$ls180.v:7934$2659_Y end - attribute \src "ls180.v:7971.8-7971.131" - cell $and $and$ls180.v:7971$2668 + attribute \src "ls180.v:7974.8-7974.131" + cell $and $and$ls180.v:7974$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263000,21 +265529,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7971$2668_Y + connect \Y $and$ls180.v:7974$2668_Y end - attribute \src "ls180.v:7971.7-7971.190" - cell $and $and$ls180.v:7971$2670 + attribute \src "ls180.v:7974.7-7974.190" + cell $and $and$ls180.v:7974$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7971$2668_Y - connect \B $not$ls180.v:7971$2669_Y - connect \Y $and$ls180.v:7971$2670_Y + connect \A $and$ls180.v:7974$2668_Y + connect \B $not$ls180.v:7974$2669_Y + connect \Y $and$ls180.v:7974$2670_Y end - attribute \src "ls180.v:7977.8-7977.131" - cell $and $and$ls180.v:7977$2673 + attribute \src "ls180.v:7980.8-7980.131" + cell $and $and$ls180.v:7980$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263022,21 +265551,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7977$2673_Y + connect \Y $and$ls180.v:7980$2673_Y end - attribute \src "ls180.v:7977.7-7977.190" - cell $and $and$ls180.v:7977$2675 + attribute \src "ls180.v:7980.7-7980.190" + cell $and $and$ls180.v:7980$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7977$2673_Y - connect \B $not$ls180.v:7977$2674_Y - connect \Y $and$ls180.v:7977$2675_Y + connect \A $and$ls180.v:7980$2673_Y + connect \B $not$ls180.v:7980$2674_Y + connect \Y $and$ls180.v:7980$2675_Y end - attribute \src "ls180.v:8017.8-8017.131" - cell $and $and$ls180.v:8017$2684 + attribute \src "ls180.v:8020.8-8020.131" + cell $and $and$ls180.v:8020$2684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263044,21 +265573,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8017$2684_Y + connect \Y $and$ls180.v:8020$2684_Y end - attribute \src "ls180.v:8017.7-8017.190" - cell $and $and$ls180.v:8017$2686 + attribute \src "ls180.v:8020.7-8020.190" + cell $and $and$ls180.v:8020$2686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8017$2684_Y - connect \B $not$ls180.v:8017$2685_Y - connect \Y $and$ls180.v:8017$2686_Y + connect \A $and$ls180.v:8020$2684_Y + connect \B $not$ls180.v:8020$2685_Y + connect \Y $and$ls180.v:8020$2686_Y end - attribute \src "ls180.v:8023.8-8023.131" - cell $and $and$ls180.v:8023$2689 + attribute \src "ls180.v:8026.8-8026.131" + cell $and $and$ls180.v:8026$2689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263066,109 +265595,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8023$2689_Y + connect \Y $and$ls180.v:8026$2689_Y end - attribute \src "ls180.v:8023.7-8023.190" - cell $and $and$ls180.v:8023$2691 + attribute \src "ls180.v:8026.7-8026.190" + cell $and $and$ls180.v:8026$2691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8023$2689_Y - connect \B $not$ls180.v:8023$2690_Y - connect \Y $and$ls180.v:8023$2691_Y + connect \A $and$ls180.v:8026$2689_Y + connect \B $not$ls180.v:8026$2690_Y + connect \Y $and$ls180.v:8026$2691_Y end - attribute \src "ls180.v:8220.48-8220.124" - cell $and $and$ls180.v:8220$2716 + attribute \src "ls180.v:8223.48-8223.124" + cell $and $and$ls180.v:8223$2716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8220$2715_Y + connect \A $eq$ls180.v:8223$2715_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8220$2716_Y + connect \Y $and$ls180.v:8223$2716_Y end - attribute \src "ls180.v:8220.130-8220.206" - cell $and $and$ls180.v:8220$2719 + attribute \src "ls180.v:8223.130-8223.206" + cell $and $and$ls180.v:8223$2719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8220$2718_Y + connect \A $eq$ls180.v:8223$2718_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8220$2719_Y + connect \Y $and$ls180.v:8223$2719_Y end - attribute \src "ls180.v:8220.212-8220.288" - cell $and $and$ls180.v:8220$2722 + attribute \src "ls180.v:8223.212-8223.288" + cell $and $and$ls180.v:8223$2722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8220$2721_Y + connect \A $eq$ls180.v:8223$2721_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8220$2722_Y + connect \Y $and$ls180.v:8223$2722_Y end - attribute \src "ls180.v:8220.294-8220.370" - cell $and $and$ls180.v:8220$2725 + attribute \src "ls180.v:8223.294-8223.370" + cell $and $and$ls180.v:8223$2725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8220$2724_Y + connect \A $eq$ls180.v:8223$2724_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8220$2725_Y + connect \Y $and$ls180.v:8223$2725_Y end - attribute \src "ls180.v:8221.49-8221.125" - cell $and $and$ls180.v:8221$2728 + attribute \src "ls180.v:8224.49-8224.125" + cell $and $and$ls180.v:8224$2728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8221$2727_Y + connect \A $eq$ls180.v:8224$2727_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8221$2728_Y + connect \Y $and$ls180.v:8224$2728_Y end - attribute \src "ls180.v:8221.131-8221.207" - cell $and $and$ls180.v:8221$2731 + attribute \src "ls180.v:8224.131-8224.207" + cell $and $and$ls180.v:8224$2731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8221$2730_Y + connect \A $eq$ls180.v:8224$2730_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8221$2731_Y + connect \Y $and$ls180.v:8224$2731_Y end - attribute \src "ls180.v:8221.213-8221.289" - cell $and $and$ls180.v:8221$2734 + attribute \src "ls180.v:8224.213-8224.289" + cell $and $and$ls180.v:8224$2734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8221$2733_Y + connect \A $eq$ls180.v:8224$2733_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8221$2734_Y + connect \Y $and$ls180.v:8224$2734_Y end - attribute \src "ls180.v:8221.295-8221.371" - cell $and $and$ls180.v:8221$2737 + attribute \src "ls180.v:8224.295-8224.371" + cell $and $and$ls180.v:8224$2737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8221$2736_Y + connect \A $eq$ls180.v:8224$2736_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8221$2737_Y + connect \Y $and$ls180.v:8224$2737_Y end - attribute \src "ls180.v:8240.8-8240.49" - cell $and $and$ls180.v:8240$2740 + attribute \src "ls180.v:8243.8-8243.49" + cell $and $and$ls180.v:8243$2740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263176,10 +265705,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8240$2740_Y + connect \Y $and$ls180.v:8243$2740_Y end - attribute \src "ls180.v:8243.8-8243.53" - cell $and $and$ls180.v:8243$2741 + attribute \src "ls180.v:8246.8-8246.53" + cell $and $and$ls180.v:8246$2741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263187,32 +265716,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8243$2741_Y + connect \Y $and$ls180.v:8246$2741_Y end - attribute \src "ls180.v:8248.8-8248.59" - cell $and $and$ls180.v:8248$2743 + attribute \src "ls180.v:8251.8-8251.59" + cell $and $and$ls180.v:8251$2743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8248$2742_Y - connect \Y $and$ls180.v:8248$2743_Y + connect \B $not$ls180.v:8251$2742_Y + connect \Y $and$ls180.v:8251$2743_Y end - attribute \src "ls180.v:8248.7-8248.90" - cell $and $and$ls180.v:8248$2745 + attribute \src "ls180.v:8251.7-8251.90" + cell $and $and$ls180.v:8251$2745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8248$2743_Y - connect \B $not$ls180.v:8248$2744_Y - connect \Y $and$ls180.v:8248$2745_Y + connect \A $and$ls180.v:8251$2743_Y + connect \B $not$ls180.v:8251$2744_Y + connect \Y $and$ls180.v:8251$2745_Y end - attribute \src "ls180.v:8254.8-8254.59" - cell $and $and$ls180.v:8254$2746 + attribute \src "ls180.v:8257.8-8257.59" + cell $and $and$ls180.v:8257$2746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263220,43 +265749,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_uart_clk_txen connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8254$2746_Y + connect \Y $and$ls180.v:8257$2746_Y end - attribute \src "ls180.v:8278.8-8278.48" - cell $and $and$ls180.v:8278$2753 + attribute \src "ls180.v:8281.8-8281.48" + cell $and $and$ls180.v:8281$2753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8278$2752_Y + connect \A $not$ls180.v:8281$2752_Y connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8278$2753_Y + connect \Y $and$ls180.v:8281$2753_Y end - attribute \src "ls180.v:8311.7-8311.57" - cell $and $and$ls180.v:8311$2759 + attribute \src "ls180.v:8314.7-8314.57" + cell $and $and$ls180.v:8314$2759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8311$2758_Y + connect \A $not$ls180.v:8314$2758_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8311$2759_Y + connect \Y $and$ls180.v:8314$2759_Y end - attribute \src "ls180.v:8318.7-8318.57" - cell $and $and$ls180.v:8318$2761 + attribute \src "ls180.v:8321.7-8321.57" + cell $and $and$ls180.v:8321$2761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8318$2760_Y + connect \A $not$ls180.v:8321$2760_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8318$2761_Y + connect \Y $and$ls180.v:8321$2761_Y end - attribute \src "ls180.v:8328.8-8328.75" - cell $and $and$ls180.v:8328$2762 + attribute \src "ls180.v:8331.8-8331.75" + cell $and $and$ls180.v:8331$2762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263264,21 +265793,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8328$2762_Y + connect \Y $and$ls180.v:8331$2762_Y end - attribute \src "ls180.v:8328.7-8328.107" - cell $and $and$ls180.v:8328$2764 + attribute \src "ls180.v:8331.7-8331.107" + cell $and $and$ls180.v:8331$2764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8328$2762_Y - connect \B $not$ls180.v:8328$2763_Y - connect \Y $and$ls180.v:8328$2764_Y + connect \A $and$ls180.v:8331$2762_Y + connect \B $not$ls180.v:8331$2763_Y + connect \Y $and$ls180.v:8331$2764_Y end - attribute \src "ls180.v:8334.8-8334.75" - cell $and $and$ls180.v:8334$2767 + attribute \src "ls180.v:8337.8-8337.75" + cell $and $and$ls180.v:8337$2767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263286,21 +265815,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8334$2767_Y + connect \Y $and$ls180.v:8337$2767_Y end - attribute \src "ls180.v:8334.7-8334.107" - cell $and $and$ls180.v:8334$2769 + attribute \src "ls180.v:8337.7-8337.107" + cell $and $and$ls180.v:8337$2769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8334$2767_Y - connect \B $not$ls180.v:8334$2768_Y - connect \Y $and$ls180.v:8334$2769_Y + connect \A $and$ls180.v:8337$2767_Y + connect \B $not$ls180.v:8337$2768_Y + connect \Y $and$ls180.v:8337$2769_Y end - attribute \src "ls180.v:8350.8-8350.75" - cell $and $and$ls180.v:8350$2773 + attribute \src "ls180.v:8353.8-8353.75" + cell $and $and$ls180.v:8353$2773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263308,21 +265837,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8350$2773_Y + connect \Y $and$ls180.v:8353$2773_Y end - attribute \src "ls180.v:8350.7-8350.107" - cell $and $and$ls180.v:8350$2775 + attribute \src "ls180.v:8353.7-8353.107" + cell $and $and$ls180.v:8353$2775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8350$2773_Y - connect \B $not$ls180.v:8350$2774_Y - connect \Y $and$ls180.v:8350$2775_Y + connect \A $and$ls180.v:8353$2773_Y + connect \B $not$ls180.v:8353$2774_Y + connect \Y $and$ls180.v:8353$2775_Y end - attribute \src "ls180.v:8356.8-8356.75" - cell $and $and$ls180.v:8356$2778 + attribute \src "ls180.v:8359.8-8359.75" + cell $and $and$ls180.v:8359$2778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263330,21 +265859,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8356$2778_Y + connect \Y $and$ls180.v:8359$2778_Y end - attribute \src "ls180.v:8356.7-8356.107" - cell $and $and$ls180.v:8356$2780 + attribute \src "ls180.v:8359.7-8359.107" + cell $and $and$ls180.v:8359$2780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8356$2778_Y - connect \B $not$ls180.v:8356$2779_Y - connect \Y $and$ls180.v:8356$2780_Y + connect \A $and$ls180.v:8359$2778_Y + connect \B $not$ls180.v:8359$2779_Y + connect \Y $and$ls180.v:8359$2780_Y end - attribute \src "ls180.v:8504.7-8504.96" - cell $and $and$ls180.v:8504$2808 + attribute \src "ls180.v:8507.7-8507.96" + cell $and $and$ls180.v:8507$2808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263352,10 +265881,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8504$2808_Y + connect \Y $and$ls180.v:8507$2808_Y end - attribute \src "ls180.v:8505.8-8505.93" - cell $and $and$ls180.v:8505$2809 + attribute \src "ls180.v:8508.8-8508.93" + cell $and $and$ls180.v:8508$2809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263363,10 +265892,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8505$2809_Y + connect \Y $and$ls180.v:8508$2809_Y end - attribute \src "ls180.v:8513.8-8513.93" - cell $and $and$ls180.v:8513$2810 + attribute \src "ls180.v:8516.8-8516.93" + cell $and $and$ls180.v:8516$2810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263374,10 +265903,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8513$2810_Y + connect \Y $and$ls180.v:8516$2810_Y end - attribute \src "ls180.v:8585.7-8585.98" - cell $and $and$ls180.v:8585$2820 + attribute \src "ls180.v:8588.7-8588.98" + cell $and $and$ls180.v:8588$2820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263385,10 +265914,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8585$2820_Y + connect \Y $and$ls180.v:8588$2820_Y end - attribute \src "ls180.v:8586.8-8586.95" - cell $and $and$ls180.v:8586$2821 + attribute \src "ls180.v:8589.8-8589.95" + cell $and $and$ls180.v:8589$2821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263396,10 +265925,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8586$2821_Y + connect \Y $and$ls180.v:8589$2821_Y end - attribute \src "ls180.v:8594.8-8594.95" - cell $and $and$ls180.v:8594$2822 + attribute \src "ls180.v:8597.8-8597.95" + cell $and $and$ls180.v:8597$2822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263407,10 +265936,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8594$2822_Y + connect \Y $and$ls180.v:8597$2822_Y end - attribute \src "ls180.v:8664.7-8664.100" - cell $and $and$ls180.v:8664$2832 + attribute \src "ls180.v:8667.7-8667.100" + cell $and $and$ls180.v:8667$2832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263418,10 +265947,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8664$2832_Y + connect \Y $and$ls180.v:8667$2832_Y end - attribute \src "ls180.v:8665.8-8665.97" - cell $and $and$ls180.v:8665$2833 + attribute \src "ls180.v:8668.8-8668.97" + cell $and $and$ls180.v:8668$2833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263429,10 +265958,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8665$2833_Y + connect \Y $and$ls180.v:8668$2833_Y end - attribute \src "ls180.v:8673.8-8673.97" - cell $and $and$ls180.v:8673$2834 + attribute \src "ls180.v:8676.8-8676.97" + cell $and $and$ls180.v:8676$2834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263440,10 +265969,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8673$2834_Y + connect \Y $and$ls180.v:8676$2834_Y end - attribute \src "ls180.v:8764.7-8764.82" - cell $and $and$ls180.v:8764$2840 + attribute \src "ls180.v:8767.7-8767.82" + cell $and $and$ls180.v:8767$2840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263451,10 +265980,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8764$2840_Y + connect \Y $and$ls180.v:8767$2840_Y end - attribute \src "ls180.v:8767.7-8767.82" - cell $and $and$ls180.v:8767$2841 + attribute \src "ls180.v:8770.7-8770.82" + cell $and $and$ls180.v:8770$2841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263462,10 +265991,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8767$2841_Y + connect \Y $and$ls180.v:8770$2841_Y end - attribute \src "ls180.v:8770.7-8770.82" - cell $and $and$ls180.v:8770$2842 + attribute \src "ls180.v:8773.7-8773.82" + cell $and $and$ls180.v:8773$2842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263473,10 +266002,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8770$2842_Y + connect \Y $and$ls180.v:8773$2842_Y end - attribute \src "ls180.v:8773.7-8773.82" - cell $and $and$ls180.v:8773$2843 + attribute \src "ls180.v:8776.7-8776.82" + cell $and $and$ls180.v:8776$2843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263484,10 +266013,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8773$2843_Y + connect \Y $and$ls180.v:8776$2843_Y end - attribute \src "ls180.v:8776.7-8776.82" - cell $and $and$ls180.v:8776$2844 + attribute \src "ls180.v:8779.7-8779.82" + cell $and $and$ls180.v:8779$2844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263495,10 +266024,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8776$2844_Y + connect \Y $and$ls180.v:8779$2844_Y end - attribute \src "ls180.v:8781.7-8781.82" - cell $and $and$ls180.v:8781$2845 + attribute \src "ls180.v:8784.7-8784.82" + cell $and $and$ls180.v:8784$2845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263506,10 +266035,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8781$2845_Y + connect \Y $and$ls180.v:8784$2845_Y end - attribute \src "ls180.v:8786.7-8786.82" - cell $and $and$ls180.v:8786$2846 + attribute \src "ls180.v:8789.7-8789.82" + cell $and $and$ls180.v:8789$2846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263517,10 +266046,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8786$2846_Y + connect \Y $and$ls180.v:8789$2846_Y end - attribute \src "ls180.v:8791.7-8791.82" - cell $and $and$ls180.v:8791$2847 + attribute \src "ls180.v:8794.7-8794.82" + cell $and $and$ls180.v:8794$2847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263528,10 +266057,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8791$2847_Y + connect \Y $and$ls180.v:8794$2847_Y end - attribute \src "ls180.v:8796.7-8796.82" - cell $and $and$ls180.v:8796$2848 + attribute \src "ls180.v:8799.7-8799.82" + cell $and $and$ls180.v:8799$2848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263539,10 +266068,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8796$2848_Y + connect \Y $and$ls180.v:8799$2848_Y end - attribute \src "ls180.v:8861.8-8861.83" - cell $and $and$ls180.v:8861$2851 + attribute \src "ls180.v:8864.8-8864.83" + cell $and $and$ls180.v:8864$2851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263550,21 +266079,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8861$2851_Y + connect \Y $and$ls180.v:8864$2851_Y end - attribute \src "ls180.v:8861.7-8861.119" - cell $and $and$ls180.v:8861$2853 + attribute \src "ls180.v:8864.7-8864.119" + cell $and $and$ls180.v:8864$2853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8861$2851_Y - connect \B $not$ls180.v:8861$2852_Y - connect \Y $and$ls180.v:8861$2853_Y + connect \A $and$ls180.v:8864$2851_Y + connect \B $not$ls180.v:8864$2852_Y + connect \Y $and$ls180.v:8864$2853_Y end - attribute \src "ls180.v:8867.8-8867.83" - cell $and $and$ls180.v:8867$2856 + attribute \src "ls180.v:8870.8-8870.83" + cell $and $and$ls180.v:8870$2856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263572,21 +266101,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8867$2856_Y + connect \Y $and$ls180.v:8870$2856_Y end - attribute \src "ls180.v:8867.7-8867.119" - cell $and $and$ls180.v:8867$2858 + attribute \src "ls180.v:8870.7-8870.119" + cell $and $and$ls180.v:8870$2858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8867$2856_Y - connect \B $not$ls180.v:8867$2857_Y - connect \Y $and$ls180.v:8867$2858_Y + connect \A $and$ls180.v:8870$2856_Y + connect \B $not$ls180.v:8870$2857_Y + connect \Y $and$ls180.v:8870$2858_Y end - attribute \src "ls180.v:8887.7-8887.88" - cell $and $and$ls180.v:8887$2865 + attribute \src "ls180.v:8890.7-8890.88" + cell $and $and$ls180.v:8890$2865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263594,10 +266123,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8887$2865_Y + connect \Y $and$ls180.v:8890$2865_Y end - attribute \src "ls180.v:8888.8-8888.85" - cell $and $and$ls180.v:8888$2866 + attribute \src "ls180.v:8891.8-8891.85" + cell $and $and$ls180.v:8891$2866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263605,10 +266134,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8888$2866_Y + connect \Y $and$ls180.v:8891$2866_Y end - attribute \src "ls180.v:8896.8-8896.85" - cell $and $and$ls180.v:8896$2867 + attribute \src "ls180.v:8899.8-8899.85" + cell $and $and$ls180.v:8899$2867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263616,10 +266145,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8896$2867_Y + connect \Y $and$ls180.v:8899$2867_Y end - attribute \src "ls180.v:8952.7-8952.88" - cell $and $and$ls180.v:8952$2871 + attribute \src "ls180.v:8955.7-8955.88" + cell $and $and$ls180.v:8955$2871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263627,10 +266156,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8952$2871_Y + connect \Y $and$ls180.v:8955$2871_Y end - attribute \src "ls180.v:8959.8-8959.83" - cell $and $and$ls180.v:8959$2873 + attribute \src "ls180.v:8962.8-8962.83" + cell $and $and$ls180.v:8962$2873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263638,21 +266167,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8959$2873_Y + connect \Y $and$ls180.v:8962$2873_Y end - attribute \src "ls180.v:8959.7-8959.119" - cell $and $and$ls180.v:8959$2875 + attribute \src "ls180.v:8962.7-8962.119" + cell $and $and$ls180.v:8962$2875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8959$2873_Y - connect \B $not$ls180.v:8959$2874_Y - connect \Y $and$ls180.v:8959$2875_Y + connect \A $and$ls180.v:8962$2873_Y + connect \B $not$ls180.v:8962$2874_Y + connect \Y $and$ls180.v:8962$2875_Y end - attribute \src "ls180.v:8965.8-8965.83" - cell $and $and$ls180.v:8965$2878 + attribute \src "ls180.v:8968.8-8968.83" + cell $and $and$ls180.v:8968$2878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263660,21 +266189,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8965$2878_Y + connect \Y $and$ls180.v:8968$2878_Y end - attribute \src "ls180.v:8965.7-8965.119" - cell $and $and$ls180.v:8965$2880 + attribute \src "ls180.v:8968.7-8968.119" + cell $and $and$ls180.v:8968$2880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8965$2878_Y - connect \B $not$ls180.v:8965$2879_Y - connect \Y $and$ls180.v:8965$2880_Y + connect \A $and$ls180.v:8968$2878_Y + connect \B $not$ls180.v:8968$2879_Y + connect \Y $and$ls180.v:8968$2880_Y end - attribute \src "ls180.v:2927.30-2927.76" - cell $eq $eq$ls180.v:2927$54 + attribute \src "ls180.v:2930.30-2930.76" + cell $eq $eq$ls180.v:2930$54 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -263682,10 +266211,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_icp_sel connect \B 1'0 - connect \Y $eq$ls180.v:2927$54_Y + connect \Y $eq$ls180.v:2930$54_Y end - attribute \src "ls180.v:2934.11-2934.42" - cell $eq $eq$ls180.v:2934$59 + attribute \src "ls180.v:2937.11-2937.42" + cell $eq $eq$ls180.v:2937$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263693,10 +266222,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter0_counter connect \B 1'1 - connect \Y $eq$ls180.v:2934$59_Y + connect \Y $eq$ls180.v:2937$59_Y end - attribute \src "ls180.v:2987.30-2987.76" - cell $eq $eq$ls180.v:2987$65 + attribute \src "ls180.v:2990.30-2990.76" + cell $eq $eq$ls180.v:2990$65 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -263704,10 +266233,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_ics_sel connect \B 1'0 - connect \Y $eq$ls180.v:2987$65_Y + connect \Y $eq$ls180.v:2990$65_Y end - attribute \src "ls180.v:2994.11-2994.42" - cell $eq $eq$ls180.v:2994$70 + attribute \src "ls180.v:2997.11-2997.42" + cell $eq $eq$ls180.v:2997$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263715,10 +266244,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter1_counter connect \B 1'1 - connect \Y $eq$ls180.v:2994$70_Y + connect \Y $eq$ls180.v:2997$70_Y end - attribute \src "ls180.v:3047.33-3047.58" - cell $eq $eq$ls180.v:3047$76 + attribute \src "ls180.v:3050.33-3050.58" + cell $eq $eq$ls180.v:3050$76 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -263726,10 +266255,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_sel connect \B 1'0 - connect \Y $eq$ls180.v:3047$76_Y + connect \Y $eq$ls180.v:3050$76_Y end - attribute \src "ls180.v:3054.11-3054.45" - cell $eq $eq$ls180.v:3054$81 + attribute \src "ls180.v:3057.11-3057.45" + cell $eq $eq$ls180.v:3057$81 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263737,10 +266266,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $eq$ls180.v:3054$81_Y + connect \Y $eq$ls180.v:3057$81_Y end - attribute \src "ls180.v:3300.34-3300.65" - cell $eq $eq$ls180.v:3300$221 + attribute \src "ls180.v:3303.34-3303.65" + cell $eq $eq$ls180.v:3303$221 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -263748,10 +266277,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_count1 connect \B 1'0 - connect \Y $eq$ls180.v:3300$221_Y + connect \Y $eq$ls180.v:3303$221_Y end - attribute \src "ls180.v:3304.68-3304.102" - cell $eq $eq$ls180.v:3304$224 + attribute \src "ls180.v:3307.68-3307.102" + cell $eq $eq$ls180.v:3307$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263759,10 +266288,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $eq$ls180.v:3304$224_Y + connect \Y $eq$ls180.v:3307$224_Y end - attribute \src "ls180.v:3348.43-3348.134" - cell $eq $eq$ls180.v:3348$229 + attribute \src "ls180.v:3351.43-3351.134" + cell $eq $eq$ls180.v:3351$229 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -263770,10 +266299,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3348$229_Y + connect \Y $eq$ls180.v:3351$229_Y end - attribute \src "ls180.v:3365.47-3365.88" - cell $eq $eq$ls180.v:3365$242 + attribute \src "ls180.v:3368.47-3368.88" + cell $eq $eq$ls180.v:3368$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263781,10 +266310,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3365$242_Y + connect \Y $eq$ls180.v:3368$242_Y end - attribute \src "ls180.v:3505.43-3505.134" - cell $eq $eq$ls180.v:3505$259 + attribute \src "ls180.v:3508.43-3508.134" + cell $eq $eq$ls180.v:3508$259 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -263792,10 +266321,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3505$259_Y + connect \Y $eq$ls180.v:3508$259_Y end - attribute \src "ls180.v:3522.47-3522.88" - cell $eq $eq$ls180.v:3522$272 + attribute \src "ls180.v:3525.47-3525.88" + cell $eq $eq$ls180.v:3525$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263803,10 +266332,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3522$272_Y + connect \Y $eq$ls180.v:3525$272_Y end - attribute \src "ls180.v:3662.43-3662.134" - cell $eq $eq$ls180.v:3662$289 + attribute \src "ls180.v:3665.43-3665.134" + cell $eq $eq$ls180.v:3665$289 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -263814,10 +266343,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3662$289_Y + connect \Y $eq$ls180.v:3665$289_Y end - attribute \src "ls180.v:3679.47-3679.88" - cell $eq $eq$ls180.v:3679$302 + attribute \src "ls180.v:3682.47-3682.88" + cell $eq $eq$ls180.v:3682$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263825,10 +266354,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3679$302_Y + connect \Y $eq$ls180.v:3682$302_Y end - attribute \src "ls180.v:3819.43-3819.134" - cell $eq $eq$ls180.v:3819$319 + attribute \src "ls180.v:3822.43-3822.134" + cell $eq $eq$ls180.v:3822$319 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -263836,10 +266365,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3819$319_Y + connect \Y $eq$ls180.v:3822$319_Y end - attribute \src "ls180.v:3836.47-3836.88" - cell $eq $eq$ls180.v:3836$332 + attribute \src "ls180.v:3839.47-3839.88" + cell $eq $eq$ls180.v:3839$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263847,10 +266376,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3836$332_Y + connect \Y $eq$ls180.v:3839$332_Y end - attribute \src "ls180.v:3973.32-3973.56" - cell $eq $eq$ls180.v:3973$379 + attribute \src "ls180.v:3976.32-3976.56" + cell $eq $eq$ls180.v:3976$379 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -263858,10 +266387,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time0 connect \B 1'0 - connect \Y $eq$ls180.v:3973$379_Y + connect \Y $eq$ls180.v:3976$379_Y end - attribute \src "ls180.v:3974.32-3974.56" - cell $eq $eq$ls180.v:3974$380 + attribute \src "ls180.v:3977.32-3977.56" + cell $eq $eq$ls180.v:3977$380 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -263869,10 +266398,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time1 connect \B 1'0 - connect \Y $eq$ls180.v:3974$380_Y + connect \Y $eq$ls180.v:3977$380_Y end - attribute \src "ls180.v:3985.339-3985.418" - cell $eq $eq$ls180.v:3985$394 + attribute \src "ls180.v:3988.339-3988.418" + cell $eq $eq$ls180.v:3988$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263880,10 +266409,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3985$394_Y + connect \Y $eq$ls180.v:3988$394_Y end - attribute \src "ls180.v:3985.423-3985.504" - cell $eq $eq$ls180.v:3985$395 + attribute \src "ls180.v:3988.423-3988.504" + cell $eq $eq$ls180.v:3988$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263891,10 +266420,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3985$395_Y + connect \Y $eq$ls180.v:3988$395_Y end - attribute \src "ls180.v:3986.339-3986.418" - cell $eq $eq$ls180.v:3986$407 + attribute \src "ls180.v:3989.339-3989.418" + cell $eq $eq$ls180.v:3989$407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263902,10 +266431,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3986$407_Y + connect \Y $eq$ls180.v:3989$407_Y end - attribute \src "ls180.v:3986.423-3986.504" - cell $eq $eq$ls180.v:3986$408 + attribute \src "ls180.v:3989.423-3989.504" + cell $eq $eq$ls180.v:3989$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263913,10 +266442,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3986$408_Y + connect \Y $eq$ls180.v:3989$408_Y end - attribute \src "ls180.v:3987.339-3987.418" - cell $eq $eq$ls180.v:3987$420 + attribute \src "ls180.v:3990.339-3990.418" + cell $eq $eq$ls180.v:3990$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263924,10 +266453,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3987$420_Y + connect \Y $eq$ls180.v:3990$420_Y end - attribute \src "ls180.v:3987.423-3987.504" - cell $eq $eq$ls180.v:3987$421 + attribute \src "ls180.v:3990.423-3990.504" + cell $eq $eq$ls180.v:3990$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263935,10 +266464,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3987$421_Y + connect \Y $eq$ls180.v:3990$421_Y end - attribute \src "ls180.v:3988.339-3988.418" - cell $eq $eq$ls180.v:3988$433 + attribute \src "ls180.v:3991.339-3991.418" + cell $eq $eq$ls180.v:3991$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263946,10 +266475,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3988$433_Y + connect \Y $eq$ls180.v:3991$433_Y end - attribute \src "ls180.v:3988.423-3988.504" - cell $eq $eq$ls180.v:3988$434 + attribute \src "ls180.v:3991.423-3991.504" + cell $eq $eq$ls180.v:3991$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263957,10 +266486,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3988$434_Y + connect \Y $eq$ls180.v:3991$434_Y end - attribute \src "ls180.v:4018.339-4018.418" - cell $eq $eq$ls180.v:4018$452 + attribute \src "ls180.v:4021.339-4021.418" + cell $eq $eq$ls180.v:4021$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263968,10 +266497,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4018$452_Y + connect \Y $eq$ls180.v:4021$452_Y end - attribute \src "ls180.v:4018.423-4018.504" - cell $eq $eq$ls180.v:4018$453 + attribute \src "ls180.v:4021.423-4021.504" + cell $eq $eq$ls180.v:4021$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263979,10 +266508,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4018$453_Y + connect \Y $eq$ls180.v:4021$453_Y end - attribute \src "ls180.v:4019.339-4019.418" - cell $eq $eq$ls180.v:4019$465 + attribute \src "ls180.v:4022.339-4022.418" + cell $eq $eq$ls180.v:4022$465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263990,10 +266519,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4019$465_Y + connect \Y $eq$ls180.v:4022$465_Y end - attribute \src "ls180.v:4019.423-4019.504" - cell $eq $eq$ls180.v:4019$466 + attribute \src "ls180.v:4022.423-4022.504" + cell $eq $eq$ls180.v:4022$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264001,10 +266530,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4019$466_Y + connect \Y $eq$ls180.v:4022$466_Y end - attribute \src "ls180.v:4020.339-4020.418" - cell $eq $eq$ls180.v:4020$478 + attribute \src "ls180.v:4023.339-4023.418" + cell $eq $eq$ls180.v:4023$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264012,10 +266541,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4020$478_Y + connect \Y $eq$ls180.v:4023$478_Y end - attribute \src "ls180.v:4020.423-4020.504" - cell $eq $eq$ls180.v:4020$479 + attribute \src "ls180.v:4023.423-4023.504" + cell $eq $eq$ls180.v:4023$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264023,10 +266552,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4020$479_Y + connect \Y $eq$ls180.v:4023$479_Y end - attribute \src "ls180.v:4021.339-4021.418" - cell $eq $eq$ls180.v:4021$491 + attribute \src "ls180.v:4024.339-4024.418" + cell $eq $eq$ls180.v:4024$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264034,10 +266563,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4021$491_Y + connect \Y $eq$ls180.v:4024$491_Y end - attribute \src "ls180.v:4021.423-4021.504" - cell $eq $eq$ls180.v:4021$492 + attribute \src "ls180.v:4024.423-4024.504" + cell $eq $eq$ls180.v:4024$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264045,10 +266574,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4021$492_Y + connect \Y $eq$ls180.v:4024$492_Y end - attribute \src "ls180.v:4050.78-4050.113" - cell $eq $eq$ls180.v:4050$501 + attribute \src "ls180.v:4053.78-4053.113" + cell $eq $eq$ls180.v:4053$501 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264056,10 +266585,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'0 - connect \Y $eq$ls180.v:4050$501_Y + connect \Y $eq$ls180.v:4053$501_Y end - attribute \src "ls180.v:4053.78-4053.113" - cell $eq $eq$ls180.v:4053$504 + attribute \src "ls180.v:4056.78-4056.113" + cell $eq $eq$ls180.v:4056$504 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264067,10 +266596,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'0 - connect \Y $eq$ls180.v:4053$504_Y + connect \Y $eq$ls180.v:4056$504_Y end - attribute \src "ls180.v:4059.78-4059.113" - cell $eq $eq$ls180.v:4059$508 + attribute \src "ls180.v:4062.78-4062.113" + cell $eq $eq$ls180.v:4062$508 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264078,10 +266607,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'1 - connect \Y $eq$ls180.v:4059$508_Y + connect \Y $eq$ls180.v:4062$508_Y end - attribute \src "ls180.v:4062.78-4062.113" - cell $eq $eq$ls180.v:4062$511 + attribute \src "ls180.v:4065.78-4065.113" + cell $eq $eq$ls180.v:4065$511 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264089,10 +266618,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'1 - connect \Y $eq$ls180.v:4062$511_Y + connect \Y $eq$ls180.v:4065$511_Y end - attribute \src "ls180.v:4068.78-4068.113" - cell $eq $eq$ls180.v:4068$515 + attribute \src "ls180.v:4071.78-4071.113" + cell $eq $eq$ls180.v:4071$515 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264100,10 +266629,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'10 - connect \Y $eq$ls180.v:4068$515_Y + connect \Y $eq$ls180.v:4071$515_Y end - attribute \src "ls180.v:4071.78-4071.113" - cell $eq $eq$ls180.v:4071$518 + attribute \src "ls180.v:4074.78-4074.113" + cell $eq $eq$ls180.v:4074$518 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264111,10 +266640,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'10 - connect \Y $eq$ls180.v:4071$518_Y + connect \Y $eq$ls180.v:4074$518_Y end - attribute \src "ls180.v:4077.78-4077.113" - cell $eq $eq$ls180.v:4077$522 + attribute \src "ls180.v:4080.78-4080.113" + cell $eq $eq$ls180.v:4080$522 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264122,10 +266651,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'11 - connect \Y $eq$ls180.v:4077$522_Y + connect \Y $eq$ls180.v:4080$522_Y end - attribute \src "ls180.v:4080.78-4080.113" - cell $eq $eq$ls180.v:4080$525 + attribute \src "ls180.v:4083.78-4083.113" + cell $eq $eq$ls180.v:4083$525 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264133,10 +266662,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'11 - connect \Y $eq$ls180.v:4080$525_Y + connect \Y $eq$ls180.v:4083$525_Y end - attribute \src "ls180.v:4161.42-4161.82" - cell $eq $eq$ls180.v:4161$548 + attribute \src "ls180.v:4164.42-4164.82" + cell $eq $eq$ls180.v:4164$548 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264144,10 +266673,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4161$548_Y + connect \Y $eq$ls180.v:4164$548_Y end - attribute \src "ls180.v:4161.145-4161.178" - cell $eq $eq$ls180.v:4161$549 + attribute \src "ls180.v:4164.145-4164.178" + cell $eq $eq$ls180.v:4164$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264155,10 +266684,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4161$549_Y + connect \Y $eq$ls180.v:4164$549_Y end - attribute \src "ls180.v:4161.220-4161.253" - cell $eq $eq$ls180.v:4161$552 + attribute \src "ls180.v:4164.220-4164.253" + cell $eq $eq$ls180.v:4164$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264166,10 +266695,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4161$552_Y + connect \Y $eq$ls180.v:4164$552_Y end - attribute \src "ls180.v:4161.295-4161.328" - cell $eq $eq$ls180.v:4161$555 + attribute \src "ls180.v:4164.295-4164.328" + cell $eq $eq$ls180.v:4164$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264177,10 +266706,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4161$555_Y + connect \Y $eq$ls180.v:4164$555_Y end - attribute \src "ls180.v:4166.42-4166.82" - cell $eq $eq$ls180.v:4166$564 + attribute \src "ls180.v:4169.42-4169.82" + cell $eq $eq$ls180.v:4169$564 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264188,10 +266717,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4166$564_Y + connect \Y $eq$ls180.v:4169$564_Y end - attribute \src "ls180.v:4166.145-4166.178" - cell $eq $eq$ls180.v:4166$565 + attribute \src "ls180.v:4169.145-4169.178" + cell $eq $eq$ls180.v:4169$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264199,10 +266728,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4166$565_Y + connect \Y $eq$ls180.v:4169$565_Y end - attribute \src "ls180.v:4166.220-4166.253" - cell $eq $eq$ls180.v:4166$568 + attribute \src "ls180.v:4169.220-4169.253" + cell $eq $eq$ls180.v:4169$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264210,10 +266739,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4166$568_Y + connect \Y $eq$ls180.v:4169$568_Y end - attribute \src "ls180.v:4166.295-4166.328" - cell $eq $eq$ls180.v:4166$571 + attribute \src "ls180.v:4169.295-4169.328" + cell $eq $eq$ls180.v:4169$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264221,10 +266750,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4166$571_Y + connect \Y $eq$ls180.v:4169$571_Y end - attribute \src "ls180.v:4171.42-4171.82" - cell $eq $eq$ls180.v:4171$580 + attribute \src "ls180.v:4174.42-4174.82" + cell $eq $eq$ls180.v:4174$580 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264232,10 +266761,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4171$580_Y + connect \Y $eq$ls180.v:4174$580_Y end - attribute \src "ls180.v:4171.145-4171.178" - cell $eq $eq$ls180.v:4171$581 + attribute \src "ls180.v:4174.145-4174.178" + cell $eq $eq$ls180.v:4174$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264243,10 +266772,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4171$581_Y + connect \Y $eq$ls180.v:4174$581_Y end - attribute \src "ls180.v:4171.220-4171.253" - cell $eq $eq$ls180.v:4171$584 + attribute \src "ls180.v:4174.220-4174.253" + cell $eq $eq$ls180.v:4174$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264254,10 +266783,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4171$584_Y + connect \Y $eq$ls180.v:4174$584_Y end - attribute \src "ls180.v:4171.295-4171.328" - cell $eq $eq$ls180.v:4171$587 + attribute \src "ls180.v:4174.295-4174.328" + cell $eq $eq$ls180.v:4174$587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264265,10 +266794,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4171$587_Y + connect \Y $eq$ls180.v:4174$587_Y end - attribute \src "ls180.v:4176.42-4176.82" - cell $eq $eq$ls180.v:4176$596 + attribute \src "ls180.v:4179.42-4179.82" + cell $eq $eq$ls180.v:4179$596 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264276,10 +266805,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4176$596_Y + connect \Y $eq$ls180.v:4179$596_Y end - attribute \src "ls180.v:4176.145-4176.178" - cell $eq $eq$ls180.v:4176$597 + attribute \src "ls180.v:4179.145-4179.178" + cell $eq $eq$ls180.v:4179$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264287,10 +266816,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4176$597_Y + connect \Y $eq$ls180.v:4179$597_Y end - attribute \src "ls180.v:4176.220-4176.253" - cell $eq $eq$ls180.v:4176$600 + attribute \src "ls180.v:4179.220-4179.253" + cell $eq $eq$ls180.v:4179$600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264298,10 +266827,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4176$600_Y + connect \Y $eq$ls180.v:4179$600_Y end - attribute \src "ls180.v:4176.295-4176.328" - cell $eq $eq$ls180.v:4176$603 + attribute \src "ls180.v:4179.295-4179.328" + cell $eq $eq$ls180.v:4179$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264309,10 +266838,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4176$603_Y + connect \Y $eq$ls180.v:4179$603_Y end - attribute \src "ls180.v:4181.44-4181.77" - cell $eq $eq$ls180.v:4181$612 + attribute \src "ls180.v:4184.44-4184.77" + cell $eq $eq$ls180.v:4184$612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264320,10 +266849,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$612_Y + connect \Y $eq$ls180.v:4184$612_Y end - attribute \src "ls180.v:4181.83-4181.123" - cell $eq $eq$ls180.v:4181$613 + attribute \src "ls180.v:4184.83-4184.123" + cell $eq $eq$ls180.v:4184$613 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264331,10 +266860,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4181$613_Y + connect \Y $eq$ls180.v:4184$613_Y end - attribute \src "ls180.v:4181.186-4181.219" - cell $eq $eq$ls180.v:4181$614 + attribute \src "ls180.v:4184.186-4184.219" + cell $eq $eq$ls180.v:4184$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264342,10 +266871,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$614_Y + connect \Y $eq$ls180.v:4184$614_Y end - attribute \src "ls180.v:4181.261-4181.294" - cell $eq $eq$ls180.v:4181$617 + attribute \src "ls180.v:4184.261-4184.294" + cell $eq $eq$ls180.v:4184$617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264353,10 +266882,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$617_Y + connect \Y $eq$ls180.v:4184$617_Y end - attribute \src "ls180.v:4181.336-4181.369" - cell $eq $eq$ls180.v:4181$620 + attribute \src "ls180.v:4184.336-4184.369" + cell $eq $eq$ls180.v:4184$620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264364,10 +266893,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$620_Y + connect \Y $eq$ls180.v:4184$620_Y end - attribute \src "ls180.v:4181.418-4181.451" - cell $eq $eq$ls180.v:4181$628 + attribute \src "ls180.v:4184.418-4184.451" + cell $eq $eq$ls180.v:4184$628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264375,10 +266904,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$628_Y + connect \Y $eq$ls180.v:4184$628_Y end - attribute \src "ls180.v:4181.457-4181.497" - cell $eq $eq$ls180.v:4181$629 + attribute \src "ls180.v:4184.457-4184.497" + cell $eq $eq$ls180.v:4184$629 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264386,10 +266915,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4181$629_Y + connect \Y $eq$ls180.v:4184$629_Y end - attribute \src "ls180.v:4181.560-4181.593" - cell $eq $eq$ls180.v:4181$630 + attribute \src "ls180.v:4184.560-4184.593" + cell $eq $eq$ls180.v:4184$630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264397,10 +266926,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$630_Y + connect \Y $eq$ls180.v:4184$630_Y end - attribute \src "ls180.v:4181.635-4181.668" - cell $eq $eq$ls180.v:4181$633 + attribute \src "ls180.v:4184.635-4184.668" + cell $eq $eq$ls180.v:4184$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264408,10 +266937,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$633_Y + connect \Y $eq$ls180.v:4184$633_Y end - attribute \src "ls180.v:4181.710-4181.743" - cell $eq $eq$ls180.v:4181$636 + attribute \src "ls180.v:4184.710-4184.743" + cell $eq $eq$ls180.v:4184$636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264419,10 +266948,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$636_Y + connect \Y $eq$ls180.v:4184$636_Y end - attribute \src "ls180.v:4181.792-4181.825" - cell $eq $eq$ls180.v:4181$644 + attribute \src "ls180.v:4184.792-4184.825" + cell $eq $eq$ls180.v:4184$644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264430,10 +266959,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$644_Y + connect \Y $eq$ls180.v:4184$644_Y end - attribute \src "ls180.v:4181.831-4181.871" - cell $eq $eq$ls180.v:4181$645 + attribute \src "ls180.v:4184.831-4184.871" + cell $eq $eq$ls180.v:4184$645 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264441,10 +266970,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4181$645_Y + connect \Y $eq$ls180.v:4184$645_Y end - attribute \src "ls180.v:4181.934-4181.967" - cell $eq $eq$ls180.v:4181$646 + attribute \src "ls180.v:4184.934-4184.967" + cell $eq $eq$ls180.v:4184$646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264452,10 +266981,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$646_Y + connect \Y $eq$ls180.v:4184$646_Y end - attribute \src "ls180.v:4181.1009-4181.1042" - cell $eq $eq$ls180.v:4181$649 + attribute \src "ls180.v:4184.1009-4184.1042" + cell $eq $eq$ls180.v:4184$649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264463,10 +266992,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$649_Y + connect \Y $eq$ls180.v:4184$649_Y end - attribute \src "ls180.v:4181.1084-4181.1117" - cell $eq $eq$ls180.v:4181$652 + attribute \src "ls180.v:4184.1084-4184.1117" + cell $eq $eq$ls180.v:4184$652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264474,10 +267003,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$652_Y + connect \Y $eq$ls180.v:4184$652_Y end - attribute \src "ls180.v:4181.1166-4181.1199" - cell $eq $eq$ls180.v:4181$660 + attribute \src "ls180.v:4184.1166-4184.1199" + cell $eq $eq$ls180.v:4184$660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264485,10 +267014,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$660_Y + connect \Y $eq$ls180.v:4184$660_Y end - attribute \src "ls180.v:4181.1205-4181.1245" - cell $eq $eq$ls180.v:4181$661 + attribute \src "ls180.v:4184.1205-4184.1245" + cell $eq $eq$ls180.v:4184$661 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264496,10 +267025,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4181$661_Y + connect \Y $eq$ls180.v:4184$661_Y end - attribute \src "ls180.v:4181.1308-4181.1341" - cell $eq $eq$ls180.v:4181$662 + attribute \src "ls180.v:4184.1308-4184.1341" + cell $eq $eq$ls180.v:4184$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264507,10 +267036,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$662_Y + connect \Y $eq$ls180.v:4184$662_Y end - attribute \src "ls180.v:4181.1383-4181.1416" - cell $eq $eq$ls180.v:4181$665 + attribute \src "ls180.v:4184.1383-4184.1416" + cell $eq $eq$ls180.v:4184$665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264518,10 +267047,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$665_Y + connect \Y $eq$ls180.v:4184$665_Y end - attribute \src "ls180.v:4181.1458-4181.1491" - cell $eq $eq$ls180.v:4181$668 + attribute \src "ls180.v:4184.1458-4184.1491" + cell $eq $eq$ls180.v:4184$668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264529,10 +267058,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4181$668_Y + connect \Y $eq$ls180.v:4184$668_Y end - attribute \src "ls180.v:4240.29-4240.57" - cell $eq $eq$ls180.v:4240$681 + attribute \src "ls180.v:4243.29-4243.57" + cell $eq $eq$ls180.v:4243$681 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264540,10 +267069,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_sel connect \B 1'0 - connect \Y $eq$ls180.v:4240$681_Y + connect \Y $eq$ls180.v:4243$681_Y end - attribute \src "ls180.v:4247.11-4247.41" - cell $eq $eq$ls180.v:4247$686 + attribute \src "ls180.v:4250.11-4250.41" + cell $eq $eq$ls180.v:4250$686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264551,76 +267080,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $eq$ls180.v:4247$686_Y + connect \Y $eq$ls180.v:4250$686_Y end - attribute \src "ls180.v:4415.37-4415.111" - cell $eq $eq$ls180.v:4415$753 + attribute \src "ls180.v:4418.37-4418.111" + cell $eq $eq$ls180.v:4418$753 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4415$752_Y - connect \Y $eq$ls180.v:4415$753_Y + connect \B $sub$ls180.v:4418$752_Y + connect \Y $eq$ls180.v:4418$753_Y end - attribute \src "ls180.v:4416.37-4416.105" - cell $eq $eq$ls180.v:4416$755 + attribute \src "ls180.v:4419.37-4419.105" + cell $eq $eq$ls180.v:4419$755 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4416$754_Y - connect \Y $eq$ls180.v:4416$755_Y + connect \B $sub$ls180.v:4419$754_Y + connect \Y $eq$ls180.v:4419$755_Y end - attribute \src "ls180.v:4443.10-4443.67" - cell $eq $eq$ls180.v:4443$759 + attribute \src "ls180.v:4446.10-4446.67" + cell $eq $eq$ls180.v:4446$759 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4443$758_Y - connect \Y $eq$ls180.v:4443$759_Y + connect \B $sub$ls180.v:4446$758_Y + connect \Y $eq$ls180.v:4446$759_Y end - attribute \src "ls180.v:4473.35-4473.108" - cell $eq $eq$ls180.v:4473$761 + attribute \src "ls180.v:4476.35-4476.108" + cell $eq $eq$ls180.v:4476$761 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4473$760_Y - connect \Y $eq$ls180.v:4473$761_Y + connect \B $sub$ls180.v:4476$760_Y + connect \Y $eq$ls180.v:4476$761_Y end - attribute \src "ls180.v:4474.35-4474.102" - cell $eq $eq$ls180.v:4474$763 + attribute \src "ls180.v:4477.35-4477.102" + cell $eq $eq$ls180.v:4477$763 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4474$762_Y - connect \Y $eq$ls180.v:4474$763_Y + connect \B $sub$ls180.v:4477$762_Y + connect \Y $eq$ls180.v:4477$763_Y end - attribute \src "ls180.v:4502.10-4502.65" - cell $eq $eq$ls180.v:4502$767 + attribute \src "ls180.v:4505.10-4505.65" + cell $eq $eq$ls180.v:4505$767 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4502$766_Y - connect \Y $eq$ls180.v:4502$767_Y + connect \B $sub$ls180.v:4505$766_Y + connect \Y $eq$ls180.v:4505$767_Y end - attribute \src "ls180.v:4606.10-4606.40" - cell $eq $eq$ls180.v:4606$794 + attribute \src "ls180.v:4609.10-4609.40" + cell $eq $eq$ls180.v:4609$794 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -264628,10 +267157,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_count connect \B 7'1001111 - connect \Y $eq$ls180.v:4606$794_Y + connect \Y $eq$ls180.v:4609$794_Y end - attribute \src "ls180.v:4663.10-4663.39" - cell $eq $eq$ls180.v:4663$797 + attribute \src "ls180.v:4666.10-4666.39" + cell $eq $eq$ls180.v:4666$797 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -264639,10 +267168,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4663$797_Y + connect \Y $eq$ls180.v:4666$797_Y end - attribute \src "ls180.v:4680.10-4680.39" - cell $eq $eq$ls180.v:4680$799 + attribute \src "ls180.v:4683.10-4683.39" + cell $eq $eq$ls180.v:4683$799 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -264650,10 +267179,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4680$799_Y + connect \Y $eq$ls180.v:4683$799_Y end - attribute \src "ls180.v:4708.38-4708.88" - cell $eq $eq$ls180.v:4708$801 + attribute \src "ls180.v:4711.38-4711.88" + cell $eq $eq$ls180.v:4711$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264661,10 +267190,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \B 1'0 - connect \Y $eq$ls180.v:4708$801_Y + connect \Y $eq$ls180.v:4711$801_Y end - attribute \src "ls180.v:4758.9-4758.40" - cell $eq $eq$ls180.v:4758$811 + attribute \src "ls180.v:4761.9-4761.40" + cell $eq $eq$ls180.v:4761$811 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -264672,21 +267201,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4758$811_Y + connect \Y $eq$ls180.v:4761$811_Y end - attribute \src "ls180.v:4767.36-4767.105" - cell $eq $eq$ls180.v:4767$813 + attribute \src "ls180.v:4770.36-4770.105" + cell $eq $eq$ls180.v:4770$813 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4767$812_Y - connect \Y $eq$ls180.v:4767$813_Y + connect \B $sub$ls180.v:4770$812_Y + connect \Y $eq$ls180.v:4770$813_Y end - attribute \src "ls180.v:4786.9-4786.40" - cell $eq $eq$ls180.v:4786$817 + attribute \src "ls180.v:4789.9-4789.40" + cell $eq $eq$ls180.v:4789$817 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -264694,10 +267223,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4786$817_Y + connect \Y $eq$ls180.v:4789$817_Y end - attribute \src "ls180.v:4798.10-4798.39" - cell $eq $eq$ls180.v:4798$819 + attribute \src "ls180.v:4801.10-4801.39" + cell $eq $eq$ls180.v:4801$819 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -264705,10 +267234,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count connect \B 3'111 - connect \Y $eq$ls180.v:4798$819_Y + connect \Y $eq$ls180.v:4801$819_Y end - attribute \src "ls180.v:4835.39-4835.94" - cell $eq $eq$ls180.v:4835$823 + attribute \src "ls180.v:4838.39-4838.94" + cell $eq $eq$ls180.v:4838$823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264716,10 +267245,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \B 1'0 - connect \Y $eq$ls180.v:4835$823_Y + connect \Y $eq$ls180.v:4838$823_Y end - attribute \src "ls180.v:4872.32-4872.89" - cell $eq $eq$ls180.v:4872$832 + attribute \src "ls180.v:4875.32-4875.89" + cell $eq $eq$ls180.v:4875$832 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -264727,10 +267256,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $eq$ls180.v:4872$832_Y + connect \Y $eq$ls180.v:4875$832_Y end - attribute \src "ls180.v:4920.10-4920.40" - cell $eq $eq$ls180.v:4920$836 + attribute \src "ls180.v:4923.10-4923.40" + cell $eq $eq$ls180.v:4923$836 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -264738,10 +267267,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $eq$ls180.v:4920$836_Y + connect \Y $eq$ls180.v:4923$836_Y end - attribute \src "ls180.v:4969.40-4969.98" - cell $eq $eq$ls180.v:4969$838 + attribute \src "ls180.v:4972.40-4972.98" + cell $eq $eq$ls180.v:4972$838 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -264749,10 +267278,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_payload_data_i connect \B 1'0 - connect \Y $eq$ls180.v:4969$838_Y + connect \Y $eq$ls180.v:4972$838_Y end - attribute \src "ls180.v:5020.9-5020.41" - cell $eq $eq$ls180.v:5020$848 + attribute \src "ls180.v:5023.9-5023.41" + cell $eq $eq$ls180.v:5023$848 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -264760,21 +267289,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:5020$848_Y + connect \Y $eq$ls180.v:5023$848_Y end - attribute \src "ls180.v:5029.37-5029.123" - cell $eq $eq$ls180.v:5029$851 + attribute \src "ls180.v:5032.37-5032.123" + cell $eq $eq$ls180.v:5032$851 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:5029$850_Y - connect \Y $eq$ls180.v:5029$851_Y + connect \B $sub$ls180.v:5032$850_Y + connect \Y $eq$ls180.v:5032$851_Y end - attribute \src "ls180.v:5052.9-5052.41" - cell $eq $eq$ls180.v:5052$854 + attribute \src "ls180.v:5055.9-5055.41" + cell $eq $eq$ls180.v:5055$854 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -264782,10 +267311,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:5052$854_Y + connect \Y $eq$ls180.v:5055$854_Y end - attribute \src "ls180.v:5062.10-5062.41" - cell $eq $eq$ls180.v:5062$856 + attribute \src "ls180.v:5065.10-5065.41" + cell $eq $eq$ls180.v:5065$856 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -264793,10 +267322,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count connect \B 6'100111 - connect \Y $eq$ls180.v:5062$856_Y + connect \Y $eq$ls180.v:5065$856_Y end - attribute \src "ls180.v:5231.9-5231.47" - cell $eq $eq$ls180.v:5231$1038 + attribute \src "ls180.v:5234.9-5234.47" + cell $eq $eq$ls180.v:5234$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -264804,10 +267333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5231$1038_Y + connect \Y $eq$ls180.v:5234$1038_Y end - attribute \src "ls180.v:5261.10-5261.48" - cell $eq $eq$ls180.v:5261$1039 + attribute \src "ls180.v:5264.10-5264.48" + cell $eq $eq$ls180.v:5264$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -264815,10 +267344,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5261$1039_Y + connect \Y $eq$ls180.v:5264$1039_Y end - attribute \src "ls180.v:5292.10-5292.78" - cell $eq $eq$ls180.v:5292$1044 + attribute \src "ls180.v:5295.10-5295.78" + cell $eq $eq$ls180.v:5295$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -264826,10 +267355,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo0 connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5292$1044_Y + connect \Y $eq$ls180.v:5295$1044_Y end - attribute \src "ls180.v:5292.83-5292.151" - cell $eq $eq$ls180.v:5292$1045 + attribute \src "ls180.v:5295.83-5295.151" + cell $eq $eq$ls180.v:5295$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -264837,10 +267366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo1 connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5292$1045_Y + connect \Y $eq$ls180.v:5295$1045_Y end - attribute \src "ls180.v:5292.157-5292.225" - cell $eq $eq$ls180.v:5292$1047 + attribute \src "ls180.v:5295.157-5295.225" + cell $eq $eq$ls180.v:5295$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -264848,10 +267377,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo2 connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5292$1047_Y + connect \Y $eq$ls180.v:5295$1047_Y end - attribute \src "ls180.v:5292.231-5292.299" - cell $eq $eq$ls180.v:5292$1049 + attribute \src "ls180.v:5295.231-5295.299" + cell $eq $eq$ls180.v:5295$1049 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -264859,10 +267388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo3 connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5292$1049_Y + connect \Y $eq$ls180.v:5295$1049_Y end - attribute \src "ls180.v:5300.7-5300.44" - cell $eq $eq$ls180.v:5300$1053 + attribute \src "ls180.v:5303.7-5303.44" + cell $eq $eq$ls180.v:5303$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -264870,10 +267399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5300$1053_Y + connect \Y $eq$ls180.v:5303$1053_Y end - attribute \src "ls180.v:5310.7-5310.44" - cell $eq $eq$ls180.v:5310$1056 + attribute \src "ls180.v:5313.7-5313.44" + cell $eq $eq$ls180.v:5313$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -264881,10 +267410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5310$1056_Y + connect \Y $eq$ls180.v:5313$1056_Y end - attribute \src "ls180.v:5320.7-5320.44" - cell $eq $eq$ls180.v:5320$1059 + attribute \src "ls180.v:5323.7-5323.44" + cell $eq $eq$ls180.v:5323$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -264892,10 +267421,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5320$1059_Y + connect \Y $eq$ls180.v:5323$1059_Y end - attribute \src "ls180.v:5330.7-5330.44" - cell $eq $eq$ls180.v:5330$1062 + attribute \src "ls180.v:5333.7-5333.44" + cell $eq $eq$ls180.v:5333$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -264903,10 +267432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5330$1062_Y + connect \Y $eq$ls180.v:5333$1062_Y end - attribute \src "ls180.v:5454.36-5454.64" - cell $eq $eq$ls180.v:5454$1113 + attribute \src "ls180.v:5457.36-5457.64" + cell $eq $eq$ls180.v:5457$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264914,10 +267443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5454$1113_Y + connect \Y $eq$ls180.v:5457$1113_Y end - attribute \src "ls180.v:5460.10-5460.39" - cell $eq $eq$ls180.v:5460$1116 + attribute \src "ls180.v:5463.10-5463.39" + cell $eq $eq$ls180.v:5463$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -264925,10 +267454,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_count connect \B 3'101 - connect \Y $eq$ls180.v:5460$1116_Y + connect \Y $eq$ls180.v:5463$1116_Y end - attribute \src "ls180.v:5461.11-5461.39" - cell $eq $eq$ls180.v:5461$1117 + attribute \src "ls180.v:5464.11-5464.39" + cell $eq $eq$ls180.v:5464$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264936,10 +267465,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5461$1117_Y + connect \Y $eq$ls180.v:5464$1117_Y end - attribute \src "ls180.v:5473.34-5473.63" - cell $eq $eq$ls180.v:5473$1118 + attribute \src "ls180.v:5476.34-5476.63" + cell $eq $eq$ls180.v:5476$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264947,10 +267476,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'0 - connect \Y $eq$ls180.v:5473$1118_Y + connect \Y $eq$ls180.v:5476$1118_Y end - attribute \src "ls180.v:5474.9-5474.37" - cell $eq $eq$ls180.v:5474$1119 + attribute \src "ls180.v:5477.9-5477.37" + cell $eq $eq$ls180.v:5477$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264958,10 +267487,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 2'10 - connect \Y $eq$ls180.v:5474$1119_Y + connect \Y $eq$ls180.v:5477$1119_Y end - attribute \src "ls180.v:5481.10-5481.55" - cell $eq $eq$ls180.v:5481$1120 + attribute \src "ls180.v:5484.10-5484.55" + cell $eq $eq$ls180.v:5484$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -264969,10 +267498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5481$1120_Y + connect \Y $eq$ls180.v:5484$1120_Y end - attribute \src "ls180.v:5487.12-5487.41" - cell $eq $eq$ls180.v:5487$1121 + attribute \src "ls180.v:5490.12-5490.41" + cell $eq $eq$ls180.v:5490$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264980,10 +267509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 2'10 - connect \Y $eq$ls180.v:5487$1121_Y + connect \Y $eq$ls180.v:5490$1121_Y end - attribute \src "ls180.v:5490.13-5490.42" - cell $eq $eq$ls180.v:5490$1122 + attribute \src "ls180.v:5493.13-5493.42" + cell $eq $eq$ls180.v:5493$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -264991,32 +267520,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'1 - connect \Y $eq$ls180.v:5490$1122_Y + connect \Y $eq$ls180.v:5493$1122_Y end - attribute \src "ls180.v:5512.10-5512.76" - cell $eq $eq$ls180.v:5512$1127 + attribute \src "ls180.v:5515.10-5515.76" + cell $eq $eq$ls180.v:5515$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5512$1126_Y - connect \Y $eq$ls180.v:5512$1127_Y + connect \B $sub$ls180.v:5515$1126_Y + connect \Y $eq$ls180.v:5515$1127_Y end - attribute \src "ls180.v:5527.35-5527.101" - cell $eq $eq$ls180.v:5527$1130 + attribute \src "ls180.v:5530.35-5530.101" + cell $eq $eq$ls180.v:5530$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5527$1129_Y - connect \Y $eq$ls180.v:5527$1130_Y + connect \B $sub$ls180.v:5530$1129_Y + connect \Y $eq$ls180.v:5530$1130_Y end - attribute \src "ls180.v:5529.10-5529.56" - cell $eq $eq$ls180.v:5529$1131 + attribute \src "ls180.v:5532.10-5532.56" + cell $eq $eq$ls180.v:5532$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265024,21 +267553,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'0 - connect \Y $eq$ls180.v:5529$1131_Y + connect \Y $eq$ls180.v:5532$1131_Y end - attribute \src "ls180.v:5538.12-5538.78" - cell $eq $eq$ls180.v:5538$1135 + attribute \src "ls180.v:5541.12-5541.78" + cell $eq $eq$ls180.v:5541$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5538$1134_Y - connect \Y $eq$ls180.v:5538$1135_Y + connect \B $sub$ls180.v:5541$1134_Y + connect \Y $eq$ls180.v:5541$1135_Y end - attribute \src "ls180.v:5545.11-5545.57" - cell $eq $eq$ls180.v:5545$1136 + attribute \src "ls180.v:5548.11-5548.57" + cell $eq $eq$ls180.v:5548$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265046,32 +267575,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5545$1136_Y + connect \Y $eq$ls180.v:5548$1136_Y end - attribute \src "ls180.v:5662.10-5662.105" - cell $eq $eq$ls180.v:5662$1153 + attribute \src "ls180.v:5665.10-5665.105" + cell $eq $eq$ls180.v:5665$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5662$1152_Y - connect \Y $eq$ls180.v:5662$1153_Y + connect \B $sub$ls180.v:5665$1152_Y + connect \Y $eq$ls180.v:5665$1153_Y end - attribute \src "ls180.v:5752.39-5752.106" - cell $eq $eq$ls180.v:5752$1159 + attribute \src "ls180.v:5755.39-5755.106" + cell $eq $eq$ls180.v:5755$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5752$1158_Y - connect \Y $eq$ls180.v:5752$1159_Y + connect \B $sub$ls180.v:5755$1158_Y + connect \Y $eq$ls180.v:5755$1159_Y end - attribute \src "ls180.v:5782.44-5782.82" - cell $eq $eq$ls180.v:5782$1162 + attribute \src "ls180.v:5785.44-5785.82" + cell $eq $eq$ls180.v:5785$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265079,10 +267608,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 1'0 - connect \Y $eq$ls180.v:5782$1162_Y + connect \Y $eq$ls180.v:5785$1162_Y end - attribute \src "ls180.v:5783.43-5783.81" - cell $eq $eq$ls180.v:5783$1163 + attribute \src "ls180.v:5786.43-5786.81" + cell $eq $eq$ls180.v:5786$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265090,10 +267619,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 3'111 - connect \Y $eq$ls180.v:5783$1163_Y + connect \Y $eq$ls180.v:5786$1163_Y end - attribute \src "ls180.v:5895.68-5895.89" - cell $eq $eq$ls180.v:5895$1179 + attribute \src "ls180.v:5898.68-5898.89" + cell $eq $eq$ls180.v:5898$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265101,10 +267630,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5895$1179_Y + connect \Y $eq$ls180.v:5898$1179_Y end - attribute \src "ls180.v:5896.68-5896.89" - cell $eq $eq$ls180.v:5896$1181 + attribute \src "ls180.v:5899.68-5899.89" + cell $eq $eq$ls180.v:5899$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265112,10 +267641,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5896$1181_Y + connect \Y $eq$ls180.v:5899$1181_Y end - attribute \src "ls180.v:5897.71-5897.92" - cell $eq $eq$ls180.v:5897$1183 + attribute \src "ls180.v:5900.71-5900.92" + cell $eq $eq$ls180.v:5900$1183 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265123,10 +267652,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5897$1183_Y + connect \Y $eq$ls180.v:5900$1183_Y end - attribute \src "ls180.v:5898.57-5898.78" - cell $eq $eq$ls180.v:5898$1185 + attribute \src "ls180.v:5901.57-5901.78" + cell $eq $eq$ls180.v:5901$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265134,10 +267663,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5898$1185_Y + connect \Y $eq$ls180.v:5901$1185_Y end - attribute \src "ls180.v:5899.57-5899.78" - cell $eq $eq$ls180.v:5899$1187 + attribute \src "ls180.v:5902.57-5902.78" + cell $eq $eq$ls180.v:5902$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265145,10 +267674,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5899$1187_Y + connect \Y $eq$ls180.v:5902$1187_Y end - attribute \src "ls180.v:5900.68-5900.89" - cell $eq $eq$ls180.v:5900$1189 + attribute \src "ls180.v:5903.68-5903.89" + cell $eq $eq$ls180.v:5903$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265156,10 +267685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5900$1189_Y + connect \Y $eq$ls180.v:5903$1189_Y end - attribute \src "ls180.v:5901.68-5901.89" - cell $eq $eq$ls180.v:5901$1191 + attribute \src "ls180.v:5904.68-5904.89" + cell $eq $eq$ls180.v:5904$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265167,10 +267696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5901$1191_Y + connect \Y $eq$ls180.v:5904$1191_Y end - attribute \src "ls180.v:5902.71-5902.92" - cell $eq $eq$ls180.v:5902$1193 + attribute \src "ls180.v:5905.71-5905.92" + cell $eq $eq$ls180.v:5905$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265178,10 +267707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5902$1193_Y + connect \Y $eq$ls180.v:5905$1193_Y end - attribute \src "ls180.v:5903.57-5903.78" - cell $eq $eq$ls180.v:5903$1195 + attribute \src "ls180.v:5906.57-5906.78" + cell $eq $eq$ls180.v:5906$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265189,10 +267718,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5903$1195_Y + connect \Y $eq$ls180.v:5906$1195_Y end - attribute \src "ls180.v:5904.57-5904.78" - cell $eq $eq$ls180.v:5904$1197 + attribute \src "ls180.v:5907.57-5907.78" + cell $eq $eq$ls180.v:5907$1197 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265200,10 +267729,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5904$1197_Y + connect \Y $eq$ls180.v:5907$1197_Y end - attribute \src "ls180.v:5908.27-5908.59" - cell $eq $eq$ls180.v:5908$1200 + attribute \src "ls180.v:5911.27-5911.59" + cell $eq $eq$ls180.v:5911$1200 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -265211,10 +267740,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:6] connect \B 1'0 - connect \Y $eq$ls180.v:5908$1200_Y + connect \Y $eq$ls180.v:5911$1200_Y end - attribute \src "ls180.v:5909.27-5909.59" - cell $eq $eq$ls180.v:5909$1201 + attribute \src "ls180.v:5912.27-5912.59" + cell $eq $eq$ls180.v:5912$1201 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -265222,10 +267751,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:6] connect \B 1'1 - connect \Y $eq$ls180.v:5909$1201_Y + connect \Y $eq$ls180.v:5912$1201_Y end - attribute \src "ls180.v:5910.27-5910.59" - cell $eq $eq$ls180.v:5910$1202 + attribute \src "ls180.v:5913.27-5913.59" + cell $eq $eq$ls180.v:5913$1202 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -265233,10 +267762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:6] connect \B 2'10 - connect \Y $eq$ls180.v:5910$1202_Y + connect \Y $eq$ls180.v:5913$1202_Y end - attribute \src "ls180.v:5911.27-5911.59" - cell $eq $eq$ls180.v:5911$1203 + attribute \src "ls180.v:5914.27-5914.59" + cell $eq $eq$ls180.v:5914$1203 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -265244,10 +267773,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:6] connect \B 2'11 - connect \Y $eq$ls180.v:5911$1203_Y + connect \Y $eq$ls180.v:5914$1203_Y end - attribute \src "ls180.v:5912.27-5912.59" - cell $eq $eq$ls180.v:5912$1204 + attribute \src "ls180.v:5915.27-5915.59" + cell $eq $eq$ls180.v:5915$1204 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -265255,10 +267784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:6] connect \B 3'100 - connect \Y $eq$ls180.v:5912$1204_Y + connect \Y $eq$ls180.v:5915$1204_Y end - attribute \src "ls180.v:5913.27-5913.68" - cell $eq $eq$ls180.v:5913$1205 + attribute \src "ls180.v:5916.27-5916.68" + cell $eq $eq$ls180.v:5916$1205 parameter \A_SIGNED 0 parameter \A_WIDTH 28 parameter \B_SIGNED 0 @@ -265266,10 +267795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:2] connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5913$1205_Y + connect \Y $eq$ls180.v:5916$1205_Y end - attribute \src "ls180.v:5914.27-5914.65" - cell $eq $eq$ls180.v:5914$1206 + attribute \src "ls180.v:5917.27-5917.65" + cell $eq $eq$ls180.v:5917$1206 parameter \A_SIGNED 0 parameter \A_WIDTH 21 parameter \B_SIGNED 0 @@ -265277,10 +267806,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:9] connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5914$1206_Y + connect \Y $eq$ls180.v:5917$1206_Y end - attribute \src "ls180.v:5915.27-5915.59" - cell $eq $eq$ls180.v:5915$1207 + attribute \src "ls180.v:5918.27-5918.59" + cell $eq $eq$ls180.v:5918$1207 parameter \A_SIGNED 0 parameter \A_WIDTH 21 parameter \B_SIGNED 0 @@ -265288,10 +267817,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:9] connect \B 1'1 - connect \Y $eq$ls180.v:5915$1207_Y + connect \Y $eq$ls180.v:5918$1207_Y end - attribute \src "ls180.v:5916.27-5916.59" - cell $eq $eq$ls180.v:5916$1208 + attribute \src "ls180.v:5919.27-5919.59" + cell $eq $eq$ls180.v:5919$1208 parameter \A_SIGNED 0 parameter \A_WIDTH 21 parameter \B_SIGNED 0 @@ -265299,10 +267828,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:9] connect \B 2'10 - connect \Y $eq$ls180.v:5916$1208_Y + connect \Y $eq$ls180.v:5919$1208_Y end - attribute \src "ls180.v:5917.27-5917.59" - cell $eq $eq$ls180.v:5917$1209 + attribute \src "ls180.v:5920.27-5920.59" + cell $eq $eq$ls180.v:5920$1209 parameter \A_SIGNED 0 parameter \A_WIDTH 21 parameter \B_SIGNED 0 @@ -265310,10 +267839,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:9] connect \B 2'11 - connect \Y $eq$ls180.v:5917$1209_Y + connect \Y $eq$ls180.v:5920$1209_Y end - attribute \src "ls180.v:5918.28-5918.60" - cell $eq $eq$ls180.v:5918$1210 + attribute \src "ls180.v:5921.28-5921.60" + cell $eq $eq$ls180.v:5921$1210 parameter \A_SIGNED 0 parameter \A_WIDTH 21 parameter \B_SIGNED 0 @@ -265321,10 +267850,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:9] connect \B 3'100 - connect \Y $eq$ls180.v:5918$1210_Y + connect \Y $eq$ls180.v:5921$1210_Y end - attribute \src "ls180.v:5919.28-5919.62" - cell $eq $eq$ls180.v:5919$1211 + attribute \src "ls180.v:5922.28-5922.62" + cell $eq $eq$ls180.v:5922$1211 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -265332,10 +267861,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:22] connect \B 7'1001000 - connect \Y $eq$ls180.v:5919$1211_Y + connect \Y $eq$ls180.v:5922$1211_Y end - attribute \src "ls180.v:5920.28-5920.66" - cell $eq $eq$ls180.v:5920$1212 + attribute \src "ls180.v:5923.28-5923.66" + cell $eq $eq$ls180.v:5923$1212 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -265343,10 +267872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:13] connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5920$1212_Y + connect \Y $eq$ls180.v:5923$1212_Y end - attribute \src "ls180.v:6040.24-6040.45" - cell $eq $eq$ls180.v:6040$1279 + attribute \src "ls180.v:6043.24-6043.45" + cell $eq $eq$ls180.v:6043$1279 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -265354,10 +267883,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_count connect \B 1'0 - connect \Y $eq$ls180.v:6040$1279_Y + connect \Y $eq$ls180.v:6043$1279_Y end - attribute \src "ls180.v:6041.32-6041.77" - cell $eq $eq$ls180.v:6041$1280 + attribute \src "ls180.v:6044.32-6044.77" + cell $eq $eq$ls180.v:6044$1280 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -265365,10 +267894,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [13:8] connect \B 1'0 - connect \Y $eq$ls180.v:6041$1280_Y + connect \Y $eq$ls180.v:6044$1280_Y end - attribute \src "ls180.v:6043.97-6043.141" - cell $eq $eq$ls180.v:6043$1282 + attribute \src "ls180.v:6046.97-6046.141" + cell $eq $eq$ls180.v:6046$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265376,10 +267905,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6043$1282_Y + connect \Y $eq$ls180.v:6046$1282_Y end - attribute \src "ls180.v:6044.100-6044.144" - cell $eq $eq$ls180.v:6044$1286 + attribute \src "ls180.v:6047.100-6047.144" + cell $eq $eq$ls180.v:6047$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265387,10 +267916,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6044$1286_Y + connect \Y $eq$ls180.v:6047$1286_Y end - attribute \src "ls180.v:6046.99-6046.143" - cell $eq $eq$ls180.v:6046$1289 + attribute \src "ls180.v:6049.99-6049.143" + cell $eq $eq$ls180.v:6049$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265398,10 +267927,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6046$1289_Y + connect \Y $eq$ls180.v:6049$1289_Y end - attribute \src "ls180.v:6047.102-6047.146" - cell $eq $eq$ls180.v:6047$1293 + attribute \src "ls180.v:6050.102-6050.146" + cell $eq $eq$ls180.v:6050$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265409,10 +267938,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6047$1293_Y + connect \Y $eq$ls180.v:6050$1293_Y end - attribute \src "ls180.v:6049.99-6049.143" - cell $eq $eq$ls180.v:6049$1296 + attribute \src "ls180.v:6052.99-6052.143" + cell $eq $eq$ls180.v:6052$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265420,10 +267949,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6049$1296_Y + connect \Y $eq$ls180.v:6052$1296_Y end - attribute \src "ls180.v:6050.102-6050.146" - cell $eq $eq$ls180.v:6050$1300 + attribute \src "ls180.v:6053.102-6053.146" + cell $eq $eq$ls180.v:6053$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265431,10 +267960,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6050$1300_Y + connect \Y $eq$ls180.v:6053$1300_Y end - attribute \src "ls180.v:6052.99-6052.143" - cell $eq $eq$ls180.v:6052$1303 + attribute \src "ls180.v:6055.99-6055.143" + cell $eq $eq$ls180.v:6055$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265442,10 +267971,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6052$1303_Y + connect \Y $eq$ls180.v:6055$1303_Y end - attribute \src "ls180.v:6053.102-6053.146" - cell $eq $eq$ls180.v:6053$1307 + attribute \src "ls180.v:6056.102-6056.146" + cell $eq $eq$ls180.v:6056$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265453,10 +267982,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6053$1307_Y + connect \Y $eq$ls180.v:6056$1307_Y end - attribute \src "ls180.v:6055.99-6055.143" - cell $eq $eq$ls180.v:6055$1310 + attribute \src "ls180.v:6058.99-6058.143" + cell $eq $eq$ls180.v:6058$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265464,10 +267993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6055$1310_Y + connect \Y $eq$ls180.v:6058$1310_Y end - attribute \src "ls180.v:6056.102-6056.146" - cell $eq $eq$ls180.v:6056$1314 + attribute \src "ls180.v:6059.102-6059.146" + cell $eq $eq$ls180.v:6059$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265475,10 +268004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6056$1314_Y + connect \Y $eq$ls180.v:6059$1314_Y end - attribute \src "ls180.v:6058.102-6058.146" - cell $eq $eq$ls180.v:6058$1317 + attribute \src "ls180.v:6061.102-6061.146" + cell $eq $eq$ls180.v:6061$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265486,10 +268015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6058$1317_Y + connect \Y $eq$ls180.v:6061$1317_Y end - attribute \src "ls180.v:6059.105-6059.149" - cell $eq $eq$ls180.v:6059$1321 + attribute \src "ls180.v:6062.105-6062.149" + cell $eq $eq$ls180.v:6062$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265497,10 +268026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6059$1321_Y + connect \Y $eq$ls180.v:6062$1321_Y end - attribute \src "ls180.v:6061.102-6061.146" - cell $eq $eq$ls180.v:6061$1324 + attribute \src "ls180.v:6064.102-6064.146" + cell $eq $eq$ls180.v:6064$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265508,10 +268037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6061$1324_Y + connect \Y $eq$ls180.v:6064$1324_Y end - attribute \src "ls180.v:6062.105-6062.149" - cell $eq $eq$ls180.v:6062$1328 + attribute \src "ls180.v:6065.105-6065.149" + cell $eq $eq$ls180.v:6065$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265519,10 +268048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6062$1328_Y + connect \Y $eq$ls180.v:6065$1328_Y end - attribute \src "ls180.v:6064.102-6064.146" - cell $eq $eq$ls180.v:6064$1331 + attribute \src "ls180.v:6067.102-6067.146" + cell $eq $eq$ls180.v:6067$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265530,10 +268059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6064$1331_Y + connect \Y $eq$ls180.v:6067$1331_Y end - attribute \src "ls180.v:6065.105-6065.149" - cell $eq $eq$ls180.v:6065$1335 + attribute \src "ls180.v:6068.105-6068.149" + cell $eq $eq$ls180.v:6068$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265541,10 +268070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6065$1335_Y + connect \Y $eq$ls180.v:6068$1335_Y end - attribute \src "ls180.v:6067.102-6067.146" - cell $eq $eq$ls180.v:6067$1338 + attribute \src "ls180.v:6070.102-6070.146" + cell $eq $eq$ls180.v:6070$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265552,10 +268081,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6067$1338_Y + connect \Y $eq$ls180.v:6070$1338_Y end - attribute \src "ls180.v:6068.105-6068.149" - cell $eq $eq$ls180.v:6068$1342 + attribute \src "ls180.v:6071.105-6071.149" + cell $eq $eq$ls180.v:6071$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265563,10 +268092,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6068$1342_Y + connect \Y $eq$ls180.v:6071$1342_Y end - attribute \src "ls180.v:6079.32-6079.77" - cell $eq $eq$ls180.v:6079$1344 + attribute \src "ls180.v:6082.32-6082.77" + cell $eq $eq$ls180.v:6082$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -265574,10 +268103,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [13:8] connect \B 3'110 - connect \Y $eq$ls180.v:6079$1344_Y + connect \Y $eq$ls180.v:6082$1344_Y end - attribute \src "ls180.v:6081.94-6081.138" - cell $eq $eq$ls180.v:6081$1346 + attribute \src "ls180.v:6084.94-6084.138" + cell $eq $eq$ls180.v:6084$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265585,10 +268114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6081$1346_Y + connect \Y $eq$ls180.v:6084$1346_Y end - attribute \src "ls180.v:6082.97-6082.141" - cell $eq $eq$ls180.v:6082$1350 + attribute \src "ls180.v:6085.97-6085.141" + cell $eq $eq$ls180.v:6085$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265596,10 +268125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6082$1350_Y + connect \Y $eq$ls180.v:6085$1350_Y end - attribute \src "ls180.v:6084.94-6084.138" - cell $eq $eq$ls180.v:6084$1353 + attribute \src "ls180.v:6087.94-6087.138" + cell $eq $eq$ls180.v:6087$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265607,10 +268136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6084$1353_Y + connect \Y $eq$ls180.v:6087$1353_Y end - attribute \src "ls180.v:6085.97-6085.141" - cell $eq $eq$ls180.v:6085$1357 + attribute \src "ls180.v:6088.97-6088.141" + cell $eq $eq$ls180.v:6088$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265618,10 +268147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6085$1357_Y + connect \Y $eq$ls180.v:6088$1357_Y end - attribute \src "ls180.v:6087.94-6087.138" - cell $eq $eq$ls180.v:6087$1360 + attribute \src "ls180.v:6090.94-6090.138" + cell $eq $eq$ls180.v:6090$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265629,10 +268158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6087$1360_Y + connect \Y $eq$ls180.v:6090$1360_Y end - attribute \src "ls180.v:6088.97-6088.141" - cell $eq $eq$ls180.v:6088$1364 + attribute \src "ls180.v:6091.97-6091.141" + cell $eq $eq$ls180.v:6091$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265640,10 +268169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6088$1364_Y + connect \Y $eq$ls180.v:6091$1364_Y end - attribute \src "ls180.v:6090.94-6090.138" - cell $eq $eq$ls180.v:6090$1367 + attribute \src "ls180.v:6093.94-6093.138" + cell $eq $eq$ls180.v:6093$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265651,10 +268180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6090$1367_Y + connect \Y $eq$ls180.v:6093$1367_Y end - attribute \src "ls180.v:6091.97-6091.141" - cell $eq $eq$ls180.v:6091$1371 + attribute \src "ls180.v:6094.97-6094.141" + cell $eq $eq$ls180.v:6094$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265662,10 +268191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6091$1371_Y + connect \Y $eq$ls180.v:6094$1371_Y end - attribute \src "ls180.v:6093.95-6093.139" - cell $eq $eq$ls180.v:6093$1374 + attribute \src "ls180.v:6096.95-6096.139" + cell $eq $eq$ls180.v:6096$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265673,10 +268202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6093$1374_Y + connect \Y $eq$ls180.v:6096$1374_Y end - attribute \src "ls180.v:6094.98-6094.142" - cell $eq $eq$ls180.v:6094$1378 + attribute \src "ls180.v:6097.98-6097.142" + cell $eq $eq$ls180.v:6097$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265684,10 +268213,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6094$1378_Y + connect \Y $eq$ls180.v:6097$1378_Y end - attribute \src "ls180.v:6096.95-6096.139" - cell $eq $eq$ls180.v:6096$1381 + attribute \src "ls180.v:6099.95-6099.139" + cell $eq $eq$ls180.v:6099$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265695,10 +268224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6096$1381_Y + connect \Y $eq$ls180.v:6099$1381_Y end - attribute \src "ls180.v:6097.98-6097.142" - cell $eq $eq$ls180.v:6097$1385 + attribute \src "ls180.v:6100.98-6100.142" + cell $eq $eq$ls180.v:6100$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -265706,10 +268235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6097$1385_Y + connect \Y $eq$ls180.v:6100$1385_Y end - attribute \src "ls180.v:6105.32-6105.78" - cell $eq $eq$ls180.v:6105$1387 + attribute \src "ls180.v:6108.32-6108.78" + cell $eq $eq$ls180.v:6108$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -265717,10 +268246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [13:8] connect \B 4'1100 - connect \Y $eq$ls180.v:6105$1387_Y + connect \Y $eq$ls180.v:6108$1387_Y end - attribute \src "ls180.v:6107.93-6107.135" - cell $eq $eq$ls180.v:6107$1389 + attribute \src "ls180.v:6110.93-6110.135" + cell $eq $eq$ls180.v:6110$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265728,10 +268257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:6107$1389_Y + connect \Y $eq$ls180.v:6110$1389_Y end - attribute \src "ls180.v:6108.96-6108.138" - cell $eq $eq$ls180.v:6108$1393 + attribute \src "ls180.v:6111.96-6111.138" + cell $eq $eq$ls180.v:6111$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265739,10 +268268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:6108$1393_Y + connect \Y $eq$ls180.v:6111$1393_Y end - attribute \src "ls180.v:6110.92-6110.134" - cell $eq $eq$ls180.v:6110$1396 + attribute \src "ls180.v:6113.92-6113.134" + cell $eq $eq$ls180.v:6113$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265750,10 +268279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:6110$1396_Y + connect \Y $eq$ls180.v:6113$1396_Y end - attribute \src "ls180.v:6111.95-6111.137" - cell $eq $eq$ls180.v:6111$1400 + attribute \src "ls180.v:6114.95-6114.137" + cell $eq $eq$ls180.v:6114$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265761,10 +268290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:6111$1400_Y + connect \Y $eq$ls180.v:6114$1400_Y end - attribute \src "ls180.v:6119.32-6119.78" - cell $eq $eq$ls180.v:6119$1402 + attribute \src "ls180.v:6122.32-6122.78" + cell $eq $eq$ls180.v:6122$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -265772,10 +268301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [13:8] connect \B 4'1010 - connect \Y $eq$ls180.v:6119$1402_Y + connect \Y $eq$ls180.v:6122$1402_Y end - attribute \src "ls180.v:6121.98-6121.142" - cell $eq $eq$ls180.v:6121$1404 + attribute \src "ls180.v:6124.98-6124.142" + cell $eq $eq$ls180.v:6124$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265783,10 +268312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6121$1404_Y + connect \Y $eq$ls180.v:6124$1404_Y end - attribute \src "ls180.v:6122.101-6122.145" - cell $eq $eq$ls180.v:6122$1408 + attribute \src "ls180.v:6125.101-6125.145" + cell $eq $eq$ls180.v:6125$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265794,10 +268323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6122$1408_Y + connect \Y $eq$ls180.v:6125$1408_Y end - attribute \src "ls180.v:6124.97-6124.141" - cell $eq $eq$ls180.v:6124$1411 + attribute \src "ls180.v:6127.97-6127.141" + cell $eq $eq$ls180.v:6127$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265805,10 +268334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6124$1411_Y + connect \Y $eq$ls180.v:6127$1411_Y end - attribute \src "ls180.v:6125.100-6125.144" - cell $eq $eq$ls180.v:6125$1415 + attribute \src "ls180.v:6128.100-6128.144" + cell $eq $eq$ls180.v:6128$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265816,10 +268345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6125$1415_Y + connect \Y $eq$ls180.v:6128$1415_Y end - attribute \src "ls180.v:6127.97-6127.141" - cell $eq $eq$ls180.v:6127$1418 + attribute \src "ls180.v:6130.97-6130.141" + cell $eq $eq$ls180.v:6130$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265827,10 +268356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6127$1418_Y + connect \Y $eq$ls180.v:6130$1418_Y end - attribute \src "ls180.v:6128.100-6128.144" - cell $eq $eq$ls180.v:6128$1422 + attribute \src "ls180.v:6131.100-6131.144" + cell $eq $eq$ls180.v:6131$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265838,10 +268367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6128$1422_Y + connect \Y $eq$ls180.v:6131$1422_Y end - attribute \src "ls180.v:6130.97-6130.141" - cell $eq $eq$ls180.v:6130$1425 + attribute \src "ls180.v:6133.97-6133.141" + cell $eq $eq$ls180.v:6133$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265849,10 +268378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6130$1425_Y + connect \Y $eq$ls180.v:6133$1425_Y end - attribute \src "ls180.v:6131.100-6131.144" - cell $eq $eq$ls180.v:6131$1429 + attribute \src "ls180.v:6134.100-6134.144" + cell $eq $eq$ls180.v:6134$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265860,10 +268389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6131$1429_Y + connect \Y $eq$ls180.v:6134$1429_Y end - attribute \src "ls180.v:6133.97-6133.141" - cell $eq $eq$ls180.v:6133$1432 + attribute \src "ls180.v:6136.97-6136.141" + cell $eq $eq$ls180.v:6136$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265871,10 +268400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6133$1432_Y + connect \Y $eq$ls180.v:6136$1432_Y end - attribute \src "ls180.v:6134.100-6134.144" - cell $eq $eq$ls180.v:6134$1436 + attribute \src "ls180.v:6137.100-6137.144" + cell $eq $eq$ls180.v:6137$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265882,10 +268411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6134$1436_Y + connect \Y $eq$ls180.v:6137$1436_Y end - attribute \src "ls180.v:6136.98-6136.142" - cell $eq $eq$ls180.v:6136$1439 + attribute \src "ls180.v:6139.98-6139.142" + cell $eq $eq$ls180.v:6139$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265893,10 +268422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6136$1439_Y + connect \Y $eq$ls180.v:6139$1439_Y end - attribute \src "ls180.v:6137.101-6137.145" - cell $eq $eq$ls180.v:6137$1443 + attribute \src "ls180.v:6140.101-6140.145" + cell $eq $eq$ls180.v:6140$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265904,10 +268433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6137$1443_Y + connect \Y $eq$ls180.v:6140$1443_Y end - attribute \src "ls180.v:6139.98-6139.142" - cell $eq $eq$ls180.v:6139$1446 + attribute \src "ls180.v:6142.98-6142.142" + cell $eq $eq$ls180.v:6142$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265915,10 +268444,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6139$1446_Y + connect \Y $eq$ls180.v:6142$1446_Y end - attribute \src "ls180.v:6140.101-6140.145" - cell $eq $eq$ls180.v:6140$1450 + attribute \src "ls180.v:6143.101-6143.145" + cell $eq $eq$ls180.v:6143$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265926,10 +268455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6140$1450_Y + connect \Y $eq$ls180.v:6143$1450_Y end - attribute \src "ls180.v:6142.98-6142.142" - cell $eq $eq$ls180.v:6142$1453 + attribute \src "ls180.v:6145.98-6145.142" + cell $eq $eq$ls180.v:6145$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265937,10 +268466,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6142$1453_Y + connect \Y $eq$ls180.v:6145$1453_Y end - attribute \src "ls180.v:6143.101-6143.145" - cell $eq $eq$ls180.v:6143$1457 + attribute \src "ls180.v:6146.101-6146.145" + cell $eq $eq$ls180.v:6146$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265948,10 +268477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6143$1457_Y + connect \Y $eq$ls180.v:6146$1457_Y end - attribute \src "ls180.v:6145.98-6145.142" - cell $eq $eq$ls180.v:6145$1460 + attribute \src "ls180.v:6148.98-6148.142" + cell $eq $eq$ls180.v:6148$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265959,10 +268488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6145$1460_Y + connect \Y $eq$ls180.v:6148$1460_Y end - attribute \src "ls180.v:6146.101-6146.145" - cell $eq $eq$ls180.v:6146$1464 + attribute \src "ls180.v:6149.101-6149.145" + cell $eq $eq$ls180.v:6149$1464 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265970,10 +268499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6146$1464_Y + connect \Y $eq$ls180.v:6149$1464_Y end - attribute \src "ls180.v:6156.32-6156.78" - cell $eq $eq$ls180.v:6156$1466 + attribute \src "ls180.v:6159.32-6159.78" + cell $eq $eq$ls180.v:6159$1466 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -265981,10 +268510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [13:8] connect \B 4'1011 - connect \Y $eq$ls180.v:6156$1466_Y + connect \Y $eq$ls180.v:6159$1466_Y end - attribute \src "ls180.v:6158.98-6158.142" - cell $eq $eq$ls180.v:6158$1468 + attribute \src "ls180.v:6161.98-6161.142" + cell $eq $eq$ls180.v:6161$1468 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -265992,10 +268521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6158$1468_Y + connect \Y $eq$ls180.v:6161$1468_Y end - attribute \src "ls180.v:6159.101-6159.145" - cell $eq $eq$ls180.v:6159$1472 + attribute \src "ls180.v:6162.101-6162.145" + cell $eq $eq$ls180.v:6162$1472 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266003,10 +268532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6159$1472_Y + connect \Y $eq$ls180.v:6162$1472_Y end - attribute \src "ls180.v:6161.97-6161.141" - cell $eq $eq$ls180.v:6161$1475 + attribute \src "ls180.v:6164.97-6164.141" + cell $eq $eq$ls180.v:6164$1475 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266014,10 +268543,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6161$1475_Y + connect \Y $eq$ls180.v:6164$1475_Y end - attribute \src "ls180.v:6162.100-6162.144" - cell $eq $eq$ls180.v:6162$1479 + attribute \src "ls180.v:6165.100-6165.144" + cell $eq $eq$ls180.v:6165$1479 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266025,10 +268554,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6162$1479_Y + connect \Y $eq$ls180.v:6165$1479_Y end - attribute \src "ls180.v:6164.97-6164.141" - cell $eq $eq$ls180.v:6164$1482 + attribute \src "ls180.v:6167.97-6167.141" + cell $eq $eq$ls180.v:6167$1482 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266036,10 +268565,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6164$1482_Y + connect \Y $eq$ls180.v:6167$1482_Y end - attribute \src "ls180.v:6165.100-6165.144" - cell $eq $eq$ls180.v:6165$1486 + attribute \src "ls180.v:6168.100-6168.144" + cell $eq $eq$ls180.v:6168$1486 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266047,10 +268576,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6165$1486_Y + connect \Y $eq$ls180.v:6168$1486_Y end - attribute \src "ls180.v:6167.97-6167.141" - cell $eq $eq$ls180.v:6167$1489 + attribute \src "ls180.v:6170.97-6170.141" + cell $eq $eq$ls180.v:6170$1489 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266058,10 +268587,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6167$1489_Y + connect \Y $eq$ls180.v:6170$1489_Y end - attribute \src "ls180.v:6168.100-6168.144" - cell $eq $eq$ls180.v:6168$1493 + attribute \src "ls180.v:6171.100-6171.144" + cell $eq $eq$ls180.v:6171$1493 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266069,10 +268598,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6168$1493_Y + connect \Y $eq$ls180.v:6171$1493_Y end - attribute \src "ls180.v:6170.97-6170.141" - cell $eq $eq$ls180.v:6170$1496 + attribute \src "ls180.v:6173.97-6173.141" + cell $eq $eq$ls180.v:6173$1496 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266080,10 +268609,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6170$1496_Y + connect \Y $eq$ls180.v:6173$1496_Y end - attribute \src "ls180.v:6171.100-6171.144" - cell $eq $eq$ls180.v:6171$1500 + attribute \src "ls180.v:6174.100-6174.144" + cell $eq $eq$ls180.v:6174$1500 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266091,10 +268620,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6171$1500_Y + connect \Y $eq$ls180.v:6174$1500_Y end - attribute \src "ls180.v:6173.98-6173.142" - cell $eq $eq$ls180.v:6173$1503 + attribute \src "ls180.v:6176.98-6176.142" + cell $eq $eq$ls180.v:6176$1503 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266102,10 +268631,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6173$1503_Y + connect \Y $eq$ls180.v:6176$1503_Y end - attribute \src "ls180.v:6174.101-6174.145" - cell $eq $eq$ls180.v:6174$1507 + attribute \src "ls180.v:6177.101-6177.145" + cell $eq $eq$ls180.v:6177$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266113,10 +268642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6174$1507_Y + connect \Y $eq$ls180.v:6177$1507_Y end - attribute \src "ls180.v:6176.98-6176.142" - cell $eq $eq$ls180.v:6176$1510 + attribute \src "ls180.v:6179.98-6179.142" + cell $eq $eq$ls180.v:6179$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266124,10 +268653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6176$1510_Y + connect \Y $eq$ls180.v:6179$1510_Y end - attribute \src "ls180.v:6177.101-6177.145" - cell $eq $eq$ls180.v:6177$1514 + attribute \src "ls180.v:6180.101-6180.145" + cell $eq $eq$ls180.v:6180$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266135,10 +268664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6177$1514_Y + connect \Y $eq$ls180.v:6180$1514_Y end - attribute \src "ls180.v:6179.98-6179.142" - cell $eq $eq$ls180.v:6179$1517 + attribute \src "ls180.v:6182.98-6182.142" + cell $eq $eq$ls180.v:6182$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266146,10 +268675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6179$1517_Y + connect \Y $eq$ls180.v:6182$1517_Y end - attribute \src "ls180.v:6180.101-6180.145" - cell $eq $eq$ls180.v:6180$1521 + attribute \src "ls180.v:6183.101-6183.145" + cell $eq $eq$ls180.v:6183$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266157,10 +268686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6180$1521_Y + connect \Y $eq$ls180.v:6183$1521_Y end - attribute \src "ls180.v:6182.98-6182.142" - cell $eq $eq$ls180.v:6182$1524 + attribute \src "ls180.v:6185.98-6185.142" + cell $eq $eq$ls180.v:6185$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266168,10 +268697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6182$1524_Y + connect \Y $eq$ls180.v:6185$1524_Y end - attribute \src "ls180.v:6183.101-6183.145" - cell $eq $eq$ls180.v:6183$1528 + attribute \src "ls180.v:6186.101-6186.145" + cell $eq $eq$ls180.v:6186$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266179,10 +268708,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6183$1528_Y + connect \Y $eq$ls180.v:6186$1528_Y end - attribute \src "ls180.v:6193.32-6193.78" - cell $eq $eq$ls180.v:6193$1530 + attribute \src "ls180.v:6196.32-6196.78" + cell $eq $eq$ls180.v:6196$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266190,10 +268719,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [13:8] connect \B 4'1111 - connect \Y $eq$ls180.v:6193$1530_Y + connect \Y $eq$ls180.v:6196$1530_Y end - attribute \src "ls180.v:6195.100-6195.144" - cell $eq $eq$ls180.v:6195$1532 + attribute \src "ls180.v:6198.100-6198.144" + cell $eq $eq$ls180.v:6198$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266201,10 +268730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6195$1532_Y + connect \Y $eq$ls180.v:6198$1532_Y end - attribute \src "ls180.v:6196.103-6196.147" - cell $eq $eq$ls180.v:6196$1536 + attribute \src "ls180.v:6199.103-6199.147" + cell $eq $eq$ls180.v:6199$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266212,10 +268741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6196$1536_Y + connect \Y $eq$ls180.v:6199$1536_Y end - attribute \src "ls180.v:6198.100-6198.144" - cell $eq $eq$ls180.v:6198$1539 + attribute \src "ls180.v:6201.100-6201.144" + cell $eq $eq$ls180.v:6201$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266223,10 +268752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6198$1539_Y + connect \Y $eq$ls180.v:6201$1539_Y end - attribute \src "ls180.v:6199.103-6199.147" - cell $eq $eq$ls180.v:6199$1543 + attribute \src "ls180.v:6202.103-6202.147" + cell $eq $eq$ls180.v:6202$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266234,10 +268763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6199$1543_Y + connect \Y $eq$ls180.v:6202$1543_Y end - attribute \src "ls180.v:6201.100-6201.144" - cell $eq $eq$ls180.v:6201$1546 + attribute \src "ls180.v:6204.100-6204.144" + cell $eq $eq$ls180.v:6204$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266245,10 +268774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6201$1546_Y + connect \Y $eq$ls180.v:6204$1546_Y end - attribute \src "ls180.v:6202.103-6202.147" - cell $eq $eq$ls180.v:6202$1550 + attribute \src "ls180.v:6205.103-6205.147" + cell $eq $eq$ls180.v:6205$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266256,10 +268785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6202$1550_Y + connect \Y $eq$ls180.v:6205$1550_Y end - attribute \src "ls180.v:6204.100-6204.144" - cell $eq $eq$ls180.v:6204$1553 + attribute \src "ls180.v:6207.100-6207.144" + cell $eq $eq$ls180.v:6207$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266267,10 +268796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6204$1553_Y + connect \Y $eq$ls180.v:6207$1553_Y end - attribute \src "ls180.v:6205.103-6205.147" - cell $eq $eq$ls180.v:6205$1557 + attribute \src "ls180.v:6208.103-6208.147" + cell $eq $eq$ls180.v:6208$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266278,10 +268807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6205$1557_Y + connect \Y $eq$ls180.v:6208$1557_Y end - attribute \src "ls180.v:6207.100-6207.144" - cell $eq $eq$ls180.v:6207$1560 + attribute \src "ls180.v:6210.100-6210.144" + cell $eq $eq$ls180.v:6210$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266289,10 +268818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6207$1560_Y + connect \Y $eq$ls180.v:6210$1560_Y end - attribute \src "ls180.v:6208.103-6208.147" - cell $eq $eq$ls180.v:6208$1564 + attribute \src "ls180.v:6211.103-6211.147" + cell $eq $eq$ls180.v:6211$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266300,10 +268829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6208$1564_Y + connect \Y $eq$ls180.v:6211$1564_Y end - attribute \src "ls180.v:6210.100-6210.144" - cell $eq $eq$ls180.v:6210$1567 + attribute \src "ls180.v:6213.100-6213.144" + cell $eq $eq$ls180.v:6213$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266311,10 +268840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6210$1567_Y + connect \Y $eq$ls180.v:6213$1567_Y end - attribute \src "ls180.v:6211.103-6211.147" - cell $eq $eq$ls180.v:6211$1571 + attribute \src "ls180.v:6214.103-6214.147" + cell $eq $eq$ls180.v:6214$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266322,10 +268851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6211$1571_Y + connect \Y $eq$ls180.v:6214$1571_Y end - attribute \src "ls180.v:6213.100-6213.144" - cell $eq $eq$ls180.v:6213$1574 + attribute \src "ls180.v:6216.100-6216.144" + cell $eq $eq$ls180.v:6216$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266333,10 +268862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6213$1574_Y + connect \Y $eq$ls180.v:6216$1574_Y end - attribute \src "ls180.v:6214.103-6214.147" - cell $eq $eq$ls180.v:6214$1578 + attribute \src "ls180.v:6217.103-6217.147" + cell $eq $eq$ls180.v:6217$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266344,10 +268873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6214$1578_Y + connect \Y $eq$ls180.v:6217$1578_Y end - attribute \src "ls180.v:6216.100-6216.144" - cell $eq $eq$ls180.v:6216$1581 + attribute \src "ls180.v:6219.100-6219.144" + cell $eq $eq$ls180.v:6219$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266355,10 +268884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6216$1581_Y + connect \Y $eq$ls180.v:6219$1581_Y end - attribute \src "ls180.v:6217.103-6217.147" - cell $eq $eq$ls180.v:6217$1585 + attribute \src "ls180.v:6220.103-6220.147" + cell $eq $eq$ls180.v:6220$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266366,10 +268895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6217$1585_Y + connect \Y $eq$ls180.v:6220$1585_Y end - attribute \src "ls180.v:6219.102-6219.146" - cell $eq $eq$ls180.v:6219$1588 + attribute \src "ls180.v:6222.102-6222.146" + cell $eq $eq$ls180.v:6222$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266377,10 +268906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6219$1588_Y + connect \Y $eq$ls180.v:6222$1588_Y end - attribute \src "ls180.v:6220.105-6220.149" - cell $eq $eq$ls180.v:6220$1592 + attribute \src "ls180.v:6223.105-6223.149" + cell $eq $eq$ls180.v:6223$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266388,10 +268917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6220$1592_Y + connect \Y $eq$ls180.v:6223$1592_Y end - attribute \src "ls180.v:6222.102-6222.146" - cell $eq $eq$ls180.v:6222$1595 + attribute \src "ls180.v:6225.102-6225.146" + cell $eq $eq$ls180.v:6225$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266399,10 +268928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6222$1595_Y + connect \Y $eq$ls180.v:6225$1595_Y end - attribute \src "ls180.v:6223.105-6223.149" - cell $eq $eq$ls180.v:6223$1599 + attribute \src "ls180.v:6226.105-6226.149" + cell $eq $eq$ls180.v:6226$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266410,10 +268939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6223$1599_Y + connect \Y $eq$ls180.v:6226$1599_Y end - attribute \src "ls180.v:6225.102-6225.147" - cell $eq $eq$ls180.v:6225$1602 + attribute \src "ls180.v:6228.102-6228.147" + cell $eq $eq$ls180.v:6228$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266421,10 +268950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6225$1602_Y + connect \Y $eq$ls180.v:6228$1602_Y end - attribute \src "ls180.v:6226.105-6226.150" - cell $eq $eq$ls180.v:6226$1606 + attribute \src "ls180.v:6229.105-6229.150" + cell $eq $eq$ls180.v:6229$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266432,10 +268961,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6226$1606_Y + connect \Y $eq$ls180.v:6229$1606_Y end - attribute \src "ls180.v:6228.102-6228.147" - cell $eq $eq$ls180.v:6228$1609 + attribute \src "ls180.v:6231.102-6231.147" + cell $eq $eq$ls180.v:6231$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266443,10 +268972,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6228$1609_Y + connect \Y $eq$ls180.v:6231$1609_Y end - attribute \src "ls180.v:6229.105-6229.150" - cell $eq $eq$ls180.v:6229$1613 + attribute \src "ls180.v:6232.105-6232.150" + cell $eq $eq$ls180.v:6232$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266454,10 +268983,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6229$1613_Y + connect \Y $eq$ls180.v:6232$1613_Y end - attribute \src "ls180.v:6231.102-6231.147" - cell $eq $eq$ls180.v:6231$1616 + attribute \src "ls180.v:6234.102-6234.147" + cell $eq $eq$ls180.v:6234$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266465,10 +268994,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6231$1616_Y + connect \Y $eq$ls180.v:6234$1616_Y end - attribute \src "ls180.v:6232.105-6232.150" - cell $eq $eq$ls180.v:6232$1620 + attribute \src "ls180.v:6235.105-6235.150" + cell $eq $eq$ls180.v:6235$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266476,10 +269005,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6232$1620_Y + connect \Y $eq$ls180.v:6235$1620_Y end - attribute \src "ls180.v:6234.99-6234.144" - cell $eq $eq$ls180.v:6234$1623 + attribute \src "ls180.v:6237.99-6237.144" + cell $eq $eq$ls180.v:6237$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266487,10 +269016,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6234$1623_Y + connect \Y $eq$ls180.v:6237$1623_Y end - attribute \src "ls180.v:6235.102-6235.147" - cell $eq $eq$ls180.v:6235$1627 + attribute \src "ls180.v:6238.102-6238.147" + cell $eq $eq$ls180.v:6238$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266498,10 +269027,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6235$1627_Y + connect \Y $eq$ls180.v:6238$1627_Y end - attribute \src "ls180.v:6237.100-6237.145" - cell $eq $eq$ls180.v:6237$1630 + attribute \src "ls180.v:6240.100-6240.145" + cell $eq $eq$ls180.v:6240$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266509,10 +269038,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6237$1630_Y + connect \Y $eq$ls180.v:6240$1630_Y end - attribute \src "ls180.v:6238.103-6238.148" - cell $eq $eq$ls180.v:6238$1634 + attribute \src "ls180.v:6241.103-6241.148" + cell $eq $eq$ls180.v:6241$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -266520,10 +269049,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6238$1634_Y + connect \Y $eq$ls180.v:6241$1634_Y end - attribute \src "ls180.v:6255.32-6255.78" - cell $eq $eq$ls180.v:6255$1636 + attribute \src "ls180.v:6258.32-6258.78" + cell $eq $eq$ls180.v:6258$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266531,10 +269060,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [13:8] connect \B 4'1110 - connect \Y $eq$ls180.v:6255$1636_Y + connect \Y $eq$ls180.v:6258$1636_Y end - attribute \src "ls180.v:6257.104-6257.148" - cell $eq $eq$ls180.v:6257$1638 + attribute \src "ls180.v:6260.104-6260.148" + cell $eq $eq$ls180.v:6260$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266542,10 +269071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:6257$1638_Y + connect \Y $eq$ls180.v:6260$1638_Y end - attribute \src "ls180.v:6258.107-6258.151" - cell $eq $eq$ls180.v:6258$1642 + attribute \src "ls180.v:6261.107-6261.151" + cell $eq $eq$ls180.v:6261$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266553,10 +269082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:6258$1642_Y + connect \Y $eq$ls180.v:6261$1642_Y end - attribute \src "ls180.v:6260.104-6260.148" - cell $eq $eq$ls180.v:6260$1645 + attribute \src "ls180.v:6263.104-6263.148" + cell $eq $eq$ls180.v:6263$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266564,10 +269093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:6260$1645_Y + connect \Y $eq$ls180.v:6263$1645_Y end - attribute \src "ls180.v:6261.107-6261.151" - cell $eq $eq$ls180.v:6261$1649 + attribute \src "ls180.v:6264.107-6264.151" + cell $eq $eq$ls180.v:6264$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266575,10 +269104,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:6261$1649_Y + connect \Y $eq$ls180.v:6264$1649_Y end - attribute \src "ls180.v:6263.104-6263.148" - cell $eq $eq$ls180.v:6263$1652 + attribute \src "ls180.v:6266.104-6266.148" + cell $eq $eq$ls180.v:6266$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266586,10 +269115,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:6263$1652_Y + connect \Y $eq$ls180.v:6266$1652_Y end - attribute \src "ls180.v:6264.107-6264.151" - cell $eq $eq$ls180.v:6264$1656 + attribute \src "ls180.v:6267.107-6267.151" + cell $eq $eq$ls180.v:6267$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266597,10 +269126,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:6264$1656_Y + connect \Y $eq$ls180.v:6267$1656_Y end - attribute \src "ls180.v:6266.104-6266.148" - cell $eq $eq$ls180.v:6266$1659 + attribute \src "ls180.v:6269.104-6269.148" + cell $eq $eq$ls180.v:6269$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266608,10 +269137,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:6266$1659_Y + connect \Y $eq$ls180.v:6269$1659_Y end - attribute \src "ls180.v:6267.107-6267.151" - cell $eq $eq$ls180.v:6267$1663 + attribute \src "ls180.v:6270.107-6270.151" + cell $eq $eq$ls180.v:6270$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266619,10 +269148,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:6267$1663_Y + connect \Y $eq$ls180.v:6270$1663_Y end - attribute \src "ls180.v:6269.103-6269.147" - cell $eq $eq$ls180.v:6269$1666 + attribute \src "ls180.v:6272.103-6272.147" + cell $eq $eq$ls180.v:6272$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266630,10 +269159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:6269$1666_Y + connect \Y $eq$ls180.v:6272$1666_Y end - attribute \src "ls180.v:6270.106-6270.150" - cell $eq $eq$ls180.v:6270$1670 + attribute \src "ls180.v:6273.106-6273.150" + cell $eq $eq$ls180.v:6273$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266641,10 +269170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:6270$1670_Y + connect \Y $eq$ls180.v:6273$1670_Y end - attribute \src "ls180.v:6272.103-6272.147" - cell $eq $eq$ls180.v:6272$1673 + attribute \src "ls180.v:6275.103-6275.147" + cell $eq $eq$ls180.v:6275$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266652,10 +269181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6272$1673_Y + connect \Y $eq$ls180.v:6275$1673_Y end - attribute \src "ls180.v:6273.106-6273.150" - cell $eq $eq$ls180.v:6273$1677 + attribute \src "ls180.v:6276.106-6276.150" + cell $eq $eq$ls180.v:6276$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266663,10 +269192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6273$1677_Y + connect \Y $eq$ls180.v:6276$1677_Y end - attribute \src "ls180.v:6275.103-6275.147" - cell $eq $eq$ls180.v:6275$1680 + attribute \src "ls180.v:6278.103-6278.147" + cell $eq $eq$ls180.v:6278$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266674,10 +269203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6275$1680_Y + connect \Y $eq$ls180.v:6278$1680_Y end - attribute \src "ls180.v:6276.106-6276.150" - cell $eq $eq$ls180.v:6276$1684 + attribute \src "ls180.v:6279.106-6279.150" + cell $eq $eq$ls180.v:6279$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266685,10 +269214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6276$1684_Y + connect \Y $eq$ls180.v:6279$1684_Y end - attribute \src "ls180.v:6278.103-6278.147" - cell $eq $eq$ls180.v:6278$1687 + attribute \src "ls180.v:6281.103-6281.147" + cell $eq $eq$ls180.v:6281$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266696,10 +269225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6278$1687_Y + connect \Y $eq$ls180.v:6281$1687_Y end - attribute \src "ls180.v:6279.106-6279.150" - cell $eq $eq$ls180.v:6279$1691 + attribute \src "ls180.v:6282.106-6282.150" + cell $eq $eq$ls180.v:6282$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266707,10 +269236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6279$1691_Y + connect \Y $eq$ls180.v:6282$1691_Y end - attribute \src "ls180.v:6281.94-6281.138" - cell $eq $eq$ls180.v:6281$1694 + attribute \src "ls180.v:6284.94-6284.138" + cell $eq $eq$ls180.v:6284$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266718,10 +269247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6281$1694_Y + connect \Y $eq$ls180.v:6284$1694_Y end - attribute \src "ls180.v:6282.97-6282.141" - cell $eq $eq$ls180.v:6282$1698 + attribute \src "ls180.v:6285.97-6285.141" + cell $eq $eq$ls180.v:6285$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266729,10 +269258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6282$1698_Y + connect \Y $eq$ls180.v:6285$1698_Y end - attribute \src "ls180.v:6284.105-6284.149" - cell $eq $eq$ls180.v:6284$1701 + attribute \src "ls180.v:6287.105-6287.149" + cell $eq $eq$ls180.v:6287$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266740,10 +269269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6284$1701_Y + connect \Y $eq$ls180.v:6287$1701_Y end - attribute \src "ls180.v:6285.108-6285.152" - cell $eq $eq$ls180.v:6285$1705 + attribute \src "ls180.v:6288.108-6288.152" + cell $eq $eq$ls180.v:6288$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266751,10 +269280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6285$1705_Y + connect \Y $eq$ls180.v:6288$1705_Y end - attribute \src "ls180.v:6287.105-6287.150" - cell $eq $eq$ls180.v:6287$1708 + attribute \src "ls180.v:6290.105-6290.150" + cell $eq $eq$ls180.v:6290$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266762,10 +269291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6287$1708_Y + connect \Y $eq$ls180.v:6290$1708_Y end - attribute \src "ls180.v:6288.108-6288.153" - cell $eq $eq$ls180.v:6288$1712 + attribute \src "ls180.v:6291.108-6291.153" + cell $eq $eq$ls180.v:6291$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266773,10 +269302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6288$1712_Y + connect \Y $eq$ls180.v:6291$1712_Y end - attribute \src "ls180.v:6290.105-6290.150" - cell $eq $eq$ls180.v:6290$1715 + attribute \src "ls180.v:6293.105-6293.150" + cell $eq $eq$ls180.v:6293$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266784,10 +269313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6290$1715_Y + connect \Y $eq$ls180.v:6293$1715_Y end - attribute \src "ls180.v:6291.108-6291.153" - cell $eq $eq$ls180.v:6291$1719 + attribute \src "ls180.v:6294.108-6294.153" + cell $eq $eq$ls180.v:6294$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266795,10 +269324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6291$1719_Y + connect \Y $eq$ls180.v:6294$1719_Y end - attribute \src "ls180.v:6293.105-6293.150" - cell $eq $eq$ls180.v:6293$1722 + attribute \src "ls180.v:6296.105-6296.150" + cell $eq $eq$ls180.v:6296$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266806,10 +269335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6293$1722_Y + connect \Y $eq$ls180.v:6296$1722_Y end - attribute \src "ls180.v:6294.108-6294.153" - cell $eq $eq$ls180.v:6294$1726 + attribute \src "ls180.v:6297.108-6297.153" + cell $eq $eq$ls180.v:6297$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266817,10 +269346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6294$1726_Y + connect \Y $eq$ls180.v:6297$1726_Y end - attribute \src "ls180.v:6296.105-6296.150" - cell $eq $eq$ls180.v:6296$1729 + attribute \src "ls180.v:6299.105-6299.150" + cell $eq $eq$ls180.v:6299$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266828,10 +269357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6296$1729_Y + connect \Y $eq$ls180.v:6299$1729_Y end - attribute \src "ls180.v:6297.108-6297.153" - cell $eq $eq$ls180.v:6297$1733 + attribute \src "ls180.v:6300.108-6300.153" + cell $eq $eq$ls180.v:6300$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266839,10 +269368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6297$1733_Y + connect \Y $eq$ls180.v:6300$1733_Y end - attribute \src "ls180.v:6299.105-6299.150" - cell $eq $eq$ls180.v:6299$1736 + attribute \src "ls180.v:6302.105-6302.150" + cell $eq $eq$ls180.v:6302$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266850,10 +269379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6299$1736_Y + connect \Y $eq$ls180.v:6302$1736_Y end - attribute \src "ls180.v:6300.108-6300.153" - cell $eq $eq$ls180.v:6300$1740 + attribute \src "ls180.v:6303.108-6303.153" + cell $eq $eq$ls180.v:6303$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266861,10 +269390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6300$1740_Y + connect \Y $eq$ls180.v:6303$1740_Y end - attribute \src "ls180.v:6302.104-6302.149" - cell $eq $eq$ls180.v:6302$1743 + attribute \src "ls180.v:6305.104-6305.149" + cell $eq $eq$ls180.v:6305$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266872,10 +269401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6302$1743_Y + connect \Y $eq$ls180.v:6305$1743_Y end - attribute \src "ls180.v:6303.107-6303.152" - cell $eq $eq$ls180.v:6303$1747 + attribute \src "ls180.v:6306.107-6306.152" + cell $eq $eq$ls180.v:6306$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266883,10 +269412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6303$1747_Y + connect \Y $eq$ls180.v:6306$1747_Y end - attribute \src "ls180.v:6305.104-6305.149" - cell $eq $eq$ls180.v:6305$1750 + attribute \src "ls180.v:6308.104-6308.149" + cell $eq $eq$ls180.v:6308$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266894,10 +269423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6305$1750_Y + connect \Y $eq$ls180.v:6308$1750_Y end - attribute \src "ls180.v:6306.107-6306.152" - cell $eq $eq$ls180.v:6306$1754 + attribute \src "ls180.v:6309.107-6309.152" + cell $eq $eq$ls180.v:6309$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266905,10 +269434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6306$1754_Y + connect \Y $eq$ls180.v:6309$1754_Y end - attribute \src "ls180.v:6308.104-6308.149" - cell $eq $eq$ls180.v:6308$1757 + attribute \src "ls180.v:6311.104-6311.149" + cell $eq $eq$ls180.v:6311$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266916,10 +269445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6308$1757_Y + connect \Y $eq$ls180.v:6311$1757_Y end - attribute \src "ls180.v:6309.107-6309.152" - cell $eq $eq$ls180.v:6309$1761 + attribute \src "ls180.v:6312.107-6312.152" + cell $eq $eq$ls180.v:6312$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266927,10 +269456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6309$1761_Y + connect \Y $eq$ls180.v:6312$1761_Y end - attribute \src "ls180.v:6311.104-6311.149" - cell $eq $eq$ls180.v:6311$1764 + attribute \src "ls180.v:6314.104-6314.149" + cell $eq $eq$ls180.v:6314$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266938,10 +269467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6311$1764_Y + connect \Y $eq$ls180.v:6314$1764_Y end - attribute \src "ls180.v:6312.107-6312.152" - cell $eq $eq$ls180.v:6312$1768 + attribute \src "ls180.v:6315.107-6315.152" + cell $eq $eq$ls180.v:6315$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266949,10 +269478,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6312$1768_Y + connect \Y $eq$ls180.v:6315$1768_Y end - attribute \src "ls180.v:6314.104-6314.149" - cell $eq $eq$ls180.v:6314$1771 + attribute \src "ls180.v:6317.104-6317.149" + cell $eq $eq$ls180.v:6317$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266960,10 +269489,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6314$1771_Y + connect \Y $eq$ls180.v:6317$1771_Y end - attribute \src "ls180.v:6315.107-6315.152" - cell $eq $eq$ls180.v:6315$1775 + attribute \src "ls180.v:6318.107-6318.152" + cell $eq $eq$ls180.v:6318$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266971,10 +269500,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6315$1775_Y + connect \Y $eq$ls180.v:6318$1775_Y end - attribute \src "ls180.v:6317.104-6317.149" - cell $eq $eq$ls180.v:6317$1778 + attribute \src "ls180.v:6320.104-6320.149" + cell $eq $eq$ls180.v:6320$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266982,10 +269511,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6317$1778_Y + connect \Y $eq$ls180.v:6320$1778_Y end - attribute \src "ls180.v:6318.107-6318.152" - cell $eq $eq$ls180.v:6318$1782 + attribute \src "ls180.v:6321.107-6321.152" + cell $eq $eq$ls180.v:6321$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -266993,10 +269522,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6318$1782_Y + connect \Y $eq$ls180.v:6321$1782_Y end - attribute \src "ls180.v:6320.104-6320.149" - cell $eq $eq$ls180.v:6320$1785 + attribute \src "ls180.v:6323.104-6323.149" + cell $eq $eq$ls180.v:6323$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267004,10 +269533,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6320$1785_Y + connect \Y $eq$ls180.v:6323$1785_Y end - attribute \src "ls180.v:6321.107-6321.152" - cell $eq $eq$ls180.v:6321$1789 + attribute \src "ls180.v:6324.107-6324.152" + cell $eq $eq$ls180.v:6324$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267015,10 +269544,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6321$1789_Y + connect \Y $eq$ls180.v:6324$1789_Y end - attribute \src "ls180.v:6323.104-6323.149" - cell $eq $eq$ls180.v:6323$1792 + attribute \src "ls180.v:6326.104-6326.149" + cell $eq $eq$ls180.v:6326$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267026,10 +269555,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6323$1792_Y + connect \Y $eq$ls180.v:6326$1792_Y end - attribute \src "ls180.v:6324.107-6324.152" - cell $eq $eq$ls180.v:6324$1796 + attribute \src "ls180.v:6327.107-6327.152" + cell $eq $eq$ls180.v:6327$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267037,10 +269566,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6324$1796_Y + connect \Y $eq$ls180.v:6327$1796_Y end - attribute \src "ls180.v:6326.104-6326.149" - cell $eq $eq$ls180.v:6326$1799 + attribute \src "ls180.v:6329.104-6329.149" + cell $eq $eq$ls180.v:6329$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267048,10 +269577,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6326$1799_Y + connect \Y $eq$ls180.v:6329$1799_Y end - attribute \src "ls180.v:6327.107-6327.152" - cell $eq $eq$ls180.v:6327$1803 + attribute \src "ls180.v:6330.107-6330.152" + cell $eq $eq$ls180.v:6330$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267059,10 +269588,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6327$1803_Y + connect \Y $eq$ls180.v:6330$1803_Y end - attribute \src "ls180.v:6329.104-6329.149" - cell $eq $eq$ls180.v:6329$1806 + attribute \src "ls180.v:6332.104-6332.149" + cell $eq $eq$ls180.v:6332$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267070,10 +269599,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6329$1806_Y + connect \Y $eq$ls180.v:6332$1806_Y end - attribute \src "ls180.v:6330.107-6330.152" - cell $eq $eq$ls180.v:6330$1810 + attribute \src "ls180.v:6333.107-6333.152" + cell $eq $eq$ls180.v:6333$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267081,10 +269610,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6330$1810_Y + connect \Y $eq$ls180.v:6333$1810_Y end - attribute \src "ls180.v:6332.100-6332.145" - cell $eq $eq$ls180.v:6332$1813 + attribute \src "ls180.v:6335.100-6335.145" + cell $eq $eq$ls180.v:6335$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267092,10 +269621,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6332$1813_Y + connect \Y $eq$ls180.v:6335$1813_Y end - attribute \src "ls180.v:6333.103-6333.148" - cell $eq $eq$ls180.v:6333$1817 + attribute \src "ls180.v:6336.103-6336.148" + cell $eq $eq$ls180.v:6336$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267103,10 +269632,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6333$1817_Y + connect \Y $eq$ls180.v:6336$1817_Y end - attribute \src "ls180.v:6335.101-6335.146" - cell $eq $eq$ls180.v:6335$1820 + attribute \src "ls180.v:6338.101-6338.146" + cell $eq $eq$ls180.v:6338$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267114,10 +269643,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6335$1820_Y + connect \Y $eq$ls180.v:6338$1820_Y end - attribute \src "ls180.v:6336.104-6336.149" - cell $eq $eq$ls180.v:6336$1824 + attribute \src "ls180.v:6339.104-6339.149" + cell $eq $eq$ls180.v:6339$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267125,10 +269654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6336$1824_Y + connect \Y $eq$ls180.v:6339$1824_Y end - attribute \src "ls180.v:6338.104-6338.149" - cell $eq $eq$ls180.v:6338$1827 + attribute \src "ls180.v:6341.104-6341.149" + cell $eq $eq$ls180.v:6341$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267136,10 +269665,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6338$1827_Y + connect \Y $eq$ls180.v:6341$1827_Y end - attribute \src "ls180.v:6339.107-6339.152" - cell $eq $eq$ls180.v:6339$1831 + attribute \src "ls180.v:6342.107-6342.152" + cell $eq $eq$ls180.v:6342$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267147,10 +269676,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6339$1831_Y + connect \Y $eq$ls180.v:6342$1831_Y end - attribute \src "ls180.v:6341.104-6341.149" - cell $eq $eq$ls180.v:6341$1834 + attribute \src "ls180.v:6344.104-6344.149" + cell $eq $eq$ls180.v:6344$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267158,10 +269687,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6341$1834_Y + connect \Y $eq$ls180.v:6344$1834_Y end - attribute \src "ls180.v:6342.107-6342.152" - cell $eq $eq$ls180.v:6342$1838 + attribute \src "ls180.v:6345.107-6345.152" + cell $eq $eq$ls180.v:6345$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267169,10 +269698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6342$1838_Y + connect \Y $eq$ls180.v:6345$1838_Y end - attribute \src "ls180.v:6344.103-6344.148" - cell $eq $eq$ls180.v:6344$1841 + attribute \src "ls180.v:6347.103-6347.148" + cell $eq $eq$ls180.v:6347$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267180,10 +269709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6344$1841_Y + connect \Y $eq$ls180.v:6347$1841_Y end - attribute \src "ls180.v:6345.106-6345.151" - cell $eq $eq$ls180.v:6345$1845 + attribute \src "ls180.v:6348.106-6348.151" + cell $eq $eq$ls180.v:6348$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267191,10 +269720,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6345$1845_Y + connect \Y $eq$ls180.v:6348$1845_Y end - attribute \src "ls180.v:6347.103-6347.148" - cell $eq $eq$ls180.v:6347$1848 + attribute \src "ls180.v:6350.103-6350.148" + cell $eq $eq$ls180.v:6350$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267202,10 +269731,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6347$1848_Y + connect \Y $eq$ls180.v:6350$1848_Y end - attribute \src "ls180.v:6348.106-6348.151" - cell $eq $eq$ls180.v:6348$1852 + attribute \src "ls180.v:6351.106-6351.151" + cell $eq $eq$ls180.v:6351$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267213,10 +269742,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6348$1852_Y + connect \Y $eq$ls180.v:6351$1852_Y end - attribute \src "ls180.v:6350.103-6350.148" - cell $eq $eq$ls180.v:6350$1855 + attribute \src "ls180.v:6353.103-6353.148" + cell $eq $eq$ls180.v:6353$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267224,10 +269753,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6350$1855_Y + connect \Y $eq$ls180.v:6353$1855_Y end - attribute \src "ls180.v:6351.106-6351.151" - cell $eq $eq$ls180.v:6351$1859 + attribute \src "ls180.v:6354.106-6354.151" + cell $eq $eq$ls180.v:6354$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267235,10 +269764,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6351$1859_Y + connect \Y $eq$ls180.v:6354$1859_Y end - attribute \src "ls180.v:6353.103-6353.148" - cell $eq $eq$ls180.v:6353$1862 + attribute \src "ls180.v:6356.103-6356.148" + cell $eq $eq$ls180.v:6356$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267246,10 +269775,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6353$1862_Y + connect \Y $eq$ls180.v:6356$1862_Y end - attribute \src "ls180.v:6354.106-6354.151" - cell $eq $eq$ls180.v:6354$1866 + attribute \src "ls180.v:6357.106-6357.151" + cell $eq $eq$ls180.v:6357$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267257,10 +269786,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6354$1866_Y + connect \Y $eq$ls180.v:6357$1866_Y end - attribute \src "ls180.v:6390.32-6390.78" - cell $eq $eq$ls180.v:6390$1868 + attribute \src "ls180.v:6393.32-6393.78" + cell $eq $eq$ls180.v:6393$1868 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267268,10 +269797,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [13:8] connect \B 5'10000 - connect \Y $eq$ls180.v:6390$1868_Y + connect \Y $eq$ls180.v:6393$1868_Y end - attribute \src "ls180.v:6392.100-6392.144" - cell $eq $eq$ls180.v:6392$1870 + attribute \src "ls180.v:6395.100-6395.144" + cell $eq $eq$ls180.v:6395$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267279,10 +269808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6392$1870_Y + connect \Y $eq$ls180.v:6395$1870_Y end - attribute \src "ls180.v:6393.103-6393.147" - cell $eq $eq$ls180.v:6393$1874 + attribute \src "ls180.v:6396.103-6396.147" + cell $eq $eq$ls180.v:6396$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267290,10 +269819,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6393$1874_Y + connect \Y $eq$ls180.v:6396$1874_Y end - attribute \src "ls180.v:6395.100-6395.144" - cell $eq $eq$ls180.v:6395$1877 + attribute \src "ls180.v:6398.100-6398.144" + cell $eq $eq$ls180.v:6398$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267301,10 +269830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6395$1877_Y + connect \Y $eq$ls180.v:6398$1877_Y end - attribute \src "ls180.v:6396.103-6396.147" - cell $eq $eq$ls180.v:6396$1881 + attribute \src "ls180.v:6399.103-6399.147" + cell $eq $eq$ls180.v:6399$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267312,10 +269841,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6396$1881_Y + connect \Y $eq$ls180.v:6399$1881_Y end - attribute \src "ls180.v:6398.100-6398.144" - cell $eq $eq$ls180.v:6398$1884 + attribute \src "ls180.v:6401.100-6401.144" + cell $eq $eq$ls180.v:6401$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267323,10 +269852,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6398$1884_Y + connect \Y $eq$ls180.v:6401$1884_Y end - attribute \src "ls180.v:6399.103-6399.147" - cell $eq $eq$ls180.v:6399$1888 + attribute \src "ls180.v:6402.103-6402.147" + cell $eq $eq$ls180.v:6402$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267334,10 +269863,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6399$1888_Y + connect \Y $eq$ls180.v:6402$1888_Y end - attribute \src "ls180.v:6401.100-6401.144" - cell $eq $eq$ls180.v:6401$1891 + attribute \src "ls180.v:6404.100-6404.144" + cell $eq $eq$ls180.v:6404$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267345,10 +269874,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6401$1891_Y + connect \Y $eq$ls180.v:6404$1891_Y end - attribute \src "ls180.v:6402.103-6402.147" - cell $eq $eq$ls180.v:6402$1895 + attribute \src "ls180.v:6405.103-6405.147" + cell $eq $eq$ls180.v:6405$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267356,10 +269885,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6402$1895_Y + connect \Y $eq$ls180.v:6405$1895_Y end - attribute \src "ls180.v:6404.100-6404.144" - cell $eq $eq$ls180.v:6404$1898 + attribute \src "ls180.v:6407.100-6407.144" + cell $eq $eq$ls180.v:6407$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267367,10 +269896,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6404$1898_Y + connect \Y $eq$ls180.v:6407$1898_Y end - attribute \src "ls180.v:6405.103-6405.147" - cell $eq $eq$ls180.v:6405$1902 + attribute \src "ls180.v:6408.103-6408.147" + cell $eq $eq$ls180.v:6408$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267378,10 +269907,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6405$1902_Y + connect \Y $eq$ls180.v:6408$1902_Y end - attribute \src "ls180.v:6407.100-6407.144" - cell $eq $eq$ls180.v:6407$1905 + attribute \src "ls180.v:6410.100-6410.144" + cell $eq $eq$ls180.v:6410$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267389,10 +269918,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6407$1905_Y + connect \Y $eq$ls180.v:6410$1905_Y end - attribute \src "ls180.v:6408.103-6408.147" - cell $eq $eq$ls180.v:6408$1909 + attribute \src "ls180.v:6411.103-6411.147" + cell $eq $eq$ls180.v:6411$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267400,10 +269929,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6408$1909_Y + connect \Y $eq$ls180.v:6411$1909_Y end - attribute \src "ls180.v:6410.100-6410.144" - cell $eq $eq$ls180.v:6410$1912 + attribute \src "ls180.v:6413.100-6413.144" + cell $eq $eq$ls180.v:6413$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267411,10 +269940,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6410$1912_Y + connect \Y $eq$ls180.v:6413$1912_Y end - attribute \src "ls180.v:6411.103-6411.147" - cell $eq $eq$ls180.v:6411$1916 + attribute \src "ls180.v:6414.103-6414.147" + cell $eq $eq$ls180.v:6414$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267422,10 +269951,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6411$1916_Y + connect \Y $eq$ls180.v:6414$1916_Y end - attribute \src "ls180.v:6413.100-6413.144" - cell $eq $eq$ls180.v:6413$1919 + attribute \src "ls180.v:6416.100-6416.144" + cell $eq $eq$ls180.v:6416$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267433,10 +269962,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6413$1919_Y + connect \Y $eq$ls180.v:6416$1919_Y end - attribute \src "ls180.v:6414.103-6414.147" - cell $eq $eq$ls180.v:6414$1923 + attribute \src "ls180.v:6417.103-6417.147" + cell $eq $eq$ls180.v:6417$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267444,10 +269973,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6414$1923_Y + connect \Y $eq$ls180.v:6417$1923_Y end - attribute \src "ls180.v:6416.102-6416.146" - cell $eq $eq$ls180.v:6416$1926 + attribute \src "ls180.v:6419.102-6419.146" + cell $eq $eq$ls180.v:6419$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267455,10 +269984,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6416$1926_Y + connect \Y $eq$ls180.v:6419$1926_Y end - attribute \src "ls180.v:6417.105-6417.149" - cell $eq $eq$ls180.v:6417$1930 + attribute \src "ls180.v:6420.105-6420.149" + cell $eq $eq$ls180.v:6420$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267466,10 +269995,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6417$1930_Y + connect \Y $eq$ls180.v:6420$1930_Y end - attribute \src "ls180.v:6419.102-6419.146" - cell $eq $eq$ls180.v:6419$1933 + attribute \src "ls180.v:6422.102-6422.146" + cell $eq $eq$ls180.v:6422$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267477,10 +270006,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6419$1933_Y + connect \Y $eq$ls180.v:6422$1933_Y end - attribute \src "ls180.v:6420.105-6420.149" - cell $eq $eq$ls180.v:6420$1937 + attribute \src "ls180.v:6423.105-6423.149" + cell $eq $eq$ls180.v:6423$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267488,10 +270017,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6420$1937_Y + connect \Y $eq$ls180.v:6423$1937_Y end - attribute \src "ls180.v:6422.102-6422.147" - cell $eq $eq$ls180.v:6422$1940 + attribute \src "ls180.v:6425.102-6425.147" + cell $eq $eq$ls180.v:6425$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267499,10 +270028,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6422$1940_Y + connect \Y $eq$ls180.v:6425$1940_Y end - attribute \src "ls180.v:6423.105-6423.150" - cell $eq $eq$ls180.v:6423$1944 + attribute \src "ls180.v:6426.105-6426.150" + cell $eq $eq$ls180.v:6426$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267510,10 +270039,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6423$1944_Y + connect \Y $eq$ls180.v:6426$1944_Y end - attribute \src "ls180.v:6425.102-6425.147" - cell $eq $eq$ls180.v:6425$1947 + attribute \src "ls180.v:6428.102-6428.147" + cell $eq $eq$ls180.v:6428$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267521,10 +270050,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6425$1947_Y + connect \Y $eq$ls180.v:6428$1947_Y end - attribute \src "ls180.v:6426.105-6426.150" - cell $eq $eq$ls180.v:6426$1951 + attribute \src "ls180.v:6429.105-6429.150" + cell $eq $eq$ls180.v:6429$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267532,10 +270061,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6426$1951_Y + connect \Y $eq$ls180.v:6429$1951_Y end - attribute \src "ls180.v:6428.102-6428.147" - cell $eq $eq$ls180.v:6428$1954 + attribute \src "ls180.v:6431.102-6431.147" + cell $eq $eq$ls180.v:6431$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267543,10 +270072,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6428$1954_Y + connect \Y $eq$ls180.v:6431$1954_Y end - attribute \src "ls180.v:6429.105-6429.150" - cell $eq $eq$ls180.v:6429$1958 + attribute \src "ls180.v:6432.105-6432.150" + cell $eq $eq$ls180.v:6432$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267554,10 +270083,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6429$1958_Y + connect \Y $eq$ls180.v:6432$1958_Y end - attribute \src "ls180.v:6431.99-6431.144" - cell $eq $eq$ls180.v:6431$1961 + attribute \src "ls180.v:6434.99-6434.144" + cell $eq $eq$ls180.v:6434$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267565,10 +270094,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6431$1961_Y + connect \Y $eq$ls180.v:6434$1961_Y end - attribute \src "ls180.v:6432.102-6432.147" - cell $eq $eq$ls180.v:6432$1965 + attribute \src "ls180.v:6435.102-6435.147" + cell $eq $eq$ls180.v:6435$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267576,10 +270105,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6432$1965_Y + connect \Y $eq$ls180.v:6435$1965_Y end - attribute \src "ls180.v:6434.100-6434.145" - cell $eq $eq$ls180.v:6434$1968 + attribute \src "ls180.v:6437.100-6437.145" + cell $eq $eq$ls180.v:6437$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267587,10 +270116,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6434$1968_Y + connect \Y $eq$ls180.v:6437$1968_Y end - attribute \src "ls180.v:6435.103-6435.148" - cell $eq $eq$ls180.v:6435$1972 + attribute \src "ls180.v:6438.103-6438.148" + cell $eq $eq$ls180.v:6438$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267598,10 +270127,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6435$1972_Y + connect \Y $eq$ls180.v:6438$1972_Y end - attribute \src "ls180.v:6437.102-6437.147" - cell $eq $eq$ls180.v:6437$1975 + attribute \src "ls180.v:6440.102-6440.147" + cell $eq $eq$ls180.v:6440$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267609,10 +270138,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6437$1975_Y + connect \Y $eq$ls180.v:6440$1975_Y end - attribute \src "ls180.v:6438.105-6438.150" - cell $eq $eq$ls180.v:6438$1979 + attribute \src "ls180.v:6441.105-6441.150" + cell $eq $eq$ls180.v:6441$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267620,10 +270149,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6438$1979_Y + connect \Y $eq$ls180.v:6441$1979_Y end - attribute \src "ls180.v:6440.102-6440.147" - cell $eq $eq$ls180.v:6440$1982 + attribute \src "ls180.v:6443.102-6443.147" + cell $eq $eq$ls180.v:6443$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267631,10 +270160,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6440$1982_Y + connect \Y $eq$ls180.v:6443$1982_Y end - attribute \src "ls180.v:6441.105-6441.150" - cell $eq $eq$ls180.v:6441$1986 + attribute \src "ls180.v:6444.105-6444.150" + cell $eq $eq$ls180.v:6444$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267642,10 +270171,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6441$1986_Y + connect \Y $eq$ls180.v:6444$1986_Y end - attribute \src "ls180.v:6443.102-6443.147" - cell $eq $eq$ls180.v:6443$1989 + attribute \src "ls180.v:6446.102-6446.147" + cell $eq $eq$ls180.v:6446$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267653,10 +270182,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6443$1989_Y + connect \Y $eq$ls180.v:6446$1989_Y end - attribute \src "ls180.v:6444.105-6444.150" - cell $eq $eq$ls180.v:6444$1993 + attribute \src "ls180.v:6447.105-6447.150" + cell $eq $eq$ls180.v:6447$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267664,10 +270193,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6444$1993_Y + connect \Y $eq$ls180.v:6447$1993_Y end - attribute \src "ls180.v:6446.102-6446.147" - cell $eq $eq$ls180.v:6446$1996 + attribute \src "ls180.v:6449.102-6449.147" + cell $eq $eq$ls180.v:6449$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267675,10 +270204,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6446$1996_Y + connect \Y $eq$ls180.v:6449$1996_Y end - attribute \src "ls180.v:6447.105-6447.150" - cell $eq $eq$ls180.v:6447$2000 + attribute \src "ls180.v:6450.105-6450.150" + cell $eq $eq$ls180.v:6450$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -267686,10 +270215,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6447$2000_Y + connect \Y $eq$ls180.v:6450$2000_Y end - attribute \src "ls180.v:6469.32-6469.78" - cell $eq $eq$ls180.v:6469$2002 + attribute \src "ls180.v:6472.32-6472.78" + cell $eq $eq$ls180.v:6472$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267697,10 +270226,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [13:8] connect \B 4'1101 - connect \Y $eq$ls180.v:6469$2002_Y + connect \Y $eq$ls180.v:6472$2002_Y end - attribute \src "ls180.v:6471.102-6471.146" - cell $eq $eq$ls180.v:6471$2004 + attribute \src "ls180.v:6474.102-6474.146" + cell $eq $eq$ls180.v:6474$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -267708,10 +270237,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6471$2004_Y + connect \Y $eq$ls180.v:6474$2004_Y end - attribute \src "ls180.v:6472.105-6472.149" - cell $eq $eq$ls180.v:6472$2008 + attribute \src "ls180.v:6475.105-6475.149" + cell $eq $eq$ls180.v:6475$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -267719,10 +270248,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6472$2008_Y + connect \Y $eq$ls180.v:6475$2008_Y end - attribute \src "ls180.v:6474.107-6474.151" - cell $eq $eq$ls180.v:6474$2011 + attribute \src "ls180.v:6477.107-6477.151" + cell $eq $eq$ls180.v:6477$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -267730,10 +270259,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6474$2011_Y + connect \Y $eq$ls180.v:6477$2011_Y end - attribute \src "ls180.v:6475.110-6475.154" - cell $eq $eq$ls180.v:6475$2015 + attribute \src "ls180.v:6478.110-6478.154" + cell $eq $eq$ls180.v:6478$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -267741,10 +270270,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6475$2015_Y + connect \Y $eq$ls180.v:6478$2015_Y end - attribute \src "ls180.v:6477.107-6477.151" - cell $eq $eq$ls180.v:6477$2018 + attribute \src "ls180.v:6480.107-6480.151" + cell $eq $eq$ls180.v:6480$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -267752,10 +270281,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6477$2018_Y + connect \Y $eq$ls180.v:6480$2018_Y end - attribute \src "ls180.v:6478.110-6478.154" - cell $eq $eq$ls180.v:6478$2022 + attribute \src "ls180.v:6481.110-6481.154" + cell $eq $eq$ls180.v:6481$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -267763,10 +270292,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6478$2022_Y + connect \Y $eq$ls180.v:6481$2022_Y end - attribute \src "ls180.v:6480.100-6480.144" - cell $eq $eq$ls180.v:6480$2025 + attribute \src "ls180.v:6483.100-6483.144" + cell $eq $eq$ls180.v:6483$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -267774,10 +270303,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6480$2025_Y + connect \Y $eq$ls180.v:6483$2025_Y end - attribute \src "ls180.v:6481.103-6481.147" - cell $eq $eq$ls180.v:6481$2029 + attribute \src "ls180.v:6484.103-6484.147" + cell $eq $eq$ls180.v:6484$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -267785,10 +270314,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6481$2029_Y + connect \Y $eq$ls180.v:6484$2029_Y end - attribute \src "ls180.v:6486.32-6486.77" - cell $eq $eq$ls180.v:6486$2031 + attribute \src "ls180.v:6489.32-6489.77" + cell $eq $eq$ls180.v:6489$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -267796,10 +270325,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [13:8] connect \B 2'11 - connect \Y $eq$ls180.v:6486$2031_Y + connect \Y $eq$ls180.v:6489$2031_Y end - attribute \src "ls180.v:6488.104-6488.148" - cell $eq $eq$ls180.v:6488$2033 + attribute \src "ls180.v:6491.104-6491.148" + cell $eq $eq$ls180.v:6491$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267807,10 +270336,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6488$2033_Y + connect \Y $eq$ls180.v:6491$2033_Y end - attribute \src "ls180.v:6489.107-6489.151" - cell $eq $eq$ls180.v:6489$2037 + attribute \src "ls180.v:6492.107-6492.151" + cell $eq $eq$ls180.v:6492$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267818,10 +270347,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6489$2037_Y + connect \Y $eq$ls180.v:6492$2037_Y end - attribute \src "ls180.v:6491.108-6491.152" - cell $eq $eq$ls180.v:6491$2040 + attribute \src "ls180.v:6494.108-6494.152" + cell $eq $eq$ls180.v:6494$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267829,10 +270358,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6491$2040_Y + connect \Y $eq$ls180.v:6494$2040_Y end - attribute \src "ls180.v:6492.111-6492.155" - cell $eq $eq$ls180.v:6492$2044 + attribute \src "ls180.v:6495.111-6495.155" + cell $eq $eq$ls180.v:6495$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267840,10 +270369,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6492$2044_Y + connect \Y $eq$ls180.v:6495$2044_Y end - attribute \src "ls180.v:6494.98-6494.142" - cell $eq $eq$ls180.v:6494$2047 + attribute \src "ls180.v:6497.98-6497.142" + cell $eq $eq$ls180.v:6497$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267851,10 +270380,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6494$2047_Y + connect \Y $eq$ls180.v:6497$2047_Y end - attribute \src "ls180.v:6495.101-6495.145" - cell $eq $eq$ls180.v:6495$2051 + attribute \src "ls180.v:6498.101-6498.145" + cell $eq $eq$ls180.v:6498$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267862,10 +270391,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6495$2051_Y + connect \Y $eq$ls180.v:6498$2051_Y end - attribute \src "ls180.v:6497.108-6497.152" - cell $eq $eq$ls180.v:6497$2054 + attribute \src "ls180.v:6500.108-6500.152" + cell $eq $eq$ls180.v:6500$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267873,10 +270402,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6497$2054_Y + connect \Y $eq$ls180.v:6500$2054_Y end - attribute \src "ls180.v:6498.111-6498.155" - cell $eq $eq$ls180.v:6498$2058 + attribute \src "ls180.v:6501.111-6501.155" + cell $eq $eq$ls180.v:6501$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267884,10 +270413,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6498$2058_Y + connect \Y $eq$ls180.v:6501$2058_Y end - attribute \src "ls180.v:6500.108-6500.152" - cell $eq $eq$ls180.v:6500$2061 + attribute \src "ls180.v:6503.108-6503.152" + cell $eq $eq$ls180.v:6503$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267895,10 +270424,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6500$2061_Y + connect \Y $eq$ls180.v:6503$2061_Y end - attribute \src "ls180.v:6501.111-6501.155" - cell $eq $eq$ls180.v:6501$2065 + attribute \src "ls180.v:6504.111-6504.155" + cell $eq $eq$ls180.v:6504$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267906,10 +270435,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6501$2065_Y + connect \Y $eq$ls180.v:6504$2065_Y end - attribute \src "ls180.v:6503.109-6503.153" - cell $eq $eq$ls180.v:6503$2068 + attribute \src "ls180.v:6506.109-6506.153" + cell $eq $eq$ls180.v:6506$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267917,10 +270446,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6503$2068_Y + connect \Y $eq$ls180.v:6506$2068_Y end - attribute \src "ls180.v:6504.112-6504.156" - cell $eq $eq$ls180.v:6504$2072 + attribute \src "ls180.v:6507.112-6507.156" + cell $eq $eq$ls180.v:6507$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267928,10 +270457,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6504$2072_Y + connect \Y $eq$ls180.v:6507$2072_Y end - attribute \src "ls180.v:6506.107-6506.151" - cell $eq $eq$ls180.v:6506$2075 + attribute \src "ls180.v:6509.107-6509.151" + cell $eq $eq$ls180.v:6509$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267939,10 +270468,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6506$2075_Y + connect \Y $eq$ls180.v:6509$2075_Y end - attribute \src "ls180.v:6507.110-6507.154" - cell $eq $eq$ls180.v:6507$2079 + attribute \src "ls180.v:6510.110-6510.154" + cell $eq $eq$ls180.v:6510$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267950,10 +270479,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6507$2079_Y + connect \Y $eq$ls180.v:6510$2079_Y end - attribute \src "ls180.v:6509.107-6509.151" - cell $eq $eq$ls180.v:6509$2082 + attribute \src "ls180.v:6512.107-6512.151" + cell $eq $eq$ls180.v:6512$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267961,10 +270490,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6509$2082_Y + connect \Y $eq$ls180.v:6512$2082_Y end - attribute \src "ls180.v:6510.110-6510.154" - cell $eq $eq$ls180.v:6510$2086 + attribute \src "ls180.v:6513.110-6513.154" + cell $eq $eq$ls180.v:6513$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267972,10 +270501,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6510$2086_Y + connect \Y $eq$ls180.v:6513$2086_Y end - attribute \src "ls180.v:6512.107-6512.151" - cell $eq $eq$ls180.v:6512$2089 + attribute \src "ls180.v:6515.107-6515.151" + cell $eq $eq$ls180.v:6515$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267983,10 +270512,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6512$2089_Y + connect \Y $eq$ls180.v:6515$2089_Y end - attribute \src "ls180.v:6513.110-6513.154" - cell $eq $eq$ls180.v:6513$2093 + attribute \src "ls180.v:6516.110-6516.154" + cell $eq $eq$ls180.v:6516$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -267994,10 +270523,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6513$2093_Y + connect \Y $eq$ls180.v:6516$2093_Y end - attribute \src "ls180.v:6515.107-6515.151" - cell $eq $eq$ls180.v:6515$2096 + attribute \src "ls180.v:6518.107-6518.151" + cell $eq $eq$ls180.v:6518$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268005,10 +270534,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6515$2096_Y + connect \Y $eq$ls180.v:6518$2096_Y end - attribute \src "ls180.v:6516.110-6516.154" - cell $eq $eq$ls180.v:6516$2100 + attribute \src "ls180.v:6519.110-6519.154" + cell $eq $eq$ls180.v:6519$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268016,10 +270545,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6516$2100_Y + connect \Y $eq$ls180.v:6519$2100_Y end - attribute \src "ls180.v:6531.33-6531.79" - cell $eq $eq$ls180.v:6531$2102 + attribute \src "ls180.v:6534.33-6534.79" + cell $eq $eq$ls180.v:6534$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -268027,10 +270556,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [13:8] connect \B 4'1000 - connect \Y $eq$ls180.v:6531$2102_Y + connect \Y $eq$ls180.v:6534$2102_Y end - attribute \src "ls180.v:6533.102-6533.147" - cell $eq $eq$ls180.v:6533$2104 + attribute \src "ls180.v:6536.102-6536.147" + cell $eq $eq$ls180.v:6536$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268038,10 +270567,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6533$2104_Y + connect \Y $eq$ls180.v:6536$2104_Y end - attribute \src "ls180.v:6534.105-6534.150" - cell $eq $eq$ls180.v:6534$2108 + attribute \src "ls180.v:6537.105-6537.150" + cell $eq $eq$ls180.v:6537$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268049,10 +270578,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6534$2108_Y + connect \Y $eq$ls180.v:6537$2108_Y end - attribute \src "ls180.v:6536.102-6536.147" - cell $eq $eq$ls180.v:6536$2111 + attribute \src "ls180.v:6539.102-6539.147" + cell $eq $eq$ls180.v:6539$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268060,10 +270589,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6536$2111_Y + connect \Y $eq$ls180.v:6539$2111_Y end - attribute \src "ls180.v:6537.105-6537.150" - cell $eq $eq$ls180.v:6537$2115 + attribute \src "ls180.v:6540.105-6540.150" + cell $eq $eq$ls180.v:6540$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268071,10 +270600,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6537$2115_Y + connect \Y $eq$ls180.v:6540$2115_Y end - attribute \src "ls180.v:6539.100-6539.145" - cell $eq $eq$ls180.v:6539$2118 + attribute \src "ls180.v:6542.100-6542.145" + cell $eq $eq$ls180.v:6542$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268082,10 +270611,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6539$2118_Y + connect \Y $eq$ls180.v:6542$2118_Y end - attribute \src "ls180.v:6540.103-6540.148" - cell $eq $eq$ls180.v:6540$2122 + attribute \src "ls180.v:6543.103-6543.148" + cell $eq $eq$ls180.v:6543$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268093,10 +270622,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6540$2122_Y + connect \Y $eq$ls180.v:6543$2122_Y end - attribute \src "ls180.v:6542.99-6542.144" - cell $eq $eq$ls180.v:6542$2125 + attribute \src "ls180.v:6545.99-6545.144" + cell $eq $eq$ls180.v:6545$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268104,10 +270633,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6542$2125_Y + connect \Y $eq$ls180.v:6545$2125_Y end - attribute \src "ls180.v:6543.102-6543.147" - cell $eq $eq$ls180.v:6543$2129 + attribute \src "ls180.v:6546.102-6546.147" + cell $eq $eq$ls180.v:6546$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268115,10 +270644,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6543$2129_Y + connect \Y $eq$ls180.v:6546$2129_Y end - attribute \src "ls180.v:6545.98-6545.143" - cell $eq $eq$ls180.v:6545$2132 + attribute \src "ls180.v:6548.98-6548.143" + cell $eq $eq$ls180.v:6548$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268126,10 +270655,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6545$2132_Y + connect \Y $eq$ls180.v:6548$2132_Y end - attribute \src "ls180.v:6546.101-6546.146" - cell $eq $eq$ls180.v:6546$2136 + attribute \src "ls180.v:6549.101-6549.146" + cell $eq $eq$ls180.v:6549$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268137,10 +270666,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6546$2136_Y + connect \Y $eq$ls180.v:6549$2136_Y end - attribute \src "ls180.v:6548.97-6548.142" - cell $eq $eq$ls180.v:6548$2139 + attribute \src "ls180.v:6551.97-6551.142" + cell $eq $eq$ls180.v:6551$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268148,10 +270677,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6548$2139_Y + connect \Y $eq$ls180.v:6551$2139_Y end - attribute \src "ls180.v:6549.100-6549.145" - cell $eq $eq$ls180.v:6549$2143 + attribute \src "ls180.v:6552.100-6552.145" + cell $eq $eq$ls180.v:6552$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268159,10 +270688,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6549$2143_Y + connect \Y $eq$ls180.v:6552$2143_Y end - attribute \src "ls180.v:6551.103-6551.148" - cell $eq $eq$ls180.v:6551$2146 + attribute \src "ls180.v:6554.103-6554.148" + cell $eq $eq$ls180.v:6554$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268170,10 +270699,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6551$2146_Y + connect \Y $eq$ls180.v:6554$2146_Y end - attribute \src "ls180.v:6552.106-6552.151" - cell $eq $eq$ls180.v:6552$2150 + attribute \src "ls180.v:6555.106-6555.151" + cell $eq $eq$ls180.v:6555$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268181,10 +270710,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6552$2150_Y + connect \Y $eq$ls180.v:6555$2150_Y end - attribute \src "ls180.v:6571.33-6571.79" - cell $eq $eq$ls180.v:6571$2153 + attribute \src "ls180.v:6574.33-6574.79" + cell $eq $eq$ls180.v:6574$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -268192,10 +270721,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [13:8] connect \B 4'1001 - connect \Y $eq$ls180.v:6571$2153_Y + connect \Y $eq$ls180.v:6574$2153_Y end - attribute \src "ls180.v:6573.102-6573.147" - cell $eq $eq$ls180.v:6573$2155 + attribute \src "ls180.v:6576.102-6576.147" + cell $eq $eq$ls180.v:6576$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268203,10 +270732,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6573$2155_Y + connect \Y $eq$ls180.v:6576$2155_Y end - attribute \src "ls180.v:6574.105-6574.150" - cell $eq $eq$ls180.v:6574$2159 + attribute \src "ls180.v:6577.105-6577.150" + cell $eq $eq$ls180.v:6577$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268214,10 +270743,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6574$2159_Y + connect \Y $eq$ls180.v:6577$2159_Y end - attribute \src "ls180.v:6576.102-6576.147" - cell $eq $eq$ls180.v:6576$2162 + attribute \src "ls180.v:6579.102-6579.147" + cell $eq $eq$ls180.v:6579$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268225,10 +270754,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6576$2162_Y + connect \Y $eq$ls180.v:6579$2162_Y end - attribute \src "ls180.v:6577.105-6577.150" - cell $eq $eq$ls180.v:6577$2166 + attribute \src "ls180.v:6580.105-6580.150" + cell $eq $eq$ls180.v:6580$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268236,10 +270765,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6577$2166_Y + connect \Y $eq$ls180.v:6580$2166_Y end - attribute \src "ls180.v:6579.100-6579.145" - cell $eq $eq$ls180.v:6579$2169 + attribute \src "ls180.v:6582.100-6582.145" + cell $eq $eq$ls180.v:6582$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268247,10 +270776,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6579$2169_Y + connect \Y $eq$ls180.v:6582$2169_Y end - attribute \src "ls180.v:6580.103-6580.148" - cell $eq $eq$ls180.v:6580$2173 + attribute \src "ls180.v:6583.103-6583.148" + cell $eq $eq$ls180.v:6583$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268258,10 +270787,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6580$2173_Y + connect \Y $eq$ls180.v:6583$2173_Y end - attribute \src "ls180.v:6582.99-6582.144" - cell $eq $eq$ls180.v:6582$2176 + attribute \src "ls180.v:6585.99-6585.144" + cell $eq $eq$ls180.v:6585$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268269,10 +270798,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6582$2176_Y + connect \Y $eq$ls180.v:6585$2176_Y end - attribute \src "ls180.v:6583.102-6583.147" - cell $eq $eq$ls180.v:6583$2180 + attribute \src "ls180.v:6586.102-6586.147" + cell $eq $eq$ls180.v:6586$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268280,10 +270809,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6583$2180_Y + connect \Y $eq$ls180.v:6586$2180_Y end - attribute \src "ls180.v:6585.98-6585.143" - cell $eq $eq$ls180.v:6585$2183 + attribute \src "ls180.v:6588.98-6588.143" + cell $eq $eq$ls180.v:6588$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268291,10 +270820,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6585$2183_Y + connect \Y $eq$ls180.v:6588$2183_Y end - attribute \src "ls180.v:6586.101-6586.146" - cell $eq $eq$ls180.v:6586$2187 + attribute \src "ls180.v:6589.101-6589.146" + cell $eq $eq$ls180.v:6589$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268302,10 +270831,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6586$2187_Y + connect \Y $eq$ls180.v:6589$2187_Y end - attribute \src "ls180.v:6588.97-6588.142" - cell $eq $eq$ls180.v:6588$2190 + attribute \src "ls180.v:6591.97-6591.142" + cell $eq $eq$ls180.v:6591$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268313,10 +270842,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6588$2190_Y + connect \Y $eq$ls180.v:6591$2190_Y end - attribute \src "ls180.v:6589.100-6589.145" - cell $eq $eq$ls180.v:6589$2194 + attribute \src "ls180.v:6592.100-6592.145" + cell $eq $eq$ls180.v:6592$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268324,10 +270853,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6589$2194_Y + connect \Y $eq$ls180.v:6592$2194_Y end - attribute \src "ls180.v:6591.103-6591.148" - cell $eq $eq$ls180.v:6591$2197 + attribute \src "ls180.v:6594.103-6594.148" + cell $eq $eq$ls180.v:6594$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268335,10 +270864,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6591$2197_Y + connect \Y $eq$ls180.v:6594$2197_Y end - attribute \src "ls180.v:6592.106-6592.151" - cell $eq $eq$ls180.v:6592$2201 + attribute \src "ls180.v:6595.106-6595.151" + cell $eq $eq$ls180.v:6595$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268346,10 +270875,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6592$2201_Y + connect \Y $eq$ls180.v:6595$2201_Y end - attribute \src "ls180.v:6594.106-6594.151" - cell $eq $eq$ls180.v:6594$2204 + attribute \src "ls180.v:6597.106-6597.151" + cell $eq $eq$ls180.v:6597$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268357,10 +270886,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6594$2204_Y + connect \Y $eq$ls180.v:6597$2204_Y end - attribute \src "ls180.v:6595.109-6595.154" - cell $eq $eq$ls180.v:6595$2208 + attribute \src "ls180.v:6598.109-6598.154" + cell $eq $eq$ls180.v:6598$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268368,10 +270897,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6595$2208_Y + connect \Y $eq$ls180.v:6598$2208_Y end - attribute \src "ls180.v:6597.106-6597.151" - cell $eq $eq$ls180.v:6597$2211 + attribute \src "ls180.v:6600.106-6600.151" + cell $eq $eq$ls180.v:6600$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268379,10 +270908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6597$2211_Y + connect \Y $eq$ls180.v:6600$2211_Y end - attribute \src "ls180.v:6598.109-6598.154" - cell $eq $eq$ls180.v:6598$2215 + attribute \src "ls180.v:6601.109-6601.154" + cell $eq $eq$ls180.v:6601$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268390,10 +270919,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6598$2215_Y + connect \Y $eq$ls180.v:6601$2215_Y end - attribute \src "ls180.v:6619.33-6619.79" - cell $eq $eq$ls180.v:6619$2218 + attribute \src "ls180.v:6622.33-6622.79" + cell $eq $eq$ls180.v:6622$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -268401,10 +270930,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [13:8] connect \B 2'10 - connect \Y $eq$ls180.v:6619$2218_Y + connect \Y $eq$ls180.v:6622$2218_Y end - attribute \src "ls180.v:6621.99-6621.144" - cell $eq $eq$ls180.v:6621$2220 + attribute \src "ls180.v:6624.99-6624.144" + cell $eq $eq$ls180.v:6624$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268412,10 +270941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6621$2220_Y + connect \Y $eq$ls180.v:6624$2220_Y end - attribute \src "ls180.v:6622.102-6622.147" - cell $eq $eq$ls180.v:6622$2224 + attribute \src "ls180.v:6625.102-6625.147" + cell $eq $eq$ls180.v:6625$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268423,10 +270952,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6622$2224_Y + connect \Y $eq$ls180.v:6625$2224_Y end - attribute \src "ls180.v:6624.99-6624.144" - cell $eq $eq$ls180.v:6624$2227 + attribute \src "ls180.v:6627.99-6627.144" + cell $eq $eq$ls180.v:6627$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268434,10 +270963,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6624$2227_Y + connect \Y $eq$ls180.v:6627$2227_Y end - attribute \src "ls180.v:6625.102-6625.147" - cell $eq $eq$ls180.v:6625$2231 + attribute \src "ls180.v:6628.102-6628.147" + cell $eq $eq$ls180.v:6628$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268445,10 +270974,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6625$2231_Y + connect \Y $eq$ls180.v:6628$2231_Y end - attribute \src "ls180.v:6627.99-6627.144" - cell $eq $eq$ls180.v:6627$2234 + attribute \src "ls180.v:6630.99-6630.144" + cell $eq $eq$ls180.v:6630$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268456,10 +270985,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6627$2234_Y + connect \Y $eq$ls180.v:6630$2234_Y end - attribute \src "ls180.v:6628.102-6628.147" - cell $eq $eq$ls180.v:6628$2238 + attribute \src "ls180.v:6631.102-6631.147" + cell $eq $eq$ls180.v:6631$2238 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268467,10 +270996,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6628$2238_Y + connect \Y $eq$ls180.v:6631$2238_Y end - attribute \src "ls180.v:6630.99-6630.144" - cell $eq $eq$ls180.v:6630$2241 + attribute \src "ls180.v:6633.99-6633.144" + cell $eq $eq$ls180.v:6633$2241 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268478,10 +271007,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6630$2241_Y + connect \Y $eq$ls180.v:6633$2241_Y end - attribute \src "ls180.v:6631.102-6631.147" - cell $eq $eq$ls180.v:6631$2245 + attribute \src "ls180.v:6634.102-6634.147" + cell $eq $eq$ls180.v:6634$2245 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268489,10 +271018,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6631$2245_Y + connect \Y $eq$ls180.v:6634$2245_Y end - attribute \src "ls180.v:6633.101-6633.146" - cell $eq $eq$ls180.v:6633$2248 + attribute \src "ls180.v:6636.101-6636.146" + cell $eq $eq$ls180.v:6636$2248 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268500,10 +271029,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6633$2248_Y + connect \Y $eq$ls180.v:6636$2248_Y end - attribute \src "ls180.v:6634.104-6634.149" - cell $eq $eq$ls180.v:6634$2252 + attribute \src "ls180.v:6637.104-6637.149" + cell $eq $eq$ls180.v:6637$2252 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268511,10 +271040,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6634$2252_Y + connect \Y $eq$ls180.v:6637$2252_Y end - attribute \src "ls180.v:6636.101-6636.146" - cell $eq $eq$ls180.v:6636$2255 + attribute \src "ls180.v:6639.101-6639.146" + cell $eq $eq$ls180.v:6639$2255 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268522,10 +271051,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6636$2255_Y + connect \Y $eq$ls180.v:6639$2255_Y end - attribute \src "ls180.v:6637.104-6637.149" - cell $eq $eq$ls180.v:6637$2259 + attribute \src "ls180.v:6640.104-6640.149" + cell $eq $eq$ls180.v:6640$2259 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268533,10 +271062,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6637$2259_Y + connect \Y $eq$ls180.v:6640$2259_Y end - attribute \src "ls180.v:6639.101-6639.146" - cell $eq $eq$ls180.v:6639$2262 + attribute \src "ls180.v:6642.101-6642.146" + cell $eq $eq$ls180.v:6642$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268544,10 +271073,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6639$2262_Y + connect \Y $eq$ls180.v:6642$2262_Y end - attribute \src "ls180.v:6640.104-6640.149" - cell $eq $eq$ls180.v:6640$2266 + attribute \src "ls180.v:6643.104-6643.149" + cell $eq $eq$ls180.v:6643$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268555,10 +271084,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6640$2266_Y + connect \Y $eq$ls180.v:6643$2266_Y end - attribute \src "ls180.v:6642.101-6642.146" - cell $eq $eq$ls180.v:6642$2269 + attribute \src "ls180.v:6645.101-6645.146" + cell $eq $eq$ls180.v:6645$2269 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268566,10 +271095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6642$2269_Y + connect \Y $eq$ls180.v:6645$2269_Y end - attribute \src "ls180.v:6643.104-6643.149" - cell $eq $eq$ls180.v:6643$2273 + attribute \src "ls180.v:6646.104-6646.149" + cell $eq $eq$ls180.v:6646$2273 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268577,10 +271106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6643$2273_Y + connect \Y $eq$ls180.v:6646$2273_Y end - attribute \src "ls180.v:6645.97-6645.142" - cell $eq $eq$ls180.v:6645$2276 + attribute \src "ls180.v:6648.97-6648.142" + cell $eq $eq$ls180.v:6648$2276 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268588,10 +271117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6645$2276_Y + connect \Y $eq$ls180.v:6648$2276_Y end - attribute \src "ls180.v:6646.100-6646.145" - cell $eq $eq$ls180.v:6646$2280 + attribute \src "ls180.v:6649.100-6649.145" + cell $eq $eq$ls180.v:6649$2280 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268599,10 +271128,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6646$2280_Y + connect \Y $eq$ls180.v:6649$2280_Y end - attribute \src "ls180.v:6648.107-6648.152" - cell $eq $eq$ls180.v:6648$2283 + attribute \src "ls180.v:6651.107-6651.152" + cell $eq $eq$ls180.v:6651$2283 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268610,10 +271139,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6648$2283_Y + connect \Y $eq$ls180.v:6651$2283_Y end - attribute \src "ls180.v:6649.110-6649.155" - cell $eq $eq$ls180.v:6649$2287 + attribute \src "ls180.v:6652.110-6652.155" + cell $eq $eq$ls180.v:6652$2287 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268621,10 +271150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6649$2287_Y + connect \Y $eq$ls180.v:6652$2287_Y end - attribute \src "ls180.v:6651.100-6651.146" - cell $eq $eq$ls180.v:6651$2290 + attribute \src "ls180.v:6654.100-6654.146" + cell $eq $eq$ls180.v:6654$2290 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268632,10 +271161,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6651$2290_Y + connect \Y $eq$ls180.v:6654$2290_Y end - attribute \src "ls180.v:6652.103-6652.149" - cell $eq $eq$ls180.v:6652$2294 + attribute \src "ls180.v:6655.103-6655.149" + cell $eq $eq$ls180.v:6655$2294 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268643,10 +271172,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6652$2294_Y + connect \Y $eq$ls180.v:6655$2294_Y end - attribute \src "ls180.v:6654.100-6654.146" - cell $eq $eq$ls180.v:6654$2297 + attribute \src "ls180.v:6657.100-6657.146" + cell $eq $eq$ls180.v:6657$2297 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268654,10 +271183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6654$2297_Y + connect \Y $eq$ls180.v:6657$2297_Y end - attribute \src "ls180.v:6655.103-6655.149" - cell $eq $eq$ls180.v:6655$2301 + attribute \src "ls180.v:6658.103-6658.149" + cell $eq $eq$ls180.v:6658$2301 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268665,10 +271194,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6655$2301_Y + connect \Y $eq$ls180.v:6658$2301_Y end - attribute \src "ls180.v:6657.100-6657.146" - cell $eq $eq$ls180.v:6657$2304 + attribute \src "ls180.v:6660.100-6660.146" + cell $eq $eq$ls180.v:6660$2304 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268676,10 +271205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6657$2304_Y + connect \Y $eq$ls180.v:6660$2304_Y end - attribute \src "ls180.v:6658.103-6658.149" - cell $eq $eq$ls180.v:6658$2308 + attribute \src "ls180.v:6661.103-6661.149" + cell $eq $eq$ls180.v:6661$2308 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268687,10 +271216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6658$2308_Y + connect \Y $eq$ls180.v:6661$2308_Y end - attribute \src "ls180.v:6660.100-6660.146" - cell $eq $eq$ls180.v:6660$2311 + attribute \src "ls180.v:6663.100-6663.146" + cell $eq $eq$ls180.v:6663$2311 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268698,10 +271227,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6660$2311_Y + connect \Y $eq$ls180.v:6663$2311_Y end - attribute \src "ls180.v:6661.103-6661.149" - cell $eq $eq$ls180.v:6661$2315 + attribute \src "ls180.v:6664.103-6664.149" + cell $eq $eq$ls180.v:6664$2315 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268709,10 +271238,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6661$2315_Y + connect \Y $eq$ls180.v:6664$2315_Y end - attribute \src "ls180.v:6663.112-6663.158" - cell $eq $eq$ls180.v:6663$2318 + attribute \src "ls180.v:6666.112-6666.158" + cell $eq $eq$ls180.v:6666$2318 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268720,10 +271249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6663$2318_Y + connect \Y $eq$ls180.v:6666$2318_Y end - attribute \src "ls180.v:6664.115-6664.161" - cell $eq $eq$ls180.v:6664$2322 + attribute \src "ls180.v:6667.115-6667.161" + cell $eq $eq$ls180.v:6667$2322 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268731,10 +271260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6664$2322_Y + connect \Y $eq$ls180.v:6667$2322_Y end - attribute \src "ls180.v:6666.113-6666.159" - cell $eq $eq$ls180.v:6666$2325 + attribute \src "ls180.v:6669.113-6669.159" + cell $eq $eq$ls180.v:6669$2325 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268742,10 +271271,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6666$2325_Y + connect \Y $eq$ls180.v:6669$2325_Y end - attribute \src "ls180.v:6667.116-6667.162" - cell $eq $eq$ls180.v:6667$2329 + attribute \src "ls180.v:6670.116-6670.162" + cell $eq $eq$ls180.v:6670$2329 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268753,10 +271282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6667$2329_Y + connect \Y $eq$ls180.v:6670$2329_Y end - attribute \src "ls180.v:6669.104-6669.150" - cell $eq $eq$ls180.v:6669$2332 + attribute \src "ls180.v:6672.104-6672.150" + cell $eq $eq$ls180.v:6672$2332 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268764,10 +271293,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6669$2332_Y + connect \Y $eq$ls180.v:6672$2332_Y end - attribute \src "ls180.v:6670.107-6670.153" - cell $eq $eq$ls180.v:6670$2336 + attribute \src "ls180.v:6673.107-6673.153" + cell $eq $eq$ls180.v:6673$2336 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268775,10 +271304,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6670$2336_Y + connect \Y $eq$ls180.v:6673$2336_Y end - attribute \src "ls180.v:6687.33-6687.79" - cell $eq $eq$ls180.v:6687$2338 + attribute \src "ls180.v:6690.33-6690.79" + cell $eq $eq$ls180.v:6690$2338 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -268786,10 +271315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [13:8] connect \B 3'101 - connect \Y $eq$ls180.v:6687$2338_Y + connect \Y $eq$ls180.v:6690$2338_Y end - attribute \src "ls180.v:6689.90-6689.135" - cell $eq $eq$ls180.v:6689$2340 + attribute \src "ls180.v:6692.90-6692.135" + cell $eq $eq$ls180.v:6692$2340 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268797,10 +271326,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6689$2340_Y + connect \Y $eq$ls180.v:6692$2340_Y end - attribute \src "ls180.v:6690.93-6690.138" - cell $eq $eq$ls180.v:6690$2344 + attribute \src "ls180.v:6693.93-6693.138" + cell $eq $eq$ls180.v:6693$2344 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268808,10 +271337,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6690$2344_Y + connect \Y $eq$ls180.v:6693$2344_Y end - attribute \src "ls180.v:6692.100-6692.145" - cell $eq $eq$ls180.v:6692$2347 + attribute \src "ls180.v:6695.100-6695.145" + cell $eq $eq$ls180.v:6695$2347 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268819,10 +271348,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6692$2347_Y + connect \Y $eq$ls180.v:6695$2347_Y end - attribute \src "ls180.v:6693.103-6693.148" - cell $eq $eq$ls180.v:6693$2351 + attribute \src "ls180.v:6696.103-6696.148" + cell $eq $eq$ls180.v:6696$2351 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268830,10 +271359,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6693$2351_Y + connect \Y $eq$ls180.v:6696$2351_Y end - attribute \src "ls180.v:6695.101-6695.146" - cell $eq $eq$ls180.v:6695$2354 + attribute \src "ls180.v:6698.101-6698.146" + cell $eq $eq$ls180.v:6698$2354 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268841,10 +271370,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6695$2354_Y + connect \Y $eq$ls180.v:6698$2354_Y end - attribute \src "ls180.v:6696.104-6696.149" - cell $eq $eq$ls180.v:6696$2358 + attribute \src "ls180.v:6699.104-6699.149" + cell $eq $eq$ls180.v:6699$2358 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268852,10 +271381,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6696$2358_Y + connect \Y $eq$ls180.v:6699$2358_Y end - attribute \src "ls180.v:6698.105-6698.150" - cell $eq $eq$ls180.v:6698$2361 + attribute \src "ls180.v:6701.105-6701.150" + cell $eq $eq$ls180.v:6701$2361 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268863,10 +271392,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6698$2361_Y + connect \Y $eq$ls180.v:6701$2361_Y end - attribute \src "ls180.v:6699.108-6699.153" - cell $eq $eq$ls180.v:6699$2365 + attribute \src "ls180.v:6702.108-6702.153" + cell $eq $eq$ls180.v:6702$2365 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268874,10 +271403,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6699$2365_Y + connect \Y $eq$ls180.v:6702$2365_Y end - attribute \src "ls180.v:6701.106-6701.151" - cell $eq $eq$ls180.v:6701$2368 + attribute \src "ls180.v:6704.106-6704.151" + cell $eq $eq$ls180.v:6704$2368 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268885,10 +271414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6701$2368_Y + connect \Y $eq$ls180.v:6704$2368_Y end - attribute \src "ls180.v:6702.109-6702.154" - cell $eq $eq$ls180.v:6702$2372 + attribute \src "ls180.v:6705.109-6705.154" + cell $eq $eq$ls180.v:6705$2372 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268896,10 +271425,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6702$2372_Y + connect \Y $eq$ls180.v:6705$2372_Y end - attribute \src "ls180.v:6704.104-6704.149" - cell $eq $eq$ls180.v:6704$2375 + attribute \src "ls180.v:6707.104-6707.149" + cell $eq $eq$ls180.v:6707$2375 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268907,10 +271436,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6704$2375_Y + connect \Y $eq$ls180.v:6707$2375_Y end - attribute \src "ls180.v:6705.107-6705.152" - cell $eq $eq$ls180.v:6705$2379 + attribute \src "ls180.v:6708.107-6708.152" + cell $eq $eq$ls180.v:6708$2379 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268918,10 +271447,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6705$2379_Y + connect \Y $eq$ls180.v:6708$2379_Y end - attribute \src "ls180.v:6707.101-6707.146" - cell $eq $eq$ls180.v:6707$2382 + attribute \src "ls180.v:6710.101-6710.146" + cell $eq $eq$ls180.v:6710$2382 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268929,10 +271458,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6707$2382_Y + connect \Y $eq$ls180.v:6710$2382_Y end - attribute \src "ls180.v:6708.104-6708.149" - cell $eq $eq$ls180.v:6708$2386 + attribute \src "ls180.v:6711.104-6711.149" + cell $eq $eq$ls180.v:6711$2386 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268940,10 +271469,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6708$2386_Y + connect \Y $eq$ls180.v:6711$2386_Y end - attribute \src "ls180.v:6710.100-6710.145" - cell $eq $eq$ls180.v:6710$2389 + attribute \src "ls180.v:6713.100-6713.145" + cell $eq $eq$ls180.v:6713$2389 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268951,10 +271480,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6710$2389_Y + connect \Y $eq$ls180.v:6713$2389_Y end - attribute \src "ls180.v:6711.103-6711.148" - cell $eq $eq$ls180.v:6711$2393 + attribute \src "ls180.v:6714.103-6714.148" + cell $eq $eq$ls180.v:6714$2393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -268962,10 +271491,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6711$2393_Y + connect \Y $eq$ls180.v:6714$2393_Y end - attribute \src "ls180.v:6721.33-6721.79" - cell $eq $eq$ls180.v:6721$2395 + attribute \src "ls180.v:6724.33-6724.79" + cell $eq $eq$ls180.v:6724$2395 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -268973,10 +271502,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [13:8] connect \B 3'100 - connect \Y $eq$ls180.v:6721$2395_Y + connect \Y $eq$ls180.v:6724$2395_Y end - attribute \src "ls180.v:6723.106-6723.151" - cell $eq $eq$ls180.v:6723$2397 + attribute \src "ls180.v:6726.106-6726.151" + cell $eq $eq$ls180.v:6726$2397 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -268984,10 +271513,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6723$2397_Y + connect \Y $eq$ls180.v:6726$2397_Y end - attribute \src "ls180.v:6724.109-6724.154" - cell $eq $eq$ls180.v:6724$2401 + attribute \src "ls180.v:6727.109-6727.154" + cell $eq $eq$ls180.v:6727$2401 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -268995,10 +271524,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6724$2401_Y + connect \Y $eq$ls180.v:6727$2401_Y end - attribute \src "ls180.v:6726.106-6726.151" - cell $eq $eq$ls180.v:6726$2404 + attribute \src "ls180.v:6729.106-6729.151" + cell $eq $eq$ls180.v:6729$2404 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269006,10 +271535,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6726$2404_Y + connect \Y $eq$ls180.v:6729$2404_Y end - attribute \src "ls180.v:6727.109-6727.154" - cell $eq $eq$ls180.v:6727$2408 + attribute \src "ls180.v:6730.109-6730.154" + cell $eq $eq$ls180.v:6730$2408 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269017,10 +271546,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6727$2408_Y + connect \Y $eq$ls180.v:6730$2408_Y end - attribute \src "ls180.v:6729.106-6729.151" - cell $eq $eq$ls180.v:6729$2411 + attribute \src "ls180.v:6732.106-6732.151" + cell $eq $eq$ls180.v:6732$2411 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269028,10 +271557,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6729$2411_Y + connect \Y $eq$ls180.v:6732$2411_Y end - attribute \src "ls180.v:6730.109-6730.154" - cell $eq $eq$ls180.v:6730$2415 + attribute \src "ls180.v:6733.109-6733.154" + cell $eq $eq$ls180.v:6733$2415 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269039,10 +271568,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6730$2415_Y + connect \Y $eq$ls180.v:6733$2415_Y end - attribute \src "ls180.v:6732.106-6732.151" - cell $eq $eq$ls180.v:6732$2418 + attribute \src "ls180.v:6735.106-6735.151" + cell $eq $eq$ls180.v:6735$2418 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269050,10 +271579,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6732$2418_Y + connect \Y $eq$ls180.v:6735$2418_Y end - attribute \src "ls180.v:6733.109-6733.154" - cell $eq $eq$ls180.v:6733$2422 + attribute \src "ls180.v:6736.109-6736.154" + cell $eq $eq$ls180.v:6736$2422 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269061,10 +271590,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6733$2422_Y + connect \Y $eq$ls180.v:6736$2422_Y end - attribute \src "ls180.v:7114.41-7114.81" - cell $eq $eq$ls180.v:7114$2459 + attribute \src "ls180.v:7117.41-7117.81" + cell $eq $eq$ls180.v:7117$2459 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269072,10 +271601,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:7114$2459_Y + connect \Y $eq$ls180.v:7117$2459_Y end - attribute \src "ls180.v:7114.144-7114.177" - cell $eq $eq$ls180.v:7114$2460 + attribute \src "ls180.v:7117.144-7117.177" + cell $eq $eq$ls180.v:7117$2460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269083,10 +271612,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7114$2460_Y + connect \Y $eq$ls180.v:7117$2460_Y end - attribute \src "ls180.v:7114.219-7114.252" - cell $eq $eq$ls180.v:7114$2463 + attribute \src "ls180.v:7117.219-7117.252" + cell $eq $eq$ls180.v:7117$2463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269094,10 +271623,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7114$2463_Y + connect \Y $eq$ls180.v:7117$2463_Y end - attribute \src "ls180.v:7114.294-7114.327" - cell $eq $eq$ls180.v:7114$2466 + attribute \src "ls180.v:7117.294-7117.327" + cell $eq $eq$ls180.v:7117$2466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269105,10 +271634,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7114$2466_Y + connect \Y $eq$ls180.v:7117$2466_Y end - attribute \src "ls180.v:7138.41-7138.81" - cell $eq $eq$ls180.v:7138$2475 + attribute \src "ls180.v:7141.41-7141.81" + cell $eq $eq$ls180.v:7141$2475 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269116,10 +271645,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:7138$2475_Y + connect \Y $eq$ls180.v:7141$2475_Y end - attribute \src "ls180.v:7138.144-7138.177" - cell $eq $eq$ls180.v:7138$2476 + attribute \src "ls180.v:7141.144-7141.177" + cell $eq $eq$ls180.v:7141$2476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269127,10 +271656,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7138$2476_Y + connect \Y $eq$ls180.v:7141$2476_Y end - attribute \src "ls180.v:7138.219-7138.252" - cell $eq $eq$ls180.v:7138$2479 + attribute \src "ls180.v:7141.219-7141.252" + cell $eq $eq$ls180.v:7141$2479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269138,10 +271667,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7138$2479_Y + connect \Y $eq$ls180.v:7141$2479_Y end - attribute \src "ls180.v:7138.294-7138.327" - cell $eq $eq$ls180.v:7138$2482 + attribute \src "ls180.v:7141.294-7141.327" + cell $eq $eq$ls180.v:7141$2482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269149,10 +271678,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7138$2482_Y + connect \Y $eq$ls180.v:7141$2482_Y end - attribute \src "ls180.v:7162.41-7162.81" - cell $eq $eq$ls180.v:7162$2491 + attribute \src "ls180.v:7165.41-7165.81" + cell $eq $eq$ls180.v:7165$2491 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269160,10 +271689,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:7162$2491_Y + connect \Y $eq$ls180.v:7165$2491_Y end - attribute \src "ls180.v:7162.144-7162.177" - cell $eq $eq$ls180.v:7162$2492 + attribute \src "ls180.v:7165.144-7165.177" + cell $eq $eq$ls180.v:7165$2492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269171,10 +271700,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7162$2492_Y + connect \Y $eq$ls180.v:7165$2492_Y end - attribute \src "ls180.v:7162.219-7162.252" - cell $eq $eq$ls180.v:7162$2495 + attribute \src "ls180.v:7165.219-7165.252" + cell $eq $eq$ls180.v:7165$2495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269182,10 +271711,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7162$2495_Y + connect \Y $eq$ls180.v:7165$2495_Y end - attribute \src "ls180.v:7162.294-7162.327" - cell $eq $eq$ls180.v:7162$2498 + attribute \src "ls180.v:7165.294-7165.327" + cell $eq $eq$ls180.v:7165$2498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269193,10 +271722,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7162$2498_Y + connect \Y $eq$ls180.v:7165$2498_Y end - attribute \src "ls180.v:7186.41-7186.81" - cell $eq $eq$ls180.v:7186$2507 + attribute \src "ls180.v:7189.41-7189.81" + cell $eq $eq$ls180.v:7189$2507 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269204,10 +271733,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:7186$2507_Y + connect \Y $eq$ls180.v:7189$2507_Y end - attribute \src "ls180.v:7186.144-7186.177" - cell $eq $eq$ls180.v:7186$2508 + attribute \src "ls180.v:7189.144-7189.177" + cell $eq $eq$ls180.v:7189$2508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269215,10 +271744,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7186$2508_Y + connect \Y $eq$ls180.v:7189$2508_Y end - attribute \src "ls180.v:7186.219-7186.252" - cell $eq $eq$ls180.v:7186$2511 + attribute \src "ls180.v:7189.219-7189.252" + cell $eq $eq$ls180.v:7189$2511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269226,10 +271755,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7186$2511_Y + connect \Y $eq$ls180.v:7189$2511_Y end - attribute \src "ls180.v:7186.294-7186.327" - cell $eq $eq$ls180.v:7186$2514 + attribute \src "ls180.v:7189.294-7189.327" + cell $eq $eq$ls180.v:7189$2514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269237,10 +271766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7186$2514_Y + connect \Y $eq$ls180.v:7189$2514_Y end - attribute \src "ls180.v:7770.8-7770.38" - cell $eq $eq$ls180.v:7770$2606 + attribute \src "ls180.v:7773.8-7773.38" + cell $eq $eq$ls180.v:7773$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -269248,10 +271777,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7770$2606_Y + connect \Y $eq$ls180.v:7773$2606_Y end - attribute \src "ls180.v:7817.8-7817.42" - cell $eq $eq$ls180.v:7817$2626 + attribute \src "ls180.v:7820.8-7820.42" + cell $eq $eq$ls180.v:7820$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269259,10 +271788,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7817$2626_Y + connect \Y $eq$ls180.v:7820$2626_Y end - attribute \src "ls180.v:7837.38-7837.74" - cell $eq $eq$ls180.v:7837$2629 + attribute \src "ls180.v:7840.38-7840.74" + cell $eq $eq$ls180.v:7840$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269270,10 +271799,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7837$2629_Y + connect \Y $eq$ls180.v:7840$2629_Y end - attribute \src "ls180.v:7844.7-7844.43" - cell $eq $eq$ls180.v:7844$2631 + attribute \src "ls180.v:7847.7-7847.43" + cell $eq $eq$ls180.v:7847$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269281,10 +271810,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7844$2631_Y + connect \Y $eq$ls180.v:7847$2631_Y end - attribute \src "ls180.v:7851.7-7851.43" - cell $eq $eq$ls180.v:7851$2632 + attribute \src "ls180.v:7854.7-7854.43" + cell $eq $eq$ls180.v:7854$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269292,10 +271821,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7851$2632_Y + connect \Y $eq$ls180.v:7854$2632_Y end - attribute \src "ls180.v:7859.7-7859.43" - cell $eq $eq$ls180.v:7859$2633 + attribute \src "ls180.v:7862.7-7862.43" + cell $eq $eq$ls180.v:7862$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269303,10 +271832,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7859$2633_Y + connect \Y $eq$ls180.v:7862$2633_Y end - attribute \src "ls180.v:7911.9-7911.54" - cell $eq $eq$ls180.v:7911$2651 + attribute \src "ls180.v:7914.9-7914.54" + cell $eq $eq$ls180.v:7914$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269314,10 +271843,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7911$2651_Y + connect \Y $eq$ls180.v:7914$2651_Y end - attribute \src "ls180.v:7957.9-7957.54" - cell $eq $eq$ls180.v:7957$2667 + attribute \src "ls180.v:7960.9-7960.54" + cell $eq $eq$ls180.v:7960$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269325,10 +271854,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7957$2667_Y + connect \Y $eq$ls180.v:7960$2667_Y end - attribute \src "ls180.v:8003.9-8003.54" - cell $eq $eq$ls180.v:8003$2683 + attribute \src "ls180.v:8006.9-8006.54" + cell $eq $eq$ls180.v:8006$2683 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269336,10 +271865,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8003$2683_Y + connect \Y $eq$ls180.v:8006$2683_Y end - attribute \src "ls180.v:8049.9-8049.54" - cell $eq $eq$ls180.v:8049$2699 + attribute \src "ls180.v:8052.9-8052.54" + cell $eq $eq$ls180.v:8052$2699 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269347,10 +271876,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8049$2699_Y + connect \Y $eq$ls180.v:8052$2699_Y end - attribute \src "ls180.v:8199.9-8199.41" - cell $eq $eq$ls180.v:8199$2711 + attribute \src "ls180.v:8202.9-8202.41" + cell $eq $eq$ls180.v:8202$2711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269358,10 +271887,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8199$2711_Y + connect \Y $eq$ls180.v:8202$2711_Y end - attribute \src "ls180.v:8214.9-8214.41" - cell $eq $eq$ls180.v:8214$2714 + attribute \src "ls180.v:8217.9-8217.41" + cell $eq $eq$ls180.v:8217$2714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269369,10 +271898,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8214$2714_Y + connect \Y $eq$ls180.v:8217$2714_Y end - attribute \src "ls180.v:8220.49-8220.82" - cell $eq $eq$ls180.v:8220$2715 + attribute \src "ls180.v:8223.49-8223.82" + cell $eq $eq$ls180.v:8223$2715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269380,10 +271909,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8220$2715_Y + connect \Y $eq$ls180.v:8223$2715_Y end - attribute \src "ls180.v:8220.131-8220.164" - cell $eq $eq$ls180.v:8220$2718 + attribute \src "ls180.v:8223.131-8223.164" + cell $eq $eq$ls180.v:8223$2718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269391,10 +271920,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8220$2718_Y + connect \Y $eq$ls180.v:8223$2718_Y end - attribute \src "ls180.v:8220.213-8220.246" - cell $eq $eq$ls180.v:8220$2721 + attribute \src "ls180.v:8223.213-8223.246" + cell $eq $eq$ls180.v:8223$2721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269402,10 +271931,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8220$2721_Y + connect \Y $eq$ls180.v:8223$2721_Y end - attribute \src "ls180.v:8220.295-8220.328" - cell $eq $eq$ls180.v:8220$2724 + attribute \src "ls180.v:8223.295-8223.328" + cell $eq $eq$ls180.v:8223$2724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269413,10 +271942,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8220$2724_Y + connect \Y $eq$ls180.v:8223$2724_Y end - attribute \src "ls180.v:8221.50-8221.83" - cell $eq $eq$ls180.v:8221$2727 + attribute \src "ls180.v:8224.50-8224.83" + cell $eq $eq$ls180.v:8224$2727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269424,10 +271953,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8221$2727_Y + connect \Y $eq$ls180.v:8224$2727_Y end - attribute \src "ls180.v:8221.132-8221.165" - cell $eq $eq$ls180.v:8221$2730 + attribute \src "ls180.v:8224.132-8224.165" + cell $eq $eq$ls180.v:8224$2730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269435,10 +271964,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8221$2730_Y + connect \Y $eq$ls180.v:8224$2730_Y end - attribute \src "ls180.v:8221.214-8221.247" - cell $eq $eq$ls180.v:8221$2733 + attribute \src "ls180.v:8224.214-8224.247" + cell $eq $eq$ls180.v:8224$2733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269446,10 +271975,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8221$2733_Y + connect \Y $eq$ls180.v:8224$2733_Y end - attribute \src "ls180.v:8221.296-8221.329" - cell $eq $eq$ls180.v:8221$2736 + attribute \src "ls180.v:8224.296-8224.329" + cell $eq $eq$ls180.v:8224$2736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269457,10 +271986,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8221$2736_Y + connect \Y $eq$ls180.v:8224$2736_Y end - attribute \src "ls180.v:8256.9-8256.42" - cell $eq $eq$ls180.v:8256$2748 + attribute \src "ls180.v:8259.9-8259.42" + cell $eq $eq$ls180.v:8259$2748 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269468,10 +271997,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:8256$2748_Y + connect \Y $eq$ls180.v:8259$2748_Y end - attribute \src "ls180.v:8259.10-8259.43" - cell $eq $eq$ls180.v:8259$2749 + attribute \src "ls180.v:8262.10-8262.43" + cell $eq $eq$ls180.v:8262$2749 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269479,10 +272008,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8259$2749_Y + connect \Y $eq$ls180.v:8262$2749_Y end - attribute \src "ls180.v:8285.9-8285.42" - cell $eq $eq$ls180.v:8285$2755 + attribute \src "ls180.v:8288.9-8288.42" + cell $eq $eq$ls180.v:8288$2755 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269490,10 +272019,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:8285$2755_Y + connect \Y $eq$ls180.v:8288$2755_Y end - attribute \src "ls180.v:8290.10-8290.43" - cell $eq $eq$ls180.v:8290$2756 + attribute \src "ls180.v:8293.10-8293.43" + cell $eq $eq$ls180.v:8293$2756 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269501,10 +272030,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8290$2756_Y + connect \Y $eq$ls180.v:8293$2756_Y end - attribute \src "ls180.v:8497.9-8497.53" - cell $eq $eq$ls180.v:8497$2805 + attribute \src "ls180.v:8500.9-8500.53" + cell $eq $eq$ls180.v:8500$2805 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269512,10 +272041,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8497$2805_Y + connect \Y $eq$ls180.v:8500$2805_Y end - attribute \src "ls180.v:8578.9-8578.54" - cell $eq $eq$ls180.v:8578$2817 + attribute \src "ls180.v:8581.9-8581.54" + cell $eq $eq$ls180.v:8581$2817 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269523,10 +272052,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8578$2817_Y + connect \Y $eq$ls180.v:8581$2817_Y end - attribute \src "ls180.v:8657.9-8657.55" - cell $eq $eq$ls180.v:8657$2829 + attribute \src "ls180.v:8660.9-8660.55" + cell $eq $eq$ls180.v:8660$2829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269534,10 +272063,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8657$2829_Y + connect \Y $eq$ls180.v:8660$2829_Y end - attribute \src "ls180.v:8880.9-8880.49" - cell $eq $eq$ls180.v:8880$2862 + attribute \src "ls180.v:8883.9-8883.49" + cell $eq $eq$ls180.v:8883$2862 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269545,32 +272074,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8880$2862_Y + connect \Y $eq$ls180.v:8883$2862_Y end - attribute \src "ls180.v:8456.8-8456.54" - cell $ge $ge$ls180.v:8456$2797 + attribute \src "ls180.v:8459.8-8459.54" + cell $ge $ge$ls180.v:8459$2797 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8456$2796_Y - connect \Y $ge$ls180.v:8456$2797_Y + connect \B $sub$ls180.v:8459$2796_Y + connect \Y $ge$ls180.v:8459$2797_Y end - attribute \src "ls180.v:8470.8-8470.54" - cell $ge $ge$ls180.v:8470$2801 + attribute \src "ls180.v:8473.8-8473.54" + cell $ge $ge$ls180.v:8473$2801 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8470$2800_Y - connect \Y $ge$ls180.v:8470$2801_Y + connect \B $sub$ls180.v:8473$2800_Y + connect \Y $ge$ls180.v:8473$2801_Y end - attribute \src "ls180.v:5339.47-5339.83" - cell $gt $gt$ls180.v:5339$1064 + attribute \src "ls180.v:5342.47-5342.83" + cell $gt $gt$ls180.v:5342$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269578,10 +272107,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $gt$ls180.v:5339$1064_Y + connect \Y $gt$ls180.v:5342$1064_Y end - attribute \src "ls180.v:5345.7-5345.43" - cell $lt $lt$ls180.v:5345$1067 + attribute \src "ls180.v:5348.7-5348.43" + cell $lt $lt$ls180.v:5348$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269589,10 +272118,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1000 - connect \Y $lt$ls180.v:5345$1067_Y + connect \Y $lt$ls180.v:5348$1067_Y end - attribute \src "ls180.v:8451.8-8451.43" - cell $lt $lt$ls180.v:8451$2795 + attribute \src "ls180.v:8454.8-8454.43" + cell $lt $lt$ls180.v:8454$2795 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -269600,10 +272129,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8451$2795_Y + connect \Y $lt$ls180.v:8454$2795_Y end - attribute \src "ls180.v:8465.8-8465.43" - cell $lt $lt$ls180.v:8465$2799 + attribute \src "ls180.v:8468.8-8468.43" + cell $lt $lt$ls180.v:8468$2799 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -269611,10 +272140,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8465$2799_Y + connect \Y $lt$ls180.v:8468$2799_Y end - attribute \src "ls180.v:10370.33-10370.36" - cell $memrd $memrd$\mem$ls180.v:10370$2916 + attribute \src "ls180.v:10373.33-10373.36" + cell $memrd $memrd$\mem$ls180.v:10373$2916 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269623,11 +272152,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10370$2916_DATA + connect \DATA $memrd$\mem$ls180.v:10373$2916_DATA connect \EN 1'x end - attribute \src "ls180.v:10398.27-10398.32" - cell $memrd $memrd$\mem_1$ls180.v:10398$2942 + attribute \src "ls180.v:10401.27-10401.32" + cell $memrd $memrd$\mem_1$ls180.v:10401$2942 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269636,11 +272165,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_1 connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10398$2942_DATA + connect \DATA $memrd$\mem_1$ls180.v:10401$2942_DATA connect \EN 1'x end - attribute \src "ls180.v:10426.27-10426.32" - cell $memrd $memrd$\mem_2$ls180.v:10426$2968 + attribute \src "ls180.v:10429.27-10429.32" + cell $memrd $memrd$\mem_2$ls180.v:10429$2968 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269649,11 +272178,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_2 connect \CLK 1'x - connect \DATA $memrd$\mem_2$ls180.v:10426$2968_DATA + connect \DATA $memrd$\mem_2$ls180.v:10429$2968_DATA connect \EN 1'x end - attribute \src "ls180.v:10454.27-10454.32" - cell $memrd $memrd$\mem_3$ls180.v:10454$2994 + attribute \src "ls180.v:10457.27-10457.32" + cell $memrd $memrd$\mem_3$ls180.v:10457$2994 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269662,11 +272191,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_3 connect \CLK 1'x - connect \DATA $memrd$\mem_3$ls180.v:10454$2994_DATA + connect \DATA $memrd$\mem_3$ls180.v:10457$2994_DATA connect \EN 1'x end - attribute \src "ls180.v:10482.27-10482.32" - cell $memrd $memrd$\mem_4$ls180.v:10482$3020 + attribute \src "ls180.v:10485.27-10485.32" + cell $memrd $memrd$\mem_4$ls180.v:10485$3020 parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269675,11 +272204,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_4 connect \CLK 1'x - connect \DATA $memrd$\mem_4$ls180.v:10482$3020_DATA + connect \DATA $memrd$\mem_4$ls180.v:10485$3020_DATA connect \EN 1'x end - attribute \src "ls180.v:10493.12-10493.19" - cell $memrd $memrd$\storage$ls180.v:10493$3025 + attribute \src "ls180.v:10496.12-10496.19" + cell $memrd $memrd$\storage$ls180.v:10496$3025 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269688,11 +272217,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10493$3025_DATA + connect \DATA $memrd$\storage$ls180.v:10496$3025_DATA connect \EN 1'x end - attribute \src "ls180.v:10500.68-10500.75" - cell $memrd $memrd$\storage$ls180.v:10500$3027 + attribute \src "ls180.v:10503.68-10503.75" + cell $memrd $memrd$\storage$ls180.v:10503$3027 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269701,11 +272230,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10500$3027_DATA + connect \DATA $memrd$\storage$ls180.v:10503$3027_DATA connect \EN 1'x end - attribute \src "ls180.v:10507.14-10507.23" - cell $memrd $memrd$\storage_1$ls180.v:10507$3032 + attribute \src "ls180.v:10510.14-10510.23" + cell $memrd $memrd$\storage_1$ls180.v:10510$3032 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269714,11 +272243,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10507$3032_DATA + connect \DATA $memrd$\storage_1$ls180.v:10510$3032_DATA connect \EN 1'x end - attribute \src "ls180.v:10514.68-10514.77" - cell $memrd $memrd$\storage_1$ls180.v:10514$3034 + attribute \src "ls180.v:10517.68-10517.77" + cell $memrd $memrd$\storage_1$ls180.v:10517$3034 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269727,11 +272256,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10514$3034_DATA + connect \DATA $memrd$\storage_1$ls180.v:10517$3034_DATA connect \EN 1'x end - attribute \src "ls180.v:10521.14-10521.23" - cell $memrd $memrd$\storage_2$ls180.v:10521$3039 + attribute \src "ls180.v:10524.14-10524.23" + cell $memrd $memrd$\storage_2$ls180.v:10524$3039 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269740,11 +272269,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10521$3039_DATA + connect \DATA $memrd$\storage_2$ls180.v:10524$3039_DATA connect \EN 1'x end - attribute \src "ls180.v:10528.68-10528.77" - cell $memrd $memrd$\storage_2$ls180.v:10528$3041 + attribute \src "ls180.v:10531.68-10531.77" + cell $memrd $memrd$\storage_2$ls180.v:10531$3041 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269753,11 +272282,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10528$3041_DATA + connect \DATA $memrd$\storage_2$ls180.v:10531$3041_DATA connect \EN 1'x end - attribute \src "ls180.v:10535.14-10535.23" - cell $memrd $memrd$\storage_3$ls180.v:10535$3046 + attribute \src "ls180.v:10538.14-10538.23" + cell $memrd $memrd$\storage_3$ls180.v:10538$3046 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269766,11 +272295,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10535$3046_DATA + connect \DATA $memrd$\storage_3$ls180.v:10538$3046_DATA connect \EN 1'x end - attribute \src "ls180.v:10542.68-10542.77" - cell $memrd $memrd$\storage_3$ls180.v:10542$3048 + attribute \src "ls180.v:10545.68-10545.77" + cell $memrd $memrd$\storage_3$ls180.v:10545$3048 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269779,11 +272308,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10542$3048_DATA + connect \DATA $memrd$\storage_3$ls180.v:10545$3048_DATA connect \EN 1'x end - attribute \src "ls180.v:10550.14-10550.23" - cell $memrd $memrd$\storage_4$ls180.v:10550$3053 + attribute \src "ls180.v:10553.14-10553.23" + cell $memrd $memrd$\storage_4$ls180.v:10553$3053 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269792,11 +272321,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10550$3053_DATA + connect \DATA $memrd$\storage_4$ls180.v:10553$3053_DATA connect \EN 1'x end - attribute \src "ls180.v:10555.15-10555.24" - cell $memrd $memrd$\storage_4$ls180.v:10555$3055 + attribute \src "ls180.v:10558.15-10558.24" + cell $memrd $memrd$\storage_4$ls180.v:10558$3055 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269805,11 +272334,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10555$3055_DATA + connect \DATA $memrd$\storage_4$ls180.v:10558$3055_DATA connect \EN 1'x end - attribute \src "ls180.v:10567.14-10567.23" - cell $memrd $memrd$\storage_5$ls180.v:10567$3060 + attribute \src "ls180.v:10570.14-10570.23" + cell $memrd $memrd$\storage_5$ls180.v:10570$3060 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269818,11 +272347,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10567$3060_DATA + connect \DATA $memrd$\storage_5$ls180.v:10570$3060_DATA connect \EN 1'x end - attribute \src "ls180.v:10572.15-10572.24" - cell $memrd $memrd$\storage_5$ls180.v:10572$3062 + attribute \src "ls180.v:10575.15-10575.24" + cell $memrd $memrd$\storage_5$ls180.v:10575$3062 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269831,11 +272360,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10572$3062_DATA + connect \DATA $memrd$\storage_5$ls180.v:10575$3062_DATA connect \EN 1'x end - attribute \src "ls180.v:10583.14-10583.23" - cell $memrd $memrd$\storage_6$ls180.v:10583$3067 + attribute \src "ls180.v:10586.14-10586.23" + cell $memrd $memrd$\storage_6$ls180.v:10586$3067 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269844,11 +272373,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10583$3067_DATA + connect \DATA $memrd$\storage_6$ls180.v:10586$3067_DATA connect \EN 1'x end - attribute \src "ls180.v:10590.45-10590.54" - cell $memrd $memrd$\storage_6$ls180.v:10590$3069 + attribute \src "ls180.v:10593.45-10593.54" + cell $memrd $memrd$\storage_6$ls180.v:10593$3069 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269857,11 +272386,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10590$3069_DATA + connect \DATA $memrd$\storage_6$ls180.v:10593$3069_DATA connect \EN 1'x end - attribute \src "ls180.v:10597.14-10597.23" - cell $memrd $memrd$\storage_7$ls180.v:10597$3074 + attribute \src "ls180.v:10600.14-10600.23" + cell $memrd $memrd$\storage_7$ls180.v:10600$3074 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269870,11 +272399,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10597$3074_DATA + connect \DATA $memrd$\storage_7$ls180.v:10600$3074_DATA connect \EN 1'x end - attribute \src "ls180.v:10604.45-10604.54" - cell $memrd $memrd$\storage_7$ls180.v:10604$3076 + attribute \src "ls180.v:10607.45-10607.54" + cell $memrd $memrd$\storage_7$ls180.v:10607$3076 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -269883,7 +272412,7 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10604$3076_DATA + connect \DATA $memrd$\storage_7$ls180.v:10607$3076_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" @@ -269894,10 +272423,10 @@ module \ls180 parameter \MEMID "\\mem" parameter \PRIORITY 3078 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10352$1_ADDR + connect \ADDR $memwr$\mem$ls180.v:10355$1_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10352$1_DATA - connect \EN $memwr$\mem$ls180.v:10352$1_EN + connect \DATA $memwr$\mem$ls180.v:10355$1_DATA + connect \EN $memwr$\mem$ls180.v:10355$1_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$3079 @@ -269907,10 +272436,10 @@ module \ls180 parameter \MEMID "\\mem" parameter \PRIORITY 3079 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10354$2_ADDR + connect \ADDR $memwr$\mem$ls180.v:10357$2_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10354$2_DATA - connect \EN $memwr$\mem$ls180.v:10354$2_EN + connect \DATA $memwr$\mem$ls180.v:10357$2_DATA + connect \EN $memwr$\mem$ls180.v:10357$2_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$3080 @@ -269920,10 +272449,10 @@ module \ls180 parameter \MEMID "\\mem" parameter \PRIORITY 3080 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10356$3_ADDR + connect \ADDR $memwr$\mem$ls180.v:10359$3_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10356$3_DATA - connect \EN $memwr$\mem$ls180.v:10356$3_EN + connect \DATA $memwr$\mem$ls180.v:10359$3_DATA + connect \EN $memwr$\mem$ls180.v:10359$3_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$3081 @@ -269933,10 +272462,10 @@ module \ls180 parameter \MEMID "\\mem" parameter \PRIORITY 3081 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10358$4_ADDR + connect \ADDR $memwr$\mem$ls180.v:10361$4_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10358$4_DATA - connect \EN $memwr$\mem$ls180.v:10358$4_EN + connect \DATA $memwr$\mem$ls180.v:10361$4_DATA + connect \EN $memwr$\mem$ls180.v:10361$4_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$3082 @@ -269946,10 +272475,10 @@ module \ls180 parameter \MEMID "\\mem" parameter \PRIORITY 3082 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10360$5_ADDR + connect \ADDR $memwr$\mem$ls180.v:10363$5_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10360$5_DATA - connect \EN $memwr$\mem$ls180.v:10360$5_EN + connect \DATA $memwr$\mem$ls180.v:10363$5_DATA + connect \EN $memwr$\mem$ls180.v:10363$5_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$3083 @@ -269959,10 +272488,10 @@ module \ls180 parameter \MEMID "\\mem" parameter \PRIORITY 3083 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10362$6_ADDR + connect \ADDR $memwr$\mem$ls180.v:10365$6_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10362$6_DATA - connect \EN $memwr$\mem$ls180.v:10362$6_EN + connect \DATA $memwr$\mem$ls180.v:10365$6_DATA + connect \EN $memwr$\mem$ls180.v:10365$6_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$3084 @@ -269972,10 +272501,10 @@ module \ls180 parameter \MEMID "\\mem" parameter \PRIORITY 3084 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10364$7_ADDR + connect \ADDR $memwr$\mem$ls180.v:10367$7_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10364$7_DATA - connect \EN $memwr$\mem$ls180.v:10364$7_EN + connect \DATA $memwr$\mem$ls180.v:10367$7_DATA + connect \EN $memwr$\mem$ls180.v:10367$7_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem$ls180.v:0$3085 @@ -269985,10 +272514,10 @@ module \ls180 parameter \MEMID "\\mem" parameter \PRIORITY 3085 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10366$8_ADDR + connect \ADDR $memwr$\mem$ls180.v:10369$8_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10366$8_DATA - connect \EN $memwr$\mem$ls180.v:10366$8_EN + connect \DATA $memwr$\mem$ls180.v:10369$8_DATA + connect \EN $memwr$\mem$ls180.v:10369$8_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_1$ls180.v:0$3086 @@ -269998,10 +272527,10 @@ module \ls180 parameter \MEMID "\\mem_1" parameter \PRIORITY 3086 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10380$9_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10383$9_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10380$9_DATA - connect \EN $memwr$\mem_1$ls180.v:10380$9_EN + connect \DATA $memwr$\mem_1$ls180.v:10383$9_DATA + connect \EN $memwr$\mem_1$ls180.v:10383$9_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_1$ls180.v:0$3087 @@ -270011,10 +272540,10 @@ module \ls180 parameter \MEMID "\\mem_1" parameter \PRIORITY 3087 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10382$10_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10385$10_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10382$10_DATA - connect \EN $memwr$\mem_1$ls180.v:10382$10_EN + connect \DATA $memwr$\mem_1$ls180.v:10385$10_DATA + connect \EN $memwr$\mem_1$ls180.v:10385$10_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_1$ls180.v:0$3088 @@ -270024,10 +272553,10 @@ module \ls180 parameter \MEMID "\\mem_1" parameter \PRIORITY 3088 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10384$11_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10387$11_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10384$11_DATA - connect \EN $memwr$\mem_1$ls180.v:10384$11_EN + connect \DATA $memwr$\mem_1$ls180.v:10387$11_DATA + connect \EN $memwr$\mem_1$ls180.v:10387$11_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_1$ls180.v:0$3089 @@ -270037,10 +272566,10 @@ module \ls180 parameter \MEMID "\\mem_1" parameter \PRIORITY 3089 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10386$12_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10389$12_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10386$12_DATA - connect \EN $memwr$\mem_1$ls180.v:10386$12_EN + connect \DATA $memwr$\mem_1$ls180.v:10389$12_DATA + connect \EN $memwr$\mem_1$ls180.v:10389$12_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_1$ls180.v:0$3090 @@ -270050,10 +272579,10 @@ module \ls180 parameter \MEMID "\\mem_1" parameter \PRIORITY 3090 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10388$13_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10391$13_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10388$13_DATA - connect \EN $memwr$\mem_1$ls180.v:10388$13_EN + connect \DATA $memwr$\mem_1$ls180.v:10391$13_DATA + connect \EN $memwr$\mem_1$ls180.v:10391$13_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_1$ls180.v:0$3091 @@ -270063,10 +272592,10 @@ module \ls180 parameter \MEMID "\\mem_1" parameter \PRIORITY 3091 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10390$14_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10393$14_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10390$14_DATA - connect \EN $memwr$\mem_1$ls180.v:10390$14_EN + connect \DATA $memwr$\mem_1$ls180.v:10393$14_DATA + connect \EN $memwr$\mem_1$ls180.v:10393$14_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_1$ls180.v:0$3092 @@ -270076,10 +272605,10 @@ module \ls180 parameter \MEMID "\\mem_1" parameter \PRIORITY 3092 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10392$15_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10395$15_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10392$15_DATA - connect \EN $memwr$\mem_1$ls180.v:10392$15_EN + connect \DATA $memwr$\mem_1$ls180.v:10395$15_DATA + connect \EN $memwr$\mem_1$ls180.v:10395$15_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_1$ls180.v:0$3093 @@ -270089,10 +272618,10 @@ module \ls180 parameter \MEMID "\\mem_1" parameter \PRIORITY 3093 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10394$16_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10397$16_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10394$16_DATA - connect \EN $memwr$\mem_1$ls180.v:10394$16_EN + connect \DATA $memwr$\mem_1$ls180.v:10397$16_DATA + connect \EN $memwr$\mem_1$ls180.v:10397$16_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_2$ls180.v:0$3094 @@ -270102,10 +272631,10 @@ module \ls180 parameter \MEMID "\\mem_2" parameter \PRIORITY 3094 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10408$17_ADDR + connect \ADDR $memwr$\mem_2$ls180.v:10411$17_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10408$17_DATA - connect \EN $memwr$\mem_2$ls180.v:10408$17_EN + connect \DATA $memwr$\mem_2$ls180.v:10411$17_DATA + connect \EN $memwr$\mem_2$ls180.v:10411$17_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_2$ls180.v:0$3095 @@ -270115,10 +272644,10 @@ module \ls180 parameter \MEMID "\\mem_2" parameter \PRIORITY 3095 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10410$18_ADDR + connect \ADDR $memwr$\mem_2$ls180.v:10413$18_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10410$18_DATA - connect \EN $memwr$\mem_2$ls180.v:10410$18_EN + connect \DATA $memwr$\mem_2$ls180.v:10413$18_DATA + connect \EN $memwr$\mem_2$ls180.v:10413$18_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_2$ls180.v:0$3096 @@ -270128,10 +272657,10 @@ module \ls180 parameter \MEMID "\\mem_2" parameter \PRIORITY 3096 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10412$19_ADDR + connect \ADDR $memwr$\mem_2$ls180.v:10415$19_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10412$19_DATA - connect \EN $memwr$\mem_2$ls180.v:10412$19_EN + connect \DATA $memwr$\mem_2$ls180.v:10415$19_DATA + connect \EN $memwr$\mem_2$ls180.v:10415$19_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_2$ls180.v:0$3097 @@ -270141,10 +272670,10 @@ module \ls180 parameter \MEMID "\\mem_2" parameter \PRIORITY 3097 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10414$20_ADDR + connect \ADDR $memwr$\mem_2$ls180.v:10417$20_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10414$20_DATA - connect \EN $memwr$\mem_2$ls180.v:10414$20_EN + connect \DATA $memwr$\mem_2$ls180.v:10417$20_DATA + connect \EN $memwr$\mem_2$ls180.v:10417$20_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_2$ls180.v:0$3098 @@ -270154,10 +272683,10 @@ module \ls180 parameter \MEMID "\\mem_2" parameter \PRIORITY 3098 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10416$21_ADDR + connect \ADDR $memwr$\mem_2$ls180.v:10419$21_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10416$21_DATA - connect \EN $memwr$\mem_2$ls180.v:10416$21_EN + connect \DATA $memwr$\mem_2$ls180.v:10419$21_DATA + connect \EN $memwr$\mem_2$ls180.v:10419$21_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_2$ls180.v:0$3099 @@ -270167,10 +272696,10 @@ module \ls180 parameter \MEMID "\\mem_2" parameter \PRIORITY 3099 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10418$22_ADDR + connect \ADDR $memwr$\mem_2$ls180.v:10421$22_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10418$22_DATA - connect \EN $memwr$\mem_2$ls180.v:10418$22_EN + connect \DATA $memwr$\mem_2$ls180.v:10421$22_DATA + connect \EN $memwr$\mem_2$ls180.v:10421$22_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_2$ls180.v:0$3100 @@ -270180,10 +272709,10 @@ module \ls180 parameter \MEMID "\\mem_2" parameter \PRIORITY 3100 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10420$23_ADDR + connect \ADDR $memwr$\mem_2$ls180.v:10423$23_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10420$23_DATA - connect \EN $memwr$\mem_2$ls180.v:10420$23_EN + connect \DATA $memwr$\mem_2$ls180.v:10423$23_DATA + connect \EN $memwr$\mem_2$ls180.v:10423$23_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_2$ls180.v:0$3101 @@ -270193,10 +272722,10 @@ module \ls180 parameter \MEMID "\\mem_2" parameter \PRIORITY 3101 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10422$24_ADDR + connect \ADDR $memwr$\mem_2$ls180.v:10425$24_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10422$24_DATA - connect \EN $memwr$\mem_2$ls180.v:10422$24_EN + connect \DATA $memwr$\mem_2$ls180.v:10425$24_DATA + connect \EN $memwr$\mem_2$ls180.v:10425$24_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_3$ls180.v:0$3102 @@ -270206,10 +272735,10 @@ module \ls180 parameter \MEMID "\\mem_3" parameter \PRIORITY 3102 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10436$25_ADDR + connect \ADDR $memwr$\mem_3$ls180.v:10439$25_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10436$25_DATA - connect \EN $memwr$\mem_3$ls180.v:10436$25_EN + connect \DATA $memwr$\mem_3$ls180.v:10439$25_DATA + connect \EN $memwr$\mem_3$ls180.v:10439$25_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_3$ls180.v:0$3103 @@ -270219,10 +272748,10 @@ module \ls180 parameter \MEMID "\\mem_3" parameter \PRIORITY 3103 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10438$26_ADDR + connect \ADDR $memwr$\mem_3$ls180.v:10441$26_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10438$26_DATA - connect \EN $memwr$\mem_3$ls180.v:10438$26_EN + connect \DATA $memwr$\mem_3$ls180.v:10441$26_DATA + connect \EN $memwr$\mem_3$ls180.v:10441$26_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_3$ls180.v:0$3104 @@ -270232,10 +272761,10 @@ module \ls180 parameter \MEMID "\\mem_3" parameter \PRIORITY 3104 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10440$27_ADDR + connect \ADDR $memwr$\mem_3$ls180.v:10443$27_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10440$27_DATA - connect \EN $memwr$\mem_3$ls180.v:10440$27_EN + connect \DATA $memwr$\mem_3$ls180.v:10443$27_DATA + connect \EN $memwr$\mem_3$ls180.v:10443$27_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_3$ls180.v:0$3105 @@ -270245,10 +272774,10 @@ module \ls180 parameter \MEMID "\\mem_3" parameter \PRIORITY 3105 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10442$28_ADDR + connect \ADDR $memwr$\mem_3$ls180.v:10445$28_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10442$28_DATA - connect \EN $memwr$\mem_3$ls180.v:10442$28_EN + connect \DATA $memwr$\mem_3$ls180.v:10445$28_DATA + connect \EN $memwr$\mem_3$ls180.v:10445$28_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_3$ls180.v:0$3106 @@ -270258,10 +272787,10 @@ module \ls180 parameter \MEMID "\\mem_3" parameter \PRIORITY 3106 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10444$29_ADDR + connect \ADDR $memwr$\mem_3$ls180.v:10447$29_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10444$29_DATA - connect \EN $memwr$\mem_3$ls180.v:10444$29_EN + connect \DATA $memwr$\mem_3$ls180.v:10447$29_DATA + connect \EN $memwr$\mem_3$ls180.v:10447$29_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_3$ls180.v:0$3107 @@ -270271,10 +272800,10 @@ module \ls180 parameter \MEMID "\\mem_3" parameter \PRIORITY 3107 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10446$30_ADDR + connect \ADDR $memwr$\mem_3$ls180.v:10449$30_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10446$30_DATA - connect \EN $memwr$\mem_3$ls180.v:10446$30_EN + connect \DATA $memwr$\mem_3$ls180.v:10449$30_DATA + connect \EN $memwr$\mem_3$ls180.v:10449$30_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_3$ls180.v:0$3108 @@ -270284,10 +272813,10 @@ module \ls180 parameter \MEMID "\\mem_3" parameter \PRIORITY 3108 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10448$31_ADDR + connect \ADDR $memwr$\mem_3$ls180.v:10451$31_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10448$31_DATA - connect \EN $memwr$\mem_3$ls180.v:10448$31_EN + connect \DATA $memwr$\mem_3$ls180.v:10451$31_DATA + connect \EN $memwr$\mem_3$ls180.v:10451$31_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_3$ls180.v:0$3109 @@ -270297,10 +272826,10 @@ module \ls180 parameter \MEMID "\\mem_3" parameter \PRIORITY 3109 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10450$32_ADDR + connect \ADDR $memwr$\mem_3$ls180.v:10453$32_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10450$32_DATA - connect \EN $memwr$\mem_3$ls180.v:10450$32_EN + connect \DATA $memwr$\mem_3$ls180.v:10453$32_DATA + connect \EN $memwr$\mem_3$ls180.v:10453$32_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_4$ls180.v:0$3110 @@ -270310,10 +272839,10 @@ module \ls180 parameter \MEMID "\\mem_4" parameter \PRIORITY 3110 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10464$33_ADDR + connect \ADDR $memwr$\mem_4$ls180.v:10467$33_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10464$33_DATA - connect \EN $memwr$\mem_4$ls180.v:10464$33_EN + connect \DATA $memwr$\mem_4$ls180.v:10467$33_DATA + connect \EN $memwr$\mem_4$ls180.v:10467$33_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_4$ls180.v:0$3111 @@ -270323,10 +272852,10 @@ module \ls180 parameter \MEMID "\\mem_4" parameter \PRIORITY 3111 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10466$34_ADDR + connect \ADDR $memwr$\mem_4$ls180.v:10469$34_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10466$34_DATA - connect \EN $memwr$\mem_4$ls180.v:10466$34_EN + connect \DATA $memwr$\mem_4$ls180.v:10469$34_DATA + connect \EN $memwr$\mem_4$ls180.v:10469$34_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_4$ls180.v:0$3112 @@ -270336,10 +272865,10 @@ module \ls180 parameter \MEMID "\\mem_4" parameter \PRIORITY 3112 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10468$35_ADDR + connect \ADDR $memwr$\mem_4$ls180.v:10471$35_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10468$35_DATA - connect \EN $memwr$\mem_4$ls180.v:10468$35_EN + connect \DATA $memwr$\mem_4$ls180.v:10471$35_DATA + connect \EN $memwr$\mem_4$ls180.v:10471$35_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_4$ls180.v:0$3113 @@ -270349,10 +272878,10 @@ module \ls180 parameter \MEMID "\\mem_4" parameter \PRIORITY 3113 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10470$36_ADDR + connect \ADDR $memwr$\mem_4$ls180.v:10473$36_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10470$36_DATA - connect \EN $memwr$\mem_4$ls180.v:10470$36_EN + connect \DATA $memwr$\mem_4$ls180.v:10473$36_DATA + connect \EN $memwr$\mem_4$ls180.v:10473$36_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_4$ls180.v:0$3114 @@ -270362,10 +272891,10 @@ module \ls180 parameter \MEMID "\\mem_4" parameter \PRIORITY 3114 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10472$37_ADDR + connect \ADDR $memwr$\mem_4$ls180.v:10475$37_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10472$37_DATA - connect \EN $memwr$\mem_4$ls180.v:10472$37_EN + connect \DATA $memwr$\mem_4$ls180.v:10475$37_DATA + connect \EN $memwr$\mem_4$ls180.v:10475$37_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_4$ls180.v:0$3115 @@ -270375,10 +272904,10 @@ module \ls180 parameter \MEMID "\\mem_4" parameter \PRIORITY 3115 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10474$38_ADDR + connect \ADDR $memwr$\mem_4$ls180.v:10477$38_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10474$38_DATA - connect \EN $memwr$\mem_4$ls180.v:10474$38_EN + connect \DATA $memwr$\mem_4$ls180.v:10477$38_DATA + connect \EN $memwr$\mem_4$ls180.v:10477$38_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_4$ls180.v:0$3116 @@ -270388,10 +272917,10 @@ module \ls180 parameter \MEMID "\\mem_4" parameter \PRIORITY 3116 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10476$39_ADDR + connect \ADDR $memwr$\mem_4$ls180.v:10479$39_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10476$39_DATA - connect \EN $memwr$\mem_4$ls180.v:10476$39_EN + connect \DATA $memwr$\mem_4$ls180.v:10479$39_DATA + connect \EN $memwr$\mem_4$ls180.v:10479$39_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\mem_4$ls180.v:0$3117 @@ -270401,10 +272930,10 @@ module \ls180 parameter \MEMID "\\mem_4" parameter \PRIORITY 3117 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10478$40_ADDR + connect \ADDR $memwr$\mem_4$ls180.v:10481$40_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10478$40_DATA - connect \EN $memwr$\mem_4$ls180.v:10478$40_EN + connect \DATA $memwr$\mem_4$ls180.v:10481$40_DATA + connect \EN $memwr$\mem_4$ls180.v:10481$40_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\storage$ls180.v:0$3118 @@ -270414,10 +272943,10 @@ module \ls180 parameter \MEMID "\\storage" parameter \PRIORITY 3118 parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10492$41_ADDR + connect \ADDR $memwr$\storage$ls180.v:10495$41_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10492$41_DATA - connect \EN $memwr$\storage$ls180.v:10492$41_EN + connect \DATA $memwr$\storage$ls180.v:10495$41_DATA + connect \EN $memwr$\storage$ls180.v:10495$41_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\storage_1$ls180.v:0$3119 @@ -270427,10 +272956,10 @@ module \ls180 parameter \MEMID "\\storage_1" parameter \PRIORITY 3119 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10506$42_ADDR + connect \ADDR $memwr$\storage_1$ls180.v:10509$42_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10506$42_DATA - connect \EN $memwr$\storage_1$ls180.v:10506$42_EN + connect \DATA $memwr$\storage_1$ls180.v:10509$42_DATA + connect \EN $memwr$\storage_1$ls180.v:10509$42_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\storage_2$ls180.v:0$3120 @@ -270440,10 +272969,10 @@ module \ls180 parameter \MEMID "\\storage_2" parameter \PRIORITY 3120 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10520$43_ADDR + connect \ADDR $memwr$\storage_2$ls180.v:10523$43_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10520$43_DATA - connect \EN $memwr$\storage_2$ls180.v:10520$43_EN + connect \DATA $memwr$\storage_2$ls180.v:10523$43_DATA + connect \EN $memwr$\storage_2$ls180.v:10523$43_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\storage_3$ls180.v:0$3121 @@ -270453,10 +272982,10 @@ module \ls180 parameter \MEMID "\\storage_3" parameter \PRIORITY 3121 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10534$44_ADDR + connect \ADDR $memwr$\storage_3$ls180.v:10537$44_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10534$44_DATA - connect \EN $memwr$\storage_3$ls180.v:10534$44_EN + connect \DATA $memwr$\storage_3$ls180.v:10537$44_DATA + connect \EN $memwr$\storage_3$ls180.v:10537$44_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\storage_4$ls180.v:0$3122 @@ -270466,10 +272995,10 @@ module \ls180 parameter \MEMID "\\storage_4" parameter \PRIORITY 3122 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10549$45_ADDR + connect \ADDR $memwr$\storage_4$ls180.v:10552$45_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10549$45_DATA - connect \EN $memwr$\storage_4$ls180.v:10549$45_EN + connect \DATA $memwr$\storage_4$ls180.v:10552$45_DATA + connect \EN $memwr$\storage_4$ls180.v:10552$45_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\storage_5$ls180.v:0$3123 @@ -270479,10 +273008,10 @@ module \ls180 parameter \MEMID "\\storage_5" parameter \PRIORITY 3123 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10566$46_ADDR + connect \ADDR $memwr$\storage_5$ls180.v:10569$46_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10566$46_DATA - connect \EN $memwr$\storage_5$ls180.v:10566$46_EN + connect \DATA $memwr$\storage_5$ls180.v:10569$46_DATA + connect \EN $memwr$\storage_5$ls180.v:10569$46_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\storage_6$ls180.v:0$3124 @@ -270492,10 +273021,10 @@ module \ls180 parameter \MEMID "\\storage_6" parameter \PRIORITY 3124 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10582$47_ADDR + connect \ADDR $memwr$\storage_6$ls180.v:10585$47_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10582$47_DATA - connect \EN $memwr$\storage_6$ls180.v:10582$47_EN + connect \DATA $memwr$\storage_6$ls180.v:10585$47_DATA + connect \EN $memwr$\storage_6$ls180.v:10585$47_EN end attribute \src "ls180.v:0.0-0.0" cell $memwr $memwr$\storage_7$ls180.v:0$3125 @@ -270505,13 +273034,13 @@ module \ls180 parameter \MEMID "\\storage_7" parameter \PRIORITY 3125 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10596$48_ADDR + connect \ADDR $memwr$\storage_7$ls180.v:10599$48_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10596$48_DATA - connect \EN $memwr$\storage_7$ls180.v:10596$48_EN + connect \DATA $memwr$\storage_7$ls180.v:10599$48_DATA + connect \EN $memwr$\storage_7$ls180.v:10599$48_EN end - attribute \src "ls180.v:3086.41-3086.71" - cell $ne $ne$ls180.v:3086$108 + attribute \src "ls180.v:3089.41-3089.71" + cell $ne $ne$ls180.v:3089$108 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -270519,10 +273048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $ne$ls180.v:3086$108_Y + connect \Y $ne$ls180.v:3089$108_Y end - attribute \src "ls180.v:3303.70-3303.104" - cell $ne $ne$ls180.v:3303$222 + attribute \src "ls180.v:3306.70-3306.104" + cell $ne $ne$ls180.v:3306$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -270530,10 +273059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:3303$222_Y + connect \Y $ne$ls180.v:3306$222_Y end - attribute \src "ls180.v:3364.8-3364.142" - cell $ne $ne$ls180.v:3364$241 + attribute \src "ls180.v:3367.8-3367.142" + cell $ne $ne$ls180.v:3367$241 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -270541,10 +273070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3364$241_Y + connect \Y $ne$ls180.v:3367$241_Y end - attribute \src "ls180.v:3396.75-3396.133" - cell $ne $ne$ls180.v:3396$248 + attribute \src "ls180.v:3399.75-3399.133" + cell $ne $ne$ls180.v:3399$248 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270552,10 +273081,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3396$248_Y + connect \Y $ne$ls180.v:3399$248_Y end - attribute \src "ls180.v:3397.75-3397.133" - cell $ne $ne$ls180.v:3397$249 + attribute \src "ls180.v:3400.75-3400.133" + cell $ne $ne$ls180.v:3400$249 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270563,10 +273092,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3397$249_Y + connect \Y $ne$ls180.v:3400$249_Y end - attribute \src "ls180.v:3521.8-3521.142" - cell $ne $ne$ls180.v:3521$271 + attribute \src "ls180.v:3524.8-3524.142" + cell $ne $ne$ls180.v:3524$271 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -270574,10 +273103,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3521$271_Y + connect \Y $ne$ls180.v:3524$271_Y end - attribute \src "ls180.v:3553.75-3553.133" - cell $ne $ne$ls180.v:3553$278 + attribute \src "ls180.v:3556.75-3556.133" + cell $ne $ne$ls180.v:3556$278 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270585,10 +273114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3553$278_Y + connect \Y $ne$ls180.v:3556$278_Y end - attribute \src "ls180.v:3554.75-3554.133" - cell $ne $ne$ls180.v:3554$279 + attribute \src "ls180.v:3557.75-3557.133" + cell $ne $ne$ls180.v:3557$279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270596,10 +273125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3554$279_Y + connect \Y $ne$ls180.v:3557$279_Y end - attribute \src "ls180.v:3678.8-3678.142" - cell $ne $ne$ls180.v:3678$301 + attribute \src "ls180.v:3681.8-3681.142" + cell $ne $ne$ls180.v:3681$301 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -270607,10 +273136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3678$301_Y + connect \Y $ne$ls180.v:3681$301_Y end - attribute \src "ls180.v:3710.75-3710.133" - cell $ne $ne$ls180.v:3710$308 + attribute \src "ls180.v:3713.75-3713.133" + cell $ne $ne$ls180.v:3713$308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270618,10 +273147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3710$308_Y + connect \Y $ne$ls180.v:3713$308_Y end - attribute \src "ls180.v:3711.75-3711.133" - cell $ne $ne$ls180.v:3711$309 + attribute \src "ls180.v:3714.75-3714.133" + cell $ne $ne$ls180.v:3714$309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270629,10 +273158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3711$309_Y + connect \Y $ne$ls180.v:3714$309_Y end - attribute \src "ls180.v:3835.8-3835.142" - cell $ne $ne$ls180.v:3835$331 + attribute \src "ls180.v:3838.8-3838.142" + cell $ne $ne$ls180.v:3838$331 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -270640,10 +273169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3835$331_Y + connect \Y $ne$ls180.v:3838$331_Y end - attribute \src "ls180.v:3867.75-3867.133" - cell $ne $ne$ls180.v:3867$338 + attribute \src "ls180.v:3870.75-3870.133" + cell $ne $ne$ls180.v:3870$338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270651,10 +273180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3867$338_Y + connect \Y $ne$ls180.v:3870$338_Y end - attribute \src "ls180.v:3868.75-3868.133" - cell $ne $ne$ls180.v:3868$339 + attribute \src "ls180.v:3871.75-3871.133" + cell $ne $ne$ls180.v:3871$339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270662,10 +273191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3868$339_Y + connect \Y $ne$ls180.v:3871$339_Y end - attribute \src "ls180.v:4360.47-4360.80" - cell $ne $ne$ls180.v:4360$737 + attribute \src "ls180.v:4363.47-4363.80" + cell $ne $ne$ls180.v:4363$737 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -270673,10 +273202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4360$737_Y + connect \Y $ne$ls180.v:4363$737_Y end - attribute \src "ls180.v:4361.47-4361.79" - cell $ne $ne$ls180.v:4361$738 + attribute \src "ls180.v:4364.47-4364.79" + cell $ne $ne$ls180.v:4364$738 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -270684,10 +273213,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4361$738_Y + connect \Y $ne$ls180.v:4364$738_Y end - attribute \src "ls180.v:4390.47-4390.80" - cell $ne $ne$ls180.v:4390$748 + attribute \src "ls180.v:4393.47-4393.80" + cell $ne $ne$ls180.v:4393$748 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -270695,10 +273224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4390$748_Y + connect \Y $ne$ls180.v:4393$748_Y end - attribute \src "ls180.v:4391.47-4391.79" - cell $ne $ne$ls180.v:4391$749 + attribute \src "ls180.v:4394.47-4394.79" + cell $ne $ne$ls180.v:4394$749 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -270706,10 +273235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4391$749_Y + connect \Y $ne$ls180.v:4394$749_Y end - attribute \src "ls180.v:4871.32-4871.89" - cell $ne $ne$ls180.v:4871$831 + attribute \src "ls180.v:4874.32-4874.89" + cell $ne $ne$ls180.v:4874$831 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -270717,10 +273246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $ne$ls180.v:4871$831_Y + connect \Y $ne$ls180.v:4874$831_Y end - attribute \src "ls180.v:5518.10-5518.56" - cell $ne $ne$ls180.v:5518$1128 + attribute \src "ls180.v:5521.10-5521.56" + cell $ne $ne$ls180.v:5521$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270728,10 +273257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 2'10 - connect \Y $ne$ls180.v:5518$1128_Y + connect \Y $ne$ls180.v:5521$1128_Y end - attribute \src "ls180.v:5623.51-5623.87" - cell $ne $ne$ls180.v:5623$1142 + attribute \src "ls180.v:5626.51-5626.87" + cell $ne $ne$ls180.v:5626$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -270739,10 +273268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5623$1142_Y + connect \Y $ne$ls180.v:5626$1142_Y end - attribute \src "ls180.v:5624.51-5624.86" - cell $ne $ne$ls180.v:5624$1143 + attribute \src "ls180.v:5627.51-5627.86" + cell $ne $ne$ls180.v:5627$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -270750,10 +273279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5624$1143_Y + connect \Y $ne$ls180.v:5627$1143_Y end - attribute \src "ls180.v:5843.51-5843.87" - cell $ne $ne$ls180.v:5843$1173 + attribute \src "ls180.v:5846.51-5846.87" + cell $ne $ne$ls180.v:5846$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -270761,10 +273290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5843$1173_Y + connect \Y $ne$ls180.v:5846$1173_Y end - attribute \src "ls180.v:5844.51-5844.86" - cell $ne $ne$ls180.v:5844$1174 + attribute \src "ls180.v:5847.51-5847.86" + cell $ne $ne$ls180.v:5847$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -270772,10 +273301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5844$1174_Y + connect \Y $ne$ls180.v:5847$1174_Y end - attribute \src "ls180.v:5875.79-5875.119" - cell $ne $ne$ls180.v:5875$1177 + attribute \src "ls180.v:5878.79-5878.119" + cell $ne $ne$ls180.v:5878$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270783,10 +273312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_sel connect \B 1'0 - connect \Y $ne$ls180.v:5875$1177_Y + connect \Y $ne$ls180.v:5878$1177_Y end - attribute \src "ls180.v:7760.7-7760.52" - cell $ne $ne$ls180.v:7760$2601 + attribute \src "ls180.v:7763.7-7763.52" + cell $ne $ne$ls180.v:7763$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -270794,10 +273323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7760$2601_Y + connect \Y $ne$ls180.v:7763$2601_Y end - attribute \src "ls180.v:7826.9-7826.43" - cell $ne $ne$ls180.v:7826$2627 + attribute \src "ls180.v:7829.9-7829.43" + cell $ne $ne$ls180.v:7829$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -270805,10 +273334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7826$2627_Y + connect \Y $ne$ls180.v:7829$2627_Y end - attribute \src "ls180.v:7862.8-7862.44" - cell $ne $ne$ls180.v:7862$2634 + attribute \src "ls180.v:7865.8-7865.44" + cell $ne $ne$ls180.v:7865$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270816,10 +273345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7862$2634_Y + connect \Y $ne$ls180.v:7865$2634_Y end - attribute \src "ls180.v:8800.9-8800.47" - cell $ne $ne$ls180.v:8800$2849 + attribute \src "ls180.v:8803.9-8803.47" + cell $ne $ne$ls180.v:8803$2849 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270827,2738 +273356,2738 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8800$2849_Y + connect \Y $ne$ls180.v:8803$2849_Y end - attribute \src "ls180.v:2890.33-2890.73" - cell $not $not$ls180.v:2890$50 + attribute \src "ls180.v:2893.33-2893.73" + cell $not $not$ls180.v:2893$50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface0_converted_interface_cyc - connect \Y $not$ls180.v:2890$50_Y + connect \Y $not$ls180.v:2893$50_Y end - attribute \src "ls180.v:2929.48-2929.69" - cell $not $not$ls180.v:2929$55 + attribute \src "ls180.v:2932.48-2932.69" + cell $not $not$ls180.v:2932$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter0_skip - connect \Y $not$ls180.v:2929$55_Y + connect \Y $not$ls180.v:2932$55_Y end - attribute \src "ls180.v:2930.48-2930.69" - cell $not $not$ls180.v:2930$56 + attribute \src "ls180.v:2933.48-2933.69" + cell $not $not$ls180.v:2933$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter0_skip - connect \Y $not$ls180.v:2930$56_Y + connect \Y $not$ls180.v:2933$56_Y end - attribute \src "ls180.v:2950.33-2950.73" - cell $not $not$ls180.v:2950$61 + attribute \src "ls180.v:2953.33-2953.73" + cell $not $not$ls180.v:2953$61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface1_converted_interface_cyc - connect \Y $not$ls180.v:2950$61_Y + connect \Y $not$ls180.v:2953$61_Y end - attribute \src "ls180.v:2989.48-2989.69" - cell $not $not$ls180.v:2989$66 + attribute \src "ls180.v:2992.48-2992.69" + cell $not $not$ls180.v:2992$66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter1_skip - connect \Y $not$ls180.v:2989$66_Y + connect \Y $not$ls180.v:2992$66_Y end - attribute \src "ls180.v:2990.48-2990.69" - cell $not $not$ls180.v:2990$67 + attribute \src "ls180.v:2993.48-2993.69" + cell $not $not$ls180.v:2993$67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter1_skip - connect \Y $not$ls180.v:2990$67_Y + connect \Y $not$ls180.v:2993$67_Y end - attribute \src "ls180.v:3010.36-3010.79" - cell $not $not$ls180.v:3010$72 + attribute \src "ls180.v:3013.36-3013.79" + cell $not $not$ls180.v:3013$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_socbushandler_converted_interface_cyc - connect \Y $not$ls180.v:3010$72_Y + connect \Y $not$ls180.v:3013$72_Y end - attribute \src "ls180.v:3049.27-3049.51" - cell $not $not$ls180.v:3049$77 + attribute \src "ls180.v:3052.27-3052.51" + cell $not $not$ls180.v:3052$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:3049$77_Y + connect \Y $not$ls180.v:3052$77_Y end - attribute \src "ls180.v:3050.27-3050.51" - cell $not $not$ls180.v:3050$78 + attribute \src "ls180.v:3053.27-3053.51" + cell $not $not$ls180.v:3053$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:3050$78_Y + connect \Y $not$ls180.v:3053$78_Y end - attribute \src "ls180.v:3252.34-3252.64" - cell $not $not$ls180.v:3252$214 + attribute \src "ls180.v:3255.34-3255.64" + cell $not $not$ls180.v:3255$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3252$214_Y + connect \Y $not$ls180.v:3255$214_Y end - attribute \src "ls180.v:3253.31-3253.61" - cell $not $not$ls180.v:3253$215 + attribute \src "ls180.v:3256.31-3256.61" + cell $not $not$ls180.v:3256$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3253$215_Y + connect \Y $not$ls180.v:3256$215_Y end - attribute \src "ls180.v:3254.32-3254.62" - cell $not $not$ls180.v:3254$216 + attribute \src "ls180.v:3257.32-3257.62" + cell $not $not$ls180.v:3257$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3254$216_Y + connect \Y $not$ls180.v:3257$216_Y end - attribute \src "ls180.v:3255.32-3255.62" - cell $not $not$ls180.v:3255$217 + attribute \src "ls180.v:3258.32-3258.62" + cell $not $not$ls180.v:3258$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3255$217_Y + connect \Y $not$ls180.v:3258$217_Y end - attribute \src "ls180.v:3297.33-3297.56" - cell $not $not$ls180.v:3297$220 + attribute \src "ls180.v:3300.33-3300.56" + cell $not $not$ls180.v:3300$220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3297$220_Y + connect \Y $not$ls180.v:3300$220_Y end - attribute \src "ls180.v:3398.58-3398.106" - cell $not $not$ls180.v:3398$250 + attribute \src "ls180.v:3401.58-3401.106" + cell $not $not$ls180.v:3401$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3398$250_Y + connect \Y $not$ls180.v:3401$250_Y end - attribute \src "ls180.v:3452.9-3452.45" - cell $not $not$ls180.v:3452$255 + attribute \src "ls180.v:3455.9-3455.45" + cell $not $not$ls180.v:3455$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3452$255_Y + connect \Y $not$ls180.v:3455$255_Y end - attribute \src "ls180.v:3555.58-3555.106" - cell $not $not$ls180.v:3555$280 + attribute \src "ls180.v:3558.58-3558.106" + cell $not $not$ls180.v:3558$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3555$280_Y + connect \Y $not$ls180.v:3558$280_Y end - attribute \src "ls180.v:3609.9-3609.45" - cell $not $not$ls180.v:3609$285 + attribute \src "ls180.v:3612.9-3612.45" + cell $not $not$ls180.v:3612$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3609$285_Y + connect \Y $not$ls180.v:3612$285_Y end - attribute \src "ls180.v:3712.58-3712.106" - cell $not $not$ls180.v:3712$310 + attribute \src "ls180.v:3715.58-3715.106" + cell $not $not$ls180.v:3715$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3712$310_Y + connect \Y $not$ls180.v:3715$310_Y end - attribute \src "ls180.v:3766.9-3766.45" - cell $not $not$ls180.v:3766$315 + attribute \src "ls180.v:3769.9-3769.45" + cell $not $not$ls180.v:3769$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3766$315_Y + connect \Y $not$ls180.v:3769$315_Y end - attribute \src "ls180.v:3869.58-3869.106" - cell $not $not$ls180.v:3869$340 + attribute \src "ls180.v:3872.58-3872.106" + cell $not $not$ls180.v:3872$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3869$340_Y + connect \Y $not$ls180.v:3872$340_Y end - attribute \src "ls180.v:3923.9-3923.45" - cell $not $not$ls180.v:3923$345 + attribute \src "ls180.v:3926.9-3926.45" + cell $not $not$ls180.v:3926$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3923$345_Y + connect \Y $not$ls180.v:3926$345_Y end - attribute \src "ls180.v:3965.149-3965.187" - cell $not $not$ls180.v:3965$348 + attribute \src "ls180.v:3968.149-3968.187" + cell $not $not$ls180.v:3968$348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3965$348_Y + connect \Y $not$ls180.v:3968$348_Y end - attribute \src "ls180.v:3965.193-3965.230" - cell $not $not$ls180.v:3965$350 + attribute \src "ls180.v:3968.193-3968.230" + cell $not $not$ls180.v:3968$350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3965$350_Y + connect \Y $not$ls180.v:3968$350_Y end - attribute \src "ls180.v:3966.149-3966.187" - cell $not $not$ls180.v:3966$354 + attribute \src "ls180.v:3969.149-3969.187" + cell $not $not$ls180.v:3969$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3966$354_Y + connect \Y $not$ls180.v:3969$354_Y end - attribute \src "ls180.v:3966.193-3966.230" - cell $not $not$ls180.v:3966$356 + attribute \src "ls180.v:3969.193-3969.230" + cell $not $not$ls180.v:3969$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3966$356_Y + connect \Y $not$ls180.v:3969$356_Y end - attribute \src "ls180.v:3982.43-3982.73" - cell $not $not$ls180.v:3982$384 + attribute \src "ls180.v:3985.43-3985.73" + cell $not $not$ls180.v:3985$384 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3982$384_Y + connect \Y $not$ls180.v:3985$384_Y end - attribute \src "ls180.v:3985.205-3985.245" - cell $not $not$ls180.v:3985$387 + attribute \src "ls180.v:3988.205-3988.245" + cell $not $not$ls180.v:3988$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3985$387_Y + connect \Y $not$ls180.v:3988$387_Y end - attribute \src "ls180.v:3985.251-3985.290" - cell $not $not$ls180.v:3985$389 + attribute \src "ls180.v:3988.251-3988.290" + cell $not $not$ls180.v:3988$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3985$389_Y + connect \Y $not$ls180.v:3988$389_Y end - attribute \src "ls180.v:3985.159-3985.292" - cell $not $not$ls180.v:3985$391 + attribute \src "ls180.v:3988.159-3988.292" + cell $not $not$ls180.v:3988$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$390_Y - connect \Y $not$ls180.v:3985$391_Y + connect \A $and$ls180.v:3988$390_Y + connect \Y $not$ls180.v:3988$391_Y end - attribute \src "ls180.v:3986.205-3986.245" - cell $not $not$ls180.v:3986$400 + attribute \src "ls180.v:3989.205-3989.245" + cell $not $not$ls180.v:3989$400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3986$400_Y + connect \Y $not$ls180.v:3989$400_Y end - attribute \src "ls180.v:3986.251-3986.290" - cell $not $not$ls180.v:3986$402 + attribute \src "ls180.v:3989.251-3989.290" + cell $not $not$ls180.v:3989$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3986$402_Y + connect \Y $not$ls180.v:3989$402_Y end - attribute \src "ls180.v:3986.159-3986.292" - cell $not $not$ls180.v:3986$404 + attribute \src "ls180.v:3989.159-3989.292" + cell $not $not$ls180.v:3989$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3986$403_Y - connect \Y $not$ls180.v:3986$404_Y + connect \A $and$ls180.v:3989$403_Y + connect \Y $not$ls180.v:3989$404_Y end - attribute \src "ls180.v:3987.205-3987.245" - cell $not $not$ls180.v:3987$413 + attribute \src "ls180.v:3990.205-3990.245" + cell $not $not$ls180.v:3990$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3987$413_Y + connect \Y $not$ls180.v:3990$413_Y end - attribute \src "ls180.v:3987.251-3987.290" - cell $not $not$ls180.v:3987$415 + attribute \src "ls180.v:3990.251-3990.290" + cell $not $not$ls180.v:3990$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3987$415_Y + connect \Y $not$ls180.v:3990$415_Y end - attribute \src "ls180.v:3987.159-3987.292" - cell $not $not$ls180.v:3987$417 + attribute \src "ls180.v:3990.159-3990.292" + cell $not $not$ls180.v:3990$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3987$416_Y - connect \Y $not$ls180.v:3987$417_Y + connect \A $and$ls180.v:3990$416_Y + connect \Y $not$ls180.v:3990$417_Y end - attribute \src "ls180.v:3988.205-3988.245" - cell $not $not$ls180.v:3988$426 + attribute \src "ls180.v:3991.205-3991.245" + cell $not $not$ls180.v:3991$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3988$426_Y + connect \Y $not$ls180.v:3991$426_Y end - attribute \src "ls180.v:3988.251-3988.290" - cell $not $not$ls180.v:3988$428 + attribute \src "ls180.v:3991.251-3991.290" + cell $not $not$ls180.v:3991$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3988$428_Y + connect \Y $not$ls180.v:3991$428_Y end - attribute \src "ls180.v:3988.159-3988.292" - cell $not $not$ls180.v:3988$430 + attribute \src "ls180.v:3991.159-3991.292" + cell $not $not$ls180.v:3991$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$429_Y - connect \Y $not$ls180.v:3988$430_Y + connect \A $and$ls180.v:3991$429_Y + connect \Y $not$ls180.v:3991$430_Y end - attribute \src "ls180.v:4015.71-4015.103" - cell $not $not$ls180.v:4015$441 + attribute \src "ls180.v:4018.71-4018.103" + cell $not $not$ls180.v:4018$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:4015$441_Y + connect \Y $not$ls180.v:4018$441_Y end - attribute \src "ls180.v:4018.205-4018.245" - cell $not $not$ls180.v:4018$445 + attribute \src "ls180.v:4021.205-4021.245" + cell $not $not$ls180.v:4021$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:4018$445_Y + connect \Y $not$ls180.v:4021$445_Y end - attribute \src "ls180.v:4018.251-4018.290" - cell $not $not$ls180.v:4018$447 + attribute \src "ls180.v:4021.251-4021.290" + cell $not $not$ls180.v:4021$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:4018$447_Y + connect \Y $not$ls180.v:4021$447_Y end - attribute \src "ls180.v:4018.159-4018.292" - cell $not $not$ls180.v:4018$449 + attribute \src "ls180.v:4021.159-4021.292" + cell $not $not$ls180.v:4021$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4018$448_Y - connect \Y $not$ls180.v:4018$449_Y + connect \A $and$ls180.v:4021$448_Y + connect \Y $not$ls180.v:4021$449_Y end - attribute \src "ls180.v:4019.205-4019.245" - cell $not $not$ls180.v:4019$458 + attribute \src "ls180.v:4022.205-4022.245" + cell $not $not$ls180.v:4022$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:4019$458_Y + connect \Y $not$ls180.v:4022$458_Y end - attribute \src "ls180.v:4019.251-4019.290" - cell $not $not$ls180.v:4019$460 + attribute \src "ls180.v:4022.251-4022.290" + cell $not $not$ls180.v:4022$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:4019$460_Y + connect \Y $not$ls180.v:4022$460_Y end - attribute \src "ls180.v:4019.159-4019.292" - cell $not $not$ls180.v:4019$462 + attribute \src "ls180.v:4022.159-4022.292" + cell $not $not$ls180.v:4022$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4019$461_Y - connect \Y $not$ls180.v:4019$462_Y + connect \A $and$ls180.v:4022$461_Y + connect \Y $not$ls180.v:4022$462_Y end - attribute \src "ls180.v:4020.205-4020.245" - cell $not $not$ls180.v:4020$471 + attribute \src "ls180.v:4023.205-4023.245" + cell $not $not$ls180.v:4023$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:4020$471_Y + connect \Y $not$ls180.v:4023$471_Y end - attribute \src "ls180.v:4020.251-4020.290" - cell $not $not$ls180.v:4020$473 + attribute \src "ls180.v:4023.251-4023.290" + cell $not $not$ls180.v:4023$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:4020$473_Y + connect \Y $not$ls180.v:4023$473_Y end - attribute \src "ls180.v:4020.159-4020.292" - cell $not $not$ls180.v:4020$475 + attribute \src "ls180.v:4023.159-4023.292" + cell $not $not$ls180.v:4023$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4020$474_Y - connect \Y $not$ls180.v:4020$475_Y + connect \A $and$ls180.v:4023$474_Y + connect \Y $not$ls180.v:4023$475_Y end - attribute \src "ls180.v:4021.205-4021.245" - cell $not $not$ls180.v:4021$484 + attribute \src "ls180.v:4024.205-4024.245" + cell $not $not$ls180.v:4024$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:4021$484_Y + connect \Y $not$ls180.v:4024$484_Y end - attribute \src "ls180.v:4021.251-4021.290" - cell $not $not$ls180.v:4021$486 + attribute \src "ls180.v:4024.251-4024.290" + cell $not $not$ls180.v:4024$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:4021$486_Y + connect \Y $not$ls180.v:4024$486_Y end - attribute \src "ls180.v:4021.159-4021.292" - cell $not $not$ls180.v:4021$488 + attribute \src "ls180.v:4024.159-4024.292" + cell $not $not$ls180.v:4024$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$487_Y - connect \Y $not$ls180.v:4021$488_Y + connect \A $and$ls180.v:4024$487_Y + connect \Y $not$ls180.v:4024$488_Y end - attribute \src "ls180.v:4084.71-4084.103" - cell $not $not$ls180.v:4084$527 + attribute \src "ls180.v:4087.71-4087.103" + cell $not $not$ls180.v:4087$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:4084$527_Y + connect \Y $not$ls180.v:4087$527_Y end - attribute \src "ls180.v:4105.112-4105.150" - cell $not $not$ls180.v:4105$530 + attribute \src "ls180.v:4108.112-4108.150" + cell $not $not$ls180.v:4108$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4105$530_Y + connect \Y $not$ls180.v:4108$530_Y end - attribute \src "ls180.v:4105.156-4105.193" - cell $not $not$ls180.v:4105$532 + attribute \src "ls180.v:4108.156-4108.193" + cell $not $not$ls180.v:4108$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4105$532_Y + connect \Y $not$ls180.v:4108$532_Y end - attribute \src "ls180.v:4105.68-4105.195" - cell $not $not$ls180.v:4105$534 + attribute \src "ls180.v:4108.68-4108.195" + cell $not $not$ls180.v:4108$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4105$533_Y - connect \Y $not$ls180.v:4105$534_Y + connect \A $and$ls180.v:4108$533_Y + connect \Y $not$ls180.v:4108$534_Y end - attribute \src "ls180.v:4113.11-4113.38" - cell $not $not$ls180.v:4113$537 + attribute \src "ls180.v:4116.11-4116.38" + cell $not $not$ls180.v:4116$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_write_available - connect \Y $not$ls180.v:4113$537_Y + connect \Y $not$ls180.v:4116$537_Y end - attribute \src "ls180.v:4143.112-4143.150" - cell $not $not$ls180.v:4143$539 + attribute \src "ls180.v:4146.112-4146.150" + cell $not $not$ls180.v:4146$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4143$539_Y + connect \Y $not$ls180.v:4146$539_Y end - attribute \src "ls180.v:4143.156-4143.193" - cell $not $not$ls180.v:4143$541 + attribute \src "ls180.v:4146.156-4146.193" + cell $not $not$ls180.v:4146$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4143$541_Y + connect \Y $not$ls180.v:4146$541_Y end - attribute \src "ls180.v:4143.68-4143.195" - cell $not $not$ls180.v:4143$543 + attribute \src "ls180.v:4146.68-4146.195" + cell $not $not$ls180.v:4146$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4143$542_Y - connect \Y $not$ls180.v:4143$543_Y + connect \A $and$ls180.v:4146$542_Y + connect \Y $not$ls180.v:4146$543_Y end - attribute \src "ls180.v:4151.11-4151.37" - cell $not $not$ls180.v:4151$546 + attribute \src "ls180.v:4154.11-4154.37" + cell $not $not$ls180.v:4154$546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_read_available - connect \Y $not$ls180.v:4151$546_Y + connect \Y $not$ls180.v:4154$546_Y end - attribute \src "ls180.v:4161.87-4161.331" - cell $not $not$ls180.v:4161$558 + attribute \src "ls180.v:4164.87-4164.331" + cell $not $not$ls180.v:4164$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4161$557_Y - connect \Y $not$ls180.v:4161$558_Y + connect \A $or$ls180.v:4164$557_Y + connect \Y $not$ls180.v:4164$558_Y end - attribute \src "ls180.v:4162.35-4162.68" - cell $not $not$ls180.v:4162$561 + attribute \src "ls180.v:4165.35-4165.68" + cell $not $not$ls180.v:4165$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:4162$561_Y + connect \Y $not$ls180.v:4165$561_Y end - attribute \src "ls180.v:4162.73-4162.105" - cell $not $not$ls180.v:4162$562 + attribute \src "ls180.v:4165.73-4165.105" + cell $not $not$ls180.v:4165$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:4162$562_Y + connect \Y $not$ls180.v:4165$562_Y end - attribute \src "ls180.v:4166.87-4166.331" - cell $not $not$ls180.v:4166$574 + attribute \src "ls180.v:4169.87-4169.331" + cell $not $not$ls180.v:4169$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4166$573_Y - connect \Y $not$ls180.v:4166$574_Y + connect \A $or$ls180.v:4169$573_Y + connect \Y $not$ls180.v:4169$574_Y end - attribute \src "ls180.v:4167.35-4167.68" - cell $not $not$ls180.v:4167$577 + attribute \src "ls180.v:4170.35-4170.68" + cell $not $not$ls180.v:4170$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:4167$577_Y + connect \Y $not$ls180.v:4170$577_Y end - attribute \src "ls180.v:4167.73-4167.105" - cell $not $not$ls180.v:4167$578 + attribute \src "ls180.v:4170.73-4170.105" + cell $not $not$ls180.v:4170$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:4167$578_Y + connect \Y $not$ls180.v:4170$578_Y end - attribute \src "ls180.v:4171.87-4171.331" - cell $not $not$ls180.v:4171$590 + attribute \src "ls180.v:4174.87-4174.331" + cell $not $not$ls180.v:4174$590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4171$589_Y - connect \Y $not$ls180.v:4171$590_Y + connect \A $or$ls180.v:4174$589_Y + connect \Y $not$ls180.v:4174$590_Y end - attribute \src "ls180.v:4172.35-4172.68" - cell $not $not$ls180.v:4172$593 + attribute \src "ls180.v:4175.35-4175.68" + cell $not $not$ls180.v:4175$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:4172$593_Y + connect \Y $not$ls180.v:4175$593_Y end - attribute \src "ls180.v:4172.73-4172.105" - cell $not $not$ls180.v:4172$594 + attribute \src "ls180.v:4175.73-4175.105" + cell $not $not$ls180.v:4175$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:4172$594_Y + connect \Y $not$ls180.v:4175$594_Y end - attribute \src "ls180.v:4176.87-4176.331" - cell $not $not$ls180.v:4176$606 + attribute \src "ls180.v:4179.87-4179.331" + cell $not $not$ls180.v:4179$606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4176$605_Y - connect \Y $not$ls180.v:4176$606_Y + connect \A $or$ls180.v:4179$605_Y + connect \Y $not$ls180.v:4179$606_Y end - attribute \src "ls180.v:4177.35-4177.68" - cell $not $not$ls180.v:4177$609 + attribute \src "ls180.v:4180.35-4180.68" + cell $not $not$ls180.v:4180$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4177$609_Y + connect \Y $not$ls180.v:4180$609_Y end - attribute \src "ls180.v:4177.73-4177.105" - cell $not $not$ls180.v:4177$610 + attribute \src "ls180.v:4180.73-4180.105" + cell $not $not$ls180.v:4180$610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4177$610_Y + connect \Y $not$ls180.v:4180$610_Y end - attribute \src "ls180.v:4181.128-4181.372" - cell $not $not$ls180.v:4181$623 + attribute \src "ls180.v:4184.128-4184.372" + cell $not $not$ls180.v:4184$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$622_Y - connect \Y $not$ls180.v:4181$623_Y + connect \A $or$ls180.v:4184$622_Y + connect \Y $not$ls180.v:4184$623_Y end - attribute \src "ls180.v:4181.502-4181.746" - cell $not $not$ls180.v:4181$639 + attribute \src "ls180.v:4184.502-4184.746" + cell $not $not$ls180.v:4184$639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$638_Y - connect \Y $not$ls180.v:4181$639_Y + connect \A $or$ls180.v:4184$638_Y + connect \Y $not$ls180.v:4184$639_Y end - attribute \src "ls180.v:4181.876-4181.1120" - cell $not $not$ls180.v:4181$655 + attribute \src "ls180.v:4184.876-4184.1120" + cell $not $not$ls180.v:4184$655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$654_Y - connect \Y $not$ls180.v:4181$655_Y + connect \A $or$ls180.v:4184$654_Y + connect \Y $not$ls180.v:4184$655_Y end - attribute \src "ls180.v:4181.1250-4181.1494" - cell $not $not$ls180.v:4181$671 + attribute \src "ls180.v:4184.1250-4184.1494" + cell $not $not$ls180.v:4184$671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$670_Y - connect \Y $not$ls180.v:4181$671_Y + connect \A $or$ls180.v:4184$670_Y + connect \Y $not$ls180.v:4184$671_Y end - attribute \src "ls180.v:4203.32-4203.50" - cell $not $not$ls180.v:4203$677 + attribute \src "ls180.v:4206.32-4206.50" + cell $not $not$ls180.v:4206$677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4203$677_Y + connect \Y $not$ls180.v:4206$677_Y end - attribute \src "ls180.v:4242.30-4242.50" - cell $not $not$ls180.v:4242$682 + attribute \src "ls180.v:4245.30-4245.50" + cell $not $not$ls180.v:4245$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4242$682_Y + connect \Y $not$ls180.v:4245$682_Y end - attribute \src "ls180.v:4243.30-4243.50" - cell $not $not$ls180.v:4243$683 + attribute \src "ls180.v:4246.30-4246.50" + cell $not $not$ls180.v:4246$683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4243$683_Y + connect \Y $not$ls180.v:4246$683_Y end - attribute \src "ls180.v:4268.27-4268.48" - cell $not $not$ls180.v:4268$689 + attribute \src "ls180.v:4271.27-4271.48" + cell $not $not$ls180.v:4271$689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4268$689_Y + connect \Y $not$ls180.v:4271$689_Y end - attribute \src "ls180.v:4269.30-4269.50" - cell $not $not$ls180.v:4269$690 + attribute \src "ls180.v:4272.30-4272.50" + cell $not $not$ls180.v:4272$690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4269$690_Y + connect \Y $not$ls180.v:4272$690_Y end - attribute \src "ls180.v:4270.80-4270.98" - cell $not $not$ls180.v:4270$692 + attribute \src "ls180.v:4273.80-4273.98" + cell $not $not$ls180.v:4273$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4270$692_Y + connect \Y $not$ls180.v:4273$692_Y end - attribute \src "ls180.v:4271.107-4271.127" - cell $not $not$ls180.v:4271$696 + attribute \src "ls180.v:4274.107-4274.127" + cell $not $not$ls180.v:4274$696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4271$696_Y + connect \Y $not$ls180.v:4274$696_Y end - attribute \src "ls180.v:4272.78-4272.103" - cell $not $not$ls180.v:4272$699 + attribute \src "ls180.v:4275.78-4275.103" + cell $not $not$ls180.v:4275$699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4272$699_Y + connect \Y $not$ls180.v:4275$699_Y end - attribute \src "ls180.v:4273.91-4273.111" - cell $not $not$ls180.v:4273$702 + attribute \src "ls180.v:4276.91-4276.111" + cell $not $not$ls180.v:4276$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4273$702_Y + connect \Y $not$ls180.v:4276$702_Y end - attribute \src "ls180.v:4289.35-4289.64" - cell $not $not$ls180.v:4289$711 + attribute \src "ls180.v:4292.35-4292.64" + cell $not $not$ls180.v:4292$711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4289$711_Y + connect \Y $not$ls180.v:4292$711_Y end - attribute \src "ls180.v:4290.36-4290.67" - cell $not $not$ls180.v:4290$712 + attribute \src "ls180.v:4293.36-4293.67" + cell $not $not$ls180.v:4293$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4290$712_Y + connect \Y $not$ls180.v:4293$712_Y end - attribute \src "ls180.v:4296.32-4296.61" - cell $not $not$ls180.v:4296$713 + attribute \src "ls180.v:4299.32-4299.61" + cell $not $not$ls180.v:4299$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4296$713_Y + connect \Y $not$ls180.v:4299$713_Y end - attribute \src "ls180.v:4302.36-4302.67" - cell $not $not$ls180.v:4302$714 + attribute \src "ls180.v:4305.36-4305.67" + cell $not $not$ls180.v:4305$714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4302$714_Y + connect \Y $not$ls180.v:4305$714_Y end - attribute \src "ls180.v:4303.35-4303.64" - cell $not $not$ls180.v:4303$715 + attribute \src "ls180.v:4306.35-4306.64" + cell $not $not$ls180.v:4306$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4303$715_Y + connect \Y $not$ls180.v:4306$715_Y end - attribute \src "ls180.v:4306.32-4306.63" - cell $not $not$ls180.v:4306$718 + attribute \src "ls180.v:4309.32-4309.63" + cell $not $not$ls180.v:4309$718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4306$718_Y + connect \Y $not$ls180.v:4309$718_Y end - attribute \src "ls180.v:4344.81-4344.108" - cell $not $not$ls180.v:4344$728 + attribute \src "ls180.v:4347.81-4347.108" + cell $not $not$ls180.v:4347$728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4344$728_Y + connect \Y $not$ls180.v:4347$728_Y end - attribute \src "ls180.v:4374.81-4374.108" - cell $not $not$ls180.v:4374$739 + attribute \src "ls180.v:4377.81-4377.108" + cell $not $not$ls180.v:4377$739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4374$739_Y + connect \Y $not$ls180.v:4377$739_Y end - attribute \src "ls180.v:4585.60-4585.85" - cell $not $not$ls180.v:4585$790 + attribute \src "ls180.v:4588.60-4588.85" + cell $not $not$ls180.v:4588$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4585$790_Y + connect \Y $not$ls180.v:4588$790_Y end - attribute \src "ls180.v:4726.54-4726.96" - cell $not $not$ls180.v:4726$804 + attribute \src "ls180.v:4729.54-4729.96" + cell $not $not$ls180.v:4729$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4726$804_Y + connect \Y $not$ls180.v:4729$804_Y end - attribute \src "ls180.v:4729.48-4729.86" - cell $not $not$ls180.v:4729$807 + attribute \src "ls180.v:4732.48-4732.86" + cell $not $not$ls180.v:4732$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4729$807_Y + connect \Y $not$ls180.v:4732$807_Y end - attribute \src "ls180.v:4853.55-4853.98" - cell $not $not$ls180.v:4853$825 + attribute \src "ls180.v:4856.55-4856.98" + cell $not $not$ls180.v:4856$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4853$825_Y + connect \Y $not$ls180.v:4856$825_Y end - attribute \src "ls180.v:4856.49-4856.88" - cell $not $not$ls180.v:4856$828 + attribute \src "ls180.v:4859.49-4859.88" + cell $not $not$ls180.v:4859$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4856$828_Y + connect \Y $not$ls180.v:4859$828_Y end - attribute \src "ls180.v:4906.30-4906.58" - cell $not $not$ls180.v:4906$834 + attribute \src "ls180.v:4909.30-4909.58" + cell $not $not$ls180.v:4909$834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4906$834_Y + connect \Y $not$ls180.v:4909$834_Y end - attribute \src "ls180.v:4987.56-4987.100" - cell $not $not$ls180.v:4987$840 + attribute \src "ls180.v:4990.56-4990.100" + cell $not $not$ls180.v:4990$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4987$840_Y + connect \Y $not$ls180.v:4990$840_Y end - attribute \src "ls180.v:4990.50-4990.90" - cell $not $not$ls180.v:4990$843 + attribute \src "ls180.v:4993.50-4993.90" + cell $not $not$ls180.v:4993$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4990$843_Y + connect \Y $not$ls180.v:4993$843_Y end - attribute \src "ls180.v:5106.42-5106.74" - cell $not $not$ls180.v:5106$859 + attribute \src "ls180.v:5109.42-5109.74" + cell $not $not$ls180.v:5109$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:5106$859_Y + connect \Y $not$ls180.v:5109$859_Y end - attribute \src "ls180.v:5630.50-5630.88" - cell $not $not$ls180.v:5630$1144 + attribute \src "ls180.v:5633.50-5633.88" + cell $not $not$ls180.v:5633$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5630$1144_Y + connect \Y $not$ls180.v:5633$1144_Y end - attribute \src "ls180.v:5642.52-5642.102" - cell $not $not$ls180.v:5642$1147 + attribute \src "ls180.v:5645.52-5645.102" + cell $not $not$ls180.v:5645$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5642$1147_Y + connect \Y $not$ls180.v:5645$1147_Y end - attribute \src "ls180.v:5701.38-5701.74" - cell $not $not$ls180.v:5701$1154 + attribute \src "ls180.v:5704.38-5704.74" + cell $not $not$ls180.v:5704$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5701$1154_Y + connect \Y $not$ls180.v:5704$1154_Y end - attribute \src "ls180.v:6027.69-6027.88" - cell $not $not$ls180.v:6027$1239 + attribute \src "ls180.v:6030.69-6030.88" + cell $not $not$ls180.v:6030$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \Y $not$ls180.v:6027$1239_Y - end - attribute \src "ls180.v:6044.63-6044.94" - cell $not $not$ls180.v:6044$1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6044$1284_Y + connect \Y $not$ls180.v:6030$1239_Y end - attribute \src "ls180.v:6047.65-6047.96" - cell $not $not$ls180.v:6047$1291 + attribute \src "ls180.v:6047.63-6047.94" + cell $not $not$ls180.v:6047$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6047$1291_Y + connect \Y $not$ls180.v:6047$1284_Y end attribute \src "ls180.v:6050.65-6050.96" - cell $not $not$ls180.v:6050$1298 + cell $not $not$ls180.v:6050$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6050$1298_Y + connect \Y $not$ls180.v:6050$1291_Y end attribute \src "ls180.v:6053.65-6053.96" - cell $not $not$ls180.v:6053$1305 + cell $not $not$ls180.v:6053$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6053$1305_Y + connect \Y $not$ls180.v:6053$1298_Y end attribute \src "ls180.v:6056.65-6056.96" - cell $not $not$ls180.v:6056$1312 + cell $not $not$ls180.v:6056$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6056$1312_Y + connect \Y $not$ls180.v:6056$1305_Y end - attribute \src "ls180.v:6059.68-6059.99" - cell $not $not$ls180.v:6059$1319 + attribute \src "ls180.v:6059.65-6059.96" + cell $not $not$ls180.v:6059$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6059$1319_Y + connect \Y $not$ls180.v:6059$1312_Y end attribute \src "ls180.v:6062.68-6062.99" - cell $not $not$ls180.v:6062$1326 + cell $not $not$ls180.v:6062$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6062$1326_Y + connect \Y $not$ls180.v:6062$1319_Y end attribute \src "ls180.v:6065.68-6065.99" - cell $not $not$ls180.v:6065$1333 + cell $not $not$ls180.v:6065$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6065$1333_Y + connect \Y $not$ls180.v:6065$1326_Y end attribute \src "ls180.v:6068.68-6068.99" - cell $not $not$ls180.v:6068$1340 + cell $not $not$ls180.v:6068$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6068$1340_Y + connect \Y $not$ls180.v:6068$1333_Y end - attribute \src "ls180.v:6082.60-6082.91" - cell $not $not$ls180.v:6082$1348 + attribute \src "ls180.v:6071.68-6071.99" + cell $not $not$ls180.v:6071$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6082$1348_Y + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6071$1340_Y end attribute \src "ls180.v:6085.60-6085.91" - cell $not $not$ls180.v:6085$1355 + cell $not $not$ls180.v:6085$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6085$1355_Y + connect \Y $not$ls180.v:6085$1348_Y end attribute \src "ls180.v:6088.60-6088.91" - cell $not $not$ls180.v:6088$1362 + cell $not $not$ls180.v:6088$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6088$1362_Y + connect \Y $not$ls180.v:6088$1355_Y end attribute \src "ls180.v:6091.60-6091.91" - cell $not $not$ls180.v:6091$1369 + cell $not $not$ls180.v:6091$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6091$1369_Y + connect \Y $not$ls180.v:6091$1362_Y end - attribute \src "ls180.v:6094.61-6094.92" - cell $not $not$ls180.v:6094$1376 + attribute \src "ls180.v:6094.60-6094.91" + cell $not $not$ls180.v:6094$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6094$1376_Y + connect \Y $not$ls180.v:6094$1369_Y end attribute \src "ls180.v:6097.61-6097.92" - cell $not $not$ls180.v:6097$1383 + cell $not $not$ls180.v:6097$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6097$1383_Y + connect \Y $not$ls180.v:6097$1376_Y end - attribute \src "ls180.v:6108.59-6108.90" - cell $not $not$ls180.v:6108$1391 + attribute \src "ls180.v:6100.61-6100.92" + cell $not $not$ls180.v:6100$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:6108$1391_Y + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6100$1383_Y end - attribute \src "ls180.v:6111.58-6111.89" - cell $not $not$ls180.v:6111$1398 + attribute \src "ls180.v:6111.59-6111.90" + cell $not $not$ls180.v:6111$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:6111$1398_Y + connect \Y $not$ls180.v:6111$1391_Y end - attribute \src "ls180.v:6122.64-6122.95" - cell $not $not$ls180.v:6122$1406 + attribute \src "ls180.v:6114.58-6114.89" + cell $not $not$ls180.v:6114$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6122$1406_Y + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:6114$1398_Y end - attribute \src "ls180.v:6125.63-6125.94" - cell $not $not$ls180.v:6125$1413 + attribute \src "ls180.v:6125.64-6125.95" + cell $not $not$ls180.v:6125$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6125$1413_Y + connect \Y $not$ls180.v:6125$1406_Y end attribute \src "ls180.v:6128.63-6128.94" - cell $not $not$ls180.v:6128$1420 + cell $not $not$ls180.v:6128$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6128$1420_Y + connect \Y $not$ls180.v:6128$1413_Y end attribute \src "ls180.v:6131.63-6131.94" - cell $not $not$ls180.v:6131$1427 + cell $not $not$ls180.v:6131$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6131$1427_Y + connect \Y $not$ls180.v:6131$1420_Y end attribute \src "ls180.v:6134.63-6134.94" - cell $not $not$ls180.v:6134$1434 + cell $not $not$ls180.v:6134$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6134$1434_Y + connect \Y $not$ls180.v:6134$1427_Y end - attribute \src "ls180.v:6137.64-6137.95" - cell $not $not$ls180.v:6137$1441 + attribute \src "ls180.v:6137.63-6137.94" + cell $not $not$ls180.v:6137$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6137$1441_Y + connect \Y $not$ls180.v:6137$1434_Y end attribute \src "ls180.v:6140.64-6140.95" - cell $not $not$ls180.v:6140$1448 + cell $not $not$ls180.v:6140$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6140$1448_Y + connect \Y $not$ls180.v:6140$1441_Y end attribute \src "ls180.v:6143.64-6143.95" - cell $not $not$ls180.v:6143$1455 + cell $not $not$ls180.v:6143$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6143$1455_Y + connect \Y $not$ls180.v:6143$1448_Y end attribute \src "ls180.v:6146.64-6146.95" - cell $not $not$ls180.v:6146$1462 + cell $not $not$ls180.v:6146$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6146$1462_Y + connect \Y $not$ls180.v:6146$1455_Y end - attribute \src "ls180.v:6159.64-6159.95" - cell $not $not$ls180.v:6159$1470 + attribute \src "ls180.v:6149.64-6149.95" + cell $not $not$ls180.v:6149$1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6159$1470_Y + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6149$1462_Y end - attribute \src "ls180.v:6162.63-6162.94" - cell $not $not$ls180.v:6162$1477 + attribute \src "ls180.v:6162.64-6162.95" + cell $not $not$ls180.v:6162$1470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6162$1477_Y + connect \Y $not$ls180.v:6162$1470_Y end attribute \src "ls180.v:6165.63-6165.94" - cell $not $not$ls180.v:6165$1484 + cell $not $not$ls180.v:6165$1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6165$1484_Y + connect \Y $not$ls180.v:6165$1477_Y end attribute \src "ls180.v:6168.63-6168.94" - cell $not $not$ls180.v:6168$1491 + cell $not $not$ls180.v:6168$1484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6168$1491_Y + connect \Y $not$ls180.v:6168$1484_Y end attribute \src "ls180.v:6171.63-6171.94" - cell $not $not$ls180.v:6171$1498 + cell $not $not$ls180.v:6171$1491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6171$1498_Y + connect \Y $not$ls180.v:6171$1491_Y end - attribute \src "ls180.v:6174.64-6174.95" - cell $not $not$ls180.v:6174$1505 + attribute \src "ls180.v:6174.63-6174.94" + cell $not $not$ls180.v:6174$1498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6174$1505_Y + connect \Y $not$ls180.v:6174$1498_Y end attribute \src "ls180.v:6177.64-6177.95" - cell $not $not$ls180.v:6177$1512 + cell $not $not$ls180.v:6177$1505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6177$1512_Y + connect \Y $not$ls180.v:6177$1505_Y end attribute \src "ls180.v:6180.64-6180.95" - cell $not $not$ls180.v:6180$1519 + cell $not $not$ls180.v:6180$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6180$1519_Y + connect \Y $not$ls180.v:6180$1512_Y end attribute \src "ls180.v:6183.64-6183.95" - cell $not $not$ls180.v:6183$1526 + cell $not $not$ls180.v:6183$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6183$1526_Y + connect \Y $not$ls180.v:6183$1519_Y end - attribute \src "ls180.v:6196.66-6196.97" - cell $not $not$ls180.v:6196$1534 + attribute \src "ls180.v:6186.64-6186.95" + cell $not $not$ls180.v:6186$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6196$1534_Y + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6186$1526_Y end attribute \src "ls180.v:6199.66-6199.97" - cell $not $not$ls180.v:6199$1541 + cell $not $not$ls180.v:6199$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6199$1541_Y + connect \Y $not$ls180.v:6199$1534_Y end attribute \src "ls180.v:6202.66-6202.97" - cell $not $not$ls180.v:6202$1548 + cell $not $not$ls180.v:6202$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6202$1548_Y + connect \Y $not$ls180.v:6202$1541_Y end attribute \src "ls180.v:6205.66-6205.97" - cell $not $not$ls180.v:6205$1555 + cell $not $not$ls180.v:6205$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6205$1555_Y + connect \Y $not$ls180.v:6205$1548_Y end attribute \src "ls180.v:6208.66-6208.97" - cell $not $not$ls180.v:6208$1562 + cell $not $not$ls180.v:6208$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6208$1562_Y + connect \Y $not$ls180.v:6208$1555_Y end attribute \src "ls180.v:6211.66-6211.97" - cell $not $not$ls180.v:6211$1569 + cell $not $not$ls180.v:6211$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6211$1569_Y + connect \Y $not$ls180.v:6211$1562_Y end attribute \src "ls180.v:6214.66-6214.97" - cell $not $not$ls180.v:6214$1576 + cell $not $not$ls180.v:6214$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6214$1576_Y + connect \Y $not$ls180.v:6214$1569_Y end attribute \src "ls180.v:6217.66-6217.97" - cell $not $not$ls180.v:6217$1583 + cell $not $not$ls180.v:6217$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6217$1583_Y + connect \Y $not$ls180.v:6217$1576_Y end - attribute \src "ls180.v:6220.68-6220.99" - cell $not $not$ls180.v:6220$1590 + attribute \src "ls180.v:6220.66-6220.97" + cell $not $not$ls180.v:6220$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6220$1590_Y + connect \Y $not$ls180.v:6220$1583_Y end attribute \src "ls180.v:6223.68-6223.99" - cell $not $not$ls180.v:6223$1597 + cell $not $not$ls180.v:6223$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6223$1597_Y + connect \Y $not$ls180.v:6223$1590_Y end attribute \src "ls180.v:6226.68-6226.99" - cell $not $not$ls180.v:6226$1604 + cell $not $not$ls180.v:6226$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6226$1604_Y + connect \Y $not$ls180.v:6226$1597_Y end attribute \src "ls180.v:6229.68-6229.99" - cell $not $not$ls180.v:6229$1611 + cell $not $not$ls180.v:6229$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6229$1611_Y + connect \Y $not$ls180.v:6229$1604_Y end attribute \src "ls180.v:6232.68-6232.99" - cell $not $not$ls180.v:6232$1618 + cell $not $not$ls180.v:6232$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6232$1618_Y + connect \Y $not$ls180.v:6232$1611_Y end - attribute \src "ls180.v:6235.65-6235.96" - cell $not $not$ls180.v:6235$1625 + attribute \src "ls180.v:6235.68-6235.99" + cell $not $not$ls180.v:6235$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6235$1625_Y + connect \Y $not$ls180.v:6235$1618_Y end - attribute \src "ls180.v:6238.66-6238.97" - cell $not $not$ls180.v:6238$1632 + attribute \src "ls180.v:6238.65-6238.96" + cell $not $not$ls180.v:6238$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6238$1632_Y + connect \Y $not$ls180.v:6238$1625_Y end - attribute \src "ls180.v:6258.70-6258.101" - cell $not $not$ls180.v:6258$1640 + attribute \src "ls180.v:6241.66-6241.97" + cell $not $not$ls180.v:6241$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6258$1640_Y + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6241$1632_Y end attribute \src "ls180.v:6261.70-6261.101" - cell $not $not$ls180.v:6261$1647 + cell $not $not$ls180.v:6261$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6261$1647_Y + connect \Y $not$ls180.v:6261$1640_Y end attribute \src "ls180.v:6264.70-6264.101" - cell $not $not$ls180.v:6264$1654 + cell $not $not$ls180.v:6264$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6264$1654_Y + connect \Y $not$ls180.v:6264$1647_Y end attribute \src "ls180.v:6267.70-6267.101" - cell $not $not$ls180.v:6267$1661 + cell $not $not$ls180.v:6267$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6267$1661_Y + connect \Y $not$ls180.v:6267$1654_Y end - attribute \src "ls180.v:6270.69-6270.100" - cell $not $not$ls180.v:6270$1668 + attribute \src "ls180.v:6270.70-6270.101" + cell $not $not$ls180.v:6270$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6270$1668_Y + connect \Y $not$ls180.v:6270$1661_Y end attribute \src "ls180.v:6273.69-6273.100" - cell $not $not$ls180.v:6273$1675 + cell $not $not$ls180.v:6273$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6273$1675_Y + connect \Y $not$ls180.v:6273$1668_Y end attribute \src "ls180.v:6276.69-6276.100" - cell $not $not$ls180.v:6276$1682 + cell $not $not$ls180.v:6276$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6276$1682_Y + connect \Y $not$ls180.v:6276$1675_Y end attribute \src "ls180.v:6279.69-6279.100" - cell $not $not$ls180.v:6279$1689 + cell $not $not$ls180.v:6279$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6279$1689_Y + connect \Y $not$ls180.v:6279$1682_Y end - attribute \src "ls180.v:6282.60-6282.91" - cell $not $not$ls180.v:6282$1696 + attribute \src "ls180.v:6282.69-6282.100" + cell $not $not$ls180.v:6282$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6282$1696_Y + connect \Y $not$ls180.v:6282$1689_Y end - attribute \src "ls180.v:6285.71-6285.102" - cell $not $not$ls180.v:6285$1703 + attribute \src "ls180.v:6285.60-6285.91" + cell $not $not$ls180.v:6285$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6285$1703_Y + connect \Y $not$ls180.v:6285$1696_Y end attribute \src "ls180.v:6288.71-6288.102" - cell $not $not$ls180.v:6288$1710 + cell $not $not$ls180.v:6288$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6288$1710_Y + connect \Y $not$ls180.v:6288$1703_Y end attribute \src "ls180.v:6291.71-6291.102" - cell $not $not$ls180.v:6291$1717 + cell $not $not$ls180.v:6291$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6291$1717_Y + connect \Y $not$ls180.v:6291$1710_Y end attribute \src "ls180.v:6294.71-6294.102" - cell $not $not$ls180.v:6294$1724 + cell $not $not$ls180.v:6294$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6294$1724_Y + connect \Y $not$ls180.v:6294$1717_Y end attribute \src "ls180.v:6297.71-6297.102" - cell $not $not$ls180.v:6297$1731 + cell $not $not$ls180.v:6297$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6297$1731_Y + connect \Y $not$ls180.v:6297$1724_Y end attribute \src "ls180.v:6300.71-6300.102" - cell $not $not$ls180.v:6300$1738 + cell $not $not$ls180.v:6300$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6300$1738_Y + connect \Y $not$ls180.v:6300$1731_Y end - attribute \src "ls180.v:6303.70-6303.101" - cell $not $not$ls180.v:6303$1745 + attribute \src "ls180.v:6303.71-6303.102" + cell $not $not$ls180.v:6303$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6303$1745_Y + connect \Y $not$ls180.v:6303$1738_Y end attribute \src "ls180.v:6306.70-6306.101" - cell $not $not$ls180.v:6306$1752 + cell $not $not$ls180.v:6306$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6306$1752_Y + connect \Y $not$ls180.v:6306$1745_Y end attribute \src "ls180.v:6309.70-6309.101" - cell $not $not$ls180.v:6309$1759 + cell $not $not$ls180.v:6309$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6309$1759_Y + connect \Y $not$ls180.v:6309$1752_Y end attribute \src "ls180.v:6312.70-6312.101" - cell $not $not$ls180.v:6312$1766 + cell $not $not$ls180.v:6312$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6312$1766_Y + connect \Y $not$ls180.v:6312$1759_Y end attribute \src "ls180.v:6315.70-6315.101" - cell $not $not$ls180.v:6315$1773 + cell $not $not$ls180.v:6315$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6315$1773_Y + connect \Y $not$ls180.v:6315$1766_Y end attribute \src "ls180.v:6318.70-6318.101" - cell $not $not$ls180.v:6318$1780 + cell $not $not$ls180.v:6318$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6318$1780_Y + connect \Y $not$ls180.v:6318$1773_Y end attribute \src "ls180.v:6321.70-6321.101" - cell $not $not$ls180.v:6321$1787 + cell $not $not$ls180.v:6321$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6321$1787_Y + connect \Y $not$ls180.v:6321$1780_Y end attribute \src "ls180.v:6324.70-6324.101" - cell $not $not$ls180.v:6324$1794 + cell $not $not$ls180.v:6324$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6324$1794_Y + connect \Y $not$ls180.v:6324$1787_Y end attribute \src "ls180.v:6327.70-6327.101" - cell $not $not$ls180.v:6327$1801 + cell $not $not$ls180.v:6327$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6327$1801_Y + connect \Y $not$ls180.v:6327$1794_Y end attribute \src "ls180.v:6330.70-6330.101" - cell $not $not$ls180.v:6330$1808 + cell $not $not$ls180.v:6330$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6330$1808_Y + connect \Y $not$ls180.v:6330$1801_Y end - attribute \src "ls180.v:6333.66-6333.97" - cell $not $not$ls180.v:6333$1815 + attribute \src "ls180.v:6333.70-6333.101" + cell $not $not$ls180.v:6333$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6333$1815_Y + connect \Y $not$ls180.v:6333$1808_Y end - attribute \src "ls180.v:6336.67-6336.98" - cell $not $not$ls180.v:6336$1822 + attribute \src "ls180.v:6336.66-6336.97" + cell $not $not$ls180.v:6336$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6336$1822_Y + connect \Y $not$ls180.v:6336$1815_Y end - attribute \src "ls180.v:6339.70-6339.101" - cell $not $not$ls180.v:6339$1829 + attribute \src "ls180.v:6339.67-6339.98" + cell $not $not$ls180.v:6339$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6339$1829_Y + connect \Y $not$ls180.v:6339$1822_Y end attribute \src "ls180.v:6342.70-6342.101" - cell $not $not$ls180.v:6342$1836 + cell $not $not$ls180.v:6342$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6342$1836_Y + connect \Y $not$ls180.v:6342$1829_Y end - attribute \src "ls180.v:6345.69-6345.100" - cell $not $not$ls180.v:6345$1843 + attribute \src "ls180.v:6345.70-6345.101" + cell $not $not$ls180.v:6345$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6345$1843_Y + connect \Y $not$ls180.v:6345$1836_Y end attribute \src "ls180.v:6348.69-6348.100" - cell $not $not$ls180.v:6348$1850 + cell $not $not$ls180.v:6348$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6348$1850_Y + connect \Y $not$ls180.v:6348$1843_Y end attribute \src "ls180.v:6351.69-6351.100" - cell $not $not$ls180.v:6351$1857 + cell $not $not$ls180.v:6351$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6351$1857_Y + connect \Y $not$ls180.v:6351$1850_Y end attribute \src "ls180.v:6354.69-6354.100" - cell $not $not$ls180.v:6354$1864 + cell $not $not$ls180.v:6354$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6354$1864_Y + connect \Y $not$ls180.v:6354$1857_Y end - attribute \src "ls180.v:6393.66-6393.97" - cell $not $not$ls180.v:6393$1872 + attribute \src "ls180.v:6357.69-6357.100" + cell $not $not$ls180.v:6357$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6393$1872_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6357$1864_Y end attribute \src "ls180.v:6396.66-6396.97" - cell $not $not$ls180.v:6396$1879 + cell $not $not$ls180.v:6396$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6396$1879_Y + connect \Y $not$ls180.v:6396$1872_Y end attribute \src "ls180.v:6399.66-6399.97" - cell $not $not$ls180.v:6399$1886 + cell $not $not$ls180.v:6399$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6399$1886_Y + connect \Y $not$ls180.v:6399$1879_Y end attribute \src "ls180.v:6402.66-6402.97" - cell $not $not$ls180.v:6402$1893 + cell $not $not$ls180.v:6402$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6402$1893_Y + connect \Y $not$ls180.v:6402$1886_Y end attribute \src "ls180.v:6405.66-6405.97" - cell $not $not$ls180.v:6405$1900 + cell $not $not$ls180.v:6405$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6405$1900_Y + connect \Y $not$ls180.v:6405$1893_Y end attribute \src "ls180.v:6408.66-6408.97" - cell $not $not$ls180.v:6408$1907 + cell $not $not$ls180.v:6408$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6408$1907_Y + connect \Y $not$ls180.v:6408$1900_Y end attribute \src "ls180.v:6411.66-6411.97" - cell $not $not$ls180.v:6411$1914 + cell $not $not$ls180.v:6411$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6411$1914_Y + connect \Y $not$ls180.v:6411$1907_Y end attribute \src "ls180.v:6414.66-6414.97" - cell $not $not$ls180.v:6414$1921 + cell $not $not$ls180.v:6414$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6414$1921_Y + connect \Y $not$ls180.v:6414$1914_Y end - attribute \src "ls180.v:6417.68-6417.99" - cell $not $not$ls180.v:6417$1928 + attribute \src "ls180.v:6417.66-6417.97" + cell $not $not$ls180.v:6417$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6417$1928_Y + connect \Y $not$ls180.v:6417$1921_Y end attribute \src "ls180.v:6420.68-6420.99" - cell $not $not$ls180.v:6420$1935 + cell $not $not$ls180.v:6420$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6420$1935_Y + connect \Y $not$ls180.v:6420$1928_Y end attribute \src "ls180.v:6423.68-6423.99" - cell $not $not$ls180.v:6423$1942 + cell $not $not$ls180.v:6423$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6423$1942_Y + connect \Y $not$ls180.v:6423$1935_Y end attribute \src "ls180.v:6426.68-6426.99" - cell $not $not$ls180.v:6426$1949 + cell $not $not$ls180.v:6426$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6426$1949_Y + connect \Y $not$ls180.v:6426$1942_Y end attribute \src "ls180.v:6429.68-6429.99" - cell $not $not$ls180.v:6429$1956 + cell $not $not$ls180.v:6429$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6429$1956_Y + connect \Y $not$ls180.v:6429$1949_Y end - attribute \src "ls180.v:6432.65-6432.96" - cell $not $not$ls180.v:6432$1963 + attribute \src "ls180.v:6432.68-6432.99" + cell $not $not$ls180.v:6432$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6432$1963_Y + connect \Y $not$ls180.v:6432$1956_Y end - attribute \src "ls180.v:6435.66-6435.97" - cell $not $not$ls180.v:6435$1970 + attribute \src "ls180.v:6435.65-6435.96" + cell $not $not$ls180.v:6435$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6435$1970_Y + connect \Y $not$ls180.v:6435$1963_Y end - attribute \src "ls180.v:6438.68-6438.99" - cell $not $not$ls180.v:6438$1977 + attribute \src "ls180.v:6438.66-6438.97" + cell $not $not$ls180.v:6438$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6438$1977_Y + connect \Y $not$ls180.v:6438$1970_Y end attribute \src "ls180.v:6441.68-6441.99" - cell $not $not$ls180.v:6441$1984 + cell $not $not$ls180.v:6441$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6441$1984_Y + connect \Y $not$ls180.v:6441$1977_Y end attribute \src "ls180.v:6444.68-6444.99" - cell $not $not$ls180.v:6444$1991 + cell $not $not$ls180.v:6444$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6444$1991_Y + connect \Y $not$ls180.v:6444$1984_Y end attribute \src "ls180.v:6447.68-6447.99" - cell $not $not$ls180.v:6447$1998 + cell $not $not$ls180.v:6447$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6447$1998_Y + connect \Y $not$ls180.v:6447$1991_Y end - attribute \src "ls180.v:6472.68-6472.99" - cell $not $not$ls180.v:6472$2006 + attribute \src "ls180.v:6450.68-6450.99" + cell $not $not$ls180.v:6450$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6472$2006_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6450$1998_Y end - attribute \src "ls180.v:6475.73-6475.104" - cell $not $not$ls180.v:6475$2013 + attribute \src "ls180.v:6475.68-6475.99" + cell $not $not$ls180.v:6475$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6475$2013_Y + connect \Y $not$ls180.v:6475$2006_Y end attribute \src "ls180.v:6478.73-6478.104" - cell $not $not$ls180.v:6478$2020 + cell $not $not$ls180.v:6478$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6478$2020_Y + connect \Y $not$ls180.v:6478$2013_Y end - attribute \src "ls180.v:6481.66-6481.97" - cell $not $not$ls180.v:6481$2027 + attribute \src "ls180.v:6481.73-6481.104" + cell $not $not$ls180.v:6481$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6481$2027_Y + connect \Y $not$ls180.v:6481$2020_Y end - attribute \src "ls180.v:6489.70-6489.101" - cell $not $not$ls180.v:6489$2035 + attribute \src "ls180.v:6484.66-6484.97" + cell $not $not$ls180.v:6484$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6489$2035_Y + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6484$2027_Y end - attribute \src "ls180.v:6492.74-6492.105" - cell $not $not$ls180.v:6492$2042 + attribute \src "ls180.v:6492.70-6492.101" + cell $not $not$ls180.v:6492$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6492$2042_Y + connect \Y $not$ls180.v:6492$2035_Y end - attribute \src "ls180.v:6495.64-6495.95" - cell $not $not$ls180.v:6495$2049 + attribute \src "ls180.v:6495.74-6495.105" + cell $not $not$ls180.v:6495$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6495$2049_Y + connect \Y $not$ls180.v:6495$2042_Y end - attribute \src "ls180.v:6498.74-6498.105" - cell $not $not$ls180.v:6498$2056 + attribute \src "ls180.v:6498.64-6498.95" + cell $not $not$ls180.v:6498$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6498$2056_Y + connect \Y $not$ls180.v:6498$2049_Y end attribute \src "ls180.v:6501.74-6501.105" - cell $not $not$ls180.v:6501$2063 + cell $not $not$ls180.v:6501$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6501$2063_Y + connect \Y $not$ls180.v:6501$2056_Y end - attribute \src "ls180.v:6504.75-6504.106" - cell $not $not$ls180.v:6504$2070 + attribute \src "ls180.v:6504.74-6504.105" + cell $not $not$ls180.v:6504$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6504$2070_Y + connect \Y $not$ls180.v:6504$2063_Y end - attribute \src "ls180.v:6507.73-6507.104" - cell $not $not$ls180.v:6507$2077 + attribute \src "ls180.v:6507.75-6507.106" + cell $not $not$ls180.v:6507$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6507$2077_Y + connect \Y $not$ls180.v:6507$2070_Y end attribute \src "ls180.v:6510.73-6510.104" - cell $not $not$ls180.v:6510$2084 + cell $not $not$ls180.v:6510$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6510$2084_Y + connect \Y $not$ls180.v:6510$2077_Y end attribute \src "ls180.v:6513.73-6513.104" - cell $not $not$ls180.v:6513$2091 + cell $not $not$ls180.v:6513$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6513$2091_Y + connect \Y $not$ls180.v:6513$2084_Y end attribute \src "ls180.v:6516.73-6516.104" - cell $not $not$ls180.v:6516$2098 + cell $not $not$ls180.v:6516$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6516$2098_Y + connect \Y $not$ls180.v:6516$2091_Y end - attribute \src "ls180.v:6534.67-6534.99" - cell $not $not$ls180.v:6534$2106 + attribute \src "ls180.v:6519.73-6519.104" + cell $not $not$ls180.v:6519$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6534$2106_Y + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6519$2098_Y end attribute \src "ls180.v:6537.67-6537.99" - cell $not $not$ls180.v:6537$2113 + cell $not $not$ls180.v:6537$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6537$2113_Y + connect \Y $not$ls180.v:6537$2106_Y end - attribute \src "ls180.v:6540.65-6540.97" - cell $not $not$ls180.v:6540$2120 + attribute \src "ls180.v:6540.67-6540.99" + cell $not $not$ls180.v:6540$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6540$2120_Y + connect \Y $not$ls180.v:6540$2113_Y end - attribute \src "ls180.v:6543.64-6543.96" - cell $not $not$ls180.v:6543$2127 + attribute \src "ls180.v:6543.65-6543.97" + cell $not $not$ls180.v:6543$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6543$2127_Y + connect \Y $not$ls180.v:6543$2120_Y end - attribute \src "ls180.v:6546.63-6546.95" - cell $not $not$ls180.v:6546$2134 + attribute \src "ls180.v:6546.64-6546.96" + cell $not $not$ls180.v:6546$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6546$2134_Y + connect \Y $not$ls180.v:6546$2127_Y end - attribute \src "ls180.v:6549.62-6549.94" - cell $not $not$ls180.v:6549$2141 + attribute \src "ls180.v:6549.63-6549.95" + cell $not $not$ls180.v:6549$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6549$2141_Y + connect \Y $not$ls180.v:6549$2134_Y end - attribute \src "ls180.v:6552.68-6552.100" - cell $not $not$ls180.v:6552$2148 + attribute \src "ls180.v:6552.62-6552.94" + cell $not $not$ls180.v:6552$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6552$2148_Y + connect \Y $not$ls180.v:6552$2141_Y end - attribute \src "ls180.v:6574.67-6574.99" - cell $not $not$ls180.v:6574$2157 + attribute \src "ls180.v:6555.68-6555.100" + cell $not $not$ls180.v:6555$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6574$2157_Y + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6555$2148_Y end attribute \src "ls180.v:6577.67-6577.99" - cell $not $not$ls180.v:6577$2164 + cell $not $not$ls180.v:6577$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6577$2164_Y + connect \Y $not$ls180.v:6577$2157_Y end - attribute \src "ls180.v:6580.65-6580.97" - cell $not $not$ls180.v:6580$2171 + attribute \src "ls180.v:6580.67-6580.99" + cell $not $not$ls180.v:6580$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6580$2171_Y + connect \Y $not$ls180.v:6580$2164_Y end - attribute \src "ls180.v:6583.64-6583.96" - cell $not $not$ls180.v:6583$2178 + attribute \src "ls180.v:6583.65-6583.97" + cell $not $not$ls180.v:6583$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6583$2178_Y + connect \Y $not$ls180.v:6583$2171_Y end - attribute \src "ls180.v:6586.63-6586.95" - cell $not $not$ls180.v:6586$2185 + attribute \src "ls180.v:6586.64-6586.96" + cell $not $not$ls180.v:6586$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6586$2185_Y + connect \Y $not$ls180.v:6586$2178_Y end - attribute \src "ls180.v:6589.62-6589.94" - cell $not $not$ls180.v:6589$2192 + attribute \src "ls180.v:6589.63-6589.95" + cell $not $not$ls180.v:6589$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6589$2192_Y + connect \Y $not$ls180.v:6589$2185_Y end - attribute \src "ls180.v:6592.68-6592.100" - cell $not $not$ls180.v:6592$2199 + attribute \src "ls180.v:6592.62-6592.94" + cell $not $not$ls180.v:6592$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6592$2199_Y + connect \Y $not$ls180.v:6592$2192_Y end - attribute \src "ls180.v:6595.71-6595.103" - cell $not $not$ls180.v:6595$2206 + attribute \src "ls180.v:6595.68-6595.100" + cell $not $not$ls180.v:6595$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6595$2206_Y + connect \Y $not$ls180.v:6595$2199_Y end attribute \src "ls180.v:6598.71-6598.103" - cell $not $not$ls180.v:6598$2213 + cell $not $not$ls180.v:6598$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6598$2213_Y + connect \Y $not$ls180.v:6598$2206_Y end - attribute \src "ls180.v:6622.64-6622.96" - cell $not $not$ls180.v:6622$2222 + attribute \src "ls180.v:6601.71-6601.103" + cell $not $not$ls180.v:6601$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6622$2222_Y + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6601$2213_Y end attribute \src "ls180.v:6625.64-6625.96" - cell $not $not$ls180.v:6625$2229 + cell $not $not$ls180.v:6625$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6625$2229_Y + connect \Y $not$ls180.v:6625$2222_Y end attribute \src "ls180.v:6628.64-6628.96" - cell $not $not$ls180.v:6628$2236 + cell $not $not$ls180.v:6628$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6628$2236_Y + connect \Y $not$ls180.v:6628$2229_Y end attribute \src "ls180.v:6631.64-6631.96" - cell $not $not$ls180.v:6631$2243 + cell $not $not$ls180.v:6631$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6631$2243_Y + connect \Y $not$ls180.v:6631$2236_Y end - attribute \src "ls180.v:6634.66-6634.98" - cell $not $not$ls180.v:6634$2250 + attribute \src "ls180.v:6634.64-6634.96" + cell $not $not$ls180.v:6634$2243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6634$2250_Y + connect \Y $not$ls180.v:6634$2243_Y end attribute \src "ls180.v:6637.66-6637.98" - cell $not $not$ls180.v:6637$2257 + cell $not $not$ls180.v:6637$2250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6637$2257_Y + connect \Y $not$ls180.v:6637$2250_Y end attribute \src "ls180.v:6640.66-6640.98" - cell $not $not$ls180.v:6640$2264 + cell $not $not$ls180.v:6640$2257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6640$2264_Y + connect \Y $not$ls180.v:6640$2257_Y end attribute \src "ls180.v:6643.66-6643.98" - cell $not $not$ls180.v:6643$2271 + cell $not $not$ls180.v:6643$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6643$2271_Y + connect \Y $not$ls180.v:6643$2264_Y end - attribute \src "ls180.v:6646.62-6646.94" - cell $not $not$ls180.v:6646$2278 + attribute \src "ls180.v:6646.66-6646.98" + cell $not $not$ls180.v:6646$2271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6646$2278_Y + connect \Y $not$ls180.v:6646$2271_Y end - attribute \src "ls180.v:6649.72-6649.104" - cell $not $not$ls180.v:6649$2285 + attribute \src "ls180.v:6649.62-6649.94" + cell $not $not$ls180.v:6649$2278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6649$2285_Y + connect \Y $not$ls180.v:6649$2278_Y end - attribute \src "ls180.v:6652.65-6652.97" - cell $not $not$ls180.v:6652$2292 + attribute \src "ls180.v:6652.72-6652.104" + cell $not $not$ls180.v:6652$2285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6652$2292_Y + connect \Y $not$ls180.v:6652$2285_Y end attribute \src "ls180.v:6655.65-6655.97" - cell $not $not$ls180.v:6655$2299 + cell $not $not$ls180.v:6655$2292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6655$2299_Y + connect \Y $not$ls180.v:6655$2292_Y end attribute \src "ls180.v:6658.65-6658.97" - cell $not $not$ls180.v:6658$2306 + cell $not $not$ls180.v:6658$2299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6658$2306_Y + connect \Y $not$ls180.v:6658$2299_Y end attribute \src "ls180.v:6661.65-6661.97" - cell $not $not$ls180.v:6661$2313 + cell $not $not$ls180.v:6661$2306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6661$2313_Y + connect \Y $not$ls180.v:6661$2306_Y end - attribute \src "ls180.v:6664.77-6664.109" - cell $not $not$ls180.v:6664$2320 + attribute \src "ls180.v:6664.65-6664.97" + cell $not $not$ls180.v:6664$2313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6664$2320_Y + connect \Y $not$ls180.v:6664$2313_Y end - attribute \src "ls180.v:6667.78-6667.110" - cell $not $not$ls180.v:6667$2327 + attribute \src "ls180.v:6667.77-6667.109" + cell $not $not$ls180.v:6667$2320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6667$2327_Y + connect \Y $not$ls180.v:6667$2320_Y end - attribute \src "ls180.v:6670.69-6670.101" - cell $not $not$ls180.v:6670$2334 + attribute \src "ls180.v:6670.78-6670.110" + cell $not $not$ls180.v:6670$2327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6670$2334_Y + connect \Y $not$ls180.v:6670$2327_Y end - attribute \src "ls180.v:6690.55-6690.87" - cell $not $not$ls180.v:6690$2342 + attribute \src "ls180.v:6673.69-6673.101" + cell $not $not$ls180.v:6673$2334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6690$2342_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6673$2334_Y end - attribute \src "ls180.v:6693.65-6693.97" - cell $not $not$ls180.v:6693$2349 + attribute \src "ls180.v:6693.55-6693.87" + cell $not $not$ls180.v:6693$2342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6693$2349_Y + connect \Y $not$ls180.v:6693$2342_Y end - attribute \src "ls180.v:6696.66-6696.98" - cell $not $not$ls180.v:6696$2356 + attribute \src "ls180.v:6696.65-6696.97" + cell $not $not$ls180.v:6696$2349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6696$2356_Y + connect \Y $not$ls180.v:6696$2349_Y end - attribute \src "ls180.v:6699.70-6699.102" - cell $not $not$ls180.v:6699$2363 + attribute \src "ls180.v:6699.66-6699.98" + cell $not $not$ls180.v:6699$2356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6699$2363_Y + connect \Y $not$ls180.v:6699$2356_Y end - attribute \src "ls180.v:6702.71-6702.103" - cell $not $not$ls180.v:6702$2370 + attribute \src "ls180.v:6702.70-6702.102" + cell $not $not$ls180.v:6702$2363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6702$2370_Y + connect \Y $not$ls180.v:6702$2363_Y end - attribute \src "ls180.v:6705.69-6705.101" - cell $not $not$ls180.v:6705$2377 + attribute \src "ls180.v:6705.71-6705.103" + cell $not $not$ls180.v:6705$2370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6705$2377_Y + connect \Y $not$ls180.v:6705$2370_Y end - attribute \src "ls180.v:6708.66-6708.98" - cell $not $not$ls180.v:6708$2384 + attribute \src "ls180.v:6708.69-6708.101" + cell $not $not$ls180.v:6708$2377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6708$2384_Y + connect \Y $not$ls180.v:6708$2377_Y end - attribute \src "ls180.v:6711.65-6711.97" - cell $not $not$ls180.v:6711$2391 + attribute \src "ls180.v:6711.66-6711.98" + cell $not $not$ls180.v:6711$2384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6711$2391_Y + connect \Y $not$ls180.v:6711$2384_Y end - attribute \src "ls180.v:6724.71-6724.103" - cell $not $not$ls180.v:6724$2399 + attribute \src "ls180.v:6714.65-6714.97" + cell $not $not$ls180.v:6714$2391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6724$2399_Y + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6714$2391_Y end attribute \src "ls180.v:6727.71-6727.103" - cell $not $not$ls180.v:6727$2406 + cell $not $not$ls180.v:6727$2399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6727$2406_Y + connect \Y $not$ls180.v:6727$2399_Y end attribute \src "ls180.v:6730.71-6730.103" - cell $not $not$ls180.v:6730$2413 + cell $not $not$ls180.v:6730$2406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6730$2413_Y + connect \Y $not$ls180.v:6730$2406_Y end attribute \src "ls180.v:6733.71-6733.103" - cell $not $not$ls180.v:6733$2420 + cell $not $not$ls180.v:6733$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6733$2413_Y + end + attribute \src "ls180.v:6736.71-6736.103" + cell $not $not$ls180.v:6736$2420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6733$2420_Y + connect \Y $not$ls180.v:6736$2420_Y end - attribute \src "ls180.v:7114.86-7114.330" - cell $not $not$ls180.v:7114$2469 + attribute \src "ls180.v:7117.86-7117.330" + cell $not $not$ls180.v:7117$2469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7114$2468_Y - connect \Y $not$ls180.v:7114$2469_Y + connect \A $or$ls180.v:7117$2468_Y + connect \Y $not$ls180.v:7117$2469_Y end - attribute \src "ls180.v:7138.86-7138.330" - cell $not $not$ls180.v:7138$2485 + attribute \src "ls180.v:7141.86-7141.330" + cell $not $not$ls180.v:7141$2485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7138$2484_Y - connect \Y $not$ls180.v:7138$2485_Y + connect \A $or$ls180.v:7141$2484_Y + connect \Y $not$ls180.v:7141$2485_Y end - attribute \src "ls180.v:7162.86-7162.330" - cell $not $not$ls180.v:7162$2501 + attribute \src "ls180.v:7165.86-7165.330" + cell $not $not$ls180.v:7165$2501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7162$2500_Y - connect \Y $not$ls180.v:7162$2501_Y + connect \A $or$ls180.v:7165$2500_Y + connect \Y $not$ls180.v:7165$2501_Y end - attribute \src "ls180.v:7186.86-7186.330" - cell $not $not$ls180.v:7186$2517 + attribute \src "ls180.v:7189.86-7189.330" + cell $not $not$ls180.v:7189$2517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7186$2516_Y - connect \Y $not$ls180.v:7186$2517_Y + connect \A $or$ls180.v:7189$2516_Y + connect \Y $not$ls180.v:7189$2517_Y end - attribute \src "ls180.v:7687.18-7687.42" - cell $not $not$ls180.v:7687$2571 + attribute \src "ls180.v:7690.18-7690.42" + cell $not $not$ls180.v:7690$2571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7687$2571_Y + connect \Y $not$ls180.v:7690$2571_Y end - attribute \src "ls180.v:7766.72-7766.101" - cell $not $not$ls180.v:7766$2604 + attribute \src "ls180.v:7769.72-7769.101" + cell $not $not$ls180.v:7769$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7766$2604_Y + connect \Y $not$ls180.v:7769$2604_Y end - attribute \src "ls180.v:7785.8-7785.38" - cell $not $not$ls180.v:7785$2608 + attribute \src "ls180.v:7788.8-7788.38" + cell $not $not$ls180.v:7788$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7785$2608_Y + connect \Y $not$ls180.v:7788$2608_Y end - attribute \src "ls180.v:7789.70-7789.98" - cell $not $not$ls180.v:7789$2611 + attribute \src "ls180.v:7792.70-7792.98" + cell $not $not$ls180.v:7792$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_ack - connect \Y $not$ls180.v:7789$2611_Y + connect \Y $not$ls180.v:7792$2611_Y end - attribute \src "ls180.v:7793.70-7793.98" - cell $not $not$ls180.v:7793$2614 + attribute \src "ls180.v:7796.70-7796.98" + cell $not $not$ls180.v:7796$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_ack - connect \Y $not$ls180.v:7793$2614_Y + connect \Y $not$ls180.v:7796$2614_Y end - attribute \src "ls180.v:7797.70-7797.98" - cell $not $not$ls180.v:7797$2617 + attribute \src "ls180.v:7800.70-7800.98" + cell $not $not$ls180.v:7800$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_ack - connect \Y $not$ls180.v:7797$2617_Y + connect \Y $not$ls180.v:7800$2617_Y end - attribute \src "ls180.v:7801.70-7801.98" - cell $not $not$ls180.v:7801$2620 + attribute \src "ls180.v:7804.70-7804.98" + cell $not $not$ls180.v:7804$2620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface3_ram_bus_ack - connect \Y $not$ls180.v:7801$2620_Y + connect \Y $not$ls180.v:7804$2620_Y end - attribute \src "ls180.v:7809.32-7809.55" - cell $not $not$ls180.v:7809$2622 + attribute \src "ls180.v:7812.32-7812.55" + cell $not $not$ls180.v:7812$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7809$2622_Y + connect \Y $not$ls180.v:7812$2622_Y end - attribute \src "ls180.v:7879.136-7879.189" - cell $not $not$ls180.v:7879$2637 + attribute \src "ls180.v:7882.136-7882.189" + cell $not $not$ls180.v:7882$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7879$2637_Y + connect \Y $not$ls180.v:7882$2637_Y end - attribute \src "ls180.v:7885.136-7885.189" - cell $not $not$ls180.v:7885$2642 + attribute \src "ls180.v:7888.136-7888.189" + cell $not $not$ls180.v:7888$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7885$2642_Y + connect \Y $not$ls180.v:7888$2642_Y end - attribute \src "ls180.v:7886.8-7886.61" - cell $not $not$ls180.v:7886$2644 + attribute \src "ls180.v:7889.8-7889.61" + cell $not $not$ls180.v:7889$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7886$2644_Y + connect \Y $not$ls180.v:7889$2644_Y end - attribute \src "ls180.v:7894.8-7894.56" - cell $not $not$ls180.v:7894$2647 + attribute \src "ls180.v:7897.8-7897.56" + cell $not $not$ls180.v:7897$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7894$2647_Y + connect \Y $not$ls180.v:7897$2647_Y end - attribute \src "ls180.v:7909.8-7909.46" - cell $not $not$ls180.v:7909$2649 + attribute \src "ls180.v:7912.8-7912.46" + cell $not $not$ls180.v:7912$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7909$2649_Y + connect \Y $not$ls180.v:7912$2649_Y end - attribute \src "ls180.v:7925.136-7925.189" - cell $not $not$ls180.v:7925$2653 + attribute \src "ls180.v:7928.136-7928.189" + cell $not $not$ls180.v:7928$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7925$2653_Y + connect \Y $not$ls180.v:7928$2653_Y end - attribute \src "ls180.v:7931.136-7931.189" - cell $not $not$ls180.v:7931$2658 + attribute \src "ls180.v:7934.136-7934.189" + cell $not $not$ls180.v:7934$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7931$2658_Y + connect \Y $not$ls180.v:7934$2658_Y end - attribute \src "ls180.v:7932.8-7932.61" - cell $not $not$ls180.v:7932$2660 + attribute \src "ls180.v:7935.8-7935.61" + cell $not $not$ls180.v:7935$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7932$2660_Y + connect \Y $not$ls180.v:7935$2660_Y end - attribute \src "ls180.v:7940.8-7940.56" - cell $not $not$ls180.v:7940$2663 + attribute \src "ls180.v:7943.8-7943.56" + cell $not $not$ls180.v:7943$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7940$2663_Y + connect \Y $not$ls180.v:7943$2663_Y end - attribute \src "ls180.v:7955.8-7955.46" - cell $not $not$ls180.v:7955$2665 + attribute \src "ls180.v:7958.8-7958.46" + cell $not $not$ls180.v:7958$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7955$2665_Y + connect \Y $not$ls180.v:7958$2665_Y end - attribute \src "ls180.v:7971.136-7971.189" - cell $not $not$ls180.v:7971$2669 + attribute \src "ls180.v:7974.136-7974.189" + cell $not $not$ls180.v:7974$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7971$2669_Y + connect \Y $not$ls180.v:7974$2669_Y end - attribute \src "ls180.v:7977.136-7977.189" - cell $not $not$ls180.v:7977$2674 + attribute \src "ls180.v:7980.136-7980.189" + cell $not $not$ls180.v:7980$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7977$2674_Y + connect \Y $not$ls180.v:7980$2674_Y end - attribute \src "ls180.v:7978.8-7978.61" - cell $not $not$ls180.v:7978$2676 + attribute \src "ls180.v:7981.8-7981.61" + cell $not $not$ls180.v:7981$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7978$2676_Y + connect \Y $not$ls180.v:7981$2676_Y end - attribute \src "ls180.v:7986.8-7986.56" - cell $not $not$ls180.v:7986$2679 + attribute \src "ls180.v:7989.8-7989.56" + cell $not $not$ls180.v:7989$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7986$2679_Y + connect \Y $not$ls180.v:7989$2679_Y end - attribute \src "ls180.v:8001.8-8001.46" - cell $not $not$ls180.v:8001$2681 + attribute \src "ls180.v:8004.8-8004.46" + cell $not $not$ls180.v:8004$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:8001$2681_Y + connect \Y $not$ls180.v:8004$2681_Y end - attribute \src "ls180.v:8017.136-8017.189" - cell $not $not$ls180.v:8017$2685 + attribute \src "ls180.v:8020.136-8020.189" + cell $not $not$ls180.v:8020$2685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8017$2685_Y + connect \Y $not$ls180.v:8020$2685_Y end - attribute \src "ls180.v:8023.136-8023.189" - cell $not $not$ls180.v:8023$2690 + attribute \src "ls180.v:8026.136-8026.189" + cell $not $not$ls180.v:8026$2690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8023$2690_Y + connect \Y $not$ls180.v:8026$2690_Y end - attribute \src "ls180.v:8024.8-8024.61" - cell $not $not$ls180.v:8024$2692 + attribute \src "ls180.v:8027.8-8027.61" + cell $not $not$ls180.v:8027$2692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:8024$2692_Y + connect \Y $not$ls180.v:8027$2692_Y end - attribute \src "ls180.v:8032.8-8032.56" - cell $not $not$ls180.v:8032$2695 + attribute \src "ls180.v:8035.8-8035.56" + cell $not $not$ls180.v:8035$2695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:8032$2695_Y + connect \Y $not$ls180.v:8035$2695_Y end - attribute \src "ls180.v:8047.8-8047.46" - cell $not $not$ls180.v:8047$2697 + attribute \src "ls180.v:8050.8-8050.46" + cell $not $not$ls180.v:8050$2697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:8047$2697_Y + connect \Y $not$ls180.v:8050$2697_Y end - attribute \src "ls180.v:8055.7-8055.22" - cell $not $not$ls180.v:8055$2700 + attribute \src "ls180.v:8058.7-8058.22" + cell $not $not$ls180.v:8058$2700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:8055$2700_Y + connect \Y $not$ls180.v:8058$2700_Y end - attribute \src "ls180.v:8058.8-8058.29" - cell $not $not$ls180.v:8058$2701 + attribute \src "ls180.v:8061.8-8061.29" + cell $not $not$ls180.v:8061$2701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:8058$2701_Y + connect \Y $not$ls180.v:8061$2701_Y end - attribute \src "ls180.v:8062.7-8062.22" - cell $not $not$ls180.v:8062$2703 + attribute \src "ls180.v:8065.7-8065.22" + cell $not $not$ls180.v:8065$2703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:8062$2703_Y + connect \Y $not$ls180.v:8065$2703_Y end - attribute \src "ls180.v:8065.8-8065.29" - cell $not $not$ls180.v:8065$2704 + attribute \src "ls180.v:8068.8-8068.29" + cell $not $not$ls180.v:8068$2704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:8065$2704_Y + connect \Y $not$ls180.v:8068$2704_Y end - attribute \src "ls180.v:8184.30-8184.60" - cell $not $not$ls180.v:8184$2706 + attribute \src "ls180.v:8187.30-8187.60" + cell $not $not$ls180.v:8187$2706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:8184$2706_Y + connect \Y $not$ls180.v:8187$2706_Y end - attribute \src "ls180.v:8185.30-8185.60" - cell $not $not$ls180.v:8185$2707 + attribute \src "ls180.v:8188.30-8188.60" + cell $not $not$ls180.v:8188$2707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:8185$2707_Y + connect \Y $not$ls180.v:8188$2707_Y end - attribute \src "ls180.v:8186.29-8186.59" - cell $not $not$ls180.v:8186$2708 + attribute \src "ls180.v:8189.29-8189.59" + cell $not $not$ls180.v:8189$2708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:8186$2708_Y + connect \Y $not$ls180.v:8189$2708_Y end - attribute \src "ls180.v:8197.8-8197.33" - cell $not $not$ls180.v:8197$2709 + attribute \src "ls180.v:8200.8-8200.33" + cell $not $not$ls180.v:8200$2709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:8197$2709_Y + connect \Y $not$ls180.v:8200$2709_Y end - attribute \src "ls180.v:8212.8-8212.33" - cell $not $not$ls180.v:8212$2712 + attribute \src "ls180.v:8215.8-8215.33" + cell $not $not$ls180.v:8215$2712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8212$2712_Y + connect \Y $not$ls180.v:8215$2712_Y end - attribute \src "ls180.v:8248.36-8248.58" - cell $not $not$ls180.v:8248$2742 + attribute \src "ls180.v:8251.36-8251.58" + cell $not $not$ls180.v:8251$2742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8248$2742_Y + connect \Y $not$ls180.v:8251$2742_Y end - attribute \src "ls180.v:8248.64-8248.89" - cell $not $not$ls180.v:8248$2744 + attribute \src "ls180.v:8251.64-8251.89" + cell $not $not$ls180.v:8251$2744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8248$2744_Y + connect \Y $not$ls180.v:8251$2744_Y end - attribute \src "ls180.v:8277.7-8277.29" - cell $not $not$ls180.v:8277$2751 + attribute \src "ls180.v:8280.7-8280.29" + cell $not $not$ls180.v:8280$2751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8277$2751_Y + connect \Y $not$ls180.v:8280$2751_Y end - attribute \src "ls180.v:8278.9-8278.26" - cell $not $not$ls180.v:8278$2752 + attribute \src "ls180.v:8281.9-8281.26" + cell $not $not$ls180.v:8281$2752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8278$2752_Y + connect \Y $not$ls180.v:8281$2752_Y end - attribute \src "ls180.v:8311.8-8311.29" - cell $not $not$ls180.v:8311$2758 + attribute \src "ls180.v:8314.8-8314.29" + cell $not $not$ls180.v:8314$2758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8311$2758_Y + connect \Y $not$ls180.v:8314$2758_Y end - attribute \src "ls180.v:8318.8-8318.29" - cell $not $not$ls180.v:8318$2760 + attribute \src "ls180.v:8321.8-8321.29" + cell $not $not$ls180.v:8321$2760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8318$2760_Y + connect \Y $not$ls180.v:8321$2760_Y end - attribute \src "ls180.v:8328.80-8328.106" - cell $not $not$ls180.v:8328$2763 + attribute \src "ls180.v:8331.80-8331.106" + cell $not $not$ls180.v:8331$2763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8328$2763_Y + connect \Y $not$ls180.v:8331$2763_Y end - attribute \src "ls180.v:8334.80-8334.106" - cell $not $not$ls180.v:8334$2768 + attribute \src "ls180.v:8337.80-8337.106" + cell $not $not$ls180.v:8337$2768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8334$2768_Y + connect \Y $not$ls180.v:8337$2768_Y end - attribute \src "ls180.v:8335.8-8335.34" - cell $not $not$ls180.v:8335$2770 + attribute \src "ls180.v:8338.8-8338.34" + cell $not $not$ls180.v:8338$2770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8335$2770_Y + connect \Y $not$ls180.v:8338$2770_Y end - attribute \src "ls180.v:8350.80-8350.106" - cell $not $not$ls180.v:8350$2774 + attribute \src "ls180.v:8353.80-8353.106" + cell $not $not$ls180.v:8353$2774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8350$2774_Y + connect \Y $not$ls180.v:8353$2774_Y end - attribute \src "ls180.v:8356.80-8356.106" - cell $not $not$ls180.v:8356$2779 + attribute \src "ls180.v:8359.80-8359.106" + cell $not $not$ls180.v:8359$2779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8356$2779_Y + connect \Y $not$ls180.v:8359$2779_Y end - attribute \src "ls180.v:8357.8-8357.34" - cell $not $not$ls180.v:8357$2781 + attribute \src "ls180.v:8360.8-8360.34" + cell $not $not$ls180.v:8360$2781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8357$2781_Y + connect \Y $not$ls180.v:8360$2781_Y end - attribute \src "ls180.v:8388.22-8388.41" - cell $not $not$ls180.v:8388$2785 + attribute \src "ls180.v:8391.22-8391.41" + cell $not $not$ls180.v:8391$2785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8388$2785_Y + connect \Y $not$ls180.v:8391$2785_Y end - attribute \src "ls180.v:8388.46-8388.73" - cell $not $not$ls180.v:8388$2786 + attribute \src "ls180.v:8391.46-8391.73" + cell $not $not$ls180.v:8391$2786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8388$2786_Y + connect \Y $not$ls180.v:8391$2786_Y end - attribute \src "ls180.v:8423.22-8423.40" - cell $not $not$ls180.v:8423$2790 + attribute \src "ls180.v:8426.22-8426.40" + cell $not $not$ls180.v:8426$2790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8423$2790_Y + connect \Y $not$ls180.v:8426$2790_Y end - attribute \src "ls180.v:8423.45-8423.70" - cell $not $not$ls180.v:8423$2791 + attribute \src "ls180.v:8426.45-8426.70" + cell $not $not$ls180.v:8426$2791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8423$2791_Y + connect \Y $not$ls180.v:8426$2791_Y end - attribute \src "ls180.v:8477.7-8477.31" - cell $not $not$ls180.v:8477$2802 + attribute \src "ls180.v:8480.7-8480.31" + cell $not $not$ls180.v:8480$2802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8477$2802_Y + connect \Y $not$ls180.v:8480$2802_Y end - attribute \src "ls180.v:8549.8-8549.46" - cell $not $not$ls180.v:8549$2814 + attribute \src "ls180.v:8552.8-8552.46" + cell $not $not$ls180.v:8552$2814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8549$2814_Y + connect \Y $not$ls180.v:8552$2814_Y end - attribute \src "ls180.v:8630.8-8630.47" - cell $not $not$ls180.v:8630$2826 + attribute \src "ls180.v:8633.8-8633.47" + cell $not $not$ls180.v:8633$2826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8630$2826_Y + connect \Y $not$ls180.v:8633$2826_Y end - attribute \src "ls180.v:8691.8-8691.48" - cell $not $not$ls180.v:8691$2838 + attribute \src "ls180.v:8694.8-8694.48" + cell $not $not$ls180.v:8694$2838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8691$2838_Y + connect \Y $not$ls180.v:8694$2838_Y end - attribute \src "ls180.v:8861.88-8861.118" - cell $not $not$ls180.v:8861$2852 + attribute \src "ls180.v:8864.88-8864.118" + cell $not $not$ls180.v:8864$2852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8861$2852_Y + connect \Y $not$ls180.v:8864$2852_Y end - attribute \src "ls180.v:8867.88-8867.118" - cell $not $not$ls180.v:8867$2857 + attribute \src "ls180.v:8870.88-8870.118" + cell $not $not$ls180.v:8870$2857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8867$2857_Y + connect \Y $not$ls180.v:8870$2857_Y end - attribute \src "ls180.v:8868.8-8868.38" - cell $not $not$ls180.v:8868$2859 + attribute \src "ls180.v:8871.8-8871.38" + cell $not $not$ls180.v:8871$2859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8868$2859_Y + connect \Y $not$ls180.v:8871$2859_Y end - attribute \src "ls180.v:8959.88-8959.118" - cell $not $not$ls180.v:8959$2874 + attribute \src "ls180.v:8962.88-8962.118" + cell $not $not$ls180.v:8962$2874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8959$2874_Y + connect \Y $not$ls180.v:8962$2874_Y end - attribute \src "ls180.v:8965.88-8965.118" - cell $not $not$ls180.v:8965$2879 + attribute \src "ls180.v:8968.88-8968.118" + cell $not $not$ls180.v:8968$2879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8965$2879_Y + connect \Y $not$ls180.v:8968$2879_Y end - attribute \src "ls180.v:8966.8-8966.38" - cell $not $not$ls180.v:8966$2881 + attribute \src "ls180.v:8969.8-8969.38" + cell $not $not$ls180.v:8969$2881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8966$2881_Y + connect \Y $not$ls180.v:8969$2881_Y end - attribute \src "ls180.v:8986.9-8986.28" - cell $not $not$ls180.v:8986$2884 + attribute \src "ls180.v:8989.9-8989.28" + cell $not $not$ls180.v:8989$2884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8986$2884_Y + connect \Y $not$ls180.v:8989$2884_Y end - attribute \src "ls180.v:9005.9-9005.28" - cell $not $not$ls180.v:9005$2885 + attribute \src "ls180.v:9008.9-9008.28" + cell $not $not$ls180.v:9008$2885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:9005$2885_Y + connect \Y $not$ls180.v:9008$2885_Y end - attribute \src "ls180.v:9024.9-9024.28" - cell $not $not$ls180.v:9024$2886 + attribute \src "ls180.v:9027.9-9027.28" + cell $not $not$ls180.v:9027$2886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:9024$2886_Y + connect \Y $not$ls180.v:9027$2886_Y end - attribute \src "ls180.v:9043.9-9043.28" - cell $not $not$ls180.v:9043$2887 + attribute \src "ls180.v:9046.9-9046.28" + cell $not $not$ls180.v:9046$2887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:9043$2887_Y + connect \Y $not$ls180.v:9046$2887_Y end - attribute \src "ls180.v:9062.9-9062.28" - cell $not $not$ls180.v:9062$2888 + attribute \src "ls180.v:9065.9-9065.28" + cell $not $not$ls180.v:9065$2888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:9062$2888_Y + connect \Y $not$ls180.v:9065$2888_Y end - attribute \src "ls180.v:9083.8-9083.21" - cell $not $not$ls180.v:9083$2889 + attribute \src "ls180.v:9086.8-9086.21" + cell $not $not$ls180.v:9086$2889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:9083$2889_Y + connect \Y $not$ls180.v:9086$2889_Y end - attribute \src "ls180.v:10685.8-10685.51" - cell $or $or$ls180.v:10685$3077 + attribute \src "ls180.v:10709.8-10709.51" + cell $or $or$ls180.v:10709$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273566,10 +276095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10685$3077_Y + connect \Y $or$ls180.v:10709$3077_Y end - attribute \src "ls180.v:2931.10-2931.71" - cell $or $or$ls180.v:2931$57 + attribute \src "ls180.v:2934.10-2934.71" + cell $or $or$ls180.v:2934$57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273577,10 +276106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_icp_ack connect \B \main_converter0_skip - connect \Y $or$ls180.v:2931$57_Y + connect \Y $or$ls180.v:2934$57_Y end - attribute \src "ls180.v:2991.10-2991.71" - cell $or $or$ls180.v:2991$68 + attribute \src "ls180.v:2994.10-2994.71" + cell $or $or$ls180.v:2994$68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273588,10 +276117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_ics_ack connect \B \main_converter1_skip - connect \Y $or$ls180.v:2991$68_Y + connect \Y $or$ls180.v:2994$68_Y end - attribute \src "ls180.v:3051.10-3051.53" - cell $or $or$ls180.v:3051$79 + attribute \src "ls180.v:3054.10-3054.53" + cell $or $or$ls180.v:3054$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273599,21 +276128,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_ack connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:3051$79_Y + connect \Y $or$ls180.v:3054$79_Y end - attribute \src "ls180.v:3303.39-3303.105" - cell $or $or$ls180.v:3303$223 + attribute \src "ls180.v:3306.39-3306.105" + cell $or $or$ls180.v:3306$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3303$222_Y - connect \Y $or$ls180.v:3303$223_Y + connect \B $ne$ls180.v:3306$222_Y + connect \Y $or$ls180.v:3306$223_Y end - attribute \src "ls180.v:3346.59-3346.140" - cell $or $or$ls180.v:3346$227 + attribute \src "ls180.v:3349.59-3349.140" + cell $or $or$ls180.v:3349$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273621,10 +276150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_req_wdata_ready connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3346$227_Y + connect \Y $or$ls180.v:3349$227_Y end - attribute \src "ls180.v:3347.44-3347.151" - cell $or $or$ls180.v:3347$228 + attribute \src "ls180.v:3350.44-3350.151" + cell $or $or$ls180.v:3350$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273632,21 +276161,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3347$228_Y + connect \Y $or$ls180.v:3350$228_Y end - attribute \src "ls180.v:3355.45-3355.170" - cell $or $or$ls180.v:3355$232 + attribute \src "ls180.v:3358.45-3358.170" + cell $or $or$ls180.v:3358$232 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3355$231_Y + connect \A $sshl$ls180.v:3358$231_Y connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3355$232_Y + connect \Y $or$ls180.v:3358$232_Y end - attribute \src "ls180.v:3392.127-3392.245" - cell $or $or$ls180.v:3392$245 + attribute \src "ls180.v:3395.127-3395.245" + cell $or $or$ls180.v:3395$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273654,21 +276183,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3392$245_Y + connect \Y $or$ls180.v:3395$245_Y end - attribute \src "ls180.v:3398.57-3398.157" - cell $or $or$ls180.v:3398$251 + attribute \src "ls180.v:3401.57-3401.157" + cell $or $or$ls180.v:3401$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3398$250_Y + connect \A $not$ls180.v:3401$250_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3398$251_Y + connect \Y $or$ls180.v:3401$251_Y end - attribute \src "ls180.v:3503.59-3503.140" - cell $or $or$ls180.v:3503$257 + attribute \src "ls180.v:3506.59-3506.140" + cell $or $or$ls180.v:3506$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273676,10 +276205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_req_wdata_ready connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3503$257_Y + connect \Y $or$ls180.v:3506$257_Y end - attribute \src "ls180.v:3504.44-3504.151" - cell $or $or$ls180.v:3504$258 + attribute \src "ls180.v:3507.44-3507.151" + cell $or $or$ls180.v:3507$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273687,21 +276216,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3504$258_Y + connect \Y $or$ls180.v:3507$258_Y end - attribute \src "ls180.v:3512.45-3512.170" - cell $or $or$ls180.v:3512$262 + attribute \src "ls180.v:3515.45-3515.170" + cell $or $or$ls180.v:3515$262 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3512$261_Y + connect \A $sshl$ls180.v:3515$261_Y connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3512$262_Y + connect \Y $or$ls180.v:3515$262_Y end - attribute \src "ls180.v:3549.127-3549.245" - cell $or $or$ls180.v:3549$275 + attribute \src "ls180.v:3552.127-3552.245" + cell $or $or$ls180.v:3552$275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273709,21 +276238,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3549$275_Y + connect \Y $or$ls180.v:3552$275_Y end - attribute \src "ls180.v:3555.57-3555.157" - cell $or $or$ls180.v:3555$281 + attribute \src "ls180.v:3558.57-3558.157" + cell $or $or$ls180.v:3558$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3555$280_Y + connect \A $not$ls180.v:3558$280_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3555$281_Y + connect \Y $or$ls180.v:3558$281_Y end - attribute \src "ls180.v:3660.59-3660.140" - cell $or $or$ls180.v:3660$287 + attribute \src "ls180.v:3663.59-3663.140" + cell $or $or$ls180.v:3663$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273731,10 +276260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_req_wdata_ready connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3660$287_Y + connect \Y $or$ls180.v:3663$287_Y end - attribute \src "ls180.v:3661.44-3661.151" - cell $or $or$ls180.v:3661$288 + attribute \src "ls180.v:3664.44-3664.151" + cell $or $or$ls180.v:3664$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273742,21 +276271,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3661$288_Y + connect \Y $or$ls180.v:3664$288_Y end - attribute \src "ls180.v:3669.45-3669.170" - cell $or $or$ls180.v:3669$292 + attribute \src "ls180.v:3672.45-3672.170" + cell $or $or$ls180.v:3672$292 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3669$291_Y + connect \A $sshl$ls180.v:3672$291_Y connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3669$292_Y + connect \Y $or$ls180.v:3672$292_Y end - attribute \src "ls180.v:3706.127-3706.245" - cell $or $or$ls180.v:3706$305 + attribute \src "ls180.v:3709.127-3709.245" + cell $or $or$ls180.v:3709$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273764,21 +276293,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3706$305_Y + connect \Y $or$ls180.v:3709$305_Y end - attribute \src "ls180.v:3712.57-3712.157" - cell $or $or$ls180.v:3712$311 + attribute \src "ls180.v:3715.57-3715.157" + cell $or $or$ls180.v:3715$311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3712$310_Y + connect \A $not$ls180.v:3715$310_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3712$311_Y + connect \Y $or$ls180.v:3715$311_Y end - attribute \src "ls180.v:3817.59-3817.140" - cell $or $or$ls180.v:3817$317 + attribute \src "ls180.v:3820.59-3820.140" + cell $or $or$ls180.v:3820$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273786,10 +276315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_req_wdata_ready connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3817$317_Y + connect \Y $or$ls180.v:3820$317_Y end - attribute \src "ls180.v:3818.44-3818.151" - cell $or $or$ls180.v:3818$318 + attribute \src "ls180.v:3821.44-3821.151" + cell $or $or$ls180.v:3821$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273797,21 +276326,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3818$318_Y + connect \Y $or$ls180.v:3821$318_Y end - attribute \src "ls180.v:3826.45-3826.170" - cell $or $or$ls180.v:3826$322 + attribute \src "ls180.v:3829.45-3829.170" + cell $or $or$ls180.v:3829$322 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3826$321_Y + connect \A $sshl$ls180.v:3829$321_Y connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3826$322_Y + connect \Y $or$ls180.v:3829$322_Y end - attribute \src "ls180.v:3863.127-3863.245" - cell $or $or$ls180.v:3863$335 + attribute \src "ls180.v:3866.127-3866.245" + cell $or $or$ls180.v:3866$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273819,21 +276348,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3863$335_Y + connect \Y $or$ls180.v:3866$335_Y end - attribute \src "ls180.v:3869.57-3869.157" - cell $or $or$ls180.v:3869$341 + attribute \src "ls180.v:3872.57-3872.157" + cell $or $or$ls180.v:3872$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3869$340_Y + connect \A $not$ls180.v:3872$340_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3869$341_Y + connect \Y $or$ls180.v:3872$341_Y end - attribute \src "ls180.v:3968.107-3968.193" - cell $or $or$ls180.v:3968$361 + attribute \src "ls180.v:3971.107-3971.193" + cell $or $or$ls180.v:3971$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -273841,626 +276370,626 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_is_write connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3968$361_Y + connect \Y $or$ls180.v:3971$361_Y end - attribute \src "ls180.v:3971.39-3971.204" - cell $or $or$ls180.v:3971$367 + attribute \src "ls180.v:3974.39-3974.204" + cell $or $or$ls180.v:3974$367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3971$365_Y - connect \B $and$ls180.v:3971$366_Y - connect \Y $or$ls180.v:3971$367_Y + connect \A $and$ls180.v:3974$365_Y + connect \B $and$ls180.v:3974$366_Y + connect \Y $or$ls180.v:3974$367_Y end - attribute \src "ls180.v:3971.38-3971.289" - cell $or $or$ls180.v:3971$369 + attribute \src "ls180.v:3974.38-3974.289" + cell $or $or$ls180.v:3974$369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3971$367_Y - connect \B $and$ls180.v:3971$368_Y - connect \Y $or$ls180.v:3971$369_Y + connect \A $or$ls180.v:3974$367_Y + connect \B $and$ls180.v:3974$368_Y + connect \Y $or$ls180.v:3974$369_Y end - attribute \src "ls180.v:3971.37-3971.374" - cell $or $or$ls180.v:3971$371 + attribute \src "ls180.v:3974.37-3974.374" + cell $or $or$ls180.v:3974$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3971$369_Y - connect \B $and$ls180.v:3971$370_Y - connect \Y $or$ls180.v:3971$371_Y + connect \A $or$ls180.v:3974$369_Y + connect \B $and$ls180.v:3974$370_Y + connect \Y $or$ls180.v:3974$371_Y end - attribute \src "ls180.v:3972.40-3972.207" - cell $or $or$ls180.v:3972$374 + attribute \src "ls180.v:3975.40-3975.207" + cell $or $or$ls180.v:3975$374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3972$372_Y - connect \B $and$ls180.v:3972$373_Y - connect \Y $or$ls180.v:3972$374_Y + connect \A $and$ls180.v:3975$372_Y + connect \B $and$ls180.v:3975$373_Y + connect \Y $or$ls180.v:3975$374_Y end - attribute \src "ls180.v:3972.39-3972.293" - cell $or $or$ls180.v:3972$376 + attribute \src "ls180.v:3975.39-3975.293" + cell $or $or$ls180.v:3975$376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3972$374_Y - connect \B $and$ls180.v:3972$375_Y - connect \Y $or$ls180.v:3972$376_Y + connect \A $or$ls180.v:3975$374_Y + connect \B $and$ls180.v:3975$375_Y + connect \Y $or$ls180.v:3975$376_Y end - attribute \src "ls180.v:3972.38-3972.379" - cell $or $or$ls180.v:3972$378 + attribute \src "ls180.v:3975.38-3975.379" + cell $or $or$ls180.v:3975$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3972$376_Y - connect \B $and$ls180.v:3972$377_Y - connect \Y $or$ls180.v:3972$378_Y + connect \A $or$ls180.v:3975$376_Y + connect \B $and$ls180.v:3975$377_Y + connect \Y $or$ls180.v:3975$378_Y end - attribute \src "ls180.v:3985.158-3985.332" - cell $or $or$ls180.v:3985$392 + attribute \src "ls180.v:3988.158-3988.332" + cell $or $or$ls180.v:3988$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3985$391_Y + connect \A $not$ls180.v:3988$391_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3985$392_Y + connect \Y $or$ls180.v:3988$392_Y end - attribute \src "ls180.v:3985.75-3985.506" - cell $or $or$ls180.v:3985$397 + attribute \src "ls180.v:3988.75-3988.506" + cell $or $or$ls180.v:3988$397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$393_Y - connect \B $and$ls180.v:3985$396_Y - connect \Y $or$ls180.v:3985$397_Y + connect \A $and$ls180.v:3988$393_Y + connect \B $and$ls180.v:3988$396_Y + connect \Y $or$ls180.v:3988$397_Y end - attribute \src "ls180.v:3986.158-3986.332" - cell $or $or$ls180.v:3986$405 + attribute \src "ls180.v:3989.158-3989.332" + cell $or $or$ls180.v:3989$405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3986$404_Y + connect \A $not$ls180.v:3989$404_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3986$405_Y + connect \Y $or$ls180.v:3989$405_Y end - attribute \src "ls180.v:3986.75-3986.506" - cell $or $or$ls180.v:3986$410 + attribute \src "ls180.v:3989.75-3989.506" + cell $or $or$ls180.v:3989$410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3986$406_Y - connect \B $and$ls180.v:3986$409_Y - connect \Y $or$ls180.v:3986$410_Y + connect \A $and$ls180.v:3989$406_Y + connect \B $and$ls180.v:3989$409_Y + connect \Y $or$ls180.v:3989$410_Y end - attribute \src "ls180.v:3987.158-3987.332" - cell $or $or$ls180.v:3987$418 + attribute \src "ls180.v:3990.158-3990.332" + cell $or $or$ls180.v:3990$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3987$417_Y + connect \A $not$ls180.v:3990$417_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3987$418_Y + connect \Y $or$ls180.v:3990$418_Y end - attribute \src "ls180.v:3987.75-3987.506" - cell $or $or$ls180.v:3987$423 + attribute \src "ls180.v:3990.75-3990.506" + cell $or $or$ls180.v:3990$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3987$419_Y - connect \B $and$ls180.v:3987$422_Y - connect \Y $or$ls180.v:3987$423_Y + connect \A $and$ls180.v:3990$419_Y + connect \B $and$ls180.v:3990$422_Y + connect \Y $or$ls180.v:3990$423_Y end - attribute \src "ls180.v:3988.158-3988.332" - cell $or $or$ls180.v:3988$431 + attribute \src "ls180.v:3991.158-3991.332" + cell $or $or$ls180.v:3991$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3988$430_Y + connect \A $not$ls180.v:3991$430_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3988$431_Y + connect \Y $or$ls180.v:3991$431_Y end - attribute \src "ls180.v:3988.75-3988.506" - cell $or $or$ls180.v:3988$436 + attribute \src "ls180.v:3991.75-3991.506" + cell $or $or$ls180.v:3991$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$432_Y - connect \B $and$ls180.v:3988$435_Y - connect \Y $or$ls180.v:3988$436_Y + connect \A $and$ls180.v:3991$432_Y + connect \B $and$ls180.v:3991$435_Y + connect \Y $or$ls180.v:3991$436_Y end - attribute \src "ls180.v:4015.36-4015.104" - cell $or $or$ls180.v:4015$442 + attribute \src "ls180.v:4018.36-4018.104" + cell $or $or$ls180.v:4018$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:4015$441_Y - connect \Y $or$ls180.v:4015$442_Y + connect \B $not$ls180.v:4018$441_Y + connect \Y $or$ls180.v:4018$442_Y end - attribute \src "ls180.v:4018.158-4018.332" - cell $or $or$ls180.v:4018$450 + attribute \src "ls180.v:4021.158-4021.332" + cell $or $or$ls180.v:4021$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4018$449_Y + connect \A $not$ls180.v:4021$449_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4018$450_Y + connect \Y $or$ls180.v:4021$450_Y end - attribute \src "ls180.v:4018.75-4018.506" - cell $or $or$ls180.v:4018$455 + attribute \src "ls180.v:4021.75-4021.506" + cell $or $or$ls180.v:4021$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4018$451_Y - connect \B $and$ls180.v:4018$454_Y - connect \Y $or$ls180.v:4018$455_Y + connect \A $and$ls180.v:4021$451_Y + connect \B $and$ls180.v:4021$454_Y + connect \Y $or$ls180.v:4021$455_Y end - attribute \src "ls180.v:4019.158-4019.332" - cell $or $or$ls180.v:4019$463 + attribute \src "ls180.v:4022.158-4022.332" + cell $or $or$ls180.v:4022$463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4019$462_Y + connect \A $not$ls180.v:4022$462_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4019$463_Y + connect \Y $or$ls180.v:4022$463_Y end - attribute \src "ls180.v:4019.75-4019.506" - cell $or $or$ls180.v:4019$468 + attribute \src "ls180.v:4022.75-4022.506" + cell $or $or$ls180.v:4022$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4019$464_Y - connect \B $and$ls180.v:4019$467_Y - connect \Y $or$ls180.v:4019$468_Y + connect \A $and$ls180.v:4022$464_Y + connect \B $and$ls180.v:4022$467_Y + connect \Y $or$ls180.v:4022$468_Y end - attribute \src "ls180.v:4020.158-4020.332" - cell $or $or$ls180.v:4020$476 + attribute \src "ls180.v:4023.158-4023.332" + cell $or $or$ls180.v:4023$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4020$475_Y + connect \A $not$ls180.v:4023$475_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4020$476_Y + connect \Y $or$ls180.v:4023$476_Y end - attribute \src "ls180.v:4020.75-4020.506" - cell $or $or$ls180.v:4020$481 + attribute \src "ls180.v:4023.75-4023.506" + cell $or $or$ls180.v:4023$481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4020$477_Y - connect \B $and$ls180.v:4020$480_Y - connect \Y $or$ls180.v:4020$481_Y + connect \A $and$ls180.v:4023$477_Y + connect \B $and$ls180.v:4023$480_Y + connect \Y $or$ls180.v:4023$481_Y end - attribute \src "ls180.v:4021.158-4021.332" - cell $or $or$ls180.v:4021$489 + attribute \src "ls180.v:4024.158-4024.332" + cell $or $or$ls180.v:4024$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4021$488_Y + connect \A $not$ls180.v:4024$488_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4021$489_Y + connect \Y $or$ls180.v:4024$489_Y end - attribute \src "ls180.v:4021.75-4021.506" - cell $or $or$ls180.v:4021$494 + attribute \src "ls180.v:4024.75-4024.506" + cell $or $or$ls180.v:4024$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$490_Y - connect \B $and$ls180.v:4021$493_Y - connect \Y $or$ls180.v:4021$494_Y + connect \A $and$ls180.v:4024$490_Y + connect \B $and$ls180.v:4024$493_Y + connect \Y $or$ls180.v:4024$494_Y end - attribute \src "ls180.v:4084.36-4084.104" - cell $or $or$ls180.v:4084$528 + attribute \src "ls180.v:4087.36-4087.104" + cell $or $or$ls180.v:4087$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:4084$527_Y - connect \Y $or$ls180.v:4084$528_Y + connect \B $not$ls180.v:4087$527_Y + connect \Y $or$ls180.v:4087$528_Y end - attribute \src "ls180.v:4105.67-4105.221" - cell $or $or$ls180.v:4105$535 + attribute \src "ls180.v:4108.67-4108.221" + cell $or $or$ls180.v:4108$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4105$534_Y + connect \A $not$ls180.v:4108$534_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4105$535_Y + connect \Y $or$ls180.v:4108$535_Y end - attribute \src "ls180.v:4113.10-4113.62" - cell $or $or$ls180.v:4113$538 + attribute \src "ls180.v:4116.10-4116.62" + cell $or $or$ls180.v:4116$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4113$537_Y + connect \A $not$ls180.v:4116$537_Y connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:4113$538_Y + connect \Y $or$ls180.v:4116$538_Y end - attribute \src "ls180.v:4143.67-4143.221" - cell $or $or$ls180.v:4143$544 + attribute \src "ls180.v:4146.67-4146.221" + cell $or $or$ls180.v:4146$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4143$543_Y + connect \A $not$ls180.v:4146$543_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4143$544_Y + connect \Y $or$ls180.v:4146$544_Y end - attribute \src "ls180.v:4151.10-4151.61" - cell $or $or$ls180.v:4151$547 + attribute \src "ls180.v:4154.10-4154.61" + cell $or $or$ls180.v:4154$547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4151$546_Y + connect \A $not$ls180.v:4154$546_Y connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:4151$547_Y + connect \Y $or$ls180.v:4154$547_Y end - attribute \src "ls180.v:4161.91-4161.180" - cell $or $or$ls180.v:4161$551 + attribute \src "ls180.v:4164.91-4164.180" + cell $or $or$ls180.v:4164$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4161$550_Y - connect \Y $or$ls180.v:4161$551_Y + connect \B $and$ls180.v:4164$550_Y + connect \Y $or$ls180.v:4164$551_Y end - attribute \src "ls180.v:4161.90-4161.255" - cell $or $or$ls180.v:4161$554 + attribute \src "ls180.v:4164.90-4164.255" + cell $or $or$ls180.v:4164$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4161$551_Y - connect \B $and$ls180.v:4161$553_Y - connect \Y $or$ls180.v:4161$554_Y + connect \A $or$ls180.v:4164$551_Y + connect \B $and$ls180.v:4164$553_Y + connect \Y $or$ls180.v:4164$554_Y end - attribute \src "ls180.v:4161.89-4161.330" - cell $or $or$ls180.v:4161$557 + attribute \src "ls180.v:4164.89-4164.330" + cell $or $or$ls180.v:4164$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4161$554_Y - connect \B $and$ls180.v:4161$556_Y - connect \Y $or$ls180.v:4161$557_Y + connect \A $or$ls180.v:4164$554_Y + connect \B $and$ls180.v:4164$556_Y + connect \Y $or$ls180.v:4164$557_Y end - attribute \src "ls180.v:4166.91-4166.180" - cell $or $or$ls180.v:4166$567 + attribute \src "ls180.v:4169.91-4169.180" + cell $or $or$ls180.v:4169$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4166$566_Y - connect \Y $or$ls180.v:4166$567_Y + connect \B $and$ls180.v:4169$566_Y + connect \Y $or$ls180.v:4169$567_Y end - attribute \src "ls180.v:4166.90-4166.255" - cell $or $or$ls180.v:4166$570 + attribute \src "ls180.v:4169.90-4169.255" + cell $or $or$ls180.v:4169$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4166$567_Y - connect \B $and$ls180.v:4166$569_Y - connect \Y $or$ls180.v:4166$570_Y + connect \A $or$ls180.v:4169$567_Y + connect \B $and$ls180.v:4169$569_Y + connect \Y $or$ls180.v:4169$570_Y end - attribute \src "ls180.v:4166.89-4166.330" - cell $or $or$ls180.v:4166$573 + attribute \src "ls180.v:4169.89-4169.330" + cell $or $or$ls180.v:4169$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4166$570_Y - connect \B $and$ls180.v:4166$572_Y - connect \Y $or$ls180.v:4166$573_Y + connect \A $or$ls180.v:4169$570_Y + connect \B $and$ls180.v:4169$572_Y + connect \Y $or$ls180.v:4169$573_Y end - attribute \src "ls180.v:4171.91-4171.180" - cell $or $or$ls180.v:4171$583 + attribute \src "ls180.v:4174.91-4174.180" + cell $or $or$ls180.v:4174$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4171$582_Y - connect \Y $or$ls180.v:4171$583_Y + connect \B $and$ls180.v:4174$582_Y + connect \Y $or$ls180.v:4174$583_Y end - attribute \src "ls180.v:4171.90-4171.255" - cell $or $or$ls180.v:4171$586 + attribute \src "ls180.v:4174.90-4174.255" + cell $or $or$ls180.v:4174$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4171$583_Y - connect \B $and$ls180.v:4171$585_Y - connect \Y $or$ls180.v:4171$586_Y + connect \A $or$ls180.v:4174$583_Y + connect \B $and$ls180.v:4174$585_Y + connect \Y $or$ls180.v:4174$586_Y end - attribute \src "ls180.v:4171.89-4171.330" - cell $or $or$ls180.v:4171$589 + attribute \src "ls180.v:4174.89-4174.330" + cell $or $or$ls180.v:4174$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4171$586_Y - connect \B $and$ls180.v:4171$588_Y - connect \Y $or$ls180.v:4171$589_Y + connect \A $or$ls180.v:4174$586_Y + connect \B $and$ls180.v:4174$588_Y + connect \Y $or$ls180.v:4174$589_Y end - attribute \src "ls180.v:4176.91-4176.180" - cell $or $or$ls180.v:4176$599 + attribute \src "ls180.v:4179.91-4179.180" + cell $or $or$ls180.v:4179$599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4176$598_Y - connect \Y $or$ls180.v:4176$599_Y + connect \B $and$ls180.v:4179$598_Y + connect \Y $or$ls180.v:4179$599_Y end - attribute \src "ls180.v:4176.90-4176.255" - cell $or $or$ls180.v:4176$602 + attribute \src "ls180.v:4179.90-4179.255" + cell $or $or$ls180.v:4179$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4176$599_Y - connect \B $and$ls180.v:4176$601_Y - connect \Y $or$ls180.v:4176$602_Y + connect \A $or$ls180.v:4179$599_Y + connect \B $and$ls180.v:4179$601_Y + connect \Y $or$ls180.v:4179$602_Y end - attribute \src "ls180.v:4176.89-4176.330" - cell $or $or$ls180.v:4176$605 + attribute \src "ls180.v:4179.89-4179.330" + cell $or $or$ls180.v:4179$605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4176$602_Y - connect \B $and$ls180.v:4176$604_Y - connect \Y $or$ls180.v:4176$605_Y + connect \A $or$ls180.v:4179$602_Y + connect \B $and$ls180.v:4179$604_Y + connect \Y $or$ls180.v:4179$605_Y end - attribute \src "ls180.v:4181.132-4181.221" - cell $or $or$ls180.v:4181$616 + attribute \src "ls180.v:4184.132-4184.221" + cell $or $or$ls180.v:4184$616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4181$615_Y - connect \Y $or$ls180.v:4181$616_Y + connect \B $and$ls180.v:4184$615_Y + connect \Y $or$ls180.v:4184$616_Y end - attribute \src "ls180.v:4181.131-4181.296" - cell $or $or$ls180.v:4181$619 + attribute \src "ls180.v:4184.131-4184.296" + cell $or $or$ls180.v:4184$619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$616_Y - connect \B $and$ls180.v:4181$618_Y - connect \Y $or$ls180.v:4181$619_Y + connect \A $or$ls180.v:4184$616_Y + connect \B $and$ls180.v:4184$618_Y + connect \Y $or$ls180.v:4184$619_Y end - attribute \src "ls180.v:4181.130-4181.371" - cell $or $or$ls180.v:4181$622 + attribute \src "ls180.v:4184.130-4184.371" + cell $or $or$ls180.v:4184$622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$619_Y - connect \B $and$ls180.v:4181$621_Y - connect \Y $or$ls180.v:4181$622_Y + connect \A $or$ls180.v:4184$619_Y + connect \B $and$ls180.v:4184$621_Y + connect \Y $or$ls180.v:4184$622_Y end - attribute \src "ls180.v:4181.34-4181.411" - cell $or $or$ls180.v:4181$627 + attribute \src "ls180.v:4184.34-4184.411" + cell $or $or$ls180.v:4184$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:4181$626_Y - connect \Y $or$ls180.v:4181$627_Y + connect \B $and$ls180.v:4184$626_Y + connect \Y $or$ls180.v:4184$627_Y end - attribute \src "ls180.v:4181.506-4181.595" - cell $or $or$ls180.v:4181$632 + attribute \src "ls180.v:4184.506-4184.595" + cell $or $or$ls180.v:4184$632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4181$631_Y - connect \Y $or$ls180.v:4181$632_Y + connect \B $and$ls180.v:4184$631_Y + connect \Y $or$ls180.v:4184$632_Y end - attribute \src "ls180.v:4181.505-4181.670" - cell $or $or$ls180.v:4181$635 + attribute \src "ls180.v:4184.505-4184.670" + cell $or $or$ls180.v:4184$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$632_Y - connect \B $and$ls180.v:4181$634_Y - connect \Y $or$ls180.v:4181$635_Y + connect \A $or$ls180.v:4184$632_Y + connect \B $and$ls180.v:4184$634_Y + connect \Y $or$ls180.v:4184$635_Y end - attribute \src "ls180.v:4181.504-4181.745" - cell $or $or$ls180.v:4181$638 + attribute \src "ls180.v:4184.504-4184.745" + cell $or $or$ls180.v:4184$638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$635_Y - connect \B $and$ls180.v:4181$637_Y - connect \Y $or$ls180.v:4181$638_Y + connect \A $or$ls180.v:4184$635_Y + connect \B $and$ls180.v:4184$637_Y + connect \Y $or$ls180.v:4184$638_Y end - attribute \src "ls180.v:4181.33-4181.785" - cell $or $or$ls180.v:4181$643 + attribute \src "ls180.v:4184.33-4184.785" + cell $or $or$ls180.v:4184$643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$627_Y - connect \B $and$ls180.v:4181$642_Y - connect \Y $or$ls180.v:4181$643_Y + connect \A $or$ls180.v:4184$627_Y + connect \B $and$ls180.v:4184$642_Y + connect \Y $or$ls180.v:4184$643_Y end - attribute \src "ls180.v:4181.880-4181.969" - cell $or $or$ls180.v:4181$648 + attribute \src "ls180.v:4184.880-4184.969" + cell $or $or$ls180.v:4184$648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4181$647_Y - connect \Y $or$ls180.v:4181$648_Y + connect \B $and$ls180.v:4184$647_Y + connect \Y $or$ls180.v:4184$648_Y end - attribute \src "ls180.v:4181.879-4181.1044" - cell $or $or$ls180.v:4181$651 + attribute \src "ls180.v:4184.879-4184.1044" + cell $or $or$ls180.v:4184$651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$648_Y - connect \B $and$ls180.v:4181$650_Y - connect \Y $or$ls180.v:4181$651_Y + connect \A $or$ls180.v:4184$648_Y + connect \B $and$ls180.v:4184$650_Y + connect \Y $or$ls180.v:4184$651_Y end - attribute \src "ls180.v:4181.878-4181.1119" - cell $or $or$ls180.v:4181$654 + attribute \src "ls180.v:4184.878-4184.1119" + cell $or $or$ls180.v:4184$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$651_Y - connect \B $and$ls180.v:4181$653_Y - connect \Y $or$ls180.v:4181$654_Y + connect \A $or$ls180.v:4184$651_Y + connect \B $and$ls180.v:4184$653_Y + connect \Y $or$ls180.v:4184$654_Y end - attribute \src "ls180.v:4181.32-4181.1159" - cell $or $or$ls180.v:4181$659 + attribute \src "ls180.v:4184.32-4184.1159" + cell $or $or$ls180.v:4184$659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$643_Y - connect \B $and$ls180.v:4181$658_Y - connect \Y $or$ls180.v:4181$659_Y + connect \A $or$ls180.v:4184$643_Y + connect \B $and$ls180.v:4184$658_Y + connect \Y $or$ls180.v:4184$659_Y end - attribute \src "ls180.v:4181.1254-4181.1343" - cell $or $or$ls180.v:4181$664 + attribute \src "ls180.v:4184.1254-4184.1343" + cell $or $or$ls180.v:4184$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4181$663_Y - connect \Y $or$ls180.v:4181$664_Y + connect \B $and$ls180.v:4184$663_Y + connect \Y $or$ls180.v:4184$664_Y end - attribute \src "ls180.v:4181.1253-4181.1418" - cell $or $or$ls180.v:4181$667 + attribute \src "ls180.v:4184.1253-4184.1418" + cell $or $or$ls180.v:4184$667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$664_Y - connect \B $and$ls180.v:4181$666_Y - connect \Y $or$ls180.v:4181$667_Y + connect \A $or$ls180.v:4184$664_Y + connect \B $and$ls180.v:4184$666_Y + connect \Y $or$ls180.v:4184$667_Y end - attribute \src "ls180.v:4181.1252-4181.1493" - cell $or $or$ls180.v:4181$670 + attribute \src "ls180.v:4184.1252-4184.1493" + cell $or $or$ls180.v:4184$670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$667_Y - connect \B $and$ls180.v:4181$669_Y - connect \Y $or$ls180.v:4181$670_Y + connect \A $or$ls180.v:4184$667_Y + connect \B $and$ls180.v:4184$669_Y + connect \Y $or$ls180.v:4184$670_Y end - attribute \src "ls180.v:4181.31-4181.1533" - cell $or $or$ls180.v:4181$675 + attribute \src "ls180.v:4184.31-4184.1533" + cell $or $or$ls180.v:4184$675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$659_Y - connect \B $and$ls180.v:4181$674_Y - connect \Y $or$ls180.v:4181$675_Y + connect \A $or$ls180.v:4184$659_Y + connect \B $and$ls180.v:4184$674_Y + connect \Y $or$ls180.v:4184$675_Y end - attribute \src "ls180.v:4244.10-4244.52" - cell $or $or$ls180.v:4244$684 + attribute \src "ls180.v:4247.10-4247.52" + cell $or $or$ls180.v:4247$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274468,10 +276997,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:4244$684_Y + connect \Y $or$ls180.v:4247$684_Y end - attribute \src "ls180.v:4271.35-4271.74" - cell $or $or$ls180.v:4271$694 + attribute \src "ls180.v:4274.35-4274.74" + cell $or $or$ls180.v:4274$694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274479,10 +277008,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4271$694_Y + connect \Y $or$ls180.v:4274$694_Y end - attribute \src "ls180.v:4272.34-4272.73" - cell $or $or$ls180.v:4272$698 + attribute \src "ls180.v:4275.34-4275.73" + cell $or $or$ls180.v:4275$698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274490,76 +277019,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4272$698_Y + connect \Y $or$ls180.v:4275$698_Y end - attribute \src "ls180.v:4273.48-4273.130" - cell $or $or$ls180.v:4273$704 + attribute \src "ls180.v:4276.48-4276.130" + cell $or $or$ls180.v:4276$704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4273$701_Y - connect \B $and$ls180.v:4273$703_Y - connect \Y $or$ls180.v:4273$704_Y + connect \A $and$ls180.v:4276$701_Y + connect \B $and$ls180.v:4276$703_Y + connect \Y $or$ls180.v:4276$704_Y end - attribute \src "ls180.v:4274.24-4274.87" - cell $or $or$ls180.v:4274$707 + attribute \src "ls180.v:4277.24-4277.87" + cell $or $or$ls180.v:4277$707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4274$706_Y + connect \A $and$ls180.v:4277$706_Y connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4274$707_Y + connect \Y $or$ls180.v:4277$707_Y end - attribute \src "ls180.v:4275.26-4275.95" - cell $or $or$ls180.v:4275$709 + attribute \src "ls180.v:4278.26-4278.95" + cell $or $or$ls180.v:4278$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4275$708_Y + connect \A $and$ls180.v:4278$708_Y connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4275$709_Y + connect \Y $or$ls180.v:4278$709_Y end - attribute \src "ls180.v:4305.42-4305.89" - cell $or $or$ls180.v:4305$717 + attribute \src "ls180.v:4308.42-4308.89" + cell $or $or$ls180.v:4308$717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4305$716_Y - connect \Y $or$ls180.v:4305$717_Y + connect \B $and$ls180.v:4308$716_Y + connect \Y $or$ls180.v:4308$717_Y end - attribute \src "ls180.v:4329.25-4329.174" - cell $or $or$ls180.v:4329$727 + attribute \src "ls180.v:4332.25-4332.174" + cell $or $or$ls180.v:4332$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4329$725_Y - connect \B $and$ls180.v:4329$726_Y - connect \Y $or$ls180.v:4329$727_Y + connect \A $and$ls180.v:4332$725_Y + connect \B $and$ls180.v:4332$726_Y + connect \Y $or$ls180.v:4332$727_Y end - attribute \src "ls180.v:4344.80-4344.132" - cell $or $or$ls180.v:4344$729 + attribute \src "ls180.v:4347.80-4347.132" + cell $or $or$ls180.v:4347$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4344$728_Y + connect \A $not$ls180.v:4347$728_Y connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4344$729_Y + connect \Y $or$ls180.v:4347$729_Y end - attribute \src "ls180.v:4355.72-4355.135" - cell $or $or$ls180.v:4355$734 + attribute \src "ls180.v:4358.72-4358.135" + cell $or $or$ls180.v:4358$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274567,21 +277096,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_writable connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4355$734_Y + connect \Y $or$ls180.v:4358$734_Y end - attribute \src "ls180.v:4374.80-4374.132" - cell $or $or$ls180.v:4374$740 + attribute \src "ls180.v:4377.80-4377.132" + cell $or $or$ls180.v:4377$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4374$739_Y + connect \A $not$ls180.v:4377$739_Y connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4374$740_Y + connect \Y $or$ls180.v:4377$740_Y end - attribute \src "ls180.v:4385.72-4385.135" - cell $or $or$ls180.v:4385$745 + attribute \src "ls180.v:4388.72-4388.135" + cell $or $or$ls180.v:4388$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274589,10 +277118,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_writable connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4385$745_Y + connect \Y $or$ls180.v:4388$745_Y end - attribute \src "ls180.v:4530.36-4530.111" - cell $or $or$ls180.v:4530$768 + attribute \src "ls180.v:4533.36-4533.111" + cell $or $or$ls180.v:4533$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274600,43 +277129,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_clk connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4530$768_Y + connect \Y $or$ls180.v:4533$768_Y end - attribute \src "ls180.v:4530.35-4530.151" - cell $or $or$ls180.v:4530$769 + attribute \src "ls180.v:4533.35-4533.151" + cell $or $or$ls180.v:4533$769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4530$768_Y + connect \A $or$ls180.v:4533$768_Y connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4530$769_Y + connect \Y $or$ls180.v:4533$769_Y end - attribute \src "ls180.v:4530.34-4530.192" - cell $or $or$ls180.v:4530$770 + attribute \src "ls180.v:4533.34-4533.192" + cell $or $or$ls180.v:4533$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4530$769_Y + connect \A $or$ls180.v:4533$769_Y connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4530$770_Y + connect \Y $or$ls180.v:4533$770_Y end - attribute \src "ls180.v:4530.33-4530.233" - cell $or $or$ls180.v:4530$771 + attribute \src "ls180.v:4533.33-4533.233" + cell $or $or$ls180.v:4533$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4530$770_Y + connect \A $or$ls180.v:4533$770_Y connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4530$771_Y + connect \Y $or$ls180.v:4533$771_Y end - attribute \src "ls180.v:4531.39-4531.120" - cell $or $or$ls180.v:4531$772 + attribute \src "ls180.v:4534.39-4534.120" + cell $or $or$ls180.v:4534$772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274644,43 +277173,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_oe connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4531$772_Y + connect \Y $or$ls180.v:4534$772_Y end - attribute \src "ls180.v:4531.38-4531.163" - cell $or $or$ls180.v:4531$773 + attribute \src "ls180.v:4534.38-4534.163" + cell $or $or$ls180.v:4534$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4531$772_Y + connect \A $or$ls180.v:4534$772_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4531$773_Y + connect \Y $or$ls180.v:4534$773_Y end - attribute \src "ls180.v:4531.37-4531.207" - cell $or $or$ls180.v:4531$774 + attribute \src "ls180.v:4534.37-4534.207" + cell $or $or$ls180.v:4534$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4531$773_Y + connect \A $or$ls180.v:4534$773_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4531$774_Y + connect \Y $or$ls180.v:4534$774_Y end - attribute \src "ls180.v:4531.36-4531.251" - cell $or $or$ls180.v:4531$775 + attribute \src "ls180.v:4534.36-4534.251" + cell $or $or$ls180.v:4534$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4531$774_Y + connect \A $or$ls180.v:4534$774_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4531$775_Y + connect \Y $or$ls180.v:4534$775_Y end - attribute \src "ls180.v:4532.38-4532.117" - cell $or $or$ls180.v:4532$776 + attribute \src "ls180.v:4535.38-4535.117" + cell $or $or$ls180.v:4535$776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274688,43 +277217,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_o connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4532$776_Y + connect \Y $or$ls180.v:4535$776_Y end - attribute \src "ls180.v:4532.37-4532.159" - cell $or $or$ls180.v:4532$777 + attribute \src "ls180.v:4535.37-4535.159" + cell $or $or$ls180.v:4535$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4532$776_Y + connect \A $or$ls180.v:4535$776_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4532$777_Y + connect \Y $or$ls180.v:4535$777_Y end - attribute \src "ls180.v:4532.36-4532.202" - cell $or $or$ls180.v:4532$778 + attribute \src "ls180.v:4535.36-4535.202" + cell $or $or$ls180.v:4535$778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4532$777_Y + connect \A $or$ls180.v:4535$777_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4532$778_Y + connect \Y $or$ls180.v:4535$778_Y end - attribute \src "ls180.v:4532.35-4532.245" - cell $or $or$ls180.v:4532$779 + attribute \src "ls180.v:4535.35-4535.245" + cell $or $or$ls180.v:4535$779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4532$778_Y + connect \A $or$ls180.v:4535$778_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4532$779_Y + connect \Y $or$ls180.v:4535$779_Y end - attribute \src "ls180.v:4533.40-4533.123" - cell $or $or$ls180.v:4533$780 + attribute \src "ls180.v:4536.40-4536.123" + cell $or $or$ls180.v:4536$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274732,43 +277261,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_data_oe connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4533$780_Y + connect \Y $or$ls180.v:4536$780_Y end - attribute \src "ls180.v:4533.39-4533.167" - cell $or $or$ls180.v:4533$781 + attribute \src "ls180.v:4536.39-4536.167" + cell $or $or$ls180.v:4536$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$780_Y + connect \A $or$ls180.v:4536$780_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4533$781_Y + connect \Y $or$ls180.v:4536$781_Y end - attribute \src "ls180.v:4533.38-4533.212" - cell $or $or$ls180.v:4533$782 + attribute \src "ls180.v:4536.38-4536.212" + cell $or $or$ls180.v:4536$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$781_Y + connect \A $or$ls180.v:4536$781_Y connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4533$782_Y + connect \Y $or$ls180.v:4536$782_Y end - attribute \src "ls180.v:4533.37-4533.257" - cell $or $or$ls180.v:4533$783 + attribute \src "ls180.v:4536.37-4536.257" + cell $or $or$ls180.v:4536$783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$782_Y + connect \A $or$ls180.v:4536$782_Y connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4533$783_Y + connect \Y $or$ls180.v:4536$783_Y end - attribute \src "ls180.v:4534.39-4534.120" - cell $or $or$ls180.v:4534$784 + attribute \src "ls180.v:4537.39-4537.120" + cell $or $or$ls180.v:4537$784 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274776,43 +277305,43 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_init_pads_out_payload_data_o connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4534$784_Y + connect \Y $or$ls180.v:4537$784_Y end - attribute \src "ls180.v:4534.38-4534.163" - cell $or $or$ls180.v:4534$785 + attribute \src "ls180.v:4537.38-4537.163" + cell $or $or$ls180.v:4537$785 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4534$784_Y + connect \A $or$ls180.v:4537$784_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4534$785_Y + connect \Y $or$ls180.v:4537$785_Y end - attribute \src "ls180.v:4534.37-4534.207" - cell $or $or$ls180.v:4534$786 + attribute \src "ls180.v:4537.37-4537.207" + cell $or $or$ls180.v:4537$786 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4534$785_Y + connect \A $or$ls180.v:4537$785_Y connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4534$786_Y + connect \Y $or$ls180.v:4537$786_Y end - attribute \src "ls180.v:4534.36-4534.251" - cell $or $or$ls180.v:4534$787 + attribute \src "ls180.v:4537.36-4537.251" + cell $or $or$ls180.v:4537$787 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4534$786_Y + connect \A $or$ls180.v:4537$786_Y connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4534$787_Y + connect \Y $or$ls180.v:4537$787_Y end - attribute \src "ls180.v:4555.35-4555.80" - cell $or $or$ls180.v:4555$788 + attribute \src "ls180.v:4558.35-4558.80" + cell $or $or$ls180.v:4558$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274820,10 +277349,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_stop connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4555$788_Y + connect \Y $or$ls180.v:4558$788_Y end - attribute \src "ls180.v:4709.91-4709.144" - cell $or $or$ls180.v:4709$802 + attribute \src "ls180.v:4712.91-4712.144" + cell $or $or$ls180.v:4712$802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274831,76 +277360,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4709$802_Y + connect \Y $or$ls180.v:4712$802_Y end - attribute \src "ls180.v:4726.53-4726.143" - cell $or $or$ls180.v:4726$805 + attribute \src "ls180.v:4729.53-4729.143" + cell $or $or$ls180.v:4729$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4726$804_Y + connect \A $not$ls180.v:4729$804_Y connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4726$805_Y + connect \Y $or$ls180.v:4729$805_Y end - attribute \src "ls180.v:4729.47-4729.127" - cell $or $or$ls180.v:4729$808 + attribute \src "ls180.v:4732.47-4732.127" + cell $or $or$ls180.v:4732$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4729$807_Y + connect \A $not$ls180.v:4732$807_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4729$808_Y + connect \Y $or$ls180.v:4732$808_Y end - attribute \src "ls180.v:4853.54-4853.146" - cell $or $or$ls180.v:4853$826 + attribute \src "ls180.v:4856.54-4856.146" + cell $or $or$ls180.v:4856$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4853$825_Y + connect \A $not$ls180.v:4856$825_Y connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4853$826_Y + connect \Y $or$ls180.v:4856$826_Y end - attribute \src "ls180.v:4856.48-4856.130" - cell $or $or$ls180.v:4856$829 + attribute \src "ls180.v:4859.48-4859.130" + cell $or $or$ls180.v:4859$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4856$828_Y + connect \A $not$ls180.v:4859$828_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4856$829_Y + connect \Y $or$ls180.v:4859$829_Y end - attribute \src "ls180.v:4987.55-4987.149" - cell $or $or$ls180.v:4987$841 + attribute \src "ls180.v:4990.55-4990.149" + cell $or $or$ls180.v:4990$841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4987$840_Y + connect \A $not$ls180.v:4990$840_Y connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4987$841_Y + connect \Y $or$ls180.v:4990$841_Y end - attribute \src "ls180.v:4990.49-4990.133" - cell $or $or$ls180.v:4990$844 + attribute \src "ls180.v:4993.49-4993.133" + cell $or $or$ls180.v:4993$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4990$843_Y + connect \A $not$ls180.v:4993$843_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4990$844_Y + connect \Y $or$ls180.v:4993$844_Y end - attribute \src "ls180.v:5619.80-5619.151" - cell $or $or$ls180.v:5619$1139 + attribute \src "ls180.v:5622.80-5622.151" + cell $or $or$ls180.v:5622$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274908,21 +277437,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_writable connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5619$1139_Y + connect \Y $or$ls180.v:5622$1139_Y end - attribute \src "ls180.v:5630.49-5630.131" - cell $or $or$ls180.v:5630$1145 + attribute \src "ls180.v:5633.49-5633.131" + cell $or $or$ls180.v:5633$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5630$1144_Y + connect \A $not$ls180.v:5633$1144_Y connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5630$1145_Y + connect \Y $or$ls180.v:5633$1145_Y end - attribute \src "ls180.v:5839.80-5839.151" - cell $or $or$ls180.v:5839$1170 + attribute \src "ls180.v:5842.80-5842.151" + cell $or $or$ls180.v:5842$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274930,10 +277459,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_writable connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5839$1170_Y + connect \Y $or$ls180.v:5842$1170_Y end - attribute \src "ls180.v:6026.41-6026.99" - cell $or $or$ls180.v:6026$1226 + attribute \src "ls180.v:6029.41-6029.99" + cell $or $or$ls180.v:6029$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274941,131 +277470,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_err connect \B \main_interface0_ram_bus_err - connect \Y $or$ls180.v:6026$1226_Y + connect \Y $or$ls180.v:6029$1226_Y end - attribute \src "ls180.v:6026.40-6026.130" - cell $or $or$ls180.v:6026$1227 + attribute \src "ls180.v:6029.40-6029.130" + cell $or $or$ls180.v:6029$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1226_Y + connect \A $or$ls180.v:6029$1226_Y connect \B \main_interface1_ram_bus_err - connect \Y $or$ls180.v:6026$1227_Y + connect \Y $or$ls180.v:6029$1227_Y end - attribute \src "ls180.v:6026.39-6026.161" - cell $or $or$ls180.v:6026$1228 + attribute \src "ls180.v:6029.39-6029.161" + cell $or $or$ls180.v:6029$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1227_Y + connect \A $or$ls180.v:6029$1227_Y connect \B \main_interface2_ram_bus_err - connect \Y $or$ls180.v:6026$1228_Y + connect \Y $or$ls180.v:6029$1228_Y end - attribute \src "ls180.v:6026.38-6026.192" - cell $or $or$ls180.v:6026$1229 + attribute \src "ls180.v:6029.38-6029.192" + cell $or $or$ls180.v:6029$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1228_Y + connect \A $or$ls180.v:6029$1228_Y connect \B \main_interface3_ram_bus_err - connect \Y $or$ls180.v:6026$1229_Y + connect \Y $or$ls180.v:6029$1229_Y end - attribute \src "ls180.v:6026.37-6026.235" - cell $or $or$ls180.v:6026$1230 + attribute \src "ls180.v:6029.37-6029.235" + cell $or $or$ls180.v:6029$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1229_Y + connect \A $or$ls180.v:6029$1229_Y connect \B \main_interface0_converted_interface_err - connect \Y $or$ls180.v:6026$1230_Y + connect \Y $or$ls180.v:6029$1230_Y end - attribute \src "ls180.v:6026.36-6026.278" - cell $or $or$ls180.v:6026$1231 + attribute \src "ls180.v:6029.36-6029.278" + cell $or $or$ls180.v:6029$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1230_Y + connect \A $or$ls180.v:6029$1230_Y connect \B \main_interface1_converted_interface_err - connect \Y $or$ls180.v:6026$1231_Y + connect \Y $or$ls180.v:6029$1231_Y end - attribute \src "ls180.v:6026.35-6026.322" - cell $or $or$ls180.v:6026$1232 + attribute \src "ls180.v:6029.35-6029.322" + cell $or $or$ls180.v:6029$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1231_Y + connect \A $or$ls180.v:6029$1231_Y connect \B \main_libresocsim_libresoc_interface0_err - connect \Y $or$ls180.v:6026$1232_Y + connect \Y $or$ls180.v:6029$1232_Y end - attribute \src "ls180.v:6026.34-6026.366" - cell $or $or$ls180.v:6026$1233 + attribute \src "ls180.v:6029.34-6029.366" + cell $or $or$ls180.v:6029$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1232_Y + connect \A $or$ls180.v:6029$1232_Y connect \B \main_libresocsim_libresoc_interface1_err - connect \Y $or$ls180.v:6026$1233_Y + connect \Y $or$ls180.v:6029$1233_Y end - attribute \src "ls180.v:6026.33-6026.410" - cell $or $or$ls180.v:6026$1234 + attribute \src "ls180.v:6029.33-6029.410" + cell $or $or$ls180.v:6029$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1233_Y + connect \A $or$ls180.v:6029$1233_Y connect \B \main_libresocsim_libresoc_interface2_err - connect \Y $or$ls180.v:6026$1234_Y + connect \Y $or$ls180.v:6029$1234_Y end - attribute \src "ls180.v:6026.32-6026.454" - cell $or $or$ls180.v:6026$1235 + attribute \src "ls180.v:6029.32-6029.454" + cell $or $or$ls180.v:6029$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1234_Y + connect \A $or$ls180.v:6029$1234_Y connect \B \main_libresocsim_libresoc_interface3_err - connect \Y $or$ls180.v:6026$1235_Y + connect \Y $or$ls180.v:6029$1235_Y end - attribute \src "ls180.v:6026.31-6026.500" - cell $or $or$ls180.v:6026$1236 + attribute \src "ls180.v:6029.31-6029.500" + cell $or $or$ls180.v:6029$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1235_Y + connect \A $or$ls180.v:6029$1235_Y connect \B \main_socbushandler_converted_interface_err - connect \Y $or$ls180.v:6026$1236_Y + connect \Y $or$ls180.v:6029$1236_Y end - attribute \src "ls180.v:6026.30-6026.547" - cell $or $or$ls180.v:6026$1237 + attribute \src "ls180.v:6029.30-6029.547" + cell $or $or$ls180.v:6029$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1236_Y + connect \A $or$ls180.v:6029$1236_Y connect \B \builder_libresocsim_converted_interface_err - connect \Y $or$ls180.v:6026$1237_Y + connect \Y $or$ls180.v:6029$1237_Y end - attribute \src "ls180.v:6032.36-6032.94" - cell $or $or$ls180.v:6032$1242 + attribute \src "ls180.v:6035.36-6035.94" + cell $or $or$ls180.v:6035$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275073,263 +277602,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack connect \B \main_interface0_ram_bus_ack - connect \Y $or$ls180.v:6032$1242_Y + connect \Y $or$ls180.v:6035$1242_Y end - attribute \src "ls180.v:6032.35-6032.125" - cell $or $or$ls180.v:6032$1243 + attribute \src "ls180.v:6035.35-6035.125" + cell $or $or$ls180.v:6035$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1242_Y + connect \A $or$ls180.v:6035$1242_Y connect \B \main_interface1_ram_bus_ack - connect \Y $or$ls180.v:6032$1243_Y + connect \Y $or$ls180.v:6035$1243_Y end - attribute \src "ls180.v:6032.34-6032.156" - cell $or $or$ls180.v:6032$1244 + attribute \src "ls180.v:6035.34-6035.156" + cell $or $or$ls180.v:6035$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1243_Y + connect \A $or$ls180.v:6035$1243_Y connect \B \main_interface2_ram_bus_ack - connect \Y $or$ls180.v:6032$1244_Y + connect \Y $or$ls180.v:6035$1244_Y end - attribute \src "ls180.v:6032.33-6032.187" - cell $or $or$ls180.v:6032$1245 + attribute \src "ls180.v:6035.33-6035.187" + cell $or $or$ls180.v:6035$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1244_Y + connect \A $or$ls180.v:6035$1244_Y connect \B \main_interface3_ram_bus_ack - connect \Y $or$ls180.v:6032$1245_Y + connect \Y $or$ls180.v:6035$1245_Y end - attribute \src "ls180.v:6032.32-6032.230" - cell $or $or$ls180.v:6032$1246 + attribute \src "ls180.v:6035.32-6035.230" + cell $or $or$ls180.v:6035$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1245_Y + connect \A $or$ls180.v:6035$1245_Y connect \B \main_interface0_converted_interface_ack - connect \Y $or$ls180.v:6032$1246_Y + connect \Y $or$ls180.v:6035$1246_Y end - attribute \src "ls180.v:6032.31-6032.273" - cell $or $or$ls180.v:6032$1247 + attribute \src "ls180.v:6035.31-6035.273" + cell $or $or$ls180.v:6035$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1246_Y + connect \A $or$ls180.v:6035$1246_Y connect \B \main_interface1_converted_interface_ack - connect \Y $or$ls180.v:6032$1247_Y + connect \Y $or$ls180.v:6035$1247_Y end - attribute \src "ls180.v:6032.30-6032.317" - cell $or $or$ls180.v:6032$1248 + attribute \src "ls180.v:6035.30-6035.317" + cell $or $or$ls180.v:6035$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1247_Y + connect \A $or$ls180.v:6035$1247_Y connect \B \main_libresocsim_libresoc_interface0_ack - connect \Y $or$ls180.v:6032$1248_Y + connect \Y $or$ls180.v:6035$1248_Y end - attribute \src "ls180.v:6032.29-6032.361" - cell $or $or$ls180.v:6032$1249 + attribute \src "ls180.v:6035.29-6035.361" + cell $or $or$ls180.v:6035$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1248_Y + connect \A $or$ls180.v:6035$1248_Y connect \B \main_libresocsim_libresoc_interface1_ack - connect \Y $or$ls180.v:6032$1249_Y + connect \Y $or$ls180.v:6035$1249_Y end - attribute \src "ls180.v:6032.28-6032.405" - cell $or $or$ls180.v:6032$1250 + attribute \src "ls180.v:6035.28-6035.405" + cell $or $or$ls180.v:6035$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1249_Y + connect \A $or$ls180.v:6035$1249_Y connect \B \main_libresocsim_libresoc_interface2_ack - connect \Y $or$ls180.v:6032$1250_Y + connect \Y $or$ls180.v:6035$1250_Y end - attribute \src "ls180.v:6032.27-6032.449" - cell $or $or$ls180.v:6032$1251 + attribute \src "ls180.v:6035.27-6035.449" + cell $or $or$ls180.v:6035$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1250_Y + connect \A $or$ls180.v:6035$1250_Y connect \B \main_libresocsim_libresoc_interface3_ack - connect \Y $or$ls180.v:6032$1251_Y + connect \Y $or$ls180.v:6035$1251_Y end - attribute \src "ls180.v:6032.26-6032.495" - cell $or $or$ls180.v:6032$1252 + attribute \src "ls180.v:6035.26-6035.495" + cell $or $or$ls180.v:6035$1252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1251_Y + connect \A $or$ls180.v:6035$1251_Y connect \B \main_socbushandler_converted_interface_ack - connect \Y $or$ls180.v:6032$1252_Y + connect \Y $or$ls180.v:6035$1252_Y end - attribute \src "ls180.v:6032.25-6032.542" - cell $or $or$ls180.v:6032$1253 + attribute \src "ls180.v:6035.25-6035.542" + cell $or $or$ls180.v:6035$1253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1252_Y + connect \A $or$ls180.v:6035$1252_Y connect \B \builder_libresocsim_converted_interface_ack - connect \Y $or$ls180.v:6032$1253_Y + connect \Y $or$ls180.v:6035$1253_Y end - attribute \src "ls180.v:6033.38-6033.166" - cell $or $or$ls180.v:6033$1256 + attribute \src "ls180.v:6036.38-6036.166" + cell $or $or$ls180.v:6036$1256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $and$ls180.v:6033$1254_Y - connect \B $and$ls180.v:6033$1255_Y - connect \Y $or$ls180.v:6033$1256_Y + connect \A $and$ls180.v:6036$1254_Y + connect \B $and$ls180.v:6036$1255_Y + connect \Y $or$ls180.v:6036$1256_Y end - attribute \src "ls180.v:6033.37-6033.232" - cell $or $or$ls180.v:6033$1258 + attribute \src "ls180.v:6036.37-6036.232" + cell $or $or$ls180.v:6036$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1256_Y - connect \B $and$ls180.v:6033$1257_Y - connect \Y $or$ls180.v:6033$1258_Y + connect \A $or$ls180.v:6036$1256_Y + connect \B $and$ls180.v:6036$1257_Y + connect \Y $or$ls180.v:6036$1258_Y end - attribute \src "ls180.v:6033.36-6033.298" - cell $or $or$ls180.v:6033$1260 + attribute \src "ls180.v:6036.36-6036.298" + cell $or $or$ls180.v:6036$1260 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1258_Y - connect \B $and$ls180.v:6033$1259_Y - connect \Y $or$ls180.v:6033$1260_Y + connect \A $or$ls180.v:6036$1258_Y + connect \B $and$ls180.v:6036$1259_Y + connect \Y $or$ls180.v:6036$1260_Y end - attribute \src "ls180.v:6033.35-6033.364" - cell $or $or$ls180.v:6033$1262 + attribute \src "ls180.v:6036.35-6036.364" + cell $or $or$ls180.v:6036$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1260_Y - connect \B $and$ls180.v:6033$1261_Y - connect \Y $or$ls180.v:6033$1262_Y + connect \A $or$ls180.v:6036$1260_Y + connect \B $and$ls180.v:6036$1261_Y + connect \Y $or$ls180.v:6036$1262_Y end - attribute \src "ls180.v:6033.34-6033.442" - cell $or $or$ls180.v:6033$1264 + attribute \src "ls180.v:6036.34-6036.442" + cell $or $or$ls180.v:6036$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1262_Y - connect \B $and$ls180.v:6033$1263_Y - connect \Y $or$ls180.v:6033$1264_Y + connect \A $or$ls180.v:6036$1262_Y + connect \B $and$ls180.v:6036$1263_Y + connect \Y $or$ls180.v:6036$1264_Y end - attribute \src "ls180.v:6033.33-6033.520" - cell $or $or$ls180.v:6033$1266 + attribute \src "ls180.v:6036.33-6036.520" + cell $or $or$ls180.v:6036$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1264_Y - connect \B $and$ls180.v:6033$1265_Y - connect \Y $or$ls180.v:6033$1266_Y + connect \A $or$ls180.v:6036$1264_Y + connect \B $and$ls180.v:6036$1265_Y + connect \Y $or$ls180.v:6036$1266_Y end - attribute \src "ls180.v:6033.32-6033.599" - cell $or $or$ls180.v:6033$1268 + attribute \src "ls180.v:6036.32-6036.599" + cell $or $or$ls180.v:6036$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1266_Y - connect \B $and$ls180.v:6033$1267_Y - connect \Y $or$ls180.v:6033$1268_Y + connect \A $or$ls180.v:6036$1266_Y + connect \B $and$ls180.v:6036$1267_Y + connect \Y $or$ls180.v:6036$1268_Y end - attribute \src "ls180.v:6033.31-6033.678" - cell $or $or$ls180.v:6033$1270 + attribute \src "ls180.v:6036.31-6036.678" + cell $or $or$ls180.v:6036$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1268_Y - connect \B $and$ls180.v:6033$1269_Y - connect \Y $or$ls180.v:6033$1270_Y + connect \A $or$ls180.v:6036$1268_Y + connect \B $and$ls180.v:6036$1269_Y + connect \Y $or$ls180.v:6036$1270_Y end - attribute \src "ls180.v:6033.30-6033.757" - cell $or $or$ls180.v:6033$1272 + attribute \src "ls180.v:6036.30-6036.757" + cell $or $or$ls180.v:6036$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1270_Y - connect \B $and$ls180.v:6033$1271_Y - connect \Y $or$ls180.v:6033$1272_Y + connect \A $or$ls180.v:6036$1270_Y + connect \B $and$ls180.v:6036$1271_Y + connect \Y $or$ls180.v:6036$1272_Y end - attribute \src "ls180.v:6033.29-6033.837" - cell $or $or$ls180.v:6033$1274 + attribute \src "ls180.v:6036.29-6036.837" + cell $or $or$ls180.v:6036$1274 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1272_Y - connect \B $and$ls180.v:6033$1273_Y - connect \Y $or$ls180.v:6033$1274_Y + connect \A $or$ls180.v:6036$1272_Y + connect \B $and$ls180.v:6036$1273_Y + connect \Y $or$ls180.v:6036$1274_Y end - attribute \src "ls180.v:6033.28-6033.919" - cell $or $or$ls180.v:6033$1276 + attribute \src "ls180.v:6036.28-6036.919" + cell $or $or$ls180.v:6036$1276 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1274_Y - connect \B $and$ls180.v:6033$1275_Y - connect \Y $or$ls180.v:6033$1276_Y + connect \A $or$ls180.v:6036$1274_Y + connect \B $and$ls180.v:6036$1275_Y + connect \Y $or$ls180.v:6036$1276_Y end - attribute \src "ls180.v:6033.27-6033.1002" - cell $or $or$ls180.v:6033$1278 + attribute \src "ls180.v:6036.27-6036.1002" + cell $or $or$ls180.v:6036$1278 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1276_Y - connect \B $and$ls180.v:6033$1277_Y - connect \Y $or$ls180.v:6033$1278_Y + connect \A $or$ls180.v:6036$1276_Y + connect \B $and$ls180.v:6036$1277_Y + connect \Y $or$ls180.v:6036$1278_Y end - attribute \src "ls180.v:6787.55-6787.124" - cell $or $or$ls180.v:6787$2424 + attribute \src "ls180.v:6790.55-6790.124" + cell $or $or$ls180.v:6790$2424 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -275337,285 +277866,285 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \builder_interface0_bank_bus_dat_r connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2424_Y + connect \Y $or$ls180.v:6790$2424_Y end - attribute \src "ls180.v:6787.54-6787.161" - cell $or $or$ls180.v:6787$2425 + attribute \src "ls180.v:6790.54-6790.161" + cell $or $or$ls180.v:6790$2425 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2424_Y + connect \A $or$ls180.v:6790$2424_Y connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2425_Y + connect \Y $or$ls180.v:6790$2425_Y end - attribute \src "ls180.v:6787.53-6787.198" - cell $or $or$ls180.v:6787$2426 + attribute \src "ls180.v:6790.53-6790.198" + cell $or $or$ls180.v:6790$2426 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2425_Y + connect \A $or$ls180.v:6790$2425_Y connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2426_Y + connect \Y $or$ls180.v:6790$2426_Y end - attribute \src "ls180.v:6787.52-6787.235" - cell $or $or$ls180.v:6787$2427 + attribute \src "ls180.v:6790.52-6790.235" + cell $or $or$ls180.v:6790$2427 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2426_Y + connect \A $or$ls180.v:6790$2426_Y connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2427_Y + connect \Y $or$ls180.v:6790$2427_Y end - attribute \src "ls180.v:6787.51-6787.272" - cell $or $or$ls180.v:6787$2428 + attribute \src "ls180.v:6790.51-6790.272" + cell $or $or$ls180.v:6790$2428 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2427_Y + connect \A $or$ls180.v:6790$2427_Y connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2428_Y + connect \Y $or$ls180.v:6790$2428_Y end - attribute \src "ls180.v:6787.50-6787.309" - cell $or $or$ls180.v:6787$2429 + attribute \src "ls180.v:6790.50-6790.309" + cell $or $or$ls180.v:6790$2429 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2428_Y + connect \A $or$ls180.v:6790$2428_Y connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2429_Y + connect \Y $or$ls180.v:6790$2429_Y end - attribute \src "ls180.v:6787.49-6787.346" - cell $or $or$ls180.v:6787$2430 + attribute \src "ls180.v:6790.49-6790.346" + cell $or $or$ls180.v:6790$2430 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2429_Y + connect \A $or$ls180.v:6790$2429_Y connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2430_Y + connect \Y $or$ls180.v:6790$2430_Y end - attribute \src "ls180.v:6787.48-6787.383" - cell $or $or$ls180.v:6787$2431 + attribute \src "ls180.v:6790.48-6790.383" + cell $or $or$ls180.v:6790$2431 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2430_Y + connect \A $or$ls180.v:6790$2430_Y connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2431_Y + connect \Y $or$ls180.v:6790$2431_Y end - attribute \src "ls180.v:6787.47-6787.420" - cell $or $or$ls180.v:6787$2432 + attribute \src "ls180.v:6790.47-6790.420" + cell $or $or$ls180.v:6790$2432 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2431_Y + connect \A $or$ls180.v:6790$2431_Y connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2432_Y + connect \Y $or$ls180.v:6790$2432_Y end - attribute \src "ls180.v:6787.46-6787.458" - cell $or $or$ls180.v:6787$2433 + attribute \src "ls180.v:6790.46-6790.458" + cell $or $or$ls180.v:6790$2433 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2432_Y + connect \A $or$ls180.v:6790$2432_Y connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2433_Y + connect \Y $or$ls180.v:6790$2433_Y end - attribute \src "ls180.v:6787.45-6787.496" - cell $or $or$ls180.v:6787$2434 + attribute \src "ls180.v:6790.45-6790.496" + cell $or $or$ls180.v:6790$2434 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2433_Y + connect \A $or$ls180.v:6790$2433_Y connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2434_Y + connect \Y $or$ls180.v:6790$2434_Y end - attribute \src "ls180.v:6787.44-6787.534" - cell $or $or$ls180.v:6787$2435 + attribute \src "ls180.v:6790.44-6790.534" + cell $or $or$ls180.v:6790$2435 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2434_Y + connect \A $or$ls180.v:6790$2434_Y connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2435_Y + connect \Y $or$ls180.v:6790$2435_Y end - attribute \src "ls180.v:6787.43-6787.572" - cell $or $or$ls180.v:6787$2436 + attribute \src "ls180.v:6790.43-6790.572" + cell $or $or$ls180.v:6790$2436 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2435_Y + connect \A $or$ls180.v:6790$2435_Y connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2436_Y + connect \Y $or$ls180.v:6790$2436_Y end - attribute \src "ls180.v:6787.42-6787.610" - cell $or $or$ls180.v:6787$2437 + attribute \src "ls180.v:6790.42-6790.610" + cell $or $or$ls180.v:6790$2437 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2436_Y + connect \A $or$ls180.v:6790$2436_Y connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2437_Y + connect \Y $or$ls180.v:6790$2437_Y end - attribute \src "ls180.v:7114.90-7114.179" - cell $or $or$ls180.v:7114$2462 + attribute \src "ls180.v:7117.90-7117.179" + cell $or $or$ls180.v:7117$2462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:7114$2461_Y - connect \Y $or$ls180.v:7114$2462_Y + connect \B $and$ls180.v:7117$2461_Y + connect \Y $or$ls180.v:7117$2462_Y end - attribute \src "ls180.v:7114.89-7114.254" - cell $or $or$ls180.v:7114$2465 + attribute \src "ls180.v:7117.89-7117.254" + cell $or $or$ls180.v:7117$2465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7114$2462_Y - connect \B $and$ls180.v:7114$2464_Y - connect \Y $or$ls180.v:7114$2465_Y + connect \A $or$ls180.v:7117$2462_Y + connect \B $and$ls180.v:7117$2464_Y + connect \Y $or$ls180.v:7117$2465_Y end - attribute \src "ls180.v:7114.88-7114.329" - cell $or $or$ls180.v:7114$2468 + attribute \src "ls180.v:7117.88-7117.329" + cell $or $or$ls180.v:7117$2468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7114$2465_Y - connect \B $and$ls180.v:7114$2467_Y - connect \Y $or$ls180.v:7114$2468_Y + connect \A $or$ls180.v:7117$2465_Y + connect \B $and$ls180.v:7117$2467_Y + connect \Y $or$ls180.v:7117$2468_Y end - attribute \src "ls180.v:7138.90-7138.179" - cell $or $or$ls180.v:7138$2478 + attribute \src "ls180.v:7141.90-7141.179" + cell $or $or$ls180.v:7141$2478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:7138$2477_Y - connect \Y $or$ls180.v:7138$2478_Y + connect \B $and$ls180.v:7141$2477_Y + connect \Y $or$ls180.v:7141$2478_Y end - attribute \src "ls180.v:7138.89-7138.254" - cell $or $or$ls180.v:7138$2481 + attribute \src "ls180.v:7141.89-7141.254" + cell $or $or$ls180.v:7141$2481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7138$2478_Y - connect \B $and$ls180.v:7138$2480_Y - connect \Y $or$ls180.v:7138$2481_Y + connect \A $or$ls180.v:7141$2478_Y + connect \B $and$ls180.v:7141$2480_Y + connect \Y $or$ls180.v:7141$2481_Y end - attribute \src "ls180.v:7138.88-7138.329" - cell $or $or$ls180.v:7138$2484 + attribute \src "ls180.v:7141.88-7141.329" + cell $or $or$ls180.v:7141$2484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7138$2481_Y - connect \B $and$ls180.v:7138$2483_Y - connect \Y $or$ls180.v:7138$2484_Y + connect \A $or$ls180.v:7141$2481_Y + connect \B $and$ls180.v:7141$2483_Y + connect \Y $or$ls180.v:7141$2484_Y end - attribute \src "ls180.v:7162.90-7162.179" - cell $or $or$ls180.v:7162$2494 + attribute \src "ls180.v:7165.90-7165.179" + cell $or $or$ls180.v:7165$2494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:7162$2493_Y - connect \Y $or$ls180.v:7162$2494_Y + connect \B $and$ls180.v:7165$2493_Y + connect \Y $or$ls180.v:7165$2494_Y end - attribute \src "ls180.v:7162.89-7162.254" - cell $or $or$ls180.v:7162$2497 + attribute \src "ls180.v:7165.89-7165.254" + cell $or $or$ls180.v:7165$2497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7162$2494_Y - connect \B $and$ls180.v:7162$2496_Y - connect \Y $or$ls180.v:7162$2497_Y + connect \A $or$ls180.v:7165$2494_Y + connect \B $and$ls180.v:7165$2496_Y + connect \Y $or$ls180.v:7165$2497_Y end - attribute \src "ls180.v:7162.88-7162.329" - cell $or $or$ls180.v:7162$2500 + attribute \src "ls180.v:7165.88-7165.329" + cell $or $or$ls180.v:7165$2500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7162$2497_Y - connect \B $and$ls180.v:7162$2499_Y - connect \Y $or$ls180.v:7162$2500_Y + connect \A $or$ls180.v:7165$2497_Y + connect \B $and$ls180.v:7165$2499_Y + connect \Y $or$ls180.v:7165$2500_Y end - attribute \src "ls180.v:7186.90-7186.179" - cell $or $or$ls180.v:7186$2510 + attribute \src "ls180.v:7189.90-7189.179" + cell $or $or$ls180.v:7189$2510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:7186$2509_Y - connect \Y $or$ls180.v:7186$2510_Y + connect \B $and$ls180.v:7189$2509_Y + connect \Y $or$ls180.v:7189$2510_Y end - attribute \src "ls180.v:7186.89-7186.254" - cell $or $or$ls180.v:7186$2513 + attribute \src "ls180.v:7189.89-7189.254" + cell $or $or$ls180.v:7189$2513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7186$2510_Y - connect \B $and$ls180.v:7186$2512_Y - connect \Y $or$ls180.v:7186$2513_Y + connect \A $or$ls180.v:7189$2510_Y + connect \B $and$ls180.v:7189$2512_Y + connect \Y $or$ls180.v:7189$2513_Y end - attribute \src "ls180.v:7186.88-7186.329" - cell $or $or$ls180.v:7186$2516 + attribute \src "ls180.v:7189.88-7189.329" + cell $or $or$ls180.v:7189$2516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7186$2513_Y - connect \B $and$ls180.v:7186$2515_Y - connect \Y $or$ls180.v:7186$2516_Y + connect \A $or$ls180.v:7189$2513_Y + connect \B $and$ls180.v:7189$2515_Y + connect \Y $or$ls180.v:7189$2516_Y end - attribute \src "ls180.v:7703.20-7703.71" - cell $or $or$ls180.v:7703$2574 + attribute \src "ls180.v:7706.20-7706.71" + cell $or $or$ls180.v:7706$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275623,10 +278152,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7703$2574_Y + connect \Y $or$ls180.v:7706$2574_Y end - attribute \src "ls180.v:7704.20-7704.71" - cell $or $or$ls180.v:7704$2575 + attribute \src "ls180.v:7707.20-7707.71" + cell $or $or$ls180.v:7707$2575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275634,10 +278163,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7704$2575_Y + connect \Y $or$ls180.v:7707$2575_Y end - attribute \src "ls180.v:7705.20-7705.71" - cell $or $or$ls180.v:7705$2576 + attribute \src "ls180.v:7708.20-7708.71" + cell $or $or$ls180.v:7708$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275645,10 +278174,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7705$2576_Y + connect \Y $or$ls180.v:7708$2576_Y end - attribute \src "ls180.v:7706.20-7706.71" - cell $or $or$ls180.v:7706$2577 + attribute \src "ls180.v:7709.20-7709.71" + cell $or $or$ls180.v:7709$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275656,10 +278185,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7706$2577_Y + connect \Y $or$ls180.v:7709$2577_Y end - attribute \src "ls180.v:7707.20-7707.71" - cell $or $or$ls180.v:7707$2578 + attribute \src "ls180.v:7710.20-7710.71" + cell $or $or$ls180.v:7710$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275667,10 +278196,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7707$2578_Y + connect \Y $or$ls180.v:7710$2578_Y end - attribute \src "ls180.v:7708.20-7708.71" - cell $or $or$ls180.v:7708$2579 + attribute \src "ls180.v:7711.20-7711.71" + cell $or $or$ls180.v:7711$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275678,10 +278207,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7708$2579_Y + connect \Y $or$ls180.v:7711$2579_Y end - attribute \src "ls180.v:7709.20-7709.71" - cell $or $or$ls180.v:7709$2580 + attribute \src "ls180.v:7712.20-7712.71" + cell $or $or$ls180.v:7712$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275689,10 +278218,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7709$2580_Y + connect \Y $or$ls180.v:7712$2580_Y end - attribute \src "ls180.v:7710.20-7710.71" - cell $or $or$ls180.v:7710$2581 + attribute \src "ls180.v:7713.20-7713.71" + cell $or $or$ls180.v:7713$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275700,10 +278229,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7710$2581_Y + connect \Y $or$ls180.v:7713$2581_Y end - attribute \src "ls180.v:7711.20-7711.71" - cell $or $or$ls180.v:7711$2582 + attribute \src "ls180.v:7714.20-7714.71" + cell $or $or$ls180.v:7714$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275711,10 +278240,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7711$2582_Y + connect \Y $or$ls180.v:7714$2582_Y end - attribute \src "ls180.v:7712.20-7712.71" - cell $or $or$ls180.v:7712$2583 + attribute \src "ls180.v:7715.20-7715.71" + cell $or $or$ls180.v:7715$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275722,10 +278251,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7712$2583_Y + connect \Y $or$ls180.v:7715$2583_Y end - attribute \src "ls180.v:7713.21-7713.73" - cell $or $or$ls180.v:7713$2584 + attribute \src "ls180.v:7716.21-7716.73" + cell $or $or$ls180.v:7716$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275733,10 +278262,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7713$2584_Y + connect \Y $or$ls180.v:7716$2584_Y end - attribute \src "ls180.v:7714.21-7714.73" - cell $or $or$ls180.v:7714$2585 + attribute \src "ls180.v:7717.21-7717.73" + cell $or $or$ls180.v:7717$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275744,10 +278273,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7714$2585_Y + connect \Y $or$ls180.v:7717$2585_Y end - attribute \src "ls180.v:7715.21-7715.73" - cell $or $or$ls180.v:7715$2586 + attribute \src "ls180.v:7718.21-7718.73" + cell $or $or$ls180.v:7718$2586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275755,10 +278284,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7715$2586_Y + connect \Y $or$ls180.v:7718$2586_Y end - attribute \src "ls180.v:7716.21-7716.73" - cell $or $or$ls180.v:7716$2587 + attribute \src "ls180.v:7719.21-7719.73" + cell $or $or$ls180.v:7719$2587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275766,10 +278295,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7716$2587_Y + connect \Y $or$ls180.v:7719$2587_Y end - attribute \src "ls180.v:7717.21-7717.73" - cell $or $or$ls180.v:7717$2588 + attribute \src "ls180.v:7720.21-7720.73" + cell $or $or$ls180.v:7720$2588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275777,10 +278306,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7717$2588_Y + connect \Y $or$ls180.v:7720$2588_Y end - attribute \src "ls180.v:7718.21-7718.73" - cell $or $or$ls180.v:7718$2589 + attribute \src "ls180.v:7721.21-7721.73" + cell $or $or$ls180.v:7721$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275788,10 +278317,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7718$2589_Y + connect \Y $or$ls180.v:7721$2589_Y end - attribute \src "ls180.v:7719.21-7719.73" - cell $or $or$ls180.v:7719$2590 + attribute \src "ls180.v:7722.21-7722.73" + cell $or $or$ls180.v:7722$2590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275799,10 +278328,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7719$2590_Y + connect \Y $or$ls180.v:7722$2590_Y end - attribute \src "ls180.v:7720.21-7720.73" - cell $or $or$ls180.v:7720$2591 + attribute \src "ls180.v:7723.21-7723.73" + cell $or $or$ls180.v:7723$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275810,10 +278339,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7720$2591_Y + connect \Y $or$ls180.v:7723$2591_Y end - attribute \src "ls180.v:7721.21-7721.73" - cell $or $or$ls180.v:7721$2592 + attribute \src "ls180.v:7724.21-7724.73" + cell $or $or$ls180.v:7724$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275821,10 +278350,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7721$2592_Y + connect \Y $or$ls180.v:7724$2592_Y end - attribute \src "ls180.v:7722.21-7722.73" - cell $or $or$ls180.v:7722$2593 + attribute \src "ls180.v:7725.21-7725.73" + cell $or $or$ls180.v:7725$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275832,10 +278361,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7722$2593_Y + connect \Y $or$ls180.v:7725$2593_Y end - attribute \src "ls180.v:7723.21-7723.73" - cell $or $or$ls180.v:7723$2594 + attribute \src "ls180.v:7726.21-7726.73" + cell $or $or$ls180.v:7726$2594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275843,10 +278372,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7723$2594_Y + connect \Y $or$ls180.v:7726$2594_Y end - attribute \src "ls180.v:7724.21-7724.73" - cell $or $or$ls180.v:7724$2595 + attribute \src "ls180.v:7727.21-7727.73" + cell $or $or$ls180.v:7727$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275854,10 +278383,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7724$2595_Y + connect \Y $or$ls180.v:7727$2595_Y end - attribute \src "ls180.v:7725.21-7725.73" - cell $or $or$ls180.v:7725$2596 + attribute \src "ls180.v:7728.21-7728.73" + cell $or $or$ls180.v:7728$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275865,10 +278394,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7725$2596_Y + connect \Y $or$ls180.v:7728$2596_Y end - attribute \src "ls180.v:7726.21-7726.73" - cell $or $or$ls180.v:7726$2597 + attribute \src "ls180.v:7729.21-7729.73" + cell $or $or$ls180.v:7729$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275876,10 +278405,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7726$2597_Y + connect \Y $or$ls180.v:7729$2597_Y end - attribute \src "ls180.v:7727.7-7727.68" - cell $or $or$ls180.v:7727$2598 + attribute \src "ls180.v:7730.7-7730.68" + cell $or $or$ls180.v:7730$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275887,10 +278416,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_icp_ack connect \B \main_converter0_skip - connect \Y $or$ls180.v:7727$2598_Y + connect \Y $or$ls180.v:7730$2598_Y end - attribute \src "ls180.v:7738.7-7738.68" - cell $or $or$ls180.v:7738$2599 + attribute \src "ls180.v:7741.7-7741.68" + cell $or $or$ls180.v:7741$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275898,10 +278427,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_ics_ack connect \B \main_converter1_skip - connect \Y $or$ls180.v:7738$2599_Y + connect \Y $or$ls180.v:7741$2599_Y end - attribute \src "ls180.v:7749.7-7749.50" - cell $or $or$ls180.v:7749$2600 + attribute \src "ls180.v:7752.7-7752.50" + cell $or $or$ls180.v:7752$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275909,142 +278438,142 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_ack connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:7749$2600_Y + connect \Y $or$ls180.v:7752$2600_Y end - attribute \src "ls180.v:7894.7-7894.107" - cell $or $or$ls180.v:7894$2648 + attribute \src "ls180.v:7897.7-7897.107" + cell $or $or$ls180.v:7897$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7894$2647_Y + connect \A $not$ls180.v:7897$2647_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7894$2648_Y + connect \Y $or$ls180.v:7897$2648_Y end - attribute \src "ls180.v:7940.7-7940.107" - cell $or $or$ls180.v:7940$2664 + attribute \src "ls180.v:7943.7-7943.107" + cell $or $or$ls180.v:7943$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7940$2663_Y + connect \A $not$ls180.v:7943$2663_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7940$2664_Y + connect \Y $or$ls180.v:7943$2664_Y end - attribute \src "ls180.v:7986.7-7986.107" - cell $or $or$ls180.v:7986$2680 + attribute \src "ls180.v:7989.7-7989.107" + cell $or $or$ls180.v:7989$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7986$2679_Y + connect \A $not$ls180.v:7989$2679_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7986$2680_Y + connect \Y $or$ls180.v:7989$2680_Y end - attribute \src "ls180.v:8032.7-8032.107" - cell $or $or$ls180.v:8032$2696 + attribute \src "ls180.v:8035.7-8035.107" + cell $or $or$ls180.v:8035$2696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8032$2695_Y + connect \A $not$ls180.v:8035$2695_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:8032$2696_Y + connect \Y $or$ls180.v:8035$2696_Y end - attribute \src "ls180.v:8220.40-8220.125" - cell $or $or$ls180.v:8220$2717 + attribute \src "ls180.v:8223.40-8223.125" + cell $or $or$ls180.v:8223$2717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8220$2716_Y - connect \Y $or$ls180.v:8220$2717_Y + connect \B $and$ls180.v:8223$2716_Y + connect \Y $or$ls180.v:8223$2717_Y end - attribute \src "ls180.v:8220.39-8220.207" - cell $or $or$ls180.v:8220$2720 + attribute \src "ls180.v:8223.39-8223.207" + cell $or $or$ls180.v:8223$2720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8220$2717_Y - connect \B $and$ls180.v:8220$2719_Y - connect \Y $or$ls180.v:8220$2720_Y + connect \A $or$ls180.v:8223$2717_Y + connect \B $and$ls180.v:8223$2719_Y + connect \Y $or$ls180.v:8223$2720_Y end - attribute \src "ls180.v:8220.38-8220.289" - cell $or $or$ls180.v:8220$2723 + attribute \src "ls180.v:8223.38-8223.289" + cell $or $or$ls180.v:8223$2723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8220$2720_Y - connect \B $and$ls180.v:8220$2722_Y - connect \Y $or$ls180.v:8220$2723_Y + connect \A $or$ls180.v:8223$2720_Y + connect \B $and$ls180.v:8223$2722_Y + connect \Y $or$ls180.v:8223$2723_Y end - attribute \src "ls180.v:8220.37-8220.371" - cell $or $or$ls180.v:8220$2726 + attribute \src "ls180.v:8223.37-8223.371" + cell $or $or$ls180.v:8223$2726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8220$2723_Y - connect \B $and$ls180.v:8220$2725_Y - connect \Y $or$ls180.v:8220$2726_Y + connect \A $or$ls180.v:8223$2723_Y + connect \B $and$ls180.v:8223$2725_Y + connect \Y $or$ls180.v:8223$2726_Y end - attribute \src "ls180.v:8221.41-8221.126" - cell $or $or$ls180.v:8221$2729 + attribute \src "ls180.v:8224.41-8224.126" + cell $or $or$ls180.v:8224$2729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8221$2728_Y - connect \Y $or$ls180.v:8221$2729_Y + connect \B $and$ls180.v:8224$2728_Y + connect \Y $or$ls180.v:8224$2729_Y end - attribute \src "ls180.v:8221.40-8221.208" - cell $or $or$ls180.v:8221$2732 + attribute \src "ls180.v:8224.40-8224.208" + cell $or $or$ls180.v:8224$2732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8221$2729_Y - connect \B $and$ls180.v:8221$2731_Y - connect \Y $or$ls180.v:8221$2732_Y + connect \A $or$ls180.v:8224$2729_Y + connect \B $and$ls180.v:8224$2731_Y + connect \Y $or$ls180.v:8224$2732_Y end - attribute \src "ls180.v:8221.39-8221.290" - cell $or $or$ls180.v:8221$2735 + attribute \src "ls180.v:8224.39-8224.290" + cell $or $or$ls180.v:8224$2735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8221$2732_Y - connect \B $and$ls180.v:8221$2734_Y - connect \Y $or$ls180.v:8221$2735_Y + connect \A $or$ls180.v:8224$2732_Y + connect \B $and$ls180.v:8224$2734_Y + connect \Y $or$ls180.v:8224$2735_Y end - attribute \src "ls180.v:8221.38-8221.372" - cell $or $or$ls180.v:8221$2738 + attribute \src "ls180.v:8224.38-8224.372" + cell $or $or$ls180.v:8224$2738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8221$2735_Y - connect \B $and$ls180.v:8221$2737_Y - connect \Y $or$ls180.v:8221$2738_Y + connect \A $or$ls180.v:8224$2735_Y + connect \B $and$ls180.v:8224$2737_Y + connect \Y $or$ls180.v:8224$2738_Y end - attribute \src "ls180.v:8225.7-8225.49" - cell $or $or$ls180.v:8225$2739 + attribute \src "ls180.v:8228.7-8228.49" + cell $or $or$ls180.v:8228$2739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276052,32 +278581,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:8225$2739_Y + connect \Y $or$ls180.v:8228$2739_Y end - attribute \src "ls180.v:8388.21-8388.74" - cell $or $or$ls180.v:8388$2787 + attribute \src "ls180.v:8391.21-8391.74" + cell $or $or$ls180.v:8391$2787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8388$2785_Y - connect \B $not$ls180.v:8388$2786_Y - connect \Y $or$ls180.v:8388$2787_Y + connect \A $not$ls180.v:8391$2785_Y + connect \B $not$ls180.v:8391$2786_Y + connect \Y $or$ls180.v:8391$2787_Y end - attribute \src "ls180.v:8423.21-8423.71" - cell $or $or$ls180.v:8423$2792 + attribute \src "ls180.v:8426.21-8426.71" + cell $or $or$ls180.v:8426$2792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8423$2790_Y - connect \B $not$ls180.v:8423$2791_Y - connect \Y $or$ls180.v:8423$2792_Y + connect \A $not$ls180.v:8426$2790_Y + connect \B $not$ls180.v:8426$2791_Y + connect \Y $or$ls180.v:8426$2792_Y end - attribute \src "ls180.v:8491.32-8491.85" - cell $or $or$ls180.v:8491$2804 + attribute \src "ls180.v:8494.32-8494.85" + cell $or $or$ls180.v:8494$2804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276085,21 +278614,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8491$2804_Y + connect \Y $or$ls180.v:8494$2804_Y end - attribute \src "ls180.v:8497.8-8497.97" - cell $or $or$ls180.v:8497$2806 + attribute \src "ls180.v:8500.8-8500.97" + cell $or $or$ls180.v:8500$2806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8497$2805_Y + connect \A $eq$ls180.v:8500$2805_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8497$2806_Y + connect \Y $or$ls180.v:8500$2806_Y end - attribute \src "ls180.v:8514.52-8514.139" - cell $or $or$ls180.v:8514$2811 + attribute \src "ls180.v:8517.52-8517.139" + cell $or $or$ls180.v:8517$2811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276107,10 +278636,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8514$2811_Y + connect \Y $or$ls180.v:8517$2811_Y end - attribute \src "ls180.v:8515.51-8515.136" - cell $or $or$ls180.v:8515$2812 + attribute \src "ls180.v:8518.51-8518.136" + cell $or $or$ls180.v:8518$2812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276118,21 +278647,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8515$2812_Y + connect \Y $or$ls180.v:8518$2812_Y end - attribute \src "ls180.v:8549.7-8549.87" - cell $or $or$ls180.v:8549$2815 + attribute \src "ls180.v:8552.7-8552.87" + cell $or $or$ls180.v:8552$2815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8549$2814_Y + connect \A $not$ls180.v:8552$2814_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8549$2815_Y + connect \Y $or$ls180.v:8552$2815_Y end - attribute \src "ls180.v:8572.33-8572.88" - cell $or $or$ls180.v:8572$2816 + attribute \src "ls180.v:8575.33-8575.88" + cell $or $or$ls180.v:8575$2816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276140,21 +278669,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8572$2816_Y + connect \Y $or$ls180.v:8575$2816_Y end - attribute \src "ls180.v:8578.8-8578.99" - cell $or $or$ls180.v:8578$2818 + attribute \src "ls180.v:8581.8-8581.99" + cell $or $or$ls180.v:8581$2818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8578$2817_Y + connect \A $eq$ls180.v:8581$2817_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8578$2818_Y + connect \Y $or$ls180.v:8581$2818_Y end - attribute \src "ls180.v:8595.53-8595.142" - cell $or $or$ls180.v:8595$2823 + attribute \src "ls180.v:8598.53-8598.142" + cell $or $or$ls180.v:8598$2823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276162,10 +278691,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8595$2823_Y + connect \Y $or$ls180.v:8598$2823_Y end - attribute \src "ls180.v:8596.52-8596.139" - cell $or $or$ls180.v:8596$2824 + attribute \src "ls180.v:8599.52-8599.139" + cell $or $or$ls180.v:8599$2824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276173,21 +278702,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8596$2824_Y + connect \Y $or$ls180.v:8599$2824_Y end - attribute \src "ls180.v:8630.7-8630.89" - cell $or $or$ls180.v:8630$2827 + attribute \src "ls180.v:8633.7-8633.89" + cell $or $or$ls180.v:8633$2827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8630$2826_Y + connect \A $not$ls180.v:8633$2826_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8630$2827_Y + connect \Y $or$ls180.v:8633$2827_Y end - attribute \src "ls180.v:8651.34-8651.91" - cell $or $or$ls180.v:8651$2828 + attribute \src "ls180.v:8654.34-8654.91" + cell $or $or$ls180.v:8654$2828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276195,21 +278724,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8651$2828_Y + connect \Y $or$ls180.v:8654$2828_Y end - attribute \src "ls180.v:8657.8-8657.101" - cell $or $or$ls180.v:8657$2830 + attribute \src "ls180.v:8660.8-8660.101" + cell $or $or$ls180.v:8660$2830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8657$2829_Y + connect \A $eq$ls180.v:8660$2829_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8657$2830_Y + connect \Y $or$ls180.v:8660$2830_Y end - attribute \src "ls180.v:8674.54-8674.145" - cell $or $or$ls180.v:8674$2835 + attribute \src "ls180.v:8677.54-8677.145" + cell $or $or$ls180.v:8677$2835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276217,10 +278746,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8674$2835_Y + connect \Y $or$ls180.v:8677$2835_Y end - attribute \src "ls180.v:8675.53-8675.142" - cell $or $or$ls180.v:8675$2836 + attribute \src "ls180.v:8678.53-8678.142" + cell $or $or$ls180.v:8678$2836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276228,32 +278757,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8675$2836_Y + connect \Y $or$ls180.v:8678$2836_Y end - attribute \src "ls180.v:8691.7-8691.91" - cell $or $or$ls180.v:8691$2839 + attribute \src "ls180.v:8694.7-8694.91" + cell $or $or$ls180.v:8694$2839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8691$2838_Y + connect \A $not$ls180.v:8694$2838_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8691$2839_Y + connect \Y $or$ls180.v:8694$2839_Y end - attribute \src "ls180.v:8880.8-8880.89" - cell $or $or$ls180.v:8880$2863 + attribute \src "ls180.v:8883.8-8883.89" + cell $or $or$ls180.v:8883$2863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8880$2862_Y + connect \A $eq$ls180.v:8883$2862_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8880$2863_Y + connect \Y $or$ls180.v:8883$2863_Y end - attribute \src "ls180.v:8897.48-8897.127" - cell $or $or$ls180.v:8897$2868 + attribute \src "ls180.v:8900.48-8900.127" + cell $or $or$ls180.v:8900$2868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276261,10 +278790,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8897$2868_Y + connect \Y $or$ls180.v:8900$2868_Y end - attribute \src "ls180.v:8898.47-8898.124" - cell $or $or$ls180.v:8898$2869 + attribute \src "ls180.v:8901.47-8901.124" + cell $or $or$ls180.v:8901$2869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276272,10 +278801,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8898$2869_Y + connect \Y $or$ls180.v:8901$2869_Y end - attribute \src "ls180.v:3355.46-3355.94" - cell $sshl $sshl$ls180.v:3355$231 + attribute \src "ls180.v:3358.46-3358.94" + cell $sshl $sshl$ls180.v:3358$231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276283,10 +278812,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine0_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3355$231_Y + connect \Y $sshl$ls180.v:3358$231_Y end - attribute \src "ls180.v:3512.46-3512.94" - cell $sshl $sshl$ls180.v:3512$261 + attribute \src "ls180.v:3515.46-3515.94" + cell $sshl $sshl$ls180.v:3515$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276294,10 +278823,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine1_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3512$261_Y + connect \Y $sshl$ls180.v:3515$261_Y end - attribute \src "ls180.v:3669.46-3669.94" - cell $sshl $sshl$ls180.v:3669$291 + attribute \src "ls180.v:3672.46-3672.94" + cell $sshl $sshl$ls180.v:3672$291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276305,10 +278834,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine2_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3669$291_Y + connect \Y $sshl$ls180.v:3672$291_Y end - attribute \src "ls180.v:3826.46-3826.94" - cell $sshl $sshl$ls180.v:3826$321 + attribute \src "ls180.v:3829.46-3829.94" + cell $sshl $sshl$ls180.v:3829$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276316,10 +278845,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine3_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3826$321_Y + connect \Y $sshl$ls180.v:3829$321_Y end - attribute \src "ls180.v:3386.63-3386.122" - cell $sub $sub$ls180.v:3386$244 + attribute \src "ls180.v:3389.63-3389.122" + cell $sub $sub$ls180.v:3389$244 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276327,10 +278856,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3386$244_Y + connect \Y $sub$ls180.v:3389$244_Y end - attribute \src "ls180.v:3543.63-3543.122" - cell $sub $sub$ls180.v:3543$274 + attribute \src "ls180.v:3546.63-3546.122" + cell $sub $sub$ls180.v:3546$274 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276338,10 +278867,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3543$274_Y + connect \Y $sub$ls180.v:3546$274_Y end - attribute \src "ls180.v:3700.63-3700.122" - cell $sub $sub$ls180.v:3700$304 + attribute \src "ls180.v:3703.63-3703.122" + cell $sub $sub$ls180.v:3703$304 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276349,10 +278878,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3700$304_Y + connect \Y $sub$ls180.v:3703$304_Y end - attribute \src "ls180.v:3857.63-3857.122" - cell $sub $sub$ls180.v:3857$334 + attribute \src "ls180.v:3860.63-3860.122" + cell $sub $sub$ls180.v:3860$334 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276360,10 +278889,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3857$334_Y + connect \Y $sub$ls180.v:3860$334_Y end - attribute \src "ls180.v:4263.38-4263.75" - cell $sub $sub$ls180.v:4263$688 + attribute \src "ls180.v:4266.38-4266.75" + cell $sub $sub$ls180.v:4266$688 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 @@ -276371,10 +278900,10 @@ module \ls180 parameter \Y_WIDTH 31 connect \A \main_litedram_wb_adr connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4263$688_Y + connect \Y $sub$ls180.v:4266$688_Y end - attribute \src "ls180.v:4349.36-4349.68" - cell $sub $sub$ls180.v:4349$733 + attribute \src "ls180.v:4352.36-4352.68" + cell $sub $sub$ls180.v:4352$733 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -276382,10 +278911,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4349$733_Y + connect \Y $sub$ls180.v:4352$733_Y end - attribute \src "ls180.v:4379.36-4379.68" - cell $sub $sub$ls180.v:4379$744 + attribute \src "ls180.v:4382.36-4382.68" + cell $sub $sub$ls180.v:4382$744 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -276393,10 +278922,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4379$744_Y + connect \Y $sub$ls180.v:4382$744_Y end - attribute \src "ls180.v:4415.70-4415.110" - cell $sub $sub$ls180.v:4415$752 + attribute \src "ls180.v:4418.70-4418.110" + cell $sub $sub$ls180.v:4418$752 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -276404,10 +278933,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4415$752_Y + connect \Y $sub$ls180.v:4418$752_Y end - attribute \src "ls180.v:4416.70-4416.104" - cell $sub $sub$ls180.v:4416$754 + attribute \src "ls180.v:4419.70-4419.104" + cell $sub $sub$ls180.v:4419$754 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -276415,10 +278944,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider connect \B 1'1 - connect \Y $sub$ls180.v:4416$754_Y + connect \Y $sub$ls180.v:4419$754_Y end - attribute \src "ls180.v:4443.37-4443.66" - cell $sub $sub$ls180.v:4443$758 + attribute \src "ls180.v:4446.37-4446.66" + cell $sub $sub$ls180.v:4446$758 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -276426,10 +278955,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spimaster1_length connect \B 1'1 - connect \Y $sub$ls180.v:4443$758_Y + connect \Y $sub$ls180.v:4446$758_Y end - attribute \src "ls180.v:4473.67-4473.107" - cell $sub $sub$ls180.v:4473$760 + attribute \src "ls180.v:4476.67-4476.107" + cell $sub $sub$ls180.v:4476$760 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -276437,10 +278966,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4473$760_Y + connect \Y $sub$ls180.v:4476$760_Y end - attribute \src "ls180.v:4474.67-4474.101" - cell $sub $sub$ls180.v:4474$762 + attribute \src "ls180.v:4477.67-4477.101" + cell $sub $sub$ls180.v:4477$762 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -276448,10 +278977,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 connect \B 1'1 - connect \Y $sub$ls180.v:4474$762_Y + connect \Y $sub$ls180.v:4477$762_Y end - attribute \src "ls180.v:4502.35-4502.64" - cell $sub $sub$ls180.v:4502$766 + attribute \src "ls180.v:4505.35-4505.64" + cell $sub $sub$ls180.v:4505$766 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -276459,10 +278988,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spisdcard_length0 connect \B 1'1 - connect \Y $sub$ls180.v:4502$766_Y + connect \Y $sub$ls180.v:4505$766_Y end - attribute \src "ls180.v:4756.60-4756.90" - cell $sub $sub$ls180.v:4756$810 + attribute \src "ls180.v:4759.60-4759.90" + cell $sub $sub$ls180.v:4759$810 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276470,10 +278999,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4756$810_Y + connect \Y $sub$ls180.v:4759$810_Y end - attribute \src "ls180.v:4767.62-4767.104" - cell $sub $sub$ls180.v:4767$812 + attribute \src "ls180.v:4770.62-4770.104" + cell $sub $sub$ls180.v:4770$812 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -276481,10 +279010,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_sink_payload_length connect \B 1'1 - connect \Y $sub$ls180.v:4767$812_Y + connect \Y $sub$ls180.v:4770$812_Y end - attribute \src "ls180.v:4784.60-4784.90" - cell $sub $sub$ls180.v:4784$816 + attribute \src "ls180.v:4787.60-4787.90" + cell $sub $sub$ls180.v:4787$816 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276492,10 +279021,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4784$816_Y + connect \Y $sub$ls180.v:4787$816_Y end - attribute \src "ls180.v:5013.62-5013.93" - cell $sub $sub$ls180.v:5013$846 + attribute \src "ls180.v:5016.62-5016.93" + cell $sub $sub$ls180.v:5016$846 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276503,10 +279032,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:5013$846_Y + connect \Y $sub$ls180.v:5016$846_Y end - attribute \src "ls180.v:5018.62-5018.93" - cell $sub $sub$ls180.v:5018$847 + attribute \src "ls180.v:5021.62-5021.93" + cell $sub $sub$ls180.v:5021$847 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276514,21 +279043,21 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:5018$847_Y + connect \Y $sub$ls180.v:5021$847_Y end - attribute \src "ls180.v:5029.64-5029.122" - cell $sub $sub$ls180.v:5029$850 + attribute \src "ls180.v:5032.64-5032.122" + cell $sub $sub$ls180.v:5032$850 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 10 - connect \A $add$ls180.v:5029$849_Y + connect \A $add$ls180.v:5032$849_Y connect \B 1'1 - connect \Y $sub$ls180.v:5029$850_Y + connect \Y $sub$ls180.v:5032$850_Y end - attribute \src "ls180.v:5050.62-5050.93" - cell $sub $sub$ls180.v:5050$853 + attribute \src "ls180.v:5053.62-5053.93" + cell $sub $sub$ls180.v:5053$853 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276536,10 +279065,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:5050$853_Y + connect \Y $sub$ls180.v:5053$853_Y end - attribute \src "ls180.v:5512.37-5512.75" - cell $sub $sub$ls180.v:5512$1126 + attribute \src "ls180.v:5515.37-5515.75" + cell $sub $sub$ls180.v:5515$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276547,10 +279076,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5512$1126_Y + connect \Y $sub$ls180.v:5515$1126_Y end - attribute \src "ls180.v:5527.62-5527.100" - cell $sub $sub$ls180.v:5527$1129 + attribute \src "ls180.v:5530.62-5530.100" + cell $sub $sub$ls180.v:5530$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276558,10 +279087,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5527$1129_Y + connect \Y $sub$ls180.v:5530$1129_Y end - attribute \src "ls180.v:5538.39-5538.77" - cell $sub $sub$ls180.v:5538$1134 + attribute \src "ls180.v:5541.39-5541.77" + cell $sub $sub$ls180.v:5541$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276569,10 +279098,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5538$1134_Y + connect \Y $sub$ls180.v:5541$1134_Y end - attribute \src "ls180.v:5613.40-5613.76" - cell $sub $sub$ls180.v:5613$1138 + attribute \src "ls180.v:5616.40-5616.76" + cell $sub $sub$ls180.v:5616$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -276580,10 +279109,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5613$1138_Y + connect \Y $sub$ls180.v:5616$1138_Y end - attribute \src "ls180.v:5662.56-5662.104" - cell $sub $sub$ls180.v:5662$1152 + attribute \src "ls180.v:5665.56-5665.104" + cell $sub $sub$ls180.v:5665$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276591,10 +279120,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_length connect \B 1'1 - connect \Y $sub$ls180.v:5662$1152_Y + connect \Y $sub$ls180.v:5665$1152_Y end - attribute \src "ls180.v:5752.71-5752.105" - cell $sub $sub$ls180.v:5752$1158 + attribute \src "ls180.v:5755.71-5755.105" + cell $sub $sub$ls180.v:5755$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276602,10 +279131,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_length connect \B 1'1 - connect \Y $sub$ls180.v:5752$1158_Y + connect \Y $sub$ls180.v:5755$1158_Y end - attribute \src "ls180.v:5833.40-5833.76" - cell $sub $sub$ls180.v:5833$1169 + attribute \src "ls180.v:5836.40-5836.76" + cell $sub $sub$ls180.v:5836$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -276613,10 +279142,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5833$1169_Y + connect \Y $sub$ls180.v:5836$1169_Y end - attribute \src "ls180.v:7773.31-7773.60" - cell $sub $sub$ls180.v:7773$2607 + attribute \src "ls180.v:7776.31-7776.60" + cell $sub $sub$ls180.v:7776$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276624,10 +279153,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7773$2607_Y + connect \Y $sub$ls180.v:7776$2607_Y end - attribute \src "ls180.v:7810.31-7810.61" - cell $sub $sub$ls180.v:7810$2624 + attribute \src "ls180.v:7813.31-7813.61" + cell $sub $sub$ls180.v:7813$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -276635,10 +279164,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7810$2624_Y + connect \Y $sub$ls180.v:7813$2624_Y end - attribute \src "ls180.v:7816.34-7816.67" - cell $sub $sub$ls180.v:7816$2625 + attribute \src "ls180.v:7819.34-7819.67" + cell $sub $sub$ls180.v:7819$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276646,10 +279175,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7816$2625_Y + connect \Y $sub$ls180.v:7819$2625_Y end - attribute \src "ls180.v:7827.36-7827.69" - cell $sub $sub$ls180.v:7827$2628 + attribute \src "ls180.v:7830.36-7830.69" + cell $sub $sub$ls180.v:7830$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276657,10 +279186,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7827$2628_Y + connect \Y $sub$ls180.v:7830$2628_Y end - attribute \src "ls180.v:7891.59-7891.116" - cell $sub $sub$ls180.v:7891$2646 + attribute \src "ls180.v:7894.59-7894.116" + cell $sub $sub$ls180.v:7894$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -276668,10 +279197,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7891$2646_Y + connect \Y $sub$ls180.v:7894$2646_Y end - attribute \src "ls180.v:7910.46-7910.90" - cell $sub $sub$ls180.v:7910$2650 + attribute \src "ls180.v:7913.46-7913.90" + cell $sub $sub$ls180.v:7913$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276679,10 +279208,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7910$2650_Y + connect \Y $sub$ls180.v:7913$2650_Y end - attribute \src "ls180.v:7937.59-7937.116" - cell $sub $sub$ls180.v:7937$2662 + attribute \src "ls180.v:7940.59-7940.116" + cell $sub $sub$ls180.v:7940$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -276690,10 +279219,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7937$2662_Y + connect \Y $sub$ls180.v:7940$2662_Y end - attribute \src "ls180.v:7956.46-7956.90" - cell $sub $sub$ls180.v:7956$2666 + attribute \src "ls180.v:7959.46-7959.90" + cell $sub $sub$ls180.v:7959$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276701,10 +279230,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7956$2666_Y + connect \Y $sub$ls180.v:7959$2666_Y end - attribute \src "ls180.v:7983.59-7983.116" - cell $sub $sub$ls180.v:7983$2678 + attribute \src "ls180.v:7986.59-7986.116" + cell $sub $sub$ls180.v:7986$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -276712,10 +279241,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7983$2678_Y + connect \Y $sub$ls180.v:7986$2678_Y end - attribute \src "ls180.v:8002.46-8002.90" - cell $sub $sub$ls180.v:8002$2682 + attribute \src "ls180.v:8005.46-8005.90" + cell $sub $sub$ls180.v:8005$2682 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276723,10 +279252,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8002$2682_Y + connect \Y $sub$ls180.v:8005$2682_Y end - attribute \src "ls180.v:8029.59-8029.116" - cell $sub $sub$ls180.v:8029$2694 + attribute \src "ls180.v:8032.59-8032.116" + cell $sub $sub$ls180.v:8032$2694 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -276734,10 +279263,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:8029$2694_Y + connect \Y $sub$ls180.v:8032$2694_Y end - attribute \src "ls180.v:8048.46-8048.90" - cell $sub $sub$ls180.v:8048$2698 + attribute \src "ls180.v:8051.46-8051.90" + cell $sub $sub$ls180.v:8051$2698 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276745,10 +279274,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8048$2698_Y + connect \Y $sub$ls180.v:8051$2698_Y end - attribute \src "ls180.v:8059.25-8059.48" - cell $sub $sub$ls180.v:8059$2702 + attribute \src "ls180.v:8062.25-8062.48" + cell $sub $sub$ls180.v:8062$2702 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -276756,10 +279285,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:8059$2702_Y + connect \Y $sub$ls180.v:8062$2702_Y end - attribute \src "ls180.v:8066.25-8066.48" - cell $sub $sub$ls180.v:8066$2705 + attribute \src "ls180.v:8069.25-8069.48" + cell $sub $sub$ls180.v:8069$2705 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -276767,10 +279296,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:8066$2705_Y + connect \Y $sub$ls180.v:8069$2705_Y end - attribute \src "ls180.v:8198.33-8198.64" - cell $sub $sub$ls180.v:8198$2710 + attribute \src "ls180.v:8201.33-8201.64" + cell $sub $sub$ls180.v:8201$2710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276778,10 +279307,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8198$2710_Y + connect \Y $sub$ls180.v:8201$2710_Y end - attribute \src "ls180.v:8213.33-8213.64" - cell $sub $sub$ls180.v:8213$2713 + attribute \src "ls180.v:8216.33-8216.64" + cell $sub $sub$ls180.v:8216$2713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276789,10 +279318,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8213$2713_Y + connect \Y $sub$ls180.v:8216$2713_Y end - attribute \src "ls180.v:8340.33-8340.64" - cell $sub $sub$ls180.v:8340$2772 + attribute \src "ls180.v:8343.33-8343.64" + cell $sub $sub$ls180.v:8343$2772 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -276800,10 +279329,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8340$2772_Y + connect \Y $sub$ls180.v:8343$2772_Y end - attribute \src "ls180.v:8362.33-8362.64" - cell $sub $sub$ls180.v:8362$2783 + attribute \src "ls180.v:8365.33-8365.64" + cell $sub $sub$ls180.v:8365$2783 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -276811,10 +279340,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8362$2783_Y + connect \Y $sub$ls180.v:8365$2783_Y end - attribute \src "ls180.v:8397.34-8397.66" - cell $sub $sub$ls180.v:8397$2788 + attribute \src "ls180.v:8400.34-8400.66" + cell $sub $sub$ls180.v:8400$2788 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276822,10 +279351,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster34_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8397$2788_Y + connect \Y $sub$ls180.v:8400$2788_Y end - attribute \src "ls180.v:8432.32-8432.62" - cell $sub $sub$ls180.v:8432$2793 + attribute \src "ls180.v:8435.32-8435.62" + cell $sub $sub$ls180.v:8435$2793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -276833,10 +279362,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8432$2793_Y + connect \Y $sub$ls180.v:8435$2793_Y end - attribute \src "ls180.v:8456.30-8456.53" - cell $sub $sub$ls180.v:8456$2796 + attribute \src "ls180.v:8459.30-8459.53" + cell $sub $sub$ls180.v:8459$2796 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276844,10 +279373,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8456$2796_Y + connect \Y $sub$ls180.v:8459$2796_Y end - attribute \src "ls180.v:8470.30-8470.53" - cell $sub $sub$ls180.v:8470$2800 + attribute \src "ls180.v:8473.30-8473.53" + cell $sub $sub$ls180.v:8473$2800 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -276855,10 +279384,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8470$2800_Y + connect \Y $sub$ls180.v:8473$2800_Y end - attribute \src "ls180.v:8873.36-8873.70" - cell $sub $sub$ls180.v:8873$2861 + attribute \src "ls180.v:8876.36-8876.70" + cell $sub $sub$ls180.v:8876$2861 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -276866,10 +279395,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8873$2861_Y + connect \Y $sub$ls180.v:8876$2861_Y end - attribute \src "ls180.v:8971.36-8971.70" - cell $sub $sub$ls180.v:8971$2883 + attribute \src "ls180.v:8974.36-8974.70" + cell $sub $sub$ls180.v:8974$2883 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -276877,10 +279406,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8971$2883_Y + connect \Y $sub$ls180.v:8974$2883_Y end - attribute \src "ls180.v:9084.22-9084.42" - cell $sub $sub$ls180.v:9084$2890 + attribute \src "ls180.v:9087.22-9087.42" + cell $sub $sub$ls180.v:9087$2890 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -276888,10 +279417,10 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:9084$2890_Y + connect \Y $sub$ls180.v:9087$2890_Y end - attribute \src "ls180.v:5110.353-5110.425" - cell $xor $xor$ls180.v:5110$860 + attribute \src "ls180.v:5113.353-5113.425" + cell $xor $xor$ls180.v:5113$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276899,10 +279428,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:5110$860_Y + connect \Y $xor$ls180.v:5113$860_Y end - attribute \src "ls180.v:5110.200-5110.272" - cell $xor $xor$ls180.v:5110$861 + attribute \src "ls180.v:5113.200-5113.272" + cell $xor $xor$ls180.v:5113$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276910,21 +279439,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:5110$861_Y + connect \Y $xor$ls180.v:5113$861_Y end - attribute \src "ls180.v:5110.160-5110.273" - cell $xor $xor$ls180.v:5110$862 + attribute \src "ls180.v:5113.160-5113.273" + cell $xor $xor$ls180.v:5113$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:5110$861_Y - connect \Y $xor$ls180.v:5110$862_Y + connect \B $xor$ls180.v:5113$861_Y + connect \Y $xor$ls180.v:5113$862_Y end - attribute \src "ls180.v:5111.353-5111.425" - cell $xor $xor$ls180.v:5111$863 + attribute \src "ls180.v:5114.353-5114.425" + cell $xor $xor$ls180.v:5114$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276932,10 +279461,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:5111$863_Y + connect \Y $xor$ls180.v:5114$863_Y end - attribute \src "ls180.v:5111.200-5111.272" - cell $xor $xor$ls180.v:5111$864 + attribute \src "ls180.v:5114.200-5114.272" + cell $xor $xor$ls180.v:5114$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276943,21 +279472,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:5111$864_Y + connect \Y $xor$ls180.v:5114$864_Y end - attribute \src "ls180.v:5111.160-5111.273" - cell $xor $xor$ls180.v:5111$865 + attribute \src "ls180.v:5114.160-5114.273" + cell $xor $xor$ls180.v:5114$865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:5111$864_Y - connect \Y $xor$ls180.v:5111$865_Y + connect \B $xor$ls180.v:5114$864_Y + connect \Y $xor$ls180.v:5114$865_Y end - attribute \src "ls180.v:5112.353-5112.425" - cell $xor $xor$ls180.v:5112$866 + attribute \src "ls180.v:5115.353-5115.425" + cell $xor $xor$ls180.v:5115$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276965,10 +279494,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:5112$866_Y + connect \Y $xor$ls180.v:5115$866_Y end - attribute \src "ls180.v:5112.200-5112.272" - cell $xor $xor$ls180.v:5112$867 + attribute \src "ls180.v:5115.200-5115.272" + cell $xor $xor$ls180.v:5115$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276976,21 +279505,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:5112$867_Y + connect \Y $xor$ls180.v:5115$867_Y end - attribute \src "ls180.v:5112.160-5112.273" - cell $xor $xor$ls180.v:5112$868 + attribute \src "ls180.v:5115.160-5115.273" + cell $xor $xor$ls180.v:5115$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:5112$867_Y - connect \Y $xor$ls180.v:5112$868_Y + connect \B $xor$ls180.v:5115$867_Y + connect \Y $xor$ls180.v:5115$868_Y end - attribute \src "ls180.v:5113.353-5113.425" - cell $xor $xor$ls180.v:5113$869 + attribute \src "ls180.v:5116.353-5116.425" + cell $xor $xor$ls180.v:5116$869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -276998,10 +279527,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5113$869_Y + connect \Y $xor$ls180.v:5116$869_Y end - attribute \src "ls180.v:5113.200-5113.272" - cell $xor $xor$ls180.v:5113$870 + attribute \src "ls180.v:5116.200-5116.272" + cell $xor $xor$ls180.v:5116$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277009,21 +279538,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5113$870_Y + connect \Y $xor$ls180.v:5116$870_Y end - attribute \src "ls180.v:5113.160-5113.273" - cell $xor $xor$ls180.v:5113$871 + attribute \src "ls180.v:5116.160-5116.273" + cell $xor $xor$ls180.v:5116$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:5113$870_Y - connect \Y $xor$ls180.v:5113$871_Y + connect \B $xor$ls180.v:5116$870_Y + connect \Y $xor$ls180.v:5116$871_Y end - attribute \src "ls180.v:5114.353-5114.425" - cell $xor $xor$ls180.v:5114$872 + attribute \src "ls180.v:5117.353-5117.425" + cell $xor $xor$ls180.v:5117$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277031,10 +279560,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5114$872_Y + connect \Y $xor$ls180.v:5117$872_Y end - attribute \src "ls180.v:5114.200-5114.272" - cell $xor $xor$ls180.v:5114$873 + attribute \src "ls180.v:5117.200-5117.272" + cell $xor $xor$ls180.v:5117$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277042,21 +279571,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5114$873_Y + connect \Y $xor$ls180.v:5117$873_Y end - attribute \src "ls180.v:5114.160-5114.273" - cell $xor $xor$ls180.v:5114$874 + attribute \src "ls180.v:5117.160-5117.273" + cell $xor $xor$ls180.v:5117$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:5114$873_Y - connect \Y $xor$ls180.v:5114$874_Y + connect \B $xor$ls180.v:5117$873_Y + connect \Y $xor$ls180.v:5117$874_Y end - attribute \src "ls180.v:5115.353-5115.425" - cell $xor $xor$ls180.v:5115$875 + attribute \src "ls180.v:5118.353-5118.425" + cell $xor $xor$ls180.v:5118$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277064,10 +279593,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5115$875_Y + connect \Y $xor$ls180.v:5118$875_Y end - attribute \src "ls180.v:5115.200-5115.272" - cell $xor $xor$ls180.v:5115$876 + attribute \src "ls180.v:5118.200-5118.272" + cell $xor $xor$ls180.v:5118$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277075,21 +279604,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5115$876_Y + connect \Y $xor$ls180.v:5118$876_Y end - attribute \src "ls180.v:5115.160-5115.273" - cell $xor $xor$ls180.v:5115$877 + attribute \src "ls180.v:5118.160-5118.273" + cell $xor $xor$ls180.v:5118$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:5115$876_Y - connect \Y $xor$ls180.v:5115$877_Y + connect \B $xor$ls180.v:5118$876_Y + connect \Y $xor$ls180.v:5118$877_Y end - attribute \src "ls180.v:5116.353-5116.425" - cell $xor $xor$ls180.v:5116$878 + attribute \src "ls180.v:5119.353-5119.425" + cell $xor $xor$ls180.v:5119$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277097,10 +279626,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5116$878_Y + connect \Y $xor$ls180.v:5119$878_Y end - attribute \src "ls180.v:5116.200-5116.272" - cell $xor $xor$ls180.v:5116$879 + attribute \src "ls180.v:5119.200-5119.272" + cell $xor $xor$ls180.v:5119$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277108,21 +279637,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5116$879_Y + connect \Y $xor$ls180.v:5119$879_Y end - attribute \src "ls180.v:5116.160-5116.273" - cell $xor $xor$ls180.v:5116$880 + attribute \src "ls180.v:5119.160-5119.273" + cell $xor $xor$ls180.v:5119$880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:5116$879_Y - connect \Y $xor$ls180.v:5116$880_Y + connect \B $xor$ls180.v:5119$879_Y + connect \Y $xor$ls180.v:5119$880_Y end - attribute \src "ls180.v:5117.353-5117.425" - cell $xor $xor$ls180.v:5117$881 + attribute \src "ls180.v:5120.353-5120.425" + cell $xor $xor$ls180.v:5120$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277130,10 +279659,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5117$881_Y + connect \Y $xor$ls180.v:5120$881_Y end - attribute \src "ls180.v:5117.200-5117.272" - cell $xor $xor$ls180.v:5117$882 + attribute \src "ls180.v:5120.200-5120.272" + cell $xor $xor$ls180.v:5120$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277141,21 +279670,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5117$882_Y + connect \Y $xor$ls180.v:5120$882_Y end - attribute \src "ls180.v:5117.160-5117.273" - cell $xor $xor$ls180.v:5117$883 + attribute \src "ls180.v:5120.160-5120.273" + cell $xor $xor$ls180.v:5120$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:5117$882_Y - connect \Y $xor$ls180.v:5117$883_Y + connect \B $xor$ls180.v:5120$882_Y + connect \Y $xor$ls180.v:5120$883_Y end - attribute \src "ls180.v:5118.353-5118.425" - cell $xor $xor$ls180.v:5118$884 + attribute \src "ls180.v:5121.353-5121.425" + cell $xor $xor$ls180.v:5121$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277163,10 +279692,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5118$884_Y + connect \Y $xor$ls180.v:5121$884_Y end - attribute \src "ls180.v:5118.200-5118.272" - cell $xor $xor$ls180.v:5118$885 + attribute \src "ls180.v:5121.200-5121.272" + cell $xor $xor$ls180.v:5121$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277174,21 +279703,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5118$885_Y + connect \Y $xor$ls180.v:5121$885_Y end - attribute \src "ls180.v:5118.160-5118.273" - cell $xor $xor$ls180.v:5118$886 + attribute \src "ls180.v:5121.160-5121.273" + cell $xor $xor$ls180.v:5121$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:5118$885_Y - connect \Y $xor$ls180.v:5118$886_Y + connect \B $xor$ls180.v:5121$885_Y + connect \Y $xor$ls180.v:5121$886_Y end - attribute \src "ls180.v:5119.354-5119.426" - cell $xor $xor$ls180.v:5119$887 + attribute \src "ls180.v:5122.354-5122.426" + cell $xor $xor$ls180.v:5122$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277196,10 +279725,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5119$887_Y + connect \Y $xor$ls180.v:5122$887_Y end - attribute \src "ls180.v:5119.201-5119.273" - cell $xor $xor$ls180.v:5119$888 + attribute \src "ls180.v:5122.201-5122.273" + cell $xor $xor$ls180.v:5122$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277207,21 +279736,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5119$888_Y + connect \Y $xor$ls180.v:5122$888_Y end - attribute \src "ls180.v:5119.161-5119.274" - cell $xor $xor$ls180.v:5119$889 + attribute \src "ls180.v:5122.161-5122.274" + cell $xor $xor$ls180.v:5122$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:5119$888_Y - connect \Y $xor$ls180.v:5119$889_Y + connect \B $xor$ls180.v:5122$888_Y + connect \Y $xor$ls180.v:5122$889_Y end - attribute \src "ls180.v:5120.361-5120.434" - cell $xor $xor$ls180.v:5120$890 + attribute \src "ls180.v:5123.361-5123.434" + cell $xor $xor$ls180.v:5123$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277229,10 +279758,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5120$890_Y + connect \Y $xor$ls180.v:5123$890_Y end - attribute \src "ls180.v:5120.205-5120.278" - cell $xor $xor$ls180.v:5120$891 + attribute \src "ls180.v:5123.205-5123.278" + cell $xor $xor$ls180.v:5123$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277240,21 +279769,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5120$891_Y + connect \Y $xor$ls180.v:5123$891_Y end - attribute \src "ls180.v:5120.164-5120.279" - cell $xor $xor$ls180.v:5120$892 + attribute \src "ls180.v:5123.164-5123.279" + cell $xor $xor$ls180.v:5123$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:5120$891_Y - connect \Y $xor$ls180.v:5120$892_Y + connect \B $xor$ls180.v:5123$891_Y + connect \Y $xor$ls180.v:5123$892_Y end - attribute \src "ls180.v:5121.361-5121.434" - cell $xor $xor$ls180.v:5121$893 + attribute \src "ls180.v:5124.361-5124.434" + cell $xor $xor$ls180.v:5124$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277262,10 +279791,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5121$893_Y + connect \Y $xor$ls180.v:5124$893_Y end - attribute \src "ls180.v:5121.205-5121.278" - cell $xor $xor$ls180.v:5121$894 + attribute \src "ls180.v:5124.205-5124.278" + cell $xor $xor$ls180.v:5124$894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277273,21 +279802,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5121$894_Y + connect \Y $xor$ls180.v:5124$894_Y end - attribute \src "ls180.v:5121.164-5121.279" - cell $xor $xor$ls180.v:5121$895 + attribute \src "ls180.v:5124.164-5124.279" + cell $xor $xor$ls180.v:5124$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:5121$894_Y - connect \Y $xor$ls180.v:5121$895_Y + connect \B $xor$ls180.v:5124$894_Y + connect \Y $xor$ls180.v:5124$895_Y end - attribute \src "ls180.v:5122.361-5122.434" - cell $xor $xor$ls180.v:5122$896 + attribute \src "ls180.v:5125.361-5125.434" + cell $xor $xor$ls180.v:5125$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277295,10 +279824,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5122$896_Y + connect \Y $xor$ls180.v:5125$896_Y end - attribute \src "ls180.v:5122.205-5122.278" - cell $xor $xor$ls180.v:5122$897 + attribute \src "ls180.v:5125.205-5125.278" + cell $xor $xor$ls180.v:5125$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277306,21 +279835,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5122$897_Y + connect \Y $xor$ls180.v:5125$897_Y end - attribute \src "ls180.v:5122.164-5122.279" - cell $xor $xor$ls180.v:5122$898 + attribute \src "ls180.v:5125.164-5125.279" + cell $xor $xor$ls180.v:5125$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:5122$897_Y - connect \Y $xor$ls180.v:5122$898_Y + connect \B $xor$ls180.v:5125$897_Y + connect \Y $xor$ls180.v:5125$898_Y end - attribute \src "ls180.v:5123.361-5123.434" - cell $xor $xor$ls180.v:5123$899 + attribute \src "ls180.v:5126.361-5126.434" + cell $xor $xor$ls180.v:5126$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277328,10 +279857,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5123$899_Y + connect \Y $xor$ls180.v:5126$899_Y end - attribute \src "ls180.v:5123.205-5123.278" - cell $xor $xor$ls180.v:5123$900 + attribute \src "ls180.v:5126.205-5126.278" + cell $xor $xor$ls180.v:5126$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277339,21 +279868,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5123$900_Y + connect \Y $xor$ls180.v:5126$900_Y end - attribute \src "ls180.v:5123.164-5123.279" - cell $xor $xor$ls180.v:5123$901 + attribute \src "ls180.v:5126.164-5126.279" + cell $xor $xor$ls180.v:5126$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:5123$900_Y - connect \Y $xor$ls180.v:5123$901_Y + connect \B $xor$ls180.v:5126$900_Y + connect \Y $xor$ls180.v:5126$901_Y end - attribute \src "ls180.v:5124.361-5124.434" - cell $xor $xor$ls180.v:5124$902 + attribute \src "ls180.v:5127.361-5127.434" + cell $xor $xor$ls180.v:5127$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277361,10 +279890,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5124$902_Y + connect \Y $xor$ls180.v:5127$902_Y end - attribute \src "ls180.v:5124.205-5124.278" - cell $xor $xor$ls180.v:5124$903 + attribute \src "ls180.v:5127.205-5127.278" + cell $xor $xor$ls180.v:5127$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277372,21 +279901,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5124$903_Y + connect \Y $xor$ls180.v:5127$903_Y end - attribute \src "ls180.v:5124.164-5124.279" - cell $xor $xor$ls180.v:5124$904 + attribute \src "ls180.v:5127.164-5127.279" + cell $xor $xor$ls180.v:5127$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:5124$903_Y - connect \Y $xor$ls180.v:5124$904_Y + connect \B $xor$ls180.v:5127$903_Y + connect \Y $xor$ls180.v:5127$904_Y end - attribute \src "ls180.v:5125.361-5125.434" - cell $xor $xor$ls180.v:5125$905 + attribute \src "ls180.v:5128.361-5128.434" + cell $xor $xor$ls180.v:5128$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277394,10 +279923,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5125$905_Y + connect \Y $xor$ls180.v:5128$905_Y end - attribute \src "ls180.v:5125.205-5125.278" - cell $xor $xor$ls180.v:5125$906 + attribute \src "ls180.v:5128.205-5128.278" + cell $xor $xor$ls180.v:5128$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277405,21 +279934,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5125$906_Y + connect \Y $xor$ls180.v:5128$906_Y end - attribute \src "ls180.v:5125.164-5125.279" - cell $xor $xor$ls180.v:5125$907 + attribute \src "ls180.v:5128.164-5128.279" + cell $xor $xor$ls180.v:5128$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:5125$906_Y - connect \Y $xor$ls180.v:5125$907_Y + connect \B $xor$ls180.v:5128$906_Y + connect \Y $xor$ls180.v:5128$907_Y end - attribute \src "ls180.v:5126.361-5126.434" - cell $xor $xor$ls180.v:5126$908 + attribute \src "ls180.v:5129.361-5129.434" + cell $xor $xor$ls180.v:5129$908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277427,10 +279956,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5126$908_Y + connect \Y $xor$ls180.v:5129$908_Y end - attribute \src "ls180.v:5126.205-5126.278" - cell $xor $xor$ls180.v:5126$909 + attribute \src "ls180.v:5129.205-5129.278" + cell $xor $xor$ls180.v:5129$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277438,21 +279967,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5126$909_Y + connect \Y $xor$ls180.v:5129$909_Y end - attribute \src "ls180.v:5126.164-5126.279" - cell $xor $xor$ls180.v:5126$910 + attribute \src "ls180.v:5129.164-5129.279" + cell $xor $xor$ls180.v:5129$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:5126$909_Y - connect \Y $xor$ls180.v:5126$910_Y + connect \B $xor$ls180.v:5129$909_Y + connect \Y $xor$ls180.v:5129$910_Y end - attribute \src "ls180.v:5127.361-5127.434" - cell $xor $xor$ls180.v:5127$911 + attribute \src "ls180.v:5130.361-5130.434" + cell $xor $xor$ls180.v:5130$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277460,10 +279989,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5127$911_Y + connect \Y $xor$ls180.v:5130$911_Y end - attribute \src "ls180.v:5127.205-5127.278" - cell $xor $xor$ls180.v:5127$912 + attribute \src "ls180.v:5130.205-5130.278" + cell $xor $xor$ls180.v:5130$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277471,21 +280000,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5127$912_Y + connect \Y $xor$ls180.v:5130$912_Y end - attribute \src "ls180.v:5127.164-5127.279" - cell $xor $xor$ls180.v:5127$913 + attribute \src "ls180.v:5130.164-5130.279" + cell $xor $xor$ls180.v:5130$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:5127$912_Y - connect \Y $xor$ls180.v:5127$913_Y + connect \B $xor$ls180.v:5130$912_Y + connect \Y $xor$ls180.v:5130$913_Y end - attribute \src "ls180.v:5128.361-5128.434" - cell $xor $xor$ls180.v:5128$914 + attribute \src "ls180.v:5131.361-5131.434" + cell $xor $xor$ls180.v:5131$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277493,10 +280022,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5128$914_Y + connect \Y $xor$ls180.v:5131$914_Y end - attribute \src "ls180.v:5128.205-5128.278" - cell $xor $xor$ls180.v:5128$915 + attribute \src "ls180.v:5131.205-5131.278" + cell $xor $xor$ls180.v:5131$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277504,21 +280033,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5128$915_Y + connect \Y $xor$ls180.v:5131$915_Y end - attribute \src "ls180.v:5128.164-5128.279" - cell $xor $xor$ls180.v:5128$916 + attribute \src "ls180.v:5131.164-5131.279" + cell $xor $xor$ls180.v:5131$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:5128$915_Y - connect \Y $xor$ls180.v:5128$916_Y + connect \B $xor$ls180.v:5131$915_Y + connect \Y $xor$ls180.v:5131$916_Y end - attribute \src "ls180.v:5129.361-5129.434" - cell $xor $xor$ls180.v:5129$917 + attribute \src "ls180.v:5132.361-5132.434" + cell $xor $xor$ls180.v:5132$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277526,10 +280055,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5129$917_Y + connect \Y $xor$ls180.v:5132$917_Y end - attribute \src "ls180.v:5129.205-5129.278" - cell $xor $xor$ls180.v:5129$918 + attribute \src "ls180.v:5132.205-5132.278" + cell $xor $xor$ls180.v:5132$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277537,21 +280066,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5129$918_Y + connect \Y $xor$ls180.v:5132$918_Y end - attribute \src "ls180.v:5129.164-5129.279" - cell $xor $xor$ls180.v:5129$919 + attribute \src "ls180.v:5132.164-5132.279" + cell $xor $xor$ls180.v:5132$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:5129$918_Y - connect \Y $xor$ls180.v:5129$919_Y + connect \B $xor$ls180.v:5132$918_Y + connect \Y $xor$ls180.v:5132$919_Y end - attribute \src "ls180.v:5130.361-5130.434" - cell $xor $xor$ls180.v:5130$920 + attribute \src "ls180.v:5133.361-5133.434" + cell $xor $xor$ls180.v:5133$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277559,10 +280088,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5130$920_Y + connect \Y $xor$ls180.v:5133$920_Y end - attribute \src "ls180.v:5130.205-5130.278" - cell $xor $xor$ls180.v:5130$921 + attribute \src "ls180.v:5133.205-5133.278" + cell $xor $xor$ls180.v:5133$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277570,21 +280099,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5130$921_Y + connect \Y $xor$ls180.v:5133$921_Y end - attribute \src "ls180.v:5130.164-5130.279" - cell $xor $xor$ls180.v:5130$922 + attribute \src "ls180.v:5133.164-5133.279" + cell $xor $xor$ls180.v:5133$922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:5130$921_Y - connect \Y $xor$ls180.v:5130$922_Y + connect \B $xor$ls180.v:5133$921_Y + connect \Y $xor$ls180.v:5133$922_Y end - attribute \src "ls180.v:5131.361-5131.434" - cell $xor $xor$ls180.v:5131$923 + attribute \src "ls180.v:5134.361-5134.434" + cell $xor $xor$ls180.v:5134$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277592,10 +280121,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5131$923_Y + connect \Y $xor$ls180.v:5134$923_Y end - attribute \src "ls180.v:5131.205-5131.278" - cell $xor $xor$ls180.v:5131$924 + attribute \src "ls180.v:5134.205-5134.278" + cell $xor $xor$ls180.v:5134$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277603,21 +280132,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5131$924_Y + connect \Y $xor$ls180.v:5134$924_Y end - attribute \src "ls180.v:5131.164-5131.279" - cell $xor $xor$ls180.v:5131$925 + attribute \src "ls180.v:5134.164-5134.279" + cell $xor $xor$ls180.v:5134$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:5131$924_Y - connect \Y $xor$ls180.v:5131$925_Y + connect \B $xor$ls180.v:5134$924_Y + connect \Y $xor$ls180.v:5134$925_Y end - attribute \src "ls180.v:5132.361-5132.434" - cell $xor $xor$ls180.v:5132$926 + attribute \src "ls180.v:5135.361-5135.434" + cell $xor $xor$ls180.v:5135$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277625,10 +280154,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5132$926_Y + connect \Y $xor$ls180.v:5135$926_Y end - attribute \src "ls180.v:5132.205-5132.278" - cell $xor $xor$ls180.v:5132$927 + attribute \src "ls180.v:5135.205-5135.278" + cell $xor $xor$ls180.v:5135$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277636,21 +280165,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5132$927_Y + connect \Y $xor$ls180.v:5135$927_Y end - attribute \src "ls180.v:5132.164-5132.279" - cell $xor $xor$ls180.v:5132$928 + attribute \src "ls180.v:5135.164-5135.279" + cell $xor $xor$ls180.v:5135$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:5132$927_Y - connect \Y $xor$ls180.v:5132$928_Y + connect \B $xor$ls180.v:5135$927_Y + connect \Y $xor$ls180.v:5135$928_Y end - attribute \src "ls180.v:5133.361-5133.434" - cell $xor $xor$ls180.v:5133$929 + attribute \src "ls180.v:5136.361-5136.434" + cell $xor $xor$ls180.v:5136$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277658,10 +280187,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5133$929_Y + connect \Y $xor$ls180.v:5136$929_Y end - attribute \src "ls180.v:5133.205-5133.278" - cell $xor $xor$ls180.v:5133$930 + attribute \src "ls180.v:5136.205-5136.278" + cell $xor $xor$ls180.v:5136$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277669,21 +280198,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5133$930_Y + connect \Y $xor$ls180.v:5136$930_Y end - attribute \src "ls180.v:5133.164-5133.279" - cell $xor $xor$ls180.v:5133$931 + attribute \src "ls180.v:5136.164-5136.279" + cell $xor $xor$ls180.v:5136$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:5133$930_Y - connect \Y $xor$ls180.v:5133$931_Y + connect \B $xor$ls180.v:5136$930_Y + connect \Y $xor$ls180.v:5136$931_Y end - attribute \src "ls180.v:5134.361-5134.434" - cell $xor $xor$ls180.v:5134$932 + attribute \src "ls180.v:5137.361-5137.434" + cell $xor $xor$ls180.v:5137$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277691,10 +280220,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5134$932_Y + connect \Y $xor$ls180.v:5137$932_Y end - attribute \src "ls180.v:5134.205-5134.278" - cell $xor $xor$ls180.v:5134$933 + attribute \src "ls180.v:5137.205-5137.278" + cell $xor $xor$ls180.v:5137$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277702,21 +280231,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5134$933_Y + connect \Y $xor$ls180.v:5137$933_Y end - attribute \src "ls180.v:5134.164-5134.279" - cell $xor $xor$ls180.v:5134$934 + attribute \src "ls180.v:5137.164-5137.279" + cell $xor $xor$ls180.v:5137$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:5134$933_Y - connect \Y $xor$ls180.v:5134$934_Y + connect \B $xor$ls180.v:5137$933_Y + connect \Y $xor$ls180.v:5137$934_Y end - attribute \src "ls180.v:5135.361-5135.434" - cell $xor $xor$ls180.v:5135$935 + attribute \src "ls180.v:5138.361-5138.434" + cell $xor $xor$ls180.v:5138$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277724,10 +280253,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5135$935_Y + connect \Y $xor$ls180.v:5138$935_Y end - attribute \src "ls180.v:5135.205-5135.278" - cell $xor $xor$ls180.v:5135$936 + attribute \src "ls180.v:5138.205-5138.278" + cell $xor $xor$ls180.v:5138$936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277735,21 +280264,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5135$936_Y + connect \Y $xor$ls180.v:5138$936_Y end - attribute \src "ls180.v:5135.164-5135.279" - cell $xor $xor$ls180.v:5135$937 + attribute \src "ls180.v:5138.164-5138.279" + cell $xor $xor$ls180.v:5138$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:5135$936_Y - connect \Y $xor$ls180.v:5135$937_Y + connect \B $xor$ls180.v:5138$936_Y + connect \Y $xor$ls180.v:5138$937_Y end - attribute \src "ls180.v:5136.361-5136.434" - cell $xor $xor$ls180.v:5136$938 + attribute \src "ls180.v:5139.361-5139.434" + cell $xor $xor$ls180.v:5139$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277757,10 +280286,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5136$938_Y + connect \Y $xor$ls180.v:5139$938_Y end - attribute \src "ls180.v:5136.205-5136.278" - cell $xor $xor$ls180.v:5136$939 + attribute \src "ls180.v:5139.205-5139.278" + cell $xor $xor$ls180.v:5139$939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277768,21 +280297,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5136$939_Y + connect \Y $xor$ls180.v:5139$939_Y end - attribute \src "ls180.v:5136.164-5136.279" - cell $xor $xor$ls180.v:5136$940 + attribute \src "ls180.v:5139.164-5139.279" + cell $xor $xor$ls180.v:5139$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:5136$939_Y - connect \Y $xor$ls180.v:5136$940_Y + connect \B $xor$ls180.v:5139$939_Y + connect \Y $xor$ls180.v:5139$940_Y end - attribute \src "ls180.v:5137.361-5137.434" - cell $xor $xor$ls180.v:5137$941 + attribute \src "ls180.v:5140.361-5140.434" + cell $xor $xor$ls180.v:5140$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277790,10 +280319,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5137$941_Y + connect \Y $xor$ls180.v:5140$941_Y end - attribute \src "ls180.v:5137.205-5137.278" - cell $xor $xor$ls180.v:5137$942 + attribute \src "ls180.v:5140.205-5140.278" + cell $xor $xor$ls180.v:5140$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277801,21 +280330,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5137$942_Y + connect \Y $xor$ls180.v:5140$942_Y end - attribute \src "ls180.v:5137.164-5137.279" - cell $xor $xor$ls180.v:5137$943 + attribute \src "ls180.v:5140.164-5140.279" + cell $xor $xor$ls180.v:5140$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:5137$942_Y - connect \Y $xor$ls180.v:5137$943_Y + connect \B $xor$ls180.v:5140$942_Y + connect \Y $xor$ls180.v:5140$943_Y end - attribute \src "ls180.v:5138.361-5138.434" - cell $xor $xor$ls180.v:5138$944 + attribute \src "ls180.v:5141.361-5141.434" + cell $xor $xor$ls180.v:5141$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277823,10 +280352,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5138$944_Y + connect \Y $xor$ls180.v:5141$944_Y end - attribute \src "ls180.v:5138.205-5138.278" - cell $xor $xor$ls180.v:5138$945 + attribute \src "ls180.v:5141.205-5141.278" + cell $xor $xor$ls180.v:5141$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277834,21 +280363,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5138$945_Y + connect \Y $xor$ls180.v:5141$945_Y end - attribute \src "ls180.v:5138.164-5138.279" - cell $xor $xor$ls180.v:5138$946 + attribute \src "ls180.v:5141.164-5141.279" + cell $xor $xor$ls180.v:5141$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:5138$945_Y - connect \Y $xor$ls180.v:5138$946_Y + connect \B $xor$ls180.v:5141$945_Y + connect \Y $xor$ls180.v:5141$946_Y end - attribute \src "ls180.v:5139.361-5139.434" - cell $xor $xor$ls180.v:5139$947 + attribute \src "ls180.v:5142.361-5142.434" + cell $xor $xor$ls180.v:5142$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277856,10 +280385,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5139$947_Y + connect \Y $xor$ls180.v:5142$947_Y end - attribute \src "ls180.v:5139.205-5139.278" - cell $xor $xor$ls180.v:5139$948 + attribute \src "ls180.v:5142.205-5142.278" + cell $xor $xor$ls180.v:5142$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277867,21 +280396,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5139$948_Y + connect \Y $xor$ls180.v:5142$948_Y end - attribute \src "ls180.v:5139.164-5139.279" - cell $xor $xor$ls180.v:5139$949 + attribute \src "ls180.v:5142.164-5142.279" + cell $xor $xor$ls180.v:5142$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:5139$948_Y - connect \Y $xor$ls180.v:5139$949_Y + connect \B $xor$ls180.v:5142$948_Y + connect \Y $xor$ls180.v:5142$949_Y end - attribute \src "ls180.v:5140.360-5140.432" - cell $xor $xor$ls180.v:5140$950 + attribute \src "ls180.v:5143.360-5143.432" + cell $xor $xor$ls180.v:5143$950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277889,10 +280418,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5140$950_Y + connect \Y $xor$ls180.v:5143$950_Y end - attribute \src "ls180.v:5140.205-5140.277" - cell $xor $xor$ls180.v:5140$951 + attribute \src "ls180.v:5143.205-5143.277" + cell $xor $xor$ls180.v:5143$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277900,21 +280429,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5140$951_Y + connect \Y $xor$ls180.v:5143$951_Y end - attribute \src "ls180.v:5140.164-5140.278" - cell $xor $xor$ls180.v:5140$952 + attribute \src "ls180.v:5143.164-5143.278" + cell $xor $xor$ls180.v:5143$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:5140$951_Y - connect \Y $xor$ls180.v:5140$952_Y + connect \B $xor$ls180.v:5143$951_Y + connect \Y $xor$ls180.v:5143$952_Y end - attribute \src "ls180.v:5141.360-5141.432" - cell $xor $xor$ls180.v:5141$953 + attribute \src "ls180.v:5144.360-5144.432" + cell $xor $xor$ls180.v:5144$953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277922,10 +280451,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5141$953_Y + connect \Y $xor$ls180.v:5144$953_Y end - attribute \src "ls180.v:5141.205-5141.277" - cell $xor $xor$ls180.v:5141$954 + attribute \src "ls180.v:5144.205-5144.277" + cell $xor $xor$ls180.v:5144$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277933,21 +280462,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5141$954_Y + connect \Y $xor$ls180.v:5144$954_Y end - attribute \src "ls180.v:5141.164-5141.278" - cell $xor $xor$ls180.v:5141$955 + attribute \src "ls180.v:5144.164-5144.278" + cell $xor $xor$ls180.v:5144$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:5141$954_Y - connect \Y $xor$ls180.v:5141$955_Y + connect \B $xor$ls180.v:5144$954_Y + connect \Y $xor$ls180.v:5144$955_Y end - attribute \src "ls180.v:5142.360-5142.432" - cell $xor $xor$ls180.v:5142$956 + attribute \src "ls180.v:5145.360-5145.432" + cell $xor $xor$ls180.v:5145$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277955,10 +280484,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5142$956_Y + connect \Y $xor$ls180.v:5145$956_Y end - attribute \src "ls180.v:5142.205-5142.277" - cell $xor $xor$ls180.v:5142$957 + attribute \src "ls180.v:5145.205-5145.277" + cell $xor $xor$ls180.v:5145$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277966,21 +280495,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5142$957_Y + connect \Y $xor$ls180.v:5145$957_Y end - attribute \src "ls180.v:5142.164-5142.278" - cell $xor $xor$ls180.v:5142$958 + attribute \src "ls180.v:5145.164-5145.278" + cell $xor $xor$ls180.v:5145$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:5142$957_Y - connect \Y $xor$ls180.v:5142$958_Y + connect \B $xor$ls180.v:5145$957_Y + connect \Y $xor$ls180.v:5145$958_Y end - attribute \src "ls180.v:5143.360-5143.432" - cell $xor $xor$ls180.v:5143$959 + attribute \src "ls180.v:5146.360-5146.432" + cell $xor $xor$ls180.v:5146$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277988,10 +280517,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5143$959_Y + connect \Y $xor$ls180.v:5146$959_Y end - attribute \src "ls180.v:5143.205-5143.277" - cell $xor $xor$ls180.v:5143$960 + attribute \src "ls180.v:5146.205-5146.277" + cell $xor $xor$ls180.v:5146$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277999,21 +280528,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5143$960_Y + connect \Y $xor$ls180.v:5146$960_Y end - attribute \src "ls180.v:5143.164-5143.278" - cell $xor $xor$ls180.v:5143$961 + attribute \src "ls180.v:5146.164-5146.278" + cell $xor $xor$ls180.v:5146$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:5143$960_Y - connect \Y $xor$ls180.v:5143$961_Y + connect \B $xor$ls180.v:5146$960_Y + connect \Y $xor$ls180.v:5146$961_Y end - attribute \src "ls180.v:5144.360-5144.432" - cell $xor $xor$ls180.v:5144$962 + attribute \src "ls180.v:5147.360-5147.432" + cell $xor $xor$ls180.v:5147$962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278021,10 +280550,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5144$962_Y + connect \Y $xor$ls180.v:5147$962_Y end - attribute \src "ls180.v:5144.205-5144.277" - cell $xor $xor$ls180.v:5144$963 + attribute \src "ls180.v:5147.205-5147.277" + cell $xor $xor$ls180.v:5147$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278032,21 +280561,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5144$963_Y + connect \Y $xor$ls180.v:5147$963_Y end - attribute \src "ls180.v:5144.164-5144.278" - cell $xor $xor$ls180.v:5144$964 + attribute \src "ls180.v:5147.164-5147.278" + cell $xor $xor$ls180.v:5147$964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:5144$963_Y - connect \Y $xor$ls180.v:5144$964_Y + connect \B $xor$ls180.v:5147$963_Y + connect \Y $xor$ls180.v:5147$964_Y end - attribute \src "ls180.v:5145.360-5145.432" - cell $xor $xor$ls180.v:5145$965 + attribute \src "ls180.v:5148.360-5148.432" + cell $xor $xor$ls180.v:5148$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278054,10 +280583,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5145$965_Y + connect \Y $xor$ls180.v:5148$965_Y end - attribute \src "ls180.v:5145.205-5145.277" - cell $xor $xor$ls180.v:5145$966 + attribute \src "ls180.v:5148.205-5148.277" + cell $xor $xor$ls180.v:5148$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278065,21 +280594,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5145$966_Y + connect \Y $xor$ls180.v:5148$966_Y end - attribute \src "ls180.v:5145.164-5145.278" - cell $xor $xor$ls180.v:5145$967 + attribute \src "ls180.v:5148.164-5148.278" + cell $xor $xor$ls180.v:5148$967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:5145$966_Y - connect \Y $xor$ls180.v:5145$967_Y + connect \B $xor$ls180.v:5148$966_Y + connect \Y $xor$ls180.v:5148$967_Y end - attribute \src "ls180.v:5146.360-5146.432" - cell $xor $xor$ls180.v:5146$968 + attribute \src "ls180.v:5149.360-5149.432" + cell $xor $xor$ls180.v:5149$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278087,10 +280616,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5146$968_Y + connect \Y $xor$ls180.v:5149$968_Y end - attribute \src "ls180.v:5146.205-5146.277" - cell $xor $xor$ls180.v:5146$969 + attribute \src "ls180.v:5149.205-5149.277" + cell $xor $xor$ls180.v:5149$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278098,21 +280627,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5146$969_Y + connect \Y $xor$ls180.v:5149$969_Y end - attribute \src "ls180.v:5146.164-5146.278" - cell $xor $xor$ls180.v:5146$970 + attribute \src "ls180.v:5149.164-5149.278" + cell $xor $xor$ls180.v:5149$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:5146$969_Y - connect \Y $xor$ls180.v:5146$970_Y + connect \B $xor$ls180.v:5149$969_Y + connect \Y $xor$ls180.v:5149$970_Y end - attribute \src "ls180.v:5147.360-5147.432" - cell $xor $xor$ls180.v:5147$971 + attribute \src "ls180.v:5150.360-5150.432" + cell $xor $xor$ls180.v:5150$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278120,10 +280649,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5147$971_Y + connect \Y $xor$ls180.v:5150$971_Y end - attribute \src "ls180.v:5147.205-5147.277" - cell $xor $xor$ls180.v:5147$972 + attribute \src "ls180.v:5150.205-5150.277" + cell $xor $xor$ls180.v:5150$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278131,21 +280660,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5147$972_Y + connect \Y $xor$ls180.v:5150$972_Y end - attribute \src "ls180.v:5147.164-5147.278" - cell $xor $xor$ls180.v:5147$973 + attribute \src "ls180.v:5150.164-5150.278" + cell $xor $xor$ls180.v:5150$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:5147$972_Y - connect \Y $xor$ls180.v:5147$973_Y + connect \B $xor$ls180.v:5150$972_Y + connect \Y $xor$ls180.v:5150$973_Y end - attribute \src "ls180.v:5148.360-5148.432" - cell $xor $xor$ls180.v:5148$974 + attribute \src "ls180.v:5151.360-5151.432" + cell $xor $xor$ls180.v:5151$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278153,10 +280682,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5148$974_Y + connect \Y $xor$ls180.v:5151$974_Y end - attribute \src "ls180.v:5148.205-5148.277" - cell $xor $xor$ls180.v:5148$975 + attribute \src "ls180.v:5151.205-5151.277" + cell $xor $xor$ls180.v:5151$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278164,21 +280693,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5148$975_Y + connect \Y $xor$ls180.v:5151$975_Y end - attribute \src "ls180.v:5148.164-5148.278" - cell $xor $xor$ls180.v:5148$976 + attribute \src "ls180.v:5151.164-5151.278" + cell $xor $xor$ls180.v:5151$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:5148$975_Y - connect \Y $xor$ls180.v:5148$976_Y + connect \B $xor$ls180.v:5151$975_Y + connect \Y $xor$ls180.v:5151$976_Y end - attribute \src "ls180.v:5149.360-5149.432" - cell $xor $xor$ls180.v:5149$977 + attribute \src "ls180.v:5152.360-5152.432" + cell $xor $xor$ls180.v:5152$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278186,10 +280715,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5149$977_Y + connect \Y $xor$ls180.v:5152$977_Y end - attribute \src "ls180.v:5149.205-5149.277" - cell $xor $xor$ls180.v:5149$978 + attribute \src "ls180.v:5152.205-5152.277" + cell $xor $xor$ls180.v:5152$978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278197,21 +280726,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5149$978_Y + connect \Y $xor$ls180.v:5152$978_Y end - attribute \src "ls180.v:5149.164-5149.278" - cell $xor $xor$ls180.v:5149$979 + attribute \src "ls180.v:5152.164-5152.278" + cell $xor $xor$ls180.v:5152$979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:5149$978_Y - connect \Y $xor$ls180.v:5149$979_Y + connect \B $xor$ls180.v:5152$978_Y + connect \Y $xor$ls180.v:5152$979_Y end - attribute \src "ls180.v:5170.899-5170.983" - cell $xor $xor$ls180.v:5170$993 + attribute \src "ls180.v:5173.899-5173.983" + cell $xor $xor$ls180.v:5173$993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278219,10 +280748,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5170$993_Y + connect \Y $xor$ls180.v:5173$993_Y end - attribute \src "ls180.v:5170.634-5170.718" - cell $xor $xor$ls180.v:5170$994 + attribute \src "ls180.v:5173.634-5173.718" + cell $xor $xor$ls180.v:5173$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278230,21 +280759,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5170$994_Y + connect \Y $xor$ls180.v:5173$994_Y end - attribute \src "ls180.v:5170.588-5170.719" - cell $xor $xor$ls180.v:5170$995 + attribute \src "ls180.v:5173.588-5173.719" + cell $xor $xor$ls180.v:5173$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5170$994_Y - connect \Y $xor$ls180.v:5170$995_Y + connect \B $xor$ls180.v:5173$994_Y + connect \Y $xor$ls180.v:5173$995_Y end - attribute \src "ls180.v:5170.234-5170.318" - cell $xor $xor$ls180.v:5170$996 + attribute \src "ls180.v:5173.234-5173.318" + cell $xor $xor$ls180.v:5173$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278252,32 +280781,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5170$996_Y + connect \Y $xor$ls180.v:5173$996_Y end - attribute \src "ls180.v:5170.187-5170.319" - cell $xor $xor$ls180.v:5170$997 + attribute \src "ls180.v:5173.187-5173.319" + cell $xor $xor$ls180.v:5173$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5170$996_Y - connect \Y $xor$ls180.v:5170$997_Y + connect \B $xor$ls180.v:5173$996_Y + connect \Y $xor$ls180.v:5173$997_Y end - attribute \src "ls180.v:5171.588-5171.719" - cell $xor $xor$ls180.v:5171$1000 + attribute \src "ls180.v:5174.588-5174.719" + cell $xor $xor$ls180.v:5174$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5171$999_Y - connect \Y $xor$ls180.v:5171$1000_Y + connect \B $xor$ls180.v:5174$999_Y + connect \Y $xor$ls180.v:5174$1000_Y end - attribute \src "ls180.v:5171.234-5171.318" - cell $xor $xor$ls180.v:5171$1001 + attribute \src "ls180.v:5174.234-5174.318" + cell $xor $xor$ls180.v:5174$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278285,21 +280814,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5171$1001_Y + connect \Y $xor$ls180.v:5174$1001_Y end - attribute \src "ls180.v:5171.187-5171.319" - cell $xor $xor$ls180.v:5171$1002 + attribute \src "ls180.v:5174.187-5174.319" + cell $xor $xor$ls180.v:5174$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5171$1001_Y - connect \Y $xor$ls180.v:5171$1002_Y + connect \B $xor$ls180.v:5174$1001_Y + connect \Y $xor$ls180.v:5174$1002_Y end - attribute \src "ls180.v:5171.899-5171.983" - cell $xor $xor$ls180.v:5171$998 + attribute \src "ls180.v:5174.899-5174.983" + cell $xor $xor$ls180.v:5174$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278307,10 +280836,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5171$998_Y + connect \Y $xor$ls180.v:5174$998_Y end - attribute \src "ls180.v:5171.634-5171.718" - cell $xor $xor$ls180.v:5171$999 + attribute \src "ls180.v:5174.634-5174.718" + cell $xor $xor$ls180.v:5174$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278318,10 +280847,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5171$999_Y + connect \Y $xor$ls180.v:5174$999_Y end - attribute \src "ls180.v:5180.899-5180.983" - cell $xor $xor$ls180.v:5180$1004 + attribute \src "ls180.v:5183.899-5183.983" + cell $xor $xor$ls180.v:5183$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278329,10 +280858,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5180$1004_Y + connect \Y $xor$ls180.v:5183$1004_Y end - attribute \src "ls180.v:5180.634-5180.718" - cell $xor $xor$ls180.v:5180$1005 + attribute \src "ls180.v:5183.634-5183.718" + cell $xor $xor$ls180.v:5183$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278340,21 +280869,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5180$1005_Y + connect \Y $xor$ls180.v:5183$1005_Y end - attribute \src "ls180.v:5180.588-5180.719" - cell $xor $xor$ls180.v:5180$1006 + attribute \src "ls180.v:5183.588-5183.719" + cell $xor $xor$ls180.v:5183$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5180$1005_Y - connect \Y $xor$ls180.v:5180$1006_Y + connect \B $xor$ls180.v:5183$1005_Y + connect \Y $xor$ls180.v:5183$1006_Y end - attribute \src "ls180.v:5180.234-5180.318" - cell $xor $xor$ls180.v:5180$1007 + attribute \src "ls180.v:5183.234-5183.318" + cell $xor $xor$ls180.v:5183$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278362,21 +280891,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5180$1007_Y + connect \Y $xor$ls180.v:5183$1007_Y end - attribute \src "ls180.v:5180.187-5180.319" - cell $xor $xor$ls180.v:5180$1008 + attribute \src "ls180.v:5183.187-5183.319" + cell $xor $xor$ls180.v:5183$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5180$1007_Y - connect \Y $xor$ls180.v:5180$1008_Y + connect \B $xor$ls180.v:5183$1007_Y + connect \Y $xor$ls180.v:5183$1008_Y end - attribute \src "ls180.v:5181.899-5181.983" - cell $xor $xor$ls180.v:5181$1009 + attribute \src "ls180.v:5184.899-5184.983" + cell $xor $xor$ls180.v:5184$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278384,10 +280913,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5181$1009_Y + connect \Y $xor$ls180.v:5184$1009_Y end - attribute \src "ls180.v:5181.634-5181.718" - cell $xor $xor$ls180.v:5181$1010 + attribute \src "ls180.v:5184.634-5184.718" + cell $xor $xor$ls180.v:5184$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278395,21 +280924,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5181$1010_Y + connect \Y $xor$ls180.v:5184$1010_Y end - attribute \src "ls180.v:5181.588-5181.719" - cell $xor $xor$ls180.v:5181$1011 + attribute \src "ls180.v:5184.588-5184.719" + cell $xor $xor$ls180.v:5184$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5181$1010_Y - connect \Y $xor$ls180.v:5181$1011_Y + connect \B $xor$ls180.v:5184$1010_Y + connect \Y $xor$ls180.v:5184$1011_Y end - attribute \src "ls180.v:5181.234-5181.318" - cell $xor $xor$ls180.v:5181$1012 + attribute \src "ls180.v:5184.234-5184.318" + cell $xor $xor$ls180.v:5184$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278417,21 +280946,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5181$1012_Y + connect \Y $xor$ls180.v:5184$1012_Y end - attribute \src "ls180.v:5181.187-5181.319" - cell $xor $xor$ls180.v:5181$1013 + attribute \src "ls180.v:5184.187-5184.319" + cell $xor $xor$ls180.v:5184$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5181$1012_Y - connect \Y $xor$ls180.v:5181$1013_Y + connect \B $xor$ls180.v:5184$1012_Y + connect \Y $xor$ls180.v:5184$1013_Y end - attribute \src "ls180.v:5190.899-5190.983" - cell $xor $xor$ls180.v:5190$1015 + attribute \src "ls180.v:5193.899-5193.983" + cell $xor $xor$ls180.v:5193$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278439,10 +280968,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5190$1015_Y + connect \Y $xor$ls180.v:5193$1015_Y end - attribute \src "ls180.v:5190.634-5190.718" - cell $xor $xor$ls180.v:5190$1016 + attribute \src "ls180.v:5193.634-5193.718" + cell $xor $xor$ls180.v:5193$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278450,21 +280979,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5190$1016_Y + connect \Y $xor$ls180.v:5193$1016_Y end - attribute \src "ls180.v:5190.588-5190.719" - cell $xor $xor$ls180.v:5190$1017 + attribute \src "ls180.v:5193.588-5193.719" + cell $xor $xor$ls180.v:5193$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5190$1016_Y - connect \Y $xor$ls180.v:5190$1017_Y + connect \B $xor$ls180.v:5193$1016_Y + connect \Y $xor$ls180.v:5193$1017_Y end - attribute \src "ls180.v:5190.234-5190.318" - cell $xor $xor$ls180.v:5190$1018 + attribute \src "ls180.v:5193.234-5193.318" + cell $xor $xor$ls180.v:5193$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278472,21 +281001,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5190$1018_Y + connect \Y $xor$ls180.v:5193$1018_Y end - attribute \src "ls180.v:5190.187-5190.319" - cell $xor $xor$ls180.v:5190$1019 + attribute \src "ls180.v:5193.187-5193.319" + cell $xor $xor$ls180.v:5193$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5190$1018_Y - connect \Y $xor$ls180.v:5190$1019_Y + connect \B $xor$ls180.v:5193$1018_Y + connect \Y $xor$ls180.v:5193$1019_Y end - attribute \src "ls180.v:5191.899-5191.983" - cell $xor $xor$ls180.v:5191$1020 + attribute \src "ls180.v:5194.899-5194.983" + cell $xor $xor$ls180.v:5194$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278494,10 +281023,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5191$1020_Y + connect \Y $xor$ls180.v:5194$1020_Y end - attribute \src "ls180.v:5191.634-5191.718" - cell $xor $xor$ls180.v:5191$1021 + attribute \src "ls180.v:5194.634-5194.718" + cell $xor $xor$ls180.v:5194$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278505,21 +281034,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5191$1021_Y + connect \Y $xor$ls180.v:5194$1021_Y end - attribute \src "ls180.v:5191.588-5191.719" - cell $xor $xor$ls180.v:5191$1022 + attribute \src "ls180.v:5194.588-5194.719" + cell $xor $xor$ls180.v:5194$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5191$1021_Y - connect \Y $xor$ls180.v:5191$1022_Y + connect \B $xor$ls180.v:5194$1021_Y + connect \Y $xor$ls180.v:5194$1022_Y end - attribute \src "ls180.v:5191.234-5191.318" - cell $xor $xor$ls180.v:5191$1023 + attribute \src "ls180.v:5194.234-5194.318" + cell $xor $xor$ls180.v:5194$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278527,21 +281056,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5191$1023_Y + connect \Y $xor$ls180.v:5194$1023_Y end - attribute \src "ls180.v:5191.187-5191.319" - cell $xor $xor$ls180.v:5191$1024 + attribute \src "ls180.v:5194.187-5194.319" + cell $xor $xor$ls180.v:5194$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5191$1023_Y - connect \Y $xor$ls180.v:5191$1024_Y + connect \B $xor$ls180.v:5194$1023_Y + connect \Y $xor$ls180.v:5194$1024_Y end - attribute \src "ls180.v:5200.899-5200.983" - cell $xor $xor$ls180.v:5200$1026 + attribute \src "ls180.v:5203.899-5203.983" + cell $xor $xor$ls180.v:5203$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278549,10 +281078,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5200$1026_Y + connect \Y $xor$ls180.v:5203$1026_Y end - attribute \src "ls180.v:5200.634-5200.718" - cell $xor $xor$ls180.v:5200$1027 + attribute \src "ls180.v:5203.634-5203.718" + cell $xor $xor$ls180.v:5203$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278560,21 +281089,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5200$1027_Y + connect \Y $xor$ls180.v:5203$1027_Y end - attribute \src "ls180.v:5200.588-5200.719" - cell $xor $xor$ls180.v:5200$1028 + attribute \src "ls180.v:5203.588-5203.719" + cell $xor $xor$ls180.v:5203$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5200$1027_Y - connect \Y $xor$ls180.v:5200$1028_Y + connect \B $xor$ls180.v:5203$1027_Y + connect \Y $xor$ls180.v:5203$1028_Y end - attribute \src "ls180.v:5200.234-5200.318" - cell $xor $xor$ls180.v:5200$1029 + attribute \src "ls180.v:5203.234-5203.318" + cell $xor $xor$ls180.v:5203$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278582,21 +281111,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5200$1029_Y + connect \Y $xor$ls180.v:5203$1029_Y end - attribute \src "ls180.v:5200.187-5200.319" - cell $xor $xor$ls180.v:5200$1030 + attribute \src "ls180.v:5203.187-5203.319" + cell $xor $xor$ls180.v:5203$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5200$1029_Y - connect \Y $xor$ls180.v:5200$1030_Y + connect \B $xor$ls180.v:5203$1029_Y + connect \Y $xor$ls180.v:5203$1030_Y end - attribute \src "ls180.v:5201.899-5201.983" - cell $xor $xor$ls180.v:5201$1031 + attribute \src "ls180.v:5204.899-5204.983" + cell $xor $xor$ls180.v:5204$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278604,10 +281133,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5201$1031_Y + connect \Y $xor$ls180.v:5204$1031_Y end - attribute \src "ls180.v:5201.634-5201.718" - cell $xor $xor$ls180.v:5201$1032 + attribute \src "ls180.v:5204.634-5204.718" + cell $xor $xor$ls180.v:5204$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278615,21 +281144,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5201$1032_Y + connect \Y $xor$ls180.v:5204$1032_Y end - attribute \src "ls180.v:5201.588-5201.719" - cell $xor $xor$ls180.v:5201$1033 + attribute \src "ls180.v:5204.588-5204.719" + cell $xor $xor$ls180.v:5204$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5201$1032_Y - connect \Y $xor$ls180.v:5201$1033_Y + connect \B $xor$ls180.v:5204$1032_Y + connect \Y $xor$ls180.v:5204$1033_Y end - attribute \src "ls180.v:5201.234-5201.318" - cell $xor $xor$ls180.v:5201$1034 + attribute \src "ls180.v:5204.234-5204.318" + cell $xor $xor$ls180.v:5204$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278637,21 +281166,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5201$1034_Y + connect \Y $xor$ls180.v:5204$1034_Y end - attribute \src "ls180.v:5201.187-5201.319" - cell $xor $xor$ls180.v:5201$1035 + attribute \src "ls180.v:5204.187-5204.319" + cell $xor $xor$ls180.v:5204$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5201$1034_Y - connect \Y $xor$ls180.v:5201$1035_Y + connect \B $xor$ls180.v:5204$1034_Y + connect \Y $xor$ls180.v:5204$1035_Y end - attribute \src "ls180.v:5352.879-5352.961" - cell $xor $xor$ls180.v:5352$1068 + attribute \src "ls180.v:5355.879-5355.961" + cell $xor $xor$ls180.v:5355$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278659,10 +281188,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5352$1068_Y + connect \Y $xor$ls180.v:5355$1068_Y end - attribute \src "ls180.v:5352.620-5352.702" - cell $xor $xor$ls180.v:5352$1069 + attribute \src "ls180.v:5355.620-5355.702" + cell $xor $xor$ls180.v:5355$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278670,21 +281199,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5352$1069_Y + connect \Y $xor$ls180.v:5355$1069_Y end - attribute \src "ls180.v:5352.575-5352.703" - cell $xor $xor$ls180.v:5352$1070 + attribute \src "ls180.v:5355.575-5355.703" + cell $xor $xor$ls180.v:5355$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5352$1069_Y - connect \Y $xor$ls180.v:5352$1070_Y + connect \B $xor$ls180.v:5355$1069_Y + connect \Y $xor$ls180.v:5355$1070_Y end - attribute \src "ls180.v:5352.229-5352.311" - cell $xor $xor$ls180.v:5352$1071 + attribute \src "ls180.v:5355.229-5355.311" + cell $xor $xor$ls180.v:5355$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278692,21 +281221,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5352$1071_Y + connect \Y $xor$ls180.v:5355$1071_Y end - attribute \src "ls180.v:5352.183-5352.312" - cell $xor $xor$ls180.v:5352$1072 + attribute \src "ls180.v:5355.183-5355.312" + cell $xor $xor$ls180.v:5355$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5352$1071_Y - connect \Y $xor$ls180.v:5352$1072_Y + connect \B $xor$ls180.v:5355$1071_Y + connect \Y $xor$ls180.v:5355$1072_Y end - attribute \src "ls180.v:5353.879-5353.961" - cell $xor $xor$ls180.v:5353$1073 + attribute \src "ls180.v:5356.879-5356.961" + cell $xor $xor$ls180.v:5356$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278714,10 +281243,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5353$1073_Y + connect \Y $xor$ls180.v:5356$1073_Y end - attribute \src "ls180.v:5353.620-5353.702" - cell $xor $xor$ls180.v:5353$1074 + attribute \src "ls180.v:5356.620-5356.702" + cell $xor $xor$ls180.v:5356$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278725,21 +281254,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5353$1074_Y + connect \Y $xor$ls180.v:5356$1074_Y end - attribute \src "ls180.v:5353.575-5353.703" - cell $xor $xor$ls180.v:5353$1075 + attribute \src "ls180.v:5356.575-5356.703" + cell $xor $xor$ls180.v:5356$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5353$1074_Y - connect \Y $xor$ls180.v:5353$1075_Y + connect \B $xor$ls180.v:5356$1074_Y + connect \Y $xor$ls180.v:5356$1075_Y end - attribute \src "ls180.v:5353.229-5353.311" - cell $xor $xor$ls180.v:5353$1076 + attribute \src "ls180.v:5356.229-5356.311" + cell $xor $xor$ls180.v:5356$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278747,21 +281276,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5353$1076_Y + connect \Y $xor$ls180.v:5356$1076_Y end - attribute \src "ls180.v:5353.183-5353.312" - cell $xor $xor$ls180.v:5353$1077 + attribute \src "ls180.v:5356.183-5356.312" + cell $xor $xor$ls180.v:5356$1077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5353$1076_Y - connect \Y $xor$ls180.v:5353$1077_Y + connect \B $xor$ls180.v:5356$1076_Y + connect \Y $xor$ls180.v:5356$1077_Y end - attribute \src "ls180.v:5362.879-5362.961" - cell $xor $xor$ls180.v:5362$1079 + attribute \src "ls180.v:5365.879-5365.961" + cell $xor $xor$ls180.v:5365$1079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278769,10 +281298,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5362$1079_Y + connect \Y $xor$ls180.v:5365$1079_Y end - attribute \src "ls180.v:5362.620-5362.702" - cell $xor $xor$ls180.v:5362$1080 + attribute \src "ls180.v:5365.620-5365.702" + cell $xor $xor$ls180.v:5365$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278780,21 +281309,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5362$1080_Y + connect \Y $xor$ls180.v:5365$1080_Y end - attribute \src "ls180.v:5362.575-5362.703" - cell $xor $xor$ls180.v:5362$1081 + attribute \src "ls180.v:5365.575-5365.703" + cell $xor $xor$ls180.v:5365$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5362$1080_Y - connect \Y $xor$ls180.v:5362$1081_Y + connect \B $xor$ls180.v:5365$1080_Y + connect \Y $xor$ls180.v:5365$1081_Y end - attribute \src "ls180.v:5362.229-5362.311" - cell $xor $xor$ls180.v:5362$1082 + attribute \src "ls180.v:5365.229-5365.311" + cell $xor $xor$ls180.v:5365$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278802,21 +281331,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5362$1082_Y + connect \Y $xor$ls180.v:5365$1082_Y end - attribute \src "ls180.v:5362.183-5362.312" - cell $xor $xor$ls180.v:5362$1083 + attribute \src "ls180.v:5365.183-5365.312" + cell $xor $xor$ls180.v:5365$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5362$1082_Y - connect \Y $xor$ls180.v:5362$1083_Y + connect \B $xor$ls180.v:5365$1082_Y + connect \Y $xor$ls180.v:5365$1083_Y end - attribute \src "ls180.v:5363.879-5363.961" - cell $xor $xor$ls180.v:5363$1084 + attribute \src "ls180.v:5366.879-5366.961" + cell $xor $xor$ls180.v:5366$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278824,10 +281353,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5363$1084_Y + connect \Y $xor$ls180.v:5366$1084_Y end - attribute \src "ls180.v:5363.620-5363.702" - cell $xor $xor$ls180.v:5363$1085 + attribute \src "ls180.v:5366.620-5366.702" + cell $xor $xor$ls180.v:5366$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278835,21 +281364,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5363$1085_Y + connect \Y $xor$ls180.v:5366$1085_Y end - attribute \src "ls180.v:5363.575-5363.703" - cell $xor $xor$ls180.v:5363$1086 + attribute \src "ls180.v:5366.575-5366.703" + cell $xor $xor$ls180.v:5366$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5363$1085_Y - connect \Y $xor$ls180.v:5363$1086_Y + connect \B $xor$ls180.v:5366$1085_Y + connect \Y $xor$ls180.v:5366$1086_Y end - attribute \src "ls180.v:5363.229-5363.311" - cell $xor $xor$ls180.v:5363$1087 + attribute \src "ls180.v:5366.229-5366.311" + cell $xor $xor$ls180.v:5366$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278857,21 +281386,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5363$1087_Y + connect \Y $xor$ls180.v:5366$1087_Y end - attribute \src "ls180.v:5363.183-5363.312" - cell $xor $xor$ls180.v:5363$1088 + attribute \src "ls180.v:5366.183-5366.312" + cell $xor $xor$ls180.v:5366$1088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5363$1087_Y - connect \Y $xor$ls180.v:5363$1088_Y + connect \B $xor$ls180.v:5366$1087_Y + connect \Y $xor$ls180.v:5366$1088_Y end - attribute \src "ls180.v:5372.879-5372.961" - cell $xor $xor$ls180.v:5372$1090 + attribute \src "ls180.v:5375.879-5375.961" + cell $xor $xor$ls180.v:5375$1090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278879,10 +281408,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5372$1090_Y + connect \Y $xor$ls180.v:5375$1090_Y end - attribute \src "ls180.v:5372.620-5372.702" - cell $xor $xor$ls180.v:5372$1091 + attribute \src "ls180.v:5375.620-5375.702" + cell $xor $xor$ls180.v:5375$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278890,21 +281419,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5372$1091_Y + connect \Y $xor$ls180.v:5375$1091_Y end - attribute \src "ls180.v:5372.575-5372.703" - cell $xor $xor$ls180.v:5372$1092 + attribute \src "ls180.v:5375.575-5375.703" + cell $xor $xor$ls180.v:5375$1092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5372$1091_Y - connect \Y $xor$ls180.v:5372$1092_Y + connect \B $xor$ls180.v:5375$1091_Y + connect \Y $xor$ls180.v:5375$1092_Y end - attribute \src "ls180.v:5372.229-5372.311" - cell $xor $xor$ls180.v:5372$1093 + attribute \src "ls180.v:5375.229-5375.311" + cell $xor $xor$ls180.v:5375$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278912,21 +281441,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5372$1093_Y + connect \Y $xor$ls180.v:5375$1093_Y end - attribute \src "ls180.v:5372.183-5372.312" - cell $xor $xor$ls180.v:5372$1094 + attribute \src "ls180.v:5375.183-5375.312" + cell $xor $xor$ls180.v:5375$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5372$1093_Y - connect \Y $xor$ls180.v:5372$1094_Y + connect \B $xor$ls180.v:5375$1093_Y + connect \Y $xor$ls180.v:5375$1094_Y end - attribute \src "ls180.v:5373.879-5373.961" - cell $xor $xor$ls180.v:5373$1095 + attribute \src "ls180.v:5376.879-5376.961" + cell $xor $xor$ls180.v:5376$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278934,10 +281463,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5373$1095_Y + connect \Y $xor$ls180.v:5376$1095_Y end - attribute \src "ls180.v:5373.620-5373.702" - cell $xor $xor$ls180.v:5373$1096 + attribute \src "ls180.v:5376.620-5376.702" + cell $xor $xor$ls180.v:5376$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278945,21 +281474,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5373$1096_Y + connect \Y $xor$ls180.v:5376$1096_Y end - attribute \src "ls180.v:5373.575-5373.703" - cell $xor $xor$ls180.v:5373$1097 + attribute \src "ls180.v:5376.575-5376.703" + cell $xor $xor$ls180.v:5376$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5373$1096_Y - connect \Y $xor$ls180.v:5373$1097_Y + connect \B $xor$ls180.v:5376$1096_Y + connect \Y $xor$ls180.v:5376$1097_Y end - attribute \src "ls180.v:5373.229-5373.311" - cell $xor $xor$ls180.v:5373$1098 + attribute \src "ls180.v:5376.229-5376.311" + cell $xor $xor$ls180.v:5376$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278967,21 +281496,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5373$1098_Y + connect \Y $xor$ls180.v:5376$1098_Y end - attribute \src "ls180.v:5373.183-5373.312" - cell $xor $xor$ls180.v:5373$1099 + attribute \src "ls180.v:5376.183-5376.312" + cell $xor $xor$ls180.v:5376$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5373$1098_Y - connect \Y $xor$ls180.v:5373$1099_Y + connect \B $xor$ls180.v:5376$1098_Y + connect \Y $xor$ls180.v:5376$1099_Y end - attribute \src "ls180.v:5382.879-5382.961" - cell $xor $xor$ls180.v:5382$1101 + attribute \src "ls180.v:5385.879-5385.961" + cell $xor $xor$ls180.v:5385$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278989,10 +281518,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5382$1101_Y + connect \Y $xor$ls180.v:5385$1101_Y end - attribute \src "ls180.v:5382.620-5382.702" - cell $xor $xor$ls180.v:5382$1102 + attribute \src "ls180.v:5385.620-5385.702" + cell $xor $xor$ls180.v:5385$1102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279000,21 +281529,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5382$1102_Y + connect \Y $xor$ls180.v:5385$1102_Y end - attribute \src "ls180.v:5382.575-5382.703" - cell $xor $xor$ls180.v:5382$1103 + attribute \src "ls180.v:5385.575-5385.703" + cell $xor $xor$ls180.v:5385$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5382$1102_Y - connect \Y $xor$ls180.v:5382$1103_Y + connect \B $xor$ls180.v:5385$1102_Y + connect \Y $xor$ls180.v:5385$1103_Y end - attribute \src "ls180.v:5382.229-5382.311" - cell $xor $xor$ls180.v:5382$1104 + attribute \src "ls180.v:5385.229-5385.311" + cell $xor $xor$ls180.v:5385$1104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279022,21 +281551,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5382$1104_Y + connect \Y $xor$ls180.v:5385$1104_Y end - attribute \src "ls180.v:5382.183-5382.312" - cell $xor $xor$ls180.v:5382$1105 + attribute \src "ls180.v:5385.183-5385.312" + cell $xor $xor$ls180.v:5385$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5382$1104_Y - connect \Y $xor$ls180.v:5382$1105_Y + connect \B $xor$ls180.v:5385$1104_Y + connect \Y $xor$ls180.v:5385$1105_Y end - attribute \src "ls180.v:5383.879-5383.961" - cell $xor $xor$ls180.v:5383$1106 + attribute \src "ls180.v:5386.879-5386.961" + cell $xor $xor$ls180.v:5386$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279044,10 +281573,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5383$1106_Y + connect \Y $xor$ls180.v:5386$1106_Y end - attribute \src "ls180.v:5383.620-5383.702" - cell $xor $xor$ls180.v:5383$1107 + attribute \src "ls180.v:5386.620-5386.702" + cell $xor $xor$ls180.v:5386$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279055,21 +281584,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5383$1107_Y + connect \Y $xor$ls180.v:5386$1107_Y end - attribute \src "ls180.v:5383.575-5383.703" - cell $xor $xor$ls180.v:5383$1108 + attribute \src "ls180.v:5386.575-5386.703" + cell $xor $xor$ls180.v:5386$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5383$1107_Y - connect \Y $xor$ls180.v:5383$1108_Y + connect \B $xor$ls180.v:5386$1107_Y + connect \Y $xor$ls180.v:5386$1108_Y end - attribute \src "ls180.v:5383.229-5383.311" - cell $xor $xor$ls180.v:5383$1109 + attribute \src "ls180.v:5386.229-5386.311" + cell $xor $xor$ls180.v:5386$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279077,21 +281606,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5383$1109_Y + connect \Y $xor$ls180.v:5386$1109_Y end - attribute \src "ls180.v:5383.183-5383.312" - cell $xor $xor$ls180.v:5383$1110 + attribute \src "ls180.v:5386.183-5386.312" + cell $xor $xor$ls180.v:5386$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5383$1109_Y - connect \Y $xor$ls180.v:5383$1110_Y + connect \B $xor$ls180.v:5386$1109_Y + connect \Y $xor$ls180.v:5386$1110_Y end attribute \module_not_derived 1 - attribute \src "ls180.v:10606.13-11016.2" + attribute \src "ls180.v:10609.13-11015.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi @@ -279287,7 +281816,7 @@ module \ls180 connect \pwm_0__pad__o \pwm_1 [0] connect \pwm_1__core__o \pwm [1] connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10685$3077_Y + connect \rst $or$ls180.v:10709$3077_Y connect \sd0_clk__core__o \sdcard_clk connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk connect \sd0_cmd__core__i \sdcard_cmd_i @@ -279296,30 +281825,30 @@ module \ls180 connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data0__core__i \sdcard_cmd_i - connect \sd0_data0__core__o \sdcard_cmd_o - connect \sd0_data0__core__oe \sdcard_cmd_oe - connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data1__core__i \sdcard_cmd_i - connect \sd0_data1__core__o \sdcard_cmd_o - connect \sd0_data1__core__oe \sdcard_cmd_oe - connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data2__core__i \sdcard_cmd_i - connect \sd0_data2__core__o \sdcard_cmd_o - connect \sd0_data2__core__oe \sdcard_cmd_oe - connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data3__core__i \sdcard_cmd_i - connect \sd0_data3__core__o \sdcard_cmd_o - connect \sd0_data3__core__oe \sdcard_cmd_oe - connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data0__core__i \sdcard_data_i [0] + connect \sd0_data0__core__o \sdcard_data_o [0] + connect \sd0_data0__core__oe \sdcard_data_oe + connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [0] + connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [0] + connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data1__core__i \sdcard_data_i [1] + connect \sd0_data1__core__o \sdcard_data_o [1] + connect \sd0_data1__core__oe \sdcard_data_oe + connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [1] + connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [1] + connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data2__core__i \sdcard_data_i [2] + connect \sd0_data2__core__o \sdcard_data_o [2] + connect \sd0_data2__core__oe \sdcard_data_oe + connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [2] + connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [2] + connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe + connect \sd0_data3__core__i \sdcard_data_i [3] + connect \sd0_data3__core__o \sdcard_data_o [3] + connect \sd0_data3__core__oe \sdcard_data_oe + connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [3] + connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [3] + connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe connect \sdr_a_0__core__o \sdram_a [0] connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] connect \sdr_a_10__core__o \sdram_a [10] @@ -279360,12 +281889,8 @@ module \ls180 connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n connect \sdr_dm_0__core__o \sdram_dm [0] connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] - connect \sdr_dm_1__core__i \sdram_dq_i [1] - connect \sdr_dm_1__core__o \sdram_dq_o [1] - connect \sdr_dm_1__core__oe \sdram_dq_oe - connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] - connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] - connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dm_1__core__o \sdram_dm [1] + connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [1] connect \sdr_dq_0__core__i \sdram_dq_i [0] connect \sdr_dq_0__core__o \sdram_dq_o [0] connect \sdr_dq_0__core__oe \sdram_dq_oe @@ -279504,27 +282029,27 @@ module \ls180 connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4093 + process $proc$ls180.v:0$4091 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4094 + process $proc$ls180.v:0$4092 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4095 + process $proc$ls180.v:0$4093 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4096 + process $proc$ls180.v:0$4094 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4097 + process $proc$ls180.v:0$4095 sync always sync init end @@ -279536,14 +282061,6 @@ module \ls180 sync init update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] end - attribute \src "ls180.v:1009.5-1009.40" - process $proc$ls180.v:1009$3485 - assign { } { } - assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] - sync init - end attribute \src "ls180.v:101.5-101.50" process $proc$ls180.v:101$3145 assign { } { } @@ -279552,21 +282069,21 @@ module \ls180 sync init update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] end - attribute \src "ls180.v:1010.5-1010.39" - process $proc$ls180.v:1010$3486 + attribute \src "ls180.v:1012.5-1012.40" + process $proc$ls180.v:1012$3483 assign { } { } - assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always - update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init end - attribute \src "ls180.v:1018.5-1018.38" - process $proc$ls180.v:1018$3487 + attribute \src "ls180.v:1013.5-1013.39" + process $proc$ls180.v:1013$3484 assign { } { } - assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init - update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end attribute \src "ls180.v:102.5-102.50" process $proc$ls180.v:102$3146 @@ -279576,48 +282093,56 @@ module \ls180 sync init update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] end - attribute \src "ls180.v:1025.11-1025.42" - process $proc$ls180.v:1025$3488 + attribute \src "ls180.v:1021.5-1021.38" + process $proc$ls180.v:1021$3485 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:1028.11-1028.42" + process $proc$ls180.v:1028$3486 assign { } { } assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end - attribute \src "ls180.v:1026.5-1026.37" - process $proc$ls180.v:1026$3489 + attribute \src "ls180.v:1029.5-1029.37" + process $proc$ls180.v:1029$3487 assign { } { } assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1027.11-1027.43" - process $proc$ls180.v:1027$3490 + attribute \src "ls180.v:1030.11-1030.43" + process $proc$ls180.v:1030$3488 assign { } { } assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end - attribute \src "ls180.v:1028.11-1028.43" - process $proc$ls180.v:1028$3491 + attribute \src "ls180.v:1031.11-1031.43" + process $proc$ls180.v:1031$3489 assign { } { } assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end - attribute \src "ls180.v:1029.11-1029.46" - process $proc$ls180.v:1029$3492 + attribute \src "ls180.v:1032.11-1032.46" + process $proc$ls180.v:1032$3490 assign { } { } assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:10350.1-10368.4" - process $proc$ls180.v:10350$2891 + attribute \src "ls180.v:10353.1-10371.4" + process $proc$ls180.v:10353$2891 assign { } { } assign { } { } assign { } { } @@ -279643,132 +282168,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr[5:0] \main_libresocsim_adr - attribute \src "ls180.v:10351.2-10352.65" + attribute \src "ls180.v:10354.2-10355.65" switch \main_libresocsim_we [0] - attribute \src "ls180.v:10351.6-10351.28" + attribute \src "ls180.v:10354.6-10354.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10353.2-10354.67" + attribute \src "ls180.v:10356.2-10357.67" switch \main_libresocsim_we [1] - attribute \src "ls180.v:10353.6-10353.28" + attribute \src "ls180.v:10356.6-10356.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10355.2-10356.69" + attribute \src "ls180.v:10358.2-10359.69" switch \main_libresocsim_we [2] - attribute \src "ls180.v:10355.6-10355.28" + attribute \src "ls180.v:10358.6-10358.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10357.2-10358.69" + attribute \src "ls180.v:10360.2-10361.69" switch \main_libresocsim_we [3] - attribute \src "ls180.v:10357.6-10357.28" + attribute \src "ls180.v:10360.6-10360.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 64'0000000000000000000000000000000011111111000000000000000000000000 case end - attribute \src "ls180.v:10359.2-10360.69" + attribute \src "ls180.v:10362.2-10363.69" switch \main_libresocsim_we [4] - attribute \src "ls180.v:10359.6-10359.28" + attribute \src "ls180.v:10362.6-10362.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 64'0000000000000000000000001111111100000000000000000000000000000000 case end - attribute \src "ls180.v:10361.2-10362.69" + attribute \src "ls180.v:10364.2-10365.69" switch \main_libresocsim_we [5] - attribute \src "ls180.v:10361.6-10361.28" + attribute \src "ls180.v:10364.6-10364.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 64'0000000000000000111111110000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10363.2-10364.69" + attribute \src "ls180.v:10366.2-10367.69" switch \main_libresocsim_we [6] - attribute \src "ls180.v:10363.6-10363.28" + attribute \src "ls180.v:10366.6-10366.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 64'0000000011111111000000000000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10365.2-10366.69" + attribute \src "ls180.v:10368.2-10369.69" switch \main_libresocsim_we [7] - attribute \src "ls180.v:10365.6-10365.28" + attribute \src "ls180.v:10368.6-10368.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr $0\memadr[5:0] - update $memwr$\mem$ls180.v:10352$1_ADDR $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 - update $memwr$\mem$ls180.v:10352$1_DATA $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 - update $memwr$\mem$ls180.v:10352$1_EN $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 - update $memwr$\mem$ls180.v:10354$2_ADDR $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 - update $memwr$\mem$ls180.v:10354$2_DATA $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 - update $memwr$\mem$ls180.v:10354$2_EN $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 - update $memwr$\mem$ls180.v:10356$3_ADDR $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 - update $memwr$\mem$ls180.v:10356$3_DATA $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 - update $memwr$\mem$ls180.v:10356$3_EN $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 - update $memwr$\mem$ls180.v:10358$4_ADDR $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 - update $memwr$\mem$ls180.v:10358$4_DATA $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 - update $memwr$\mem$ls180.v:10358$4_EN $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 - update $memwr$\mem$ls180.v:10360$5_ADDR $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 - update $memwr$\mem$ls180.v:10360$5_DATA $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 - update $memwr$\mem$ls180.v:10360$5_EN $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 - update $memwr$\mem$ls180.v:10362$6_ADDR $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 - update $memwr$\mem$ls180.v:10362$6_DATA $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 - update $memwr$\mem$ls180.v:10362$6_EN $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 - update $memwr$\mem$ls180.v:10364$7_ADDR $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 - update $memwr$\mem$ls180.v:10364$7_DATA $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 - update $memwr$\mem$ls180.v:10364$7_EN $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 - update $memwr$\mem$ls180.v:10366$8_ADDR $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 - update $memwr$\mem$ls180.v:10366$8_DATA $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 - update $memwr$\mem$ls180.v:10366$8_EN $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 + update $memwr$\mem$ls180.v:10355$1_ADDR $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2892 + update $memwr$\mem$ls180.v:10355$1_DATA $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2893 + update $memwr$\mem$ls180.v:10355$1_EN $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2894 + update $memwr$\mem$ls180.v:10357$2_ADDR $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2895 + update $memwr$\mem$ls180.v:10357$2_DATA $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2896 + update $memwr$\mem$ls180.v:10357$2_EN $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2897 + update $memwr$\mem$ls180.v:10359$3_ADDR $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2898 + update $memwr$\mem$ls180.v:10359$3_DATA $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2899 + update $memwr$\mem$ls180.v:10359$3_EN $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2900 + update $memwr$\mem$ls180.v:10361$4_ADDR $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2901 + update $memwr$\mem$ls180.v:10361$4_DATA $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2902 + update $memwr$\mem$ls180.v:10361$4_EN $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2903 + update $memwr$\mem$ls180.v:10363$5_ADDR $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2904 + update $memwr$\mem$ls180.v:10363$5_DATA $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2905 + update $memwr$\mem$ls180.v:10363$5_EN $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2906 + update $memwr$\mem$ls180.v:10365$6_ADDR $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2907 + update $memwr$\mem$ls180.v:10365$6_DATA $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2908 + update $memwr$\mem$ls180.v:10365$6_EN $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2909 + update $memwr$\mem$ls180.v:10367$7_ADDR $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2910 + update $memwr$\mem$ls180.v:10367$7_DATA $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2911 + update $memwr$\mem$ls180.v:10367$7_EN $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2912 + update $memwr$\mem$ls180.v:10369$8_ADDR $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2913 + update $memwr$\mem$ls180.v:10369$8_DATA $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2914 + update $memwr$\mem$ls180.v:10369$8_EN $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2915 end - attribute \src "ls180.v:10378.1-10396.4" - process $proc$ls180.v:10378$2917 + attribute \src "ls180.v:10381.1-10399.4" + process $proc$ls180.v:10381$2917 assign { } { } assign { } { } assign { } { } @@ -279794,129 +282319,129 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_1[5:0] \main_sram0_adr - attribute \src "ls180.v:10379.2-10380.55" + attribute \src "ls180.v:10382.2-10383.55" switch \main_sram0_we [0] - attribute \src "ls180.v:10379.6-10379.22" + attribute \src "ls180.v:10382.6-10382.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10381.2-10382.57" + attribute \src "ls180.v:10384.2-10385.57" switch \main_sram0_we [1] - attribute \src "ls180.v:10381.6-10381.22" + attribute \src "ls180.v:10384.6-10384.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10383.2-10384.59" + attribute \src "ls180.v:10386.2-10387.59" switch \main_sram0_we [2] - attribute \src "ls180.v:10383.6-10383.22" + attribute \src "ls180.v:10386.6-10386.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10385.2-10386.59" + attribute \src "ls180.v:10388.2-10389.59" switch \main_sram0_we [3] - attribute \src "ls180.v:10385.6-10385.22" + attribute \src "ls180.v:10388.6-10388.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 64'0000000000000000000000000000000011111111000000000000000000000000 case end - attribute \src "ls180.v:10387.2-10388.59" + attribute \src "ls180.v:10390.2-10391.59" switch \main_sram0_we [4] - attribute \src "ls180.v:10387.6-10387.22" + attribute \src "ls180.v:10390.6-10390.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 64'0000000000000000000000001111111100000000000000000000000000000000 case end - attribute \src "ls180.v:10389.2-10390.59" + attribute \src "ls180.v:10392.2-10393.59" switch \main_sram0_we [5] - attribute \src "ls180.v:10389.6-10389.22" + attribute \src "ls180.v:10392.6-10392.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 64'0000000000000000111111110000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10391.2-10392.59" + attribute \src "ls180.v:10394.2-10395.59" switch \main_sram0_we [6] - attribute \src "ls180.v:10391.6-10391.22" + attribute \src "ls180.v:10394.6-10394.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 64'0000000011111111000000000000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10393.2-10394.59" + attribute \src "ls180.v:10396.2-10397.59" switch \main_sram0_we [7] - attribute \src "ls180.v:10393.6-10393.22" + attribute \src "ls180.v:10396.6-10396.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_1 $0\memadr_1[5:0] - update $memwr$\mem_1$ls180.v:10380$9_ADDR $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 - update $memwr$\mem_1$ls180.v:10380$9_DATA $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 - update $memwr$\mem_1$ls180.v:10380$9_EN $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 - update $memwr$\mem_1$ls180.v:10382$10_ADDR $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 - update $memwr$\mem_1$ls180.v:10382$10_DATA $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 - update $memwr$\mem_1$ls180.v:10382$10_EN $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 - update $memwr$\mem_1$ls180.v:10384$11_ADDR $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 - update $memwr$\mem_1$ls180.v:10384$11_DATA $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 - update $memwr$\mem_1$ls180.v:10384$11_EN $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 - update $memwr$\mem_1$ls180.v:10386$12_ADDR $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 - update $memwr$\mem_1$ls180.v:10386$12_DATA $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 - update $memwr$\mem_1$ls180.v:10386$12_EN $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 - update $memwr$\mem_1$ls180.v:10388$13_ADDR $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 - update $memwr$\mem_1$ls180.v:10388$13_DATA $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 - update $memwr$\mem_1$ls180.v:10388$13_EN $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 - update $memwr$\mem_1$ls180.v:10390$14_ADDR $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 - update $memwr$\mem_1$ls180.v:10390$14_DATA $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 - update $memwr$\mem_1$ls180.v:10390$14_EN $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 - update $memwr$\mem_1$ls180.v:10392$15_ADDR $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 - update $memwr$\mem_1$ls180.v:10392$15_DATA $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 - update $memwr$\mem_1$ls180.v:10392$15_EN $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 - update $memwr$\mem_1$ls180.v:10394$16_ADDR $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 - update $memwr$\mem_1$ls180.v:10394$16_DATA $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 - update $memwr$\mem_1$ls180.v:10394$16_EN $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 + update $memwr$\mem_1$ls180.v:10383$9_ADDR $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2918 + update $memwr$\mem_1$ls180.v:10383$9_DATA $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2919 + update $memwr$\mem_1$ls180.v:10383$9_EN $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2920 + update $memwr$\mem_1$ls180.v:10385$10_ADDR $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2921 + update $memwr$\mem_1$ls180.v:10385$10_DATA $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2922 + update $memwr$\mem_1$ls180.v:10385$10_EN $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2923 + update $memwr$\mem_1$ls180.v:10387$11_ADDR $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2924 + update $memwr$\mem_1$ls180.v:10387$11_DATA $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2925 + update $memwr$\mem_1$ls180.v:10387$11_EN $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2926 + update $memwr$\mem_1$ls180.v:10389$12_ADDR $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2927 + update $memwr$\mem_1$ls180.v:10389$12_DATA $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2928 + update $memwr$\mem_1$ls180.v:10389$12_EN $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2929 + update $memwr$\mem_1$ls180.v:10391$13_ADDR $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2930 + update $memwr$\mem_1$ls180.v:10391$13_DATA $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2931 + update $memwr$\mem_1$ls180.v:10391$13_EN $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2932 + update $memwr$\mem_1$ls180.v:10393$14_ADDR $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2933 + update $memwr$\mem_1$ls180.v:10393$14_DATA $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2934 + update $memwr$\mem_1$ls180.v:10393$14_EN $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2935 + update $memwr$\mem_1$ls180.v:10395$15_ADDR $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2936 + update $memwr$\mem_1$ls180.v:10395$15_DATA $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2937 + update $memwr$\mem_1$ls180.v:10395$15_EN $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2938 + update $memwr$\mem_1$ls180.v:10397$16_ADDR $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2939 + update $memwr$\mem_1$ls180.v:10397$16_DATA $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2940 + update $memwr$\mem_1$ls180.v:10397$16_EN $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2941 end attribute \src "ls180.v:104.5-104.49" process $proc$ls180.v:104$3147 @@ -279926,8 +282451,8 @@ module \ls180 sync init update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] end - attribute \src "ls180.v:10406.1-10424.4" - process $proc$ls180.v:10406$2943 + attribute \src "ls180.v:10409.1-10427.4" + process $proc$ls180.v:10409$2943 assign { } { } assign { } { } assign { } { } @@ -279953,132 +282478,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_2[5:0] \main_sram1_adr - attribute \src "ls180.v:10407.2-10408.55" + attribute \src "ls180.v:10410.2-10411.55" switch \main_sram1_we [0] - attribute \src "ls180.v:10407.6-10407.22" + attribute \src "ls180.v:10410.6-10410.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } - assign $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } + assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10409.2-10410.57" + attribute \src "ls180.v:10412.2-10413.57" switch \main_sram1_we [1] - attribute \src "ls180.v:10409.6-10409.22" + attribute \src "ls180.v:10412.6-10412.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10411.2-10412.59" + attribute \src "ls180.v:10414.2-10415.59" switch \main_sram1_we [2] - attribute \src "ls180.v:10411.6-10411.22" + attribute \src "ls180.v:10414.6-10414.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10413.2-10414.59" + attribute \src "ls180.v:10416.2-10417.59" switch \main_sram1_we [3] - attribute \src "ls180.v:10413.6-10413.22" + attribute \src "ls180.v:10416.6-10416.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 64'0000000000000000000000000000000011111111000000000000000000000000 case end - attribute \src "ls180.v:10415.2-10416.59" + attribute \src "ls180.v:10418.2-10419.59" switch \main_sram1_we [4] - attribute \src "ls180.v:10415.6-10415.22" + attribute \src "ls180.v:10418.6-10418.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 64'0000000000000000000000001111111100000000000000000000000000000000 case end - attribute \src "ls180.v:10417.2-10418.59" + attribute \src "ls180.v:10420.2-10421.59" switch \main_sram1_we [5] - attribute \src "ls180.v:10417.6-10417.22" + attribute \src "ls180.v:10420.6-10420.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 64'0000000000000000111111110000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10419.2-10420.59" + attribute \src "ls180.v:10422.2-10423.59" switch \main_sram1_we [6] - attribute \src "ls180.v:10419.6-10419.22" + attribute \src "ls180.v:10422.6-10422.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 64'0000000011111111000000000000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10421.2-10422.59" + attribute \src "ls180.v:10424.2-10425.59" switch \main_sram1_we [7] - attribute \src "ls180.v:10421.6-10421.22" + attribute \src "ls180.v:10424.6-10424.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_2 $0\memadr_2[5:0] - update $memwr$\mem_2$ls180.v:10408$17_ADDR $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 - update $memwr$\mem_2$ls180.v:10408$17_DATA $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 - update $memwr$\mem_2$ls180.v:10408$17_EN $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 - update $memwr$\mem_2$ls180.v:10410$18_ADDR $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 - update $memwr$\mem_2$ls180.v:10410$18_DATA $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 - update $memwr$\mem_2$ls180.v:10410$18_EN $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 - update $memwr$\mem_2$ls180.v:10412$19_ADDR $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 - update $memwr$\mem_2$ls180.v:10412$19_DATA $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 - update $memwr$\mem_2$ls180.v:10412$19_EN $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 - update $memwr$\mem_2$ls180.v:10414$20_ADDR $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 - update $memwr$\mem_2$ls180.v:10414$20_DATA $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 - update $memwr$\mem_2$ls180.v:10414$20_EN $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 - update $memwr$\mem_2$ls180.v:10416$21_ADDR $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 - update $memwr$\mem_2$ls180.v:10416$21_DATA $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 - update $memwr$\mem_2$ls180.v:10416$21_EN $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 - update $memwr$\mem_2$ls180.v:10418$22_ADDR $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 - update $memwr$\mem_2$ls180.v:10418$22_DATA $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 - update $memwr$\mem_2$ls180.v:10418$22_EN $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 - update $memwr$\mem_2$ls180.v:10420$23_ADDR $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 - update $memwr$\mem_2$ls180.v:10420$23_DATA $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 - update $memwr$\mem_2$ls180.v:10420$23_EN $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 - update $memwr$\mem_2$ls180.v:10422$24_ADDR $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 - update $memwr$\mem_2$ls180.v:10422$24_DATA $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 - update $memwr$\mem_2$ls180.v:10422$24_EN $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 + update $memwr$\mem_2$ls180.v:10411$17_ADDR $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2944 + update $memwr$\mem_2$ls180.v:10411$17_DATA $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2945 + update $memwr$\mem_2$ls180.v:10411$17_EN $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2946 + update $memwr$\mem_2$ls180.v:10413$18_ADDR $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2947 + update $memwr$\mem_2$ls180.v:10413$18_DATA $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2948 + update $memwr$\mem_2$ls180.v:10413$18_EN $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2949 + update $memwr$\mem_2$ls180.v:10415$19_ADDR $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2950 + update $memwr$\mem_2$ls180.v:10415$19_DATA $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2951 + update $memwr$\mem_2$ls180.v:10415$19_EN $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2952 + update $memwr$\mem_2$ls180.v:10417$20_ADDR $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2953 + update $memwr$\mem_2$ls180.v:10417$20_DATA $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2954 + update $memwr$\mem_2$ls180.v:10417$20_EN $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2955 + update $memwr$\mem_2$ls180.v:10419$21_ADDR $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2956 + update $memwr$\mem_2$ls180.v:10419$21_DATA $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2957 + update $memwr$\mem_2$ls180.v:10419$21_EN $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2958 + update $memwr$\mem_2$ls180.v:10421$22_ADDR $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2959 + update $memwr$\mem_2$ls180.v:10421$22_DATA $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2960 + update $memwr$\mem_2$ls180.v:10421$22_EN $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2961 + update $memwr$\mem_2$ls180.v:10423$23_ADDR $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2962 + update $memwr$\mem_2$ls180.v:10423$23_DATA $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2963 + update $memwr$\mem_2$ls180.v:10423$23_EN $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2964 + update $memwr$\mem_2$ls180.v:10425$24_ADDR $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2965 + update $memwr$\mem_2$ls180.v:10425$24_DATA $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2966 + update $memwr$\mem_2$ls180.v:10425$24_EN $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2967 end - attribute \src "ls180.v:10434.1-10452.4" - process $proc$ls180.v:10434$2969 + attribute \src "ls180.v:10437.1-10455.4" + process $proc$ls180.v:10437$2969 assign { } { } assign { } { } assign { } { } @@ -280104,132 +282629,132 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_3[5:0] \main_sram2_adr - attribute \src "ls180.v:10435.2-10436.55" + attribute \src "ls180.v:10438.2-10439.55" switch \main_sram2_we [0] - attribute \src "ls180.v:10435.6-10435.22" + attribute \src "ls180.v:10438.6-10438.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } - assign $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } + assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10437.2-10438.57" + attribute \src "ls180.v:10440.2-10441.57" switch \main_sram2_we [1] - attribute \src "ls180.v:10437.6-10437.22" + attribute \src "ls180.v:10440.6-10440.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10439.2-10440.59" + attribute \src "ls180.v:10442.2-10443.59" switch \main_sram2_we [2] - attribute \src "ls180.v:10439.6-10439.22" + attribute \src "ls180.v:10442.6-10442.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10441.2-10442.59" + attribute \src "ls180.v:10444.2-10445.59" switch \main_sram2_we [3] - attribute \src "ls180.v:10441.6-10441.22" + attribute \src "ls180.v:10444.6-10444.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 64'0000000000000000000000000000000011111111000000000000000000000000 case end - attribute \src "ls180.v:10443.2-10444.59" + attribute \src "ls180.v:10446.2-10447.59" switch \main_sram2_we [4] - attribute \src "ls180.v:10443.6-10443.22" + attribute \src "ls180.v:10446.6-10446.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 64'0000000000000000000000001111111100000000000000000000000000000000 case end - attribute \src "ls180.v:10445.2-10446.59" + attribute \src "ls180.v:10448.2-10449.59" switch \main_sram2_we [5] - attribute \src "ls180.v:10445.6-10445.22" + attribute \src "ls180.v:10448.6-10448.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 64'0000000000000000111111110000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10447.2-10448.59" + attribute \src "ls180.v:10450.2-10451.59" switch \main_sram2_we [6] - attribute \src "ls180.v:10447.6-10447.22" + attribute \src "ls180.v:10450.6-10450.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 64'0000000011111111000000000000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10449.2-10450.59" + attribute \src "ls180.v:10452.2-10453.59" switch \main_sram2_we [7] - attribute \src "ls180.v:10449.6-10449.22" + attribute \src "ls180.v:10452.6-10452.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_3 $0\memadr_3[5:0] - update $memwr$\mem_3$ls180.v:10436$25_ADDR $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 - update $memwr$\mem_3$ls180.v:10436$25_DATA $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 - update $memwr$\mem_3$ls180.v:10436$25_EN $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 - update $memwr$\mem_3$ls180.v:10438$26_ADDR $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 - update $memwr$\mem_3$ls180.v:10438$26_DATA $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 - update $memwr$\mem_3$ls180.v:10438$26_EN $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 - update $memwr$\mem_3$ls180.v:10440$27_ADDR $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 - update $memwr$\mem_3$ls180.v:10440$27_DATA $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 - update $memwr$\mem_3$ls180.v:10440$27_EN $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 - update $memwr$\mem_3$ls180.v:10442$28_ADDR $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 - update $memwr$\mem_3$ls180.v:10442$28_DATA $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 - update $memwr$\mem_3$ls180.v:10442$28_EN $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 - update $memwr$\mem_3$ls180.v:10444$29_ADDR $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 - update $memwr$\mem_3$ls180.v:10444$29_DATA $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 - update $memwr$\mem_3$ls180.v:10444$29_EN $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 - update $memwr$\mem_3$ls180.v:10446$30_ADDR $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 - update $memwr$\mem_3$ls180.v:10446$30_DATA $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 - update $memwr$\mem_3$ls180.v:10446$30_EN $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 - update $memwr$\mem_3$ls180.v:10448$31_ADDR $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 - update $memwr$\mem_3$ls180.v:10448$31_DATA $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 - update $memwr$\mem_3$ls180.v:10448$31_EN $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 - update $memwr$\mem_3$ls180.v:10450$32_ADDR $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 - update $memwr$\mem_3$ls180.v:10450$32_DATA $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 - update $memwr$\mem_3$ls180.v:10450$32_EN $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 + update $memwr$\mem_3$ls180.v:10439$25_ADDR $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2970 + update $memwr$\mem_3$ls180.v:10439$25_DATA $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2971 + update $memwr$\mem_3$ls180.v:10439$25_EN $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2972 + update $memwr$\mem_3$ls180.v:10441$26_ADDR $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2973 + update $memwr$\mem_3$ls180.v:10441$26_DATA $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2974 + update $memwr$\mem_3$ls180.v:10441$26_EN $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2975 + update $memwr$\mem_3$ls180.v:10443$27_ADDR $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2976 + update $memwr$\mem_3$ls180.v:10443$27_DATA $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2977 + update $memwr$\mem_3$ls180.v:10443$27_EN $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2978 + update $memwr$\mem_3$ls180.v:10445$28_ADDR $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2979 + update $memwr$\mem_3$ls180.v:10445$28_DATA $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2980 + update $memwr$\mem_3$ls180.v:10445$28_EN $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2981 + update $memwr$\mem_3$ls180.v:10447$29_ADDR $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2982 + update $memwr$\mem_3$ls180.v:10447$29_DATA $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2983 + update $memwr$\mem_3$ls180.v:10447$29_EN $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2984 + update $memwr$\mem_3$ls180.v:10449$30_ADDR $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2985 + update $memwr$\mem_3$ls180.v:10449$30_DATA $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2986 + update $memwr$\mem_3$ls180.v:10449$30_EN $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2987 + update $memwr$\mem_3$ls180.v:10451$31_ADDR $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2988 + update $memwr$\mem_3$ls180.v:10451$31_DATA $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2989 + update $memwr$\mem_3$ls180.v:10451$31_EN $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2990 + update $memwr$\mem_3$ls180.v:10453$32_ADDR $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2991 + update $memwr$\mem_3$ls180.v:10453$32_DATA $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2992 + update $memwr$\mem_3$ls180.v:10453$32_EN $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2993 end - attribute \src "ls180.v:10462.1-10480.4" - process $proc$ls180.v:10462$2995 + attribute \src "ls180.v:10465.1-10483.4" + process $proc$ls180.v:10465$2995 assign { } { } assign { } { } assign { } { } @@ -280255,700 +282780,692 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\memadr_4[5:0] \main_sram3_adr - attribute \src "ls180.v:10463.2-10464.55" + attribute \src "ls180.v:10466.2-10467.55" switch \main_sram3_we [0] - attribute \src "ls180.v:10463.6-10463.22" + attribute \src "ls180.v:10466.6-10466.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } - assign $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } + assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10465.2-10466.57" + attribute \src "ls180.v:10468.2-10469.57" switch \main_sram3_we [1] - attribute \src "ls180.v:10465.6-10465.22" + attribute \src "ls180.v:10468.6-10468.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10467.2-10468.59" + attribute \src "ls180.v:10470.2-10471.59" switch \main_sram3_we [2] - attribute \src "ls180.v:10467.6-10467.22" + attribute \src "ls180.v:10470.6-10470.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10469.2-10470.59" + attribute \src "ls180.v:10472.2-10473.59" switch \main_sram3_we [3] - attribute \src "ls180.v:10469.6-10469.22" + attribute \src "ls180.v:10472.6-10472.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 64'0000000000000000000000000000000011111111000000000000000000000000 case end - attribute \src "ls180.v:10471.2-10472.59" + attribute \src "ls180.v:10474.2-10475.59" switch \main_sram3_we [4] - attribute \src "ls180.v:10471.6-10471.22" + attribute \src "ls180.v:10474.6-10474.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 64'0000000000000000000000001111111100000000000000000000000000000000 case end - attribute \src "ls180.v:10473.2-10474.59" + attribute \src "ls180.v:10476.2-10477.59" switch \main_sram3_we [5] - attribute \src "ls180.v:10473.6-10473.22" + attribute \src "ls180.v:10476.6-10476.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 64'0000000000000000111111110000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10475.2-10476.59" + attribute \src "ls180.v:10478.2-10479.59" switch \main_sram3_we [6] - attribute \src "ls180.v:10475.6-10475.22" + attribute \src "ls180.v:10478.6-10478.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 64'0000000011111111000000000000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10477.2-10478.59" + attribute \src "ls180.v:10480.2-10481.59" switch \main_sram3_we [7] - attribute \src "ls180.v:10477.6-10477.22" + attribute \src "ls180.v:10480.6-10480.22" case 1'1 - assign $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr_4 $0\memadr_4[5:0] - update $memwr$\mem_4$ls180.v:10464$33_ADDR $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 - update $memwr$\mem_4$ls180.v:10464$33_DATA $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 - update $memwr$\mem_4$ls180.v:10464$33_EN $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 - update $memwr$\mem_4$ls180.v:10466$34_ADDR $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 - update $memwr$\mem_4$ls180.v:10466$34_DATA $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 - update $memwr$\mem_4$ls180.v:10466$34_EN $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 - update $memwr$\mem_4$ls180.v:10468$35_ADDR $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 - update $memwr$\mem_4$ls180.v:10468$35_DATA $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 - update $memwr$\mem_4$ls180.v:10468$35_EN $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 - update $memwr$\mem_4$ls180.v:10470$36_ADDR $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 - update $memwr$\mem_4$ls180.v:10470$36_DATA $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 - update $memwr$\mem_4$ls180.v:10470$36_EN $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 - update $memwr$\mem_4$ls180.v:10472$37_ADDR $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 - update $memwr$\mem_4$ls180.v:10472$37_DATA $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 - update $memwr$\mem_4$ls180.v:10472$37_EN $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 - update $memwr$\mem_4$ls180.v:10474$38_ADDR $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 - update $memwr$\mem_4$ls180.v:10474$38_DATA $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 - update $memwr$\mem_4$ls180.v:10474$38_EN $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 - update $memwr$\mem_4$ls180.v:10476$39_ADDR $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 - update $memwr$\mem_4$ls180.v:10476$39_DATA $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 - update $memwr$\mem_4$ls180.v:10476$39_EN $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 - update $memwr$\mem_4$ls180.v:10478$40_ADDR $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 - update $memwr$\mem_4$ls180.v:10478$40_DATA $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 - update $memwr$\mem_4$ls180.v:10478$40_EN $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 - end - attribute \src "ls180.v:10490.1-10494.4" - process $proc$ls180.v:10490$3021 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 3'xxx - assign $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10493$3025_DATA - attribute \src "ls180.v:10491.2-10492.129" + update $memwr$\mem_4$ls180.v:10467$33_ADDR $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2996 + update $memwr$\mem_4$ls180.v:10467$33_DATA $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2997 + update $memwr$\mem_4$ls180.v:10467$33_EN $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$2998 + update $memwr$\mem_4$ls180.v:10469$34_ADDR $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$2999 + update $memwr$\mem_4$ls180.v:10469$34_DATA $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3000 + update $memwr$\mem_4$ls180.v:10469$34_EN $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3001 + update $memwr$\mem_4$ls180.v:10471$35_ADDR $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3002 + update $memwr$\mem_4$ls180.v:10471$35_DATA $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3003 + update $memwr$\mem_4$ls180.v:10471$35_EN $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3004 + update $memwr$\mem_4$ls180.v:10473$36_ADDR $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3005 + update $memwr$\mem_4$ls180.v:10473$36_DATA $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3006 + update $memwr$\mem_4$ls180.v:10473$36_EN $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3007 + update $memwr$\mem_4$ls180.v:10475$37_ADDR $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3008 + update $memwr$\mem_4$ls180.v:10475$37_DATA $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3009 + update $memwr$\mem_4$ls180.v:10475$37_EN $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3010 + update $memwr$\mem_4$ls180.v:10477$38_ADDR $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3011 + update $memwr$\mem_4$ls180.v:10477$38_DATA $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3012 + update $memwr$\mem_4$ls180.v:10477$38_EN $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3013 + update $memwr$\mem_4$ls180.v:10479$39_ADDR $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3014 + update $memwr$\mem_4$ls180.v:10479$39_DATA $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3015 + update $memwr$\mem_4$ls180.v:10479$39_EN $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3016 + update $memwr$\mem_4$ls180.v:10481$40_ADDR $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3017 + update $memwr$\mem_4$ls180.v:10481$40_DATA $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3018 + update $memwr$\mem_4$ls180.v:10481$40_EN $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3019 + end + attribute \src "ls180.v:10493.1-10497.4" + process $proc$ls180.v:10493$3021 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 3'xxx + assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10496$3025_DATA + attribute \src "ls180.v:10494.2-10495.129" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10491.6-10491.60" + attribute \src "ls180.v:10494.6-10494.60" case 1'1 - assign $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 25'1111111111111111111111111 + assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10492$41_ADDR $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 - update $memwr$\storage$ls180.v:10492$41_DATA $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 - update $memwr$\storage$ls180.v:10492$41_EN $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 + update $memwr$\storage$ls180.v:10495$41_ADDR $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3022 + update $memwr$\storage$ls180.v:10495$41_DATA $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3023 + update $memwr$\storage$ls180.v:10495$41_EN $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3024 end - attribute \src "ls180.v:10496.1-10497.4" - process $proc$ls180.v:10496$3026 + attribute \src "ls180.v:10499.1-10500.4" + process $proc$ls180.v:10499$3026 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10504.1-10508.4" - process $proc$ls180.v:10504$3028 + attribute \src "ls180.v:10507.1-10511.4" + process $proc$ls180.v:10507$3028 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 3'xxx - assign $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10507$3032_DATA - attribute \src "ls180.v:10505.2-10506.131" + assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 3'xxx + assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10510$3032_DATA + attribute \src "ls180.v:10508.2-10509.131" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10505.6-10505.60" + attribute \src "ls180.v:10508.6-10508.60" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 25'1111111111111111111111111 + assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10506$42_ADDR $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 - update $memwr$\storage_1$ls180.v:10506$42_DATA $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 - update $memwr$\storage_1$ls180.v:10506$42_EN $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 + update $memwr$\storage_1$ls180.v:10509$42_ADDR $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3029 + update $memwr$\storage_1$ls180.v:10509$42_DATA $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3030 + update $memwr$\storage_1$ls180.v:10509$42_EN $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3031 end - attribute \src "ls180.v:10510.1-10511.4" - process $proc$ls180.v:10510$3033 + attribute \src "ls180.v:10513.1-10514.4" + process $proc$ls180.v:10513$3033 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10518.1-10522.4" - process $proc$ls180.v:10518$3035 + attribute \src "ls180.v:10521.1-10525.4" + process $proc$ls180.v:10521$3035 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 3'xxx - assign $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10521$3039_DATA - attribute \src "ls180.v:10519.2-10520.131" + assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 3'xxx + assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10524$3039_DATA + attribute \src "ls180.v:10522.2-10523.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10519.6-10519.60" + attribute \src "ls180.v:10522.6-10522.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10520$43_ADDR $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 - update $memwr$\storage_2$ls180.v:10520$43_DATA $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 - update $memwr$\storage_2$ls180.v:10520$43_EN $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 + update $memwr$\storage_2$ls180.v:10523$43_ADDR $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3036 + update $memwr$\storage_2$ls180.v:10523$43_DATA $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3037 + update $memwr$\storage_2$ls180.v:10523$43_EN $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3038 end - attribute \src "ls180.v:10524.1-10525.4" - process $proc$ls180.v:10524$3040 + attribute \src "ls180.v:10527.1-10528.4" + process $proc$ls180.v:10527$3040 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10532.1-10536.4" - process $proc$ls180.v:10532$3042 + attribute \src "ls180.v:10535.1-10539.4" + process $proc$ls180.v:10535$3042 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 3'xxx - assign $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10535$3046_DATA - attribute \src "ls180.v:10533.2-10534.131" + assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 3'xxx + assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10538$3046_DATA + attribute \src "ls180.v:10536.2-10537.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10533.6-10533.60" + attribute \src "ls180.v:10536.6-10536.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10534$44_ADDR $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 - update $memwr$\storage_3$ls180.v:10534$44_DATA $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 - update $memwr$\storage_3$ls180.v:10534$44_EN $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 + update $memwr$\storage_3$ls180.v:10537$44_ADDR $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3043 + update $memwr$\storage_3$ls180.v:10537$44_DATA $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3044 + update $memwr$\storage_3$ls180.v:10537$44_EN $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3045 end - attribute \src "ls180.v:10538.1-10539.4" - process $proc$ls180.v:10538$3047 + attribute \src "ls180.v:10541.1-10542.4" + process $proc$ls180.v:10541$3047 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10547.1-10551.4" - process $proc$ls180.v:10547$3049 + attribute \src "ls180.v:10550.1-10554.4" + process $proc$ls180.v:10550$3049 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10550$3053_DATA - attribute \src "ls180.v:10548.2-10549.77" + assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10553$3053_DATA + attribute \src "ls180.v:10551.2-10552.77" switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10548.6-10548.33" + attribute \src "ls180.v:10551.6-10551.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10549$45_ADDR $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 - update $memwr$\storage_4$ls180.v:10549$45_DATA $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 - update $memwr$\storage_4$ls180.v:10549$45_EN $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 + update $memwr$\storage_4$ls180.v:10552$45_ADDR $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3050 + update $memwr$\storage_4$ls180.v:10552$45_DATA $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3051 + update $memwr$\storage_4$ls180.v:10552$45_EN $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3052 end - attribute \src "ls180.v:1055.5-1055.38" - process $proc$ls180.v:1055$3493 - assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] - end - attribute \src "ls180.v:10553.1-10556.4" - process $proc$ls180.v:10553$3054 + attribute \src "ls180.v:10556.1-10559.4" + process $proc$ls180.v:10556$3054 assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10554.2-10555.55" + attribute \src "ls180.v:10557.2-10558.55" switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10554.6-10554.33" + attribute \src "ls180.v:10557.6-10557.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10555$3055_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10558$3055_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end - attribute \src "ls180.v:10564.1-10568.4" - process $proc$ls180.v:10564$3056 + attribute \src "ls180.v:10567.1-10571.4" + process $proc$ls180.v:10567$3056 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10567$3060_DATA - attribute \src "ls180.v:10565.2-10566.77" + assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10570$3060_DATA + attribute \src "ls180.v:10568.2-10569.77" switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10565.6-10565.33" + attribute \src "ls180.v:10568.6-10568.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10566$46_ADDR $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 - update $memwr$\storage_5$ls180.v:10566$46_DATA $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 - update $memwr$\storage_5$ls180.v:10566$46_EN $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 + update $memwr$\storage_5$ls180.v:10569$46_ADDR $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3057 + update $memwr$\storage_5$ls180.v:10569$46_DATA $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3058 + update $memwr$\storage_5$ls180.v:10569$46_EN $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3059 end - attribute \src "ls180.v:10570.1-10573.4" - process $proc$ls180.v:10570$3061 + attribute \src "ls180.v:10573.1-10576.4" + process $proc$ls180.v:10573$3061 assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10571.2-10572.55" + attribute \src "ls180.v:10574.2-10575.55" switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10571.6-10571.33" + attribute \src "ls180.v:10574.6-10574.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10572$3062_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10575$3062_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end - attribute \src "ls180.v:10580.1-10584.4" - process $proc$ls180.v:10580$3063 + attribute \src "ls180.v:1058.5-1058.38" + process $proc$ls180.v:1058$3491 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:10583.1-10587.4" + process $proc$ls180.v:10583$3063 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10583$3067_DATA - attribute \src "ls180.v:10581.2-10582.85" + assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10586$3067_DATA + attribute \src "ls180.v:10584.2-10585.85" switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10581.6-10581.37" + attribute \src "ls180.v:10584.6-10584.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10582$47_ADDR $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 - update $memwr$\storage_6$ls180.v:10582$47_DATA $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 - update $memwr$\storage_6$ls180.v:10582$47_EN $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 + update $memwr$\storage_6$ls180.v:10585$47_ADDR $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3064 + update $memwr$\storage_6$ls180.v:10585$47_DATA $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3065 + update $memwr$\storage_6$ls180.v:10585$47_EN $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3066 end - attribute \src "ls180.v:10586.1-10587.4" - process $proc$ls180.v:10586$3068 + attribute \src "ls180.v:10589.1-10590.4" + process $proc$ls180.v:10589$3068 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10594.1-10598.4" - process $proc$ls180.v:10594$3070 + attribute \src "ls180.v:10597.1-10601.4" + process $proc$ls180.v:10597$3070 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10597$3074_DATA - attribute \src "ls180.v:10595.2-10596.85" + assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10600$3074_DATA + attribute \src "ls180.v:10598.2-10599.85" switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10595.6-10595.37" + attribute \src "ls180.v:10598.6-10598.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10596$48_ADDR $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 - update $memwr$\storage_7$ls180.v:10596$48_DATA $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 - update $memwr$\storage_7$ls180.v:10596$48_EN $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 + update $memwr$\storage_7$ls180.v:10599$48_ADDR $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3071 + update $memwr$\storage_7$ls180.v:10599$48_DATA $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3072 + update $memwr$\storage_7$ls180.v:10599$48_EN $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3073 end - attribute \src "ls180.v:10600.1-10601.4" - process $proc$ls180.v:10600$3075 + attribute \src "ls180.v:10603.1-10604.4" + process $proc$ls180.v:10603$3075 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1062.11-1062.42" - process $proc$ls180.v:1062$3494 + attribute \src "ls180.v:1065.11-1065.42" + process $proc$ls180.v:1065$3492 assign { } { } assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] end - attribute \src "ls180.v:1063.5-1063.37" - process $proc$ls180.v:1063$3495 + attribute \src "ls180.v:1066.5-1066.37" + process $proc$ls180.v:1066$3493 assign { } { } assign $0\main_uart_rx_fifo_replace[0:0] 1'0 sync always update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1064.11-1064.43" - process $proc$ls180.v:1064$3496 + attribute \src "ls180.v:1067.11-1067.43" + process $proc$ls180.v:1067$3494 assign { } { } assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end - attribute \src "ls180.v:1065.11-1065.43" - process $proc$ls180.v:1065$3497 + attribute \src "ls180.v:1068.11-1068.43" + process $proc$ls180.v:1068$3495 assign { } { } assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end - attribute \src "ls180.v:1066.11-1066.46" - process $proc$ls180.v:1066$3498 + attribute \src "ls180.v:1069.11-1069.46" + process $proc$ls180.v:1069$3496 assign { } { } assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:1081.5-1081.27" - process $proc$ls180.v:1081$3499 + attribute \src "ls180.v:1084.5-1084.27" + process $proc$ls180.v:1084$3497 assign { } { } assign $0\main_uart_reset[0:0] 1'0 sync always update \main_uart_reset $0\main_uart_reset[0:0] sync init end - attribute \src "ls180.v:1082.12-1082.53" - process $proc$ls180.v:1082$3500 + attribute \src "ls180.v:1085.12-1085.53" + process $proc$ls180.v:1085$3498 assign { } { } assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 sync always update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] sync init end - attribute \src "ls180.v:1083.12-1083.49" - process $proc$ls180.v:1083$3501 + attribute \src "ls180.v:1086.12-1086.49" + process $proc$ls180.v:1086$3499 assign { } { } assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 sync always sync init update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] end - attribute \src "ls180.v:1084.12-1084.54" - process $proc$ls180.v:1084$3502 + attribute \src "ls180.v:1087.12-1087.54" + process $proc$ls180.v:1087$3500 assign { } { } assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 sync always update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] sync init end - attribute \src "ls180.v:1088.12-1088.53" - process $proc$ls180.v:1088$3503 + attribute \src "ls180.v:1091.12-1091.53" + process $proc$ls180.v:1091$3501 assign { } { } assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 sync always sync init update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] end - attribute \src "ls180.v:1089.5-1089.40" - process $proc$ls180.v:1089$3504 + attribute \src "ls180.v:1092.5-1092.40" + process $proc$ls180.v:1092$3502 assign { } { } assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 sync always sync init update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] end - attribute \src "ls180.v:1090.12-1090.49" - process $proc$ls180.v:1090$3505 + attribute \src "ls180.v:1093.12-1093.49" + process $proc$ls180.v:1093$3503 assign { } { } assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 sync always sync init update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] end - attribute \src "ls180.v:1092.12-1092.54" - process $proc$ls180.v:1092$3506 + attribute \src "ls180.v:1095.12-1095.54" + process $proc$ls180.v:1095$3504 assign { } { } assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 sync always sync init update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] end - attribute \src "ls180.v:1093.5-1093.41" - process $proc$ls180.v:1093$3507 + attribute \src "ls180.v:1096.5-1096.41" + process $proc$ls180.v:1096$3505 assign { } { } assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 sync always sync init update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] end - attribute \src "ls180.v:1099.5-1099.32" - process $proc$ls180.v:1099$3508 + attribute \src "ls180.v:1102.5-1102.32" + process $proc$ls180.v:1102$3506 assign { } { } assign $1\main_spimaster2_done[0:0] 1'0 sync always sync init update \main_spimaster2_done $1\main_spimaster2_done[0:0] end - attribute \src "ls180.v:1100.5-1100.31" - process $proc$ls180.v:1100$3509 + attribute \src "ls180.v:1103.5-1103.31" + process $proc$ls180.v:1103$3507 assign { } { } assign $1\main_spimaster3_irq[0:0] 1'0 sync always sync init update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] end - attribute \src "ls180.v:1102.11-1102.38" - process $proc$ls180.v:1102$3510 + attribute \src "ls180.v:1105.11-1105.38" + process $proc$ls180.v:1105$3508 assign { } { } assign $1\main_spimaster5_miso[7:0] 8'00000000 sync always sync init update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] end - attribute \src "ls180.v:1105.12-1105.47" - process $proc$ls180.v:1105$3511 + attribute \src "ls180.v:1108.12-1108.47" + process $proc$ls180.v:1108$3509 assign { } { } assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 sync always update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] sync init end - attribute \src "ls180.v:1106.5-1106.33" - process $proc$ls180.v:1106$3512 + attribute \src "ls180.v:1109.5-1109.33" + process $proc$ls180.v:1109$3510 assign { } { } assign $1\main_spimaster9_start[0:0] 1'0 sync always sync init update \main_spimaster9_start $1\main_spimaster9_start[0:0] end - attribute \src "ls180.v:1108.12-1108.44" - process $proc$ls180.v:1108$3513 + attribute \src "ls180.v:1111.12-1111.44" + process $proc$ls180.v:1111$3511 assign { } { } assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 sync always sync init update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] end - attribute \src "ls180.v:1109.5-1109.31" - process $proc$ls180.v:1109$3514 + attribute \src "ls180.v:1112.5-1112.31" + process $proc$ls180.v:1112$3512 assign { } { } assign $1\main_spimaster12_re[0:0] 1'0 sync always sync init update \main_spimaster12_re $1\main_spimaster12_re[0:0] end - attribute \src "ls180.v:1113.11-1113.42" - process $proc$ls180.v:1113$3515 + attribute \src "ls180.v:1116.11-1116.42" + process $proc$ls180.v:1116$3513 assign { } { } assign $1\main_spimaster16_storage[7:0] 8'00000000 sync always sync init update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] end - attribute \src "ls180.v:1114.5-1114.31" - process $proc$ls180.v:1114$3516 + attribute \src "ls180.v:1117.5-1117.31" + process $proc$ls180.v:1117$3514 assign { } { } assign $1\main_spimaster17_re[0:0] 1'0 sync always sync init update \main_spimaster17_re $1\main_spimaster17_re[0:0] end - attribute \src "ls180.v:1118.5-1118.36" - process $proc$ls180.v:1118$3517 + attribute \src "ls180.v:1121.5-1121.36" + process $proc$ls180.v:1121$3515 assign { } { } assign $1\main_spimaster21_storage[0:0] 1'1 sync always sync init update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] end - attribute \src "ls180.v:1119.5-1119.31" - process $proc$ls180.v:1119$3518 + attribute \src "ls180.v:1122.5-1122.31" + process $proc$ls180.v:1122$3516 assign { } { } assign $1\main_spimaster22_re[0:0] 1'0 sync always sync init update \main_spimaster22_re $1\main_spimaster22_re[0:0] end - attribute \src "ls180.v:1120.5-1120.36" - process $proc$ls180.v:1120$3519 + attribute \src "ls180.v:1123.5-1123.36" + process $proc$ls180.v:1123$3517 assign { } { } assign $1\main_spimaster23_storage[0:0] 1'0 sync always sync init update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] end - attribute \src "ls180.v:1121.5-1121.31" - process $proc$ls180.v:1121$3520 + attribute \src "ls180.v:1124.5-1124.31" + process $proc$ls180.v:1124$3518 assign { } { } assign $1\main_spimaster24_re[0:0] 1'0 sync always sync init update \main_spimaster24_re $1\main_spimaster24_re[0:0] end - attribute \src "ls180.v:1122.5-1122.39" - process $proc$ls180.v:1122$3521 + attribute \src "ls180.v:1125.5-1125.39" + process $proc$ls180.v:1125$3519 assign { } { } assign $1\main_spimaster25_clk_enable[0:0] 1'0 sync always sync init update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] end - attribute \src "ls180.v:1123.5-1123.38" - process $proc$ls180.v:1123$3522 + attribute \src "ls180.v:1126.5-1126.38" + process $proc$ls180.v:1126$3520 assign { } { } assign $1\main_spimaster26_cs_enable[0:0] 1'0 sync always sync init update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] end - attribute \src "ls180.v:1124.11-1124.40" - process $proc$ls180.v:1124$3523 + attribute \src "ls180.v:1127.11-1127.40" + process $proc$ls180.v:1127$3521 assign { } { } assign $1\main_spimaster27_count[2:0] 3'000 sync always sync init update \main_spimaster27_count $1\main_spimaster27_count[2:0] end - attribute \src "ls180.v:1125.5-1125.39" - process $proc$ls180.v:1125$3524 + attribute \src "ls180.v:1128.5-1128.39" + process $proc$ls180.v:1128$3522 assign { } { } assign $1\main_spimaster28_mosi_latch[0:0] 1'0 sync always sync init update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] end - attribute \src "ls180.v:1126.5-1126.39" - process $proc$ls180.v:1126$3525 + attribute \src "ls180.v:1129.5-1129.39" + process $proc$ls180.v:1129$3523 assign { } { } assign $1\main_spimaster29_miso_latch[0:0] 1'0 sync always sync init update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] end - attribute \src "ls180.v:1127.12-1127.48" - process $proc$ls180.v:1127$3526 + attribute \src "ls180.v:1130.12-1130.48" + process $proc$ls180.v:1130$3524 assign { } { } assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 sync always sync init update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] end - attribute \src "ls180.v:1130.11-1130.44" - process $proc$ls180.v:1130$3527 + attribute \src "ls180.v:1133.11-1133.44" + process $proc$ls180.v:1133$3525 assign { } { } assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 sync always sync init update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] end - attribute \src "ls180.v:1131.11-1131.43" - process $proc$ls180.v:1131$3528 + attribute \src "ls180.v:1134.11-1134.43" + process $proc$ls180.v:1134$3526 assign { } { } assign $1\main_spimaster34_mosi_sel[2:0] 3'000 sync always sync init update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] end - attribute \src "ls180.v:1132.11-1132.44" - process $proc$ls180.v:1132$3529 + attribute \src "ls180.v:1135.11-1135.44" + process $proc$ls180.v:1135$3527 assign { } { } assign $1\main_spimaster35_miso_data[7:0] 8'00000000 sync always sync init update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] end - attribute \src "ls180.v:1135.5-1135.32" - process $proc$ls180.v:1135$3530 + attribute \src "ls180.v:1138.5-1138.32" + process $proc$ls180.v:1138$3528 assign { } { } assign $1\main_spisdcard_done0[0:0] 1'0 sync always sync init update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] end - attribute \src "ls180.v:1136.5-1136.30" - process $proc$ls180.v:1136$3531 + attribute \src "ls180.v:1139.5-1139.30" + process $proc$ls180.v:1139$3529 assign { } { } assign $1\main_spisdcard_irq[0:0] 1'0 sync always sync init update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] end - attribute \src "ls180.v:1138.11-1138.37" - process $proc$ls180.v:1138$3532 - assign { } { } - assign $1\main_spisdcard_miso[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] - end attribute \src "ls180.v:114.11-114.55" process $proc$ls180.v:114$3148 assign { } { } @@ -280957,38 +283474,38 @@ module \ls180 update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] sync init end - attribute \src "ls180.v:1142.5-1142.33" - process $proc$ls180.v:1142$3533 + attribute \src "ls180.v:1141.11-1141.37" + process $proc$ls180.v:1141$3530 + assign { } { } + assign $1\main_spisdcard_miso[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] + end + attribute \src "ls180.v:1145.5-1145.33" + process $proc$ls180.v:1145$3531 assign { } { } assign $1\main_spisdcard_start1[0:0] 1'0 sync always sync init update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] end - attribute \src "ls180.v:1144.12-1144.50" - process $proc$ls180.v:1144$3534 + attribute \src "ls180.v:1147.12-1147.50" + process $proc$ls180.v:1147$3532 assign { } { } assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] end - attribute \src "ls180.v:1145.5-1145.37" - process $proc$ls180.v:1145$3535 + attribute \src "ls180.v:1148.5-1148.37" + process $proc$ls180.v:1148$3533 assign { } { } assign $1\main_spisdcard_control_re[0:0] 1'0 sync always sync init update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] end - attribute \src "ls180.v:1149.11-1149.45" - process $proc$ls180.v:1149$3536 - assign { } { } - assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] - end attribute \src "ls180.v:115.11-115.55" process $proc$ls180.v:115$3149 assign { } { } @@ -280997,4720 +283514,4704 @@ module \ls180 update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] sync init end - attribute \src "ls180.v:1150.5-1150.34" - process $proc$ls180.v:1150$3537 + attribute \src "ls180.v:1152.11-1152.45" + process $proc$ls180.v:1152$3534 + assign { } { } + assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] + end + attribute \src "ls180.v:1153.5-1153.34" + process $proc$ls180.v:1153$3535 assign { } { } assign $1\main_spisdcard_mosi_re[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] end - attribute \src "ls180.v:1154.5-1154.37" - process $proc$ls180.v:1154$3538 + attribute \src "ls180.v:1157.5-1157.37" + process $proc$ls180.v:1157$3536 assign { } { } assign $1\main_spisdcard_cs_storage[0:0] 1'1 sync always sync init update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] end - attribute \src "ls180.v:1155.5-1155.32" - process $proc$ls180.v:1155$3539 + attribute \src "ls180.v:1158.5-1158.32" + process $proc$ls180.v:1158$3537 assign { } { } assign $1\main_spisdcard_cs_re[0:0] 1'0 sync always sync init update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] end - attribute \src "ls180.v:1156.5-1156.43" - process $proc$ls180.v:1156$3540 + attribute \src "ls180.v:1159.5-1159.43" + process $proc$ls180.v:1159$3538 assign { } { } assign $1\main_spisdcard_loopback_storage[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] end - attribute \src "ls180.v:1157.5-1157.38" - process $proc$ls180.v:1157$3541 + attribute \src "ls180.v:1160.5-1160.38" + process $proc$ls180.v:1160$3539 assign { } { } assign $1\main_spisdcard_loopback_re[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] end - attribute \src "ls180.v:1158.5-1158.37" - process $proc$ls180.v:1158$3542 + attribute \src "ls180.v:1161.5-1161.37" + process $proc$ls180.v:1161$3540 assign { } { } assign $1\main_spisdcard_clk_enable[0:0] 1'0 sync always sync init update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] end - attribute \src "ls180.v:1159.5-1159.36" - process $proc$ls180.v:1159$3543 + attribute \src "ls180.v:1162.5-1162.36" + process $proc$ls180.v:1162$3541 assign { } { } assign $1\main_spisdcard_cs_enable[0:0] 1'0 sync always sync init update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] end - attribute \src "ls180.v:1160.11-1160.38" - process $proc$ls180.v:1160$3544 + attribute \src "ls180.v:1163.11-1163.38" + process $proc$ls180.v:1163$3542 assign { } { } assign $1\main_spisdcard_count[2:0] 3'000 sync always sync init update \main_spisdcard_count $1\main_spisdcard_count[2:0] end - attribute \src "ls180.v:1161.5-1161.37" - process $proc$ls180.v:1161$3545 + attribute \src "ls180.v:1164.5-1164.37" + process $proc$ls180.v:1164$3543 assign { } { } assign $1\main_spisdcard_mosi_latch[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] end - attribute \src "ls180.v:1162.5-1162.37" - process $proc$ls180.v:1162$3546 + attribute \src "ls180.v:1165.5-1165.37" + process $proc$ls180.v:1165$3544 assign { } { } assign $1\main_spisdcard_miso_latch[0:0] 1'0 sync always sync init update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] end - attribute \src "ls180.v:1163.12-1163.47" - process $proc$ls180.v:1163$3547 + attribute \src "ls180.v:1166.12-1166.47" + process $proc$ls180.v:1166$3545 assign { } { } assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] end - attribute \src "ls180.v:1166.11-1166.42" - process $proc$ls180.v:1166$3548 + attribute \src "ls180.v:1169.11-1169.42" + process $proc$ls180.v:1169$3546 assign { } { } assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] end - attribute \src "ls180.v:1167.11-1167.41" - process $proc$ls180.v:1167$3549 + attribute \src "ls180.v:1170.11-1170.41" + process $proc$ls180.v:1170$3547 assign { } { } assign $1\main_spisdcard_mosi_sel[2:0] 3'000 sync always sync init update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] end - attribute \src "ls180.v:1168.11-1168.42" - process $proc$ls180.v:1168$3550 + attribute \src "ls180.v:1171.11-1171.42" + process $proc$ls180.v:1171$3548 assign { } { } assign $1\main_spisdcard_miso_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] end - attribute \src "ls180.v:1169.12-1169.45" - process $proc$ls180.v:1169$3551 + attribute \src "ls180.v:1172.12-1172.45" + process $proc$ls180.v:1172$3549 assign { } { } assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 sync always sync init update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] end - attribute \src "ls180.v:1170.5-1170.30" - process $proc$ls180.v:1170$3552 + attribute \src "ls180.v:1173.5-1173.30" + process $proc$ls180.v:1173$3550 assign { } { } assign $1\main_spimaster1_re[0:0] 1'0 sync always sync init update \main_spimaster1_re $1\main_spimaster1_re[0:0] end - attribute \src "ls180.v:1172.12-1172.30" - process $proc$ls180.v:1172$3553 + attribute \src "ls180.v:1175.12-1175.30" + process $proc$ls180.v:1175$3551 assign { } { } assign $1\main_dummy[23:0] 24'000000000000000000000000 sync always sync init update \main_dummy $1\main_dummy[23:0] end - attribute \src "ls180.v:1176.12-1176.37" - process $proc$ls180.v:1176$3554 + attribute \src "ls180.v:1179.12-1179.37" + process $proc$ls180.v:1179$3552 assign { } { } assign $1\main_pwm0_counter[31:0] 0 sync always sync init update \main_pwm0_counter $1\main_pwm0_counter[31:0] end - attribute \src "ls180.v:1177.5-1177.36" - process $proc$ls180.v:1177$3555 + attribute \src "ls180.v:1180.5-1180.36" + process $proc$ls180.v:1180$3553 assign { } { } assign $1\main_pwm0_enable_storage[0:0] 1'0 sync always sync init update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] end - attribute \src "ls180.v:1178.5-1178.31" - process $proc$ls180.v:1178$3556 + attribute \src "ls180.v:1181.5-1181.31" + process $proc$ls180.v:1181$3554 assign { } { } assign $1\main_pwm0_enable_re[0:0] 1'0 sync always sync init update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] end - attribute \src "ls180.v:1179.12-1179.43" - process $proc$ls180.v:1179$3557 + attribute \src "ls180.v:1182.12-1182.43" + process $proc$ls180.v:1182$3555 assign { } { } assign $1\main_pwm0_width_storage[31:0] 0 sync always sync init update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] end - attribute \src "ls180.v:1180.5-1180.30" - process $proc$ls180.v:1180$3558 + attribute \src "ls180.v:1183.5-1183.30" + process $proc$ls180.v:1183$3556 assign { } { } assign $1\main_pwm0_width_re[0:0] 1'0 sync always sync init update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] end - attribute \src "ls180.v:1181.12-1181.44" - process $proc$ls180.v:1181$3559 + attribute \src "ls180.v:1184.12-1184.44" + process $proc$ls180.v:1184$3557 assign { } { } assign $1\main_pwm0_period_storage[31:0] 0 sync always sync init update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] end - attribute \src "ls180.v:1182.5-1182.31" - process $proc$ls180.v:1182$3560 + attribute \src "ls180.v:1185.5-1185.31" + process $proc$ls180.v:1185$3558 assign { } { } assign $1\main_pwm0_period_re[0:0] 1'0 sync always sync init update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] end - attribute \src "ls180.v:1186.12-1186.37" - process $proc$ls180.v:1186$3561 + attribute \src "ls180.v:1189.12-1189.37" + process $proc$ls180.v:1189$3559 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always sync init update \main_pwm1_counter $1\main_pwm1_counter[31:0] end - attribute \src "ls180.v:1187.5-1187.36" - process $proc$ls180.v:1187$3562 + attribute \src "ls180.v:1190.5-1190.36" + process $proc$ls180.v:1190$3560 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always sync init update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end - attribute \src "ls180.v:1188.5-1188.31" - process $proc$ls180.v:1188$3563 + attribute \src "ls180.v:1191.5-1191.31" + process $proc$ls180.v:1191$3561 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always sync init update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end - attribute \src "ls180.v:1189.12-1189.43" - process $proc$ls180.v:1189$3564 + attribute \src "ls180.v:1192.12-1192.43" + process $proc$ls180.v:1192$3562 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always sync init update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end - attribute \src "ls180.v:1190.5-1190.30" - process $proc$ls180.v:1190$3565 + attribute \src "ls180.v:1193.5-1193.30" + process $proc$ls180.v:1193$3563 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always sync init update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end - attribute \src "ls180.v:1191.12-1191.44" - process $proc$ls180.v:1191$3566 + attribute \src "ls180.v:1194.12-1194.44" + process $proc$ls180.v:1194$3564 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always sync init update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end - attribute \src "ls180.v:1192.5-1192.31" - process $proc$ls180.v:1192$3567 + attribute \src "ls180.v:1195.5-1195.31" + process $proc$ls180.v:1195$3565 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always sync init update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end - attribute \src "ls180.v:1196.11-1196.34" - process $proc$ls180.v:1196$3568 + attribute \src "ls180.v:1199.11-1199.34" + process $proc$ls180.v:1199$3566 assign { } { } assign $1\main_i2c_storage[2:0] 3'000 sync always sync init update \main_i2c_storage $1\main_i2c_storage[2:0] end - attribute \src "ls180.v:1197.5-1197.23" - process $proc$ls180.v:1197$3569 + attribute \src "ls180.v:1200.5-1200.23" + process $proc$ls180.v:1200$3567 assign { } { } assign $1\main_i2c_re[0:0] 1'0 sync always sync init update \main_i2c_re $1\main_i2c_re[0:0] end - attribute \src "ls180.v:1203.11-1203.46" - process $proc$ls180.v:1203$3570 + attribute \src "ls180.v:1206.11-1206.46" + process $proc$ls180.v:1206$3568 assign { } { } assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always sync init update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end - attribute \src "ls180.v:1204.5-1204.33" - process $proc$ls180.v:1204$3571 + attribute \src "ls180.v:1207.5-1207.33" + process $proc$ls180.v:1207$3569 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always sync init update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end - attribute \src "ls180.v:1206.5-1206.35" - process $proc$ls180.v:1206$3572 + attribute \src "ls180.v:1209.5-1209.35" + process $proc$ls180.v:1209$3570 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end - attribute \src "ls180.v:1208.11-1208.41" - process $proc$ls180.v:1208$3573 + attribute \src "ls180.v:1211.11-1211.41" + process $proc$ls180.v:1211$3571 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always sync init update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end - attribute \src "ls180.v:1209.5-1209.35" - process $proc$ls180.v:1209$3574 + attribute \src "ls180.v:1212.5-1212.35" + process $proc$ls180.v:1212$3572 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:1210.5-1210.36" - process $proc$ls180.v:1210$3575 + attribute \src "ls180.v:1213.5-1213.36" + process $proc$ls180.v:1213$3573 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end - attribute \src "ls180.v:1214.5-1214.40" - process $proc$ls180.v:1214$3576 + attribute \src "ls180.v:1217.5-1217.40" + process $proc$ls180.v:1217$3574 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] sync init end - attribute \src "ls180.v:1219.5-1219.48" - process $proc$ls180.v:1219$3577 + attribute \src "ls180.v:1222.5-1222.48" + process $proc$ls180.v:1222$3575 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1220.5-1220.50" - process $proc$ls180.v:1220$3578 + attribute \src "ls180.v:1223.5-1223.50" + process $proc$ls180.v:1223$3576 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1221.5-1221.51" - process $proc$ls180.v:1221$3579 + attribute \src "ls180.v:1224.5-1224.51" + process $proc$ls180.v:1224$3577 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1222.11-1222.57" - process $proc$ls180.v:1222$3580 + attribute \src "ls180.v:1225.11-1225.57" + process $proc$ls180.v:1225$3578 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1223.5-1223.52" - process $proc$ls180.v:1223$3581 + attribute \src "ls180.v:1226.5-1226.52" + process $proc$ls180.v:1226$3579 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1224.11-1224.39" - process $proc$ls180.v:1224$3582 + attribute \src "ls180.v:1227.11-1227.39" + process $proc$ls180.v:1227$3580 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end - attribute \src "ls180.v:1229.5-1229.48" - process $proc$ls180.v:1229$3583 + attribute \src "ls180.v:1232.5-1232.48" + process $proc$ls180.v:1232$3581 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1230.5-1230.50" - process $proc$ls180.v:1230$3584 + attribute \src "ls180.v:1233.5-1233.50" + process $proc$ls180.v:1233$3582 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1231.5-1231.51" - process $proc$ls180.v:1231$3585 + attribute \src "ls180.v:1234.5-1234.51" + process $proc$ls180.v:1234$3583 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1232.11-1232.57" - process $proc$ls180.v:1232$3586 + attribute \src "ls180.v:1235.11-1235.57" + process $proc$ls180.v:1235$3584 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1233.5-1233.52" - process $proc$ls180.v:1233$3587 + attribute \src "ls180.v:1236.5-1236.52" + process $proc$ls180.v:1236$3585 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1234.5-1234.38" - process $proc$ls180.v:1234$3588 + attribute \src "ls180.v:1237.5-1237.38" + process $proc$ls180.v:1237$3586 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end - attribute \src "ls180.v:1235.5-1235.38" - process $proc$ls180.v:1235$3589 + attribute \src "ls180.v:1238.5-1238.38" + process $proc$ls180.v:1238$3587 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end - attribute \src "ls180.v:1236.5-1236.37" - process $proc$ls180.v:1236$3590 + attribute \src "ls180.v:1239.5-1239.37" + process $proc$ls180.v:1239$3588 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end - attribute \src "ls180.v:1237.11-1237.51" - process $proc$ls180.v:1237$3591 + attribute \src "ls180.v:1240.11-1240.51" + process $proc$ls180.v:1240$3589 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end - attribute \src "ls180.v:1238.5-1238.32" - process $proc$ls180.v:1238$3592 + attribute \src "ls180.v:1241.5-1241.32" + process $proc$ls180.v:1241$3590 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end - attribute \src "ls180.v:1239.11-1239.39" - process $proc$ls180.v:1239$3593 + attribute \src "ls180.v:1242.11-1242.39" + process $proc$ls180.v:1242$3591 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end - attribute \src "ls180.v:1242.5-1242.49" - process $proc$ls180.v:1242$3594 + attribute \src "ls180.v:1245.5-1245.49" + process $proc$ls180.v:1245$3592 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1243.5-1243.48" - process $proc$ls180.v:1243$3595 + attribute \src "ls180.v:1246.5-1246.48" + process $proc$ls180.v:1246$3593 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1244.5-1244.55" - process $proc$ls180.v:1244$3596 + attribute \src "ls180.v:1247.5-1247.55" + process $proc$ls180.v:1247$3594 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1246.5-1246.57" - process $proc$ls180.v:1246$3597 + attribute \src "ls180.v:1249.5-1249.57" + process $proc$ls180.v:1249$3595 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1247.5-1247.58" - process $proc$ls180.v:1247$3598 + attribute \src "ls180.v:1250.5-1250.58" + process $proc$ls180.v:1250$3596 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1249.11-1249.64" - process $proc$ls180.v:1249$3599 + attribute \src "ls180.v:1252.11-1252.64" + process $proc$ls180.v:1252$3597 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1250.5-1250.59" - process $proc$ls180.v:1250$3600 + attribute \src "ls180.v:1253.5-1253.59" + process $proc$ls180.v:1253$3598 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1252.5-1252.48" - process $proc$ls180.v:1252$3601 + attribute \src "ls180.v:1255.5-1255.48" + process $proc$ls180.v:1255$3599 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1253.5-1253.50" - process $proc$ls180.v:1253$3602 + attribute \src "ls180.v:1256.5-1256.50" + process $proc$ls180.v:1256$3600 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1254.5-1254.51" - process $proc$ls180.v:1254$3603 + attribute \src "ls180.v:1257.5-1257.51" + process $proc$ls180.v:1257$3601 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1255.11-1255.57" - process $proc$ls180.v:1255$3604 + attribute \src "ls180.v:1258.11-1258.57" + process $proc$ls180.v:1258$3602 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1256.5-1256.52" - process $proc$ls180.v:1256$3605 + attribute \src "ls180.v:1259.5-1259.52" + process $proc$ls180.v:1259$3603 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1257.5-1257.38" - process $proc$ls180.v:1257$3606 + attribute \src "ls180.v:1260.5-1260.38" + process $proc$ls180.v:1260$3604 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end - attribute \src "ls180.v:1258.5-1258.38" - process $proc$ls180.v:1258$3607 + attribute \src "ls180.v:1261.5-1261.38" + process $proc$ls180.v:1261$3605 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end - attribute \src "ls180.v:1259.5-1259.37" - process $proc$ls180.v:1259$3608 + attribute \src "ls180.v:1262.5-1262.37" + process $proc$ls180.v:1262$3606 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end - attribute \src "ls180.v:1260.11-1260.53" - process $proc$ls180.v:1260$3609 + attribute \src "ls180.v:1263.11-1263.53" + process $proc$ls180.v:1263$3607 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end - attribute \src "ls180.v:1261.5-1261.40" - process $proc$ls180.v:1261$3610 + attribute \src "ls180.v:1264.5-1264.40" + process $proc$ls180.v:1264$3608 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end - attribute \src "ls180.v:1262.5-1262.40" - process $proc$ls180.v:1262$3611 + attribute \src "ls180.v:1265.5-1265.40" + process $proc$ls180.v:1265$3609 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end - attribute \src "ls180.v:1263.5-1263.39" - process $proc$ls180.v:1263$3612 + attribute \src "ls180.v:1266.5-1266.39" + process $proc$ls180.v:1266$3610 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end - attribute \src "ls180.v:1264.11-1264.53" - process $proc$ls180.v:1264$3613 + attribute \src "ls180.v:1267.11-1267.53" + process $proc$ls180.v:1267$3611 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end - attribute \src "ls180.v:1265.11-1265.55" - process $proc$ls180.v:1265$3614 + attribute \src "ls180.v:1268.11-1268.55" + process $proc$ls180.v:1268$3612 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end - attribute \src "ls180.v:1266.12-1266.48" - process $proc$ls180.v:1266$3615 + attribute \src "ls180.v:1269.12-1269.48" + process $proc$ls180.v:1269$3613 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always sync init update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end - attribute \src "ls180.v:1267.11-1267.39" - process $proc$ls180.v:1267$3616 + attribute \src "ls180.v:1270.11-1270.39" + process $proc$ls180.v:1270$3614 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end - attribute \src "ls180.v:1269.5-1269.46" - process $proc$ls180.v:1269$3617 + attribute \src "ls180.v:1272.5-1272.46" + process $proc$ls180.v:1272$3615 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1280.5-1280.53" - process $proc$ls180.v:1280$3618 + attribute \src "ls180.v:1283.5-1283.53" + process $proc$ls180.v:1283$3616 assign { } { } assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end - attribute \src "ls180.v:1285.5-1285.36" - process $proc$ls180.v:1285$3619 + attribute \src "ls180.v:1288.5-1288.36" + process $proc$ls180.v:1288$3617 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end - attribute \src "ls180.v:1288.5-1288.53" - process $proc$ls180.v:1288$3620 + attribute \src "ls180.v:1291.5-1291.53" + process $proc$ls180.v:1291$3618 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1289.5-1289.52" - process $proc$ls180.v:1289$3621 + attribute \src "ls180.v:1292.5-1292.52" + process $proc$ls180.v:1292$3619 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1293.5-1293.55" - process $proc$ls180.v:1293$3622 + attribute \src "ls180.v:1296.5-1296.55" + process $proc$ls180.v:1296$3620 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end - attribute \src "ls180.v:1294.5-1294.54" - process $proc$ls180.v:1294$3623 + attribute \src "ls180.v:1297.5-1297.54" + process $proc$ls180.v:1297$3621 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end - attribute \src "ls180.v:1295.11-1295.68" - process $proc$ls180.v:1295$3624 + attribute \src "ls180.v:1298.11-1298.68" + process $proc$ls180.v:1298$3622 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1296.11-1296.81" - process $proc$ls180.v:1296$3625 + attribute \src "ls180.v:1299.11-1299.81" + process $proc$ls180.v:1299$3623 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1297.11-1297.54" - process $proc$ls180.v:1297$3626 + attribute \src "ls180.v:1300.11-1300.54" + process $proc$ls180.v:1300$3624 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end - attribute \src "ls180.v:1299.5-1299.53" - process $proc$ls180.v:1299$3627 + attribute \src "ls180.v:1302.5-1302.53" + process $proc$ls180.v:1302$3625 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1310.5-1310.49" - process $proc$ls180.v:1310$3628 + attribute \src "ls180.v:1313.5-1313.49" + process $proc$ls180.v:1313$3626 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end - attribute \src "ls180.v:1312.5-1312.49" - process $proc$ls180.v:1312$3629 + attribute \src "ls180.v:1315.5-1315.49" + process $proc$ls180.v:1315$3627 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end - attribute \src "ls180.v:1313.5-1313.48" - process $proc$ls180.v:1313$3630 + attribute \src "ls180.v:1316.5-1316.48" + process $proc$ls180.v:1316$3628 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end - attribute \src "ls180.v:1314.11-1314.62" - process $proc$ls180.v:1314$3631 + attribute \src "ls180.v:1317.11-1317.62" + process $proc$ls180.v:1317$3629 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1315.5-1315.38" - process $proc$ls180.v:1315$3632 + attribute \src "ls180.v:1318.5-1318.38" + process $proc$ls180.v:1318$3630 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end - attribute \src "ls180.v:1320.5-1320.49" - process $proc$ls180.v:1320$3633 + attribute \src "ls180.v:1323.5-1323.49" + process $proc$ls180.v:1323$3631 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1321.5-1321.51" - process $proc$ls180.v:1321$3634 + attribute \src "ls180.v:1324.5-1324.51" + process $proc$ls180.v:1324$3632 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1322.5-1322.52" - process $proc$ls180.v:1322$3635 + attribute \src "ls180.v:1325.5-1325.52" + process $proc$ls180.v:1325$3633 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1323.11-1323.58" - process $proc$ls180.v:1323$3636 + attribute \src "ls180.v:1326.11-1326.58" + process $proc$ls180.v:1326$3634 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1324.5-1324.53" - process $proc$ls180.v:1324$3637 + attribute \src "ls180.v:1327.5-1327.53" + process $proc$ls180.v:1327$3635 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1325.5-1325.39" - process $proc$ls180.v:1325$3638 + attribute \src "ls180.v:1328.5-1328.39" + process $proc$ls180.v:1328$3636 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end - attribute \src "ls180.v:1326.5-1326.39" - process $proc$ls180.v:1326$3639 + attribute \src "ls180.v:1329.5-1329.39" + process $proc$ls180.v:1329$3637 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end - attribute \src "ls180.v:1327.5-1327.39" - process $proc$ls180.v:1327$3640 + attribute \src "ls180.v:1330.5-1330.39" + process $proc$ls180.v:1330$3638 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end - attribute \src "ls180.v:1328.5-1328.38" - process $proc$ls180.v:1328$3641 + attribute \src "ls180.v:1331.5-1331.38" + process $proc$ls180.v:1331$3639 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end - attribute \src "ls180.v:1329.11-1329.52" - process $proc$ls180.v:1329$3642 + attribute \src "ls180.v:1332.11-1332.52" + process $proc$ls180.v:1332$3640 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end - attribute \src "ls180.v:1330.5-1330.33" - process $proc$ls180.v:1330$3643 + attribute \src "ls180.v:1333.5-1333.33" + process $proc$ls180.v:1333$3641 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always sync init update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end - attribute \src "ls180.v:1331.11-1331.40" - process $proc$ls180.v:1331$3644 + attribute \src "ls180.v:1334.11-1334.40" + process $proc$ls180.v:1334$3642 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end - attribute \src "ls180.v:1332.5-1332.50" - process $proc$ls180.v:1332$3645 + attribute \src "ls180.v:1335.5-1335.50" + process $proc$ls180.v:1335$3643 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] sync init end - attribute \src "ls180.v:1334.5-1334.50" - process $proc$ls180.v:1334$3646 + attribute \src "ls180.v:1337.5-1337.50" + process $proc$ls180.v:1337$3644 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1335.5-1335.49" - process $proc$ls180.v:1335$3647 + attribute \src "ls180.v:1338.5-1338.49" + process $proc$ls180.v:1338$3645 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1336.5-1336.56" - process $proc$ls180.v:1336$3648 + attribute \src "ls180.v:1339.5-1339.56" + process $proc$ls180.v:1339$3646 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1337.5-1337.58" - process $proc$ls180.v:1337$3649 + attribute \src "ls180.v:1340.5-1340.58" + process $proc$ls180.v:1340$3647 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] sync init end - attribute \src "ls180.v:1338.5-1338.58" - process $proc$ls180.v:1338$3650 + attribute \src "ls180.v:1341.5-1341.58" + process $proc$ls180.v:1341$3648 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1339.5-1339.59" - process $proc$ls180.v:1339$3651 + attribute \src "ls180.v:1342.5-1342.59" + process $proc$ls180.v:1342$3649 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1340.11-1340.65" - process $proc$ls180.v:1340$3652 + attribute \src "ls180.v:1343.11-1343.65" + process $proc$ls180.v:1343$3650 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] sync init end - attribute \src "ls180.v:1341.11-1341.65" - process $proc$ls180.v:1341$3653 + attribute \src "ls180.v:1344.11-1344.65" + process $proc$ls180.v:1344$3651 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1342.5-1342.60" - process $proc$ls180.v:1342$3654 + attribute \src "ls180.v:1345.5-1345.60" + process $proc$ls180.v:1345$3652 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1343.5-1343.34" - process $proc$ls180.v:1343$3655 + attribute \src "ls180.v:1346.5-1346.34" + process $proc$ls180.v:1346$3653 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always sync init update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end - attribute \src "ls180.v:1344.5-1344.34" - process $proc$ls180.v:1344$3656 + attribute \src "ls180.v:1347.5-1347.34" + process $proc$ls180.v:1347$3654 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end - attribute \src "ls180.v:1345.5-1345.34" - process $proc$ls180.v:1345$3657 + attribute \src "ls180.v:1348.5-1348.34" + process $proc$ls180.v:1348$3655 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always sync init update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end - attribute \src "ls180.v:1347.5-1347.47" - process $proc$ls180.v:1347$3658 + attribute \src "ls180.v:1350.5-1350.47" + process $proc$ls180.v:1350$3656 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1358.5-1358.54" - process $proc$ls180.v:1358$3659 + attribute \src "ls180.v:1361.5-1361.54" + process $proc$ls180.v:1361$3657 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end - attribute \src "ls180.v:1363.5-1363.37" - process $proc$ls180.v:1363$3660 + attribute \src "ls180.v:1366.5-1366.37" + process $proc$ls180.v:1366$3658 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end - attribute \src "ls180.v:1366.5-1366.54" - process $proc$ls180.v:1366$3661 + attribute \src "ls180.v:1369.5-1369.54" + process $proc$ls180.v:1369$3659 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1367.5-1367.53" - process $proc$ls180.v:1367$3662 + attribute \src "ls180.v:1370.5-1370.53" + process $proc$ls180.v:1370$3660 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1371.5-1371.56" - process $proc$ls180.v:1371$3663 + attribute \src "ls180.v:1374.5-1374.56" + process $proc$ls180.v:1374$3661 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end - attribute \src "ls180.v:1372.5-1372.55" - process $proc$ls180.v:1372$3664 + attribute \src "ls180.v:1375.5-1375.55" + process $proc$ls180.v:1375$3662 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end - attribute \src "ls180.v:1373.11-1373.69" - process $proc$ls180.v:1373$3665 + attribute \src "ls180.v:1376.11-1376.69" + process $proc$ls180.v:1376$3663 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1374.11-1374.82" - process $proc$ls180.v:1374$3666 + attribute \src "ls180.v:1377.11-1377.82" + process $proc$ls180.v:1377$3664 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1375.11-1375.55" - process $proc$ls180.v:1375$3667 + attribute \src "ls180.v:1378.11-1378.55" + process $proc$ls180.v:1378$3665 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end - attribute \src "ls180.v:1377.5-1377.54" - process $proc$ls180.v:1377$3668 + attribute \src "ls180.v:1380.5-1380.54" + process $proc$ls180.v:1380$3666 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1388.5-1388.50" - process $proc$ls180.v:1388$3669 + attribute \src "ls180.v:1391.5-1391.50" + process $proc$ls180.v:1391$3667 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end - attribute \src "ls180.v:1390.5-1390.50" - process $proc$ls180.v:1390$3670 + attribute \src "ls180.v:1393.5-1393.50" + process $proc$ls180.v:1393$3668 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end - attribute \src "ls180.v:1391.5-1391.49" - process $proc$ls180.v:1391$3671 + attribute \src "ls180.v:1394.5-1394.49" + process $proc$ls180.v:1394$3669 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end - attribute \src "ls180.v:1392.11-1392.63" - process $proc$ls180.v:1392$3672 + attribute \src "ls180.v:1395.11-1395.63" + process $proc$ls180.v:1395$3670 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1393.5-1393.39" - process $proc$ls180.v:1393$3673 + attribute \src "ls180.v:1396.5-1396.39" + process $proc$ls180.v:1396$3671 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end - attribute \src "ls180.v:1396.5-1396.50" - process $proc$ls180.v:1396$3674 + attribute \src "ls180.v:1399.5-1399.50" + process $proc$ls180.v:1399$3672 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1397.5-1397.49" - process $proc$ls180.v:1397$3675 + attribute \src "ls180.v:1400.5-1400.49" + process $proc$ls180.v:1400$3673 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1398.5-1398.56" - process $proc$ls180.v:1398$3676 + attribute \src "ls180.v:1401.5-1401.56" + process $proc$ls180.v:1401$3674 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1400.5-1400.58" - process $proc$ls180.v:1400$3677 + attribute \src "ls180.v:1403.5-1403.58" + process $proc$ls180.v:1403$3675 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1401.5-1401.59" - process $proc$ls180.v:1401$3678 + attribute \src "ls180.v:1404.5-1404.59" + process $proc$ls180.v:1404$3676 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1403.11-1403.65" - process $proc$ls180.v:1403$3679 + attribute \src "ls180.v:1406.11-1406.65" + process $proc$ls180.v:1406$3677 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1404.5-1404.60" - process $proc$ls180.v:1404$3680 + attribute \src "ls180.v:1407.5-1407.60" + process $proc$ls180.v:1407$3678 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1406.5-1406.49" - process $proc$ls180.v:1406$3681 + attribute \src "ls180.v:1409.5-1409.49" + process $proc$ls180.v:1409$3679 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1407.5-1407.51" - process $proc$ls180.v:1407$3682 + attribute \src "ls180.v:1410.5-1410.51" + process $proc$ls180.v:1410$3680 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1408.5-1408.52" - process $proc$ls180.v:1408$3683 + attribute \src "ls180.v:1411.5-1411.52" + process $proc$ls180.v:1411$3681 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1409.11-1409.58" - process $proc$ls180.v:1409$3684 + attribute \src "ls180.v:1412.11-1412.58" + process $proc$ls180.v:1412$3682 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1410.5-1410.53" - process $proc$ls180.v:1410$3685 + attribute \src "ls180.v:1413.5-1413.53" + process $proc$ls180.v:1413$3683 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1411.5-1411.39" - process $proc$ls180.v:1411$3686 + attribute \src "ls180.v:1414.5-1414.39" + process $proc$ls180.v:1414$3684 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end - attribute \src "ls180.v:1412.5-1412.39" - process $proc$ls180.v:1412$3687 + attribute \src "ls180.v:1415.5-1415.39" + process $proc$ls180.v:1415$3685 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end - attribute \src "ls180.v:1413.5-1413.38" - process $proc$ls180.v:1413$3688 + attribute \src "ls180.v:1416.5-1416.38" + process $proc$ls180.v:1416$3686 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end - attribute \src "ls180.v:1414.11-1414.61" - process $proc$ls180.v:1414$3689 + attribute \src "ls180.v:1417.11-1417.61" + process $proc$ls180.v:1417$3687 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end - attribute \src "ls180.v:1415.5-1415.41" - process $proc$ls180.v:1415$3690 + attribute \src "ls180.v:1418.5-1418.41" + process $proc$ls180.v:1418$3688 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end - attribute \src "ls180.v:1416.5-1416.41" - process $proc$ls180.v:1416$3691 + attribute \src "ls180.v:1419.5-1419.41" + process $proc$ls180.v:1419$3689 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end - attribute \src "ls180.v:1417.5-1417.41" - process $proc$ls180.v:1417$3692 + attribute \src "ls180.v:1420.5-1420.41" + process $proc$ls180.v:1420$3690 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] sync init end - attribute \src "ls180.v:1418.5-1418.40" - process $proc$ls180.v:1418$3693 + attribute \src "ls180.v:1421.5-1421.40" + process $proc$ls180.v:1421$3691 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end - attribute \src "ls180.v:1419.11-1419.54" - process $proc$ls180.v:1419$3694 + attribute \src "ls180.v:1422.11-1422.54" + process $proc$ls180.v:1422$3692 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end - attribute \src "ls180.v:1420.11-1420.56" - process $proc$ls180.v:1420$3695 + attribute \src "ls180.v:1423.11-1423.56" + process $proc$ls180.v:1423$3693 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end - attribute \src "ls180.v:1421.5-1421.33" - process $proc$ls180.v:1421$3696 + attribute \src "ls180.v:1424.5-1424.33" + process $proc$ls180.v:1424$3694 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always sync init update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end - attribute \src "ls180.v:1422.12-1422.49" - process $proc$ls180.v:1422$3697 + attribute \src "ls180.v:1425.12-1425.49" + process $proc$ls180.v:1425$3695 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always sync init update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end - attribute \src "ls180.v:1423.11-1423.41" - process $proc$ls180.v:1423$3698 + attribute \src "ls180.v:1426.11-1426.41" + process $proc$ls180.v:1426$3696 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end - attribute \src "ls180.v:1425.5-1425.48" - process $proc$ls180.v:1425$3699 + attribute \src "ls180.v:1428.5-1428.48" + process $proc$ls180.v:1428$3697 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1436.5-1436.55" - process $proc$ls180.v:1436$3700 + attribute \src "ls180.v:1439.5-1439.55" + process $proc$ls180.v:1439$3698 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end - attribute \src "ls180.v:1441.5-1441.38" - process $proc$ls180.v:1441$3701 + attribute \src "ls180.v:1444.5-1444.38" + process $proc$ls180.v:1444$3699 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end - attribute \src "ls180.v:1444.5-1444.55" - process $proc$ls180.v:1444$3702 + attribute \src "ls180.v:1447.5-1447.55" + process $proc$ls180.v:1447$3700 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1445.5-1445.54" - process $proc$ls180.v:1445$3703 + attribute \src "ls180.v:1448.5-1448.54" + process $proc$ls180.v:1448$3701 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1449.5-1449.57" - process $proc$ls180.v:1449$3704 + attribute \src "ls180.v:1452.5-1452.57" + process $proc$ls180.v:1452$3702 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end - attribute \src "ls180.v:1450.5-1450.56" - process $proc$ls180.v:1450$3705 + attribute \src "ls180.v:1453.5-1453.56" + process $proc$ls180.v:1453$3703 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end - attribute \src "ls180.v:1451.11-1451.70" - process $proc$ls180.v:1451$3706 + attribute \src "ls180.v:1454.11-1454.70" + process $proc$ls180.v:1454$3704 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1452.11-1452.83" - process $proc$ls180.v:1452$3707 + attribute \src "ls180.v:1455.11-1455.83" + process $proc$ls180.v:1455$3705 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end - attribute \src "ls180.v:1453.5-1453.50" - process $proc$ls180.v:1453$3708 + attribute \src "ls180.v:1456.5-1456.50" + process $proc$ls180.v:1456$3706 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end - attribute \src "ls180.v:1455.5-1455.55" - process $proc$ls180.v:1455$3709 + attribute \src "ls180.v:1458.5-1458.55" + process $proc$ls180.v:1458$3707 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end - attribute \src "ls180.v:1466.5-1466.51" - process $proc$ls180.v:1466$3710 + attribute \src "ls180.v:1469.5-1469.51" + process $proc$ls180.v:1469$3708 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end - attribute \src "ls180.v:1468.5-1468.51" - process $proc$ls180.v:1468$3711 + attribute \src "ls180.v:1471.5-1471.51" + process $proc$ls180.v:1471$3709 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end - attribute \src "ls180.v:1469.5-1469.50" - process $proc$ls180.v:1469$3712 + attribute \src "ls180.v:1472.5-1472.50" + process $proc$ls180.v:1472$3710 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end - attribute \src "ls180.v:1470.11-1470.64" - process $proc$ls180.v:1470$3713 + attribute \src "ls180.v:1473.11-1473.64" + process $proc$ls180.v:1473$3711 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1471.5-1471.40" - process $proc$ls180.v:1471$3714 + attribute \src "ls180.v:1474.5-1474.40" + process $proc$ls180.v:1474$3712 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end - attribute \src "ls180.v:1473.5-1473.35" - process $proc$ls180.v:1473$3715 + attribute \src "ls180.v:1476.5-1476.35" + process $proc$ls180.v:1476$3713 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always sync init update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end - attribute \src "ls180.v:1476.11-1476.42" - process $proc$ls180.v:1476$3716 + attribute \src "ls180.v:1479.11-1479.42" + process $proc$ls180.v:1479$3714 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always sync init update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:1489.12-1489.52" - process $proc$ls180.v:1489$3717 + attribute \src "ls180.v:1492.12-1492.52" + process $proc$ls180.v:1492$3715 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end - attribute \src "ls180.v:1490.5-1490.39" - process $proc$ls180.v:1490$3718 + attribute \src "ls180.v:1493.5-1493.39" + process $proc$ls180.v:1493$3716 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end - attribute \src "ls180.v:1491.12-1491.51" - process $proc$ls180.v:1491$3719 + attribute \src "ls180.v:1494.12-1494.51" + process $proc$ls180.v:1494$3717 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end - attribute \src "ls180.v:1492.5-1492.38" - process $proc$ls180.v:1492$3720 + attribute \src "ls180.v:1495.5-1495.38" + process $proc$ls180.v:1495$3718 assign { } { } assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end - attribute \src "ls180.v:1496.5-1496.34" - process $proc$ls180.v:1496$3721 + attribute \src "ls180.v:1499.5-1499.34" + process $proc$ls180.v:1499$3719 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] sync init end - attribute \src "ls180.v:1497.13-1497.53" - process $proc$ls180.v:1497$3722 + attribute \src "ls180.v:1500.13-1500.53" + process $proc$ls180.v:1500$3720 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end - attribute \src "ls180.v:1503.11-1503.51" - process $proc$ls180.v:1503$3723 + attribute \src "ls180.v:1506.11-1506.51" + process $proc$ls180.v:1506$3721 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always sync init update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end - attribute \src "ls180.v:1504.5-1504.39" - process $proc$ls180.v:1504$3724 + attribute \src "ls180.v:1507.5-1507.39" + process $proc$ls180.v:1507$3722 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always sync init update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end - attribute \src "ls180.v:1505.12-1505.51" - process $proc$ls180.v:1505$3725 + attribute \src "ls180.v:1508.12-1508.51" + process $proc$ls180.v:1508$3723 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always sync init update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end - attribute \src "ls180.v:1506.5-1506.38" - process $proc$ls180.v:1506$3726 + attribute \src "ls180.v:1509.5-1509.38" + process $proc$ls180.v:1509$3724 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always sync init update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end - attribute \src "ls180.v:1507.11-1507.51" - process $proc$ls180.v:1507$3727 + attribute \src "ls180.v:1510.11-1510.51" + process $proc$ls180.v:1510$3725 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end - attribute \src "ls180.v:1549.11-1549.47" - process $proc$ls180.v:1549$3728 + attribute \src "ls180.v:1552.11-1552.47" + process $proc$ls180.v:1552$3726 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:1553.5-1553.49" - process $proc$ls180.v:1553$3729 + attribute \src "ls180.v:1556.5-1556.49" + process $proc$ls180.v:1556$3727 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end - attribute \src "ls180.v:1557.5-1557.51" - process $proc$ls180.v:1557$3730 + attribute \src "ls180.v:1560.5-1560.51" + process $proc$ls180.v:1560$3728 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end - attribute \src "ls180.v:1558.5-1558.51" - process $proc$ls180.v:1558$3731 + attribute \src "ls180.v:1561.5-1561.51" + process $proc$ls180.v:1561$3729 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end - attribute \src "ls180.v:1559.5-1559.51" - process $proc$ls180.v:1559$3732 + attribute \src "ls180.v:1562.5-1562.51" + process $proc$ls180.v:1562$3730 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] sync init end - attribute \src "ls180.v:1560.5-1560.50" - process $proc$ls180.v:1560$3733 + attribute \src "ls180.v:1563.5-1563.50" + process $proc$ls180.v:1563$3731 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end - attribute \src "ls180.v:1561.11-1561.64" - process $proc$ls180.v:1561$3734 + attribute \src "ls180.v:1564.11-1564.64" + process $proc$ls180.v:1564$3732 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end - attribute \src "ls180.v:1562.11-1562.48" - process $proc$ls180.v:1562$3735 + attribute \src "ls180.v:1565.11-1565.48" + process $proc$ls180.v:1565$3733 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end - attribute \src "ls180.v:1563.12-1563.59" - process $proc$ls180.v:1563$3736 + attribute \src "ls180.v:1566.12-1566.59" + process $proc$ls180.v:1566$3734 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1567.12-1567.55" - process $proc$ls180.v:1567$3737 + attribute \src "ls180.v:1570.12-1570.55" + process $proc$ls180.v:1570$3735 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:1570.12-1570.59" - process $proc$ls180.v:1570$3738 + attribute \src "ls180.v:1573.12-1573.59" + process $proc$ls180.v:1573$3736 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1574.12-1574.55" - process $proc$ls180.v:1574$3739 + attribute \src "ls180.v:1577.12-1577.55" + process $proc$ls180.v:1577$3737 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:1577.12-1577.59" - process $proc$ls180.v:1577$3740 + attribute \src "ls180.v:1580.12-1580.59" + process $proc$ls180.v:1580$3738 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1581.12-1581.55" - process $proc$ls180.v:1581$3741 + attribute \src "ls180.v:1584.12-1584.55" + process $proc$ls180.v:1584$3739 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:1584.12-1584.59" - process $proc$ls180.v:1584$3742 + attribute \src "ls180.v:1587.12-1587.59" + process $proc$ls180.v:1587$3740 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1588.12-1588.55" - process $proc$ls180.v:1588$3743 + attribute \src "ls180.v:1591.12-1591.55" + process $proc$ls180.v:1591$3741 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:1591.12-1591.54" - process $proc$ls180.v:1591$3744 + attribute \src "ls180.v:1594.12-1594.54" + process $proc$ls180.v:1594$3742 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end - attribute \src "ls180.v:1592.12-1592.54" - process $proc$ls180.v:1592$3745 + attribute \src "ls180.v:1595.12-1595.54" + process $proc$ls180.v:1595$3743 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end - attribute \src "ls180.v:1593.12-1593.54" - process $proc$ls180.v:1593$3746 + attribute \src "ls180.v:1596.12-1596.54" + process $proc$ls180.v:1596$3744 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end - attribute \src "ls180.v:1594.12-1594.54" - process $proc$ls180.v:1594$3747 + attribute \src "ls180.v:1597.12-1597.54" + process $proc$ls180.v:1597$3745 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end - attribute \src "ls180.v:1595.5-1595.48" - process $proc$ls180.v:1595$3748 + attribute \src "ls180.v:1598.5-1598.48" + process $proc$ls180.v:1598$3746 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end - attribute \src "ls180.v:1596.5-1596.48" - process $proc$ls180.v:1596$3749 + attribute \src "ls180.v:1599.5-1599.48" + process $proc$ls180.v:1599$3747 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:1597.5-1597.48" - process $proc$ls180.v:1597$3750 + attribute \src "ls180.v:1600.5-1600.48" + process $proc$ls180.v:1600$3748 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end - attribute \src "ls180.v:1598.5-1598.47" - process $proc$ls180.v:1598$3751 + attribute \src "ls180.v:1601.5-1601.47" + process $proc$ls180.v:1601$3749 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end - attribute \src "ls180.v:1599.11-1599.61" - process $proc$ls180.v:1599$3752 + attribute \src "ls180.v:1602.11-1602.61" + process $proc$ls180.v:1602$3750 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end - attribute \src "ls180.v:1600.5-1600.50" - process $proc$ls180.v:1600$3753 + attribute \src "ls180.v:1603.5-1603.50" + process $proc$ls180.v:1603$3751 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:1602.5-1602.50" - process $proc$ls180.v:1602$3754 + attribute \src "ls180.v:1605.5-1605.50" + process $proc$ls180.v:1605$3752 assign { } { } assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] sync init end - attribute \src "ls180.v:1605.11-1605.47" - process $proc$ls180.v:1605$3755 + attribute \src "ls180.v:1608.11-1608.47" + process $proc$ls180.v:1608$3753 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end - attribute \src "ls180.v:1606.11-1606.47" - process $proc$ls180.v:1606$3756 + attribute \src "ls180.v:1609.11-1609.47" + process $proc$ls180.v:1609$3754 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always sync init update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end - attribute \src "ls180.v:1607.12-1607.58" - process $proc$ls180.v:1607$3757 + attribute \src "ls180.v:1610.12-1610.58" + process $proc$ls180.v:1610$3755 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1611.12-1611.54" - process $proc$ls180.v:1611$3758 + attribute \src "ls180.v:1614.12-1614.54" + process $proc$ls180.v:1614$3756 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:1612.5-1612.46" - process $proc$ls180.v:1612$3759 + attribute \src "ls180.v:1615.5-1615.46" + process $proc$ls180.v:1615$3757 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:1614.12-1614.58" - process $proc$ls180.v:1614$3760 + attribute \src "ls180.v:1617.12-1617.58" + process $proc$ls180.v:1617$3758 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1618.12-1618.54" - process $proc$ls180.v:1618$3761 + attribute \src "ls180.v:1621.12-1621.54" + process $proc$ls180.v:1621$3759 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:1619.5-1619.46" - process $proc$ls180.v:1619$3762 + attribute \src "ls180.v:1622.5-1622.46" + process $proc$ls180.v:1622$3760 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:1621.12-1621.58" - process $proc$ls180.v:1621$3763 + attribute \src "ls180.v:1624.12-1624.58" + process $proc$ls180.v:1624$3761 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1625.12-1625.54" - process $proc$ls180.v:1625$3764 + attribute \src "ls180.v:1628.12-1628.54" + process $proc$ls180.v:1628$3762 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:1626.5-1626.46" - process $proc$ls180.v:1626$3765 + attribute \src "ls180.v:1629.5-1629.46" + process $proc$ls180.v:1629$3763 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:1628.12-1628.58" - process $proc$ls180.v:1628$3766 + attribute \src "ls180.v:1631.12-1631.58" + process $proc$ls180.v:1631$3764 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1632.12-1632.54" - process $proc$ls180.v:1632$3767 + attribute \src "ls180.v:1635.12-1635.54" + process $proc$ls180.v:1635$3765 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:1633.5-1633.46" - process $proc$ls180.v:1633$3768 + attribute \src "ls180.v:1636.5-1636.46" + process $proc$ls180.v:1636$3766 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:1635.12-1635.53" - process $proc$ls180.v:1635$3769 + attribute \src "ls180.v:1638.12-1638.53" + process $proc$ls180.v:1638$3767 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end - attribute \src "ls180.v:1636.12-1636.53" - process $proc$ls180.v:1636$3770 + attribute \src "ls180.v:1639.12-1639.53" + process $proc$ls180.v:1639$3768 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end - attribute \src "ls180.v:1637.12-1637.53" - process $proc$ls180.v:1637$3771 + attribute \src "ls180.v:1640.12-1640.53" + process $proc$ls180.v:1640$3769 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end - attribute \src "ls180.v:1638.12-1638.53" - process $proc$ls180.v:1638$3772 + attribute \src "ls180.v:1641.12-1641.53" + process $proc$ls180.v:1641$3770 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end - attribute \src "ls180.v:1639.5-1639.43" - process $proc$ls180.v:1639$3773 + attribute \src "ls180.v:1642.5-1642.43" + process $proc$ls180.v:1642$3771 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:1640.12-1640.51" - process $proc$ls180.v:1640$3774 + attribute \src "ls180.v:1643.12-1643.51" + process $proc$ls180.v:1643$3772 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end - attribute \src "ls180.v:1641.12-1641.51" - process $proc$ls180.v:1641$3775 + attribute \src "ls180.v:1644.12-1644.51" + process $proc$ls180.v:1644$3773 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end - attribute \src "ls180.v:1642.12-1642.51" - process $proc$ls180.v:1642$3776 + attribute \src "ls180.v:1645.12-1645.51" + process $proc$ls180.v:1645$3774 assign { } { } assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end - attribute \src "ls180.v:1643.12-1643.51" - process $proc$ls180.v:1643$3777 + attribute \src "ls180.v:1646.12-1646.51" + process $proc$ls180.v:1646$3775 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end - attribute \src "ls180.v:1645.11-1645.39" - process $proc$ls180.v:1645$3778 + attribute \src "ls180.v:1648.11-1648.39" + process $proc$ls180.v:1648$3776 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end - attribute \src "ls180.v:1646.5-1646.32" - process $proc$ls180.v:1646$3779 + attribute \src "ls180.v:1649.5-1649.32" + process $proc$ls180.v:1649$3777 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end - attribute \src "ls180.v:1647.5-1647.33" - process $proc$ls180.v:1647$3780 + attribute \src "ls180.v:1650.5-1650.33" + process $proc$ls180.v:1650$3778 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end - attribute \src "ls180.v:1648.5-1648.35" - process $proc$ls180.v:1648$3781 + attribute \src "ls180.v:1651.5-1651.35" + process $proc$ls180.v:1651$3779 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end - attribute \src "ls180.v:1650.12-1650.42" - process $proc$ls180.v:1650$3782 + attribute \src "ls180.v:1653.12-1653.42" + process $proc$ls180.v:1653$3780 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always sync init update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end - attribute \src "ls180.v:1651.5-1651.33" - process $proc$ls180.v:1651$3783 + attribute \src "ls180.v:1654.5-1654.33" + process $proc$ls180.v:1654$3781 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always sync init update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end - attribute \src "ls180.v:1652.5-1652.34" - process $proc$ls180.v:1652$3784 + attribute \src "ls180.v:1655.5-1655.34" + process $proc$ls180.v:1655$3782 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always sync init update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end - attribute \src "ls180.v:1653.5-1653.36" - process $proc$ls180.v:1653$3785 + attribute \src "ls180.v:1656.5-1656.36" + process $proc$ls180.v:1656$3783 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end - attribute \src "ls180.v:1662.11-1662.41" - process $proc$ls180.v:1662$3786 + attribute \src "ls180.v:1665.11-1665.41" + process $proc$ls180.v:1665$3784 assign { } { } assign $0\main_interface0_bus_cti[2:0] 3'000 sync always update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] sync init end - attribute \src "ls180.v:1663.11-1663.41" - process $proc$ls180.v:1663$3787 + attribute \src "ls180.v:1666.11-1666.41" + process $proc$ls180.v:1666$3785 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] sync init end - attribute \src "ls180.v:1686.11-1686.45" - process $proc$ls180.v:1686$3788 + attribute \src "ls180.v:1689.11-1689.45" + process $proc$ls180.v:1689$3786 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always sync init update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end - attribute \src "ls180.v:1687.5-1687.41" - process $proc$ls180.v:1687$3789 + attribute \src "ls180.v:1690.5-1690.41" + process $proc$ls180.v:1690$3787 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1688.11-1688.47" - process $proc$ls180.v:1688$3790 + attribute \src "ls180.v:1691.11-1691.47" + process $proc$ls180.v:1691$3788 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end - attribute \src "ls180.v:1689.11-1689.47" - process $proc$ls180.v:1689$3791 + attribute \src "ls180.v:1692.11-1692.47" + process $proc$ls180.v:1692$3789 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end - attribute \src "ls180.v:1690.11-1690.50" - process $proc$ls180.v:1690$3792 + attribute \src "ls180.v:1693.11-1693.50" + process $proc$ls180.v:1693$3790 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:1710.5-1710.51" - process $proc$ls180.v:1710$3793 + attribute \src "ls180.v:1713.5-1713.51" + process $proc$ls180.v:1713$3791 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end - attribute \src "ls180.v:1711.5-1711.50" - process $proc$ls180.v:1711$3794 + attribute \src "ls180.v:1714.5-1714.50" + process $proc$ls180.v:1714$3792 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end - attribute \src "ls180.v:1712.12-1712.66" - process $proc$ls180.v:1712$3795 + attribute \src "ls180.v:1715.12-1715.66" + process $proc$ls180.v:1715$3793 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] end - attribute \src "ls180.v:1713.11-1713.77" - process $proc$ls180.v:1713$3796 + attribute \src "ls180.v:1716.11-1716.77" + process $proc$ls180.v:1716$3794 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1714.11-1714.50" - process $proc$ls180.v:1714$3797 + attribute \src "ls180.v:1717.11-1717.50" + process $proc$ls180.v:1717$3795 assign { } { } assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 sync always sync init update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] end - attribute \src "ls180.v:1716.5-1716.49" - process $proc$ls180.v:1716$3798 + attribute \src "ls180.v:1719.5-1719.49" + process $proc$ls180.v:1719$3796 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:172.5-172.69" + attribute \src "ls180.v:172.5-172.72" process $proc$ls180.v:172$3150 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] sync init end - attribute \src "ls180.v:1722.5-1722.45" - process $proc$ls180.v:1722$3799 + attribute \src "ls180.v:1725.5-1725.45" + process $proc$ls180.v:1725$3797 assign { } { } assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always sync init update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:1724.12-1724.62" - process $proc$ls180.v:1724$3800 + attribute \src "ls180.v:1727.12-1727.62" + process $proc$ls180.v:1727$3798 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end - attribute \src "ls180.v:1725.12-1725.60" - process $proc$ls180.v:1725$3801 + attribute \src "ls180.v:1728.12-1728.60" + process $proc$ls180.v:1728$3799 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] end - attribute \src "ls180.v:1727.5-1727.57" - process $proc$ls180.v:1727$3802 + attribute \src "ls180.v:1730.5-1730.57" + process $proc$ls180.v:1730$3800 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end - attribute \src "ls180.v:1731.12-1731.67" - process $proc$ls180.v:1731$3803 + attribute \src "ls180.v:1734.12-1734.67" + process $proc$ls180.v:1734$3801 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end - attribute \src "ls180.v:1732.5-1732.54" - process $proc$ls180.v:1732$3804 + attribute \src "ls180.v:1735.5-1735.54" + process $proc$ls180.v:1735$3802 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end - attribute \src "ls180.v:1733.12-1733.69" - process $proc$ls180.v:1733$3805 + attribute \src "ls180.v:1736.12-1736.69" + process $proc$ls180.v:1736$3803 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end - attribute \src "ls180.v:1734.5-1734.56" - process $proc$ls180.v:1734$3806 + attribute \src "ls180.v:1737.5-1737.56" + process $proc$ls180.v:1737$3804 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end - attribute \src "ls180.v:1735.5-1735.61" - process $proc$ls180.v:1735$3807 + attribute \src "ls180.v:1738.5-1738.61" + process $proc$ls180.v:1738$3805 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end - attribute \src "ls180.v:1736.5-1736.56" - process $proc$ls180.v:1736$3808 + attribute \src "ls180.v:1739.5-1739.56" + process $proc$ls180.v:1739$3806 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end - attribute \src "ls180.v:1737.5-1737.53" - process $proc$ls180.v:1737$3809 + attribute \src "ls180.v:1740.5-1740.53" + process $proc$ls180.v:1740$3807 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end - attribute \src "ls180.v:1739.5-1739.59" - process $proc$ls180.v:1739$3810 + attribute \src "ls180.v:1742.5-1742.59" + process $proc$ls180.v:1742$3808 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end - attribute \src "ls180.v:1740.5-1740.54" - process $proc$ls180.v:1740$3811 + attribute \src "ls180.v:1743.5-1743.54" + process $proc$ls180.v:1743$3809 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end - attribute \src "ls180.v:1742.12-1742.61" - process $proc$ls180.v:1742$3812 + attribute \src "ls180.v:1745.12-1745.61" + process $proc$ls180.v:1745$3810 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end - attribute \src "ls180.v:1745.12-1745.43" - process $proc$ls180.v:1745$3813 + attribute \src "ls180.v:1748.12-1748.43" + process $proc$ls180.v:1748$3811 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always sync init update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end - attribute \src "ls180.v:1746.12-1746.45" - process $proc$ls180.v:1746$3814 + attribute \src "ls180.v:1749.12-1749.45" + process $proc$ls180.v:1749$3812 assign { } { } assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] sync init end - attribute \src "ls180.v:1748.11-1748.41" - process $proc$ls180.v:1748$3815 + attribute \src "ls180.v:175.11-175.79" + process $proc$ls180.v:175$3151 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + sync init + end + attribute \src "ls180.v:1751.11-1751.41" + process $proc$ls180.v:1751$3813 assign { } { } assign $1\main_interface1_bus_sel[7:0] 8'00000000 sync always sync init update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] end - attribute \src "ls180.v:1749.5-1749.35" - process $proc$ls180.v:1749$3816 + attribute \src "ls180.v:1752.5-1752.35" + process $proc$ls180.v:1752$3814 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always sync init update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end - attribute \src "ls180.v:1750.5-1750.35" - process $proc$ls180.v:1750$3817 + attribute \src "ls180.v:1753.5-1753.35" + process $proc$ls180.v:1753$3815 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always sync init update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end - attribute \src "ls180.v:1752.5-1752.34" - process $proc$ls180.v:1752$3818 + attribute \src "ls180.v:1755.5-1755.34" + process $proc$ls180.v:1755$3816 assign { } { } assign $1\main_interface1_bus_we[0:0] 1'0 sync always sync init update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end - attribute \src "ls180.v:1753.11-1753.41" - process $proc$ls180.v:1753$3819 + attribute \src "ls180.v:1756.11-1756.41" + process $proc$ls180.v:1756$3817 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] sync init end - attribute \src "ls180.v:1754.11-1754.41" - process $proc$ls180.v:1754$3820 + attribute \src "ls180.v:1757.11-1757.41" + process $proc$ls180.v:1757$3818 assign { } { } assign $0\main_interface1_bus_bte[1:0] 2'00 sync always update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end - attribute \src "ls180.v:176.5-176.72" - process $proc$ls180.v:176$3151 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:1761.5-1761.43" - process $proc$ls180.v:1761$3821 + attribute \src "ls180.v:1764.5-1764.43" + process $proc$ls180.v:1764$3819 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end - attribute \src "ls180.v:1762.5-1762.43" - process $proc$ls180.v:1762$3822 + attribute \src "ls180.v:1765.5-1765.43" + process $proc$ls180.v:1765$3820 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end - attribute \src "ls180.v:1763.5-1763.42" - process $proc$ls180.v:1763$3823 + attribute \src "ls180.v:1766.5-1766.42" + process $proc$ls180.v:1766$3821 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end - attribute \src "ls180.v:1764.12-1764.61" - process $proc$ls180.v:1764$3824 + attribute \src "ls180.v:1767.12-1767.61" + process $proc$ls180.v:1767$3822 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always sync init update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end - attribute \src "ls180.v:1765.5-1765.45" - process $proc$ls180.v:1765$3825 + attribute \src "ls180.v:1768.5-1768.45" + process $proc$ls180.v:1768$3823 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end - attribute \src "ls180.v:1767.5-1767.45" - process $proc$ls180.v:1767$3826 + attribute \src "ls180.v:1770.5-1770.45" + process $proc$ls180.v:1770$3824 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] sync init end - attribute \src "ls180.v:1768.5-1768.44" - process $proc$ls180.v:1768$3827 + attribute \src "ls180.v:1771.5-1771.44" + process $proc$ls180.v:1771$3825 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end - attribute \src "ls180.v:1769.12-1769.60" - process $proc$ls180.v:1769$3828 + attribute \src "ls180.v:1772.12-1772.60" + process $proc$ls180.v:1772$3826 assign { } { } assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] end - attribute \src "ls180.v:1770.12-1770.45" - process $proc$ls180.v:1770$3829 + attribute \src "ls180.v:1773.12-1773.45" + process $proc$ls180.v:1773$3827 assign { } { } assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] end - attribute \src "ls180.v:1771.12-1771.53" - process $proc$ls180.v:1771$3830 + attribute \src "ls180.v:1774.12-1774.53" + process $proc$ls180.v:1774$3828 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end - attribute \src "ls180.v:1772.5-1772.40" - process $proc$ls180.v:1772$3831 + attribute \src "ls180.v:1775.5-1775.40" + process $proc$ls180.v:1775$3829 assign { } { } assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end - attribute \src "ls180.v:1773.12-1773.55" - process $proc$ls180.v:1773$3832 + attribute \src "ls180.v:1776.12-1776.55" + process $proc$ls180.v:1776$3830 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always sync init update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end - attribute \src "ls180.v:1774.5-1774.42" - process $proc$ls180.v:1774$3833 + attribute \src "ls180.v:1777.5-1777.42" + process $proc$ls180.v:1777$3831 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end - attribute \src "ls180.v:1775.5-1775.47" - process $proc$ls180.v:1775$3834 + attribute \src "ls180.v:1778.5-1778.47" + process $proc$ls180.v:1778$3832 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end - attribute \src "ls180.v:1776.5-1776.42" - process $proc$ls180.v:1776$3835 + attribute \src "ls180.v:1779.5-1779.42" + process $proc$ls180.v:1779$3833 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end - attribute \src "ls180.v:1777.5-1777.44" - process $proc$ls180.v:1777$3836 + attribute \src "ls180.v:1780.5-1780.44" + process $proc$ls180.v:1780$3834 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end - attribute \src "ls180.v:1779.5-1779.45" - process $proc$ls180.v:1779$3837 + attribute \src "ls180.v:1782.5-1782.45" + process $proc$ls180.v:1782$3835 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end - attribute \src "ls180.v:1780.5-1780.40" - process $proc$ls180.v:1780$3838 + attribute \src "ls180.v:1783.5-1783.40" + process $proc$ls180.v:1783$3836 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end - attribute \src "ls180.v:1784.12-1784.47" - process $proc$ls180.v:1784$3839 + attribute \src "ls180.v:1787.12-1787.47" + process $proc$ls180.v:1787$3837 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end - attribute \src "ls180.v:179.12-179.74" + attribute \src "ls180.v:179.5-179.69" process $proc$ls180.v:179$3152 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] sync init end - attribute \src "ls180.v:1796.11-1796.64" - process $proc$ls180.v:1796$3840 + attribute \src "ls180.v:1799.11-1799.64" + process $proc$ls180.v:1799$3838 assign { } { } assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1798.11-1798.48" - process $proc$ls180.v:1798$3841 + attribute \src "ls180.v:1801.11-1801.48" + process $proc$ls180.v:1801$3839 assign { } { } assign $1\main_sdmem2block_converter_mux[2:0] 3'000 sync always sync init update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:1822.11-1822.45" - process $proc$ls180.v:1822$3842 + attribute \src "ls180.v:182.12-182.74" + process $proc$ls180.v:182$3153 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end + attribute \src "ls180.v:1825.11-1825.45" + process $proc$ls180.v:1825$3840 assign { } { } assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always sync init update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end - attribute \src "ls180.v:1823.5-1823.41" - process $proc$ls180.v:1823$3843 + attribute \src "ls180.v:1826.5-1826.41" + process $proc$ls180.v:1826$3841 assign { } { } assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1824.11-1824.47" - process $proc$ls180.v:1824$3844 + attribute \src "ls180.v:1827.11-1827.47" + process $proc$ls180.v:1827$3842 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end - attribute \src "ls180.v:1825.11-1825.47" - process $proc$ls180.v:1825$3845 + attribute \src "ls180.v:1828.11-1828.47" + process $proc$ls180.v:1828$3843 assign { } { } assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end - attribute \src "ls180.v:1826.11-1826.50" - process $proc$ls180.v:1826$3846 + attribute \src "ls180.v:1829.11-1829.50" + process $proc$ls180.v:1829$3844 assign { } { } assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:183.12-183.78" - process $proc$ls180.v:183$3153 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - sync init - end - attribute \src "ls180.v:1839.5-1839.36" - process $proc$ls180.v:1839$3847 + attribute \src "ls180.v:1842.5-1842.36" + process $proc$ls180.v:1842$3845 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always sync init update \builder_converter0_state $1\builder_converter0_state[0:0] end - attribute \src "ls180.v:1840.5-1840.41" - process $proc$ls180.v:1840$3848 + attribute \src "ls180.v:1843.5-1843.41" + process $proc$ls180.v:1843$3846 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always sync init update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end - attribute \src "ls180.v:1841.5-1841.57" - process $proc$ls180.v:1841$3849 + attribute \src "ls180.v:1844.5-1844.57" + process $proc$ls180.v:1844$3847 assign { } { } assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 sync always sync init update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] end - attribute \src "ls180.v:1842.5-1842.60" - process $proc$ls180.v:1842$3850 + attribute \src "ls180.v:1845.5-1845.60" + process $proc$ls180.v:1845$3848 assign { } { } assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always sync init update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:1843.5-1843.36" - process $proc$ls180.v:1843$3851 + attribute \src "ls180.v:1846.5-1846.36" + process $proc$ls180.v:1846$3849 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always sync init update \builder_converter1_state $1\builder_converter1_state[0:0] end - attribute \src "ls180.v:1844.5-1844.41" - process $proc$ls180.v:1844$3852 + attribute \src "ls180.v:1847.5-1847.41" + process $proc$ls180.v:1847$3850 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always sync init update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end - attribute \src "ls180.v:1845.5-1845.57" - process $proc$ls180.v:1845$3853 + attribute \src "ls180.v:1848.5-1848.57" + process $proc$ls180.v:1848$3851 assign { } { } assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 sync always sync init update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] end - attribute \src "ls180.v:1846.5-1846.60" - process $proc$ls180.v:1846$3854 + attribute \src "ls180.v:1849.5-1849.60" + process $proc$ls180.v:1849$3852 assign { } { } assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always sync init update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:1847.5-1847.36" - process $proc$ls180.v:1847$3855 + attribute \src "ls180.v:1850.5-1850.36" + process $proc$ls180.v:1850$3853 assign { } { } assign $1\builder_converter2_state[0:0] 1'0 sync always sync init update \builder_converter2_state $1\builder_converter2_state[0:0] end - attribute \src "ls180.v:1848.5-1848.41" - process $proc$ls180.v:1848$3856 + attribute \src "ls180.v:1851.5-1851.41" + process $proc$ls180.v:1851$3854 assign { } { } assign $1\builder_converter2_next_state[0:0] 1'0 sync always sync init update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end - attribute \src "ls180.v:1849.5-1849.60" - process $proc$ls180.v:1849$3857 + attribute \src "ls180.v:1852.5-1852.60" + process $proc$ls180.v:1852$3855 assign { } { } assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 sync always sync init update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] end - attribute \src "ls180.v:1850.5-1850.63" - process $proc$ls180.v:1850$3858 + attribute \src "ls180.v:1853.5-1853.63" + process $proc$ls180.v:1853$3856 assign { } { } assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 sync always sync init update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:1851.11-1851.41" - process $proc$ls180.v:1851$3859 + attribute \src "ls180.v:1854.11-1854.41" + process $proc$ls180.v:1854$3857 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always sync init update \builder_refresher_state $1\builder_refresher_state[1:0] end - attribute \src "ls180.v:1852.11-1852.46" - process $proc$ls180.v:1852$3860 + attribute \src "ls180.v:1855.11-1855.46" + process $proc$ls180.v:1855$3858 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always sync init update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:1853.11-1853.44" - process $proc$ls180.v:1853$3861 + attribute \src "ls180.v:1856.11-1856.44" + process $proc$ls180.v:1856$3859 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end - attribute \src "ls180.v:1854.11-1854.49" - process $proc$ls180.v:1854$3862 + attribute \src "ls180.v:1857.11-1857.49" + process $proc$ls180.v:1857$3860 assign { } { } assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:1855.11-1855.44" - process $proc$ls180.v:1855$3863 + attribute \src "ls180.v:1858.11-1858.44" + process $proc$ls180.v:1858$3861 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end - attribute \src "ls180.v:1856.11-1856.49" - process $proc$ls180.v:1856$3864 + attribute \src "ls180.v:1859.11-1859.49" + process $proc$ls180.v:1859$3862 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:1857.11-1857.44" - process $proc$ls180.v:1857$3865 + attribute \src "ls180.v:1860.11-1860.44" + process $proc$ls180.v:1860$3863 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end - attribute \src "ls180.v:1858.11-1858.49" - process $proc$ls180.v:1858$3866 + attribute \src "ls180.v:1861.11-1861.49" + process $proc$ls180.v:1861$3864 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:1859.11-1859.44" - process $proc$ls180.v:1859$3867 + attribute \src "ls180.v:1862.11-1862.44" + process $proc$ls180.v:1862$3865 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end - attribute \src "ls180.v:1860.11-1860.49" - process $proc$ls180.v:1860$3868 + attribute \src "ls180.v:1863.11-1863.49" + process $proc$ls180.v:1863$3866 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:1861.11-1861.43" - process $proc$ls180.v:1861$3869 + attribute \src "ls180.v:1864.11-1864.43" + process $proc$ls180.v:1864$3867 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always sync init update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end - attribute \src "ls180.v:1862.11-1862.48" - process $proc$ls180.v:1862$3870 + attribute \src "ls180.v:1865.11-1865.48" + process $proc$ls180.v:1865$3868 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always sync init update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:1875.5-1875.27" - process $proc$ls180.v:1875$3871 + attribute \src "ls180.v:1878.5-1878.27" + process $proc$ls180.v:1878$3869 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always update \builder_locked0 $0\builder_locked0[0:0] sync init end - attribute \src "ls180.v:1876.5-1876.27" - process $proc$ls180.v:1876$3872 + attribute \src "ls180.v:1879.5-1879.27" + process $proc$ls180.v:1879$3870 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:1877.5-1877.27" - process $proc$ls180.v:1877$3873 + attribute \src "ls180.v:1880.5-1880.27" + process $proc$ls180.v:1880$3871 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always update \builder_locked2 $0\builder_locked2[0:0] sync init end - attribute \src "ls180.v:1878.5-1878.27" - process $proc$ls180.v:1878$3874 + attribute \src "ls180.v:1881.5-1881.27" + process $proc$ls180.v:1881$3872 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always update \builder_locked3 $0\builder_locked3[0:0] sync init end - attribute \src "ls180.v:1879.5-1879.42" - process $proc$ls180.v:1879$3875 + attribute \src "ls180.v:1882.5-1882.42" + process $proc$ls180.v:1882$3873 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always sync init update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:1880.5-1880.43" - process $proc$ls180.v:1880$3876 + attribute \src "ls180.v:1883.5-1883.43" + process $proc$ls180.v:1883$3874 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:1881.5-1881.43" - process $proc$ls180.v:1881$3877 + attribute \src "ls180.v:1884.5-1884.43" + process $proc$ls180.v:1884$3875 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:1882.5-1882.43" - process $proc$ls180.v:1882$3878 + attribute \src "ls180.v:1885.5-1885.43" + process $proc$ls180.v:1885$3876 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:1883.5-1883.43" - process $proc$ls180.v:1883$3879 + attribute \src "ls180.v:1886.5-1886.43" + process $proc$ls180.v:1886$3877 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:1884.5-1884.35" - process $proc$ls180.v:1884$3880 + attribute \src "ls180.v:1887.5-1887.35" + process $proc$ls180.v:1887$3878 assign { } { } assign $1\builder_converter_state[0:0] 1'0 sync always sync init update \builder_converter_state $1\builder_converter_state[0:0] end - attribute \src "ls180.v:1885.5-1885.40" - process $proc$ls180.v:1885$3881 + attribute \src "ls180.v:1888.5-1888.40" + process $proc$ls180.v:1888$3879 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always sync init update \builder_converter_next_state $1\builder_converter_next_state[0:0] end - attribute \src "ls180.v:1886.5-1886.55" - process $proc$ls180.v:1886$3882 + attribute \src "ls180.v:1889.5-1889.55" + process $proc$ls180.v:1889$3880 assign { } { } assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end - attribute \src "ls180.v:1887.5-1887.58" - process $proc$ls180.v:1887$3883 + attribute \src "ls180.v:1890.5-1890.58" + process $proc$ls180.v:1890$3881 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:1888.11-1888.42" - process $proc$ls180.v:1888$3884 + attribute \src "ls180.v:1891.11-1891.42" + process $proc$ls180.v:1891$3882 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always sync init update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end - attribute \src "ls180.v:1889.11-1889.47" - process $proc$ls180.v:1889$3885 + attribute \src "ls180.v:1892.11-1892.47" + process $proc$ls180.v:1892$3883 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always sync init update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end - attribute \src "ls180.v:1890.11-1890.62" - process $proc$ls180.v:1890$3886 + attribute \src "ls180.v:1893.11-1893.62" + process $proc$ls180.v:1893$3884 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 sync always sync init update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] end - attribute \src "ls180.v:1891.5-1891.59" - process $proc$ls180.v:1891$3887 + attribute \src "ls180.v:1894.5-1894.59" + process $proc$ls180.v:1894$3885 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 sync always sync init update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:1892.11-1892.42" - process $proc$ls180.v:1892$3888 + attribute \src "ls180.v:1895.11-1895.42" + process $proc$ls180.v:1895$3886 assign { } { } assign $1\builder_spimaster1_state[1:0] 2'00 sync always sync init update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] end - attribute \src "ls180.v:1893.11-1893.47" - process $proc$ls180.v:1893$3889 + attribute \src "ls180.v:1896.11-1896.47" + process $proc$ls180.v:1896$3887 assign { } { } assign $1\builder_spimaster1_next_state[1:0] 2'00 sync always sync init update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] end - attribute \src "ls180.v:1894.11-1894.60" - process $proc$ls180.v:1894$3890 + attribute \src "ls180.v:1897.11-1897.60" + process $proc$ls180.v:1897$3888 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 sync always sync init update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] end - attribute \src "ls180.v:1895.5-1895.57" - process $proc$ls180.v:1895$3891 + attribute \src "ls180.v:1898.5-1898.57" + process $proc$ls180.v:1898$3889 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 sync always sync init update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:1896.5-1896.41" - process $proc$ls180.v:1896$3892 + attribute \src "ls180.v:1899.5-1899.41" + process $proc$ls180.v:1899$3890 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end - attribute \src "ls180.v:1897.5-1897.46" - process $proc$ls180.v:1897$3893 + attribute \src "ls180.v:1900.5-1900.46" + process $proc$ls180.v:1900$3891 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end - attribute \src "ls180.v:1898.11-1898.66" - process $proc$ls180.v:1898$3894 + attribute \src "ls180.v:1901.11-1901.66" + process $proc$ls180.v:1901$3892 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end - attribute \src "ls180.v:1899.5-1899.63" - process $proc$ls180.v:1899$3895 + attribute \src "ls180.v:1902.5-1902.63" + process $proc$ls180.v:1902$3893 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:1900.11-1900.47" - process $proc$ls180.v:1900$3896 + attribute \src "ls180.v:1903.11-1903.47" + process $proc$ls180.v:1903$3894 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end - attribute \src "ls180.v:1901.11-1901.52" - process $proc$ls180.v:1901$3897 + attribute \src "ls180.v:1904.11-1904.52" + process $proc$ls180.v:1904$3895 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end - attribute \src "ls180.v:1902.11-1902.66" - process $proc$ls180.v:1902$3898 + attribute \src "ls180.v:1905.11-1905.66" + process $proc$ls180.v:1905$3896 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end - attribute \src "ls180.v:1903.5-1903.63" - process $proc$ls180.v:1903$3899 + attribute \src "ls180.v:1906.5-1906.63" + process $proc$ls180.v:1906$3897 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:1904.11-1904.47" - process $proc$ls180.v:1904$3900 + attribute \src "ls180.v:1907.11-1907.47" + process $proc$ls180.v:1907$3898 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end - attribute \src "ls180.v:1905.11-1905.52" - process $proc$ls180.v:1905$3901 + attribute \src "ls180.v:1908.11-1908.52" + process $proc$ls180.v:1908$3899 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end - attribute \src "ls180.v:1906.11-1906.67" - process $proc$ls180.v:1906$3902 + attribute \src "ls180.v:1909.11-1909.67" + process $proc$ls180.v:1909$3900 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end - attribute \src "ls180.v:1907.5-1907.64" - process $proc$ls180.v:1907$3903 + attribute \src "ls180.v:1910.5-1910.64" + process $proc$ls180.v:1910$3901 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end - attribute \src "ls180.v:1908.12-1908.71" - process $proc$ls180.v:1908$3904 + attribute \src "ls180.v:1911.12-1911.71" + process $proc$ls180.v:1911$3902 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end - attribute \src "ls180.v:1909.5-1909.66" - process $proc$ls180.v:1909$3905 + attribute \src "ls180.v:1912.5-1912.66" + process $proc$ls180.v:1912$3903 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end - attribute \src "ls180.v:1910.5-1910.66" - process $proc$ls180.v:1910$3906 + attribute \src "ls180.v:1913.5-1913.66" + process $proc$ls180.v:1913$3904 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end - attribute \src "ls180.v:1911.5-1911.69" - process $proc$ls180.v:1911$3907 + attribute \src "ls180.v:1914.5-1914.69" + process $proc$ls180.v:1914$3905 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:1912.5-1912.41" - process $proc$ls180.v:1912$3908 + attribute \src "ls180.v:1915.5-1915.41" + process $proc$ls180.v:1915$3906 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end - attribute \src "ls180.v:1913.5-1913.46" - process $proc$ls180.v:1913$3909 + attribute \src "ls180.v:1916.5-1916.46" + process $proc$ls180.v:1916$3907 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end - attribute \src "ls180.v:1914.5-1914.66" - process $proc$ls180.v:1914$3910 + attribute \src "ls180.v:1917.5-1917.66" + process $proc$ls180.v:1917$3908 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end - attribute \src "ls180.v:1915.5-1915.69" - process $proc$ls180.v:1915$3911 + attribute \src "ls180.v:1918.5-1918.69" + process $proc$ls180.v:1918$3909 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:1916.11-1916.41" - process $proc$ls180.v:1916$3912 + attribute \src "ls180.v:1919.11-1919.41" + process $proc$ls180.v:1919$3910 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end - attribute \src "ls180.v:1917.11-1917.46" - process $proc$ls180.v:1917$3913 + attribute \src "ls180.v:1920.11-1920.46" + process $proc$ls180.v:1920$3911 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end - attribute \src "ls180.v:1918.11-1918.61" - process $proc$ls180.v:1918$3914 + attribute \src "ls180.v:1921.11-1921.61" + process $proc$ls180.v:1921$3912 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end - attribute \src "ls180.v:1919.5-1919.58" - process $proc$ls180.v:1919$3915 + attribute \src "ls180.v:1922.5-1922.58" + process $proc$ls180.v:1922$3913 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1920.11-1920.48" - process $proc$ls180.v:1920$3916 + attribute \src "ls180.v:1923.11-1923.48" + process $proc$ls180.v:1923$3914 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end - attribute \src "ls180.v:1921.11-1921.53" - process $proc$ls180.v:1921$3917 + attribute \src "ls180.v:1924.11-1924.53" + process $proc$ls180.v:1924$3915 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end - attribute \src "ls180.v:1922.11-1922.70" - process $proc$ls180.v:1922$3918 + attribute \src "ls180.v:1925.11-1925.70" + process $proc$ls180.v:1925$3916 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end - attribute \src "ls180.v:1923.5-1923.66" - process $proc$ls180.v:1923$3919 + attribute \src "ls180.v:1926.5-1926.66" + process $proc$ls180.v:1926$3917 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end - attribute \src "ls180.v:1924.12-1924.73" - process $proc$ls180.v:1924$3920 + attribute \src "ls180.v:1927.12-1927.73" + process $proc$ls180.v:1927$3918 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end - attribute \src "ls180.v:1925.5-1925.68" - process $proc$ls180.v:1925$3921 + attribute \src "ls180.v:1928.5-1928.68" + process $proc$ls180.v:1928$3919 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end - attribute \src "ls180.v:1926.5-1926.69" - process $proc$ls180.v:1926$3922 + attribute \src "ls180.v:1929.5-1929.69" + process $proc$ls180.v:1929$3920 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end - attribute \src "ls180.v:1927.5-1927.72" - process $proc$ls180.v:1927$3923 + attribute \src "ls180.v:1930.5-1930.72" + process $proc$ls180.v:1930$3921 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:1928.5-1928.52" - process $proc$ls180.v:1928$3924 + attribute \src "ls180.v:1931.5-1931.52" + process $proc$ls180.v:1931$3922 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end - attribute \src "ls180.v:1929.5-1929.57" - process $proc$ls180.v:1929$3925 + attribute \src "ls180.v:1932.5-1932.57" + process $proc$ls180.v:1932$3923 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end - attribute \src "ls180.v:1930.12-1930.93" - process $proc$ls180.v:1930$3926 + attribute \src "ls180.v:1933.12-1933.93" + process $proc$ls180.v:1933$3924 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end - attribute \src "ls180.v:1931.5-1931.88" - process $proc$ls180.v:1931$3927 + attribute \src "ls180.v:1934.5-1934.88" + process $proc$ls180.v:1934$3925 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end - attribute \src "ls180.v:1932.12-1932.93" - process $proc$ls180.v:1932$3928 + attribute \src "ls180.v:1935.12-1935.93" + process $proc$ls180.v:1935$3926 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end - attribute \src "ls180.v:1933.5-1933.88" - process $proc$ls180.v:1933$3929 + attribute \src "ls180.v:1936.5-1936.88" + process $proc$ls180.v:1936$3927 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end - attribute \src "ls180.v:1934.12-1934.93" - process $proc$ls180.v:1934$3930 + attribute \src "ls180.v:1937.12-1937.93" + process $proc$ls180.v:1937$3928 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end - attribute \src "ls180.v:1935.5-1935.88" - process $proc$ls180.v:1935$3931 + attribute \src "ls180.v:1938.5-1938.88" + process $proc$ls180.v:1938$3929 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end - attribute \src "ls180.v:1936.12-1936.93" - process $proc$ls180.v:1936$3932 + attribute \src "ls180.v:1939.12-1939.93" + process $proc$ls180.v:1939$3930 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end - attribute \src "ls180.v:1937.5-1937.88" - process $proc$ls180.v:1937$3933 + attribute \src "ls180.v:1940.5-1940.88" + process $proc$ls180.v:1940$3931 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end - attribute \src "ls180.v:1938.11-1938.87" - process $proc$ls180.v:1938$3934 + attribute \src "ls180.v:1941.11-1941.87" + process $proc$ls180.v:1941$3932 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end - attribute \src "ls180.v:1939.5-1939.84" - process $proc$ls180.v:1939$3935 + attribute \src "ls180.v:1942.5-1942.84" + process $proc$ls180.v:1942$3933 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:1940.11-1940.42" - process $proc$ls180.v:1940$3936 + attribute \src "ls180.v:1943.11-1943.42" + process $proc$ls180.v:1943$3934 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end - attribute \src "ls180.v:1941.11-1941.47" - process $proc$ls180.v:1941$3937 + attribute \src "ls180.v:1944.11-1944.47" + process $proc$ls180.v:1944$3935 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end - attribute \src "ls180.v:1942.5-1942.55" - process $proc$ls180.v:1942$3938 + attribute \src "ls180.v:1945.5-1945.55" + process $proc$ls180.v:1945$3936 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end - attribute \src "ls180.v:1943.5-1943.58" - process $proc$ls180.v:1943$3939 + attribute \src "ls180.v:1946.5-1946.58" + process $proc$ls180.v:1946$3937 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end - attribute \src "ls180.v:1944.5-1944.56" - process $proc$ls180.v:1944$3940 + attribute \src "ls180.v:1947.5-1947.56" + process $proc$ls180.v:1947$3938 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end - attribute \src "ls180.v:1945.5-1945.59" - process $proc$ls180.v:1945$3941 + attribute \src "ls180.v:1948.5-1948.59" + process $proc$ls180.v:1948$3939 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end - attribute \src "ls180.v:1946.11-1946.62" - process $proc$ls180.v:1946$3942 + attribute \src "ls180.v:1949.11-1949.62" + process $proc$ls180.v:1949$3940 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:1947.5-1947.59" - process $proc$ls180.v:1947$3943 + attribute \src "ls180.v:195.12-195.78" + process $proc$ls180.v:195$3154 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end + attribute \src "ls180.v:1950.5-1950.59" + process $proc$ls180.v:1950$3941 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end - attribute \src "ls180.v:1948.12-1948.65" - process $proc$ls180.v:1948$3944 + attribute \src "ls180.v:1951.12-1951.65" + process $proc$ls180.v:1951$3942 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end - attribute \src "ls180.v:1949.5-1949.60" - process $proc$ls180.v:1949$3945 + attribute \src "ls180.v:1952.5-1952.60" + process $proc$ls180.v:1952$3943 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end - attribute \src "ls180.v:1950.5-1950.56" - process $proc$ls180.v:1950$3946 + attribute \src "ls180.v:1953.5-1953.56" + process $proc$ls180.v:1953$3944 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end - attribute \src "ls180.v:1951.5-1951.59" - process $proc$ls180.v:1951$3947 + attribute \src "ls180.v:1954.5-1954.59" + process $proc$ls180.v:1954$3945 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end - attribute \src "ls180.v:1952.5-1952.58" - process $proc$ls180.v:1952$3948 + attribute \src "ls180.v:1955.5-1955.58" + process $proc$ls180.v:1955$3946 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end - attribute \src "ls180.v:1953.5-1953.61" - process $proc$ls180.v:1953$3949 + attribute \src "ls180.v:1956.5-1956.61" + process $proc$ls180.v:1956$3947 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end - attribute \src "ls180.v:1954.5-1954.57" - process $proc$ls180.v:1954$3950 + attribute \src "ls180.v:1957.5-1957.57" + process $proc$ls180.v:1957$3948 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end - attribute \src "ls180.v:1955.5-1955.60" - process $proc$ls180.v:1955$3951 + attribute \src "ls180.v:1958.5-1958.60" + process $proc$ls180.v:1958$3949 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end - attribute \src "ls180.v:1956.5-1956.59" - process $proc$ls180.v:1956$3952 + attribute \src "ls180.v:1959.5-1959.59" + process $proc$ls180.v:1959$3950 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end - attribute \src "ls180.v:1957.5-1957.62" - process $proc$ls180.v:1957$3953 + attribute \src "ls180.v:1960.5-1960.62" + process $proc$ls180.v:1960$3951 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end - attribute \src "ls180.v:1958.13-1958.76" - process $proc$ls180.v:1958$3954 + attribute \src "ls180.v:1961.13-1961.76" + process $proc$ls180.v:1961$3952 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end - attribute \src "ls180.v:1959.5-1959.69" - process $proc$ls180.v:1959$3955 + attribute \src "ls180.v:1962.5-1962.69" + process $proc$ls180.v:1962$3953 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:1960.11-1960.46" - process $proc$ls180.v:1960$3956 + attribute \src "ls180.v:1963.11-1963.46" + process $proc$ls180.v:1963$3954 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end - attribute \src "ls180.v:1961.11-1961.51" - process $proc$ls180.v:1961$3957 + attribute \src "ls180.v:1964.11-1964.51" + process $proc$ls180.v:1964$3955 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end - attribute \src "ls180.v:1962.12-1962.87" - process $proc$ls180.v:1962$3958 + attribute \src "ls180.v:1965.12-1965.87" + process $proc$ls180.v:1965$3956 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end - attribute \src "ls180.v:1963.5-1963.82" - process $proc$ls180.v:1963$3959 + attribute \src "ls180.v:1966.5-1966.82" + process $proc$ls180.v:1966$3957 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:1964.5-1964.44" - process $proc$ls180.v:1964$3960 + attribute \src "ls180.v:1967.5-1967.44" + process $proc$ls180.v:1967$3958 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end - attribute \src "ls180.v:1965.5-1965.49" - process $proc$ls180.v:1965$3961 + attribute \src "ls180.v:1968.5-1968.49" + process $proc$ls180.v:1968$3959 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end - attribute \src "ls180.v:1966.12-1966.75" - process $proc$ls180.v:1966$3962 + attribute \src "ls180.v:1969.12-1969.75" + process $proc$ls180.v:1969$3960 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] end - attribute \src "ls180.v:1967.5-1967.70" - process $proc$ls180.v:1967$3963 + attribute \src "ls180.v:1970.5-1970.70" + process $proc$ls180.v:1970$3961 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1968.11-1968.60" - process $proc$ls180.v:1968$3964 + attribute \src "ls180.v:1971.11-1971.60" + process $proc$ls180.v:1971$3962 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end - attribute \src "ls180.v:1969.11-1969.65" - process $proc$ls180.v:1969$3965 + attribute \src "ls180.v:1972.11-1972.65" + process $proc$ls180.v:1972$3963 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end - attribute \src "ls180.v:197.5-197.74" - process $proc$ls180.v:197$3154 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] - sync init - end - attribute \src "ls180.v:1970.12-1970.87" - process $proc$ls180.v:1970$3966 + attribute \src "ls180.v:1973.12-1973.87" + process $proc$ls180.v:1973$3964 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end - attribute \src "ls180.v:1971.5-1971.82" - process $proc$ls180.v:1971$3967 + attribute \src "ls180.v:1974.5-1974.82" + process $proc$ls180.v:1974$3965 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:1972.12-1972.43" - process $proc$ls180.v:1972$3968 + attribute \src "ls180.v:1975.12-1975.43" + process $proc$ls180.v:1975$3966 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end - attribute \src "ls180.v:1973.5-1973.34" - process $proc$ls180.v:1973$3969 + attribute \src "ls180.v:1976.5-1976.34" + process $proc$ls180.v:1976$3967 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always sync init update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end - attribute \src "ls180.v:1974.11-1974.43" - process $proc$ls180.v:1974$3970 + attribute \src "ls180.v:1977.11-1977.43" + process $proc$ls180.v:1977$3968 assign { } { } assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1976.12-1976.52" - process $proc$ls180.v:1976$3971 + attribute \src "ls180.v:1979.12-1979.52" + process $proc$ls180.v:1979$3969 assign { } { } assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 sync always update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] sync init end - attribute \src "ls180.v:1977.12-1977.54" - process $proc$ls180.v:1977$3972 + attribute \src "ls180.v:1980.12-1980.54" + process $proc$ls180.v:1980$3970 assign { } { } assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 sync always update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] sync init end - attribute \src "ls180.v:1978.12-1978.54" - process $proc$ls180.v:1978$3973 + attribute \src "ls180.v:1981.12-1981.54" + process $proc$ls180.v:1981$3971 assign { } { } assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1979.11-1979.50" - process $proc$ls180.v:1979$3974 + attribute \src "ls180.v:1982.11-1982.50" + process $proc$ls180.v:1982$3972 assign { } { } assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 sync always update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] sync init end - attribute \src "ls180.v:198.11-198.24" - process $proc$ls180.v:198$3155 - assign { } { } - assign $0\eint_1[2:0] 3'000 - sync always - update \eint_1 $0\eint_1[2:0] - sync init - end - attribute \src "ls180.v:1980.5-1980.44" - process $proc$ls180.v:1980$3975 + attribute \src "ls180.v:1983.5-1983.44" + process $proc$ls180.v:1983$3973 assign { } { } assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 sync always update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] sync init end - attribute \src "ls180.v:1981.5-1981.44" - process $proc$ls180.v:1981$3976 + attribute \src "ls180.v:1984.5-1984.44" + process $proc$ls180.v:1984$3974 assign { } { } assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 sync always update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] sync init end - attribute \src "ls180.v:1982.5-1982.44" - process $proc$ls180.v:1982$3977 + attribute \src "ls180.v:1985.5-1985.44" + process $proc$ls180.v:1985$3975 assign { } { } assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:1983.5-1983.43" - process $proc$ls180.v:1983$3978 + attribute \src "ls180.v:1986.5-1986.43" + process $proc$ls180.v:1986$3976 assign { } { } assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 sync always update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] sync init end - attribute \src "ls180.v:1986.12-1986.65" - process $proc$ls180.v:1986$3979 + attribute \src "ls180.v:1989.12-1989.65" + process $proc$ls180.v:1989$3977 assign { } { } assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] sync init end - attribute \src "ls180.v:1990.5-1990.55" - process $proc$ls180.v:1990$3980 + attribute \src "ls180.v:1993.5-1993.55" + process $proc$ls180.v:1993$3978 assign { } { } assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 sync always update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] sync init end - attribute \src "ls180.v:1994.5-1994.55" - process $proc$ls180.v:1994$3981 + attribute \src "ls180.v:1997.5-1997.55" + process $proc$ls180.v:1997$3979 assign { } { } assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 sync always update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] sync init end - attribute \src "ls180.v:1997.12-1997.40" - process $proc$ls180.v:1997$3982 + attribute \src "ls180.v:2000.12-2000.40" + process $proc$ls180.v:2000$3980 assign { } { } assign $1\builder_shared_dat_r[31:0] 0 sync always sync init update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:2001.5-2001.30" - process $proc$ls180.v:2001$3983 + attribute \src "ls180.v:2004.5-2004.30" + process $proc$ls180.v:2004$3981 assign { } { } assign $1\builder_shared_ack[0:0] 1'0 sync always sync init update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "ls180.v:2007.11-2007.31" - process $proc$ls180.v:2007$3984 + attribute \src "ls180.v:2010.11-2010.31" + process $proc$ls180.v:2010$3982 assign { } { } assign $1\builder_grant[2:0] 3'000 sync always sync init update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:2008.12-2008.37" - process $proc$ls180.v:2008$3985 + attribute \src "ls180.v:2011.12-2011.37" + process $proc$ls180.v:2011$3983 assign { } { } assign $1\builder_slave_sel[12:0] 13'0000000000000 sync always sync init update \builder_slave_sel $1\builder_slave_sel[12:0] end - attribute \src "ls180.v:2009.12-2009.39" - process $proc$ls180.v:2009$3986 + attribute \src "ls180.v:2012.12-2012.39" + process $proc$ls180.v:2012$3984 assign { } { } assign $1\builder_slave_sel_r[12:0] 13'0000000000000 sync always sync init update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] end - attribute \src "ls180.v:2010.5-2010.25" - process $proc$ls180.v:2010$3987 + attribute \src "ls180.v:2013.5-2013.25" + process $proc$ls180.v:2013$3985 assign { } { } assign $1\builder_error[0:0] 1'0 sync always sync init update \builder_error $1\builder_error[0:0] end - attribute \src "ls180.v:2013.12-2013.39" - process $proc$ls180.v:2013$3988 + attribute \src "ls180.v:2016.12-2016.39" + process $proc$ls180.v:2016$3986 assign { } { } assign $1\builder_count[19:0] 20'11110100001001000000 sync always sync init update \builder_count $1\builder_count[19:0] end - attribute \src "ls180.v:2017.11-2017.51" - process $proc$ls180.v:2017$3989 + attribute \src "ls180.v:2020.11-2020.51" + process $proc$ls180.v:2020$3987 assign { } { } assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:202.5-202.74" - process $proc$ls180.v:202$3156 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] - sync init - end - attribute \src "ls180.v:2058.11-2058.51" - process $proc$ls180.v:2058$3990 + attribute \src "ls180.v:2061.11-2061.51" + process $proc$ls180.v:2061$3988 assign { } { } assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2087.11-2087.51" - process $proc$ls180.v:2087$3991 + attribute \src "ls180.v:2090.11-2090.51" + process $proc$ls180.v:2090$3989 assign { } { } assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:210.5-210.40" - process $proc$ls180.v:210$3157 - assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2100.11-2100.51" - process $proc$ls180.v:2100$3992 + attribute \src "ls180.v:2103.11-2103.51" + process $proc$ls180.v:2103$3990 assign { } { } assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:214.5-214.40" - process $proc$ls180.v:214$3158 + attribute \src "ls180.v:213.5-213.40" + process $proc$ls180.v:213$3155 assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:2141.11-2141.51" - process $proc$ls180.v:2141$3993 + attribute \src "ls180.v:2144.11-2144.51" + process $proc$ls180.v:2144$3991 assign { } { } assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:217.11-217.37" - process $proc$ls180.v:217$3159 + attribute \src "ls180.v:217.5-217.40" + process $proc$ls180.v:217$3156 assign { } { } - assign $1\main_libresocsim_we[7:0] 8'00000000 + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init - update \main_libresocsim_we $1\main_libresocsim_we[7:0] end - attribute \src "ls180.v:2182.11-2182.51" - process $proc$ls180.v:2182$3994 + attribute \src "ls180.v:2185.11-2185.51" + process $proc$ls180.v:2185$3992 assign { } { } assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:219.12-219.49" - process $proc$ls180.v:219$3160 + attribute \src "ls180.v:220.11-220.37" + process $proc$ls180.v:220$3157 + assign { } { } + assign $1\main_libresocsim_we[7:0] 8'00000000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:222.12-222.49" + process $proc$ls180.v:222$3158 assign { } { } assign $1\main_libresocsim_load_storage[31:0] 0 sync always sync init update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] end - attribute \src "ls180.v:220.5-220.36" - process $proc$ls180.v:220$3161 + attribute \src "ls180.v:223.5-223.36" + process $proc$ls180.v:223$3159 assign { } { } assign $1\main_libresocsim_load_re[0:0] 1'0 sync always sync init update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end - attribute \src "ls180.v:221.12-221.51" - process $proc$ls180.v:221$3162 + attribute \src "ls180.v:224.12-224.51" + process $proc$ls180.v:224$3160 assign { } { } assign $1\main_libresocsim_reload_storage[31:0] 0 sync always sync init update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:222.5-222.38" - process $proc$ls180.v:222$3163 + attribute \src "ls180.v:225.5-225.38" + process $proc$ls180.v:225$3161 assign { } { } assign $1\main_libresocsim_reload_re[0:0] 1'0 sync always sync init update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] end - attribute \src "ls180.v:223.5-223.39" - process $proc$ls180.v:223$3164 + attribute \src "ls180.v:2250.11-2250.51" + process $proc$ls180.v:2250$3993 assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:224.5-224.34" - process $proc$ls180.v:224$3165 + attribute \src "ls180.v:226.5-226.39" + process $proc$ls180.v:226$3162 assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 + assign $1\main_libresocsim_en_storage[0:0] 1'0 sync always sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] end - attribute \src "ls180.v:2247.11-2247.51" - process $proc$ls180.v:2247$3995 + attribute \src "ls180.v:227.5-227.34" + process $proc$ls180.v:227$3163 assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_en_re[0:0] 1'0 sync always sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] end - attribute \src "ls180.v:225.5-225.49" - process $proc$ls180.v:225$3166 + attribute \src "ls180.v:228.5-228.49" + process $proc$ls180.v:228$3164 assign { } { } assign $1\main_libresocsim_update_value_storage[0:0] 1'0 sync always sync init update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end - attribute \src "ls180.v:226.5-226.44" - process $proc$ls180.v:226$3167 + attribute \src "ls180.v:229.5-229.44" + process $proc$ls180.v:229$3165 assign { } { } assign $1\main_libresocsim_update_value_re[0:0] 1'0 sync always sync init update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] end - attribute \src "ls180.v:227.12-227.49" - process $proc$ls180.v:227$3168 + attribute \src "ls180.v:230.12-230.49" + process $proc$ls180.v:230$3166 assign { } { } assign $1\main_libresocsim_value_status[31:0] 0 sync always sync init update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] end - attribute \src "ls180.v:231.5-231.41" - process $proc$ls180.v:231$3169 + attribute \src "ls180.v:234.5-234.41" + process $proc$ls180.v:234$3167 assign { } { } assign $1\main_libresocsim_zero_pending[0:0] 1'0 sync always sync init update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] end - attribute \src "ls180.v:233.5-233.39" - process $proc$ls180.v:233$3170 + attribute \src "ls180.v:236.5-236.39" + process $proc$ls180.v:236$3168 assign { } { } assign $1\main_libresocsim_zero_clear[0:0] 1'0 sync always sync init update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:234.5-234.45" - process $proc$ls180.v:234$3171 + attribute \src "ls180.v:237.5-237.45" + process $proc$ls180.v:237$3169 assign { } { } assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 sync always sync init update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] end - attribute \src "ls180.v:2380.11-2380.51" - process $proc$ls180.v:2380$3996 + attribute \src "ls180.v:2383.11-2383.51" + process $proc$ls180.v:2383$3994 assign { } { } assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:243.5-243.49" - process $proc$ls180.v:243$3172 + attribute \src "ls180.v:246.5-246.49" + process $proc$ls180.v:246$3170 assign { } { } assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always sync init update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:244.5-244.44" - process $proc$ls180.v:244$3173 + attribute \src "ls180.v:2464.11-2464.51" + process $proc$ls180.v:2464$3995 assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:245.12-245.42" - process $proc$ls180.v:245$3174 + attribute \src "ls180.v:247.5-247.44" + process $proc$ls180.v:247$3171 assign { } { } - assign $1\main_libresocsim_value[31:0] 0 + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 sync always sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end - attribute \src "ls180.v:2461.11-2461.51" - process $proc$ls180.v:2461$3997 + attribute \src "ls180.v:248.12-248.42" + process $proc$ls180.v:248$3172 assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_value[31:0] 0 sync always sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + update \main_libresocsim_value $1\main_libresocsim_value[31:0] end - attribute \src "ls180.v:2478.11-2478.51" - process $proc$ls180.v:2478$3998 + attribute \src "ls180.v:2481.11-2481.51" + process $proc$ls180.v:2481$3996 assign { } { } assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2519.11-2519.52" - process $proc$ls180.v:2519$3999 + attribute \src "ls180.v:2522.11-2522.52" + process $proc$ls180.v:2522$3997 assign { } { } assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:252.5-252.39" - process $proc$ls180.v:252$3175 + attribute \src "ls180.v:255.5-255.39" + process $proc$ls180.v:255$3173 assign { } { } assign $1\main_interface0_ram_bus_ack[0:0] 1'0 sync always sync init update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] end - attribute \src "ls180.v:2552.11-2552.52" - process $proc$ls180.v:2552$4000 + attribute \src "ls180.v:2555.11-2555.52" + process $proc$ls180.v:2555$3998 assign { } { } assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:256.5-256.39" - process $proc$ls180.v:256$3176 + attribute \src "ls180.v:259.5-259.39" + process $proc$ls180.v:259$3174 assign { } { } assign $0\main_interface0_ram_bus_err[0:0] 1'0 sync always update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] sync init end - attribute \src "ls180.v:259.11-259.31" - process $proc$ls180.v:259$3177 + attribute \src "ls180.v:2596.11-2596.52" + process $proc$ls180.v:2596$3999 assign { } { } - assign $1\main_sram0_we[7:0] 8'00000000 + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_sram0_we $1\main_sram0_we[7:0] + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2593.11-2593.52" - process $proc$ls180.v:2593$4001 + attribute \src "ls180.v:262.11-262.31" + process $proc$ls180.v:262$3175 assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_sram0_we[7:0] 8'00000000 sync always sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + update \main_sram0_we $1\main_sram0_we[7:0] end - attribute \src "ls180.v:2658.11-2658.52" - process $proc$ls180.v:2658$4002 + attribute \src "ls180.v:2661.11-2661.52" + process $proc$ls180.v:2661$4000 assign { } { } assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:267.5-267.39" - process $proc$ls180.v:267$3178 + attribute \src "ls180.v:2686.11-2686.52" + process $proc$ls180.v:2686$4001 assign { } { } - assign $1\main_interface1_ram_bus_ack[0:0] 1'0 + assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] + update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2683.11-2683.52" - process $proc$ls180.v:2683$4003 + attribute \src "ls180.v:270.5-270.39" + process $proc$ls180.v:270$3176 assign { } { } - assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_interface1_ram_bus_ack[0:0] 1'0 sync always sync init - update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] + update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] end - attribute \src "ls180.v:2705.11-2705.31" - process $proc$ls180.v:2705$4004 + attribute \src "ls180.v:2708.11-2708.31" + process $proc$ls180.v:2708$4002 assign { } { } assign $1\builder_state[1:0] 2'00 sync always sync init update \builder_state $1\builder_state[1:0] end - attribute \src "ls180.v:2706.11-2706.36" - process $proc$ls180.v:2706$4005 + attribute \src "ls180.v:2709.11-2709.36" + process $proc$ls180.v:2709$4003 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always sync init update \builder_next_state $1\builder_next_state[1:0] end - attribute \src "ls180.v:2707.11-2707.55" - process $proc$ls180.v:2707$4006 + attribute \src "ls180.v:2710.11-2710.55" + process $proc$ls180.v:2710$4004 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end - attribute \src "ls180.v:2708.5-2708.52" - process $proc$ls180.v:2708$4007 + attribute \src "ls180.v:2711.5-2711.52" + process $proc$ls180.v:2711$4005 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always sync init update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end - attribute \src "ls180.v:2709.12-2709.55" - process $proc$ls180.v:2709$4008 + attribute \src "ls180.v:2712.12-2712.55" + process $proc$ls180.v:2712$4006 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end - attribute \src "ls180.v:271.5-271.39" - process $proc$ls180.v:271$3179 - assign { } { } - assign $0\main_interface1_ram_bus_err[0:0] 1'0 - sync always - update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:2710.5-2710.50" - process $proc$ls180.v:2710$4009 + attribute \src "ls180.v:2713.5-2713.50" + process $proc$ls180.v:2713$4007 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always sync init update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end - attribute \src "ls180.v:2711.5-2711.46" - process $proc$ls180.v:2711$4010 + attribute \src "ls180.v:2714.5-2714.46" + process $proc$ls180.v:2714$4008 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end - attribute \src "ls180.v:2712.5-2712.49" - process $proc$ls180.v:2712$4011 + attribute \src "ls180.v:2715.5-2715.49" + process $proc$ls180.v:2715$4009 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:2713.5-2713.41" - process $proc$ls180.v:2713$4012 + attribute \src "ls180.v:2716.5-2716.41" + process $proc$ls180.v:2716$4010 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2714.12-2714.49" - process $proc$ls180.v:2714$4013 + attribute \src "ls180.v:2717.12-2717.49" + process $proc$ls180.v:2717$4011 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2715.11-2715.47" - process $proc$ls180.v:2715$4014 + attribute \src "ls180.v:2718.11-2718.47" + process $proc$ls180.v:2718$4012 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2716.5-2716.41" - process $proc$ls180.v:2716$4015 + attribute \src "ls180.v:2719.5-2719.41" + process $proc$ls180.v:2719$4013 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2717.5-2717.41" - process $proc$ls180.v:2717$4016 + attribute \src "ls180.v:2720.5-2720.41" + process $proc$ls180.v:2720$4014 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2718.5-2718.41" - process $proc$ls180.v:2718$4017 + attribute \src "ls180.v:2721.5-2721.41" + process $proc$ls180.v:2721$4015 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2719.5-2719.39" - process $proc$ls180.v:2719$4018 + attribute \src "ls180.v:2722.5-2722.39" + process $proc$ls180.v:2722$4016 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:2720.5-2720.39" - process $proc$ls180.v:2720$4019 + attribute \src "ls180.v:2723.5-2723.39" + process $proc$ls180.v:2723$4017 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:2721.5-2721.39" - process $proc$ls180.v:2721$4020 + attribute \src "ls180.v:2724.5-2724.39" + process $proc$ls180.v:2724$4018 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:2722.5-2722.41" - process $proc$ls180.v:2722$4021 + attribute \src "ls180.v:2725.5-2725.41" + process $proc$ls180.v:2725$4019 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2723.12-2723.49" - process $proc$ls180.v:2723$4022 + attribute \src "ls180.v:2726.12-2726.49" + process $proc$ls180.v:2726$4020 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2724.11-2724.47" - process $proc$ls180.v:2724$4023 + attribute \src "ls180.v:2727.11-2727.47" + process $proc$ls180.v:2727$4021 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2725.5-2725.41" - process $proc$ls180.v:2725$4024 + attribute \src "ls180.v:2728.5-2728.41" + process $proc$ls180.v:2728$4022 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2726.5-2726.42" - process $proc$ls180.v:2726$4025 + attribute \src "ls180.v:2729.5-2729.42" + process $proc$ls180.v:2729$4023 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2727.5-2727.42" - process $proc$ls180.v:2727$4026 + attribute \src "ls180.v:2730.5-2730.42" + process $proc$ls180.v:2730$4024 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2728.5-2728.39" - process $proc$ls180.v:2728$4027 + attribute \src "ls180.v:2731.5-2731.39" + process $proc$ls180.v:2731$4025 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:2729.5-2729.39" - process $proc$ls180.v:2729$4028 + attribute \src "ls180.v:2732.5-2732.39" + process $proc$ls180.v:2732$4026 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:2730.5-2730.39" - process $proc$ls180.v:2730$4029 + attribute \src "ls180.v:2733.5-2733.39" + process $proc$ls180.v:2733$4027 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:2731.12-2731.50" - process $proc$ls180.v:2731$4030 + attribute \src "ls180.v:2734.12-2734.50" + process $proc$ls180.v:2734$4028 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:2732.5-2732.42" - process $proc$ls180.v:2732$4031 + attribute \src "ls180.v:2735.5-2735.42" + process $proc$ls180.v:2735$4029 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:2733.5-2733.42" - process $proc$ls180.v:2733$4032 + attribute \src "ls180.v:2736.5-2736.42" + process $proc$ls180.v:2736$4030 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2734.12-2734.50" - process $proc$ls180.v:2734$4033 + attribute \src "ls180.v:2737.12-2737.50" + process $proc$ls180.v:2737$4031 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2735.5-2735.42" - process $proc$ls180.v:2735$4034 + attribute \src "ls180.v:2738.5-2738.42" + process $proc$ls180.v:2738$4032 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2736.5-2736.42" - process $proc$ls180.v:2736$4035 + attribute \src "ls180.v:2739.5-2739.42" + process $proc$ls180.v:2739$4033 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:2737.12-2737.50" - process $proc$ls180.v:2737$4036 + attribute \src "ls180.v:274.5-274.39" + process $proc$ls180.v:274$3177 + assign { } { } + assign $0\main_interface1_ram_bus_err[0:0] 1'0 + sync always + update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2740.12-2740.50" + process $proc$ls180.v:2740$4034 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2738.5-2738.42" - process $proc$ls180.v:2738$4037 + attribute \src "ls180.v:2741.5-2741.42" + process $proc$ls180.v:2741$4035 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2739.5-2739.42" - process $proc$ls180.v:2739$4038 + attribute \src "ls180.v:2742.5-2742.42" + process $proc$ls180.v:2742$4036 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:274.11-274.31" - process $proc$ls180.v:274$3180 - assign { } { } - assign $1\main_sram1_we[7:0] 8'00000000 - sync always - sync init - update \main_sram1_we $1\main_sram1_we[7:0] - end - attribute \src "ls180.v:2740.12-2740.50" - process $proc$ls180.v:2740$4039 + attribute \src "ls180.v:2743.12-2743.50" + process $proc$ls180.v:2743$4037 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2741.5-2741.42" - process $proc$ls180.v:2741$4040 + attribute \src "ls180.v:2744.5-2744.42" + process $proc$ls180.v:2744$4038 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:2742.5-2742.42" - process $proc$ls180.v:2742$4041 + attribute \src "ls180.v:2745.5-2745.42" + process $proc$ls180.v:2745$4039 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2743.12-2743.50" - process $proc$ls180.v:2743$4042 + attribute \src "ls180.v:2746.12-2746.50" + process $proc$ls180.v:2746$4040 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:2744.12-2744.50" - process $proc$ls180.v:2744$4043 + attribute \src "ls180.v:2747.12-2747.50" + process $proc$ls180.v:2747$4041 assign { } { } assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:2745.11-2745.48" - process $proc$ls180.v:2745$4044 + attribute \src "ls180.v:2748.11-2748.48" + process $proc$ls180.v:2748$4042 assign { } { } assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 sync always sync init update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:2746.5-2746.42" - process $proc$ls180.v:2746$4045 + attribute \src "ls180.v:2749.5-2749.42" + process $proc$ls180.v:2749$4043 assign { } { } assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2747.5-2747.42" - process $proc$ls180.v:2747$4046 + attribute \src "ls180.v:2750.5-2750.42" + process $proc$ls180.v:2750$4044 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2748.5-2748.42" - process $proc$ls180.v:2748$4047 + attribute \src "ls180.v:2751.5-2751.42" + process $proc$ls180.v:2751$4045 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2749.11-2749.48" - process $proc$ls180.v:2749$4048 + attribute \src "ls180.v:2752.11-2752.48" + process $proc$ls180.v:2752$4046 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always sync init update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2750.11-2750.48" - process $proc$ls180.v:2750$4049 + attribute \src "ls180.v:2753.11-2753.48" + process $proc$ls180.v:2753$4047 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2751.11-2751.47" - process $proc$ls180.v:2751$4050 + attribute \src "ls180.v:2754.11-2754.47" + process $proc$ls180.v:2754$4048 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always sync init update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:2752.12-2752.49" - process $proc$ls180.v:2752$4051 + attribute \src "ls180.v:2755.12-2755.49" + process $proc$ls180.v:2755$4049 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2753.5-2753.41" - process $proc$ls180.v:2753$4052 + attribute \src "ls180.v:2756.5-2756.41" + process $proc$ls180.v:2756$4050 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:2754.5-2754.41" - process $proc$ls180.v:2754$4053 + attribute \src "ls180.v:2757.5-2757.41" + process $proc$ls180.v:2757$4051 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2755.5-2755.41" - process $proc$ls180.v:2755$4054 + attribute \src "ls180.v:2758.5-2758.41" + process $proc$ls180.v:2758$4052 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2756.5-2756.41" - process $proc$ls180.v:2756$4055 + attribute \src "ls180.v:2759.5-2759.41" + process $proc$ls180.v:2759$4053 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2757.5-2757.41" - process $proc$ls180.v:2757$4056 + attribute \src "ls180.v:2760.5-2760.41" + process $proc$ls180.v:2760$4054 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2758.5-2758.39" - process $proc$ls180.v:2758$4057 + attribute \src "ls180.v:2761.5-2761.39" + process $proc$ls180.v:2761$4055 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:2759.5-2759.39" - process $proc$ls180.v:2759$4058 + attribute \src "ls180.v:2762.5-2762.39" + process $proc$ls180.v:2762$4056 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:2816.32-2816.66" - process $proc$ls180.v:2816$4059 + attribute \src "ls180.v:277.11-277.31" + process $proc$ls180.v:277$3178 + assign { } { } + assign $1\main_sram1_we[7:0] 8'00000000 + sync always + sync init + update \main_sram1_we $1\main_sram1_we[7:0] + end + attribute \src "ls180.v:2819.32-2819.66" + process $proc$ls180.v:2819$4057 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end - attribute \src "ls180.v:2817.32-2817.66" - process $proc$ls180.v:2817$4060 + attribute \src "ls180.v:2820.32-2820.66" + process $proc$ls180.v:2820$4058 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end - attribute \src "ls180.v:2818.32-2818.66" - process $proc$ls180.v:2818$4061 + attribute \src "ls180.v:2821.32-2821.66" + process $proc$ls180.v:2821$4059 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end - attribute \src "ls180.v:2819.32-2819.66" - process $proc$ls180.v:2819$4062 + attribute \src "ls180.v:2822.32-2822.66" + process $proc$ls180.v:2822$4060 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end - attribute \src "ls180.v:282.5-282.39" - process $proc$ls180.v:282$3181 - assign { } { } - assign $1\main_interface2_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2820.32-2820.66" - process $proc$ls180.v:2820$4063 + attribute \src "ls180.v:2823.32-2823.66" + process $proc$ls180.v:2823$4061 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end - attribute \src "ls180.v:2821.32-2821.66" - process $proc$ls180.v:2821$4064 + attribute \src "ls180.v:2824.32-2824.66" + process $proc$ls180.v:2824$4062 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end - attribute \src "ls180.v:2822.32-2822.66" - process $proc$ls180.v:2822$4065 + attribute \src "ls180.v:2825.32-2825.66" + process $proc$ls180.v:2825$4063 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end - attribute \src "ls180.v:2823.32-2823.66" - process $proc$ls180.v:2823$4066 + attribute \src "ls180.v:2826.32-2826.66" + process $proc$ls180.v:2826$4064 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end - attribute \src "ls180.v:2824.32-2824.66" - process $proc$ls180.v:2824$4067 + attribute \src "ls180.v:2827.32-2827.66" + process $proc$ls180.v:2827$4065 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end - attribute \src "ls180.v:2825.32-2825.66" - process $proc$ls180.v:2825$4068 + attribute \src "ls180.v:2828.32-2828.66" + process $proc$ls180.v:2828$4066 assign { } { } assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end - attribute \src "ls180.v:2826.32-2826.66" - process $proc$ls180.v:2826$4069 + attribute \src "ls180.v:2829.32-2829.66" + process $proc$ls180.v:2829$4067 assign { } { } assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end - attribute \src "ls180.v:2827.32-2827.66" - process $proc$ls180.v:2827$4070 + attribute \src "ls180.v:2830.32-2830.66" + process $proc$ls180.v:2830$4068 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end - attribute \src "ls180.v:2828.32-2828.66" - process $proc$ls180.v:2828$4071 + attribute \src "ls180.v:2831.32-2831.66" + process $proc$ls180.v:2831$4069 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end - attribute \src "ls180.v:2829.32-2829.66" - process $proc$ls180.v:2829$4072 + attribute \src "ls180.v:2832.32-2832.66" + process $proc$ls180.v:2832$4070 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end - attribute \src "ls180.v:2830.32-2830.66" - process $proc$ls180.v:2830$4073 + attribute \src "ls180.v:2833.32-2833.66" + process $proc$ls180.v:2833$4071 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end - attribute \src "ls180.v:2831.32-2831.66" - process $proc$ls180.v:2831$4074 + attribute \src "ls180.v:2834.32-2834.66" + process $proc$ls180.v:2834$4072 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end - attribute \src "ls180.v:2832.32-2832.66" - process $proc$ls180.v:2832$4075 + attribute \src "ls180.v:2835.32-2835.66" + process $proc$ls180.v:2835$4073 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end - attribute \src "ls180.v:2833.32-2833.66" - process $proc$ls180.v:2833$4076 + attribute \src "ls180.v:2836.32-2836.66" + process $proc$ls180.v:2836$4074 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end - attribute \src "ls180.v:2834.32-2834.66" - process $proc$ls180.v:2834$4077 + attribute \src "ls180.v:2837.32-2837.66" + process $proc$ls180.v:2837$4075 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end - attribute \src "ls180.v:2835.32-2835.66" - process $proc$ls180.v:2835$4078 + attribute \src "ls180.v:2838.32-2838.66" + process $proc$ls180.v:2838$4076 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end - attribute \src "ls180.v:2836.32-2836.67" - process $proc$ls180.v:2836$4079 + attribute \src "ls180.v:2839.32-2839.67" + process $proc$ls180.v:2839$4077 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end - attribute \src "ls180.v:2837.32-2837.67" - process $proc$ls180.v:2837$4080 + attribute \src "ls180.v:2840.32-2840.67" + process $proc$ls180.v:2840$4078 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end - attribute \src "ls180.v:2838.32-2838.67" - process $proc$ls180.v:2838$4081 + attribute \src "ls180.v:2841.32-2841.67" + process $proc$ls180.v:2841$4079 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end - attribute \src "ls180.v:2839.32-2839.67" - process $proc$ls180.v:2839$4082 + attribute \src "ls180.v:2842.32-2842.67" + process $proc$ls180.v:2842$4080 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end - attribute \src "ls180.v:2840.32-2840.67" - process $proc$ls180.v:2840$4083 + attribute \src "ls180.v:2843.32-2843.67" + process $proc$ls180.v:2843$4081 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end - attribute \src "ls180.v:2841.32-2841.67" - process $proc$ls180.v:2841$4084 + attribute \src "ls180.v:2844.32-2844.67" + process $proc$ls180.v:2844$4082 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end - attribute \src "ls180.v:2842.32-2842.67" - process $proc$ls180.v:2842$4085 + attribute \src "ls180.v:2845.32-2845.67" + process $proc$ls180.v:2845$4083 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end - attribute \src "ls180.v:2843.32-2843.67" - process $proc$ls180.v:2843$4086 + attribute \src "ls180.v:2846.32-2846.67" + process $proc$ls180.v:2846$4084 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end - attribute \src "ls180.v:2844.32-2844.67" - process $proc$ls180.v:2844$4087 + attribute \src "ls180.v:2847.32-2847.67" + process $proc$ls180.v:2847$4085 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end - attribute \src "ls180.v:2845.32-2845.67" - process $proc$ls180.v:2845$4088 + attribute \src "ls180.v:2848.32-2848.67" + process $proc$ls180.v:2848$4086 assign { } { } assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end - attribute \src "ls180.v:2846.32-2846.67" - process $proc$ls180.v:2846$4089 + attribute \src "ls180.v:2849.32-2849.67" + process $proc$ls180.v:2849$4087 assign { } { } assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end - attribute \src "ls180.v:2847.32-2847.67" - process $proc$ls180.v:2847$4090 + attribute \src "ls180.v:285.5-285.39" + process $proc$ls180.v:285$3179 + assign { } { } + assign $1\main_interface2_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2850.32-2850.67" + process $proc$ls180.v:2850$4088 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end - attribute \src "ls180.v:2848.32-2848.67" - process $proc$ls180.v:2848$4091 + attribute \src "ls180.v:2851.32-2851.67" + process $proc$ls180.v:2851$4089 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end - attribute \src "ls180.v:2849.32-2849.67" - process $proc$ls180.v:2849$4092 + attribute \src "ls180.v:2852.32-2852.67" + process $proc$ls180.v:2852$4090 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:286.5-286.39" - process $proc$ls180.v:286$3182 - assign { } { } - assign $0\main_interface2_ram_bus_err[0:0] 1'0 - sync always - update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:2884.1-2889.4" - process $proc$ls180.v:2884$49 + attribute \src "ls180.v:2887.1-2892.4" + process $proc$ls180.v:2887$49 assign { } { } assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } @@ -285719,19 +288220,19 @@ module \ls180 sync always update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:289.11-289.31" - process $proc$ls180.v:289$3183 + attribute \src "ls180.v:289.5-289.39" + process $proc$ls180.v:289$3180 assign { } { } - assign $1\main_sram2_we[7:0] 8'00000000 + assign $0\main_interface2_ram_bus_err[0:0] 1'0 sync always + update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] sync init - update \main_sram2_we $1\main_sram2_we[7:0] end - attribute \src "ls180.v:2891.1-2901.4" - process $proc$ls180.v:2891$51 + attribute \src "ls180.v:2894.1-2904.4" + process $proc$ls180.v:2894$51 assign { } { } assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 - attribute \src "ls180.v:2893.2-2900.9" + attribute \src "ls180.v:2896.2-2903.9" switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -285744,8 +288245,8 @@ module \ls180 sync always update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:2903.1-2949.4" - process $proc$ls180.v:2903$52 + attribute \src "ls180.v:2906.1-2952.4" + process $proc$ls180.v:2906$52 assign { } { } assign { } { } assign { } { } @@ -285764,15 +288265,15 @@ module \ls180 assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 assign $0\main_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2915.2-2948.9" + attribute \src "ls180.v:2918.2-2951.9" switch \builder_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } - attribute \src "ls180.v:2918.4-2925.11" + attribute \src "ls180.v:2921.4-2928.11" switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -285782,23 +288283,23 @@ module \ls180 assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2926.4-2939.7" - switch $and$ls180.v:2926$53_Y - attribute \src "ls180.v:2926.8-2926.91" + attribute \src "ls180.v:2929.4-2942.7" + switch $and$ls180.v:2929$53_Y + attribute \src "ls180.v:2929.8-2929.91" case 1'1 - assign $0\main_converter0_skip[0:0] $eq$ls180.v:2927$54_Y + assign $0\main_converter0_skip[0:0] $eq$ls180.v:2930$54_Y assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2929$55_Y - assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2930$56_Y - attribute \src "ls180.v:2931.5-2938.8" - switch $or$ls180.v:2931$57_Y - attribute \src "ls180.v:2931.9-2931.72" + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2932$55_Y + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2933$56_Y + attribute \src "ls180.v:2934.5-2941.8" + switch $or$ls180.v:2934$57_Y + attribute \src "ls180.v:2934.9-2934.72" case 1'1 - assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2932$58_Y + assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2935$58_Y assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2934.6-2937.9" - switch $eq$ls180.v:2934$59_Y - attribute \src "ls180.v:2934.10-2934.43" + attribute \src "ls180.v:2937.6-2940.9" + switch $eq$ls180.v:2937$59_Y + attribute \src "ls180.v:2937.10-2937.43" case 1'1 assign $0\main_interface0_converted_interface_ack[0:0] 1'1 assign $0\builder_converter0_next_state[0:0] 1'0 @@ -285812,9 +288313,9 @@ module \ls180 case assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2944.4-2946.7" - switch $and$ls180.v:2944$60_Y - attribute \src "ls180.v:2944.8-2944.91" + attribute \src "ls180.v:2947.4-2949.7" + switch $and$ls180.v:2947$60_Y + attribute \src "ls180.v:2947.8-2947.91" case 1'1 assign $0\builder_converter0_next_state[0:0] 1'1 case @@ -285832,11 +288333,19 @@ module \ls180 update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:2951.1-2961.4" - process $proc$ls180.v:2951$62 + attribute \src "ls180.v:292.11-292.31" + process $proc$ls180.v:292$3181 + assign { } { } + assign $1\main_sram2_we[7:0] 8'00000000 + sync always + sync init + update \main_sram2_we $1\main_sram2_we[7:0] + end + attribute \src "ls180.v:2954.1-2964.4" + process $proc$ls180.v:2954$62 assign { } { } assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 - attribute \src "ls180.v:2953.2-2960.9" + attribute \src "ls180.v:2956.2-2963.9" switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -285849,8 +288358,8 @@ module \ls180 sync always update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:2963.1-3009.4" - process $proc$ls180.v:2963$63 + attribute \src "ls180.v:2966.1-3012.4" + process $proc$ls180.v:2966$63 assign { } { } assign { } { } assign { } { } @@ -285861,23 +288370,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 assign $0\main_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + assign { } { } + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2975.2-3008.9" + attribute \src "ls180.v:2978.2-3011.9" switch \builder_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } - attribute \src "ls180.v:2978.4-2985.11" + attribute \src "ls180.v:2981.4-2988.11" switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -285887,23 +288396,23 @@ module \ls180 assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2986.4-2999.7" - switch $and$ls180.v:2986$64_Y - attribute \src "ls180.v:2986.8-2986.91" + attribute \src "ls180.v:2989.4-3002.7" + switch $and$ls180.v:2989$64_Y + attribute \src "ls180.v:2989.8-2989.91" case 1'1 - assign $0\main_converter1_skip[0:0] $eq$ls180.v:2987$65_Y + assign $0\main_converter1_skip[0:0] $eq$ls180.v:2990$65_Y assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2989$66_Y - assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2990$67_Y - attribute \src "ls180.v:2991.5-2998.8" - switch $or$ls180.v:2991$68_Y - attribute \src "ls180.v:2991.9-2991.72" + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2992$66_Y + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2993$67_Y + attribute \src "ls180.v:2994.5-3001.8" + switch $or$ls180.v:2994$68_Y + attribute \src "ls180.v:2994.9-2994.72" case 1'1 - assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2992$69_Y + assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2995$69_Y assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2994.6-2997.9" - switch $eq$ls180.v:2994$70_Y - attribute \src "ls180.v:2994.10-2994.43" + attribute \src "ls180.v:2997.6-3000.9" + switch $eq$ls180.v:2997$70_Y + attribute \src "ls180.v:2997.10-2997.43" case 1'1 assign $0\main_interface1_converted_interface_ack[0:0] 1'1 assign $0\builder_converter1_next_state[0:0] 1'0 @@ -285917,9 +288426,9 @@ module \ls180 case assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3004.4-3006.7" - switch $and$ls180.v:3004$71_Y - attribute \src "ls180.v:3004.8-3004.91" + attribute \src "ls180.v:3007.4-3009.7" + switch $and$ls180.v:3007$71_Y + attribute \src "ls180.v:3007.8-3007.91" case 1'1 assign $0\builder_converter1_next_state[0:0] 1'1 case @@ -285937,27 +288446,19 @@ module \ls180 update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:297.5-297.39" - process $proc$ls180.v:297$3184 + attribute \src "ls180.v:300.5-300.39" + process $proc$ls180.v:300$3182 assign { } { } assign $1\main_interface3_ram_bus_ack[0:0] 1'0 sync always sync init update \main_interface3_ram_bus_ack $1\main_interface3_ram_bus_ack[0:0] end - attribute \src "ls180.v:301.5-301.39" - process $proc$ls180.v:301$3185 - assign { } { } - assign $0\main_interface3_ram_bus_err[0:0] 1'0 - sync always - update \main_interface3_ram_bus_err $0\main_interface3_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:3011.1-3021.4" - process $proc$ls180.v:3011$73 + attribute \src "ls180.v:3014.1-3024.4" + process $proc$ls180.v:3014$73 assign { } { } assign $0\main_wb_sdram_dat_w[31:0] 0 - attribute \src "ls180.v:3013.2-3020.9" + attribute \src "ls180.v:3016.2-3023.9" switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -285970,8 +288471,8 @@ module \ls180 sync always update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] end - attribute \src "ls180.v:3023.1-3069.4" - process $proc$ls180.v:3023$74 + attribute \src "ls180.v:3026.1-3072.4" + process $proc$ls180.v:3026$74 assign { } { } assign { } { } assign { } { } @@ -285982,9 +288483,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_wb_sdram_we[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_wb_sdram_we[0:0] 1'0 assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 assign $0\main_wb_sdram_sel[3:0] 4'0000 assign $0\main_wb_sdram_cyc[0:0] 1'0 @@ -285992,13 +288492,14 @@ module \ls180 assign $0\main_socbushandler_skip[0:0] 1'0 assign { } { } assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:3035.2-3068.9" + attribute \src "ls180.v:3038.2-3071.9" switch \builder_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } - attribute \src "ls180.v:3038.4-3045.11" + attribute \src "ls180.v:3041.4-3048.11" switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -286008,23 +288509,23 @@ module \ls180 assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] case end - attribute \src "ls180.v:3046.4-3059.7" - switch $and$ls180.v:3046$75_Y - attribute \src "ls180.v:3046.8-3046.97" + attribute \src "ls180.v:3049.4-3062.7" + switch $and$ls180.v:3049$75_Y + attribute \src "ls180.v:3049.8-3049.97" case 1'1 - assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3047$76_Y + assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3050$76_Y assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we - assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3049$77_Y - assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3050$78_Y - attribute \src "ls180.v:3051.5-3058.8" - switch $or$ls180.v:3051$79_Y - attribute \src "ls180.v:3051.9-3051.54" + assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3052$77_Y + assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3053$78_Y + attribute \src "ls180.v:3054.5-3061.8" + switch $or$ls180.v:3054$79_Y + attribute \src "ls180.v:3054.9-3054.54" case 1'1 - assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3052$80_Y + assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3055$80_Y assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3054.6-3057.9" - switch $eq$ls180.v:3054$81_Y - attribute \src "ls180.v:3054.10-3054.46" + attribute \src "ls180.v:3057.6-3060.9" + switch $eq$ls180.v:3057$81_Y + attribute \src "ls180.v:3057.10-3057.46" case 1'1 assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 assign $0\builder_converter2_next_state[0:0] 1'0 @@ -286038,9 +288539,9 @@ module \ls180 case assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3064.4-3066.7" - switch $and$ls180.v:3064$82_Y - attribute \src "ls180.v:3064.8-3064.97" + attribute \src "ls180.v:3067.4-3069.7" + switch $and$ls180.v:3067$82_Y + attribute \src "ls180.v:3067.8-3067.97" case 1'1 assign $0\builder_converter2_next_state[0:0] 1'1 case @@ -286058,36 +288559,44 @@ module \ls180 update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:304.11-304.31" - process $proc$ls180.v:304$3186 + attribute \src "ls180.v:304.5-304.39" + process $proc$ls180.v:304$3183 + assign { } { } + assign $0\main_interface3_ram_bus_err[0:0] 1'0 + sync always + update \main_interface3_ram_bus_err $0\main_interface3_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:307.11-307.31" + process $proc$ls180.v:307$3184 assign { } { } assign $1\main_sram3_we[7:0] 8'00000000 sync always sync init update \main_sram3_we $1\main_sram3_we[7:0] end - attribute \src "ls180.v:3072.1-3082.4" - process $proc$ls180.v:3072$83 + attribute \src "ls180.v:3075.1-3085.4" + process $proc$ls180.v:3075$83 assign { } { } assign { } { } - assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3074$86_Y - assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3075$89_Y - assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3076$92_Y - assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3077$95_Y - assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3078$98_Y - assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3079$101_Y - assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3080$104_Y - assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3081$107_Y + assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3077$86_Y + assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3078$89_Y + assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3079$92_Y + assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3080$95_Y + assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3081$98_Y + assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3082$101_Y + assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3083$104_Y + assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3084$107_Y sync always update \main_libresocsim_we $0\main_libresocsim_we[7:0] end - attribute \src "ls180.v:3088.1-3093.4" - process $proc$ls180.v:3088$109 + attribute \src "ls180.v:3091.1-3096.4" + process $proc$ls180.v:3091$109 assign { } { } assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:3090.2-3092.5" - switch $and$ls180.v:3090$110_Y - attribute \src "ls180.v:3090.6-3090.90" + attribute \src "ls180.v:3093.2-3095.5" + switch $and$ls180.v:3093$110_Y + attribute \src "ls180.v:3093.6-3093.90" case 1'1 assign $0\main_libresocsim_zero_clear[0:0] 1'1 case @@ -286095,100 +288604,84 @@ module \ls180 sync always update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:3097.1-3107.4" - process $proc$ls180.v:3097$112 + attribute \src "ls180.v:3100.1-3110.4" + process $proc$ls180.v:3100$112 assign { } { } assign { } { } - assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3099$115_Y - assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3100$118_Y - assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3101$121_Y - assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3102$124_Y - assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3103$127_Y - assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3104$130_Y - assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3105$133_Y - assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3106$136_Y + assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3102$115_Y + assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3103$118_Y + assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3104$121_Y + assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3105$124_Y + assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3106$127_Y + assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3107$130_Y + assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3108$133_Y + assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3109$136_Y sync always update \main_sram0_we $0\main_sram0_we[7:0] end - attribute \src "ls180.v:3111.1-3121.4" - process $proc$ls180.v:3111$137 + attribute \src "ls180.v:3114.1-3124.4" + process $proc$ls180.v:3114$137 assign { } { } assign { } { } - assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3113$140_Y - assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3114$143_Y - assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3115$146_Y - assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3116$149_Y - assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3117$152_Y - assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3118$155_Y - assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3119$158_Y - assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3120$161_Y + assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3116$140_Y + assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3117$143_Y + assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3118$146_Y + assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3119$149_Y + assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3120$152_Y + assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3121$155_Y + assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3122$158_Y + assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3123$161_Y sync always update \main_sram1_we $0\main_sram1_we[7:0] end - attribute \src "ls180.v:312.5-312.51" - process $proc$ls180.v:312$3187 - assign { } { } - assign $1\main_interface0_converted_interface_ack[0:0] 1'0 - sync always - sync init - update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] - end - attribute \src "ls180.v:3125.1-3135.4" - process $proc$ls180.v:3125$162 + attribute \src "ls180.v:3128.1-3138.4" + process $proc$ls180.v:3128$162 assign { } { } assign { } { } - assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3127$165_Y - assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3128$168_Y - assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3129$171_Y - assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3130$174_Y - assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3131$177_Y - assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3132$180_Y - assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3133$183_Y - assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3134$186_Y + assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3130$165_Y + assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3131$168_Y + assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3132$171_Y + assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3133$174_Y + assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3134$177_Y + assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3135$180_Y + assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3136$183_Y + assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3137$186_Y sync always update \main_sram2_we $0\main_sram2_we[7:0] end - attribute \src "ls180.v:3139.1-3149.4" - process $proc$ls180.v:3139$187 + attribute \src "ls180.v:3142.1-3152.4" + process $proc$ls180.v:3142$187 assign { } { } assign { } { } - assign $0\main_sram3_we[7:0] [0] $and$ls180.v:3141$190_Y - assign $0\main_sram3_we[7:0] [1] $and$ls180.v:3142$193_Y - assign $0\main_sram3_we[7:0] [2] $and$ls180.v:3143$196_Y - assign $0\main_sram3_we[7:0] [3] $and$ls180.v:3144$199_Y - assign $0\main_sram3_we[7:0] [4] $and$ls180.v:3145$202_Y - assign $0\main_sram3_we[7:0] [5] $and$ls180.v:3146$205_Y - assign $0\main_sram3_we[7:0] [6] $and$ls180.v:3147$208_Y - assign $0\main_sram3_we[7:0] [7] $and$ls180.v:3148$211_Y + assign $0\main_sram3_we[7:0] [0] $and$ls180.v:3144$190_Y + assign $0\main_sram3_we[7:0] [1] $and$ls180.v:3145$193_Y + assign $0\main_sram3_we[7:0] [2] $and$ls180.v:3146$196_Y + assign $0\main_sram3_we[7:0] [3] $and$ls180.v:3147$199_Y + assign $0\main_sram3_we[7:0] [4] $and$ls180.v:3148$202_Y + assign $0\main_sram3_we[7:0] [5] $and$ls180.v:3149$205_Y + assign $0\main_sram3_we[7:0] [6] $and$ls180.v:3150$208_Y + assign $0\main_sram3_we[7:0] [7] $and$ls180.v:3151$211_Y sync always update \main_sram3_we $0\main_sram3_we[7:0] end - attribute \src "ls180.v:316.5-316.51" - process $proc$ls180.v:316$3188 + attribute \src "ls180.v:315.5-315.51" + process $proc$ls180.v:315$3185 assign { } { } - assign $0\main_interface0_converted_interface_err[0:0] 1'0 - sync always - update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:317.5-317.32" - process $proc$ls180.v:317$3189 - assign { } { } - assign $1\main_converter0_skip[0:0] 1'0 + assign $1\main_interface0_converted_interface_ack[0:0] 1'0 sync always sync init - update \main_converter0_skip $1\main_converter0_skip[0:0] + update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] end - attribute \src "ls180.v:318.5-318.35" - process $proc$ls180.v:318$3190 + attribute \src "ls180.v:319.5-319.51" + process $proc$ls180.v:319$3186 assign { } { } - assign $1\main_converter0_counter[0:0] 1'0 + assign $0\main_interface0_converted_interface_err[0:0] 1'0 sync always + update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] sync init - update \main_converter0_counter $1\main_converter0_counter[0:0] end - attribute \src "ls180.v:3188.1-3242.4" - process $proc$ls180.v:3188$212 + attribute \src "ls180.v:3191.1-3245.4" + process $proc$ls180.v:3191$212 assign { } { } assign { } { } assign { } { } @@ -286225,9 +288718,9 @@ module \ls180 assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - attribute \src "ls180.v:3207.2-3241.5" + attribute \src "ls180.v:3210.2-3244.5" switch \main_sdram_sel - attribute \src "ls180.v:3207.6-3207.20" + attribute \src "ls180.v:3210.6-3210.20" case 1'1 assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank @@ -286245,7 +288738,7 @@ module \ls180 assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3224.6-3224.10" + attribute \src "ls180.v:3227.6-3227.10" case assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank @@ -286284,33 +288777,49 @@ module \ls180 update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:320.12-320.41" - process $proc$ls180.v:320$3191 + attribute \src "ls180.v:320.5-320.32" + process $proc$ls180.v:320$3187 + assign { } { } + assign $1\main_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_converter0_skip $1\main_converter0_skip[0:0] + end + attribute \src "ls180.v:321.5-321.35" + process $proc$ls180.v:321$3188 + assign { } { } + assign $1\main_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_converter0_counter $1\main_converter0_counter[0:0] + end + attribute \src "ls180.v:323.12-323.41" + process $proc$ls180.v:323$3189 assign { } { } assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] end - attribute \src "ls180.v:3246.1-3262.4" - process $proc$ls180.v:3246$213 + attribute \src "ls180.v:3249.1-3265.4" + process $proc$ls180.v:3249$213 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - attribute \src "ls180.v:3251.2-3261.5" + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + attribute \src "ls180.v:3254.2-3264.5" switch \main_sdram_command_issue_re - attribute \src "ls180.v:3251.6-3251.33" + attribute \src "ls180.v:3254.6-3254.33" case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3252$214_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3253$215_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3254$216_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3255$217_Y - attribute \src "ls180.v:3256.6-3256.10" + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3255$214_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3256$215_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3257$216_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3258$217_Y + attribute \src "ls180.v:3259.6-3259.10" case assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 @@ -286323,17 +288832,16 @@ module \ls180 update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:327.5-327.51" - process $proc$ls180.v:327$3192 + attribute \src "ls180.v:330.5-330.51" + process $proc$ls180.v:330$3190 assign { } { } assign $1\main_interface1_converted_interface_ack[0:0] 1'0 sync always sync init update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] end - attribute \src "ls180.v:3305.1-3335.4" - process $proc$ls180.v:3305$226 - assign { } { } + attribute \src "ls180.v:3308.1-3338.4" + process $proc$ls180.v:3308$226 assign { } { } assign { } { } assign { } { } @@ -286341,15 +288849,16 @@ module \ls180 assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign { } { } assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3311.2-3334.9" + attribute \src "ls180.v:3314.2-3337.9" switch \builder_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3314.4-3317.7" + attribute \src "ls180.v:3317.4-3320.7" switch \main_sdram_cmd_ready - attribute \src "ls180.v:3314.8-3314.28" + attribute \src "ls180.v:3317.8-3317.28" case 1'1 assign $0\main_sdram_sequencer_start0[0:0] 1'1 assign $0\builder_refresher_next_state[1:0] 2'10 @@ -286358,9 +288867,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3321.4-3325.7" + attribute \src "ls180.v:3324.4-3328.7" switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3321.8-3321.34" + attribute \src "ls180.v:3324.8-3324.34" case 1'1 assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\main_sdram_cmd_last[0:0] 1'1 @@ -286369,13 +288878,13 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3328.4-3332.7" + attribute \src "ls180.v:3331.4-3335.7" switch 1'1 - attribute \src "ls180.v:3328.8-3328.12" + attribute \src "ls180.v:3331.8-3331.12" case 1'1 - attribute \src "ls180.v:3329.5-3331.8" + attribute \src "ls180.v:3332.5-3334.8" switch \main_sdram_wants_refresh - attribute \src "ls180.v:3329.9-3329.33" + attribute \src "ls180.v:3332.9-3332.33" case 1'1 assign $0\builder_refresher_next_state[1:0] 2'01 case @@ -286389,67 +288898,59 @@ module \ls180 update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:331.5-331.51" - process $proc$ls180.v:331$3193 + attribute \src "ls180.v:334.5-334.51" + process $proc$ls180.v:334$3191 assign { } { } assign $0\main_interface1_converted_interface_err[0:0] 1'0 sync always update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] sync init end - attribute \src "ls180.v:332.5-332.32" - process $proc$ls180.v:332$3194 + attribute \src "ls180.v:335.5-335.32" + process $proc$ls180.v:335$3192 assign { } { } assign $1\main_converter1_skip[0:0] 1'0 sync always sync init update \main_converter1_skip $1\main_converter1_skip[0:0] end - attribute \src "ls180.v:333.5-333.35" - process $proc$ls180.v:333$3195 - assign { } { } - assign $1\main_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_converter1_counter $1\main_converter1_counter[0:0] - end - attribute \src "ls180.v:335.12-335.41" - process $proc$ls180.v:335$3196 - assign { } { } - assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] - end - attribute \src "ls180.v:3350.1-3357.4" - process $proc$ls180.v:3350$230 + attribute \src "ls180.v:3353.1-3360.4" + process $proc$ls180.v:3353$230 assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3352.2-3356.5" + attribute \src "ls180.v:3355.2-3359.5" switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3352.6-3352.48" + attribute \src "ls180.v:3355.6-3355.48" case 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3354.6-3354.10" + attribute \src "ls180.v:3357.6-3357.10" case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3355$232_Y + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3358$232_Y end sync always update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:3361.1-3368.4" - process $proc$ls180.v:3361$239 + attribute \src "ls180.v:336.5-336.35" + process $proc$ls180.v:336$3193 + assign { } { } + assign $1\main_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_converter1_counter $1\main_converter1_counter[0:0] + end + attribute \src "ls180.v:3364.1-3371.4" + process $proc$ls180.v:3364$239 assign { } { } assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3363.2-3367.5" - switch $and$ls180.v:3363$240_Y - attribute \src "ls180.v:3363.6-3363.115" + attribute \src "ls180.v:3366.2-3370.5" + switch $and$ls180.v:3366$240_Y + attribute \src "ls180.v:3366.6-3366.115" case 1'1 - attribute \src "ls180.v:3364.3-3366.6" - switch $ne$ls180.v:3364$241_Y - attribute \src "ls180.v:3364.7-3364.143" + attribute \src "ls180.v:3367.3-3369.6" + switch $ne$ls180.v:3367$241_Y + attribute \src "ls180.v:3367.7-3367.143" case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3365$242_Y + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3368$242_Y case end case @@ -286457,32 +288958,32 @@ module \ls180 sync always update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:3383.1-3390.4" - process $proc$ls180.v:3383$243 + attribute \src "ls180.v:338.12-338.41" + process $proc$ls180.v:338$3194 + assign { } { } + assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] + end + attribute \src "ls180.v:3386.1-3393.4" + process $proc$ls180.v:3386$243 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3385.2-3389.5" + attribute \src "ls180.v:3388.2-3392.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3385.6-3385.58" + attribute \src "ls180.v:3388.6-3388.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3386$244_Y - attribute \src "ls180.v:3387.6-3387.10" + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3389$244_Y + attribute \src "ls180.v:3390.6-3390.10" case assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:339.5-339.24" - process $proc$ls180.v:339$3197 - assign { } { } - assign $1\main_int_rst[0:0] 1'1 - sync always - sync init - update \main_int_rst $1\main_int_rst[0:0] - end - attribute \src "ls180.v:3399.1-3492.4" - process $proc$ls180.v:3399$252 + attribute \src "ls180.v:3402.1-3495.4" + process $proc$ls180.v:3402$252 assign { } { } assign { } { } assign { } { } @@ -286497,8 +288998,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 @@ -286511,23 +289010,25 @@ module \ls180 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3415.2-3491.9" + attribute \src "ls180.v:3418.2-3494.9" switch \builder_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3417.4-3425.7" - switch $and$ls180.v:3417$253_Y - attribute \src "ls180.v:3417.8-3417.87" + attribute \src "ls180.v:3420.4-3428.7" + switch $and$ls180.v:3420$253_Y + attribute \src "ls180.v:3420.8-3420.87" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3419.5-3421.8" + attribute \src "ls180.v:3422.5-3424.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3419.9-3419.42" + attribute \src "ls180.v:3422.9-3422.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case @@ -286537,27 +289038,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3429.4-3431.7" - switch $and$ls180.v:3429$254_Y - attribute \src "ls180.v:3429.8-3429.87" + attribute \src "ls180.v:3432.4-3434.7" + switch $and$ls180.v:3432$254_Y + attribute \src "ls180.v:3432.8-3432.87" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3435.4-3444.7" + attribute \src "ls180.v:3438.4-3447.7" switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3435.8-3435.44" + attribute \src "ls180.v:3438.8-3438.44" case 1'1 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3440.5-3442.8" + attribute \src "ls180.v:3443.5-3445.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3440.9-3440.42" + attribute \src "ls180.v:3443.9-3443.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'110 case @@ -286568,16 +289069,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3447.4-3449.7" + attribute \src "ls180.v:3450.4-3452.7" switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3447.8-3447.45" + attribute \src "ls180.v:3450.8-3450.45" case 1'1 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3452.4-3454.7" - switch $not$ls180.v:3452$255_Y - attribute \src "ls180.v:3452.8-3452.46" + attribute \src "ls180.v:3455.4-3457.7" + switch $not$ls180.v:3455$255_Y + attribute \src "ls180.v:3455.8-3455.46" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'000 case @@ -286590,51 +289091,51 @@ module \ls180 assign $0\builder_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3463.4-3489.7" + attribute \src "ls180.v:3466.4-3492.7" switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3463.8-3463.43" + attribute \src "ls180.v:3466.8-3466.43" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3465.8-3465.12" + attribute \src "ls180.v:3468.8-3468.12" case - attribute \src "ls180.v:3466.5-3488.8" + attribute \src "ls180.v:3469.5-3491.8" switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3466.9-3466.56" + attribute \src "ls180.v:3469.9-3469.56" case 1'1 - attribute \src "ls180.v:3467.6-3487.9" + attribute \src "ls180.v:3470.6-3490.9" switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3467.10-3467.44" + attribute \src "ls180.v:3470.10-3470.44" case 1'1 - attribute \src "ls180.v:3468.7-3484.10" + attribute \src "ls180.v:3471.7-3487.10" switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3468.11-3468.42" + attribute \src "ls180.v:3471.11-3471.42" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3470.8-3477.11" + attribute \src "ls180.v:3473.8-3480.11" switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3470.12-3470.64" + attribute \src "ls180.v:3473.12-3473.64" case 1'1 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3474.12-3474.16" + attribute \src "ls180.v:3477.12-3477.16" case assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3479.8-3481.11" - switch $and$ls180.v:3479$256_Y - attribute \src "ls180.v:3479.12-3479.88" + attribute \src "ls180.v:3482.8-3484.11" + switch $and$ls180.v:3482$256_Y + attribute \src "ls180.v:3482.12-3482.88" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3482.11-3482.15" + attribute \src "ls180.v:3485.11-3485.15" case assign $0\builder_bankmachine0_next_state[2:0] 3'001 end - attribute \src "ls180.v:3485.10-3485.14" + attribute \src "ls180.v:3488.10-3488.14" case assign $0\builder_bankmachine0_next_state[2:0] 3'011 end @@ -286658,35 +289159,43 @@ module \ls180 update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:3507.1-3514.4" - process $proc$ls180.v:3507$260 + attribute \src "ls180.v:342.5-342.24" + process $proc$ls180.v:342$3195 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:3510.1-3517.4" + process $proc$ls180.v:3510$260 assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3509.2-3513.5" + attribute \src "ls180.v:3512.2-3516.5" switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3509.6-3509.48" + attribute \src "ls180.v:3512.6-3512.48" case 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3511.6-3511.10" + attribute \src "ls180.v:3514.6-3514.10" case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3512$262_Y + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3515$262_Y end sync always update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:3518.1-3525.4" - process $proc$ls180.v:3518$269 + attribute \src "ls180.v:3521.1-3528.4" + process $proc$ls180.v:3521$269 assign { } { } assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3520.2-3524.5" - switch $and$ls180.v:3520$270_Y - attribute \src "ls180.v:3520.6-3520.115" + attribute \src "ls180.v:3523.2-3527.5" + switch $and$ls180.v:3523$270_Y + attribute \src "ls180.v:3523.6-3523.115" case 1'1 - attribute \src "ls180.v:3521.3-3523.6" - switch $ne$ls180.v:3521$271_Y - attribute \src "ls180.v:3521.7-3521.143" + attribute \src "ls180.v:3524.3-3526.6" + switch $ne$ls180.v:3524$271_Y + attribute \src "ls180.v:3524.7-3524.143" case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3522$272_Y + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3525$272_Y case end case @@ -286694,40 +289203,24 @@ module \ls180 sync always update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:354.12-354.38" - process $proc$ls180.v:354$3198 - assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] - end - attribute \src "ls180.v:3540.1-3547.4" - process $proc$ls180.v:3540$273 + attribute \src "ls180.v:3543.1-3550.4" + process $proc$ls180.v:3543$273 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3542.2-3546.5" + attribute \src "ls180.v:3545.2-3549.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3542.6-3542.58" + attribute \src "ls180.v:3545.6-3545.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3543$274_Y - attribute \src "ls180.v:3544.6-3544.10" + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3546$274_Y + attribute \src "ls180.v:3547.6-3547.10" case assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:355.5-355.36" - process $proc$ls180.v:355$3199 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:3556.1-3649.4" - process $proc$ls180.v:3556$282 + attribute \src "ls180.v:3559.1-3652.4" + process $proc$ls180.v:3559$282 assign { } { } assign { } { } assign { } { } @@ -286742,8 +289235,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 @@ -286756,23 +289247,25 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3572.2-3648.9" + attribute \src "ls180.v:3575.2-3651.9" switch \builder_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3574.4-3582.7" - switch $and$ls180.v:3574$283_Y - attribute \src "ls180.v:3574.8-3574.87" + attribute \src "ls180.v:3577.4-3585.7" + switch $and$ls180.v:3577$283_Y + attribute \src "ls180.v:3577.8-3577.87" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3576.5-3578.8" + attribute \src "ls180.v:3579.5-3581.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3576.9-3576.42" + attribute \src "ls180.v:3579.9-3579.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case @@ -286782,27 +289275,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3586.4-3588.7" - switch $and$ls180.v:3586$284_Y - attribute \src "ls180.v:3586.8-3586.87" + attribute \src "ls180.v:3589.4-3591.7" + switch $and$ls180.v:3589$284_Y + attribute \src "ls180.v:3589.8-3589.87" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3592.4-3601.7" + attribute \src "ls180.v:3595.4-3604.7" switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3592.8-3592.44" + attribute \src "ls180.v:3595.8-3595.44" case 1'1 assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3597.5-3599.8" + attribute \src "ls180.v:3600.5-3602.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3597.9-3597.42" + attribute \src "ls180.v:3600.9-3600.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'110 case @@ -286813,16 +289306,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3604.4-3606.7" + attribute \src "ls180.v:3607.4-3609.7" switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3604.8-3604.45" + attribute \src "ls180.v:3607.8-3607.45" case 1'1 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3609.4-3611.7" - switch $not$ls180.v:3609$285_Y - attribute \src "ls180.v:3609.8-3609.46" + attribute \src "ls180.v:3612.4-3614.7" + switch $not$ls180.v:3612$285_Y + attribute \src "ls180.v:3612.8-3612.46" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'000 case @@ -286835,51 +289328,51 @@ module \ls180 assign $0\builder_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3620.4-3646.7" + attribute \src "ls180.v:3623.4-3649.7" switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3620.8-3620.43" + attribute \src "ls180.v:3623.8-3623.43" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3622.8-3622.12" + attribute \src "ls180.v:3625.8-3625.12" case - attribute \src "ls180.v:3623.5-3645.8" + attribute \src "ls180.v:3626.5-3648.8" switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3623.9-3623.56" + attribute \src "ls180.v:3626.9-3626.56" case 1'1 - attribute \src "ls180.v:3624.6-3644.9" + attribute \src "ls180.v:3627.6-3647.9" switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3624.10-3624.44" + attribute \src "ls180.v:3627.10-3627.44" case 1'1 - attribute \src "ls180.v:3625.7-3641.10" + attribute \src "ls180.v:3628.7-3644.10" switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3625.11-3625.42" + attribute \src "ls180.v:3628.11-3628.42" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3627.8-3634.11" + attribute \src "ls180.v:3630.8-3637.11" switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3627.12-3627.64" + attribute \src "ls180.v:3630.12-3630.64" case 1'1 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3631.12-3631.16" + attribute \src "ls180.v:3634.12-3634.16" case assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3636.8-3638.11" - switch $and$ls180.v:3636$286_Y - attribute \src "ls180.v:3636.12-3636.88" + attribute \src "ls180.v:3639.8-3641.11" + switch $and$ls180.v:3639$286_Y + attribute \src "ls180.v:3639.12-3639.88" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3639.11-3639.15" + attribute \src "ls180.v:3642.11-3642.15" case assign $0\builder_bankmachine1_next_state[2:0] 3'001 end - attribute \src "ls180.v:3642.10-3642.14" + attribute \src "ls180.v:3645.10-3645.14" case assign $0\builder_bankmachine1_next_state[2:0] 3'011 end @@ -286903,83 +289396,91 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:356.11-356.32" - process $proc$ls180.v:356$3200 + attribute \src "ls180.v:357.12-357.38" + process $proc$ls180.v:357$3196 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:358.5-358.36" + process $proc$ls180.v:358$3197 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:359.11-359.32" + process $proc$ls180.v:359$3198 assign { } { } assign $1\main_rddata_en[2:0] 3'000 sync always sync init update \main_rddata_en $1\main_rddata_en[2:0] end - attribute \src "ls180.v:359.5-359.36" - process $proc$ls180.v:359$3201 + attribute \src "ls180.v:362.5-362.36" + process $proc$ls180.v:362$3199 assign { } { } assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 sync always sync init update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] end - attribute \src "ls180.v:360.5-360.35" - process $proc$ls180.v:360$3202 + attribute \src "ls180.v:363.5-363.35" + process $proc$ls180.v:363$3200 assign { } { } assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 sync always sync init update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] end - attribute \src "ls180.v:361.5-361.36" - process $proc$ls180.v:361$3203 + attribute \src "ls180.v:364.5-364.36" + process $proc$ls180.v:364$3201 assign { } { } assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 sync always sync init update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:362.5-362.35" - process $proc$ls180.v:362$3204 + attribute \src "ls180.v:365.5-365.35" + process $proc$ls180.v:365$3202 assign { } { } assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 sync always sync init update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:366.5-366.36" - process $proc$ls180.v:366$3205 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:3664.1-3671.4" - process $proc$ls180.v:3664$290 + attribute \src "ls180.v:3667.1-3674.4" + process $proc$ls180.v:3667$290 assign { } { } assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3666.2-3670.5" + attribute \src "ls180.v:3669.2-3673.5" switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3666.6-3666.48" + attribute \src "ls180.v:3669.6-3669.48" case 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3668.6-3668.10" + attribute \src "ls180.v:3671.6-3671.10" case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3669$292_Y + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3672$292_Y end sync always update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:3675.1-3682.4" - process $proc$ls180.v:3675$299 + attribute \src "ls180.v:3678.1-3685.4" + process $proc$ls180.v:3678$299 assign { } { } assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3677.2-3681.5" - switch $and$ls180.v:3677$300_Y - attribute \src "ls180.v:3677.6-3677.115" + attribute \src "ls180.v:3680.2-3684.5" + switch $and$ls180.v:3680$300_Y + attribute \src "ls180.v:3680.6-3680.115" case 1'1 - attribute \src "ls180.v:3678.3-3680.6" - switch $ne$ls180.v:3678$301_Y - attribute \src "ls180.v:3678.7-3678.143" + attribute \src "ls180.v:3681.3-3683.6" + switch $ne$ls180.v:3681$301_Y + attribute \src "ls180.v:3681.7-3681.143" case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3679$302_Y + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3682$302_Y case end case @@ -286987,32 +289488,32 @@ module \ls180 sync always update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:3697.1-3704.4" - process $proc$ls180.v:3697$303 + attribute \src "ls180.v:369.5-369.36" + process $proc$ls180.v:369$3203 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:3700.1-3707.4" + process $proc$ls180.v:3700$303 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3699.2-3703.5" + attribute \src "ls180.v:3702.2-3706.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3699.6-3699.58" + attribute \src "ls180.v:3702.6-3702.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3700$304_Y - attribute \src "ls180.v:3701.6-3701.10" + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3703$304_Y + attribute \src "ls180.v:3704.6-3704.10" case assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:371.12-371.45" - process $proc$ls180.v:371$3206 - assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] - end - attribute \src "ls180.v:3713.1-3806.4" - process $proc$ls180.v:3713$312 + attribute \src "ls180.v:3716.1-3809.4" + process $proc$ls180.v:3716$312 assign { } { } assign { } { } assign { } { } @@ -287027,37 +289528,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3729.2-3805.9" + attribute \src "ls180.v:3732.2-3808.9" switch \builder_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3731.4-3739.7" - switch $and$ls180.v:3731$313_Y - attribute \src "ls180.v:3731.8-3731.87" + attribute \src "ls180.v:3734.4-3742.7" + switch $and$ls180.v:3734$313_Y + attribute \src "ls180.v:3734.8-3734.87" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3733.5-3735.8" + attribute \src "ls180.v:3736.5-3738.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3733.9-3733.42" + attribute \src "ls180.v:3736.9-3736.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case @@ -287067,27 +289568,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3743.4-3745.7" - switch $and$ls180.v:3743$314_Y - attribute \src "ls180.v:3743.8-3743.87" + attribute \src "ls180.v:3746.4-3748.7" + switch $and$ls180.v:3746$314_Y + attribute \src "ls180.v:3746.8-3746.87" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3749.4-3758.7" + attribute \src "ls180.v:3752.4-3761.7" switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3749.8-3749.44" + attribute \src "ls180.v:3752.8-3752.44" case 1'1 assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3754.5-3756.8" + attribute \src "ls180.v:3757.5-3759.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3754.9-3754.42" + attribute \src "ls180.v:3757.9-3757.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'110 case @@ -287098,16 +289599,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3761.4-3763.7" + attribute \src "ls180.v:3764.4-3766.7" switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3761.8-3761.45" + attribute \src "ls180.v:3764.8-3764.45" case 1'1 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3766.4-3768.7" - switch $not$ls180.v:3766$315_Y - attribute \src "ls180.v:3766.8-3766.46" + attribute \src "ls180.v:3769.4-3771.7" + switch $not$ls180.v:3769$315_Y + attribute \src "ls180.v:3769.8-3769.46" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'000 case @@ -287120,51 +289621,51 @@ module \ls180 assign $0\builder_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3777.4-3803.7" + attribute \src "ls180.v:3780.4-3806.7" switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3777.8-3777.43" + attribute \src "ls180.v:3780.8-3780.43" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3779.8-3779.12" + attribute \src "ls180.v:3782.8-3782.12" case - attribute \src "ls180.v:3780.5-3802.8" + attribute \src "ls180.v:3783.5-3805.8" switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3780.9-3780.56" + attribute \src "ls180.v:3783.9-3783.56" case 1'1 - attribute \src "ls180.v:3781.6-3801.9" + attribute \src "ls180.v:3784.6-3804.9" switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3781.10-3781.44" + attribute \src "ls180.v:3784.10-3784.44" case 1'1 - attribute \src "ls180.v:3782.7-3798.10" + attribute \src "ls180.v:3785.7-3801.10" switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3782.11-3782.42" + attribute \src "ls180.v:3785.11-3785.42" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3784.8-3791.11" + attribute \src "ls180.v:3787.8-3794.11" switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3784.12-3784.64" + attribute \src "ls180.v:3787.12-3787.64" case 1'1 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3788.12-3788.16" + attribute \src "ls180.v:3791.12-3791.16" case assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3793.8-3795.11" - switch $and$ls180.v:3793$316_Y - attribute \src "ls180.v:3793.12-3793.88" + attribute \src "ls180.v:3796.8-3798.11" + switch $and$ls180.v:3796$316_Y + attribute \src "ls180.v:3796.12-3796.88" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3796.11-3796.15" + attribute \src "ls180.v:3799.11-3799.15" case assign $0\builder_bankmachine2_next_state[2:0] 3'001 end - attribute \src "ls180.v:3799.10-3799.14" + attribute \src "ls180.v:3802.10-3802.14" case assign $0\builder_bankmachine2_next_state[2:0] 3'011 end @@ -287188,43 +289689,51 @@ module \ls180 update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:372.5-372.43" - process $proc$ls180.v:372$3207 + attribute \src "ls180.v:374.12-374.45" + process $proc$ls180.v:374$3204 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:375.5-375.43" + process $proc$ls180.v:375$3205 assign { } { } assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always sync init update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:3821.1-3828.4" - process $proc$ls180.v:3821$320 + attribute \src "ls180.v:3824.1-3831.4" + process $proc$ls180.v:3824$320 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3823.2-3827.5" + attribute \src "ls180.v:3826.2-3830.5" switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3823.6-3823.48" + attribute \src "ls180.v:3826.6-3826.48" case 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3825.6-3825.10" + attribute \src "ls180.v:3828.6-3828.10" case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3826$322_Y + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3829$322_Y end sync always update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:3832.1-3839.4" - process $proc$ls180.v:3832$329 + attribute \src "ls180.v:3835.1-3842.4" + process $proc$ls180.v:3835$329 assign { } { } assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3834.2-3838.5" - switch $and$ls180.v:3834$330_Y - attribute \src "ls180.v:3834.6-3834.115" + attribute \src "ls180.v:3837.2-3841.5" + switch $and$ls180.v:3837$330_Y + attribute \src "ls180.v:3837.6-3837.115" case 1'1 - attribute \src "ls180.v:3835.3-3837.6" - switch $ne$ls180.v:3835$331_Y - attribute \src "ls180.v:3835.7-3835.143" + attribute \src "ls180.v:3838.3-3840.6" + switch $ne$ls180.v:3838$331_Y + attribute \src "ls180.v:3838.7-3838.143" case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3836$332_Y + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3839$332_Y case end case @@ -287232,32 +289741,24 @@ module \ls180 sync always update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:3854.1-3861.4" - process $proc$ls180.v:3854$333 + attribute \src "ls180.v:3857.1-3864.4" + process $proc$ls180.v:3857$333 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3856.2-3860.5" + attribute \src "ls180.v:3859.2-3863.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3856.6-3856.58" + attribute \src "ls180.v:3859.6-3859.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3857$334_Y - attribute \src "ls180.v:3858.6-3858.10" + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3860$334_Y + attribute \src "ls180.v:3861.6-3861.10" case assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:387.12-387.46" - process $proc$ls180.v:387$3208 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:3870.1-3963.4" - process $proc$ls180.v:3870$342 + attribute \src "ls180.v:3873.1-3966.4" + process $proc$ls180.v:3873$342 assign { } { } assign { } { } assign { } { } @@ -287272,37 +289773,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3886.2-3962.9" + attribute \src "ls180.v:3889.2-3965.9" switch \builder_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3888.4-3896.7" - switch $and$ls180.v:3888$343_Y - attribute \src "ls180.v:3888.8-3888.87" + attribute \src "ls180.v:3891.4-3899.7" + switch $and$ls180.v:3891$343_Y + attribute \src "ls180.v:3891.8-3891.87" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3890.5-3892.8" + attribute \src "ls180.v:3893.5-3895.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3890.9-3890.42" + attribute \src "ls180.v:3893.9-3893.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case @@ -287312,27 +289813,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3900.4-3902.7" - switch $and$ls180.v:3900$344_Y - attribute \src "ls180.v:3900.8-3900.87" + attribute \src "ls180.v:3903.4-3905.7" + switch $and$ls180.v:3903$344_Y + attribute \src "ls180.v:3903.8-3903.87" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3906.4-3915.7" + attribute \src "ls180.v:3909.4-3918.7" switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3906.8-3906.44" + attribute \src "ls180.v:3909.8-3909.44" case 1'1 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3911.5-3913.8" + attribute \src "ls180.v:3914.5-3916.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3911.9-3911.42" + attribute \src "ls180.v:3914.9-3914.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'110 case @@ -287343,16 +289844,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3918.4-3920.7" + attribute \src "ls180.v:3921.4-3923.7" switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3918.8-3918.45" + attribute \src "ls180.v:3921.8-3921.45" case 1'1 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3923.4-3925.7" - switch $not$ls180.v:3923$345_Y - attribute \src "ls180.v:3923.8-3923.46" + attribute \src "ls180.v:3926.4-3928.7" + switch $not$ls180.v:3926$345_Y + attribute \src "ls180.v:3926.8-3926.46" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'000 case @@ -287365,51 +289866,51 @@ module \ls180 assign $0\builder_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3934.4-3960.7" + attribute \src "ls180.v:3937.4-3963.7" switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3934.8-3934.43" + attribute \src "ls180.v:3937.8-3937.43" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3936.8-3936.12" + attribute \src "ls180.v:3939.8-3939.12" case - attribute \src "ls180.v:3937.5-3959.8" + attribute \src "ls180.v:3940.5-3962.8" switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3937.9-3937.56" + attribute \src "ls180.v:3940.9-3940.56" case 1'1 - attribute \src "ls180.v:3938.6-3958.9" + attribute \src "ls180.v:3941.6-3961.9" switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3938.10-3938.44" + attribute \src "ls180.v:3941.10-3941.44" case 1'1 - attribute \src "ls180.v:3939.7-3955.10" + attribute \src "ls180.v:3942.7-3958.10" switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3939.11-3939.42" + attribute \src "ls180.v:3942.11-3942.42" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3941.8-3948.11" + attribute \src "ls180.v:3944.8-3951.11" switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3941.12-3941.64" + attribute \src "ls180.v:3944.12-3944.64" case 1'1 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3945.12-3945.16" + attribute \src "ls180.v:3948.12-3948.16" case assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3950.8-3952.11" - switch $and$ls180.v:3950$346_Y - attribute \src "ls180.v:3950.12-3950.88" + attribute \src "ls180.v:3953.8-3955.11" + switch $and$ls180.v:3953$346_Y + attribute \src "ls180.v:3953.12-3953.88" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3953.11-3953.15" + attribute \src "ls180.v:3956.11-3956.15" case assign $0\builder_bankmachine3_next_state[2:0] 3'001 end - attribute \src "ls180.v:3956.10-3956.14" + attribute \src "ls180.v:3959.10-3959.14" case assign $0\builder_bankmachine3_next_state[2:0] 3'011 end @@ -287433,120 +289934,112 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:388.5-388.44" - process $proc$ls180.v:388$3209 + attribute \src "ls180.v:390.12-390.46" + process $proc$ls180.v:390$3206 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:391.5-391.44" + process $proc$ls180.v:391$3207 assign { } { } assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] end - attribute \src "ls180.v:389.12-389.48" - process $proc$ls180.v:389$3210 + attribute \src "ls180.v:392.12-392.48" + process $proc$ls180.v:392$3208 assign { } { } assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 sync always sync init update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] end - attribute \src "ls180.v:390.11-390.43" - process $proc$ls180.v:390$3211 + attribute \src "ls180.v:393.11-393.43" + process $proc$ls180.v:393$3209 assign { } { } assign $1\main_sdram_master_p0_bank[1:0] 2'00 sync always sync init update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] end - attribute \src "ls180.v:391.5-391.38" - process $proc$ls180.v:391$3212 + attribute \src "ls180.v:394.5-394.38" + process $proc$ls180.v:394$3210 assign { } { } assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 sync always sync init update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] end - attribute \src "ls180.v:392.5-392.37" - process $proc$ls180.v:392$3213 + attribute \src "ls180.v:395.5-395.37" + process $proc$ls180.v:395$3211 assign { } { } assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 sync always sync init update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:393.5-393.38" - process $proc$ls180.v:393$3214 + attribute \src "ls180.v:396.5-396.38" + process $proc$ls180.v:396$3212 assign { } { } assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 sync always sync init update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:394.5-394.37" - process $proc$ls180.v:394$3215 + attribute \src "ls180.v:397.5-397.37" + process $proc$ls180.v:397$3213 assign { } { } assign $1\main_sdram_master_p0_we_n[0:0] 1'1 sync always sync init update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] end - attribute \src "ls180.v:395.5-395.36" - process $proc$ls180.v:395$3216 + attribute \src "ls180.v:398.5-398.36" + process $proc$ls180.v:398$3214 assign { } { } assign $1\main_sdram_master_p0_cke[0:0] 1'0 sync always sync init update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] end - attribute \src "ls180.v:396.5-396.36" - process $proc$ls180.v:396$3217 + attribute \src "ls180.v:3986.1-3992.4" + process $proc$ls180.v:3986$385 assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] - end - attribute \src "ls180.v:397.5-397.40" - process $proc$ls180.v:397$3218 assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3988$398_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3989$411_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3990$424_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3991$437_Y sync always - sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:398.5-398.38" - process $proc$ls180.v:398$3219 + attribute \src "ls180.v:399.5-399.36" + process $proc$ls180.v:399$3215 assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + assign $1\main_sdram_master_p0_odt[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:3983.1-3989.4" - process $proc$ls180.v:3983$385 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3985$398_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3986$411_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3987$424_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3988$437_Y - sync always - update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] end - attribute \src "ls180.v:399.12-399.47" - process $proc$ls180.v:399$3220 + attribute \src "ls180.v:400.5-400.40" + process $proc$ls180.v:400$3216 assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] end - attribute \src "ls180.v:3997.1-4002.4" - process $proc$ls180.v:3997$438 + attribute \src "ls180.v:4000.1-4005.4" + process $proc$ls180.v:4000$438 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3999.2-4001.5" + attribute \src "ls180.v:4002.2-4004.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3999.6-3999.37" + attribute \src "ls180.v:4002.6-4002.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 case @@ -287554,21 +290047,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:400.5-400.42" - process $proc$ls180.v:400$3221 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:4003.1-4008.4" - process $proc$ls180.v:4003$439 + attribute \src "ls180.v:4006.1-4011.4" + process $proc$ls180.v:4006$439 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:4005.2-4007.5" + attribute \src "ls180.v:4008.2-4010.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4005.6-4005.37" + attribute \src "ls180.v:4008.6-4008.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 case @@ -287576,13 +290061,21 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:4009.1-4014.4" - process $proc$ls180.v:4009$440 + attribute \src "ls180.v:401.5-401.38" + process $proc$ls180.v:401$3217 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:4012.1-4017.4" + process $proc$ls180.v:4012$440 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:4011.2-4013.5" + attribute \src "ls180.v:4014.2-4016.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4011.6-4011.37" + attribute \src "ls180.v:4014.6-4014.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 case @@ -287590,40 +290083,40 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:401.11-401.50" - process $proc$ls180.v:401$3222 + attribute \src "ls180.v:4019.1-4025.4" + process $proc$ls180.v:4019$443 assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:4021$456_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:4022$469_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:4023$482_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:4024$495_Y sync always - sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:4016.1-4022.4" - process $proc$ls180.v:4016$443 - assign { } { } + attribute \src "ls180.v:402.12-402.47" + process $proc$ls180.v:402$3218 assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:4018$456_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:4019$469_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:4020$482_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:4021$495_Y + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always - update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] end - attribute \src "ls180.v:402.5-402.42" - process $proc$ls180.v:402$3223 + attribute \src "ls180.v:403.5-403.42" + process $proc$ls180.v:403$3219 assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] end - attribute \src "ls180.v:4030.1-4035.4" - process $proc$ls180.v:4030$496 + attribute \src "ls180.v:4033.1-4038.4" + process $proc$ls180.v:4033$496 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:4032.2-4034.5" + attribute \src "ls180.v:4035.2-4037.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4032.6-4032.37" + attribute \src "ls180.v:4035.6-4035.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 case @@ -287631,13 +290124,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:4036.1-4041.4" - process $proc$ls180.v:4036$497 + attribute \src "ls180.v:4039.1-4044.4" + process $proc$ls180.v:4039$497 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:4038.2-4040.5" + attribute \src "ls180.v:4041.2-4043.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4038.6-4038.37" + attribute \src "ls180.v:4041.6-4041.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 case @@ -287645,13 +290138,21 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:4042.1-4047.4" - process $proc$ls180.v:4042$498 + attribute \src "ls180.v:404.11-404.50" + process $proc$ls180.v:404$3220 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:4045.1-4050.4" + process $proc$ls180.v:4045$498 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:4044.2-4046.5" + attribute \src "ls180.v:4047.2-4049.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4044.6-4044.37" + attribute \src "ls180.v:4047.6-4047.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 case @@ -287659,20 +290160,28 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:4048.1-4056.4" - process $proc$ls180.v:4048$499 + attribute \src "ls180.v:405.5-405.42" + process $proc$ls180.v:405$3221 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:4051.1-4059.4" + process $proc$ls180.v:4051$499 assign { } { } assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4050.2-4052.5" - switch $and$ls180.v:4050$502_Y - attribute \src "ls180.v:4050.6-4050.115" + attribute \src "ls180.v:4053.2-4055.5" + switch $and$ls180.v:4053$502_Y + attribute \src "ls180.v:4053.6-4053.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:4053.2-4055.5" - switch $and$ls180.v:4053$505_Y - attribute \src "ls180.v:4053.6-4053.115" + attribute \src "ls180.v:4056.2-4058.5" + switch $and$ls180.v:4056$505_Y + attribute \src "ls180.v:4056.6-4056.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case @@ -287680,20 +290189,20 @@ module \ls180 sync always update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:4057.1-4065.4" - process $proc$ls180.v:4057$506 + attribute \src "ls180.v:4060.1-4068.4" + process $proc$ls180.v:4060$506 assign { } { } assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4059.2-4061.5" - switch $and$ls180.v:4059$509_Y - attribute \src "ls180.v:4059.6-4059.115" + attribute \src "ls180.v:4062.2-4064.5" + switch $and$ls180.v:4062$509_Y + attribute \src "ls180.v:4062.6-4062.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:4062.2-4064.5" - switch $and$ls180.v:4062$512_Y - attribute \src "ls180.v:4062.6-4062.115" + attribute \src "ls180.v:4065.2-4067.5" + switch $and$ls180.v:4065$512_Y + attribute \src "ls180.v:4065.6-4065.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case @@ -287701,20 +290210,20 @@ module \ls180 sync always update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:4066.1-4074.4" - process $proc$ls180.v:4066$513 + attribute \src "ls180.v:4069.1-4077.4" + process $proc$ls180.v:4069$513 assign { } { } assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4068.2-4070.5" - switch $and$ls180.v:4068$516_Y - attribute \src "ls180.v:4068.6-4068.115" + attribute \src "ls180.v:4071.2-4073.5" + switch $and$ls180.v:4071$516_Y + attribute \src "ls180.v:4071.6-4071.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:4071.2-4073.5" - switch $and$ls180.v:4071$519_Y - attribute \src "ls180.v:4071.6-4071.115" + attribute \src "ls180.v:4074.2-4076.5" + switch $and$ls180.v:4074$519_Y + attribute \src "ls180.v:4074.6-4074.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case @@ -287722,20 +290231,20 @@ module \ls180 sync always update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:4075.1-4083.4" - process $proc$ls180.v:4075$520 + attribute \src "ls180.v:4078.1-4086.4" + process $proc$ls180.v:4078$520 assign { } { } assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4077.2-4079.5" - switch $and$ls180.v:4077$523_Y - attribute \src "ls180.v:4077.6-4077.115" + attribute \src "ls180.v:4080.2-4082.5" + switch $and$ls180.v:4080$523_Y + attribute \src "ls180.v:4080.6-4080.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:4080.2-4082.5" - switch $and$ls180.v:4080$526_Y - attribute \src "ls180.v:4080.6-4080.115" + attribute \src "ls180.v:4083.2-4085.5" + switch $and$ls180.v:4083$526_Y + attribute \src "ls180.v:4083.6-4083.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case @@ -287743,8 +290252,8 @@ module \ls180 sync always update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:4088.1-4160.4" - process $proc$ls180.v:4088$529 + attribute \src "ls180.v:4091.1-4163.4" + process $proc$ls180.v:4091$529 assign { } { } assign { } { } assign { } { } @@ -287759,42 +290268,42 @@ module \ls180 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 assign $0\main_sdram_cmd_ready[0:0] 1'0 assign { } { } - assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_en0[0:0] 1'0 assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:4100.2-4159.9" + attribute \src "ls180.v:4103.2-4162.9" switch \builder_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_en1[0:0] 1'1 assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4104.4-4110.7" + attribute \src "ls180.v:4107.4-4113.7" switch 1'1 - attribute \src "ls180.v:4104.8-4104.12" + attribute \src "ls180.v:4107.8-4107.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4105$536_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4108$536_Y case end - attribute \src "ls180.v:4112.4-4116.7" + attribute \src "ls180.v:4115.4-4119.7" switch \main_sdram_read_available - attribute \src "ls180.v:4112.8-4112.33" + attribute \src "ls180.v:4115.8-4115.33" case 1'1 - attribute \src "ls180.v:4113.5-4115.8" - switch $or$ls180.v:4113$538_Y - attribute \src "ls180.v:4113.9-4113.63" + attribute \src "ls180.v:4116.5-4118.8" + switch $or$ls180.v:4116$538_Y + attribute \src "ls180.v:4116.9-4116.63" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:4117.4-4119.7" + attribute \src "ls180.v:4120.4-4122.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4117.8-4117.32" + attribute \src "ls180.v:4120.8-4120.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -287803,18 +290312,18 @@ module \ls180 case 3'010 assign $0\main_sdram_steerer_sel[1:0] 2'11 assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:4124.4-4126.7" + attribute \src "ls180.v:4127.4-4129.7" switch \main_sdram_cmd_last - attribute \src "ls180.v:4124.8-4124.27" + attribute \src "ls180.v:4127.8-4127.27" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:4129.4-4131.7" + attribute \src "ls180.v:4132.4-4134.7" switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:4129.8-4129.32" + attribute \src "ls180.v:4132.8-4132.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case @@ -287830,29 +290339,29 @@ module \ls180 assign $0\main_sdram_en0[0:0] 1'1 assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4142.4-4148.7" + attribute \src "ls180.v:4145.4-4151.7" switch 1'1 - attribute \src "ls180.v:4142.8-4142.12" + attribute \src "ls180.v:4145.8-4145.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4143$545_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4146$545_Y case end - attribute \src "ls180.v:4150.4-4154.7" + attribute \src "ls180.v:4153.4-4157.7" switch \main_sdram_write_available - attribute \src "ls180.v:4150.8-4150.34" + attribute \src "ls180.v:4153.8-4153.34" case 1'1 - attribute \src "ls180.v:4151.5-4153.8" - switch $or$ls180.v:4151$547_Y - attribute \src "ls180.v:4151.9-4151.62" + attribute \src "ls180.v:4154.5-4156.8" + switch $or$ls180.v:4154$547_Y + attribute \src "ls180.v:4154.9-4154.62" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'100 case end case end - attribute \src "ls180.v:4155.4-4157.7" + attribute \src "ls180.v:4158.4-4160.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4155.8-4155.32" + attribute \src "ls180.v:4158.8-4158.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -287869,69 +290378,45 @@ module \ls180 update \main_sdram_en1 $0\main_sdram_en1[0:0] update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:409.11-409.36" - process $proc$ls180.v:409$3224 + attribute \src "ls180.v:412.11-412.36" + process $proc$ls180.v:412$3222 assign { } { } assign $1\main_sdram_storage[3:0] 4'0001 sync always sync init update \main_sdram_storage $1\main_sdram_storage[3:0] end - attribute \src "ls180.v:410.5-410.25" - process $proc$ls180.v:410$3225 + attribute \src "ls180.v:413.5-413.25" + process $proc$ls180.v:413$3223 assign { } { } assign $1\main_sdram_re[0:0] 1'0 sync always sync init update \main_sdram_re $1\main_sdram_re[0:0] end - attribute \src "ls180.v:411.11-411.44" - process $proc$ls180.v:411$3226 + attribute \src "ls180.v:414.11-414.44" + process $proc$ls180.v:414$3224 assign { } { } assign $1\main_sdram_command_storage[5:0] 6'000000 sync always sync init update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] end - attribute \src "ls180.v:412.5-412.33" - process $proc$ls180.v:412$3227 + attribute \src "ls180.v:415.5-415.33" + process $proc$ls180.v:415$3225 assign { } { } assign $1\main_sdram_command_re[0:0] 1'0 sync always sync init update \main_sdram_command_re $1\main_sdram_command_re[0:0] end - attribute \src "ls180.v:416.5-416.38" - process $proc$ls180.v:416$3228 + attribute \src "ls180.v:4187.1-4200.4" + process $proc$ls180.v:4187$676 assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 - sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] - sync init - end - attribute \src "ls180.v:417.12-417.46" - process $proc$ls180.v:417$3229 assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] - end - attribute \src "ls180.v:418.5-418.33" - process $proc$ls180.v:418$3230 - assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 - sync always - sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] - end - attribute \src "ls180.v:4184.1-4197.4" - process $proc$ls180.v:4184$676 - assign { } { } - assign { } { } - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:4187.2-4196.9" + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + attribute \src "ls180.v:4190.2-4199.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -287946,27 +290431,27 @@ module \ls180 update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:419.11-419.45" - process $proc$ls180.v:419$3231 + attribute \src "ls180.v:419.5-419.38" + process $proc$ls180.v:419$3226 assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 + assign $0\main_sdram_command_issue_w[0:0] 1'0 sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] end - attribute \src "ls180.v:420.5-420.34" - process $proc$ls180.v:420$3232 + attribute \src "ls180.v:420.12-420.46" + process $proc$ls180.v:420$3227 assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 sync always sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] end - attribute \src "ls180.v:4204.1-4214.4" - process $proc$ls180.v:4204$678 + attribute \src "ls180.v:4207.1-4217.4" + process $proc$ls180.v:4207$678 assign { } { } assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4206.2-4213.9" + attribute \src "ls180.v:4209.2-4216.9" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -287979,16 +290464,16 @@ module \ls180 sync always update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:421.12-421.45" - process $proc$ls180.v:421$3233 + attribute \src "ls180.v:421.5-421.33" + process $proc$ls180.v:421$3228 assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + assign $1\main_sdram_address_re[0:0] 1'0 sync always sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + update \main_sdram_address_re $1\main_sdram_address_re[0:0] end - attribute \src "ls180.v:4216.1-4262.4" - process $proc$ls180.v:4216$679 + attribute \src "ls180.v:4219.1-4265.4" + process $proc$ls180.v:4219$679 assign { } { } assign { } { } assign { } { } @@ -287999,7 +290484,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\main_litedram_wb_cyc[0:0] 1'0 assign { } { } assign $0\main_litedram_wb_stb[0:0] 1'0 @@ -288009,13 +290493,14 @@ module \ls180 assign $0\main_converter_skip[0:0] 1'0 assign $0\main_wb_sdram_ack[0:0] 1'0 assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4228.2-4261.9" + attribute \src "ls180.v:4231.2-4264.9" switch \builder_converter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4231.4-4238.11" + attribute \src "ls180.v:4234.4-4241.11" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -288025,23 +290510,23 @@ module \ls180 assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] case end - attribute \src "ls180.v:4239.4-4252.7" - switch $and$ls180.v:4239$680_Y - attribute \src "ls180.v:4239.8-4239.47" + attribute \src "ls180.v:4242.4-4255.7" + switch $and$ls180.v:4242$680_Y + attribute \src "ls180.v:4242.8-4242.47" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4240$681_Y + assign $0\main_converter_skip[0:0] $eq$ls180.v:4243$681_Y assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4242$682_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4243$683_Y - attribute \src "ls180.v:4244.5-4251.8" - switch $or$ls180.v:4244$684_Y - attribute \src "ls180.v:4244.9-4244.53" + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4245$682_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4246$683_Y + attribute \src "ls180.v:4247.5-4254.8" + switch $or$ls180.v:4247$684_Y + attribute \src "ls180.v:4247.9-4247.53" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4245$685_Y + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4248$685_Y assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4247.6-4250.9" - switch $eq$ls180.v:4247$686_Y - attribute \src "ls180.v:4247.10-4247.42" + attribute \src "ls180.v:4250.6-4253.9" + switch $eq$ls180.v:4250$686_Y + attribute \src "ls180.v:4250.10-4250.42" case 1'1 assign $0\main_wb_sdram_ack[0:0] 1'1 assign $0\builder_converter_next_state[0:0] 1'0 @@ -288055,9 +290540,9 @@ module \ls180 case assign $0\main_converter_counter_converter_next_value[0:0] 1'0 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4257.4-4259.7" - switch $and$ls180.v:4257$687_Y - attribute \src "ls180.v:4257.8-4257.47" + attribute \src "ls180.v:4260.4-4262.7" + switch $and$ls180.v:4260$687_Y + attribute \src "ls180.v:4260.8-4260.47" case 1'1 assign $0\builder_converter_next_state[0:0] 1'1 case @@ -288075,29 +290560,53 @@ module \ls180 update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:422.5-422.32" - process $proc$ls180.v:422$3234 + attribute \src "ls180.v:422.11-422.45" + process $proc$ls180.v:422$3229 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:423.5-423.34" + process $proc$ls180.v:423$3230 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:424.12-424.45" + process $proc$ls180.v:424$3231 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:425.5-425.32" + process $proc$ls180.v:425$3232 assign { } { } assign $1\main_sdram_wrdata_re[0:0] 1'0 sync always sync init update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] end - attribute \src "ls180.v:423.12-423.37" - process $proc$ls180.v:423$3235 + attribute \src "ls180.v:426.12-426.37" + process $proc$ls180.v:426$3233 assign { } { } assign $1\main_sdram_status[15:0] 16'0000000000000000 sync always sync init update \main_sdram_status $1\main_sdram_status[15:0] end - attribute \src "ls180.v:4307.1-4312.4" - process $proc$ls180.v:4307$719 + attribute \src "ls180.v:4310.1-4315.4" + process $proc$ls180.v:4310$719 assign { } { } assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4309.2-4311.5" - switch $and$ls180.v:4309$720_Y - attribute \src "ls180.v:4309.6-4309.79" + attribute \src "ls180.v:4312.2-4314.5" + switch $and$ls180.v:4312$720_Y + attribute \src "ls180.v:4312.6-4312.79" case 1'1 assign $0\main_uart_tx_clear[0:0] 1'1 case @@ -288105,8 +290614,8 @@ module \ls180 sync always update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:4313.1-4317.4" - process $proc$ls180.v:4313$721 + attribute \src "ls180.v:4316.1-4320.4" + process $proc$ls180.v:4316$721 assign { } { } assign { } { } assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status @@ -288114,13 +290623,13 @@ module \ls180 sync always update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:4318.1-4323.4" - process $proc$ls180.v:4318$722 + attribute \src "ls180.v:4321.1-4326.4" + process $proc$ls180.v:4321$722 assign { } { } assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4320.2-4322.5" - switch $and$ls180.v:4320$723_Y - attribute \src "ls180.v:4320.6-4320.79" + attribute \src "ls180.v:4323.2-4325.5" + switch $and$ls180.v:4323$723_Y + attribute \src "ls180.v:4323.6-4323.79" case 1'1 assign $0\main_uart_rx_clear[0:0] 1'1 case @@ -288128,8 +290637,8 @@ module \ls180 sync always update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:4324.1-4328.4" - process $proc$ls180.v:4324$724 + attribute \src "ls180.v:4327.1-4331.4" + process $proc$ls180.v:4327$724 assign { } { } assign { } { } assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending @@ -288137,40 +290646,40 @@ module \ls180 sync always update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:4346.1-4353.4" - process $proc$ls180.v:4346$732 + attribute \src "ls180.v:4349.1-4356.4" + process $proc$ls180.v:4349$732 assign { } { } assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4348.2-4352.5" + attribute \src "ls180.v:4351.2-4355.5" switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4348.6-4348.31" + attribute \src "ls180.v:4351.6-4351.31" case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4349$733_Y - attribute \src "ls180.v:4350.6-4350.10" + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4352$733_Y + attribute \src "ls180.v:4353.6-4353.10" case assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce end sync always update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:4376.1-4383.4" - process $proc$ls180.v:4376$743 + attribute \src "ls180.v:4379.1-4386.4" + process $proc$ls180.v:4379$743 assign { } { } assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4378.2-4382.5" + attribute \src "ls180.v:4381.2-4385.5" switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4378.6-4378.31" + attribute \src "ls180.v:4381.6-4381.31" case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4379$744_Y - attribute \src "ls180.v:4380.6-4380.10" + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4382$744_Y + attribute \src "ls180.v:4383.6-4383.10" case assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce end sync always update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:4396.1-4400.4" - process $proc$ls180.v:4396$750 + attribute \src "ls180.v:4399.1-4403.4" + process $proc$ls180.v:4399$750 assign { } { } assign { } { } assign { } { } @@ -288178,8 +290687,8 @@ module \ls180 sync always update \gpio_o $0\gpio_o[15:0] end - attribute \src "ls180.v:4401.1-4405.4" - process $proc$ls180.v:4401$751 + attribute \src "ls180.v:4404.1-4408.4" + process $proc$ls180.v:4404$751 assign { } { } assign { } { } assign { } { } @@ -288187,9 +290696,8 @@ module \ls180 sync always update \gpio_oe $0\gpio_oe[15:0] end - attribute \src "ls180.v:4417.1-4465.4" - process $proc$ls180.v:4417$756 - assign { } { } + attribute \src "ls180.v:4420.1-4468.4" + process $proc$ls180.v:4420$756 assign { } { } assign { } { } assign { } { } @@ -288207,16 +290715,17 @@ module \ls180 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster29_miso_latch[0:0] 1'0 assign $0\main_spimaster3_irq[0:0] 1'0 + assign { } { } assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4428.2-4464.9" + attribute \src "ls180.v:4431.2-4467.9" switch \builder_spimaster0_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4432.4-4435.7" + attribute \src "ls180.v:4435.4-4438.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4432.8-4432.33" + attribute \src "ls180.v:4435.8-4435.33" case 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'10 @@ -288226,15 +290735,15 @@ module \ls180 case 2'10 assign $0\main_spimaster25_clk_enable[0:0] 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4440.4-4446.7" + attribute \src "ls180.v:4443.4-4449.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4440.8-4440.33" + attribute \src "ls180.v:4443.8-4443.33" case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4441$757_Y + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4444$757_Y assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4443.5-4445.8" - switch $eq$ls180.v:4443$759_Y - attribute \src "ls180.v:4443.9-4443.68" + attribute \src "ls180.v:4446.5-4448.8" + switch $eq$ls180.v:4446$759_Y + attribute \src "ls180.v:4446.9-4446.68" case 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'11 case @@ -288244,9 +290753,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4450.4-4454.7" + attribute \src "ls180.v:4453.4-4457.7" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4450.8-4450.33" + attribute \src "ls180.v:4453.8-4453.33" case 1'1 assign $0\main_spimaster29_miso_latch[0:0] 1'1 assign $0\main_spimaster3_irq[0:0] 1'1 @@ -288256,9 +290765,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4458.4-4462.7" + attribute \src "ls180.v:4461.4-4465.7" switch \main_spimaster0_start - attribute \src "ls180.v:4458.8-4458.29" + attribute \src "ls180.v:4461.8-4461.29" case 1'1 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster28_mosi_latch[0:0] 1'1 @@ -288277,8 +290786,8 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:4476.1-4524.4" - process $proc$ls180.v:4476$764 + attribute \src "ls180.v:4479.1-4527.4" + process $proc$ls180.v:4479$764 assign { } { } assign { } { } assign { } { } @@ -288298,15 +290807,15 @@ module \ls180 assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4487.2-4523.9" + attribute \src "ls180.v:4490.2-4526.9" switch \builder_spimaster1_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4491.4-4494.7" + attribute \src "ls180.v:4494.4-4497.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4491.8-4491.31" + attribute \src "ls180.v:4494.8-4494.31" case 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'10 @@ -288316,15 +290825,15 @@ module \ls180 case 2'10 assign $0\main_spisdcard_clk_enable[0:0] 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4499.4-4505.7" + attribute \src "ls180.v:4502.4-4508.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4499.8-4499.31" + attribute \src "ls180.v:4502.8-4502.31" case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4500$765_Y + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4503$765_Y assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4502.5-4504.8" - switch $eq$ls180.v:4502$767_Y - attribute \src "ls180.v:4502.9-4502.66" + attribute \src "ls180.v:4505.5-4507.8" + switch $eq$ls180.v:4505$767_Y + attribute \src "ls180.v:4505.9-4505.66" case 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'11 case @@ -288334,9 +290843,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4509.4-4513.7" + attribute \src "ls180.v:4512.4-4516.7" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4509.8-4509.31" + attribute \src "ls180.v:4512.8-4512.31" case 1'1 assign $0\main_spisdcard_miso_latch[0:0] 1'1 assign $0\main_spisdcard_irq[0:0] 1'1 @@ -288346,9 +290855,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4517.4-4521.7" + attribute \src "ls180.v:4520.4-4524.7" switch \main_spisdcard_start0 - attribute \src "ls180.v:4517.8-4517.29" + attribute \src "ls180.v:4520.8-4520.29" case 1'1 assign $0\main_spisdcard_done0[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'1 @@ -288367,27 +290876,11 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:453.12-453.46" - process $proc$ls180.v:453$3236 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:454.11-454.47" - process $proc$ls180.v:454$3237 - assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:4556.1-4584.4" - process $proc$ls180.v:4556$789 + attribute \src "ls180.v:4559.1-4587.4" + process $proc$ls180.v:4559$789 assign { } { } assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4558.2-4583.9" + attribute \src "ls180.v:4561.2-4586.9" switch \main_sdphy_clocker_storage attribute \src "ls180.v:0.0-0.0" case 9'000000100 @@ -288417,32 +290910,24 @@ module \ls180 sync always update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:456.12-456.45" - process $proc$ls180.v:456$3238 + attribute \src "ls180.v:456.12-456.46" + process $proc$ls180.v:456$3234 assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:457.11-457.40" - process $proc$ls180.v:457$3239 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] end - attribute \src "ls180.v:458.5-458.35" - process $proc$ls180.v:458$3240 + attribute \src "ls180.v:457.11-457.47" + process $proc$ls180.v:457$3235 assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 sync always sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:4586.1-4619.4" - process $proc$ls180.v:4586$792 + attribute \src "ls180.v:4589.1-4622.4" + process $proc$ls180.v:4589$792 assign { } { } assign { } { } assign { } { } @@ -288451,7 +290936,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 @@ -288459,8 +290943,9 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4596.2-4618.9" + attribute \src "ls180.v:4599.2-4621.9" switch \builder_sdphy_sdphyinit_state attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -288469,15 +290954,15 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4603.4-4609.7" + attribute \src "ls180.v:4606.4-4612.7" switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4603.8-4603.38" + attribute \src "ls180.v:4606.8-4606.38" case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4604$793_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4607$793_Y assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4606.5-4608.8" - switch $eq$ls180.v:4606$794_Y - attribute \src "ls180.v:4606.9-4606.41" + attribute \src "ls180.v:4609.5-4611.8" + switch $eq$ls180.v:4609$794_Y + attribute \src "ls180.v:4609.9-4609.41" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 case @@ -288488,9 +290973,9 @@ module \ls180 case assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4614.4-4616.7" + attribute \src "ls180.v:4617.4-4619.7" switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4614.8-4614.37" + attribute \src "ls180.v:4617.8-4617.37" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 case @@ -288506,32 +290991,40 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:459.5-459.34" - process $proc$ls180.v:459$3241 + attribute \src "ls180.v:459.12-459.45" + process $proc$ls180.v:459$3236 assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 sync always sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end - attribute \src "ls180.v:460.5-460.35" - process $proc$ls180.v:460$3242 + attribute \src "ls180.v:460.11-460.40" + process $proc$ls180.v:460$3237 assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 sync always sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] end - attribute \src "ls180.v:461.5-461.34" - process $proc$ls180.v:461$3243 + attribute \src "ls180.v:461.5-461.35" + process $proc$ls180.v:461$3238 assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] end - attribute \src "ls180.v:4620.1-4696.4" - process $proc$ls180.v:4620$795 + attribute \src "ls180.v:462.5-462.34" + process $proc$ls180.v:462$3239 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:4623.1-4699.4" + process $proc$ls180.v:4623$795 assign { } { } assign { } { } assign { } { } @@ -288549,13 +291042,13 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4630.2-4695.9" + attribute \src "ls180.v:4633.2-4698.9" switch \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4634.4-4659.11" + attribute \src "ls180.v:4637.4-4662.11" switch \main_sdphy_cmdw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -288583,22 +291076,22 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] case end - attribute \src "ls180.v:4660.4-4671.7" + attribute \src "ls180.v:4663.4-4674.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4660.8-4660.38" + attribute \src "ls180.v:4663.8-4663.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4661$796_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4664$796_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4663.5-4670.8" - switch $eq$ls180.v:4663$797_Y - attribute \src "ls180.v:4663.9-4663.40" + attribute \src "ls180.v:4666.5-4673.8" + switch $eq$ls180.v:4666$797_Y + attribute \src "ls180.v:4666.9-4666.40" case 1'1 - attribute \src "ls180.v:4664.6-4669.9" + attribute \src "ls180.v:4667.6-4672.9" switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4664.10-4664.35" + attribute \src "ls180.v:4667.10-4667.35" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4666.10-4666.14" + attribute \src "ls180.v:4669.10-4669.14" case assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -288612,15 +291105,15 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4677.4-4684.7" + attribute \src "ls180.v:4680.4-4687.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4677.8-4677.38" + attribute \src "ls180.v:4680.8-4680.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4678$798_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4681$798_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4680.5-4683.8" - switch $eq$ls180.v:4680$799_Y - attribute \src "ls180.v:4680.9-4680.40" + attribute \src "ls180.v:4683.5-4686.8" + switch $eq$ls180.v:4683$799_Y + attribute \src "ls180.v:4683.9-4683.40" case 1'1 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -288632,12 +291125,12 @@ module \ls180 case assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4689.4-4693.7" - switch $and$ls180.v:4689$800_Y - attribute \src "ls180.v:4689.8-4689.69" + attribute \src "ls180.v:4692.4-4696.7" + switch $and$ls180.v:4692$800_Y + attribute \src "ls180.v:4692.8-4692.69" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4691.8-4691.12" + attribute \src "ls180.v:4694.8-4694.12" case assign $0\main_sdphy_cmdw_done[0:0] 1'1 end @@ -288652,48 +291145,48 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:465.5-465.35" - process $proc$ls180.v:465$3244 + attribute \src "ls180.v:463.5-463.35" + process $proc$ls180.v:463$3240 assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] end - attribute \src "ls180.v:467.5-467.39" - process $proc$ls180.v:467$3245 + attribute \src "ls180.v:464.5-464.34" + process $proc$ls180.v:464$3241 assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:469.5-469.39" - process $proc$ls180.v:469$3246 + attribute \src "ls180.v:468.5-468.35" + process $proc$ls180.v:468$3242 assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:472.5-472.32" - process $proc$ls180.v:472$3247 + attribute \src "ls180.v:470.5-470.39" + process $proc$ls180.v:470$3243 assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "ls180.v:473.5-473.32" - process $proc$ls180.v:473$3248 + attribute \src "ls180.v:472.5-472.39" + process $proc$ls180.v:472$3244 assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 sync always sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:4730.1-4823.4" - process $proc$ls180.v:4730$809 + attribute \src "ls180.v:4733.1-4826.4" + process $proc$ls180.v:4733$809 assign { } { } assign { } { } assign { } { } @@ -288710,7 +291203,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 @@ -288726,26 +291218,27 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4748.2-4822.9" + attribute \src "ls180.v:4751.2-4825.9" switch \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4756$810_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4759$810_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4753.4-4755.7" + attribute \src "ls180.v:4756.4-4758.7" switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4753.8-4753.49" + attribute \src "ls180.v:4756.8-4756.49" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4758.4-4761.7" - switch $eq$ls180.v:4758$811_Y - attribute \src "ls180.v:4758.8-4758.41" + attribute \src "ls180.v:4761.4-4764.7" + switch $eq$ls180.v:4761$811_Y + attribute \src "ls180.v:4761.8-4761.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -288756,30 +291249,30 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4767$813_Y + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4770$813_Y assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4784$816_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4787$816_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4769.4-4783.7" - switch $and$ls180.v:4769$814_Y - attribute \src "ls180.v:4769.8-4769.69" + attribute \src "ls180.v:4772.4-4786.7" + switch $and$ls180.v:4772$814_Y + attribute \src "ls180.v:4772.8-4772.69" case 1'1 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4771$815_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4774$815_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4773.5-4782.8" + attribute \src "ls180.v:4776.5-4785.8" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4773.9-4773.36" + attribute \src "ls180.v:4776.9-4776.36" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4775.6-4781.9" + attribute \src "ls180.v:4778.6-4784.9" switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4775.10-4775.35" + attribute \src "ls180.v:4778.10-4778.35" case 1'1 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4779.10-4779.14" + attribute \src "ls180.v:4782.10-4782.14" case assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 end @@ -288787,9 +291280,9 @@ module \ls180 end case end - attribute \src "ls180.v:4786.4-4789.7" - switch $eq$ls180.v:4786$817_Y - attribute \src "ls180.v:4786.8-4786.41" + attribute \src "ls180.v:4789.4-4792.7" + switch $eq$ls180.v:4789$817_Y + attribute \src "ls180.v:4789.8-4789.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -288800,15 +291293,15 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4795.4-4801.7" + attribute \src "ls180.v:4798.4-4804.7" switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4795.8-4795.38" + attribute \src "ls180.v:4798.8-4798.38" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4796$818_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4799$818_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4798.5-4800.8" - switch $eq$ls180.v:4798$819_Y - attribute \src "ls180.v:4798.9-4798.40" + attribute \src "ls180.v:4801.5-4803.8" + switch $eq$ls180.v:4801$819_Y + attribute \src "ls180.v:4801.9-4801.40" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -288820,9 +291313,9 @@ module \ls180 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4807.4-4809.7" - switch $and$ls180.v:4807$820_Y - attribute \src "ls180.v:4807.8-4807.69" + attribute \src "ls180.v:4810.4-4812.7" + switch $and$ls180.v:4810$820_Y + attribute \src "ls180.v:4810.8-4810.69" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -288833,9 +291326,9 @@ module \ls180 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4816.4-4820.7" - switch $and$ls180.v:4816$822_Y - attribute \src "ls180.v:4816.8-4816.94" + attribute \src "ls180.v:4819.4-4823.7" + switch $and$ls180.v:4819$822_Y + attribute \src "ls180.v:4819.8-4819.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 @@ -288861,106 +291354,122 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:474.5-474.31" - process $proc$ls180.v:474$3249 + attribute \src "ls180.v:475.5-475.32" + process $proc$ls180.v:475$3245 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:476.5-476.32" + process $proc$ls180.v:476$3246 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:477.5-477.31" + process $proc$ls180.v:477$3247 assign { } { } assign $1\main_sdram_cmd_last[0:0] 1'0 sync always sync init update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end - attribute \src "ls180.v:475.12-475.44" - process $proc$ls180.v:475$3250 + attribute \src "ls180.v:478.12-478.44" + process $proc$ls180.v:478$3248 assign { } { } assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:476.11-476.43" - process $proc$ls180.v:476$3251 + attribute \src "ls180.v:479.11-479.43" + process $proc$ls180.v:479$3249 assign { } { } assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 sync always sync init update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end - attribute \src "ls180.v:477.5-477.38" - process $proc$ls180.v:477$3252 + attribute \src "ls180.v:480.5-480.38" + process $proc$ls180.v:480$3250 assign { } { } assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:478.5-478.38" - process $proc$ls180.v:478$3253 + attribute \src "ls180.v:481.5-481.38" + process $proc$ls180.v:481$3251 assign { } { } assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] end - attribute \src "ls180.v:479.5-479.37" - process $proc$ls180.v:479$3254 + attribute \src "ls180.v:482.5-482.37" + process $proc$ls180.v:482$3252 assign { } { } assign $1\main_sdram_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] end - attribute \src "ls180.v:480.5-480.42" - process $proc$ls180.v:480$3255 + attribute \src "ls180.v:483.5-483.42" + process $proc$ls180.v:483$3253 assign { } { } assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 sync always update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] sync init end - attribute \src "ls180.v:481.5-481.43" - process $proc$ls180.v:481$3256 + attribute \src "ls180.v:484.5-484.43" + process $proc$ls180.v:484$3254 assign { } { } assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 sync always update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init end - attribute \src "ls180.v:4857.1-4884.4" - process $proc$ls180.v:4857$830 + attribute \src "ls180.v:4860.1-4887.4" + process $proc$ls180.v:4860$830 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign { } { } assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4865.2-4883.9" + attribute \src "ls180.v:4868.2-4886.9" switch \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4870.4-4874.7" + attribute \src "ls180.v:4873.4-4877.7" switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4870.8-4870.50" + attribute \src "ls180.v:4873.8-4873.50" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4871$831_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4872$832_Y + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4874$831_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4875$832_Y assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 case end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4877.4-4881.7" + attribute \src "ls180.v:4880.4-4884.7" switch \main_sdphy_dataw_start - attribute \src "ls180.v:4877.8-4877.30" + attribute \src "ls180.v:4880.8-4880.30" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 @@ -288976,16 +291485,8 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:487.11-487.44" - process $proc$ls180.v:487$3257 - assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 - sync always - sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] - end - attribute \src "ls180.v:4885.1-4957.4" - process $proc$ls180.v:4885$833 + attribute \src "ls180.v:4888.1-4960.4" + process $proc$ls180.v:4888$833 assign { } { } assign { } { } assign { } { } @@ -288995,7 +291496,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 @@ -289004,27 +291504,28 @@ module \ls180 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4896.2-4956.9" + attribute \src "ls180.v:4899.2-4959.9" switch \builder_sdphy_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4901.4-4903.7" + attribute \src "ls180.v:4904.4-4906.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4901.8-4901.39" + attribute \src "ls180.v:4904.8-4904.39" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4906$834_Y + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4909$834_Y assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4909.4-4916.11" + attribute \src "ls180.v:4912.4-4919.11" switch \main_sdphy_dataw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -289034,24 +291535,24 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] case end - attribute \src "ls180.v:4917.4-4929.7" + attribute \src "ls180.v:4920.4-4932.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4917.8-4917.39" + attribute \src "ls180.v:4920.8-4920.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4918$835_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4921$835_Y assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4920.5-4928.8" - switch $eq$ls180.v:4920$836_Y - attribute \src "ls180.v:4920.9-4920.41" + attribute \src "ls180.v:4923.5-4931.8" + switch $eq$ls180.v:4923$836_Y + attribute \src "ls180.v:4923.9-4923.41" case 1'1 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4923.6-4927.9" + attribute \src "ls180.v:4926.6-4930.9" switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4923.10-4923.36" + attribute \src "ls180.v:4926.10-4926.36" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4925.10-4925.14" + attribute \src "ls180.v:4928.10-4928.14" case assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 end @@ -289064,9 +291565,9 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4935.4-4938.7" + attribute \src "ls180.v:4938.4-4941.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4935.8-4935.39" + attribute \src "ls180.v:4938.8-4938.39" case 1'1 assign $0\main_sdphy_dataw_start[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 @@ -289075,13 +291576,13 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4942.4-4947.7" + attribute \src "ls180.v:4945.4-4950.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4942.8-4942.39" + attribute \src "ls180.v:4945.8-4945.39" case 1'1 - attribute \src "ls180.v:4943.5-4946.8" + attribute \src "ls180.v:4946.5-4949.8" switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4943.9-4943.51" + attribute \src "ls180.v:4946.9-4946.51" case 1'1 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 @@ -289093,9 +291594,9 @@ module \ls180 case assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4952.4-4954.7" - switch $and$ls180.v:4952$837_Y - attribute \src "ls180.v:4952.8-4952.71" + attribute \src "ls180.v:4955.4-4957.7" + switch $and$ls180.v:4955$837_Y + attribute \src "ls180.v:4955.8-4955.71" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 case @@ -289112,56 +291613,64 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:489.5-489.38" - process $proc$ls180.v:489$3258 + attribute \src "ls180.v:490.11-490.44" + process $proc$ls180.v:490$3255 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:492.5-492.38" + process $proc$ls180.v:492$3256 assign { } { } assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always sync init update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end - attribute \src "ls180.v:490.5-490.38" - process $proc$ls180.v:490$3259 + attribute \src "ls180.v:493.5-493.38" + process $proc$ls180.v:493$3257 assign { } { } assign $1\main_sdram_postponer_count[0:0] 1'0 sync always sync init update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] end - attribute \src "ls180.v:491.5-491.39" - process $proc$ls180.v:491$3260 + attribute \src "ls180.v:494.5-494.39" + process $proc$ls180.v:494$3258 assign { } { } assign $1\main_sdram_sequencer_start0[0:0] 1'0 sync always sync init update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:494.5-494.38" - process $proc$ls180.v:494$3261 + attribute \src "ls180.v:497.5-497.38" + process $proc$ls180.v:497$3259 assign { } { } assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always sync init update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:495.11-495.46" - process $proc$ls180.v:495$3262 + attribute \src "ls180.v:498.11-498.46" + process $proc$ls180.v:498$3260 assign { } { } assign $1\main_sdram_sequencer_counter[3:0] 4'0000 sync always sync init update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:496.5-496.38" - process $proc$ls180.v:496$3263 + attribute \src "ls180.v:499.5-499.38" + process $proc$ls180.v:499$3261 assign { } { } assign $1\main_sdram_sequencer_count[0:0] 1'0 sync always sync init update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] end - attribute \src "ls180.v:4991.1-5092.4" - process $proc$ls180.v:4991$845 + attribute \src "ls180.v:4994.1-5095.4" + process $proc$ls180.v:4994$845 assign { } { } assign { } { } assign { } { } @@ -289177,23 +291686,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_source_last[0:0] 1'0 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:5008.2-5091.9" + attribute \src "ls180.v:5011.2-5094.9" switch \builder_sdphy_sdphydatar_state attribute \src "ls180.v:0.0-0.0" case 3'001 @@ -289202,18 +291711,18 @@ module \ls180 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 assign { } { } assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5018$847_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5021$847_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:5015.4-5017.7" + attribute \src "ls180.v:5018.4-5020.7" switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:5015.8-5015.51" + attribute \src "ls180.v:5018.8-5018.51" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 case end - attribute \src "ls180.v:5020.4-5023.7" - switch $eq$ls180.v:5020$848_Y - attribute \src "ls180.v:5020.8-5020.42" + attribute \src "ls180.v:5023.4-5026.7" + switch $eq$ls180.v:5023$848_Y + attribute \src "ls180.v:5023.8-5023.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -289224,48 +291733,48 @@ module \ls180 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:5029$851_Y + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:5032$851_Y assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5050$853_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5053$853_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:5031.4-5049.7" + attribute \src "ls180.v:5034.4-5052.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5031.8-5031.37" + attribute \src "ls180.v:5034.8-5034.37" case 1'1 - attribute \src "ls180.v:5032.5-5048.8" + attribute \src "ls180.v:5035.5-5051.8" switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:5032.9-5032.38" + attribute \src "ls180.v:5035.9-5035.38" case 1'1 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5034$852_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5037$852_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5036.6-5045.9" + attribute \src "ls180.v:5039.6-5048.9" switch \main_sdphy_datar_source_last - attribute \src "ls180.v:5036.10-5036.38" + attribute \src "ls180.v:5039.10-5039.38" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5038.7-5044.10" + attribute \src "ls180.v:5041.7-5047.10" switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:5038.11-5038.37" + attribute \src "ls180.v:5041.11-5041.37" case 1'1 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:5042.11-5042.15" + attribute \src "ls180.v:5045.11-5045.15" case assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 end case end - attribute \src "ls180.v:5046.9-5046.13" + attribute \src "ls180.v:5049.9-5049.13" case assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:5052.4-5055.7" - switch $eq$ls180.v:5052$854_Y - attribute \src "ls180.v:5052.8-5052.42" + attribute \src "ls180.v:5055.4-5058.7" + switch $eq$ls180.v:5055$854_Y + attribute \src "ls180.v:5055.8-5055.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -289274,15 +291783,15 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:5059.4-5065.7" + attribute \src "ls180.v:5062.4-5068.7" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:5059.8-5059.39" + attribute \src "ls180.v:5062.8-5062.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5060$855_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5063$855_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5062.5-5064.8" - switch $eq$ls180.v:5062$856_Y - attribute \src "ls180.v:5062.9-5062.42" + attribute \src "ls180.v:5065.5-5067.8" + switch $eq$ls180.v:5065$856_Y + attribute \src "ls180.v:5065.9-5065.42" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -289294,9 +291803,9 @@ module \ls180 assign $0\main_sdphy_datar_source_valid[0:0] 1'1 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:5071.4-5073.7" - switch $and$ls180.v:5071$857_Y - attribute \src "ls180.v:5071.8-5071.71" + attribute \src "ls180.v:5074.4-5076.7" + switch $and$ls180.v:5074$857_Y + attribute \src "ls180.v:5074.8-5074.71" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -289305,14 +291814,14 @@ module \ls180 case assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5078.4-5089.7" - switch $and$ls180.v:5078$858_Y - attribute \src "ls180.v:5078.8-5078.71" + attribute \src "ls180.v:5081.4-5092.7" + switch $and$ls180.v:5081$858_Y + attribute \src "ls180.v:5081.8-5081.71" case 1'1 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:5080.5-5088.8" + attribute \src "ls180.v:5083.5-5091.8" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:5080.9-5080.40" + attribute \src "ls180.v:5083.9-5083.40" case 1'1 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 @@ -289343,208 +291852,192 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:502.5-502.51" - process $proc$ls180.v:502$3264 + attribute \src "ls180.v:505.5-505.51" + process $proc$ls180.v:505$3262 assign { } { } assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] end - attribute \src "ls180.v:503.5-503.51" - process $proc$ls180.v:503$3265 + attribute \src "ls180.v:506.5-506.51" + process $proc$ls180.v:506$3263 assign { } { } assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "ls180.v:505.5-505.47" - process $proc$ls180.v:505$3266 + attribute \src "ls180.v:508.5-508.47" + process $proc$ls180.v:508$3264 assign { } { } assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] end - attribute \src "ls180.v:506.5-506.45" - process $proc$ls180.v:506$3267 + attribute \src "ls180.v:509.5-509.45" + process $proc$ls180.v:509$3265 assign { } { } assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] end - attribute \src "ls180.v:507.5-507.45" - process $proc$ls180.v:507$3268 + attribute \src "ls180.v:510.5-510.45" + process $proc$ls180.v:510$3266 assign { } { } assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:508.12-508.57" - process $proc$ls180.v:508$3269 + attribute \src "ls180.v:511.12-511.57" + process $proc$ls180.v:511$3267 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:510.5-510.51" - process $proc$ls180.v:510$3270 + attribute \src "ls180.v:513.5-513.51" + process $proc$ls180.v:513$3268 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] end - attribute \src "ls180.v:511.5-511.51" - process $proc$ls180.v:511$3271 + attribute \src "ls180.v:514.5-514.51" + process $proc$ls180.v:514$3269 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] end - attribute \src "ls180.v:512.5-512.50" - process $proc$ls180.v:512$3272 + attribute \src "ls180.v:515.5-515.50" + process $proc$ls180.v:515$3270 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] end - attribute \src "ls180.v:513.5-513.54" - process $proc$ls180.v:513$3273 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:514.5-514.55" - process $proc$ls180.v:514$3274 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:515.5-515.56" - process $proc$ls180.v:515$3275 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:5150.1-5157.4" - process $proc$ls180.v:5150$980 + attribute \src "ls180.v:5153.1-5160.4" + process $proc$ls180.v:5153$980 assign { } { } assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:5152.2-5156.5" + attribute \src "ls180.v:5155.2-5159.5" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:5152.6-5152.38" + attribute \src "ls180.v:5155.6-5155.38" case 1'1 assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:5154.6-5154.10" + attribute \src "ls180.v:5157.6-5157.10" case assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 end sync always update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:516.5-516.50" - process $proc$ls180.v:516$3276 + attribute \src "ls180.v:516.5-516.54" + process $proc$ls180.v:516$3271 assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:517.5-517.55" + process $proc$ls180.v:517$3272 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:5172.1-5179.4" - process $proc$ls180.v:5172$1003 + attribute \src "ls180.v:5175.1-5182.4" + process $proc$ls180.v:5175$1003 assign { } { } assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5174.2-5178.5" + attribute \src "ls180.v:5177.2-5181.5" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:5174.6-5174.44" + attribute \src "ls180.v:5177.6-5177.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:5176.6-5176.10" + attribute \src "ls180.v:5179.6-5179.10" case assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:5182.1-5189.4" - process $proc$ls180.v:5182$1014 + attribute \src "ls180.v:518.5-518.56" + process $proc$ls180.v:518$3273 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:5185.1-5192.4" + process $proc$ls180.v:5185$1014 assign { } { } assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5184.2-5188.5" + attribute \src "ls180.v:5187.2-5191.5" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:5184.6-5184.44" + attribute \src "ls180.v:5187.6-5187.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:5186.6-5186.10" + attribute \src "ls180.v:5189.6-5189.10" case assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:519.5-519.67" - process $proc$ls180.v:519$3277 + attribute \src "ls180.v:519.5-519.50" + process $proc$ls180.v:519$3274 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:5192.1-5199.4" - process $proc$ls180.v:5192$1025 + attribute \src "ls180.v:5195.1-5202.4" + process $proc$ls180.v:5195$1025 assign { } { } assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5194.2-5198.5" + attribute \src "ls180.v:5197.2-5201.5" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5194.6-5194.44" + attribute \src "ls180.v:5197.6-5197.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5196.6-5196.10" + attribute \src "ls180.v:5199.6-5199.10" case assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:520.5-520.66" - process $proc$ls180.v:520$3278 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:5202.1-5209.4" - process $proc$ls180.v:5202$1036 + attribute \src "ls180.v:5205.1-5212.4" + process $proc$ls180.v:5205$1036 assign { } { } assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5204.2-5208.5" + attribute \src "ls180.v:5207.2-5211.5" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5204.6-5204.44" + attribute \src "ls180.v:5207.6-5207.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5206.6-5206.10" + attribute \src "ls180.v:5209.6-5209.10" case assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:5210.1-5289.4" - process $proc$ls180.v:5210$1037 + attribute \src "ls180.v:5213.1-5292.4" + process $proc$ls180.v:5213$1037 assign { } { } assign { } { } assign { } { } @@ -289560,36 +292053,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign { } { } assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5227.2-5288.9" + attribute \src "ls180.v:5230.2-5291.9" switch \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5231.4-5233.7" - switch $eq$ls180.v:5231$1038_Y - attribute \src "ls180.v:5231.8-5231.48" + attribute \src "ls180.v:5234.4-5236.7" + switch $eq$ls180.v:5234$1038_Y + attribute \src "ls180.v:5234.8-5234.48" case 1'1 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 case end - attribute \src "ls180.v:5234.4-5259.11" + attribute \src "ls180.v:5237.4-5262.11" switch \main_sdcore_crc16_inserter_cnt attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -289617,18 +292110,18 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } case end - attribute \src "ls180.v:5260.4-5267.7" + attribute \src "ls180.v:5263.4-5270.7" switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5260.8-5260.47" + attribute \src "ls180.v:5263.8-5263.47" case 1'1 - attribute \src "ls180.v:5261.5-5266.8" - switch $eq$ls180.v:5261$1039_Y - attribute \src "ls180.v:5261.9-5261.49" + attribute \src "ls180.v:5264.5-5269.8" + switch $eq$ls180.v:5264$1039_Y + attribute \src "ls180.v:5264.9-5264.49" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5263.9-5263.13" + attribute \src "ls180.v:5266.9-5266.13" case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5264$1040_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5267$1040_Y assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case @@ -289647,9 +292140,9 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5282.4-5286.7" - switch $and$ls180.v:5282$1042_Y - attribute \src "ls180.v:5282.8-5282.128" + attribute \src "ls180.v:5285.4-5289.7" + switch $and$ls180.v:5285$1042_Y + attribute \src "ls180.v:5285.8-5285.128" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 @@ -289674,13 +292167,29 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:5290.1-5295.4" - process $proc$ls180.v:5290$1043 + attribute \src "ls180.v:522.5-522.67" + process $proc$ls180.v:522$3275 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:523.5-523.66" + process $proc$ls180.v:523$3276 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:5293.1-5298.4" + process $proc$ls180.v:5293$1043 assign { } { } assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5292.2-5294.5" - switch $and$ls180.v:5292$1050_Y - attribute \src "ls180.v:5292.6-5292.301" + attribute \src "ls180.v:5295.2-5297.5" + switch $and$ls180.v:5295$1050_Y + attribute \src "ls180.v:5295.6-5295.301" case 1'1 assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 case @@ -289688,77 +292197,77 @@ module \ls180 sync always update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:5298.1-5305.4" - process $proc$ls180.v:5298$1052 + attribute \src "ls180.v:5301.1-5308.4" + process $proc$ls180.v:5301$1052 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5300.2-5304.5" - switch $eq$ls180.v:5300$1053_Y - attribute \src "ls180.v:5300.6-5300.45" + attribute \src "ls180.v:5303.2-5307.5" + switch $eq$ls180.v:5303$1053_Y + attribute \src "ls180.v:5303.6-5303.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5302.6-5302.10" + attribute \src "ls180.v:5305.6-5305.10" case assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:5308.1-5315.4" - process $proc$ls180.v:5308$1055 + attribute \src "ls180.v:5311.1-5318.4" + process $proc$ls180.v:5311$1055 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5310.2-5314.5" - switch $eq$ls180.v:5310$1056_Y - attribute \src "ls180.v:5310.6-5310.45" + attribute \src "ls180.v:5313.2-5317.5" + switch $eq$ls180.v:5313$1056_Y + attribute \src "ls180.v:5313.6-5313.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5312.6-5312.10" + attribute \src "ls180.v:5315.6-5315.10" case assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:5318.1-5325.4" - process $proc$ls180.v:5318$1058 + attribute \src "ls180.v:5321.1-5328.4" + process $proc$ls180.v:5321$1058 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5320.2-5324.5" - switch $eq$ls180.v:5320$1059_Y - attribute \src "ls180.v:5320.6-5320.45" + attribute \src "ls180.v:5323.2-5327.5" + switch $eq$ls180.v:5323$1059_Y + attribute \src "ls180.v:5323.6-5323.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5322.6-5322.10" + attribute \src "ls180.v:5325.6-5325.10" case assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:5328.1-5335.4" - process $proc$ls180.v:5328$1061 + attribute \src "ls180.v:5331.1-5338.4" + process $proc$ls180.v:5331$1061 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5330.2-5334.5" - switch $eq$ls180.v:5330$1062_Y - attribute \src "ls180.v:5330.6-5330.45" + attribute \src "ls180.v:5333.2-5337.5" + switch $eq$ls180.v:5333$1062_Y + attribute \src "ls180.v:5333.6-5333.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5332.6-5332.10" + attribute \src "ls180.v:5335.6-5335.10" case assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:5337.1-5342.4" - process $proc$ls180.v:5337$1063 + attribute \src "ls180.v:5340.1-5345.4" + process $proc$ls180.v:5340$1063 assign { } { } assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5339.2-5341.5" - switch $and$ls180.v:5339$1065_Y - attribute \src "ls180.v:5339.6-5339.85" + attribute \src "ls180.v:5342.2-5344.5" + switch $and$ls180.v:5342$1065_Y + attribute \src "ls180.v:5342.6-5342.85" case 1'1 assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 case @@ -289766,128 +292275,104 @@ module \ls180 sync always update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:5343.1-5350.4" - process $proc$ls180.v:5343$1066 + attribute \src "ls180.v:5346.1-5353.4" + process $proc$ls180.v:5346$1066 assign { } { } assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5345.2-5349.5" - switch $lt$ls180.v:5345$1067_Y - attribute \src "ls180.v:5345.6-5345.44" + attribute \src "ls180.v:5348.2-5352.5" + switch $lt$ls180.v:5348$1067_Y + attribute \src "ls180.v:5348.6-5348.44" case 1'1 assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5347.6-5347.10" + attribute \src "ls180.v:5350.6-5350.10" case assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:535.11-535.68" - process $proc$ls180.v:535$3279 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:5354.1-5361.4" - process $proc$ls180.v:5354$1078 + attribute \src "ls180.v:5357.1-5364.4" + process $proc$ls180.v:5357$1078 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5356.2-5360.5" + attribute \src "ls180.v:5359.2-5363.5" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5356.6-5356.43" + attribute \src "ls180.v:5359.6-5359.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5358.6-5358.10" + attribute \src "ls180.v:5361.6-5361.10" case assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end sync always update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:536.5-536.64" - process $proc$ls180.v:536$3280 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:5364.1-5371.4" - process $proc$ls180.v:5364$1089 + attribute \src "ls180.v:5367.1-5374.4" + process $proc$ls180.v:5367$1089 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5366.2-5370.5" + attribute \src "ls180.v:5369.2-5373.5" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5366.6-5366.43" + attribute \src "ls180.v:5369.6-5369.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5368.6-5368.10" + attribute \src "ls180.v:5371.6-5371.10" case assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:537.11-537.70" - process $proc$ls180.v:537$3281 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:5374.1-5381.4" - process $proc$ls180.v:5374$1100 + attribute \src "ls180.v:5377.1-5384.4" + process $proc$ls180.v:5377$1100 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5376.2-5380.5" + attribute \src "ls180.v:5379.2-5383.5" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5376.6-5376.43" + attribute \src "ls180.v:5379.6-5379.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5378.6-5378.10" + attribute \src "ls180.v:5381.6-5381.10" case assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:538.11-538.70" - process $proc$ls180.v:538$3282 + attribute \src "ls180.v:538.11-538.68" + process $proc$ls180.v:538$3277 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:5384.1-5391.4" - process $proc$ls180.v:5384$1111 + attribute \src "ls180.v:5387.1-5394.4" + process $proc$ls180.v:5387$1111 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5386.2-5390.5" + attribute \src "ls180.v:5389.2-5393.5" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5386.6-5386.43" + attribute \src "ls180.v:5389.6-5389.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5388.6-5388.10" + attribute \src "ls180.v:5391.6-5391.10" case assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:539.11-539.73" - process $proc$ls180.v:539$3283 + attribute \src "ls180.v:539.5-539.64" + process $proc$ls180.v:539$3278 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:5392.1-5582.4" - process $proc$ls180.v:5392$1112 + attribute \src "ls180.v:5395.1-5585.4" + process $proc$ls180.v:5395$1112 assign { } { } assign { } { } assign { } { } @@ -289927,7 +292412,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 @@ -289966,13 +292450,14 @@ module \ls180 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5433.2-5581.9" + attribute \src "ls180.v:5436.2-5584.9" switch \builder_sdcore_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5436.4-5456.11" + attribute \src "ls180.v:5439.4-5459.11" switch \main_sdcore_cmd_count attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -289992,27 +292477,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5454$1113_Y + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5457$1113_Y case end - attribute \src "ls180.v:5457.4-5469.7" - switch $and$ls180.v:5457$1114_Y - attribute \src "ls180.v:5457.8-5457.65" + attribute \src "ls180.v:5460.4-5472.7" + switch $and$ls180.v:5460$1114_Y + attribute \src "ls180.v:5460.8-5460.65" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5458$1115_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5461$1115_Y assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5460.5-5468.8" - switch $eq$ls180.v:5460$1116_Y - attribute \src "ls180.v:5460.9-5460.40" + attribute \src "ls180.v:5463.5-5471.8" + switch $eq$ls180.v:5463$1116_Y + attribute \src "ls180.v:5463.9-5463.40" case 1'1 - attribute \src "ls180.v:5461.6-5467.9" - switch $eq$ls180.v:5461$1117_Y - attribute \src "ls180.v:5461.10-5461.40" + attribute \src "ls180.v:5464.6-5470.9" + switch $eq$ls180.v:5464$1117_Y + attribute \src "ls180.v:5464.10-5464.40" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5465.10-5465.14" + attribute \src "ls180.v:5468.10-5468.14" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 end @@ -290023,52 +292508,52 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5473$1118_Y + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5476$1118_Y assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5474.4-5478.7" - switch $eq$ls180.v:5474$1119_Y - attribute \src "ls180.v:5474.8-5474.38" + attribute \src "ls180.v:5477.4-5481.7" + switch $eq$ls180.v:5477$1119_Y + attribute \src "ls180.v:5477.8-5477.38" case 1'1 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5476.8-5476.12" + attribute \src "ls180.v:5479.8-5479.12" case assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5480.4-5501.7" + attribute \src "ls180.v:5483.4-5504.7" switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5480.8-5480.36" + attribute \src "ls180.v:5483.8-5483.36" case 1'1 - attribute \src "ls180.v:5481.5-5500.8" - switch $eq$ls180.v:5481$1120_Y - attribute \src "ls180.v:5481.9-5481.56" + attribute \src "ls180.v:5484.5-5503.8" + switch $eq$ls180.v:5484$1120_Y + attribute \src "ls180.v:5484.9-5484.56" case 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5485.9-5485.13" + attribute \src "ls180.v:5488.9-5488.13" case - attribute \src "ls180.v:5486.6-5499.9" + attribute \src "ls180.v:5489.6-5502.9" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5486.10-5486.37" + attribute \src "ls180.v:5489.10-5489.37" case 1'1 - attribute \src "ls180.v:5487.7-5495.10" - switch $eq$ls180.v:5487$1121_Y - attribute \src "ls180.v:5487.11-5487.42" + attribute \src "ls180.v:5490.7-5498.10" + switch $eq$ls180.v:5490$1121_Y + attribute \src "ls180.v:5490.11-5490.42" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5489.11-5489.15" + attribute \src "ls180.v:5492.11-5492.15" case - attribute \src "ls180.v:5490.8-5494.11" - switch $eq$ls180.v:5490$1122_Y - attribute \src "ls180.v:5490.12-5490.43" + attribute \src "ls180.v:5493.8-5497.11" + switch $eq$ls180.v:5493$1122_Y + attribute \src "ls180.v:5493.12-5493.43" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5492.12-5492.16" + attribute \src "ls180.v:5495.12-5495.16" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 end end - attribute \src "ls180.v:5496.10-5496.14" + attribute \src "ls180.v:5499.10-5499.14" case assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 @@ -290084,28 +292569,28 @@ module \ls180 assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5509.4-5515.7" - switch $and$ls180.v:5509$1124_Y - attribute \src "ls180.v:5509.8-5509.98" + attribute \src "ls180.v:5512.4-5518.7" + switch $and$ls180.v:5512$1124_Y + attribute \src "ls180.v:5512.8-5512.98" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5510$1125_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5513$1125_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5512.5-5514.8" - switch $eq$ls180.v:5512$1127_Y - attribute \src "ls180.v:5512.9-5512.77" + attribute \src "ls180.v:5515.5-5517.8" + switch $eq$ls180.v:5515$1127_Y + attribute \src "ls180.v:5515.9-5515.77" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 case end case end - attribute \src "ls180.v:5517.4-5522.7" + attribute \src "ls180.v:5520.4-5525.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5517.8-5517.37" + attribute \src "ls180.v:5520.8-5520.37" case 1'1 - attribute \src "ls180.v:5518.5-5521.8" - switch $ne$ls180.v:5518$1128_Y - attribute \src "ls180.v:5518.9-5518.57" + attribute \src "ls180.v:5521.5-5524.8" + switch $ne$ls180.v:5521$1128_Y + attribute \src "ls180.v:5521.9-5521.57" case 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 @@ -290117,42 +292602,42 @@ module \ls180 case 3'100 assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5527$1130_Y - attribute \src "ls180.v:5528.4-5554.7" + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5530$1130_Y + attribute \src "ls180.v:5531.4-5557.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5528.8-5528.37" + attribute \src "ls180.v:5531.8-5531.37" case 1'1 - attribute \src "ls180.v:5529.5-5553.8" - switch $eq$ls180.v:5529$1131_Y - attribute \src "ls180.v:5529.9-5529.57" + attribute \src "ls180.v:5532.5-5556.8" + switch $eq$ls180.v:5532$1131_Y + attribute \src "ls180.v:5532.9-5532.57" case 1'1 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5535.6-5543.9" - switch $and$ls180.v:5535$1132_Y - attribute \src "ls180.v:5535.10-5535.72" + attribute \src "ls180.v:5538.6-5546.9" + switch $and$ls180.v:5538$1132_Y + attribute \src "ls180.v:5538.10-5538.72" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5536$1133_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5539$1133_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5538.7-5542.10" - switch $eq$ls180.v:5538$1135_Y - attribute \src "ls180.v:5538.11-5538.79" + attribute \src "ls180.v:5541.7-5545.10" + switch $eq$ls180.v:5541$1135_Y + attribute \src "ls180.v:5541.11-5541.79" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5540.11-5540.15" + attribute \src "ls180.v:5543.11-5543.15" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 end case end - attribute \src "ls180.v:5544.9-5544.13" + attribute \src "ls180.v:5547.9-5547.13" case - attribute \src "ls180.v:5545.6-5552.9" - switch $eq$ls180.v:5545$1136_Y - attribute \src "ls180.v:5545.10-5545.58" + attribute \src "ls180.v:5548.6-5555.9" + switch $eq$ls180.v:5548$1136_Y + attribute \src "ls180.v:5548.10-5548.58" case 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 @@ -290175,9 +292660,9 @@ module \ls180 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5565.4-5579.7" + attribute \src "ls180.v:5568.4-5582.7" switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5565.8-5565.31" + attribute \src "ls180.v:5568.8-5568.31" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 @@ -290236,6 +292721,30 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end + attribute \src "ls180.v:540.11-540.70" + process $proc$ls180.v:540$3279 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:541.11-541.70" + process $proc$ls180.v:541$3280 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:542.11-542.73" + process $proc$ls180.v:542$3281 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end attribute \src "ls180.v:55.5-55.42" process $proc$ls180.v:55$3126 assign { } { } @@ -290252,56 +292761,32 @@ module \ls180 sync init update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] end - attribute \src "ls180.v:560.5-560.59" - process $proc$ls180.v:560$3284 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:5610.1-5617.4" - process $proc$ls180.v:5610$1137 + attribute \src "ls180.v:5613.1-5620.4" + process $proc$ls180.v:5613$1137 assign { } { } assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5612.2-5616.5" + attribute \src "ls180.v:5615.2-5619.5" switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5612.6-5612.35" + attribute \src "ls180.v:5615.6-5615.35" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5613$1138_Y - attribute \src "ls180.v:5614.6-5614.10" + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5616$1138_Y + attribute \src "ls180.v:5617.6-5617.10" case assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce end sync always update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:562.5-562.59" - process $proc$ls180.v:562$3285 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:563.5-563.58" - process $proc$ls180.v:563$3286 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:564.5-564.64" - process $proc$ls180.v:564$3287 + attribute \src "ls180.v:563.5-563.59" + process $proc$ls180.v:563$3282 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:5643.1-5682.4" - process $proc$ls180.v:5643$1148 + attribute \src "ls180.v:5646.1-5685.4" + process $proc$ls180.v:5646$1148 assign { } { } assign { } { } assign { } { } @@ -290319,31 +292804,31 @@ module \ls180 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5653.2-5681.9" + attribute \src "ls180.v:5656.2-5684.9" switch \builder_sdblock2memdma_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5657$1149_Y + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5660$1149_Y assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5659.4-5670.7" - switch $and$ls180.v:5659$1150_Y - attribute \src "ls180.v:5659.8-5659.103" + attribute \src "ls180.v:5662.4-5673.7" + switch $and$ls180.v:5662$1150_Y + attribute \src "ls180.v:5662.8-5662.103" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5660$1151_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5663$1151_Y assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5662.5-5669.8" - switch $eq$ls180.v:5662$1153_Y - attribute \src "ls180.v:5662.9-5662.106" + attribute \src "ls180.v:5665.5-5672.8" + switch $eq$ls180.v:5665$1153_Y + attribute \src "ls180.v:5665.9-5665.106" case 1'1 - attribute \src "ls180.v:5663.6-5668.9" + attribute \src "ls180.v:5666.6-5671.9" switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5663.10-5663.57" + attribute \src "ls180.v:5666.10-5666.57" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5666.10-5666.14" + attribute \src "ls180.v:5669.10-5669.14" case assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 end @@ -290371,37 +292856,45 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:565.12-565.74" - process $proc$ls180.v:565$3288 + attribute \src "ls180.v:565.5-565.59" + process $proc$ls180.v:565$3283 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:566.12-566.47" - process $proc$ls180.v:566$3289 + attribute \src "ls180.v:566.5-566.58" + process $proc$ls180.v:566$3284 assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:567.5-567.46" - process $proc$ls180.v:567$3290 + attribute \src "ls180.v:567.5-567.64" + process $proc$ls180.v:567$3285 assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:569.5-569.44" - process $proc$ls180.v:569$3291 + attribute \src "ls180.v:568.12-568.74" + process $proc$ls180.v:568$3286 assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:569.12-569.47" + process $proc$ls180.v:569$3287 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end attribute \src "ls180.v:57.12-57.60" process $proc$ls180.v:57$3128 @@ -290411,16 +292904,16 @@ module \ls180 sync init update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] end - attribute \src "ls180.v:570.5-570.45" - process $proc$ls180.v:570$3292 + attribute \src "ls180.v:570.5-570.46" + process $proc$ls180.v:570$3288 assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] end - attribute \src "ls180.v:5702.1-5739.4" - process $proc$ls180.v:5702$1155 + attribute \src "ls180.v:5705.1-5742.4" + process $proc$ls180.v:5705$1155 assign { } { } assign { } { } assign { } { } @@ -290446,16 +292939,16 @@ module \ls180 assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5716.2-5738.9" + attribute \src "ls180.v:5719.2-5741.9" switch \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5721.4-5724.7" + attribute \src "ls180.v:5724.4-5727.7" switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5721.8-5721.41" + attribute \src "ls180.v:5724.8-5724.41" case 1'1 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 @@ -290468,9 +292961,9 @@ module \ls180 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_interface1_bus_sel[7:0] 8'11111111 assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5732.4-5736.7" - switch $and$ls180.v:5732$1156_Y - attribute \src "ls180.v:5732.8-5732.59" + attribute \src "ls180.v:5735.4-5739.7" + switch $and$ls180.v:5735$1156_Y + attribute \src "ls180.v:5735.8-5735.59" case 1'1 assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 @@ -290492,32 +292985,32 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:571.5-571.54" - process $proc$ls180.v:571$3293 + attribute \src "ls180.v:572.5-572.44" + process $proc$ls180.v:572$3289 assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] end - attribute \src "ls180.v:573.32-573.76" - process $proc$ls180.v:573$3294 + attribute \src "ls180.v:573.5-573.45" + process $proc$ls180.v:573$3290 assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] end - attribute \src "ls180.v:574.11-574.55" - process $proc$ls180.v:574$3295 + attribute \src "ls180.v:574.5-574.54" + process $proc$ls180.v:574$3291 assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:5740.1-5776.4" - process $proc$ls180.v:5740$1157 + attribute \src "ls180.v:5743.1-5779.4" + process $proc$ls180.v:5743$1157 assign { } { } assign { } { } assign { } { } @@ -290525,38 +293018,38 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 assign { } { } + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5749.2-5775.9" + attribute \src "ls180.v:5752.2-5778.9" switch \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5752$1159_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5753$1160_Y - attribute \src "ls180.v:5754.4-5765.7" + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5755$1159_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5756$1160_Y + attribute \src "ls180.v:5757.4-5768.7" switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5754.8-5754.39" + attribute \src "ls180.v:5757.8-5757.39" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5755$1161_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5758$1161_Y assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5757.5-5764.8" + attribute \src "ls180.v:5760.5-5767.8" switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5757.9-5757.39" + attribute \src "ls180.v:5760.9-5760.39" case 1'1 - attribute \src "ls180.v:5758.6-5763.9" + attribute \src "ls180.v:5761.6-5766.9" switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5758.10-5758.43" + attribute \src "ls180.v:5761.10-5761.43" case 1'1 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5761.10-5761.14" + attribute \src "ls180.v:5764.10-5764.14" case assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end @@ -290582,27 +293075,35 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:576.32-576.75" - process $proc$ls180.v:576$3296 + attribute \src "ls180.v:576.32-576.76" + process $proc$ls180.v:576$3292 assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "ls180.v:578.32-578.76" - process $proc$ls180.v:578$3297 + attribute \src "ls180.v:577.11-577.55" + process $proc$ls180.v:577$3293 assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:579.32-579.75" + process $proc$ls180.v:579$3294 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init end - attribute \src "ls180.v:5788.1-5816.4" - process $proc$ls180.v:5788$1167 + attribute \src "ls180.v:5791.1-5819.4" + process $proc$ls180.v:5791$1167 assign { } { } assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5790.2-5815.9" + attribute \src "ls180.v:5793.2-5818.9" switch \main_sdmem2block_converter_mux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -290640,32 +293141,32 @@ module \ls180 sync init update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] end - attribute \src "ls180.v:5830.1-5837.4" - process $proc$ls180.v:5830$1168 + attribute \src "ls180.v:581.32-581.76" + process $proc$ls180.v:581$3295 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:5833.1-5840.4" + process $proc$ls180.v:5833$1168 assign { } { } assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5832.2-5836.5" + attribute \src "ls180.v:5835.2-5839.5" switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5832.6-5832.35" + attribute \src "ls180.v:5835.6-5835.35" case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5833$1169_Y - attribute \src "ls180.v:5834.6-5834.10" + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5836$1169_Y + attribute \src "ls180.v:5837.6-5837.10" case assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce end sync always update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:584.5-584.51" - process $proc$ls180.v:584$3298 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - end - attribute \src "ls180.v:5845.1-5881.4" - process $proc$ls180.v:5845$1175 + attribute \src "ls180.v:5848.1-5884.4" + process $proc$ls180.v:5848$1175 assign { } { } assign { } { } assign { } { } @@ -290675,8 +293176,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign { } { } assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 @@ -290684,8 +293183,10 @@ module \ls180 assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign { } { } assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5856.2-5880.9" + attribute \src "ls180.v:5859.2-5883.9" switch \builder_state attribute \src "ls180.v:0.0-0.0" case 2'01 @@ -290703,13 +293204,13 @@ module \ls180 case assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5872.4-5878.7" - switch $and$ls180.v:5872$1176_Y - attribute \src "ls180.v:5872.8-5872.77" + attribute \src "ls180.v:5875.4-5881.7" + switch $and$ls180.v:5875$1176_Y + attribute \src "ls180.v:5875.8-5875.77" case 1'1 assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5875$1178_Y + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5878$1178_Y assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 assign $0\builder_next_state[1:0] 2'01 case @@ -290726,151 +293227,143 @@ module \ls180 update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:585.5-585.51" - process $proc$ls180.v:585$3299 + attribute \src "ls180.v:587.5-587.51" + process $proc$ls180.v:587$3296 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:588.5-588.51" + process $proc$ls180.v:588$3297 assign { } { } assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] end - attribute \src "ls180.v:587.5-587.47" - process $proc$ls180.v:587$3300 + attribute \src "ls180.v:590.5-590.47" + process $proc$ls180.v:590$3298 assign { } { } assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] end - attribute \src "ls180.v:588.5-588.45" - process $proc$ls180.v:588$3301 + attribute \src "ls180.v:5909.1-5924.4" + process $proc$ls180.v:5909$1199 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[12:0] [0] $eq$ls180.v:5911$1200_Y + assign $0\builder_slave_sel[12:0] [1] $eq$ls180.v:5912$1201_Y + assign $0\builder_slave_sel[12:0] [2] $eq$ls180.v:5913$1202_Y + assign $0\builder_slave_sel[12:0] [3] $eq$ls180.v:5914$1203_Y + assign $0\builder_slave_sel[12:0] [4] $eq$ls180.v:5915$1204_Y + assign $0\builder_slave_sel[12:0] [5] $eq$ls180.v:5916$1205_Y + assign $0\builder_slave_sel[12:0] [6] $eq$ls180.v:5917$1206_Y + assign $0\builder_slave_sel[12:0] [7] $eq$ls180.v:5918$1207_Y + assign $0\builder_slave_sel[12:0] [8] $eq$ls180.v:5919$1208_Y + assign $0\builder_slave_sel[12:0] [9] $eq$ls180.v:5920$1209_Y + assign $0\builder_slave_sel[12:0] [10] $eq$ls180.v:5921$1210_Y + assign $0\builder_slave_sel[12:0] [11] $eq$ls180.v:5922$1211_Y + assign $0\builder_slave_sel[12:0] [12] $eq$ls180.v:5923$1212_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[12:0] + end + attribute \src "ls180.v:591.5-591.45" + process $proc$ls180.v:591$3299 assign { } { } assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] end - attribute \src "ls180.v:589.5-589.45" - process $proc$ls180.v:589$3302 + attribute \src "ls180.v:592.5-592.45" + process $proc$ls180.v:592$3300 assign { } { } assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:590.12-590.57" - process $proc$ls180.v:590$3303 + attribute \src "ls180.v:593.12-593.57" + process $proc$ls180.v:593$3301 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:5906.1-5921.4" - process $proc$ls180.v:5906$1199 - assign { } { } - assign { } { } - assign $0\builder_slave_sel[12:0] [0] $eq$ls180.v:5908$1200_Y - assign $0\builder_slave_sel[12:0] [1] $eq$ls180.v:5909$1201_Y - assign $0\builder_slave_sel[12:0] [2] $eq$ls180.v:5910$1202_Y - assign $0\builder_slave_sel[12:0] [3] $eq$ls180.v:5911$1203_Y - assign $0\builder_slave_sel[12:0] [4] $eq$ls180.v:5912$1204_Y - assign $0\builder_slave_sel[12:0] [5] $eq$ls180.v:5913$1205_Y - assign $0\builder_slave_sel[12:0] [6] $eq$ls180.v:5914$1206_Y - assign $0\builder_slave_sel[12:0] [7] $eq$ls180.v:5915$1207_Y - assign $0\builder_slave_sel[12:0] [8] $eq$ls180.v:5916$1208_Y - assign $0\builder_slave_sel[12:0] [9] $eq$ls180.v:5917$1209_Y - assign $0\builder_slave_sel[12:0] [10] $eq$ls180.v:5918$1210_Y - assign $0\builder_slave_sel[12:0] [11] $eq$ls180.v:5919$1211_Y - assign $0\builder_slave_sel[12:0] [12] $eq$ls180.v:5920$1212_Y - sync always - update \builder_slave_sel $0\builder_slave_sel[12:0] - end - attribute \src "ls180.v:592.5-592.51" - process $proc$ls180.v:592$3304 + attribute \src "ls180.v:595.5-595.51" + process $proc$ls180.v:595$3302 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:593.5-593.51" - process $proc$ls180.v:593$3305 + attribute \src "ls180.v:596.5-596.51" + process $proc$ls180.v:596$3303 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] end - attribute \src "ls180.v:594.5-594.50" - process $proc$ls180.v:594$3306 + attribute \src "ls180.v:597.5-597.50" + process $proc$ls180.v:597$3304 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] end - attribute \src "ls180.v:595.5-595.54" - process $proc$ls180.v:595$3307 + attribute \src "ls180.v:598.5-598.54" + process $proc$ls180.v:598$3305 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:596.5-596.55" - process $proc$ls180.v:596$3308 + attribute \src "ls180.v:599.5-599.55" + process $proc$ls180.v:599$3306 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:597.5-597.56" - process $proc$ls180.v:597$3309 + attribute \src "ls180.v:600.5-600.56" + process $proc$ls180.v:600$3307 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:598.5-598.50" - process $proc$ls180.v:598$3310 + attribute \src "ls180.v:601.5-601.50" + process $proc$ls180.v:601$3308 assign { } { } assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:601.5-601.67" - process $proc$ls180.v:601$3311 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:602.5-602.66" - process $proc$ls180.v:602$3312 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6028.1-6039.4" - process $proc$ls180.v:6028$1241 + attribute \src "ls180.v:6031.1-6042.4" + process $proc$ls180.v:6031$1241 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\builder_error[0:0] 1'0 - assign $0\builder_shared_ack[0:0] $or$ls180.v:6032$1253_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:6033$1278_Y [31:0] - attribute \src "ls180.v:6034.2-6038.5" + assign $0\builder_shared_ack[0:0] $or$ls180.v:6035$1253_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:6036$1278_Y [31:0] + attribute \src "ls180.v:6037.2-6041.5" switch \builder_done - attribute \src "ls180.v:6034.6-6034.18" + attribute \src "ls180.v:6037.6-6037.18" case 1'1 assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 assign $0\builder_shared_ack[0:0] 1'1 @@ -290882,40 +293375,56 @@ module \ls180 update \builder_shared_ack $0\builder_shared_ack[0:0] update \builder_error $0\builder_error[0:0] end - attribute \src "ls180.v:617.11-617.68" - process $proc$ls180.v:617$3313 + attribute \src "ls180.v:604.5-604.67" + process $proc$ls180.v:604$3309 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:605.5-605.66" + process $proc$ls180.v:605$3310 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:620.11-620.68" + process $proc$ls180.v:620$3311 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:618.5-618.64" - process $proc$ls180.v:618$3314 + attribute \src "ls180.v:621.5-621.64" + process $proc$ls180.v:621$3312 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:619.11-619.70" - process $proc$ls180.v:619$3315 + attribute \src "ls180.v:622.11-622.70" + process $proc$ls180.v:622$3313 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:620.11-620.70" - process $proc$ls180.v:620$3316 + attribute \src "ls180.v:623.11-623.70" + process $proc$ls180.v:623$3314 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:621.11-621.73" - process $proc$ls180.v:621$3317 + attribute \src "ls180.v:624.11-624.73" + process $proc$ls180.v:624$3315 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -290930,109 +293439,93 @@ module \ls180 sync init update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end - attribute \src "ls180.v:642.5-642.59" - process $proc$ls180.v:642$3318 + attribute \src "ls180.v:645.5-645.59" + process $proc$ls180.v:645$3316 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:644.5-644.59" - process $proc$ls180.v:644$3319 + attribute \src "ls180.v:647.5-647.59" + process $proc$ls180.v:647$3317 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:645.5-645.58" - process $proc$ls180.v:645$3320 + attribute \src "ls180.v:648.5-648.58" + process $proc$ls180.v:648$3318 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:646.5-646.64" - process $proc$ls180.v:646$3321 + attribute \src "ls180.v:649.5-649.64" + process $proc$ls180.v:649$3319 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:647.12-647.74" - process $proc$ls180.v:647$3322 + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$3131 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:650.12-650.74" + process $proc$ls180.v:650$3320 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:648.12-648.47" - process $proc$ls180.v:648$3323 + attribute \src "ls180.v:651.12-651.47" + process $proc$ls180.v:651$3321 assign { } { } assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end - attribute \src "ls180.v:649.5-649.46" - process $proc$ls180.v:649$3324 + attribute \src "ls180.v:652.5-652.46" + process $proc$ls180.v:652$3322 assign { } { } assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end - attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$3131 - assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:651.5-651.44" - process $proc$ls180.v:651$3325 + attribute \src "ls180.v:654.5-654.44" + process $proc$ls180.v:654$3323 assign { } { } assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] end - attribute \src "ls180.v:652.5-652.45" - process $proc$ls180.v:652$3326 + attribute \src "ls180.v:655.5-655.45" + process $proc$ls180.v:655$3324 assign { } { } assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:653.5-653.54" - process $proc$ls180.v:653$3327 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:655.32-655.76" - process $proc$ls180.v:655$3328 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - end - attribute \src "ls180.v:6553.1-6558.4" - process $proc$ls180.v:6553$2152 + attribute \src "ls180.v:6556.1-6561.4" + process $proc$ls180.v:6556$2152 assign { } { } assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6555.2-6557.5" + attribute \src "ls180.v:6558.2-6560.5" switch \main_spimaster12_re - attribute \src "ls180.v:6555.6-6555.25" + attribute \src "ls180.v:6558.6-6558.25" case 1'1 assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] case @@ -291040,29 +293533,37 @@ module \ls180 sync always update \main_spimaster9_start $0\main_spimaster9_start[0:0] end - attribute \src "ls180.v:656.11-656.55" - process $proc$ls180.v:656$3329 + attribute \src "ls180.v:656.5-656.54" + process $proc$ls180.v:656$3325 assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:658.32-658.75" - process $proc$ls180.v:658$3330 + attribute \src "ls180.v:658.32-658.76" + process $proc$ls180.v:658$3326 assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "ls180.v:6599.1-6604.4" - process $proc$ls180.v:6599$2217 + attribute \src "ls180.v:659.11-659.55" + process $proc$ls180.v:659$3327 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:6602.1-6607.4" + process $proc$ls180.v:6602$2217 assign { } { } assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6601.2-6603.5" + attribute \src "ls180.v:6604.2-6606.5" switch \main_spisdcard_control_re - attribute \src "ls180.v:6601.6-6601.31" + attribute \src "ls180.v:6604.6-6604.31" case 1'1 assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] case @@ -291070,107 +293571,99 @@ module \ls180 sync always update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] end - attribute \src "ls180.v:660.32-660.76" - process $proc$ls180.v:660$3331 + attribute \src "ls180.v:661.32-661.75" + process $proc$ls180.v:661$3328 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:663.32-663.76" + process $proc$ls180.v:663$3329 assign { } { } assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init end - attribute \src "ls180.v:666.5-666.51" - process $proc$ls180.v:666$3332 + attribute \src "ls180.v:669.5-669.51" + process $proc$ls180.v:669$3330 assign { } { } assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "ls180.v:667.5-667.51" - process $proc$ls180.v:667$3333 + attribute \src "ls180.v:670.5-670.51" + process $proc$ls180.v:670$3331 assign { } { } assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:669.5-669.47" - process $proc$ls180.v:669$3334 + attribute \src "ls180.v:672.5-672.47" + process $proc$ls180.v:672$3332 assign { } { } assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:670.5-670.45" - process $proc$ls180.v:670$3335 + attribute \src "ls180.v:673.5-673.45" + process $proc$ls180.v:673$3333 assign { } { } assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:671.5-671.45" - process $proc$ls180.v:671$3336 + attribute \src "ls180.v:674.5-674.45" + process $proc$ls180.v:674$3334 assign { } { } assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:672.12-672.57" - process $proc$ls180.v:672$3337 + attribute \src "ls180.v:675.12-675.57" + process $proc$ls180.v:675$3335 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:674.5-674.51" - process $proc$ls180.v:674$3338 + attribute \src "ls180.v:677.5-677.51" + process $proc$ls180.v:677$3336 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:675.5-675.51" - process $proc$ls180.v:675$3339 + attribute \src "ls180.v:678.5-678.51" + process $proc$ls180.v:678$3337 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:676.5-676.50" - process $proc$ls180.v:676$3340 + attribute \src "ls180.v:679.5-679.50" + process $proc$ls180.v:679$3338 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:677.5-677.54" - process $proc$ls180.v:677$3341 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:678.5-678.55" - process $proc$ls180.v:678$3342 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:6788.1-6804.4" - process $proc$ls180.v:6788$2438 + attribute \src "ls180.v:6791.1-6807.4" + process $proc$ls180.v:6791$2438 assign { } { } assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6790.2-6803.9" + attribute \src "ls180.v:6793.2-6806.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291188,27 +293681,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:679.5-679.56" - process $proc$ls180.v:679$3343 + attribute \src "ls180.v:680.5-680.54" + process $proc$ls180.v:680$3339 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:680.5-680.50" - process $proc$ls180.v:680$3344 - assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:6805.1-6821.4" - process $proc$ls180.v:6805$2439 + attribute \src "ls180.v:6808.1-6824.4" + process $proc$ls180.v:6808$2439 assign { } { } assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6807.2-6820.9" + attribute \src "ls180.v:6810.2-6823.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291226,11 +293711,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:6822.1-6838.4" - process $proc$ls180.v:6822$2440 + attribute \src "ls180.v:681.5-681.55" + process $proc$ls180.v:681$3340 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:682.5-682.56" + process $proc$ls180.v:682$3341 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:6825.1-6841.4" + process $proc$ls180.v:6825$2440 assign { } { } assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6824.2-6837.9" + attribute \src "ls180.v:6827.2-6840.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291248,19 +293749,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:683.5-683.67" - process $proc$ls180.v:683$3345 + attribute \src "ls180.v:683.5-683.50" + process $proc$ls180.v:683$3342 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:6839.1-6855.4" - process $proc$ls180.v:6839$2441 + attribute \src "ls180.v:6842.1-6858.4" + process $proc$ls180.v:6842$2441 assign { } { } assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6841.2-6854.9" + attribute \src "ls180.v:6844.2-6857.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291278,19 +293779,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:684.5-684.66" - process $proc$ls180.v:684$3346 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6856.1-6872.4" - process $proc$ls180.v:6856$2442 + attribute \src "ls180.v:6859.1-6875.4" + process $proc$ls180.v:6859$2442 assign { } { } assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6858.2-6871.9" + attribute \src "ls180.v:6861.2-6874.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291308,11 +293801,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:6873.1-6889.4" - process $proc$ls180.v:6873$2443 + attribute \src "ls180.v:686.5-686.67" + process $proc$ls180.v:686$3343 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:687.5-687.66" + process $proc$ls180.v:687$3344 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6876.1-6892.4" + process $proc$ls180.v:6876$2443 assign { } { } assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6875.2-6888.9" + attribute \src "ls180.v:6878.2-6891.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291330,11 +293839,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:6890.1-6906.4" - process $proc$ls180.v:6890$2444 + attribute \src "ls180.v:6893.1-6909.4" + process $proc$ls180.v:6893$2444 assign { } { } assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6892.2-6905.9" + attribute \src "ls180.v:6895.2-6908.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291352,11 +293861,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:6907.1-6923.4" - process $proc$ls180.v:6907$2445 + attribute \src "ls180.v:6910.1-6926.4" + process $proc$ls180.v:6910$2445 assign { } { } assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6909.2-6922.9" + attribute \src "ls180.v:6912.2-6925.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291374,11 +293883,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:6924.1-6940.4" - process $proc$ls180.v:6924$2446 + attribute \src "ls180.v:6927.1-6943.4" + process $proc$ls180.v:6927$2446 assign { } { } assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6926.2-6939.9" + attribute \src "ls180.v:6929.2-6942.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291396,11 +293905,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:6941.1-6957.4" - process $proc$ls180.v:6941$2447 + attribute \src "ls180.v:6944.1-6960.4" + process $proc$ls180.v:6944$2447 assign { } { } assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6943.2-6956.9" + attribute \src "ls180.v:6946.2-6959.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291418,11 +293927,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:6958.1-6974.4" - process $proc$ls180.v:6958$2448 + attribute \src "ls180.v:6961.1-6977.4" + process $proc$ls180.v:6961$2448 assign { } { } assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6960.2-6973.9" + attribute \src "ls180.v:6963.2-6976.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291440,11 +293949,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:6975.1-6991.4" - process $proc$ls180.v:6975$2449 + attribute \src "ls180.v:6978.1-6994.4" + process $proc$ls180.v:6978$2449 assign { } { } assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6977.2-6990.9" + attribute \src "ls180.v:6980.2-6993.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291462,19 +293971,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:699.11-699.68" - process $proc$ls180.v:699$3347 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:6992.1-7008.4" - process $proc$ls180.v:6992$2450 + attribute \src "ls180.v:6995.1-7011.4" + process $proc$ls180.v:6995$2450 assign { } { } assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6994.2-7007.9" + attribute \src "ls180.v:6997.2-7010.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291492,19 +293993,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:700.5-700.64" - process $proc$ls180.v:700$3348 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:7009.1-7025.4" - process $proc$ls180.v:7009$2451 + attribute \src "ls180.v:7012.1-7028.4" + process $proc$ls180.v:7012$2451 assign { } { } assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:7011.2-7024.9" + attribute \src "ls180.v:7014.2-7027.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291522,27 +294015,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:701.11-701.70" - process $proc$ls180.v:701$3349 + attribute \src "ls180.v:702.11-702.68" + process $proc$ls180.v:702$3345 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:702.11-702.70" - process $proc$ls180.v:702$3350 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:7026.1-7042.4" - process $proc$ls180.v:7026$2452 + attribute \src "ls180.v:7029.1-7045.4" + process $proc$ls180.v:7029$2452 assign { } { } assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:7028.2-7041.9" + attribute \src "ls180.v:7031.2-7044.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291560,19 +294045,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:703.11-703.73" - process $proc$ls180.v:703$3351 + attribute \src "ls180.v:703.5-703.64" + process $proc$ls180.v:703$3346 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:7043.1-7059.4" - process $proc$ls180.v:7043$2453 + attribute \src "ls180.v:704.11-704.70" + process $proc$ls180.v:704$3347 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:7046.1-7062.4" + process $proc$ls180.v:7046$2453 assign { } { } assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7045.2-7058.9" + attribute \src "ls180.v:7048.2-7061.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291590,11 +294083,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:7060.1-7076.4" - process $proc$ls180.v:7060$2454 + attribute \src "ls180.v:705.11-705.70" + process $proc$ls180.v:705$3348 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:706.11-706.73" + process $proc$ls180.v:706$3349 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:7063.1-7079.4" + process $proc$ls180.v:7063$2454 assign { } { } assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7062.2-7075.9" + attribute \src "ls180.v:7065.2-7078.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291612,11 +294121,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:7077.1-7093.4" - process $proc$ls180.v:7077$2455 + attribute \src "ls180.v:7080.1-7096.4" + process $proc$ls180.v:7080$2455 assign { } { } assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7079.2-7092.9" + attribute \src "ls180.v:7082.2-7095.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -291634,11 +294143,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:7094.1-7101.4" - process $proc$ls180.v:7094$2456 + attribute \src "ls180.v:7097.1-7104.4" + process $proc$ls180.v:7097$2456 assign { } { } assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7096.2-7100.9" + attribute \src "ls180.v:7099.2-7103.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -291647,11 +294156,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:7102.1-7109.4" - process $proc$ls180.v:7102$2457 + attribute \src "ls180.v:7105.1-7112.4" + process $proc$ls180.v:7105$2457 assign { } { } assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:7104.2-7108.9" + attribute \src "ls180.v:7107.2-7111.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -291660,24 +294169,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:7110.1-7117.4" - process $proc$ls180.v:7110$2458 + attribute \src "ls180.v:7113.1-7120.4" + process $proc$ls180.v:7113$2458 assign { } { } assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:7112.2-7116.9" + attribute \src "ls180.v:7115.2-7119.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7114$2471_Y + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7117$2471_Y end sync always update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:7118.1-7125.4" - process $proc$ls180.v:7118$2472 + attribute \src "ls180.v:7121.1-7128.4" + process $proc$ls180.v:7121$2472 assign { } { } assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7120.2-7124.9" + attribute \src "ls180.v:7123.2-7127.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -291686,11 +294195,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:7126.1-7133.4" - process $proc$ls180.v:7126$2473 + attribute \src "ls180.v:7129.1-7136.4" + process $proc$ls180.v:7129$2473 assign { } { } assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:7128.2-7132.9" + attribute \src "ls180.v:7131.2-7135.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -291699,24 +294208,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:7134.1-7141.4" - process $proc$ls180.v:7134$2474 + attribute \src "ls180.v:7137.1-7144.4" + process $proc$ls180.v:7137$2474 assign { } { } assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:7136.2-7140.9" + attribute \src "ls180.v:7139.2-7143.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7138$2487_Y + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7141$2487_Y end sync always update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:7142.1-7149.4" - process $proc$ls180.v:7142$2488 + attribute \src "ls180.v:7145.1-7152.4" + process $proc$ls180.v:7145$2488 assign { } { } assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7144.2-7148.9" + attribute \src "ls180.v:7147.2-7151.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -291725,11 +294234,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:7150.1-7157.4" - process $proc$ls180.v:7150$2489 + attribute \src "ls180.v:7153.1-7160.4" + process $proc$ls180.v:7153$2489 assign { } { } assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:7152.2-7156.9" + attribute \src "ls180.v:7155.2-7159.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -291738,24 +294247,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:7158.1-7165.4" - process $proc$ls180.v:7158$2490 + attribute \src "ls180.v:7161.1-7168.4" + process $proc$ls180.v:7161$2490 assign { } { } assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:7160.2-7164.9" + attribute \src "ls180.v:7163.2-7167.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7162$2503_Y + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7165$2503_Y end sync always update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:7166.1-7173.4" - process $proc$ls180.v:7166$2504 + attribute \src "ls180.v:7169.1-7176.4" + process $proc$ls180.v:7169$2504 assign { } { } assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7168.2-7172.9" + attribute \src "ls180.v:7171.2-7175.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -291764,11 +294273,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:7174.1-7181.4" - process $proc$ls180.v:7174$2505 + attribute \src "ls180.v:7177.1-7184.4" + process $proc$ls180.v:7177$2505 assign { } { } assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:7176.2-7180.9" + attribute \src "ls180.v:7179.2-7183.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -291777,24 +294286,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:7182.1-7189.4" - process $proc$ls180.v:7182$2506 + attribute \src "ls180.v:7185.1-7192.4" + process $proc$ls180.v:7185$2506 assign { } { } assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:7184.2-7188.9" + attribute \src "ls180.v:7187.2-7191.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7186$2519_Y + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7189$2519_Y end sync always update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:7190.1-7209.4" - process $proc$ls180.v:7190$2520 + attribute \src "ls180.v:7193.1-7212.4" + process $proc$ls180.v:7193$2520 assign { } { } assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:7192.2-7208.9" + attribute \src "ls180.v:7195.2-7211.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -291815,11 +294324,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:7210.1-7229.4" - process $proc$ls180.v:7210$2521 + attribute \src "ls180.v:7213.1-7232.4" + process $proc$ls180.v:7213$2521 assign { } { } assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "ls180.v:7212.2-7228.9" + attribute \src "ls180.v:7215.2-7231.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -291840,11 +294349,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:7230.1-7249.4" - process $proc$ls180.v:7230$2522 + attribute \src "ls180.v:7233.1-7252.4" + process $proc$ls180.v:7233$2522 assign { } { } assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 - attribute \src "ls180.v:7232.2-7248.9" + attribute \src "ls180.v:7235.2-7251.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -291865,19 +294374,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:724.5-724.59" - process $proc$ls180.v:724$3352 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:7250.1-7269.4" - process $proc$ls180.v:7250$2523 + attribute \src "ls180.v:7253.1-7272.4" + process $proc$ls180.v:7253$2523 assign { } { } assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:7252.2-7268.9" + attribute \src "ls180.v:7255.2-7271.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -291898,27 +294399,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:726.5-726.59" - process $proc$ls180.v:726$3353 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:727.5-727.58" - process $proc$ls180.v:727$3354 + attribute \src "ls180.v:727.5-727.59" + process $proc$ls180.v:727$3350 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:7270.1-7289.4" - process $proc$ls180.v:7270$2524 + attribute \src "ls180.v:7273.1-7292.4" + process $proc$ls180.v:7273$2524 assign { } { } assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7272.2-7288.9" + attribute \src "ls180.v:7275.2-7291.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -291939,27 +294432,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:728.5-728.64" - process $proc$ls180.v:728$3355 + attribute \src "ls180.v:729.5-729.59" + process $proc$ls180.v:729$3351 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:729.12-729.74" - process $proc$ls180.v:729$3356 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:7290.1-7309.4" - process $proc$ls180.v:7290$2525 + attribute \src "ls180.v:7293.1-7312.4" + process $proc$ls180.v:7293$2525 assign { } { } assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7292.2-7308.9" + attribute \src "ls180.v:7295.2-7311.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -291980,27 +294465,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:730.12-730.47" - process $proc$ls180.v:730$3357 + attribute \src "ls180.v:730.5-730.58" + process $proc$ls180.v:730$3352 assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:731.5-731.46" - process $proc$ls180.v:731$3358 + attribute \src "ls180.v:731.5-731.64" + process $proc$ls180.v:731$3353 assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:7310.1-7329.4" - process $proc$ls180.v:7310$2526 + attribute \src "ls180.v:7313.1-7332.4" + process $proc$ls180.v:7313$2526 assign { } { } assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7312.2-7328.9" + attribute \src "ls180.v:7315.2-7331.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -292021,19 +294506,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:733.5-733.44" - process $proc$ls180.v:733$3359 + attribute \src "ls180.v:732.12-732.74" + process $proc$ls180.v:732$3354 assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:7330.1-7349.4" - process $proc$ls180.v:7330$2527 + attribute \src "ls180.v:733.12-733.47" + process $proc$ls180.v:733$3355 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:7333.1-7352.4" + process $proc$ls180.v:7333$2527 assign { } { } assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7332.2-7348.9" + attribute \src "ls180.v:7335.2-7351.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -292054,27 +294547,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:734.5-734.45" - process $proc$ls180.v:734$3360 - assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] - end - attribute \src "ls180.v:735.5-735.54" - process $proc$ls180.v:735$3361 + attribute \src "ls180.v:734.5-734.46" + process $proc$ls180.v:734$3356 assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] end - attribute \src "ls180.v:7350.1-7366.4" - process $proc$ls180.v:7350$2528 + attribute \src "ls180.v:7353.1-7369.4" + process $proc$ls180.v:7353$2528 assign { } { } assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7352.2-7365.9" + attribute \src "ls180.v:7355.2-7368.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -292092,11 +294577,27 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:7367.1-7383.4" - process $proc$ls180.v:7367$2529 + attribute \src "ls180.v:736.5-736.44" + process $proc$ls180.v:736$3357 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:737.5-737.45" + process $proc$ls180.v:737$3358 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:7370.1-7386.4" + process $proc$ls180.v:7370$2529 assign { } { } assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7369.2-7382.9" + attribute \src "ls180.v:7372.2-7385.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -292114,40 +294615,32 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:737.32-737.76" - process $proc$ls180.v:737$3362 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - end - attribute \src "ls180.v:738.11-738.55" - process $proc$ls180.v:738$3363 + attribute \src "ls180.v:738.5-738.54" + process $proc$ls180.v:738$3359 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:7384.1-7400.4" - process $proc$ls180.v:7384$2530 + attribute \src "ls180.v:7387.1-7403.4" + process $proc$ls180.v:7387$2530 assign { } { } assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7386.2-7399.9" + attribute \src "ls180.v:7389.2-7402.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7391$2532_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7394$2532_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7394$2534_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7397$2534_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7397$2536_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7400$2536_Y end sync always update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] @@ -292160,115 +294653,131 @@ module \ls180 update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] sync init end - attribute \src "ls180.v:740.32-740.75" - process $proc$ls180.v:740$3364 + attribute \src "ls180.v:740.32-740.76" + process $proc$ls180.v:740$3360 assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] end - attribute \src "ls180.v:7401.1-7417.4" - process $proc$ls180.v:7401$2537 + attribute \src "ls180.v:7404.1-7420.4" + process $proc$ls180.v:7404$2537 assign { } { } assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7403.2-7416.9" + attribute \src "ls180.v:7406.2-7419.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7408$2539_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7411$2539_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7411$2541_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7414$2541_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7414$2543_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7417$2543_Y end sync always update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:7418.1-7434.4" - process $proc$ls180.v:7418$2544 + attribute \src "ls180.v:741.11-741.55" + process $proc$ls180.v:741$3361 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:7421.1-7437.4" + process $proc$ls180.v:7421$2544 assign { } { } assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7420.2-7433.9" + attribute \src "ls180.v:7423.2-7436.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7425$2546_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7428$2546_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7428$2548_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7431$2548_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7431$2550_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7434$2550_Y end sync always update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:742.32-742.76" - process $proc$ls180.v:742$3365 + attribute \src "ls180.v:743.32-743.75" + process $proc$ls180.v:743$3362 assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] sync init end - attribute \src "ls180.v:7435.1-7451.4" - process $proc$ls180.v:7435$2551 + attribute \src "ls180.v:7438.1-7454.4" + process $proc$ls180.v:7438$2551 assign { } { } assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7437.2-7450.9" + attribute \src "ls180.v:7440.2-7453.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7442$2553_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7445$2553_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7445$2555_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7448$2555_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7448$2557_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7451$2557_Y end sync always update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:7452.1-7468.4" - process $proc$ls180.v:7452$2558 + attribute \src "ls180.v:745.32-745.76" + process $proc$ls180.v:745$3363 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:7455.1-7471.4" + process $proc$ls180.v:7455$2558 assign { } { } assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7454.2-7467.9" + attribute \src "ls180.v:7457.2-7470.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7459$2560_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7462$2560_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7462$2562_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7465$2562_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7465$2564_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7468$2564_Y end sync always update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:7469.1-7497.4" - process $proc$ls180.v:7469$2565 + attribute \src "ls180.v:7472.1-7500.4" + process $proc$ls180.v:7472$2565 assign { } { } assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7471.2-7496.9" + attribute \src "ls180.v:7474.2-7499.9" switch \main_spimaster34_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -292298,27 +294807,19 @@ module \ls180 sync always update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:748.5-748.51" - process $proc$ls180.v:748$3366 - assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - end - attribute \src "ls180.v:749.5-749.51" - process $proc$ls180.v:749$3367 + attribute \src "ls180.v:75.11-75.52" + process $proc$ls180.v:75$3133 assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 sync always + update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end - attribute \src "ls180.v:7498.1-7526.4" - process $proc$ls180.v:7498$2566 + attribute \src "ls180.v:7501.1-7529.4" + process $proc$ls180.v:7501$2566 assign { } { } assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7500.2-7525.9" + attribute \src "ls180.v:7503.2-7528.9" switch \main_spisdcard_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -292348,72 +294849,56 @@ module \ls180 sync always update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:75.11-75.52" - process $proc$ls180.v:75$3133 + attribute \src "ls180.v:751.5-751.51" + process $proc$ls180.v:751$3364 assign { } { } - assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always - update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "ls180.v:751.5-751.47" - process $proc$ls180.v:751$3368 + attribute \src "ls180.v:752.5-752.51" + process $proc$ls180.v:752$3365 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:754.5-754.47" + process $proc$ls180.v:754$3366 assign { } { } assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] end - attribute \src "ls180.v:752.5-752.45" - process $proc$ls180.v:752$3369 + attribute \src "ls180.v:755.5-755.45" + process $proc$ls180.v:755$3367 assign { } { } assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] end - attribute \src "ls180.v:753.5-753.45" - process $proc$ls180.v:753$3370 + attribute \src "ls180.v:756.5-756.45" + process $proc$ls180.v:756$3368 assign { } { } assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:754.12-754.57" - process $proc$ls180.v:754$3371 + attribute \src "ls180.v:757.12-757.57" + process $proc$ls180.v:757$3369 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:756.5-756.51" - process $proc$ls180.v:756$3372 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:757.5-757.51" - process $proc$ls180.v:757$3373 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:758.5-758.50" - process $proc$ls180.v:758$3374 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - end - attribute \src "ls180.v:7584.1-7594.4" - process $proc$ls180.v:7584$2567 + attribute \src "ls180.v:7587.1-7597.4" + process $proc$ls180.v:7587$2567 assign { } { } assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 @@ -292427,16 +294912,16 @@ module \ls180 sync always update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] end - attribute \src "ls180.v:759.5-759.54" - process $proc$ls180.v:759$3375 + attribute \src "ls180.v:759.5-759.51" + process $proc$ls180.v:759$3370 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "ls180.v:7595.1-7605.4" - process $proc$ls180.v:7595$2568 + attribute \src "ls180.v:7598.1-7608.4" + process $proc$ls180.v:7598$2568 assign { } { } assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 @@ -292450,39 +294935,47 @@ module \ls180 sync always update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] end - attribute \src "ls180.v:760.5-760.55" - process $proc$ls180.v:760$3376 + attribute \src "ls180.v:760.5-760.51" + process $proc$ls180.v:760$3371 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] end - attribute \src "ls180.v:761.5-761.56" - process $proc$ls180.v:761$3377 + attribute \src "ls180.v:761.5-761.50" + process $proc$ls180.v:761$3372 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end - attribute \src "ls180.v:762.5-762.50" - process $proc$ls180.v:762$3378 + attribute \src "ls180.v:762.5-762.54" + process $proc$ls180.v:762$3373 assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:7626.1-7628.4" - process $proc$ls180.v:7626$2569 + attribute \src "ls180.v:7629.1-7631.4" + process $proc$ls180.v:7629$2569 assign { } { } assign $0\main_int_rst[0:0] \sys_rst sync posedge \por_clk update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "ls180.v:7630.1-7700.4" - process $proc$ls180.v:7630$2570 + attribute \src "ls180.v:763.5-763.55" + process $proc$ls180.v:763$3374 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:7633.1-7703.4" + process $proc$ls180.v:7633$2570 assign { } { } assign { } { } assign { } { } @@ -292558,7 +295051,7 @@ module \ls180 assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7687$2572_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7690$2572_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -292592,24 +295085,40 @@ module \ls180 update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:765.5-765.67" - process $proc$ls180.v:765$3379 + attribute \src "ls180.v:764.5-764.56" + process $proc$ls180.v:764$3375 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:765.5-765.50" + process $proc$ls180.v:765$3376 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:768.5-768.67" + process $proc$ls180.v:768$3377 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:766.5-766.66" - process $proc$ls180.v:766$3380 + attribute \src "ls180.v:769.5-769.66" + process $proc$ls180.v:769$3378 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:7702.1-10346.4" - process $proc$ls180.v:7702$2573 + attribute \src "ls180.v:7705.1-10349.4" + process $proc$ls180.v:7705$2573 assign $0\uart_tx[0:0] \uart_tx assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi @@ -293026,30 +295535,30 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7703$2574_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7704$2575_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7705$2576_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7706$2577_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7707$2578_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7708$2579_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7709$2580_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7710$2581_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7711$2582_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7712$2583_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7713$2584_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7714$2585_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7715$2586_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7716$2587_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7717$2588_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7718$2589_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7719$2590_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7720$2591_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7721$2592_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7722$2593_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7723$2594_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7724$2595_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7725$2596_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7726$2597_Y + assign $0\main_dummy[23:0] [0] $or$ls180.v:7706$2574_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7707$2575_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7708$2576_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7709$2577_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7710$2578_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7711$2579_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7712$2580_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7713$2581_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7714$2582_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7715$2583_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7716$2584_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7717$2585_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7718$2586_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7719$2587_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7720$2588_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7721$2589_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7722$2590_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7723$2591_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7724$2592_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7725$2593_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7726$2594_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7727$2595_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7728$2596_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7729$2597_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state @@ -293076,14 +295585,14 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8184$2706_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8185$2707_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8186$2708_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8187$2706_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8188$2707_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8189$2708_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8220$2726_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8221$2738_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8223$2726_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8224$2738_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 @@ -293093,11 +295602,11 @@ module \ls180 assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8379$2784_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8388$2787_Y + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8382$2784_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8391$2787_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8414$2789_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8423$2792_Y + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8417$2789_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8426$2792_Y assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 @@ -293208,182 +295717,182 @@ module \ls180 assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7727.2-7729.5" - switch $or$ls180.v:7727$2598_Y - attribute \src "ls180.v:7727.6-7727.69" + attribute \src "ls180.v:7730.2-7732.5" + switch $or$ls180.v:7730$2598_Y + attribute \src "ls180.v:7730.6-7730.69" case 1'1 assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r case end - attribute \src "ls180.v:7731.2-7733.5" + attribute \src "ls180.v:7734.2-7736.5" switch \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7731.6-7731.54" + attribute \src "ls180.v:7734.6-7734.54" case 1'1 assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value case end - attribute \src "ls180.v:7734.2-7737.5" + attribute \src "ls180.v:7737.2-7740.5" switch \main_converter0_reset - attribute \src "ls180.v:7734.6-7734.27" + attribute \src "ls180.v:7737.6-7737.27" case 1'1 assign $0\main_converter0_counter[0:0] 1'0 assign $0\builder_converter0_state[0:0] 1'0 case end - attribute \src "ls180.v:7738.2-7740.5" - switch $or$ls180.v:7738$2599_Y - attribute \src "ls180.v:7738.6-7738.69" + attribute \src "ls180.v:7741.2-7743.5" + switch $or$ls180.v:7741$2599_Y + attribute \src "ls180.v:7741.6-7741.69" case 1'1 assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r case end - attribute \src "ls180.v:7742.2-7744.5" + attribute \src "ls180.v:7745.2-7747.5" switch \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7742.6-7742.54" + attribute \src "ls180.v:7745.6-7745.54" case 1'1 assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value case end - attribute \src "ls180.v:7745.2-7748.5" + attribute \src "ls180.v:7748.2-7751.5" switch \main_converter1_reset - attribute \src "ls180.v:7745.6-7745.27" + attribute \src "ls180.v:7748.6-7748.27" case 1'1 assign $0\main_converter1_counter[0:0] 1'0 assign $0\builder_converter1_state[0:0] 1'0 case end - attribute \src "ls180.v:7749.2-7751.5" - switch $or$ls180.v:7749$2600_Y - attribute \src "ls180.v:7749.6-7749.51" + attribute \src "ls180.v:7752.2-7754.5" + switch $or$ls180.v:7752$2600_Y + attribute \src "ls180.v:7752.6-7752.51" case 1'1 assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r case end - attribute \src "ls180.v:7753.2-7755.5" + attribute \src "ls180.v:7756.2-7758.5" switch \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:7753.6-7753.57" + attribute \src "ls180.v:7756.6-7756.57" case 1'1 assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value case end - attribute \src "ls180.v:7756.2-7759.5" + attribute \src "ls180.v:7759.2-7762.5" switch \main_socbushandler_reset - attribute \src "ls180.v:7756.6-7756.30" + attribute \src "ls180.v:7759.6-7759.30" case 1'1 assign $0\main_socbushandler_counter[0:0] 1'0 assign $0\builder_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7760.2-7764.5" - switch $ne$ls180.v:7760$2601_Y - attribute \src "ls180.v:7760.6-7760.53" + attribute \src "ls180.v:7763.2-7767.5" + switch $ne$ls180.v:7763$2601_Y + attribute \src "ls180.v:7763.6-7763.53" case 1'1 - attribute \src "ls180.v:7761.3-7763.6" + attribute \src "ls180.v:7764.3-7766.6" switch \main_libresocsim_bus_error - attribute \src "ls180.v:7761.7-7761.33" + attribute \src "ls180.v:7764.7-7764.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7762$2602_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7765$2602_Y case end case end - attribute \src "ls180.v:7766.2-7768.5" - switch $and$ls180.v:7766$2605_Y - attribute \src "ls180.v:7766.6-7766.103" + attribute \src "ls180.v:7769.2-7771.5" + switch $and$ls180.v:7769$2605_Y + attribute \src "ls180.v:7769.6-7769.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7769.2-7777.5" + attribute \src "ls180.v:7772.2-7780.5" switch \main_libresocsim_en_storage - attribute \src "ls180.v:7769.6-7769.33" + attribute \src "ls180.v:7772.6-7772.33" case 1'1 - attribute \src "ls180.v:7770.3-7774.6" - switch $eq$ls180.v:7770$2606_Y - attribute \src "ls180.v:7770.7-7770.39" + attribute \src "ls180.v:7773.3-7777.6" + switch $eq$ls180.v:7773$2606_Y + attribute \src "ls180.v:7773.7-7773.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7772.7-7772.11" + attribute \src "ls180.v:7775.7-7775.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7773$2607_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7776$2607_Y end - attribute \src "ls180.v:7775.6-7775.10" + attribute \src "ls180.v:7778.6-7778.10" case assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage end - attribute \src "ls180.v:7778.2-7780.5" + attribute \src "ls180.v:7781.2-7783.5" switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7778.6-7778.38" + attribute \src "ls180.v:7781.6-7781.38" case 1'1 assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value case end - attribute \src "ls180.v:7781.2-7783.5" + attribute \src "ls180.v:7784.2-7786.5" switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7781.6-7781.33" + attribute \src "ls180.v:7784.6-7784.33" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7785.2-7787.5" - switch $and$ls180.v:7785$2609_Y - attribute \src "ls180.v:7785.6-7785.76" + attribute \src "ls180.v:7788.2-7790.5" + switch $and$ls180.v:7788$2609_Y + attribute \src "ls180.v:7788.6-7788.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7789.2-7791.5" - switch $and$ls180.v:7789$2612_Y - attribute \src "ls180.v:7789.6-7789.100" + attribute \src "ls180.v:7792.2-7794.5" + switch $and$ls180.v:7792$2612_Y + attribute \src "ls180.v:7792.6-7792.100" case 1'1 assign $0\main_interface0_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7793.2-7795.5" - switch $and$ls180.v:7793$2615_Y - attribute \src "ls180.v:7793.6-7793.100" + attribute \src "ls180.v:7796.2-7798.5" + switch $and$ls180.v:7796$2615_Y + attribute \src "ls180.v:7796.6-7796.100" case 1'1 assign $0\main_interface1_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7797.2-7799.5" - switch $and$ls180.v:7797$2618_Y - attribute \src "ls180.v:7797.6-7797.100" + attribute \src "ls180.v:7800.2-7802.5" + switch $and$ls180.v:7800$2618_Y + attribute \src "ls180.v:7800.6-7800.100" case 1'1 assign $0\main_interface2_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7801.2-7803.5" - switch $and$ls180.v:7801$2621_Y - attribute \src "ls180.v:7801.6-7801.100" + attribute \src "ls180.v:7804.2-7806.5" + switch $and$ls180.v:7804$2621_Y + attribute \src "ls180.v:7804.6-7804.100" case 1'1 assign $0\main_interface3_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7806.2-7808.5" + attribute \src "ls180.v:7809.2-7811.5" switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7806.6-7806.37" + attribute \src "ls180.v:7809.6-7809.37" case 1'1 assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata case end - attribute \src "ls180.v:7809.2-7813.5" - switch $and$ls180.v:7809$2623_Y - attribute \src "ls180.v:7809.6-7809.57" + attribute \src "ls180.v:7812.2-7816.5" + switch $and$ls180.v:7812$2623_Y + attribute \src "ls180.v:7812.6-7812.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7810$2624_Y - attribute \src "ls180.v:7811.6-7811.10" + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7813$2624_Y + attribute \src "ls180.v:7814.6-7814.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7815.2-7821.5" + attribute \src "ls180.v:7818.2-7824.5" switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7815.6-7815.32" + attribute \src "ls180.v:7818.6-7818.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7816$2625_Y - attribute \src "ls180.v:7817.3-7820.6" - switch $eq$ls180.v:7817$2626_Y - attribute \src "ls180.v:7817.7-7817.43" + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7819$2625_Y + attribute \src "ls180.v:7820.3-7823.6" + switch $eq$ls180.v:7820$2626_Y + attribute \src "ls180.v:7820.7-7820.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 assign $0\main_sdram_postponer_req_o[0:0] 1'1 @@ -293391,30 +295900,30 @@ module \ls180 end case end - attribute \src "ls180.v:7822.2-7830.5" + attribute \src "ls180.v:7825.2-7833.5" switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7822.6-7822.33" + attribute \src "ls180.v:7825.6-7825.33" case 1'1 assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7824.6-7824.10" + attribute \src "ls180.v:7827.6-7827.10" case - attribute \src "ls180.v:7825.3-7829.6" + attribute \src "ls180.v:7828.3-7832.6" switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7825.7-7825.33" + attribute \src "ls180.v:7828.7-7828.33" case 1'1 - attribute \src "ls180.v:7826.4-7828.7" - switch $ne$ls180.v:7826$2627_Y - attribute \src "ls180.v:7826.8-7826.44" + attribute \src "ls180.v:7829.4-7831.7" + switch $ne$ls180.v:7829$2627_Y + attribute \src "ls180.v:7829.8-7829.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7827$2628_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7830$2628_Y case end case end end - attribute \src "ls180.v:7837.2-7843.5" - switch $and$ls180.v:7837$2630_Y - attribute \src "ls180.v:7837.6-7837.76" + attribute \src "ls180.v:7840.2-7846.5" + switch $and$ls180.v:7840$2630_Y + attribute \src "ls180.v:7840.6-7840.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -293423,9 +295932,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7844.2-7850.5" - switch $eq$ls180.v:7844$2631_Y - attribute \src "ls180.v:7844.6-7844.44" + attribute \src "ls180.v:7847.2-7853.5" + switch $eq$ls180.v:7847$2631_Y + attribute \src "ls180.v:7847.6-7847.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -293434,9 +295943,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7851.2-7858.5" - switch $eq$ls180.v:7851$2632_Y - attribute \src "ls180.v:7851.6-7851.44" + attribute \src "ls180.v:7854.2-7861.5" + switch $eq$ls180.v:7854$2632_Y + attribute \src "ls180.v:7854.6-7854.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -293446,83 +295955,83 @@ module \ls180 assign $0\main_sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7859.2-7869.5" - switch $eq$ls180.v:7859$2633_Y - attribute \src "ls180.v:7859.6-7859.44" + attribute \src "ls180.v:7862.2-7872.5" + switch $eq$ls180.v:7862$2633_Y + attribute \src "ls180.v:7862.6-7862.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7861.6-7861.10" + attribute \src "ls180.v:7864.6-7864.10" case - attribute \src "ls180.v:7862.3-7868.6" - switch $ne$ls180.v:7862$2634_Y - attribute \src "ls180.v:7862.7-7862.45" + attribute \src "ls180.v:7865.3-7871.6" + switch $ne$ls180.v:7865$2634_Y + attribute \src "ls180.v:7865.7-7865.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7863$2635_Y - attribute \src "ls180.v:7864.7-7864.11" + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7866$2635_Y + attribute \src "ls180.v:7867.7-7867.11" case - attribute \src "ls180.v:7865.4-7867.7" + attribute \src "ls180.v:7868.4-7870.7" switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7865.8-7865.35" + attribute \src "ls180.v:7868.8-7868.35" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7871.2-7878.5" + attribute \src "ls180.v:7874.2-7881.5" switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7871.6-7871.39" + attribute \src "ls180.v:7874.6-7874.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7873.6-7873.10" + attribute \src "ls180.v:7876.6-7876.10" case - attribute \src "ls180.v:7874.3-7877.6" + attribute \src "ls180.v:7877.3-7880.6" switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7874.7-7874.39" + attribute \src "ls180.v:7877.7-7877.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7879.2-7881.5" - switch $and$ls180.v:7879$2638_Y - attribute \src "ls180.v:7879.6-7879.191" + attribute \src "ls180.v:7882.2-7884.5" + switch $and$ls180.v:7882$2638_Y + attribute \src "ls180.v:7882.6-7882.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7880$2639_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7883$2639_Y case end - attribute \src "ls180.v:7882.2-7884.5" + attribute \src "ls180.v:7885.2-7887.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7882.6-7882.58" + attribute \src "ls180.v:7885.6-7885.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7883$2640_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7886$2640_Y case end - attribute \src "ls180.v:7885.2-7893.5" - switch $and$ls180.v:7885$2643_Y - attribute \src "ls180.v:7885.6-7885.191" + attribute \src "ls180.v:7888.2-7896.5" + switch $and$ls180.v:7888$2643_Y + attribute \src "ls180.v:7888.6-7888.191" case 1'1 - attribute \src "ls180.v:7886.3-7888.6" - switch $not$ls180.v:7886$2644_Y - attribute \src "ls180.v:7886.7-7886.62" + attribute \src "ls180.v:7889.3-7891.6" + switch $not$ls180.v:7889$2644_Y + attribute \src "ls180.v:7889.7-7889.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7887$2645_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7890$2645_Y case end - attribute \src "ls180.v:7889.6-7889.10" + attribute \src "ls180.v:7892.6-7892.10" case - attribute \src "ls180.v:7890.3-7892.6" + attribute \src "ls180.v:7893.3-7895.6" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7890.7-7890.59" + attribute \src "ls180.v:7893.7-7893.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7891$2646_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7894$2646_Y case end end - attribute \src "ls180.v:7894.2-7900.5" - switch $or$ls180.v:7894$2648_Y - attribute \src "ls180.v:7894.6-7894.108" + attribute \src "ls180.v:7897.2-7903.5" + switch $or$ls180.v:7897$2648_Y + attribute \src "ls180.v:7897.6-7897.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first @@ -293531,27 +296040,27 @@ module \ls180 assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7901.2-7915.5" + attribute \src "ls180.v:7904.2-7918.5" switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7901.6-7901.43" + attribute \src "ls180.v:7904.6-7904.43" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7903.3-7907.6" + attribute \src "ls180.v:7906.3-7910.6" switch 1'0 - attribute \src "ls180.v:7905.7-7905.11" + attribute \src "ls180.v:7908.7-7908.11" case assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7908.6-7908.10" + attribute \src "ls180.v:7911.6-7911.10" case - attribute \src "ls180.v:7909.3-7914.6" - switch $not$ls180.v:7909$2649_Y - attribute \src "ls180.v:7909.7-7909.47" + attribute \src "ls180.v:7912.3-7917.6" + switch $not$ls180.v:7912$2649_Y + attribute \src "ls180.v:7912.7-7912.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7910$2650_Y - attribute \src "ls180.v:7911.4-7913.7" - switch $eq$ls180.v:7911$2651_Y - attribute \src "ls180.v:7911.8-7911.55" + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7913$2650_Y + attribute \src "ls180.v:7914.4-7916.7" + switch $eq$ls180.v:7914$2651_Y + attribute \src "ls180.v:7914.8-7914.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case @@ -293559,60 +296068,60 @@ module \ls180 case end end - attribute \src "ls180.v:7917.2-7924.5" + attribute \src "ls180.v:7920.2-7927.5" switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7917.6-7917.39" + attribute \src "ls180.v:7920.6-7920.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7919.6-7919.10" + attribute \src "ls180.v:7922.6-7922.10" case - attribute \src "ls180.v:7920.3-7923.6" + attribute \src "ls180.v:7923.3-7926.6" switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7920.7-7920.39" + attribute \src "ls180.v:7923.7-7923.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7925.2-7927.5" - switch $and$ls180.v:7925$2654_Y - attribute \src "ls180.v:7925.6-7925.191" + attribute \src "ls180.v:7928.2-7930.5" + switch $and$ls180.v:7928$2654_Y + attribute \src "ls180.v:7928.6-7928.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7926$2655_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7929$2655_Y case end - attribute \src "ls180.v:7928.2-7930.5" + attribute \src "ls180.v:7931.2-7933.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7928.6-7928.58" + attribute \src "ls180.v:7931.6-7931.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7929$2656_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7932$2656_Y case end - attribute \src "ls180.v:7931.2-7939.5" - switch $and$ls180.v:7931$2659_Y - attribute \src "ls180.v:7931.6-7931.191" + attribute \src "ls180.v:7934.2-7942.5" + switch $and$ls180.v:7934$2659_Y + attribute \src "ls180.v:7934.6-7934.191" case 1'1 - attribute \src "ls180.v:7932.3-7934.6" - switch $not$ls180.v:7932$2660_Y - attribute \src "ls180.v:7932.7-7932.62" + attribute \src "ls180.v:7935.3-7937.6" + switch $not$ls180.v:7935$2660_Y + attribute \src "ls180.v:7935.7-7935.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7933$2661_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7936$2661_Y case end - attribute \src "ls180.v:7935.6-7935.10" + attribute \src "ls180.v:7938.6-7938.10" case - attribute \src "ls180.v:7936.3-7938.6" + attribute \src "ls180.v:7939.3-7941.6" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7936.7-7936.59" + attribute \src "ls180.v:7939.7-7939.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7937$2662_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7940$2662_Y case end end - attribute \src "ls180.v:7940.2-7946.5" - switch $or$ls180.v:7940$2664_Y - attribute \src "ls180.v:7940.6-7940.108" + attribute \src "ls180.v:7943.2-7949.5" + switch $or$ls180.v:7943$2664_Y + attribute \src "ls180.v:7943.6-7943.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first @@ -293621,27 +296130,27 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7947.2-7961.5" + attribute \src "ls180.v:7950.2-7964.5" switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7947.6-7947.43" + attribute \src "ls180.v:7950.6-7950.43" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7949.3-7953.6" + attribute \src "ls180.v:7952.3-7956.6" switch 1'0 - attribute \src "ls180.v:7951.7-7951.11" + attribute \src "ls180.v:7954.7-7954.11" case assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7954.6-7954.10" + attribute \src "ls180.v:7957.6-7957.10" case - attribute \src "ls180.v:7955.3-7960.6" - switch $not$ls180.v:7955$2665_Y - attribute \src "ls180.v:7955.7-7955.47" + attribute \src "ls180.v:7958.3-7963.6" + switch $not$ls180.v:7958$2665_Y + attribute \src "ls180.v:7958.7-7958.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7956$2666_Y - attribute \src "ls180.v:7957.4-7959.7" - switch $eq$ls180.v:7957$2667_Y - attribute \src "ls180.v:7957.8-7957.55" + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7959$2666_Y + attribute \src "ls180.v:7960.4-7962.7" + switch $eq$ls180.v:7960$2667_Y + attribute \src "ls180.v:7960.8-7960.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case @@ -293649,60 +296158,60 @@ module \ls180 case end end - attribute \src "ls180.v:7963.2-7970.5" + attribute \src "ls180.v:7966.2-7973.5" switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7963.6-7963.39" + attribute \src "ls180.v:7966.6-7966.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7965.6-7965.10" + attribute \src "ls180.v:7968.6-7968.10" case - attribute \src "ls180.v:7966.3-7969.6" + attribute \src "ls180.v:7969.3-7972.6" switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7966.7-7966.39" + attribute \src "ls180.v:7969.7-7969.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7971.2-7973.5" - switch $and$ls180.v:7971$2670_Y - attribute \src "ls180.v:7971.6-7971.191" + attribute \src "ls180.v:7974.2-7976.5" + switch $and$ls180.v:7974$2670_Y + attribute \src "ls180.v:7974.6-7974.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7972$2671_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7975$2671_Y case end - attribute \src "ls180.v:7974.2-7976.5" + attribute \src "ls180.v:7977.2-7979.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7974.6-7974.58" + attribute \src "ls180.v:7977.6-7977.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7975$2672_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7978$2672_Y case end - attribute \src "ls180.v:7977.2-7985.5" - switch $and$ls180.v:7977$2675_Y - attribute \src "ls180.v:7977.6-7977.191" + attribute \src "ls180.v:7980.2-7988.5" + switch $and$ls180.v:7980$2675_Y + attribute \src "ls180.v:7980.6-7980.191" case 1'1 - attribute \src "ls180.v:7978.3-7980.6" - switch $not$ls180.v:7978$2676_Y - attribute \src "ls180.v:7978.7-7978.62" + attribute \src "ls180.v:7981.3-7983.6" + switch $not$ls180.v:7981$2676_Y + attribute \src "ls180.v:7981.7-7981.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7979$2677_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7982$2677_Y case end - attribute \src "ls180.v:7981.6-7981.10" + attribute \src "ls180.v:7984.6-7984.10" case - attribute \src "ls180.v:7982.3-7984.6" + attribute \src "ls180.v:7985.3-7987.6" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7982.7-7982.59" + attribute \src "ls180.v:7985.7-7985.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7983$2678_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7986$2678_Y case end end - attribute \src "ls180.v:7986.2-7992.5" - switch $or$ls180.v:7986$2680_Y - attribute \src "ls180.v:7986.6-7986.108" + attribute \src "ls180.v:7989.2-7995.5" + switch $or$ls180.v:7989$2680_Y + attribute \src "ls180.v:7989.6-7989.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first @@ -293711,27 +296220,27 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7993.2-8007.5" + attribute \src "ls180.v:7996.2-8010.5" switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7993.6-7993.43" + attribute \src "ls180.v:7996.6-7996.43" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7995.3-7999.6" + attribute \src "ls180.v:7998.3-8002.6" switch 1'0 - attribute \src "ls180.v:7997.7-7997.11" + attribute \src "ls180.v:8000.7-8000.11" case assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8000.6-8000.10" + attribute \src "ls180.v:8003.6-8003.10" case - attribute \src "ls180.v:8001.3-8006.6" - switch $not$ls180.v:8001$2681_Y - attribute \src "ls180.v:8001.7-8001.47" + attribute \src "ls180.v:8004.3-8009.6" + switch $not$ls180.v:8004$2681_Y + attribute \src "ls180.v:8004.7-8004.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8002$2682_Y - attribute \src "ls180.v:8003.4-8005.7" - switch $eq$ls180.v:8003$2683_Y - attribute \src "ls180.v:8003.8-8003.55" + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8005$2682_Y + attribute \src "ls180.v:8006.4-8008.7" + switch $eq$ls180.v:8006$2683_Y + attribute \src "ls180.v:8006.8-8006.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case @@ -293739,60 +296248,60 @@ module \ls180 case end end - attribute \src "ls180.v:8009.2-8016.5" + attribute \src "ls180.v:8012.2-8019.5" switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:8009.6-8009.39" + attribute \src "ls180.v:8012.6-8012.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:8011.6-8011.10" + attribute \src "ls180.v:8014.6-8014.10" case - attribute \src "ls180.v:8012.3-8015.6" + attribute \src "ls180.v:8015.3-8018.6" switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:8012.7-8012.39" + attribute \src "ls180.v:8015.7-8015.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:8017.2-8019.5" - switch $and$ls180.v:8017$2686_Y - attribute \src "ls180.v:8017.6-8017.191" + attribute \src "ls180.v:8020.2-8022.5" + switch $and$ls180.v:8020$2686_Y + attribute \src "ls180.v:8020.6-8020.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8018$2687_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8021$2687_Y case end - attribute \src "ls180.v:8020.2-8022.5" + attribute \src "ls180.v:8023.2-8025.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:8020.6-8020.58" + attribute \src "ls180.v:8023.6-8023.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8021$2688_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8024$2688_Y case end - attribute \src "ls180.v:8023.2-8031.5" - switch $and$ls180.v:8023$2691_Y - attribute \src "ls180.v:8023.6-8023.191" + attribute \src "ls180.v:8026.2-8034.5" + switch $and$ls180.v:8026$2691_Y + attribute \src "ls180.v:8026.6-8026.191" case 1'1 - attribute \src "ls180.v:8024.3-8026.6" - switch $not$ls180.v:8024$2692_Y - attribute \src "ls180.v:8024.7-8024.62" + attribute \src "ls180.v:8027.3-8029.6" + switch $not$ls180.v:8027$2692_Y + attribute \src "ls180.v:8027.7-8027.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8025$2693_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8028$2693_Y case end - attribute \src "ls180.v:8027.6-8027.10" + attribute \src "ls180.v:8030.6-8030.10" case - attribute \src "ls180.v:8028.3-8030.6" + attribute \src "ls180.v:8031.3-8033.6" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:8028.7-8028.59" + attribute \src "ls180.v:8031.7-8031.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8029$2694_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8032$2694_Y case end end - attribute \src "ls180.v:8032.2-8038.5" - switch $or$ls180.v:8032$2696_Y - attribute \src "ls180.v:8032.6-8032.108" + attribute \src "ls180.v:8035.2-8041.5" + switch $or$ls180.v:8035$2696_Y + attribute \src "ls180.v:8035.6-8035.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first @@ -293801,27 +296310,27 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:8039.2-8053.5" + attribute \src "ls180.v:8042.2-8056.5" switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:8039.6-8039.43" + attribute \src "ls180.v:8042.6-8042.43" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:8041.3-8045.6" + attribute \src "ls180.v:8044.3-8048.6" switch 1'0 - attribute \src "ls180.v:8043.7-8043.11" + attribute \src "ls180.v:8046.7-8046.11" case assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8046.6-8046.10" + attribute \src "ls180.v:8049.6-8049.10" case - attribute \src "ls180.v:8047.3-8052.6" - switch $not$ls180.v:8047$2697_Y - attribute \src "ls180.v:8047.7-8047.47" + attribute \src "ls180.v:8050.3-8055.6" + switch $not$ls180.v:8050$2697_Y + attribute \src "ls180.v:8050.7-8050.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8048$2698_Y - attribute \src "ls180.v:8049.4-8051.7" - switch $eq$ls180.v:8049$2699_Y - attribute \src "ls180.v:8049.8-8049.55" + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8051$2698_Y + attribute \src "ls180.v:8052.4-8054.7" + switch $eq$ls180.v:8052$2699_Y + attribute \src "ls180.v:8052.8-8052.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case @@ -293829,61 +296338,61 @@ module \ls180 case end end - attribute \src "ls180.v:8055.2-8061.5" - switch $not$ls180.v:8055$2700_Y - attribute \src "ls180.v:8055.6-8055.23" + attribute \src "ls180.v:8058.2-8064.5" + switch $not$ls180.v:8058$2700_Y + attribute \src "ls180.v:8058.6-8058.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:8057.6-8057.10" + attribute \src "ls180.v:8060.6-8060.10" case - attribute \src "ls180.v:8058.3-8060.6" - switch $not$ls180.v:8058$2701_Y - attribute \src "ls180.v:8058.7-8058.30" + attribute \src "ls180.v:8061.3-8063.6" + switch $not$ls180.v:8061$2701_Y + attribute \src "ls180.v:8061.7-8061.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:8059$2702_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:8062$2702_Y case end end - attribute \src "ls180.v:8062.2-8068.5" - switch $not$ls180.v:8062$2703_Y - attribute \src "ls180.v:8062.6-8062.23" + attribute \src "ls180.v:8065.2-8071.5" + switch $not$ls180.v:8065$2703_Y + attribute \src "ls180.v:8065.6-8065.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:8064.6-8064.10" + attribute \src "ls180.v:8067.6-8067.10" case - attribute \src "ls180.v:8065.3-8067.6" - switch $not$ls180.v:8065$2704_Y - attribute \src "ls180.v:8065.7-8065.30" + attribute \src "ls180.v:8068.3-8070.6" + switch $not$ls180.v:8068$2704_Y + attribute \src "ls180.v:8068.7-8068.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:8066$2705_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:8069$2705_Y case end end - attribute \src "ls180.v:8069.2-8124.5" + attribute \src "ls180.v:8072.2-8127.5" switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:8069.6-8069.30" + attribute \src "ls180.v:8072.6-8072.30" case 1'1 - attribute \src "ls180.v:8070.3-8123.10" + attribute \src "ls180.v:8073.3-8126.10" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:8072.5-8082.8" + attribute \src "ls180.v:8075.5-8085.8" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8072.9-8072.41" + attribute \src "ls180.v:8075.9-8075.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:8074.9-8074.13" + attribute \src "ls180.v:8077.9-8077.13" case - attribute \src "ls180.v:8075.6-8081.9" + attribute \src "ls180.v:8078.6-8084.9" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8075.10-8075.42" + attribute \src "ls180.v:8078.10-8078.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:8077.10-8077.14" + attribute \src "ls180.v:8080.10-8080.14" case - attribute \src "ls180.v:8078.7-8080.10" + attribute \src "ls180.v:8081.7-8083.10" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8078.11-8078.43" + attribute \src "ls180.v:8081.11-8081.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 case @@ -293892,23 +296401,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:8085.5-8095.8" + attribute \src "ls180.v:8088.5-8098.8" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8085.9-8085.41" + attribute \src "ls180.v:8088.9-8088.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:8087.9-8087.13" + attribute \src "ls180.v:8090.9-8090.13" case - attribute \src "ls180.v:8088.6-8094.9" + attribute \src "ls180.v:8091.6-8097.9" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8088.10-8088.42" + attribute \src "ls180.v:8091.10-8091.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:8090.10-8090.14" + attribute \src "ls180.v:8093.10-8093.14" case - attribute \src "ls180.v:8091.7-8093.10" + attribute \src "ls180.v:8094.7-8096.10" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8091.11-8091.43" + attribute \src "ls180.v:8094.11-8094.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 case @@ -293917,23 +296426,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:8098.5-8108.8" + attribute \src "ls180.v:8101.5-8111.8" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8098.9-8098.41" + attribute \src "ls180.v:8101.9-8101.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:8100.9-8100.13" + attribute \src "ls180.v:8103.9-8103.13" case - attribute \src "ls180.v:8101.6-8107.9" + attribute \src "ls180.v:8104.6-8110.9" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8101.10-8101.42" + attribute \src "ls180.v:8104.10-8104.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:8103.10-8103.14" + attribute \src "ls180.v:8106.10-8106.14" case - attribute \src "ls180.v:8104.7-8106.10" + attribute \src "ls180.v:8107.7-8109.10" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8104.11-8104.43" + attribute \src "ls180.v:8107.11-8107.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 case @@ -293942,23 +296451,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:8111.5-8121.8" + attribute \src "ls180.v:8114.5-8124.8" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8111.9-8111.41" + attribute \src "ls180.v:8114.9-8114.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:8113.9-8113.13" + attribute \src "ls180.v:8116.9-8116.13" case - attribute \src "ls180.v:8114.6-8120.9" + attribute \src "ls180.v:8117.6-8123.9" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8114.10-8114.42" + attribute \src "ls180.v:8117.10-8117.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:8116.10-8116.14" + attribute \src "ls180.v:8119.10-8119.14" case - attribute \src "ls180.v:8117.7-8119.10" + attribute \src "ls180.v:8120.7-8122.10" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8117.11-8117.43" + attribute \src "ls180.v:8120.11-8120.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 case @@ -293969,31 +296478,31 @@ module \ls180 end case end - attribute \src "ls180.v:8125.2-8180.5" + attribute \src "ls180.v:8128.2-8183.5" switch \main_sdram_choose_req_ce - attribute \src "ls180.v:8125.6-8125.30" + attribute \src "ls180.v:8128.6-8128.30" case 1'1 - attribute \src "ls180.v:8126.3-8179.10" + attribute \src "ls180.v:8129.3-8182.10" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:8128.5-8138.8" + attribute \src "ls180.v:8131.5-8141.8" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8128.9-8128.41" + attribute \src "ls180.v:8131.9-8131.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:8130.9-8130.13" + attribute \src "ls180.v:8133.9-8133.13" case - attribute \src "ls180.v:8131.6-8137.9" + attribute \src "ls180.v:8134.6-8140.9" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8131.10-8131.42" + attribute \src "ls180.v:8134.10-8134.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:8133.10-8133.14" + attribute \src "ls180.v:8136.10-8136.14" case - attribute \src "ls180.v:8134.7-8136.10" + attribute \src "ls180.v:8137.7-8139.10" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8134.11-8134.43" + attribute \src "ls180.v:8137.11-8137.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 case @@ -294002,23 +296511,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:8141.5-8151.8" + attribute \src "ls180.v:8144.5-8154.8" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8141.9-8141.41" + attribute \src "ls180.v:8144.9-8144.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:8143.9-8143.13" + attribute \src "ls180.v:8146.9-8146.13" case - attribute \src "ls180.v:8144.6-8150.9" + attribute \src "ls180.v:8147.6-8153.9" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8144.10-8144.42" + attribute \src "ls180.v:8147.10-8147.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:8146.10-8146.14" + attribute \src "ls180.v:8149.10-8149.14" case - attribute \src "ls180.v:8147.7-8149.10" + attribute \src "ls180.v:8150.7-8152.10" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8147.11-8147.43" + attribute \src "ls180.v:8150.11-8150.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 case @@ -294027,23 +296536,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:8154.5-8164.8" + attribute \src "ls180.v:8157.5-8167.8" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8154.9-8154.41" + attribute \src "ls180.v:8157.9-8157.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:8156.9-8156.13" + attribute \src "ls180.v:8159.9-8159.13" case - attribute \src "ls180.v:8157.6-8163.9" + attribute \src "ls180.v:8160.6-8166.9" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8157.10-8157.42" + attribute \src "ls180.v:8160.10-8160.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:8159.10-8159.14" + attribute \src "ls180.v:8162.10-8162.14" case - attribute \src "ls180.v:8160.7-8162.10" + attribute \src "ls180.v:8163.7-8165.10" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8160.11-8160.43" + attribute \src "ls180.v:8163.11-8163.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 case @@ -294052,23 +296561,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:8167.5-8177.8" + attribute \src "ls180.v:8170.5-8180.8" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8167.9-8167.41" + attribute \src "ls180.v:8170.9-8170.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:8169.9-8169.13" + attribute \src "ls180.v:8172.9-8172.13" case - attribute \src "ls180.v:8170.6-8176.9" + attribute \src "ls180.v:8173.6-8179.9" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8170.10-8170.42" + attribute \src "ls180.v:8173.10-8173.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:8172.10-8172.14" + attribute \src "ls180.v:8175.10-8175.14" case - attribute \src "ls180.v:8173.7-8175.10" + attribute \src "ls180.v:8176.7-8178.10" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8173.11-8173.43" + attribute \src "ls180.v:8176.11-8176.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 case @@ -294079,28 +296588,28 @@ module \ls180 end case end - attribute \src "ls180.v:8189.2-8203.5" + attribute \src "ls180.v:8192.2-8206.5" switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:8189.6-8189.30" + attribute \src "ls180.v:8192.6-8192.30" case 1'1 assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:8191.3-8195.6" + attribute \src "ls180.v:8194.3-8198.6" switch 1'1 - attribute \src "ls180.v:8191.7-8191.11" + attribute \src "ls180.v:8194.7-8194.11" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:8196.6-8196.10" + attribute \src "ls180.v:8199.6-8199.10" case - attribute \src "ls180.v:8197.3-8202.6" - switch $not$ls180.v:8197$2709_Y - attribute \src "ls180.v:8197.7-8197.34" + attribute \src "ls180.v:8200.3-8205.6" + switch $not$ls180.v:8200$2709_Y + attribute \src "ls180.v:8200.7-8200.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8198$2710_Y - attribute \src "ls180.v:8199.4-8201.7" - switch $eq$ls180.v:8199$2711_Y - attribute \src "ls180.v:8199.8-8199.42" + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8201$2710_Y + attribute \src "ls180.v:8202.4-8204.7" + switch $eq$ls180.v:8202$2711_Y + attribute \src "ls180.v:8202.8-8202.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case @@ -294108,27 +296617,27 @@ module \ls180 case end end - attribute \src "ls180.v:8204.2-8218.5" + attribute \src "ls180.v:8207.2-8221.5" switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:8204.6-8204.30" + attribute \src "ls180.v:8207.6-8207.30" case 1'1 assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:8206.3-8210.6" + attribute \src "ls180.v:8209.3-8213.6" switch 1'0 - attribute \src "ls180.v:8208.7-8208.11" + attribute \src "ls180.v:8211.7-8211.11" case assign $0\main_sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8211.6-8211.10" + attribute \src "ls180.v:8214.6-8214.10" case - attribute \src "ls180.v:8212.3-8217.6" - switch $not$ls180.v:8212$2712_Y - attribute \src "ls180.v:8212.7-8212.34" + attribute \src "ls180.v:8215.3-8220.6" + switch $not$ls180.v:8215$2712_Y + attribute \src "ls180.v:8215.7-8215.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8213$2713_Y - attribute \src "ls180.v:8214.4-8216.7" - switch $eq$ls180.v:8214$2714_Y - attribute \src "ls180.v:8214.8-8214.42" + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8216$2713_Y + attribute \src "ls180.v:8217.4-8219.7" + switch $eq$ls180.v:8217$2714_Y + attribute \src "ls180.v:8217.8-8217.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 case @@ -294136,81 +296645,81 @@ module \ls180 case end end - attribute \src "ls180.v:8225.2-8227.5" - switch $or$ls180.v:8225$2739_Y - attribute \src "ls180.v:8225.6-8225.50" + attribute \src "ls180.v:8228.2-8230.5" + switch $or$ls180.v:8228$2739_Y + attribute \src "ls180.v:8228.6-8228.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r case end - attribute \src "ls180.v:8229.2-8231.5" + attribute \src "ls180.v:8232.2-8234.5" switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:8229.6-8229.52" + attribute \src "ls180.v:8232.6-8232.52" case 1'1 assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value case end - attribute \src "ls180.v:8232.2-8235.5" + attribute \src "ls180.v:8235.2-8238.5" switch \main_converter_reset - attribute \src "ls180.v:8232.6-8232.26" + attribute \src "ls180.v:8235.6-8235.26" case 1'1 assign $0\main_converter_counter[0:0] 1'0 assign $0\builder_converter_state[0:0] 1'0 case end - attribute \src "ls180.v:8236.2-8246.5" + attribute \src "ls180.v:8239.2-8249.5" switch \main_litedram_wb_ack - attribute \src "ls180.v:8236.6-8236.26" + attribute \src "ls180.v:8239.6-8239.26" case 1'1 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:8239.6-8239.10" + attribute \src "ls180.v:8242.6-8242.10" case - attribute \src "ls180.v:8240.3-8242.6" - switch $and$ls180.v:8240$2740_Y - attribute \src "ls180.v:8240.7-8240.50" + attribute \src "ls180.v:8243.3-8245.6" + switch $and$ls180.v:8243$2740_Y + attribute \src "ls180.v:8243.7-8243.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:8243.3-8245.6" - switch $and$ls180.v:8243$2741_Y - attribute \src "ls180.v:8243.7-8243.54" + attribute \src "ls180.v:8246.3-8248.6" + switch $and$ls180.v:8246$2741_Y + attribute \src "ls180.v:8246.7-8246.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:8248.2-8269.5" - switch $and$ls180.v:8248$2745_Y - attribute \src "ls180.v:8248.6-8248.91" + attribute \src "ls180.v:8251.2-8272.5" + switch $and$ls180.v:8251$2745_Y + attribute \src "ls180.v:8251.6-8251.91" case 1'1 assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 assign $0\main_uart_phy_tx_busy[0:0] 1'1 assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:8253.6-8253.10" + attribute \src "ls180.v:8256.6-8256.10" case - attribute \src "ls180.v:8254.3-8268.6" - switch $and$ls180.v:8254$2746_Y - attribute \src "ls180.v:8254.7-8254.60" + attribute \src "ls180.v:8257.3-8271.6" + switch $and$ls180.v:8257$2746_Y + attribute \src "ls180.v:8257.7-8257.60" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8255$2747_Y - attribute \src "ls180.v:8256.4-8267.7" - switch $eq$ls180.v:8256$2748_Y - attribute \src "ls180.v:8256.8-8256.43" + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8258$2747_Y + attribute \src "ls180.v:8259.4-8270.7" + switch $eq$ls180.v:8259$2748_Y + attribute \src "ls180.v:8259.8-8259.43" case 1'1 assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:8258.8-8258.12" + attribute \src "ls180.v:8261.8-8261.12" case - attribute \src "ls180.v:8259.5-8266.8" - switch $eq$ls180.v:8259$2749_Y - attribute \src "ls180.v:8259.9-8259.44" + attribute \src "ls180.v:8262.5-8269.8" + switch $eq$ls180.v:8262$2749_Y + attribute \src "ls180.v:8262.9-8262.44" case 1'1 assign $0\uart_tx[0:0] 1'1 assign $0\main_uart_phy_tx_busy[0:0] 1'0 assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:8263.9-8263.13" + attribute \src "ls180.v:8266.9-8266.13" case assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } @@ -294219,61 +296728,61 @@ module \ls180 case end end - attribute \src "ls180.v:8270.2-8274.5" + attribute \src "ls180.v:8273.2-8277.5" switch \main_uart_phy_tx_busy - attribute \src "ls180.v:8270.6-8270.27" + attribute \src "ls180.v:8273.6-8273.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8271$2750_Y - attribute \src "ls180.v:8272.6-8272.10" + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8274$2750_Y + attribute \src "ls180.v:8275.6-8275.10" case assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } end - attribute \src "ls180.v:8277.2-8301.5" - switch $not$ls180.v:8277$2751_Y - attribute \src "ls180.v:8277.6-8277.30" + attribute \src "ls180.v:8280.2-8304.5" + switch $not$ls180.v:8280$2751_Y + attribute \src "ls180.v:8280.6-8280.30" case 1'1 - attribute \src "ls180.v:8278.3-8281.6" - switch $and$ls180.v:8278$2753_Y - attribute \src "ls180.v:8278.7-8278.49" + attribute \src "ls180.v:8281.3-8284.6" + switch $and$ls180.v:8281$2753_Y + attribute \src "ls180.v:8281.7-8281.49" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'1 assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:8282.6-8282.10" + attribute \src "ls180.v:8285.6-8285.10" case - attribute \src "ls180.v:8283.3-8300.6" + attribute \src "ls180.v:8286.3-8303.6" switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:8283.7-8283.34" + attribute \src "ls180.v:8286.7-8286.34" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8284$2754_Y - attribute \src "ls180.v:8285.4-8299.7" - switch $eq$ls180.v:8285$2755_Y - attribute \src "ls180.v:8285.8-8285.43" + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8287$2754_Y + attribute \src "ls180.v:8288.4-8302.7" + switch $eq$ls180.v:8288$2755_Y + attribute \src "ls180.v:8288.8-8288.43" case 1'1 - attribute \src "ls180.v:8286.5-8288.8" + attribute \src "ls180.v:8289.5-8291.8" switch \main_uart_phy_rx - attribute \src "ls180.v:8286.9-8286.25" + attribute \src "ls180.v:8289.9-8289.25" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:8289.8-8289.12" + attribute \src "ls180.v:8292.8-8292.12" case - attribute \src "ls180.v:8290.5-8298.8" - switch $eq$ls180.v:8290$2756_Y - attribute \src "ls180.v:8290.9-8290.44" + attribute \src "ls180.v:8293.5-8301.8" + switch $eq$ls180.v:8293$2756_Y + attribute \src "ls180.v:8293.9-8293.44" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8292.6-8295.9" + attribute \src "ls180.v:8295.6-8298.9" switch \main_uart_phy_rx - attribute \src "ls180.v:8292.10-8292.26" + attribute \src "ls180.v:8295.10-8295.26" case 1'1 assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg assign $0\main_uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:8296.9-8296.13" + attribute \src "ls180.v:8299.9-8299.13" case assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } end @@ -294281,146 +296790,146 @@ module \ls180 case end end - attribute \src "ls180.v:8302.2-8306.5" + attribute \src "ls180.v:8305.2-8309.5" switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8302.6-8302.27" + attribute \src "ls180.v:8305.6-8305.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8303$2757_Y - attribute \src "ls180.v:8304.6-8304.10" + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8306$2757_Y + attribute \src "ls180.v:8307.6-8307.10" case assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:8307.2-8309.5" + attribute \src "ls180.v:8310.2-8312.5" switch \main_uart_tx_clear - attribute \src "ls180.v:8307.6-8307.24" + attribute \src "ls180.v:8310.6-8310.24" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8311.2-8313.5" - switch $and$ls180.v:8311$2759_Y - attribute \src "ls180.v:8311.6-8311.58" + attribute \src "ls180.v:8314.2-8316.5" + switch $and$ls180.v:8314$2759_Y + attribute \src "ls180.v:8314.6-8314.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8314.2-8316.5" + attribute \src "ls180.v:8317.2-8319.5" switch \main_uart_rx_clear - attribute \src "ls180.v:8314.6-8314.24" + attribute \src "ls180.v:8317.6-8317.24" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8318.2-8320.5" - switch $and$ls180.v:8318$2761_Y - attribute \src "ls180.v:8318.6-8318.58" + attribute \src "ls180.v:8321.2-8323.5" + switch $and$ls180.v:8321$2761_Y + attribute \src "ls180.v:8321.6-8321.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8321.2-8327.5" + attribute \src "ls180.v:8324.2-8330.5" switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8321.6-8321.35" + attribute \src "ls180.v:8324.6-8324.35" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8323.6-8323.10" + attribute \src "ls180.v:8326.6-8326.10" case - attribute \src "ls180.v:8324.3-8326.6" + attribute \src "ls180.v:8327.3-8329.6" switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8324.7-8324.27" + attribute \src "ls180.v:8327.7-8327.27" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8328.2-8330.5" - switch $and$ls180.v:8328$2764_Y - attribute \src "ls180.v:8328.6-8328.108" + attribute \src "ls180.v:8331.2-8333.5" + switch $and$ls180.v:8331$2764_Y + attribute \src "ls180.v:8331.6-8331.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8329$2765_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8332$2765_Y case end - attribute \src "ls180.v:8331.2-8333.5" + attribute \src "ls180.v:8334.2-8336.5" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8331.6-8331.31" + attribute \src "ls180.v:8334.6-8334.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8332$2766_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8335$2766_Y case end - attribute \src "ls180.v:8334.2-8342.5" - switch $and$ls180.v:8334$2769_Y - attribute \src "ls180.v:8334.6-8334.108" + attribute \src "ls180.v:8337.2-8345.5" + switch $and$ls180.v:8337$2769_Y + attribute \src "ls180.v:8337.6-8337.108" case 1'1 - attribute \src "ls180.v:8335.3-8337.6" - switch $not$ls180.v:8335$2770_Y - attribute \src "ls180.v:8335.7-8335.35" + attribute \src "ls180.v:8338.3-8340.6" + switch $not$ls180.v:8338$2770_Y + attribute \src "ls180.v:8338.7-8338.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8336$2771_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8339$2771_Y case end - attribute \src "ls180.v:8338.6-8338.10" + attribute \src "ls180.v:8341.6-8341.10" case - attribute \src "ls180.v:8339.3-8341.6" + attribute \src "ls180.v:8342.3-8344.6" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8339.7-8339.32" + attribute \src "ls180.v:8342.7-8342.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8340$2772_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8343$2772_Y case end end - attribute \src "ls180.v:8343.2-8349.5" + attribute \src "ls180.v:8346.2-8352.5" switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8343.6-8343.35" + attribute \src "ls180.v:8346.6-8346.35" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8345.6-8345.10" + attribute \src "ls180.v:8348.6-8348.10" case - attribute \src "ls180.v:8346.3-8348.6" + attribute \src "ls180.v:8349.3-8351.6" switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8346.7-8346.27" + attribute \src "ls180.v:8349.7-8349.27" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8350.2-8352.5" - switch $and$ls180.v:8350$2775_Y - attribute \src "ls180.v:8350.6-8350.108" + attribute \src "ls180.v:8353.2-8355.5" + switch $and$ls180.v:8353$2775_Y + attribute \src "ls180.v:8353.6-8353.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8351$2776_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8354$2776_Y case end - attribute \src "ls180.v:8353.2-8355.5" + attribute \src "ls180.v:8356.2-8358.5" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8353.6-8353.31" + attribute \src "ls180.v:8356.6-8356.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8354$2777_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8357$2777_Y case end - attribute \src "ls180.v:8356.2-8364.5" - switch $and$ls180.v:8356$2780_Y - attribute \src "ls180.v:8356.6-8356.108" + attribute \src "ls180.v:8359.2-8367.5" + switch $and$ls180.v:8359$2780_Y + attribute \src "ls180.v:8359.6-8359.108" case 1'1 - attribute \src "ls180.v:8357.3-8359.6" - switch $not$ls180.v:8357$2781_Y - attribute \src "ls180.v:8357.7-8357.35" + attribute \src "ls180.v:8360.3-8362.6" + switch $not$ls180.v:8360$2781_Y + attribute \src "ls180.v:8360.7-8360.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8358$2782_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8361$2782_Y case end - attribute \src "ls180.v:8360.6-8360.10" + attribute \src "ls180.v:8363.6-8363.10" case - attribute \src "ls180.v:8361.3-8363.6" + attribute \src "ls180.v:8364.3-8366.6" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8361.7-8361.32" + attribute \src "ls180.v:8364.7-8364.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8362$2783_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8365$2783_Y case end end - attribute \src "ls180.v:8365.2-8378.5" + attribute \src "ls180.v:8368.2-8381.5" switch \main_uart_reset - attribute \src "ls180.v:8365.6-8365.21" + attribute \src "ls180.v:8368.6-8368.21" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 assign $0\main_uart_tx_old_trigger[0:0] 1'0 @@ -294436,38 +296945,38 @@ module \ls180 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:8380.2-8387.5" + attribute \src "ls180.v:8383.2-8390.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8380.6-8380.31" + attribute \src "ls180.v:8383.6-8383.31" case 1'1 assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8382.6-8382.10" + attribute \src "ls180.v:8385.6-8385.10" case - attribute \src "ls180.v:8383.3-8386.6" + attribute \src "ls180.v:8386.3-8389.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8383.7-8383.32" + attribute \src "ls180.v:8386.7-8386.32" case 1'1 assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 assign $0\spisdcard_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8389.2-8399.5" + attribute \src "ls180.v:8392.2-8402.5" switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8389.6-8389.33" + attribute \src "ls180.v:8392.6-8392.33" case 1'1 assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8392.6-8392.10" + attribute \src "ls180.v:8395.6-8395.10" case - attribute \src "ls180.v:8393.3-8398.6" + attribute \src "ls180.v:8396.3-8401.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8393.7-8393.32" + attribute \src "ls180.v:8396.7-8396.32" case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8397$2788_Y - attribute \src "ls180.v:8394.4-8396.7" + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8400$2788_Y + attribute \src "ls180.v:8397.4-8399.7" switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8394.8-8394.34" + attribute \src "ls180.v:8397.8-8397.34" case 1'1 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 case @@ -294475,67 +296984,67 @@ module \ls180 case end end - attribute \src "ls180.v:8400.2-8406.5" + attribute \src "ls180.v:8403.2-8409.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8400.6-8400.31" + attribute \src "ls180.v:8403.6-8403.31" case 1'1 - attribute \src "ls180.v:8401.3-8405.6" + attribute \src "ls180.v:8404.3-8408.6" switch \main_spimaster7_loopback - attribute \src "ls180.v:8401.7-8401.31" + attribute \src "ls180.v:8404.7-8404.31" case 1'1 assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8403.7-8403.11" + attribute \src "ls180.v:8406.7-8406.11" case assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } end case end - attribute \src "ls180.v:8407.2-8409.5" + attribute \src "ls180.v:8410.2-8412.5" switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8407.6-8407.33" + attribute \src "ls180.v:8410.6-8410.33" case 1'1 assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data case end - attribute \src "ls180.v:8411.2-8413.5" + attribute \src "ls180.v:8414.2-8416.5" switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8411.6-8411.53" + attribute \src "ls180.v:8414.6-8414.53" case 1'1 assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value case end - attribute \src "ls180.v:8415.2-8422.5" + attribute \src "ls180.v:8418.2-8425.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8415.6-8415.29" + attribute \src "ls180.v:8418.6-8418.29" case 1'1 assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8417.6-8417.10" + attribute \src "ls180.v:8420.6-8420.10" case - attribute \src "ls180.v:8418.3-8421.6" + attribute \src "ls180.v:8421.3-8424.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8418.7-8418.30" + attribute \src "ls180.v:8421.7-8421.30" case 1'1 assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 assign $0\spimaster_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8424.2-8434.5" + attribute \src "ls180.v:8427.2-8437.5" switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8424.6-8424.31" + attribute \src "ls180.v:8427.6-8427.31" case 1'1 assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8427.6-8427.10" + attribute \src "ls180.v:8430.6-8430.10" case - attribute \src "ls180.v:8428.3-8433.6" + attribute \src "ls180.v:8431.3-8436.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8428.7-8428.30" + attribute \src "ls180.v:8431.7-8431.30" case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8432$2793_Y - attribute \src "ls180.v:8429.4-8431.7" + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8435$2793_Y + attribute \src "ls180.v:8432.4-8434.7" switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8429.8-8429.32" + attribute \src "ls180.v:8432.8-8432.32" case 1'1 assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 case @@ -294543,169 +297052,169 @@ module \ls180 case end end - attribute \src "ls180.v:8435.2-8441.5" + attribute \src "ls180.v:8438.2-8444.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8435.6-8435.29" + attribute \src "ls180.v:8438.6-8438.29" case 1'1 - attribute \src "ls180.v:8436.3-8440.6" + attribute \src "ls180.v:8439.3-8443.6" switch \main_spisdcard_loopback - attribute \src "ls180.v:8436.7-8436.30" + attribute \src "ls180.v:8439.7-8439.30" case 1'1 assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8438.7-8438.11" + attribute \src "ls180.v:8441.7-8441.11" case assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } end case end - attribute \src "ls180.v:8442.2-8444.5" + attribute \src "ls180.v:8445.2-8447.5" switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8442.6-8442.31" + attribute \src "ls180.v:8445.6-8445.31" case 1'1 assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data case end - attribute \src "ls180.v:8446.2-8448.5" + attribute \src "ls180.v:8449.2-8451.5" switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8446.6-8446.51" + attribute \src "ls180.v:8449.6-8449.51" case 1'1 assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value case end - attribute \src "ls180.v:8449.2-8462.5" + attribute \src "ls180.v:8452.2-8465.5" switch \main_pwm0_enable - attribute \src "ls180.v:8449.6-8449.22" + attribute \src "ls180.v:8452.6-8452.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8450$2794_Y - attribute \src "ls180.v:8451.3-8455.6" - switch $lt$ls180.v:8451$2795_Y - attribute \src "ls180.v:8451.7-8451.44" + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8453$2794_Y + attribute \src "ls180.v:8454.3-8458.6" + switch $lt$ls180.v:8454$2795_Y + attribute \src "ls180.v:8454.7-8454.44" case 1'1 assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8453.7-8453.11" + attribute \src "ls180.v:8456.7-8456.11" case assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8456.3-8458.6" - switch $ge$ls180.v:8456$2797_Y - attribute \src "ls180.v:8456.7-8456.55" + attribute \src "ls180.v:8459.3-8461.6" + switch $ge$ls180.v:8459$2797_Y + attribute \src "ls180.v:8459.7-8459.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 case end - attribute \src "ls180.v:8459.6-8459.10" + attribute \src "ls180.v:8462.6-8462.10" case assign $0\main_pwm0_counter[31:0] 0 assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8463.2-8476.5" + attribute \src "ls180.v:8466.2-8479.5" switch \main_pwm1_enable - attribute \src "ls180.v:8463.6-8463.22" + attribute \src "ls180.v:8466.6-8466.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8464$2798_Y - attribute \src "ls180.v:8465.3-8469.6" - switch $lt$ls180.v:8465$2799_Y - attribute \src "ls180.v:8465.7-8465.44" + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8467$2798_Y + attribute \src "ls180.v:8468.3-8472.6" + switch $lt$ls180.v:8468$2799_Y + attribute \src "ls180.v:8468.7-8468.44" case 1'1 assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8467.7-8467.11" + attribute \src "ls180.v:8470.7-8470.11" case assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8470.3-8472.6" - switch $ge$ls180.v:8470$2801_Y - attribute \src "ls180.v:8470.7-8470.55" + attribute \src "ls180.v:8473.3-8475.6" + switch $ge$ls180.v:8473$2801_Y + attribute \src "ls180.v:8473.7-8473.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 case end - attribute \src "ls180.v:8473.6-8473.10" + attribute \src "ls180.v:8476.6-8476.10" case assign $0\main_pwm1_counter[31:0] 0 assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8477.2-8479.5" - switch $not$ls180.v:8477$2802_Y - attribute \src "ls180.v:8477.6-8477.32" + attribute \src "ls180.v:8480.2-8482.5" + switch $not$ls180.v:8480$2802_Y + attribute \src "ls180.v:8480.6-8480.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8478$2803_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8481$2803_Y case end - attribute \src "ls180.v:8483.2-8485.5" + attribute \src "ls180.v:8486.2-8488.5" switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8483.6-8483.57" + attribute \src "ls180.v:8486.6-8486.57" case 1'1 assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value case end - attribute \src "ls180.v:8487.2-8489.5" + attribute \src "ls180.v:8490.2-8492.5" switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8487.6-8487.57" + attribute \src "ls180.v:8490.6-8490.57" case 1'1 assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value case end - attribute \src "ls180.v:8490.2-8492.5" + attribute \src "ls180.v:8493.2-8495.5" switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8490.6-8490.40" + attribute \src "ls180.v:8493.6-8493.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8491$2804_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8494$2804_Y case end - attribute \src "ls180.v:8493.2-8495.5" + attribute \src "ls180.v:8496.2-8498.5" switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8493.6-8493.49" + attribute \src "ls180.v:8496.6-8496.49" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8496.2-8503.5" + attribute \src "ls180.v:8499.2-8506.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8496.6-8496.46" + attribute \src "ls180.v:8499.6-8499.46" case 1'1 - attribute \src "ls180.v:8497.3-8502.6" - switch $or$ls180.v:8497$2806_Y - attribute \src "ls180.v:8497.7-8497.98" + attribute \src "ls180.v:8500.3-8505.6" + switch $or$ls180.v:8500$2806_Y + attribute \src "ls180.v:8500.7-8500.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8500.7-8500.11" + attribute \src "ls180.v:8503.7-8503.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8501$2807_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8504$2807_Y end case end - attribute \src "ls180.v:8504.2-8517.5" - switch $and$ls180.v:8504$2808_Y - attribute \src "ls180.v:8504.6-8504.97" + attribute \src "ls180.v:8507.2-8520.5" + switch $and$ls180.v:8507$2808_Y + attribute \src "ls180.v:8507.6-8507.97" case 1'1 - attribute \src "ls180.v:8505.3-8511.6" - switch $and$ls180.v:8505$2809_Y - attribute \src "ls180.v:8505.7-8505.94" + attribute \src "ls180.v:8508.3-8514.6" + switch $and$ls180.v:8508$2809_Y + attribute \src "ls180.v:8508.7-8508.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8508.7-8508.11" + attribute \src "ls180.v:8511.7-8511.11" case assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8512.6-8512.10" + attribute \src "ls180.v:8515.6-8515.10" case - attribute \src "ls180.v:8513.3-8516.6" - switch $and$ls180.v:8513$2810_Y - attribute \src "ls180.v:8513.7-8513.94" + attribute \src "ls180.v:8516.3-8519.6" + switch $and$ls180.v:8516$2810_Y + attribute \src "ls180.v:8516.7-8516.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8514$2811_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8515$2812_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8517$2811_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8518$2812_Y case end end - attribute \src "ls180.v:8518.2-8545.5" + attribute \src "ls180.v:8521.2-8548.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8518.6-8518.46" + attribute \src "ls180.v:8521.6-8521.46" case 1'1 - attribute \src "ls180.v:8519.3-8544.10" + attribute \src "ls180.v:8522.3-8547.10" switch \main_sdphy_cmdr_cmdr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -294735,16 +297244,16 @@ module \ls180 end case end - attribute \src "ls180.v:8546.2-8548.5" + attribute \src "ls180.v:8549.2-8551.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8546.6-8546.46" + attribute \src "ls180.v:8549.6-8549.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8547$2813_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8550$2813_Y case end - attribute \src "ls180.v:8549.2-8554.5" - switch $or$ls180.v:8549$2815_Y - attribute \src "ls180.v:8549.6-8549.88" + attribute \src "ls180.v:8552.2-8557.5" + switch $or$ls180.v:8552$2815_Y + attribute \src "ls180.v:8552.6-8552.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first @@ -294752,9 +297261,9 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data case end - attribute \src "ls180.v:8555.2-8560.5" + attribute \src "ls180.v:8558.2-8563.5" switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8555.6-8555.32" + attribute \src "ls180.v:8558.6-8558.32" case 1'1 assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 @@ -294762,88 +297271,88 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8562.2-8564.5" + attribute \src "ls180.v:8565.2-8567.5" switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8562.6-8562.58" + attribute \src "ls180.v:8565.6-8565.58" case 1'1 assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 case end - attribute \src "ls180.v:8565.2-8567.5" + attribute \src "ls180.v:8568.2-8570.5" switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8565.6-8565.60" + attribute \src "ls180.v:8568.6-8568.60" case 1'1 assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 case end - attribute \src "ls180.v:8568.2-8570.5" + attribute \src "ls180.v:8571.2-8573.5" switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8568.6-8568.63" + attribute \src "ls180.v:8571.6-8571.63" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 case end - attribute \src "ls180.v:8571.2-8573.5" + attribute \src "ls180.v:8574.2-8576.5" switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8571.6-8571.41" + attribute \src "ls180.v:8574.6-8574.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8572$2816_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8575$2816_Y case end - attribute \src "ls180.v:8574.2-8576.5" + attribute \src "ls180.v:8577.2-8579.5" switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8574.6-8574.50" + attribute \src "ls180.v:8577.6-8577.50" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8577.2-8584.5" + attribute \src "ls180.v:8580.2-8587.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8577.6-8577.47" + attribute \src "ls180.v:8580.6-8580.47" case 1'1 - attribute \src "ls180.v:8578.3-8583.6" - switch $or$ls180.v:8578$2818_Y - attribute \src "ls180.v:8578.7-8578.100" + attribute \src "ls180.v:8581.3-8586.6" + switch $or$ls180.v:8581$2818_Y + attribute \src "ls180.v:8581.7-8581.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8581.7-8581.11" + attribute \src "ls180.v:8584.7-8584.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8582$2819_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8585$2819_Y end case end - attribute \src "ls180.v:8585.2-8598.5" - switch $and$ls180.v:8585$2820_Y - attribute \src "ls180.v:8585.6-8585.99" + attribute \src "ls180.v:8588.2-8601.5" + switch $and$ls180.v:8588$2820_Y + attribute \src "ls180.v:8588.6-8588.99" case 1'1 - attribute \src "ls180.v:8586.3-8592.6" - switch $and$ls180.v:8586$2821_Y - attribute \src "ls180.v:8586.7-8586.96" + attribute \src "ls180.v:8589.3-8595.6" + switch $and$ls180.v:8589$2821_Y + attribute \src "ls180.v:8589.7-8589.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8589.7-8589.11" + attribute \src "ls180.v:8592.7-8592.11" case assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8593.6-8593.10" + attribute \src "ls180.v:8596.6-8596.10" case - attribute \src "ls180.v:8594.3-8597.6" - switch $and$ls180.v:8594$2822_Y - attribute \src "ls180.v:8594.7-8594.96" + attribute \src "ls180.v:8597.3-8600.6" + switch $and$ls180.v:8597$2822_Y + attribute \src "ls180.v:8597.7-8597.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8595$2823_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8596$2824_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8598$2823_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8599$2824_Y case end end - attribute \src "ls180.v:8599.2-8626.5" + attribute \src "ls180.v:8602.2-8629.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8599.6-8599.47" + attribute \src "ls180.v:8602.6-8602.47" case 1'1 - attribute \src "ls180.v:8600.3-8625.10" + attribute \src "ls180.v:8603.3-8628.10" switch \main_sdphy_dataw_crcr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -294873,16 +297382,16 @@ module \ls180 end case end - attribute \src "ls180.v:8627.2-8629.5" + attribute \src "ls180.v:8630.2-8632.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8627.6-8627.47" + attribute \src "ls180.v:8630.6-8630.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8628$2825_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8631$2825_Y case end - attribute \src "ls180.v:8630.2-8635.5" - switch $or$ls180.v:8630$2827_Y - attribute \src "ls180.v:8630.6-8630.90" + attribute \src "ls180.v:8633.2-8638.5" + switch $or$ls180.v:8633$2827_Y + attribute \src "ls180.v:8633.6-8633.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first @@ -294890,9 +297399,9 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data case end - attribute \src "ls180.v:8636.2-8641.5" + attribute \src "ls180.v:8639.2-8644.5" switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8636.6-8636.33" + attribute \src "ls180.v:8639.6-8639.33" case 1'1 assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 @@ -294900,81 +297409,81 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8643.2-8645.5" + attribute \src "ls180.v:8646.2-8648.5" switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8643.6-8643.63" + attribute \src "ls180.v:8646.6-8646.63" case 1'1 assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value case end - attribute \src "ls180.v:8647.2-8649.5" + attribute \src "ls180.v:8650.2-8652.5" switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8647.6-8647.52" + attribute \src "ls180.v:8650.6-8650.52" case 1'1 assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value case end - attribute \src "ls180.v:8650.2-8652.5" + attribute \src "ls180.v:8653.2-8655.5" switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8650.6-8650.42" + attribute \src "ls180.v:8653.6-8653.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8651$2828_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8654$2828_Y case end - attribute \src "ls180.v:8653.2-8655.5" + attribute \src "ls180.v:8656.2-8658.5" switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8653.6-8653.51" + attribute \src "ls180.v:8656.6-8656.51" case 1'1 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8656.2-8663.5" + attribute \src "ls180.v:8659.2-8666.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8656.6-8656.48" + attribute \src "ls180.v:8659.6-8659.48" case 1'1 - attribute \src "ls180.v:8657.3-8662.6" - switch $or$ls180.v:8657$2830_Y - attribute \src "ls180.v:8657.7-8657.102" + attribute \src "ls180.v:8660.3-8665.6" + switch $or$ls180.v:8660$2830_Y + attribute \src "ls180.v:8660.7-8660.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8660.7-8660.11" + attribute \src "ls180.v:8663.7-8663.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8661$2831_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8664$2831_Y end case end - attribute \src "ls180.v:8664.2-8677.5" - switch $and$ls180.v:8664$2832_Y - attribute \src "ls180.v:8664.6-8664.101" + attribute \src "ls180.v:8667.2-8680.5" + switch $and$ls180.v:8667$2832_Y + attribute \src "ls180.v:8667.6-8667.101" case 1'1 - attribute \src "ls180.v:8665.3-8671.6" - switch $and$ls180.v:8665$2833_Y - attribute \src "ls180.v:8665.7-8665.98" + attribute \src "ls180.v:8668.3-8674.6" + switch $and$ls180.v:8668$2833_Y + attribute \src "ls180.v:8668.7-8668.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8668.7-8668.11" + attribute \src "ls180.v:8671.7-8671.11" case assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8672.6-8672.10" + attribute \src "ls180.v:8675.6-8675.10" case - attribute \src "ls180.v:8673.3-8676.6" - switch $and$ls180.v:8673$2834_Y - attribute \src "ls180.v:8673.7-8673.98" + attribute \src "ls180.v:8676.3-8679.6" + switch $and$ls180.v:8676$2834_Y + attribute \src "ls180.v:8676.7-8676.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8674$2835_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8675$2836_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8677$2835_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8678$2836_Y case end end - attribute \src "ls180.v:8678.2-8687.5" + attribute \src "ls180.v:8681.2-8690.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8678.6-8678.48" + attribute \src "ls180.v:8681.6-8681.48" case 1'1 - attribute \src "ls180.v:8679.3-8686.10" + attribute \src "ls180.v:8682.3-8689.10" switch \main_sdphy_datar_datar_converter_demux attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -294986,16 +297495,16 @@ module \ls180 end case end - attribute \src "ls180.v:8688.2-8690.5" + attribute \src "ls180.v:8691.2-8693.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8688.6-8688.48" + attribute \src "ls180.v:8691.6-8691.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8689$2837_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8692$2837_Y case end - attribute \src "ls180.v:8691.2-8696.5" - switch $or$ls180.v:8691$2839_Y - attribute \src "ls180.v:8691.6-8691.92" + attribute \src "ls180.v:8694.2-8699.5" + switch $or$ls180.v:8694$2839_Y + attribute \src "ls180.v:8694.6-8694.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first @@ -295003,9 +297512,9 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data case end - attribute \src "ls180.v:8697.2-8702.5" + attribute \src "ls180.v:8700.2-8705.5" switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8697.6-8697.34" + attribute \src "ls180.v:8700.6-8700.34" case 1'1 assign $0\main_sdphy_datar_datar_run[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 @@ -295013,434 +297522,434 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8704.2-8706.5" + attribute \src "ls180.v:8707.2-8709.5" switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8704.6-8704.60" + attribute \src "ls180.v:8707.6-8707.60" case 1'1 assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 case end - attribute \src "ls180.v:8707.2-8709.5" + attribute \src "ls180.v:8710.2-8712.5" switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8707.6-8707.62" + attribute \src "ls180.v:8710.6-8710.62" case 1'1 assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 case end - attribute \src "ls180.v:8710.2-8712.5" + attribute \src "ls180.v:8713.2-8715.5" switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8710.6-8710.66" + attribute \src "ls180.v:8713.6-8713.66" case 1'1 assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 case end - attribute \src "ls180.v:8713.2-8719.5" + attribute \src "ls180.v:8716.2-8722.5" switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8713.6-8713.35" + attribute \src "ls180.v:8716.6-8716.35" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8715.6-8715.10" + attribute \src "ls180.v:8718.6-8718.10" case - attribute \src "ls180.v:8716.3-8718.6" + attribute \src "ls180.v:8719.3-8721.6" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8716.7-8716.39" + attribute \src "ls180.v:8719.7-8719.39" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 case end end - attribute \src "ls180.v:8720.2-8726.5" + attribute \src "ls180.v:8723.2-8729.5" switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8720.6-8720.41" + attribute \src "ls180.v:8723.6-8723.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8722.6-8722.10" + attribute \src "ls180.v:8725.6-8725.10" case - attribute \src "ls180.v:8723.3-8725.6" + attribute \src "ls180.v:8726.3-8728.6" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8723.7-8723.45" + attribute \src "ls180.v:8726.7-8726.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 case end end - attribute \src "ls180.v:8727.2-8733.5" + attribute \src "ls180.v:8730.2-8736.5" switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8727.6-8727.41" + attribute \src "ls180.v:8730.6-8730.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8729.6-8729.10" + attribute \src "ls180.v:8732.6-8732.10" case - attribute \src "ls180.v:8730.3-8732.6" + attribute \src "ls180.v:8733.3-8735.6" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8730.7-8730.45" + attribute \src "ls180.v:8733.7-8733.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 case end end - attribute \src "ls180.v:8734.2-8740.5" + attribute \src "ls180.v:8737.2-8743.5" switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8734.6-8734.41" + attribute \src "ls180.v:8737.6-8737.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8736.6-8736.10" + attribute \src "ls180.v:8739.6-8739.10" case - attribute \src "ls180.v:8737.3-8739.6" + attribute \src "ls180.v:8740.3-8742.6" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8737.7-8737.45" + attribute \src "ls180.v:8740.7-8740.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 case end end - attribute \src "ls180.v:8741.2-8747.5" + attribute \src "ls180.v:8744.2-8750.5" switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8741.6-8741.41" + attribute \src "ls180.v:8744.6-8744.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8743.6-8743.10" + attribute \src "ls180.v:8746.6-8746.10" case - attribute \src "ls180.v:8744.3-8746.6" + attribute \src "ls180.v:8747.3-8749.6" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8744.7-8744.45" + attribute \src "ls180.v:8747.7-8747.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 case end end - attribute \src "ls180.v:8749.2-8751.5" + attribute \src "ls180.v:8752.2-8754.5" switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8749.6-8749.82" + attribute \src "ls180.v:8752.6-8752.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 case end - attribute \src "ls180.v:8752.2-8754.5" + attribute \src "ls180.v:8755.2-8757.5" switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8752.6-8752.82" + attribute \src "ls180.v:8755.6-8755.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 case end - attribute \src "ls180.v:8755.2-8757.5" + attribute \src "ls180.v:8758.2-8760.5" switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8755.6-8755.82" + attribute \src "ls180.v:8758.6-8758.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 case end - attribute \src "ls180.v:8758.2-8760.5" + attribute \src "ls180.v:8761.2-8763.5" switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8758.6-8758.82" + attribute \src "ls180.v:8761.6-8761.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 case end - attribute \src "ls180.v:8761.2-8763.5" + attribute \src "ls180.v:8764.2-8766.5" switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8761.6-8761.78" + attribute \src "ls180.v:8764.6-8764.78" case 1'1 assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 case end - attribute \src "ls180.v:8764.2-8766.5" - switch $and$ls180.v:8764$2840_Y - attribute \src "ls180.v:8764.6-8764.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc - case - end attribute \src "ls180.v:8767.2-8769.5" - switch $and$ls180.v:8767$2841_Y + switch $and$ls180.v:8767$2840_Y attribute \src "ls180.v:8767.6-8767.83" case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end attribute \src "ls180.v:8770.2-8772.5" - switch $and$ls180.v:8770$2842_Y + switch $and$ls180.v:8770$2841_Y attribute \src "ls180.v:8770.6-8770.83" case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end attribute \src "ls180.v:8773.2-8775.5" - switch $and$ls180.v:8773$2843_Y + switch $and$ls180.v:8773$2842_Y attribute \src "ls180.v:8773.6-8773.83" case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end - attribute \src "ls180.v:8776.2-8780.5" - switch $and$ls180.v:8776$2844_Y + attribute \src "ls180.v:8776.2-8778.5" + switch $and$ls180.v:8776$2843_Y attribute \src "ls180.v:8776.6-8776.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8779.2-8783.5" + switch $and$ls180.v:8779$2844_Y + attribute \src "ls180.v:8779.6-8779.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] case end - attribute \src "ls180.v:8781.2-8785.5" - switch $and$ls180.v:8781$2845_Y - attribute \src "ls180.v:8781.6-8781.83" + attribute \src "ls180.v:8784.2-8788.5" + switch $and$ls180.v:8784$2845_Y + attribute \src "ls180.v:8784.6-8784.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] case end - attribute \src "ls180.v:8786.2-8790.5" - switch $and$ls180.v:8786$2846_Y - attribute \src "ls180.v:8786.6-8786.83" + attribute \src "ls180.v:8789.2-8793.5" + switch $and$ls180.v:8789$2846_Y + attribute \src "ls180.v:8789.6-8789.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] case end - attribute \src "ls180.v:8791.2-8795.5" - switch $and$ls180.v:8791$2847_Y - attribute \src "ls180.v:8791.6-8791.83" + attribute \src "ls180.v:8794.2-8798.5" + switch $and$ls180.v:8794$2847_Y + attribute \src "ls180.v:8794.6-8794.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] case end - attribute \src "ls180.v:8796.2-8804.5" - switch $and$ls180.v:8796$2848_Y - attribute \src "ls180.v:8796.6-8796.83" + attribute \src "ls180.v:8799.2-8807.5" + switch $and$ls180.v:8799$2848_Y + attribute \src "ls180.v:8799.6-8799.83" case 1'1 - attribute \src "ls180.v:8797.3-8803.6" + attribute \src "ls180.v:8800.3-8806.6" switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8797.7-8797.42" + attribute \src "ls180.v:8800.7-8800.42" case 1'1 assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8799.7-8799.11" + attribute \src "ls180.v:8802.7-8802.11" case - attribute \src "ls180.v:8800.4-8802.7" - switch $ne$ls180.v:8800$2849_Y - attribute \src "ls180.v:8800.8-8800.48" + attribute \src "ls180.v:8803.4-8805.7" + switch $ne$ls180.v:8803$2849_Y + attribute \src "ls180.v:8803.8-8803.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8801$2850_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8804$2850_Y case end end case end - attribute \src "ls180.v:8805.2-8811.5" + attribute \src "ls180.v:8808.2-8814.5" switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8805.6-8805.40" + attribute \src "ls180.v:8808.6-8808.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8807.6-8807.10" + attribute \src "ls180.v:8810.6-8810.10" case - attribute \src "ls180.v:8808.3-8810.6" + attribute \src "ls180.v:8811.3-8813.6" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8808.7-8808.44" + attribute \src "ls180.v:8811.7-8811.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 case end end - attribute \src "ls180.v:8812.2-8818.5" + attribute \src "ls180.v:8815.2-8821.5" switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8812.6-8812.40" + attribute \src "ls180.v:8815.6-8815.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8814.6-8814.10" + attribute \src "ls180.v:8817.6-8817.10" case - attribute \src "ls180.v:8815.3-8817.6" + attribute \src "ls180.v:8818.3-8820.6" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8815.7-8815.44" + attribute \src "ls180.v:8818.7-8818.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 case end end - attribute \src "ls180.v:8819.2-8825.5" + attribute \src "ls180.v:8822.2-8828.5" switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8819.6-8819.40" + attribute \src "ls180.v:8822.6-8822.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8821.6-8821.10" + attribute \src "ls180.v:8824.6-8824.10" case - attribute \src "ls180.v:8822.3-8824.6" + attribute \src "ls180.v:8825.3-8827.6" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8822.7-8822.44" + attribute \src "ls180.v:8825.7-8825.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 case end end - attribute \src "ls180.v:8826.2-8832.5" + attribute \src "ls180.v:8829.2-8835.5" switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8826.6-8826.40" + attribute \src "ls180.v:8829.6-8829.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8828.6-8828.10" + attribute \src "ls180.v:8831.6-8831.10" case - attribute \src "ls180.v:8829.3-8831.6" + attribute \src "ls180.v:8832.3-8834.6" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8829.7-8829.44" + attribute \src "ls180.v:8832.7-8832.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 case end end - attribute \src "ls180.v:8834.2-8836.5" + attribute \src "ls180.v:8837.2-8839.5" switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8834.6-8834.52" + attribute \src "ls180.v:8837.6-8837.52" case 1'1 assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 case end - attribute \src "ls180.v:8837.2-8839.5" + attribute \src "ls180.v:8840.2-8842.5" switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8837.6-8837.53" + attribute \src "ls180.v:8840.6-8840.53" case 1'1 assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 case end - attribute \src "ls180.v:8840.2-8842.5" + attribute \src "ls180.v:8843.2-8845.5" switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8840.6-8840.53" + attribute \src "ls180.v:8843.6-8843.53" case 1'1 assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 case end - attribute \src "ls180.v:8843.2-8845.5" + attribute \src "ls180.v:8846.2-8848.5" switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8843.6-8843.54" + attribute \src "ls180.v:8846.6-8846.54" case 1'1 assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 case end - attribute \src "ls180.v:8846.2-8848.5" + attribute \src "ls180.v:8849.2-8851.5" switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8846.6-8846.53" + attribute \src "ls180.v:8849.6-8849.53" case 1'1 assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 case end - attribute \src "ls180.v:8849.2-8851.5" + attribute \src "ls180.v:8852.2-8854.5" switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8849.6-8849.55" + attribute \src "ls180.v:8852.6-8852.55" case 1'1 assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 case end - attribute \src "ls180.v:8852.2-8854.5" + attribute \src "ls180.v:8855.2-8857.5" switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8852.6-8852.54" + attribute \src "ls180.v:8855.6-8855.54" case 1'1 assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 case end - attribute \src "ls180.v:8855.2-8857.5" + attribute \src "ls180.v:8858.2-8860.5" switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8855.6-8855.56" + attribute \src "ls180.v:8858.6-8858.56" case 1'1 assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 case end - attribute \src "ls180.v:8858.2-8860.5" + attribute \src "ls180.v:8861.2-8863.5" switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8858.6-8858.63" + attribute \src "ls180.v:8861.6-8861.63" case 1'1 assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 case end - attribute \src "ls180.v:8861.2-8863.5" - switch $and$ls180.v:8861$2853_Y - attribute \src "ls180.v:8861.6-8861.120" + attribute \src "ls180.v:8864.2-8866.5" + switch $and$ls180.v:8864$2853_Y + attribute \src "ls180.v:8864.6-8864.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8862$2854_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8865$2854_Y case end - attribute \src "ls180.v:8864.2-8866.5" + attribute \src "ls180.v:8867.2-8869.5" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8864.6-8864.35" + attribute \src "ls180.v:8867.6-8867.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8865$2855_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8868$2855_Y case end - attribute \src "ls180.v:8867.2-8875.5" - switch $and$ls180.v:8867$2858_Y - attribute \src "ls180.v:8867.6-8867.120" + attribute \src "ls180.v:8870.2-8878.5" + switch $and$ls180.v:8870$2858_Y + attribute \src "ls180.v:8870.6-8870.120" case 1'1 - attribute \src "ls180.v:8868.3-8870.6" - switch $not$ls180.v:8868$2859_Y - attribute \src "ls180.v:8868.7-8868.39" + attribute \src "ls180.v:8871.3-8873.6" + switch $not$ls180.v:8871$2859_Y + attribute \src "ls180.v:8871.7-8871.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8869$2860_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8872$2860_Y case end - attribute \src "ls180.v:8871.6-8871.10" + attribute \src "ls180.v:8874.6-8874.10" case - attribute \src "ls180.v:8872.3-8874.6" + attribute \src "ls180.v:8875.3-8877.6" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8872.7-8872.36" + attribute \src "ls180.v:8875.7-8875.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8873$2861_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8876$2861_Y case end end - attribute \src "ls180.v:8876.2-8878.5" + attribute \src "ls180.v:8879.2-8881.5" switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8876.6-8876.45" + attribute \src "ls180.v:8879.6-8879.45" case 1'1 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8879.2-8886.5" + attribute \src "ls180.v:8882.2-8889.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8879.6-8879.42" + attribute \src "ls180.v:8882.6-8882.42" case 1'1 - attribute \src "ls180.v:8880.3-8885.6" - switch $or$ls180.v:8880$2863_Y - attribute \src "ls180.v:8880.7-8880.90" + attribute \src "ls180.v:8883.3-8888.6" + switch $or$ls180.v:8883$2863_Y + attribute \src "ls180.v:8883.7-8883.90" case 1'1 assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8883.7-8883.11" + attribute \src "ls180.v:8886.7-8886.11" case - assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8884$2864_Y + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8887$2864_Y end case end - attribute \src "ls180.v:8887.2-8900.5" - switch $and$ls180.v:8887$2865_Y - attribute \src "ls180.v:8887.6-8887.89" + attribute \src "ls180.v:8890.2-8903.5" + switch $and$ls180.v:8890$2865_Y + attribute \src "ls180.v:8890.6-8890.89" case 1'1 - attribute \src "ls180.v:8888.3-8894.6" - switch $and$ls180.v:8888$2866_Y - attribute \src "ls180.v:8888.7-8888.86" + attribute \src "ls180.v:8891.3-8897.6" + switch $and$ls180.v:8891$2866_Y + attribute \src "ls180.v:8891.7-8891.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8891.7-8891.11" + attribute \src "ls180.v:8894.7-8894.11" case assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8895.6-8895.10" + attribute \src "ls180.v:8898.6-8898.10" case - attribute \src "ls180.v:8896.3-8899.6" - switch $and$ls180.v:8896$2867_Y - attribute \src "ls180.v:8896.7-8896.86" + attribute \src "ls180.v:8899.3-8902.6" + switch $and$ls180.v:8899$2867_Y + attribute \src "ls180.v:8899.7-8899.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8897$2868_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8898$2869_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8900$2868_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8901$2869_Y case end end - attribute \src "ls180.v:8901.2-8928.5" + attribute \src "ls180.v:8904.2-8931.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8901.6-8901.42" + attribute \src "ls180.v:8904.6-8904.42" case 1'1 - attribute \src "ls180.v:8902.3-8927.10" + attribute \src "ls180.v:8905.3-8930.10" switch \main_sdblock2mem_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -295470,153 +297979,153 @@ module \ls180 end case end - attribute \src "ls180.v:8929.2-8931.5" + attribute \src "ls180.v:8932.2-8934.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8929.6-8929.42" + attribute \src "ls180.v:8932.6-8932.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8930$2870_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8933$2870_Y case end - attribute \src "ls180.v:8933.2-8935.5" + attribute \src "ls180.v:8936.2-8938.5" switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8933.6-8933.76" + attribute \src "ls180.v:8936.6-8936.76" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value case end - attribute \src "ls180.v:8936.2-8939.5" + attribute \src "ls180.v:8939.2-8942.5" switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8936.6-8936.46" + attribute \src "ls180.v:8939.6-8939.46" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 assign $0\builder_sdblock2memdma_state[1:0] 2'00 case end - attribute \src "ls180.v:8941.2-8943.5" + attribute \src "ls180.v:8944.2-8946.5" switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8941.6-8941.64" + attribute \src "ls180.v:8944.6-8944.64" case 1'1 assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value case end - attribute \src "ls180.v:8945.2-8947.5" + attribute \src "ls180.v:8948.2-8950.5" switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8945.6-8945.76" + attribute \src "ls180.v:8948.6-8948.76" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value case end - attribute \src "ls180.v:8948.2-8951.5" + attribute \src "ls180.v:8951.2-8954.5" switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8948.6-8948.32" + attribute \src "ls180.v:8951.6-8951.32" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 case end - attribute \src "ls180.v:8952.2-8958.5" - switch $and$ls180.v:8952$2871_Y - attribute \src "ls180.v:8952.6-8952.89" + attribute \src "ls180.v:8955.2-8961.5" + switch $and$ls180.v:8955$2871_Y + attribute \src "ls180.v:8955.6-8955.89" case 1'1 - attribute \src "ls180.v:8953.3-8957.6" + attribute \src "ls180.v:8956.3-8960.6" switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8953.7-8953.38" + attribute \src "ls180.v:8956.7-8956.38" case 1'1 assign $0\main_sdmem2block_converter_mux[2:0] 3'000 - attribute \src "ls180.v:8955.7-8955.11" + attribute \src "ls180.v:8958.7-8958.11" case - assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8956$2872_Y + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8959$2872_Y end case end - attribute \src "ls180.v:8959.2-8961.5" - switch $and$ls180.v:8959$2875_Y - attribute \src "ls180.v:8959.6-8959.120" + attribute \src "ls180.v:8962.2-8964.5" + switch $and$ls180.v:8962$2875_Y + attribute \src "ls180.v:8962.6-8962.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8960$2876_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8963$2876_Y case end - attribute \src "ls180.v:8962.2-8964.5" + attribute \src "ls180.v:8965.2-8967.5" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8962.6-8962.35" + attribute \src "ls180.v:8965.6-8965.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8963$2877_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8966$2877_Y case end - attribute \src "ls180.v:8965.2-8973.5" - switch $and$ls180.v:8965$2880_Y - attribute \src "ls180.v:8965.6-8965.120" + attribute \src "ls180.v:8968.2-8976.5" + switch $and$ls180.v:8968$2880_Y + attribute \src "ls180.v:8968.6-8968.120" case 1'1 - attribute \src "ls180.v:8966.3-8968.6" - switch $not$ls180.v:8966$2881_Y - attribute \src "ls180.v:8966.7-8966.39" + attribute \src "ls180.v:8969.3-8971.6" + switch $not$ls180.v:8969$2881_Y + attribute \src "ls180.v:8969.7-8969.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8967$2882_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8970$2882_Y case end - attribute \src "ls180.v:8969.6-8969.10" + attribute \src "ls180.v:8972.6-8972.10" case - attribute \src "ls180.v:8970.3-8972.6" + attribute \src "ls180.v:8973.3-8975.6" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8970.7-8970.36" + attribute \src "ls180.v:8973.7-8973.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8971$2883_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8974$2883_Y case end end - attribute \src "ls180.v:8975.2-8977.5" + attribute \src "ls180.v:8978.2-8980.5" switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8975.6-8975.46" + attribute \src "ls180.v:8978.6-8978.46" case 1'1 assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 case end - attribute \src "ls180.v:8978.2-8980.5" + attribute \src "ls180.v:8981.2-8983.5" switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8978.6-8978.44" + attribute \src "ls180.v:8981.6-8981.44" case 1'1 assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 case end - attribute \src "ls180.v:8981.2-8983.5" + attribute \src "ls180.v:8984.2-8986.5" switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8981.6-8981.43" + attribute \src "ls180.v:8984.6-8984.43" case 1'1 assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 case end - attribute \src "ls180.v:8984.2-9080.9" + attribute \src "ls180.v:8987.2-9083.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - attribute \src "ls180.v:8986.4-9002.7" - switch $not$ls180.v:8986$2884_Y - attribute \src "ls180.v:8986.8-8986.29" + attribute \src "ls180.v:8989.4-9005.7" + switch $not$ls180.v:8989$2884_Y + attribute \src "ls180.v:8989.8-8989.29" case 1'1 - attribute \src "ls180.v:8987.5-9001.8" + attribute \src "ls180.v:8990.5-9004.8" switch \builder_request [1] - attribute \src "ls180.v:8987.9-8987.27" + attribute \src "ls180.v:8990.9-8990.27" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8989.9-8989.13" + attribute \src "ls180.v:8992.9-8992.13" case - attribute \src "ls180.v:8990.6-9000.9" + attribute \src "ls180.v:8993.6-9003.9" switch \builder_request [2] - attribute \src "ls180.v:8990.10-8990.28" + attribute \src "ls180.v:8993.10-8993.28" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8992.10-8992.14" + attribute \src "ls180.v:8995.10-8995.14" case - attribute \src "ls180.v:8993.7-8999.10" + attribute \src "ls180.v:8996.7-9002.10" switch \builder_request [3] - attribute \src "ls180.v:8993.11-8993.29" + attribute \src "ls180.v:8996.11-8996.29" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8995.11-8995.15" + attribute \src "ls180.v:8998.11-8998.15" case - attribute \src "ls180.v:8996.8-8998.11" + attribute \src "ls180.v:8999.8-9001.11" switch \builder_request [4] - attribute \src "ls180.v:8996.12-8996.30" + attribute \src "ls180.v:8999.12-8999.30" case 1'1 assign $0\builder_grant[2:0] 3'100 case @@ -295628,34 +298137,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'001 - attribute \src "ls180.v:9005.4-9021.7" - switch $not$ls180.v:9005$2885_Y - attribute \src "ls180.v:9005.8-9005.29" + attribute \src "ls180.v:9008.4-9024.7" + switch $not$ls180.v:9008$2885_Y + attribute \src "ls180.v:9008.8-9008.29" case 1'1 - attribute \src "ls180.v:9006.5-9020.8" + attribute \src "ls180.v:9009.5-9023.8" switch \builder_request [2] - attribute \src "ls180.v:9006.9-9006.27" + attribute \src "ls180.v:9009.9-9009.27" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:9008.9-9008.13" + attribute \src "ls180.v:9011.9-9011.13" case - attribute \src "ls180.v:9009.6-9019.9" + attribute \src "ls180.v:9012.6-9022.9" switch \builder_request [3] - attribute \src "ls180.v:9009.10-9009.28" + attribute \src "ls180.v:9012.10-9012.28" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:9011.10-9011.14" + attribute \src "ls180.v:9014.10-9014.14" case - attribute \src "ls180.v:9012.7-9018.10" + attribute \src "ls180.v:9015.7-9021.10" switch \builder_request [4] - attribute \src "ls180.v:9012.11-9012.29" + attribute \src "ls180.v:9015.11-9015.29" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9014.11-9014.15" + attribute \src "ls180.v:9017.11-9017.15" case - attribute \src "ls180.v:9015.8-9017.11" + attribute \src "ls180.v:9018.8-9020.11" switch \builder_request [0] - attribute \src "ls180.v:9015.12-9015.30" + attribute \src "ls180.v:9018.12-9018.30" case 1'1 assign $0\builder_grant[2:0] 3'000 case @@ -295667,34 +298176,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'010 - attribute \src "ls180.v:9024.4-9040.7" - switch $not$ls180.v:9024$2886_Y - attribute \src "ls180.v:9024.8-9024.29" + attribute \src "ls180.v:9027.4-9043.7" + switch $not$ls180.v:9027$2886_Y + attribute \src "ls180.v:9027.8-9027.29" case 1'1 - attribute \src "ls180.v:9025.5-9039.8" + attribute \src "ls180.v:9028.5-9042.8" switch \builder_request [3] - attribute \src "ls180.v:9025.9-9025.27" + attribute \src "ls180.v:9028.9-9028.27" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:9027.9-9027.13" + attribute \src "ls180.v:9030.9-9030.13" case - attribute \src "ls180.v:9028.6-9038.9" + attribute \src "ls180.v:9031.6-9041.9" switch \builder_request [4] - attribute \src "ls180.v:9028.10-9028.28" + attribute \src "ls180.v:9031.10-9031.28" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9030.10-9030.14" + attribute \src "ls180.v:9033.10-9033.14" case - attribute \src "ls180.v:9031.7-9037.10" + attribute \src "ls180.v:9034.7-9040.10" switch \builder_request [0] - attribute \src "ls180.v:9031.11-9031.29" + attribute \src "ls180.v:9034.11-9034.29" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9033.11-9033.15" + attribute \src "ls180.v:9036.11-9036.15" case - attribute \src "ls180.v:9034.8-9036.11" + attribute \src "ls180.v:9037.8-9039.11" switch \builder_request [1] - attribute \src "ls180.v:9034.12-9034.30" + attribute \src "ls180.v:9037.12-9037.30" case 1'1 assign $0\builder_grant[2:0] 3'001 case @@ -295706,34 +298215,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:9043.4-9059.7" - switch $not$ls180.v:9043$2887_Y - attribute \src "ls180.v:9043.8-9043.29" + attribute \src "ls180.v:9046.4-9062.7" + switch $not$ls180.v:9046$2887_Y + attribute \src "ls180.v:9046.8-9046.29" case 1'1 - attribute \src "ls180.v:9044.5-9058.8" + attribute \src "ls180.v:9047.5-9061.8" switch \builder_request [4] - attribute \src "ls180.v:9044.9-9044.27" + attribute \src "ls180.v:9047.9-9047.27" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9046.9-9046.13" + attribute \src "ls180.v:9049.9-9049.13" case - attribute \src "ls180.v:9047.6-9057.9" + attribute \src "ls180.v:9050.6-9060.9" switch \builder_request [0] - attribute \src "ls180.v:9047.10-9047.28" + attribute \src "ls180.v:9050.10-9050.28" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9049.10-9049.14" + attribute \src "ls180.v:9052.10-9052.14" case - attribute \src "ls180.v:9050.7-9056.10" + attribute \src "ls180.v:9053.7-9059.10" switch \builder_request [1] - attribute \src "ls180.v:9050.11-9050.29" + attribute \src "ls180.v:9053.11-9053.29" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:9052.11-9052.15" + attribute \src "ls180.v:9055.11-9055.15" case - attribute \src "ls180.v:9053.8-9055.11" + attribute \src "ls180.v:9056.8-9058.11" switch \builder_request [2] - attribute \src "ls180.v:9053.12-9053.30" + attribute \src "ls180.v:9056.12-9056.30" case 1'1 assign $0\builder_grant[2:0] 3'010 case @@ -295745,34 +298254,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'100 - attribute \src "ls180.v:9062.4-9078.7" - switch $not$ls180.v:9062$2888_Y - attribute \src "ls180.v:9062.8-9062.29" + attribute \src "ls180.v:9065.4-9081.7" + switch $not$ls180.v:9065$2888_Y + attribute \src "ls180.v:9065.8-9065.29" case 1'1 - attribute \src "ls180.v:9063.5-9077.8" + attribute \src "ls180.v:9066.5-9080.8" switch \builder_request [0] - attribute \src "ls180.v:9063.9-9063.27" + attribute \src "ls180.v:9066.9-9066.27" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9065.9-9065.13" + attribute \src "ls180.v:9068.9-9068.13" case - attribute \src "ls180.v:9066.6-9076.9" + attribute \src "ls180.v:9069.6-9079.9" switch \builder_request [1] - attribute \src "ls180.v:9066.10-9066.28" + attribute \src "ls180.v:9069.10-9069.28" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:9068.10-9068.14" + attribute \src "ls180.v:9071.10-9071.14" case - attribute \src "ls180.v:9069.7-9075.10" + attribute \src "ls180.v:9072.7-9078.10" switch \builder_request [2] - attribute \src "ls180.v:9069.11-9069.29" + attribute \src "ls180.v:9072.11-9072.29" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:9071.11-9071.15" + attribute \src "ls180.v:9074.11-9074.15" case - attribute \src "ls180.v:9072.8-9074.11" + attribute \src "ls180.v:9075.8-9077.11" switch \builder_request [3] - attribute \src "ls180.v:9072.12-9072.30" + attribute \src "ls180.v:9075.12-9075.30" case 1'1 assign $0\builder_grant[2:0] 3'011 case @@ -295784,26 +298293,26 @@ module \ls180 end case end - attribute \src "ls180.v:9082.2-9088.5" + attribute \src "ls180.v:9085.2-9091.5" switch \builder_wait - attribute \src "ls180.v:9082.6-9082.18" + attribute \src "ls180.v:9085.6-9085.18" case 1'1 - attribute \src "ls180.v:9083.3-9085.6" - switch $not$ls180.v:9083$2889_Y - attribute \src "ls180.v:9083.7-9083.22" + attribute \src "ls180.v:9086.3-9088.6" + switch $not$ls180.v:9086$2889_Y + attribute \src "ls180.v:9086.7-9086.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:9084$2890_Y + assign $0\builder_count[19:0] $sub$ls180.v:9087$2890_Y case end - attribute \src "ls180.v:9086.6-9086.10" + attribute \src "ls180.v:9089.6-9089.10" case assign $0\builder_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:9090.2-9120.5" + attribute \src "ls180.v:9093.2-9123.5" switch \builder_csrbank0_sel - attribute \src "ls180.v:9090.6-9090.26" + attribute \src "ls180.v:9093.6-9093.26" case 1'1 - attribute \src "ls180.v:9091.3-9119.10" + attribute \src "ls180.v:9094.3-9122.10" switch \builder_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -295836,46 +298345,46 @@ module \ls180 end case end - attribute \src "ls180.v:9121.2-9123.5" + attribute \src "ls180.v:9124.2-9126.5" switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:9121.6-9121.32" + attribute \src "ls180.v:9124.6-9124.32" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r case end - attribute \src "ls180.v:9125.2-9127.5" + attribute \src "ls180.v:9128.2-9130.5" switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:9125.6-9125.34" + attribute \src "ls180.v:9128.6-9128.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r case end - attribute \src "ls180.v:9128.2-9130.5" + attribute \src "ls180.v:9131.2-9133.5" switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:9128.6-9128.34" + attribute \src "ls180.v:9131.6-9131.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r case end - attribute \src "ls180.v:9131.2-9133.5" + attribute \src "ls180.v:9134.2-9136.5" switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:9131.6-9131.34" + attribute \src "ls180.v:9134.6-9134.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r case end - attribute \src "ls180.v:9134.2-9136.5" + attribute \src "ls180.v:9137.2-9139.5" switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:9134.6-9134.34" + attribute \src "ls180.v:9137.6-9137.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r case end - attribute \src "ls180.v:9139.2-9160.5" + attribute \src "ls180.v:9142.2-9163.5" switch \builder_csrbank1_sel - attribute \src "ls180.v:9139.6-9139.26" + attribute \src "ls180.v:9142.6-9142.26" case 1'1 - attribute \src "ls180.v:9140.3-9159.10" + attribute \src "ls180.v:9143.3-9162.10" switch \builder_interface1_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -295899,39 +298408,39 @@ module \ls180 end case end - attribute \src "ls180.v:9161.2-9163.5" + attribute \src "ls180.v:9164.2-9166.5" switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:9161.6-9161.29" + attribute \src "ls180.v:9164.6-9164.29" case 1'1 assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r case end - attribute \src "ls180.v:9164.2-9166.5" + attribute \src "ls180.v:9167.2-9169.5" switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:9164.6-9164.29" + attribute \src "ls180.v:9167.6-9167.29" case 1'1 assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r case end - attribute \src "ls180.v:9168.2-9170.5" + attribute \src "ls180.v:9171.2-9173.5" switch \builder_csrbank1_out1_re - attribute \src "ls180.v:9168.6-9168.30" + attribute \src "ls180.v:9171.6-9171.30" case 1'1 assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r case end - attribute \src "ls180.v:9171.2-9173.5" + attribute \src "ls180.v:9174.2-9176.5" switch \builder_csrbank1_out0_re - attribute \src "ls180.v:9171.6-9171.30" + attribute \src "ls180.v:9174.6-9174.30" case 1'1 assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r case end - attribute \src "ls180.v:9176.2-9185.5" + attribute \src "ls180.v:9179.2-9188.5" switch \builder_csrbank2_sel - attribute \src "ls180.v:9176.6-9176.26" + attribute \src "ls180.v:9179.6-9179.26" case 1'1 - attribute \src "ls180.v:9177.3-9184.10" + attribute \src "ls180.v:9180.3-9187.10" switch \builder_interface2_bank_bus_adr [0] attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -295943,18 +298452,18 @@ module \ls180 end case end - attribute \src "ls180.v:9186.2-9188.5" + attribute \src "ls180.v:9189.2-9191.5" switch \builder_csrbank2_w0_re - attribute \src "ls180.v:9186.6-9186.28" + attribute \src "ls180.v:9189.6-9189.28" case 1'1 assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r case end - attribute \src "ls180.v:9191.2-9221.5" + attribute \src "ls180.v:9194.2-9224.5" switch \builder_csrbank3_sel - attribute \src "ls180.v:9191.6-9191.26" + attribute \src "ls180.v:9194.6-9194.26" case 1'1 - attribute \src "ls180.v:9192.3-9220.10" + attribute \src "ls180.v:9195.3-9223.10" switch \builder_interface3_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -295987,74 +298496,74 @@ module \ls180 end case end - attribute \src "ls180.v:9222.2-9224.5" + attribute \src "ls180.v:9225.2-9227.5" switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:9222.6-9222.33" + attribute \src "ls180.v:9225.6-9225.33" case 1'1 assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r case end - attribute \src "ls180.v:9226.2-9228.5" + attribute \src "ls180.v:9229.2-9231.5" switch \builder_csrbank3_width3_re - attribute \src "ls180.v:9226.6-9226.32" + attribute \src "ls180.v:9229.6-9229.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r case end - attribute \src "ls180.v:9229.2-9231.5" + attribute \src "ls180.v:9232.2-9234.5" switch \builder_csrbank3_width2_re - attribute \src "ls180.v:9229.6-9229.32" + attribute \src "ls180.v:9232.6-9232.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r case end - attribute \src "ls180.v:9232.2-9234.5" + attribute \src "ls180.v:9235.2-9237.5" switch \builder_csrbank3_width1_re - attribute \src "ls180.v:9232.6-9232.32" + attribute \src "ls180.v:9235.6-9235.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r case end - attribute \src "ls180.v:9235.2-9237.5" + attribute \src "ls180.v:9238.2-9240.5" switch \builder_csrbank3_width0_re - attribute \src "ls180.v:9235.6-9235.32" + attribute \src "ls180.v:9238.6-9238.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r case end - attribute \src "ls180.v:9239.2-9241.5" + attribute \src "ls180.v:9242.2-9244.5" switch \builder_csrbank3_period3_re - attribute \src "ls180.v:9239.6-9239.33" + attribute \src "ls180.v:9242.6-9242.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r case end - attribute \src "ls180.v:9242.2-9244.5" + attribute \src "ls180.v:9245.2-9247.5" switch \builder_csrbank3_period2_re - attribute \src "ls180.v:9242.6-9242.33" + attribute \src "ls180.v:9245.6-9245.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r case end - attribute \src "ls180.v:9245.2-9247.5" + attribute \src "ls180.v:9248.2-9250.5" switch \builder_csrbank3_period1_re - attribute \src "ls180.v:9245.6-9245.33" + attribute \src "ls180.v:9248.6-9248.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r case end - attribute \src "ls180.v:9248.2-9250.5" + attribute \src "ls180.v:9251.2-9253.5" switch \builder_csrbank3_period0_re - attribute \src "ls180.v:9248.6-9248.33" + attribute \src "ls180.v:9251.6-9251.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r case end - attribute \src "ls180.v:9253.2-9283.5" + attribute \src "ls180.v:9256.2-9286.5" switch \builder_csrbank4_sel - attribute \src "ls180.v:9253.6-9253.26" + attribute \src "ls180.v:9256.6-9256.26" case 1'1 - attribute \src "ls180.v:9254.3-9282.10" + attribute \src "ls180.v:9257.3-9285.10" switch \builder_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -296087,74 +298596,74 @@ module \ls180 end case end - attribute \src "ls180.v:9284.2-9286.5" + attribute \src "ls180.v:9287.2-9289.5" switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:9284.6-9284.33" + attribute \src "ls180.v:9287.6-9287.33" case 1'1 assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r case end - attribute \src "ls180.v:9288.2-9290.5" + attribute \src "ls180.v:9291.2-9293.5" switch \builder_csrbank4_width3_re - attribute \src "ls180.v:9288.6-9288.32" + attribute \src "ls180.v:9291.6-9291.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r case end - attribute \src "ls180.v:9291.2-9293.5" + attribute \src "ls180.v:9294.2-9296.5" switch \builder_csrbank4_width2_re - attribute \src "ls180.v:9291.6-9291.32" + attribute \src "ls180.v:9294.6-9294.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r case end - attribute \src "ls180.v:9294.2-9296.5" + attribute \src "ls180.v:9297.2-9299.5" switch \builder_csrbank4_width1_re - attribute \src "ls180.v:9294.6-9294.32" + attribute \src "ls180.v:9297.6-9297.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r case end - attribute \src "ls180.v:9297.2-9299.5" + attribute \src "ls180.v:9300.2-9302.5" switch \builder_csrbank4_width0_re - attribute \src "ls180.v:9297.6-9297.32" + attribute \src "ls180.v:9300.6-9300.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r case end - attribute \src "ls180.v:9301.2-9303.5" + attribute \src "ls180.v:9304.2-9306.5" switch \builder_csrbank4_period3_re - attribute \src "ls180.v:9301.6-9301.33" + attribute \src "ls180.v:9304.6-9304.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r case end - attribute \src "ls180.v:9304.2-9306.5" + attribute \src "ls180.v:9307.2-9309.5" switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9304.6-9304.33" + attribute \src "ls180.v:9307.6-9307.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r case end - attribute \src "ls180.v:9307.2-9309.5" + attribute \src "ls180.v:9310.2-9312.5" switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9307.6-9307.33" + attribute \src "ls180.v:9310.6-9310.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r case end - attribute \src "ls180.v:9310.2-9312.5" + attribute \src "ls180.v:9313.2-9315.5" switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9310.6-9310.33" + attribute \src "ls180.v:9313.6-9313.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r case end - attribute \src "ls180.v:9315.2-9363.5" + attribute \src "ls180.v:9318.2-9366.5" switch \builder_csrbank5_sel - attribute \src "ls180.v:9315.6-9315.26" + attribute \src "ls180.v:9318.6-9318.26" case 1'1 - attribute \src "ls180.v:9316.3-9362.10" + attribute \src "ls180.v:9319.3-9365.10" switch \builder_interface5_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -296205,109 +298714,109 @@ module \ls180 end case end - attribute \src "ls180.v:9364.2-9366.5" + attribute \src "ls180.v:9367.2-9369.5" switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9364.6-9364.35" + attribute \src "ls180.v:9367.6-9367.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r case end - attribute \src "ls180.v:9367.2-9369.5" + attribute \src "ls180.v:9370.2-9372.5" switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9367.6-9367.35" + attribute \src "ls180.v:9370.6-9370.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r case end - attribute \src "ls180.v:9370.2-9372.5" + attribute \src "ls180.v:9373.2-9375.5" switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9370.6-9370.35" + attribute \src "ls180.v:9373.6-9373.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r case end - attribute \src "ls180.v:9373.2-9375.5" + attribute \src "ls180.v:9376.2-9378.5" switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9373.6-9373.35" + attribute \src "ls180.v:9376.6-9376.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r case end - attribute \src "ls180.v:9376.2-9378.5" + attribute \src "ls180.v:9379.2-9381.5" switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9376.6-9376.35" + attribute \src "ls180.v:9379.6-9379.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r case end - attribute \src "ls180.v:9379.2-9381.5" + attribute \src "ls180.v:9382.2-9384.5" switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9379.6-9379.35" + attribute \src "ls180.v:9382.6-9382.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r case end - attribute \src "ls180.v:9382.2-9384.5" + attribute \src "ls180.v:9385.2-9387.5" switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9382.6-9382.35" + attribute \src "ls180.v:9385.6-9385.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r case end - attribute \src "ls180.v:9385.2-9387.5" + attribute \src "ls180.v:9388.2-9390.5" switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9385.6-9385.35" + attribute \src "ls180.v:9388.6-9388.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r case end - attribute \src "ls180.v:9389.2-9391.5" + attribute \src "ls180.v:9392.2-9394.5" switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9389.6-9389.37" + attribute \src "ls180.v:9392.6-9392.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r case end - attribute \src "ls180.v:9392.2-9394.5" + attribute \src "ls180.v:9395.2-9397.5" switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9392.6-9392.37" + attribute \src "ls180.v:9395.6-9395.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r case end - attribute \src "ls180.v:9395.2-9397.5" + attribute \src "ls180.v:9398.2-9400.5" switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9395.6-9395.37" + attribute \src "ls180.v:9398.6-9398.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r case end - attribute \src "ls180.v:9398.2-9400.5" + attribute \src "ls180.v:9401.2-9403.5" switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9398.6-9398.37" + attribute \src "ls180.v:9401.6-9401.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r case end - attribute \src "ls180.v:9402.2-9404.5" + attribute \src "ls180.v:9405.2-9407.5" switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9402.6-9402.37" + attribute \src "ls180.v:9405.6-9405.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r case end - attribute \src "ls180.v:9406.2-9408.5" + attribute \src "ls180.v:9409.2-9411.5" switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9406.6-9406.35" + attribute \src "ls180.v:9409.6-9409.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r case end - attribute \src "ls180.v:9411.2-9513.5" + attribute \src "ls180.v:9414.2-9516.5" switch \builder_csrbank6_sel - attribute \src "ls180.v:9411.6-9411.26" + attribute \src "ls180.v:9414.6-9414.26" case 1'1 - attribute \src "ls180.v:9412.3-9512.10" + attribute \src "ls180.v:9415.3-9515.10" switch \builder_interface6_bank_bus_adr [5:0] attribute \src "ls180.v:0.0-0.0" case 6'000000 @@ -296412,109 +298921,109 @@ module \ls180 end case end - attribute \src "ls180.v:9514.2-9516.5" + attribute \src "ls180.v:9517.2-9519.5" switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9514.6-9514.39" + attribute \src "ls180.v:9517.6-9517.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r case end - attribute \src "ls180.v:9517.2-9519.5" + attribute \src "ls180.v:9520.2-9522.5" switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9517.6-9517.39" + attribute \src "ls180.v:9520.6-9520.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r case end - attribute \src "ls180.v:9520.2-9522.5" + attribute \src "ls180.v:9523.2-9525.5" switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9520.6-9520.39" + attribute \src "ls180.v:9523.6-9523.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r case end - attribute \src "ls180.v:9523.2-9525.5" + attribute \src "ls180.v:9526.2-9528.5" switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9523.6-9523.39" + attribute \src "ls180.v:9526.6-9526.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r case end - attribute \src "ls180.v:9527.2-9529.5" + attribute \src "ls180.v:9530.2-9532.5" switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9527.6-9527.38" + attribute \src "ls180.v:9530.6-9530.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r case end - attribute \src "ls180.v:9530.2-9532.5" + attribute \src "ls180.v:9533.2-9535.5" switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9530.6-9530.38" + attribute \src "ls180.v:9533.6-9533.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r case end - attribute \src "ls180.v:9533.2-9535.5" + attribute \src "ls180.v:9536.2-9538.5" switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9533.6-9533.38" + attribute \src "ls180.v:9536.6-9536.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r case end - attribute \src "ls180.v:9536.2-9538.5" + attribute \src "ls180.v:9539.2-9541.5" switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9536.6-9536.38" + attribute \src "ls180.v:9539.6-9539.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r case end - attribute \src "ls180.v:9540.2-9542.5" + attribute \src "ls180.v:9543.2-9545.5" switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9540.6-9540.39" + attribute \src "ls180.v:9543.6-9543.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r case end - attribute \src "ls180.v:9543.2-9545.5" + attribute \src "ls180.v:9546.2-9548.5" switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9543.6-9543.39" + attribute \src "ls180.v:9546.6-9546.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r case end - attribute \src "ls180.v:9547.2-9549.5" + attribute \src "ls180.v:9550.2-9552.5" switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9547.6-9547.38" + attribute \src "ls180.v:9550.6-9550.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r case end - attribute \src "ls180.v:9550.2-9552.5" + attribute \src "ls180.v:9553.2-9555.5" switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9550.6-9550.38" + attribute \src "ls180.v:9553.6-9553.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r case end - attribute \src "ls180.v:9553.2-9555.5" + attribute \src "ls180.v:9556.2-9558.5" switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9553.6-9553.38" + attribute \src "ls180.v:9556.6-9556.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r case end - attribute \src "ls180.v:9556.2-9558.5" + attribute \src "ls180.v:9559.2-9561.5" switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9556.6-9556.38" + attribute \src "ls180.v:9559.6-9559.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r case end - attribute \src "ls180.v:9561.2-9621.5" + attribute \src "ls180.v:9564.2-9624.5" switch \builder_csrbank7_sel - attribute \src "ls180.v:9561.6-9561.26" + attribute \src "ls180.v:9564.6-9564.26" case 1'1 - attribute \src "ls180.v:9562.3-9620.10" + attribute \src "ls180.v:9565.3-9623.10" switch \builder_interface7_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -296577,109 +299086,109 @@ module \ls180 end case end - attribute \src "ls180.v:9622.2-9624.5" + attribute \src "ls180.v:9625.2-9627.5" switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9622.6-9622.35" + attribute \src "ls180.v:9625.6-9625.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r case end - attribute \src "ls180.v:9625.2-9627.5" + attribute \src "ls180.v:9628.2-9630.5" switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9625.6-9625.35" + attribute \src "ls180.v:9628.6-9628.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r case end - attribute \src "ls180.v:9628.2-9630.5" + attribute \src "ls180.v:9631.2-9633.5" switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9628.6-9628.35" + attribute \src "ls180.v:9631.6-9631.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r case end - attribute \src "ls180.v:9631.2-9633.5" + attribute \src "ls180.v:9634.2-9636.5" switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9631.6-9631.35" + attribute \src "ls180.v:9634.6-9634.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r case end - attribute \src "ls180.v:9634.2-9636.5" + attribute \src "ls180.v:9637.2-9639.5" switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9634.6-9634.35" + attribute \src "ls180.v:9637.6-9637.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r case end - attribute \src "ls180.v:9637.2-9639.5" + attribute \src "ls180.v:9640.2-9642.5" switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9637.6-9637.35" + attribute \src "ls180.v:9640.6-9640.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r case end - attribute \src "ls180.v:9640.2-9642.5" + attribute \src "ls180.v:9643.2-9645.5" switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9640.6-9640.35" + attribute \src "ls180.v:9643.6-9643.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r case end - attribute \src "ls180.v:9643.2-9645.5" + attribute \src "ls180.v:9646.2-9648.5" switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9643.6-9643.35" + attribute \src "ls180.v:9646.6-9646.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r case end - attribute \src "ls180.v:9647.2-9649.5" + attribute \src "ls180.v:9650.2-9652.5" switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9647.6-9647.37" + attribute \src "ls180.v:9650.6-9650.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r case end - attribute \src "ls180.v:9650.2-9652.5" + attribute \src "ls180.v:9653.2-9655.5" switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9650.6-9650.37" + attribute \src "ls180.v:9653.6-9653.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r case end - attribute \src "ls180.v:9653.2-9655.5" + attribute \src "ls180.v:9656.2-9658.5" switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9653.6-9653.37" + attribute \src "ls180.v:9656.6-9656.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r case end - attribute \src "ls180.v:9656.2-9658.5" + attribute \src "ls180.v:9659.2-9661.5" switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9656.6-9656.37" + attribute \src "ls180.v:9659.6-9659.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r case end - attribute \src "ls180.v:9660.2-9662.5" + attribute \src "ls180.v:9663.2-9665.5" switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9660.6-9660.37" + attribute \src "ls180.v:9663.6-9663.37" case 1'1 assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r case end - attribute \src "ls180.v:9664.2-9666.5" + attribute \src "ls180.v:9667.2-9669.5" switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9664.6-9664.35" + attribute \src "ls180.v:9667.6-9667.35" case 1'1 assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r case end - attribute \src "ls180.v:9669.2-9684.5" + attribute \src "ls180.v:9672.2-9687.5" switch \builder_csrbank8_sel - attribute \src "ls180.v:9669.6-9669.26" + attribute \src "ls180.v:9672.6-9672.26" case 1'1 - attribute \src "ls180.v:9670.3-9683.10" + attribute \src "ls180.v:9673.3-9686.10" switch \builder_interface8_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296697,25 +299206,25 @@ module \ls180 end case end - attribute \src "ls180.v:9685.2-9687.5" + attribute \src "ls180.v:9688.2-9690.5" switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9685.6-9685.42" + attribute \src "ls180.v:9688.6-9688.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r case end - attribute \src "ls180.v:9688.2-9690.5" + attribute \src "ls180.v:9691.2-9693.5" switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9688.6-9688.42" + attribute \src "ls180.v:9691.6-9691.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r case end - attribute \src "ls180.v:9693.2-9726.5" + attribute \src "ls180.v:9696.2-9729.5" switch \builder_csrbank9_sel - attribute \src "ls180.v:9693.6-9693.26" + attribute \src "ls180.v:9696.6-9696.26" case 1'1 - attribute \src "ls180.v:9694.3-9725.10" + attribute \src "ls180.v:9697.3-9728.10" switch \builder_interface9_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -296751,60 +299260,60 @@ module \ls180 end case end - attribute \src "ls180.v:9727.2-9729.5" + attribute \src "ls180.v:9730.2-9732.5" switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9727.6-9727.39" + attribute \src "ls180.v:9730.6-9730.39" case 1'1 assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r case end - attribute \src "ls180.v:9731.2-9733.5" + attribute \src "ls180.v:9734.2-9736.5" switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9731.6-9731.43" + attribute \src "ls180.v:9734.6-9734.43" case 1'1 assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r case end - attribute \src "ls180.v:9735.2-9737.5" + attribute \src "ls180.v:9738.2-9740.5" switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9735.6-9735.43" + attribute \src "ls180.v:9738.6-9738.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r case end - attribute \src "ls180.v:9738.2-9740.5" + attribute \src "ls180.v:9741.2-9743.5" switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9738.6-9738.43" + attribute \src "ls180.v:9741.6-9741.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r case end - attribute \src "ls180.v:9742.2-9744.5" + attribute \src "ls180.v:9745.2-9747.5" switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9742.6-9742.44" + attribute \src "ls180.v:9745.6-9745.44" case 1'1 assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9746.2-9748.5" + attribute \src "ls180.v:9749.2-9751.5" switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9746.6-9746.42" + attribute \src "ls180.v:9749.6-9749.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9749.2-9751.5" + attribute \src "ls180.v:9752.2-9754.5" switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9749.6-9749.42" + attribute \src "ls180.v:9752.6-9752.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9754.2-9778.5" + attribute \src "ls180.v:9757.2-9781.5" switch \builder_csrbank10_sel - attribute \src "ls180.v:9754.6-9754.27" + attribute \src "ls180.v:9757.6-9757.27" case 1'1 - attribute \src "ls180.v:9755.3-9777.10" + attribute \src "ls180.v:9758.3-9780.10" switch \builder_interface10_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -296831,46 +299340,46 @@ module \ls180 end case end - attribute \src "ls180.v:9779.2-9781.5" + attribute \src "ls180.v:9782.2-9784.5" switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9779.6-9779.35" + attribute \src "ls180.v:9782.6-9782.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r case end - attribute \src "ls180.v:9782.2-9784.5" + attribute \src "ls180.v:9785.2-9787.5" switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9782.6-9782.35" + attribute \src "ls180.v:9785.6-9785.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r case end - attribute \src "ls180.v:9786.2-9788.5" + attribute \src "ls180.v:9789.2-9791.5" switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9786.6-9786.32" + attribute \src "ls180.v:9789.6-9789.32" case 1'1 assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r case end - attribute \src "ls180.v:9790.2-9792.5" + attribute \src "ls180.v:9793.2-9795.5" switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9790.6-9790.30" + attribute \src "ls180.v:9793.6-9793.30" case 1'1 assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r case end - attribute \src "ls180.v:9794.2-9796.5" + attribute \src "ls180.v:9797.2-9799.5" switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9794.6-9794.36" + attribute \src "ls180.v:9797.6-9797.36" case 1'1 assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r case end - attribute \src "ls180.v:9799.2-9829.5" + attribute \src "ls180.v:9802.2-9832.5" switch \builder_csrbank11_sel - attribute \src "ls180.v:9799.6-9799.27" + attribute \src "ls180.v:9802.6-9802.27" case 1'1 - attribute \src "ls180.v:9800.3-9828.10" + attribute \src "ls180.v:9803.3-9831.10" switch \builder_interface11_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -296903,60 +299412,60 @@ module \ls180 end case end - attribute \src "ls180.v:9830.2-9832.5" + attribute \src "ls180.v:9833.2-9835.5" switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9830.6-9830.35" + attribute \src "ls180.v:9833.6-9833.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r case end - attribute \src "ls180.v:9833.2-9835.5" + attribute \src "ls180.v:9836.2-9838.5" switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9833.6-9833.35" + attribute \src "ls180.v:9836.6-9836.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r case end - attribute \src "ls180.v:9837.2-9839.5" + attribute \src "ls180.v:9840.2-9842.5" switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9837.6-9837.32" + attribute \src "ls180.v:9840.6-9840.32" case 1'1 assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r case end - attribute \src "ls180.v:9841.2-9843.5" + attribute \src "ls180.v:9844.2-9846.5" switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9841.6-9841.30" + attribute \src "ls180.v:9844.6-9844.30" case 1'1 assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r case end - attribute \src "ls180.v:9845.2-9847.5" + attribute \src "ls180.v:9848.2-9850.5" switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9845.6-9845.36" + attribute \src "ls180.v:9848.6-9848.36" case 1'1 assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r case end - attribute \src "ls180.v:9849.2-9851.5" + attribute \src "ls180.v:9852.2-9854.5" switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9849.6-9849.39" + attribute \src "ls180.v:9852.6-9852.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r case end - attribute \src "ls180.v:9852.2-9854.5" + attribute \src "ls180.v:9855.2-9857.5" switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9852.6-9852.39" + attribute \src "ls180.v:9855.6-9855.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r case end - attribute \src "ls180.v:9857.2-9911.5" + attribute \src "ls180.v:9860.2-9914.5" switch \builder_csrbank12_sel - attribute \src "ls180.v:9857.6-9857.27" + attribute \src "ls180.v:9860.6-9860.27" case 1'1 - attribute \src "ls180.v:9858.3-9910.10" + attribute \src "ls180.v:9861.3-9913.10" switch \builder_interface12_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -297013,88 +299522,88 @@ module \ls180 end case end - attribute \src "ls180.v:9912.2-9914.5" + attribute \src "ls180.v:9915.2-9917.5" switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9912.6-9912.32" + attribute \src "ls180.v:9915.6-9915.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r case end - attribute \src "ls180.v:9915.2-9917.5" + attribute \src "ls180.v:9918.2-9920.5" switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9915.6-9915.32" + attribute \src "ls180.v:9918.6-9918.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r case end - attribute \src "ls180.v:9918.2-9920.5" + attribute \src "ls180.v:9921.2-9923.5" switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9918.6-9918.32" + attribute \src "ls180.v:9921.6-9921.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r case end - attribute \src "ls180.v:9921.2-9923.5" + attribute \src "ls180.v:9924.2-9926.5" switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9921.6-9921.32" + attribute \src "ls180.v:9924.6-9924.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r case end - attribute \src "ls180.v:9925.2-9927.5" + attribute \src "ls180.v:9928.2-9930.5" switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9925.6-9925.34" + attribute \src "ls180.v:9928.6-9928.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r case end - attribute \src "ls180.v:9928.2-9930.5" + attribute \src "ls180.v:9931.2-9933.5" switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9928.6-9928.34" + attribute \src "ls180.v:9931.6-9931.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r case end - attribute \src "ls180.v:9931.2-9933.5" + attribute \src "ls180.v:9934.2-9936.5" switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9931.6-9931.34" + attribute \src "ls180.v:9934.6-9934.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r case end - attribute \src "ls180.v:9934.2-9936.5" + attribute \src "ls180.v:9937.2-9939.5" switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9934.6-9934.34" + attribute \src "ls180.v:9937.6-9937.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r case end - attribute \src "ls180.v:9938.2-9940.5" + attribute \src "ls180.v:9941.2-9943.5" switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9938.6-9938.30" + attribute \src "ls180.v:9941.6-9941.30" case 1'1 assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r case end - attribute \src "ls180.v:9942.2-9944.5" + attribute \src "ls180.v:9945.2-9947.5" switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9942.6-9942.40" + attribute \src "ls180.v:9945.6-9945.40" case 1'1 assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r case end - attribute \src "ls180.v:9946.2-9948.5" + attribute \src "ls180.v:9949.2-9951.5" switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9946.6-9946.37" + attribute \src "ls180.v:9949.6-9949.37" case 1'1 assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r case end - attribute \src "ls180.v:9951.2-9978.5" + attribute \src "ls180.v:9954.2-9981.5" switch \builder_csrbank13_sel - attribute \src "ls180.v:9951.6-9951.27" + attribute \src "ls180.v:9954.6-9954.27" case 1'1 - attribute \src "ls180.v:9952.3-9977.10" + attribute \src "ls180.v:9955.3-9980.10" switch \builder_interface13_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -297124,18 +299633,18 @@ module \ls180 end case end - attribute \src "ls180.v:9979.2-9981.5" + attribute \src "ls180.v:9982.2-9984.5" switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9979.6-9979.37" + attribute \src "ls180.v:9982.6-9982.37" case 1'1 assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r case end - attribute \src "ls180.v:9984.2-9999.5" + attribute \src "ls180.v:9987.2-10002.5" switch \builder_csrbank14_sel - attribute \src "ls180.v:9984.6-9984.27" + attribute \src "ls180.v:9987.6-9987.27" case 1'1 - attribute \src "ls180.v:9985.3-9998.10" + attribute \src "ls180.v:9988.3-10001.10" switch \builder_interface14_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -297153,37 +299662,37 @@ module \ls180 end case end - attribute \src "ls180.v:10000.2-10002.5" + attribute \src "ls180.v:10003.2-10005.5" switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:10000.6-10000.39" + attribute \src "ls180.v:10003.6-10003.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r case end - attribute \src "ls180.v:10003.2-10005.5" + attribute \src "ls180.v:10006.2-10008.5" switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:10003.6-10003.39" + attribute \src "ls180.v:10006.6-10006.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r case end - attribute \src "ls180.v:10006.2-10008.5" + attribute \src "ls180.v:10009.2-10011.5" switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:10006.6-10006.39" + attribute \src "ls180.v:10009.6-10009.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r case end - attribute \src "ls180.v:10009.2-10011.5" + attribute \src "ls180.v:10012.2-10014.5" switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:10009.6-10009.39" + attribute \src "ls180.v:10012.6-10012.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r case end - attribute \src "ls180.v:10013.2-10311.5" + attribute \src "ls180.v:10016.2-10314.5" switch \sys_rst_1 - attribute \src "ls180.v:10013.6-10013.15" + attribute \src "ls180.v:10016.6-10016.15" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] 1'0 assign $0\main_libresocsim_reset_re[0:0] 1'0 @@ -297902,262 +300411,254 @@ module \ls180 update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:781.11-781.68" - process $proc$ls180.v:781$3381 + attribute \src "ls180.v:784.11-784.68" + process $proc$ls180.v:784$3379 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:782.5-782.64" - process $proc$ls180.v:782$3382 + attribute \src "ls180.v:785.5-785.64" + process $proc$ls180.v:785$3380 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:783.11-783.70" - process $proc$ls180.v:783$3383 + attribute \src "ls180.v:786.11-786.70" + process $proc$ls180.v:786$3381 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:784.11-784.70" - process $proc$ls180.v:784$3384 + attribute \src "ls180.v:787.11-787.70" + process $proc$ls180.v:787$3382 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:785.11-785.73" - process $proc$ls180.v:785$3385 + attribute \src "ls180.v:788.11-788.73" + process $proc$ls180.v:788$3383 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:806.5-806.59" - process $proc$ls180.v:806$3386 + attribute \src "ls180.v:809.5-809.59" + process $proc$ls180.v:809$3384 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:808.5-808.59" - process $proc$ls180.v:808$3387 + attribute \src "ls180.v:811.5-811.59" + process $proc$ls180.v:811$3385 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:809.5-809.58" - process $proc$ls180.v:809$3388 + attribute \src "ls180.v:812.5-812.58" + process $proc$ls180.v:812$3386 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:810.5-810.64" - process $proc$ls180.v:810$3389 + attribute \src "ls180.v:813.5-813.64" + process $proc$ls180.v:813$3387 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:811.12-811.74" - process $proc$ls180.v:811$3390 + attribute \src "ls180.v:814.12-814.74" + process $proc$ls180.v:814$3388 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:812.12-812.47" - process $proc$ls180.v:812$3391 + attribute \src "ls180.v:815.12-815.47" + process $proc$ls180.v:815$3389 assign { } { } assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "ls180.v:813.5-813.46" - process $proc$ls180.v:813$3392 + attribute \src "ls180.v:816.5-816.46" + process $proc$ls180.v:816$3390 assign { } { } assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end - attribute \src "ls180.v:815.5-815.44" - process $proc$ls180.v:815$3393 + attribute \src "ls180.v:818.5-818.44" + process $proc$ls180.v:818$3391 assign { } { } assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end - attribute \src "ls180.v:816.5-816.45" - process $proc$ls180.v:816$3394 + attribute \src "ls180.v:819.5-819.45" + process $proc$ls180.v:819$3392 assign { } { } assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end - attribute \src "ls180.v:817.5-817.54" - process $proc$ls180.v:817$3395 + attribute \src "ls180.v:820.5-820.54" + process $proc$ls180.v:820$3393 assign { } { } assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:819.32-819.76" - process $proc$ls180.v:819$3396 + attribute \src "ls180.v:822.32-822.76" + process $proc$ls180.v:822$3394 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "ls180.v:820.11-820.55" - process $proc$ls180.v:820$3397 + attribute \src "ls180.v:823.11-823.55" + process $proc$ls180.v:823$3395 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 sync always sync init update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end - attribute \src "ls180.v:822.32-822.75" - process $proc$ls180.v:822$3398 + attribute \src "ls180.v:825.32-825.75" + process $proc$ls180.v:825$3396 assign { } { } assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] sync init end - attribute \src "ls180.v:824.32-824.76" - process $proc$ls180.v:824$3399 + attribute \src "ls180.v:827.32-827.76" + process $proc$ls180.v:827$3397 assign { } { } assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] sync init end - attribute \src "ls180.v:827.5-827.44" - process $proc$ls180.v:827$3400 + attribute \src "ls180.v:830.5-830.44" + process $proc$ls180.v:830$3398 assign { } { } assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] sync init end - attribute \src "ls180.v:828.5-828.45" - process $proc$ls180.v:828$3401 + attribute \src "ls180.v:831.5-831.45" + process $proc$ls180.v:831$3399 assign { } { } assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] sync init end - attribute \src "ls180.v:829.5-829.43" - process $proc$ls180.v:829$3402 + attribute \src "ls180.v:832.5-832.43" + process $proc$ls180.v:832$3400 assign { } { } assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init end - attribute \src "ls180.v:830.5-830.48" - process $proc$ls180.v:830$3403 + attribute \src "ls180.v:833.5-833.48" + process $proc$ls180.v:833$3401 assign { } { } assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] sync init end - attribute \src "ls180.v:832.5-832.43" - process $proc$ls180.v:832$3404 + attribute \src "ls180.v:835.5-835.43" + process $proc$ls180.v:835$3402 assign { } { } assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] sync init end - attribute \src "ls180.v:835.5-835.49" - process $proc$ls180.v:835$3405 + attribute \src "ls180.v:838.5-838.49" + process $proc$ls180.v:838$3403 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:836.5-836.49" - process $proc$ls180.v:836$3406 + attribute \src "ls180.v:839.5-839.49" + process $proc$ls180.v:839$3404 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:837.5-837.48" - process $proc$ls180.v:837$3407 + attribute \src "ls180.v:840.5-840.48" + process $proc$ls180.v:840$3405 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:841.11-841.46" - process $proc$ls180.v:841$3408 + attribute \src "ls180.v:844.11-844.46" + process $proc$ls180.v:844$3406 assign { } { } assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:843.11-843.45" - process $proc$ls180.v:843$3409 + attribute \src "ls180.v:846.11-846.45" + process $proc$ls180.v:846$3407 assign { } { } assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end - attribute \src "ls180.v:845.5-845.44" - process $proc$ls180.v:845$3410 + attribute \src "ls180.v:848.5-848.44" + process $proc$ls180.v:848$3408 assign { } { } assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \src "ls180.v:846.5-846.45" - process $proc$ls180.v:846$3411 + attribute \src "ls180.v:849.5-849.45" + process $proc$ls180.v:849$3409 assign { } { } assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \src "ls180.v:848.5-848.48" - process $proc$ls180.v:848$3412 - assign { } { } - assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] - end attribute \src "ls180.v:85.11-85.52" process $proc$ls180.v:85$3134 assign { } { } @@ -298166,46 +300667,46 @@ module \ls180 update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] sync init end - attribute \src "ls180.v:850.5-850.43" - process $proc$ls180.v:850$3413 + attribute \src "ls180.v:851.5-851.48" + process $proc$ls180.v:851$3410 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:853.5-853.43" + process $proc$ls180.v:853$3411 assign { } { } assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \src "ls180.v:853.5-853.49" - process $proc$ls180.v:853$3414 + attribute \src "ls180.v:856.5-856.49" + process $proc$ls180.v:856$3412 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:854.5-854.49" - process $proc$ls180.v:854$3415 + attribute \src "ls180.v:857.5-857.49" + process $proc$ls180.v:857$3413 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:855.5-855.48" - process $proc$ls180.v:855$3416 + attribute \src "ls180.v:858.5-858.48" + process $proc$ls180.v:858$3414 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:859.11-859.46" - process $proc$ls180.v:859$3417 - assign { } { } - assign $1\main_sdram_choose_req_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] - end attribute \src "ls180.v:86.11-86.52" process $proc$ls180.v:86$3135 assign { } { } @@ -298214,102 +300715,102 @@ module \ls180 update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] sync init end - attribute \src "ls180.v:861.11-861.45" - process $proc$ls180.v:861$3418 + attribute \src "ls180.v:862.11-862.46" + process $proc$ls180.v:862$3415 + assign { } { } + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:864.11-864.45" + process $proc$ls180.v:864$3416 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "ls180.v:863.12-863.36" - process $proc$ls180.v:863$3419 + attribute \src "ls180.v:866.12-866.36" + process $proc$ls180.v:866$3417 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init end - attribute \src "ls180.v:864.11-864.35" - process $proc$ls180.v:864$3420 + attribute \src "ls180.v:867.11-867.35" + process $proc$ls180.v:867$3418 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init end - attribute \src "ls180.v:865.11-865.40" - process $proc$ls180.v:865$3421 + attribute \src "ls180.v:868.11-868.40" + process $proc$ls180.v:868$3419 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "ls180.v:866.5-866.31" - process $proc$ls180.v:866$3422 + attribute \src "ls180.v:869.5-869.31" + process $proc$ls180.v:869$3420 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init end - attribute \src "ls180.v:867.5-867.31" - process $proc$ls180.v:867$3423 + attribute \src "ls180.v:870.5-870.31" + process $proc$ls180.v:870$3421 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init end - attribute \src "ls180.v:869.32-869.63" - process $proc$ls180.v:869$3424 + attribute \src "ls180.v:872.32-872.63" + process $proc$ls180.v:872$3422 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init end - attribute \src "ls180.v:871.32-871.63" - process $proc$ls180.v:871$3425 + attribute \src "ls180.v:874.32-874.63" + process $proc$ls180.v:874$3423 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init end - attribute \src "ls180.v:873.32-873.63" - process $proc$ls180.v:873$3426 + attribute \src "ls180.v:876.32-876.63" + process $proc$ls180.v:876$3424 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "ls180.v:874.5-874.36" - process $proc$ls180.v:874$3427 + attribute \src "ls180.v:877.5-877.36" + process $proc$ls180.v:877$3425 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "ls180.v:876.32-876.63" - process $proc$ls180.v:876$3428 + attribute \src "ls180.v:879.32-879.63" + process $proc$ls180.v:879$3426 assign { } { } assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always sync init update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:877.11-877.42" - process $proc$ls180.v:877$3429 - assign { } { } - assign $1\main_sdram_twtrcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] - end attribute \src "ls180.v:88.12-88.58" process $proc$ls180.v:88$3136 assign { } { } @@ -298318,32 +300819,40 @@ module \ls180 sync init update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] end - attribute \src "ls180.v:880.5-880.26" - process $proc$ls180.v:880$3430 + attribute \src "ls180.v:880.11-880.42" + process $proc$ls180.v:880$3427 + assign { } { } + assign $1\main_sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + end + attribute \src "ls180.v:883.5-883.26" + process $proc$ls180.v:883$3428 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always sync init update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "ls180.v:882.11-882.34" - process $proc$ls180.v:882$3431 + attribute \src "ls180.v:885.11-885.34" + process $proc$ls180.v:885$3429 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "ls180.v:883.5-883.26" - process $proc$ls180.v:883$3432 + attribute \src "ls180.v:886.5-886.26" + process $proc$ls180.v:886$3430 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always sync init update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "ls180.v:885.11-885.34" - process $proc$ls180.v:885$3433 + attribute \src "ls180.v:888.11-888.34" + process $proc$ls180.v:888$3431 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always @@ -298358,62 +300867,54 @@ module \ls180 sync init update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:900.12-900.37" - process $proc$ls180.v:900$3434 + attribute \src "ls180.v:903.12-903.37" + process $proc$ls180.v:903$3432 assign { } { } assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] end - attribute \src "ls180.v:901.12-901.39" - process $proc$ls180.v:901$3435 + attribute \src "ls180.v:904.12-904.39" + process $proc$ls180.v:904$3433 assign { } { } assign $1\main_wb_sdram_dat_w[31:0] 0 sync always sync init update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] end - attribute \src "ls180.v:903.11-903.35" - process $proc$ls180.v:903$3436 + attribute \src "ls180.v:906.11-906.35" + process $proc$ls180.v:906$3434 assign { } { } assign $1\main_wb_sdram_sel[3:0] 4'0000 sync always sync init update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] end - attribute \src "ls180.v:904.5-904.29" - process $proc$ls180.v:904$3437 + attribute \src "ls180.v:907.5-907.29" + process $proc$ls180.v:907$3435 assign { } { } assign $1\main_wb_sdram_cyc[0:0] 1'0 sync always sync init update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] end - attribute \src "ls180.v:905.5-905.29" - process $proc$ls180.v:905$3438 + attribute \src "ls180.v:908.5-908.29" + process $proc$ls180.v:908$3436 assign { } { } assign $1\main_wb_sdram_stb[0:0] 1'0 sync always sync init update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] end - attribute \src "ls180.v:906.5-906.29" - process $proc$ls180.v:906$3439 + attribute \src "ls180.v:909.5-909.29" + process $proc$ls180.v:909$3437 assign { } { } assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "ls180.v:907.5-907.28" - process $proc$ls180.v:907$3440 - assign { } { } - assign $1\main_wb_sdram_we[0:0] 1'0 - sync always - sync init - update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] - end attribute \src "ls180.v:91.11-91.56" process $proc$ls180.v:91$3138 assign { } { } @@ -298422,296 +300923,304 @@ module \ls180 sync init update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] end - attribute \src "ls180.v:914.5-914.54" - process $proc$ls180.v:914$3441 + attribute \src "ls180.v:910.5-910.28" + process $proc$ls180.v:910$3438 + assign { } { } + assign $1\main_wb_sdram_we[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] + end + attribute \src "ls180.v:917.5-917.54" + process $proc$ls180.v:917$3439 assign { } { } assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 sync always sync init update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] end - attribute \src "ls180.v:918.5-918.54" - process $proc$ls180.v:918$3442 + attribute \src "ls180.v:92.5-92.50" + process $proc$ls180.v:92$3139 assign { } { } - assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 sync always - update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] sync init + update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] end - attribute \src "ls180.v:919.5-919.35" - process $proc$ls180.v:919$3443 + attribute \src "ls180.v:921.5-921.54" + process $proc$ls180.v:921$3440 assign { } { } - assign $1\main_socbushandler_skip[0:0] 1'0 + assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 sync always + update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] sync init - update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] end - attribute \src "ls180.v:92.5-92.50" - process $proc$ls180.v:92$3139 + attribute \src "ls180.v:922.5-922.35" + process $proc$ls180.v:922$3441 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $1\main_socbushandler_skip[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] end - attribute \src "ls180.v:920.5-920.38" - process $proc$ls180.v:920$3444 + attribute \src "ls180.v:923.5-923.38" + process $proc$ls180.v:923$3442 assign { } { } assign $1\main_socbushandler_counter[0:0] 1'0 sync always sync init update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] end - attribute \src "ls180.v:922.12-922.44" - process $proc$ls180.v:922$3445 + attribute \src "ls180.v:925.12-925.44" + process $proc$ls180.v:925$3443 assign { } { } assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] end - attribute \src "ls180.v:923.12-923.40" - process $proc$ls180.v:923$3446 + attribute \src "ls180.v:926.12-926.40" + process $proc$ls180.v:926$3444 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "ls180.v:924.12-924.42" - process $proc$ls180.v:924$3447 + attribute \src "ls180.v:927.12-927.42" + process $proc$ls180.v:927$3445 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:926.11-926.38" - process $proc$ls180.v:926$3448 + attribute \src "ls180.v:929.11-929.38" + process $proc$ls180.v:929$3446 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "ls180.v:927.5-927.32" - process $proc$ls180.v:927$3449 + attribute \src "ls180.v:93.5-93.50" + process $proc$ls180.v:93$3140 assign { } { } - assign $1\main_litedram_wb_cyc[0:0] 1'0 + assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 sync always sync init - update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] end - attribute \src "ls180.v:928.5-928.32" - process $proc$ls180.v:928$3450 + attribute \src "ls180.v:930.5-930.32" + process $proc$ls180.v:930$3447 assign { } { } - assign $1\main_litedram_wb_stb[0:0] 1'0 + assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init - update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "ls180.v:93.5-93.50" - process $proc$ls180.v:93$3140 + attribute \src "ls180.v:931.5-931.32" + process $proc$ls180.v:931$3448 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:930.5-930.31" - process $proc$ls180.v:930$3451 + attribute \src "ls180.v:933.5-933.31" + process $proc$ls180.v:933$3449 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "ls180.v:931.5-931.31" - process $proc$ls180.v:931$3452 + attribute \src "ls180.v:934.5-934.31" + process $proc$ls180.v:934$3450 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always sync init update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "ls180.v:932.5-932.34" - process $proc$ls180.v:932$3453 + attribute \src "ls180.v:935.5-935.34" + process $proc$ls180.v:935$3451 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always sync init update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "ls180.v:934.12-934.40" - process $proc$ls180.v:934$3454 + attribute \src "ls180.v:937.12-937.40" + process $proc$ls180.v:937$3452 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always sync init update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "ls180.v:935.5-935.29" - process $proc$ls180.v:935$3455 + attribute \src "ls180.v:938.5-938.29" + process $proc$ls180.v:938$3453 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "ls180.v:936.5-936.31" - process $proc$ls180.v:936$3456 + attribute \src "ls180.v:939.5-939.31" + process $proc$ls180.v:939$3454 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "ls180.v:940.12-940.47" - process $proc$ls180.v:940$3457 + attribute \src "ls180.v:943.12-943.47" + process $proc$ls180.v:943$3455 assign { } { } assign $1\main_uart_phy_storage[31:0] 9895604 sync always sync init update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end - attribute \src "ls180.v:941.5-941.28" - process $proc$ls180.v:941$3458 + attribute \src "ls180.v:944.5-944.28" + process $proc$ls180.v:944$3456 assign { } { } assign $1\main_uart_phy_re[0:0] 1'0 sync always sync init update \main_uart_phy_re $1\main_uart_phy_re[0:0] end - attribute \src "ls180.v:943.5-943.36" - process $proc$ls180.v:943$3459 + attribute \src "ls180.v:946.5-946.36" + process $proc$ls180.v:946$3457 assign { } { } assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always sync init update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:947.5-947.39" - process $proc$ls180.v:947$3460 + attribute \src "ls180.v:95.5-95.49" + process $proc$ls180.v:95$3141 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + end + attribute \src "ls180.v:950.5-950.39" + process $proc$ls180.v:950$3458 assign { } { } assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:948.12-948.54" - process $proc$ls180.v:948$3461 + attribute \src "ls180.v:951.12-951.54" + process $proc$ls180.v:951$3459 assign { } { } assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:949.11-949.38" - process $proc$ls180.v:949$3462 + attribute \src "ls180.v:952.11-952.38" + process $proc$ls180.v:952$3460 assign { } { } assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:95.5-95.49" - process $proc$ls180.v:95$3141 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] - end - attribute \src "ls180.v:950.11-950.43" - process $proc$ls180.v:950$3463 + attribute \src "ls180.v:953.11-953.43" + process $proc$ls180.v:953$3461 assign { } { } assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:951.5-951.33" - process $proc$ls180.v:951$3464 + attribute \src "ls180.v:954.5-954.33" + process $proc$ls180.v:954$3462 assign { } { } assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:952.5-952.38" - process $proc$ls180.v:952$3465 + attribute \src "ls180.v:955.5-955.38" + process $proc$ls180.v:955$3463 assign { } { } assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always sync init update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end - attribute \src "ls180.v:954.5-954.38" - process $proc$ls180.v:954$3466 + attribute \src "ls180.v:957.5-957.38" + process $proc$ls180.v:957$3464 assign { } { } assign $0\main_uart_phy_source_first[0:0] 1'0 sync always update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init end - attribute \src "ls180.v:955.5-955.37" - process $proc$ls180.v:955$3467 + attribute \src "ls180.v:958.5-958.37" + process $proc$ls180.v:958$3465 assign { } { } assign $0\main_uart_phy_source_last[0:0] 1'0 sync always update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] sync init end - attribute \src "ls180.v:956.11-956.51" - process $proc$ls180.v:956$3468 + attribute \src "ls180.v:959.11-959.51" + process $proc$ls180.v:959$3466 assign { } { } assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:957.5-957.39" - process $proc$ls180.v:957$3469 + attribute \src "ls180.v:960.5-960.39" + process $proc$ls180.v:960$3467 assign { } { } assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:958.12-958.54" - process $proc$ls180.v:958$3470 + attribute \src "ls180.v:961.12-961.54" + process $proc$ls180.v:961$3468 assign { } { } assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:960.5-960.30" - process $proc$ls180.v:960$3471 + attribute \src "ls180.v:963.5-963.30" + process $proc$ls180.v:963$3469 assign { } { } assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always sync init update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end - attribute \src "ls180.v:961.11-961.38" - process $proc$ls180.v:961$3472 + attribute \src "ls180.v:964.11-964.38" + process $proc$ls180.v:964$3470 assign { } { } assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:962.11-962.43" - process $proc$ls180.v:962$3473 + attribute \src "ls180.v:965.11-965.43" + process $proc$ls180.v:965$3471 assign { } { } assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:963.5-963.33" - process $proc$ls180.v:963$3474 + attribute \src "ls180.v:966.5-966.33" + process $proc$ls180.v:966$3472 assign { } { } assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always @@ -298726,88 +301235,88 @@ module \ls180 sync init update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] end - attribute \src "ls180.v:974.5-974.32" - process $proc$ls180.v:974$3475 + attribute \src "ls180.v:977.5-977.32" + process $proc$ls180.v:977$3473 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:976.5-976.30" - process $proc$ls180.v:976$3476 + attribute \src "ls180.v:979.5-979.30" + process $proc$ls180.v:979$3474 assign { } { } assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:977.5-977.36" - process $proc$ls180.v:977$3477 + attribute \src "ls180.v:98.12-98.60" + process $proc$ls180.v:98$3143 assign { } { } - assign $1\main_uart_tx_old_trigger[0:0] 1'0 + assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 sync always sync init - update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:979.5-979.32" - process $proc$ls180.v:979$3478 + attribute \src "ls180.v:980.5-980.36" + process $proc$ls180.v:980$3475 assign { } { } - assign $1\main_uart_rx_pending[0:0] 1'0 + assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init - update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "ls180.v:98.12-98.60" - process $proc$ls180.v:98$3143 + attribute \src "ls180.v:982.5-982.32" + process $proc$ls180.v:982$3476 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "ls180.v:981.5-981.30" - process $proc$ls180.v:981$3479 + attribute \src "ls180.v:984.5-984.30" + process $proc$ls180.v:984$3477 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:982.5-982.36" - process $proc$ls180.v:982$3480 + attribute \src "ls180.v:985.5-985.36" + process $proc$ls180.v:985$3478 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "ls180.v:986.11-986.49" - process $proc$ls180.v:986$3481 + attribute \src "ls180.v:989.11-989.49" + process $proc$ls180.v:989$3479 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:990.11-990.50" - process $proc$ls180.v:990$3482 + attribute \src "ls180.v:993.11-993.50" + process $proc$ls180.v:993$3480 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:991.11-991.48" - process $proc$ls180.v:991$3483 + attribute \src "ls180.v:994.11-994.48" + process $proc$ls180.v:994$3481 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "ls180.v:992.5-992.37" - process $proc$ls180.v:992$3484 + attribute \src "ls180.v:995.5-995.37" + process $proc$ls180.v:995$3482 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always @@ -298834,21 +301343,21 @@ module \ls180 connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 connect \main_libresocsim_bus_error \builder_error - connect \main_converter0_reset $not$ls180.v:2890$50_Y + connect \main_converter0_reset $not$ls180.v:2893$50_Y connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } - connect \main_converter1_reset $not$ls180.v:2950$61_Y + connect \main_converter1_reset $not$ls180.v:2953$61_Y connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } - connect \main_socbushandler_reset $not$ls180.v:3010$72_Y + connect \main_socbushandler_reset $not$ls180.v:3013$72_Y connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } connect \main_libresocsim_reset \main_libresocsim_reset_re connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:3086$108_Y + connect \main_libresocsim_zero_trigger $ne$ls180.v:3089$108_Y connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:3095$111_Y + connect \main_libresocsim_irq $and$ls180.v:3098$111_Y connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0] connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r @@ -298902,8 +301411,8 @@ module \ls180 connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n connect \main_sdram_inti_p0_address \main_sdram_address_storage connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3265$218_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3266$219_Y + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3268$218_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3269$219_Y connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage connect \main_sdram_inti_p0_wrdata_mask 2'00 connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid @@ -298934,14 +301443,14 @@ module \ls180 connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3297$220_Y + connect \main_sdram_timer_wait $not$ls180.v:3300$220_Y connect \main_sdram_postponer_req_i \main_sdram_timer_done0 connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3300$221_Y + connect \main_sdram_timer_done1 $eq$ls180.v:3303$221_Y connect \main_sdram_timer_done0 \main_sdram_timer_done1 connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3303$223_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3304$225_Y + connect \main_sdram_sequencer_start1 $or$ls180.v:3306$223_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3307$225_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we @@ -298952,13 +301461,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3346$227_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3347$228_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3348$229_Y + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3349$227_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3350$228_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3351$229_Y connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3358$234_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3359$236_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3360$238_Y + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3361$234_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3362$236_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3363$238_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable @@ -298974,13 +301483,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3392$246_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3393$247_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3395$246_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3396$247_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3396$248_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3397$249_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3398$251_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3399$248_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3400$249_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3401$251_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we @@ -298991,13 +301500,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3503$257_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3504$258_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3505$259_Y + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3506$257_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3507$258_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3508$259_Y connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3515$264_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3516$266_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3517$268_Y + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3518$264_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3519$266_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3520$268_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable @@ -299013,13 +301522,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3549$276_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3550$277_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3552$276_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3553$277_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3553$278_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3554$279_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3555$281_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3556$278_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3557$279_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3558$281_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we @@ -299030,13 +301539,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3660$287_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3661$288_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3662$289_Y + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3663$287_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3664$288_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3665$289_Y connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3672$294_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3673$296_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3674$298_Y + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3675$294_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3676$296_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3677$298_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable @@ -299052,13 +301561,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3706$306_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3707$307_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3709$306_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3710$307_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3710$308_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3711$309_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3712$311_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3713$308_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3714$309_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3715$311_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we @@ -299069,13 +301578,13 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3817$317_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3818$318_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3819$319_Y + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3820$317_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3821$318_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3822$319_Y connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3829$324_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3830$326_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3831$328_Y + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3832$324_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3833$326_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3834$328_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable @@ -299091,32 +301600,32 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3863$336_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3864$337_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3866$336_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3867$337_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3867$338_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3868$339_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3869$341_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3870$338_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3871$339_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3872$341_Y connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3965$352_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3966$358_Y - connect \main_sdram_ras_allowed $and$ls180.v:3967$359_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3968$362_Y + connect \main_sdram_trrdcon_valid $and$ls180.v:3968$352_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3969$358_Y + connect \main_sdram_ras_allowed $and$ls180.v:3970$359_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3971$362_Y connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3970$364_Y - connect \main_sdram_read_available $or$ls180.v:3971$371_Y - connect \main_sdram_write_available $or$ls180.v:3972$378_Y - connect \main_sdram_max_time0 $eq$ls180.v:3973$379_Y - connect \main_sdram_max_time1 $eq$ls180.v:3974$380_Y + connect \main_sdram_twtrcon_valid $and$ls180.v:3973$364_Y + connect \main_sdram_read_available $or$ls180.v:3974$371_Y + connect \main_sdram_write_available $or$ls180.v:3975$378_Y + connect \main_sdram_max_time0 $eq$ls180.v:3976$379_Y + connect \main_sdram_max_time1 $eq$ls180.v:3977$380_Y connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3979$383_Y + connect \main_sdram_go_to_refresh $and$ls180.v:3982$383_Y connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3982$384_Y + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3985$384_Y connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 @@ -299124,7 +301633,7 @@ module \ls180 connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:4015$442_Y + connect \main_sdram_choose_cmd_ce $or$ls180.v:4018$442_Y connect \main_sdram_choose_req_request \main_sdram_choose_req_valids connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 @@ -299132,31 +301641,31 @@ module \ls180 connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:4084$528_Y + connect \main_sdram_choose_req_ce $or$ls180.v:4087$528_Y connect \main_sdram_dfi_p0_reset_n 1'1 connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:4161$560_Y - connect \builder_roundrobin0_ce $and$ls180.v:4162$563_Y + connect \builder_roundrobin0_request $and$ls180.v:4164$560_Y + connect \builder_roundrobin0_ce $and$ls180.v:4165$563_Y connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:4166$576_Y - connect \builder_roundrobin1_ce $and$ls180.v:4167$579_Y + connect \builder_roundrobin1_request $and$ls180.v:4169$576_Y + connect \builder_roundrobin1_ce $and$ls180.v:4170$579_Y connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:4171$592_Y - connect \builder_roundrobin2_ce $and$ls180.v:4172$595_Y + connect \builder_roundrobin2_request $and$ls180.v:4174$592_Y + connect \builder_roundrobin2_ce $and$ls180.v:4175$595_Y connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:4176$608_Y - connect \builder_roundrobin3_ce $and$ls180.v:4177$611_Y + connect \builder_roundrobin3_request $and$ls180.v:4179$608_Y + connect \builder_roundrobin3_ce $and$ls180.v:4180$611_Y connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4181$675_Y + connect \main_port_cmd_ready $or$ls180.v:4184$675_Y connect \main_port_wdata_ready \builder_new_master_wdata_ready connect \main_port_rdata_valid \builder_new_master_rdata_valid3 connect \main_port_rdata_payload_data \main_sdram_interface_rdata @@ -299164,22 +301673,22 @@ module \ls180 connect \builder_roundrobin1_grant 1'0 connect \builder_roundrobin2_grant 1'0 connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4203$677_Y + connect \main_converter_reset $not$ls180.v:4206$677_Y connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4263$688_Y [23:0] + connect \main_port_cmd_payload_addr $sub$ls180.v:4266$688_Y [23:0] connect \main_port_cmd_payload_we \main_litedram_wb_we connect \main_port_wdata_payload_data \main_litedram_wb_dat_w connect \main_port_wdata_payload_we \main_litedram_wb_sel connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4268$689_Y - connect \main_port_cmd_last $not$ls180.v:4269$690_Y - connect \main_port_cmd_valid $and$ls180.v:4270$693_Y - connect \main_port_wdata_valid $and$ls180.v:4271$697_Y - connect \main_port_rdata_ready $and$ls180.v:4272$700_Y - connect \main_litedram_wb_ack $and$ls180.v:4273$705_Y - connect \main_ack_cmd $or$ls180.v:4274$707_Y - connect \main_ack_wdata $or$ls180.v:4275$709_Y - connect \main_ack_rdata $and$ls180.v:4276$710_Y + connect \main_port_flush $not$ls180.v:4271$689_Y + connect \main_port_cmd_last $not$ls180.v:4272$690_Y + connect \main_port_cmd_valid $and$ls180.v:4273$693_Y + connect \main_port_wdata_valid $and$ls180.v:4274$697_Y + connect \main_port_rdata_ready $and$ls180.v:4275$700_Y + connect \main_litedram_wb_ack $and$ls180.v:4276$705_Y + connect \main_ack_cmd $or$ls180.v:4277$707_Y + connect \main_ack_wdata $or$ls180.v:4278$709_Y + connect \main_ack_rdata $and$ls180.v:4279$710_Y connect \main_uart_uart_sink_valid \main_uart_phy_source_valid connect \main_uart_phy_source_ready \main_uart_uart_sink_ready connect \main_uart_uart_sink_first \main_uart_phy_source_first @@ -299192,25 +301701,25 @@ module \ls180 connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4289$711_Y - connect \main_uart_txempty_status $not$ls180.v:4290$712_Y + connect \main_uart_txfull_status $not$ls180.v:4292$711_Y + connect \main_uart_txempty_status $not$ls180.v:4293$712_Y connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4296$713_Y + connect \main_uart_tx_trigger $not$ls180.v:4299$713_Y connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4302$714_Y - connect \main_uart_rxfull_status $not$ls180.v:4303$715_Y + connect \main_uart_rxempty_status $not$ls180.v:4305$714_Y + connect \main_uart_rxfull_status $not$ls180.v:4306$715_Y connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4305$717_Y - connect \main_uart_rx_trigger $not$ls180.v:4306$718_Y - connect \main_uart_irq $or$ls180.v:4329$727_Y + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4308$717_Y + connect \main_uart_rx_trigger $not$ls180.v:4309$718_Y + connect \main_uart_irq $or$ls180.v:4332$727_Y connect \main_uart_tx_status \main_uart_tx_trigger connect \main_uart_rx_status \main_uart_rx_trigger connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } @@ -299225,16 +301734,16 @@ module \ls180 connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4344$730_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4345$731_Y + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4347$730_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4348$731_Y connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4355$735_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4356$736_Y + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4358$735_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4359$736_Y connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4360$737_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4361$738_Y + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4363$737_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4364$738_Y connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable @@ -299247,16 +301756,16 @@ module \ls180 connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4374$741_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4375$742_Y + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4377$741_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4378$742_Y connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4385$746_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4386$747_Y + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4388$746_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4389$747_Y connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4390$748_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4391$749_Y + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4393$748_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4394$749_Y connect \main_gpiotristateasic0_pads_i \gpio_i connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage @@ -299270,8 +301779,8 @@ module \ls180 connect \main_spimaster18_status \main_spimaster5_miso connect \main_spimaster6_cs \main_spimaster21_storage connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4415$753_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4416$755_Y + connect \main_spimaster31_clk_rise $eq$ls180.v:4418$753_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4419$755_Y connect \main_spisdcard_start0 \main_spisdcard_start1 connect \main_spisdcard_length0 \main_spisdcard_length1 connect \main_spisdcard_mosi \main_spisdcard_mosi_storage @@ -299279,19 +301788,19 @@ module \ls180 connect \main_spisdcard_miso_status \main_spisdcard_miso connect \main_spisdcard_cs \main_spisdcard_cs_storage connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4473$761_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4474$763_Y + connect \main_spisdcard_clk_rise $eq$ls180.v:4476$761_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4477$763_Y connect \main_spisdcard_clk_divider0 \main_spimaster1_storage connect \i2c_scl \main_i2c_scl connect \i2c_sda_oe \main_i2c_oe connect \i2c_sda_o \main_i2c_sda0 connect \main_i2c_sda1 \i2c_sda_i connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4530$771_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4531$775_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4532$779_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4533$783_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4534$787_Y + connect \main_sdphy_sdpads_clk $or$ls180.v:4533$771_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4534$775_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4535$779_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4536$783_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4537$787_Y connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce @@ -299312,8 +301821,8 @@ module \ls180 connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4555$788_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4585$791_Y + connect \main_sdphy_clocker_stop $or$ls180.v:4558$788_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4588$791_Y connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first @@ -299325,8 +301834,8 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4708$801_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4709$803_Y + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4711$801_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4712$803_Y connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready @@ -299343,10 +301852,10 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4726$805_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4729$805_Y connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4728$806_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4729$808_Y + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4731$806_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4732$808_Y connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first @@ -299358,8 +301867,8 @@ module \ls180 connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4835$823_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4836$824_Y + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4838$823_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4839$824_Y connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready @@ -299376,10 +301885,10 @@ module \ls180 connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4853$826_Y + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4856$826_Y connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4855$827_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4856$829_Y + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4858$827_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4859$829_Y connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first @@ -299391,8 +301900,8 @@ module \ls180 connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4969$838_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4970$839_Y + connect \main_sdphy_datar_datar_start $eq$ls180.v:4972$838_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4973$839_Y connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready @@ -299409,10 +301918,10 @@ module \ls180 connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4987$841_Y + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4990$841_Y connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4989$842_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4990$844_Y + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4992$842_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4993$844_Y connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first @@ -299426,88 +301935,88 @@ module \ls180 connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:5106$859_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_data_event_status { $not$ls180.v:5109$859_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } connect \main_sdcore_crc7_inserter_clr 1'1 connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5110$862_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5110$860_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5111$865_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5111$863_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5112$868_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5112$866_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5113$871_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5113$869_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5114$874_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5114$872_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5115$877_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5115$875_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5116$880_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5116$878_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5117$883_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5117$881_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5118$886_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5118$884_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5119$889_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5119$887_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5120$892_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5120$890_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5121$895_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5121$893_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5122$898_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5122$896_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5123$901_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5123$899_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5124$904_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5124$902_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5125$907_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5125$905_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5126$910_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5126$908_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5127$913_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5127$911_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5128$916_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5128$914_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5129$919_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5129$917_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5130$922_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5130$920_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5131$925_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5131$923_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5132$928_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5132$926_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5133$931_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5133$929_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5134$934_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5134$932_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5135$937_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5135$935_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5136$940_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5136$938_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5137$943_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5137$941_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5138$946_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5138$944_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5139$949_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5139$947_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5140$952_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5140$950_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5141$955_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5141$953_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5142$958_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5142$956_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5143$961_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5143$959_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5144$964_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5144$962_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5145$967_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5145$965_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5146$970_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5146$968_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5147$973_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5147$971_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5148$976_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5148$974_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5149$979_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5149$977_Y } + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5113$862_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5113$860_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5114$865_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5114$863_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5115$868_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5115$866_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5116$871_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5116$869_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5117$874_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5117$872_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5118$877_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5118$875_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5119$880_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5119$878_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5120$883_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5120$881_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5121$886_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5121$884_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5122$889_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5122$887_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5123$892_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5123$890_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5124$895_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5124$893_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5125$898_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5125$896_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5126$901_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5126$899_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5127$904_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5127$902_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5128$907_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5128$905_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5129$910_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5129$908_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5130$913_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5130$911_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5131$916_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5131$914_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5132$919_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5132$917_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5133$922_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5133$920_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5134$925_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5134$923_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5135$928_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5135$926_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5136$931_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5136$929_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5137$934_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5137$932_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5138$937_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5138$935_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5139$940_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5139$938_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5140$943_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5140$941_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5141$946_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5141$944_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5142$949_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5142$947_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5143$952_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5143$950_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5144$955_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5144$953_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5145$958_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5145$956_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5146$961_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5146$959_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5147$964_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5147$962_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5148$967_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5148$965_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5149$970_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5149$968_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5150$973_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5150$971_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5151$976_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5151$974_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5152$979_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5152$977_Y } connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5159$982_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5160$983_Y + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5162$982_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5163$983_Y connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5162$985_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5163$986_Y + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5165$985_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5166$986_Y connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5165$988_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5166$989_Y + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5168$988_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5169$989_Y connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5168$991_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5169$992_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5170$997_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5170$995_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5170$993_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5171$1002_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5171$1000_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5171$998_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5180$1008_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5180$1006_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5180$1004_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5181$1013_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5181$1011_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5181$1009_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5190$1019_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5190$1017_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5190$1015_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5191$1024_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5191$1022_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5191$1020_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5200$1030_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5200$1028_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5200$1026_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5201$1035_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5201$1033_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5201$1031_Y } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5171$991_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5172$992_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5173$997_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5173$995_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5173$993_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5174$1002_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5174$1000_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5174$998_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5183$1008_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5183$1006_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5183$1004_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5184$1013_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5184$1011_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5184$1009_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5193$1019_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5193$1017_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5193$1015_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5194$1024_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5194$1022_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5194$1020_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5203$1030_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5203$1028_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5203$1026_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5204$1035_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5204$1033_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5204$1031_Y } connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5297$1051_Y + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5300$1051_Y connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5307$1054_Y + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5310$1054_Y connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5317$1057_Y + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5320$1057_Y connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5327$1060_Y + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5330$1060_Y connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5352$1072_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5352$1070_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5352$1068_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5353$1077_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5353$1075_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5353$1073_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5362$1083_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5362$1081_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5362$1079_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5363$1088_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5363$1086_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5363$1084_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5372$1094_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5372$1092_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5372$1090_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5373$1099_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5373$1097_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5373$1095_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5382$1105_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5382$1103_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5382$1101_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5383$1110_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5383$1108_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5383$1106_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5355$1072_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5355$1070_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5355$1068_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5356$1077_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5356$1075_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5356$1073_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5365$1083_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5365$1081_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5365$1079_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5366$1088_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5366$1086_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5366$1084_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5375$1094_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5375$1092_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5375$1090_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5376$1099_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5376$1097_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5376$1095_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5385$1105_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5385$1103_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5385$1101_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5386$1110_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5386$1108_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5386$1106_Y } connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first @@ -299536,20 +302045,20 @@ module \ls180 connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5619$1140_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5620$1141_Y + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5622$1140_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5623$1141_Y connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5623$1142_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5624$1143_Y + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5626$1142_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5627$1143_Y connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5630$1145_Y + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5633$1145_Y connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5632$1146_Y + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5635$1146_Y connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_we 1'1 @@ -299559,7 +302068,7 @@ module \ls180 connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5642$1147_Y + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5645$1147_Y connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first @@ -299578,18 +302087,18 @@ module \ls180 connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5701$1154_Y + connect \main_sdmem2block_dma_reset $not$ls180.v:5704$1154_Y connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5782$1162_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5783$1163_Y + connect \main_sdmem2block_converter_first $eq$ls180.v:5785$1162_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5786$1163_Y connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5785$1164_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5786$1165_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5787$1166_Y + connect \main_sdmem2block_converter_source_first $and$ls180.v:5788$1164_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5789$1165_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5790$1166_Y connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout @@ -299604,12 +302113,12 @@ module \ls180 connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5839$1171_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5840$1172_Y + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5842$1171_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5843$1172_Y connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5843$1173_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5844$1174_Y + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5846$1173_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5847$1174_Y connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] @@ -299623,16 +302132,16 @@ module \ls180 connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5895$1180_Y - connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5896$1182_Y - connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5897$1184_Y - connect \main_interface0_bus_ack $and$ls180.v:5898$1186_Y - connect \main_interface1_bus_ack $and$ls180.v:5899$1188_Y - connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5900$1190_Y - connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5901$1192_Y - connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5902$1194_Y - connect \main_interface0_bus_err $and$ls180.v:5903$1196_Y - connect \main_interface1_bus_err $and$ls180.v:5904$1198_Y + connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5898$1180_Y + connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5899$1182_Y + connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5900$1184_Y + connect \main_interface0_bus_ack $and$ls180.v:5901$1186_Y + connect \main_interface1_bus_ack $and$ls180.v:5902$1188_Y + connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5903$1190_Y + connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5904$1192_Y + connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5905$1194_Y + connect \main_interface0_bus_err $and$ls180.v:5906$1196_Y + connect \main_interface1_bus_err $and$ls180.v:5907$1198_Y connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } connect \main_libresocsim_ram_bus_adr \builder_shared_adr connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } @@ -299725,50 +302234,50 @@ module \ls180 connect \builder_libresocsim_converted_interface_we \builder_shared_we connect \builder_libresocsim_converted_interface_cti \builder_shared_cti connect \builder_libresocsim_converted_interface_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:6013$1213_Y - connect \main_interface0_ram_bus_cyc $and$ls180.v:6014$1214_Y - connect \main_interface1_ram_bus_cyc $and$ls180.v:6015$1215_Y - connect \main_interface2_ram_bus_cyc $and$ls180.v:6016$1216_Y - connect \main_interface3_ram_bus_cyc $and$ls180.v:6017$1217_Y - connect \main_interface0_converted_interface_cyc $and$ls180.v:6018$1218_Y - connect \main_interface1_converted_interface_cyc $and$ls180.v:6019$1219_Y - connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:6020$1220_Y - connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:6021$1221_Y - connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:6022$1222_Y - connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:6023$1223_Y - connect \main_socbushandler_converted_interface_cyc $and$ls180.v:6024$1224_Y - connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:6025$1225_Y - connect \builder_shared_err $or$ls180.v:6026$1237_Y - connect \builder_wait $and$ls180.v:6027$1240_Y - connect \builder_done $eq$ls180.v:6040$1279_Y - connect \builder_csrbank0_sel $eq$ls180.v:6041$1280_Y + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:6016$1213_Y + connect \main_interface0_ram_bus_cyc $and$ls180.v:6017$1214_Y + connect \main_interface1_ram_bus_cyc $and$ls180.v:6018$1215_Y + connect \main_interface2_ram_bus_cyc $and$ls180.v:6019$1216_Y + connect \main_interface3_ram_bus_cyc $and$ls180.v:6020$1217_Y + connect \main_interface0_converted_interface_cyc $and$ls180.v:6021$1218_Y + connect \main_interface1_converted_interface_cyc $and$ls180.v:6022$1219_Y + connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:6023$1220_Y + connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:6024$1221_Y + connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:6025$1222_Y + connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:6026$1223_Y + connect \main_socbushandler_converted_interface_cyc $and$ls180.v:6027$1224_Y + connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:6028$1225_Y + connect \builder_shared_err $or$ls180.v:6029$1237_Y + connect \builder_wait $and$ls180.v:6030$1240_Y + connect \builder_done $eq$ls180.v:6043$1279_Y + connect \builder_csrbank0_sel $eq$ls180.v:6044$1280_Y connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:6043$1283_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:6044$1287_Y + connect \builder_csrbank0_reset0_re $and$ls180.v:6046$1283_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:6047$1287_Y connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:6046$1290_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:6047$1294_Y + connect \builder_csrbank0_scratch3_re $and$ls180.v:6049$1290_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:6050$1294_Y connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:6049$1297_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:6050$1301_Y + connect \builder_csrbank0_scratch2_re $and$ls180.v:6052$1297_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:6053$1301_Y connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:6052$1304_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:6053$1308_Y + connect \builder_csrbank0_scratch1_re $and$ls180.v:6055$1304_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:6056$1308_Y connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:6055$1311_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:6056$1315_Y + connect \builder_csrbank0_scratch0_re $and$ls180.v:6058$1311_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:6059$1315_Y connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:6058$1318_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:6059$1322_Y + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:6061$1318_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:6062$1322_Y connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:6061$1325_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:6062$1329_Y + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:6064$1325_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:6065$1329_Y connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:6064$1332_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:6065$1336_Y + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:6067$1332_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:6068$1336_Y connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:6067$1339_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:6068$1343_Y + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:6070$1339_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:6071$1343_Y connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] @@ -299779,25 +302288,25 @@ module \ls180 connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:6079$1344_Y + connect \builder_csrbank1_sel $eq$ls180.v:6082$1344_Y connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:6081$1347_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:6082$1351_Y + connect \builder_csrbank1_oe1_re $and$ls180.v:6084$1347_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:6085$1351_Y connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:6084$1354_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:6085$1358_Y + connect \builder_csrbank1_oe0_re $and$ls180.v:6087$1354_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:6088$1358_Y connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:6087$1361_Y - connect \builder_csrbank1_in1_we $and$ls180.v:6088$1365_Y + connect \builder_csrbank1_in1_re $and$ls180.v:6090$1361_Y + connect \builder_csrbank1_in1_we $and$ls180.v:6091$1365_Y connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:6090$1368_Y - connect \builder_csrbank1_in0_we $and$ls180.v:6091$1372_Y + connect \builder_csrbank1_in0_re $and$ls180.v:6093$1368_Y + connect \builder_csrbank1_in0_we $and$ls180.v:6094$1372_Y connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:6093$1375_Y - connect \builder_csrbank1_out1_we $and$ls180.v:6094$1379_Y + connect \builder_csrbank1_out1_re $and$ls180.v:6096$1375_Y + connect \builder_csrbank1_out1_we $and$ls180.v:6097$1379_Y connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:6096$1382_Y - connect \builder_csrbank1_out0_we $and$ls180.v:6097$1386_Y + connect \builder_csrbank1_out0_re $and$ls180.v:6099$1382_Y + connect \builder_csrbank1_out0_we $and$ls180.v:6100$1386_Y connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] @@ -299805,13 +302314,13 @@ module \ls180 connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:6105$1387_Y + connect \builder_csrbank2_sel $eq$ls180.v:6108$1387_Y connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:6107$1390_Y - connect \builder_csrbank2_w0_we $and$ls180.v:6108$1394_Y + connect \builder_csrbank2_w0_re $and$ls180.v:6110$1390_Y + connect \builder_csrbank2_w0_we $and$ls180.v:6111$1394_Y connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:6110$1397_Y - connect \builder_csrbank2_r_we $and$ls180.v:6111$1401_Y + connect \builder_csrbank2_r_re $and$ls180.v:6113$1397_Y + connect \builder_csrbank2_r_we $and$ls180.v:6114$1401_Y connect \main_i2c_scl \main_i2c_storage [0] connect \main_i2c_oe \main_i2c_storage [1] connect \main_i2c_sda0 \main_i2c_storage [2] @@ -299819,34 +302328,34 @@ module \ls180 connect \main_i2c_status \main_i2c_sda1 connect \builder_csrbank2_r_w \main_i2c_status connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:6119$1402_Y + connect \builder_csrbank3_sel $eq$ls180.v:6122$1402_Y connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:6121$1405_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:6122$1409_Y + connect \builder_csrbank3_enable0_re $and$ls180.v:6124$1405_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:6125$1409_Y connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:6124$1412_Y - connect \builder_csrbank3_width3_we $and$ls180.v:6125$1416_Y + connect \builder_csrbank3_width3_re $and$ls180.v:6127$1412_Y + connect \builder_csrbank3_width3_we $and$ls180.v:6128$1416_Y connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:6127$1419_Y - connect \builder_csrbank3_width2_we $and$ls180.v:6128$1423_Y + connect \builder_csrbank3_width2_re $and$ls180.v:6130$1419_Y + connect \builder_csrbank3_width2_we $and$ls180.v:6131$1423_Y connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:6130$1426_Y - connect \builder_csrbank3_width1_we $and$ls180.v:6131$1430_Y + connect \builder_csrbank3_width1_re $and$ls180.v:6133$1426_Y + connect \builder_csrbank3_width1_we $and$ls180.v:6134$1430_Y connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:6133$1433_Y - connect \builder_csrbank3_width0_we $and$ls180.v:6134$1437_Y + connect \builder_csrbank3_width0_re $and$ls180.v:6136$1433_Y + connect \builder_csrbank3_width0_we $and$ls180.v:6137$1437_Y connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:6136$1440_Y - connect \builder_csrbank3_period3_we $and$ls180.v:6137$1444_Y + connect \builder_csrbank3_period3_re $and$ls180.v:6139$1440_Y + connect \builder_csrbank3_period3_we $and$ls180.v:6140$1444_Y connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:6139$1447_Y - connect \builder_csrbank3_period2_we $and$ls180.v:6140$1451_Y + connect \builder_csrbank3_period2_re $and$ls180.v:6142$1447_Y + connect \builder_csrbank3_period2_we $and$ls180.v:6143$1451_Y connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:6142$1454_Y - connect \builder_csrbank3_period1_we $and$ls180.v:6143$1458_Y + connect \builder_csrbank3_period1_re $and$ls180.v:6145$1454_Y + connect \builder_csrbank3_period1_we $and$ls180.v:6146$1458_Y connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:6145$1461_Y - connect \builder_csrbank3_period0_we $and$ls180.v:6146$1465_Y + connect \builder_csrbank3_period0_re $and$ls180.v:6148$1461_Y + connect \builder_csrbank3_period0_we $and$ls180.v:6149$1465_Y connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] @@ -299856,34 +302365,34 @@ module \ls180 connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:6156$1466_Y + connect \builder_csrbank4_sel $eq$ls180.v:6159$1466_Y connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:6158$1469_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:6159$1473_Y + connect \builder_csrbank4_enable0_re $and$ls180.v:6161$1469_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:6162$1473_Y connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:6161$1476_Y - connect \builder_csrbank4_width3_we $and$ls180.v:6162$1480_Y + connect \builder_csrbank4_width3_re $and$ls180.v:6164$1476_Y + connect \builder_csrbank4_width3_we $and$ls180.v:6165$1480_Y connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:6164$1483_Y - connect \builder_csrbank4_width2_we $and$ls180.v:6165$1487_Y + connect \builder_csrbank4_width2_re $and$ls180.v:6167$1483_Y + connect \builder_csrbank4_width2_we $and$ls180.v:6168$1487_Y connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:6167$1490_Y - connect \builder_csrbank4_width1_we $and$ls180.v:6168$1494_Y + connect \builder_csrbank4_width1_re $and$ls180.v:6170$1490_Y + connect \builder_csrbank4_width1_we $and$ls180.v:6171$1494_Y connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:6170$1497_Y - connect \builder_csrbank4_width0_we $and$ls180.v:6171$1501_Y + connect \builder_csrbank4_width0_re $and$ls180.v:6173$1497_Y + connect \builder_csrbank4_width0_we $and$ls180.v:6174$1501_Y connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:6173$1504_Y - connect \builder_csrbank4_period3_we $and$ls180.v:6174$1508_Y + connect \builder_csrbank4_period3_re $and$ls180.v:6176$1504_Y + connect \builder_csrbank4_period3_we $and$ls180.v:6177$1508_Y connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:6176$1511_Y - connect \builder_csrbank4_period2_we $and$ls180.v:6177$1515_Y + connect \builder_csrbank4_period2_re $and$ls180.v:6179$1511_Y + connect \builder_csrbank4_period2_we $and$ls180.v:6180$1515_Y connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:6179$1518_Y - connect \builder_csrbank4_period1_we $and$ls180.v:6180$1522_Y + connect \builder_csrbank4_period1_re $and$ls180.v:6182$1518_Y + connect \builder_csrbank4_period1_we $and$ls180.v:6183$1522_Y connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:6182$1525_Y - connect \builder_csrbank4_period0_we $and$ls180.v:6183$1529_Y + connect \builder_csrbank4_period0_re $and$ls180.v:6185$1525_Y + connect \builder_csrbank4_period0_we $and$ls180.v:6186$1529_Y connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] @@ -299893,52 +302402,52 @@ module \ls180 connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:6193$1530_Y + connect \builder_csrbank5_sel $eq$ls180.v:6196$1530_Y connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:6195$1533_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:6196$1537_Y + connect \builder_csrbank5_dma_base7_re $and$ls180.v:6198$1533_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:6199$1537_Y connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:6198$1540_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:6199$1544_Y + connect \builder_csrbank5_dma_base6_re $and$ls180.v:6201$1540_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:6202$1544_Y connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:6201$1547_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:6202$1551_Y + connect \builder_csrbank5_dma_base5_re $and$ls180.v:6204$1547_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:6205$1551_Y connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:6204$1554_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:6205$1558_Y + connect \builder_csrbank5_dma_base4_re $and$ls180.v:6207$1554_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:6208$1558_Y connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:6207$1561_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:6208$1565_Y + connect \builder_csrbank5_dma_base3_re $and$ls180.v:6210$1561_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:6211$1565_Y connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:6210$1568_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:6211$1572_Y + connect \builder_csrbank5_dma_base2_re $and$ls180.v:6213$1568_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:6214$1572_Y connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:6213$1575_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:6214$1579_Y + connect \builder_csrbank5_dma_base1_re $and$ls180.v:6216$1575_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:6217$1579_Y connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:6216$1582_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:6217$1586_Y + connect \builder_csrbank5_dma_base0_re $and$ls180.v:6219$1582_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:6220$1586_Y connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:6219$1589_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:6220$1593_Y + connect \builder_csrbank5_dma_length3_re $and$ls180.v:6222$1589_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:6223$1593_Y connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:6222$1596_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:6223$1600_Y + connect \builder_csrbank5_dma_length2_re $and$ls180.v:6225$1596_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:6226$1600_Y connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:6225$1603_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:6226$1607_Y + connect \builder_csrbank5_dma_length1_re $and$ls180.v:6228$1603_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:6229$1607_Y connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:6228$1610_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:6229$1614_Y + connect \builder_csrbank5_dma_length0_re $and$ls180.v:6231$1610_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:6232$1614_Y connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6231$1617_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6232$1621_Y + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6234$1617_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6235$1621_Y connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:6234$1624_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:6235$1628_Y + connect \builder_csrbank5_dma_done_re $and$ls180.v:6237$1624_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:6238$1628_Y connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6237$1631_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6238$1635_Y + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6240$1631_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6241$1635_Y connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] @@ -299955,106 +302464,106 @@ module \ls180 connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:6255$1636_Y + connect \builder_csrbank6_sel $eq$ls180.v:6258$1636_Y connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6257$1639_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6258$1643_Y + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6260$1639_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6261$1643_Y connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6260$1646_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6261$1650_Y + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6263$1646_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6264$1650_Y connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6263$1653_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6264$1657_Y + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6266$1653_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6267$1657_Y connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6266$1660_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6267$1664_Y + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6269$1660_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6270$1664_Y connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6269$1667_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6270$1671_Y + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6272$1667_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6273$1671_Y connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6272$1674_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6273$1678_Y + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6275$1674_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6276$1678_Y connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6275$1681_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6276$1685_Y + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6278$1681_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6279$1685_Y connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6278$1688_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6279$1692_Y + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6281$1688_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6282$1692_Y connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6281$1695_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6282$1699_Y + connect \main_sdcore_cmd_send_re $and$ls180.v:6284$1695_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6285$1699_Y connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6284$1702_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6285$1706_Y + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6287$1702_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6288$1706_Y connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6287$1709_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6288$1713_Y + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6290$1709_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6291$1713_Y connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6290$1716_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6291$1720_Y + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6293$1716_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6294$1720_Y connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6293$1723_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6294$1727_Y + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6296$1723_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6297$1727_Y connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6296$1730_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6297$1734_Y + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6299$1730_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6300$1734_Y connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6299$1737_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6300$1741_Y + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6302$1737_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6303$1741_Y connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6302$1744_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6303$1748_Y + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6305$1744_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6306$1748_Y connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6305$1751_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6306$1755_Y + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6308$1751_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6309$1755_Y connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6308$1758_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6309$1762_Y + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6311$1758_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6312$1762_Y connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6311$1765_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6312$1769_Y + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6314$1765_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6315$1769_Y connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6314$1772_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6315$1776_Y + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6317$1772_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6318$1776_Y connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6317$1779_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6318$1783_Y + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6320$1779_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6321$1783_Y connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6320$1786_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6321$1790_Y + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6323$1786_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6324$1790_Y connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6323$1793_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6324$1797_Y + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6326$1793_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6327$1797_Y connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6326$1800_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6327$1804_Y + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6329$1800_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6330$1804_Y connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6329$1807_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6330$1811_Y + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6332$1807_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6333$1811_Y connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6332$1814_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6333$1818_Y + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6335$1814_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6336$1818_Y connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6335$1821_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6336$1825_Y + connect \builder_csrbank6_data_event_re $and$ls180.v:6338$1821_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6339$1825_Y connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6338$1828_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6339$1832_Y + connect \builder_csrbank6_block_length1_re $and$ls180.v:6341$1828_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6342$1832_Y connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6341$1835_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6342$1839_Y + connect \builder_csrbank6_block_length0_re $and$ls180.v:6344$1835_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6345$1839_Y connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6344$1842_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6345$1846_Y + connect \builder_csrbank6_block_count3_re $and$ls180.v:6347$1842_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6348$1846_Y connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6347$1849_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6348$1853_Y + connect \builder_csrbank6_block_count2_re $and$ls180.v:6350$1849_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6351$1853_Y connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6350$1856_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6351$1860_Y + connect \builder_csrbank6_block_count1_re $and$ls180.v:6353$1856_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6354$1860_Y connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6353$1863_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6354$1867_Y + connect \builder_csrbank6_block_count0_re $and$ls180.v:6356$1863_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6357$1867_Y connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] @@ -300090,64 +302599,64 @@ module \ls180 connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6390$1868_Y + connect \builder_csrbank7_sel $eq$ls180.v:6393$1868_Y connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6392$1871_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6393$1875_Y + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6395$1871_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6396$1875_Y connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6395$1878_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6396$1882_Y + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6398$1878_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6399$1882_Y connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6398$1885_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6399$1889_Y + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6401$1885_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6402$1889_Y connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6401$1892_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6402$1896_Y + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6404$1892_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6405$1896_Y connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6404$1899_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6405$1903_Y + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6407$1899_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6408$1903_Y connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6407$1906_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6408$1910_Y + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6410$1906_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6411$1910_Y connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6410$1913_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6411$1917_Y + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6413$1913_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6414$1917_Y connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6413$1920_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6414$1924_Y + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6416$1920_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6417$1924_Y connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6416$1927_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6417$1931_Y + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6419$1927_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6420$1931_Y connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6419$1934_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6420$1938_Y + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6422$1934_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6423$1938_Y connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6422$1941_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6423$1945_Y + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6425$1941_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6426$1945_Y connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6425$1948_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6426$1952_Y + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6428$1948_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6429$1952_Y connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6428$1955_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6429$1959_Y + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6431$1955_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6432$1959_Y connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6431$1962_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6432$1966_Y + connect \builder_csrbank7_dma_done_re $and$ls180.v:6434$1962_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6435$1966_Y connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6434$1969_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6435$1973_Y + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6437$1969_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6438$1973_Y connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6437$1976_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6438$1980_Y + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6440$1976_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6441$1980_Y connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6440$1983_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6441$1987_Y + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6443$1983_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6444$1987_Y connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6443$1990_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6444$1994_Y + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6446$1990_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6447$1994_Y connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6446$1997_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6447$2001_Y + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6449$1997_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6450$2001_Y connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] @@ -300169,54 +302678,54 @@ module \ls180 connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6469$2002_Y + connect \builder_csrbank8_sel $eq$ls180.v:6472$2002_Y connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6471$2005_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6472$2009_Y + connect \builder_csrbank8_card_detect_re $and$ls180.v:6474$2005_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6475$2009_Y connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6474$2012_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6475$2016_Y + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6477$2012_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6478$2016_Y connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6477$2019_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6478$2023_Y + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6480$2019_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6481$2023_Y connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6480$2026_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6481$2030_Y + connect \main_sdphy_init_initialize_re $and$ls180.v:6483$2026_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6484$2030_Y connect \builder_csrbank8_card_detect_w \main_sdphy_status connect \main_sdphy_we \builder_csrbank8_card_detect_we connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6486$2031_Y + connect \builder_csrbank9_sel $eq$ls180.v:6489$2031_Y connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6488$2034_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6489$2038_Y + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6491$2034_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6492$2038_Y connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6491$2041_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6492$2045_Y + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6494$2041_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6495$2045_Y connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6494$2048_Y - connect \main_sdram_command_issue_we $and$ls180.v:6495$2052_Y + connect \main_sdram_command_issue_re $and$ls180.v:6497$2048_Y + connect \main_sdram_command_issue_we $and$ls180.v:6498$2052_Y connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6497$2055_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6498$2059_Y + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6500$2055_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6501$2059_Y connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6500$2062_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6501$2066_Y + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6503$2062_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6504$2066_Y connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6503$2069_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6504$2073_Y + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6506$2069_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6507$2073_Y connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6506$2076_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6507$2080_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6509$2076_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6510$2080_Y connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6509$2083_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6510$2087_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6512$2083_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6513$2087_Y connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6512$2090_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6513$2094_Y + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6515$2090_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6516$2094_Y connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6515$2097_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6516$2101_Y + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6518$2097_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6519$2101_Y connect \main_sdram_sel \main_sdram_storage [0] connect \main_sdram_cke \main_sdram_storage [1] connect \main_sdram_odt \main_sdram_storage [2] @@ -300231,28 +302740,28 @@ module \ls180 connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6531$2102_Y + connect \builder_csrbank10_sel $eq$ls180.v:6534$2102_Y connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6533$2105_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6534$2109_Y + connect \builder_csrbank10_control1_re $and$ls180.v:6536$2105_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6537$2109_Y connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6536$2112_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6537$2116_Y + connect \builder_csrbank10_control0_re $and$ls180.v:6539$2112_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6540$2116_Y connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6539$2119_Y - connect \builder_csrbank10_status_we $and$ls180.v:6540$2123_Y + connect \builder_csrbank10_status_re $and$ls180.v:6542$2119_Y + connect \builder_csrbank10_status_we $and$ls180.v:6543$2123_Y connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6542$2126_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6543$2130_Y + connect \builder_csrbank10_mosi0_re $and$ls180.v:6545$2126_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6546$2130_Y connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6545$2133_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6546$2137_Y + connect \builder_csrbank10_miso_re $and$ls180.v:6548$2133_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6549$2137_Y connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6548$2140_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6549$2144_Y + connect \builder_csrbank10_cs0_re $and$ls180.v:6551$2140_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6552$2144_Y connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6551$2147_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6552$2151_Y + connect \builder_csrbank10_loopback0_re $and$ls180.v:6554$2147_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6555$2151_Y connect \main_spimaster10_length \main_spimaster11_storage [15:8] connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] @@ -300265,34 +302774,34 @@ module \ls180 connect \main_spimaster20_sel \main_spimaster21_storage connect \builder_csrbank10_cs0_w \main_spimaster21_storage connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6571$2153_Y + connect \builder_csrbank11_sel $eq$ls180.v:6574$2153_Y connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6573$2156_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6574$2160_Y + connect \builder_csrbank11_control1_re $and$ls180.v:6576$2156_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6577$2160_Y connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6576$2163_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6577$2167_Y + connect \builder_csrbank11_control0_re $and$ls180.v:6579$2163_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6580$2167_Y connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6579$2170_Y - connect \builder_csrbank11_status_we $and$ls180.v:6580$2174_Y + connect \builder_csrbank11_status_re $and$ls180.v:6582$2170_Y + connect \builder_csrbank11_status_we $and$ls180.v:6583$2174_Y connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6582$2177_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6583$2181_Y + connect \builder_csrbank11_mosi0_re $and$ls180.v:6585$2177_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6586$2181_Y connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6585$2184_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6586$2188_Y + connect \builder_csrbank11_miso_re $and$ls180.v:6588$2184_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6589$2188_Y connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6588$2191_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6589$2195_Y + connect \builder_csrbank11_cs0_re $and$ls180.v:6591$2191_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6592$2195_Y connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6591$2198_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6592$2202_Y + connect \builder_csrbank11_loopback0_re $and$ls180.v:6594$2198_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6595$2202_Y connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6594$2205_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6595$2209_Y + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6597$2205_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6598$2209_Y connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6597$2212_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6598$2216_Y + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6600$2212_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6601$2216_Y connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] @@ -300307,58 +302816,58 @@ module \ls180 connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6619$2218_Y + connect \builder_csrbank12_sel $eq$ls180.v:6622$2218_Y connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6621$2221_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6622$2225_Y + connect \builder_csrbank12_load3_re $and$ls180.v:6624$2221_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6625$2225_Y connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6624$2228_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6625$2232_Y + connect \builder_csrbank12_load2_re $and$ls180.v:6627$2228_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6628$2232_Y connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6627$2235_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6628$2239_Y + connect \builder_csrbank12_load1_re $and$ls180.v:6630$2235_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6631$2239_Y connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6630$2242_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6631$2246_Y + connect \builder_csrbank12_load0_re $and$ls180.v:6633$2242_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6634$2246_Y connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6633$2249_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6634$2253_Y + connect \builder_csrbank12_reload3_re $and$ls180.v:6636$2249_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6637$2253_Y connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6636$2256_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6637$2260_Y + connect \builder_csrbank12_reload2_re $and$ls180.v:6639$2256_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6640$2260_Y connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6639$2263_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6640$2267_Y + connect \builder_csrbank12_reload1_re $and$ls180.v:6642$2263_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6643$2267_Y connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6642$2270_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6643$2274_Y + connect \builder_csrbank12_reload0_re $and$ls180.v:6645$2270_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6646$2274_Y connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6645$2277_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6646$2281_Y + connect \builder_csrbank12_en0_re $and$ls180.v:6648$2277_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6649$2281_Y connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6648$2284_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6649$2288_Y + connect \builder_csrbank12_update_value0_re $and$ls180.v:6651$2284_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6652$2288_Y connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6651$2291_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6652$2295_Y + connect \builder_csrbank12_value3_re $and$ls180.v:6654$2291_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6655$2295_Y connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6654$2298_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6655$2302_Y + connect \builder_csrbank12_value2_re $and$ls180.v:6657$2298_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6658$2302_Y connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6657$2305_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6658$2309_Y + connect \builder_csrbank12_value1_re $and$ls180.v:6660$2305_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6661$2309_Y connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6660$2312_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6661$2316_Y + connect \builder_csrbank12_value0_re $and$ls180.v:6663$2312_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6664$2316_Y connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6663$2319_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6664$2323_Y + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6666$2319_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6667$2323_Y connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6666$2326_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6667$2330_Y + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6669$2326_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6670$2330_Y connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6669$2333_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6670$2337_Y + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6672$2333_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6673$2337_Y connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] @@ -300375,31 +302884,31 @@ module \ls180 connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] connect \main_libresocsim_value_we \builder_csrbank12_value0_we connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6687$2338_Y + connect \builder_csrbank13_sel $eq$ls180.v:6690$2338_Y connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6689$2341_Y - connect \main_uart_rxtx_we $and$ls180.v:6690$2345_Y + connect \main_uart_rxtx_re $and$ls180.v:6692$2341_Y + connect \main_uart_rxtx_we $and$ls180.v:6693$2345_Y connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6692$2348_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6693$2352_Y + connect \builder_csrbank13_txfull_re $and$ls180.v:6695$2348_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6696$2352_Y connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6695$2355_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6696$2359_Y + connect \builder_csrbank13_rxempty_re $and$ls180.v:6698$2355_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6699$2359_Y connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6698$2362_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6699$2366_Y + connect \main_uart_eventmanager_status_re $and$ls180.v:6701$2362_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6702$2366_Y connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6701$2369_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6702$2373_Y + connect \main_uart_eventmanager_pending_re $and$ls180.v:6704$2369_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6705$2373_Y connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6704$2376_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6705$2380_Y + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6707$2376_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6708$2380_Y connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6707$2383_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6708$2387_Y + connect \builder_csrbank13_txempty_re $and$ls180.v:6710$2383_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6711$2387_Y connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6710$2390_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6711$2394_Y + connect \builder_csrbank13_rxfull_re $and$ls180.v:6713$2390_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6714$2394_Y connect \builder_csrbank13_txfull_w \main_uart_txfull_status connect \main_uart_txfull_we \builder_csrbank13_txfull_we connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status @@ -300409,19 +302918,19 @@ module \ls180 connect \main_uart_txempty_we \builder_csrbank13_txempty_we connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6721$2395_Y + connect \builder_csrbank14_sel $eq$ls180.v:6724$2395_Y connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6723$2398_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6724$2402_Y + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6726$2398_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6727$2402_Y connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6726$2405_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6727$2409_Y + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6729$2405_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6730$2409_Y connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6729$2412_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6730$2416_Y + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6732$2412_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6733$2416_Y connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6732$2419_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6733$2423_Y + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6735$2419_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6736$2423_Y connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] @@ -300475,7 +302984,7 @@ module \ls180 connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6787$2437_Y + connect \builder_csr_interconnect_dat_r $or$ls180.v:6790$2437_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -300552,59 +303061,59 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10370$2916_DATA - connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10398$2942_DATA - connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10426$2968_DATA - connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10454$2994_DATA - connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10482$3020_DATA + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10373$2916_DATA + connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10401$2942_DATA + connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10429$2968_DATA + connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10457$2994_DATA + connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10485$3020_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10500$3027_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10503$3027_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10514$3034_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10517$3034_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10528$3041_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10531$3041_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10542$3048_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10545$3048_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10590$3069_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10593$3069_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10604$3076_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3076_DATA end -attribute \src "libresoc.v:143116.1-143174.10" +attribute \src "libresoc.v:144930.1-144988.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:143117.7-143117.20" + attribute \src "libresoc.v:144931.7-144931.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143162.3-143170.6" - wire $0\q_int$next[0:0]$7056 - attribute \src "libresoc.v:143160.3-143161.27" + attribute \src "libresoc.v:144976.3-144984.6" + wire $0\q_int$next[0:0]$7101 + attribute \src "libresoc.v:144974.3-144975.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143162.3-143170.6" - wire $1\q_int$next[0:0]$7057 - attribute \src "libresoc.v:143139.7-143139.19" + attribute \src "libresoc.v:144976.3-144984.6" + wire $1\q_int$next[0:0]$7102 + attribute \src "libresoc.v:144953.7-144953.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143152.17-143152.96" - wire $and$libresoc.v:143152$7046_Y - attribute \src "libresoc.v:143157.17-143157.96" - wire $and$libresoc.v:143157$7051_Y - attribute \src "libresoc.v:143154.18-143154.93" - wire $not$libresoc.v:143154$7048_Y - attribute \src "libresoc.v:143156.17-143156.92" - wire $not$libresoc.v:143156$7050_Y - attribute \src "libresoc.v:143159.17-143159.92" - wire $not$libresoc.v:143159$7053_Y - attribute \src "libresoc.v:143153.18-143153.98" - wire $or$libresoc.v:143153$7047_Y - attribute \src "libresoc.v:143155.18-143155.99" - wire $or$libresoc.v:143155$7049_Y - attribute \src "libresoc.v:143158.17-143158.97" - wire $or$libresoc.v:143158$7052_Y + attribute \src "libresoc.v:144966.17-144966.96" + wire $and$libresoc.v:144966$7091_Y + attribute \src "libresoc.v:144971.17-144971.96" + wire $and$libresoc.v:144971$7096_Y + attribute \src "libresoc.v:144968.18-144968.93" + wire $not$libresoc.v:144968$7093_Y + attribute \src "libresoc.v:144970.17-144970.92" + wire $not$libresoc.v:144970$7095_Y + attribute \src "libresoc.v:144973.17-144973.92" + wire $not$libresoc.v:144973$7098_Y + attribute \src "libresoc.v:144967.18-144967.98" + wire $or$libresoc.v:144967$7092_Y + attribute \src "libresoc.v:144969.18-144969.99" + wire $or$libresoc.v:144969$7094_Y + attribute \src "libresoc.v:144972.17-144972.97" + wire $or$libresoc.v:144972$7097_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -300621,11 +303130,11 @@ module \lsd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:143117.7-143117.15" + attribute \src "libresoc.v:144931.7-144931.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -300642,7 +303151,7 @@ module \lsd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:143152$7046 + cell $and $and$libresoc.v:144966$7091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300650,10 +303159,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143152$7046_Y + connect \Y $and$libresoc.v:144966$7091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:143157$7051 + cell $and $and$libresoc.v:144971$7096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300661,34 +303170,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143157$7051_Y + connect \Y $and$libresoc.v:144971$7096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:143154$7048 + cell $not $not$libresoc.v:144968$7093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:143154$7048_Y + connect \Y $not$libresoc.v:144968$7093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:143156$7050 + cell $not $not$libresoc.v:144970$7095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:143156$7050_Y + connect \Y $not$libresoc.v:144970$7095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:143159$7053 + cell $not $not$libresoc.v:144973$7098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:143159$7053_Y + connect \Y $not$libresoc.v:144973$7098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:143153$7047 + cell $or $or$libresoc.v:144967$7092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300696,10 +303205,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:143153$7047_Y + connect \Y $or$libresoc.v:144967$7092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:143155$7049 + cell $or $or$libresoc.v:144969$7094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300707,10 +303216,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:143155$7049_Y + connect \Y $or$libresoc.v:144969$7094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:143158$7052 + cell $or $or$libresoc.v:144972$7097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300718,39 +303227,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:143158$7052_Y + connect \Y $or$libresoc.v:144972$7097_Y end - attribute \src "libresoc.v:143117.7-143117.20" - process $proc$libresoc.v:143117$7058 + attribute \src "libresoc.v:144931.7-144931.20" + process $proc$libresoc.v:144931$7103 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143139.7-143139.19" - process $proc$libresoc.v:143139$7059 + attribute \src "libresoc.v:144953.7-144953.19" + process $proc$libresoc.v:144953$7104 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143160.3-143161.27" - process $proc$libresoc.v:143160$7054 + attribute \src "libresoc.v:144974.3-144975.27" + process $proc$libresoc.v:144974$7099 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143162.3-143170.6" - process $proc$libresoc.v:143162$7055 + attribute \src "libresoc.v:144976.3-144984.6" + process $proc$libresoc.v:144976$7100 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7056 $1\q_int$next[0:0]$7057 - attribute \src "libresoc.v:143163.5-143163.29" + assign $0\q_int$next[0:0]$7101 $1\q_int$next[0:0]$7102 + attribute \src "libresoc.v:144977.5-144977.29" switch \initial - attribute \src "libresoc.v:143163.9-143163.17" + attribute \src "libresoc.v:144977.9-144977.17" case 1'1 case end @@ -300759,266 +303268,266 @@ module \lsd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7057 1'0 + assign $1\q_int$next[0:0]$7102 1'0 case - assign $1\q_int$next[0:0]$7057 \$5 + assign $1\q_int$next[0:0]$7102 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7056 + update \q_int$next $0\q_int$next[0:0]$7101 end - connect \$9 $and$libresoc.v:143152$7046_Y - connect \$11 $or$libresoc.v:143153$7047_Y - connect \$13 $not$libresoc.v:143154$7048_Y - connect \$15 $or$libresoc.v:143155$7049_Y - connect \$1 $not$libresoc.v:143156$7050_Y - connect \$3 $and$libresoc.v:143157$7051_Y - connect \$5 $or$libresoc.v:143158$7052_Y - connect \$7 $not$libresoc.v:143159$7053_Y + connect \$9 $and$libresoc.v:144966$7091_Y + connect \$11 $or$libresoc.v:144967$7092_Y + connect \$13 $not$libresoc.v:144968$7093_Y + connect \$15 $or$libresoc.v:144969$7094_Y + connect \$1 $not$libresoc.v:144970$7095_Y + connect \$3 $and$libresoc.v:144971$7096_Y + connect \$5 $or$libresoc.v:144972$7097_Y + connect \$7 $not$libresoc.v:144973$7098_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:143178.1-143712.10" +attribute \src "libresoc.v:144992.1-145526.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:143566.3-143591.6" - wire width 45 $0\dbus__adr$next[44:0]$7145 - attribute \src "libresoc.v:143416.3-143417.35" + attribute \src "libresoc.v:145380.3-145405.6" + wire width 45 $0\dbus__adr$next[44:0]$7190 + attribute \src "libresoc.v:145230.3-145231.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:143426.3-143453.6" - wire $0\dbus__cyc$next[0:0]$7119 - attribute \src "libresoc.v:143424.3-143425.35" + attribute \src "libresoc.v:145240.3-145267.6" + wire $0\dbus__cyc$next[0:0]$7164 + attribute \src "libresoc.v:145238.3-145239.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:143618.3-143643.6" - wire width 64 $0\dbus__dat_w$next[63:0]$7155 - attribute \src "libresoc.v:143412.3-143413.39" + attribute \src "libresoc.v:145432.3-145457.6" + wire width 64 $0\dbus__dat_w$next[63:0]$7200 + attribute \src "libresoc.v:145226.3-145227.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:143510.3-143540.6" - wire width 8 $0\dbus__sel$next[7:0]$7133 - attribute \src "libresoc.v:143420.3-143421.35" + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $0\dbus__sel$next[7:0]$7178 + attribute \src "libresoc.v:145234.3-145235.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:143454.3-143481.6" - wire $0\dbus__stb$next[0:0]$7125 - attribute \src "libresoc.v:143422.3-143423.35" + attribute \src "libresoc.v:145268.3-145295.6" + wire $0\dbus__stb$next[0:0]$7170 + attribute \src "libresoc.v:145236.3-145237.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:143592.3-143617.6" - wire $0\dbus__we$next[0:0]$7150 - attribute \src "libresoc.v:143414.3-143415.33" + attribute \src "libresoc.v:145406.3-145431.6" + wire $0\dbus__we$next[0:0]$7195 + attribute \src "libresoc.v:145228.3-145229.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:143179.7-143179.20" + attribute \src "libresoc.v:144993.7-144993.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143690.3-143709.6" - wire width 45 $0\m_badaddr_o$next[44:0]$7170 - attribute \src "libresoc.v:143406.3-143407.39" + attribute \src "libresoc.v:145504.3-145523.6" + wire width 45 $0\m_badaddr_o$next[44:0]$7215 + attribute \src "libresoc.v:145220.3-145221.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:143492.3-143509.6" + attribute \src "libresoc.v:145306.3-145323.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:143541.3-143565.6" - wire width 64 $0\m_ld_data_o$next[63:0]$7139 - attribute \src "libresoc.v:143418.3-143419.39" + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $0\m_ld_data_o$next[63:0]$7184 + attribute \src "libresoc.v:145232.3-145233.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:143644.3-143666.6" - wire $0\m_load_err_o$next[0:0]$7160 - attribute \src "libresoc.v:143410.3-143411.41" + attribute \src "libresoc.v:145458.3-145480.6" + wire $0\m_load_err_o$next[0:0]$7205 + attribute \src "libresoc.v:145224.3-145225.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:143667.3-143689.6" - wire $0\m_store_err_o$next[0:0]$7165 - attribute \src "libresoc.v:143408.3-143409.43" + attribute \src "libresoc.v:145481.3-145503.6" + wire $0\m_store_err_o$next[0:0]$7210 + attribute \src "libresoc.v:145222.3-145223.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:143482.3-143491.6" + attribute \src "libresoc.v:145296.3-145305.6" wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:143566.3-143591.6" - wire width 45 $1\dbus__adr$next[44:0]$7146 - attribute \src "libresoc.v:143284.14-143284.42" + attribute \src "libresoc.v:145380.3-145405.6" + wire width 45 $1\dbus__adr$next[44:0]$7191 + attribute \src "libresoc.v:145098.14-145098.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:143426.3-143453.6" - wire $1\dbus__cyc$next[0:0]$7120 - attribute \src "libresoc.v:143289.7-143289.23" + attribute \src "libresoc.v:145240.3-145267.6" + wire $1\dbus__cyc$next[0:0]$7165 + attribute \src "libresoc.v:145103.7-145103.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:143618.3-143643.6" - wire width 64 $1\dbus__dat_w$next[63:0]$7156 - attribute \src "libresoc.v:143296.14-143296.48" + attribute \src "libresoc.v:145432.3-145457.6" + wire width 64 $1\dbus__dat_w$next[63:0]$7201 + attribute \src "libresoc.v:145110.14-145110.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:143510.3-143540.6" - wire width 8 $1\dbus__sel$next[7:0]$7134 - attribute \src "libresoc.v:143303.13-143303.30" + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $1\dbus__sel$next[7:0]$7179 + attribute \src "libresoc.v:145117.13-145117.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:143454.3-143481.6" - wire $1\dbus__stb$next[0:0]$7126 - attribute \src "libresoc.v:143308.7-143308.23" + attribute \src "libresoc.v:145268.3-145295.6" + wire $1\dbus__stb$next[0:0]$7171 + attribute \src "libresoc.v:145122.7-145122.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:143592.3-143617.6" - wire $1\dbus__we$next[0:0]$7151 - attribute \src "libresoc.v:143313.7-143313.22" + attribute \src "libresoc.v:145406.3-145431.6" + wire $1\dbus__we$next[0:0]$7196 + attribute \src "libresoc.v:145127.7-145127.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:143690.3-143709.6" - wire width 45 $1\m_badaddr_o$next[44:0]$7171 - attribute \src "libresoc.v:143317.14-143317.44" + attribute \src "libresoc.v:145504.3-145523.6" + wire width 45 $1\m_badaddr_o$next[44:0]$7216 + attribute \src "libresoc.v:145131.14-145131.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:143492.3-143509.6" + attribute \src "libresoc.v:145306.3-145323.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:143541.3-143565.6" - wire width 64 $1\m_ld_data_o$next[63:0]$7140 - attribute \src "libresoc.v:143324.14-143324.48" + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $1\m_ld_data_o$next[63:0]$7185 + attribute \src "libresoc.v:145138.14-145138.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:143644.3-143666.6" - wire $1\m_load_err_o$next[0:0]$7161 - attribute \src "libresoc.v:143328.7-143328.26" + attribute \src "libresoc.v:145458.3-145480.6" + wire $1\m_load_err_o$next[0:0]$7206 + attribute \src "libresoc.v:145142.7-145142.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:143667.3-143689.6" - wire $1\m_store_err_o$next[0:0]$7166 - attribute \src "libresoc.v:143334.7-143334.27" + attribute \src "libresoc.v:145481.3-145503.6" + wire $1\m_store_err_o$next[0:0]$7211 + attribute \src "libresoc.v:145148.7-145148.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:143482.3-143491.6" + attribute \src "libresoc.v:145296.3-145305.6" wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:143566.3-143591.6" - wire width 45 $2\dbus__adr$next[44:0]$7147 - attribute \src "libresoc.v:143426.3-143453.6" - wire $2\dbus__cyc$next[0:0]$7121 - attribute \src "libresoc.v:143618.3-143643.6" - wire width 64 $2\dbus__dat_w$next[63:0]$7157 - attribute \src "libresoc.v:143510.3-143540.6" - wire width 8 $2\dbus__sel$next[7:0]$7135 - attribute \src "libresoc.v:143454.3-143481.6" - wire $2\dbus__stb$next[0:0]$7127 - attribute \src "libresoc.v:143592.3-143617.6" - wire $2\dbus__we$next[0:0]$7152 - attribute \src "libresoc.v:143690.3-143709.6" - wire width 45 $2\m_badaddr_o$next[44:0]$7172 - attribute \src "libresoc.v:143492.3-143509.6" + attribute \src "libresoc.v:145380.3-145405.6" + wire width 45 $2\dbus__adr$next[44:0]$7192 + attribute \src "libresoc.v:145240.3-145267.6" + wire $2\dbus__cyc$next[0:0]$7166 + attribute \src "libresoc.v:145432.3-145457.6" + wire width 64 $2\dbus__dat_w$next[63:0]$7202 + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $2\dbus__sel$next[7:0]$7180 + attribute \src "libresoc.v:145268.3-145295.6" + wire $2\dbus__stb$next[0:0]$7172 + attribute \src "libresoc.v:145406.3-145431.6" + wire $2\dbus__we$next[0:0]$7197 + attribute \src "libresoc.v:145504.3-145523.6" + wire width 45 $2\m_badaddr_o$next[44:0]$7217 + attribute \src "libresoc.v:145306.3-145323.6" wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:143541.3-143565.6" - wire width 64 $2\m_ld_data_o$next[63:0]$7141 - attribute \src "libresoc.v:143644.3-143666.6" - wire $2\m_load_err_o$next[0:0]$7162 - attribute \src "libresoc.v:143667.3-143689.6" - wire $2\m_store_err_o$next[0:0]$7167 - attribute \src "libresoc.v:143566.3-143591.6" - wire width 45 $3\dbus__adr$next[44:0]$7148 - attribute \src "libresoc.v:143426.3-143453.6" - wire $3\dbus__cyc$next[0:0]$7122 - attribute \src "libresoc.v:143618.3-143643.6" - wire width 64 $3\dbus__dat_w$next[63:0]$7158 - attribute \src "libresoc.v:143510.3-143540.6" - wire width 8 $3\dbus__sel$next[7:0]$7136 - attribute \src "libresoc.v:143454.3-143481.6" - wire $3\dbus__stb$next[0:0]$7128 - attribute \src "libresoc.v:143592.3-143617.6" - wire $3\dbus__we$next[0:0]$7153 - attribute \src "libresoc.v:143690.3-143709.6" - wire width 45 $3\m_badaddr_o$next[44:0]$7173 - attribute \src "libresoc.v:143541.3-143565.6" - wire width 64 $3\m_ld_data_o$next[63:0]$7142 - attribute \src "libresoc.v:143644.3-143666.6" - wire $3\m_load_err_o$next[0:0]$7163 - attribute \src "libresoc.v:143667.3-143689.6" - wire $3\m_store_err_o$next[0:0]$7168 - attribute \src "libresoc.v:143426.3-143453.6" - wire $4\dbus__cyc$next[0:0]$7123 - attribute \src "libresoc.v:143510.3-143540.6" - wire width 8 $4\dbus__sel$next[7:0]$7137 - attribute \src "libresoc.v:143454.3-143481.6" - wire $4\dbus__stb$next[0:0]$7129 - attribute \src "libresoc.v:143541.3-143565.6" - wire width 64 $4\m_ld_data_o$next[63:0]$7143 - attribute \src "libresoc.v:143362.18-143362.116" - wire $and$libresoc.v:143362$7064_Y - attribute \src "libresoc.v:143365.18-143365.111" - wire $and$libresoc.v:143365$7067_Y - attribute \src "libresoc.v:143370.18-143370.116" - wire $and$libresoc.v:143370$7072_Y - attribute \src "libresoc.v:143372.18-143372.111" - wire $and$libresoc.v:143372$7074_Y - attribute \src "libresoc.v:143374.17-143374.114" - wire $and$libresoc.v:143374$7076_Y - attribute \src "libresoc.v:143378.18-143378.116" - wire $and$libresoc.v:143378$7080_Y - attribute \src "libresoc.v:143380.18-143380.111" - wire $and$libresoc.v:143380$7082_Y - attribute \src "libresoc.v:143386.18-143386.116" - wire $and$libresoc.v:143386$7088_Y - attribute \src "libresoc.v:143388.18-143388.111" - wire $and$libresoc.v:143388$7090_Y - attribute \src "libresoc.v:143390.18-143390.116" - wire $and$libresoc.v:143390$7092_Y - attribute \src "libresoc.v:143392.18-143392.111" - wire $and$libresoc.v:143392$7094_Y - attribute \src "libresoc.v:143394.18-143394.116" - wire $and$libresoc.v:143394$7096_Y - attribute \src "libresoc.v:143396.17-143396.108" - wire $and$libresoc.v:143396$7098_Y - attribute \src "libresoc.v:143397.18-143397.111" - wire $and$libresoc.v:143397$7099_Y - attribute \src "libresoc.v:143398.18-143398.120" - wire $and$libresoc.v:143398$7100_Y - attribute \src "libresoc.v:143401.18-143401.120" - wire $and$libresoc.v:143401$7103_Y - attribute \src "libresoc.v:143403.18-143403.120" - wire $and$libresoc.v:143403$7105_Y - attribute \src "libresoc.v:143359.18-143359.110" - wire $not$libresoc.v:143359$7061_Y - attribute \src "libresoc.v:143364.18-143364.110" - wire $not$libresoc.v:143364$7066_Y - attribute \src "libresoc.v:143367.18-143367.110" - wire $not$libresoc.v:143367$7069_Y - attribute \src "libresoc.v:143371.18-143371.110" - wire $not$libresoc.v:143371$7073_Y - attribute \src "libresoc.v:143375.18-143375.110" - wire $not$libresoc.v:143375$7077_Y - attribute \src "libresoc.v:143379.18-143379.110" - wire $not$libresoc.v:143379$7081_Y - attribute \src "libresoc.v:143382.18-143382.110" - wire $not$libresoc.v:143382$7084_Y - attribute \src "libresoc.v:143385.17-143385.109" - wire $not$libresoc.v:143385$7087_Y - attribute \src "libresoc.v:143387.18-143387.110" - wire $not$libresoc.v:143387$7089_Y - attribute \src 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wire $or$libresoc.v:143368$7070_Y - attribute \src "libresoc.v:143369.18-143369.114" - wire $or$libresoc.v:143369$7071_Y - attribute \src "libresoc.v:143373.18-143373.120" - wire $or$libresoc.v:143373$7075_Y - attribute \src "libresoc.v:143376.18-143376.111" - wire $or$libresoc.v:143376$7078_Y - attribute \src "libresoc.v:143377.18-143377.114" - wire $or$libresoc.v:143377$7079_Y - attribute \src "libresoc.v:143381.18-143381.120" - wire $or$libresoc.v:143381$7083_Y - attribute \src "libresoc.v:143383.18-143383.111" - wire $or$libresoc.v:143383$7085_Y - attribute \src "libresoc.v:143384.18-143384.114" - wire $or$libresoc.v:143384$7086_Y - attribute \src "libresoc.v:143389.18-143389.114" - wire $or$libresoc.v:143389$7091_Y - attribute \src "libresoc.v:143393.18-143393.114" - wire $or$libresoc.v:143393$7095_Y - attribute \src "libresoc.v:143405.18-143405.127" - wire $or$libresoc.v:143405$7107_Y + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $2\m_ld_data_o$next[63:0]$7186 + attribute \src "libresoc.v:145458.3-145480.6" + wire $2\m_load_err_o$next[0:0]$7207 + attribute \src "libresoc.v:145481.3-145503.6" + wire $2\m_store_err_o$next[0:0]$7212 + attribute \src "libresoc.v:145380.3-145405.6" + wire width 45 $3\dbus__adr$next[44:0]$7193 + attribute \src "libresoc.v:145240.3-145267.6" + wire $3\dbus__cyc$next[0:0]$7167 + attribute \src "libresoc.v:145432.3-145457.6" + wire width 64 $3\dbus__dat_w$next[63:0]$7203 + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $3\dbus__sel$next[7:0]$7181 + attribute \src "libresoc.v:145268.3-145295.6" + wire $3\dbus__stb$next[0:0]$7173 + attribute \src "libresoc.v:145406.3-145431.6" + wire $3\dbus__we$next[0:0]$7198 + attribute \src "libresoc.v:145504.3-145523.6" + wire width 45 $3\m_badaddr_o$next[44:0]$7218 + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $3\m_ld_data_o$next[63:0]$7187 + attribute \src "libresoc.v:145458.3-145480.6" + wire $3\m_load_err_o$next[0:0]$7208 + attribute \src "libresoc.v:145481.3-145503.6" + wire $3\m_store_err_o$next[0:0]$7213 + attribute \src "libresoc.v:145240.3-145267.6" + wire $4\dbus__cyc$next[0:0]$7168 + attribute \src "libresoc.v:145324.3-145354.6" + wire width 8 $4\dbus__sel$next[7:0]$7182 + attribute \src "libresoc.v:145268.3-145295.6" + wire $4\dbus__stb$next[0:0]$7174 + attribute \src "libresoc.v:145355.3-145379.6" + wire width 64 $4\m_ld_data_o$next[63:0]$7188 + attribute \src "libresoc.v:145176.18-145176.116" + wire $and$libresoc.v:145176$7109_Y + attribute \src "libresoc.v:145179.18-145179.111" + wire $and$libresoc.v:145179$7112_Y + attribute \src "libresoc.v:145184.18-145184.116" + wire $and$libresoc.v:145184$7117_Y + attribute \src "libresoc.v:145186.18-145186.111" + wire $and$libresoc.v:145186$7119_Y + attribute \src "libresoc.v:145188.17-145188.114" + wire $and$libresoc.v:145188$7121_Y + attribute \src "libresoc.v:145192.18-145192.116" + wire $and$libresoc.v:145192$7125_Y + attribute \src "libresoc.v:145194.18-145194.111" + wire $and$libresoc.v:145194$7127_Y + attribute \src "libresoc.v:145200.18-145200.116" + wire $and$libresoc.v:145200$7133_Y + attribute \src "libresoc.v:145202.18-145202.111" + wire $and$libresoc.v:145202$7135_Y + attribute \src "libresoc.v:145204.18-145204.116" + wire $and$libresoc.v:145204$7137_Y + attribute \src "libresoc.v:145206.18-145206.111" + wire $and$libresoc.v:145206$7139_Y + attribute \src "libresoc.v:145208.18-145208.116" + wire $and$libresoc.v:145208$7141_Y + attribute \src "libresoc.v:145210.17-145210.108" + wire $and$libresoc.v:145210$7143_Y + attribute \src "libresoc.v:145211.18-145211.111" + wire $and$libresoc.v:145211$7144_Y + attribute \src "libresoc.v:145212.18-145212.120" + wire $and$libresoc.v:145212$7145_Y + attribute \src "libresoc.v:145215.18-145215.120" + wire $and$libresoc.v:145215$7148_Y + attribute \src "libresoc.v:145217.18-145217.120" + wire $and$libresoc.v:145217$7150_Y + attribute \src "libresoc.v:145173.18-145173.110" + wire $not$libresoc.v:145173$7106_Y + attribute \src "libresoc.v:145178.18-145178.110" + wire $not$libresoc.v:145178$7111_Y + attribute \src "libresoc.v:145181.18-145181.110" + wire $not$libresoc.v:145181$7114_Y + attribute \src "libresoc.v:145185.18-145185.110" + wire $not$libresoc.v:145185$7118_Y + attribute \src "libresoc.v:145189.18-145189.110" + wire $not$libresoc.v:145189$7122_Y + attribute \src "libresoc.v:145193.18-145193.110" + wire $not$libresoc.v:145193$7126_Y + attribute \src "libresoc.v:145196.18-145196.110" + wire $not$libresoc.v:145196$7129_Y + attribute \src "libresoc.v:145199.17-145199.109" + wire $not$libresoc.v:145199$7132_Y + attribute \src "libresoc.v:145201.18-145201.110" + wire $not$libresoc.v:145201$7134_Y + attribute \src "libresoc.v:145205.18-145205.110" + wire $not$libresoc.v:145205$7138_Y + attribute \src "libresoc.v:145209.18-145209.110" + wire $not$libresoc.v:145209$7142_Y + attribute \src "libresoc.v:145213.18-145213.110" + wire $not$libresoc.v:145213$7146_Y + attribute \src "libresoc.v:145214.18-145214.109" + wire $not$libresoc.v:145214$7147_Y + attribute \src "libresoc.v:145216.18-145216.110" + wire $not$libresoc.v:145216$7149_Y + attribute \src "libresoc.v:145218.18-145218.110" + wire $not$libresoc.v:145218$7151_Y + attribute \src "libresoc.v:145172.17-145172.119" + wire $or$libresoc.v:145172$7105_Y + attribute \src "libresoc.v:145174.18-145174.110" + wire $or$libresoc.v:145174$7107_Y + attribute \src "libresoc.v:145175.18-145175.114" + wire $or$libresoc.v:145175$7108_Y + attribute \src "libresoc.v:145177.17-145177.113" + wire $or$libresoc.v:145177$7110_Y + attribute \src "libresoc.v:145180.18-145180.120" + wire $or$libresoc.v:145180$7113_Y + attribute \src "libresoc.v:145182.18-145182.111" + wire $or$libresoc.v:145182$7115_Y + attribute \src "libresoc.v:145183.18-145183.114" + wire $or$libresoc.v:145183$7116_Y + attribute \src "libresoc.v:145187.18-145187.120" + wire $or$libresoc.v:145187$7120_Y + attribute \src "libresoc.v:145190.18-145190.111" + wire $or$libresoc.v:145190$7123_Y + attribute \src "libresoc.v:145191.18-145191.114" + wire $or$libresoc.v:145191$7124_Y + attribute \src "libresoc.v:145195.18-145195.120" + wire $or$libresoc.v:145195$7128_Y + attribute \src "libresoc.v:145197.18-145197.111" + wire $or$libresoc.v:145197$7130_Y + attribute \src "libresoc.v:145198.18-145198.114" + wire $or$libresoc.v:145198$7131_Y + attribute \src "libresoc.v:145203.18-145203.114" + wire $or$libresoc.v:145203$7136_Y + attribute \src "libresoc.v:145207.18-145207.114" + wire $or$libresoc.v:145207$7140_Y + attribute \src "libresoc.v:145219.18-145219.127" + wire $or$libresoc.v:145219$7152_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" @@ -301115,9 +303624,9 @@ module \lsmem wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 13 \dbus__ack @@ -301149,7 +303658,7 @@ module \lsmem wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:143179.7-143179.15" + attribute \src "libresoc.v:144993.7-144993.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o @@ -301192,7 +303701,7 @@ module \lsmem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143362$7064 + cell $and $and$libresoc.v:145176$7109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301200,10 +303709,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:143362$7064_Y + connect \Y $and$libresoc.v:145176$7109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143365$7067 + cell $and $and$libresoc.v:145179$7112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301211,10 +303720,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:143365$7067_Y + connect \Y $and$libresoc.v:145179$7112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143370$7072 + cell $and $and$libresoc.v:145184$7117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301222,10 +303731,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:143370$7072_Y + connect \Y $and$libresoc.v:145184$7117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143372$7074 + cell $and $and$libresoc.v:145186$7119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301233,10 +303742,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:143372$7074_Y + connect \Y $and$libresoc.v:145186$7119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143374$7076 + cell $and $and$libresoc.v:145188$7121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301244,10 +303753,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:143374$7076_Y + connect \Y $and$libresoc.v:145188$7121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143378$7080 + cell $and $and$libresoc.v:145192$7125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301255,10 +303764,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:143378$7080_Y + connect \Y $and$libresoc.v:145192$7125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143380$7082 + cell $and $and$libresoc.v:145194$7127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301266,10 +303775,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:143380$7082_Y + connect \Y $and$libresoc.v:145194$7127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143386$7088 + cell $and $and$libresoc.v:145200$7133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301277,10 +303786,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:143386$7088_Y + connect \Y $and$libresoc.v:145200$7133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143388$7090 + cell $and $and$libresoc.v:145202$7135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301288,10 +303797,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:143388$7090_Y + connect \Y $and$libresoc.v:145202$7135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143390$7092 + cell $and $and$libresoc.v:145204$7137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301299,10 +303808,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:143390$7092_Y + connect \Y $and$libresoc.v:145204$7137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143392$7094 + cell $and $and$libresoc.v:145206$7139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301310,10 +303819,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:143392$7094_Y + connect \Y $and$libresoc.v:145206$7139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143394$7096 + cell $and $and$libresoc.v:145208$7141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301321,10 +303830,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:143394$7096_Y + connect \Y $and$libresoc.v:145208$7141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143396$7098 + cell $and $and$libresoc.v:145210$7143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301332,10 +303841,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:143396$7098_Y + connect \Y $and$libresoc.v:145210$7143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:143397$7099 + cell $and $and$libresoc.v:145211$7144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301343,10 +303852,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:143397$7099_Y + connect \Y $and$libresoc.v:145211$7144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:143398$7100 + cell $and $and$libresoc.v:145212$7145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301354,10 +303863,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:143398$7100_Y + connect \Y $and$libresoc.v:145212$7145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:143401$7103 + cell $and $and$libresoc.v:145215$7148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301365,10 +303874,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:143401$7103_Y + connect \Y $and$libresoc.v:145215$7148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:143403$7105 + cell $and $and$libresoc.v:145217$7150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301376,130 +303885,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:143403$7105_Y + connect \Y $and$libresoc.v:145217$7150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:143359$7061 + cell $not $not$libresoc.v:145173$7106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:143359$7061_Y + connect \Y $not$libresoc.v:145173$7106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:143364$7066 + cell $not $not$libresoc.v:145178$7111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:143364$7066_Y + connect \Y $not$libresoc.v:145178$7111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:143367$7069 + cell $not $not$libresoc.v:145181$7114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:143367$7069_Y + connect \Y $not$libresoc.v:145181$7114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:143371$7073 + cell $not $not$libresoc.v:145185$7118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:143371$7073_Y + connect \Y $not$libresoc.v:145185$7118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:143375$7077 + cell $not $not$libresoc.v:145189$7122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:143375$7077_Y + connect \Y $not$libresoc.v:145189$7122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:143379$7081 + cell $not $not$libresoc.v:145193$7126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:143379$7081_Y + connect \Y $not$libresoc.v:145193$7126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:143382$7084 + cell $not $not$libresoc.v:145196$7129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:143382$7084_Y + connect \Y $not$libresoc.v:145196$7129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:143385$7087 + cell $not $not$libresoc.v:145199$7132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:143385$7087_Y + connect \Y $not$libresoc.v:145199$7132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:143387$7089 + cell $not $not$libresoc.v:145201$7134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:143387$7089_Y + connect \Y $not$libresoc.v:145201$7134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:143391$7093 + cell $not $not$libresoc.v:145205$7138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:143391$7093_Y + connect \Y $not$libresoc.v:145205$7138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:143395$7097 + cell $not $not$libresoc.v:145209$7142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:143395$7097_Y + connect \Y $not$libresoc.v:145209$7142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:143399$7101 + cell $not $not$libresoc.v:145213$7146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:143399$7101_Y + connect \Y $not$libresoc.v:145213$7146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:143400$7102 + cell $not $not$libresoc.v:145214$7147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:143400$7102_Y + connect \Y $not$libresoc.v:145214$7147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:143402$7104 + cell $not $not$libresoc.v:145216$7149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:143402$7104_Y + connect \Y $not$libresoc.v:145216$7149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:143404$7106 + cell $not $not$libresoc.v:145218$7151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:143404$7106_Y + connect \Y $not$libresoc.v:145218$7151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:143358$7060 + cell $or $or$libresoc.v:145172$7105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301507,10 +304016,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:143358$7060_Y + connect \Y $or$libresoc.v:145172$7105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:143360$7062 + cell $or $or$libresoc.v:145174$7107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301518,10 +304027,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:143360$7062_Y + connect \Y $or$libresoc.v:145174$7107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:143361$7063 + cell $or $or$libresoc.v:145175$7108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301529,10 +304038,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:143361$7063_Y + connect \Y $or$libresoc.v:145175$7108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:143363$7065 + cell $or $or$libresoc.v:145177$7110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301540,10 +304049,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:143363$7065_Y + connect \Y $or$libresoc.v:145177$7110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:143366$7068 + cell $or $or$libresoc.v:145180$7113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301551,10 +304060,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:143366$7068_Y + connect \Y $or$libresoc.v:145180$7113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:143368$7070 + cell $or $or$libresoc.v:145182$7115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301562,10 +304071,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:143368$7070_Y + connect \Y $or$libresoc.v:145182$7115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:143369$7071 + cell $or $or$libresoc.v:145183$7116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301573,10 +304082,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:143369$7071_Y + connect \Y $or$libresoc.v:145183$7116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:143373$7075 + cell $or $or$libresoc.v:145187$7120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301584,10 +304093,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:143373$7075_Y + connect \Y $or$libresoc.v:145187$7120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:143376$7078 + cell $or $or$libresoc.v:145190$7123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301595,10 +304104,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:143376$7078_Y + connect \Y $or$libresoc.v:145190$7123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:143377$7079 + cell $or $or$libresoc.v:145191$7124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301606,10 +304115,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:143377$7079_Y + connect \Y $or$libresoc.v:145191$7124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:143381$7083 + cell $or $or$libresoc.v:145195$7128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301617,10 +304126,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:143381$7083_Y + connect \Y $or$libresoc.v:145195$7128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:143383$7085 + cell $or $or$libresoc.v:145197$7130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301628,10 +304137,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:143383$7085_Y + connect \Y $or$libresoc.v:145197$7130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:143384$7086 + cell $or $or$libresoc.v:145198$7131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301639,10 +304148,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:143384$7086_Y + connect \Y $or$libresoc.v:145198$7131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:143389$7091 + cell $or $or$libresoc.v:145203$7136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301650,10 +304159,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:143389$7091_Y + connect \Y $or$libresoc.v:145203$7136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:143393$7095 + cell $or $or$libresoc.v:145207$7140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301661,10 +304170,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:143393$7095_Y + connect \Y $or$libresoc.v:145207$7140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:143405$7107 + cell $or $or$libresoc.v:145219$7152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301672,175 +304181,175 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:143405$7107_Y + connect \Y $or$libresoc.v:145219$7152_Y end - attribute \src "libresoc.v:143179.7-143179.20" - process $proc$libresoc.v:143179$7174 + attribute \src "libresoc.v:144993.7-144993.20" + process $proc$libresoc.v:144993$7219 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143284.14-143284.42" - process $proc$libresoc.v:143284$7175 + attribute \src "libresoc.v:145098.14-145098.42" + process $proc$libresoc.v:145098$7220 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:143289.7-143289.23" - process $proc$libresoc.v:143289$7176 + attribute \src "libresoc.v:145103.7-145103.23" + process $proc$libresoc.v:145103$7221 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:143296.14-143296.48" - process $proc$libresoc.v:143296$7177 + attribute \src "libresoc.v:145110.14-145110.48" + process $proc$libresoc.v:145110$7222 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:143303.13-143303.30" - process $proc$libresoc.v:143303$7178 + attribute \src "libresoc.v:145117.13-145117.30" + process $proc$libresoc.v:145117$7223 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:143308.7-143308.23" - process $proc$libresoc.v:143308$7179 + attribute \src "libresoc.v:145122.7-145122.23" + process $proc$libresoc.v:145122$7224 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:143313.7-143313.22" - process $proc$libresoc.v:143313$7180 + attribute \src "libresoc.v:145127.7-145127.22" + process $proc$libresoc.v:145127$7225 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:143317.14-143317.44" - process $proc$libresoc.v:143317$7181 + attribute \src "libresoc.v:145131.14-145131.44" + process $proc$libresoc.v:145131$7226 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:143324.14-143324.48" - process $proc$libresoc.v:143324$7182 + attribute \src "libresoc.v:145138.14-145138.48" + process $proc$libresoc.v:145138$7227 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:143328.7-143328.26" - process $proc$libresoc.v:143328$7183 + attribute \src "libresoc.v:145142.7-145142.26" + process $proc$libresoc.v:145142$7228 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:143334.7-143334.27" - process $proc$libresoc.v:143334$7184 + attribute \src "libresoc.v:145148.7-145148.27" + process $proc$libresoc.v:145148$7229 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:143406.3-143407.39" - process $proc$libresoc.v:143406$7108 + attribute \src "libresoc.v:145220.3-145221.39" + process $proc$libresoc.v:145220$7153 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:143408.3-143409.43" - process $proc$libresoc.v:143408$7109 + attribute \src "libresoc.v:145222.3-145223.43" + process $proc$libresoc.v:145222$7154 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:143410.3-143411.41" - process $proc$libresoc.v:143410$7110 + attribute \src "libresoc.v:145224.3-145225.41" + process $proc$libresoc.v:145224$7155 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:143412.3-143413.39" - process $proc$libresoc.v:143412$7111 + attribute \src "libresoc.v:145226.3-145227.39" + process $proc$libresoc.v:145226$7156 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:143414.3-143415.33" - process $proc$libresoc.v:143414$7112 + attribute \src "libresoc.v:145228.3-145229.33" + process $proc$libresoc.v:145228$7157 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:143416.3-143417.35" - process $proc$libresoc.v:143416$7113 + attribute \src "libresoc.v:145230.3-145231.35" + process $proc$libresoc.v:145230$7158 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:143418.3-143419.39" - process $proc$libresoc.v:143418$7114 + attribute \src "libresoc.v:145232.3-145233.39" + process $proc$libresoc.v:145232$7159 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:143420.3-143421.35" - process $proc$libresoc.v:143420$7115 + attribute \src "libresoc.v:145234.3-145235.35" + process $proc$libresoc.v:145234$7160 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:143422.3-143423.35" - process $proc$libresoc.v:143422$7116 + attribute \src "libresoc.v:145236.3-145237.35" + process $proc$libresoc.v:145236$7161 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:143424.3-143425.35" - process $proc$libresoc.v:143424$7117 + attribute \src "libresoc.v:145238.3-145239.35" + process $proc$libresoc.v:145238$7162 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:143426.3-143453.6" - process $proc$libresoc.v:143426$7118 + attribute \src "libresoc.v:145240.3-145267.6" + process $proc$libresoc.v:145240$7163 assign { } { } assign { } { } assign { } { } - assign $0\dbus__cyc$next[0:0]$7119 $4\dbus__cyc$next[0:0]$7123 - attribute \src "libresoc.v:143427.5-143427.29" + assign $0\dbus__cyc$next[0:0]$7164 $4\dbus__cyc$next[0:0]$7168 + attribute \src "libresoc.v:145241.5-145241.29" switch \initial - attribute \src "libresoc.v:143427.9-143427.17" + attribute \src "libresoc.v:145241.9-145241.17" case 1'1 case end @@ -301849,53 +304358,53 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__cyc$next[0:0]$7120 $2\dbus__cyc$next[0:0]$7121 + assign $1\dbus__cyc$next[0:0]$7165 $2\dbus__cyc$next[0:0]$7166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$7 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__cyc$next[0:0]$7121 $3\dbus__cyc$next[0:0]$7122 + assign $2\dbus__cyc$next[0:0]$7166 $3\dbus__cyc$next[0:0]$7167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__cyc$next[0:0]$7122 1'0 + assign $3\dbus__cyc$next[0:0]$7167 1'0 case - assign $3\dbus__cyc$next[0:0]$7122 \dbus__cyc + assign $3\dbus__cyc$next[0:0]$7167 \dbus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__cyc$next[0:0]$7121 1'1 + assign $2\dbus__cyc$next[0:0]$7166 1'1 case - assign $2\dbus__cyc$next[0:0]$7121 \dbus__cyc + assign $2\dbus__cyc$next[0:0]$7166 \dbus__cyc end case - assign $1\dbus__cyc$next[0:0]$7120 \dbus__cyc + assign $1\dbus__cyc$next[0:0]$7165 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__cyc$next[0:0]$7123 1'0 + assign $4\dbus__cyc$next[0:0]$7168 1'0 case - assign $4\dbus__cyc$next[0:0]$7123 $1\dbus__cyc$next[0:0]$7120 + assign $4\dbus__cyc$next[0:0]$7168 $1\dbus__cyc$next[0:0]$7165 end sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7119 + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7164 end - attribute \src "libresoc.v:143454.3-143481.6" - process $proc$libresoc.v:143454$7124 + attribute \src "libresoc.v:145268.3-145295.6" + process $proc$libresoc.v:145268$7169 assign { } { } assign { } { } assign { } { } - assign $0\dbus__stb$next[0:0]$7125 $4\dbus__stb$next[0:0]$7129 - attribute \src "libresoc.v:143455.5-143455.29" + assign $0\dbus__stb$next[0:0]$7170 $4\dbus__stb$next[0:0]$7174 + attribute \src "libresoc.v:145269.5-145269.29" switch \initial - attribute \src "libresoc.v:143455.9-143455.17" + attribute \src "libresoc.v:145269.9-145269.17" case 1'1 case end @@ -301904,52 +304413,52 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__stb$next[0:0]$7126 $2\dbus__stb$next[0:0]$7127 + assign $1\dbus__stb$next[0:0]$7171 $2\dbus__stb$next[0:0]$7172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$21 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__stb$next[0:0]$7127 $3\dbus__stb$next[0:0]$7128 + assign $2\dbus__stb$next[0:0]$7172 $3\dbus__stb$next[0:0]$7173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__stb$next[0:0]$7128 1'0 + assign $3\dbus__stb$next[0:0]$7173 1'0 case - assign $3\dbus__stb$next[0:0]$7128 \dbus__stb + assign $3\dbus__stb$next[0:0]$7173 \dbus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__stb$next[0:0]$7127 1'1 + assign $2\dbus__stb$next[0:0]$7172 1'1 case - assign $2\dbus__stb$next[0:0]$7127 \dbus__stb + assign $2\dbus__stb$next[0:0]$7172 \dbus__stb end case - assign $1\dbus__stb$next[0:0]$7126 \dbus__stb + assign $1\dbus__stb$next[0:0]$7171 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__stb$next[0:0]$7129 1'0 + assign $4\dbus__stb$next[0:0]$7174 1'0 case - assign $4\dbus__stb$next[0:0]$7129 $1\dbus__stb$next[0:0]$7126 + assign $4\dbus__stb$next[0:0]$7174 $1\dbus__stb$next[0:0]$7171 end sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$7125 + update \dbus__stb$next $0\dbus__stb$next[0:0]$7170 end - attribute \src "libresoc.v:143482.3-143491.6" - process $proc$libresoc.v:143482$7130 + attribute \src "libresoc.v:145296.3-145305.6" + process $proc$libresoc.v:145296$7175 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:143483.5-143483.29" + attribute \src "libresoc.v:145297.5-145297.29" switch \initial - attribute \src "libresoc.v:143483.9-143483.17" + attribute \src "libresoc.v:145297.9-145297.17" case 1'1 case end @@ -301965,14 +304474,14 @@ module \lsmem sync always update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:143492.3-143509.6" - process $proc$libresoc.v:143492$7131 + attribute \src "libresoc.v:145306.3-145323.6" + process $proc$libresoc.v:145306$7176 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:143493.5-143493.29" + attribute \src "libresoc.v:145307.5-145307.29" switch \initial - attribute \src "libresoc.v:143493.9-143493.17" + attribute \src "libresoc.v:145307.9-145307.17" case 1'1 case end @@ -301999,15 +304508,15 @@ module \lsmem sync always update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:143510.3-143540.6" - process $proc$libresoc.v:143510$7132 + attribute \src "libresoc.v:145324.3-145354.6" + process $proc$libresoc.v:145324$7177 assign { } { } assign { } { } assign { } { } - assign $0\dbus__sel$next[7:0]$7133 $4\dbus__sel$next[7:0]$7137 - attribute \src "libresoc.v:143511.5-143511.29" + assign $0\dbus__sel$next[7:0]$7178 $4\dbus__sel$next[7:0]$7182 + attribute \src "libresoc.v:145325.5-145325.29" switch \initial - attribute \src "libresoc.v:143511.9-143511.17" + attribute \src "libresoc.v:145325.9-145325.17" case 1'1 case end @@ -302016,55 +304525,55 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__sel$next[7:0]$7134 $2\dbus__sel$next[7:0]$7135 + assign $1\dbus__sel$next[7:0]$7179 $2\dbus__sel$next[7:0]$7180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$35 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__sel$next[7:0]$7135 $3\dbus__sel$next[7:0]$7136 + assign $2\dbus__sel$next[7:0]$7180 $3\dbus__sel$next[7:0]$7181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__sel$next[7:0]$7136 8'00000000 + assign $3\dbus__sel$next[7:0]$7181 8'00000000 case - assign $3\dbus__sel$next[7:0]$7136 \dbus__sel + assign $3\dbus__sel$next[7:0]$7181 \dbus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__sel$next[7:0]$7135 \x_mask_i + assign $2\dbus__sel$next[7:0]$7180 \x_mask_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__sel$next[7:0]$7135 8'00000000 + assign $2\dbus__sel$next[7:0]$7180 8'00000000 end case - assign $1\dbus__sel$next[7:0]$7134 \dbus__sel + assign $1\dbus__sel$next[7:0]$7179 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__sel$next[7:0]$7137 8'00000000 + assign $4\dbus__sel$next[7:0]$7182 8'00000000 case - assign $4\dbus__sel$next[7:0]$7137 $1\dbus__sel$next[7:0]$7134 + assign $4\dbus__sel$next[7:0]$7182 $1\dbus__sel$next[7:0]$7179 end sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$7133 + update \dbus__sel$next $0\dbus__sel$next[7:0]$7178 end - attribute \src "libresoc.v:143541.3-143565.6" - process $proc$libresoc.v:143541$7138 + attribute \src "libresoc.v:145355.3-145379.6" + process $proc$libresoc.v:145355$7183 assign { } { } assign { } { } assign { } { } - assign $0\m_ld_data_o$next[63:0]$7139 $4\m_ld_data_o$next[63:0]$7143 - attribute \src "libresoc.v:143542.5-143542.29" + assign $0\m_ld_data_o$next[63:0]$7184 $4\m_ld_data_o$next[63:0]$7188 + attribute \src "libresoc.v:145356.5-145356.29" switch \initial - attribute \src "libresoc.v:143542.9-143542.17" + attribute \src "libresoc.v:145356.9-145356.17" case 1'1 case end @@ -302073,49 +304582,49 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_ld_data_o$next[63:0]$7140 $2\m_ld_data_o$next[63:0]$7141 + assign $1\m_ld_data_o$next[63:0]$7185 $2\m_ld_data_o$next[63:0]$7186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$49 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_ld_data_o$next[63:0]$7141 $3\m_ld_data_o$next[63:0]$7142 + assign $2\m_ld_data_o$next[63:0]$7186 $3\m_ld_data_o$next[63:0]$7187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_ld_data_o$next[63:0]$7142 \dbus__dat_r + assign $3\m_ld_data_o$next[63:0]$7187 \dbus__dat_r case - assign $3\m_ld_data_o$next[63:0]$7142 \m_ld_data_o + assign $3\m_ld_data_o$next[63:0]$7187 \m_ld_data_o end case - assign $2\m_ld_data_o$next[63:0]$7141 \m_ld_data_o + assign $2\m_ld_data_o$next[63:0]$7186 \m_ld_data_o end case - assign $1\m_ld_data_o$next[63:0]$7140 \m_ld_data_o + assign $1\m_ld_data_o$next[63:0]$7185 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\m_ld_data_o$next[63:0]$7143 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\m_ld_data_o$next[63:0]$7188 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\m_ld_data_o$next[63:0]$7143 $1\m_ld_data_o$next[63:0]$7140 + assign $4\m_ld_data_o$next[63:0]$7188 $1\m_ld_data_o$next[63:0]$7185 end sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7139 + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7184 end - attribute \src "libresoc.v:143566.3-143591.6" - process $proc$libresoc.v:143566$7144 + attribute \src "libresoc.v:145380.3-145405.6" + process $proc$libresoc.v:145380$7189 assign { } { } assign { } { } assign { } { } - assign $0\dbus__adr$next[44:0]$7145 $3\dbus__adr$next[44:0]$7148 - attribute \src "libresoc.v:143567.5-143567.29" + assign $0\dbus__adr$next[44:0]$7190 $3\dbus__adr$next[44:0]$7193 + attribute \src "libresoc.v:145381.5-145381.29" switch \initial - attribute \src "libresoc.v:143567.9-143567.17" + attribute \src "libresoc.v:145381.9-145381.17" case 1'1 case end @@ -302124,45 +304633,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__adr$next[44:0]$7146 $2\dbus__adr$next[44:0]$7147 + assign $1\dbus__adr$next[44:0]$7191 $2\dbus__adr$next[44:0]$7192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$63 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__adr$next[44:0]$7147 \dbus__adr + assign $2\dbus__adr$next[44:0]$7192 \dbus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__adr$next[44:0]$7147 \x_addr_i [47:3] + assign $2\dbus__adr$next[44:0]$7192 \x_addr_i [47:3] attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__adr$next[44:0]$7147 45'000000000000000000000000000000000000000000000 + assign $2\dbus__adr$next[44:0]$7192 45'000000000000000000000000000000000000000000000 end case - assign $1\dbus__adr$next[44:0]$7146 \dbus__adr + assign $1\dbus__adr$next[44:0]$7191 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__adr$next[44:0]$7148 45'000000000000000000000000000000000000000000000 + assign $3\dbus__adr$next[44:0]$7193 45'000000000000000000000000000000000000000000000 case - assign $3\dbus__adr$next[44:0]$7148 $1\dbus__adr$next[44:0]$7146 + assign $3\dbus__adr$next[44:0]$7193 $1\dbus__adr$next[44:0]$7191 end sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$7145 + update \dbus__adr$next $0\dbus__adr$next[44:0]$7190 end - attribute \src "libresoc.v:143592.3-143617.6" - process $proc$libresoc.v:143592$7149 + attribute \src "libresoc.v:145406.3-145431.6" + process $proc$libresoc.v:145406$7194 assign { } { } assign { } { } assign { } { } - assign $0\dbus__we$next[0:0]$7150 $3\dbus__we$next[0:0]$7153 - attribute \src "libresoc.v:143593.5-143593.29" + assign $0\dbus__we$next[0:0]$7195 $3\dbus__we$next[0:0]$7198 + attribute \src "libresoc.v:145407.5-145407.29" switch \initial - attribute \src "libresoc.v:143593.9-143593.17" + attribute \src "libresoc.v:145407.9-145407.17" case 1'1 case end @@ -302171,45 +304680,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__we$next[0:0]$7151 $2\dbus__we$next[0:0]$7152 + assign $1\dbus__we$next[0:0]$7196 $2\dbus__we$next[0:0]$7197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$71 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__we$next[0:0]$7152 \dbus__we + assign $2\dbus__we$next[0:0]$7197 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__we$next[0:0]$7152 \x_st_i + assign $2\dbus__we$next[0:0]$7197 \x_st_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__we$next[0:0]$7152 1'0 + assign $2\dbus__we$next[0:0]$7197 1'0 end case - assign $1\dbus__we$next[0:0]$7151 \dbus__we + assign $1\dbus__we$next[0:0]$7196 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__we$next[0:0]$7153 1'0 + assign $3\dbus__we$next[0:0]$7198 1'0 case - assign $3\dbus__we$next[0:0]$7153 $1\dbus__we$next[0:0]$7151 + assign $3\dbus__we$next[0:0]$7198 $1\dbus__we$next[0:0]$7196 end sync always - update \dbus__we$next $0\dbus__we$next[0:0]$7150 + update \dbus__we$next $0\dbus__we$next[0:0]$7195 end - attribute \src "libresoc.v:143618.3-143643.6" - process $proc$libresoc.v:143618$7154 + attribute \src "libresoc.v:145432.3-145457.6" + process $proc$libresoc.v:145432$7199 assign { } { } assign { } { } assign { } { } - assign $0\dbus__dat_w$next[63:0]$7155 $3\dbus__dat_w$next[63:0]$7158 - attribute \src "libresoc.v:143619.5-143619.29" + assign $0\dbus__dat_w$next[63:0]$7200 $3\dbus__dat_w$next[63:0]$7203 + attribute \src "libresoc.v:145433.5-145433.29" switch \initial - attribute \src "libresoc.v:143619.9-143619.17" + attribute \src "libresoc.v:145433.9-145433.17" case 1'1 case end @@ -302218,45 +304727,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__dat_w$next[63:0]$7156 $2\dbus__dat_w$next[63:0]$7157 + assign $1\dbus__dat_w$next[63:0]$7201 $2\dbus__dat_w$next[63:0]$7202 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$79 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__dat_w$next[63:0]$7157 \dbus__dat_w + assign $2\dbus__dat_w$next[63:0]$7202 \dbus__dat_w attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__dat_w$next[63:0]$7157 \x_st_data_i + assign $2\dbus__dat_w$next[63:0]$7202 \x_st_data_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__dat_w$next[63:0]$7157 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dbus__dat_w$next[63:0]$7202 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\dbus__dat_w$next[63:0]$7156 \dbus__dat_w + assign $1\dbus__dat_w$next[63:0]$7201 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__dat_w$next[63:0]$7158 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dbus__dat_w$next[63:0]$7203 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dbus__dat_w$next[63:0]$7158 $1\dbus__dat_w$next[63:0]$7156 + assign $3\dbus__dat_w$next[63:0]$7203 $1\dbus__dat_w$next[63:0]$7201 end sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7155 + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7200 end - attribute \src "libresoc.v:143644.3-143666.6" - process $proc$libresoc.v:143644$7159 + attribute \src "libresoc.v:145458.3-145480.6" + process $proc$libresoc.v:145458$7204 assign { } { } assign { } { } assign { } { } - assign $0\m_load_err_o$next[0:0]$7160 $3\m_load_err_o$next[0:0]$7163 - attribute \src "libresoc.v:143645.5-143645.29" + assign $0\m_load_err_o$next[0:0]$7205 $3\m_load_err_o$next[0:0]$7208 + attribute \src "libresoc.v:145459.5-145459.29" switch \initial - attribute \src "libresoc.v:143645.9-143645.17" + attribute \src "libresoc.v:145459.9-145459.17" case 1'1 case end @@ -302265,44 +304774,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_load_err_o$next[0:0]$7161 $2\m_load_err_o$next[0:0]$7162 + assign $1\m_load_err_o$next[0:0]$7206 $2\m_load_err_o$next[0:0]$7207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_load_err_o$next[0:0]$7162 \$85 + assign $2\m_load_err_o$next[0:0]$7207 \$85 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_load_err_o$next[0:0]$7162 1'0 + assign $2\m_load_err_o$next[0:0]$7207 1'0 case - assign $2\m_load_err_o$next[0:0]$7162 \m_load_err_o + assign $2\m_load_err_o$next[0:0]$7207 \m_load_err_o end case - assign $1\m_load_err_o$next[0:0]$7161 \m_load_err_o + assign $1\m_load_err_o$next[0:0]$7206 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_load_err_o$next[0:0]$7163 1'0 + assign $3\m_load_err_o$next[0:0]$7208 1'0 case - assign $3\m_load_err_o$next[0:0]$7163 $1\m_load_err_o$next[0:0]$7161 + assign $3\m_load_err_o$next[0:0]$7208 $1\m_load_err_o$next[0:0]$7206 end sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7160 + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7205 end - attribute \src "libresoc.v:143667.3-143689.6" - process $proc$libresoc.v:143667$7164 + attribute \src "libresoc.v:145481.3-145503.6" + process $proc$libresoc.v:145481$7209 assign { } { } assign { } { } assign { } { } - assign $0\m_store_err_o$next[0:0]$7165 $3\m_store_err_o$next[0:0]$7168 - attribute \src "libresoc.v:143668.5-143668.29" + assign $0\m_store_err_o$next[0:0]$7210 $3\m_store_err_o$next[0:0]$7213 + attribute \src "libresoc.v:145482.5-145482.29" switch \initial - attribute \src "libresoc.v:143668.9-143668.17" + attribute \src "libresoc.v:145482.9-145482.17" case 1'1 case end @@ -302311,44 +304820,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_store_err_o$next[0:0]$7166 $2\m_store_err_o$next[0:0]$7167 + assign $1\m_store_err_o$next[0:0]$7211 $2\m_store_err_o$next[0:0]$7212 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$89 \$87 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_store_err_o$next[0:0]$7167 \dbus__we + assign $2\m_store_err_o$next[0:0]$7212 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_store_err_o$next[0:0]$7167 1'0 + assign $2\m_store_err_o$next[0:0]$7212 1'0 case - assign $2\m_store_err_o$next[0:0]$7167 \m_store_err_o + assign $2\m_store_err_o$next[0:0]$7212 \m_store_err_o end case - assign $1\m_store_err_o$next[0:0]$7166 \m_store_err_o + assign $1\m_store_err_o$next[0:0]$7211 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_store_err_o$next[0:0]$7168 1'0 + assign $3\m_store_err_o$next[0:0]$7213 1'0 case - assign $3\m_store_err_o$next[0:0]$7168 $1\m_store_err_o$next[0:0]$7166 + assign $3\m_store_err_o$next[0:0]$7213 $1\m_store_err_o$next[0:0]$7211 end sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7165 + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7210 end - attribute \src "libresoc.v:143690.3-143709.6" - process $proc$libresoc.v:143690$7169 + attribute \src "libresoc.v:145504.3-145523.6" + process $proc$libresoc.v:145504$7214 assign { } { } assign { } { } assign { } { } - assign $0\m_badaddr_o$next[44:0]$7170 $3\m_badaddr_o$next[44:0]$7173 - attribute \src "libresoc.v:143691.5-143691.29" + assign $0\m_badaddr_o$next[44:0]$7215 $3\m_badaddr_o$next[44:0]$7218 + attribute \src "libresoc.v:145505.5-145505.29" switch \initial - attribute \src "libresoc.v:143691.9-143691.17" + attribute \src "libresoc.v:145505.9-145505.17" case 1'1 case end @@ -302357,343 +304866,343 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_badaddr_o$next[44:0]$7171 $2\m_badaddr_o$next[44:0]$7172 + assign $1\m_badaddr_o$next[44:0]$7216 $2\m_badaddr_o$next[44:0]$7217 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$93 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_badaddr_o$next[44:0]$7172 \dbus__adr + assign $2\m_badaddr_o$next[44:0]$7217 \dbus__adr case - assign $2\m_badaddr_o$next[44:0]$7172 \m_badaddr_o + assign $2\m_badaddr_o$next[44:0]$7217 \m_badaddr_o end case - assign $1\m_badaddr_o$next[44:0]$7171 \m_badaddr_o + assign $1\m_badaddr_o$next[44:0]$7216 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_badaddr_o$next[44:0]$7173 45'000000000000000000000000000000000000000000000 - case - assign $3\m_badaddr_o$next[44:0]$7173 $1\m_badaddr_o$next[44:0]$7171 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7170 - end - connect \$9 $or$libresoc.v:143358$7060_Y - connect \$11 $not$libresoc.v:143359$7061_Y - connect \$13 $or$libresoc.v:143360$7062_Y - connect \$15 $or$libresoc.v:143361$7063_Y - connect \$17 $and$libresoc.v:143362$7064_Y - connect \$1 $or$libresoc.v:143363$7065_Y - connect \$19 $not$libresoc.v:143364$7066_Y - connect \$21 $and$libresoc.v:143365$7067_Y - connect \$23 $or$libresoc.v:143366$7068_Y - connect \$25 $not$libresoc.v:143367$7069_Y - connect \$27 $or$libresoc.v:143368$7070_Y - connect \$29 $or$libresoc.v:143369$7071_Y - connect \$31 $and$libresoc.v:143370$7072_Y - connect \$33 $not$libresoc.v:143371$7073_Y - connect \$35 $and$libresoc.v:143372$7074_Y - connect \$37 $or$libresoc.v:143373$7075_Y - connect \$3 $and$libresoc.v:143374$7076_Y - connect \$39 $not$libresoc.v:143375$7077_Y - connect \$41 $or$libresoc.v:143376$7078_Y - connect \$43 $or$libresoc.v:143377$7079_Y - connect \$45 $and$libresoc.v:143378$7080_Y - connect \$47 $not$libresoc.v:143379$7081_Y - connect \$49 $and$libresoc.v:143380$7082_Y - connect \$51 $or$libresoc.v:143381$7083_Y - connect \$53 $not$libresoc.v:143382$7084_Y - connect \$55 $or$libresoc.v:143383$7085_Y - connect \$57 $or$libresoc.v:143384$7086_Y - connect \$5 $not$libresoc.v:143385$7087_Y - connect \$59 $and$libresoc.v:143386$7088_Y - connect \$61 $not$libresoc.v:143387$7089_Y - connect \$63 $and$libresoc.v:143388$7090_Y - connect \$65 $or$libresoc.v:143389$7091_Y - connect \$67 $and$libresoc.v:143390$7092_Y - connect \$69 $not$libresoc.v:143391$7093_Y - connect \$71 $and$libresoc.v:143392$7094_Y - connect \$73 $or$libresoc.v:143393$7095_Y - connect \$75 $and$libresoc.v:143394$7096_Y - connect \$77 $not$libresoc.v:143395$7097_Y - connect \$7 $and$libresoc.v:143396$7098_Y - connect \$79 $and$libresoc.v:143397$7099_Y - connect \$81 $and$libresoc.v:143398$7100_Y - connect \$83 $not$libresoc.v:143399$7101_Y - connect \$85 $not$libresoc.v:143400$7102_Y - connect \$87 $and$libresoc.v:143401$7103_Y - connect \$89 $not$libresoc.v:143402$7104_Y - connect \$91 $and$libresoc.v:143403$7105_Y - connect \$93 $not$libresoc.v:143404$7106_Y - connect \$95 $or$libresoc.v:143405$7107_Y + assign $3\m_badaddr_o$next[44:0]$7218 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$7218 $1\m_badaddr_o$next[44:0]$7216 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7215 + end + connect \$9 $or$libresoc.v:145172$7105_Y + connect \$11 $not$libresoc.v:145173$7106_Y + connect \$13 $or$libresoc.v:145174$7107_Y + connect \$15 $or$libresoc.v:145175$7108_Y + connect \$17 $and$libresoc.v:145176$7109_Y + connect \$1 $or$libresoc.v:145177$7110_Y + connect \$19 $not$libresoc.v:145178$7111_Y + connect \$21 $and$libresoc.v:145179$7112_Y + connect \$23 $or$libresoc.v:145180$7113_Y + connect \$25 $not$libresoc.v:145181$7114_Y + connect \$27 $or$libresoc.v:145182$7115_Y + connect \$29 $or$libresoc.v:145183$7116_Y + connect \$31 $and$libresoc.v:145184$7117_Y + connect \$33 $not$libresoc.v:145185$7118_Y + connect \$35 $and$libresoc.v:145186$7119_Y + connect \$37 $or$libresoc.v:145187$7120_Y + connect \$3 $and$libresoc.v:145188$7121_Y + connect \$39 $not$libresoc.v:145189$7122_Y + connect \$41 $or$libresoc.v:145190$7123_Y + connect \$43 $or$libresoc.v:145191$7124_Y + connect \$45 $and$libresoc.v:145192$7125_Y + connect \$47 $not$libresoc.v:145193$7126_Y + connect \$49 $and$libresoc.v:145194$7127_Y + connect \$51 $or$libresoc.v:145195$7128_Y + connect \$53 $not$libresoc.v:145196$7129_Y + connect \$55 $or$libresoc.v:145197$7130_Y + connect \$57 $or$libresoc.v:145198$7131_Y + connect \$5 $not$libresoc.v:145199$7132_Y + connect \$59 $and$libresoc.v:145200$7133_Y + connect \$61 $not$libresoc.v:145201$7134_Y + connect \$63 $and$libresoc.v:145202$7135_Y + connect \$65 $or$libresoc.v:145203$7136_Y + connect \$67 $and$libresoc.v:145204$7137_Y + connect \$69 $not$libresoc.v:145205$7138_Y + connect \$71 $and$libresoc.v:145206$7139_Y + connect \$73 $or$libresoc.v:145207$7140_Y + connect \$75 $and$libresoc.v:145208$7141_Y + connect \$77 $not$libresoc.v:145209$7142_Y + connect \$7 $and$libresoc.v:145210$7143_Y + connect \$79 $and$libresoc.v:145211$7144_Y + connect \$81 $and$libresoc.v:145212$7145_Y + connect \$83 $not$libresoc.v:145213$7146_Y + connect \$85 $not$libresoc.v:145214$7147_Y + connect \$87 $and$libresoc.v:145215$7148_Y + connect \$89 $not$libresoc.v:145216$7149_Y + connect \$91 $and$libresoc.v:145217$7150_Y + connect \$93 $not$libresoc.v:145218$7151_Y + connect \$95 $or$libresoc.v:145219$7152_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end -attribute \src "libresoc.v:143716.1-144673.10" +attribute \src "libresoc.v:145530.1-146491.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:144245.3-144267.6" + attribute \src "libresoc.v:146063.3-146085.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:144344.3-144370.6" + attribute \src "libresoc.v:146162.3-146188.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:144625.3-144635.6" + attribute \src "libresoc.v:146443.3-146453.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:144595.3-144604.6" + attribute \src "libresoc.v:146413.3-146422.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:144605.3-144614.6" + attribute \src "libresoc.v:146423.3-146432.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:144615.3-144624.6" + attribute \src "libresoc.v:146433.3-146442.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:144483.3-144505.6" + attribute \src "libresoc.v:146301.3-146323.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:144469.3-144482.6" + attribute \src "libresoc.v:146287.3-146300.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:144636.3-144646.6" + attribute \src "libresoc.v:146454.3-146464.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:144647.3-144657.6" + attribute \src "libresoc.v:146465.3-146475.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:144371.3-144396.6" + attribute \src "libresoc.v:146189.3-146214.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:144397.3-144411.6" + attribute \src "libresoc.v:146215.3-146229.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:144575.3-144594.6" + attribute \src "libresoc.v:146393.3-146412.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:143717.7-143717.20" + attribute \src "libresoc.v:145531.7-145531.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144235.3-144244.6" + attribute \src "libresoc.v:146053.3-146062.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:144306.3-144324.6" + attribute \src "libresoc.v:146124.3-146142.6" wire $0\msb_a[0:0] - attribute \src "libresoc.v:144325.3-144343.6" + attribute \src "libresoc.v:146143.3-146161.6" wire $0\msb_b[0:0] - attribute \src "libresoc.v:144412.3-144449.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:144450.3-144468.6" + attribute \src "libresoc.v:146268.3-146286.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:144528.3-144541.6" + attribute \src "libresoc.v:146346.3-146359.6" wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:144564.3-144574.6" + attribute \src "libresoc.v:146382.3-146392.6" wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:144279.3-144305.6" + attribute \src "libresoc.v:146097.3-146123.6" wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:144506.3-144516.6" - wire width 2 $0\xer_ca$20[1:0]$7260 - attribute \src "libresoc.v:144517.3-144527.6" + attribute \src "libresoc.v:146324.3-146334.6" + wire width 2 $0\xer_ca$20[1:0]$7305 + attribute \src "libresoc.v:146335.3-146345.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:144542.3-144552.6" + attribute \src "libresoc.v:146360.3-146370.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:144553.3-144563.6" + attribute \src "libresoc.v:146371.3-146381.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:144268.3-144278.6" + attribute \src "libresoc.v:146086.3-146096.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:144658.3-144668.6" + attribute \src "libresoc.v:146476.3-146486.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:144245.3-144267.6" + attribute \src "libresoc.v:146063.3-146085.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:144344.3-144370.6" + attribute \src "libresoc.v:146162.3-146188.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:144625.3-144635.6" + attribute \src "libresoc.v:146443.3-146453.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:144595.3-144604.6" + attribute \src "libresoc.v:146413.3-146422.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:144605.3-144614.6" + attribute \src "libresoc.v:146423.3-146432.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:144615.3-144624.6" + attribute \src "libresoc.v:146433.3-146442.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:144483.3-144505.6" + attribute \src "libresoc.v:146301.3-146323.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:144469.3-144482.6" + attribute \src "libresoc.v:146287.3-146300.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:144636.3-144646.6" + attribute \src "libresoc.v:146454.3-146464.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:144647.3-144657.6" + attribute \src "libresoc.v:146465.3-146475.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:144371.3-144396.6" + attribute \src "libresoc.v:146189.3-146214.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:144397.3-144411.6" + attribute \src "libresoc.v:146215.3-146229.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:144575.3-144594.6" + attribute \src "libresoc.v:146393.3-146412.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:144235.3-144244.6" + attribute \src "libresoc.v:146053.3-146062.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:144306.3-144324.6" + attribute \src "libresoc.v:146124.3-146142.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:144325.3-144343.6" + attribute \src "libresoc.v:146143.3-146161.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:144412.3-144449.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:144450.3-144468.6" + attribute \src "libresoc.v:146268.3-146286.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:144528.3-144541.6" + attribute \src "libresoc.v:146346.3-146359.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:144564.3-144574.6" + attribute \src "libresoc.v:146382.3-146392.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:144279.3-144305.6" + attribute \src "libresoc.v:146097.3-146123.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:144506.3-144516.6" - wire width 2 $1\xer_ca$20[1:0]$7261 - attribute \src "libresoc.v:144517.3-144527.6" + attribute \src "libresoc.v:146324.3-146334.6" + wire width 2 $1\xer_ca$20[1:0]$7306 + attribute \src "libresoc.v:146335.3-146345.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:144542.3-144552.6" + attribute \src "libresoc.v:146360.3-146370.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:144553.3-144563.6" + attribute \src "libresoc.v:146371.3-146381.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:144268.3-144278.6" + attribute \src "libresoc.v:146086.3-146096.6" wire $1\zerohi[0:0] - attribute \src "libresoc.v:144658.3-144668.6" + attribute \src "libresoc.v:146476.3-146486.6" wire $1\zerolo[0:0] - attribute \src "libresoc.v:144245.3-144267.6" + attribute \src "libresoc.v:146063.3-146085.6" wire width 64 $2\a_i[63:0] - attribute \src "libresoc.v:144344.3-144370.6" + attribute \src "libresoc.v:146162.3-146188.6" wire $2\a_lt[0:0] - attribute \src "libresoc.v:144483.3-144505.6" + attribute \src "libresoc.v:146301.3-146323.6" wire width 64 $2\b_i[63:0] - attribute \src "libresoc.v:144371.3-144396.6" + attribute \src "libresoc.v:146189.3-146214.6" wire width 2 $2\cr_a[3:2] - attribute \src "libresoc.v:144306.3-144324.6" + attribute \src "libresoc.v:146124.3-146142.6" wire $2\msb_a[0:0] - attribute \src "libresoc.v:144325.3-144343.6" + attribute \src "libresoc.v:146143.3-146161.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:144412.3-144449.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:144279.3-144305.6" + attribute \src "libresoc.v:146097.3-146123.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:144344.3-144370.6" + attribute \src "libresoc.v:146162.3-146188.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:144412.3-144449.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:144279.3-144305.6" + attribute \src "libresoc.v:146097.3-146123.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:144412.3-144449.6" + attribute \src "libresoc.v:146230.3-146267.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:144210.18-144210.105" - wire width 67 $add$libresoc.v:144210$7221_Y - attribute \src "libresoc.v:144184.19-144184.107" - wire $and$libresoc.v:144184$7195_Y - attribute \src "libresoc.v:144188.19-144188.107" - wire $and$libresoc.v:144188$7199_Y - attribute \src "libresoc.v:144221.18-144221.106" - wire $and$libresoc.v:144221$7232_Y - attribute \src "libresoc.v:144226.18-144226.106" - wire $and$libresoc.v:144226$7237_Y - attribute \src "libresoc.v:144229.18-144229.106" - wire $and$libresoc.v:144229$7240_Y - attribute \src "libresoc.v:144232.18-144232.106" - wire $and$libresoc.v:144232$7243_Y - attribute \src "libresoc.v:144175.19-144175.118" - wire $eq$libresoc.v:144175$7186_Y - attribute \src "libresoc.v:144176.19-144176.118" - wire $eq$libresoc.v:144176$7187_Y - attribute \src "libresoc.v:144177.19-144177.118" - wire $eq$libresoc.v:144177$7188_Y - attribute \src "libresoc.v:144189.19-144189.109" - wire $eq$libresoc.v:144189$7200_Y - attribute \src "libresoc.v:144190.19-144190.110" - wire $eq$libresoc.v:144190$7201_Y - attribute \src "libresoc.v:144191.19-144191.111" - wire $eq$libresoc.v:144191$7202_Y - attribute \src "libresoc.v:144192.19-144192.111" - wire $eq$libresoc.v:144192$7203_Y - attribute \src "libresoc.v:144193.19-144193.111" - wire $eq$libresoc.v:144193$7204_Y - attribute \src "libresoc.v:144194.19-144194.111" - wire $eq$libresoc.v:144194$7205_Y - attribute \src "libresoc.v:144195.19-144195.111" - wire $eq$libresoc.v:144195$7206_Y - attribute \src "libresoc.v:144196.19-144196.111" - wire $eq$libresoc.v:144196$7207_Y - attribute \src "libresoc.v:144197.18-144197.118" - wire $eq$libresoc.v:144197$7208_Y - attribute \src "libresoc.v:144199.18-144199.118" - wire $eq$libresoc.v:144199$7210_Y - attribute \src "libresoc.v:144200.18-144200.118" - wire $eq$libresoc.v:144200$7211_Y - attribute \src "libresoc.v:144201.18-144201.118" - wire $eq$libresoc.v:144201$7212_Y - attribute \src "libresoc.v:144202.18-144202.118" - wire $eq$libresoc.v:144202$7213_Y - attribute \src "libresoc.v:144204.18-144204.118" - wire $eq$libresoc.v:144204$7215_Y - attribute \src "libresoc.v:144205.18-144205.118" - wire $eq$libresoc.v:144205$7216_Y - attribute \src "libresoc.v:144207.18-144207.118" - wire $eq$libresoc.v:144207$7218_Y - attribute \src "libresoc.v:144208.18-144208.118" - wire $eq$libresoc.v:144208$7219_Y - attribute \src "libresoc.v:144222.18-144222.107" - wire $ne$libresoc.v:144222$7233_Y - attribute \src "libresoc.v:144233.18-144233.107" - wire $ne$libresoc.v:144233$7244_Y - attribute \src "libresoc.v:144183.19-144183.100" - wire $not$libresoc.v:144183$7194_Y - attribute \src "libresoc.v:144187.19-144187.100" - wire $not$libresoc.v:144187$7198_Y - attribute \src "libresoc.v:144198.18-144198.110" - wire $not$libresoc.v:144198$7209_Y - attribute \src "libresoc.v:144211.18-144211.97" - wire width 64 $not$libresoc.v:144211$7222_Y - attribute \src "libresoc.v:144216.18-144216.99" - wire $not$libresoc.v:144216$7227_Y - attribute \src "libresoc.v:144219.18-144219.99" - wire $not$libresoc.v:144219$7230_Y - attribute \src "libresoc.v:144223.18-144223.99" - wire $not$libresoc.v:144223$7234_Y - attribute \src "libresoc.v:144224.18-144224.99" - wire $not$libresoc.v:144224$7235_Y - attribute \src "libresoc.v:144203.18-144203.104" - wire $or$libresoc.v:144203$7214_Y - attribute \src "libresoc.v:144206.18-144206.104" - wire $or$libresoc.v:144206$7217_Y - attribute \src "libresoc.v:144209.18-144209.104" - wire $or$libresoc.v:144209$7220_Y - attribute \src "libresoc.v:144220.18-144220.110" - wire $or$libresoc.v:144220$7231_Y - attribute \src "libresoc.v:144225.18-144225.110" - wire $or$libresoc.v:144225$7236_Y - attribute \src "libresoc.v:144228.18-144228.110" - wire $or$libresoc.v:144228$7239_Y - attribute \src "libresoc.v:144231.18-144231.110" - wire $or$libresoc.v:144231$7242_Y - attribute \src "libresoc.v:144174.18-144174.98" - wire $reduce_or$libresoc.v:144174$7185_Y - attribute \src "libresoc.v:144178.19-144178.99" - wire $reduce_or$libresoc.v:144178$7189_Y - attribute \src "libresoc.v:144215.18-144215.99" - wire $reduce_or$libresoc.v:144215$7226_Y - attribute \src "libresoc.v:144218.18-144218.99" - wire $reduce_or$libresoc.v:144218$7229_Y - attribute \src "libresoc.v:144227.18-144227.121" - wire $ternary$libresoc.v:144227$7238_Y - attribute \src "libresoc.v:144230.18-144230.119" - wire $ternary$libresoc.v:144230$7241_Y - attribute \src "libresoc.v:144234.18-144234.123" - wire $ternary$libresoc.v:144234$7245_Y - attribute \src "libresoc.v:144179.19-144179.111" - wire $xor$libresoc.v:144179$7190_Y - attribute \src "libresoc.v:144180.19-144180.111" - wire $xor$libresoc.v:144180$7191_Y - attribute \src "libresoc.v:144181.19-144181.110" - wire $xor$libresoc.v:144181$7192_Y - attribute \src "libresoc.v:144182.19-144182.110" - wire $xor$libresoc.v:144182$7193_Y - attribute \src "libresoc.v:144185.19-144185.110" - wire $xor$libresoc.v:144185$7196_Y - attribute \src "libresoc.v:144186.19-144186.110" - wire $xor$libresoc.v:144186$7197_Y - attribute \src "libresoc.v:144212.18-144212.111" - wire $xor$libresoc.v:144212$7223_Y - attribute \src "libresoc.v:144213.18-144213.107" - wire $xor$libresoc.v:144213$7224_Y - attribute \src "libresoc.v:144214.18-144214.113" - wire width 32 $xor$libresoc.v:144214$7225_Y - attribute \src "libresoc.v:144217.18-144217.115" - wire width 32 $xor$libresoc.v:144217$7228_Y + attribute \src "libresoc.v:146028.18-146028.105" + wire width 67 $add$libresoc.v:146028$7266_Y + attribute \src "libresoc.v:146002.19-146002.107" + wire $and$libresoc.v:146002$7240_Y + attribute \src "libresoc.v:146006.19-146006.107" + wire $and$libresoc.v:146006$7244_Y + attribute \src "libresoc.v:146039.18-146039.106" + wire $and$libresoc.v:146039$7277_Y + attribute \src "libresoc.v:146044.18-146044.106" + wire $and$libresoc.v:146044$7282_Y + attribute \src "libresoc.v:146047.18-146047.106" + wire $and$libresoc.v:146047$7285_Y + attribute \src "libresoc.v:146050.18-146050.106" + wire $and$libresoc.v:146050$7288_Y + attribute \src "libresoc.v:145993.19-145993.118" + wire $eq$libresoc.v:145993$7231_Y + attribute \src "libresoc.v:145994.19-145994.118" + wire $eq$libresoc.v:145994$7232_Y + attribute \src "libresoc.v:145995.19-145995.118" + wire $eq$libresoc.v:145995$7233_Y + attribute \src "libresoc.v:146007.19-146007.109" + wire $eq$libresoc.v:146007$7245_Y + attribute \src "libresoc.v:146008.19-146008.110" + wire $eq$libresoc.v:146008$7246_Y + attribute \src "libresoc.v:146009.19-146009.111" + wire $eq$libresoc.v:146009$7247_Y + attribute \src "libresoc.v:146010.19-146010.111" + wire $eq$libresoc.v:146010$7248_Y + attribute \src "libresoc.v:146011.19-146011.111" + wire $eq$libresoc.v:146011$7249_Y + attribute \src "libresoc.v:146012.19-146012.111" + wire $eq$libresoc.v:146012$7250_Y + attribute \src "libresoc.v:146013.19-146013.111" + wire $eq$libresoc.v:146013$7251_Y + attribute \src "libresoc.v:146014.19-146014.111" + wire $eq$libresoc.v:146014$7252_Y + attribute \src "libresoc.v:146015.18-146015.118" + wire $eq$libresoc.v:146015$7253_Y + attribute \src "libresoc.v:146017.18-146017.118" + wire $eq$libresoc.v:146017$7255_Y + attribute \src "libresoc.v:146018.18-146018.118" + wire $eq$libresoc.v:146018$7256_Y + attribute \src "libresoc.v:146019.18-146019.118" + wire $eq$libresoc.v:146019$7257_Y + attribute \src "libresoc.v:146020.18-146020.118" + wire $eq$libresoc.v:146020$7258_Y + attribute \src "libresoc.v:146022.18-146022.118" + wire $eq$libresoc.v:146022$7260_Y + attribute \src "libresoc.v:146023.18-146023.118" + wire $eq$libresoc.v:146023$7261_Y + attribute \src "libresoc.v:146025.18-146025.118" + wire $eq$libresoc.v:146025$7263_Y + attribute \src "libresoc.v:146026.18-146026.118" + wire $eq$libresoc.v:146026$7264_Y + attribute \src "libresoc.v:146040.18-146040.107" + wire $ne$libresoc.v:146040$7278_Y + attribute \src "libresoc.v:146051.18-146051.107" + wire $ne$libresoc.v:146051$7289_Y + attribute \src "libresoc.v:146001.19-146001.100" + wire $not$libresoc.v:146001$7239_Y + attribute \src "libresoc.v:146005.19-146005.100" + wire $not$libresoc.v:146005$7243_Y + attribute \src "libresoc.v:146016.18-146016.110" + wire $not$libresoc.v:146016$7254_Y + attribute \src "libresoc.v:146029.18-146029.97" + wire width 64 $not$libresoc.v:146029$7267_Y + attribute \src "libresoc.v:146034.18-146034.99" + wire $not$libresoc.v:146034$7272_Y + attribute \src "libresoc.v:146037.18-146037.99" + wire $not$libresoc.v:146037$7275_Y + attribute \src "libresoc.v:146041.18-146041.99" + wire $not$libresoc.v:146041$7279_Y + attribute \src "libresoc.v:146042.18-146042.99" + wire $not$libresoc.v:146042$7280_Y + attribute \src "libresoc.v:146021.18-146021.104" + wire $or$libresoc.v:146021$7259_Y + attribute \src "libresoc.v:146024.18-146024.104" + wire $or$libresoc.v:146024$7262_Y + attribute \src "libresoc.v:146027.18-146027.104" + wire $or$libresoc.v:146027$7265_Y + attribute \src "libresoc.v:146038.18-146038.110" + wire $or$libresoc.v:146038$7276_Y + attribute \src "libresoc.v:146043.18-146043.110" + wire $or$libresoc.v:146043$7281_Y + attribute \src "libresoc.v:146046.18-146046.110" + wire $or$libresoc.v:146046$7284_Y + attribute \src "libresoc.v:146049.18-146049.110" + wire $or$libresoc.v:146049$7287_Y + attribute \src "libresoc.v:145992.18-145992.98" + wire $reduce_or$libresoc.v:145992$7230_Y + attribute \src "libresoc.v:145996.19-145996.99" + wire $reduce_or$libresoc.v:145996$7234_Y + attribute \src "libresoc.v:146033.18-146033.99" + wire $reduce_or$libresoc.v:146033$7271_Y + attribute \src "libresoc.v:146036.18-146036.99" + wire $reduce_or$libresoc.v:146036$7274_Y + attribute \src "libresoc.v:146045.18-146045.121" + wire $ternary$libresoc.v:146045$7283_Y + attribute \src "libresoc.v:146048.18-146048.119" + wire $ternary$libresoc.v:146048$7286_Y + attribute \src "libresoc.v:146052.18-146052.123" + wire $ternary$libresoc.v:146052$7290_Y + attribute \src "libresoc.v:145997.19-145997.111" + wire $xor$libresoc.v:145997$7235_Y + attribute \src "libresoc.v:145998.19-145998.111" + wire $xor$libresoc.v:145998$7236_Y + attribute \src "libresoc.v:145999.19-145999.110" + wire $xor$libresoc.v:145999$7237_Y + attribute \src "libresoc.v:146000.19-146000.110" + wire $xor$libresoc.v:146000$7238_Y + attribute \src "libresoc.v:146003.19-146003.110" + wire $xor$libresoc.v:146003$7241_Y + attribute \src "libresoc.v:146004.19-146004.110" + wire $xor$libresoc.v:146004$7242_Y + attribute \src "libresoc.v:146030.18-146030.111" + wire $xor$libresoc.v:146030$7268_Y + attribute \src "libresoc.v:146031.18-146031.107" + wire $xor$libresoc.v:146031$7269_Y + attribute \src "libresoc.v:146032.18-146032.113" + wire width 32 $xor$libresoc.v:146032$7270_Y + attribute \src "libresoc.v:146035.18-146035.115" + wire width 32 $xor$libresoc.v:146035$7273_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" @@ -302835,37 +305344,39 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \alu_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \alu_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -302964,6 +305475,7 @@ module \main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -303040,6 +305552,7 @@ module \main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -303100,7 +305613,7 @@ module \main wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:143717.7-143717.15" + attribute \src "libresoc.v:145531.7-145531.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit @@ -303145,7 +305658,7 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:144210$7221 + cell $add $add$libresoc.v:146028$7266 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -303153,10 +305666,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:144210$7221_Y + connect \Y $add$libresoc.v:146028$7266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:144184$7195 + cell $and $and$libresoc.v:146002$7240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303164,10 +305677,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:144184$7195_Y + connect \Y $and$libresoc.v:146002$7240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:144188$7199 + cell $and $and$libresoc.v:146006$7244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303175,10 +305688,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:144188$7199_Y + connect \Y $and$libresoc.v:146006$7244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:144221$7232 + cell $and $and$libresoc.v:146039$7277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303186,10 +305699,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:144221$7232_Y + connect \Y $and$libresoc.v:146039$7277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:144226$7237 + cell $and $and$libresoc.v:146044$7282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303197,10 +305710,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:144226$7237_Y + connect \Y $and$libresoc.v:146044$7282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:144229$7240 + cell $and $and$libresoc.v:146047$7285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303208,10 +305721,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:144229$7240_Y + connect \Y $and$libresoc.v:146047$7285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:144232$7243 + cell $and $and$libresoc.v:146050$7288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303219,10 +305732,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:144232$7243_Y + connect \Y $and$libresoc.v:146050$7288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:144175$7186 + cell $eq $eq$libresoc.v:145993$7231 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -303230,10 +305743,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:144175$7186_Y + connect \Y $eq$libresoc.v:145993$7231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:144176$7187 + cell $eq $eq$libresoc.v:145994$7232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -303241,10 +305754,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:144176$7187_Y + connect \Y $eq$libresoc.v:145994$7232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:144177$7188 + cell $eq $eq$libresoc.v:145995$7233 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -303252,10 +305765,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:144177$7188_Y + connect \Y $eq$libresoc.v:145995$7233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:144189$7200 + cell $eq $eq$libresoc.v:146007$7245 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -303263,10 +305776,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:144189$7200_Y + connect \Y $eq$libresoc.v:146007$7245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:144190$7201 + cell $eq $eq$libresoc.v:146008$7246 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -303274,10 +305787,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:144190$7201_Y + connect \Y $eq$libresoc.v:146008$7246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:144191$7202 + cell $eq $eq$libresoc.v:146009$7247 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -303285,10 +305798,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:144191$7202_Y + connect \Y $eq$libresoc.v:146009$7247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:144192$7203 + cell $eq $eq$libresoc.v:146010$7248 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -303296,10 +305809,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:144192$7203_Y + connect \Y $eq$libresoc.v:146010$7248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:144193$7204 + cell $eq $eq$libresoc.v:146011$7249 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -303307,10 +305820,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:144193$7204_Y + connect \Y $eq$libresoc.v:146011$7249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:144194$7205 + cell $eq $eq$libresoc.v:146012$7250 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -303318,10 +305831,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:144194$7205_Y + connect \Y $eq$libresoc.v:146012$7250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:144195$7206 + cell $eq $eq$libresoc.v:146013$7251 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -303329,10 +305842,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:144195$7206_Y + connect \Y $eq$libresoc.v:146013$7251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:144196$7207 + cell $eq $eq$libresoc.v:146014$7252 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -303340,10 +305853,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:144196$7207_Y + connect \Y $eq$libresoc.v:146014$7252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:144197$7208 + cell $eq $eq$libresoc.v:146015$7253 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303351,10 +305864,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:144197$7208_Y + connect \Y $eq$libresoc.v:146015$7253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:144199$7210 + cell $eq $eq$libresoc.v:146017$7255 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303362,10 +305875,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:144199$7210_Y + connect \Y $eq$libresoc.v:146017$7255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:144200$7211 + cell $eq $eq$libresoc.v:146018$7256 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303373,10 +305886,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:144200$7211_Y + connect \Y $eq$libresoc.v:146018$7256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:144201$7212 + cell $eq $eq$libresoc.v:146019$7257 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303384,10 +305897,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:144201$7212_Y + connect \Y $eq$libresoc.v:146019$7257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:144202$7213 + cell $eq $eq$libresoc.v:146020$7258 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303395,10 +305908,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:144202$7213_Y + connect \Y $eq$libresoc.v:146020$7258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:144204$7215 + cell $eq $eq$libresoc.v:146022$7260 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303406,10 +305919,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:144204$7215_Y + connect \Y $eq$libresoc.v:146022$7260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:144205$7216 + cell $eq $eq$libresoc.v:146023$7261 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303417,10 +305930,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:144205$7216_Y + connect \Y $eq$libresoc.v:146023$7261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:144207$7218 + cell $eq $eq$libresoc.v:146025$7263 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303428,10 +305941,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:144207$7218_Y + connect \Y $eq$libresoc.v:146025$7263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:144208$7219 + cell $eq $eq$libresoc.v:146026$7264 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -303439,10 +305952,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:144208$7219_Y + connect \Y $eq$libresoc.v:146026$7264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:144222$7233 + cell $ne $ne$libresoc.v:146040$7278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303450,10 +305963,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:144222$7233_Y + connect \Y $ne$libresoc.v:146040$7278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:144233$7244 + cell $ne $ne$libresoc.v:146051$7289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303461,74 +305974,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:144233$7244_Y + connect \Y $ne$libresoc.v:146051$7289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:144183$7194 + cell $not $not$libresoc.v:146001$7239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:144183$7194_Y + connect \Y $not$libresoc.v:146001$7239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:144187$7198 + cell $not $not$libresoc.v:146005$7243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:144187$7198_Y + connect \Y $not$libresoc.v:146005$7243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:144198$7209 + cell $not $not$libresoc.v:146016$7254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:144198$7209_Y + connect \Y $not$libresoc.v:146016$7254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:144211$7222 + cell $not $not$libresoc.v:146029$7267 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:144211$7222_Y + connect \Y $not$libresoc.v:146029$7267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:144216$7227 + cell $not $not$libresoc.v:146034$7272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:144216$7227_Y + connect \Y $not$libresoc.v:146034$7272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:144219$7230 + cell $not $not$libresoc.v:146037$7275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:144219$7230_Y + connect \Y $not$libresoc.v:146037$7275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:144223$7234 + cell $not $not$libresoc.v:146041$7279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:144223$7234_Y + connect \Y $not$libresoc.v:146041$7279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:144224$7235 + cell $not $not$libresoc.v:146042$7280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:144224$7235_Y + connect \Y $not$libresoc.v:146042$7280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:144203$7214 + cell $or $or$libresoc.v:146021$7259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303536,10 +306049,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:144203$7214_Y + connect \Y $or$libresoc.v:146021$7259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:144206$7217 + cell $or $or$libresoc.v:146024$7262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303547,10 +306060,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:144206$7217_Y + connect \Y $or$libresoc.v:146024$7262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:144209$7220 + cell $or $or$libresoc.v:146027$7265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303558,10 +306071,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:144209$7220_Y + connect \Y $or$libresoc.v:146027$7265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:144220$7231 + cell $or $or$libresoc.v:146038$7276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303569,10 +306082,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:144220$7231_Y + connect \Y $or$libresoc.v:146038$7276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:144225$7236 + cell $or $or$libresoc.v:146043$7281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303580,10 +306093,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:144225$7236_Y + connect \Y $or$libresoc.v:146043$7281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:144228$7239 + cell $or $or$libresoc.v:146046$7284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303591,10 +306104,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:144228$7239_Y + connect \Y $or$libresoc.v:146046$7284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:144231$7242 + cell $or $or$libresoc.v:146049$7287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303602,66 +306115,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:144231$7242_Y + connect \Y $or$libresoc.v:146049$7287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:144174$7185 + cell $reduce_or $reduce_or$libresoc.v:145992$7230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:144174$7185_Y + connect \Y $reduce_or$libresoc.v:145992$7230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:144178$7189 + cell $reduce_or $reduce_or$libresoc.v:145996$7234 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:144178$7189_Y + connect \Y $reduce_or$libresoc.v:145996$7234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:144215$7226 + cell $reduce_or $reduce_or$libresoc.v:146033$7271 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:144215$7226_Y + connect \Y $reduce_or$libresoc.v:146033$7271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:144218$7229 + cell $reduce_or $reduce_or$libresoc.v:146036$7274 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:144218$7229_Y + connect \Y $reduce_or$libresoc.v:146036$7274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:144227$7238 + cell $mux $ternary$libresoc.v:146045$7283 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:144227$7238_Y + connect \Y $ternary$libresoc.v:146045$7283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:144230$7241 + cell $mux $ternary$libresoc.v:146048$7286 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:144230$7241_Y + connect \Y $ternary$libresoc.v:146048$7286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:144234$7245 + cell $mux $ternary$libresoc.v:146052$7290 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:144234$7245_Y + connect \Y $ternary$libresoc.v:146052$7290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:144179$7190 + cell $xor $xor$libresoc.v:145997$7235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303669,10 +306182,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:144179$7190_Y + connect \Y $xor$libresoc.v:145997$7235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:144180$7191 + cell $xor $xor$libresoc.v:145998$7236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303680,10 +306193,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:144180$7191_Y + connect \Y $xor$libresoc.v:145998$7236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:144181$7192 + cell $xor $xor$libresoc.v:145999$7237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303691,10 +306204,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:144181$7192_Y + connect \Y $xor$libresoc.v:145999$7237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:144182$7193 + cell $xor $xor$libresoc.v:146000$7238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303702,10 +306215,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:144182$7193_Y + connect \Y $xor$libresoc.v:146000$7238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:144185$7196 + cell $xor $xor$libresoc.v:146003$7241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303713,10 +306226,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:144185$7196_Y + connect \Y $xor$libresoc.v:146003$7241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:144186$7197 + cell $xor $xor$libresoc.v:146004$7242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303724,10 +306237,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:144186$7197_Y + connect \Y $xor$libresoc.v:146004$7242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:144212$7223 + cell $xor $xor$libresoc.v:146030$7268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303735,10 +306248,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:144212$7223_Y + connect \Y $xor$libresoc.v:146030$7268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:144213$7224 + cell $xor $xor$libresoc.v:146031$7269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303746,10 +306259,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:144213$7224_Y + connect \Y $xor$libresoc.v:146031$7269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:144214$7225 + cell $xor $xor$libresoc.v:146032$7270 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -303757,10 +306270,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:144214$7225_Y + connect \Y $xor$libresoc.v:146032$7270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:144217$7228 + cell $xor $xor$libresoc.v:146035$7273 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -303768,24 +306281,24 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:144217$7228_Y + connect \Y $xor$libresoc.v:146035$7273_Y end - attribute \src "libresoc.v:143717.7-143717.20" - process $proc$libresoc.v:143717$7275 + attribute \src "libresoc.v:145531.7-145531.20" + process $proc$libresoc.v:145531$7320 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144235.3-144244.6" - process $proc$libresoc.v:144235$7246 + attribute \src "libresoc.v:146053.3-146062.6" + process $proc$libresoc.v:146053$7291 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:144236.5-144236.29" + attribute \src "libresoc.v:146054.5-146054.29" switch \initial - attribute \src "libresoc.v:144236.9-144236.17" + attribute \src "libresoc.v:146054.9-146054.17" case 1'1 case end @@ -303801,13 +306314,13 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:144245.3-144267.6" - process $proc$libresoc.v:144245$7247 + attribute \src "libresoc.v:146063.3-146085.6" + process $proc$libresoc.v:146063$7292 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:144246.5-144246.29" + attribute \src "libresoc.v:146064.5-146064.29" switch \initial - attribute \src "libresoc.v:144246.9-144246.17" + attribute \src "libresoc.v:146064.9-146064.17" case 1'1 case end @@ -303840,14 +306353,14 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:144268.3-144278.6" - process $proc$libresoc.v:144268$7248 + attribute \src "libresoc.v:146086.3-146096.6" + process $proc$libresoc.v:146086$7293 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:144269.5-144269.29" + attribute \src "libresoc.v:146087.5-146087.29" switch \initial - attribute \src "libresoc.v:144269.9-144269.17" + attribute \src "libresoc.v:146087.9-146087.17" case 1'1 case end @@ -303863,14 +306376,14 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:144279.3-144305.6" - process $proc$libresoc.v:144279$7249 + attribute \src "libresoc.v:146097.3-146123.6" + process $proc$libresoc.v:146097$7294 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:144280.5-144280.29" + attribute \src "libresoc.v:146098.5-146098.29" switch \initial - attribute \src "libresoc.v:144280.9-144280.17" + attribute \src "libresoc.v:146098.9-146098.17" case 1'1 case end @@ -303908,14 +306421,14 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:144306.3-144324.6" - process $proc$libresoc.v:144306$7250 + attribute \src "libresoc.v:146124.3-146142.6" + process $proc$libresoc.v:146124$7295 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:144307.5-144307.29" + attribute \src "libresoc.v:146125.5-146125.29" switch \initial - attribute \src "libresoc.v:144307.9-144307.17" + attribute \src "libresoc.v:146125.9-146125.17" case 1'1 case end @@ -303941,14 +306454,14 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:144325.3-144343.6" - process $proc$libresoc.v:144325$7251 + attribute \src "libresoc.v:146143.3-146161.6" + process $proc$libresoc.v:146143$7296 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:144326.5-144326.29" + attribute \src "libresoc.v:146144.5-146144.29" switch \initial - attribute \src "libresoc.v:144326.9-144326.17" + attribute \src "libresoc.v:146144.9-146144.17" case 1'1 case end @@ -303974,14 +306487,14 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:144344.3-144370.6" - process $proc$libresoc.v:144344$7252 + attribute \src "libresoc.v:146162.3-146188.6" + process $proc$libresoc.v:146162$7297 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:144345.5-144345.29" + attribute \src "libresoc.v:146163.5-146163.29" switch \initial - attribute \src "libresoc.v:144345.9-144345.17" + attribute \src "libresoc.v:146163.9-146163.17" case 1'1 case end @@ -304017,14 +306530,14 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:144371.3-144396.6" - process $proc$libresoc.v:144371$7253 + attribute \src "libresoc.v:146189.3-146214.6" + process $proc$libresoc.v:146189$7298 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:144372.5-144372.29" + attribute \src "libresoc.v:146190.5-146190.29" switch \initial - attribute \src "libresoc.v:144372.9-144372.17" + attribute \src "libresoc.v:146190.9-146190.17" case 1'1 case end @@ -304056,14 +306569,14 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:144397.3-144411.6" - process $proc$libresoc.v:144397$7254 + attribute \src "libresoc.v:146215.3-146229.6" + process $proc$libresoc.v:146215$7299 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:144398.5-144398.29" + attribute \src "libresoc.v:146216.5-146216.29" switch \initial - attribute \src "libresoc.v:144398.9-144398.17" + attribute \src "libresoc.v:146216.9-146216.17" case 1'1 case end @@ -304083,14 +306596,14 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:144412.3-144449.6" - process $proc$libresoc.v:144412$7255 + attribute \src "libresoc.v:146230.3-146267.6" + process $proc$libresoc.v:146230$7300 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:144413.5-144413.29" + attribute \src "libresoc.v:146231.5-146231.29" switch \initial - attribute \src "libresoc.v:144413.9-144413.17" + attribute \src "libresoc.v:146231.9-146231.17" case 1'1 case end @@ -304143,14 +306656,14 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:144450.3-144468.6" - process $proc$libresoc.v:144450$7256 + attribute \src "libresoc.v:146268.3-146286.6" + process $proc$libresoc.v:146268$7301 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:144451.5-144451.29" + attribute \src "libresoc.v:146269.5-146269.29" switch \initial - attribute \src "libresoc.v:144451.9-144451.17" + attribute \src "libresoc.v:146269.9-146269.17" case 1'1 case end @@ -304174,14 +306687,14 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:144469.3-144482.6" - process $proc$libresoc.v:144469$7257 + attribute \src "libresoc.v:146287.3-146300.6" + process $proc$libresoc.v:146287$7302 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:144470.5-144470.29" + attribute \src "libresoc.v:146288.5-146288.29" switch \initial - attribute \src "libresoc.v:144470.9-144470.17" + attribute \src "libresoc.v:146288.9-146288.17" case 1'1 case end @@ -304198,13 +306711,13 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:144483.3-144505.6" - process $proc$libresoc.v:144483$7258 + attribute \src "libresoc.v:146301.3-146323.6" + process $proc$libresoc.v:146301$7303 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:144484.5-144484.29" + attribute \src "libresoc.v:146302.5-146302.29" switch \initial - attribute \src "libresoc.v:144484.9-144484.17" + attribute \src "libresoc.v:146302.9-146302.17" case 1'1 case end @@ -304237,14 +306750,14 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:144506.3-144516.6" - process $proc$libresoc.v:144506$7259 + attribute \src "libresoc.v:146324.3-146334.6" + process $proc$libresoc.v:146324$7304 assign { } { } assign { } { } - assign $0\xer_ca$20[1:0]$7260 $1\xer_ca$20[1:0]$7261 - attribute \src "libresoc.v:144507.5-144507.29" + assign $0\xer_ca$20[1:0]$7305 $1\xer_ca$20[1:0]$7306 + attribute \src "libresoc.v:146325.5-146325.29" switch \initial - attribute \src "libresoc.v:144507.9-144507.17" + attribute \src "libresoc.v:146325.9-146325.17" case 1'1 case end @@ -304253,21 +306766,21 @@ module \main attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } - assign $1\xer_ca$20[1:0]$7261 \ca + assign $1\xer_ca$20[1:0]$7306 \ca case - assign $1\xer_ca$20[1:0]$7261 2'00 + assign $1\xer_ca$20[1:0]$7306 2'00 end sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$7260 + update \xer_ca$20 $0\xer_ca$20[1:0]$7305 end - attribute \src "libresoc.v:144517.3-144527.6" - process $proc$libresoc.v:144517$7262 + attribute \src "libresoc.v:146335.3-146345.6" + process $proc$libresoc.v:146335$7307 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:144518.5-144518.29" + attribute \src "libresoc.v:146336.5-146336.29" switch \initial - attribute \src "libresoc.v:144518.9-144518.17" + attribute \src "libresoc.v:146336.9-146336.17" case 1'1 case end @@ -304283,14 +306796,14 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:144528.3-144541.6" - process $proc$libresoc.v:144528$7263 + attribute \src "libresoc.v:146346.3-146359.6" + process $proc$libresoc.v:146346$7308 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:144529.5-144529.29" + attribute \src "libresoc.v:146347.5-146347.29" switch \initial - attribute \src "libresoc.v:144529.9-144529.17" + attribute \src "libresoc.v:146347.9-146347.17" case 1'1 case end @@ -304307,14 +306820,14 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:144542.3-144552.6" - process $proc$libresoc.v:144542$7264 + attribute \src "libresoc.v:146360.3-146370.6" + process $proc$libresoc.v:146360$7309 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:144543.5-144543.29" + attribute \src "libresoc.v:146361.5-146361.29" switch \initial - attribute \src "libresoc.v:144543.9-144543.17" + attribute \src "libresoc.v:146361.9-146361.17" case 1'1 case end @@ -304330,14 +306843,14 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:144553.3-144563.6" - process $proc$libresoc.v:144553$7265 + attribute \src "libresoc.v:146371.3-146381.6" + process $proc$libresoc.v:146371$7310 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:144554.5-144554.29" + attribute \src "libresoc.v:146372.5-146372.29" switch \initial - attribute \src "libresoc.v:144554.9-144554.17" + attribute \src "libresoc.v:146372.9-146372.17" case 1'1 case end @@ -304353,14 +306866,14 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:144564.3-144574.6" - process $proc$libresoc.v:144564$7266 + attribute \src "libresoc.v:146382.3-146392.6" + process $proc$libresoc.v:146382$7311 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:144565.5-144565.29" + attribute \src "libresoc.v:146383.5-146383.29" switch \initial - attribute \src "libresoc.v:144565.9-144565.17" + attribute \src "libresoc.v:146383.9-146383.17" case 1'1 case end @@ -304376,14 +306889,14 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:144575.3-144594.6" - process $proc$libresoc.v:144575$7267 + attribute \src "libresoc.v:146393.3-146412.6" + process $proc$libresoc.v:146393$7312 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:144576.5-144576.29" + attribute \src "libresoc.v:146394.5-146394.29" switch \initial - attribute \src "libresoc.v:144576.9-144576.17" + attribute \src "libresoc.v:146394.9-146394.17" case 1'1 case end @@ -304406,14 +306919,14 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:144595.3-144604.6" - process $proc$libresoc.v:144595$7268 + attribute \src "libresoc.v:146413.3-146422.6" + process $proc$libresoc.v:146413$7313 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:144596.5-144596.29" + attribute \src "libresoc.v:146414.5-146414.29" switch \initial - attribute \src "libresoc.v:144596.9-144596.17" + attribute \src "libresoc.v:146414.9-146414.17" case 1'1 case end @@ -304429,14 +306942,14 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:144605.3-144614.6" - process $proc$libresoc.v:144605$7269 + attribute \src "libresoc.v:146423.3-146432.6" + process $proc$libresoc.v:146423$7314 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:144606.5-144606.29" + attribute \src "libresoc.v:146424.5-146424.29" switch \initial - attribute \src "libresoc.v:144606.9-144606.17" + attribute \src "libresoc.v:146424.9-146424.17" case 1'1 case end @@ -304452,14 +306965,14 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:144615.3-144624.6" - process $proc$libresoc.v:144615$7270 + attribute \src "libresoc.v:146433.3-146442.6" + process $proc$libresoc.v:146433$7315 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:144616.5-144616.29" + attribute \src "libresoc.v:146434.5-146434.29" switch \initial - attribute \src "libresoc.v:144616.9-144616.17" + attribute \src "libresoc.v:146434.9-146434.17" case 1'1 case end @@ -304475,14 +306988,14 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:144625.3-144635.6" - process $proc$libresoc.v:144625$7271 + attribute \src "libresoc.v:146443.3-146453.6" + process $proc$libresoc.v:146443$7316 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:144626.5-144626.29" + attribute \src "libresoc.v:146444.5-146444.29" switch \initial - attribute \src "libresoc.v:144626.9-144626.17" + attribute \src "libresoc.v:146444.9-146444.17" case 1'1 case end @@ -304498,14 +307011,14 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:144636.3-144646.6" - process $proc$libresoc.v:144636$7272 + attribute \src "libresoc.v:146454.3-146464.6" + process $proc$libresoc.v:146454$7317 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:144637.5-144637.29" + attribute \src "libresoc.v:146455.5-146455.29" switch \initial - attribute \src "libresoc.v:144637.9-144637.17" + attribute \src "libresoc.v:146455.9-146455.17" case 1'1 case end @@ -304521,14 +307034,14 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:144647.3-144657.6" - process $proc$libresoc.v:144647$7273 + attribute \src "libresoc.v:146465.3-146475.6" + process $proc$libresoc.v:146465$7318 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:144648.5-144648.29" + attribute \src "libresoc.v:146466.5-146466.29" switch \initial - attribute \src "libresoc.v:144648.9-144648.17" + attribute \src "libresoc.v:146466.9-146466.17" case 1'1 case end @@ -304544,14 +307057,14 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:144658.3-144668.6" - process $proc$libresoc.v:144658$7274 + attribute \src "libresoc.v:146476.3-146486.6" + process $proc$libresoc.v:146476$7319 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:144659.5-144659.29" + attribute \src "libresoc.v:146477.5-146477.29" switch \initial - attribute \src "libresoc.v:144659.9-144659.17" + attribute \src "libresoc.v:146477.9-146477.17" case 1'1 case end @@ -304567,88 +307080,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:144174$7185_Y - connect \$101 $eq$libresoc.v:144175$7186_Y - connect \$103 $eq$libresoc.v:144176$7187_Y - connect \$105 $eq$libresoc.v:144177$7188_Y - connect \$107 $reduce_or$libresoc.v:144178$7189_Y - connect \$109 $xor$libresoc.v:144179$7190_Y - connect \$111 $xor$libresoc.v:144180$7191_Y - connect \$113 $xor$libresoc.v:144181$7192_Y - connect \$116 $xor$libresoc.v:144182$7193_Y - connect \$115 $not$libresoc.v:144183$7194_Y - connect \$119 $and$libresoc.v:144184$7195_Y - connect \$121 $xor$libresoc.v:144185$7196_Y - connect \$124 $xor$libresoc.v:144186$7197_Y - connect \$123 $not$libresoc.v:144187$7198_Y - connect \$127 $and$libresoc.v:144188$7199_Y - connect \$129 $eq$libresoc.v:144189$7200_Y - connect \$131 $eq$libresoc.v:144190$7201_Y - connect \$133 $eq$libresoc.v:144191$7202_Y - connect \$135 $eq$libresoc.v:144192$7203_Y - connect \$137 $eq$libresoc.v:144193$7204_Y - connect \$139 $eq$libresoc.v:144194$7205_Y - connect \$141 $eq$libresoc.v:144195$7206_Y - connect \$143 $eq$libresoc.v:144196$7207_Y - connect \$22 $eq$libresoc.v:144197$7208_Y - connect \$24 $not$libresoc.v:144198$7209_Y - connect \$26 $eq$libresoc.v:144199$7210_Y - connect \$28 $eq$libresoc.v:144200$7211_Y - connect \$30 $eq$libresoc.v:144201$7212_Y - connect \$32 $eq$libresoc.v:144202$7213_Y - connect \$34 $or$libresoc.v:144203$7214_Y - connect \$36 $eq$libresoc.v:144204$7215_Y - connect \$38 $eq$libresoc.v:144205$7216_Y - connect \$40 $or$libresoc.v:144206$7217_Y - connect \$42 $eq$libresoc.v:144207$7218_Y - connect \$44 $eq$libresoc.v:144208$7219_Y - connect \$46 $or$libresoc.v:144209$7220_Y - connect \$49 $add$libresoc.v:144210$7221_Y - connect \$51 $not$libresoc.v:144211$7222_Y - connect \$53 $xor$libresoc.v:144212$7223_Y - connect \$55 $xor$libresoc.v:144213$7224_Y - connect \$59 $xor$libresoc.v:144214$7225_Y - connect \$58 $reduce_or$libresoc.v:144215$7226_Y - connect \$57 $not$libresoc.v:144216$7227_Y - connect \$65 $xor$libresoc.v:144217$7228_Y - connect \$64 $reduce_or$libresoc.v:144218$7229_Y - connect \$63 $not$libresoc.v:144219$7230_Y - connect \$69 $or$libresoc.v:144220$7231_Y - connect \$71 $and$libresoc.v:144221$7232_Y - connect \$73 $ne$libresoc.v:144222$7233_Y - connect \$75 $not$libresoc.v:144223$7234_Y - connect \$77 $not$libresoc.v:144224$7235_Y - connect \$79 $or$libresoc.v:144225$7236_Y - connect \$81 $and$libresoc.v:144226$7237_Y - connect \$83 $ternary$libresoc.v:144227$7238_Y - connect \$85 $or$libresoc.v:144228$7239_Y - connect \$87 $and$libresoc.v:144229$7240_Y - connect \$89 $ternary$libresoc.v:144230$7241_Y - connect \$91 $or$libresoc.v:144231$7242_Y - connect \$93 $and$libresoc.v:144232$7243_Y - connect \$95 $ne$libresoc.v:144233$7244_Y - connect \$97 $ternary$libresoc.v:144234$7245_Y + connect \$99 $reduce_or$libresoc.v:145992$7230_Y + connect \$101 $eq$libresoc.v:145993$7231_Y + connect \$103 $eq$libresoc.v:145994$7232_Y + connect \$105 $eq$libresoc.v:145995$7233_Y + connect \$107 $reduce_or$libresoc.v:145996$7234_Y + connect \$109 $xor$libresoc.v:145997$7235_Y + connect \$111 $xor$libresoc.v:145998$7236_Y + connect \$113 $xor$libresoc.v:145999$7237_Y + connect \$116 $xor$libresoc.v:146000$7238_Y + connect \$115 $not$libresoc.v:146001$7239_Y + connect \$119 $and$libresoc.v:146002$7240_Y + connect \$121 $xor$libresoc.v:146003$7241_Y + connect \$124 $xor$libresoc.v:146004$7242_Y + connect \$123 $not$libresoc.v:146005$7243_Y + connect \$127 $and$libresoc.v:146006$7244_Y + connect \$129 $eq$libresoc.v:146007$7245_Y + connect \$131 $eq$libresoc.v:146008$7246_Y + connect \$133 $eq$libresoc.v:146009$7247_Y + connect \$135 $eq$libresoc.v:146010$7248_Y + connect \$137 $eq$libresoc.v:146011$7249_Y + connect \$139 $eq$libresoc.v:146012$7250_Y + connect \$141 $eq$libresoc.v:146013$7251_Y + connect \$143 $eq$libresoc.v:146014$7252_Y + connect \$22 $eq$libresoc.v:146015$7253_Y + connect \$24 $not$libresoc.v:146016$7254_Y + connect \$26 $eq$libresoc.v:146017$7255_Y + connect \$28 $eq$libresoc.v:146018$7256_Y + connect \$30 $eq$libresoc.v:146019$7257_Y + connect \$32 $eq$libresoc.v:146020$7258_Y + connect \$34 $or$libresoc.v:146021$7259_Y + connect \$36 $eq$libresoc.v:146022$7260_Y + connect \$38 $eq$libresoc.v:146023$7261_Y + connect \$40 $or$libresoc.v:146024$7262_Y + connect \$42 $eq$libresoc.v:146025$7263_Y + connect \$44 $eq$libresoc.v:146026$7264_Y + connect \$46 $or$libresoc.v:146027$7265_Y + connect \$49 $add$libresoc.v:146028$7266_Y + connect \$51 $not$libresoc.v:146029$7267_Y + connect \$53 $xor$libresoc.v:146030$7268_Y + connect \$55 $xor$libresoc.v:146031$7269_Y + connect \$59 $xor$libresoc.v:146032$7270_Y + connect \$58 $reduce_or$libresoc.v:146033$7271_Y + connect \$57 $not$libresoc.v:146034$7272_Y + connect \$65 $xor$libresoc.v:146035$7273_Y + connect \$64 $reduce_or$libresoc.v:146036$7274_Y + connect \$63 $not$libresoc.v:146037$7275_Y + connect \$69 $or$libresoc.v:146038$7276_Y + connect \$71 $and$libresoc.v:146039$7277_Y + connect \$73 $ne$libresoc.v:146040$7278_Y + connect \$75 $not$libresoc.v:146041$7279_Y + connect \$77 $not$libresoc.v:146042$7280_Y + connect \$79 $or$libresoc.v:146043$7281_Y + connect \$81 $and$libresoc.v:146044$7282_Y + connect \$83 $ternary$libresoc.v:146045$7283_Y + connect \$85 $or$libresoc.v:146046$7284_Y + connect \$87 $and$libresoc.v:146047$7285_Y + connect \$89 $ternary$libresoc.v:146048$7286_Y + connect \$91 $or$libresoc.v:146049$7287_Y + connect \$93 $and$libresoc.v:146050$7288_Y + connect \$95 $ne$libresoc.v:146051$7289_Y + connect \$97 $ternary$libresoc.v:146052$7290_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:144677.1-145087.10" +attribute \src "libresoc.v:146495.1-146909.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 - attribute \src "libresoc.v:144678.7-144678.20" + attribute \src "libresoc.v:146496.7-146496.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145039.3-145069.6" + attribute \src "libresoc.v:146861.3-146891.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:145004.3-145038.6" + attribute \src "libresoc.v:146826.3-146860.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:145039.3-145069.6" + attribute \src "libresoc.v:146861.3-146891.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:145004.3-145038.6" + attribute \src "libresoc.v:146826.3-146860.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:144678.7-144678.15" + attribute \src "libresoc.v:146496.7-146496.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -304701,37 +307214,39 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire \rotator_sign_ext_rs attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 24 \sr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -304834,6 +307349,7 @@ module \main$114 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -304910,6 +307426,7 @@ module \main$114 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -304959,7 +307476,7 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:144988.11-145003.4" + attribute \src "libresoc.v:146810.11-146825.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -304976,22 +307493,22 @@ module \main$114 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:144678.7-144678.20" - process $proc$libresoc.v:144678$7278 + attribute \src "libresoc.v:146496.7-146496.20" + process $proc$libresoc.v:146496$7323 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145004.3-145038.6" - process $proc$libresoc.v:145004$7276 + attribute \src "libresoc.v:146826.3-146860.6" + process $proc$libresoc.v:146826$7321 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:145005.5-145005.29" + attribute \src "libresoc.v:146827.5-146827.29" switch \initial - attribute \src "libresoc.v:145005.9-145005.17" + attribute \src "libresoc.v:146827.9-146827.17" case 1'1 case end @@ -305023,14 +307540,14 @@ module \main$114 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:145039.3-145069.6" - process $proc$libresoc.v:145039$7277 + attribute \src "libresoc.v:146861.3-146891.6" + process $proc$libresoc.v:146861$7322 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:145040.5-145040.29" + attribute \src "libresoc.v:146862.5-146862.29" switch \initial - attribute \src "libresoc.v:145040.9-145040.17" + attribute \src "libresoc.v:146862.9-146862.17" case 1'1 case end @@ -305084,109 +307601,109 @@ module \main$114 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:145091.1-145623.10" +attribute \src "libresoc.v:146913.1-147449.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:145530.3-145553.6" + attribute \src "libresoc.v:147356.3-147379.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:145409.3-145420.6" + attribute \src "libresoc.v:147235.3-147246.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:145421.3-145447.6" + attribute \src "libresoc.v:147247.3-147273.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:145448.3-145466.6" + attribute \src "libresoc.v:147274.3-147292.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:145502.3-145516.6" + attribute \src "libresoc.v:147328.3-147342.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:145580.3-145600.6" + attribute \src "libresoc.v:147406.3-147426.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:145554.3-145566.6" + attribute \src "libresoc.v:147380.3-147392.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:145517.3-145529.6" + attribute \src "libresoc.v:147343.3-147355.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:145601.3-145613.6" + attribute \src "libresoc.v:147427.3-147439.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:145567.3-145579.6" - wire width 64 $0\fast1$10[63:0]$7311 - attribute \src "libresoc.v:145467.3-145481.6" + attribute \src "libresoc.v:147393.3-147405.6" + wire width 64 $0\fast1$10[63:0]$7356 + attribute \src "libresoc.v:147293.3-147307.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:145482.3-145491.6" - wire width 64 $0\fast2$11[63:0]$7303 - attribute \src "libresoc.v:145492.3-145501.6" + attribute \src "libresoc.v:147308.3-147317.6" + wire width 64 $0\fast2$11[63:0]$7348 + attribute \src "libresoc.v:147318.3-147327.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:145092.7-145092.20" + attribute \src "libresoc.v:146914.7-146914.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145530.3-145553.6" + attribute \src "libresoc.v:147356.3-147379.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:145409.3-145420.6" + attribute \src "libresoc.v:147235.3-147246.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:145421.3-145447.6" + attribute \src "libresoc.v:147247.3-147273.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:145448.3-145466.6" + attribute \src "libresoc.v:147274.3-147292.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:145502.3-145516.6" + attribute \src "libresoc.v:147328.3-147342.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:145580.3-145600.6" + attribute \src "libresoc.v:147406.3-147426.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:145554.3-145566.6" + attribute \src "libresoc.v:147380.3-147392.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:145517.3-145529.6" + attribute \src "libresoc.v:147343.3-147355.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:145601.3-145613.6" + attribute \src "libresoc.v:147427.3-147439.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:145567.3-145579.6" - wire width 64 $1\fast1$10[63:0]$7312 - attribute \src "libresoc.v:145467.3-145481.6" + attribute \src "libresoc.v:147393.3-147405.6" + wire width 64 $1\fast1$10[63:0]$7357 + attribute \src "libresoc.v:147293.3-147307.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:145482.3-145491.6" - wire width 64 $1\fast2$11[63:0]$7304 - attribute \src "libresoc.v:145492.3-145501.6" + attribute \src "libresoc.v:147308.3-147317.6" + wire width 64 $1\fast2$11[63:0]$7349 + attribute \src "libresoc.v:147318.3-147327.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:145530.3-145553.6" + attribute \src "libresoc.v:147356.3-147379.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:145421.3-145447.6" + attribute \src "libresoc.v:147247.3-147273.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:145580.3-145600.6" + attribute \src "libresoc.v:147406.3-147426.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:145393.18-145393.119" - wire width 65 $add$libresoc.v:145393$7281_Y - attribute \src "libresoc.v:145408.18-145408.113" - wire width 65 $add$libresoc.v:145408$7297_Y - attribute \src "libresoc.v:145400.18-145400.115" - wire $and$libresoc.v:145400$7288_Y - attribute \src "libresoc.v:145401.18-145401.117" - wire $and$libresoc.v:145401$7289_Y - attribute \src "libresoc.v:145407.18-145407.118" - wire $and$libresoc.v:145407$7296_Y - attribute \src "libresoc.v:145391.18-145391.120" - wire $eq$libresoc.v:145391$7279_Y - attribute \src "libresoc.v:145394.18-145394.111" - wire $eq$libresoc.v:145394$7282_Y - attribute \src "libresoc.v:145396.18-145396.111" - wire $eq$libresoc.v:145396$7284_Y - attribute \src "libresoc.v:145397.18-145397.111" - wire $eq$libresoc.v:145397$7285_Y - attribute \src "libresoc.v:145398.18-145398.109" - wire $eq$libresoc.v:145398$7286_Y - attribute \src "libresoc.v:145403.18-145403.98" - wire width 64 $extend$libresoc.v:145403$7291_Y - attribute \src "libresoc.v:145399.18-145399.104" - wire $not$libresoc.v:145399$7287_Y - attribute \src "libresoc.v:145406.18-145406.112" - wire $not$libresoc.v:145406$7295_Y - attribute \src "libresoc.v:145392.18-145392.116" - wire $or$libresoc.v:145392$7280_Y - attribute \src "libresoc.v:145395.18-145395.109" - wire $or$libresoc.v:145395$7283_Y - attribute \src "libresoc.v:145403.18-145403.98" - wire width 64 $pos$libresoc.v:145403$7292_Y - attribute \src "libresoc.v:145404.18-145404.103" - wire $reduce_or$libresoc.v:145404$7293_Y - attribute \src "libresoc.v:145402.18-145402.108" - wire width 65 $sub$libresoc.v:145402$7290_Y - attribute \src "libresoc.v:145405.18-145405.108" - wire $xor$libresoc.v:145405$7294_Y + attribute \src "libresoc.v:147219.18-147219.119" + wire width 65 $add$libresoc.v:147219$7326_Y + attribute \src "libresoc.v:147234.18-147234.113" + wire width 65 $add$libresoc.v:147234$7342_Y + attribute \src "libresoc.v:147226.18-147226.115" + wire $and$libresoc.v:147226$7333_Y + attribute \src "libresoc.v:147227.18-147227.117" + wire $and$libresoc.v:147227$7334_Y + attribute \src "libresoc.v:147233.18-147233.118" + wire $and$libresoc.v:147233$7341_Y + attribute \src "libresoc.v:147217.18-147217.120" + wire $eq$libresoc.v:147217$7324_Y + attribute \src "libresoc.v:147220.18-147220.111" + wire $eq$libresoc.v:147220$7327_Y + attribute \src "libresoc.v:147222.18-147222.111" + wire $eq$libresoc.v:147222$7329_Y + attribute \src "libresoc.v:147223.18-147223.111" + wire $eq$libresoc.v:147223$7330_Y + attribute \src "libresoc.v:147224.18-147224.109" + wire $eq$libresoc.v:147224$7331_Y + attribute \src "libresoc.v:147229.18-147229.98" + wire width 64 $extend$libresoc.v:147229$7336_Y + attribute \src "libresoc.v:147225.18-147225.104" + wire $not$libresoc.v:147225$7332_Y + attribute \src "libresoc.v:147232.18-147232.112" + wire $not$libresoc.v:147232$7340_Y + attribute \src "libresoc.v:147218.18-147218.116" + wire $or$libresoc.v:147218$7325_Y + attribute \src "libresoc.v:147221.18-147221.109" + wire $or$libresoc.v:147221$7328_Y + attribute \src "libresoc.v:147229.18-147229.98" + wire width 64 $pos$libresoc.v:147229$7337_Y + attribute \src "libresoc.v:147230.18-147230.103" + wire $reduce_or$libresoc.v:147230$7338_Y + attribute \src "libresoc.v:147228.18-147228.108" + wire width 65 $sub$libresoc.v:147228$7335_Y + attribute \src "libresoc.v:147231.18-147231.108" + wire $xor$libresoc.v:147231$7339_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -305244,37 +307761,39 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 13 \br_op__cia$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \br_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 15 \br_op__fn_unit$4 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 15 \br_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 5 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -305361,6 +307880,7 @@ module \main$22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \br_op__insn_type attribute \enum_base_type "MicrOp" @@ -305437,6 +307957,7 @@ module \main$22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 14 \br_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -305473,7 +307994,7 @@ module \main$22 wire width 64 output 23 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \fast2_ok - attribute \src "libresoc.v:145092.7-145092.15" + attribute \src "libresoc.v:146914.7-146914.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid @@ -305484,7 +308005,7 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:145393$7281 + cell $add $add$libresoc.v:147219$7326 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -305492,10 +308013,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:145393$7281_Y + connect \Y $add$libresoc.v:147219$7326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:145408$7297 + cell $add $add$libresoc.v:147234$7342 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -305503,10 +308024,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:145408$7297_Y + connect \Y $add$libresoc.v:147234$7342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:145400$7288 + cell $and $and$libresoc.v:147226$7333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305514,10 +308035,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:145400$7288_Y + connect \Y $and$libresoc.v:147226$7333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:145401$7289 + cell $and $and$libresoc.v:147227$7334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305525,10 +308046,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:145401$7289_Y + connect \Y $and$libresoc.v:147227$7334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:145407$7296 + cell $and $and$libresoc.v:147233$7341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305536,10 +308057,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:145407$7296_Y + connect \Y $and$libresoc.v:147233$7341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:145391$7279 + cell $eq $eq$libresoc.v:147217$7324 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305547,10 +308068,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:145391$7279_Y + connect \Y $eq$libresoc.v:147217$7324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:145394$7282 + cell $eq $eq$libresoc.v:147220$7327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305558,10 +308079,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:145394$7282_Y + connect \Y $eq$libresoc.v:147220$7327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:145396$7284 + cell $eq $eq$libresoc.v:147222$7329 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -305569,10 +308090,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:145396$7284_Y + connect \Y $eq$libresoc.v:147222$7329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:145397$7285 + cell $eq $eq$libresoc.v:147223$7330 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -305580,10 +308101,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:145397$7285_Y + connect \Y $eq$libresoc.v:147223$7330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:145398$7286 + cell $eq $eq$libresoc.v:147224$7331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305591,34 +308112,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:145398$7286_Y + connect \Y $eq$libresoc.v:147224$7331_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:145403$7291 + cell $pos $extend$libresoc.v:147229$7336 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:145403$7291_Y + connect \Y $extend$libresoc.v:147229$7336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:145399$7287 + cell $not $not$libresoc.v:147225$7332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:145399$7287_Y + connect \Y $not$libresoc.v:147225$7332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:145406$7295 + cell $not $not$libresoc.v:147232$7340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:145406$7295_Y + connect \Y $not$libresoc.v:147232$7340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:145392$7280 + cell $or $or$libresoc.v:147218$7325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305626,10 +308147,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:145392$7280_Y + connect \Y $or$libresoc.v:147218$7325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:145395$7283 + cell $or $or$libresoc.v:147221$7328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305637,26 +308158,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:145395$7283_Y + connect \Y $or$libresoc.v:147221$7328_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:145403$7292 + cell $pos $pos$libresoc.v:147229$7337 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:145403$7291_Y - connect \Y $pos$libresoc.v:145403$7292_Y + connect \A $extend$libresoc.v:147229$7336_Y + connect \Y $pos$libresoc.v:147229$7337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:145404$7293 + cell $reduce_or $reduce_or$libresoc.v:147230$7338 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:145404$7293_Y + connect \Y $reduce_or$libresoc.v:147230$7338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:145402$7290 + cell $sub $sub$libresoc.v:147228$7335 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -305664,10 +308185,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:145402$7290_Y + connect \Y $sub$libresoc.v:147228$7335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:145405$7294 + cell $xor $xor$libresoc.v:147231$7339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305675,23 +308196,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:145405$7294_Y + connect \Y $xor$libresoc.v:147231$7339_Y end - attribute \src "libresoc.v:145092.7-145092.20" - process $proc$libresoc.v:145092$7315 + attribute \src "libresoc.v:146914.7-146914.20" + process $proc$libresoc.v:146914$7360 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145409.3-145420.6" - process $proc$libresoc.v:145409$7298 + attribute \src "libresoc.v:147235.3-147246.6" + process $proc$libresoc.v:147235$7343 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:145410.5-145410.29" + attribute \src "libresoc.v:147236.5-147236.29" switch \initial - attribute \src "libresoc.v:145410.9-145410.17" + attribute \src "libresoc.v:147236.9-147236.17" case 1'1 case end @@ -305709,14 +308230,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:145421.3-145447.6" - process $proc$libresoc.v:145421$7299 + attribute \src "libresoc.v:147247.3-147273.6" + process $proc$libresoc.v:147247$7344 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:145422.5-145422.29" + attribute \src "libresoc.v:147248.5-147248.29" switch \initial - attribute \src "libresoc.v:145422.9-145422.17" + attribute \src "libresoc.v:147248.9-147248.17" case 1'1 case end @@ -305751,14 +308272,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:145448.3-145466.6" - process $proc$libresoc.v:145448$7300 + attribute \src "libresoc.v:147274.3-147292.6" + process $proc$libresoc.v:147274$7345 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:145449.5-145449.29" + attribute \src "libresoc.v:147275.5-147275.29" switch \initial - attribute \src "libresoc.v:145449.9-145449.17" + attribute \src "libresoc.v:147275.9-147275.17" case 1'1 case end @@ -305782,14 +308303,14 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:145467.3-145481.6" - process $proc$libresoc.v:145467$7301 + attribute \src "libresoc.v:147293.3-147307.6" + process $proc$libresoc.v:147293$7346 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:145468.5-145468.29" + attribute \src "libresoc.v:147294.5-147294.29" switch \initial - attribute \src "libresoc.v:145468.9-145468.17" + attribute \src "libresoc.v:147294.9-147294.17" case 1'1 case end @@ -305809,14 +308330,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:145482.3-145491.6" - process $proc$libresoc.v:145482$7302 + attribute \src "libresoc.v:147308.3-147317.6" + process $proc$libresoc.v:147308$7347 assign { } { } assign { } { } - assign $0\fast2$11[63:0]$7303 $1\fast2$11[63:0]$7304 - attribute \src "libresoc.v:145483.5-145483.29" + assign $0\fast2$11[63:0]$7348 $1\fast2$11[63:0]$7349 + attribute \src "libresoc.v:147309.5-147309.29" switch \initial - attribute \src "libresoc.v:145483.9-145483.17" + attribute \src "libresoc.v:147309.9-147309.17" case 1'1 case end @@ -305825,21 +308346,21 @@ module \main$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast2$11[63:0]$7304 \$48 [63:0] + assign $1\fast2$11[63:0]$7349 \$48 [63:0] case - assign $1\fast2$11[63:0]$7304 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$11[63:0]$7349 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$11 $0\fast2$11[63:0]$7303 + update \fast2$11 $0\fast2$11[63:0]$7348 end - attribute \src "libresoc.v:145492.3-145501.6" - process $proc$libresoc.v:145492$7305 + attribute \src "libresoc.v:147318.3-147327.6" + process $proc$libresoc.v:147318$7350 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:145493.5-145493.29" + attribute \src "libresoc.v:147319.5-147319.29" switch \initial - attribute \src "libresoc.v:145493.9-145493.17" + attribute \src "libresoc.v:147319.9-147319.17" case 1'1 case end @@ -305855,14 +308376,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:145502.3-145516.6" - process $proc$libresoc.v:145502$7306 + attribute \src "libresoc.v:147328.3-147342.6" + process $proc$libresoc.v:147328$7351 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:145503.5-145503.29" + attribute \src "libresoc.v:147329.5-147329.29" switch \initial - attribute \src "libresoc.v:145503.9-145503.17" + attribute \src "libresoc.v:147329.9-147329.17" case 1'1 case end @@ -305890,14 +308411,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:145517.3-145529.6" - process $proc$libresoc.v:145517$7307 + attribute \src "libresoc.v:147343.3-147355.6" + process $proc$libresoc.v:147343$7352 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:145518.5-145518.29" + attribute \src "libresoc.v:147344.5-147344.29" switch \initial - attribute \src "libresoc.v:145518.9-145518.17" + attribute \src "libresoc.v:147344.9-147344.17" case 1'1 case end @@ -305914,14 +308435,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:145530.3-145553.6" - process $proc$libresoc.v:145530$7308 + attribute \src "libresoc.v:147356.3-147379.6" + process $proc$libresoc.v:147356$7353 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:145531.5-145531.29" + attribute \src "libresoc.v:147357.5-147357.29" switch \initial - attribute \src "libresoc.v:145531.9-145531.17" + attribute \src "libresoc.v:147357.9-147357.17" case 1'1 case end @@ -305956,14 +308477,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:145554.3-145566.6" - process $proc$libresoc.v:145554$7309 + attribute \src "libresoc.v:147380.3-147392.6" + process $proc$libresoc.v:147380$7354 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:145555.5-145555.29" + attribute \src "libresoc.v:147381.5-147381.29" switch \initial - attribute \src "libresoc.v:145555.9-145555.17" + attribute \src "libresoc.v:147381.9-147381.17" case 1'1 case end @@ -305980,14 +308501,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:145567.3-145579.6" - process $proc$libresoc.v:145567$7310 + attribute \src "libresoc.v:147393.3-147405.6" + process $proc$libresoc.v:147393$7355 assign { } { } assign { } { } - assign $0\fast1$10[63:0]$7311 $1\fast1$10[63:0]$7312 - attribute \src "libresoc.v:145568.5-145568.29" + assign $0\fast1$10[63:0]$7356 $1\fast1$10[63:0]$7357 + attribute \src "libresoc.v:147394.5-147394.29" switch \initial - attribute \src "libresoc.v:145568.9-145568.17" + attribute \src "libresoc.v:147394.9-147394.17" case 1'1 case end @@ -305995,23 +308516,23 @@ module \main$22 switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $1\fast1$10[63:0]$7312 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$10[63:0]$7357 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\fast1$10[63:0]$7312 \ctr_n + assign $1\fast1$10[63:0]$7357 \ctr_n end sync always - update \fast1$10 $0\fast1$10[63:0]$7311 + update \fast1$10 $0\fast1$10[63:0]$7356 end - attribute \src "libresoc.v:145580.3-145600.6" - process $proc$libresoc.v:145580$7313 + attribute \src "libresoc.v:147406.3-147426.6" + process $proc$libresoc.v:147406$7358 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:145581.5-145581.29" + attribute \src "libresoc.v:147407.5-147407.29" switch \initial - attribute \src "libresoc.v:145581.9-145581.17" + attribute \src "libresoc.v:147407.9-147407.17" case 1'1 case end @@ -306039,14 +308560,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:145601.3-145613.6" - process $proc$libresoc.v:145601$7314 + attribute \src "libresoc.v:147427.3-147439.6" + process $proc$libresoc.v:147427$7359 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:145602.5-145602.29" + attribute \src "libresoc.v:147428.5-147428.29" switch \initial - attribute \src "libresoc.v:145602.9-145602.17" + attribute \src "libresoc.v:147428.9-147428.17" case 1'1 case end @@ -306063,24 +308584,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:145391$7279_Y - connect \$14 $or$libresoc.v:145392$7280_Y - connect \$17 $add$libresoc.v:145393$7281_Y - connect \$19 $eq$libresoc.v:145394$7282_Y - connect \$21 $or$libresoc.v:145395$7283_Y - connect \$23 $eq$libresoc.v:145396$7284_Y - connect \$25 $eq$libresoc.v:145397$7285_Y - connect \$27 $eq$libresoc.v:145398$7286_Y - connect \$29 $not$libresoc.v:145399$7287_Y - connect \$31 $and$libresoc.v:145400$7288_Y - connect \$33 $and$libresoc.v:145401$7289_Y - connect \$36 $sub$libresoc.v:145402$7290_Y - connect \$38 $pos$libresoc.v:145403$7292_Y - connect \$40 $reduce_or$libresoc.v:145404$7293_Y - connect \$42 $xor$libresoc.v:145405$7294_Y - connect \$44 $not$libresoc.v:145406$7295_Y - connect \$46 $and$libresoc.v:145407$7296_Y - connect \$49 $add$libresoc.v:145408$7297_Y + connect \$12 $eq$libresoc.v:147217$7324_Y + connect \$14 $or$libresoc.v:147218$7325_Y + connect \$17 $add$libresoc.v:147219$7326_Y + connect \$19 $eq$libresoc.v:147220$7327_Y + connect \$21 $or$libresoc.v:147221$7328_Y + connect \$23 $eq$libresoc.v:147222$7329_Y + connect \$25 $eq$libresoc.v:147223$7330_Y + connect \$27 $eq$libresoc.v:147224$7331_Y + connect \$29 $not$libresoc.v:147225$7332_Y + connect \$31 $and$libresoc.v:147226$7333_Y + connect \$33 $and$libresoc.v:147227$7334_Y + connect \$36 $sub$libresoc.v:147228$7335_Y + connect \$38 $pos$libresoc.v:147229$7337_Y + connect \$40 $reduce_or$libresoc.v:147230$7338_Y + connect \$42 $xor$libresoc.v:147231$7339_Y + connect \$44 $not$libresoc.v:147232$7340_Y + connect \$46 $and$libresoc.v:147233$7341_Y + connect \$49 $add$libresoc.v:147234$7342_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -306091,279 +308612,279 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:145627.1-146573.10" +attribute \src "libresoc.v:147453.1-148403.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 - attribute \src "libresoc.v:146538.3-146549.6" + attribute \src "libresoc.v:148368.3-148379.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:146036.3-146047.6" + attribute \src "libresoc.v:147866.3-147877.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:146550.3-146561.6" + attribute \src "libresoc.v:148380.3-148391.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:146319.3-146330.6" + attribute \src "libresoc.v:148149.3-148160.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:146112.3-146143.6" - wire width 64 $0\fast1$11[63:0]$7361 - attribute \src "libresoc.v:146144.3-146175.6" + attribute \src "libresoc.v:147942.3-147973.6" + wire width 64 $0\fast1$11[63:0]$7406 + attribute \src "libresoc.v:147974.3-148005.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:146176.3-146258.6" - wire width 64 $0\fast2$12[63:0]$7366 - attribute \src "libresoc.v:146259.3-146290.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire width 64 $0\fast2$12[63:0]$7411 + attribute \src "libresoc.v:148089.3-148120.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:145628.7-145628.20" + attribute \src "libresoc.v:147454.7-147454.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:146048.3-146079.6" + attribute \src "libresoc.v:147878.3-147909.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:146080.3-146111.6" + attribute \src "libresoc.v:147910.3-147941.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:146500.3-146518.6" + attribute \src "libresoc.v:148330.3-148348.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:146519.3-146537.6" + attribute \src "libresoc.v:148349.3-148367.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:146291.3-146318.6" - wire $0\trapexc_$signal$60[0:0]$7380 - attribute \src "libresoc.v:146291.3-146318.6" - wire $0\trapexc_$signal$61[0:0]$7381 - attribute \src "libresoc.v:146291.3-146318.6" - wire $0\trapexc_$signal$62[0:0]$7382 - attribute \src "libresoc.v:146291.3-146318.6" - wire $0\trapexc_$signal$67[0:0]$7383 - attribute \src "libresoc.v:146291.3-146318.6" - wire $0\trapexc_$signal$68[0:0]$7384 - attribute \src "libresoc.v:146291.3-146318.6" - wire $0\trapexc_$signal$69[0:0]$7385 - attribute \src "libresoc.v:146291.3-146318.6" - wire $0\trapexc_$signal$70[0:0]$7386 - attribute \src "libresoc.v:146291.3-146318.6" - wire $0\trapexc_$signal[0:0]$7379 - attribute \src "libresoc.v:146176.3-146258.6" - wire $10\fast2$12[19:19]$7376 - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$60[0:0]$7425 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$61[0:0]$7426 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$62[0:0]$7427 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$67[0:0]$7428 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$68[0:0]$7429 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$69[0:0]$7430 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal$70[0:0]$7431 + attribute \src "libresoc.v:148121.3-148148.6" + wire $0\trapexc_$signal[0:0]$7424 + attribute \src "libresoc.v:148006.3-148088.6" + wire $10\fast2$12[19:19]$7421 + attribute \src "libresoc.v:148161.3-148329.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $11\msr[15:15] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $12\msr[12:12] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $13\msr[60:60] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $14\msr[12:12] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $15\msr[12:12] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $17\msr[15:15] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:146538.3-146549.6" + attribute \src "libresoc.v:148368.3-148379.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:146036.3-146047.6" + attribute \src "libresoc.v:147866.3-147877.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:146550.3-146561.6" + attribute \src "libresoc.v:148380.3-148391.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:146319.3-146330.6" + attribute \src "libresoc.v:148149.3-148160.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:146112.3-146143.6" - wire width 64 $1\fast1$11[63:0]$7362 - attribute \src "libresoc.v:146144.3-146175.6" + attribute \src "libresoc.v:147942.3-147973.6" + wire width 64 $1\fast1$11[63:0]$7407 + attribute \src "libresoc.v:147974.3-148005.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:146176.3-146258.6" - wire width 64 $1\fast2$12[63:0]$7367 - attribute \src "libresoc.v:146259.3-146290.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire width 64 $1\fast2$12[63:0]$7412 + attribute \src "libresoc.v:148089.3-148120.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:146048.3-146079.6" + attribute \src "libresoc.v:147878.3-147909.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:146080.3-146111.6" + attribute \src "libresoc.v:147910.3-147941.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:146500.3-146518.6" + attribute \src "libresoc.v:148330.3-148348.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:146519.3-146537.6" + attribute \src "libresoc.v:148349.3-148367.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:146291.3-146318.6" - wire $1\trapexc_$signal$60[0:0]$7388 - attribute \src "libresoc.v:146291.3-146318.6" - wire $1\trapexc_$signal$61[0:0]$7389 - attribute \src "libresoc.v:146291.3-146318.6" - wire $1\trapexc_$signal$62[0:0]$7390 - attribute \src "libresoc.v:146291.3-146318.6" - wire $1\trapexc_$signal$67[0:0]$7391 - attribute \src "libresoc.v:146291.3-146318.6" - wire $1\trapexc_$signal$68[0:0]$7392 - attribute \src "libresoc.v:146291.3-146318.6" - wire $1\trapexc_$signal$69[0:0]$7393 - attribute \src "libresoc.v:146291.3-146318.6" - wire $1\trapexc_$signal$70[0:0]$7394 - attribute \src "libresoc.v:146291.3-146318.6" - wire $1\trapexc_$signal[0:0]$7387 - attribute \src "libresoc.v:146112.3-146143.6" - wire width 64 $2\fast1$11[63:0]$7363 - attribute \src "libresoc.v:146144.3-146175.6" + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$60[0:0]$7433 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$61[0:0]$7434 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$62[0:0]$7435 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$67[0:0]$7436 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$68[0:0]$7437 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$69[0:0]$7438 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal$70[0:0]$7439 + attribute \src "libresoc.v:148121.3-148148.6" + wire $1\trapexc_$signal[0:0]$7432 + attribute \src "libresoc.v:147942.3-147973.6" + wire width 64 $2\fast1$11[63:0]$7408 + attribute \src "libresoc.v:147974.3-148005.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:146176.3-146258.6" - wire width 64 $2\fast2$12[63:0]$7368 - attribute \src "libresoc.v:146259.3-146290.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire width 64 $2\fast2$12[63:0]$7413 + attribute \src "libresoc.v:148089.3-148120.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148161.3-148329.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:146048.3-146079.6" + attribute \src "libresoc.v:147878.3-147909.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:146080.3-146111.6" + attribute \src "libresoc.v:147910.3-147941.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:146291.3-146318.6" - wire $2\trapexc_$signal$60[0:0]$7396 - attribute \src "libresoc.v:146291.3-146318.6" - wire $2\trapexc_$signal$61[0:0]$7397 - attribute \src "libresoc.v:146291.3-146318.6" - wire $2\trapexc_$signal$62[0:0]$7398 - attribute \src "libresoc.v:146291.3-146318.6" - wire $2\trapexc_$signal$67[0:0]$7399 - attribute \src "libresoc.v:146291.3-146318.6" - wire $2\trapexc_$signal$68[0:0]$7400 - attribute \src "libresoc.v:146291.3-146318.6" - wire $2\trapexc_$signal$69[0:0]$7401 - attribute \src "libresoc.v:146291.3-146318.6" - wire $2\trapexc_$signal$70[0:0]$7402 - attribute \src "libresoc.v:146291.3-146318.6" - wire $2\trapexc_$signal[0:0]$7395 - attribute \src "libresoc.v:146176.3-146258.6" - wire $3\fast2$12[17:17]$7369 - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$60[0:0]$7441 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$61[0:0]$7442 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$62[0:0]$7443 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$67[0:0]$7444 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$68[0:0]$7445 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$69[0:0]$7446 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal$70[0:0]$7447 + attribute \src "libresoc.v:148121.3-148148.6" + wire $2\trapexc_$signal[0:0]$7440 + attribute \src "libresoc.v:148006.3-148088.6" + wire $3\fast2$12[17:17]$7414 + attribute \src "libresoc.v:148161.3-148329.6" wire width 11 $3\msr[11:1] - attribute \src "libresoc.v:146291.3-146318.6" - wire $3\trapexc_$signal$60[0:0]$7404 - attribute \src "libresoc.v:146291.3-146318.6" - wire $3\trapexc_$signal$61[0:0]$7405 - attribute \src "libresoc.v:146291.3-146318.6" - wire $3\trapexc_$signal$62[0:0]$7406 - attribute \src "libresoc.v:146291.3-146318.6" - wire $3\trapexc_$signal$67[0:0]$7407 - attribute \src "libresoc.v:146291.3-146318.6" - wire $3\trapexc_$signal$68[0:0]$7408 - attribute \src "libresoc.v:146291.3-146318.6" - wire $3\trapexc_$signal$69[0:0]$7409 - attribute \src "libresoc.v:146291.3-146318.6" - wire $3\trapexc_$signal$70[0:0]$7410 - attribute \src "libresoc.v:146291.3-146318.6" - wire $3\trapexc_$signal[0:0]$7403 - attribute \src "libresoc.v:146176.3-146258.6" - wire $4\fast2$12[18:18]$7370 - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$60[0:0]$7449 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$61[0:0]$7450 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$62[0:0]$7451 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$67[0:0]$7452 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$68[0:0]$7453 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$69[0:0]$7454 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal$70[0:0]$7455 + attribute \src "libresoc.v:148121.3-148148.6" + wire $3\trapexc_$signal[0:0]$7448 + attribute \src "libresoc.v:148006.3-148088.6" + wire $4\fast2$12[18:18]$7415 + attribute \src "libresoc.v:148161.3-148329.6" wire width 47 $4\msr[59:13] - attribute \src "libresoc.v:146176.3-146258.6" - wire $5\fast2$12[20:20]$7371 - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire $5\fast2$12[20:20]$7416 + attribute \src "libresoc.v:148161.3-148329.6" wire width 3 $5\msr[63:61] - attribute \src "libresoc.v:146176.3-146258.6" - wire $6\fast2$12[16:16]$7372 - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire $6\fast2$12[16:16]$7417 + attribute \src "libresoc.v:148161.3-148329.6" wire width 11 $6\msr[11:1] - attribute \src "libresoc.v:146176.3-146258.6" - wire width 2 $7\fast2$12[19:18]$7373 - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire width 2 $7\fast2$12[19:18]$7418 + attribute \src "libresoc.v:148161.3-148329.6" wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:146176.3-146258.6" - wire $8\fast2$12[28:28]$7374 - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire $8\fast2$12[28:28]$7419 + attribute \src "libresoc.v:148161.3-148329.6" wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:146176.3-146258.6" - wire $9\fast2$12[30:30]$7375 - attribute \src "libresoc.v:146331.3-146499.6" + attribute \src "libresoc.v:148006.3-148088.6" + wire $9\fast2$12[30:30]$7420 + attribute \src "libresoc.v:148161.3-148329.6" wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:146012.18-146012.113" - wire width 65 $add$libresoc.v:146012$7332_Y - attribute \src "libresoc.v:146006.18-146006.108" - wire width 5 $and$libresoc.v:146006$7325_Y - attribute \src "libresoc.v:146014.18-146014.118" - wire width 8 $and$libresoc.v:146014$7334_Y - attribute \src "libresoc.v:146016.18-146016.118" - wire width 8 $and$libresoc.v:146016$7336_Y - attribute \src "libresoc.v:146018.18-146018.118" - wire width 8 $and$libresoc.v:146018$7338_Y - attribute \src "libresoc.v:146020.18-146020.119" - wire width 8 $and$libresoc.v:146020$7340_Y - attribute \src "libresoc.v:146022.18-146022.119" - wire width 8 $and$libresoc.v:146022$7342_Y - attribute \src "libresoc.v:146024.18-146024.119" - wire width 8 $and$libresoc.v:146024$7344_Y - attribute \src "libresoc.v:146030.18-146030.106" - wire $and$libresoc.v:146030$7351_Y - attribute \src "libresoc.v:146035.18-146035.106" - wire $and$libresoc.v:146035$7356_Y - attribute \src "libresoc.v:146005.18-146005.100" - wire $eq$libresoc.v:146005$7324_Y - attribute \src "libresoc.v:146013.18-146013.119" - wire $eq$libresoc.v:146013$7333_Y - attribute \src "libresoc.v:146027.18-146027.121" - wire $eq$libresoc.v:146027$7348_Y - attribute \src "libresoc.v:146028.18-146028.121" - wire $eq$libresoc.v:146028$7349_Y - attribute \src "libresoc.v:146029.18-146029.111" - wire $eq$libresoc.v:146029$7350_Y - attribute \src "libresoc.v:146033.18-146033.121" - wire $eq$libresoc.v:146033$7354_Y - attribute \src "libresoc.v:146034.18-146034.114" - wire $eq$libresoc.v:146034$7355_Y - attribute \src "libresoc.v:145999.18-145999.95" - wire width 64 $extend$libresoc.v:145999$7316_Y - attribute \src "libresoc.v:146000.18-146000.95" - wire width 64 $extend$libresoc.v:146000$7318_Y - attribute \src "libresoc.v:146011.18-146011.100" - wire width 64 $extend$libresoc.v:146011$7330_Y - attribute \src "libresoc.v:146026.18-146026.109" - wire width 65 $extend$libresoc.v:146026$7346_Y - attribute \src "libresoc.v:146002.18-146002.121" - wire $gt$libresoc.v:146002$7321_Y - attribute \src "libresoc.v:146004.18-146004.99" - wire $gt$libresoc.v:146004$7323_Y - attribute \src "libresoc.v:146001.18-146001.121" - wire $lt$libresoc.v:146001$7320_Y - attribute \src "libresoc.v:146003.18-146003.99" - wire $lt$libresoc.v:146003$7322_Y - attribute \src "libresoc.v:146031.18-146031.112" - wire $not$libresoc.v:146031$7352_Y - attribute \src "libresoc.v:146032.18-146032.112" - wire $not$libresoc.v:146032$7353_Y - attribute \src "libresoc.v:146009.18-146009.106" - wire $or$libresoc.v:146009$7328_Y - attribute \src "libresoc.v:145999.18-145999.95" - wire width 64 $pos$libresoc.v:145999$7317_Y - attribute \src "libresoc.v:146000.18-146000.95" - wire width 64 $pos$libresoc.v:146000$7319_Y - attribute \src "libresoc.v:146011.18-146011.100" - wire width 64 $pos$libresoc.v:146011$7331_Y - attribute \src "libresoc.v:146026.18-146026.109" - wire width 65 $pos$libresoc.v:146026$7347_Y - attribute \src "libresoc.v:146007.18-146007.100" - wire $reduce_or$libresoc.v:146007$7326_Y - attribute \src "libresoc.v:146008.18-146008.113" - wire $reduce_or$libresoc.v:146008$7327_Y - attribute \src "libresoc.v:146015.18-146015.91" - wire $reduce_or$libresoc.v:146015$7335_Y - attribute \src "libresoc.v:146017.18-146017.91" - wire $reduce_or$libresoc.v:146017$7337_Y - attribute \src "libresoc.v:146019.18-146019.91" - wire $reduce_or$libresoc.v:146019$7339_Y - attribute \src "libresoc.v:146021.18-146021.91" - wire $reduce_or$libresoc.v:146021$7341_Y - attribute \src "libresoc.v:146023.18-146023.91" - wire $reduce_or$libresoc.v:146023$7343_Y - attribute \src "libresoc.v:146025.18-146025.91" - wire $reduce_or$libresoc.v:146025$7345_Y - attribute \src "libresoc.v:146010.18-146010.120" - wire width 20 $sshl$libresoc.v:146010$7329_Y + attribute \src "libresoc.v:147842.18-147842.113" + wire width 65 $add$libresoc.v:147842$7377_Y + attribute \src "libresoc.v:147836.18-147836.108" + wire width 5 $and$libresoc.v:147836$7370_Y + attribute \src "libresoc.v:147844.18-147844.118" + wire width 8 $and$libresoc.v:147844$7379_Y + attribute \src "libresoc.v:147846.18-147846.118" + wire width 8 $and$libresoc.v:147846$7381_Y + attribute \src "libresoc.v:147848.18-147848.118" + wire width 8 $and$libresoc.v:147848$7383_Y + attribute \src "libresoc.v:147850.18-147850.119" + wire width 8 $and$libresoc.v:147850$7385_Y + attribute \src "libresoc.v:147852.18-147852.119" + wire width 8 $and$libresoc.v:147852$7387_Y + attribute \src "libresoc.v:147854.18-147854.119" + wire width 8 $and$libresoc.v:147854$7389_Y + attribute \src "libresoc.v:147860.18-147860.106" + wire $and$libresoc.v:147860$7396_Y + attribute \src "libresoc.v:147865.18-147865.106" + wire $and$libresoc.v:147865$7401_Y + attribute \src "libresoc.v:147835.18-147835.100" + wire $eq$libresoc.v:147835$7369_Y + attribute \src "libresoc.v:147843.18-147843.119" + wire $eq$libresoc.v:147843$7378_Y + attribute \src "libresoc.v:147857.18-147857.121" + wire $eq$libresoc.v:147857$7393_Y + attribute \src "libresoc.v:147858.18-147858.121" + wire $eq$libresoc.v:147858$7394_Y + attribute \src "libresoc.v:147859.18-147859.111" + wire $eq$libresoc.v:147859$7395_Y + attribute \src "libresoc.v:147863.18-147863.121" + wire $eq$libresoc.v:147863$7399_Y + attribute \src "libresoc.v:147864.18-147864.114" + wire $eq$libresoc.v:147864$7400_Y + attribute \src "libresoc.v:147829.18-147829.95" + wire width 64 $extend$libresoc.v:147829$7361_Y + attribute \src "libresoc.v:147830.18-147830.95" + wire width 64 $extend$libresoc.v:147830$7363_Y + attribute \src "libresoc.v:147841.18-147841.100" + wire width 64 $extend$libresoc.v:147841$7375_Y + attribute \src "libresoc.v:147856.18-147856.109" + wire width 65 $extend$libresoc.v:147856$7391_Y + attribute \src "libresoc.v:147832.18-147832.121" + wire $gt$libresoc.v:147832$7366_Y + attribute \src "libresoc.v:147834.18-147834.99" + wire $gt$libresoc.v:147834$7368_Y + attribute \src "libresoc.v:147831.18-147831.121" + wire $lt$libresoc.v:147831$7365_Y + attribute \src "libresoc.v:147833.18-147833.99" + wire $lt$libresoc.v:147833$7367_Y + attribute \src "libresoc.v:147861.18-147861.112" + wire $not$libresoc.v:147861$7397_Y + attribute \src "libresoc.v:147862.18-147862.112" + wire $not$libresoc.v:147862$7398_Y + attribute \src "libresoc.v:147839.18-147839.106" + wire $or$libresoc.v:147839$7373_Y + attribute \src "libresoc.v:147829.18-147829.95" + wire width 64 $pos$libresoc.v:147829$7362_Y + attribute \src "libresoc.v:147830.18-147830.95" + wire width 64 $pos$libresoc.v:147830$7364_Y + attribute \src "libresoc.v:147841.18-147841.100" + wire width 64 $pos$libresoc.v:147841$7376_Y + attribute \src "libresoc.v:147856.18-147856.109" + wire width 65 $pos$libresoc.v:147856$7392_Y + attribute \src "libresoc.v:147837.18-147837.100" + wire $reduce_or$libresoc.v:147837$7371_Y + attribute \src "libresoc.v:147838.18-147838.113" + wire $reduce_or$libresoc.v:147838$7372_Y + attribute \src "libresoc.v:147845.18-147845.91" + wire $reduce_or$libresoc.v:147845$7380_Y + attribute \src "libresoc.v:147847.18-147847.91" + wire $reduce_or$libresoc.v:147847$7382_Y + attribute \src "libresoc.v:147849.18-147849.91" + wire $reduce_or$libresoc.v:147849$7384_Y + attribute \src "libresoc.v:147851.18-147851.91" + wire $reduce_or$libresoc.v:147851$7386_Y + attribute \src "libresoc.v:147853.18-147853.91" + wire $reduce_or$libresoc.v:147853$7388_Y + attribute \src "libresoc.v:147855.18-147855.91" + wire $reduce_or$libresoc.v:147855$7390_Y + attribute \src "libresoc.v:147840.18-147840.120" + wire width 20 $sshl$libresoc.v:147840$7374_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" @@ -306466,7 +308987,7 @@ module \main$38 wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:145628.7-145628.15" + attribute \src "libresoc.v:147454.7-147454.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s @@ -306503,37 +309024,39 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \trap_op__cia$6 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 16 \trap_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 16 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -306612,6 +309135,7 @@ module \main$38 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -306688,6 +309212,7 @@ module \main$38 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 15 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -306727,7 +309252,7 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:146012$7332 + cell $add $add$libresoc.v:147842$7377 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -306735,10 +309260,10 @@ module \main$38 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:146012$7332_Y + connect \Y $add$libresoc.v:147842$7377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:146006$7325 + cell $and $and$libresoc.v:147836$7370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -306746,10 +309271,10 @@ module \main$38 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:146006$7325_Y + connect \Y $and$libresoc.v:147836$7370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:146014$7334 + cell $and $and$libresoc.v:147844$7379 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -306757,10 +309282,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:146014$7334_Y + connect \Y $and$libresoc.v:147844$7379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:146016$7336 + cell $and $and$libresoc.v:147846$7381 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -306768,10 +309293,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:146016$7336_Y + connect \Y $and$libresoc.v:147846$7381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:146018$7338 + cell $and $and$libresoc.v:147848$7383 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -306779,10 +309304,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:146018$7338_Y + connect \Y $and$libresoc.v:147848$7383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:146020$7340 + cell $and $and$libresoc.v:147850$7385 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -306790,10 +309315,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:146020$7340_Y + connect \Y $and$libresoc.v:147850$7385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:146022$7342 + cell $and $and$libresoc.v:147852$7387 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -306801,10 +309326,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 - connect \Y $and$libresoc.v:146022$7342_Y + connect \Y $and$libresoc.v:147852$7387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:146024$7344 + cell $and $and$libresoc.v:147854$7389 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -306812,10 +309337,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:146024$7344_Y + connect \Y $and$libresoc.v:147854$7389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:146030$7351 + cell $and $and$libresoc.v:147860$7396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306823,10 +309348,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:146030$7351_Y + connect \Y $and$libresoc.v:147860$7396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:146035$7356 + cell $and $and$libresoc.v:147865$7401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306834,10 +309359,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:146035$7356_Y + connect \Y $and$libresoc.v:147865$7401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:146005$7324 + cell $eq $eq$libresoc.v:147835$7369 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -306845,10 +309370,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:146005$7324_Y + connect \Y $eq$libresoc.v:147835$7369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:146013$7333 + cell $eq $eq$libresoc.v:147843$7378 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -306856,10 +309381,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:146013$7333_Y + connect \Y $eq$libresoc.v:147843$7378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:146027$7348 + cell $eq $eq$libresoc.v:147857$7393 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -306867,10 +309392,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:146027$7348_Y + connect \Y $eq$libresoc.v:147857$7393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:146028$7349 + cell $eq $eq$libresoc.v:147858$7394 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -306878,10 +309403,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:146028$7349_Y + connect \Y $eq$libresoc.v:147858$7394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:146029$7350 + cell $eq $eq$libresoc.v:147859$7395 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -306889,10 +309414,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:146029$7350_Y + connect \Y $eq$libresoc.v:147859$7395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:146033$7354 + cell $eq $eq$libresoc.v:147863$7399 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -306900,10 +309425,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:146033$7354_Y + connect \Y $eq$libresoc.v:147863$7399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:146034$7355 + cell $eq $eq$libresoc.v:147864$7400 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -306911,42 +309436,42 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:146034$7355_Y + connect \Y $eq$libresoc.v:147864$7400_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:145999$7316 + cell $pos $extend$libresoc.v:147829$7361 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:145999$7316_Y + connect \Y $extend$libresoc.v:147829$7361_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:146000$7318 + cell $pos $extend$libresoc.v:147830$7363 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:146000$7318_Y + connect \Y $extend$libresoc.v:147830$7363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:146011$7330 + cell $pos $extend$libresoc.v:147841$7375 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 - connect \Y $extend$libresoc.v:146011$7330_Y + connect \Y $extend$libresoc.v:147841$7375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:146026$7346 + cell $pos $extend$libresoc.v:147856$7391 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:146026$7346_Y + connect \Y $extend$libresoc.v:147856$7391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:146002$7321 + cell $gt $gt$libresoc.v:147832$7366 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -306954,10 +309479,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:146002$7321_Y + connect \Y $gt$libresoc.v:147832$7366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:146004$7323 + cell $gt $gt$libresoc.v:147834$7368 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -306965,10 +309490,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:146004$7323_Y + connect \Y $gt$libresoc.v:147834$7368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:146001$7320 + cell $lt $lt$libresoc.v:147831$7365 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -306976,10 +309501,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:146001$7320_Y + connect \Y $lt$libresoc.v:147831$7365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:146003$7322 + cell $lt $lt$libresoc.v:147833$7367 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -306987,26 +309512,26 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:146003$7322_Y + connect \Y $lt$libresoc.v:147833$7367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:146031$7352 + cell $not $not$libresoc.v:147861$7397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:146031$7352_Y + connect \Y $not$libresoc.v:147861$7397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:146032$7353 + cell $not $not$libresoc.v:147862$7398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:146032$7353_Y + connect \Y $not$libresoc.v:147862$7398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:146009$7328 + cell $or $or$libresoc.v:147839$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307014,106 +309539,106 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 - connect \Y $or$libresoc.v:146009$7328_Y + connect \Y $or$libresoc.v:147839$7373_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:145999$7317 + cell $pos $pos$libresoc.v:147829$7362 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:145999$7316_Y - connect \Y $pos$libresoc.v:145999$7317_Y + connect \A $extend$libresoc.v:147829$7361_Y + connect \Y $pos$libresoc.v:147829$7362_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:146000$7319 + cell $pos $pos$libresoc.v:147830$7364 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:146000$7318_Y - connect \Y $pos$libresoc.v:146000$7319_Y + connect \A $extend$libresoc.v:147830$7363_Y + connect \Y $pos$libresoc.v:147830$7364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:146011$7331 + cell $pos $pos$libresoc.v:147841$7376 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:146011$7330_Y - connect \Y $pos$libresoc.v:146011$7331_Y + connect \A $extend$libresoc.v:147841$7375_Y + connect \Y $pos$libresoc.v:147841$7376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:146026$7347 + cell $pos $pos$libresoc.v:147856$7392 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:146026$7346_Y - connect \Y $pos$libresoc.v:146026$7347_Y + connect \A $extend$libresoc.v:147856$7391_Y + connect \Y $pos$libresoc.v:147856$7392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:146007$7326 + cell $reduce_or $reduce_or$libresoc.v:147837$7371 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $reduce_or$libresoc.v:146007$7326_Y + connect \Y $reduce_or$libresoc.v:147837$7371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:146008$7327 + cell $reduce_or $reduce_or$libresoc.v:147838$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:146008$7327_Y + connect \Y $reduce_or$libresoc.v:147838$7372_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:146015$7335 + cell $reduce_or $reduce_or$libresoc.v:147845$7380 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 - connect \Y $reduce_or$libresoc.v:146015$7335_Y + connect \Y $reduce_or$libresoc.v:147845$7380_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:146017$7337 + cell $reduce_or $reduce_or$libresoc.v:147847$7382 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 - connect \Y $reduce_or$libresoc.v:146017$7337_Y + connect \Y $reduce_or$libresoc.v:147847$7382_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:146019$7339 + cell $reduce_or $reduce_or$libresoc.v:147849$7384 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 - connect \Y $reduce_or$libresoc.v:146019$7339_Y + connect \Y $reduce_or$libresoc.v:147849$7384_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:146021$7341 + cell $reduce_or $reduce_or$libresoc.v:147851$7386 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 - connect \Y $reduce_or$libresoc.v:146021$7341_Y + connect \Y $reduce_or$libresoc.v:147851$7386_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:146023$7343 + cell $reduce_or $reduce_or$libresoc.v:147853$7388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $reduce_or$libresoc.v:146023$7343_Y + connect \Y $reduce_or$libresoc.v:147853$7388_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:146025$7345 + cell $reduce_or $reduce_or$libresoc.v:147855$7390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $reduce_or$libresoc.v:146025$7345_Y + connect \Y $reduce_or$libresoc.v:147855$7390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:146010$7329 + cell $sshl $sshl$libresoc.v:147840$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -307121,23 +309646,23 @@ module \main$38 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:146010$7329_Y + connect \Y $sshl$libresoc.v:147840$7374_Y end - attribute \src "libresoc.v:145628.7-145628.20" - process $proc$libresoc.v:145628$7417 + attribute \src "libresoc.v:147454.7-147454.20" + process $proc$libresoc.v:147454$7462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146036.3-146047.6" - process $proc$libresoc.v:146036$7357 + attribute \src "libresoc.v:147866.3-147877.6" + process $proc$libresoc.v:147866$7402 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:146037.5-146037.29" + attribute \src "libresoc.v:147867.5-147867.29" switch \initial - attribute \src "libresoc.v:146037.9-146037.17" + attribute \src "libresoc.v:147867.9-147867.17" case 1'1 case end @@ -307155,14 +309680,14 @@ module \main$38 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:146048.3-146079.6" - process $proc$libresoc.v:146048$7358 + attribute \src "libresoc.v:147878.3-147909.6" + process $proc$libresoc.v:147878$7403 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:146049.5-146049.29" + attribute \src "libresoc.v:147879.5-147879.29" switch \initial - attribute \src "libresoc.v:146049.9-146049.17" + attribute \src "libresoc.v:147879.9-147879.17" case 1'1 case end @@ -307201,14 +309726,14 @@ module \main$38 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:146080.3-146111.6" - process $proc$libresoc.v:146080$7359 + attribute \src "libresoc.v:147910.3-147941.6" + process $proc$libresoc.v:147910$7404 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:146081.5-146081.29" + attribute \src "libresoc.v:147911.5-147911.29" switch \initial - attribute \src "libresoc.v:146081.9-146081.17" + attribute \src "libresoc.v:147911.9-147911.17" case 1'1 case end @@ -307247,14 +309772,14 @@ module \main$38 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:146112.3-146143.6" - process $proc$libresoc.v:146112$7360 + attribute \src "libresoc.v:147942.3-147973.6" + process $proc$libresoc.v:147942$7405 assign { } { } assign { } { } - assign $0\fast1$11[63:0]$7361 $1\fast1$11[63:0]$7362 - attribute \src "libresoc.v:146113.5-146113.29" + assign $0\fast1$11[63:0]$7406 $1\fast1$11[63:0]$7407 + attribute \src "libresoc.v:147943.5-147943.29" switch \initial - attribute \src "libresoc.v:146113.9-146113.17" + attribute \src "libresoc.v:147943.9-147943.17" case 1'1 case end @@ -307263,43 +309788,43 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast1$11[63:0]$7362 $2\fast1$11[63:0]$7363 + assign $1\fast1$11[63:0]$7407 $2\fast1$11[63:0]$7408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1$11[63:0]$7363 \trap_op__cia + assign $2\fast1$11[63:0]$7408 \trap_op__cia case - assign $2\fast1$11[63:0]$7363 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$11[63:0]$7408 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast1$11[63:0]$7362 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast1$11[63:0]$7362 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast1$11[63:0]$7362 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign $1\fast1$11[63:0]$7362 \$39 [63:0] + assign $1\fast1$11[63:0]$7407 \$39 [63:0] case - assign $1\fast1$11[63:0]$7362 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$11 $0\fast1$11[63:0]$7361 + update \fast1$11 $0\fast1$11[63:0]$7406 end - attribute \src "libresoc.v:146144.3-146175.6" - process $proc$libresoc.v:146144$7364 + attribute \src "libresoc.v:147974.3-148005.6" + process $proc$libresoc.v:147974$7409 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:146145.5-146145.29" + attribute \src "libresoc.v:147975.5-147975.29" switch \initial - attribute \src "libresoc.v:146145.9-146145.17" + attribute \src "libresoc.v:147975.9-147975.17" case 1'1 case end @@ -307337,14 +309862,14 @@ module \main$38 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:146176.3-146258.6" - process $proc$libresoc.v:146176$7365 + attribute \src "libresoc.v:148006.3-148088.6" + process $proc$libresoc.v:148006$7410 assign { } { } assign { } { } - assign $0\fast2$12[63:0]$7366 $1\fast2$12[63:0]$7367 - attribute \src "libresoc.v:146177.5-146177.29" + assign $0\fast2$12[63:0]$7411 $1\fast2$12[63:0]$7412 + attribute \src "libresoc.v:148007.5-148007.29" switch \initial - attribute \src "libresoc.v:146177.9-146177.17" + attribute \src "libresoc.v:148007.9-148007.17" case 1'1 case end @@ -307353,59 +309878,59 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast2$12[63:0]$7367 $2\fast2$12[63:0]$7368 + assign $1\fast2$12[63:0]$7412 $2\fast2$12[63:0]$7413 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { $2\fast2$12[63:0]$7368 [29] $2\fast2$12[63:0]$7368 [27] $2\fast2$12[63:0]$7368 [21] } 3'000 - assign $2\fast2$12[63:0]$7368 [15:0] \trap_op__msr [15:0] - assign $2\fast2$12[63:0]$7368 [26:22] \trap_op__msr [26:22] - assign $2\fast2$12[63:0]$7368 [63:31] \trap_op__msr [63:31] - assign $2\fast2$12[63:0]$7368 [17] $3\fast2$12[17:17]$7369 - assign { } { } - assign $2\fast2$12[63:0]$7368 [20] $5\fast2$12[20:20]$7371 - assign $2\fast2$12[63:0]$7368 [16] $6\fast2$12[16:16]$7372 - assign $2\fast2$12[63:0]$7368 [18] $7\fast2$12[19:18]$7373 [0] - assign $2\fast2$12[63:0]$7368 [28] $8\fast2$12[28:28]$7374 - assign $2\fast2$12[63:0]$7368 [30] $9\fast2$12[30:30]$7375 - assign $2\fast2$12[63:0]$7368 [19] $10\fast2$12[19:19]$7376 + assign { $2\fast2$12[63:0]$7413 [29] $2\fast2$12[63:0]$7413 [27] $2\fast2$12[63:0]$7413 [21] } 3'000 + assign $2\fast2$12[63:0]$7413 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7413 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7413 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7413 [17] $3\fast2$12[17:17]$7414 + assign { } { } + assign $2\fast2$12[63:0]$7413 [20] $5\fast2$12[20:20]$7416 + assign $2\fast2$12[63:0]$7413 [16] $6\fast2$12[16:16]$7417 + assign $2\fast2$12[63:0]$7413 [18] $7\fast2$12[19:18]$7418 [0] + assign $2\fast2$12[63:0]$7413 [28] $8\fast2$12[28:28]$7419 + assign $2\fast2$12[63:0]$7413 [30] $9\fast2$12[30:30]$7420 + assign $2\fast2$12[63:0]$7413 [19] $10\fast2$12[19:19]$7421 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fast2$12[17:17]$7369 1'1 + assign $3\fast2$12[17:17]$7414 1'1 case - assign $3\fast2$12[17:17]$7369 1'0 + assign $3\fast2$12[17:17]$7414 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fast2$12[18:18]$7370 1'1 + assign $4\fast2$12[18:18]$7415 1'1 case - assign $4\fast2$12[18:18]$7370 1'0 + assign $4\fast2$12[18:18]$7415 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fast2$12[20:20]$7371 1'1 + assign $5\fast2$12[20:20]$7416 1'1 case - assign $5\fast2$12[20:20]$7371 1'0 + assign $5\fast2$12[20:20]$7416 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fast2$12[16:16]$7372 1'1 + assign $6\fast2$12[16:16]$7417 1'1 case - assign $6\fast2$12[16:16]$7372 1'0 + assign $6\fast2$12[16:16]$7417 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$56 @@ -307414,57 +309939,57 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $9\fast2$12[30:30]$7375 \trapexc_$signal - assign $8\fast2$12[28:28]$7374 \trapexc_$signal$60 - assign $7\fast2$12[19:18]$7373 [1] \trapexc_$signal$61 - assign $7\fast2$12[19:18]$7373 [0] \trapexc_$signal$62 + assign $9\fast2$12[30:30]$7420 \trapexc_$signal + assign $8\fast2$12[28:28]$7419 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7418 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7418 [0] \trapexc_$signal$62 case - assign $7\fast2$12[19:18]$7373 { 1'0 $4\fast2$12[18:18]$7370 } - assign $8\fast2$12[28:28]$7374 1'0 - assign $9\fast2$12[30:30]$7375 1'0 + assign $7\fast2$12[19:18]$7418 { 1'0 $4\fast2$12[18:18]$7415 } + assign $8\fast2$12[28:28]$7419 1'0 + assign $9\fast2$12[30:30]$7420 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\fast2$12[19:19]$7376 1'1 + assign $10\fast2$12[19:19]$7421 1'1 case - assign $10\fast2$12[19:19]$7376 $7\fast2$12[19:18]$7373 [1] + assign $10\fast2$12[19:19]$7421 $7\fast2$12[19:18]$7418 [1] end case - assign $2\fast2$12[63:0]$7368 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast2$12[63:0]$7413 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast2$12[63:0]$7367 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast2$12[63:0]$7367 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast2$12[63:0]$7367 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign { $1\fast2$12[63:0]$7367 [30:27] $1\fast2$12[63:0]$7367 [21:16] } 10'0000000000 - assign $1\fast2$12[63:0]$7367 [15:0] \trap_op__msr [15:0] - assign $1\fast2$12[63:0]$7367 [26:22] \trap_op__msr [26:22] - assign $1\fast2$12[63:0]$7367 [63:31] \trap_op__msr [63:31] + assign { $1\fast2$12[63:0]$7412 [30:27] $1\fast2$12[63:0]$7412 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7412 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7412 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7412 [63:31] \trap_op__msr [63:31] case - assign $1\fast2$12[63:0]$7367 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$12 $0\fast2$12[63:0]$7366 + update \fast2$12 $0\fast2$12[63:0]$7411 end - attribute \src "libresoc.v:146259.3-146290.6" - process $proc$libresoc.v:146259$7377 + attribute \src "libresoc.v:148089.3-148120.6" + process $proc$libresoc.v:148089$7422 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:146260.5-146260.29" + attribute \src "libresoc.v:148090.5-148090.29" switch \initial - attribute \src "libresoc.v:146260.9-146260.17" + attribute \src "libresoc.v:148090.9-148090.17" case 1'1 case end @@ -307502,8 +310027,8 @@ module \main$38 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:146291.3-146318.6" - process $proc$libresoc.v:146291$7378 + attribute \src "libresoc.v:148121.3-148148.6" + process $proc$libresoc.v:148121$7423 assign { } { } assign { } { } assign { } { } @@ -307520,17 +310045,17 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $0\trapexc_$signal[0:0]$7379 $1\trapexc_$signal[0:0]$7387 - assign $0\trapexc_$signal$60[0:0]$7380 $1\trapexc_$signal$60[0:0]$7388 - assign $0\trapexc_$signal$61[0:0]$7381 $1\trapexc_$signal$61[0:0]$7389 - assign $0\trapexc_$signal$62[0:0]$7382 $1\trapexc_$signal$62[0:0]$7390 - assign $0\trapexc_$signal$67[0:0]$7383 $1\trapexc_$signal$67[0:0]$7391 - assign $0\trapexc_$signal$68[0:0]$7384 $1\trapexc_$signal$68[0:0]$7392 - assign $0\trapexc_$signal$69[0:0]$7385 $1\trapexc_$signal$69[0:0]$7393 - assign $0\trapexc_$signal$70[0:0]$7386 $1\trapexc_$signal$70[0:0]$7394 - attribute \src "libresoc.v:146292.5-146292.29" + assign $0\trapexc_$signal[0:0]$7424 $1\trapexc_$signal[0:0]$7432 + assign $0\trapexc_$signal$60[0:0]$7425 $1\trapexc_$signal$60[0:0]$7433 + assign $0\trapexc_$signal$61[0:0]$7426 $1\trapexc_$signal$61[0:0]$7434 + assign $0\trapexc_$signal$62[0:0]$7427 $1\trapexc_$signal$62[0:0]$7435 + assign $0\trapexc_$signal$67[0:0]$7428 $1\trapexc_$signal$67[0:0]$7436 + assign $0\trapexc_$signal$68[0:0]$7429 $1\trapexc_$signal$68[0:0]$7437 + assign $0\trapexc_$signal$69[0:0]$7430 $1\trapexc_$signal$69[0:0]$7438 + assign $0\trapexc_$signal$70[0:0]$7431 $1\trapexc_$signal$70[0:0]$7439 + attribute \src "libresoc.v:148122.5-148122.29" switch \initial - attribute \src "libresoc.v:146292.9-146292.17" + attribute \src "libresoc.v:148122.9-148122.17" case 1'1 case end @@ -307546,14 +310071,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $1\trapexc_$signal[0:0]$7387 $2\trapexc_$signal[0:0]$7395 - assign $1\trapexc_$signal$60[0:0]$7388 $2\trapexc_$signal$60[0:0]$7396 - assign $1\trapexc_$signal$61[0:0]$7389 $2\trapexc_$signal$61[0:0]$7397 - assign $1\trapexc_$signal$62[0:0]$7390 $2\trapexc_$signal$62[0:0]$7398 - assign $1\trapexc_$signal$67[0:0]$7391 $2\trapexc_$signal$67[0:0]$7399 - assign $1\trapexc_$signal$68[0:0]$7392 $2\trapexc_$signal$68[0:0]$7400 - assign $1\trapexc_$signal$69[0:0]$7393 $2\trapexc_$signal$69[0:0]$7401 - assign $1\trapexc_$signal$70[0:0]$7394 $2\trapexc_$signal$70[0:0]$7402 + assign $1\trapexc_$signal[0:0]$7432 $2\trapexc_$signal[0:0]$7440 + assign $1\trapexc_$signal$60[0:0]$7433 $2\trapexc_$signal$60[0:0]$7441 + assign $1\trapexc_$signal$61[0:0]$7434 $2\trapexc_$signal$61[0:0]$7442 + assign $1\trapexc_$signal$62[0:0]$7435 $2\trapexc_$signal$62[0:0]$7443 + assign $1\trapexc_$signal$67[0:0]$7436 $2\trapexc_$signal$67[0:0]$7444 + assign $1\trapexc_$signal$68[0:0]$7437 $2\trapexc_$signal$68[0:0]$7445 + assign $1\trapexc_$signal$69[0:0]$7438 $2\trapexc_$signal$69[0:0]$7446 + assign $1\trapexc_$signal$70[0:0]$7439 $2\trapexc_$signal$70[0:0]$7447 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" @@ -307566,14 +310091,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $2\trapexc_$signal[0:0]$7395 $3\trapexc_$signal[0:0]$7403 - assign $2\trapexc_$signal$60[0:0]$7396 $3\trapexc_$signal$60[0:0]$7404 - assign $2\trapexc_$signal$61[0:0]$7397 $3\trapexc_$signal$61[0:0]$7405 - assign $2\trapexc_$signal$62[0:0]$7398 $3\trapexc_$signal$62[0:0]$7406 - assign $2\trapexc_$signal$67[0:0]$7399 $3\trapexc_$signal$67[0:0]$7407 - assign $2\trapexc_$signal$68[0:0]$7400 $3\trapexc_$signal$68[0:0]$7408 - assign $2\trapexc_$signal$69[0:0]$7401 $3\trapexc_$signal$69[0:0]$7409 - assign $2\trapexc_$signal$70[0:0]$7402 $3\trapexc_$signal$70[0:0]$7410 + assign $2\trapexc_$signal[0:0]$7440 $3\trapexc_$signal[0:0]$7448 + assign $2\trapexc_$signal$60[0:0]$7441 $3\trapexc_$signal$60[0:0]$7449 + assign $2\trapexc_$signal$61[0:0]$7442 $3\trapexc_$signal$61[0:0]$7450 + assign $2\trapexc_$signal$62[0:0]$7443 $3\trapexc_$signal$62[0:0]$7451 + assign $2\trapexc_$signal$67[0:0]$7444 $3\trapexc_$signal$67[0:0]$7452 + assign $2\trapexc_$signal$68[0:0]$7445 $3\trapexc_$signal$68[0:0]$7453 + assign $2\trapexc_$signal$69[0:0]$7446 $3\trapexc_$signal$69[0:0]$7454 + assign $2\trapexc_$signal$70[0:0]$7447 $3\trapexc_$signal$70[0:0]$7455 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$71 attribute \src "libresoc.v:0.0-0.0" @@ -307586,54 +310111,54 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign { $3\trapexc_$signal$70[0:0]$7410 $3\trapexc_$signal$62[0:0]$7406 $3\trapexc_$signal$60[0:0]$7404 $3\trapexc_$signal$61[0:0]$7405 $3\trapexc_$signal[0:0]$7403 $3\trapexc_$signal$69[0:0]$7409 $3\trapexc_$signal$68[0:0]$7408 $3\trapexc_$signal$67[0:0]$7407 } \trap_op__ldst_exc + assign { $3\trapexc_$signal$70[0:0]$7455 $3\trapexc_$signal$62[0:0]$7451 $3\trapexc_$signal$60[0:0]$7449 $3\trapexc_$signal$61[0:0]$7450 $3\trapexc_$signal[0:0]$7448 $3\trapexc_$signal$69[0:0]$7454 $3\trapexc_$signal$68[0:0]$7453 $3\trapexc_$signal$67[0:0]$7452 } \trap_op__ldst_exc case - assign $3\trapexc_$signal[0:0]$7403 1'0 - assign $3\trapexc_$signal$60[0:0]$7404 1'0 - assign $3\trapexc_$signal$61[0:0]$7405 1'0 - assign $3\trapexc_$signal$62[0:0]$7406 1'0 - assign $3\trapexc_$signal$67[0:0]$7407 1'0 - assign $3\trapexc_$signal$68[0:0]$7408 1'0 - assign $3\trapexc_$signal$69[0:0]$7409 1'0 - assign $3\trapexc_$signal$70[0:0]$7410 1'0 + assign $3\trapexc_$signal[0:0]$7448 1'0 + assign $3\trapexc_$signal$60[0:0]$7449 1'0 + assign $3\trapexc_$signal$61[0:0]$7450 1'0 + assign $3\trapexc_$signal$62[0:0]$7451 1'0 + assign $3\trapexc_$signal$67[0:0]$7452 1'0 + assign $3\trapexc_$signal$68[0:0]$7453 1'0 + assign $3\trapexc_$signal$69[0:0]$7454 1'0 + assign $3\trapexc_$signal$70[0:0]$7455 1'0 end case - assign $2\trapexc_$signal[0:0]$7395 1'0 - assign $2\trapexc_$signal$60[0:0]$7396 1'0 - assign $2\trapexc_$signal$61[0:0]$7397 1'0 - assign $2\trapexc_$signal$62[0:0]$7398 1'0 - assign $2\trapexc_$signal$67[0:0]$7399 1'0 - assign $2\trapexc_$signal$68[0:0]$7400 1'0 - assign $2\trapexc_$signal$69[0:0]$7401 1'0 - assign $2\trapexc_$signal$70[0:0]$7402 1'0 - end - case - assign $1\trapexc_$signal[0:0]$7387 1'0 - assign $1\trapexc_$signal$60[0:0]$7388 1'0 - assign $1\trapexc_$signal$61[0:0]$7389 1'0 - assign $1\trapexc_$signal$62[0:0]$7390 1'0 - assign $1\trapexc_$signal$67[0:0]$7391 1'0 - assign $1\trapexc_$signal$68[0:0]$7392 1'0 - assign $1\trapexc_$signal$69[0:0]$7393 1'0 - assign $1\trapexc_$signal$70[0:0]$7394 1'0 - end - sync always - update \trapexc_$signal $0\trapexc_$signal[0:0]$7379 - update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7380 - update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7381 - update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7382 - update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7383 - update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7384 - update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7385 - update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7386 - end - attribute \src "libresoc.v:146319.3-146330.6" - process $proc$libresoc.v:146319$7411 + assign $2\trapexc_$signal[0:0]$7440 1'0 + assign $2\trapexc_$signal$60[0:0]$7441 1'0 + assign $2\trapexc_$signal$61[0:0]$7442 1'0 + assign $2\trapexc_$signal$62[0:0]$7443 1'0 + assign $2\trapexc_$signal$67[0:0]$7444 1'0 + assign $2\trapexc_$signal$68[0:0]$7445 1'0 + assign $2\trapexc_$signal$69[0:0]$7446 1'0 + assign $2\trapexc_$signal$70[0:0]$7447 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7432 1'0 + assign $1\trapexc_$signal$60[0:0]$7433 1'0 + assign $1\trapexc_$signal$61[0:0]$7434 1'0 + assign $1\trapexc_$signal$62[0:0]$7435 1'0 + assign $1\trapexc_$signal$67[0:0]$7436 1'0 + assign $1\trapexc_$signal$68[0:0]$7437 1'0 + assign $1\trapexc_$signal$69[0:0]$7438 1'0 + assign $1\trapexc_$signal$70[0:0]$7439 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7424 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7425 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7426 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7427 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7428 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7429 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7430 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7431 + end + attribute \src "libresoc.v:148149.3-148160.6" + process $proc$libresoc.v:148149$7456 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:146320.5-146320.29" + attribute \src "libresoc.v:148150.5-148150.29" switch \initial - attribute \src "libresoc.v:146320.9-146320.17" + attribute \src "libresoc.v:148150.9-148150.17" case 1'1 case end @@ -307651,17 +310176,17 @@ module \main$38 sync always update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:146331.3-146499.6" - process $proc$libresoc.v:146331$7412 + attribute \src "libresoc.v:148161.3-148329.6" + process $proc$libresoc.v:148161$7457 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:146332.5-146332.29" + attribute \src "libresoc.v:148162.5-148162.29" switch \initial - attribute \src "libresoc.v:146332.9-146332.17" + attribute \src "libresoc.v:148162.9-148162.17" case 1'1 case end @@ -307875,14 +310400,14 @@ module \main$38 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:146500.3-146518.6" - process $proc$libresoc.v:146500$7413 + attribute \src "libresoc.v:148330.3-148348.6" + process $proc$libresoc.v:148330$7458 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:146501.5-146501.29" + attribute \src "libresoc.v:148331.5-148331.29" switch \initial - attribute \src "libresoc.v:146501.9-146501.17" + attribute \src "libresoc.v:148331.9-148331.17" case 1'1 case end @@ -307904,14 +310429,14 @@ module \main$38 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:146519.3-146537.6" - process $proc$libresoc.v:146519$7414 + attribute \src "libresoc.v:148349.3-148367.6" + process $proc$libresoc.v:148349$7459 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:146520.5-146520.29" + attribute \src "libresoc.v:148350.5-148350.29" switch \initial - attribute \src "libresoc.v:146520.9-146520.17" + attribute \src "libresoc.v:148350.9-148350.17" case 1'1 case end @@ -307933,13 +310458,13 @@ module \main$38 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:146538.3-146549.6" - process $proc$libresoc.v:146538$7415 + attribute \src "libresoc.v:148368.3-148379.6" + process $proc$libresoc.v:148368$7460 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:146539.5-146539.29" + attribute \src "libresoc.v:148369.5-148369.29" switch \initial - attribute \src "libresoc.v:146539.9-146539.17" + attribute \src "libresoc.v:148369.9-148369.17" case 1'1 case end @@ -307957,13 +310482,13 @@ module \main$38 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:146550.3-146561.6" - process $proc$libresoc.v:146550$7416 + attribute \src "libresoc.v:148380.3-148391.6" + process $proc$libresoc.v:148380$7461 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:146551.5-146551.29" + attribute \src "libresoc.v:148381.5-148381.29" switch \initial - attribute \src "libresoc.v:146551.9-146551.17" + attribute \src "libresoc.v:148381.9-148381.17" case 1'1 case end @@ -307981,43 +310506,43 @@ module \main$38 sync always update \b $0\b[63:0] end - connect \$13 $pos$libresoc.v:145999$7317_Y - connect \$15 $pos$libresoc.v:146000$7319_Y - connect \$17 $lt$libresoc.v:146001$7320_Y - connect \$19 $gt$libresoc.v:146002$7321_Y - connect \$21 $lt$libresoc.v:146003$7322_Y - connect \$23 $gt$libresoc.v:146004$7323_Y - connect \$25 $eq$libresoc.v:146005$7324_Y - connect \$28 $and$libresoc.v:146006$7325_Y - connect \$27 $reduce_or$libresoc.v:146007$7326_Y - connect \$31 $reduce_or$libresoc.v:146008$7327_Y - connect \$33 $or$libresoc.v:146009$7328_Y - connect \$36 $sshl$libresoc.v:146010$7329_Y - connect \$35 $pos$libresoc.v:146011$7331_Y - connect \$40 $add$libresoc.v:146012$7332_Y - connect \$42 $eq$libresoc.v:146013$7333_Y - connect \$45 $and$libresoc.v:146014$7334_Y - connect \$44 $reduce_or$libresoc.v:146015$7335_Y - connect \$49 $and$libresoc.v:146016$7336_Y - connect \$48 $reduce_or$libresoc.v:146017$7337_Y - connect \$53 $and$libresoc.v:146018$7338_Y - connect \$52 $reduce_or$libresoc.v:146019$7339_Y - connect \$57 $and$libresoc.v:146020$7340_Y - connect \$56 $reduce_or$libresoc.v:146021$7341_Y - connect \$64 $and$libresoc.v:146022$7342_Y - connect \$63 $reduce_or$libresoc.v:146023$7343_Y - connect \$72 $and$libresoc.v:146024$7344_Y - connect \$71 $reduce_or$libresoc.v:146025$7345_Y - connect \$75 $pos$libresoc.v:146026$7347_Y - connect \$77 $eq$libresoc.v:146027$7348_Y - connect \$79 $eq$libresoc.v:146028$7349_Y - connect \$81 $eq$libresoc.v:146029$7350_Y - connect \$83 $and$libresoc.v:146030$7351_Y - connect \$85 $not$libresoc.v:146031$7352_Y - connect \$87 $not$libresoc.v:146032$7353_Y - connect \$89 $eq$libresoc.v:146033$7354_Y - connect \$91 $eq$libresoc.v:146034$7355_Y - connect \$93 $and$libresoc.v:146035$7356_Y + connect \$13 $pos$libresoc.v:147829$7362_Y + connect \$15 $pos$libresoc.v:147830$7364_Y + connect \$17 $lt$libresoc.v:147831$7365_Y + connect \$19 $gt$libresoc.v:147832$7366_Y + connect \$21 $lt$libresoc.v:147833$7367_Y + connect \$23 $gt$libresoc.v:147834$7368_Y + connect \$25 $eq$libresoc.v:147835$7369_Y + connect \$28 $and$libresoc.v:147836$7370_Y + connect \$27 $reduce_or$libresoc.v:147837$7371_Y + connect \$31 $reduce_or$libresoc.v:147838$7372_Y + connect \$33 $or$libresoc.v:147839$7373_Y + connect \$36 $sshl$libresoc.v:147840$7374_Y + connect \$35 $pos$libresoc.v:147841$7376_Y + connect \$40 $add$libresoc.v:147842$7377_Y + connect \$42 $eq$libresoc.v:147843$7378_Y + connect \$45 $and$libresoc.v:147844$7379_Y + connect \$44 $reduce_or$libresoc.v:147845$7380_Y + connect \$49 $and$libresoc.v:147846$7381_Y + connect \$48 $reduce_or$libresoc.v:147847$7382_Y + connect \$53 $and$libresoc.v:147848$7383_Y + connect \$52 $reduce_or$libresoc.v:147849$7384_Y + connect \$57 $and$libresoc.v:147850$7385_Y + connect \$56 $reduce_or$libresoc.v:147851$7386_Y + connect \$64 $and$libresoc.v:147852$7387_Y + connect \$63 $reduce_or$libresoc.v:147853$7388_Y + connect \$72 $and$libresoc.v:147854$7389_Y + connect \$71 $reduce_or$libresoc.v:147855$7390_Y + connect \$75 $pos$libresoc.v:147856$7392_Y + connect \$77 $eq$libresoc.v:147857$7393_Y + connect \$79 $eq$libresoc.v:147858$7394_Y + connect \$81 $eq$libresoc.v:147859$7395_Y + connect \$83 $and$libresoc.v:147860$7396_Y + connect \$85 $not$libresoc.v:147861$7397_Y + connect \$87 $not$libresoc.v:147862$7398_Y + connect \$89 $eq$libresoc.v:147863$7399_Y + connect \$91 $eq$libresoc.v:147864$7400_Y + connect \$93 $and$libresoc.v:147865$7401_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid @@ -308030,239 +310555,239 @@ module \main$38 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:146577.1-147322.10" +attribute \src "libresoc.v:148407.1-149156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 - attribute \src "libresoc.v:147289.3-147299.6" + attribute \src "libresoc.v:149123.3-149133.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:147234.3-147244.6" + attribute \src "libresoc.v:149068.3-149078.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:147212.3-147222.6" + attribute \src "libresoc.v:149046.3-149056.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:147201.3-147211.6" + attribute \src "libresoc.v:149035.3-149045.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:147190.3-147200.6" + attribute \src "libresoc.v:149024.3-149034.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:147300.3-147318.6" + attribute \src "libresoc.v:149134.3-149152.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:147278.3-147288.6" + attribute \src "libresoc.v:149112.3-149122.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:146578.7-146578.20" + attribute \src "libresoc.v:148408.7-148408.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147135.3-147189.6" + attribute \src "libresoc.v:148969.3-149023.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:147135.3-147189.6" + attribute \src "libresoc.v:148969.3-149023.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:147256.3-147266.6" + attribute \src "libresoc.v:149090.3-149100.6" wire $0\par0[0:0] - attribute \src "libresoc.v:147267.3-147277.6" + attribute \src "libresoc.v:149101.3-149111.6" wire $0\par1[0:0] - attribute \src "libresoc.v:147223.3-147233.6" + attribute \src "libresoc.v:149057.3-149067.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:147245.3-147255.6" + attribute \src "libresoc.v:149079.3-149089.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:147289.3-147299.6" + attribute \src "libresoc.v:149123.3-149133.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:147234.3-147244.6" + attribute \src "libresoc.v:149068.3-149078.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:147212.3-147222.6" + attribute \src "libresoc.v:149046.3-149056.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:147201.3-147211.6" + attribute \src "libresoc.v:149035.3-149045.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:147190.3-147200.6" + attribute \src "libresoc.v:149024.3-149034.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:147300.3-147318.6" + attribute \src "libresoc.v:149134.3-149152.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:147278.3-147288.6" + attribute \src "libresoc.v:149112.3-149122.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:147135.3-147189.6" + attribute \src "libresoc.v:148969.3-149023.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:147135.3-147189.6" + attribute \src "libresoc.v:148969.3-149023.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:147256.3-147266.6" + attribute \src "libresoc.v:149090.3-149100.6" wire $1\par0[0:0] - attribute \src "libresoc.v:147267.3-147277.6" + attribute \src "libresoc.v:149101.3-149111.6" wire $1\par1[0:0] - attribute \src "libresoc.v:147223.3-147233.6" + attribute \src "libresoc.v:149057.3-149067.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:147245.3-147255.6" + attribute \src "libresoc.v:149079.3-149089.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:147300.3-147318.6" + attribute \src "libresoc.v:149134.3-149152.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:147135.3-147189.6" + attribute \src "libresoc.v:148969.3-149023.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:147082.18-147082.103" - wire width 64 $and$libresoc.v:147082$7464_Y - attribute \src "libresoc.v:147041.18-147041.118" - wire $eq$libresoc.v:147041$7418_Y - attribute \src "libresoc.v:147042.19-147042.119" - wire $eq$libresoc.v:147042$7419_Y - attribute \src "libresoc.v:147043.19-147043.119" - wire $eq$libresoc.v:147043$7420_Y - attribute \src "libresoc.v:147044.19-147044.119" - wire $eq$libresoc.v:147044$7421_Y - attribute \src "libresoc.v:147045.19-147045.119" - wire $eq$libresoc.v:147045$7422_Y - attribute \src "libresoc.v:147046.19-147046.119" - wire $eq$libresoc.v:147046$7423_Y - attribute \src "libresoc.v:147047.19-147047.119" - wire $eq$libresoc.v:147047$7424_Y - attribute \src "libresoc.v:147048.19-147048.119" - wire $eq$libresoc.v:147048$7425_Y - attribute \src "libresoc.v:147049.19-147049.119" - wire $eq$libresoc.v:147049$7426_Y - attribute \src "libresoc.v:147050.19-147050.119" - wire $eq$libresoc.v:147050$7427_Y - attribute \src "libresoc.v:147051.19-147051.119" - wire $eq$libresoc.v:147051$7428_Y - attribute \src "libresoc.v:147052.19-147052.119" - wire $eq$libresoc.v:147052$7429_Y - attribute \src "libresoc.v:147053.19-147053.119" - wire $eq$libresoc.v:147053$7430_Y - attribute \src "libresoc.v:147054.19-147054.119" - wire $eq$libresoc.v:147054$7431_Y - attribute \src "libresoc.v:147055.19-147055.119" - wire $eq$libresoc.v:147055$7432_Y - attribute \src "libresoc.v:147056.19-147056.119" - wire $eq$libresoc.v:147056$7433_Y - attribute \src "libresoc.v:147057.19-147057.119" - wire $eq$libresoc.v:147057$7434_Y - attribute \src "libresoc.v:147058.19-147058.119" - wire $eq$libresoc.v:147058$7435_Y - attribute \src "libresoc.v:147059.19-147059.119" - wire $eq$libresoc.v:147059$7436_Y - attribute \src "libresoc.v:147060.19-147060.119" - wire $eq$libresoc.v:147060$7437_Y - attribute \src "libresoc.v:147061.19-147061.119" - wire $eq$libresoc.v:147061$7438_Y - attribute \src "libresoc.v:147062.19-147062.119" - wire $eq$libresoc.v:147062$7439_Y - attribute \src "libresoc.v:147063.19-147063.119" - wire $eq$libresoc.v:147063$7440_Y - attribute \src "libresoc.v:147064.19-147064.119" - wire $eq$libresoc.v:147064$7441_Y - attribute \src "libresoc.v:147065.19-147065.119" - wire $eq$libresoc.v:147065$7442_Y - attribute \src "libresoc.v:147066.19-147066.119" - wire $eq$libresoc.v:147066$7443_Y - attribute \src "libresoc.v:147067.19-147067.119" - wire $eq$libresoc.v:147067$7444_Y - attribute \src "libresoc.v:147068.19-147068.119" - wire $eq$libresoc.v:147068$7445_Y - attribute \src "libresoc.v:147069.19-147069.128" - wire $eq$libresoc.v:147069$7446_Y - attribute \src "libresoc.v:147085.18-147085.114" - wire $eq$libresoc.v:147085$7467_Y - attribute \src "libresoc.v:147086.18-147086.114" - wire $eq$libresoc.v:147086$7468_Y - attribute \src "libresoc.v:147087.18-147087.114" - wire $eq$libresoc.v:147087$7469_Y - attribute \src "libresoc.v:147088.18-147088.114" - wire $eq$libresoc.v:147088$7470_Y - attribute \src "libresoc.v:147089.18-147089.114" - wire $eq$libresoc.v:147089$7471_Y - attribute \src "libresoc.v:147090.18-147090.114" - wire $eq$libresoc.v:147090$7472_Y - attribute \src "libresoc.v:147091.18-147091.114" - wire $eq$libresoc.v:147091$7473_Y - attribute \src "libresoc.v:147092.18-147092.114" - wire $eq$libresoc.v:147092$7474_Y - attribute \src "libresoc.v:147093.18-147093.116" - wire $eq$libresoc.v:147093$7475_Y - attribute \src "libresoc.v:147094.18-147094.116" - wire $eq$libresoc.v:147094$7476_Y - attribute \src "libresoc.v:147095.18-147095.116" - wire $eq$libresoc.v:147095$7477_Y - attribute \src "libresoc.v:147096.18-147096.116" - wire $eq$libresoc.v:147096$7478_Y - attribute \src "libresoc.v:147097.18-147097.116" - wire $eq$libresoc.v:147097$7479_Y - attribute \src "libresoc.v:147098.18-147098.116" - wire $eq$libresoc.v:147098$7480_Y - attribute \src "libresoc.v:147099.18-147099.116" - wire $eq$libresoc.v:147099$7481_Y - attribute \src "libresoc.v:147100.18-147100.116" - wire $eq$libresoc.v:147100$7482_Y - attribute \src "libresoc.v:147101.18-147101.118" - wire $eq$libresoc.v:147101$7483_Y - attribute \src "libresoc.v:147102.18-147102.118" - wire $eq$libresoc.v:147102$7484_Y - attribute \src "libresoc.v:147103.18-147103.118" - wire $eq$libresoc.v:147103$7485_Y - attribute \src "libresoc.v:147104.18-147104.118" - wire $eq$libresoc.v:147104$7486_Y - attribute \src "libresoc.v:147105.18-147105.118" - wire $eq$libresoc.v:147105$7487_Y - attribute \src "libresoc.v:147106.18-147106.118" - wire $eq$libresoc.v:147106$7488_Y - attribute \src "libresoc.v:147107.18-147107.118" - wire $eq$libresoc.v:147107$7489_Y - attribute \src "libresoc.v:147108.18-147108.118" - wire $eq$libresoc.v:147108$7490_Y - attribute \src "libresoc.v:147109.18-147109.118" - wire $eq$libresoc.v:147109$7491_Y - attribute \src "libresoc.v:147110.18-147110.118" - wire $eq$libresoc.v:147110$7492_Y - attribute \src "libresoc.v:147111.18-147111.118" - wire $eq$libresoc.v:147111$7493_Y - attribute \src "libresoc.v:147112.18-147112.118" - wire $eq$libresoc.v:147112$7494_Y - attribute \src "libresoc.v:147113.18-147113.118" - wire $eq$libresoc.v:147113$7495_Y - attribute \src "libresoc.v:147114.18-147114.118" - wire $eq$libresoc.v:147114$7496_Y - attribute \src "libresoc.v:147115.18-147115.118" - wire $eq$libresoc.v:147115$7497_Y - attribute \src "libresoc.v:147116.18-147116.118" - wire $eq$libresoc.v:147116$7498_Y - attribute \src "libresoc.v:147117.18-147117.118" - wire $eq$libresoc.v:147117$7499_Y - attribute \src "libresoc.v:147118.18-147118.118" - wire $eq$libresoc.v:147118$7500_Y - attribute \src "libresoc.v:147119.18-147119.118" - wire $eq$libresoc.v:147119$7501_Y - attribute \src "libresoc.v:147120.18-147120.118" - wire $eq$libresoc.v:147120$7502_Y - attribute \src "libresoc.v:147071.19-147071.104" - wire width 64 $extend$libresoc.v:147071$7448_Y - attribute \src "libresoc.v:147073.19-147073.93" - wire width 8 $extend$libresoc.v:147073$7451_Y - attribute \src "libresoc.v:147075.19-147075.105" - wire width 64 $extend$libresoc.v:147075$7454_Y - attribute \src "libresoc.v:147076.19-147076.118" - wire width 64 $extend$libresoc.v:147076$7456_Y - attribute \src "libresoc.v:147080.19-147080.105" - wire width 64 $extend$libresoc.v:147080$7461_Y - attribute \src "libresoc.v:147083.18-147083.103" - wire width 64 $or$libresoc.v:147083$7465_Y - attribute \src "libresoc.v:147071.19-147071.104" - wire width 64 $pos$libresoc.v:147071$7449_Y - attribute \src "libresoc.v:147073.19-147073.93" - wire width 8 $pos$libresoc.v:147073$7452_Y - attribute \src "libresoc.v:147075.19-147075.105" - wire width 64 $pos$libresoc.v:147075$7455_Y - attribute \src "libresoc.v:147076.19-147076.118" - wire width 64 $pos$libresoc.v:147076$7457_Y - attribute \src "libresoc.v:147080.19-147080.105" - wire width 64 $pos$libresoc.v:147080$7462_Y - attribute \src "libresoc.v:147077.19-147077.131" - wire $reduce_xor$libresoc.v:147077$7458_Y - attribute \src "libresoc.v:147078.19-147078.133" - wire $reduce_xor$libresoc.v:147078$7459_Y - attribute \src "libresoc.v:147072.19-147072.112" - wire width 8 $sub$libresoc.v:147072$7450_Y - attribute \src "libresoc.v:147074.19-147074.135" - wire width 8 $ternary$libresoc.v:147074$7453_Y - attribute \src "libresoc.v:147079.19-147079.398" - wire width 32 $ternary$libresoc.v:147079$7460_Y - attribute \src "libresoc.v:147081.19-147081.621" - wire width 64 $ternary$libresoc.v:147081$7463_Y - attribute \src "libresoc.v:147070.19-147070.108" - wire $xor$libresoc.v:147070$7447_Y - attribute \src "libresoc.v:147084.18-147084.103" - wire width 64 $xor$libresoc.v:147084$7466_Y + attribute \src "libresoc.v:148916.18-148916.103" + wire width 64 $and$libresoc.v:148916$7509_Y + attribute \src "libresoc.v:148875.18-148875.118" + wire $eq$libresoc.v:148875$7463_Y + attribute \src "libresoc.v:148876.19-148876.119" + wire $eq$libresoc.v:148876$7464_Y + attribute \src "libresoc.v:148877.19-148877.119" + wire $eq$libresoc.v:148877$7465_Y + attribute \src "libresoc.v:148878.19-148878.119" + wire $eq$libresoc.v:148878$7466_Y + attribute \src "libresoc.v:148879.19-148879.119" + wire $eq$libresoc.v:148879$7467_Y + attribute \src "libresoc.v:148880.19-148880.119" + wire $eq$libresoc.v:148880$7468_Y + attribute \src "libresoc.v:148881.19-148881.119" + wire $eq$libresoc.v:148881$7469_Y + attribute \src "libresoc.v:148882.19-148882.119" + wire $eq$libresoc.v:148882$7470_Y + attribute \src "libresoc.v:148883.19-148883.119" + wire $eq$libresoc.v:148883$7471_Y + attribute \src "libresoc.v:148884.19-148884.119" + wire $eq$libresoc.v:148884$7472_Y + attribute \src "libresoc.v:148885.19-148885.119" + wire $eq$libresoc.v:148885$7473_Y + attribute \src "libresoc.v:148886.19-148886.119" + wire $eq$libresoc.v:148886$7474_Y + attribute \src "libresoc.v:148887.19-148887.119" + wire $eq$libresoc.v:148887$7475_Y + attribute \src "libresoc.v:148888.19-148888.119" + wire $eq$libresoc.v:148888$7476_Y + attribute \src "libresoc.v:148889.19-148889.119" + wire $eq$libresoc.v:148889$7477_Y + attribute \src "libresoc.v:148890.19-148890.119" + wire $eq$libresoc.v:148890$7478_Y + attribute \src "libresoc.v:148891.19-148891.119" + wire $eq$libresoc.v:148891$7479_Y + attribute \src "libresoc.v:148892.19-148892.119" + wire $eq$libresoc.v:148892$7480_Y + attribute \src "libresoc.v:148893.19-148893.119" + wire $eq$libresoc.v:148893$7481_Y + attribute \src "libresoc.v:148894.19-148894.119" + wire $eq$libresoc.v:148894$7482_Y + attribute \src "libresoc.v:148895.19-148895.119" + wire $eq$libresoc.v:148895$7483_Y + attribute \src "libresoc.v:148896.19-148896.119" + wire $eq$libresoc.v:148896$7484_Y + attribute \src "libresoc.v:148897.19-148897.119" + wire $eq$libresoc.v:148897$7485_Y + attribute \src "libresoc.v:148898.19-148898.119" + wire $eq$libresoc.v:148898$7486_Y + attribute \src "libresoc.v:148899.19-148899.119" + wire $eq$libresoc.v:148899$7487_Y + attribute \src "libresoc.v:148900.19-148900.119" + wire $eq$libresoc.v:148900$7488_Y + attribute \src "libresoc.v:148901.19-148901.119" + wire $eq$libresoc.v:148901$7489_Y + attribute \src "libresoc.v:148902.19-148902.119" + wire $eq$libresoc.v:148902$7490_Y + attribute \src "libresoc.v:148903.19-148903.128" + wire $eq$libresoc.v:148903$7491_Y + attribute \src "libresoc.v:148919.18-148919.114" + wire $eq$libresoc.v:148919$7512_Y + attribute \src "libresoc.v:148920.18-148920.114" + wire $eq$libresoc.v:148920$7513_Y + attribute \src "libresoc.v:148921.18-148921.114" + wire $eq$libresoc.v:148921$7514_Y + attribute \src "libresoc.v:148922.18-148922.114" + wire $eq$libresoc.v:148922$7515_Y + attribute \src "libresoc.v:148923.18-148923.114" + wire $eq$libresoc.v:148923$7516_Y + attribute \src "libresoc.v:148924.18-148924.114" + wire $eq$libresoc.v:148924$7517_Y + attribute \src "libresoc.v:148925.18-148925.114" + wire $eq$libresoc.v:148925$7518_Y + attribute \src "libresoc.v:148926.18-148926.114" + wire $eq$libresoc.v:148926$7519_Y + attribute \src "libresoc.v:148927.18-148927.116" + wire $eq$libresoc.v:148927$7520_Y + attribute \src "libresoc.v:148928.18-148928.116" + wire $eq$libresoc.v:148928$7521_Y + attribute \src "libresoc.v:148929.18-148929.116" + wire $eq$libresoc.v:148929$7522_Y + attribute \src "libresoc.v:148930.18-148930.116" + wire $eq$libresoc.v:148930$7523_Y + attribute \src "libresoc.v:148931.18-148931.116" + wire $eq$libresoc.v:148931$7524_Y + attribute \src "libresoc.v:148932.18-148932.116" + wire $eq$libresoc.v:148932$7525_Y + attribute \src "libresoc.v:148933.18-148933.116" + wire $eq$libresoc.v:148933$7526_Y + attribute \src "libresoc.v:148934.18-148934.116" + wire $eq$libresoc.v:148934$7527_Y + attribute \src "libresoc.v:148935.18-148935.118" + wire $eq$libresoc.v:148935$7528_Y + attribute \src "libresoc.v:148936.18-148936.118" + wire $eq$libresoc.v:148936$7529_Y + attribute \src "libresoc.v:148937.18-148937.118" + wire $eq$libresoc.v:148937$7530_Y + attribute \src "libresoc.v:148938.18-148938.118" + wire $eq$libresoc.v:148938$7531_Y + attribute \src "libresoc.v:148939.18-148939.118" + wire $eq$libresoc.v:148939$7532_Y + attribute \src "libresoc.v:148940.18-148940.118" + wire $eq$libresoc.v:148940$7533_Y + attribute \src "libresoc.v:148941.18-148941.118" + wire $eq$libresoc.v:148941$7534_Y + attribute \src "libresoc.v:148942.18-148942.118" + wire $eq$libresoc.v:148942$7535_Y + attribute \src "libresoc.v:148943.18-148943.118" + wire $eq$libresoc.v:148943$7536_Y + attribute \src "libresoc.v:148944.18-148944.118" + wire $eq$libresoc.v:148944$7537_Y + attribute \src "libresoc.v:148945.18-148945.118" + wire $eq$libresoc.v:148945$7538_Y + attribute \src "libresoc.v:148946.18-148946.118" + wire $eq$libresoc.v:148946$7539_Y + attribute \src "libresoc.v:148947.18-148947.118" + wire $eq$libresoc.v:148947$7540_Y + attribute \src "libresoc.v:148948.18-148948.118" + wire $eq$libresoc.v:148948$7541_Y + attribute \src "libresoc.v:148949.18-148949.118" + wire $eq$libresoc.v:148949$7542_Y + attribute \src "libresoc.v:148950.18-148950.118" + wire $eq$libresoc.v:148950$7543_Y + attribute \src "libresoc.v:148951.18-148951.118" + wire $eq$libresoc.v:148951$7544_Y + attribute \src "libresoc.v:148952.18-148952.118" + wire $eq$libresoc.v:148952$7545_Y + attribute \src "libresoc.v:148953.18-148953.118" + wire $eq$libresoc.v:148953$7546_Y + attribute \src "libresoc.v:148954.18-148954.118" + wire $eq$libresoc.v:148954$7547_Y + attribute \src "libresoc.v:148905.19-148905.104" + wire width 64 $extend$libresoc.v:148905$7493_Y + attribute \src "libresoc.v:148907.19-148907.93" + wire width 8 $extend$libresoc.v:148907$7496_Y + attribute \src "libresoc.v:148909.19-148909.105" + wire width 64 $extend$libresoc.v:148909$7499_Y + attribute \src "libresoc.v:148910.19-148910.118" + wire width 64 $extend$libresoc.v:148910$7501_Y + attribute \src "libresoc.v:148914.19-148914.105" + wire width 64 $extend$libresoc.v:148914$7506_Y + attribute \src "libresoc.v:148917.18-148917.103" + wire width 64 $or$libresoc.v:148917$7510_Y + attribute \src "libresoc.v:148905.19-148905.104" + wire width 64 $pos$libresoc.v:148905$7494_Y + attribute \src "libresoc.v:148907.19-148907.93" + wire width 8 $pos$libresoc.v:148907$7497_Y + attribute \src "libresoc.v:148909.19-148909.105" + wire width 64 $pos$libresoc.v:148909$7500_Y + attribute \src "libresoc.v:148910.19-148910.118" + wire width 64 $pos$libresoc.v:148910$7502_Y + attribute \src "libresoc.v:148914.19-148914.105" + wire width 64 $pos$libresoc.v:148914$7507_Y + attribute \src "libresoc.v:148911.19-148911.131" + wire $reduce_xor$libresoc.v:148911$7503_Y + attribute \src "libresoc.v:148912.19-148912.133" + wire $reduce_xor$libresoc.v:148912$7504_Y + attribute \src "libresoc.v:148906.19-148906.112" + wire width 8 $sub$libresoc.v:148906$7495_Y + attribute \src "libresoc.v:148908.19-148908.135" + wire width 8 $ternary$libresoc.v:148908$7498_Y + attribute \src "libresoc.v:148913.19-148913.398" + wire width 32 $ternary$libresoc.v:148913$7505_Y + attribute \src "libresoc.v:148915.19-148915.621" + wire width 64 $ternary$libresoc.v:148915$7508_Y + attribute \src "libresoc.v:148904.19-148904.108" + wire $xor$libresoc.v:148904$7492_Y + attribute \src "libresoc.v:148918.18-148918.103" + wire width 64 $xor$libresoc.v:148918$7511_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -308441,44 +310966,46 @@ module \main$51 wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:146578.7-146578.15" + attribute \src "libresoc.v:148408.7-148408.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 24 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -308577,6 +311104,7 @@ module \main$51 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -308653,6 +311181,7 @@ module \main$51 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -308726,7 +311255,7 @@ module \main$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:147082$7464 + cell $and $and$libresoc.v:148916$7509 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308734,10 +311263,10 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:147082$7464_Y + connect \Y $and$libresoc.v:148916$7509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147041$7418 + cell $eq $eq$libresoc.v:148875$7463 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308745,10 +311274,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147041$7418_Y + connect \Y $eq$libresoc.v:148875$7463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147042$7419 + cell $eq $eq$libresoc.v:148876$7464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308756,10 +311285,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147042$7419_Y + connect \Y $eq$libresoc.v:148876$7464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147043$7420 + cell $eq $eq$libresoc.v:148877$7465 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308767,10 +311296,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147043$7420_Y + connect \Y $eq$libresoc.v:148877$7465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147044$7421 + cell $eq $eq$libresoc.v:148878$7466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308778,10 +311307,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147044$7421_Y + connect \Y $eq$libresoc.v:148878$7466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147045$7422 + cell $eq $eq$libresoc.v:148879$7467 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308789,10 +311318,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147045$7422_Y + connect \Y $eq$libresoc.v:148879$7467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147046$7423 + cell $eq $eq$libresoc.v:148880$7468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308800,10 +311329,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147046$7423_Y + connect \Y $eq$libresoc.v:148880$7468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147047$7424 + cell $eq $eq$libresoc.v:148881$7469 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308811,10 +311340,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147047$7424_Y + connect \Y $eq$libresoc.v:148881$7469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147048$7425 + cell $eq $eq$libresoc.v:148882$7470 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308822,10 +311351,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147048$7425_Y + connect \Y $eq$libresoc.v:148882$7470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147049$7426 + cell $eq $eq$libresoc.v:148883$7471 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308833,10 +311362,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147049$7426_Y + connect \Y $eq$libresoc.v:148883$7471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147050$7427 + cell $eq $eq$libresoc.v:148884$7472 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308844,10 +311373,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147050$7427_Y + connect \Y $eq$libresoc.v:148884$7472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147051$7428 + cell $eq $eq$libresoc.v:148885$7473 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308855,10 +311384,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147051$7428_Y + connect \Y $eq$libresoc.v:148885$7473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147052$7429 + cell $eq $eq$libresoc.v:148886$7474 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308866,10 +311395,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147052$7429_Y + connect \Y $eq$libresoc.v:148886$7474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147053$7430 + cell $eq $eq$libresoc.v:148887$7475 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308877,10 +311406,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147053$7430_Y + connect \Y $eq$libresoc.v:148887$7475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147054$7431 + cell $eq $eq$libresoc.v:148888$7476 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308888,10 +311417,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147054$7431_Y + connect \Y $eq$libresoc.v:148888$7476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147055$7432 + cell $eq $eq$libresoc.v:148889$7477 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308899,10 +311428,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147055$7432_Y + connect \Y $eq$libresoc.v:148889$7477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147056$7433 + cell $eq $eq$libresoc.v:148890$7478 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308910,10 +311439,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147056$7433_Y + connect \Y $eq$libresoc.v:148890$7478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147057$7434 + cell $eq $eq$libresoc.v:148891$7479 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308921,10 +311450,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147057$7434_Y + connect \Y $eq$libresoc.v:148891$7479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147058$7435 + cell $eq $eq$libresoc.v:148892$7480 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308932,10 +311461,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147058$7435_Y + connect \Y $eq$libresoc.v:148892$7480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147059$7436 + cell $eq $eq$libresoc.v:148893$7481 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308943,10 +311472,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147059$7436_Y + connect \Y $eq$libresoc.v:148893$7481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147060$7437 + cell $eq $eq$libresoc.v:148894$7482 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308954,10 +311483,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147060$7437_Y + connect \Y $eq$libresoc.v:148894$7482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147061$7438 + cell $eq $eq$libresoc.v:148895$7483 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308965,10 +311494,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147061$7438_Y + connect \Y $eq$libresoc.v:148895$7483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147062$7439 + cell $eq $eq$libresoc.v:148896$7484 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308976,10 +311505,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147062$7439_Y + connect \Y $eq$libresoc.v:148896$7484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147063$7440 + cell $eq $eq$libresoc.v:148897$7485 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308987,10 +311516,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147063$7440_Y + connect \Y $eq$libresoc.v:148897$7485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147064$7441 + cell $eq $eq$libresoc.v:148898$7486 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308998,10 +311527,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147064$7441_Y + connect \Y $eq$libresoc.v:148898$7486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147065$7442 + cell $eq $eq$libresoc.v:148899$7487 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309009,10 +311538,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147065$7442_Y + connect \Y $eq$libresoc.v:148899$7487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147066$7443 + cell $eq $eq$libresoc.v:148900$7488 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309020,10 +311549,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147066$7443_Y + connect \Y $eq$libresoc.v:148900$7488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147067$7444 + cell $eq $eq$libresoc.v:148901$7489 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309031,10 +311560,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147067$7444_Y + connect \Y $eq$libresoc.v:148901$7489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147068$7445 + cell $eq $eq$libresoc.v:148902$7490 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309042,10 +311571,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147068$7445_Y + connect \Y $eq$libresoc.v:148902$7490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:147069$7446 + cell $eq $eq$libresoc.v:148903$7491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309053,10 +311582,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:147069$7446_Y + connect \Y $eq$libresoc.v:148903$7491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147085$7467 + cell $eq $eq$libresoc.v:148919$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309064,10 +311593,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147085$7467_Y + connect \Y $eq$libresoc.v:148919$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147086$7468 + cell $eq $eq$libresoc.v:148920$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309075,10 +311604,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147086$7468_Y + connect \Y $eq$libresoc.v:148920$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147087$7469 + cell $eq $eq$libresoc.v:148921$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309086,10 +311615,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147087$7469_Y + connect \Y $eq$libresoc.v:148921$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147088$7470 + cell $eq $eq$libresoc.v:148922$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309097,10 +311626,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147088$7470_Y + connect \Y $eq$libresoc.v:148922$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147089$7471 + cell $eq $eq$libresoc.v:148923$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309108,10 +311637,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147089$7471_Y + connect \Y $eq$libresoc.v:148923$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147090$7472 + cell $eq $eq$libresoc.v:148924$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309119,10 +311648,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147090$7472_Y + connect \Y $eq$libresoc.v:148924$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147091$7473 + cell $eq $eq$libresoc.v:148925$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309130,10 +311659,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147091$7473_Y + connect \Y $eq$libresoc.v:148925$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147092$7474 + cell $eq $eq$libresoc.v:148926$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309141,10 +311670,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147092$7474_Y + connect \Y $eq$libresoc.v:148926$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147093$7475 + cell $eq $eq$libresoc.v:148927$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309152,10 +311681,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147093$7475_Y + connect \Y $eq$libresoc.v:148927$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147094$7476 + cell $eq $eq$libresoc.v:148928$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309163,10 +311692,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147094$7476_Y + connect \Y $eq$libresoc.v:148928$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147095$7477 + cell $eq $eq$libresoc.v:148929$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309174,10 +311703,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147095$7477_Y + connect \Y $eq$libresoc.v:148929$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147096$7478 + cell $eq $eq$libresoc.v:148930$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309185,10 +311714,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147096$7478_Y + connect \Y $eq$libresoc.v:148930$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147097$7479 + cell $eq $eq$libresoc.v:148931$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309196,10 +311725,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147097$7479_Y + connect \Y $eq$libresoc.v:148931$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147098$7480 + cell $eq $eq$libresoc.v:148932$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309207,10 +311736,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147098$7480_Y + connect \Y $eq$libresoc.v:148932$7525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147099$7481 + cell $eq $eq$libresoc.v:148933$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309218,10 +311747,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147099$7481_Y + connect \Y $eq$libresoc.v:148933$7526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147100$7482 + cell $eq $eq$libresoc.v:148934$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309229,10 +311758,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147100$7482_Y + connect \Y $eq$libresoc.v:148934$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147101$7483 + cell $eq $eq$libresoc.v:148935$7528 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309240,10 +311769,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147101$7483_Y + connect \Y $eq$libresoc.v:148935$7528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147102$7484 + cell $eq $eq$libresoc.v:148936$7529 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309251,10 +311780,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147102$7484_Y + connect \Y $eq$libresoc.v:148936$7529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147103$7485 + cell $eq $eq$libresoc.v:148937$7530 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309262,10 +311791,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147103$7485_Y + connect \Y $eq$libresoc.v:148937$7530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147104$7486 + cell $eq $eq$libresoc.v:148938$7531 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309273,10 +311802,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147104$7486_Y + connect \Y $eq$libresoc.v:148938$7531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147105$7487 + cell $eq $eq$libresoc.v:148939$7532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309284,10 +311813,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147105$7487_Y + connect \Y $eq$libresoc.v:148939$7532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147106$7488 + cell $eq $eq$libresoc.v:148940$7533 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309295,10 +311824,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147106$7488_Y + connect \Y $eq$libresoc.v:148940$7533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147107$7489 + cell $eq $eq$libresoc.v:148941$7534 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309306,10 +311835,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147107$7489_Y + connect \Y $eq$libresoc.v:148941$7534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147108$7490 + cell $eq $eq$libresoc.v:148942$7535 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309317,10 +311846,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147108$7490_Y + connect \Y $eq$libresoc.v:148942$7535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147109$7491 + cell $eq $eq$libresoc.v:148943$7536 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309328,10 +311857,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147109$7491_Y + connect \Y $eq$libresoc.v:148943$7536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147110$7492 + cell $eq $eq$libresoc.v:148944$7537 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309339,10 +311868,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147110$7492_Y + connect \Y $eq$libresoc.v:148944$7537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147111$7493 + cell $eq $eq$libresoc.v:148945$7538 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309350,10 +311879,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147111$7493_Y + connect \Y $eq$libresoc.v:148945$7538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147112$7494 + cell $eq $eq$libresoc.v:148946$7539 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309361,10 +311890,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147112$7494_Y + connect \Y $eq$libresoc.v:148946$7539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147113$7495 + cell $eq $eq$libresoc.v:148947$7540 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309372,10 +311901,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147113$7495_Y + connect \Y $eq$libresoc.v:148947$7540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147114$7496 + cell $eq $eq$libresoc.v:148948$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309383,10 +311912,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147114$7496_Y + connect \Y $eq$libresoc.v:148948$7541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147115$7497 + cell $eq $eq$libresoc.v:148949$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309394,10 +311923,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147115$7497_Y + connect \Y $eq$libresoc.v:148949$7542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147116$7498 + cell $eq $eq$libresoc.v:148950$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309405,10 +311934,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147116$7498_Y + connect \Y $eq$libresoc.v:148950$7543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147117$7499 + cell $eq $eq$libresoc.v:148951$7544 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309416,10 +311945,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147117$7499_Y + connect \Y $eq$libresoc.v:148951$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147118$7500 + cell $eq $eq$libresoc.v:148952$7545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309427,10 +311956,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147118$7500_Y + connect \Y $eq$libresoc.v:148952$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147119$7501 + cell $eq $eq$libresoc.v:148953$7546 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309438,10 +311967,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147119$7501_Y + connect \Y $eq$libresoc.v:148953$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:147120$7502 + cell $eq $eq$libresoc.v:148954$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309449,50 +311978,50 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147120$7502_Y + connect \Y $eq$libresoc.v:148954$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:147071$7448 + cell $pos $extend$libresoc.v:148905$7493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:147071$7448_Y + connect \Y $extend$libresoc.v:148905$7493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $extend$libresoc.v:147073$7451 + cell $pos $extend$libresoc.v:148907$7496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:147073$7451_Y + connect \Y $extend$libresoc.v:148907$7496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:147075$7454 + cell $pos $extend$libresoc.v:148909$7499 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:147075$7454_Y + connect \Y $extend$libresoc.v:148909$7499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:147076$7456 + cell $pos $extend$libresoc.v:148910$7501 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:147076$7456_Y + connect \Y $extend$libresoc.v:148910$7501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:147080$7461 + cell $pos $extend$libresoc.v:148914$7506 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:147080$7461_Y + connect \Y $extend$libresoc.v:148914$7506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:147083$7465 + cell $or $or$libresoc.v:148917$7510 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309500,66 +312029,66 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:147083$7465_Y + connect \Y $or$libresoc.v:148917$7510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:147071$7449 + cell $pos $pos$libresoc.v:148905$7494 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147071$7448_Y - connect \Y $pos$libresoc.v:147071$7449_Y + connect \A $extend$libresoc.v:148905$7493_Y + connect \Y $pos$libresoc.v:148905$7494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $pos$libresoc.v:147073$7452 + cell $pos $pos$libresoc.v:148907$7497 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:147073$7451_Y - connect \Y $pos$libresoc.v:147073$7452_Y + connect \A $extend$libresoc.v:148907$7496_Y + connect \Y $pos$libresoc.v:148907$7497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:147075$7455 + cell $pos $pos$libresoc.v:148909$7500 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147075$7454_Y - connect \Y $pos$libresoc.v:147075$7455_Y + connect \A $extend$libresoc.v:148909$7499_Y + connect \Y $pos$libresoc.v:148909$7500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:147076$7457 + cell $pos $pos$libresoc.v:148910$7502 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147076$7456_Y - connect \Y $pos$libresoc.v:147076$7457_Y + connect \A $extend$libresoc.v:148910$7501_Y + connect \Y $pos$libresoc.v:148910$7502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:147080$7462 + cell $pos $pos$libresoc.v:148914$7507 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147080$7461_Y - connect \Y $pos$libresoc.v:147080$7462_Y + connect \A $extend$libresoc.v:148914$7506_Y + connect \Y $pos$libresoc.v:148914$7507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:147077$7458 + cell $reduce_xor $reduce_xor$libresoc.v:148911$7503 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:147077$7458_Y + connect \Y $reduce_xor$libresoc.v:148911$7503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:147078$7459 + cell $reduce_xor $reduce_xor$libresoc.v:148912$7504 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:147078$7459_Y + connect \Y $reduce_xor$libresoc.v:148912$7504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:147072$7450 + cell $sub $sub$libresoc.v:148906$7495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -309567,34 +312096,34 @@ module \main$51 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:147072$7450_Y + connect \Y $sub$libresoc.v:148906$7495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:147074$7453 + cell $mux $ternary$libresoc.v:148908$7498 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:147074$7453_Y + connect \Y $ternary$libresoc.v:148908$7498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:147079$7460 + cell $mux $ternary$libresoc.v:148913$7505 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:147079$7460_Y + connect \Y $ternary$libresoc.v:148913$7505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:147081$7463 + cell $mux $ternary$libresoc.v:148915$7508 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:147081$7463_Y + connect \Y $ternary$libresoc.v:148915$7508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:147070$7447 + cell $xor $xor$libresoc.v:148904$7492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309602,10 +312131,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:147070$7447_Y + connect \Y $xor$libresoc.v:148904$7492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:147084$7466 + cell $xor $xor$libresoc.v:148918$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309613,47 +312142,47 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:147084$7466_Y + connect \Y $xor$libresoc.v:148918$7511_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:147121.10-147125.4" + attribute \src "libresoc.v:148955.10-148959.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:147126.7-147129.4" + attribute \src "libresoc.v:148960.7-148963.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:147130.12-147134.4" + attribute \src "libresoc.v:148964.12-148968.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:146578.7-146578.20" - process $proc$libresoc.v:146578$7515 + attribute \src "libresoc.v:148408.7-148408.20" + process $proc$libresoc.v:148408$7560 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147135.3-147189.6" - process $proc$libresoc.v:147135$7503 + attribute \src "libresoc.v:148969.3-149023.6" + process $proc$libresoc.v:148969$7548 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:147136.5-147136.29" + attribute \src "libresoc.v:148970.5-148970.29" switch \initial - attribute \src "libresoc.v:147136.9-147136.17" + attribute \src "libresoc.v:148970.9-148970.17" case 1'1 case end @@ -309721,14 +312250,14 @@ module \main$51 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:147190.3-147200.6" - process $proc$libresoc.v:147190$7504 + attribute \src "libresoc.v:149024.3-149034.6" + process $proc$libresoc.v:149024$7549 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:147191.5-147191.29" + attribute \src "libresoc.v:149025.5-149025.29" switch \initial - attribute \src "libresoc.v:147191.9-147191.17" + attribute \src "libresoc.v:149025.9-149025.17" case 1'1 case end @@ -309744,14 +312273,14 @@ module \main$51 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:147201.3-147211.6" - process $proc$libresoc.v:147201$7505 + attribute \src "libresoc.v:149035.3-149045.6" + process $proc$libresoc.v:149035$7550 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:147202.5-147202.29" + attribute \src "libresoc.v:149036.5-149036.29" switch \initial - attribute \src "libresoc.v:147202.9-147202.17" + attribute \src "libresoc.v:149036.9-149036.17" case 1'1 case end @@ -309767,14 +312296,14 @@ module \main$51 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:147212.3-147222.6" - process $proc$libresoc.v:147212$7506 + attribute \src "libresoc.v:149046.3-149056.6" + process $proc$libresoc.v:149046$7551 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:147213.5-147213.29" + attribute \src "libresoc.v:149047.5-149047.29" switch \initial - attribute \src "libresoc.v:147213.9-147213.17" + attribute \src "libresoc.v:149047.9-149047.17" case 1'1 case end @@ -309790,14 +312319,14 @@ module \main$51 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:147223.3-147233.6" - process $proc$libresoc.v:147223$7507 + attribute \src "libresoc.v:149057.3-149067.6" + process $proc$libresoc.v:149057$7552 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:147224.5-147224.29" + attribute \src "libresoc.v:149058.5-149058.29" switch \initial - attribute \src "libresoc.v:147224.9-147224.17" + attribute \src "libresoc.v:149058.9-149058.17" case 1'1 case end @@ -309813,14 +312342,14 @@ module \main$51 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:147234.3-147244.6" - process $proc$libresoc.v:147234$7508 + attribute \src "libresoc.v:149068.3-149078.6" + process $proc$libresoc.v:149068$7553 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:147235.5-147235.29" + attribute \src "libresoc.v:149069.5-149069.29" switch \initial - attribute \src "libresoc.v:147235.9-147235.17" + attribute \src "libresoc.v:149069.9-149069.17" case 1'1 case end @@ -309836,14 +312365,14 @@ module \main$51 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:147245.3-147255.6" - process $proc$libresoc.v:147245$7509 + attribute \src "libresoc.v:149079.3-149089.6" + process $proc$libresoc.v:149079$7554 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:147246.5-147246.29" + attribute \src "libresoc.v:149080.5-149080.29" switch \initial - attribute \src "libresoc.v:147246.9-147246.17" + attribute \src "libresoc.v:149080.9-149080.17" case 1'1 case end @@ -309859,14 +312388,14 @@ module \main$51 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:147256.3-147266.6" - process $proc$libresoc.v:147256$7510 + attribute \src "libresoc.v:149090.3-149100.6" + process $proc$libresoc.v:149090$7555 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:147257.5-147257.29" + attribute \src "libresoc.v:149091.5-149091.29" switch \initial - attribute \src "libresoc.v:147257.9-147257.17" + attribute \src "libresoc.v:149091.9-149091.17" case 1'1 case end @@ -309882,14 +312411,14 @@ module \main$51 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:147267.3-147277.6" - process $proc$libresoc.v:147267$7511 + attribute \src "libresoc.v:149101.3-149111.6" + process $proc$libresoc.v:149101$7556 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:147268.5-147268.29" + attribute \src "libresoc.v:149102.5-149102.29" switch \initial - attribute \src "libresoc.v:147268.9-147268.17" + attribute \src "libresoc.v:149102.9-149102.17" case 1'1 case end @@ -309905,14 +312434,14 @@ module \main$51 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:147278.3-147288.6" - process $proc$libresoc.v:147278$7512 + attribute \src "libresoc.v:149112.3-149122.6" + process $proc$libresoc.v:149112$7557 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:147279.5-147279.29" + attribute \src "libresoc.v:149113.5-149113.29" switch \initial - attribute \src "libresoc.v:147279.9-147279.17" + attribute \src "libresoc.v:149113.9-149113.17" case 1'1 case end @@ -309928,14 +312457,14 @@ module \main$51 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:147289.3-147299.6" - process $proc$libresoc.v:147289$7513 + attribute \src "libresoc.v:149123.3-149133.6" + process $proc$libresoc.v:149123$7558 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:147290.5-147290.29" + attribute \src "libresoc.v:149124.5-149124.29" switch \initial - attribute \src "libresoc.v:147290.9-147290.17" + attribute \src "libresoc.v:149124.9-149124.17" case 1'1 case end @@ -309951,14 +312480,14 @@ module \main$51 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:147300.3-147318.6" - process $proc$libresoc.v:147300$7514 + attribute \src "libresoc.v:149134.3-149152.6" + process $proc$libresoc.v:149134$7559 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:147301.5-147301.29" + attribute \src "libresoc.v:149135.5-149135.29" switch \initial - attribute \src "libresoc.v:147301.9-147301.17" + attribute \src "libresoc.v:149135.9-149135.17" case 1'1 case end @@ -309985,193 +312514,193 @@ module \main$51 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:147041$7418_Y - connect \$101 $eq$libresoc.v:147042$7419_Y - connect \$103 $eq$libresoc.v:147043$7420_Y - connect \$105 $eq$libresoc.v:147044$7421_Y - connect \$107 $eq$libresoc.v:147045$7422_Y - connect \$109 $eq$libresoc.v:147046$7423_Y - connect \$111 $eq$libresoc.v:147047$7424_Y - connect \$113 $eq$libresoc.v:147048$7425_Y - connect \$115 $eq$libresoc.v:147049$7426_Y - connect \$117 $eq$libresoc.v:147050$7427_Y - connect \$119 $eq$libresoc.v:147051$7428_Y - connect \$121 $eq$libresoc.v:147052$7429_Y - connect \$123 $eq$libresoc.v:147053$7430_Y - connect \$125 $eq$libresoc.v:147054$7431_Y - connect \$127 $eq$libresoc.v:147055$7432_Y - connect \$129 $eq$libresoc.v:147056$7433_Y - connect \$131 $eq$libresoc.v:147057$7434_Y - connect \$133 $eq$libresoc.v:147058$7435_Y - connect \$135 $eq$libresoc.v:147059$7436_Y - connect \$137 $eq$libresoc.v:147060$7437_Y - connect \$139 $eq$libresoc.v:147061$7438_Y - connect \$141 $eq$libresoc.v:147062$7439_Y - connect \$143 $eq$libresoc.v:147063$7440_Y - connect \$145 $eq$libresoc.v:147064$7441_Y - connect \$147 $eq$libresoc.v:147065$7442_Y - connect \$149 $eq$libresoc.v:147066$7443_Y - connect \$151 $eq$libresoc.v:147067$7444_Y - connect \$153 $eq$libresoc.v:147068$7445_Y - connect \$155 $eq$libresoc.v:147069$7446_Y - connect \$158 $xor$libresoc.v:147070$7447_Y - connect \$157 $pos$libresoc.v:147071$7449_Y - connect \$162 $sub$libresoc.v:147072$7450_Y - connect \$164 $pos$libresoc.v:147073$7452_Y - connect \$166 $ternary$libresoc.v:147074$7453_Y - connect \$161 $pos$libresoc.v:147075$7455_Y - connect \$169 $pos$libresoc.v:147076$7457_Y - connect \$171 $reduce_xor$libresoc.v:147077$7458_Y - connect \$173 $reduce_xor$libresoc.v:147078$7459_Y - connect \$176 $ternary$libresoc.v:147079$7460_Y - connect \$175 $pos$libresoc.v:147080$7462_Y - connect \$179 $ternary$libresoc.v:147081$7463_Y - connect \$21 $and$libresoc.v:147082$7464_Y - connect \$23 $or$libresoc.v:147083$7465_Y - connect \$25 $xor$libresoc.v:147084$7466_Y - connect \$27 $eq$libresoc.v:147085$7467_Y - connect \$29 $eq$libresoc.v:147086$7468_Y - connect \$31 $eq$libresoc.v:147087$7469_Y - connect \$33 $eq$libresoc.v:147088$7470_Y - connect \$35 $eq$libresoc.v:147089$7471_Y - connect \$37 $eq$libresoc.v:147090$7472_Y - connect \$39 $eq$libresoc.v:147091$7473_Y - connect \$41 $eq$libresoc.v:147092$7474_Y - connect \$43 $eq$libresoc.v:147093$7475_Y - connect \$45 $eq$libresoc.v:147094$7476_Y - connect \$47 $eq$libresoc.v:147095$7477_Y - connect \$49 $eq$libresoc.v:147096$7478_Y - connect \$51 $eq$libresoc.v:147097$7479_Y - connect \$53 $eq$libresoc.v:147098$7480_Y - connect \$55 $eq$libresoc.v:147099$7481_Y - connect \$57 $eq$libresoc.v:147100$7482_Y - connect \$59 $eq$libresoc.v:147101$7483_Y - connect \$61 $eq$libresoc.v:147102$7484_Y - connect \$63 $eq$libresoc.v:147103$7485_Y - connect \$65 $eq$libresoc.v:147104$7486_Y - connect \$67 $eq$libresoc.v:147105$7487_Y - connect \$69 $eq$libresoc.v:147106$7488_Y - connect \$71 $eq$libresoc.v:147107$7489_Y - connect \$73 $eq$libresoc.v:147108$7490_Y - connect \$75 $eq$libresoc.v:147109$7491_Y - connect \$77 $eq$libresoc.v:147110$7492_Y - connect \$79 $eq$libresoc.v:147111$7493_Y - connect \$81 $eq$libresoc.v:147112$7494_Y - connect \$83 $eq$libresoc.v:147113$7495_Y - connect \$85 $eq$libresoc.v:147114$7496_Y - connect \$87 $eq$libresoc.v:147115$7497_Y - connect \$89 $eq$libresoc.v:147116$7498_Y - connect \$91 $eq$libresoc.v:147117$7499_Y - connect \$93 $eq$libresoc.v:147118$7500_Y - connect \$95 $eq$libresoc.v:147119$7501_Y - connect \$97 $eq$libresoc.v:147120$7502_Y + connect \$99 $eq$libresoc.v:148875$7463_Y + connect \$101 $eq$libresoc.v:148876$7464_Y + connect \$103 $eq$libresoc.v:148877$7465_Y + connect \$105 $eq$libresoc.v:148878$7466_Y + connect \$107 $eq$libresoc.v:148879$7467_Y + connect \$109 $eq$libresoc.v:148880$7468_Y + connect \$111 $eq$libresoc.v:148881$7469_Y + connect \$113 $eq$libresoc.v:148882$7470_Y + connect \$115 $eq$libresoc.v:148883$7471_Y + connect \$117 $eq$libresoc.v:148884$7472_Y + connect \$119 $eq$libresoc.v:148885$7473_Y + connect \$121 $eq$libresoc.v:148886$7474_Y + connect \$123 $eq$libresoc.v:148887$7475_Y + connect \$125 $eq$libresoc.v:148888$7476_Y + connect \$127 $eq$libresoc.v:148889$7477_Y + connect \$129 $eq$libresoc.v:148890$7478_Y + connect \$131 $eq$libresoc.v:148891$7479_Y + connect \$133 $eq$libresoc.v:148892$7480_Y + connect \$135 $eq$libresoc.v:148893$7481_Y + connect \$137 $eq$libresoc.v:148894$7482_Y + connect \$139 $eq$libresoc.v:148895$7483_Y + connect \$141 $eq$libresoc.v:148896$7484_Y + connect \$143 $eq$libresoc.v:148897$7485_Y + connect \$145 $eq$libresoc.v:148898$7486_Y + connect \$147 $eq$libresoc.v:148899$7487_Y + connect \$149 $eq$libresoc.v:148900$7488_Y + connect \$151 $eq$libresoc.v:148901$7489_Y + connect \$153 $eq$libresoc.v:148902$7490_Y + connect \$155 $eq$libresoc.v:148903$7491_Y + connect \$158 $xor$libresoc.v:148904$7492_Y + connect \$157 $pos$libresoc.v:148905$7494_Y + connect \$162 $sub$libresoc.v:148906$7495_Y + connect \$164 $pos$libresoc.v:148907$7497_Y + connect \$166 $ternary$libresoc.v:148908$7498_Y + connect \$161 $pos$libresoc.v:148909$7500_Y + connect \$169 $pos$libresoc.v:148910$7502_Y + connect \$171 $reduce_xor$libresoc.v:148911$7503_Y + connect \$173 $reduce_xor$libresoc.v:148912$7504_Y + connect \$176 $ternary$libresoc.v:148913$7505_Y + connect \$175 $pos$libresoc.v:148914$7507_Y + connect \$179 $ternary$libresoc.v:148915$7508_Y + connect \$21 $and$libresoc.v:148916$7509_Y + connect \$23 $or$libresoc.v:148917$7510_Y + connect \$25 $xor$libresoc.v:148918$7511_Y + connect \$27 $eq$libresoc.v:148919$7512_Y + connect \$29 $eq$libresoc.v:148920$7513_Y + connect \$31 $eq$libresoc.v:148921$7514_Y + connect \$33 $eq$libresoc.v:148922$7515_Y + connect \$35 $eq$libresoc.v:148923$7516_Y + connect \$37 $eq$libresoc.v:148924$7517_Y + connect \$39 $eq$libresoc.v:148925$7518_Y + connect \$41 $eq$libresoc.v:148926$7519_Y + connect \$43 $eq$libresoc.v:148927$7520_Y + connect \$45 $eq$libresoc.v:148928$7521_Y + connect \$47 $eq$libresoc.v:148929$7522_Y + connect \$49 $eq$libresoc.v:148930$7523_Y + connect \$51 $eq$libresoc.v:148931$7524_Y + connect \$53 $eq$libresoc.v:148932$7525_Y + connect \$55 $eq$libresoc.v:148933$7526_Y + connect \$57 $eq$libresoc.v:148934$7527_Y + connect \$59 $eq$libresoc.v:148935$7528_Y + connect \$61 $eq$libresoc.v:148936$7529_Y + connect \$63 $eq$libresoc.v:148937$7530_Y + connect \$65 $eq$libresoc.v:148938$7531_Y + connect \$67 $eq$libresoc.v:148939$7532_Y + connect \$69 $eq$libresoc.v:148940$7533_Y + connect \$71 $eq$libresoc.v:148941$7534_Y + connect \$73 $eq$libresoc.v:148942$7535_Y + connect \$75 $eq$libresoc.v:148943$7536_Y + connect \$77 $eq$libresoc.v:148944$7537_Y + connect \$79 $eq$libresoc.v:148945$7538_Y + connect \$81 $eq$libresoc.v:148946$7539_Y + connect \$83 $eq$libresoc.v:148947$7540_Y + connect \$85 $eq$libresoc.v:148948$7541_Y + connect \$87 $eq$libresoc.v:148949$7542_Y + connect \$89 $eq$libresoc.v:148950$7543_Y + connect \$91 $eq$libresoc.v:148951$7544_Y + connect \$93 $eq$libresoc.v:148952$7545_Y + connect \$95 $eq$libresoc.v:148953$7546_Y + connect \$97 $eq$libresoc.v:148954$7547_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:147326.1-147837.10" +attribute \src "libresoc.v:149160.1-149675.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:147692.3-147702.6" + attribute \src "libresoc.v:149530.3-149540.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:147746.3-147756.6" + attribute \src "libresoc.v:149584.3-149594.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:147757.3-147767.6" + attribute \src "libresoc.v:149595.3-149605.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:147768.3-147788.6" + attribute \src "libresoc.v:149606.3-149626.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:147789.3-147809.6" + attribute \src "libresoc.v:149627.3-149647.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:147810.3-147820.6" + attribute \src "libresoc.v:149648.3-149658.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:147735.3-147745.6" + attribute \src "libresoc.v:149573.3-149583.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:147604.3-147638.6" - wire width 4 $0\cr_a$6[3:0]$7530 - attribute \src "libresoc.v:147604.3-147638.6" + attribute \src "libresoc.v:149442.3-149476.6" + wire width 4 $0\cr_a$6[3:0]$7575 + attribute \src "libresoc.v:149442.3-149476.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:147703.3-147723.6" + attribute \src "libresoc.v:149541.3-149561.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:147821.3-147831.6" - wire width 32 $0\full_cr$5[31:0]$7545 - attribute \src "libresoc.v:147639.3-147649.6" + attribute \src "libresoc.v:149659.3-149669.6" + wire width 32 $0\full_cr$5[31:0]$7590 + attribute \src "libresoc.v:149477.3-149487.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:147327.7-147327.20" + attribute \src "libresoc.v:149161.7-149161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147724.3-147734.6" + attribute \src "libresoc.v:149562.3-149572.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:147650.3-147691.6" + attribute \src "libresoc.v:149488.3-149529.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:147650.3-147691.6" + attribute \src "libresoc.v:149488.3-149529.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:147692.3-147702.6" + attribute \src "libresoc.v:149530.3-149540.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:147746.3-147756.6" + attribute \src "libresoc.v:149584.3-149594.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:147757.3-147767.6" + attribute \src "libresoc.v:149595.3-149605.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:147768.3-147788.6" + attribute \src "libresoc.v:149606.3-149626.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:147789.3-147809.6" + attribute \src "libresoc.v:149627.3-149647.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:147810.3-147820.6" + attribute \src "libresoc.v:149648.3-149658.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:147735.3-147745.6" + attribute \src "libresoc.v:149573.3-149583.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:147604.3-147638.6" - wire width 4 $1\cr_a$6[3:0]$7531 - attribute \src "libresoc.v:147604.3-147638.6" + attribute \src "libresoc.v:149442.3-149476.6" + wire width 4 $1\cr_a$6[3:0]$7576 + attribute \src "libresoc.v:149442.3-149476.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:147703.3-147723.6" + attribute \src "libresoc.v:149541.3-149561.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:147821.3-147831.6" - wire width 32 $1\full_cr$5[31:0]$7546 - attribute \src "libresoc.v:147639.3-147649.6" + attribute \src "libresoc.v:149659.3-149669.6" + wire width 32 $1\full_cr$5[31:0]$7591 + attribute \src "libresoc.v:149477.3-149487.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:147724.3-147734.6" + attribute \src "libresoc.v:149562.3-149572.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:147650.3-147691.6" + attribute \src "libresoc.v:149488.3-149529.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:147650.3-147691.6" + attribute \src "libresoc.v:149488.3-149529.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:147768.3-147788.6" + attribute \src "libresoc.v:149606.3-149626.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:147789.3-147809.6" + attribute \src "libresoc.v:149627.3-149647.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:147604.3-147638.6" - wire width 4 $2\cr_a$6[3:0]$7532 - attribute \src "libresoc.v:147703.3-147723.6" + attribute \src "libresoc.v:149442.3-149476.6" + wire width 4 $2\cr_a$6[3:0]$7577 + attribute \src "libresoc.v:149541.3-149561.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:147650.3-147691.6" + attribute \src "libresoc.v:149488.3-149529.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:147600.18-147600.96" - wire width 64 $extend$libresoc.v:147600$7522_Y - attribute \src "libresoc.v:147602.18-147602.98" - wire width 65 $extend$libresoc.v:147602$7525_Y - attribute \src "libresoc.v:147603.17-147603.92" - wire width 5 $extend$libresoc.v:147603$7527_Y - attribute \src "libresoc.v:147600.18-147600.96" - wire width 64 $pos$libresoc.v:147600$7523_Y - attribute \src "libresoc.v:147602.18-147602.98" - wire width 65 $pos$libresoc.v:147602$7526_Y - attribute \src "libresoc.v:147603.17-147603.92" - wire width 5 $pos$libresoc.v:147603$7528_Y - attribute \src "libresoc.v:147594.18-147594.116" - wire width 3 $sub$libresoc.v:147594$7516_Y - attribute \src "libresoc.v:147595.18-147595.116" - wire width 3 $sub$libresoc.v:147595$7517_Y - attribute \src "libresoc.v:147596.18-147596.116" - wire width 3 $sub$libresoc.v:147596$7518_Y - attribute \src "libresoc.v:147597.18-147597.114" - wire $ternary$libresoc.v:147597$7519_Y - attribute \src "libresoc.v:147598.18-147598.115" - wire $ternary$libresoc.v:147598$7520_Y - attribute \src "libresoc.v:147599.18-147599.112" - wire $ternary$libresoc.v:147599$7521_Y - attribute \src "libresoc.v:147601.18-147601.108" - wire width 64 $ternary$libresoc.v:147601$7524_Y + attribute \src "libresoc.v:149438.18-149438.96" + wire width 64 $extend$libresoc.v:149438$7567_Y + attribute \src "libresoc.v:149440.18-149440.98" + wire width 65 $extend$libresoc.v:149440$7570_Y + attribute \src "libresoc.v:149441.17-149441.92" + wire width 5 $extend$libresoc.v:149441$7572_Y + attribute \src "libresoc.v:149438.18-149438.96" + wire width 64 $pos$libresoc.v:149438$7568_Y + attribute \src "libresoc.v:149440.18-149440.98" + wire width 65 $pos$libresoc.v:149440$7571_Y + attribute \src "libresoc.v:149441.17-149441.92" + wire width 5 $pos$libresoc.v:149441$7573_Y + attribute \src "libresoc.v:149432.18-149432.116" + wire width 3 $sub$libresoc.v:149432$7561_Y + attribute \src "libresoc.v:149433.18-149433.116" + wire width 3 $sub$libresoc.v:149433$7562_Y + attribute \src "libresoc.v:149434.18-149434.116" + wire width 3 $sub$libresoc.v:149434$7563_Y + attribute \src "libresoc.v:149435.18-149435.114" + wire $ternary$libresoc.v:149435$7564_Y + attribute \src "libresoc.v:149436.18-149436.115" + wire $ternary$libresoc.v:149436$7565_Y + attribute \src "libresoc.v:149437.18-149437.112" + wire $ternary$libresoc.v:149437$7566_Y + attribute \src "libresoc.v:149439.18-149439.108" + wire width 64 $ternary$libresoc.v:149439$7569_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -310225,37 +312754,39 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 9 \cr_c attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \cr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 12 \cr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 12 \cr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -310334,6 +312865,7 @@ module \main$9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \cr_op__insn_type attribute \enum_base_type "MicrOp" @@ -310410,6 +312942,7 @@ module \main$9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 11 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -310418,7 +312951,7 @@ module \main$9 wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \full_cr_ok - attribute \src "libresoc.v:147327.7-147327.15" + attribute \src "libresoc.v:149161.7-149161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut @@ -310435,55 +312968,55 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:147600$7522 + cell $pos $extend$libresoc.v:149438$7567 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:147600$7522_Y + connect \Y $extend$libresoc.v:149438$7567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:147602$7525 + cell $pos $extend$libresoc.v:149440$7570 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:147602$7525_Y + connect \Y $extend$libresoc.v:149440$7570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:147603$7527 + cell $pos $extend$libresoc.v:149441$7572 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:147603$7527_Y + connect \Y $extend$libresoc.v:149441$7572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:147600$7523 + cell $pos $pos$libresoc.v:149438$7568 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147600$7522_Y - connect \Y $pos$libresoc.v:147600$7523_Y + connect \A $extend$libresoc.v:149438$7567_Y + connect \Y $pos$libresoc.v:149438$7568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:147602$7526 + cell $pos $pos$libresoc.v:149440$7571 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:147602$7525_Y - connect \Y $pos$libresoc.v:147602$7526_Y + connect \A $extend$libresoc.v:149440$7570_Y + connect \Y $pos$libresoc.v:149440$7571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:147603$7528 + cell $pos $pos$libresoc.v:149441$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:147603$7527_Y - connect \Y $pos$libresoc.v:147603$7528_Y + connect \A $extend$libresoc.v:149441$7572_Y + connect \Y $pos$libresoc.v:149441$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:147594$7516 + cell $sub $sub$libresoc.v:149432$7561 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -310491,10 +313024,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:147594$7516_Y + connect \Y $sub$libresoc.v:149432$7561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:147595$7517 + cell $sub $sub$libresoc.v:149433$7562 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -310502,10 +313035,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:147595$7517_Y + connect \Y $sub$libresoc.v:149433$7562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:147596$7518 + cell $sub $sub$libresoc.v:149434$7563 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -310513,59 +313046,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:147596$7518_Y + connect \Y $sub$libresoc.v:149434$7563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:147597$7519 + cell $mux $ternary$libresoc.v:149435$7564 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:147597$7519_Y + connect \Y $ternary$libresoc.v:149435$7564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:147598$7520 + cell $mux $ternary$libresoc.v:149436$7565 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:147598$7520_Y + connect \Y $ternary$libresoc.v:149436$7565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:147599$7521 + cell $mux $ternary$libresoc.v:149437$7566 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:147599$7521_Y + connect \Y $ternary$libresoc.v:149437$7566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:147601$7524 + cell $mux $ternary$libresoc.v:149439$7569 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:147601$7524_Y + connect \Y $ternary$libresoc.v:149439$7569_Y end - attribute \src "libresoc.v:147327.7-147327.20" - process $proc$libresoc.v:147327$7547 + attribute \src "libresoc.v:149161.7-149161.20" + process $proc$libresoc.v:149161$7592 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147604.3-147638.6" - process $proc$libresoc.v:147604$7529 + attribute \src "libresoc.v:149442.3-149476.6" + process $proc$libresoc.v:149442$7574 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$7530 $1\cr_a$6[3:0]$7531 - attribute \src "libresoc.v:147605.5-147605.29" + assign $0\cr_a$6[3:0]$7575 $1\cr_a$6[3:0]$7576 + attribute \src "libresoc.v:149443.5-149443.29" switch \initial - attribute \src "libresoc.v:147605.9-147605.17" + attribute \src "libresoc.v:149443.9-149443.17" case 1'1 case end @@ -310575,52 +313108,52 @@ module \main$9 case 7'0101010 assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7531 \$7 [3:0] + assign $1\cr_a$6[3:0]$7576 \$7 [3:0] assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7531 $2\cr_a$6[3:0]$7532 + assign $1\cr_a$6[3:0]$7576 $2\cr_a$6[3:0]$7577 assign $1\cr_a_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $2\cr_a$6[3:0]$7532 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$7532 [0] \bit_o + assign $2\cr_a$6[3:0]$7577 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7577 [0] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'01 - assign { $2\cr_a$6[3:0]$7532 [3:2] $2\cr_a$6[3:0]$7532 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$7532 [1] \bit_o + assign { $2\cr_a$6[3:0]$7577 [3:2] $2\cr_a$6[3:0]$7577 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7577 [1] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'10 - assign { $2\cr_a$6[3:0]$7532 [3] $2\cr_a$6[3:0]$7532 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$7532 [2] \bit_o + assign { $2\cr_a$6[3:0]$7577 [3] $2\cr_a$6[3:0]$7577 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7577 [2] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'-- - assign $2\cr_a$6[3:0]$7532 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$7532 [3] \bit_o + assign $2\cr_a$6[3:0]$7577 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7577 [3] \bit_o case - assign $2\cr_a$6[3:0]$7532 \cr_c + assign $2\cr_a$6[3:0]$7577 \cr_c end case assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$7531 4'0000 + assign $1\cr_a$6[3:0]$7576 4'0000 end sync always update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$7530 + update \cr_a$6 $0\cr_a$6[3:0]$7575 end - attribute \src "libresoc.v:147639.3-147649.6" - process $proc$libresoc.v:147639$7533 + attribute \src "libresoc.v:149477.3-149487.6" + process $proc$libresoc.v:149477$7578 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:147640.5-147640.29" + attribute \src "libresoc.v:149478.5-149478.29" switch \initial - attribute \src "libresoc.v:147640.9-147640.17" + attribute \src "libresoc.v:149478.9-149478.17" case 1'1 case end @@ -310636,17 +313169,17 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:147650.3-147691.6" - process $proc$libresoc.v:147650$7534 + attribute \src "libresoc.v:149488.3-149529.6" + process $proc$libresoc.v:149488$7579 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:147651.5-147651.29" + attribute \src "libresoc.v:149489.5-149489.29" switch \initial - attribute \src "libresoc.v:147651.9-147651.17" + attribute \src "libresoc.v:149489.9-149489.17" case 1'1 case end @@ -310693,14 +313226,14 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:147692.3-147702.6" - process $proc$libresoc.v:147692$7535 + attribute \src "libresoc.v:149530.3-149540.6" + process $proc$libresoc.v:149530$7580 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:147693.5-147693.29" + attribute \src "libresoc.v:149531.5-149531.29" switch \initial - attribute \src "libresoc.v:147693.9-147693.17" + attribute \src "libresoc.v:149531.9-149531.17" case 1'1 case end @@ -310716,14 +313249,14 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:147703.3-147723.6" - process $proc$libresoc.v:147703$7536 + attribute \src "libresoc.v:149541.3-149561.6" + process $proc$libresoc.v:149541$7581 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:147704.5-147704.29" + attribute \src "libresoc.v:149542.5-149542.29" switch \initial - attribute \src "libresoc.v:147704.9-147704.17" + attribute \src "libresoc.v:149542.9-149542.17" case 1'1 case end @@ -310760,14 +313293,14 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:147724.3-147734.6" - process $proc$libresoc.v:147724$7537 + attribute \src "libresoc.v:149562.3-149572.6" + process $proc$libresoc.v:149562$7582 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:147725.5-147725.29" + attribute \src "libresoc.v:149563.5-149563.29" switch \initial - attribute \src "libresoc.v:147725.9-147725.17" + attribute \src "libresoc.v:149563.9-149563.17" case 1'1 case end @@ -310783,14 +313316,14 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:147735.3-147745.6" - process $proc$libresoc.v:147735$7538 + attribute \src "libresoc.v:149573.3-149583.6" + process $proc$libresoc.v:149573$7583 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:147736.5-147736.29" + attribute \src "libresoc.v:149574.5-149574.29" switch \initial - attribute \src "libresoc.v:147736.9-147736.17" + attribute \src "libresoc.v:149574.9-149574.17" case 1'1 case end @@ -310806,14 +313339,14 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:147746.3-147756.6" - process $proc$libresoc.v:147746$7539 + attribute \src "libresoc.v:149584.3-149594.6" + process $proc$libresoc.v:149584$7584 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:147747.5-147747.29" + attribute \src "libresoc.v:149585.5-149585.29" switch \initial - attribute \src "libresoc.v:147747.9-147747.17" + attribute \src "libresoc.v:149585.9-149585.17" case 1'1 case end @@ -310829,14 +313362,14 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:147757.3-147767.6" - process $proc$libresoc.v:147757$7540 + attribute \src "libresoc.v:149595.3-149605.6" + process $proc$libresoc.v:149595$7585 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:147758.5-147758.29" + attribute \src "libresoc.v:149596.5-149596.29" switch \initial - attribute \src "libresoc.v:147758.9-147758.17" + attribute \src "libresoc.v:149596.9-149596.17" case 1'1 case end @@ -310852,14 +313385,14 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:147768.3-147788.6" - process $proc$libresoc.v:147768$7541 + attribute \src "libresoc.v:149606.3-149626.6" + process $proc$libresoc.v:149606$7586 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:147769.5-147769.29" + attribute \src "libresoc.v:149607.5-149607.29" switch \initial - attribute \src "libresoc.v:147769.9-147769.17" + attribute \src "libresoc.v:149607.9-149607.17" case 1'1 case end @@ -310896,14 +313429,14 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:147789.3-147809.6" - process $proc$libresoc.v:147789$7542 + attribute \src "libresoc.v:149627.3-149647.6" + process $proc$libresoc.v:149627$7587 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:147790.5-147790.29" + attribute \src "libresoc.v:149628.5-149628.29" switch \initial - attribute \src "libresoc.v:147790.9-147790.17" + attribute \src "libresoc.v:149628.9-149628.17" case 1'1 case end @@ -310940,14 +313473,14 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:147810.3-147820.6" - process $proc$libresoc.v:147810$7543 + attribute \src "libresoc.v:149648.3-149658.6" + process $proc$libresoc.v:149648$7588 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:147811.5-147811.29" + attribute \src "libresoc.v:149649.5-149649.29" switch \initial - attribute \src "libresoc.v:147811.9-147811.17" + attribute \src "libresoc.v:149649.9-149649.17" case 1'1 case end @@ -310963,14 +313496,14 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:147821.3-147831.6" - process $proc$libresoc.v:147821$7544 + attribute \src "libresoc.v:149659.3-149669.6" + process $proc$libresoc.v:149659$7589 assign { } { } assign { } { } - assign $0\full_cr$5[31:0]$7545 $1\full_cr$5[31:0]$7546 - attribute \src "libresoc.v:147822.5-147822.29" + assign $0\full_cr$5[31:0]$7590 $1\full_cr$5[31:0]$7591 + attribute \src "libresoc.v:149660.5-149660.29" switch \initial - attribute \src "libresoc.v:147822.9-147822.17" + attribute \src "libresoc.v:149660.9-149660.17" case 1'1 case end @@ -310979,508 +313512,508 @@ module \main$9 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } - assign $1\full_cr$5[31:0]$7546 \ra [31:0] + assign $1\full_cr$5[31:0]$7591 \ra [31:0] case - assign $1\full_cr$5[31:0]$7546 0 + assign $1\full_cr$5[31:0]$7591 0 end sync always - update \full_cr$5 $0\full_cr$5[31:0]$7545 + update \full_cr$5 $0\full_cr$5[31:0]$7590 end - connect \$10 $sub$libresoc.v:147594$7516_Y - connect \$13 $sub$libresoc.v:147595$7517_Y - connect \$16 $sub$libresoc.v:147596$7518_Y - connect \$18 $ternary$libresoc.v:147597$7519_Y - connect \$20 $ternary$libresoc.v:147598$7520_Y - connect \$22 $ternary$libresoc.v:147599$7521_Y - connect \$24 $pos$libresoc.v:147600$7523_Y - connect \$27 $ternary$libresoc.v:147601$7524_Y - connect \$26 $pos$libresoc.v:147602$7526_Y - connect \$7 $pos$libresoc.v:147603$7528_Y + connect \$10 $sub$libresoc.v:149432$7561_Y + connect \$13 $sub$libresoc.v:149433$7562_Y + connect \$16 $sub$libresoc.v:149434$7563_Y + connect \$18 $ternary$libresoc.v:149435$7564_Y + connect \$20 $ternary$libresoc.v:149436$7565_Y + connect \$22 $ternary$libresoc.v:149437$7566_Y + connect \$24 $pos$libresoc.v:149438$7568_Y + connect \$27 $ternary$libresoc.v:149439$7569_Y + connect \$26 $pos$libresoc.v:149440$7571_Y + connect \$7 $pos$libresoc.v:149441$7573_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:147841.1-148998.10" +attribute \src "libresoc.v:149679.1-150840.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:148569.3-148570.25" + attribute \src "libresoc.v:150411.3-150412.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:148567.3-148568.40" + attribute \src "libresoc.v:150409.3-150410.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:148910.3-148918.6" - wire $0\alu_l_r_alu$next[0:0]$7753 - attribute \src "libresoc.v:148495.3-148496.39" + attribute \src "libresoc.v:150752.3-150760.6" + wire $0\alu_l_r_alu$next[0:0]$7798 + attribute \src "libresoc.v:150337.3-150338.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 13 $0\alu_mul0_mul_op__fn_unit$next[12:0]$7678 - attribute \src "libresoc.v:148523.3-148524.65" - wire width 13 $0\alu_mul0_mul_op__fn_unit[12:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7679 - attribute \src "libresoc.v:148525.3-148526.79" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 + attribute \src "libresoc.v:150365.3-150366.65" + wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] + attribute \src "libresoc.v:150592.3-150624.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 + attribute \src "libresoc.v:150367.3-150368.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7680 - attribute \src "libresoc.v:148527.3-148528.75" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 + attribute \src "libresoc.v:150369.3-150370.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7681 - attribute \src "libresoc.v:148543.3-148544.59" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7726 + attribute \src "libresoc.v:150385.3-150386.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7682 - attribute \src "libresoc.v:148521.3-148522.69" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 + attribute \src "libresoc.v:150363.3-150364.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7683 - attribute \src "libresoc.v:148539.3-148540.67" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 + attribute \src "libresoc.v:150381.3-150382.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7684 - attribute \src "libresoc.v:148541.3-148542.69" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 + attribute \src "libresoc.v:150383.3-150384.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7685 - attribute \src "libresoc.v:148533.3-148534.63" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 + attribute \src "libresoc.v:150375.3-150376.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7686 - attribute \src "libresoc.v:148535.3-148536.63" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 + attribute \src "libresoc.v:150377.3-150378.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7687 - attribute \src "libresoc.v:148531.3-148532.63" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 + attribute \src "libresoc.v:150373.3-150374.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7688 - attribute \src "libresoc.v:148529.3-148530.63" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 + attribute \src "libresoc.v:150371.3-150372.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7689 - attribute \src "libresoc.v:148537.3-148538.69" + attribute \src "libresoc.v:150592.3-150624.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 + attribute \src "libresoc.v:150379.3-150380.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:148901.3-148909.6" - wire $0\alui_l_r_alui$next[0:0]$7750 - attribute \src "libresoc.v:148497.3-148498.43" + attribute \src "libresoc.v:150743.3-150751.6" + wire $0\alui_l_r_alui$next[0:0]$7795 + attribute \src "libresoc.v:150339.3-150340.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:148783.3-148804.6" - wire width 64 $0\data_r0__o$next[63:0]$7709 - attribute \src "libresoc.v:148517.3-148518.37" + attribute \src "libresoc.v:150625.3-150646.6" + wire width 64 $0\data_r0__o$next[63:0]$7754 + attribute \src "libresoc.v:150359.3-150360.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:148783.3-148804.6" - wire $0\data_r0__o_ok$next[0:0]$7710 - attribute \src "libresoc.v:148519.3-148520.43" + attribute \src "libresoc.v:150625.3-150646.6" + wire $0\data_r0__o_ok$next[0:0]$7755 + attribute \src "libresoc.v:150361.3-150362.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:148805.3-148826.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7717 - attribute \src "libresoc.v:148513.3-148514.43" + attribute \src "libresoc.v:150647.3-150668.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7762 + attribute \src "libresoc.v:150355.3-150356.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:148805.3-148826.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7718 - attribute \src "libresoc.v:148515.3-148516.49" + attribute \src "libresoc.v:150647.3-150668.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7763 + attribute \src "libresoc.v:150357.3-150358.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:148827.3-148848.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7725 - attribute \src "libresoc.v:148509.3-148510.47" + attribute \src "libresoc.v:150669.3-150690.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7770 + attribute \src "libresoc.v:150351.3-150352.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:148827.3-148848.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7726 - attribute \src "libresoc.v:148511.3-148512.53" + attribute \src "libresoc.v:150669.3-150690.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7771 + attribute \src "libresoc.v:150353.3-150354.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:148849.3-148870.6" - wire $0\data_r3__xer_so$next[0:0]$7733 - attribute \src "libresoc.v:148505.3-148506.47" + attribute \src "libresoc.v:150691.3-150712.6" + wire $0\data_r3__xer_so$next[0:0]$7778 + attribute \src "libresoc.v:150347.3-150348.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:148849.3-148870.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7734 - attribute \src "libresoc.v:148507.3-148508.53" + attribute \src "libresoc.v:150691.3-150712.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7779 + attribute \src "libresoc.v:150349.3-150350.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:148919.3-148928.6" + attribute \src "libresoc.v:150761.3-150770.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:148929.3-148938.6" + attribute \src "libresoc.v:150771.3-150780.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:148939.3-148948.6" + attribute \src "libresoc.v:150781.3-150790.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:148949.3-148958.6" + attribute \src "libresoc.v:150791.3-150800.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:147842.7-147842.20" + attribute \src "libresoc.v:149680.7-149680.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148705.3-148713.6" - wire $0\opc_l_r_opc$next[0:0]$7663 - attribute \src "libresoc.v:148553.3-148554.39" + attribute \src "libresoc.v:150547.3-150555.6" + wire $0\opc_l_r_opc$next[0:0]$7708 + attribute \src "libresoc.v:150395.3-150396.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:148696.3-148704.6" - wire $0\opc_l_s_opc$next[0:0]$7660 - attribute \src "libresoc.v:148555.3-148556.39" + attribute \src "libresoc.v:150538.3-150546.6" + wire $0\opc_l_s_opc$next[0:0]$7705 + attribute \src "libresoc.v:150397.3-150398.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:148959.3-148967.6" - wire width 4 $0\prev_wr_go$next[3:0]$7760 - attribute \src "libresoc.v:148565.3-148566.37" + attribute \src "libresoc.v:150801.3-150809.6" + wire width 4 $0\prev_wr_go$next[3:0]$7805 + attribute \src "libresoc.v:150407.3-150408.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:148650.3-148659.6" + attribute \src "libresoc.v:150492.3-150501.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:148741.3-148749.6" - wire width 4 $0\req_l_r_req$next[3:0]$7675 - attribute \src "libresoc.v:148545.3-148546.39" + attribute \src "libresoc.v:150583.3-150591.6" + wire width 4 $0\req_l_r_req$next[3:0]$7720 + attribute \src "libresoc.v:150387.3-150388.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:148732.3-148740.6" - wire width 4 $0\req_l_s_req$next[3:0]$7672 - attribute \src "libresoc.v:148547.3-148548.39" + attribute \src "libresoc.v:150574.3-150582.6" + wire width 4 $0\req_l_s_req$next[3:0]$7717 + attribute \src "libresoc.v:150389.3-150390.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:148669.3-148677.6" - wire $0\rok_l_r_rdok$next[0:0]$7651 - attribute \src "libresoc.v:148561.3-148562.41" + attribute \src "libresoc.v:150511.3-150519.6" + wire $0\rok_l_r_rdok$next[0:0]$7696 + attribute \src "libresoc.v:150403.3-150404.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:148660.3-148668.6" - wire $0\rok_l_s_rdok$next[0:0]$7648 - attribute \src "libresoc.v:148563.3-148564.41" + attribute \src "libresoc.v:150502.3-150510.6" + wire $0\rok_l_s_rdok$next[0:0]$7693 + attribute \src "libresoc.v:150405.3-150406.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:148687.3-148695.6" - wire $0\rst_l_r_rst$next[0:0]$7657 - attribute \src "libresoc.v:148557.3-148558.39" + attribute \src "libresoc.v:150529.3-150537.6" + wire $0\rst_l_r_rst$next[0:0]$7702 + attribute \src "libresoc.v:150399.3-150400.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:148678.3-148686.6" - wire $0\rst_l_s_rst$next[0:0]$7654 - attribute \src "libresoc.v:148559.3-148560.39" + attribute \src "libresoc.v:150520.3-150528.6" + wire $0\rst_l_s_rst$next[0:0]$7699 + attribute \src "libresoc.v:150401.3-150402.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:148723.3-148731.6" - wire width 3 $0\src_l_r_src$next[2:0]$7669 - attribute \src "libresoc.v:148549.3-148550.39" + attribute \src "libresoc.v:150565.3-150573.6" + wire width 3 $0\src_l_r_src$next[2:0]$7714 + attribute \src "libresoc.v:150391.3-150392.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:148714.3-148722.6" - wire width 3 $0\src_l_s_src$next[2:0]$7666 - attribute \src "libresoc.v:148551.3-148552.39" + attribute \src "libresoc.v:150556.3-150564.6" + wire width 3 $0\src_l_s_src$next[2:0]$7711 + attribute \src "libresoc.v:150393.3-150394.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:148871.3-148880.6" - wire width 64 $0\src_r0$next[63:0]$7741 - attribute \src "libresoc.v:148503.3-148504.29" + attribute \src "libresoc.v:150713.3-150722.6" + wire width 64 $0\src_r0$next[63:0]$7786 + attribute \src "libresoc.v:150345.3-150346.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:148881.3-148890.6" - wire width 64 $0\src_r1$next[63:0]$7744 - attribute \src "libresoc.v:148501.3-148502.29" + attribute \src "libresoc.v:150723.3-150732.6" + wire width 64 $0\src_r1$next[63:0]$7789 + attribute \src "libresoc.v:150343.3-150344.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:148891.3-148900.6" - wire $0\src_r2$next[0:0]$7747 - attribute \src "libresoc.v:148499.3-148500.29" + attribute \src "libresoc.v:150733.3-150742.6" + wire $0\src_r2$next[0:0]$7792 + attribute \src "libresoc.v:150341.3-150342.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:147966.7-147966.24" + attribute \src "libresoc.v:149804.7-149804.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:147976.7-147976.26" + attribute \src "libresoc.v:149814.7-149814.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:148910.3-148918.6" - wire $1\alu_l_r_alu$next[0:0]$7754 - attribute \src "libresoc.v:147984.7-147984.25" + attribute \src "libresoc.v:150752.3-150760.6" + wire $1\alu_l_r_alu$next[0:0]$7799 + attribute \src "libresoc.v:149822.7-149822.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 13 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7690 - attribute \src "libresoc.v:148006.14-148006.49" - wire width 13 $1\alu_mul0_mul_op__fn_unit[12:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7691 - attribute \src "libresoc.v:148010.14-148010.68" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 + attribute \src "libresoc.v:149845.14-149845.49" + wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] + attribute \src "libresoc.v:150592.3-150624.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 + attribute \src "libresoc.v:149849.14-149849.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7692 - attribute \src "libresoc.v:148014.7-148014.43" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 + attribute \src "libresoc.v:149853.7-149853.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7693 - attribute \src "libresoc.v:148018.14-148018.43" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7738 + attribute \src "libresoc.v:149857.14-149857.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7694 - attribute \src "libresoc.v:148096.13-148096.47" + attribute \src "libresoc.v:150592.3-150624.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 + attribute \src "libresoc.v:149936.13-149936.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7695 - attribute \src "libresoc.v:148100.7-148100.39" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 + attribute \src "libresoc.v:149940.7-149940.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7696 - attribute \src "libresoc.v:148104.7-148104.40" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 + attribute \src "libresoc.v:149944.7-149944.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7697 - attribute \src "libresoc.v:148108.7-148108.37" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 + attribute \src "libresoc.v:149948.7-149948.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7698 - attribute \src "libresoc.v:148112.7-148112.37" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 + attribute \src "libresoc.v:149952.7-149952.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7699 - attribute \src "libresoc.v:148116.7-148116.37" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 + attribute \src "libresoc.v:149956.7-149956.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7700 - attribute \src "libresoc.v:148120.7-148120.37" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 + attribute \src "libresoc.v:149960.7-149960.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7701 - attribute \src "libresoc.v:148124.7-148124.40" + attribute \src "libresoc.v:150592.3-150624.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 + attribute \src "libresoc.v:149964.7-149964.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:148901.3-148909.6" - wire $1\alui_l_r_alui$next[0:0]$7751 - attribute \src "libresoc.v:148154.7-148154.27" + attribute \src "libresoc.v:150743.3-150751.6" + wire $1\alui_l_r_alui$next[0:0]$7796 + attribute \src "libresoc.v:149994.7-149994.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:148783.3-148804.6" - wire width 64 $1\data_r0__o$next[63:0]$7711 - attribute \src "libresoc.v:148188.14-148188.47" + attribute \src "libresoc.v:150625.3-150646.6" + wire width 64 $1\data_r0__o$next[63:0]$7756 + attribute \src "libresoc.v:150028.14-150028.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:148783.3-148804.6" - wire $1\data_r0__o_ok$next[0:0]$7712 - attribute \src "libresoc.v:148192.7-148192.27" + attribute \src "libresoc.v:150625.3-150646.6" + wire $1\data_r0__o_ok$next[0:0]$7757 + attribute \src "libresoc.v:150032.7-150032.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:148805.3-148826.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$7719 - attribute \src "libresoc.v:148196.13-148196.33" + attribute \src "libresoc.v:150647.3-150668.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7764 + attribute \src "libresoc.v:150036.13-150036.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:148805.3-148826.6" - wire $1\data_r1__cr_a_ok$next[0:0]$7720 - attribute \src "libresoc.v:148200.7-148200.30" + attribute \src "libresoc.v:150647.3-150668.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7765 + attribute \src "libresoc.v:150040.7-150040.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:148827.3-148848.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$7727 - attribute \src "libresoc.v:148204.13-148204.35" + attribute \src "libresoc.v:150669.3-150690.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7772 + attribute \src "libresoc.v:150044.13-150044.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:148827.3-148848.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$7728 - attribute \src "libresoc.v:148208.7-148208.32" + attribute \src "libresoc.v:150669.3-150690.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7773 + attribute \src "libresoc.v:150048.7-150048.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:148849.3-148870.6" - wire $1\data_r3__xer_so$next[0:0]$7735 - attribute \src "libresoc.v:148212.7-148212.29" + attribute \src "libresoc.v:150691.3-150712.6" + wire $1\data_r3__xer_so$next[0:0]$7780 + attribute \src "libresoc.v:150052.7-150052.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:148849.3-148870.6" - wire $1\data_r3__xer_so_ok$next[0:0]$7736 - attribute \src "libresoc.v:148216.7-148216.32" + attribute \src "libresoc.v:150691.3-150712.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7781 + attribute \src "libresoc.v:150056.7-150056.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:148919.3-148928.6" + attribute \src "libresoc.v:150761.3-150770.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:148929.3-148938.6" + attribute \src "libresoc.v:150771.3-150780.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:148939.3-148948.6" + attribute \src "libresoc.v:150781.3-150790.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:148949.3-148958.6" + attribute \src "libresoc.v:150791.3-150800.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:148705.3-148713.6" - wire $1\opc_l_r_opc$next[0:0]$7664 - attribute \src "libresoc.v:148236.7-148236.25" + attribute \src "libresoc.v:150547.3-150555.6" + wire $1\opc_l_r_opc$next[0:0]$7709 + attribute \src "libresoc.v:150076.7-150076.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:148696.3-148704.6" - wire $1\opc_l_s_opc$next[0:0]$7661 - attribute \src "libresoc.v:148240.7-148240.25" + attribute \src "libresoc.v:150538.3-150546.6" + wire $1\opc_l_s_opc$next[0:0]$7706 + attribute \src "libresoc.v:150080.7-150080.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:148959.3-148967.6" - wire width 4 $1\prev_wr_go$next[3:0]$7761 - attribute \src "libresoc.v:148356.13-148356.30" + attribute \src "libresoc.v:150801.3-150809.6" + wire width 4 $1\prev_wr_go$next[3:0]$7806 + attribute \src "libresoc.v:150198.13-150198.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:148650.3-148659.6" + attribute \src "libresoc.v:150492.3-150501.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:148741.3-148749.6" - wire width 4 $1\req_l_r_req$next[3:0]$7676 - attribute \src "libresoc.v:148364.13-148364.31" + attribute \src "libresoc.v:150583.3-150591.6" + wire width 4 $1\req_l_r_req$next[3:0]$7721 + attribute \src "libresoc.v:150206.13-150206.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:148732.3-148740.6" - wire width 4 $1\req_l_s_req$next[3:0]$7673 - attribute \src "libresoc.v:148368.13-148368.31" + attribute \src "libresoc.v:150574.3-150582.6" + wire width 4 $1\req_l_s_req$next[3:0]$7718 + attribute \src "libresoc.v:150210.13-150210.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:148669.3-148677.6" - wire $1\rok_l_r_rdok$next[0:0]$7652 - attribute \src "libresoc.v:148380.7-148380.26" + attribute \src "libresoc.v:150511.3-150519.6" + wire $1\rok_l_r_rdok$next[0:0]$7697 + attribute \src "libresoc.v:150222.7-150222.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:148660.3-148668.6" - wire $1\rok_l_s_rdok$next[0:0]$7649 - attribute \src "libresoc.v:148384.7-148384.26" + attribute \src "libresoc.v:150502.3-150510.6" + wire $1\rok_l_s_rdok$next[0:0]$7694 + attribute \src "libresoc.v:150226.7-150226.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:148687.3-148695.6" - wire $1\rst_l_r_rst$next[0:0]$7658 - attribute \src "libresoc.v:148388.7-148388.25" + attribute \src "libresoc.v:150529.3-150537.6" + wire $1\rst_l_r_rst$next[0:0]$7703 + attribute \src "libresoc.v:150230.7-150230.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:148678.3-148686.6" - wire $1\rst_l_s_rst$next[0:0]$7655 - attribute \src "libresoc.v:148392.7-148392.25" + attribute \src "libresoc.v:150520.3-150528.6" + wire $1\rst_l_s_rst$next[0:0]$7700 + attribute \src "libresoc.v:150234.7-150234.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:148723.3-148731.6" - wire width 3 $1\src_l_r_src$next[2:0]$7670 - attribute \src "libresoc.v:148406.13-148406.31" + attribute \src "libresoc.v:150565.3-150573.6" + wire width 3 $1\src_l_r_src$next[2:0]$7715 + attribute \src "libresoc.v:150248.13-150248.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:148714.3-148722.6" - wire width 3 $1\src_l_s_src$next[2:0]$7667 - attribute \src "libresoc.v:148410.13-148410.31" + attribute \src "libresoc.v:150556.3-150564.6" + wire width 3 $1\src_l_s_src$next[2:0]$7712 + attribute \src "libresoc.v:150252.13-150252.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:148871.3-148880.6" - wire width 64 $1\src_r0$next[63:0]$7742 - attribute \src "libresoc.v:148416.14-148416.43" + attribute \src "libresoc.v:150713.3-150722.6" + wire width 64 $1\src_r0$next[63:0]$7787 + attribute \src "libresoc.v:150258.14-150258.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:148881.3-148890.6" - wire width 64 $1\src_r1$next[63:0]$7745 - attribute \src "libresoc.v:148420.14-148420.43" + attribute \src "libresoc.v:150723.3-150732.6" + wire width 64 $1\src_r1$next[63:0]$7790 + attribute \src "libresoc.v:150262.14-150262.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:148891.3-148900.6" - wire $1\src_r2$next[0:0]$7748 - attribute \src "libresoc.v:148424.7-148424.20" + attribute \src "libresoc.v:150733.3-150742.6" + wire $1\src_r2$next[0:0]$7793 + attribute \src "libresoc.v:150266.7-150266.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:148750.3-148782.6" - wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7702 - attribute \src "libresoc.v:148750.3-148782.6" - wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7703 - attribute \src "libresoc.v:148750.3-148782.6" - wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7704 - attribute \src "libresoc.v:148750.3-148782.6" - wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7705 - attribute \src "libresoc.v:148750.3-148782.6" - wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7706 - attribute \src "libresoc.v:148750.3-148782.6" - wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7707 - attribute \src "libresoc.v:148783.3-148804.6" - wire width 64 $2\data_r0__o$next[63:0]$7713 - attribute \src "libresoc.v:148783.3-148804.6" - wire $2\data_r0__o_ok$next[0:0]$7714 - attribute \src "libresoc.v:148805.3-148826.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$7721 - attribute \src "libresoc.v:148805.3-148826.6" - wire $2\data_r1__cr_a_ok$next[0:0]$7722 - attribute \src "libresoc.v:148827.3-148848.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$7729 - attribute \src "libresoc.v:148827.3-148848.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$7730 - attribute \src "libresoc.v:148849.3-148870.6" - wire $2\data_r3__xer_so$next[0:0]$7737 - attribute \src "libresoc.v:148849.3-148870.6" - wire $2\data_r3__xer_so_ok$next[0:0]$7738 - attribute \src "libresoc.v:148783.3-148804.6" - wire $3\data_r0__o_ok$next[0:0]$7715 - attribute \src "libresoc.v:148805.3-148826.6" - wire $3\data_r1__cr_a_ok$next[0:0]$7723 - attribute \src "libresoc.v:148827.3-148848.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$7731 - attribute \src "libresoc.v:148849.3-148870.6" - wire $3\data_r3__xer_so_ok$next[0:0]$7739 - attribute \src "libresoc.v:148435.19-148435.113" - wire width 3 $and$libresoc.v:148435$7548_Y - attribute \src "libresoc.v:148436.19-148436.125" - wire $and$libresoc.v:148436$7549_Y - attribute \src "libresoc.v:148437.19-148437.125" - wire $and$libresoc.v:148437$7550_Y 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$and$libresoc.v:150288$7604_Y + attribute \src "libresoc.v:150290.18-150290.98" + wire $and$libresoc.v:150290$7606_Y + attribute \src "libresoc.v:150292.18-150292.100" + wire $and$libresoc.v:150292$7608_Y + attribute \src "libresoc.v:150293.18-150293.160" + wire width 4 $and$libresoc.v:150293$7609_Y + attribute \src "libresoc.v:150295.18-150295.119" + wire width 4 $and$libresoc.v:150295$7611_Y + attribute \src "libresoc.v:150298.17-150298.123" + wire $and$libresoc.v:150298$7614_Y + attribute \src "libresoc.v:150299.18-150299.116" + wire $and$libresoc.v:150299$7615_Y + attribute \src "libresoc.v:150304.18-150304.113" + wire $and$libresoc.v:150304$7620_Y + attribute \src "libresoc.v:150305.18-150305.125" + wire width 4 $and$libresoc.v:150305$7621_Y + attribute \src "libresoc.v:150307.18-150307.112" + wire $and$libresoc.v:150307$7623_Y + attribute \src "libresoc.v:150309.18-150309.126" + wire $and$libresoc.v:150309$7625_Y + attribute \src "libresoc.v:150310.18-150310.126" + wire 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$and$libresoc.v:150335$7651_Y + attribute \src "libresoc.v:150306.18-150306.113" + wire $eq$libresoc.v:150306$7622_Y + attribute \src "libresoc.v:150308.18-150308.119" + wire $eq$libresoc.v:150308$7624_Y + attribute \src "libresoc.v:150289.18-150289.97" + wire $not$libresoc.v:150289$7605_Y + attribute \src "libresoc.v:150291.18-150291.99" + wire $not$libresoc.v:150291$7607_Y + attribute \src "libresoc.v:150294.18-150294.113" + wire width 4 $not$libresoc.v:150294$7610_Y + attribute \src "libresoc.v:150297.18-150297.106" + wire $not$libresoc.v:150297$7613_Y + attribute \src "libresoc.v:150303.18-150303.120" + wire $not$libresoc.v:150303$7619_Y + attribute \src "libresoc.v:150314.17-150314.113" + wire width 3 $not$libresoc.v:150314$7630_Y + attribute \src "libresoc.v:150334.18-150334.131" + wire $not$libresoc.v:150334$7650_Y + attribute \src "libresoc.v:150336.18-150336.114" + wire width 3 $not$libresoc.v:150336$7652_Y + attribute \src "libresoc.v:150302.18-150302.112" + wire $or$libresoc.v:150302$7618_Y + attribute \src "libresoc.v:150312.18-150312.122" + wire $or$libresoc.v:150312$7628_Y + attribute \src "libresoc.v:150313.18-150313.124" + wire $or$libresoc.v:150313$7629_Y + attribute \src "libresoc.v:150315.18-150315.168" + wire width 4 $or$libresoc.v:150315$7631_Y + attribute \src "libresoc.v:150316.18-150316.155" + wire width 3 $or$libresoc.v:150316$7632_Y + attribute \src "libresoc.v:150319.18-150319.120" + wire width 4 $or$libresoc.v:150319$7635_Y + attribute \src "libresoc.v:150325.17-150325.117" + wire width 3 $or$libresoc.v:150325$7641_Y + attribute \src "libresoc.v:150331.17-150331.104" + wire $reduce_and$libresoc.v:150331$7647_Y + attribute \src "libresoc.v:150296.18-150296.106" + wire $reduce_or$libresoc.v:150296$7612_Y + attribute \src "libresoc.v:150300.18-150300.113" + wire $reduce_or$libresoc.v:150300$7616_Y + attribute \src "libresoc.v:150301.18-150301.112" + wire $reduce_or$libresoc.v:150301$7617_Y + attribute \src "libresoc.v:150324.18-150324.160" + wire $ternary$libresoc.v:150324$7640_Y + attribute \src "libresoc.v:150326.18-150326.172" + wire width 64 $ternary$libresoc.v:150326$7642_Y + attribute \src "libresoc.v:150327.18-150327.118" + wire width 64 $ternary$libresoc.v:150327$7643_Y + attribute \src "libresoc.v:150328.18-150328.115" + wire width 64 $ternary$libresoc.v:150328$7644_Y + attribute \src "libresoc.v:150329.18-150329.118" + wire $ternary$libresoc.v:150329$7645_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -311630,23 +314163,24 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_mul0_cr_a attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_mul0_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_mul0_mul_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_mul0_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_mul0_mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_mul0_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -311733,6 +314267,7 @@ module \mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_mul0_mul_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -311797,9 +314332,9 @@ module \mul0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \cr_a_ok @@ -311865,7 +314400,7 @@ module \mul0 wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o - attribute \src "libresoc.v:147842.7-147842.15" + attribute \src "libresoc.v:149680.7-149680.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \o_ok @@ -311880,21 +314415,22 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_mul0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -311975,6 +314511,7 @@ module \mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -312072,7 +314609,7 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:148435$7548 + cell $and $and$libresoc.v:150277$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -312080,10 +314617,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:148435$7548_Y + connect \Y $and$libresoc.v:150277$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:148436$7549 + cell $and $and$libresoc.v:150278$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312091,10 +314628,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:148436$7549_Y + connect \Y $and$libresoc.v:150278$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:148437$7550 + cell $and $and$libresoc.v:150279$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312102,10 +314639,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:148437$7550_Y + connect \Y $and$libresoc.v:150279$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:148438$7551 + cell $and $and$libresoc.v:150280$7596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312113,10 +314650,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:148438$7551_Y + connect \Y $and$libresoc.v:150280$7596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:148439$7552 + cell $and $and$libresoc.v:150281$7597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312124,10 +314661,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:148439$7552_Y + connect \Y $and$libresoc.v:150281$7597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:148440$7553 + cell $and $and$libresoc.v:150282$7598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312135,10 +314672,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:148440$7553_Y + connect \Y $and$libresoc.v:150282$7598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:148441$7554 + cell $and $and$libresoc.v:150283$7599 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312146,10 +314683,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:148441$7554_Y + connect \Y $and$libresoc.v:150283$7599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:148442$7555 + cell $and $and$libresoc.v:150284$7600 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312157,10 +314694,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:148442$7555_Y + connect \Y $and$libresoc.v:150284$7600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:148443$7556 + cell $and $and$libresoc.v:150285$7601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312168,10 +314705,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:148443$7556_Y + connect \Y $and$libresoc.v:150285$7601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:148444$7557 + cell $and $and$libresoc.v:150286$7602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312179,10 +314716,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:148444$7557_Y + connect \Y $and$libresoc.v:150286$7602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:148445$7558 + cell $and $and$libresoc.v:150287$7603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312190,10 +314727,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:148445$7558_Y + connect \Y $and$libresoc.v:150287$7603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:148446$7559 + cell $and $and$libresoc.v:150288$7604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312201,10 +314738,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:148446$7559_Y + connect \Y $and$libresoc.v:150288$7604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:148448$7561 + cell $and $and$libresoc.v:150290$7606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312212,10 +314749,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:148448$7561_Y + connect \Y $and$libresoc.v:150290$7606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:148450$7563 + cell $and $and$libresoc.v:150292$7608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312223,10 +314760,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:148450$7563_Y + connect \Y $and$libresoc.v:150292$7608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:148451$7564 + cell $and $and$libresoc.v:150293$7609 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312234,10 +314771,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:148451$7564_Y + connect \Y $and$libresoc.v:150293$7609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:148453$7566 + cell $and $and$libresoc.v:150295$7611 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312245,10 +314782,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:148453$7566_Y + connect \Y $and$libresoc.v:150295$7611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:148456$7569 + cell $and $and$libresoc.v:150298$7614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312256,10 +314793,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:148456$7569_Y + connect \Y $and$libresoc.v:150298$7614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:148457$7570 + cell $and $and$libresoc.v:150299$7615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312267,10 +314804,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:148457$7570_Y + connect \Y $and$libresoc.v:150299$7615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:148462$7575 + cell $and $and$libresoc.v:150304$7620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312278,10 +314815,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:148462$7575_Y + connect \Y $and$libresoc.v:150304$7620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:148463$7576 + cell $and $and$libresoc.v:150305$7621 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312289,10 +314826,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:148463$7576_Y + connect \Y $and$libresoc.v:150305$7621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:148465$7578 + cell $and $and$libresoc.v:150307$7623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312300,10 +314837,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:148465$7578_Y + connect \Y $and$libresoc.v:150307$7623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:148467$7580 + cell $and $and$libresoc.v:150309$7625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312311,10 +314848,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:148467$7580_Y + connect \Y $and$libresoc.v:150309$7625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:148468$7581 + cell $and $and$libresoc.v:150310$7626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312322,10 +314859,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:148468$7581_Y + connect \Y $and$libresoc.v:150310$7626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:148469$7582 + cell $and $and$libresoc.v:150311$7627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312333,10 +314870,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:148469$7582_Y + connect \Y $and$libresoc.v:150311$7627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:148475$7588 + cell $and $and$libresoc.v:150317$7633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312344,10 +314881,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:148475$7588_Y + connect \Y $and$libresoc.v:150317$7633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:148476$7589 + cell $and $and$libresoc.v:150318$7634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312355,10 +314892,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:148476$7589_Y + connect \Y $and$libresoc.v:150318$7634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:148478$7591 + cell $and $and$libresoc.v:150320$7636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312366,10 +314903,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:148478$7591_Y + connect \Y $and$libresoc.v:150320$7636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:148479$7592 + cell $and $and$libresoc.v:150321$7637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312377,10 +314914,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:148479$7592_Y + connect \Y $and$libresoc.v:150321$7637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:148480$7593 + cell $and $and$libresoc.v:150322$7638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312388,10 +314925,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:148480$7593_Y + connect \Y $and$libresoc.v:150322$7638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:148481$7594 + cell $and $and$libresoc.v:150323$7639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312399,10 +314936,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:148481$7594_Y + connect \Y $and$libresoc.v:150323$7639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:148488$7601 + cell $and $and$libresoc.v:150330$7646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312410,10 +314947,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:148488$7601_Y + connect \Y $and$libresoc.v:150330$7646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:148490$7603 + cell $and $and$libresoc.v:150332$7648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312421,10 +314958,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:148490$7603_Y + connect \Y $and$libresoc.v:150332$7648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:148491$7604 + cell $and $and$libresoc.v:150333$7649 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -312432,10 +314969,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:148491$7604_Y + connect \Y $and$libresoc.v:150333$7649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:148493$7606 + cell $and $and$libresoc.v:150335$7651 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -312443,10 +314980,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:148493$7606_Y + connect \Y $and$libresoc.v:150335$7651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:148464$7577 + cell $eq $eq$libresoc.v:150306$7622 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312454,10 +314991,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:148464$7577_Y + connect \Y $eq$libresoc.v:150306$7622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:148466$7579 + cell $eq $eq$libresoc.v:150308$7624 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312465,74 +315002,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:148466$7579_Y + connect \Y $eq$libresoc.v:150308$7624_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:148447$7560 + cell $not $not$libresoc.v:150289$7605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:148447$7560_Y + connect \Y $not$libresoc.v:150289$7605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:148449$7562 + cell $not $not$libresoc.v:150291$7607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:148449$7562_Y + connect \Y $not$libresoc.v:150291$7607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:148452$7565 + cell $not $not$libresoc.v:150294$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:148452$7565_Y + connect \Y $not$libresoc.v:150294$7610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:148455$7568 + cell $not $not$libresoc.v:150297$7613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:148455$7568_Y + connect \Y $not$libresoc.v:150297$7613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:148461$7574 + cell $not $not$libresoc.v:150303$7619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:148461$7574_Y + connect \Y $not$libresoc.v:150303$7619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:148472$7585 + cell $not $not$libresoc.v:150314$7630 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:148472$7585_Y + connect \Y $not$libresoc.v:150314$7630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:148492$7605 + cell $not $not$libresoc.v:150334$7650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:148492$7605_Y + connect \Y $not$libresoc.v:150334$7650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:148494$7607 + cell $not $not$libresoc.v:150336$7652 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:148494$7607_Y + connect \Y $not$libresoc.v:150336$7652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:148460$7573 + cell $or $or$libresoc.v:150302$7618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312540,10 +315077,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:148460$7573_Y + connect \Y $or$libresoc.v:150302$7618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:148470$7583 + cell $or $or$libresoc.v:150312$7628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312551,10 +315088,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:148470$7583_Y + connect \Y $or$libresoc.v:150312$7628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:148471$7584 + cell $or $or$libresoc.v:150313$7629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312562,10 +315099,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:148471$7584_Y + connect \Y $or$libresoc.v:150313$7629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:148473$7586 + cell $or $or$libresoc.v:150315$7631 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312573,10 +315110,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:148473$7586_Y + connect \Y $or$libresoc.v:150315$7631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:148474$7587 + cell $or $or$libresoc.v:150316$7632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -312584,10 +315121,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:148474$7587_Y + connect \Y $or$libresoc.v:150316$7632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:148477$7590 + cell $or $or$libresoc.v:150319$7635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -312595,10 +315132,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:148477$7590_Y + connect \Y $or$libresoc.v:150319$7635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:148483$7596 + cell $or $or$libresoc.v:150325$7641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -312606,82 +315143,82 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:148483$7596_Y + connect \Y $or$libresoc.v:150325$7641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:148489$7602 + cell $reduce_and $reduce_and$libresoc.v:150331$7647 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:148489$7602_Y + connect \Y $reduce_and$libresoc.v:150331$7647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:148454$7567 + cell $reduce_or $reduce_or$libresoc.v:150296$7612 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:148454$7567_Y + connect \Y $reduce_or$libresoc.v:150296$7612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:148458$7571 + cell $reduce_or $reduce_or$libresoc.v:150300$7616 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:148458$7571_Y + connect \Y $reduce_or$libresoc.v:150300$7616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:148459$7572 + cell $reduce_or $reduce_or$libresoc.v:150301$7617 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:148459$7572_Y + connect \Y $reduce_or$libresoc.v:150301$7617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:148482$7595 + cell $mux $ternary$libresoc.v:150324$7640 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:148482$7595_Y + connect \Y $ternary$libresoc.v:150324$7640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:148484$7597 + cell $mux $ternary$libresoc.v:150326$7642 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:148484$7597_Y + connect \Y $ternary$libresoc.v:150326$7642_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:148485$7598 + cell $mux $ternary$libresoc.v:150327$7643 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:148485$7598_Y + connect \Y $ternary$libresoc.v:150327$7643_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:148486$7599 + cell $mux $ternary$libresoc.v:150328$7644 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:148486$7599_Y + connect \Y $ternary$libresoc.v:150328$7644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:148487$7600 + cell $mux $ternary$libresoc.v:150329$7645 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:148487$7600_Y + connect \Y $ternary$libresoc.v:150329$7645_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:148571.15-148577.4" + attribute \src "libresoc.v:150413.15-150419.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -312690,7 +315227,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:148578.12-148608.4" + attribute \src "libresoc.v:150420.12-150450.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -312723,7 +315260,7 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:148609.16-148615.4" + attribute \src "libresoc.v:150451.16-150457.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -312732,7 +315269,7 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:148616.15-148622.4" + attribute \src "libresoc.v:150458.15-150464.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -312741,7 +315278,7 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:148623.15-148629.4" + attribute \src "libresoc.v:150465.15-150471.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -312750,7 +315287,7 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:148630.15-148636.4" + attribute \src "libresoc.v:150472.15-150478.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -312759,7 +315296,7 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:148637.15-148642.4" + attribute \src "libresoc.v:150479.15-150484.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -312767,7 +315304,7 @@ module \mul0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:148643.15-148649.4" + attribute \src "libresoc.v:150485.15-150491.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -312775,592 +315312,592 @@ module \mul0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:147842.7-147842.20" - process $proc$libresoc.v:147842$7762 + attribute \src "libresoc.v:149680.7-149680.20" + process $proc$libresoc.v:149680$7807 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147966.7-147966.24" - process $proc$libresoc.v:147966$7763 + attribute \src "libresoc.v:149804.7-149804.24" + process $proc$libresoc.v:149804$7808 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:147976.7-147976.26" - process $proc$libresoc.v:147976$7764 + attribute \src "libresoc.v:149814.7-149814.26" + process $proc$libresoc.v:149814$7809 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:147984.7-147984.25" - process $proc$libresoc.v:147984$7765 + attribute \src "libresoc.v:149822.7-149822.25" + process $proc$libresoc.v:149822$7810 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:148006.14-148006.49" - process $proc$libresoc.v:148006$7766 + attribute \src "libresoc.v:149845.14-149845.49" + process $proc$libresoc.v:149845$7811 assign { } { } - assign $1\alu_mul0_mul_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[12:0] + update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:148010.14-148010.68" - process $proc$libresoc.v:148010$7767 + attribute \src "libresoc.v:149849.14-149849.68" + process $proc$libresoc.v:149849$7812 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:148014.7-148014.43" - process $proc$libresoc.v:148014$7768 + attribute \src "libresoc.v:149853.7-149853.43" + process $proc$libresoc.v:149853$7813 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:148018.14-148018.43" - process $proc$libresoc.v:148018$7769 + attribute \src "libresoc.v:149857.14-149857.43" + process $proc$libresoc.v:149857$7814 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:148096.13-148096.47" - process $proc$libresoc.v:148096$7770 + attribute \src "libresoc.v:149936.13-149936.47" + process $proc$libresoc.v:149936$7815 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:148100.7-148100.39" - process $proc$libresoc.v:148100$7771 + attribute \src "libresoc.v:149940.7-149940.39" + process $proc$libresoc.v:149940$7816 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:148104.7-148104.40" - process $proc$libresoc.v:148104$7772 + attribute \src "libresoc.v:149944.7-149944.40" + process $proc$libresoc.v:149944$7817 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:148108.7-148108.37" - process $proc$libresoc.v:148108$7773 + attribute \src "libresoc.v:149948.7-149948.37" + process $proc$libresoc.v:149948$7818 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:148112.7-148112.37" - process $proc$libresoc.v:148112$7774 + attribute \src "libresoc.v:149952.7-149952.37" + process $proc$libresoc.v:149952$7819 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:148116.7-148116.37" - process $proc$libresoc.v:148116$7775 + attribute \src "libresoc.v:149956.7-149956.37" + process $proc$libresoc.v:149956$7820 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:148120.7-148120.37" - process $proc$libresoc.v:148120$7776 + attribute \src "libresoc.v:149960.7-149960.37" + process $proc$libresoc.v:149960$7821 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:148124.7-148124.40" - process $proc$libresoc.v:148124$7777 + attribute \src "libresoc.v:149964.7-149964.40" + process $proc$libresoc.v:149964$7822 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:148154.7-148154.27" - process $proc$libresoc.v:148154$7778 + attribute \src "libresoc.v:149994.7-149994.27" + process $proc$libresoc.v:149994$7823 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:148188.14-148188.47" - process $proc$libresoc.v:148188$7779 + attribute \src "libresoc.v:150028.14-150028.47" + process $proc$libresoc.v:150028$7824 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:148192.7-148192.27" - process $proc$libresoc.v:148192$7780 + attribute \src "libresoc.v:150032.7-150032.27" + process $proc$libresoc.v:150032$7825 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:148196.13-148196.33" - process $proc$libresoc.v:148196$7781 + attribute \src "libresoc.v:150036.13-150036.33" + process $proc$libresoc.v:150036$7826 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:148200.7-148200.30" - process $proc$libresoc.v:148200$7782 + attribute \src "libresoc.v:150040.7-150040.30" + process $proc$libresoc.v:150040$7827 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:148204.13-148204.35" - process $proc$libresoc.v:148204$7783 + attribute \src "libresoc.v:150044.13-150044.35" + process $proc$libresoc.v:150044$7828 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:148208.7-148208.32" - process $proc$libresoc.v:148208$7784 + attribute \src "libresoc.v:150048.7-150048.32" + process $proc$libresoc.v:150048$7829 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:148212.7-148212.29" - process $proc$libresoc.v:148212$7785 + attribute \src "libresoc.v:150052.7-150052.29" + process $proc$libresoc.v:150052$7830 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:148216.7-148216.32" - process $proc$libresoc.v:148216$7786 + attribute \src "libresoc.v:150056.7-150056.32" + process $proc$libresoc.v:150056$7831 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:148236.7-148236.25" - process $proc$libresoc.v:148236$7787 + attribute \src "libresoc.v:150076.7-150076.25" + process $proc$libresoc.v:150076$7832 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:148240.7-148240.25" - process $proc$libresoc.v:148240$7788 + attribute \src "libresoc.v:150080.7-150080.25" + process $proc$libresoc.v:150080$7833 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:148356.13-148356.30" - process $proc$libresoc.v:148356$7789 + attribute \src "libresoc.v:150198.13-150198.30" + process $proc$libresoc.v:150198$7834 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:148364.13-148364.31" - process $proc$libresoc.v:148364$7790 + attribute \src "libresoc.v:150206.13-150206.31" + process $proc$libresoc.v:150206$7835 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:148368.13-148368.31" - process $proc$libresoc.v:148368$7791 + attribute \src "libresoc.v:150210.13-150210.31" + process $proc$libresoc.v:150210$7836 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:148380.7-148380.26" - process $proc$libresoc.v:148380$7792 + attribute \src "libresoc.v:150222.7-150222.26" + process $proc$libresoc.v:150222$7837 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:148384.7-148384.26" - process $proc$libresoc.v:148384$7793 + attribute \src "libresoc.v:150226.7-150226.26" + process $proc$libresoc.v:150226$7838 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:148388.7-148388.25" - process $proc$libresoc.v:148388$7794 + attribute \src "libresoc.v:150230.7-150230.25" + process $proc$libresoc.v:150230$7839 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:148392.7-148392.25" - process $proc$libresoc.v:148392$7795 + attribute \src "libresoc.v:150234.7-150234.25" + process $proc$libresoc.v:150234$7840 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:148406.13-148406.31" - process $proc$libresoc.v:148406$7796 + attribute \src "libresoc.v:150248.13-150248.31" + process $proc$libresoc.v:150248$7841 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:148410.13-148410.31" - process $proc$libresoc.v:148410$7797 + attribute \src "libresoc.v:150252.13-150252.31" + process $proc$libresoc.v:150252$7842 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:148416.14-148416.43" - process $proc$libresoc.v:148416$7798 + attribute \src "libresoc.v:150258.14-150258.43" + process $proc$libresoc.v:150258$7843 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:148420.14-148420.43" - process $proc$libresoc.v:148420$7799 + attribute \src "libresoc.v:150262.14-150262.43" + process $proc$libresoc.v:150262$7844 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:148424.7-148424.20" - process $proc$libresoc.v:148424$7800 + attribute \src "libresoc.v:150266.7-150266.20" + process $proc$libresoc.v:150266$7845 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:148495.3-148496.39" - process $proc$libresoc.v:148495$7608 + attribute \src "libresoc.v:150337.3-150338.39" + process $proc$libresoc.v:150337$7653 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:148497.3-148498.43" - process $proc$libresoc.v:148497$7609 + attribute \src "libresoc.v:150339.3-150340.43" + process $proc$libresoc.v:150339$7654 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:148499.3-148500.29" - process $proc$libresoc.v:148499$7610 + attribute \src "libresoc.v:150341.3-150342.29" + process $proc$libresoc.v:150341$7655 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:148501.3-148502.29" - process $proc$libresoc.v:148501$7611 + attribute \src "libresoc.v:150343.3-150344.29" + process $proc$libresoc.v:150343$7656 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:148503.3-148504.29" - process $proc$libresoc.v:148503$7612 + attribute \src "libresoc.v:150345.3-150346.29" + process $proc$libresoc.v:150345$7657 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:148505.3-148506.47" - process $proc$libresoc.v:148505$7613 + attribute \src "libresoc.v:150347.3-150348.47" + process $proc$libresoc.v:150347$7658 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:148507.3-148508.53" - process $proc$libresoc.v:148507$7614 + attribute \src "libresoc.v:150349.3-150350.53" + process $proc$libresoc.v:150349$7659 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:148509.3-148510.47" - process $proc$libresoc.v:148509$7615 + attribute \src "libresoc.v:150351.3-150352.47" + process $proc$libresoc.v:150351$7660 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:148511.3-148512.53" - process $proc$libresoc.v:148511$7616 + attribute \src "libresoc.v:150353.3-150354.53" + process $proc$libresoc.v:150353$7661 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:148513.3-148514.43" - process $proc$libresoc.v:148513$7617 + attribute \src "libresoc.v:150355.3-150356.43" + process $proc$libresoc.v:150355$7662 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:148515.3-148516.49" - process $proc$libresoc.v:148515$7618 + attribute \src "libresoc.v:150357.3-150358.49" + process $proc$libresoc.v:150357$7663 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:148517.3-148518.37" - process $proc$libresoc.v:148517$7619 + attribute \src "libresoc.v:150359.3-150360.37" + process $proc$libresoc.v:150359$7664 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:148519.3-148520.43" - process $proc$libresoc.v:148519$7620 + attribute \src "libresoc.v:150361.3-150362.43" + process $proc$libresoc.v:150361$7665 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:148521.3-148522.69" - process $proc$libresoc.v:148521$7621 + attribute \src "libresoc.v:150363.3-150364.69" + process $proc$libresoc.v:150363$7666 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:148523.3-148524.65" - process $proc$libresoc.v:148523$7622 + attribute \src "libresoc.v:150365.3-150366.65" + process $proc$libresoc.v:150365$7667 assign { } { } - assign $0\alu_mul0_mul_op__fn_unit[12:0] \alu_mul0_mul_op__fn_unit$next + assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk - update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[12:0] + update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:148525.3-148526.79" - process $proc$libresoc.v:148525$7623 + attribute \src "libresoc.v:150367.3-150368.79" + process $proc$libresoc.v:150367$7668 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:148527.3-148528.75" - process $proc$libresoc.v:148527$7624 + attribute \src "libresoc.v:150369.3-150370.75" + process $proc$libresoc.v:150369$7669 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:148529.3-148530.63" - process $proc$libresoc.v:148529$7625 + attribute \src "libresoc.v:150371.3-150372.63" + process $proc$libresoc.v:150371$7670 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:148531.3-148532.63" - process $proc$libresoc.v:148531$7626 + attribute \src "libresoc.v:150373.3-150374.63" + process $proc$libresoc.v:150373$7671 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:148533.3-148534.63" - process $proc$libresoc.v:148533$7627 + attribute \src "libresoc.v:150375.3-150376.63" + process $proc$libresoc.v:150375$7672 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:148535.3-148536.63" - process $proc$libresoc.v:148535$7628 + attribute \src "libresoc.v:150377.3-150378.63" + process $proc$libresoc.v:150377$7673 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:148537.3-148538.69" - process $proc$libresoc.v:148537$7629 + attribute \src "libresoc.v:150379.3-150380.69" + process $proc$libresoc.v:150379$7674 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:148539.3-148540.67" - process $proc$libresoc.v:148539$7630 + attribute \src "libresoc.v:150381.3-150382.67" + process $proc$libresoc.v:150381$7675 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:148541.3-148542.69" - process $proc$libresoc.v:148541$7631 + attribute \src "libresoc.v:150383.3-150384.69" + process $proc$libresoc.v:150383$7676 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:148543.3-148544.59" - process $proc$libresoc.v:148543$7632 + attribute \src "libresoc.v:150385.3-150386.59" + process $proc$libresoc.v:150385$7677 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:148545.3-148546.39" - process $proc$libresoc.v:148545$7633 + attribute \src "libresoc.v:150387.3-150388.39" + process $proc$libresoc.v:150387$7678 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:148547.3-148548.39" - process $proc$libresoc.v:148547$7634 + attribute \src "libresoc.v:150389.3-150390.39" + process $proc$libresoc.v:150389$7679 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:148549.3-148550.39" - process $proc$libresoc.v:148549$7635 + attribute \src "libresoc.v:150391.3-150392.39" + process $proc$libresoc.v:150391$7680 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:148551.3-148552.39" - process $proc$libresoc.v:148551$7636 + attribute \src "libresoc.v:150393.3-150394.39" + process $proc$libresoc.v:150393$7681 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:148553.3-148554.39" - process $proc$libresoc.v:148553$7637 + attribute \src "libresoc.v:150395.3-150396.39" + process $proc$libresoc.v:150395$7682 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:148555.3-148556.39" - process $proc$libresoc.v:148555$7638 + attribute \src "libresoc.v:150397.3-150398.39" + process $proc$libresoc.v:150397$7683 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:148557.3-148558.39" - process $proc$libresoc.v:148557$7639 + attribute \src "libresoc.v:150399.3-150400.39" + process $proc$libresoc.v:150399$7684 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:148559.3-148560.39" - process $proc$libresoc.v:148559$7640 + attribute \src "libresoc.v:150401.3-150402.39" + process $proc$libresoc.v:150401$7685 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:148561.3-148562.41" - process $proc$libresoc.v:148561$7641 + attribute \src "libresoc.v:150403.3-150404.41" + process $proc$libresoc.v:150403$7686 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:148563.3-148564.41" - process $proc$libresoc.v:148563$7642 + attribute \src "libresoc.v:150405.3-150406.41" + process $proc$libresoc.v:150405$7687 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:148565.3-148566.37" - process $proc$libresoc.v:148565$7643 + attribute \src "libresoc.v:150407.3-150408.37" + process $proc$libresoc.v:150407$7688 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:148567.3-148568.40" - process $proc$libresoc.v:148567$7644 + attribute \src "libresoc.v:150409.3-150410.40" + process $proc$libresoc.v:150409$7689 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:148569.3-148570.25" - process $proc$libresoc.v:148569$7645 + attribute \src "libresoc.v:150411.3-150412.25" + process $proc$libresoc.v:150411$7690 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:148650.3-148659.6" - process $proc$libresoc.v:148650$7646 + attribute \src "libresoc.v:150492.3-150501.6" + process $proc$libresoc.v:150492$7691 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:148651.5-148651.29" + attribute \src "libresoc.v:150493.5-150493.29" switch \initial - attribute \src "libresoc.v:148651.9-148651.17" + attribute \src "libresoc.v:150493.9-150493.17" case 1'1 case end @@ -313376,14 +315913,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:148660.3-148668.6" - process $proc$libresoc.v:148660$7647 + attribute \src "libresoc.v:150502.3-150510.6" + process $proc$libresoc.v:150502$7692 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7648 $1\rok_l_s_rdok$next[0:0]$7649 - attribute \src "libresoc.v:148661.5-148661.29" + assign $0\rok_l_s_rdok$next[0:0]$7693 $1\rok_l_s_rdok$next[0:0]$7694 + attribute \src "libresoc.v:150503.5-150503.29" switch \initial - attribute \src "libresoc.v:148661.9-148661.17" + attribute \src "libresoc.v:150503.9-150503.17" case 1'1 case end @@ -313392,21 +315929,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7649 1'0 + assign $1\rok_l_s_rdok$next[0:0]$7694 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$7649 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$7694 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7648 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7693 end - attribute \src "libresoc.v:148669.3-148677.6" - process $proc$libresoc.v:148669$7650 + attribute \src "libresoc.v:150511.3-150519.6" + process $proc$libresoc.v:150511$7695 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7651 $1\rok_l_r_rdok$next[0:0]$7652 - attribute \src "libresoc.v:148670.5-148670.29" + assign $0\rok_l_r_rdok$next[0:0]$7696 $1\rok_l_r_rdok$next[0:0]$7697 + attribute \src "libresoc.v:150512.5-150512.29" switch \initial - attribute \src "libresoc.v:148670.9-148670.17" + attribute \src "libresoc.v:150512.9-150512.17" case 1'1 case end @@ -313415,21 +315952,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7652 1'1 + assign $1\rok_l_r_rdok$next[0:0]$7697 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$7652 \$64 + assign $1\rok_l_r_rdok$next[0:0]$7697 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7651 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7696 end - attribute \src "libresoc.v:148678.3-148686.6" - process $proc$libresoc.v:148678$7653 + attribute \src "libresoc.v:150520.3-150528.6" + process $proc$libresoc.v:150520$7698 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7654 $1\rst_l_s_rst$next[0:0]$7655 - attribute \src "libresoc.v:148679.5-148679.29" + assign $0\rst_l_s_rst$next[0:0]$7699 $1\rst_l_s_rst$next[0:0]$7700 + attribute \src "libresoc.v:150521.5-150521.29" switch \initial - attribute \src "libresoc.v:148679.9-148679.17" + attribute \src "libresoc.v:150521.9-150521.17" case 1'1 case end @@ -313438,21 +315975,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7655 1'0 + assign $1\rst_l_s_rst$next[0:0]$7700 1'0 case - assign $1\rst_l_s_rst$next[0:0]$7655 \all_rd + assign $1\rst_l_s_rst$next[0:0]$7700 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7654 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7699 end - attribute \src "libresoc.v:148687.3-148695.6" - process $proc$libresoc.v:148687$7656 + attribute \src "libresoc.v:150529.3-150537.6" + process $proc$libresoc.v:150529$7701 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7657 $1\rst_l_r_rst$next[0:0]$7658 - attribute \src "libresoc.v:148688.5-148688.29" + assign $0\rst_l_r_rst$next[0:0]$7702 $1\rst_l_r_rst$next[0:0]$7703 + attribute \src "libresoc.v:150530.5-150530.29" switch \initial - attribute \src "libresoc.v:148688.9-148688.17" + attribute \src "libresoc.v:150530.9-150530.17" case 1'1 case end @@ -313461,21 +315998,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7658 1'1 + assign $1\rst_l_r_rst$next[0:0]$7703 1'1 case - assign $1\rst_l_r_rst$next[0:0]$7658 \rst_r + assign $1\rst_l_r_rst$next[0:0]$7703 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7657 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7702 end - attribute \src "libresoc.v:148696.3-148704.6" - process $proc$libresoc.v:148696$7659 + attribute \src "libresoc.v:150538.3-150546.6" + process $proc$libresoc.v:150538$7704 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7660 $1\opc_l_s_opc$next[0:0]$7661 - attribute \src "libresoc.v:148697.5-148697.29" + assign $0\opc_l_s_opc$next[0:0]$7705 $1\opc_l_s_opc$next[0:0]$7706 + attribute \src "libresoc.v:150539.5-150539.29" switch \initial - attribute \src "libresoc.v:148697.9-148697.17" + attribute \src "libresoc.v:150539.9-150539.17" case 1'1 case end @@ -313484,21 +316021,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7661 1'0 + assign $1\opc_l_s_opc$next[0:0]$7706 1'0 case - assign $1\opc_l_s_opc$next[0:0]$7661 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$7706 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7660 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7705 end - attribute \src "libresoc.v:148705.3-148713.6" - process $proc$libresoc.v:148705$7662 + attribute \src "libresoc.v:150547.3-150555.6" + process $proc$libresoc.v:150547$7707 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7663 $1\opc_l_r_opc$next[0:0]$7664 - attribute \src "libresoc.v:148706.5-148706.29" + assign $0\opc_l_r_opc$next[0:0]$7708 $1\opc_l_r_opc$next[0:0]$7709 + attribute \src "libresoc.v:150548.5-150548.29" switch \initial - attribute \src "libresoc.v:148706.9-148706.17" + attribute \src "libresoc.v:150548.9-150548.17" case 1'1 case end @@ -313507,21 +316044,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7664 1'1 + assign $1\opc_l_r_opc$next[0:0]$7709 1'1 case - assign $1\opc_l_r_opc$next[0:0]$7664 \req_done + assign $1\opc_l_r_opc$next[0:0]$7709 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7663 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7708 end - attribute \src "libresoc.v:148714.3-148722.6" - process $proc$libresoc.v:148714$7665 + attribute \src "libresoc.v:150556.3-150564.6" + process $proc$libresoc.v:150556$7710 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$7666 $1\src_l_s_src$next[2:0]$7667 - attribute \src "libresoc.v:148715.5-148715.29" + assign $0\src_l_s_src$next[2:0]$7711 $1\src_l_s_src$next[2:0]$7712 + attribute \src "libresoc.v:150557.5-150557.29" switch \initial - attribute \src "libresoc.v:148715.9-148715.17" + attribute \src "libresoc.v:150557.9-150557.17" case 1'1 case end @@ -313530,21 +316067,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$7667 3'000 + assign $1\src_l_s_src$next[2:0]$7712 3'000 case - assign $1\src_l_s_src$next[2:0]$7667 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$7712 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7666 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7711 end - attribute \src "libresoc.v:148723.3-148731.6" - process $proc$libresoc.v:148723$7668 + attribute \src "libresoc.v:150565.3-150573.6" + process $proc$libresoc.v:150565$7713 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$7669 $1\src_l_r_src$next[2:0]$7670 - attribute \src "libresoc.v:148724.5-148724.29" + assign $0\src_l_r_src$next[2:0]$7714 $1\src_l_r_src$next[2:0]$7715 + attribute \src "libresoc.v:150566.5-150566.29" switch \initial - attribute \src "libresoc.v:148724.9-148724.17" + attribute \src "libresoc.v:150566.9-150566.17" case 1'1 case end @@ -313553,21 +316090,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$7670 3'111 + assign $1\src_l_r_src$next[2:0]$7715 3'111 case - assign $1\src_l_r_src$next[2:0]$7670 \reset_r + assign $1\src_l_r_src$next[2:0]$7715 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7669 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7714 end - attribute \src "libresoc.v:148732.3-148740.6" - process $proc$libresoc.v:148732$7671 + attribute \src "libresoc.v:150574.3-150582.6" + process $proc$libresoc.v:150574$7716 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$7672 $1\req_l_s_req$next[3:0]$7673 - attribute \src "libresoc.v:148733.5-148733.29" + assign $0\req_l_s_req$next[3:0]$7717 $1\req_l_s_req$next[3:0]$7718 + attribute \src "libresoc.v:150575.5-150575.29" switch \initial - attribute \src "libresoc.v:148733.9-148733.17" + attribute \src "libresoc.v:150575.9-150575.17" case 1'1 case end @@ -313576,21 +316113,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$7673 4'0000 + assign $1\req_l_s_req$next[3:0]$7718 4'0000 case - assign $1\req_l_s_req$next[3:0]$7673 \$66 + assign $1\req_l_s_req$next[3:0]$7718 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7672 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7717 end - attribute \src "libresoc.v:148741.3-148749.6" - process $proc$libresoc.v:148741$7674 + attribute \src "libresoc.v:150583.3-150591.6" + process $proc$libresoc.v:150583$7719 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$7675 $1\req_l_r_req$next[3:0]$7676 - attribute \src "libresoc.v:148742.5-148742.29" + assign $0\req_l_r_req$next[3:0]$7720 $1\req_l_r_req$next[3:0]$7721 + attribute \src "libresoc.v:150584.5-150584.29" switch \initial - attribute \src "libresoc.v:148742.9-148742.17" + attribute \src "libresoc.v:150584.9-150584.17" case 1'1 case end @@ -313599,15 +316136,15 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$7676 4'1111 + assign $1\req_l_r_req$next[3:0]$7721 4'1111 case - assign $1\req_l_r_req$next[3:0]$7676 \$68 + assign $1\req_l_r_req$next[3:0]$7721 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7675 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7720 end - attribute \src "libresoc.v:148750.3-148782.6" - process $proc$libresoc.v:148750$7677 + attribute \src "libresoc.v:150592.3-150624.6" + process $proc$libresoc.v:150592$7722 assign { } { } assign { } { } assign { } { } @@ -313632,27 +316169,27 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[12:0]$7678 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7690 + assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7681 $1\alu_mul0_mul_op__insn$next[31:0]$7693 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7682 $1\alu_mul0_mul_op__insn_type$next[6:0]$7694 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7683 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7695 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7684 $1\alu_mul0_mul_op__is_signed$next[0:0]$7696 + assign $0\alu_mul0_mul_op__insn$next[31:0]$7726 $1\alu_mul0_mul_op__insn$next[31:0]$7738 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7689 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7701 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7679 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7702 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7680 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7703 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7685 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7704 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7686 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7705 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7687 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7706 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7688 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7707 - attribute \src "libresoc.v:148751.5-148751.29" + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 + attribute \src "libresoc.v:150593.5-150593.29" switch \initial - attribute \src "libresoc.v:148751.9-148751.17" + attribute \src "libresoc.v:150593.9-150593.17" case 1'1 case end @@ -313672,20 +316209,20 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7693 $1\alu_mul0_mul_op__is_signed$next[0:0]$7696 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7695 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7701 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7698 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7697 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7699 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7700 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7692 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7691 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7690 $1\alu_mul0_mul_op__insn_type$next[6:0]$7694 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7738 $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } case - assign $1\alu_mul0_mul_op__fn_unit$next[12:0]$7690 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7691 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7692 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7693 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7694 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7695 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7696 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7697 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7698 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7699 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7700 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7701 \alu_mul0_mul_op__write_cr0 + assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7738 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 \alu_mul0_mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -313697,48 +316234,48 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7702 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7703 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7707 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7706 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7704 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7705 1'0 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 1'0 case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7702 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7691 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7703 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7692 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7704 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7697 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7705 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7698 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7706 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7699 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7707 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7700 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 end sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[12:0]$7678 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7679 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7680 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7681 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7682 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7683 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7684 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7685 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7686 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7687 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7688 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7689 + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7726 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 end - attribute \src "libresoc.v:148783.3-148804.6" - process $proc$libresoc.v:148783$7708 + attribute \src "libresoc.v:150625.3-150646.6" + process $proc$libresoc.v:150625$7753 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$7709 $2\data_r0__o$next[63:0]$7713 + assign $0\data_r0__o$next[63:0]$7754 $2\data_r0__o$next[63:0]$7758 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7710 $3\data_r0__o_ok$next[0:0]$7715 - attribute \src "libresoc.v:148784.5-148784.29" + assign $0\data_r0__o_ok$next[0:0]$7755 $3\data_r0__o_ok$next[0:0]$7760 + attribute \src "libresoc.v:150626.5-150626.29" switch \initial - attribute \src "libresoc.v:148784.9-148784.17" + attribute \src "libresoc.v:150626.9-150626.17" case 1'1 case end @@ -313748,10 +316285,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7712 $1\data_r0__o$next[63:0]$7711 } { \o_ok \alu_mul0_o } + assign { $1\data_r0__o_ok$next[0:0]$7757 $1\data_r0__o$next[63:0]$7756 } { \o_ok \alu_mul0_o } case - assign $1\data_r0__o$next[63:0]$7711 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7712 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$7756 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7757 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -313759,38 +316296,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7714 $2\data_r0__o$next[63:0]$7713 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$7759 $2\data_r0__o$next[63:0]$7758 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$7713 $1\data_r0__o$next[63:0]$7711 - assign $2\data_r0__o_ok$next[0:0]$7714 $1\data_r0__o_ok$next[0:0]$7712 + assign $2\data_r0__o$next[63:0]$7758 $1\data_r0__o$next[63:0]$7756 + assign $2\data_r0__o_ok$next[0:0]$7759 $1\data_r0__o_ok$next[0:0]$7757 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7715 1'0 + assign $3\data_r0__o_ok$next[0:0]$7760 1'0 case - assign $3\data_r0__o_ok$next[0:0]$7715 $2\data_r0__o_ok$next[0:0]$7714 + assign $3\data_r0__o_ok$next[0:0]$7760 $2\data_r0__o_ok$next[0:0]$7759 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7709 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7710 + update \data_r0__o$next $0\data_r0__o$next[63:0]$7754 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7755 end - attribute \src "libresoc.v:148805.3-148826.6" - process $proc$libresoc.v:148805$7716 + attribute \src "libresoc.v:150647.3-150668.6" + process $proc$libresoc.v:150647$7761 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7717 $2\data_r1__cr_a$next[3:0]$7721 + assign $0\data_r1__cr_a$next[3:0]$7762 $2\data_r1__cr_a$next[3:0]$7766 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7718 $3\data_r1__cr_a_ok$next[0:0]$7723 - attribute \src "libresoc.v:148806.5-148806.29" + assign $0\data_r1__cr_a_ok$next[0:0]$7763 $3\data_r1__cr_a_ok$next[0:0]$7768 + attribute \src "libresoc.v:150648.5-150648.29" switch \initial - attribute \src "libresoc.v:148806.9-148806.17" + attribute \src "libresoc.v:150648.9-150648.17" case 1'1 case end @@ -313800,10 +316337,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7720 $1\data_r1__cr_a$next[3:0]$7719 } { \cr_a_ok \alu_mul0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$7765 $1\data_r1__cr_a$next[3:0]$7764 } { \cr_a_ok \alu_mul0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$7719 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7720 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$7764 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7765 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -313811,38 +316348,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7722 $2\data_r1__cr_a$next[3:0]$7721 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$7767 $2\data_r1__cr_a$next[3:0]$7766 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$7721 $1\data_r1__cr_a$next[3:0]$7719 - assign $2\data_r1__cr_a_ok$next[0:0]$7722 $1\data_r1__cr_a_ok$next[0:0]$7720 + assign $2\data_r1__cr_a$next[3:0]$7766 $1\data_r1__cr_a$next[3:0]$7764 + assign $2\data_r1__cr_a_ok$next[0:0]$7767 $1\data_r1__cr_a_ok$next[0:0]$7765 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7723 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$7768 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$7723 $2\data_r1__cr_a_ok$next[0:0]$7722 + assign $3\data_r1__cr_a_ok$next[0:0]$7768 $2\data_r1__cr_a_ok$next[0:0]$7767 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7717 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7718 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7762 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7763 end - attribute \src "libresoc.v:148827.3-148848.6" - process $proc$libresoc.v:148827$7724 + attribute \src "libresoc.v:150669.3-150690.6" + process $proc$libresoc.v:150669$7769 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7725 $2\data_r2__xer_ov$next[1:0]$7729 + assign $0\data_r2__xer_ov$next[1:0]$7770 $2\data_r2__xer_ov$next[1:0]$7774 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7726 $3\data_r2__xer_ov_ok$next[0:0]$7731 - attribute \src "libresoc.v:148828.5-148828.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$7771 $3\data_r2__xer_ov_ok$next[0:0]$7776 + attribute \src "libresoc.v:150670.5-150670.29" switch \initial - attribute \src "libresoc.v:148828.9-148828.17" + attribute \src "libresoc.v:150670.9-150670.17" case 1'1 case end @@ -313852,10 +316389,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7728 $1\data_r2__xer_ov$next[1:0]$7727 } { \xer_ov_ok \alu_mul0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7773 $1\data_r2__xer_ov$next[1:0]$7772 } { \xer_ov_ok \alu_mul0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$7727 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7728 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$7772 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7773 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -313863,38 +316400,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7730 $2\data_r2__xer_ov$next[1:0]$7729 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$7775 $2\data_r2__xer_ov$next[1:0]$7774 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$7729 $1\data_r2__xer_ov$next[1:0]$7727 - assign $2\data_r2__xer_ov_ok$next[0:0]$7730 $1\data_r2__xer_ov_ok$next[0:0]$7728 + assign $2\data_r2__xer_ov$next[1:0]$7774 $1\data_r2__xer_ov$next[1:0]$7772 + assign $2\data_r2__xer_ov_ok$next[0:0]$7775 $1\data_r2__xer_ov_ok$next[0:0]$7773 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7731 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$7776 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$7731 $2\data_r2__xer_ov_ok$next[0:0]$7730 + assign $3\data_r2__xer_ov_ok$next[0:0]$7776 $2\data_r2__xer_ov_ok$next[0:0]$7775 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7725 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7726 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7770 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7771 end - attribute \src "libresoc.v:148849.3-148870.6" - process $proc$libresoc.v:148849$7732 + attribute \src "libresoc.v:150691.3-150712.6" + process $proc$libresoc.v:150691$7777 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7733 $2\data_r3__xer_so$next[0:0]$7737 + assign $0\data_r3__xer_so$next[0:0]$7778 $2\data_r3__xer_so$next[0:0]$7782 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7734 $3\data_r3__xer_so_ok$next[0:0]$7739 - attribute \src "libresoc.v:148850.5-148850.29" + assign $0\data_r3__xer_so_ok$next[0:0]$7779 $3\data_r3__xer_so_ok$next[0:0]$7784 + attribute \src "libresoc.v:150692.5-150692.29" switch \initial - attribute \src "libresoc.v:148850.9-148850.17" + attribute \src "libresoc.v:150692.9-150692.17" case 1'1 case end @@ -313904,10 +316441,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7736 $1\data_r3__xer_so$next[0:0]$7735 } { \xer_so_ok \alu_mul0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$7781 $1\data_r3__xer_so$next[0:0]$7780 } { \xer_so_ok \alu_mul0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$7735 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7736 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$7780 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7781 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -313915,32 +316452,32 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7738 $2\data_r3__xer_so$next[0:0]$7737 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$7783 $2\data_r3__xer_so$next[0:0]$7782 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$7737 $1\data_r3__xer_so$next[0:0]$7735 - assign $2\data_r3__xer_so_ok$next[0:0]$7738 $1\data_r3__xer_so_ok$next[0:0]$7736 + assign $2\data_r3__xer_so$next[0:0]$7782 $1\data_r3__xer_so$next[0:0]$7780 + assign $2\data_r3__xer_so_ok$next[0:0]$7783 $1\data_r3__xer_so_ok$next[0:0]$7781 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7739 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$7784 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$7739 $2\data_r3__xer_so_ok$next[0:0]$7738 + assign $3\data_r3__xer_so_ok$next[0:0]$7784 $2\data_r3__xer_so_ok$next[0:0]$7783 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7733 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7734 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7778 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7779 end - attribute \src "libresoc.v:148871.3-148880.6" - process $proc$libresoc.v:148871$7740 + attribute \src "libresoc.v:150713.3-150722.6" + process $proc$libresoc.v:150713$7785 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$7741 $1\src_r0$next[63:0]$7742 - attribute \src "libresoc.v:148872.5-148872.29" + assign $0\src_r0$next[63:0]$7786 $1\src_r0$next[63:0]$7787 + attribute \src "libresoc.v:150714.5-150714.29" switch \initial - attribute \src "libresoc.v:148872.9-148872.17" + attribute \src "libresoc.v:150714.9-150714.17" case 1'1 case end @@ -313949,21 +316486,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$7742 \src1_i + assign $1\src_r0$next[63:0]$7787 \src1_i case - assign $1\src_r0$next[63:0]$7742 \src_r0 + assign $1\src_r0$next[63:0]$7787 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$7741 + update \src_r0$next $0\src_r0$next[63:0]$7786 end - attribute \src "libresoc.v:148881.3-148890.6" - process $proc$libresoc.v:148881$7743 + attribute \src "libresoc.v:150723.3-150732.6" + process $proc$libresoc.v:150723$7788 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$7744 $1\src_r1$next[63:0]$7745 - attribute \src "libresoc.v:148882.5-148882.29" + assign $0\src_r1$next[63:0]$7789 $1\src_r1$next[63:0]$7790 + attribute \src "libresoc.v:150724.5-150724.29" switch \initial - attribute \src "libresoc.v:148882.9-148882.17" + attribute \src "libresoc.v:150724.9-150724.17" case 1'1 case end @@ -313972,21 +316509,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$7745 \src_or_imm + assign $1\src_r1$next[63:0]$7790 \src_or_imm case - assign $1\src_r1$next[63:0]$7745 \src_r1 + assign $1\src_r1$next[63:0]$7790 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$7744 + update \src_r1$next $0\src_r1$next[63:0]$7789 end - attribute \src "libresoc.v:148891.3-148900.6" - process $proc$libresoc.v:148891$7746 + attribute \src "libresoc.v:150733.3-150742.6" + process $proc$libresoc.v:150733$7791 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$7747 $1\src_r2$next[0:0]$7748 - attribute \src "libresoc.v:148892.5-148892.29" + assign $0\src_r2$next[0:0]$7792 $1\src_r2$next[0:0]$7793 + attribute \src "libresoc.v:150734.5-150734.29" switch \initial - attribute \src "libresoc.v:148892.9-148892.17" + attribute \src "libresoc.v:150734.9-150734.17" case 1'1 case end @@ -313995,21 +316532,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$7748 \src3_i + assign $1\src_r2$next[0:0]$7793 \src3_i case - assign $1\src_r2$next[0:0]$7748 \src_r2 + assign $1\src_r2$next[0:0]$7793 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$7747 + update \src_r2$next $0\src_r2$next[0:0]$7792 end - attribute \src "libresoc.v:148901.3-148909.6" - process $proc$libresoc.v:148901$7749 + attribute \src "libresoc.v:150743.3-150751.6" + process $proc$libresoc.v:150743$7794 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7750 $1\alui_l_r_alui$next[0:0]$7751 - attribute \src "libresoc.v:148902.5-148902.29" + assign $0\alui_l_r_alui$next[0:0]$7795 $1\alui_l_r_alui$next[0:0]$7796 + attribute \src "libresoc.v:150744.5-150744.29" switch \initial - attribute \src "libresoc.v:148902.9-148902.17" + attribute \src "libresoc.v:150744.9-150744.17" case 1'1 case end @@ -314018,21 +316555,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7751 1'1 + assign $1\alui_l_r_alui$next[0:0]$7796 1'1 case - assign $1\alui_l_r_alui$next[0:0]$7751 \$88 + assign $1\alui_l_r_alui$next[0:0]$7796 \$88 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7750 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7795 end - attribute \src "libresoc.v:148910.3-148918.6" - process $proc$libresoc.v:148910$7752 + attribute \src "libresoc.v:150752.3-150760.6" + process $proc$libresoc.v:150752$7797 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7753 $1\alu_l_r_alu$next[0:0]$7754 - attribute \src "libresoc.v:148911.5-148911.29" + assign $0\alu_l_r_alu$next[0:0]$7798 $1\alu_l_r_alu$next[0:0]$7799 + attribute \src "libresoc.v:150753.5-150753.29" switch \initial - attribute \src "libresoc.v:148911.9-148911.17" + attribute \src "libresoc.v:150753.9-150753.17" case 1'1 case end @@ -314041,21 +316578,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7754 1'1 + assign $1\alu_l_r_alu$next[0:0]$7799 1'1 case - assign $1\alu_l_r_alu$next[0:0]$7754 \$90 + assign $1\alu_l_r_alu$next[0:0]$7799 \$90 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7753 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7798 end - attribute \src "libresoc.v:148919.3-148928.6" - process $proc$libresoc.v:148919$7755 + attribute \src "libresoc.v:150761.3-150770.6" + process $proc$libresoc.v:150761$7800 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:148920.5-148920.29" + attribute \src "libresoc.v:150762.5-150762.29" switch \initial - attribute \src "libresoc.v:148920.9-148920.17" + attribute \src "libresoc.v:150762.9-150762.17" case 1'1 case end @@ -314071,14 +316608,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:148929.3-148938.6" - process $proc$libresoc.v:148929$7756 + attribute \src "libresoc.v:150771.3-150780.6" + process $proc$libresoc.v:150771$7801 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:148930.5-148930.29" + attribute \src "libresoc.v:150772.5-150772.29" switch \initial - attribute \src "libresoc.v:148930.9-148930.17" + attribute \src "libresoc.v:150772.9-150772.17" case 1'1 case end @@ -314094,14 +316631,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:148939.3-148948.6" - process $proc$libresoc.v:148939$7757 + attribute \src "libresoc.v:150781.3-150790.6" + process $proc$libresoc.v:150781$7802 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:148940.5-148940.29" + attribute \src "libresoc.v:150782.5-150782.29" switch \initial - attribute \src "libresoc.v:148940.9-148940.17" + attribute \src "libresoc.v:150782.9-150782.17" case 1'1 case end @@ -314117,14 +316654,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:148949.3-148958.6" - process $proc$libresoc.v:148949$7758 + attribute \src "libresoc.v:150791.3-150800.6" + process $proc$libresoc.v:150791$7803 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:148950.5-148950.29" + attribute \src "libresoc.v:150792.5-150792.29" switch \initial - attribute \src "libresoc.v:148950.9-148950.17" + attribute \src "libresoc.v:150792.9-150792.17" case 1'1 case end @@ -314140,14 +316677,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:148959.3-148967.6" - process $proc$libresoc.v:148959$7759 + attribute \src "libresoc.v:150801.3-150809.6" + process $proc$libresoc.v:150801$7804 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$7760 $1\prev_wr_go$next[3:0]$7761 - attribute \src "libresoc.v:148960.5-148960.29" + assign $0\prev_wr_go$next[3:0]$7805 $1\prev_wr_go$next[3:0]$7806 + attribute \src "libresoc.v:150802.5-150802.29" switch \initial - attribute \src "libresoc.v:148960.9-148960.17" + attribute \src "libresoc.v:150802.9-150802.17" case 1'1 case end @@ -314156,73 +316693,73 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$7761 4'0000 - case - assign $1\prev_wr_go$next[3:0]$7761 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7760 - end - connect \$100 $and$libresoc.v:148435$7548_Y - connect \$102 $and$libresoc.v:148436$7549_Y - connect \$104 $and$libresoc.v:148437$7550_Y - connect \$106 $and$libresoc.v:148438$7551_Y - connect \$108 $and$libresoc.v:148439$7552_Y - connect \$10 $and$libresoc.v:148440$7553_Y - connect \$110 $and$libresoc.v:148441$7554_Y - connect \$112 $and$libresoc.v:148442$7555_Y - connect \$114 $and$libresoc.v:148443$7556_Y - connect \$116 $and$libresoc.v:148444$7557_Y - connect \$118 $and$libresoc.v:148445$7558_Y - connect \$120 $and$libresoc.v:148446$7559_Y - connect \$12 $not$libresoc.v:148447$7560_Y - connect \$14 $and$libresoc.v:148448$7561_Y - connect \$16 $not$libresoc.v:148449$7562_Y - connect \$18 $and$libresoc.v:148450$7563_Y - connect \$20 $and$libresoc.v:148451$7564_Y - connect \$24 $not$libresoc.v:148452$7565_Y - connect \$26 $and$libresoc.v:148453$7566_Y - connect \$23 $reduce_or$libresoc.v:148454$7567_Y - connect \$22 $not$libresoc.v:148455$7568_Y - connect \$2 $and$libresoc.v:148456$7569_Y - connect \$30 $and$libresoc.v:148457$7570_Y - connect \$32 $reduce_or$libresoc.v:148458$7571_Y - connect \$34 $reduce_or$libresoc.v:148459$7572_Y - connect \$36 $or$libresoc.v:148460$7573_Y - connect \$38 $not$libresoc.v:148461$7574_Y - connect \$40 $and$libresoc.v:148462$7575_Y - connect \$42 $and$libresoc.v:148463$7576_Y - connect \$44 $eq$libresoc.v:148464$7577_Y - connect \$46 $and$libresoc.v:148465$7578_Y - connect \$48 $eq$libresoc.v:148466$7579_Y - connect \$50 $and$libresoc.v:148467$7580_Y - connect \$52 $and$libresoc.v:148468$7581_Y - connect \$54 $and$libresoc.v:148469$7582_Y - connect \$56 $or$libresoc.v:148470$7583_Y - connect \$58 $or$libresoc.v:148471$7584_Y - connect \$5 $not$libresoc.v:148472$7585_Y - connect \$60 $or$libresoc.v:148473$7586_Y - connect \$62 $or$libresoc.v:148474$7587_Y - connect \$64 $and$libresoc.v:148475$7588_Y - connect \$66 $and$libresoc.v:148476$7589_Y - connect \$68 $or$libresoc.v:148477$7590_Y - connect \$70 $and$libresoc.v:148478$7591_Y - connect \$72 $and$libresoc.v:148479$7592_Y - connect \$74 $and$libresoc.v:148480$7593_Y - connect \$76 $and$libresoc.v:148481$7594_Y - connect \$78 $ternary$libresoc.v:148482$7595_Y - connect \$7 $or$libresoc.v:148483$7596_Y - connect \$80 $ternary$libresoc.v:148484$7597_Y - connect \$82 $ternary$libresoc.v:148485$7598_Y - connect \$84 $ternary$libresoc.v:148486$7599_Y - connect \$86 $ternary$libresoc.v:148487$7600_Y - connect \$88 $and$libresoc.v:148488$7601_Y - connect \$4 $reduce_and$libresoc.v:148489$7602_Y - connect \$90 $and$libresoc.v:148490$7603_Y - connect \$92 $and$libresoc.v:148491$7604_Y - connect \$94 $not$libresoc.v:148492$7605_Y - connect \$96 $and$libresoc.v:148493$7606_Y - connect \$98 $not$libresoc.v:148494$7607_Y + assign $1\prev_wr_go$next[3:0]$7806 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7806 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7805 + end + connect \$100 $and$libresoc.v:150277$7593_Y + connect \$102 $and$libresoc.v:150278$7594_Y + connect \$104 $and$libresoc.v:150279$7595_Y + connect \$106 $and$libresoc.v:150280$7596_Y + connect \$108 $and$libresoc.v:150281$7597_Y + connect \$10 $and$libresoc.v:150282$7598_Y + connect \$110 $and$libresoc.v:150283$7599_Y + connect \$112 $and$libresoc.v:150284$7600_Y + connect \$114 $and$libresoc.v:150285$7601_Y + connect \$116 $and$libresoc.v:150286$7602_Y + connect \$118 $and$libresoc.v:150287$7603_Y + connect \$120 $and$libresoc.v:150288$7604_Y + connect \$12 $not$libresoc.v:150289$7605_Y + connect \$14 $and$libresoc.v:150290$7606_Y + connect \$16 $not$libresoc.v:150291$7607_Y + connect \$18 $and$libresoc.v:150292$7608_Y + connect \$20 $and$libresoc.v:150293$7609_Y + connect \$24 $not$libresoc.v:150294$7610_Y + connect \$26 $and$libresoc.v:150295$7611_Y + connect \$23 $reduce_or$libresoc.v:150296$7612_Y + connect \$22 $not$libresoc.v:150297$7613_Y + connect \$2 $and$libresoc.v:150298$7614_Y + connect \$30 $and$libresoc.v:150299$7615_Y + connect \$32 $reduce_or$libresoc.v:150300$7616_Y + connect \$34 $reduce_or$libresoc.v:150301$7617_Y + connect \$36 $or$libresoc.v:150302$7618_Y + connect \$38 $not$libresoc.v:150303$7619_Y + connect \$40 $and$libresoc.v:150304$7620_Y + connect \$42 $and$libresoc.v:150305$7621_Y + connect \$44 $eq$libresoc.v:150306$7622_Y + connect \$46 $and$libresoc.v:150307$7623_Y + connect \$48 $eq$libresoc.v:150308$7624_Y + connect \$50 $and$libresoc.v:150309$7625_Y + connect \$52 $and$libresoc.v:150310$7626_Y + connect \$54 $and$libresoc.v:150311$7627_Y + connect \$56 $or$libresoc.v:150312$7628_Y + connect \$58 $or$libresoc.v:150313$7629_Y + connect \$5 $not$libresoc.v:150314$7630_Y + connect \$60 $or$libresoc.v:150315$7631_Y + connect \$62 $or$libresoc.v:150316$7632_Y + connect \$64 $and$libresoc.v:150317$7633_Y + connect \$66 $and$libresoc.v:150318$7634_Y + connect \$68 $or$libresoc.v:150319$7635_Y + connect \$70 $and$libresoc.v:150320$7636_Y + connect \$72 $and$libresoc.v:150321$7637_Y + connect \$74 $and$libresoc.v:150322$7638_Y + connect \$76 $and$libresoc.v:150323$7639_Y + connect \$78 $ternary$libresoc.v:150324$7640_Y + connect \$7 $or$libresoc.v:150325$7641_Y + connect \$80 $ternary$libresoc.v:150326$7642_Y + connect \$82 $ternary$libresoc.v:150327$7643_Y + connect \$84 $ternary$libresoc.v:150328$7644_Y + connect \$86 $ternary$libresoc.v:150329$7645_Y + connect \$88 $and$libresoc.v:150330$7646_Y + connect \$4 $reduce_and$libresoc.v:150331$7647_Y + connect \$90 $and$libresoc.v:150332$7648_Y + connect \$92 $and$libresoc.v:150333$7649_Y + connect \$94 $not$libresoc.v:150334$7650_Y + connect \$96 $and$libresoc.v:150335$7651_Y + connect \$98 $not$libresoc.v:150336$7652_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -314254,51 +316791,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:149002.1-149331.10" +attribute \src "libresoc.v:150844.1-151177.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:149298.18-149298.116" - wire $and$libresoc.v:149298$7802_Y - attribute \src "libresoc.v:149300.18-149300.116" - wire $and$libresoc.v:149300$7804_Y - attribute \src "libresoc.v:149301.18-149301.117" - wire $and$libresoc.v:149301$7805_Y - attribute \src "libresoc.v:149302.18-149302.117" - wire $and$libresoc.v:149302$7806_Y - attribute \src "libresoc.v:149305.18-149305.95" - wire width 65 $extend$libresoc.v:149305$7809_Y - attribute \src "libresoc.v:149306.18-149306.91" - wire width 65 $extend$libresoc.v:149306$7811_Y - attribute \src "libresoc.v:149308.18-149308.95" - wire width 65 $extend$libresoc.v:149308$7814_Y - attribute \src "libresoc.v:149309.18-149309.91" - wire width 65 $extend$libresoc.v:149309$7816_Y - attribute \src "libresoc.v:149305.18-149305.95" - wire width 65 $neg$libresoc.v:149305$7810_Y - attribute \src "libresoc.v:149308.18-149308.95" - wire width 65 $neg$libresoc.v:149308$7815_Y - attribute \src "libresoc.v:149306.18-149306.91" - wire width 65 $pos$libresoc.v:149306$7812_Y - attribute \src "libresoc.v:149309.18-149309.91" - wire width 65 $pos$libresoc.v:149309$7817_Y - attribute \src "libresoc.v:149297.18-149297.125" - wire $ternary$libresoc.v:149297$7801_Y - attribute \src "libresoc.v:149299.18-149299.125" - wire $ternary$libresoc.v:149299$7803_Y - attribute \src "libresoc.v:149307.18-149307.112" - wire width 65 $ternary$libresoc.v:149307$7813_Y - attribute \src "libresoc.v:149310.18-149310.112" - wire width 65 $ternary$libresoc.v:149310$7818_Y - attribute \src "libresoc.v:149311.18-149311.116" - wire width 32 $ternary$libresoc.v:149311$7819_Y - attribute \src "libresoc.v:149312.18-149312.116" - wire width 32 $ternary$libresoc.v:149312$7820_Y - attribute \src "libresoc.v:149303.18-149303.106" - wire $xor$libresoc.v:149303$7807_Y - attribute \src "libresoc.v:149304.18-149304.110" - wire $xor$libresoc.v:149304$7808_Y + attribute \src "libresoc.v:151144.18-151144.116" + wire $and$libresoc.v:151144$7847_Y + attribute \src "libresoc.v:151146.18-151146.116" + wire $and$libresoc.v:151146$7849_Y + attribute \src "libresoc.v:151147.18-151147.117" + wire $and$libresoc.v:151147$7850_Y + attribute \src "libresoc.v:151148.18-151148.117" + wire $and$libresoc.v:151148$7851_Y + attribute \src "libresoc.v:151151.18-151151.95" + wire width 65 $extend$libresoc.v:151151$7854_Y + attribute \src "libresoc.v:151152.18-151152.91" + wire width 65 $extend$libresoc.v:151152$7856_Y + attribute \src "libresoc.v:151154.18-151154.95" + wire width 65 $extend$libresoc.v:151154$7859_Y + attribute \src "libresoc.v:151155.18-151155.91" + wire width 65 $extend$libresoc.v:151155$7861_Y + attribute \src "libresoc.v:151151.18-151151.95" + wire width 65 $neg$libresoc.v:151151$7855_Y + attribute \src "libresoc.v:151154.18-151154.95" + wire width 65 $neg$libresoc.v:151154$7860_Y + attribute \src "libresoc.v:151152.18-151152.91" + wire width 65 $pos$libresoc.v:151152$7857_Y + attribute \src "libresoc.v:151155.18-151155.91" + wire width 65 $pos$libresoc.v:151155$7862_Y + attribute \src "libresoc.v:151143.18-151143.125" + wire $ternary$libresoc.v:151143$7846_Y + attribute \src "libresoc.v:151145.18-151145.125" + wire $ternary$libresoc.v:151145$7848_Y + attribute \src "libresoc.v:151153.18-151153.112" + wire width 65 $ternary$libresoc.v:151153$7858_Y + attribute \src "libresoc.v:151156.18-151156.112" + wire width 65 $ternary$libresoc.v:151156$7863_Y + attribute \src "libresoc.v:151157.18-151157.116" + wire width 32 $ternary$libresoc.v:151157$7864_Y + attribute \src "libresoc.v:151158.18-151158.116" + wire width 32 $ternary$libresoc.v:151158$7865_Y + attribute \src "libresoc.v:151149.18-151149.106" + wire $xor$libresoc.v:151149$7852_Y + attribute \src "libresoc.v:151150.18-151150.110" + wire $xor$libresoc.v:151150$7853_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -314342,37 +316879,39 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" wire \is_32bit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 18 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -314459,6 +316998,7 @@ module \mul1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -314535,6 +317075,7 @@ module \mul1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -314594,7 +317135,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:149298$7802 + cell $and $and$libresoc.v:151144$7847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314602,10 +317143,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:149298$7802_Y + connect \Y $and$libresoc.v:151144$7847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:149300$7804 + cell $and $and$libresoc.v:151146$7849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314613,10 +317154,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:149300$7804_Y + connect \Y $and$libresoc.v:151146$7849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:149301$7805 + cell $and $and$libresoc.v:151147$7850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314624,10 +317165,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:149301$7805_Y + connect \Y $and$libresoc.v:151147$7850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:149302$7806 + cell $and $and$libresoc.v:151148$7851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314635,122 +317176,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:149302$7806_Y + connect \Y $and$libresoc.v:151148$7851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:149305$7809 + cell $pos $extend$libresoc.v:151151$7854 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:149305$7809_Y + connect \Y $extend$libresoc.v:151151$7854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:149306$7811 + cell $pos $extend$libresoc.v:151152$7856 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:149306$7811_Y + connect \Y $extend$libresoc.v:151152$7856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:149308$7814 + cell $pos $extend$libresoc.v:151154$7859 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:149308$7814_Y + connect \Y $extend$libresoc.v:151154$7859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:149309$7816 + cell $pos $extend$libresoc.v:151155$7861 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:149309$7816_Y + connect \Y $extend$libresoc.v:151155$7861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:149305$7810 + cell $neg $neg$libresoc.v:151151$7855 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149305$7809_Y - connect \Y $neg$libresoc.v:149305$7810_Y + connect \A $extend$libresoc.v:151151$7854_Y + connect \Y $neg$libresoc.v:151151$7855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:149308$7815 + cell $neg $neg$libresoc.v:151154$7860 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149308$7814_Y - connect \Y $neg$libresoc.v:149308$7815_Y + connect \A $extend$libresoc.v:151154$7859_Y + connect \Y $neg$libresoc.v:151154$7860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:149306$7812 + cell $pos $pos$libresoc.v:151152$7857 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149306$7811_Y - connect \Y $pos$libresoc.v:149306$7812_Y + connect \A $extend$libresoc.v:151152$7856_Y + connect \Y $pos$libresoc.v:151152$7857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:149309$7817 + cell $pos $pos$libresoc.v:151155$7862 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149309$7816_Y - connect \Y $pos$libresoc.v:149309$7817_Y + connect \A $extend$libresoc.v:151155$7861_Y + connect \Y $pos$libresoc.v:151155$7862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:149297$7801 + cell $mux $ternary$libresoc.v:151143$7846 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:149297$7801_Y + connect \Y $ternary$libresoc.v:151143$7846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:149299$7803 + cell $mux $ternary$libresoc.v:151145$7848 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:149299$7803_Y + connect \Y $ternary$libresoc.v:151145$7848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:149307$7813 + cell $mux $ternary$libresoc.v:151153$7858 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:149307$7813_Y + connect \Y $ternary$libresoc.v:151153$7858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:149310$7818 + cell $mux $ternary$libresoc.v:151156$7863 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:149310$7818_Y + connect \Y $ternary$libresoc.v:151156$7863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:149311$7819 + cell $mux $ternary$libresoc.v:151157$7864 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:149311$7819_Y + connect \Y $ternary$libresoc.v:151157$7864_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:149312$7820 + cell $mux $ternary$libresoc.v:151158$7865 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:149312$7820_Y + connect \Y $ternary$libresoc.v:151158$7865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:149303$7807 + cell $xor $xor$libresoc.v:151149$7852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314758,10 +317299,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:149303$7807_Y + connect \Y $xor$libresoc.v:151149$7852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:149304$7808 + cell $xor $xor$libresoc.v:151150$7853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314769,24 +317310,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:149304$7808_Y - end - connect \$17 $ternary$libresoc.v:149297$7801_Y - connect \$19 $and$libresoc.v:149298$7802_Y - connect \$21 $ternary$libresoc.v:149299$7803_Y - connect \$23 $and$libresoc.v:149300$7804_Y - connect \$25 $and$libresoc.v:149301$7805_Y - connect \$27 $and$libresoc.v:149302$7806_Y - connect \$29 $xor$libresoc.v:149303$7807_Y - connect \$31 $xor$libresoc.v:149304$7808_Y - connect \$34 $neg$libresoc.v:149305$7810_Y - connect \$36 $pos$libresoc.v:149306$7812_Y - connect \$38 $ternary$libresoc.v:149307$7813_Y - connect \$41 $neg$libresoc.v:149308$7815_Y - connect \$43 $pos$libresoc.v:149309$7817_Y - connect \$45 $ternary$libresoc.v:149310$7818_Y - connect \$47 $ternary$libresoc.v:149311$7819_Y - connect \$49 $ternary$libresoc.v:149312$7820_Y + connect \Y $xor$libresoc.v:151150$7853_Y + end + connect \$17 $ternary$libresoc.v:151143$7846_Y + connect \$19 $and$libresoc.v:151144$7847_Y + connect \$21 $ternary$libresoc.v:151145$7848_Y + connect \$23 $and$libresoc.v:151146$7849_Y + connect \$25 $and$libresoc.v:151147$7850_Y + connect \$27 $and$libresoc.v:151148$7851_Y + connect \$29 $xor$libresoc.v:151149$7852_Y + connect \$31 $xor$libresoc.v:151150$7853_Y + connect \$34 $neg$libresoc.v:151151$7855_Y + connect \$36 $pos$libresoc.v:151152$7857_Y + connect \$38 $ternary$libresoc.v:151153$7858_Y + connect \$41 $neg$libresoc.v:151154$7860_Y + connect \$43 $pos$libresoc.v:151155$7862_Y + connect \$45 $ternary$libresoc.v:151156$7863_Y + connect \$47 $ternary$libresoc.v:151157$7864_Y + connect \$49 $ternary$libresoc.v:151158$7865_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -314806,53 +317347,55 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:149335.1-149594.10" +attribute \src "libresoc.v:151181.1-151444.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:149587.18-149587.98" - wire width 129 $extend$libresoc.v:149587$7822_Y - attribute \src "libresoc.v:149586.18-149586.99" - wire width 128 $mul$libresoc.v:149586$7821_Y - attribute \src "libresoc.v:149587.18-149587.98" - wire width 129 $pos$libresoc.v:149587$7823_Y + attribute \src "libresoc.v:151437.18-151437.98" + wire width 129 $extend$libresoc.v:151437$7867_Y + attribute \src "libresoc.v:151436.18-151436.99" + wire width 128 $mul$libresoc.v:151436$7866_Y + attribute \src "libresoc.v:151437.18-151437.98" + wire width 129 $pos$libresoc.v:151437$7868_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 128 \$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 20 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -314939,6 +317482,7 @@ module \mul2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -315015,6 +317559,7 @@ module \mul2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 19 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -315068,15 +317613,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:149587$7822 + cell $pos $extend$libresoc.v:151437$7867 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:149587$7822_Y + connect \Y $extend$libresoc.v:151437$7867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:149586$7821 + cell $mul $mul$libresoc.v:151436$7866 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -315084,18 +317629,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:149586$7821_Y + connect \Y $mul$libresoc.v:151436$7866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:149587$7823 + cell $pos $pos$libresoc.v:151437$7868 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:149587$7822_Y - connect \Y $pos$libresoc.v:149587$7823_Y + connect \A $extend$libresoc.v:151437$7867_Y + connect \Y $pos$libresoc.v:151437$7868_Y end - connect \$18 $mul$libresoc.v:149586$7821_Y - connect \$17 $pos$libresoc.v:149587$7823_Y + connect \$18 $mul$libresoc.v:151436$7866_Y + connect \$17 $pos$libresoc.v:151437$7868_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -315103,65 +317648,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:149598.1-149979.10" +attribute \src "libresoc.v:151448.1-151833.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:149599.7-149599.20" + attribute \src "libresoc.v:151449.7-151449.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149932.3-149950.6" + attribute \src "libresoc.v:151786.3-151804.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:149894.3-149912.6" - wire width 64 $0\o$14[63:0]$7840 - attribute \src "libresoc.v:149913.3-149931.6" + attribute \src "libresoc.v:151748.3-151766.6" + wire width 64 $0\o$14[63:0]$7885 + attribute \src "libresoc.v:151767.3-151785.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149951.3-149961.6" + attribute \src "libresoc.v:151805.3-151815.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:149962.3-149972.6" + attribute \src "libresoc.v:151816.3-151826.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:149932.3-149950.6" + attribute \src "libresoc.v:151786.3-151804.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:149894.3-149912.6" - wire width 64 $1\o$14[63:0]$7841 - attribute \src "libresoc.v:149913.3-149931.6" + attribute \src "libresoc.v:151748.3-151766.6" + wire width 64 $1\o$14[63:0]$7886 + attribute \src "libresoc.v:151767.3-151785.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:149951.3-149961.6" + attribute \src "libresoc.v:151805.3-151815.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:149962.3-149972.6" + attribute \src "libresoc.v:151816.3-151826.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:149932.3-149950.6" + attribute \src "libresoc.v:151786.3-151804.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:149888.18-149888.104" - wire $and$libresoc.v:149888$7832_Y - attribute \src "libresoc.v:149892.18-149892.104" - wire $and$libresoc.v:149892$7836_Y - attribute \src "libresoc.v:149882.18-149882.95" - wire width 130 $extend$libresoc.v:149882$7824_Y - attribute \src "libresoc.v:149883.18-149883.90" - wire width 130 $extend$libresoc.v:149883$7826_Y - attribute \src "libresoc.v:149893.18-149893.95" - wire width 2 $extend$libresoc.v:149893$7837_Y - attribute \src "libresoc.v:149882.18-149882.95" - wire width 130 $neg$libresoc.v:149882$7825_Y - attribute \src "libresoc.v:149887.18-149887.98" - wire $not$libresoc.v:149887$7831_Y - attribute \src "libresoc.v:149891.18-149891.98" - wire $not$libresoc.v:149891$7835_Y - attribute \src "libresoc.v:149883.18-149883.90" - wire width 130 $pos$libresoc.v:149883$7827_Y - attribute \src "libresoc.v:149893.18-149893.95" - wire width 2 $pos$libresoc.v:149893$7838_Y - attribute \src "libresoc.v:149886.18-149886.106" - wire $reduce_and$libresoc.v:149886$7830_Y - attribute \src "libresoc.v:149890.18-149890.107" - wire $reduce_and$libresoc.v:149890$7834_Y - attribute \src "libresoc.v:149885.18-149885.106" - wire $reduce_or$libresoc.v:149885$7829_Y - attribute \src "libresoc.v:149889.18-149889.107" - wire $reduce_or$libresoc.v:149889$7833_Y - attribute \src "libresoc.v:149884.18-149884.114" - wire width 130 $ternary$libresoc.v:149884$7828_Y + attribute \src "libresoc.v:151742.18-151742.104" + wire $and$libresoc.v:151742$7877_Y + attribute \src "libresoc.v:151746.18-151746.104" + wire $and$libresoc.v:151746$7881_Y + attribute \src "libresoc.v:151736.18-151736.95" + wire width 130 $extend$libresoc.v:151736$7869_Y + attribute \src "libresoc.v:151737.18-151737.90" + wire width 130 $extend$libresoc.v:151737$7871_Y + attribute \src "libresoc.v:151747.18-151747.95" + wire width 2 $extend$libresoc.v:151747$7882_Y + attribute \src "libresoc.v:151736.18-151736.95" + wire width 130 $neg$libresoc.v:151736$7870_Y + attribute \src "libresoc.v:151741.18-151741.98" + wire $not$libresoc.v:151741$7876_Y + attribute \src "libresoc.v:151745.18-151745.98" + wire $not$libresoc.v:151745$7880_Y + attribute \src "libresoc.v:151737.18-151737.90" + wire width 130 $pos$libresoc.v:151737$7872_Y + attribute \src "libresoc.v:151747.18-151747.95" + wire width 2 $pos$libresoc.v:151747$7883_Y + attribute \src "libresoc.v:151740.18-151740.106" + wire $reduce_and$libresoc.v:151740$7875_Y + attribute \src "libresoc.v:151744.18-151744.107" + wire $reduce_and$libresoc.v:151744$7879_Y + attribute \src "libresoc.v:151739.18-151739.106" + wire $reduce_or$libresoc.v:151739$7874_Y + attribute \src "libresoc.v:151743.18-151743.107" + wire $reduce_or$libresoc.v:151743$7878_Y + attribute \src "libresoc.v:151738.18-151738.114" + wire width 130 $ternary$libresoc.v:151738$7873_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -315188,44 +317733,46 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:149599.7-149599.15" + attribute \src "libresoc.v:151449.7-151449.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" wire width 129 \mul_o attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 18 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -315312,6 +317859,7 @@ module \mul3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -315388,6 +317936,7 @@ module \mul3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -315443,7 +317992,7 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:149888$7832 + cell $and $and$libresoc.v:151742$7877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -315451,10 +318000,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:149888$7832_Y + connect \Y $and$libresoc.v:151742$7877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:149892$7836 + cell $and $and$libresoc.v:151746$7881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -315462,128 +318011,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:149892$7836_Y + connect \Y $and$libresoc.v:151746$7881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:149882$7824 + cell $pos $extend$libresoc.v:151736$7869 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:149882$7824_Y + connect \Y $extend$libresoc.v:151736$7869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:149883$7826 + cell $pos $extend$libresoc.v:151737$7871 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:149883$7826_Y + connect \Y $extend$libresoc.v:151737$7871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:149893$7837 + cell $pos $extend$libresoc.v:151747$7882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:149893$7837_Y + connect \Y $extend$libresoc.v:151747$7882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:149882$7825 + cell $neg $neg$libresoc.v:151736$7870 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:149882$7824_Y - connect \Y $neg$libresoc.v:149882$7825_Y + connect \A $extend$libresoc.v:151736$7869_Y + connect \Y $neg$libresoc.v:151736$7870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:149887$7831 + cell $not $not$libresoc.v:151741$7876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:149887$7831_Y + connect \Y $not$libresoc.v:151741$7876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:149891$7835 + cell $not $not$libresoc.v:151745$7880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:149891$7835_Y + connect \Y $not$libresoc.v:151745$7880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:149883$7827 + cell $pos $pos$libresoc.v:151737$7872 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:149883$7826_Y - connect \Y $pos$libresoc.v:149883$7827_Y + connect \A $extend$libresoc.v:151737$7871_Y + connect \Y $pos$libresoc.v:151737$7872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:149893$7838 + cell $pos $pos$libresoc.v:151747$7883 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:149893$7837_Y - connect \Y $pos$libresoc.v:149893$7838_Y + connect \A $extend$libresoc.v:151747$7882_Y + connect \Y $pos$libresoc.v:151747$7883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:149886$7830 + cell $reduce_and $reduce_and$libresoc.v:151740$7875 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:149886$7830_Y + connect \Y $reduce_and$libresoc.v:151740$7875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:149890$7834 + cell $reduce_and $reduce_and$libresoc.v:151744$7879 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:149890$7834_Y + connect \Y $reduce_and$libresoc.v:151744$7879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:149885$7829 + cell $reduce_or $reduce_or$libresoc.v:151739$7874 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:149885$7829_Y + connect \Y $reduce_or$libresoc.v:151739$7874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:149889$7833 + cell $reduce_or $reduce_or$libresoc.v:151743$7878 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:149889$7833_Y + connect \Y $reduce_or$libresoc.v:151743$7878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:149884$7828 + cell $mux $ternary$libresoc.v:151738$7873 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:149884$7828_Y + connect \Y $ternary$libresoc.v:151738$7873_Y end - attribute \src "libresoc.v:149599.7-149599.20" - process $proc$libresoc.v:149599$7846 + attribute \src "libresoc.v:151449.7-151449.20" + process $proc$libresoc.v:151449$7891 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149894.3-149912.6" - process $proc$libresoc.v:149894$7839 + attribute \src "libresoc.v:151748.3-151766.6" + process $proc$libresoc.v:151748$7884 assign { } { } assign { } { } - assign $0\o$14[63:0]$7840 $1\o$14[63:0]$7841 - attribute \src "libresoc.v:149895.5-149895.29" + assign $0\o$14[63:0]$7885 $1\o$14[63:0]$7886 + attribute \src "libresoc.v:151749.5-151749.29" switch \initial - attribute \src "libresoc.v:149895.9-149895.17" + attribute \src "libresoc.v:151749.9-151749.17" case 1'1 case end @@ -315592,29 +318141,29 @@ module \mul3 attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } - assign $1\o$14[63:0]$7841 { \mul_o [63:32] \mul_o [63:32] } + assign $1\o$14[63:0]$7886 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } - assign $1\o$14[63:0]$7841 \mul_o [127:64] + assign $1\o$14[63:0]$7886 \mul_o [127:64] attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } - assign $1\o$14[63:0]$7841 \mul_o [63:0] + assign $1\o$14[63:0]$7886 \mul_o [63:0] case - assign $1\o$14[63:0]$7841 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o$14[63:0]$7886 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$14 $0\o$14[63:0]$7840 + update \o$14 $0\o$14[63:0]$7885 end - attribute \src "libresoc.v:149913.3-149931.6" - process $proc$libresoc.v:149913$7842 + attribute \src "libresoc.v:151767.3-151785.6" + process $proc$libresoc.v:151767$7887 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:149914.5-149914.29" + attribute \src "libresoc.v:151768.5-151768.29" switch \initial - attribute \src "libresoc.v:149914.9-149914.17" + attribute \src "libresoc.v:151768.9-151768.17" case 1'1 case end @@ -315638,14 +318187,14 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:149932.3-149950.6" - process $proc$libresoc.v:149932$7843 + attribute \src "libresoc.v:151786.3-151804.6" + process $proc$libresoc.v:151786$7888 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:149933.5-149933.29" + attribute \src "libresoc.v:151787.5-151787.29" switch \initial - attribute \src "libresoc.v:149933.9-149933.17" + attribute \src "libresoc.v:151787.9-151787.17" case 1'1 case end @@ -315672,14 +318221,14 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:149951.3-149961.6" - process $proc$libresoc.v:149951$7844 + attribute \src "libresoc.v:151805.3-151815.6" + process $proc$libresoc.v:151805$7889 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:149952.5-149952.29" + attribute \src "libresoc.v:151806.5-151806.29" switch \initial - attribute \src "libresoc.v:149952.9-149952.17" + attribute \src "libresoc.v:151806.9-151806.17" case 1'1 case end @@ -315695,14 +318244,14 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:149962.3-149972.6" - process $proc$libresoc.v:149962$7845 + attribute \src "libresoc.v:151816.3-151826.6" + process $proc$libresoc.v:151816$7890 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:149963.5-149963.29" + attribute \src "libresoc.v:151817.5-151817.29" switch \initial - attribute \src "libresoc.v:149963.9-149963.17" + attribute \src "libresoc.v:151817.9-151817.17" case 1'1 case end @@ -315718,18 +318267,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:149882$7825_Y - connect \$19 $pos$libresoc.v:149883$7827_Y - connect \$21 $ternary$libresoc.v:149884$7828_Y - connect \$23 $reduce_or$libresoc.v:149885$7829_Y - connect \$26 $reduce_and$libresoc.v:149886$7830_Y - connect \$25 $not$libresoc.v:149887$7831_Y - connect \$29 $and$libresoc.v:149888$7832_Y - connect \$31 $reduce_or$libresoc.v:149889$7833_Y - connect \$34 $reduce_and$libresoc.v:149890$7834_Y - connect \$33 $not$libresoc.v:149891$7835_Y - connect \$37 $and$libresoc.v:149892$7836_Y - connect \$39 $pos$libresoc.v:149893$7838_Y + connect \$17 $neg$libresoc.v:151736$7870_Y + connect \$19 $pos$libresoc.v:151737$7872_Y + connect \$21 $ternary$libresoc.v:151738$7873_Y + connect \$23 $reduce_or$libresoc.v:151739$7874_Y + connect \$26 $reduce_and$libresoc.v:151740$7875_Y + connect \$25 $not$libresoc.v:151741$7876_Y + connect \$29 $and$libresoc.v:151742$7877_Y + connect \$31 $reduce_or$libresoc.v:151743$7878_Y + connect \$34 $reduce_and$libresoc.v:151744$7879_Y + connect \$33 $not$libresoc.v:151745$7880_Y + connect \$37 $and$libresoc.v:151746$7881_Y + connect \$39 $pos$libresoc.v:151747$7883_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -315737,221 +318286,223 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:149983.1-151186.10" +attribute \src "libresoc.v:151837.1-153054.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:149984.7-149984.20" + attribute \src "libresoc.v:151838.7-151838.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 13 $0\mul_op__fn_unit$next[12:0]$7875 - attribute \src "libresoc.v:150928.3-150929.47" - wire width 13 $0\mul_op__fn_unit[12:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7876 - attribute \src "libresoc.v:150930.3-150931.61" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 14 $0\mul_op__fn_unit$next[13:0]$7920 + attribute \src "libresoc.v:152796.3-152797.47" + wire width 14 $0\mul_op__fn_unit[13:0] + attribute \src "libresoc.v:152931.3-152966.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7921 + attribute \src "libresoc.v:152798.3-152799.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7877 - attribute \src "libresoc.v:150932.3-150933.57" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7922 + attribute \src "libresoc.v:152800.3-152801.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 32 $0\mul_op__insn$next[31:0]$7878 - attribute \src "libresoc.v:150948.3-150949.41" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 32 $0\mul_op__insn$next[31:0]$7923 + attribute \src "libresoc.v:152816.3-152817.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7879 - attribute \src "libresoc.v:150926.3-150927.51" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7924 + attribute \src "libresoc.v:152794.3-152795.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $0\mul_op__is_32bit$next[0:0]$7880 - attribute \src "libresoc.v:150944.3-150945.49" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__is_32bit$next[0:0]$7925 + attribute \src "libresoc.v:152812.3-152813.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $0\mul_op__is_signed$next[0:0]$7881 - attribute \src "libresoc.v:150946.3-150947.51" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__is_signed$next[0:0]$7926 + attribute \src "libresoc.v:152814.3-152815.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $0\mul_op__oe__oe$next[0:0]$7882 - attribute \src "libresoc.v:150938.3-150939.45" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__oe__oe$next[0:0]$7927 + attribute \src "libresoc.v:152806.3-152807.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $0\mul_op__oe__ok$next[0:0]$7883 - attribute \src "libresoc.v:150940.3-150941.45" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__oe__ok$next[0:0]$7928 + attribute \src "libresoc.v:152808.3-152809.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $0\mul_op__rc__ok$next[0:0]$7884 - attribute \src "libresoc.v:150936.3-150937.45" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__rc__ok$next[0:0]$7929 + attribute \src "libresoc.v:152804.3-152805.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $0\mul_op__rc__rc$next[0:0]$7885 - attribute \src "libresoc.v:150934.3-150935.45" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__rc__rc$next[0:0]$7930 + attribute \src "libresoc.v:152802.3-152803.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $0\mul_op__write_cr0$next[0:0]$7886 - attribute \src "libresoc.v:150942.3-150943.51" + attribute \src "libresoc.v:152931.3-152966.6" + wire $0\mul_op__write_cr0$next[0:0]$7931 + attribute \src "libresoc.v:152810.3-152811.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:151050.3-151062.6" - wire width 2 $0\muxid$next[1:0]$7872 - attribute \src "libresoc.v:150950.3-150951.27" + attribute \src "libresoc.v:152918.3-152930.6" + wire width 2 $0\muxid$next[1:0]$7917 + attribute \src "libresoc.v:152818.3-152819.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:151138.3-151150.6" - wire $0\neg_res$next[0:0]$7915 - attribute \src "libresoc.v:151151.3-151163.6" - wire $0\neg_res32$next[0:0]$7918 - attribute \src "libresoc.v:150916.3-150917.35" + attribute \src "libresoc.v:153006.3-153018.6" + wire $0\neg_res$next[0:0]$7960 + attribute \src "libresoc.v:153019.3-153031.6" + wire $0\neg_res32$next[0:0]$7963 + attribute \src "libresoc.v:152784.3-152785.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:150918.3-150919.31" + attribute \src "libresoc.v:152786.3-152787.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:151032.3-151049.6" - wire $0\r_busy$next[0:0]$7868 - attribute \src "libresoc.v:150952.3-150953.29" + attribute \src "libresoc.v:152900.3-152917.6" + wire $0\r_busy$next[0:0]$7913 + attribute \src "libresoc.v:152820.3-152821.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:151099.3-151111.6" - wire width 64 $0\ra$next[63:0]$7906 - attribute \src "libresoc.v:150924.3-150925.21" + attribute \src "libresoc.v:152967.3-152979.6" + wire width 64 $0\ra$next[63:0]$7951 + attribute \src "libresoc.v:152792.3-152793.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:151112.3-151124.6" - wire width 64 $0\rb$next[63:0]$7909 - attribute \src "libresoc.v:150922.3-150923.21" + attribute \src "libresoc.v:152980.3-152992.6" + wire width 64 $0\rb$next[63:0]$7954 + attribute \src "libresoc.v:152790.3-152791.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:151125.3-151137.6" - wire $0\xer_so$next[0:0]$7912 - attribute \src "libresoc.v:150920.3-150921.29" + attribute \src "libresoc.v:152993.3-153005.6" + wire $0\xer_so$next[0:0]$7957 + attribute \src "libresoc.v:152788.3-152789.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 13 $1\mul_op__fn_unit$next[12:0]$7887 - attribute \src "libresoc.v:150491.14-150491.40" - wire width 13 $1\mul_op__fn_unit[12:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7888 - attribute \src "libresoc.v:150528.14-150528.59" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 14 $1\mul_op__fn_unit$next[13:0]$7932 + attribute \src "libresoc.v:152354.14-152354.40" + wire width 14 $1\mul_op__fn_unit[13:0] + attribute \src "libresoc.v:152931.3-152966.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7933 + attribute \src "libresoc.v:152393.14-152393.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7889 - attribute \src "libresoc.v:150537.7-150537.34" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7934 + attribute \src "libresoc.v:152402.7-152402.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 32 $1\mul_op__insn$next[31:0]$7890 - attribute \src "libresoc.v:150546.14-150546.34" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 32 $1\mul_op__insn$next[31:0]$7935 + attribute \src "libresoc.v:152411.14-152411.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7891 - attribute \src "libresoc.v:150629.13-150629.38" + attribute \src "libresoc.v:152931.3-152966.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7936 + attribute \src "libresoc.v:152495.13-152495.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $1\mul_op__is_32bit$next[0:0]$7892 - attribute \src "libresoc.v:150786.7-150786.30" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__is_32bit$next[0:0]$7937 + attribute \src "libresoc.v:152654.7-152654.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $1\mul_op__is_signed$next[0:0]$7893 - attribute \src "libresoc.v:150795.7-150795.31" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__is_signed$next[0:0]$7938 + attribute \src "libresoc.v:152663.7-152663.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $1\mul_op__oe__oe$next[0:0]$7894 - attribute \src "libresoc.v:150804.7-150804.28" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__oe__oe$next[0:0]$7939 + attribute \src "libresoc.v:152672.7-152672.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $1\mul_op__oe__ok$next[0:0]$7895 - attribute \src "libresoc.v:150813.7-150813.28" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__oe__ok$next[0:0]$7940 + attribute \src "libresoc.v:152681.7-152681.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $1\mul_op__rc__ok$next[0:0]$7896 - attribute \src "libresoc.v:150822.7-150822.28" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__rc__ok$next[0:0]$7941 + attribute \src "libresoc.v:152690.7-152690.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $1\mul_op__rc__rc$next[0:0]$7897 - attribute \src "libresoc.v:150831.7-150831.28" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__rc__rc$next[0:0]$7942 + attribute \src "libresoc.v:152699.7-152699.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire $1\mul_op__write_cr0$next[0:0]$7898 - attribute \src "libresoc.v:150840.7-150840.31" + attribute \src "libresoc.v:152931.3-152966.6" + wire $1\mul_op__write_cr0$next[0:0]$7943 + attribute \src "libresoc.v:152708.7-152708.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:151050.3-151062.6" - wire width 2 $1\muxid$next[1:0]$7873 - attribute \src "libresoc.v:150849.13-150849.25" + attribute \src "libresoc.v:152918.3-152930.6" + wire width 2 $1\muxid$next[1:0]$7918 + attribute \src "libresoc.v:152717.13-152717.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:151138.3-151150.6" - wire $1\neg_res$next[0:0]$7916 - attribute \src "libresoc.v:151151.3-151163.6" - wire $1\neg_res32$next[0:0]$7919 - attribute \src "libresoc.v:150871.7-150871.23" + attribute \src "libresoc.v:153006.3-153018.6" + wire $1\neg_res$next[0:0]$7961 + attribute \src "libresoc.v:153019.3-153031.6" + wire $1\neg_res32$next[0:0]$7964 + attribute \src "libresoc.v:152739.7-152739.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:150864.7-150864.21" + attribute \src "libresoc.v:152732.7-152732.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:151032.3-151049.6" - wire $1\r_busy$next[0:0]$7869 - attribute \src "libresoc.v:150885.7-150885.20" + attribute \src "libresoc.v:152900.3-152917.6" + wire $1\r_busy$next[0:0]$7914 + attribute \src "libresoc.v:152753.7-152753.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:151099.3-151111.6" - wire width 64 $1\ra$next[63:0]$7907 - attribute \src "libresoc.v:150890.14-150890.39" + attribute \src "libresoc.v:152967.3-152979.6" + wire width 64 $1\ra$next[63:0]$7952 + attribute \src "libresoc.v:152758.14-152758.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:151112.3-151124.6" - wire width 64 $1\rb$next[63:0]$7910 - attribute \src "libresoc.v:150899.14-150899.39" + attribute \src "libresoc.v:152980.3-152992.6" + wire width 64 $1\rb$next[63:0]$7955 + attribute \src "libresoc.v:152767.14-152767.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:151125.3-151137.6" - wire $1\xer_so$next[0:0]$7913 - attribute \src "libresoc.v:150908.7-150908.20" + attribute \src "libresoc.v:152993.3-153005.6" + wire $1\xer_so$next[0:0]$7958 + attribute \src "libresoc.v:152776.7-152776.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:151063.3-151098.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7899 - attribute \src "libresoc.v:151063.3-151098.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7900 - attribute \src "libresoc.v:151063.3-151098.6" - wire $2\mul_op__oe__oe$next[0:0]$7901 - attribute \src "libresoc.v:151063.3-151098.6" - wire $2\mul_op__oe__ok$next[0:0]$7902 - attribute \src "libresoc.v:151063.3-151098.6" - wire $2\mul_op__rc__ok$next[0:0]$7903 - attribute \src "libresoc.v:151063.3-151098.6" - wire $2\mul_op__rc__rc$next[0:0]$7904 - attribute \src "libresoc.v:151032.3-151049.6" - wire $2\r_busy$next[0:0]$7870 - attribute \src "libresoc.v:150915.18-150915.118" - wire $and$libresoc.v:150915$7847_Y + attribute \src "libresoc.v:152931.3-152966.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7944 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7945 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__oe__oe$next[0:0]$7946 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__oe__ok$next[0:0]$7947 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__rc__ok$next[0:0]$7948 + attribute \src "libresoc.v:152931.3-152966.6" + wire $2\mul_op__rc__rc$next[0:0]$7949 + attribute \src "libresoc.v:152900.3-152917.6" + wire $2\r_busy$next[0:0]$7915 + attribute \src "libresoc.v:152783.18-152783.118" + wire $and$libresoc.v:152783$7892_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:149984.7-149984.15" + attribute \src "libresoc.v:151838.7-151838.15" wire \initial attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_mul_op__fn_unit$19 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_mul_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -316038,6 +318589,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -316114,6 +318666,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_mul_op__insn_type$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -316161,37 +318714,39 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so$32 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul1_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul1_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul1_mul_op__fn_unit$35 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul1_mul_op__fn_unit$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul1_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -316278,6 +318833,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul1_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -316354,6 +318910,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul1_mul_op__insn_type$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -316405,55 +318962,58 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul1_xer_so$48 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 26 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 26 \mul_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -316552,6 +319112,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -316628,6 +319189,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 25 \mul_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -316704,6 +319266,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -316827,7 +319390,7 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:150915$7847 + cell $and $and$libresoc.v:152783$7892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -316835,10 +319398,10 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:150915$7847_Y + connect \Y $and$libresoc.v:152783$7892_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:150954.14-150987.4" + attribute \src "libresoc.v:152822.14-152855.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 @@ -316874,7 +319437,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:150988.8-151023.4" + attribute \src "libresoc.v:152856.8-152891.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -316912,319 +319475,319 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:151024.10-151027.4" + attribute \src "libresoc.v:152892.10-152895.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:151028.10-151031.4" + attribute \src "libresoc.v:152896.10-152899.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:149984.7-149984.20" - process $proc$libresoc.v:149984$7920 + attribute \src "libresoc.v:151838.7-151838.20" + process $proc$libresoc.v:151838$7965 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:150491.14-150491.40" - process $proc$libresoc.v:150491$7921 + attribute \src "libresoc.v:152354.14-152354.40" + process $proc$libresoc.v:152354$7966 assign { } { } - assign $1\mul_op__fn_unit[12:0] 13'0000000000000 + assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \mul_op__fn_unit $1\mul_op__fn_unit[12:0] + update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:150528.14-150528.59" - process $proc$libresoc.v:150528$7922 + attribute \src "libresoc.v:152393.14-152393.59" + process $proc$libresoc.v:152393$7967 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:150537.7-150537.34" - process $proc$libresoc.v:150537$7923 + attribute \src "libresoc.v:152402.7-152402.34" + process $proc$libresoc.v:152402$7968 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:150546.14-150546.34" - process $proc$libresoc.v:150546$7924 + attribute \src "libresoc.v:152411.14-152411.34" + process $proc$libresoc.v:152411$7969 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:150629.13-150629.38" - process $proc$libresoc.v:150629$7925 + attribute \src "libresoc.v:152495.13-152495.38" + process $proc$libresoc.v:152495$7970 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:150786.7-150786.30" - process $proc$libresoc.v:150786$7926 + attribute \src "libresoc.v:152654.7-152654.30" + process $proc$libresoc.v:152654$7971 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:150795.7-150795.31" - process $proc$libresoc.v:150795$7927 + attribute \src "libresoc.v:152663.7-152663.31" + process $proc$libresoc.v:152663$7972 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:150804.7-150804.28" - process $proc$libresoc.v:150804$7928 + attribute \src "libresoc.v:152672.7-152672.28" + process $proc$libresoc.v:152672$7973 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:150813.7-150813.28" - process $proc$libresoc.v:150813$7929 + attribute \src "libresoc.v:152681.7-152681.28" + process $proc$libresoc.v:152681$7974 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:150822.7-150822.28" - process $proc$libresoc.v:150822$7930 + attribute \src "libresoc.v:152690.7-152690.28" + process $proc$libresoc.v:152690$7975 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:150831.7-150831.28" - process $proc$libresoc.v:150831$7931 + attribute \src "libresoc.v:152699.7-152699.28" + process $proc$libresoc.v:152699$7976 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:150840.7-150840.31" - process $proc$libresoc.v:150840$7932 + attribute \src "libresoc.v:152708.7-152708.31" + process $proc$libresoc.v:152708$7977 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:150849.13-150849.25" - process $proc$libresoc.v:150849$7933 + attribute \src "libresoc.v:152717.13-152717.25" + process $proc$libresoc.v:152717$7978 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:150864.7-150864.21" - process $proc$libresoc.v:150864$7934 + attribute \src "libresoc.v:152732.7-152732.21" + process $proc$libresoc.v:152732$7979 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:150871.7-150871.23" - process $proc$libresoc.v:150871$7935 + attribute \src "libresoc.v:152739.7-152739.23" + process $proc$libresoc.v:152739$7980 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:150885.7-150885.20" - process $proc$libresoc.v:150885$7936 + attribute \src "libresoc.v:152753.7-152753.20" + process $proc$libresoc.v:152753$7981 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:150890.14-150890.39" - process $proc$libresoc.v:150890$7937 + attribute \src "libresoc.v:152758.14-152758.39" + process $proc$libresoc.v:152758$7982 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:150899.14-150899.39" - process $proc$libresoc.v:150899$7938 + attribute \src "libresoc.v:152767.14-152767.39" + process $proc$libresoc.v:152767$7983 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:150908.7-150908.20" - process $proc$libresoc.v:150908$7939 + attribute \src "libresoc.v:152776.7-152776.20" + process $proc$libresoc.v:152776$7984 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:150916.3-150917.35" - process $proc$libresoc.v:150916$7848 + attribute \src "libresoc.v:152784.3-152785.35" + process $proc$libresoc.v:152784$7893 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:150918.3-150919.31" - process $proc$libresoc.v:150918$7849 + attribute \src "libresoc.v:152786.3-152787.31" + process $proc$libresoc.v:152786$7894 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:150920.3-150921.29" - process $proc$libresoc.v:150920$7850 + attribute \src "libresoc.v:152788.3-152789.29" + process $proc$libresoc.v:152788$7895 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:150922.3-150923.21" - process $proc$libresoc.v:150922$7851 + attribute \src "libresoc.v:152790.3-152791.21" + process $proc$libresoc.v:152790$7896 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:150924.3-150925.21" - process $proc$libresoc.v:150924$7852 + attribute \src "libresoc.v:152792.3-152793.21" + process $proc$libresoc.v:152792$7897 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:150926.3-150927.51" - process $proc$libresoc.v:150926$7853 + attribute \src "libresoc.v:152794.3-152795.51" + process $proc$libresoc.v:152794$7898 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:150928.3-150929.47" - process $proc$libresoc.v:150928$7854 + attribute \src "libresoc.v:152796.3-152797.47" + process $proc$libresoc.v:152796$7899 assign { } { } - assign $0\mul_op__fn_unit[12:0] \mul_op__fn_unit$next + assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk - update \mul_op__fn_unit $0\mul_op__fn_unit[12:0] + update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:150930.3-150931.61" - process $proc$libresoc.v:150930$7855 + attribute \src "libresoc.v:152798.3-152799.61" + process $proc$libresoc.v:152798$7900 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:150932.3-150933.57" - process $proc$libresoc.v:150932$7856 + attribute \src "libresoc.v:152800.3-152801.57" + process $proc$libresoc.v:152800$7901 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:150934.3-150935.45" - process $proc$libresoc.v:150934$7857 + attribute \src "libresoc.v:152802.3-152803.45" + process $proc$libresoc.v:152802$7902 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:150936.3-150937.45" - process $proc$libresoc.v:150936$7858 + attribute \src "libresoc.v:152804.3-152805.45" + process $proc$libresoc.v:152804$7903 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:150938.3-150939.45" - process $proc$libresoc.v:150938$7859 + attribute \src "libresoc.v:152806.3-152807.45" + process $proc$libresoc.v:152806$7904 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:150940.3-150941.45" - process $proc$libresoc.v:150940$7860 + attribute \src "libresoc.v:152808.3-152809.45" + process $proc$libresoc.v:152808$7905 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:150942.3-150943.51" - process $proc$libresoc.v:150942$7861 + attribute \src "libresoc.v:152810.3-152811.51" + process $proc$libresoc.v:152810$7906 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:150944.3-150945.49" - process $proc$libresoc.v:150944$7862 + attribute \src "libresoc.v:152812.3-152813.49" + process $proc$libresoc.v:152812$7907 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:150946.3-150947.51" - process $proc$libresoc.v:150946$7863 + attribute \src "libresoc.v:152814.3-152815.51" + process $proc$libresoc.v:152814$7908 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:150948.3-150949.41" - process $proc$libresoc.v:150948$7864 + attribute \src "libresoc.v:152816.3-152817.41" + process $proc$libresoc.v:152816$7909 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:150950.3-150951.27" - process $proc$libresoc.v:150950$7865 + attribute \src "libresoc.v:152818.3-152819.27" + process $proc$libresoc.v:152818$7910 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:150952.3-150953.29" - process $proc$libresoc.v:150952$7866 + attribute \src "libresoc.v:152820.3-152821.29" + process $proc$libresoc.v:152820$7911 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:151032.3-151049.6" - process $proc$libresoc.v:151032$7867 + attribute \src "libresoc.v:152900.3-152917.6" + process $proc$libresoc.v:152900$7912 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7868 $2\r_busy$next[0:0]$7870 - attribute \src "libresoc.v:151033.5-151033.29" + assign $0\r_busy$next[0:0]$7913 $2\r_busy$next[0:0]$7915 + attribute \src "libresoc.v:152901.5-152901.29" switch \initial - attribute \src "libresoc.v:151033.9-151033.17" + attribute \src "libresoc.v:152901.9-152901.17" case 1'1 case end @@ -317233,34 +319796,34 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7869 1'1 + assign $1\r_busy$next[0:0]$7914 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7869 1'0 + assign $1\r_busy$next[0:0]$7914 1'0 case - assign $1\r_busy$next[0:0]$7869 \r_busy + assign $1\r_busy$next[0:0]$7914 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7870 1'0 + assign $2\r_busy$next[0:0]$7915 1'0 case - assign $2\r_busy$next[0:0]$7870 $1\r_busy$next[0:0]$7869 + assign $2\r_busy$next[0:0]$7915 $1\r_busy$next[0:0]$7914 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7868 + update \r_busy$next $0\r_busy$next[0:0]$7913 end - attribute \src "libresoc.v:151050.3-151062.6" - process $proc$libresoc.v:151050$7871 + attribute \src "libresoc.v:152918.3-152930.6" + process $proc$libresoc.v:152918$7916 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$7872 $1\muxid$next[1:0]$7873 - attribute \src "libresoc.v:151051.5-151051.29" + assign $0\muxid$next[1:0]$7917 $1\muxid$next[1:0]$7918 + attribute \src "libresoc.v:152919.5-152919.29" switch \initial - attribute \src "libresoc.v:151051.9-151051.17" + attribute \src "libresoc.v:152919.9-152919.17" case 1'1 case end @@ -317269,19 +319832,19 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$7873 \muxid$52 + assign $1\muxid$next[1:0]$7918 \muxid$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$7873 \muxid$52 + assign $1\muxid$next[1:0]$7918 \muxid$52 case - assign $1\muxid$next[1:0]$7873 \muxid + assign $1\muxid$next[1:0]$7918 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$7872 + update \muxid$next $0\muxid$next[1:0]$7917 end - attribute \src "libresoc.v:151063.3-151098.6" - process $proc$libresoc.v:151063$7874 + attribute \src "libresoc.v:152931.3-152966.6" + process $proc$libresoc.v:152931$7919 assign { } { } assign { } { } assign { } { } @@ -317306,27 +319869,27 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$next[12:0]$7875 $1\mul_op__fn_unit$next[12:0]$7887 + assign $0\mul_op__fn_unit$next[13:0]$7920 $1\mul_op__fn_unit$next[13:0]$7932 assign { } { } assign { } { } - assign $0\mul_op__insn$next[31:0]$7878 $1\mul_op__insn$next[31:0]$7890 - assign $0\mul_op__insn_type$next[6:0]$7879 $1\mul_op__insn_type$next[6:0]$7891 - assign $0\mul_op__is_32bit$next[0:0]$7880 $1\mul_op__is_32bit$next[0:0]$7892 - assign $0\mul_op__is_signed$next[0:0]$7881 $1\mul_op__is_signed$next[0:0]$7893 + assign $0\mul_op__insn$next[31:0]$7923 $1\mul_op__insn$next[31:0]$7935 + assign $0\mul_op__insn_type$next[6:0]$7924 $1\mul_op__insn_type$next[6:0]$7936 + assign $0\mul_op__is_32bit$next[0:0]$7925 $1\mul_op__is_32bit$next[0:0]$7937 + assign $0\mul_op__is_signed$next[0:0]$7926 $1\mul_op__is_signed$next[0:0]$7938 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7886 $1\mul_op__write_cr0$next[0:0]$7898 - assign $0\mul_op__imm_data__data$next[63:0]$7876 $2\mul_op__imm_data__data$next[63:0]$7899 - assign $0\mul_op__imm_data__ok$next[0:0]$7877 $2\mul_op__imm_data__ok$next[0:0]$7900 - assign $0\mul_op__oe__oe$next[0:0]$7882 $2\mul_op__oe__oe$next[0:0]$7901 - assign $0\mul_op__oe__ok$next[0:0]$7883 $2\mul_op__oe__ok$next[0:0]$7902 - assign $0\mul_op__rc__ok$next[0:0]$7884 $2\mul_op__rc__ok$next[0:0]$7903 - assign $0\mul_op__rc__rc$next[0:0]$7885 $2\mul_op__rc__rc$next[0:0]$7904 - attribute \src "libresoc.v:151064.5-151064.29" + assign $0\mul_op__write_cr0$next[0:0]$7931 $1\mul_op__write_cr0$next[0:0]$7943 + assign $0\mul_op__imm_data__data$next[63:0]$7921 $2\mul_op__imm_data__data$next[63:0]$7944 + assign $0\mul_op__imm_data__ok$next[0:0]$7922 $2\mul_op__imm_data__ok$next[0:0]$7945 + assign $0\mul_op__oe__oe$next[0:0]$7927 $2\mul_op__oe__oe$next[0:0]$7946 + assign $0\mul_op__oe__ok$next[0:0]$7928 $2\mul_op__oe__ok$next[0:0]$7947 + assign $0\mul_op__rc__ok$next[0:0]$7929 $2\mul_op__rc__ok$next[0:0]$7948 + assign $0\mul_op__rc__rc$next[0:0]$7930 $2\mul_op__rc__rc$next[0:0]$7949 + attribute \src "libresoc.v:152932.5-152932.29" switch \initial - attribute \src "libresoc.v:151064.9-151064.17" + attribute \src "libresoc.v:152932.9-152932.17" case 1'1 case end @@ -317346,7 +319909,7 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7890 $1\mul_op__is_signed$next[0:0]$7893 $1\mul_op__is_32bit$next[0:0]$7892 $1\mul_op__write_cr0$next[0:0]$7898 $1\mul_op__oe__ok$next[0:0]$7895 $1\mul_op__oe__oe$next[0:0]$7894 $1\mul_op__rc__ok$next[0:0]$7896 $1\mul_op__rc__rc$next[0:0]$7897 $1\mul_op__imm_data__ok$next[0:0]$7889 $1\mul_op__imm_data__data$next[63:0]$7888 $1\mul_op__fn_unit$next[12:0]$7887 $1\mul_op__insn_type$next[6:0]$7891 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7935 $1\mul_op__is_signed$next[0:0]$7938 $1\mul_op__is_32bit$next[0:0]$7937 $1\mul_op__write_cr0$next[0:0]$7943 $1\mul_op__oe__ok$next[0:0]$7940 $1\mul_op__oe__oe$next[0:0]$7939 $1\mul_op__rc__ok$next[0:0]$7941 $1\mul_op__rc__rc$next[0:0]$7942 $1\mul_op__imm_data__ok$next[0:0]$7934 $1\mul_op__imm_data__data$next[63:0]$7933 $1\mul_op__fn_unit$next[13:0]$7932 $1\mul_op__insn_type$next[6:0]$7936 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -317361,20 +319924,20 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7890 $1\mul_op__is_signed$next[0:0]$7893 $1\mul_op__is_32bit$next[0:0]$7892 $1\mul_op__write_cr0$next[0:0]$7898 $1\mul_op__oe__ok$next[0:0]$7895 $1\mul_op__oe__oe$next[0:0]$7894 $1\mul_op__rc__ok$next[0:0]$7896 $1\mul_op__rc__rc$next[0:0]$7897 $1\mul_op__imm_data__ok$next[0:0]$7889 $1\mul_op__imm_data__data$next[63:0]$7888 $1\mul_op__fn_unit$next[12:0]$7887 $1\mul_op__insn_type$next[6:0]$7891 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7935 $1\mul_op__is_signed$next[0:0]$7938 $1\mul_op__is_32bit$next[0:0]$7937 $1\mul_op__write_cr0$next[0:0]$7943 $1\mul_op__oe__ok$next[0:0]$7940 $1\mul_op__oe__oe$next[0:0]$7939 $1\mul_op__rc__ok$next[0:0]$7941 $1\mul_op__rc__rc$next[0:0]$7942 $1\mul_op__imm_data__ok$next[0:0]$7934 $1\mul_op__imm_data__data$next[63:0]$7933 $1\mul_op__fn_unit$next[13:0]$7932 $1\mul_op__insn_type$next[6:0]$7936 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } case - assign $1\mul_op__fn_unit$next[12:0]$7887 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7888 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7889 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7890 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7891 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7892 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7893 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7894 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7895 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7896 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7897 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7898 \mul_op__write_cr0 + assign $1\mul_op__fn_unit$next[13:0]$7932 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7933 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7934 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7935 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7936 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7937 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7938 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7939 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7940 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7941 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7942 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7943 \mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -317386,42 +319949,42 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7899 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7900 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7904 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7903 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7901 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7902 1'0 + assign $2\mul_op__imm_data__data$next[63:0]$7944 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7945 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7949 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7948 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7946 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7947 1'0 case - assign $2\mul_op__imm_data__data$next[63:0]$7899 $1\mul_op__imm_data__data$next[63:0]$7888 - assign $2\mul_op__imm_data__ok$next[0:0]$7900 $1\mul_op__imm_data__ok$next[0:0]$7889 - assign $2\mul_op__oe__oe$next[0:0]$7901 $1\mul_op__oe__oe$next[0:0]$7894 - assign $2\mul_op__oe__ok$next[0:0]$7902 $1\mul_op__oe__ok$next[0:0]$7895 - assign $2\mul_op__rc__ok$next[0:0]$7903 $1\mul_op__rc__ok$next[0:0]$7896 - assign $2\mul_op__rc__rc$next[0:0]$7904 $1\mul_op__rc__rc$next[0:0]$7897 + assign $2\mul_op__imm_data__data$next[63:0]$7944 $1\mul_op__imm_data__data$next[63:0]$7933 + assign $2\mul_op__imm_data__ok$next[0:0]$7945 $1\mul_op__imm_data__ok$next[0:0]$7934 + assign $2\mul_op__oe__oe$next[0:0]$7946 $1\mul_op__oe__oe$next[0:0]$7939 + assign $2\mul_op__oe__ok$next[0:0]$7947 $1\mul_op__oe__ok$next[0:0]$7940 + assign $2\mul_op__rc__ok$next[0:0]$7948 $1\mul_op__rc__ok$next[0:0]$7941 + assign $2\mul_op__rc__rc$next[0:0]$7949 $1\mul_op__rc__rc$next[0:0]$7942 end sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[12:0]$7875 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7876 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7877 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7878 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7879 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7880 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7881 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7882 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7883 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7884 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7885 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7886 + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7920 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7921 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7922 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7923 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7924 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7925 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7926 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7927 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7928 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7929 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7930 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7931 end - attribute \src "libresoc.v:151099.3-151111.6" - process $proc$libresoc.v:151099$7905 + attribute \src "libresoc.v:152967.3-152979.6" + process $proc$libresoc.v:152967$7950 assign { } { } assign { } { } - assign $0\ra$next[63:0]$7906 $1\ra$next[63:0]$7907 - attribute \src "libresoc.v:151100.5-151100.29" + assign $0\ra$next[63:0]$7951 $1\ra$next[63:0]$7952 + attribute \src "libresoc.v:152968.5-152968.29" switch \initial - attribute \src "libresoc.v:151100.9-151100.17" + attribute \src "libresoc.v:152968.9-152968.17" case 1'1 case end @@ -317430,25 +319993,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$7907 \ra$65 + assign $1\ra$next[63:0]$7952 \ra$65 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$7907 \ra$65 + assign $1\ra$next[63:0]$7952 \ra$65 case - assign $1\ra$next[63:0]$7907 \ra + assign $1\ra$next[63:0]$7952 \ra end sync always - update \ra$next $0\ra$next[63:0]$7906 + update \ra$next $0\ra$next[63:0]$7951 end - attribute \src "libresoc.v:151112.3-151124.6" - process $proc$libresoc.v:151112$7908 + attribute \src "libresoc.v:152980.3-152992.6" + process $proc$libresoc.v:152980$7953 assign { } { } assign { } { } - assign $0\rb$next[63:0]$7909 $1\rb$next[63:0]$7910 - attribute \src "libresoc.v:151113.5-151113.29" + assign $0\rb$next[63:0]$7954 $1\rb$next[63:0]$7955 + attribute \src "libresoc.v:152981.5-152981.29" switch \initial - attribute \src "libresoc.v:151113.9-151113.17" + attribute \src "libresoc.v:152981.9-152981.17" case 1'1 case end @@ -317457,25 +320020,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$7910 \rb$66 + assign $1\rb$next[63:0]$7955 \rb$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$7910 \rb$66 + assign $1\rb$next[63:0]$7955 \rb$66 case - assign $1\rb$next[63:0]$7910 \rb + assign $1\rb$next[63:0]$7955 \rb end sync always - update \rb$next $0\rb$next[63:0]$7909 + update \rb$next $0\rb$next[63:0]$7954 end - attribute \src "libresoc.v:151125.3-151137.6" - process $proc$libresoc.v:151125$7911 + attribute \src "libresoc.v:152993.3-153005.6" + process $proc$libresoc.v:152993$7956 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$7912 $1\xer_so$next[0:0]$7913 - attribute \src "libresoc.v:151126.5-151126.29" + assign $0\xer_so$next[0:0]$7957 $1\xer_so$next[0:0]$7958 + attribute \src "libresoc.v:152994.5-152994.29" switch \initial - attribute \src "libresoc.v:151126.9-151126.17" + attribute \src "libresoc.v:152994.9-152994.17" case 1'1 case end @@ -317484,25 +320047,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$7913 \xer_so$67 + assign $1\xer_so$next[0:0]$7958 \xer_so$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$7913 \xer_so$67 + assign $1\xer_so$next[0:0]$7958 \xer_so$67 case - assign $1\xer_so$next[0:0]$7913 \xer_so + assign $1\xer_so$next[0:0]$7958 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$7912 + update \xer_so$next $0\xer_so$next[0:0]$7957 end - attribute \src "libresoc.v:151138.3-151150.6" - process $proc$libresoc.v:151138$7914 + attribute \src "libresoc.v:153006.3-153018.6" + process $proc$libresoc.v:153006$7959 assign { } { } assign { } { } - assign $0\neg_res$next[0:0]$7915 $1\neg_res$next[0:0]$7916 - attribute \src "libresoc.v:151139.5-151139.29" + assign $0\neg_res$next[0:0]$7960 $1\neg_res$next[0:0]$7961 + attribute \src "libresoc.v:153007.5-153007.29" switch \initial - attribute \src "libresoc.v:151139.9-151139.17" + attribute \src "libresoc.v:153007.9-153007.17" case 1'1 case end @@ -317511,25 +320074,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$next[0:0]$7916 \neg_res$68 + assign $1\neg_res$next[0:0]$7961 \neg_res$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$next[0:0]$7916 \neg_res$68 + assign $1\neg_res$next[0:0]$7961 \neg_res$68 case - assign $1\neg_res$next[0:0]$7916 \neg_res + assign $1\neg_res$next[0:0]$7961 \neg_res end sync always - update \neg_res$next $0\neg_res$next[0:0]$7915 + update \neg_res$next $0\neg_res$next[0:0]$7960 end - attribute \src "libresoc.v:151151.3-151163.6" - process $proc$libresoc.v:151151$7917 + attribute \src "libresoc.v:153019.3-153031.6" + process $proc$libresoc.v:153019$7962 assign { } { } assign { } { } - assign $0\neg_res32$next[0:0]$7918 $1\neg_res32$next[0:0]$7919 - attribute \src "libresoc.v:151152.5-151152.29" + assign $0\neg_res32$next[0:0]$7963 $1\neg_res32$next[0:0]$7964 + attribute \src "libresoc.v:153020.5-153020.29" switch \initial - attribute \src "libresoc.v:151152.9-151152.17" + attribute \src "libresoc.v:153020.9-153020.17" case 1'1 case end @@ -317538,18 +320101,18 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$next[0:0]$7919 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7964 \neg_res32$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$next[0:0]$7919 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7964 \neg_res32$69 case - assign $1\neg_res32$next[0:0]$7919 \neg_res32 + assign $1\neg_res32$next[0:0]$7964 \neg_res32 end sync always - update \neg_res32$next $0\neg_res32$next[0:0]$7918 + update \neg_res32$next $0\neg_res32$next[0:0]$7963 end - connect \$50 $and$libresoc.v:150915$7847_Y + connect \$50 $and$libresoc.v:152783$7892_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -317573,213 +320136,215 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:151190.1-152100.10" +attribute \src "libresoc.v:153058.1-153978.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:151191.7-151191.20" + attribute \src "libresoc.v:153059.7-153059.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151994.3-152029.6" - wire width 13 $0\mul_op__fn_unit$3$next[12:0]$7983 - attribute \src "libresoc.v:151892.3-151893.53" - wire width 13 $0\mul_op__fn_unit$3[12:0]$7951 - attribute \src "libresoc.v:151476.14-151476.44" - wire width 13 $0\mul_op__fn_unit$3[12:0]$8027 - attribute \src "libresoc.v:151994.3-152029.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7984 - attribute \src "libresoc.v:151894.3-151895.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7953 - attribute \src "libresoc.v:151501.14-151501.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8029 - attribute \src "libresoc.v:151994.3-152029.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$7985 - attribute \src "libresoc.v:151896.3-151897.63" - wire $0\mul_op__imm_data__ok$5[0:0]$7955 - attribute \src "libresoc.v:151510.7-151510.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8031 - attribute \src "libresoc.v:151994.3-152029.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$7986 - attribute \src "libresoc.v:151912.3-151913.49" - wire width 32 $0\mul_op__insn$13[31:0]$7971 - attribute \src "libresoc.v:151517.14-151517.39" - wire width 32 $0\mul_op__insn$13[31:0]$8033 - attribute \src "libresoc.v:151994.3-152029.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$7987 - attribute \src "libresoc.v:151890.3-151891.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7949 - attribute \src "libresoc.v:151674.13-151674.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8035 - attribute \src "libresoc.v:151994.3-152029.6" - wire $0\mul_op__is_32bit$11$next[0:0]$7988 - attribute \src "libresoc.v:151908.3-151909.57" - wire $0\mul_op__is_32bit$11[0:0]$7967 - attribute \src "libresoc.v:151757.7-151757.35" - wire $0\mul_op__is_32bit$11[0:0]$8037 - attribute \src "libresoc.v:151994.3-152029.6" - wire $0\mul_op__is_signed$12$next[0:0]$7989 - attribute \src "libresoc.v:151910.3-151911.59" - wire $0\mul_op__is_signed$12[0:0]$7969 - attribute \src "libresoc.v:151766.7-151766.36" - wire $0\mul_op__is_signed$12[0:0]$8039 - attribute \src "libresoc.v:151994.3-152029.6" - wire $0\mul_op__oe__oe$8$next[0:0]$7990 - attribute \src "libresoc.v:151902.3-151903.51" - wire $0\mul_op__oe__oe$8[0:0]$7961 - attribute \src "libresoc.v:151777.7-151777.32" - wire $0\mul_op__oe__oe$8[0:0]$8041 - attribute \src "libresoc.v:151994.3-152029.6" - wire $0\mul_op__oe__ok$9$next[0:0]$7991 - attribute \src "libresoc.v:151904.3-151905.51" - wire $0\mul_op__oe__ok$9[0:0]$7963 - attribute \src "libresoc.v:151786.7-151786.32" - wire $0\mul_op__oe__ok$9[0:0]$8043 - attribute \src "libresoc.v:151994.3-152029.6" - wire $0\mul_op__rc__ok$7$next[0:0]$7992 - attribute \src "libresoc.v:151900.3-151901.51" - wire $0\mul_op__rc__ok$7[0:0]$7959 - attribute \src "libresoc.v:151795.7-151795.32" - wire $0\mul_op__rc__ok$7[0:0]$8045 - attribute \src "libresoc.v:151994.3-152029.6" - wire $0\mul_op__rc__rc$6$next[0:0]$7993 - attribute \src "libresoc.v:151898.3-151899.51" - wire $0\mul_op__rc__rc$6[0:0]$7957 - attribute \src "libresoc.v:151804.7-151804.32" - wire $0\mul_op__rc__rc$6[0:0]$8047 - attribute \src "libresoc.v:151994.3-152029.6" - wire $0\mul_op__write_cr0$10$next[0:0]$7994 - attribute \src "libresoc.v:151906.3-151907.59" - wire $0\mul_op__write_cr0$10[0:0]$7965 - attribute \src "libresoc.v:151811.7-151811.36" - wire $0\mul_op__write_cr0$10[0:0]$8049 - attribute \src "libresoc.v:151981.3-151993.6" - wire width 2 $0\muxid$1$next[1:0]$7980 - attribute \src "libresoc.v:151914.3-151915.33" - wire width 2 $0\muxid$1[1:0]$7973 - attribute \src "libresoc.v:151820.13-151820.29" - wire width 2 $0\muxid$1[1:0]$8051 - attribute \src "libresoc.v:152056.3-152068.6" - wire $0\neg_res$15$next[0:0]$8020 - attribute \src "libresoc.v:151884.3-151885.39" - wire $0\neg_res$15[0:0]$7944 - attribute \src "libresoc.v:151835.7-151835.26" - wire $0\neg_res$15[0:0]$8053 - attribute \src "libresoc.v:152069.3-152081.6" - wire $0\neg_res32$16$next[0:0]$8023 - attribute \src "libresoc.v:151882.3-151883.43" - wire $0\neg_res32$16[0:0]$7942 - attribute \src "libresoc.v:151844.7-151844.28" - wire $0\neg_res32$16[0:0]$8055 - attribute \src "libresoc.v:152030.3-152042.6" - wire width 129 $0\o$next[128:0]$8014 - attribute \src "libresoc.v:151888.3-151889.19" + attribute \src "libresoc.v:153872.3-153907.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8028 + attribute \src "libresoc.v:153770.3-153771.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$7996 + attribute \src "libresoc.v:153350.14-153350.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8072 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8029 + attribute \src "libresoc.v:153772.3-153773.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7998 + attribute \src "libresoc.v:153376.14-153376.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8074 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8030 + attribute \src "libresoc.v:153774.3-153775.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8000 + attribute \src "libresoc.v:153385.7-153385.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8076 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8031 + attribute \src "libresoc.v:153790.3-153791.49" + wire width 32 $0\mul_op__insn$13[31:0]$8016 + attribute \src "libresoc.v:153392.14-153392.39" + wire width 32 $0\mul_op__insn$13[31:0]$8078 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8032 + attribute \src "libresoc.v:153768.3-153769.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7994 + attribute \src "libresoc.v:153551.13-153551.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8080 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8033 + attribute \src "libresoc.v:153786.3-153787.57" + wire $0\mul_op__is_32bit$11[0:0]$8012 + attribute \src "libresoc.v:153635.7-153635.35" + wire $0\mul_op__is_32bit$11[0:0]$8082 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__is_signed$12$next[0:0]$8034 + attribute \src "libresoc.v:153788.3-153789.59" + wire $0\mul_op__is_signed$12[0:0]$8014 + attribute \src "libresoc.v:153644.7-153644.36" + wire $0\mul_op__is_signed$12[0:0]$8084 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8035 + attribute \src "libresoc.v:153780.3-153781.51" + wire $0\mul_op__oe__oe$8[0:0]$8006 + attribute \src "libresoc.v:153655.7-153655.32" + wire $0\mul_op__oe__oe$8[0:0]$8086 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8036 + attribute \src "libresoc.v:153782.3-153783.51" + wire $0\mul_op__oe__ok$9[0:0]$8008 + attribute \src "libresoc.v:153664.7-153664.32" + wire $0\mul_op__oe__ok$9[0:0]$8088 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8037 + attribute \src "libresoc.v:153778.3-153779.51" + wire $0\mul_op__rc__ok$7[0:0]$8004 + attribute \src "libresoc.v:153673.7-153673.32" + wire $0\mul_op__rc__ok$7[0:0]$8090 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8038 + attribute \src "libresoc.v:153776.3-153777.51" + wire $0\mul_op__rc__rc$6[0:0]$8002 + attribute \src "libresoc.v:153682.7-153682.32" + wire $0\mul_op__rc__rc$6[0:0]$8092 + attribute \src "libresoc.v:153872.3-153907.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8039 + attribute \src "libresoc.v:153784.3-153785.59" + wire $0\mul_op__write_cr0$10[0:0]$8010 + attribute \src "libresoc.v:153689.7-153689.36" + wire $0\mul_op__write_cr0$10[0:0]$8094 + attribute \src "libresoc.v:153859.3-153871.6" + wire width 2 $0\muxid$1$next[1:0]$8025 + attribute \src "libresoc.v:153792.3-153793.33" + wire width 2 $0\muxid$1[1:0]$8018 + attribute \src "libresoc.v:153698.13-153698.29" + wire width 2 $0\muxid$1[1:0]$8096 + attribute \src "libresoc.v:153934.3-153946.6" + wire $0\neg_res$15$next[0:0]$8065 + attribute \src "libresoc.v:153762.3-153763.39" + wire $0\neg_res$15[0:0]$7989 + attribute \src "libresoc.v:153713.7-153713.26" + wire $0\neg_res$15[0:0]$8098 + attribute \src "libresoc.v:153947.3-153959.6" + wire $0\neg_res32$16$next[0:0]$8068 + attribute \src "libresoc.v:153760.3-153761.43" + wire $0\neg_res32$16[0:0]$7987 + attribute \src "libresoc.v:153722.7-153722.28" + wire $0\neg_res32$16[0:0]$8100 + attribute \src "libresoc.v:153908.3-153920.6" + wire width 129 $0\o$next[128:0]$8059 + attribute \src "libresoc.v:153766.3-153767.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:151963.3-151980.6" - wire $0\r_busy$next[0:0]$7976 - attribute \src "libresoc.v:151916.3-151917.29" + attribute \src "libresoc.v:153841.3-153858.6" + wire $0\r_busy$next[0:0]$8021 + attribute \src "libresoc.v:153794.3-153795.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:152043.3-152055.6" - wire $0\xer_so$14$next[0:0]$8017 - attribute \src "libresoc.v:151886.3-151887.37" - wire $0\xer_so$14[0:0]$7946 - attribute \src "libresoc.v:151876.7-151876.25" - wire $0\xer_so$14[0:0]$8059 - attribute \src "libresoc.v:151994.3-152029.6" - wire width 13 $1\mul_op__fn_unit$3$next[12:0]$7995 - attribute \src "libresoc.v:151994.3-152029.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7996 - attribute \src "libresoc.v:151994.3-152029.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$7997 - attribute \src "libresoc.v:151994.3-152029.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$7998 - attribute \src "libresoc.v:151994.3-152029.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$7999 - attribute \src "libresoc.v:151994.3-152029.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8000 - attribute \src "libresoc.v:151994.3-152029.6" - wire $1\mul_op__is_signed$12$next[0:0]$8001 - attribute \src "libresoc.v:151994.3-152029.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8002 - attribute \src "libresoc.v:151994.3-152029.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8003 - attribute \src "libresoc.v:151994.3-152029.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8004 - attribute \src "libresoc.v:151994.3-152029.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8005 - attribute \src "libresoc.v:151994.3-152029.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8006 - attribute \src "libresoc.v:151981.3-151993.6" - wire width 2 $1\muxid$1$next[1:0]$7981 - attribute \src "libresoc.v:152056.3-152068.6" - wire $1\neg_res$15$next[0:0]$8021 - attribute \src "libresoc.v:152069.3-152081.6" - wire $1\neg_res32$16$next[0:0]$8024 - attribute \src "libresoc.v:152030.3-152042.6" - wire width 129 $1\o$next[128:0]$8015 - attribute \src "libresoc.v:151851.15-151851.57" + attribute \src "libresoc.v:153921.3-153933.6" + wire $0\xer_so$14$next[0:0]$8062 + attribute \src "libresoc.v:153764.3-153765.37" + wire $0\xer_so$14[0:0]$7991 + attribute \src "libresoc.v:153754.7-153754.25" + wire $0\xer_so$14[0:0]$8104 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8040 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8041 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8042 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8043 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8044 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8045 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__is_signed$12$next[0:0]$8046 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8047 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8048 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8049 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8050 + attribute \src "libresoc.v:153872.3-153907.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8051 + attribute \src "libresoc.v:153859.3-153871.6" + wire width 2 $1\muxid$1$next[1:0]$8026 + attribute \src "libresoc.v:153934.3-153946.6" + wire $1\neg_res$15$next[0:0]$8066 + attribute \src "libresoc.v:153947.3-153959.6" + wire $1\neg_res32$16$next[0:0]$8069 + attribute \src "libresoc.v:153908.3-153920.6" + wire width 129 $1\o$next[128:0]$8060 + attribute \src "libresoc.v:153729.15-153729.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:151963.3-151980.6" - wire $1\r_busy$next[0:0]$7977 - attribute \src "libresoc.v:151865.7-151865.20" + attribute \src "libresoc.v:153841.3-153858.6" + wire $1\r_busy$next[0:0]$8022 + attribute \src "libresoc.v:153743.7-153743.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:152043.3-152055.6" - wire $1\xer_so$14$next[0:0]$8018 - attribute \src "libresoc.v:151994.3-152029.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8007 - attribute \src "libresoc.v:151994.3-152029.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8008 - attribute \src "libresoc.v:151994.3-152029.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8009 - attribute \src "libresoc.v:151994.3-152029.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8010 - attribute \src "libresoc.v:151994.3-152029.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8011 - attribute \src "libresoc.v:151994.3-152029.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8012 - attribute \src "libresoc.v:151963.3-151980.6" - wire $2\r_busy$next[0:0]$7978 - attribute \src "libresoc.v:151881.18-151881.118" - wire $and$libresoc.v:151881$7940_Y + attribute \src "libresoc.v:153921.3-153933.6" + wire $1\xer_so$14$next[0:0]$8063 + attribute \src "libresoc.v:153872.3-153907.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8052 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8053 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8054 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8055 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8056 + attribute \src "libresoc.v:153872.3-153907.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8057 + attribute \src "libresoc.v:153841.3-153858.6" + wire $2\r_busy$next[0:0]$8023 + attribute \src "libresoc.v:153759.18-153759.118" + wire $and$libresoc.v:153759$7985_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:151191.7-151191.15" + attribute \src "libresoc.v:153059.7-153059.15" wire \initial attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul2_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul2_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul2_mul_op__fn_unit$19 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul2_mul_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul2_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -317866,6 +320431,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul2_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -317942,6 +320508,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul2_mul_op__insn_type$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -317995,55 +320562,58 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul2_xer_so$30 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 26 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$38 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -318142,6 +320712,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -318218,6 +320789,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 25 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -318296,6 +320868,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -318415,7 +320988,7 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:151881$7940 + cell $and $and$libresoc.v:153759$7985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -318423,10 +320996,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:151881$7940_Y + connect \Y $and$libresoc.v:153759$7985_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:151918.8-151954.4" + attribute \src "libresoc.v:153796.8-153832.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -318465,304 +321038,304 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:151955.10-151958.4" + attribute \src "libresoc.v:153833.10-153836.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:151959.10-151962.4" + attribute \src "libresoc.v:153837.10-153840.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:151191.7-151191.20" - process $proc$libresoc.v:151191$8025 + attribute \src "libresoc.v:153059.7-153059.20" + process $proc$libresoc.v:153059$8070 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151476.14-151476.44" - process $proc$libresoc.v:151476$8026 + attribute \src "libresoc.v:153350.14-153350.44" + process $proc$libresoc.v:153350$8071 assign { } { } - assign $0\mul_op__fn_unit$3[12:0]$8027 13'0000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8072 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8027 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8072 end - attribute \src "libresoc.v:151501.14-151501.63" - process $proc$libresoc.v:151501$8028 + attribute \src "libresoc.v:153376.14-153376.63" + process $proc$libresoc.v:153376$8073 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8029 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8074 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8029 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8074 end - attribute \src "libresoc.v:151510.7-151510.38" - process $proc$libresoc.v:151510$8030 + attribute \src "libresoc.v:153385.7-153385.38" + process $proc$libresoc.v:153385$8075 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8031 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8076 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8031 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8076 end - attribute \src "libresoc.v:151517.14-151517.39" - process $proc$libresoc.v:151517$8032 + attribute \src "libresoc.v:153392.14-153392.39" + process $proc$libresoc.v:153392$8077 assign { } { } - assign $0\mul_op__insn$13[31:0]$8033 0 + assign $0\mul_op__insn$13[31:0]$8078 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8033 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8078 end - attribute \src "libresoc.v:151674.13-151674.42" - process $proc$libresoc.v:151674$8034 + attribute \src "libresoc.v:153551.13-153551.42" + process $proc$libresoc.v:153551$8079 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8035 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8080 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8035 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8080 end - attribute \src "libresoc.v:151757.7-151757.35" - process $proc$libresoc.v:151757$8036 + attribute \src "libresoc.v:153635.7-153635.35" + process $proc$libresoc.v:153635$8081 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8037 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8082 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8037 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8082 end - attribute \src "libresoc.v:151766.7-151766.36" - process $proc$libresoc.v:151766$8038 + attribute \src "libresoc.v:153644.7-153644.36" + process $proc$libresoc.v:153644$8083 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8039 1'0 + assign $0\mul_op__is_signed$12[0:0]$8084 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8039 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8084 end - attribute \src "libresoc.v:151777.7-151777.32" - process $proc$libresoc.v:151777$8040 + attribute \src "libresoc.v:153655.7-153655.32" + process $proc$libresoc.v:153655$8085 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8041 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8086 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8041 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8086 end - attribute \src "libresoc.v:151786.7-151786.32" - process $proc$libresoc.v:151786$8042 + attribute \src "libresoc.v:153664.7-153664.32" + process $proc$libresoc.v:153664$8087 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8043 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8088 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8043 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8088 end - attribute \src "libresoc.v:151795.7-151795.32" - process $proc$libresoc.v:151795$8044 + attribute \src "libresoc.v:153673.7-153673.32" + process $proc$libresoc.v:153673$8089 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8045 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8090 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8045 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8090 end - attribute \src "libresoc.v:151804.7-151804.32" - process $proc$libresoc.v:151804$8046 + attribute \src "libresoc.v:153682.7-153682.32" + process $proc$libresoc.v:153682$8091 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8047 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8092 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8047 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8092 end - attribute \src "libresoc.v:151811.7-151811.36" - process $proc$libresoc.v:151811$8048 + attribute \src "libresoc.v:153689.7-153689.36" + process $proc$libresoc.v:153689$8093 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8049 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8094 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8049 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8094 end - attribute \src "libresoc.v:151820.13-151820.29" - process $proc$libresoc.v:151820$8050 + attribute \src "libresoc.v:153698.13-153698.29" + process $proc$libresoc.v:153698$8095 assign { } { } - assign $0\muxid$1[1:0]$8051 2'00 + assign $0\muxid$1[1:0]$8096 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8051 + update \muxid$1 $0\muxid$1[1:0]$8096 end - attribute \src "libresoc.v:151835.7-151835.26" - process $proc$libresoc.v:151835$8052 + attribute \src "libresoc.v:153713.7-153713.26" + process $proc$libresoc.v:153713$8097 assign { } { } - assign $0\neg_res$15[0:0]$8053 1'0 + assign $0\neg_res$15[0:0]$8098 1'0 sync always sync init - update \neg_res$15 $0\neg_res$15[0:0]$8053 + update \neg_res$15 $0\neg_res$15[0:0]$8098 end - attribute \src "libresoc.v:151844.7-151844.28" - process $proc$libresoc.v:151844$8054 + attribute \src "libresoc.v:153722.7-153722.28" + process $proc$libresoc.v:153722$8099 assign { } { } - assign $0\neg_res32$16[0:0]$8055 1'0 + assign $0\neg_res32$16[0:0]$8100 1'0 sync always sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$8055 + update \neg_res32$16 $0\neg_res32$16[0:0]$8100 end - attribute \src "libresoc.v:151851.15-151851.57" - process $proc$libresoc.v:151851$8056 + attribute \src "libresoc.v:153729.15-153729.57" + process $proc$libresoc.v:153729$8101 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:151865.7-151865.20" - process $proc$libresoc.v:151865$8057 + attribute \src "libresoc.v:153743.7-153743.20" + process $proc$libresoc.v:153743$8102 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:151876.7-151876.25" - process $proc$libresoc.v:151876$8058 + attribute \src "libresoc.v:153754.7-153754.25" + process $proc$libresoc.v:153754$8103 assign { } { } - assign $0\xer_so$14[0:0]$8059 1'0 + assign $0\xer_so$14[0:0]$8104 1'0 sync always sync init - update \xer_so$14 $0\xer_so$14[0:0]$8059 + update \xer_so$14 $0\xer_so$14[0:0]$8104 end - attribute \src "libresoc.v:151882.3-151883.43" - process $proc$libresoc.v:151882$7941 + attribute \src "libresoc.v:153760.3-153761.43" + process $proc$libresoc.v:153760$7986 assign { } { } - assign $0\neg_res32$16[0:0]$7942 \neg_res32$16$next + assign $0\neg_res32$16[0:0]$7987 \neg_res32$16$next sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$7942 + update \neg_res32$16 $0\neg_res32$16[0:0]$7987 end - attribute \src "libresoc.v:151884.3-151885.39" - process $proc$libresoc.v:151884$7943 + attribute \src "libresoc.v:153762.3-153763.39" + process $proc$libresoc.v:153762$7988 assign { } { } - assign $0\neg_res$15[0:0]$7944 \neg_res$15$next + assign $0\neg_res$15[0:0]$7989 \neg_res$15$next sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$7944 + update \neg_res$15 $0\neg_res$15[0:0]$7989 end - attribute \src "libresoc.v:151886.3-151887.37" - process $proc$libresoc.v:151886$7945 + attribute \src "libresoc.v:153764.3-153765.37" + process $proc$libresoc.v:153764$7990 assign { } { } - assign $0\xer_so$14[0:0]$7946 \xer_so$14$next + assign $0\xer_so$14[0:0]$7991 \xer_so$14$next sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$7946 + update \xer_so$14 $0\xer_so$14[0:0]$7991 end - attribute \src "libresoc.v:151888.3-151889.19" - process $proc$libresoc.v:151888$7947 + attribute \src "libresoc.v:153766.3-153767.19" + process $proc$libresoc.v:153766$7992 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:151890.3-151891.57" - process $proc$libresoc.v:151890$7948 + attribute \src "libresoc.v:153768.3-153769.57" + process $proc$libresoc.v:153768$7993 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7949 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$7994 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7949 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7994 end - attribute \src "libresoc.v:151892.3-151893.53" - process $proc$libresoc.v:151892$7950 + attribute \src "libresoc.v:153770.3-153771.53" + process $proc$libresoc.v:153770$7995 assign { } { } - assign $0\mul_op__fn_unit$3[12:0]$7951 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$7996 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$7951 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$7996 end - attribute \src "libresoc.v:151894.3-151895.67" - process $proc$libresoc.v:151894$7952 + attribute \src "libresoc.v:153772.3-153773.67" + process $proc$libresoc.v:153772$7997 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7953 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$7998 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7953 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7998 end - attribute \src "libresoc.v:151896.3-151897.63" - process $proc$libresoc.v:151896$7954 + attribute \src "libresoc.v:153774.3-153775.63" + process $proc$libresoc.v:153774$7999 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7955 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8000 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7955 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8000 end - attribute \src "libresoc.v:151898.3-151899.51" - process $proc$libresoc.v:151898$7956 + attribute \src "libresoc.v:153776.3-153777.51" + process $proc$libresoc.v:153776$8001 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7957 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8002 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7957 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8002 end - attribute \src "libresoc.v:151900.3-151901.51" - process $proc$libresoc.v:151900$7958 + attribute \src "libresoc.v:153778.3-153779.51" + process $proc$libresoc.v:153778$8003 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7959 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8004 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7959 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8004 end - attribute \src "libresoc.v:151902.3-151903.51" - process $proc$libresoc.v:151902$7960 + attribute \src "libresoc.v:153780.3-153781.51" + process $proc$libresoc.v:153780$8005 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7961 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8006 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7961 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8006 end - attribute \src "libresoc.v:151904.3-151905.51" - process $proc$libresoc.v:151904$7962 + attribute \src "libresoc.v:153782.3-153783.51" + process $proc$libresoc.v:153782$8007 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7963 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8008 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7963 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8008 end - attribute \src "libresoc.v:151906.3-151907.59" - process $proc$libresoc.v:151906$7964 + attribute \src "libresoc.v:153784.3-153785.59" + process $proc$libresoc.v:153784$8009 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7965 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8010 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7965 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8010 end - attribute \src "libresoc.v:151908.3-151909.57" - process $proc$libresoc.v:151908$7966 + attribute \src "libresoc.v:153786.3-153787.57" + process $proc$libresoc.v:153786$8011 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7967 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8012 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7967 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8012 end - attribute \src "libresoc.v:151910.3-151911.59" - process $proc$libresoc.v:151910$7968 + attribute \src "libresoc.v:153788.3-153789.59" + process $proc$libresoc.v:153788$8013 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7969 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8014 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7969 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8014 end - attribute \src "libresoc.v:151912.3-151913.49" - process $proc$libresoc.v:151912$7970 + attribute \src "libresoc.v:153790.3-153791.49" + process $proc$libresoc.v:153790$8015 assign { } { } - assign $0\mul_op__insn$13[31:0]$7971 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8016 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7971 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8016 end - attribute \src "libresoc.v:151914.3-151915.33" - process $proc$libresoc.v:151914$7972 + attribute \src "libresoc.v:153792.3-153793.33" + process $proc$libresoc.v:153792$8017 assign { } { } - assign $0\muxid$1[1:0]$7973 \muxid$1$next + assign $0\muxid$1[1:0]$8018 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7973 + update \muxid$1 $0\muxid$1[1:0]$8018 end - attribute \src "libresoc.v:151916.3-151917.29" - process $proc$libresoc.v:151916$7974 + attribute \src "libresoc.v:153794.3-153795.29" + process $proc$libresoc.v:153794$8019 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:151963.3-151980.6" - process $proc$libresoc.v:151963$7975 + attribute \src "libresoc.v:153841.3-153858.6" + process $proc$libresoc.v:153841$8020 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7976 $2\r_busy$next[0:0]$7978 - attribute \src "libresoc.v:151964.5-151964.29" + assign $0\r_busy$next[0:0]$8021 $2\r_busy$next[0:0]$8023 + attribute \src "libresoc.v:153842.5-153842.29" switch \initial - attribute \src "libresoc.v:151964.9-151964.17" + attribute \src "libresoc.v:153842.9-153842.17" case 1'1 case end @@ -318771,34 +321344,34 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7977 1'1 + assign $1\r_busy$next[0:0]$8022 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7977 1'0 + assign $1\r_busy$next[0:0]$8022 1'0 case - assign $1\r_busy$next[0:0]$7977 \r_busy + assign $1\r_busy$next[0:0]$8022 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7978 1'0 + assign $2\r_busy$next[0:0]$8023 1'0 case - assign $2\r_busy$next[0:0]$7978 $1\r_busy$next[0:0]$7977 + assign $2\r_busy$next[0:0]$8023 $1\r_busy$next[0:0]$8022 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7976 + update \r_busy$next $0\r_busy$next[0:0]$8021 end - attribute \src "libresoc.v:151981.3-151993.6" - process $proc$libresoc.v:151981$7979 + attribute \src "libresoc.v:153859.3-153871.6" + process $proc$libresoc.v:153859$8024 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$7980 $1\muxid$1$next[1:0]$7981 - attribute \src "libresoc.v:151982.5-151982.29" + assign $0\muxid$1$next[1:0]$8025 $1\muxid$1$next[1:0]$8026 + attribute \src "libresoc.v:153860.5-153860.29" switch \initial - attribute \src "libresoc.v:151982.9-151982.17" + attribute \src "libresoc.v:153860.9-153860.17" case 1'1 case end @@ -318807,19 +321380,19 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$7981 \muxid$36 + assign $1\muxid$1$next[1:0]$8026 \muxid$36 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$7981 \muxid$36 + assign $1\muxid$1$next[1:0]$8026 \muxid$36 case - assign $1\muxid$1$next[1:0]$7981 \muxid$1 + assign $1\muxid$1$next[1:0]$8026 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7980 + update \muxid$1$next $0\muxid$1$next[1:0]$8025 end - attribute \src "libresoc.v:151994.3-152029.6" - process $proc$libresoc.v:151994$7982 + attribute \src "libresoc.v:153872.3-153907.6" + process $proc$libresoc.v:153872$8027 assign { } { } assign { } { } assign { } { } @@ -318844,27 +321417,27 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[12:0]$7983 $1\mul_op__fn_unit$3$next[12:0]$7995 + assign $0\mul_op__fn_unit$3$next[13:0]$8028 $1\mul_op__fn_unit$3$next[13:0]$8040 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7986 $1\mul_op__insn$13$next[31:0]$7998 - assign $0\mul_op__insn_type$2$next[6:0]$7987 $1\mul_op__insn_type$2$next[6:0]$7999 - assign $0\mul_op__is_32bit$11$next[0:0]$7988 $1\mul_op__is_32bit$11$next[0:0]$8000 - assign $0\mul_op__is_signed$12$next[0:0]$7989 $1\mul_op__is_signed$12$next[0:0]$8001 + assign $0\mul_op__insn$13$next[31:0]$8031 $1\mul_op__insn$13$next[31:0]$8043 + assign $0\mul_op__insn_type$2$next[6:0]$8032 $1\mul_op__insn_type$2$next[6:0]$8044 + assign $0\mul_op__is_32bit$11$next[0:0]$8033 $1\mul_op__is_32bit$11$next[0:0]$8045 + assign $0\mul_op__is_signed$12$next[0:0]$8034 $1\mul_op__is_signed$12$next[0:0]$8046 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7994 $1\mul_op__write_cr0$10$next[0:0]$8006 - assign $0\mul_op__imm_data__data$4$next[63:0]$7984 $2\mul_op__imm_data__data$4$next[63:0]$8007 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7985 $2\mul_op__imm_data__ok$5$next[0:0]$8008 - assign $0\mul_op__oe__oe$8$next[0:0]$7990 $2\mul_op__oe__oe$8$next[0:0]$8009 - assign $0\mul_op__oe__ok$9$next[0:0]$7991 $2\mul_op__oe__ok$9$next[0:0]$8010 - assign $0\mul_op__rc__ok$7$next[0:0]$7992 $2\mul_op__rc__ok$7$next[0:0]$8011 - assign $0\mul_op__rc__rc$6$next[0:0]$7993 $2\mul_op__rc__rc$6$next[0:0]$8012 - attribute \src "libresoc.v:151995.5-151995.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8039 $1\mul_op__write_cr0$10$next[0:0]$8051 + assign $0\mul_op__imm_data__data$4$next[63:0]$8029 $2\mul_op__imm_data__data$4$next[63:0]$8052 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8030 $2\mul_op__imm_data__ok$5$next[0:0]$8053 + assign $0\mul_op__oe__oe$8$next[0:0]$8035 $2\mul_op__oe__oe$8$next[0:0]$8054 + assign $0\mul_op__oe__ok$9$next[0:0]$8036 $2\mul_op__oe__ok$9$next[0:0]$8055 + assign $0\mul_op__rc__ok$7$next[0:0]$8037 $2\mul_op__rc__ok$7$next[0:0]$8056 + assign $0\mul_op__rc__rc$6$next[0:0]$8038 $2\mul_op__rc__rc$6$next[0:0]$8057 + attribute \src "libresoc.v:153873.5-153873.29" switch \initial - attribute \src "libresoc.v:151995.9-151995.17" + attribute \src "libresoc.v:153873.9-153873.17" case 1'1 case end @@ -318884,7 +321457,7 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7998 $1\mul_op__is_signed$12$next[0:0]$8001 $1\mul_op__is_32bit$11$next[0:0]$8000 $1\mul_op__write_cr0$10$next[0:0]$8006 $1\mul_op__oe__ok$9$next[0:0]$8003 $1\mul_op__oe__oe$8$next[0:0]$8002 $1\mul_op__rc__ok$7$next[0:0]$8004 $1\mul_op__rc__rc$6$next[0:0]$8005 $1\mul_op__imm_data__ok$5$next[0:0]$7997 $1\mul_op__imm_data__data$4$next[63:0]$7996 $1\mul_op__fn_unit$3$next[12:0]$7995 $1\mul_op__insn_type$2$next[6:0]$7999 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8043 $1\mul_op__is_signed$12$next[0:0]$8046 $1\mul_op__is_32bit$11$next[0:0]$8045 $1\mul_op__write_cr0$10$next[0:0]$8051 $1\mul_op__oe__ok$9$next[0:0]$8048 $1\mul_op__oe__oe$8$next[0:0]$8047 $1\mul_op__rc__ok$7$next[0:0]$8049 $1\mul_op__rc__rc$6$next[0:0]$8050 $1\mul_op__imm_data__ok$5$next[0:0]$8042 $1\mul_op__imm_data__data$4$next[63:0]$8041 $1\mul_op__fn_unit$3$next[13:0]$8040 $1\mul_op__insn_type$2$next[6:0]$8044 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -318899,20 +321472,20 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7998 $1\mul_op__is_signed$12$next[0:0]$8001 $1\mul_op__is_32bit$11$next[0:0]$8000 $1\mul_op__write_cr0$10$next[0:0]$8006 $1\mul_op__oe__ok$9$next[0:0]$8003 $1\mul_op__oe__oe$8$next[0:0]$8002 $1\mul_op__rc__ok$7$next[0:0]$8004 $1\mul_op__rc__rc$6$next[0:0]$8005 $1\mul_op__imm_data__ok$5$next[0:0]$7997 $1\mul_op__imm_data__data$4$next[63:0]$7996 $1\mul_op__fn_unit$3$next[12:0]$7995 $1\mul_op__insn_type$2$next[6:0]$7999 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8043 $1\mul_op__is_signed$12$next[0:0]$8046 $1\mul_op__is_32bit$11$next[0:0]$8045 $1\mul_op__write_cr0$10$next[0:0]$8051 $1\mul_op__oe__ok$9$next[0:0]$8048 $1\mul_op__oe__oe$8$next[0:0]$8047 $1\mul_op__rc__ok$7$next[0:0]$8049 $1\mul_op__rc__rc$6$next[0:0]$8050 $1\mul_op__imm_data__ok$5$next[0:0]$8042 $1\mul_op__imm_data__data$4$next[63:0]$8041 $1\mul_op__fn_unit$3$next[13:0]$8040 $1\mul_op__insn_type$2$next[6:0]$8044 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case - assign $1\mul_op__fn_unit$3$next[12:0]$7995 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7996 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7997 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7998 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7999 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8000 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8001 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8002 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8003 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8004 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8005 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8006 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8040 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8041 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8042 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8043 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8044 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8045 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8046 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8047 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8048 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8049 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8050 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8051 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -318924,42 +321497,42 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8007 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8008 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8012 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8011 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8009 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8010 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8052 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8053 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8057 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8056 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8054 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8055 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8007 $1\mul_op__imm_data__data$4$next[63:0]$7996 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8008 $1\mul_op__imm_data__ok$5$next[0:0]$7997 - assign $2\mul_op__oe__oe$8$next[0:0]$8009 $1\mul_op__oe__oe$8$next[0:0]$8002 - assign $2\mul_op__oe__ok$9$next[0:0]$8010 $1\mul_op__oe__ok$9$next[0:0]$8003 - assign $2\mul_op__rc__ok$7$next[0:0]$8011 $1\mul_op__rc__ok$7$next[0:0]$8004 - assign $2\mul_op__rc__rc$6$next[0:0]$8012 $1\mul_op__rc__rc$6$next[0:0]$8005 + assign $2\mul_op__imm_data__data$4$next[63:0]$8052 $1\mul_op__imm_data__data$4$next[63:0]$8041 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8053 $1\mul_op__imm_data__ok$5$next[0:0]$8042 + assign $2\mul_op__oe__oe$8$next[0:0]$8054 $1\mul_op__oe__oe$8$next[0:0]$8047 + assign $2\mul_op__oe__ok$9$next[0:0]$8055 $1\mul_op__oe__ok$9$next[0:0]$8048 + assign $2\mul_op__rc__ok$7$next[0:0]$8056 $1\mul_op__rc__ok$7$next[0:0]$8049 + assign $2\mul_op__rc__rc$6$next[0:0]$8057 $1\mul_op__rc__rc$6$next[0:0]$8050 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$7983 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7984 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7985 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7986 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7987 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7988 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7989 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7990 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7991 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7992 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7993 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7994 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8028 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8029 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8030 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8031 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8032 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8033 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8034 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8035 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8036 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8037 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8038 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8039 end - attribute \src "libresoc.v:152030.3-152042.6" - process $proc$libresoc.v:152030$8013 + attribute \src "libresoc.v:153908.3-153920.6" + process $proc$libresoc.v:153908$8058 assign { } { } assign { } { } - assign $0\o$next[128:0]$8014 $1\o$next[128:0]$8015 - attribute \src "libresoc.v:152031.5-152031.29" + assign $0\o$next[128:0]$8059 $1\o$next[128:0]$8060 + attribute \src "libresoc.v:153909.5-153909.29" switch \initial - attribute \src "libresoc.v:152031.9-152031.17" + attribute \src "libresoc.v:153909.9-153909.17" case 1'1 case end @@ -318968,25 +321541,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\o$next[128:0]$8015 \o$49 + assign $1\o$next[128:0]$8060 \o$49 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\o$next[128:0]$8015 \o$49 + assign $1\o$next[128:0]$8060 \o$49 case - assign $1\o$next[128:0]$8015 \o + assign $1\o$next[128:0]$8060 \o end sync always - update \o$next $0\o$next[128:0]$8014 + update \o$next $0\o$next[128:0]$8059 end - attribute \src "libresoc.v:152043.3-152055.6" - process $proc$libresoc.v:152043$8016 + attribute \src "libresoc.v:153921.3-153933.6" + process $proc$libresoc.v:153921$8061 assign { } { } assign { } { } - assign $0\xer_so$14$next[0:0]$8017 $1\xer_so$14$next[0:0]$8018 - attribute \src "libresoc.v:152044.5-152044.29" + assign $0\xer_so$14$next[0:0]$8062 $1\xer_so$14$next[0:0]$8063 + attribute \src "libresoc.v:153922.5-153922.29" switch \initial - attribute \src "libresoc.v:152044.9-152044.17" + attribute \src "libresoc.v:153922.9-153922.17" case 1'1 case end @@ -318995,25 +321568,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$14$next[0:0]$8018 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8063 \xer_so$50 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$14$next[0:0]$8018 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8063 \xer_so$50 case - assign $1\xer_so$14$next[0:0]$8018 \xer_so$14 + assign $1\xer_so$14$next[0:0]$8063 \xer_so$14 end sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$8017 + update \xer_so$14$next $0\xer_so$14$next[0:0]$8062 end - attribute \src "libresoc.v:152056.3-152068.6" - process $proc$libresoc.v:152056$8019 + attribute \src "libresoc.v:153934.3-153946.6" + process $proc$libresoc.v:153934$8064 assign { } { } assign { } { } - assign $0\neg_res$15$next[0:0]$8020 $1\neg_res$15$next[0:0]$8021 - attribute \src "libresoc.v:152057.5-152057.29" + assign $0\neg_res$15$next[0:0]$8065 $1\neg_res$15$next[0:0]$8066 + attribute \src "libresoc.v:153935.5-153935.29" switch \initial - attribute \src "libresoc.v:152057.9-152057.17" + attribute \src "libresoc.v:153935.9-153935.17" case 1'1 case end @@ -319022,25 +321595,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$15$next[0:0]$8021 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8066 \neg_res$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$15$next[0:0]$8021 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8066 \neg_res$51 case - assign $1\neg_res$15$next[0:0]$8021 \neg_res$15 + assign $1\neg_res$15$next[0:0]$8066 \neg_res$15 end sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$8020 + update \neg_res$15$next $0\neg_res$15$next[0:0]$8065 end - attribute \src "libresoc.v:152069.3-152081.6" - process $proc$libresoc.v:152069$8022 + attribute \src "libresoc.v:153947.3-153959.6" + process $proc$libresoc.v:153947$8067 assign { } { } assign { } { } - assign $0\neg_res32$16$next[0:0]$8023 $1\neg_res32$16$next[0:0]$8024 - attribute \src "libresoc.v:152070.5-152070.29" + assign $0\neg_res32$16$next[0:0]$8068 $1\neg_res32$16$next[0:0]$8069 + attribute \src "libresoc.v:153948.5-153948.29" switch \initial - attribute \src "libresoc.v:152070.9-152070.17" + attribute \src "libresoc.v:153948.9-153948.17" case 1'1 case end @@ -319049,18 +321622,18 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$16$next[0:0]$8024 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$16$next[0:0]$8024 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$52 case - assign $1\neg_res32$16$next[0:0]$8024 \neg_res32$16 + assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$16 end sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8023 + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8068 end - connect \$34 $and$libresoc.v:151881$7940_Y + connect \$34 $and$libresoc.v:153759$7985_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -319080,218 +321653,218 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:152104.1-153386.10" +attribute \src "libresoc.v:153982.1-155278.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:153304.3-153322.6" - wire width 4 $0\cr_a$next[3:0]$8143 - attribute \src "libresoc.v:153096.3-153097.25" + attribute \src "libresoc.v:155196.3-155214.6" + wire width 4 $0\cr_a$next[3:0]$8188 + attribute \src "libresoc.v:154988.3-154989.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:153304.3-153322.6" - wire $0\cr_a_ok$next[0:0]$8144 - attribute \src "libresoc.v:153098.3-153099.31" + attribute \src "libresoc.v:155196.3-155214.6" + wire $0\cr_a_ok$next[0:0]$8189 + attribute \src "libresoc.v:154990.3-154991.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:152105.7-152105.20" + attribute \src "libresoc.v:153983.7-153983.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153249.3-153284.6" - wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8106 - attribute \src "libresoc.v:153106.3-153107.53" - wire width 13 $0\mul_op__fn_unit$3[12:0]$8074 - attribute \src "libresoc.v:152410.14-152410.44" - wire width 13 $0\mul_op__fn_unit$3[12:0]$8164 - attribute \src "libresoc.v:153249.3-153284.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8107 - attribute \src "libresoc.v:153108.3-153109.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8076 - attribute \src "libresoc.v:152433.14-152433.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8166 - attribute \src "libresoc.v:153249.3-153284.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8108 - attribute \src "libresoc.v:153110.3-153111.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8078 - attribute \src "libresoc.v:152442.7-152442.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8168 - attribute \src "libresoc.v:153249.3-153284.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8109 - attribute \src "libresoc.v:153126.3-153127.49" - wire width 32 $0\mul_op__insn$13[31:0]$8094 - attribute \src "libresoc.v:152451.14-152451.39" - wire width 32 $0\mul_op__insn$13[31:0]$8170 - attribute \src "libresoc.v:153249.3-153284.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8110 - attribute \src "libresoc.v:153104.3-153105.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8072 - attribute \src "libresoc.v:152608.13-152608.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8172 - attribute \src "libresoc.v:153249.3-153284.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8111 - attribute \src "libresoc.v:153122.3-153123.57" - wire $0\mul_op__is_32bit$11[0:0]$8090 - attribute \src "libresoc.v:152691.7-152691.35" - wire $0\mul_op__is_32bit$11[0:0]$8174 - attribute \src "libresoc.v:153249.3-153284.6" - wire $0\mul_op__is_signed$12$next[0:0]$8112 - attribute \src "libresoc.v:153124.3-153125.59" - wire $0\mul_op__is_signed$12[0:0]$8092 - attribute \src "libresoc.v:152700.7-152700.36" - wire $0\mul_op__is_signed$12[0:0]$8176 - attribute \src "libresoc.v:153249.3-153284.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8113 - attribute \src "libresoc.v:153116.3-153117.51" - wire $0\mul_op__oe__oe$8[0:0]$8084 - attribute \src "libresoc.v:152711.7-152711.32" - wire $0\mul_op__oe__oe$8[0:0]$8178 - attribute \src "libresoc.v:153249.3-153284.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8114 - attribute \src "libresoc.v:153118.3-153119.51" - wire $0\mul_op__oe__ok$9[0:0]$8086 - attribute \src "libresoc.v:152720.7-152720.32" - wire $0\mul_op__oe__ok$9[0:0]$8180 - attribute \src "libresoc.v:153249.3-153284.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8115 - attribute \src "libresoc.v:153114.3-153115.51" - wire $0\mul_op__rc__ok$7[0:0]$8082 - attribute \src "libresoc.v:152729.7-152729.32" - wire $0\mul_op__rc__ok$7[0:0]$8182 - attribute \src "libresoc.v:153249.3-153284.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8116 - attribute \src "libresoc.v:153112.3-153113.51" - wire $0\mul_op__rc__rc$6[0:0]$8080 - attribute \src "libresoc.v:152736.7-152736.32" - wire $0\mul_op__rc__rc$6[0:0]$8184 - attribute \src "libresoc.v:153249.3-153284.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8117 - attribute \src "libresoc.v:153120.3-153121.59" - wire $0\mul_op__write_cr0$10[0:0]$8088 - attribute \src "libresoc.v:152745.7-152745.36" - wire $0\mul_op__write_cr0$10[0:0]$8186 - attribute \src "libresoc.v:153236.3-153248.6" - wire width 2 $0\muxid$1$next[1:0]$8103 - attribute \src "libresoc.v:153128.3-153129.33" - wire width 2 $0\muxid$1[1:0]$8096 - attribute \src "libresoc.v:152754.13-152754.29" - wire width 2 $0\muxid$1[1:0]$8188 - attribute \src "libresoc.v:153285.3-153303.6" - wire width 64 $0\o$14$next[63:0]$8138 - attribute \src "libresoc.v:153100.3-153101.27" - wire width 64 $0\o$14[63:0]$8069 - attribute \src "libresoc.v:152775.14-152775.43" - wire width 64 $0\o$14[63:0]$8190 - attribute \src "libresoc.v:153285.3-153303.6" - wire $0\o_ok$next[0:0]$8137 - attribute \src "libresoc.v:153102.3-153103.25" + attribute \src "libresoc.v:155141.3-155176.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8151 + attribute \src "libresoc.v:154998.3-154999.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8119 + attribute \src "libresoc.v:154294.14-154294.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8209 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8152 + attribute \src "libresoc.v:155000.3-155001.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8121 + attribute \src "libresoc.v:154318.14-154318.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8211 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8153 + attribute \src "libresoc.v:155002.3-155003.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8123 + attribute \src "libresoc.v:154327.7-154327.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8213 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8154 + attribute \src "libresoc.v:155018.3-155019.49" + wire width 32 $0\mul_op__insn$13[31:0]$8139 + attribute \src "libresoc.v:154336.14-154336.39" + wire width 32 $0\mul_op__insn$13[31:0]$8215 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8155 + attribute \src "libresoc.v:154996.3-154997.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8117 + attribute \src "libresoc.v:154495.13-154495.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8217 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8156 + attribute \src "libresoc.v:155014.3-155015.57" + wire $0\mul_op__is_32bit$11[0:0]$8135 + attribute \src "libresoc.v:154579.7-154579.35" + wire $0\mul_op__is_32bit$11[0:0]$8219 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__is_signed$12$next[0:0]$8157 + attribute \src "libresoc.v:155016.3-155017.59" + wire $0\mul_op__is_signed$12[0:0]$8137 + attribute \src "libresoc.v:154588.7-154588.36" + wire $0\mul_op__is_signed$12[0:0]$8221 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8158 + attribute \src "libresoc.v:155008.3-155009.51" + wire $0\mul_op__oe__oe$8[0:0]$8129 + attribute \src "libresoc.v:154599.7-154599.32" + wire $0\mul_op__oe__oe$8[0:0]$8223 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8159 + attribute \src "libresoc.v:155010.3-155011.51" + wire $0\mul_op__oe__ok$9[0:0]$8131 + attribute \src "libresoc.v:154608.7-154608.32" + wire $0\mul_op__oe__ok$9[0:0]$8225 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8160 + attribute \src "libresoc.v:155006.3-155007.51" + wire $0\mul_op__rc__ok$7[0:0]$8127 + attribute \src "libresoc.v:154617.7-154617.32" + wire $0\mul_op__rc__ok$7[0:0]$8227 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8161 + attribute \src "libresoc.v:155004.3-155005.51" + wire $0\mul_op__rc__rc$6[0:0]$8125 + attribute \src "libresoc.v:154624.7-154624.32" + wire $0\mul_op__rc__rc$6[0:0]$8229 + attribute \src "libresoc.v:155141.3-155176.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8162 + attribute \src "libresoc.v:155012.3-155013.59" + wire $0\mul_op__write_cr0$10[0:0]$8133 + attribute \src "libresoc.v:154633.7-154633.36" + wire $0\mul_op__write_cr0$10[0:0]$8231 + attribute \src "libresoc.v:155128.3-155140.6" + wire width 2 $0\muxid$1$next[1:0]$8148 + attribute \src "libresoc.v:155020.3-155021.33" + wire width 2 $0\muxid$1[1:0]$8141 + attribute \src "libresoc.v:154642.13-154642.29" + wire width 2 $0\muxid$1[1:0]$8233 + attribute \src "libresoc.v:155177.3-155195.6" + wire width 64 $0\o$14$next[63:0]$8183 + attribute \src "libresoc.v:154992.3-154993.27" + wire width 64 $0\o$14[63:0]$8114 + attribute \src "libresoc.v:154663.14-154663.43" + wire width 64 $0\o$14[63:0]$8235 + attribute \src "libresoc.v:155177.3-155195.6" + wire $0\o_ok$next[0:0]$8182 + attribute \src "libresoc.v:154994.3-154995.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:153218.3-153235.6" - wire $0\r_busy$next[0:0]$8099 - attribute \src "libresoc.v:153130.3-153131.29" + attribute \src "libresoc.v:155110.3-155127.6" + wire $0\r_busy$next[0:0]$8144 + attribute \src "libresoc.v:155022.3-155023.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:153323.3-153341.6" - wire width 2 $0\xer_ov$next[1:0]$8149 - attribute \src "libresoc.v:153092.3-153093.29" + attribute \src "libresoc.v:155215.3-155233.6" + wire width 2 $0\xer_ov$next[1:0]$8194 + attribute \src "libresoc.v:154984.3-154985.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:153323.3-153341.6" - wire $0\xer_ov_ok$next[0:0]$8150 - attribute \src "libresoc.v:153094.3-153095.35" + attribute \src "libresoc.v:155215.3-155233.6" + wire $0\xer_ov_ok$next[0:0]$8195 + attribute \src "libresoc.v:154986.3-154987.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:153342.3-153360.6" - wire $0\xer_so$15$next[0:0]$8156 - attribute \src "libresoc.v:153088.3-153089.37" - wire $0\xer_so$15[0:0]$8062 - attribute \src "libresoc.v:153073.7-153073.25" - wire $0\xer_so$15[0:0]$8196 - attribute \src "libresoc.v:153342.3-153360.6" - wire $0\xer_so_ok$next[0:0]$8155 - attribute \src "libresoc.v:153090.3-153091.35" + attribute \src "libresoc.v:155234.3-155252.6" + wire $0\xer_so$15$next[0:0]$8201 + attribute \src "libresoc.v:154980.3-154981.37" + wire $0\xer_so$15[0:0]$8107 + attribute \src "libresoc.v:154965.7-154965.25" + wire $0\xer_so$15[0:0]$8241 + attribute \src "libresoc.v:155234.3-155252.6" + wire $0\xer_so_ok$next[0:0]$8200 + attribute \src "libresoc.v:154982.3-154983.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:153304.3-153322.6" - wire width 4 $1\cr_a$next[3:0]$8145 - attribute \src "libresoc.v:152114.13-152114.24" + attribute \src "libresoc.v:155196.3-155214.6" + wire width 4 $1\cr_a$next[3:0]$8190 + attribute \src "libresoc.v:153992.13-153992.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:153304.3-153322.6" - wire $1\cr_a_ok$next[0:0]$8146 - attribute \src "libresoc.v:152123.7-152123.21" + attribute \src "libresoc.v:155196.3-155214.6" + wire $1\cr_a_ok$next[0:0]$8191 + attribute \src "libresoc.v:154001.7-154001.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:153249.3-153284.6" - wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8118 - attribute \src "libresoc.v:153249.3-153284.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8119 - attribute \src "libresoc.v:153249.3-153284.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8120 - attribute \src "libresoc.v:153249.3-153284.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8121 - attribute \src "libresoc.v:153249.3-153284.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8122 - attribute \src "libresoc.v:153249.3-153284.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8123 - attribute \src "libresoc.v:153249.3-153284.6" - wire $1\mul_op__is_signed$12$next[0:0]$8124 - attribute \src "libresoc.v:153249.3-153284.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8125 - attribute \src "libresoc.v:153249.3-153284.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8126 - attribute \src "libresoc.v:153249.3-153284.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8127 - attribute \src "libresoc.v:153249.3-153284.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8128 - attribute \src "libresoc.v:153249.3-153284.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8129 - attribute \src "libresoc.v:153236.3-153248.6" - wire width 2 $1\muxid$1$next[1:0]$8104 - attribute \src "libresoc.v:153285.3-153303.6" - wire width 64 $1\o$14$next[63:0]$8140 - attribute \src "libresoc.v:153285.3-153303.6" - wire $1\o_ok$next[0:0]$8139 - attribute \src "libresoc.v:152782.7-152782.18" + attribute \src "libresoc.v:155141.3-155176.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8163 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8164 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8165 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8166 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8167 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8168 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__is_signed$12$next[0:0]$8169 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8170 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8171 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8172 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8173 + attribute \src "libresoc.v:155141.3-155176.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8174 + attribute \src "libresoc.v:155128.3-155140.6" + wire width 2 $1\muxid$1$next[1:0]$8149 + attribute \src "libresoc.v:155177.3-155195.6" + wire width 64 $1\o$14$next[63:0]$8185 + attribute \src "libresoc.v:155177.3-155195.6" + wire $1\o_ok$next[0:0]$8184 + attribute \src "libresoc.v:154670.7-154670.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:153218.3-153235.6" - wire $1\r_busy$next[0:0]$8100 - attribute \src "libresoc.v:153050.7-153050.20" + attribute \src "libresoc.v:155110.3-155127.6" + wire $1\r_busy$next[0:0]$8145 + attribute \src "libresoc.v:154942.7-154942.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:153323.3-153341.6" - wire width 2 $1\xer_ov$next[1:0]$8151 - attribute \src "libresoc.v:153055.13-153055.26" + attribute \src "libresoc.v:155215.3-155233.6" + wire width 2 $1\xer_ov$next[1:0]$8196 + attribute \src "libresoc.v:154947.13-154947.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:153323.3-153341.6" - wire $1\xer_ov_ok$next[0:0]$8152 - attribute \src "libresoc.v:153062.7-153062.23" + attribute \src "libresoc.v:155215.3-155233.6" + wire $1\xer_ov_ok$next[0:0]$8197 + attribute \src "libresoc.v:154954.7-154954.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:153342.3-153360.6" - wire $1\xer_so$15$next[0:0]$8158 - attribute \src "libresoc.v:153342.3-153360.6" - wire $1\xer_so_ok$next[0:0]$8157 - attribute \src "libresoc.v:153080.7-153080.23" + attribute \src "libresoc.v:155234.3-155252.6" + wire $1\xer_so$15$next[0:0]$8203 + attribute \src "libresoc.v:155234.3-155252.6" + wire $1\xer_so_ok$next[0:0]$8202 + attribute \src "libresoc.v:154972.7-154972.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:153304.3-153322.6" - wire $2\cr_a_ok$next[0:0]$8147 - attribute \src "libresoc.v:153249.3-153284.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8130 - attribute \src "libresoc.v:153249.3-153284.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8131 - attribute \src "libresoc.v:153249.3-153284.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8132 - attribute \src "libresoc.v:153249.3-153284.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8133 - attribute \src "libresoc.v:153249.3-153284.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8134 - attribute \src "libresoc.v:153249.3-153284.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8135 - attribute \src "libresoc.v:153285.3-153303.6" - wire $2\o_ok$next[0:0]$8141 - attribute \src "libresoc.v:153218.3-153235.6" - wire $2\r_busy$next[0:0]$8101 - attribute \src "libresoc.v:153323.3-153341.6" - wire $2\xer_ov_ok$next[0:0]$8153 - attribute \src "libresoc.v:153342.3-153360.6" - wire $2\xer_so_ok$next[0:0]$8159 - attribute \src "libresoc.v:153087.18-153087.118" - wire $and$libresoc.v:153087$8060_Y + attribute \src "libresoc.v:155196.3-155214.6" + wire $2\cr_a_ok$next[0:0]$8192 + attribute \src "libresoc.v:155141.3-155176.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8175 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8176 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8177 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8178 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8179 + attribute \src "libresoc.v:155141.3-155176.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8180 + attribute \src "libresoc.v:155177.3-155195.6" + wire $2\o_ok$next[0:0]$8186 + attribute \src "libresoc.v:155110.3-155127.6" + wire $2\r_busy$next[0:0]$8146 + attribute \src "libresoc.v:155215.3-155233.6" + wire $2\xer_ov_ok$next[0:0]$8198 + attribute \src "libresoc.v:155234.3-155252.6" + wire $2\xer_so_ok$next[0:0]$8204 + attribute \src "libresoc.v:154979.18-154979.118" + wire $and$libresoc.v:154979$8105_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 38 \cr_a @@ -319311,40 +321884,42 @@ module \mul_pipe3 wire \cr_a_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:152105.7-152105.15" + attribute \src "libresoc.v:153983.7-153983.15" wire \initial attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul3_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul3_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul3_mul_op__fn_unit$18 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul3_mul_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -319431,6 +322006,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul3_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -319507,6 +322083,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul3_mul_op__insn_type$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -319560,55 +322137,58 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul3_xer_so_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$60 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \mul_op__fn_unit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -319707,6 +322287,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -319783,6 +322364,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -319861,6 +322443,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -319960,37 +322543,39 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_cr_a_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_mul_op__fn_unit$33 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_mul_op__fn_unit$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -320077,6 +322662,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -320153,6 +322739,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_mul_op__insn_type$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -320250,7 +322837,7 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:153087$8060 + cell $and $and$libresoc.v:154979$8105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -320258,10 +322845,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:153087$8060_Y + connect \Y $and$libresoc.v:154979$8105_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:153132.8-153168.4" + attribute \src "libresoc.v:155024.8-155060.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -320300,13 +322887,13 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:153169.10-153172.4" + attribute \src "libresoc.v:155061.10-155064.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:153173.16-153213.4" + attribute \src "libresoc.v:155065.16-155105.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 @@ -320349,358 +322936,358 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:153214.10-153217.4" + attribute \src "libresoc.v:155106.10-155109.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:152105.7-152105.20" - process $proc$libresoc.v:152105$8160 + attribute \src "libresoc.v:153983.7-153983.20" + process $proc$libresoc.v:153983$8205 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:152114.13-152114.24" - process $proc$libresoc.v:152114$8161 + attribute \src "libresoc.v:153992.13-153992.24" + process $proc$libresoc.v:153992$8206 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:152123.7-152123.21" - process $proc$libresoc.v:152123$8162 + attribute \src "libresoc.v:154001.7-154001.21" + process $proc$libresoc.v:154001$8207 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:152410.14-152410.44" - process $proc$libresoc.v:152410$8163 + attribute \src "libresoc.v:154294.14-154294.44" + process $proc$libresoc.v:154294$8208 assign { } { } - assign $0\mul_op__fn_unit$3[12:0]$8164 13'0000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8209 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8164 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8209 end - attribute \src "libresoc.v:152433.14-152433.63" - process $proc$libresoc.v:152433$8165 + attribute \src "libresoc.v:154318.14-154318.63" + process $proc$libresoc.v:154318$8210 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8166 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8211 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8166 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8211 end - attribute \src "libresoc.v:152442.7-152442.38" - process $proc$libresoc.v:152442$8167 + attribute \src "libresoc.v:154327.7-154327.38" + process $proc$libresoc.v:154327$8212 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8168 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8213 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8168 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8213 end - attribute \src "libresoc.v:152451.14-152451.39" - process $proc$libresoc.v:152451$8169 + attribute \src "libresoc.v:154336.14-154336.39" + process $proc$libresoc.v:154336$8214 assign { } { } - assign $0\mul_op__insn$13[31:0]$8170 0 + assign $0\mul_op__insn$13[31:0]$8215 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8170 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8215 end - attribute \src "libresoc.v:152608.13-152608.42" - process $proc$libresoc.v:152608$8171 + attribute \src "libresoc.v:154495.13-154495.42" + process $proc$libresoc.v:154495$8216 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8172 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8217 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8172 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8217 end - attribute \src "libresoc.v:152691.7-152691.35" - process $proc$libresoc.v:152691$8173 + attribute \src "libresoc.v:154579.7-154579.35" + process $proc$libresoc.v:154579$8218 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8174 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8219 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8174 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8219 end - attribute \src "libresoc.v:152700.7-152700.36" - process $proc$libresoc.v:152700$8175 + attribute \src "libresoc.v:154588.7-154588.36" + process $proc$libresoc.v:154588$8220 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8176 1'0 + assign $0\mul_op__is_signed$12[0:0]$8221 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8176 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8221 end - attribute \src "libresoc.v:152711.7-152711.32" - process $proc$libresoc.v:152711$8177 + attribute \src "libresoc.v:154599.7-154599.32" + process $proc$libresoc.v:154599$8222 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8178 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8223 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8178 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8223 end - attribute \src "libresoc.v:152720.7-152720.32" - process $proc$libresoc.v:152720$8179 + attribute \src "libresoc.v:154608.7-154608.32" + process $proc$libresoc.v:154608$8224 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8180 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8225 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8180 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8225 end - attribute \src "libresoc.v:152729.7-152729.32" - process $proc$libresoc.v:152729$8181 + attribute \src "libresoc.v:154617.7-154617.32" + process $proc$libresoc.v:154617$8226 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8182 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8227 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8182 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8227 end - attribute \src "libresoc.v:152736.7-152736.32" - process $proc$libresoc.v:152736$8183 + attribute \src "libresoc.v:154624.7-154624.32" + process $proc$libresoc.v:154624$8228 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8184 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8229 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8184 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8229 end - attribute \src "libresoc.v:152745.7-152745.36" - process $proc$libresoc.v:152745$8185 + attribute \src "libresoc.v:154633.7-154633.36" + process $proc$libresoc.v:154633$8230 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8186 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8231 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8186 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8231 end - attribute \src "libresoc.v:152754.13-152754.29" - process $proc$libresoc.v:152754$8187 + attribute \src "libresoc.v:154642.13-154642.29" + process $proc$libresoc.v:154642$8232 assign { } { } - assign $0\muxid$1[1:0]$8188 2'00 + assign $0\muxid$1[1:0]$8233 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8188 + update \muxid$1 $0\muxid$1[1:0]$8233 end - attribute \src "libresoc.v:152775.14-152775.43" - process $proc$libresoc.v:152775$8189 + attribute \src "libresoc.v:154663.14-154663.43" + process $proc$libresoc.v:154663$8234 assign { } { } - assign $0\o$14[63:0]$8190 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$14[63:0]$8235 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$14 $0\o$14[63:0]$8190 + update \o$14 $0\o$14[63:0]$8235 end - attribute \src "libresoc.v:152782.7-152782.18" - process $proc$libresoc.v:152782$8191 + attribute \src "libresoc.v:154670.7-154670.18" + process $proc$libresoc.v:154670$8236 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:153050.7-153050.20" - process $proc$libresoc.v:153050$8192 + attribute \src "libresoc.v:154942.7-154942.20" + process $proc$libresoc.v:154942$8237 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:153055.13-153055.26" - process $proc$libresoc.v:153055$8193 + attribute \src "libresoc.v:154947.13-154947.26" + process $proc$libresoc.v:154947$8238 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:153062.7-153062.23" - process $proc$libresoc.v:153062$8194 + attribute \src "libresoc.v:154954.7-154954.23" + process $proc$libresoc.v:154954$8239 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:153073.7-153073.25" - process $proc$libresoc.v:153073$8195 + attribute \src "libresoc.v:154965.7-154965.25" + process $proc$libresoc.v:154965$8240 assign { } { } - assign $0\xer_so$15[0:0]$8196 1'0 + assign $0\xer_so$15[0:0]$8241 1'0 sync always sync init - update \xer_so$15 $0\xer_so$15[0:0]$8196 + update \xer_so$15 $0\xer_so$15[0:0]$8241 end - attribute \src "libresoc.v:153080.7-153080.23" - process $proc$libresoc.v:153080$8197 + attribute \src "libresoc.v:154972.7-154972.23" + process $proc$libresoc.v:154972$8242 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:153088.3-153089.37" - process $proc$libresoc.v:153088$8061 + attribute \src "libresoc.v:154980.3-154981.37" + process $proc$libresoc.v:154980$8106 assign { } { } - assign $0\xer_so$15[0:0]$8062 \xer_so$15$next + assign $0\xer_so$15[0:0]$8107 \xer_so$15$next sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$8062 + update \xer_so$15 $0\xer_so$15[0:0]$8107 end - attribute \src "libresoc.v:153090.3-153091.35" - process $proc$libresoc.v:153090$8063 + attribute \src "libresoc.v:154982.3-154983.35" + process $proc$libresoc.v:154982$8108 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:153092.3-153093.29" - process $proc$libresoc.v:153092$8064 + attribute \src "libresoc.v:154984.3-154985.29" + process $proc$libresoc.v:154984$8109 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:153094.3-153095.35" - process $proc$libresoc.v:153094$8065 + attribute \src "libresoc.v:154986.3-154987.35" + process $proc$libresoc.v:154986$8110 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:153096.3-153097.25" - process $proc$libresoc.v:153096$8066 + attribute \src "libresoc.v:154988.3-154989.25" + process $proc$libresoc.v:154988$8111 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:153098.3-153099.31" - process $proc$libresoc.v:153098$8067 + attribute \src "libresoc.v:154990.3-154991.31" + process $proc$libresoc.v:154990$8112 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:153100.3-153101.27" - process $proc$libresoc.v:153100$8068 + attribute \src "libresoc.v:154992.3-154993.27" + process $proc$libresoc.v:154992$8113 assign { } { } - assign $0\o$14[63:0]$8069 \o$14$next + assign $0\o$14[63:0]$8114 \o$14$next sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$8069 + update \o$14 $0\o$14[63:0]$8114 end - attribute \src "libresoc.v:153102.3-153103.25" - process $proc$libresoc.v:153102$8070 + attribute \src "libresoc.v:154994.3-154995.25" + process $proc$libresoc.v:154994$8115 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:153104.3-153105.57" - process $proc$libresoc.v:153104$8071 + attribute \src "libresoc.v:154996.3-154997.57" + process $proc$libresoc.v:154996$8116 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8072 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8117 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8072 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8117 end - attribute \src "libresoc.v:153106.3-153107.53" - process $proc$libresoc.v:153106$8073 + attribute \src "libresoc.v:154998.3-154999.53" + process $proc$libresoc.v:154998$8118 assign { } { } - assign $0\mul_op__fn_unit$3[12:0]$8074 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8119 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8074 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8119 end - attribute \src "libresoc.v:153108.3-153109.67" - process $proc$libresoc.v:153108$8075 + attribute \src "libresoc.v:155000.3-155001.67" + process $proc$libresoc.v:155000$8120 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8076 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8121 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8076 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8121 end - attribute \src "libresoc.v:153110.3-153111.63" - process $proc$libresoc.v:153110$8077 + attribute \src "libresoc.v:155002.3-155003.63" + process $proc$libresoc.v:155002$8122 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8078 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8123 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8078 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8123 end - attribute \src "libresoc.v:153112.3-153113.51" - process $proc$libresoc.v:153112$8079 + attribute \src "libresoc.v:155004.3-155005.51" + process $proc$libresoc.v:155004$8124 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8080 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8125 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8080 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8125 end - attribute \src "libresoc.v:153114.3-153115.51" - process $proc$libresoc.v:153114$8081 + attribute \src "libresoc.v:155006.3-155007.51" + process $proc$libresoc.v:155006$8126 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8082 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8127 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8082 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8127 end - attribute \src "libresoc.v:153116.3-153117.51" - process $proc$libresoc.v:153116$8083 + attribute \src "libresoc.v:155008.3-155009.51" + process $proc$libresoc.v:155008$8128 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8084 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8129 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8084 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8129 end - attribute \src "libresoc.v:153118.3-153119.51" - process $proc$libresoc.v:153118$8085 + attribute \src "libresoc.v:155010.3-155011.51" + process $proc$libresoc.v:155010$8130 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8086 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8131 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8086 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8131 end - attribute \src "libresoc.v:153120.3-153121.59" - process $proc$libresoc.v:153120$8087 + attribute \src "libresoc.v:155012.3-155013.59" + process $proc$libresoc.v:155012$8132 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8088 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8133 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8088 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8133 end - attribute \src "libresoc.v:153122.3-153123.57" - process $proc$libresoc.v:153122$8089 + attribute \src "libresoc.v:155014.3-155015.57" + process $proc$libresoc.v:155014$8134 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8090 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8135 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8090 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8135 end - attribute \src "libresoc.v:153124.3-153125.59" - process $proc$libresoc.v:153124$8091 + attribute \src "libresoc.v:155016.3-155017.59" + process $proc$libresoc.v:155016$8136 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8092 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8137 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8092 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8137 end - attribute \src "libresoc.v:153126.3-153127.49" - process $proc$libresoc.v:153126$8093 + attribute \src "libresoc.v:155018.3-155019.49" + process $proc$libresoc.v:155018$8138 assign { } { } - assign $0\mul_op__insn$13[31:0]$8094 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8139 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8094 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8139 end - attribute \src "libresoc.v:153128.3-153129.33" - process $proc$libresoc.v:153128$8095 + attribute \src "libresoc.v:155020.3-155021.33" + process $proc$libresoc.v:155020$8140 assign { } { } - assign $0\muxid$1[1:0]$8096 \muxid$1$next + assign $0\muxid$1[1:0]$8141 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8096 + update \muxid$1 $0\muxid$1[1:0]$8141 end - attribute \src "libresoc.v:153130.3-153131.29" - process $proc$libresoc.v:153130$8097 + attribute \src "libresoc.v:155022.3-155023.29" + process $proc$libresoc.v:155022$8142 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:153218.3-153235.6" - process $proc$libresoc.v:153218$8098 + attribute \src "libresoc.v:155110.3-155127.6" + process $proc$libresoc.v:155110$8143 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8099 $2\r_busy$next[0:0]$8101 - attribute \src "libresoc.v:153219.5-153219.29" + assign $0\r_busy$next[0:0]$8144 $2\r_busy$next[0:0]$8146 + attribute \src "libresoc.v:155111.5-155111.29" switch \initial - attribute \src "libresoc.v:153219.9-153219.17" + attribute \src "libresoc.v:155111.9-155111.17" case 1'1 case end @@ -320709,34 +323296,34 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8100 1'1 + assign $1\r_busy$next[0:0]$8145 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8100 1'0 + assign $1\r_busy$next[0:0]$8145 1'0 case - assign $1\r_busy$next[0:0]$8100 \r_busy + assign $1\r_busy$next[0:0]$8145 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8101 1'0 + assign $2\r_busy$next[0:0]$8146 1'0 case - assign $2\r_busy$next[0:0]$8101 $1\r_busy$next[0:0]$8100 + assign $2\r_busy$next[0:0]$8146 $1\r_busy$next[0:0]$8145 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8099 + update \r_busy$next $0\r_busy$next[0:0]$8144 end - attribute \src "libresoc.v:153236.3-153248.6" - process $proc$libresoc.v:153236$8102 + attribute \src "libresoc.v:155128.3-155140.6" + process $proc$libresoc.v:155128$8147 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8103 $1\muxid$1$next[1:0]$8104 - attribute \src "libresoc.v:153237.5-153237.29" + assign $0\muxid$1$next[1:0]$8148 $1\muxid$1$next[1:0]$8149 + attribute \src "libresoc.v:155129.5-155129.29" switch \initial - attribute \src "libresoc.v:153237.9-153237.17" + attribute \src "libresoc.v:155129.9-155129.17" case 1'1 case end @@ -320745,19 +323332,19 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8104 \muxid$58 + assign $1\muxid$1$next[1:0]$8149 \muxid$58 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8104 \muxid$58 + assign $1\muxid$1$next[1:0]$8149 \muxid$58 case - assign $1\muxid$1$next[1:0]$8104 \muxid$1 + assign $1\muxid$1$next[1:0]$8149 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8103 + update \muxid$1$next $0\muxid$1$next[1:0]$8148 end - attribute \src "libresoc.v:153249.3-153284.6" - process $proc$libresoc.v:153249$8105 + attribute \src "libresoc.v:155141.3-155176.6" + process $proc$libresoc.v:155141$8150 assign { } { } assign { } { } assign { } { } @@ -320782,27 +323369,27 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[12:0]$8106 $1\mul_op__fn_unit$3$next[12:0]$8118 + assign $0\mul_op__fn_unit$3$next[13:0]$8151 $1\mul_op__fn_unit$3$next[13:0]$8163 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8109 $1\mul_op__insn$13$next[31:0]$8121 - assign $0\mul_op__insn_type$2$next[6:0]$8110 $1\mul_op__insn_type$2$next[6:0]$8122 - assign $0\mul_op__is_32bit$11$next[0:0]$8111 $1\mul_op__is_32bit$11$next[0:0]$8123 - assign $0\mul_op__is_signed$12$next[0:0]$8112 $1\mul_op__is_signed$12$next[0:0]$8124 + assign $0\mul_op__insn$13$next[31:0]$8154 $1\mul_op__insn$13$next[31:0]$8166 + assign $0\mul_op__insn_type$2$next[6:0]$8155 $1\mul_op__insn_type$2$next[6:0]$8167 + assign $0\mul_op__is_32bit$11$next[0:0]$8156 $1\mul_op__is_32bit$11$next[0:0]$8168 + assign $0\mul_op__is_signed$12$next[0:0]$8157 $1\mul_op__is_signed$12$next[0:0]$8169 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8117 $1\mul_op__write_cr0$10$next[0:0]$8129 - assign $0\mul_op__imm_data__data$4$next[63:0]$8107 $2\mul_op__imm_data__data$4$next[63:0]$8130 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8108 $2\mul_op__imm_data__ok$5$next[0:0]$8131 - assign $0\mul_op__oe__oe$8$next[0:0]$8113 $2\mul_op__oe__oe$8$next[0:0]$8132 - assign $0\mul_op__oe__ok$9$next[0:0]$8114 $2\mul_op__oe__ok$9$next[0:0]$8133 - assign $0\mul_op__rc__ok$7$next[0:0]$8115 $2\mul_op__rc__ok$7$next[0:0]$8134 - assign $0\mul_op__rc__rc$6$next[0:0]$8116 $2\mul_op__rc__rc$6$next[0:0]$8135 - attribute \src "libresoc.v:153250.5-153250.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8162 $1\mul_op__write_cr0$10$next[0:0]$8174 + assign $0\mul_op__imm_data__data$4$next[63:0]$8152 $2\mul_op__imm_data__data$4$next[63:0]$8175 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8153 $2\mul_op__imm_data__ok$5$next[0:0]$8176 + assign $0\mul_op__oe__oe$8$next[0:0]$8158 $2\mul_op__oe__oe$8$next[0:0]$8177 + assign $0\mul_op__oe__ok$9$next[0:0]$8159 $2\mul_op__oe__ok$9$next[0:0]$8178 + assign $0\mul_op__rc__ok$7$next[0:0]$8160 $2\mul_op__rc__ok$7$next[0:0]$8179 + assign $0\mul_op__rc__rc$6$next[0:0]$8161 $2\mul_op__rc__rc$6$next[0:0]$8180 + attribute \src "libresoc.v:155142.5-155142.29" switch \initial - attribute \src "libresoc.v:153250.9-153250.17" + attribute \src "libresoc.v:155142.9-155142.17" case 1'1 case end @@ -320822,7 +323409,7 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8121 $1\mul_op__is_signed$12$next[0:0]$8124 $1\mul_op__is_32bit$11$next[0:0]$8123 $1\mul_op__write_cr0$10$next[0:0]$8129 $1\mul_op__oe__ok$9$next[0:0]$8126 $1\mul_op__oe__oe$8$next[0:0]$8125 $1\mul_op__rc__ok$7$next[0:0]$8127 $1\mul_op__rc__rc$6$next[0:0]$8128 $1\mul_op__imm_data__ok$5$next[0:0]$8120 $1\mul_op__imm_data__data$4$next[63:0]$8119 $1\mul_op__fn_unit$3$next[12:0]$8118 $1\mul_op__insn_type$2$next[6:0]$8122 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8166 $1\mul_op__is_signed$12$next[0:0]$8169 $1\mul_op__is_32bit$11$next[0:0]$8168 $1\mul_op__write_cr0$10$next[0:0]$8174 $1\mul_op__oe__ok$9$next[0:0]$8171 $1\mul_op__oe__oe$8$next[0:0]$8170 $1\mul_op__rc__ok$7$next[0:0]$8172 $1\mul_op__rc__rc$6$next[0:0]$8173 $1\mul_op__imm_data__ok$5$next[0:0]$8165 $1\mul_op__imm_data__data$4$next[63:0]$8164 $1\mul_op__fn_unit$3$next[13:0]$8163 $1\mul_op__insn_type$2$next[6:0]$8167 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -320837,20 +323424,20 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8121 $1\mul_op__is_signed$12$next[0:0]$8124 $1\mul_op__is_32bit$11$next[0:0]$8123 $1\mul_op__write_cr0$10$next[0:0]$8129 $1\mul_op__oe__ok$9$next[0:0]$8126 $1\mul_op__oe__oe$8$next[0:0]$8125 $1\mul_op__rc__ok$7$next[0:0]$8127 $1\mul_op__rc__rc$6$next[0:0]$8128 $1\mul_op__imm_data__ok$5$next[0:0]$8120 $1\mul_op__imm_data__data$4$next[63:0]$8119 $1\mul_op__fn_unit$3$next[12:0]$8118 $1\mul_op__insn_type$2$next[6:0]$8122 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8166 $1\mul_op__is_signed$12$next[0:0]$8169 $1\mul_op__is_32bit$11$next[0:0]$8168 $1\mul_op__write_cr0$10$next[0:0]$8174 $1\mul_op__oe__ok$9$next[0:0]$8171 $1\mul_op__oe__oe$8$next[0:0]$8170 $1\mul_op__rc__ok$7$next[0:0]$8172 $1\mul_op__rc__rc$6$next[0:0]$8173 $1\mul_op__imm_data__ok$5$next[0:0]$8165 $1\mul_op__imm_data__data$4$next[63:0]$8164 $1\mul_op__fn_unit$3$next[13:0]$8163 $1\mul_op__insn_type$2$next[6:0]$8167 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } case - assign $1\mul_op__fn_unit$3$next[12:0]$8118 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8119 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8120 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8121 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8122 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8123 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8124 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8125 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8126 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8127 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8128 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8129 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8163 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8164 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8165 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8166 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8167 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8168 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8169 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8170 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8171 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8172 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8173 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8174 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -320862,46 +323449,46 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8130 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8131 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8135 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8134 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8132 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8133 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8175 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8176 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8180 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8179 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8177 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8178 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8130 $1\mul_op__imm_data__data$4$next[63:0]$8119 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8131 $1\mul_op__imm_data__ok$5$next[0:0]$8120 - assign $2\mul_op__oe__oe$8$next[0:0]$8132 $1\mul_op__oe__oe$8$next[0:0]$8125 - assign $2\mul_op__oe__ok$9$next[0:0]$8133 $1\mul_op__oe__ok$9$next[0:0]$8126 - assign $2\mul_op__rc__ok$7$next[0:0]$8134 $1\mul_op__rc__ok$7$next[0:0]$8127 - assign $2\mul_op__rc__rc$6$next[0:0]$8135 $1\mul_op__rc__rc$6$next[0:0]$8128 + assign $2\mul_op__imm_data__data$4$next[63:0]$8175 $1\mul_op__imm_data__data$4$next[63:0]$8164 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8176 $1\mul_op__imm_data__ok$5$next[0:0]$8165 + assign $2\mul_op__oe__oe$8$next[0:0]$8177 $1\mul_op__oe__oe$8$next[0:0]$8170 + assign $2\mul_op__oe__ok$9$next[0:0]$8178 $1\mul_op__oe__ok$9$next[0:0]$8171 + assign $2\mul_op__rc__ok$7$next[0:0]$8179 $1\mul_op__rc__ok$7$next[0:0]$8172 + assign $2\mul_op__rc__rc$6$next[0:0]$8180 $1\mul_op__rc__rc$6$next[0:0]$8173 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8106 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8107 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8108 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8109 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8110 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8111 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8112 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8113 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8114 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8115 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8116 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8117 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8151 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8152 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8153 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8154 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8155 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8156 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8157 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8158 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8159 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8160 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8161 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8162 end - attribute \src "libresoc.v:153285.3-153303.6" - process $proc$libresoc.v:153285$8136 + attribute \src "libresoc.v:155177.3-155195.6" + process $proc$libresoc.v:155177$8181 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$14$next[63:0]$8138 $1\o$14$next[63:0]$8140 - assign $0\o_ok$next[0:0]$8137 $2\o_ok$next[0:0]$8141 - attribute \src "libresoc.v:153286.5-153286.29" + assign $0\o$14$next[63:0]$8183 $1\o$14$next[63:0]$8185 + assign $0\o_ok$next[0:0]$8182 $2\o_ok$next[0:0]$8186 + attribute \src "libresoc.v:155178.5-155178.29" switch \initial - attribute \src "libresoc.v:153286.9-153286.17" + attribute \src "libresoc.v:155178.9-155178.17" case 1'1 case end @@ -320911,41 +323498,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8139 $1\o$14$next[63:0]$8140 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8184 $1\o$14$next[63:0]$8185 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8139 $1\o$14$next[63:0]$8140 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8184 $1\o$14$next[63:0]$8185 } { \o_ok$72 \o$71 } case - assign $1\o_ok$next[0:0]$8139 \o_ok - assign $1\o$14$next[63:0]$8140 \o$14 + assign $1\o_ok$next[0:0]$8184 \o_ok + assign $1\o$14$next[63:0]$8185 \o$14 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8141 1'0 + assign $2\o_ok$next[0:0]$8186 1'0 case - assign $2\o_ok$next[0:0]$8141 $1\o_ok$next[0:0]$8139 + assign $2\o_ok$next[0:0]$8186 $1\o_ok$next[0:0]$8184 end sync always - update \o_ok$next $0\o_ok$next[0:0]$8137 - update \o$14$next $0\o$14$next[63:0]$8138 + update \o_ok$next $0\o_ok$next[0:0]$8182 + update \o$14$next $0\o$14$next[63:0]$8183 end - attribute \src "libresoc.v:153304.3-153322.6" - process $proc$libresoc.v:153304$8142 + attribute \src "libresoc.v:155196.3-155214.6" + process $proc$libresoc.v:155196$8187 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8143 $1\cr_a$next[3:0]$8145 + assign $0\cr_a$next[3:0]$8188 $1\cr_a$next[3:0]$8190 assign { } { } - assign $0\cr_a_ok$next[0:0]$8144 $2\cr_a_ok$next[0:0]$8147 - attribute \src "libresoc.v:153305.5-153305.29" + assign $0\cr_a_ok$next[0:0]$8189 $2\cr_a_ok$next[0:0]$8192 + attribute \src "libresoc.v:155197.5-155197.29" switch \initial - attribute \src "libresoc.v:153305.9-153305.17" + attribute \src "libresoc.v:155197.9-155197.17" case 1'1 case end @@ -320955,41 +323542,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8146 $1\cr_a$next[3:0]$8145 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8191 $1\cr_a$next[3:0]$8190 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8146 $1\cr_a$next[3:0]$8145 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8191 $1\cr_a$next[3:0]$8190 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$next[3:0]$8145 \cr_a - assign $1\cr_a_ok$next[0:0]$8146 \cr_a_ok + assign $1\cr_a$next[3:0]$8190 \cr_a + assign $1\cr_a_ok$next[0:0]$8191 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8147 1'0 + assign $2\cr_a_ok$next[0:0]$8192 1'0 case - assign $2\cr_a_ok$next[0:0]$8147 $1\cr_a_ok$next[0:0]$8146 + assign $2\cr_a_ok$next[0:0]$8192 $1\cr_a_ok$next[0:0]$8191 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8143 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8144 + update \cr_a$next $0\cr_a$next[3:0]$8188 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8189 end - attribute \src "libresoc.v:153323.3-153341.6" - process $proc$libresoc.v:153323$8148 + attribute \src "libresoc.v:155215.3-155233.6" + process $proc$libresoc.v:155215$8193 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8149 $1\xer_ov$next[1:0]$8151 + assign $0\xer_ov$next[1:0]$8194 $1\xer_ov$next[1:0]$8196 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8150 $2\xer_ov_ok$next[0:0]$8153 - attribute \src "libresoc.v:153324.5-153324.29" + assign $0\xer_ov_ok$next[0:0]$8195 $2\xer_ov_ok$next[0:0]$8198 + attribute \src "libresoc.v:155216.5-155216.29" switch \initial - attribute \src "libresoc.v:153324.9-153324.17" + attribute \src "libresoc.v:155216.9-155216.17" case 1'1 case end @@ -320999,41 +323586,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8152 $1\xer_ov$next[1:0]$8151 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8197 $1\xer_ov$next[1:0]$8196 } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8152 $1\xer_ov$next[1:0]$8151 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8197 $1\xer_ov$next[1:0]$8196 } { \xer_ov_ok$76 \xer_ov$75 } case - assign $1\xer_ov$next[1:0]$8151 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8152 \xer_ov_ok + assign $1\xer_ov$next[1:0]$8196 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8197 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8153 1'0 + assign $2\xer_ov_ok$next[0:0]$8198 1'0 case - assign $2\xer_ov_ok$next[0:0]$8153 $1\xer_ov_ok$next[0:0]$8152 + assign $2\xer_ov_ok$next[0:0]$8198 $1\xer_ov_ok$next[0:0]$8197 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8149 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8150 + update \xer_ov$next $0\xer_ov$next[1:0]$8194 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8195 end - attribute \src "libresoc.v:153342.3-153360.6" - process $proc$libresoc.v:153342$8154 + attribute \src "libresoc.v:155234.3-155252.6" + process $proc$libresoc.v:155234$8199 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$15$next[0:0]$8156 $1\xer_so$15$next[0:0]$8158 - assign $0\xer_so_ok$next[0:0]$8155 $2\xer_so_ok$next[0:0]$8159 - attribute \src "libresoc.v:153343.5-153343.29" + assign $0\xer_so$15$next[0:0]$8201 $1\xer_so$15$next[0:0]$8203 + assign $0\xer_so_ok$next[0:0]$8200 $2\xer_so_ok$next[0:0]$8204 + attribute \src "libresoc.v:155235.5-155235.29" switch \initial - attribute \src "libresoc.v:153343.9-153343.17" + attribute \src "libresoc.v:155235.9-155235.17" case 1'1 case end @@ -321043,30 +323630,30 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8157 $1\xer_so$15$next[0:0]$8158 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8202 $1\xer_so$15$next[0:0]$8203 } { \xer_so_ok$78 \xer_so$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8157 $1\xer_so$15$next[0:0]$8158 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8202 $1\xer_so$15$next[0:0]$8203 } { \xer_so_ok$78 \xer_so$77 } case - assign $1\xer_so_ok$next[0:0]$8157 \xer_so_ok - assign $1\xer_so$15$next[0:0]$8158 \xer_so$15 + assign $1\xer_so_ok$next[0:0]$8202 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8203 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8159 1'0 + assign $2\xer_so_ok$next[0:0]$8204 1'0 case - assign $2\xer_so_ok$next[0:0]$8159 $1\xer_so_ok$next[0:0]$8157 + assign $2\xer_so_ok$next[0:0]$8204 $1\xer_so_ok$next[0:0]$8202 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8155 - update \xer_so$15$next $0\xer_so$15$next[0:0]$8156 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8200 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8201 end - connect \$56 $and$libresoc.v:153087$8060_Y + connect \$56 $and$libresoc.v:154979$8105_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -321093,13 +323680,13 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:153390.1-153401.10" +attribute \src "libresoc.v:155282.1-155293.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:153399.17-153399.111" - wire $and$libresoc.v:153399$8198_Y + attribute \src "libresoc.v:155291.17-155291.111" + wire $and$libresoc.v:155291$8243_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321109,7 +323696,7 @@ module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153399$8198 + cell $and $and$libresoc.v:155291$8243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321117,18 +323704,18 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153399$8198_Y + connect \Y $and$libresoc.v:155291$8243_Y end - connect \$1 $and$libresoc.v:153399$8198_Y + connect \$1 $and$libresoc.v:155291$8243_Y connect \trigger \$1 end -attribute \src "libresoc.v:153405.1-153416.10" +attribute \src "libresoc.v:155297.1-155308.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 - attribute \src "libresoc.v:153414.17-153414.111" - wire $and$libresoc.v:153414$8199_Y + attribute \src "libresoc.v:155306.17-155306.111" + wire $and$libresoc.v:155306$8244_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321138,7 +323725,7 @@ module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153414$8199 + cell $and $and$libresoc.v:155306$8244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321146,18 +323733,18 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153414$8199_Y + connect \Y $and$libresoc.v:155306$8244_Y end - connect \$1 $and$libresoc.v:153414$8199_Y + connect \$1 $and$libresoc.v:155306$8244_Y connect \trigger \$1 end -attribute \src "libresoc.v:153420.1-153431.10" +attribute \src "libresoc.v:155312.1-155323.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 - attribute \src "libresoc.v:153429.17-153429.111" - wire $and$libresoc.v:153429$8200_Y + attribute \src "libresoc.v:155321.17-155321.111" + wire $and$libresoc.v:155321$8245_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321167,7 +323754,7 @@ module \n$112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153429$8200 + cell $and $and$libresoc.v:155321$8245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321175,18 +323762,18 @@ module \n$112 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153429$8200_Y + connect \Y $and$libresoc.v:155321$8245_Y end - connect \$1 $and$libresoc.v:153429$8200_Y + connect \$1 $and$libresoc.v:155321$8245_Y connect \trigger \$1 end -attribute \src "libresoc.v:153435.1-153446.10" +attribute \src "libresoc.v:155327.1-155338.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 - attribute \src "libresoc.v:153444.17-153444.111" - wire $and$libresoc.v:153444$8201_Y + attribute \src "libresoc.v:155336.17-155336.111" + wire $and$libresoc.v:155336$8246_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321196,7 +323783,7 @@ module \n$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153444$8201 + cell $and $and$libresoc.v:155336$8246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321204,18 +323791,18 @@ module \n$117 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153444$8201_Y + connect \Y $and$libresoc.v:155336$8246_Y end - connect \$1 $and$libresoc.v:153444$8201_Y + connect \$1 $and$libresoc.v:155336$8246_Y connect \trigger \$1 end -attribute \src "libresoc.v:153450.1-153461.10" +attribute \src "libresoc.v:155342.1-155353.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:153459.17-153459.111" - wire $and$libresoc.v:153459$8202_Y + attribute \src "libresoc.v:155351.17-155351.111" + wire $and$libresoc.v:155351$8247_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321225,7 +323812,7 @@ module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153459$8202 + cell $and $and$libresoc.v:155351$8247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321233,18 +323820,18 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153459$8202_Y + connect \Y $and$libresoc.v:155351$8247_Y end - connect \$1 $and$libresoc.v:153459$8202_Y + connect \$1 $and$libresoc.v:155351$8247_Y connect \trigger \$1 end -attribute \src "libresoc.v:153465.1-153476.10" +attribute \src "libresoc.v:155357.1-155368.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:153474.17-153474.111" - wire $and$libresoc.v:153474$8203_Y + attribute \src "libresoc.v:155366.17-155366.111" + wire $and$libresoc.v:155366$8248_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321254,7 +323841,7 @@ module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153474$8203 + cell $and $and$libresoc.v:155366$8248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321262,18 +323849,18 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153474$8203_Y + connect \Y $and$libresoc.v:155366$8248_Y end - connect \$1 $and$libresoc.v:153474$8203_Y + connect \$1 $and$libresoc.v:155366$8248_Y connect \trigger \$1 end -attribute \src "libresoc.v:153480.1-153491.10" +attribute \src "libresoc.v:155372.1-155383.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:153489.17-153489.111" - wire $and$libresoc.v:153489$8204_Y + attribute \src "libresoc.v:155381.17-155381.111" + wire $and$libresoc.v:155381$8249_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321283,7 +323870,7 @@ module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153489$8204 + cell $and $and$libresoc.v:155381$8249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321291,18 +323878,18 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153489$8204_Y + connect \Y $and$libresoc.v:155381$8249_Y end - connect \$1 $and$libresoc.v:153489$8204_Y + connect \$1 $and$libresoc.v:155381$8249_Y connect \trigger \$1 end -attribute \src "libresoc.v:153495.1-153506.10" +attribute \src "libresoc.v:155387.1-155398.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:153504.17-153504.111" - wire $and$libresoc.v:153504$8205_Y + attribute \src "libresoc.v:155396.17-155396.111" + wire $and$libresoc.v:155396$8250_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321312,7 +323899,7 @@ module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153504$8205 + cell $and $and$libresoc.v:155396$8250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321320,18 +323907,18 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153504$8205_Y + connect \Y $and$libresoc.v:155396$8250_Y end - connect \$1 $and$libresoc.v:153504$8205_Y + connect \$1 $and$libresoc.v:155396$8250_Y connect \trigger \$1 end -attribute \src "libresoc.v:153510.1-153521.10" +attribute \src "libresoc.v:155402.1-155413.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:153519.17-153519.111" - wire $and$libresoc.v:153519$8206_Y + attribute \src "libresoc.v:155411.17-155411.111" + wire $and$libresoc.v:155411$8251_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321341,7 +323928,7 @@ module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153519$8206 + cell $and $and$libresoc.v:155411$8251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321349,18 +323936,18 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153519$8206_Y + connect \Y $and$libresoc.v:155411$8251_Y end - connect \$1 $and$libresoc.v:153519$8206_Y + connect \$1 $and$libresoc.v:155411$8251_Y connect \trigger \$1 end -attribute \src "libresoc.v:153525.1-153536.10" +attribute \src "libresoc.v:155417.1-155428.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 - attribute \src "libresoc.v:153534.17-153534.111" - wire $and$libresoc.v:153534$8207_Y + attribute \src "libresoc.v:155426.17-155426.111" + wire $and$libresoc.v:155426$8252_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321370,7 +323957,7 @@ module \n$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153534$8207 + cell $and $and$libresoc.v:155426$8252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321378,18 +323965,18 @@ module \n$37 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153534$8207_Y + connect \Y $and$libresoc.v:155426$8252_Y end - connect \$1 $and$libresoc.v:153534$8207_Y + connect \$1 $and$libresoc.v:155426$8252_Y connect \trigger \$1 end -attribute \src "libresoc.v:153540.1-153551.10" +attribute \src "libresoc.v:155432.1-155443.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 - attribute \src "libresoc.v:153549.17-153549.111" - wire $and$libresoc.v:153549$8208_Y + attribute \src "libresoc.v:155441.17-155441.111" + wire $and$libresoc.v:155441$8253_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321399,7 +323986,7 @@ module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153549$8208 + cell $and $and$libresoc.v:155441$8253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321407,18 +323994,18 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153549$8208_Y + connect \Y $and$libresoc.v:155441$8253_Y end - connect \$1 $and$libresoc.v:153549$8208_Y + connect \$1 $and$libresoc.v:155441$8253_Y connect \trigger \$1 end -attribute \src "libresoc.v:153555.1-153566.10" +attribute \src "libresoc.v:155447.1-155458.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 - attribute \src "libresoc.v:153564.17-153564.111" - wire $and$libresoc.v:153564$8209_Y + attribute \src "libresoc.v:155456.17-155456.111" + wire $and$libresoc.v:155456$8254_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321428,7 +324015,7 @@ module \n$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153564$8209 + cell $and $and$libresoc.v:155456$8254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321436,18 +324023,18 @@ module \n$47 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153564$8209_Y + connect \Y $and$libresoc.v:155456$8254_Y end - connect \$1 $and$libresoc.v:153564$8209_Y + connect \$1 $and$libresoc.v:155456$8254_Y connect \trigger \$1 end -attribute \src "libresoc.v:153570.1-153581.10" +attribute \src "libresoc.v:155462.1-155473.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 - attribute \src "libresoc.v:153579.17-153579.111" - wire $and$libresoc.v:153579$8210_Y + attribute \src "libresoc.v:155471.17-155471.111" + wire $and$libresoc.v:155471$8255_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321457,7 +324044,7 @@ module \n$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153579$8210 + cell $and $and$libresoc.v:155471$8255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321465,18 +324052,18 @@ module \n$49 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153579$8210_Y + connect \Y $and$libresoc.v:155471$8255_Y end - connect \$1 $and$libresoc.v:153579$8210_Y + connect \$1 $and$libresoc.v:155471$8255_Y connect \trigger \$1 end -attribute \src "libresoc.v:153585.1-153596.10" +attribute \src "libresoc.v:155477.1-155488.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 - attribute \src "libresoc.v:153594.17-153594.111" - wire $and$libresoc.v:153594$8211_Y + attribute \src "libresoc.v:155486.17-155486.111" + wire $and$libresoc.v:155486$8256_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321486,7 +324073,7 @@ module \n$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153594$8211 + cell $and $and$libresoc.v:155486$8256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321494,18 +324081,18 @@ module \n$53 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153594$8211_Y + connect \Y $and$libresoc.v:155486$8256_Y end - connect \$1 $and$libresoc.v:153594$8211_Y + connect \$1 $and$libresoc.v:155486$8256_Y connect \trigger \$1 end -attribute \src "libresoc.v:153600.1-153611.10" +attribute \src "libresoc.v:155492.1-155503.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 - attribute \src "libresoc.v:153609.17-153609.111" - wire $and$libresoc.v:153609$8212_Y + attribute \src "libresoc.v:155501.17-155501.111" + wire $and$libresoc.v:155501$8257_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321515,7 +324102,7 @@ module \n$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153609$8212 + cell $and $and$libresoc.v:155501$8257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321523,18 +324110,18 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153609$8212_Y + connect \Y $and$libresoc.v:155501$8257_Y end - connect \$1 $and$libresoc.v:153609$8212_Y + connect \$1 $and$libresoc.v:155501$8257_Y connect \trigger \$1 end -attribute \src "libresoc.v:153615.1-153626.10" +attribute \src "libresoc.v:155507.1-155518.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:153624.17-153624.111" - wire $and$libresoc.v:153624$8213_Y + attribute \src "libresoc.v:155516.17-155516.111" + wire $and$libresoc.v:155516$8258_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321544,7 +324131,7 @@ module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153624$8213 + cell $and $and$libresoc.v:155516$8258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321552,18 +324139,18 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153624$8213_Y + connect \Y $and$libresoc.v:155516$8258_Y end - connect \$1 $and$libresoc.v:153624$8213_Y + connect \$1 $and$libresoc.v:155516$8258_Y connect \trigger \$1 end -attribute \src "libresoc.v:153630.1-153641.10" +attribute \src "libresoc.v:155522.1-155533.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 - attribute \src "libresoc.v:153639.17-153639.111" - wire $and$libresoc.v:153639$8214_Y + attribute \src "libresoc.v:155531.17-155531.111" + wire $and$libresoc.v:155531$8259_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321573,7 +324160,7 @@ module \n$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153639$8214 + cell $and $and$libresoc.v:155531$8259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321581,18 +324168,18 @@ module \n$66 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153639$8214_Y + connect \Y $and$libresoc.v:155531$8259_Y end - connect \$1 $and$libresoc.v:153639$8214_Y + connect \$1 $and$libresoc.v:155531$8259_Y connect \trigger \$1 end -attribute \src "libresoc.v:153645.1-153656.10" +attribute \src "libresoc.v:155537.1-155548.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 - attribute \src "libresoc.v:153654.17-153654.111" - wire $and$libresoc.v:153654$8215_Y + attribute \src "libresoc.v:155546.17-155546.111" + wire $and$libresoc.v:155546$8260_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321602,7 +324189,7 @@ module \n$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153654$8215 + cell $and $and$libresoc.v:155546$8260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321610,18 +324197,18 @@ module \n$75 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153654$8215_Y + connect \Y $and$libresoc.v:155546$8260_Y end - connect \$1 $and$libresoc.v:153654$8215_Y + connect \$1 $and$libresoc.v:155546$8260_Y connect \trigger \$1 end -attribute \src "libresoc.v:153660.1-153671.10" +attribute \src "libresoc.v:155552.1-155563.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:153669.17-153669.111" - wire $and$libresoc.v:153669$8216_Y + attribute \src "libresoc.v:155561.17-155561.111" + wire $and$libresoc.v:155561$8261_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321631,7 +324218,7 @@ module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153669$8216 + cell $and $and$libresoc.v:155561$8261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321639,18 +324226,18 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153669$8216_Y + connect \Y $and$libresoc.v:155561$8261_Y end - connect \$1 $and$libresoc.v:153669$8216_Y + connect \$1 $and$libresoc.v:155561$8261_Y connect \trigger \$1 end -attribute \src "libresoc.v:153675.1-153686.10" +attribute \src "libresoc.v:155567.1-155578.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 - attribute \src "libresoc.v:153684.17-153684.111" - wire $and$libresoc.v:153684$8217_Y + attribute \src "libresoc.v:155576.17-155576.111" + wire $and$libresoc.v:155576$8262_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321660,7 +324247,7 @@ module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153684$8217 + cell $and $and$libresoc.v:155576$8262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321668,18 +324255,18 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153684$8217_Y + connect \Y $and$libresoc.v:155576$8262_Y end - connect \$1 $and$libresoc.v:153684$8217_Y + connect \$1 $and$libresoc.v:155576$8262_Y connect \trigger \$1 end -attribute \src "libresoc.v:153690.1-153701.10" +attribute \src "libresoc.v:155582.1-155593.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 - attribute \src "libresoc.v:153699.17-153699.111" - wire $and$libresoc.v:153699$8218_Y + attribute \src "libresoc.v:155591.17-155591.111" + wire $and$libresoc.v:155591$8263_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321689,7 +324276,7 @@ module \n$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153699$8218 + cell $and $and$libresoc.v:155591$8263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321697,18 +324284,18 @@ module \n$80 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153699$8218_Y + connect \Y $and$libresoc.v:155591$8263_Y end - connect \$1 $and$libresoc.v:153699$8218_Y + connect \$1 $and$libresoc.v:155591$8263_Y connect \trigger \$1 end -attribute \src "libresoc.v:153705.1-153716.10" +attribute \src "libresoc.v:155597.1-155608.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 - attribute \src "libresoc.v:153714.17-153714.111" - wire $and$libresoc.v:153714$8219_Y + attribute \src "libresoc.v:155606.17-155606.111" + wire $and$libresoc.v:155606$8264_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321718,7 +324305,7 @@ module \n$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153714$8219 + cell $and $and$libresoc.v:155606$8264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321726,18 +324313,18 @@ module \n$82 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153714$8219_Y + connect \Y $and$libresoc.v:155606$8264_Y end - connect \$1 $and$libresoc.v:153714$8219_Y + connect \$1 $and$libresoc.v:155606$8264_Y connect \trigger \$1 end -attribute \src "libresoc.v:153720.1-153731.10" +attribute \src "libresoc.v:155612.1-155623.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 - attribute \src "libresoc.v:153729.17-153729.111" - wire $and$libresoc.v:153729$8220_Y + attribute \src "libresoc.v:155621.17-155621.111" + wire $and$libresoc.v:155621$8265_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321747,7 +324334,7 @@ module \n$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153729$8220 + cell $and $and$libresoc.v:155621$8265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321755,18 +324342,18 @@ module \n$92 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153729$8220_Y + connect \Y $and$libresoc.v:155621$8265_Y end - connect \$1 $and$libresoc.v:153729$8220_Y + connect \$1 $and$libresoc.v:155621$8265_Y connect \trigger \$1 end -attribute \src "libresoc.v:153735.1-153746.10" +attribute \src "libresoc.v:155627.1-155638.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:153744.17-153744.111" - wire $and$libresoc.v:153744$8221_Y + attribute \src "libresoc.v:155636.17-155636.111" + wire $and$libresoc.v:155636$8266_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321776,7 +324363,7 @@ module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153744$8221 + cell $and $and$libresoc.v:155636$8266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321784,18 +324371,18 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153744$8221_Y + connect \Y $and$libresoc.v:155636$8266_Y end - connect \$1 $and$libresoc.v:153744$8221_Y + connect \$1 $and$libresoc.v:155636$8266_Y connect \trigger \$1 end -attribute \src "libresoc.v:153750.1-153761.10" +attribute \src "libresoc.v:155642.1-155653.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 - attribute \src "libresoc.v:153759.17-153759.111" - wire $and$libresoc.v:153759$8222_Y + attribute \src "libresoc.v:155651.17-155651.111" + wire $and$libresoc.v:155651$8267_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321805,7 +324392,7 @@ module \n$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153759$8222 + cell $and $and$libresoc.v:155651$8267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321813,18 +324400,18 @@ module \n$97 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153759$8222_Y + connect \Y $and$libresoc.v:155651$8267_Y end - connect \$1 $and$libresoc.v:153759$8222_Y + connect \$1 $and$libresoc.v:155651$8267_Y connect \trigger \$1 end -attribute \src "libresoc.v:153765.1-153776.10" +attribute \src "libresoc.v:155657.1-155668.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 - attribute \src "libresoc.v:153774.17-153774.111" - wire $and$libresoc.v:153774$8223_Y + attribute \src "libresoc.v:155666.17-155666.111" + wire $and$libresoc.v:155666$8268_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -321834,7 +324421,7 @@ module \n$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:153774$8223 + cell $and $and$libresoc.v:155666$8268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321842,42 +324429,42 @@ module \n$99 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:153774$8223_Y + connect \Y $and$libresoc.v:155666$8268_Y end - connect \$1 $and$libresoc.v:153774$8223_Y + connect \$1 $and$libresoc.v:155666$8268_Y connect \trigger \$1 end -attribute \src "libresoc.v:153780.1-153838.10" +attribute \src "libresoc.v:155672.1-155730.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l - attribute \src "libresoc.v:153781.7-153781.20" + attribute \src "libresoc.v:155673.7-155673.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153826.3-153834.6" - wire $0\q_int$next[0:0]$8234 - attribute \src "libresoc.v:153824.3-153825.27" + attribute \src "libresoc.v:155718.3-155726.6" + wire $0\q_int$next[0:0]$8279 + attribute \src "libresoc.v:155716.3-155717.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:153826.3-153834.6" - wire $1\q_int$next[0:0]$8235 - attribute \src "libresoc.v:153803.7-153803.19" + attribute \src "libresoc.v:155718.3-155726.6" + wire $1\q_int$next[0:0]$8280 + attribute \src "libresoc.v:155695.7-155695.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:153816.17-153816.96" - wire $and$libresoc.v:153816$8224_Y - attribute \src "libresoc.v:153821.17-153821.96" - wire $and$libresoc.v:153821$8229_Y - attribute \src "libresoc.v:153818.18-153818.93" - wire $not$libresoc.v:153818$8226_Y - attribute \src "libresoc.v:153820.17-153820.92" - wire $not$libresoc.v:153820$8228_Y - attribute \src "libresoc.v:153823.17-153823.92" - wire $not$libresoc.v:153823$8231_Y - attribute \src "libresoc.v:153817.18-153817.98" - wire $or$libresoc.v:153817$8225_Y - attribute \src "libresoc.v:153819.18-153819.99" - wire $or$libresoc.v:153819$8227_Y - attribute \src "libresoc.v:153822.17-153822.97" - wire $or$libresoc.v:153822$8230_Y + attribute \src "libresoc.v:155708.17-155708.96" + wire $and$libresoc.v:155708$8269_Y + attribute \src "libresoc.v:155713.17-155713.96" + wire $and$libresoc.v:155713$8274_Y + attribute \src "libresoc.v:155710.18-155710.93" + wire $not$libresoc.v:155710$8271_Y + attribute \src "libresoc.v:155712.17-155712.92" + wire $not$libresoc.v:155712$8273_Y + attribute \src "libresoc.v:155715.17-155715.92" + wire $not$libresoc.v:155715$8276_Y + attribute \src "libresoc.v:155709.18-155709.98" + wire $or$libresoc.v:155709$8270_Y + attribute \src "libresoc.v:155711.18-155711.99" + wire $or$libresoc.v:155711$8272_Y + attribute \src "libresoc.v:155714.17-155714.97" + wire $or$libresoc.v:155714$8275_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -321894,11 +324481,11 @@ module \opc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:153781.7-153781.15" + attribute \src "libresoc.v:155673.7-155673.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -321915,7 +324502,7 @@ module \opc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:153816$8224 + cell $and $and$libresoc.v:155708$8269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321923,10 +324510,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:153816$8224_Y + connect \Y $and$libresoc.v:155708$8269_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:153821$8229 + cell $and $and$libresoc.v:155713$8274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321934,34 +324521,34 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:153821$8229_Y + connect \Y $and$libresoc.v:155713$8274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:153818$8226 + cell $not $not$libresoc.v:155710$8271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:153818$8226_Y + connect \Y $not$libresoc.v:155710$8271_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:153820$8228 + cell $not $not$libresoc.v:155712$8273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:153820$8228_Y + connect \Y $not$libresoc.v:155712$8273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:153823$8231 + cell $not $not$libresoc.v:155715$8276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:153823$8231_Y + connect \Y $not$libresoc.v:155715$8276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:153817$8225 + cell $or $or$libresoc.v:155709$8270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321969,10 +324556,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:153817$8225_Y + connect \Y $or$libresoc.v:155709$8270_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:153819$8227 + cell $or $or$libresoc.v:155711$8272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321980,10 +324567,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:153819$8227_Y + connect \Y $or$libresoc.v:155711$8272_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:153822$8230 + cell $or $or$libresoc.v:155714$8275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321991,39 +324578,39 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:153822$8230_Y + connect \Y $or$libresoc.v:155714$8275_Y end - attribute \src "libresoc.v:153781.7-153781.20" - process $proc$libresoc.v:153781$8236 + attribute \src "libresoc.v:155673.7-155673.20" + process $proc$libresoc.v:155673$8281 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153803.7-153803.19" - process $proc$libresoc.v:153803$8237 + attribute \src "libresoc.v:155695.7-155695.19" + process $proc$libresoc.v:155695$8282 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:153824.3-153825.27" - process $proc$libresoc.v:153824$8232 + attribute \src "libresoc.v:155716.3-155717.27" + process $proc$libresoc.v:155716$8277 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:153826.3-153834.6" - process $proc$libresoc.v:153826$8233 + attribute \src "libresoc.v:155718.3-155726.6" + process $proc$libresoc.v:155718$8278 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8234 $1\q_int$next[0:0]$8235 - attribute \src "libresoc.v:153827.5-153827.29" + assign $0\q_int$next[0:0]$8279 $1\q_int$next[0:0]$8280 + attribute \src "libresoc.v:155719.5-155719.29" switch \initial - attribute \src "libresoc.v:153827.9-153827.17" + attribute \src "libresoc.v:155719.9-155719.17" case 1'1 case end @@ -322032,56 +324619,56 @@ module \opc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8235 1'0 + assign $1\q_int$next[0:0]$8280 1'0 case - assign $1\q_int$next[0:0]$8235 \$5 + assign $1\q_int$next[0:0]$8280 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8234 + update \q_int$next $0\q_int$next[0:0]$8279 end - connect \$9 $and$libresoc.v:153816$8224_Y - connect \$11 $or$libresoc.v:153817$8225_Y - connect \$13 $not$libresoc.v:153818$8226_Y - connect \$15 $or$libresoc.v:153819$8227_Y - connect \$1 $not$libresoc.v:153820$8228_Y - connect \$3 $and$libresoc.v:153821$8229_Y - connect \$5 $or$libresoc.v:153822$8230_Y - connect \$7 $not$libresoc.v:153823$8231_Y + connect \$9 $and$libresoc.v:155708$8269_Y + connect \$11 $or$libresoc.v:155709$8270_Y + connect \$13 $not$libresoc.v:155710$8271_Y + connect \$15 $or$libresoc.v:155711$8272_Y + connect \$1 $not$libresoc.v:155712$8273_Y + connect \$3 $and$libresoc.v:155713$8274_Y + connect \$5 $or$libresoc.v:155714$8275_Y + connect \$7 $not$libresoc.v:155715$8276_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:153842.1-153900.10" +attribute \src "libresoc.v:155734.1-155792.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 - attribute \src "libresoc.v:153843.7-153843.20" + attribute \src "libresoc.v:155735.7-155735.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153888.3-153896.6" - wire $0\q_int$next[0:0]$8248 - attribute \src "libresoc.v:153886.3-153887.27" + attribute \src "libresoc.v:155780.3-155788.6" + wire $0\q_int$next[0:0]$8293 + attribute \src "libresoc.v:155778.3-155779.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:153888.3-153896.6" - wire $1\q_int$next[0:0]$8249 - attribute \src "libresoc.v:153865.7-153865.19" + attribute \src "libresoc.v:155780.3-155788.6" + wire $1\q_int$next[0:0]$8294 + attribute \src "libresoc.v:155757.7-155757.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:153878.17-153878.96" - wire $and$libresoc.v:153878$8238_Y - attribute \src "libresoc.v:153883.17-153883.96" - wire $and$libresoc.v:153883$8243_Y - attribute \src "libresoc.v:153880.18-153880.93" - wire $not$libresoc.v:153880$8240_Y - attribute \src "libresoc.v:153882.17-153882.92" - wire $not$libresoc.v:153882$8242_Y - attribute \src "libresoc.v:153885.17-153885.92" - wire $not$libresoc.v:153885$8245_Y - attribute \src "libresoc.v:153879.18-153879.98" - wire $or$libresoc.v:153879$8239_Y - attribute \src "libresoc.v:153881.18-153881.99" - wire $or$libresoc.v:153881$8241_Y - attribute \src "libresoc.v:153884.17-153884.97" - wire $or$libresoc.v:153884$8244_Y + attribute \src "libresoc.v:155770.17-155770.96" + wire $and$libresoc.v:155770$8283_Y + attribute \src "libresoc.v:155775.17-155775.96" + wire $and$libresoc.v:155775$8288_Y + attribute \src "libresoc.v:155772.18-155772.93" + wire $not$libresoc.v:155772$8285_Y + attribute \src "libresoc.v:155774.17-155774.92" + wire $not$libresoc.v:155774$8287_Y + attribute \src "libresoc.v:155777.17-155777.92" + wire $not$libresoc.v:155777$8290_Y + attribute \src "libresoc.v:155771.18-155771.98" + wire $or$libresoc.v:155771$8284_Y + attribute \src "libresoc.v:155773.18-155773.99" + wire $or$libresoc.v:155773$8286_Y + attribute \src "libresoc.v:155776.17-155776.97" + wire $or$libresoc.v:155776$8289_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -322098,11 +324685,11 @@ module \opc_l$102 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:153843.7-153843.15" + attribute \src "libresoc.v:155735.7-155735.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -322119,7 +324706,7 @@ module \opc_l$102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:153878$8238 + cell $and $and$libresoc.v:155770$8283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322127,10 +324714,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:153878$8238_Y + connect \Y $and$libresoc.v:155770$8283_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:153883$8243 + cell $and $and$libresoc.v:155775$8288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322138,34 +324725,34 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:153883$8243_Y + connect \Y $and$libresoc.v:155775$8288_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:153880$8240 + cell $not $not$libresoc.v:155772$8285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:153880$8240_Y + connect \Y $not$libresoc.v:155772$8285_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:153882$8242 + cell $not $not$libresoc.v:155774$8287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:153882$8242_Y + connect \Y $not$libresoc.v:155774$8287_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:153885$8245 + cell $not $not$libresoc.v:155777$8290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:153885$8245_Y + connect \Y $not$libresoc.v:155777$8290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:153879$8239 + cell $or $or$libresoc.v:155771$8284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322173,10 +324760,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:153879$8239_Y + connect \Y $or$libresoc.v:155771$8284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:153881$8241 + cell $or $or$libresoc.v:155773$8286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322184,10 +324771,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:153881$8241_Y + connect \Y $or$libresoc.v:155773$8286_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:153884$8244 + cell $or $or$libresoc.v:155776$8289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322195,39 +324782,39 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:153884$8244_Y + connect \Y $or$libresoc.v:155776$8289_Y end - attribute \src "libresoc.v:153843.7-153843.20" - process $proc$libresoc.v:153843$8250 + attribute \src "libresoc.v:155735.7-155735.20" + process $proc$libresoc.v:155735$8295 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153865.7-153865.19" - process $proc$libresoc.v:153865$8251 + attribute \src "libresoc.v:155757.7-155757.19" + process $proc$libresoc.v:155757$8296 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:153886.3-153887.27" - process $proc$libresoc.v:153886$8246 + attribute \src "libresoc.v:155778.3-155779.27" + process $proc$libresoc.v:155778$8291 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:153888.3-153896.6" - process $proc$libresoc.v:153888$8247 + attribute \src "libresoc.v:155780.3-155788.6" + process $proc$libresoc.v:155780$8292 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8248 $1\q_int$next[0:0]$8249 - attribute \src "libresoc.v:153889.5-153889.29" + assign $0\q_int$next[0:0]$8293 $1\q_int$next[0:0]$8294 + attribute \src "libresoc.v:155781.5-155781.29" switch \initial - attribute \src "libresoc.v:153889.9-153889.17" + attribute \src "libresoc.v:155781.9-155781.17" case 1'1 case end @@ -322236,56 +324823,56 @@ module \opc_l$102 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8249 1'0 + assign $1\q_int$next[0:0]$8294 1'0 case - assign $1\q_int$next[0:0]$8249 \$5 + assign $1\q_int$next[0:0]$8294 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8248 + update \q_int$next $0\q_int$next[0:0]$8293 end - connect \$9 $and$libresoc.v:153878$8238_Y - connect \$11 $or$libresoc.v:153879$8239_Y - connect \$13 $not$libresoc.v:153880$8240_Y - connect \$15 $or$libresoc.v:153881$8241_Y - connect \$1 $not$libresoc.v:153882$8242_Y - connect \$3 $and$libresoc.v:153883$8243_Y - connect \$5 $or$libresoc.v:153884$8244_Y - connect \$7 $not$libresoc.v:153885$8245_Y + connect \$9 $and$libresoc.v:155770$8283_Y + connect \$11 $or$libresoc.v:155771$8284_Y + connect \$13 $not$libresoc.v:155772$8285_Y + connect \$15 $or$libresoc.v:155773$8286_Y + connect \$1 $not$libresoc.v:155774$8287_Y + connect \$3 $and$libresoc.v:155775$8288_Y + connect \$5 $or$libresoc.v:155776$8289_Y + connect \$7 $not$libresoc.v:155777$8290_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:153904.1-153962.10" +attribute \src "libresoc.v:155796.1-155854.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 - attribute \src "libresoc.v:153905.7-153905.20" + attribute \src "libresoc.v:155797.7-155797.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153950.3-153958.6" - wire $0\q_int$next[0:0]$8262 - attribute \src "libresoc.v:153948.3-153949.27" + attribute \src "libresoc.v:155842.3-155850.6" + wire $0\q_int$next[0:0]$8307 + attribute \src "libresoc.v:155840.3-155841.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:153950.3-153958.6" - wire $1\q_int$next[0:0]$8263 - attribute \src "libresoc.v:153927.7-153927.19" + attribute \src "libresoc.v:155842.3-155850.6" + wire $1\q_int$next[0:0]$8308 + attribute \src "libresoc.v:155819.7-155819.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:153940.17-153940.96" - wire $and$libresoc.v:153940$8252_Y - attribute \src "libresoc.v:153945.17-153945.96" - wire $and$libresoc.v:153945$8257_Y - attribute \src "libresoc.v:153942.18-153942.93" - wire $not$libresoc.v:153942$8254_Y - attribute \src "libresoc.v:153944.17-153944.92" - wire $not$libresoc.v:153944$8256_Y - attribute \src "libresoc.v:153947.17-153947.92" - wire $not$libresoc.v:153947$8259_Y - attribute \src "libresoc.v:153941.18-153941.98" - wire $or$libresoc.v:153941$8253_Y - attribute \src "libresoc.v:153943.18-153943.99" - wire $or$libresoc.v:153943$8255_Y - attribute \src "libresoc.v:153946.17-153946.97" - wire $or$libresoc.v:153946$8258_Y + attribute \src "libresoc.v:155832.17-155832.96" + wire $and$libresoc.v:155832$8297_Y + attribute \src "libresoc.v:155837.17-155837.96" + wire $and$libresoc.v:155837$8302_Y + attribute \src "libresoc.v:155834.18-155834.93" + wire $not$libresoc.v:155834$8299_Y + attribute \src "libresoc.v:155836.17-155836.92" + wire $not$libresoc.v:155836$8301_Y + attribute \src "libresoc.v:155839.17-155839.92" + wire $not$libresoc.v:155839$8304_Y + attribute \src "libresoc.v:155833.18-155833.98" + wire $or$libresoc.v:155833$8298_Y + attribute \src "libresoc.v:155835.18-155835.99" + wire $or$libresoc.v:155835$8300_Y + attribute \src "libresoc.v:155838.17-155838.97" + wire $or$libresoc.v:155838$8303_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -322302,11 +324889,11 @@ module \opc_l$11 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:153905.7-153905.15" + attribute \src "libresoc.v:155797.7-155797.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -322323,7 +324910,7 @@ module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:153940$8252 + cell $and $and$libresoc.v:155832$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322331,10 +324918,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:153940$8252_Y + connect \Y $and$libresoc.v:155832$8297_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:153945$8257 + cell $and $and$libresoc.v:155837$8302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322342,34 +324929,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:153945$8257_Y + connect \Y $and$libresoc.v:155837$8302_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:153942$8254 + cell $not $not$libresoc.v:155834$8299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:153942$8254_Y + connect \Y $not$libresoc.v:155834$8299_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:153944$8256 + cell $not $not$libresoc.v:155836$8301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:153944$8256_Y + connect \Y $not$libresoc.v:155836$8301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:153947$8259 + cell $not $not$libresoc.v:155839$8304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:153947$8259_Y + connect \Y $not$libresoc.v:155839$8304_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:153941$8253 + cell $or $or$libresoc.v:155833$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322377,10 +324964,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:153941$8253_Y + connect \Y $or$libresoc.v:155833$8298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:153943$8255 + cell $or $or$libresoc.v:155835$8300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322388,10 +324975,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:153943$8255_Y + connect \Y $or$libresoc.v:155835$8300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:153946$8258 + cell $or $or$libresoc.v:155838$8303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322399,39 +324986,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:153946$8258_Y + connect \Y $or$libresoc.v:155838$8303_Y end - attribute \src "libresoc.v:153905.7-153905.20" - process $proc$libresoc.v:153905$8264 + attribute \src "libresoc.v:155797.7-155797.20" + process $proc$libresoc.v:155797$8309 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153927.7-153927.19" - process $proc$libresoc.v:153927$8265 + attribute \src "libresoc.v:155819.7-155819.19" + process $proc$libresoc.v:155819$8310 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:153948.3-153949.27" - process $proc$libresoc.v:153948$8260 + attribute \src "libresoc.v:155840.3-155841.27" + process $proc$libresoc.v:155840$8305 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:153950.3-153958.6" - process $proc$libresoc.v:153950$8261 + attribute \src "libresoc.v:155842.3-155850.6" + process $proc$libresoc.v:155842$8306 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8262 $1\q_int$next[0:0]$8263 - attribute \src "libresoc.v:153951.5-153951.29" + assign $0\q_int$next[0:0]$8307 $1\q_int$next[0:0]$8308 + attribute \src "libresoc.v:155843.5-155843.29" switch \initial - attribute \src "libresoc.v:153951.9-153951.17" + attribute \src "libresoc.v:155843.9-155843.17" case 1'1 case end @@ -322440,56 +325027,56 @@ module \opc_l$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8263 1'0 + assign $1\q_int$next[0:0]$8308 1'0 case - assign $1\q_int$next[0:0]$8263 \$5 + assign $1\q_int$next[0:0]$8308 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8262 + update \q_int$next $0\q_int$next[0:0]$8307 end - connect \$9 $and$libresoc.v:153940$8252_Y - connect \$11 $or$libresoc.v:153941$8253_Y - connect \$13 $not$libresoc.v:153942$8254_Y - connect \$15 $or$libresoc.v:153943$8255_Y - connect \$1 $not$libresoc.v:153944$8256_Y - connect \$3 $and$libresoc.v:153945$8257_Y - connect \$5 $or$libresoc.v:153946$8258_Y - connect \$7 $not$libresoc.v:153947$8259_Y + connect \$9 $and$libresoc.v:155832$8297_Y + connect \$11 $or$libresoc.v:155833$8298_Y + connect \$13 $not$libresoc.v:155834$8299_Y + connect \$15 $or$libresoc.v:155835$8300_Y + connect \$1 $not$libresoc.v:155836$8301_Y + connect \$3 $and$libresoc.v:155837$8302_Y + connect \$5 $or$libresoc.v:155838$8303_Y + connect \$7 $not$libresoc.v:155839$8304_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:153966.1-154024.10" +attribute \src "libresoc.v:155858.1-155916.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 - attribute \src "libresoc.v:153967.7-153967.20" + attribute \src "libresoc.v:155859.7-155859.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154012.3-154020.6" - wire $0\q_int$next[0:0]$8276 - attribute \src "libresoc.v:154010.3-154011.27" + attribute \src "libresoc.v:155904.3-155912.6" + wire $0\q_int$next[0:0]$8321 + attribute \src "libresoc.v:155902.3-155903.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:154012.3-154020.6" - wire $1\q_int$next[0:0]$8277 - attribute \src "libresoc.v:153989.7-153989.19" + attribute \src "libresoc.v:155904.3-155912.6" + wire $1\q_int$next[0:0]$8322 + attribute \src "libresoc.v:155881.7-155881.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:154002.17-154002.96" - wire $and$libresoc.v:154002$8266_Y - attribute \src "libresoc.v:154007.17-154007.96" - wire $and$libresoc.v:154007$8271_Y - attribute \src "libresoc.v:154004.18-154004.93" - wire $not$libresoc.v:154004$8268_Y - attribute \src "libresoc.v:154006.17-154006.92" - wire $not$libresoc.v:154006$8270_Y - attribute \src "libresoc.v:154009.17-154009.92" - wire $not$libresoc.v:154009$8273_Y - attribute \src "libresoc.v:154003.18-154003.98" - wire $or$libresoc.v:154003$8267_Y - attribute \src "libresoc.v:154005.18-154005.99" - wire $or$libresoc.v:154005$8269_Y - attribute \src "libresoc.v:154008.17-154008.97" - wire $or$libresoc.v:154008$8272_Y + attribute \src "libresoc.v:155894.17-155894.96" + wire $and$libresoc.v:155894$8311_Y + attribute \src "libresoc.v:155899.17-155899.96" + wire $and$libresoc.v:155899$8316_Y + attribute \src "libresoc.v:155896.18-155896.93" + wire $not$libresoc.v:155896$8313_Y + attribute \src "libresoc.v:155898.17-155898.92" + wire $not$libresoc.v:155898$8315_Y + attribute \src "libresoc.v:155901.17-155901.92" + wire $not$libresoc.v:155901$8318_Y + attribute \src "libresoc.v:155895.18-155895.98" + wire $or$libresoc.v:155895$8312_Y + attribute \src "libresoc.v:155897.18-155897.99" + wire $or$libresoc.v:155897$8314_Y + attribute \src "libresoc.v:155900.17-155900.97" + wire $or$libresoc.v:155900$8317_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -322506,11 +325093,11 @@ module \opc_l$120 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:153967.7-153967.15" + attribute \src "libresoc.v:155859.7-155859.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -322527,7 +325114,7 @@ module \opc_l$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:154002$8266 + cell $and $and$libresoc.v:155894$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322535,10 +325122,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:154002$8266_Y + connect \Y $and$libresoc.v:155894$8311_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:154007$8271 + cell $and $and$libresoc.v:155899$8316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322546,34 +325133,34 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:154007$8271_Y + connect \Y $and$libresoc.v:155899$8316_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:154004$8268 + cell $not $not$libresoc.v:155896$8313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:154004$8268_Y + connect \Y $not$libresoc.v:155896$8313_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:154006$8270 + cell $not $not$libresoc.v:155898$8315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154006$8270_Y + connect \Y $not$libresoc.v:155898$8315_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:154009$8273 + cell $not $not$libresoc.v:155901$8318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154009$8273_Y + connect \Y $not$libresoc.v:155901$8318_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:154003$8267 + cell $or $or$libresoc.v:155895$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322581,10 +325168,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:154003$8267_Y + connect \Y $or$libresoc.v:155895$8312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:154005$8269 + cell $or $or$libresoc.v:155897$8314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322592,10 +325179,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:154005$8269_Y + connect \Y $or$libresoc.v:155897$8314_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:154008$8272 + cell $or $or$libresoc.v:155900$8317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322603,39 +325190,39 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:154008$8272_Y + connect \Y $or$libresoc.v:155900$8317_Y end - attribute \src "libresoc.v:153967.7-153967.20" - process $proc$libresoc.v:153967$8278 + attribute \src "libresoc.v:155859.7-155859.20" + process $proc$libresoc.v:155859$8323 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153989.7-153989.19" - process $proc$libresoc.v:153989$8279 + attribute \src "libresoc.v:155881.7-155881.19" + process $proc$libresoc.v:155881$8324 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:154010.3-154011.27" - process $proc$libresoc.v:154010$8274 + attribute \src "libresoc.v:155902.3-155903.27" + process $proc$libresoc.v:155902$8319 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:154012.3-154020.6" - process $proc$libresoc.v:154012$8275 + attribute \src "libresoc.v:155904.3-155912.6" + process $proc$libresoc.v:155904$8320 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8276 $1\q_int$next[0:0]$8277 - attribute \src "libresoc.v:154013.5-154013.29" + assign $0\q_int$next[0:0]$8321 $1\q_int$next[0:0]$8322 + attribute \src "libresoc.v:155905.5-155905.29" switch \initial - attribute \src "libresoc.v:154013.9-154013.17" + attribute \src "libresoc.v:155905.9-155905.17" case 1'1 case end @@ -322644,56 +325231,56 @@ module \opc_l$120 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8277 1'0 + assign $1\q_int$next[0:0]$8322 1'0 case - assign $1\q_int$next[0:0]$8277 \$5 + assign $1\q_int$next[0:0]$8322 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8276 + update \q_int$next $0\q_int$next[0:0]$8321 end - connect \$9 $and$libresoc.v:154002$8266_Y - connect \$11 $or$libresoc.v:154003$8267_Y - connect \$13 $not$libresoc.v:154004$8268_Y - connect \$15 $or$libresoc.v:154005$8269_Y - connect \$1 $not$libresoc.v:154006$8270_Y - connect \$3 $and$libresoc.v:154007$8271_Y - connect \$5 $or$libresoc.v:154008$8272_Y - connect \$7 $not$libresoc.v:154009$8273_Y + connect \$9 $and$libresoc.v:155894$8311_Y + connect \$11 $or$libresoc.v:155895$8312_Y + connect \$13 $not$libresoc.v:155896$8313_Y + connect \$15 $or$libresoc.v:155897$8314_Y + connect \$1 $not$libresoc.v:155898$8315_Y + connect \$3 $and$libresoc.v:155899$8316_Y + connect \$5 $or$libresoc.v:155900$8317_Y + connect \$7 $not$libresoc.v:155901$8318_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:154028.1-154086.10" +attribute \src "libresoc.v:155920.1-155978.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 - attribute \src "libresoc.v:154029.7-154029.20" + attribute \src "libresoc.v:155921.7-155921.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154074.3-154082.6" - wire $0\q_int$next[0:0]$8290 - attribute \src "libresoc.v:154072.3-154073.27" + attribute \src "libresoc.v:155966.3-155974.6" + wire $0\q_int$next[0:0]$8335 + attribute \src "libresoc.v:155964.3-155965.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:154074.3-154082.6" - wire $1\q_int$next[0:0]$8291 - attribute \src "libresoc.v:154051.7-154051.19" + attribute \src "libresoc.v:155966.3-155974.6" + wire $1\q_int$next[0:0]$8336 + attribute \src "libresoc.v:155943.7-155943.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:154064.17-154064.96" - wire $and$libresoc.v:154064$8280_Y - attribute \src "libresoc.v:154069.17-154069.96" - wire $and$libresoc.v:154069$8285_Y - attribute \src "libresoc.v:154066.18-154066.93" - wire $not$libresoc.v:154066$8282_Y - attribute \src "libresoc.v:154068.17-154068.92" - wire $not$libresoc.v:154068$8284_Y - attribute \src "libresoc.v:154071.17-154071.92" - wire $not$libresoc.v:154071$8287_Y - attribute \src "libresoc.v:154065.18-154065.98" - wire $or$libresoc.v:154065$8281_Y - attribute \src "libresoc.v:154067.18-154067.99" - wire $or$libresoc.v:154067$8283_Y - attribute \src "libresoc.v:154070.17-154070.97" - wire $or$libresoc.v:154070$8286_Y + attribute \src "libresoc.v:155956.17-155956.96" + wire $and$libresoc.v:155956$8325_Y + attribute \src "libresoc.v:155961.17-155961.96" + wire $and$libresoc.v:155961$8330_Y + attribute \src "libresoc.v:155958.18-155958.93" + wire $not$libresoc.v:155958$8327_Y + attribute \src "libresoc.v:155960.17-155960.92" + wire $not$libresoc.v:155960$8329_Y + attribute \src "libresoc.v:155963.17-155963.92" + wire $not$libresoc.v:155963$8332_Y + attribute \src "libresoc.v:155957.18-155957.98" + wire $or$libresoc.v:155957$8326_Y + attribute \src "libresoc.v:155959.18-155959.99" + wire $or$libresoc.v:155959$8328_Y + attribute \src "libresoc.v:155962.17-155962.97" + wire $or$libresoc.v:155962$8331_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -322710,11 +325297,11 @@ module \opc_l$126 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:154029.7-154029.15" + attribute \src "libresoc.v:155921.7-155921.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -322731,7 +325318,7 @@ module \opc_l$126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:154064$8280 + cell $and $and$libresoc.v:155956$8325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322739,10 +325326,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:154064$8280_Y + connect \Y $and$libresoc.v:155956$8325_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:154069$8285 + cell $and $and$libresoc.v:155961$8330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322750,34 +325337,34 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:154069$8285_Y + connect \Y $and$libresoc.v:155961$8330_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:154066$8282 + cell $not $not$libresoc.v:155958$8327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:154066$8282_Y + connect \Y $not$libresoc.v:155958$8327_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:154068$8284 + cell $not $not$libresoc.v:155960$8329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154068$8284_Y + connect \Y $not$libresoc.v:155960$8329_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:154071$8287 + cell $not $not$libresoc.v:155963$8332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154071$8287_Y + connect \Y $not$libresoc.v:155963$8332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:154065$8281 + cell $or $or$libresoc.v:155957$8326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322785,10 +325372,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:154065$8281_Y + connect \Y $or$libresoc.v:155957$8326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:154067$8283 + cell $or $or$libresoc.v:155959$8328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322796,10 +325383,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:154067$8283_Y + connect \Y $or$libresoc.v:155959$8328_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:154070$8286 + cell $or $or$libresoc.v:155962$8331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322807,39 +325394,39 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:154070$8286_Y + connect \Y $or$libresoc.v:155962$8331_Y end - attribute \src "libresoc.v:154029.7-154029.20" - process $proc$libresoc.v:154029$8292 + attribute \src "libresoc.v:155921.7-155921.20" + process $proc$libresoc.v:155921$8337 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154051.7-154051.19" - process $proc$libresoc.v:154051$8293 + attribute \src "libresoc.v:155943.7-155943.19" + process $proc$libresoc.v:155943$8338 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:154072.3-154073.27" - process $proc$libresoc.v:154072$8288 + attribute \src "libresoc.v:155964.3-155965.27" + process $proc$libresoc.v:155964$8333 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:154074.3-154082.6" - process $proc$libresoc.v:154074$8289 + attribute \src "libresoc.v:155966.3-155974.6" + process $proc$libresoc.v:155966$8334 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8290 $1\q_int$next[0:0]$8291 - attribute \src "libresoc.v:154075.5-154075.29" + assign $0\q_int$next[0:0]$8335 $1\q_int$next[0:0]$8336 + attribute \src "libresoc.v:155967.5-155967.29" switch \initial - attribute \src "libresoc.v:154075.9-154075.17" + attribute \src "libresoc.v:155967.9-155967.17" case 1'1 case end @@ -322848,56 +325435,56 @@ module \opc_l$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8291 1'0 + assign $1\q_int$next[0:0]$8336 1'0 case - assign $1\q_int$next[0:0]$8291 \$5 + assign $1\q_int$next[0:0]$8336 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8290 + update \q_int$next $0\q_int$next[0:0]$8335 end - connect \$9 $and$libresoc.v:154064$8280_Y - connect \$11 $or$libresoc.v:154065$8281_Y - connect \$13 $not$libresoc.v:154066$8282_Y - connect \$15 $or$libresoc.v:154067$8283_Y - connect \$1 $not$libresoc.v:154068$8284_Y - connect \$3 $and$libresoc.v:154069$8285_Y - connect \$5 $or$libresoc.v:154070$8286_Y - connect \$7 $not$libresoc.v:154071$8287_Y + connect \$9 $and$libresoc.v:155956$8325_Y + connect \$11 $or$libresoc.v:155957$8326_Y + connect \$13 $not$libresoc.v:155958$8327_Y + connect \$15 $or$libresoc.v:155959$8328_Y + connect \$1 $not$libresoc.v:155960$8329_Y + connect \$3 $and$libresoc.v:155961$8330_Y + connect \$5 $or$libresoc.v:155962$8331_Y + connect \$7 $not$libresoc.v:155963$8332_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:154090.1-154148.10" +attribute \src "libresoc.v:155982.1-156040.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 - attribute \src "libresoc.v:154091.7-154091.20" + attribute \src "libresoc.v:155983.7-155983.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154136.3-154144.6" - wire $0\q_int$next[0:0]$8304 - attribute \src "libresoc.v:154134.3-154135.27" + attribute \src "libresoc.v:156028.3-156036.6" + wire $0\q_int$next[0:0]$8349 + attribute \src "libresoc.v:156026.3-156027.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:154136.3-154144.6" - wire $1\q_int$next[0:0]$8305 - attribute \src "libresoc.v:154113.7-154113.19" + attribute \src "libresoc.v:156028.3-156036.6" + wire $1\q_int$next[0:0]$8350 + attribute \src "libresoc.v:156005.7-156005.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:154126.17-154126.96" - wire $and$libresoc.v:154126$8294_Y - attribute \src "libresoc.v:154131.17-154131.96" - wire $and$libresoc.v:154131$8299_Y - attribute \src "libresoc.v:154128.18-154128.93" - wire $not$libresoc.v:154128$8296_Y - attribute \src "libresoc.v:154130.17-154130.92" - wire $not$libresoc.v:154130$8298_Y - attribute \src "libresoc.v:154133.17-154133.92" - wire $not$libresoc.v:154133$8301_Y - attribute \src "libresoc.v:154127.18-154127.98" - wire $or$libresoc.v:154127$8295_Y - attribute \src "libresoc.v:154129.18-154129.99" - wire $or$libresoc.v:154129$8297_Y - attribute \src "libresoc.v:154132.17-154132.97" - wire $or$libresoc.v:154132$8300_Y + attribute \src "libresoc.v:156018.17-156018.96" + wire $and$libresoc.v:156018$8339_Y + attribute \src "libresoc.v:156023.17-156023.96" + wire $and$libresoc.v:156023$8344_Y + attribute \src "libresoc.v:156020.18-156020.93" + wire $not$libresoc.v:156020$8341_Y + attribute \src "libresoc.v:156022.17-156022.92" + wire $not$libresoc.v:156022$8343_Y + attribute \src "libresoc.v:156025.17-156025.92" + wire $not$libresoc.v:156025$8346_Y + attribute \src "libresoc.v:156019.18-156019.98" + wire $or$libresoc.v:156019$8340_Y + attribute \src "libresoc.v:156021.18-156021.99" + wire $or$libresoc.v:156021$8342_Y + attribute \src "libresoc.v:156024.17-156024.97" + wire $or$libresoc.v:156024$8345_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -322914,11 +325501,11 @@ module \opc_l$24 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:154091.7-154091.15" + attribute \src "libresoc.v:155983.7-155983.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -322935,7 +325522,7 @@ module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:154126$8294 + cell $and $and$libresoc.v:156018$8339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322943,10 +325530,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:154126$8294_Y + connect \Y $and$libresoc.v:156018$8339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:154131$8299 + cell $and $and$libresoc.v:156023$8344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322954,34 +325541,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:154131$8299_Y + connect \Y $and$libresoc.v:156023$8344_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:154128$8296 + cell $not $not$libresoc.v:156020$8341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:154128$8296_Y + connect \Y $not$libresoc.v:156020$8341_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:154130$8298 + cell $not $not$libresoc.v:156022$8343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154130$8298_Y + connect \Y $not$libresoc.v:156022$8343_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:154133$8301 + cell $not $not$libresoc.v:156025$8346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154133$8301_Y + connect \Y $not$libresoc.v:156025$8346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:154127$8295 + cell $or $or$libresoc.v:156019$8340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322989,10 +325576,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:154127$8295_Y + connect \Y $or$libresoc.v:156019$8340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:154129$8297 + cell $or $or$libresoc.v:156021$8342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323000,10 +325587,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:154129$8297_Y + connect \Y $or$libresoc.v:156021$8342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:154132$8300 + cell $or $or$libresoc.v:156024$8345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323011,39 +325598,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:154132$8300_Y + connect \Y $or$libresoc.v:156024$8345_Y end - attribute \src "libresoc.v:154091.7-154091.20" - process $proc$libresoc.v:154091$8306 + attribute \src "libresoc.v:155983.7-155983.20" + process $proc$libresoc.v:155983$8351 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154113.7-154113.19" - process $proc$libresoc.v:154113$8307 + attribute \src "libresoc.v:156005.7-156005.19" + process $proc$libresoc.v:156005$8352 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:154134.3-154135.27" - process $proc$libresoc.v:154134$8302 + attribute \src "libresoc.v:156026.3-156027.27" + process $proc$libresoc.v:156026$8347 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:154136.3-154144.6" - process $proc$libresoc.v:154136$8303 + attribute \src "libresoc.v:156028.3-156036.6" + process $proc$libresoc.v:156028$8348 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8304 $1\q_int$next[0:0]$8305 - attribute \src "libresoc.v:154137.5-154137.29" + assign $0\q_int$next[0:0]$8349 $1\q_int$next[0:0]$8350 + attribute \src "libresoc.v:156029.5-156029.29" switch \initial - attribute \src "libresoc.v:154137.9-154137.17" + attribute \src "libresoc.v:156029.9-156029.17" case 1'1 case end @@ -323052,56 +325639,56 @@ module \opc_l$24 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8305 1'0 + assign $1\q_int$next[0:0]$8350 1'0 case - assign $1\q_int$next[0:0]$8305 \$5 + assign $1\q_int$next[0:0]$8350 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8304 + update \q_int$next $0\q_int$next[0:0]$8349 end - connect \$9 $and$libresoc.v:154126$8294_Y - connect \$11 $or$libresoc.v:154127$8295_Y - connect \$13 $not$libresoc.v:154128$8296_Y - connect \$15 $or$libresoc.v:154129$8297_Y - connect \$1 $not$libresoc.v:154130$8298_Y - connect \$3 $and$libresoc.v:154131$8299_Y - connect \$5 $or$libresoc.v:154132$8300_Y - connect \$7 $not$libresoc.v:154133$8301_Y + connect \$9 $and$libresoc.v:156018$8339_Y + connect \$11 $or$libresoc.v:156019$8340_Y + connect \$13 $not$libresoc.v:156020$8341_Y + connect \$15 $or$libresoc.v:156021$8342_Y + connect \$1 $not$libresoc.v:156022$8343_Y + connect \$3 $and$libresoc.v:156023$8344_Y + connect \$5 $or$libresoc.v:156024$8345_Y + connect \$7 $not$libresoc.v:156025$8346_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:154152.1-154210.10" +attribute \src "libresoc.v:156044.1-156102.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 - attribute \src "libresoc.v:154153.7-154153.20" + attribute \src "libresoc.v:156045.7-156045.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154198.3-154206.6" - wire $0\q_int$next[0:0]$8318 - attribute \src "libresoc.v:154196.3-154197.27" + attribute \src "libresoc.v:156090.3-156098.6" + wire $0\q_int$next[0:0]$8363 + attribute \src "libresoc.v:156088.3-156089.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:154198.3-154206.6" - wire $1\q_int$next[0:0]$8319 - attribute \src "libresoc.v:154175.7-154175.19" + attribute \src "libresoc.v:156090.3-156098.6" + wire $1\q_int$next[0:0]$8364 + attribute \src "libresoc.v:156067.7-156067.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:154188.17-154188.96" - wire $and$libresoc.v:154188$8308_Y - attribute \src "libresoc.v:154193.17-154193.96" - wire $and$libresoc.v:154193$8313_Y - attribute \src "libresoc.v:154190.18-154190.93" - wire $not$libresoc.v:154190$8310_Y - attribute \src "libresoc.v:154192.17-154192.92" - wire $not$libresoc.v:154192$8312_Y - attribute \src "libresoc.v:154195.17-154195.92" - wire $not$libresoc.v:154195$8315_Y - attribute \src "libresoc.v:154189.18-154189.98" - wire $or$libresoc.v:154189$8309_Y - attribute \src "libresoc.v:154191.18-154191.99" - wire $or$libresoc.v:154191$8311_Y - attribute \src "libresoc.v:154194.17-154194.97" - wire $or$libresoc.v:154194$8314_Y + attribute \src "libresoc.v:156080.17-156080.96" + wire $and$libresoc.v:156080$8353_Y + attribute \src "libresoc.v:156085.17-156085.96" + wire $and$libresoc.v:156085$8358_Y + attribute \src "libresoc.v:156082.18-156082.93" + wire $not$libresoc.v:156082$8355_Y + attribute \src "libresoc.v:156084.17-156084.92" + wire $not$libresoc.v:156084$8357_Y + attribute \src "libresoc.v:156087.17-156087.92" + wire $not$libresoc.v:156087$8360_Y + attribute \src "libresoc.v:156081.18-156081.98" + wire $or$libresoc.v:156081$8354_Y + attribute \src "libresoc.v:156083.18-156083.99" + wire $or$libresoc.v:156083$8356_Y + attribute \src "libresoc.v:156086.17-156086.97" + wire $or$libresoc.v:156086$8359_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -323118,11 +325705,11 @@ module \opc_l$40 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:154153.7-154153.15" + attribute \src "libresoc.v:156045.7-156045.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -323139,7 +325726,7 @@ module \opc_l$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:154188$8308 + cell $and $and$libresoc.v:156080$8353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323147,10 +325734,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:154188$8308_Y + connect \Y $and$libresoc.v:156080$8353_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:154193$8313 + cell $and $and$libresoc.v:156085$8358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323158,34 +325745,34 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:154193$8313_Y + connect \Y $and$libresoc.v:156085$8358_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:154190$8310 + cell $not $not$libresoc.v:156082$8355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:154190$8310_Y + connect \Y $not$libresoc.v:156082$8355_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:154192$8312 + cell $not $not$libresoc.v:156084$8357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154192$8312_Y + connect \Y $not$libresoc.v:156084$8357_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:154195$8315 + cell $not $not$libresoc.v:156087$8360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154195$8315_Y + connect \Y $not$libresoc.v:156087$8360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:154189$8309 + cell $or $or$libresoc.v:156081$8354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323193,10 +325780,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:154189$8309_Y + connect \Y $or$libresoc.v:156081$8354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:154191$8311 + cell $or $or$libresoc.v:156083$8356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323204,10 +325791,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:154191$8311_Y + connect \Y $or$libresoc.v:156083$8356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:154194$8314 + cell $or $or$libresoc.v:156086$8359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323215,39 +325802,39 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:154194$8314_Y + connect \Y $or$libresoc.v:156086$8359_Y end - attribute \src "libresoc.v:154153.7-154153.20" - process $proc$libresoc.v:154153$8320 + attribute \src "libresoc.v:156045.7-156045.20" + process $proc$libresoc.v:156045$8365 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154175.7-154175.19" - process $proc$libresoc.v:154175$8321 + attribute \src "libresoc.v:156067.7-156067.19" + process $proc$libresoc.v:156067$8366 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:154196.3-154197.27" - process $proc$libresoc.v:154196$8316 + attribute \src "libresoc.v:156088.3-156089.27" + process $proc$libresoc.v:156088$8361 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:154198.3-154206.6" - process $proc$libresoc.v:154198$8317 + attribute \src "libresoc.v:156090.3-156098.6" + process $proc$libresoc.v:156090$8362 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8318 $1\q_int$next[0:0]$8319 - attribute \src "libresoc.v:154199.5-154199.29" + assign $0\q_int$next[0:0]$8363 $1\q_int$next[0:0]$8364 + attribute \src "libresoc.v:156091.5-156091.29" switch \initial - attribute \src "libresoc.v:154199.9-154199.17" + attribute \src "libresoc.v:156091.9-156091.17" case 1'1 case end @@ -323256,56 +325843,56 @@ module \opc_l$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8319 1'0 + assign $1\q_int$next[0:0]$8364 1'0 case - assign $1\q_int$next[0:0]$8319 \$5 + assign $1\q_int$next[0:0]$8364 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8318 + update \q_int$next $0\q_int$next[0:0]$8363 end - connect \$9 $and$libresoc.v:154188$8308_Y - connect \$11 $or$libresoc.v:154189$8309_Y - connect \$13 $not$libresoc.v:154190$8310_Y - connect \$15 $or$libresoc.v:154191$8311_Y - connect \$1 $not$libresoc.v:154192$8312_Y - connect \$3 $and$libresoc.v:154193$8313_Y - connect \$5 $or$libresoc.v:154194$8314_Y - connect \$7 $not$libresoc.v:154195$8315_Y + connect \$9 $and$libresoc.v:156080$8353_Y + connect \$11 $or$libresoc.v:156081$8354_Y + connect \$13 $not$libresoc.v:156082$8355_Y + connect \$15 $or$libresoc.v:156083$8356_Y + connect \$1 $not$libresoc.v:156084$8357_Y + connect \$3 $and$libresoc.v:156085$8358_Y + connect \$5 $or$libresoc.v:156086$8359_Y + connect \$7 $not$libresoc.v:156087$8360_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:154214.1-154272.10" +attribute \src "libresoc.v:156106.1-156164.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 - attribute \src "libresoc.v:154215.7-154215.20" + attribute \src "libresoc.v:156107.7-156107.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154260.3-154268.6" - wire $0\q_int$next[0:0]$8332 - attribute \src "libresoc.v:154258.3-154259.27" + attribute \src "libresoc.v:156152.3-156160.6" + wire $0\q_int$next[0:0]$8377 + attribute \src "libresoc.v:156150.3-156151.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:154260.3-154268.6" - wire $1\q_int$next[0:0]$8333 - attribute \src "libresoc.v:154237.7-154237.19" + attribute \src "libresoc.v:156152.3-156160.6" + wire $1\q_int$next[0:0]$8378 + attribute \src "libresoc.v:156129.7-156129.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:154250.17-154250.96" - wire $and$libresoc.v:154250$8322_Y - attribute \src "libresoc.v:154255.17-154255.96" - wire $and$libresoc.v:154255$8327_Y - attribute \src "libresoc.v:154252.18-154252.93" - wire $not$libresoc.v:154252$8324_Y - attribute \src "libresoc.v:154254.17-154254.92" - wire $not$libresoc.v:154254$8326_Y - attribute \src "libresoc.v:154257.17-154257.92" - wire $not$libresoc.v:154257$8329_Y - attribute \src "libresoc.v:154251.18-154251.98" - wire $or$libresoc.v:154251$8323_Y - attribute \src "libresoc.v:154253.18-154253.99" - wire $or$libresoc.v:154253$8325_Y - attribute \src "libresoc.v:154256.17-154256.97" - wire $or$libresoc.v:154256$8328_Y + attribute \src "libresoc.v:156142.17-156142.96" + wire $and$libresoc.v:156142$8367_Y + attribute \src "libresoc.v:156147.17-156147.96" + wire $and$libresoc.v:156147$8372_Y + attribute \src "libresoc.v:156144.18-156144.93" + wire $not$libresoc.v:156144$8369_Y + attribute \src "libresoc.v:156146.17-156146.92" + wire $not$libresoc.v:156146$8371_Y + attribute \src "libresoc.v:156149.17-156149.92" + wire $not$libresoc.v:156149$8374_Y + attribute \src "libresoc.v:156143.18-156143.98" + wire $or$libresoc.v:156143$8368_Y + attribute \src "libresoc.v:156145.18-156145.99" + wire $or$libresoc.v:156145$8370_Y + attribute \src "libresoc.v:156148.17-156148.97" + wire $or$libresoc.v:156148$8373_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -323322,11 +325909,11 @@ module \opc_l$56 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:154215.7-154215.15" + attribute \src "libresoc.v:156107.7-156107.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -323343,7 +325930,7 @@ module \opc_l$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:154250$8322 + cell $and $and$libresoc.v:156142$8367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323351,10 +325938,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:154250$8322_Y + connect \Y $and$libresoc.v:156142$8367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:154255$8327 + cell $and $and$libresoc.v:156147$8372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323362,34 +325949,34 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:154255$8327_Y + connect \Y $and$libresoc.v:156147$8372_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:154252$8324 + cell $not $not$libresoc.v:156144$8369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:154252$8324_Y + connect \Y $not$libresoc.v:156144$8369_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:154254$8326 + cell $not $not$libresoc.v:156146$8371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154254$8326_Y + connect \Y $not$libresoc.v:156146$8371_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:154257$8329 + cell $not $not$libresoc.v:156149$8374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154257$8329_Y + connect \Y $not$libresoc.v:156149$8374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:154251$8323 + cell $or $or$libresoc.v:156143$8368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323397,10 +325984,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:154251$8323_Y + connect \Y $or$libresoc.v:156143$8368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:154253$8325 + cell $or $or$libresoc.v:156145$8370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323408,10 +325995,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:154253$8325_Y + connect \Y $or$libresoc.v:156145$8370_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:154256$8328 + cell $or $or$libresoc.v:156148$8373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323419,39 +326006,39 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:154256$8328_Y + connect \Y $or$libresoc.v:156148$8373_Y end - attribute \src "libresoc.v:154215.7-154215.20" - process $proc$libresoc.v:154215$8334 + attribute \src "libresoc.v:156107.7-156107.20" + process $proc$libresoc.v:156107$8379 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154237.7-154237.19" - process $proc$libresoc.v:154237$8335 + attribute \src "libresoc.v:156129.7-156129.19" + process $proc$libresoc.v:156129$8380 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:154258.3-154259.27" - process $proc$libresoc.v:154258$8330 + attribute \src "libresoc.v:156150.3-156151.27" + process $proc$libresoc.v:156150$8375 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:154260.3-154268.6" - process $proc$libresoc.v:154260$8331 + attribute \src "libresoc.v:156152.3-156160.6" + process $proc$libresoc.v:156152$8376 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8332 $1\q_int$next[0:0]$8333 - attribute \src "libresoc.v:154261.5-154261.29" + assign $0\q_int$next[0:0]$8377 $1\q_int$next[0:0]$8378 + attribute \src "libresoc.v:156153.5-156153.29" switch \initial - attribute \src "libresoc.v:154261.9-154261.17" + attribute \src "libresoc.v:156153.9-156153.17" case 1'1 case end @@ -323460,56 +326047,56 @@ module \opc_l$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8333 1'0 + assign $1\q_int$next[0:0]$8378 1'0 case - assign $1\q_int$next[0:0]$8333 \$5 + assign $1\q_int$next[0:0]$8378 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8332 + update \q_int$next $0\q_int$next[0:0]$8377 end - connect \$9 $and$libresoc.v:154250$8322_Y - connect \$11 $or$libresoc.v:154251$8323_Y - connect \$13 $not$libresoc.v:154252$8324_Y - connect \$15 $or$libresoc.v:154253$8325_Y - connect \$1 $not$libresoc.v:154254$8326_Y - connect \$3 $and$libresoc.v:154255$8327_Y - connect \$5 $or$libresoc.v:154256$8328_Y - connect \$7 $not$libresoc.v:154257$8329_Y + connect \$9 $and$libresoc.v:156142$8367_Y + connect \$11 $or$libresoc.v:156143$8368_Y + connect \$13 $not$libresoc.v:156144$8369_Y + connect \$15 $or$libresoc.v:156145$8370_Y + connect \$1 $not$libresoc.v:156146$8371_Y + connect \$3 $and$libresoc.v:156147$8372_Y + connect \$5 $or$libresoc.v:156148$8373_Y + connect \$7 $not$libresoc.v:156149$8374_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:154276.1-154334.10" +attribute \src "libresoc.v:156168.1-156226.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 - attribute \src "libresoc.v:154277.7-154277.20" + attribute \src "libresoc.v:156169.7-156169.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154322.3-154330.6" - wire $0\q_int$next[0:0]$8346 - attribute \src "libresoc.v:154320.3-154321.27" + attribute \src "libresoc.v:156214.3-156222.6" + wire $0\q_int$next[0:0]$8391 + attribute \src "libresoc.v:156212.3-156213.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:154322.3-154330.6" - wire $1\q_int$next[0:0]$8347 - attribute \src "libresoc.v:154299.7-154299.19" + attribute \src "libresoc.v:156214.3-156222.6" + wire $1\q_int$next[0:0]$8392 + attribute \src "libresoc.v:156191.7-156191.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:154312.17-154312.96" - wire $and$libresoc.v:154312$8336_Y - attribute \src "libresoc.v:154317.17-154317.96" - wire $and$libresoc.v:154317$8341_Y - attribute \src "libresoc.v:154314.18-154314.93" - wire $not$libresoc.v:154314$8338_Y - attribute \src "libresoc.v:154316.17-154316.92" - wire $not$libresoc.v:154316$8340_Y - attribute \src "libresoc.v:154319.17-154319.92" - wire $not$libresoc.v:154319$8343_Y - attribute \src "libresoc.v:154313.18-154313.98" - wire $or$libresoc.v:154313$8337_Y - attribute \src "libresoc.v:154315.18-154315.99" - wire $or$libresoc.v:154315$8339_Y - attribute \src "libresoc.v:154318.17-154318.97" - wire $or$libresoc.v:154318$8342_Y + attribute \src "libresoc.v:156204.17-156204.96" + wire $and$libresoc.v:156204$8381_Y + attribute \src "libresoc.v:156209.17-156209.96" + wire $and$libresoc.v:156209$8386_Y + attribute \src "libresoc.v:156206.18-156206.93" + wire $not$libresoc.v:156206$8383_Y + attribute \src "libresoc.v:156208.17-156208.92" + wire $not$libresoc.v:156208$8385_Y + attribute \src "libresoc.v:156211.17-156211.92" + wire $not$libresoc.v:156211$8388_Y + attribute \src "libresoc.v:156205.18-156205.98" + wire $or$libresoc.v:156205$8382_Y + attribute \src "libresoc.v:156207.18-156207.99" + wire $or$libresoc.v:156207$8384_Y + attribute \src "libresoc.v:156210.17-156210.97" + wire $or$libresoc.v:156210$8387_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -323526,11 +326113,11 @@ module \opc_l$68 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:154277.7-154277.15" + attribute \src "libresoc.v:156169.7-156169.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -323547,7 +326134,7 @@ module \opc_l$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:154312$8336 + cell $and $and$libresoc.v:156204$8381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323555,10 +326142,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:154312$8336_Y + connect \Y $and$libresoc.v:156204$8381_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:154317$8341 + cell $and $and$libresoc.v:156209$8386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323566,34 +326153,34 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:154317$8341_Y + connect \Y $and$libresoc.v:156209$8386_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:154314$8338 + cell $not $not$libresoc.v:156206$8383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:154314$8338_Y + connect \Y $not$libresoc.v:156206$8383_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:154316$8340 + cell $not $not$libresoc.v:156208$8385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154316$8340_Y + connect \Y $not$libresoc.v:156208$8385_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:154319$8343 + cell $not $not$libresoc.v:156211$8388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154319$8343_Y + connect \Y $not$libresoc.v:156211$8388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:154313$8337 + cell $or $or$libresoc.v:156205$8382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323601,10 +326188,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:154313$8337_Y + connect \Y $or$libresoc.v:156205$8382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:154315$8339 + cell $or $or$libresoc.v:156207$8384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323612,10 +326199,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:154315$8339_Y + connect \Y $or$libresoc.v:156207$8384_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:154318$8342 + cell $or $or$libresoc.v:156210$8387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323623,39 +326210,39 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:154318$8342_Y + connect \Y $or$libresoc.v:156210$8387_Y end - attribute \src "libresoc.v:154277.7-154277.20" - process $proc$libresoc.v:154277$8348 + attribute \src "libresoc.v:156169.7-156169.20" + process $proc$libresoc.v:156169$8393 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154299.7-154299.19" - process $proc$libresoc.v:154299$8349 + attribute \src "libresoc.v:156191.7-156191.19" + process $proc$libresoc.v:156191$8394 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:154320.3-154321.27" - process $proc$libresoc.v:154320$8344 + attribute \src "libresoc.v:156212.3-156213.27" + process $proc$libresoc.v:156212$8389 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:154322.3-154330.6" - process $proc$libresoc.v:154322$8345 + attribute \src "libresoc.v:156214.3-156222.6" + process $proc$libresoc.v:156214$8390 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8346 $1\q_int$next[0:0]$8347 - attribute \src "libresoc.v:154323.5-154323.29" + assign $0\q_int$next[0:0]$8391 $1\q_int$next[0:0]$8392 + attribute \src "libresoc.v:156215.5-156215.29" switch \initial - attribute \src "libresoc.v:154323.9-154323.17" + attribute \src "libresoc.v:156215.9-156215.17" case 1'1 case end @@ -323664,56 +326251,56 @@ module \opc_l$68 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8347 1'0 + assign $1\q_int$next[0:0]$8392 1'0 case - assign $1\q_int$next[0:0]$8347 \$5 + assign $1\q_int$next[0:0]$8392 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8346 + update \q_int$next $0\q_int$next[0:0]$8391 end - connect \$9 $and$libresoc.v:154312$8336_Y - connect \$11 $or$libresoc.v:154313$8337_Y - connect \$13 $not$libresoc.v:154314$8338_Y - connect \$15 $or$libresoc.v:154315$8339_Y - connect \$1 $not$libresoc.v:154316$8340_Y - connect \$3 $and$libresoc.v:154317$8341_Y - connect \$5 $or$libresoc.v:154318$8342_Y - connect \$7 $not$libresoc.v:154319$8343_Y + connect \$9 $and$libresoc.v:156204$8381_Y + connect \$11 $or$libresoc.v:156205$8382_Y + connect \$13 $not$libresoc.v:156206$8383_Y + connect \$15 $or$libresoc.v:156207$8384_Y + connect \$1 $not$libresoc.v:156208$8385_Y + connect \$3 $and$libresoc.v:156209$8386_Y + connect \$5 $or$libresoc.v:156210$8387_Y + connect \$7 $not$libresoc.v:156211$8388_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:154338.1-154396.10" +attribute \src "libresoc.v:156230.1-156288.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 - attribute \src "libresoc.v:154339.7-154339.20" + attribute \src "libresoc.v:156231.7-156231.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154384.3-154392.6" - wire $0\q_int$next[0:0]$8360 - attribute \src "libresoc.v:154382.3-154383.27" + attribute \src "libresoc.v:156276.3-156284.6" + wire $0\q_int$next[0:0]$8405 + attribute \src "libresoc.v:156274.3-156275.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:154384.3-154392.6" - wire $1\q_int$next[0:0]$8361 - attribute \src "libresoc.v:154361.7-154361.19" + attribute \src "libresoc.v:156276.3-156284.6" + wire $1\q_int$next[0:0]$8406 + attribute \src "libresoc.v:156253.7-156253.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:154374.17-154374.96" - wire $and$libresoc.v:154374$8350_Y - attribute \src "libresoc.v:154379.17-154379.96" - wire $and$libresoc.v:154379$8355_Y - attribute \src "libresoc.v:154376.18-154376.93" - wire $not$libresoc.v:154376$8352_Y - attribute \src "libresoc.v:154378.17-154378.92" - wire $not$libresoc.v:154378$8354_Y - attribute \src "libresoc.v:154381.17-154381.92" - wire $not$libresoc.v:154381$8357_Y - attribute \src "libresoc.v:154375.18-154375.98" - wire $or$libresoc.v:154375$8351_Y - attribute \src "libresoc.v:154377.18-154377.99" - wire $or$libresoc.v:154377$8353_Y - attribute \src "libresoc.v:154380.17-154380.97" - wire $or$libresoc.v:154380$8356_Y + attribute \src "libresoc.v:156266.17-156266.96" + wire $and$libresoc.v:156266$8395_Y + attribute \src "libresoc.v:156271.17-156271.96" + wire $and$libresoc.v:156271$8400_Y + attribute \src "libresoc.v:156268.18-156268.93" + wire $not$libresoc.v:156268$8397_Y + attribute \src "libresoc.v:156270.17-156270.92" + wire $not$libresoc.v:156270$8399_Y + attribute \src "libresoc.v:156273.17-156273.92" + wire $not$libresoc.v:156273$8402_Y + attribute \src "libresoc.v:156267.18-156267.98" + wire $or$libresoc.v:156267$8396_Y + attribute \src "libresoc.v:156269.18-156269.99" + wire $or$libresoc.v:156269$8398_Y + attribute \src "libresoc.v:156272.17-156272.97" + wire $or$libresoc.v:156272$8401_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -323730,11 +326317,11 @@ module \opc_l$85 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:154339.7-154339.15" + attribute \src "libresoc.v:156231.7-156231.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -323751,7 +326338,7 @@ module \opc_l$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:154374$8350 + cell $and $and$libresoc.v:156266$8395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323759,10 +326346,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:154374$8350_Y + connect \Y $and$libresoc.v:156266$8395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:154379$8355 + cell $and $and$libresoc.v:156271$8400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323770,34 +326357,34 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:154379$8355_Y + connect \Y $and$libresoc.v:156271$8400_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:154376$8352 + cell $not $not$libresoc.v:156268$8397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:154376$8352_Y + connect \Y $not$libresoc.v:156268$8397_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:154378$8354 + cell $not $not$libresoc.v:156270$8399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154378$8354_Y + connect \Y $not$libresoc.v:156270$8399_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:154381$8357 + cell $not $not$libresoc.v:156273$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:154381$8357_Y + connect \Y $not$libresoc.v:156273$8402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:154375$8351 + cell $or $or$libresoc.v:156267$8396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323805,10 +326392,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:154375$8351_Y + connect \Y $or$libresoc.v:156267$8396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:154377$8353 + cell $or $or$libresoc.v:156269$8398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323816,10 +326403,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:154377$8353_Y + connect \Y $or$libresoc.v:156269$8398_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:154380$8356 + cell $or $or$libresoc.v:156272$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323827,39 +326414,39 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:154380$8356_Y + connect \Y $or$libresoc.v:156272$8401_Y end - attribute \src "libresoc.v:154339.7-154339.20" - process $proc$libresoc.v:154339$8362 + attribute \src "libresoc.v:156231.7-156231.20" + process $proc$libresoc.v:156231$8407 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154361.7-154361.19" - process $proc$libresoc.v:154361$8363 + attribute \src "libresoc.v:156253.7-156253.19" + process $proc$libresoc.v:156253$8408 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:154382.3-154383.27" - process $proc$libresoc.v:154382$8358 + attribute \src "libresoc.v:156274.3-156275.27" + process $proc$libresoc.v:156274$8403 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:154384.3-154392.6" - process $proc$libresoc.v:154384$8359 + attribute \src "libresoc.v:156276.3-156284.6" + process $proc$libresoc.v:156276$8404 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8360 $1\q_int$next[0:0]$8361 - attribute \src "libresoc.v:154385.5-154385.29" + assign $0\q_int$next[0:0]$8405 $1\q_int$next[0:0]$8406 + attribute \src "libresoc.v:156277.5-156277.29" switch \initial - attribute \src "libresoc.v:154385.9-154385.17" + attribute \src "libresoc.v:156277.9-156277.17" case 1'1 case end @@ -323868,90 +326455,90 @@ module \opc_l$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8361 1'0 + assign $1\q_int$next[0:0]$8406 1'0 case - assign $1\q_int$next[0:0]$8361 \$5 + assign $1\q_int$next[0:0]$8406 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8360 + update \q_int$next $0\q_int$next[0:0]$8405 end - connect \$9 $and$libresoc.v:154374$8350_Y - connect \$11 $or$libresoc.v:154375$8351_Y - connect \$13 $not$libresoc.v:154376$8352_Y - connect \$15 $or$libresoc.v:154377$8353_Y - connect \$1 $not$libresoc.v:154378$8354_Y - connect \$3 $and$libresoc.v:154379$8355_Y - connect \$5 $or$libresoc.v:154380$8356_Y - connect \$7 $not$libresoc.v:154381$8357_Y + connect \$9 $and$libresoc.v:156266$8395_Y + connect \$11 $or$libresoc.v:156267$8396_Y + connect \$13 $not$libresoc.v:156268$8397_Y + connect \$15 $or$libresoc.v:156269$8398_Y + connect \$1 $not$libresoc.v:156270$8399_Y + connect \$3 $and$libresoc.v:156271$8400_Y + connect \$5 $or$libresoc.v:156272$8401_Y + connect \$7 $not$libresoc.v:156273$8402_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:154400.1-154854.10" +attribute \src "libresoc.v:156292.1-156750.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:154773.3-154784.6" + attribute \src "libresoc.v:156669.3-156680.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:154401.7-154401.20" + attribute \src "libresoc.v:156293.7-156293.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154785.3-154796.6" - wire width 65 $0\o$28[64:0]$8382 - attribute \src "libresoc.v:154761.3-154772.6" + attribute \src "libresoc.v:156681.3-156692.6" + wire width 65 $0\o$28[64:0]$8427 + attribute \src "libresoc.v:156657.3-156668.6" wire $0\so[0:0] - attribute \src "libresoc.v:154817.3-154826.6" - wire width 2 $0\xer_ov$24[1:0]$8389 - attribute \src "libresoc.v:154827.3-154836.6" + attribute \src "libresoc.v:156713.3-156722.6" + wire width 2 $0\xer_ov$24[1:0]$8434 + attribute \src "libresoc.v:156723.3-156732.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:154797.3-154806.6" - wire $0\xer_so$25[0:0]$8385 - attribute \src "libresoc.v:154807.3-154816.6" + attribute \src "libresoc.v:156693.3-156702.6" + wire $0\xer_so$25[0:0]$8430 + attribute \src "libresoc.v:156703.3-156712.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:154773.3-154784.6" + attribute \src "libresoc.v:156669.3-156680.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:154785.3-154796.6" - wire width 65 $1\o$28[64:0]$8383 - attribute \src "libresoc.v:154761.3-154772.6" + attribute \src "libresoc.v:156681.3-156692.6" + wire width 65 $1\o$28[64:0]$8428 + attribute \src "libresoc.v:156657.3-156668.6" wire $1\so[0:0] - attribute \src "libresoc.v:154817.3-154826.6" - wire width 2 $1\xer_ov$24[1:0]$8390 - attribute \src "libresoc.v:154827.3-154836.6" + attribute \src "libresoc.v:156713.3-156722.6" + wire width 2 $1\xer_ov$24[1:0]$8435 + attribute \src "libresoc.v:156723.3-156732.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:154797.3-154806.6" - wire $1\xer_so$25[0:0]$8386 - attribute \src "libresoc.v:154807.3-154816.6" + attribute \src "libresoc.v:156693.3-156702.6" + wire $1\xer_so$25[0:0]$8431 + attribute \src "libresoc.v:156703.3-156712.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:154748.18-154748.128" - wire $and$libresoc.v:154748$8364_Y - attribute \src "libresoc.v:154756.18-154756.112" - wire $and$libresoc.v:154756$8374_Y - attribute \src "libresoc.v:154759.18-154759.125" - wire $and$libresoc.v:154759$8377_Y - attribute \src "libresoc.v:154752.18-154752.123" - wire $eq$libresoc.v:154752$8370_Y - attribute \src "libresoc.v:154753.18-154753.123" - wire $eq$libresoc.v:154753$8371_Y - attribute \src "libresoc.v:154750.18-154750.103" - wire width 65 $extend$libresoc.v:154750$8366_Y - attribute \src "libresoc.v:154751.18-154751.101" - wire width 65 $extend$libresoc.v:154751$8368_Y - attribute \src "libresoc.v:154749.18-154749.100" - wire width 64 $not$libresoc.v:154749$8365_Y - attribute \src "libresoc.v:154755.18-154755.107" - wire $not$libresoc.v:154755$8373_Y - attribute \src "libresoc.v:154758.18-154758.107" - wire $not$libresoc.v:154758$8376_Y - attribute \src "libresoc.v:154757.18-154757.115" - wire $or$libresoc.v:154757$8375_Y - attribute \src "libresoc.v:154760.18-154760.112" - wire $or$libresoc.v:154760$8378_Y - attribute \src "libresoc.v:154750.18-154750.103" - wire width 65 $pos$libresoc.v:154750$8367_Y - attribute \src "libresoc.v:154751.18-154751.101" - wire width 65 $pos$libresoc.v:154751$8369_Y - attribute \src "libresoc.v:154754.18-154754.105" - wire $reduce_or$libresoc.v:154754$8372_Y + attribute \src "libresoc.v:156644.18-156644.128" + wire $and$libresoc.v:156644$8409_Y + attribute \src "libresoc.v:156652.18-156652.112" + wire $and$libresoc.v:156652$8419_Y + attribute \src "libresoc.v:156655.18-156655.125" + wire $and$libresoc.v:156655$8422_Y + attribute \src "libresoc.v:156648.18-156648.123" + wire $eq$libresoc.v:156648$8415_Y + attribute \src "libresoc.v:156649.18-156649.123" + wire $eq$libresoc.v:156649$8416_Y + attribute \src "libresoc.v:156646.18-156646.103" + wire width 65 $extend$libresoc.v:156646$8411_Y + attribute \src "libresoc.v:156647.18-156647.101" + wire width 65 $extend$libresoc.v:156647$8413_Y + attribute \src "libresoc.v:156645.18-156645.100" + wire width 64 $not$libresoc.v:156645$8410_Y + attribute \src "libresoc.v:156651.18-156651.107" + wire $not$libresoc.v:156651$8418_Y + attribute \src "libresoc.v:156654.18-156654.107" + wire $not$libresoc.v:156654$8421_Y + attribute \src "libresoc.v:156653.18-156653.115" + wire $or$libresoc.v:156653$8420_Y + attribute \src "libresoc.v:156656.18-156656.112" + wire $or$libresoc.v:156656$8423_Y + attribute \src "libresoc.v:156646.18-156646.103" + wire width 65 $pos$libresoc.v:156646$8412_Y + attribute \src "libresoc.v:156647.18-156647.101" + wire width 65 $pos$libresoc.v:156647$8414_Y + attribute \src "libresoc.v:156650.18-156650.105" + wire $reduce_or$libresoc.v:156650$8417_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -323983,37 +326570,39 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 42 \alu_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 27 \alu_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 27 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -324112,6 +326701,7 @@ module \output attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -324188,6 +326778,7 @@ module \output attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 26 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -324242,7 +326833,7 @@ module \output wire width 4 output 46 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \cr_a_ok - attribute \src "libresoc.v:154401.7-154401.15" + attribute \src "libresoc.v:156293.7-156293.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -324297,7 +326888,7 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:154748$8364 + cell $and $and$libresoc.v:156644$8409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324305,10 +326896,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:154748$8364_Y + connect \Y $and$libresoc.v:156644$8409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:154756$8374 + cell $and $and$libresoc.v:156652$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324316,10 +326907,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:154756$8374_Y + connect \Y $and$libresoc.v:156652$8419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:154759$8377 + cell $and $and$libresoc.v:156655$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324327,10 +326918,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:154759$8377_Y + connect \Y $and$libresoc.v:156655$8422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:154752$8370 + cell $eq $eq$libresoc.v:156648$8415 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -324338,10 +326929,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:154752$8370_Y + connect \Y $eq$libresoc.v:156648$8415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:154753$8371 + cell $eq $eq$libresoc.v:156649$8416 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -324349,50 +326940,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:154753$8371_Y + connect \Y $eq$libresoc.v:156649$8416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:154750$8366 + cell $pos $extend$libresoc.v:156646$8411 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:154750$8366_Y + connect \Y $extend$libresoc.v:156646$8411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:154751$8368 + cell $pos $extend$libresoc.v:156647$8413 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:154751$8368_Y + connect \Y $extend$libresoc.v:156647$8413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:154749$8365 + cell $not $not$libresoc.v:156645$8410 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:154749$8365_Y + connect \Y $not$libresoc.v:156645$8410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:154755$8373 + cell $not $not$libresoc.v:156651$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:154755$8373_Y + connect \Y $not$libresoc.v:156651$8418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:154758$8376 + cell $not $not$libresoc.v:156654$8421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:154758$8376_Y + connect \Y $not$libresoc.v:156654$8421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:154757$8375 + cell $or $or$libresoc.v:156653$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324400,10 +326991,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:154757$8375_Y + connect \Y $or$libresoc.v:156653$8420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:154760$8378 + cell $or $or$libresoc.v:156656$8423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324411,47 +327002,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:154760$8378_Y + connect \Y $or$libresoc.v:156656$8423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:154750$8367 + cell $pos $pos$libresoc.v:156646$8412 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:154750$8366_Y - connect \Y $pos$libresoc.v:154750$8367_Y + connect \A $extend$libresoc.v:156646$8411_Y + connect \Y $pos$libresoc.v:156646$8412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:154751$8369 + cell $pos $pos$libresoc.v:156647$8414 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:154751$8368_Y - connect \Y $pos$libresoc.v:154751$8369_Y + connect \A $extend$libresoc.v:156647$8413_Y + connect \Y $pos$libresoc.v:156647$8414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:154754$8372 + cell $reduce_or $reduce_or$libresoc.v:156650$8417 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:154754$8372_Y + connect \Y $reduce_or$libresoc.v:156650$8417_Y end - attribute \src "libresoc.v:154401.7-154401.20" - process $proc$libresoc.v:154401$8392 + attribute \src "libresoc.v:156293.7-156293.20" + process $proc$libresoc.v:156293$8437 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154761.3-154772.6" - process $proc$libresoc.v:154761$8379 + attribute \src "libresoc.v:156657.3-156668.6" + process $proc$libresoc.v:156657$8424 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:154762.5-154762.29" + attribute \src "libresoc.v:156658.5-156658.29" switch \initial - attribute \src "libresoc.v:154762.9-154762.17" + attribute \src "libresoc.v:156658.9-156658.17" case 1'1 case end @@ -324469,13 +327060,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:154773.3-154784.6" - process $proc$libresoc.v:154773$8380 + attribute \src "libresoc.v:156669.3-156680.6" + process $proc$libresoc.v:156669$8425 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:154774.5-154774.29" + attribute \src "libresoc.v:156670.5-156670.29" switch \initial - attribute \src "libresoc.v:154774.9-154774.17" + attribute \src "libresoc.v:156670.9-156670.17" case 1'1 case end @@ -324493,13 +327084,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:154785.3-154796.6" - process $proc$libresoc.v:154785$8381 + attribute \src "libresoc.v:156681.3-156692.6" + process $proc$libresoc.v:156681$8426 assign { } { } - assign $0\o$28[64:0]$8382 $1\o$28[64:0]$8383 - attribute \src "libresoc.v:154786.5-154786.29" + assign $0\o$28[64:0]$8427 $1\o$28[64:0]$8428 + attribute \src "libresoc.v:156682.5-156682.29" switch \initial - attribute \src "libresoc.v:154786.9-154786.17" + attribute \src "libresoc.v:156682.9-156682.17" case 1'1 case end @@ -324508,23 +327099,23 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$28[64:0]$8383 \$29 + assign $1\o$28[64:0]$8428 \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$28[64:0]$8383 \$33 + assign $1\o$28[64:0]$8428 \$33 end sync always - update \o$28 $0\o$28[64:0]$8382 + update \o$28 $0\o$28[64:0]$8427 end - attribute \src "libresoc.v:154797.3-154806.6" - process $proc$libresoc.v:154797$8384 + attribute \src "libresoc.v:156693.3-156702.6" + process $proc$libresoc.v:156693$8429 assign { } { } assign { } { } - assign $0\xer_so$25[0:0]$8385 $1\xer_so$25[0:0]$8386 - attribute \src "libresoc.v:154798.5-154798.29" + assign $0\xer_so$25[0:0]$8430 $1\xer_so$25[0:0]$8431 + attribute \src "libresoc.v:156694.5-156694.29" switch \initial - attribute \src "libresoc.v:154798.9-154798.17" + attribute \src "libresoc.v:156694.9-156694.17" case 1'1 case end @@ -324533,21 +327124,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$25[0:0]$8386 \$52 + assign $1\xer_so$25[0:0]$8431 \$52 case - assign $1\xer_so$25[0:0]$8386 1'0 + assign $1\xer_so$25[0:0]$8431 1'0 end sync always - update \xer_so$25 $0\xer_so$25[0:0]$8385 + update \xer_so$25 $0\xer_so$25[0:0]$8430 end - attribute \src "libresoc.v:154807.3-154816.6" - process $proc$libresoc.v:154807$8387 + attribute \src "libresoc.v:156703.3-156712.6" + process $proc$libresoc.v:156703$8432 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:154808.5-154808.29" + attribute \src "libresoc.v:156704.5-156704.29" switch \initial - attribute \src "libresoc.v:154808.9-154808.17" + attribute \src "libresoc.v:156704.9-156704.17" case 1'1 case end @@ -324563,14 +327154,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:154817.3-154826.6" - process $proc$libresoc.v:154817$8388 + attribute \src "libresoc.v:156713.3-156722.6" + process $proc$libresoc.v:156713$8433 assign { } { } assign { } { } - assign $0\xer_ov$24[1:0]$8389 $1\xer_ov$24[1:0]$8390 - attribute \src "libresoc.v:154818.5-154818.29" + assign $0\xer_ov$24[1:0]$8434 $1\xer_ov$24[1:0]$8435 + attribute \src "libresoc.v:156714.5-156714.29" switch \initial - attribute \src "libresoc.v:154818.9-154818.17" + attribute \src "libresoc.v:156714.9-156714.17" case 1'1 case end @@ -324579,21 +327170,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$24[1:0]$8390 \xer_ov + assign $1\xer_ov$24[1:0]$8435 \xer_ov case - assign $1\xer_ov$24[1:0]$8390 2'00 + assign $1\xer_ov$24[1:0]$8435 2'00 end sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$8389 + update \xer_ov$24 $0\xer_ov$24[1:0]$8434 end - attribute \src "libresoc.v:154827.3-154836.6" - process $proc$libresoc.v:154827$8391 + attribute \src "libresoc.v:156723.3-156732.6" + process $proc$libresoc.v:156723$8436 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:154828.5-154828.29" + attribute \src "libresoc.v:156724.5-156724.29" switch \initial - attribute \src "libresoc.v:154828.9-154828.17" + attribute \src "libresoc.v:156724.9-156724.17" case 1'1 case end @@ -324609,19 +327200,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:154748$8364_Y - connect \$30 $not$libresoc.v:154749$8365_Y - connect \$29 $pos$libresoc.v:154750$8367_Y - connect \$33 $pos$libresoc.v:154751$8369_Y - connect \$35 $eq$libresoc.v:154752$8370_Y - connect \$37 $eq$libresoc.v:154753$8371_Y - connect \$39 $reduce_or$libresoc.v:154754$8372_Y - connect \$41 $not$libresoc.v:154755$8373_Y - connect \$43 $and$libresoc.v:154756$8374_Y - connect \$45 $or$libresoc.v:154757$8375_Y - connect \$47 $not$libresoc.v:154758$8376_Y - connect \$50 $and$libresoc.v:154759$8377_Y - connect \$52 $or$libresoc.v:154760$8378_Y + connect \$26 $and$libresoc.v:156644$8409_Y + connect \$30 $not$libresoc.v:156645$8410_Y + connect \$29 $pos$libresoc.v:156646$8412_Y + connect \$33 $pos$libresoc.v:156647$8414_Y + connect \$35 $eq$libresoc.v:156648$8415_Y + connect \$37 $eq$libresoc.v:156649$8416_Y + connect \$39 $reduce_or$libresoc.v:156650$8417_Y + connect \$41 $not$libresoc.v:156651$8418_Y + connect \$43 $and$libresoc.v:156652$8419_Y + connect \$45 $or$libresoc.v:156653$8420_Y + connect \$47 $not$libresoc.v:156654$8421_Y + connect \$50 $and$libresoc.v:156655$8422_Y + connect \$52 $or$libresoc.v:156656$8423_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -324640,61 +327231,61 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:154858.1-155255.10" +attribute \src "libresoc.v:156754.1-157155.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 - attribute \src "libresoc.v:155187.3-155198.6" + attribute \src "libresoc.v:157087.3-157098.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:154859.7-154859.20" + attribute \src "libresoc.v:156755.7-156755.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155175.3-155186.6" + attribute \src "libresoc.v:157075.3-157086.6" wire $0\so[0:0] - attribute \src "libresoc.v:155219.3-155228.6" - wire width 2 $0\xer_ov$17[1:0]$8412 - attribute \src "libresoc.v:155229.3-155238.6" + attribute \src "libresoc.v:157119.3-157128.6" + wire width 2 $0\xer_ov$17[1:0]$8457 + attribute \src "libresoc.v:157129.3-157138.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:155199.3-155208.6" - wire $0\xer_so$18[0:0]$8408 - attribute \src "libresoc.v:155209.3-155218.6" + attribute \src "libresoc.v:157099.3-157108.6" + wire $0\xer_so$18[0:0]$8453 + attribute \src "libresoc.v:157109.3-157118.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:155187.3-155198.6" + attribute \src "libresoc.v:157087.3-157098.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:155175.3-155186.6" + attribute \src "libresoc.v:157075.3-157086.6" wire $1\so[0:0] - attribute \src "libresoc.v:155219.3-155228.6" - wire width 2 $1\xer_ov$17[1:0]$8413 - attribute \src "libresoc.v:155229.3-155238.6" + attribute \src "libresoc.v:157119.3-157128.6" + wire width 2 $1\xer_ov$17[1:0]$8458 + attribute \src "libresoc.v:157129.3-157138.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:155199.3-155208.6" - wire $1\xer_so$18[0:0]$8409 - attribute \src "libresoc.v:155209.3-155218.6" + attribute \src "libresoc.v:157099.3-157108.6" + wire $1\xer_so$18[0:0]$8454 + attribute \src "libresoc.v:157109.3-157118.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:155164.18-155164.128" - wire $and$libresoc.v:155164$8393_Y - attribute \src "libresoc.v:155170.18-155170.112" - wire $and$libresoc.v:155170$8400_Y - attribute \src "libresoc.v:155173.18-155173.125" - wire $and$libresoc.v:155173$8403_Y - attribute \src "libresoc.v:155166.18-155166.123" - wire $eq$libresoc.v:155166$8396_Y - attribute \src "libresoc.v:155167.18-155167.123" - wire $eq$libresoc.v:155167$8397_Y - attribute \src "libresoc.v:155165.18-155165.101" - wire width 65 $extend$libresoc.v:155165$8394_Y - attribute \src "libresoc.v:155169.18-155169.107" - wire $not$libresoc.v:155169$8399_Y - attribute \src "libresoc.v:155172.18-155172.107" - wire $not$libresoc.v:155172$8402_Y - attribute \src "libresoc.v:155171.18-155171.115" - wire $or$libresoc.v:155171$8401_Y - attribute \src "libresoc.v:155174.18-155174.112" - wire $or$libresoc.v:155174$8404_Y - attribute \src "libresoc.v:155165.18-155165.101" - wire width 65 $pos$libresoc.v:155165$8395_Y - attribute \src "libresoc.v:155168.18-155168.105" - wire $reduce_or$libresoc.v:155168$8398_Y + attribute \src "libresoc.v:157064.18-157064.128" + wire $and$libresoc.v:157064$8438_Y + attribute \src "libresoc.v:157070.18-157070.112" + wire $and$libresoc.v:157070$8445_Y + attribute \src "libresoc.v:157073.18-157073.125" + wire $and$libresoc.v:157073$8448_Y + attribute \src "libresoc.v:157066.18-157066.123" + wire $eq$libresoc.v:157066$8441_Y + attribute \src "libresoc.v:157067.18-157067.123" + wire $eq$libresoc.v:157067$8442_Y + attribute \src "libresoc.v:157065.18-157065.101" + wire width 65 $extend$libresoc.v:157065$8439_Y + attribute \src "libresoc.v:157069.18-157069.107" + wire $not$libresoc.v:157069$8444_Y + attribute \src "libresoc.v:157072.18-157072.107" + wire $not$libresoc.v:157072$8447_Y + attribute \src "libresoc.v:157071.18-157071.115" + wire $or$libresoc.v:157071$8446_Y + attribute \src "libresoc.v:157074.18-157074.112" + wire $or$libresoc.v:157074$8449_Y + attribute \src "libresoc.v:157065.18-157065.101" + wire width 65 $pos$libresoc.v:157065$8440_Y + attribute \src "libresoc.v:157068.18-157068.105" + wire $reduce_or$libresoc.v:157068$8443_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -324725,7 +327316,7 @@ module \output$100 wire width 4 output 33 \cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \cr_a_ok - attribute \src "libresoc.v:154859.7-154859.15" + attribute \src "libresoc.v:156755.7-156755.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -324740,37 +327331,39 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 20 \mul_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -324857,6 +327450,7 @@ module \output$100 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" @@ -324933,6 +327527,7 @@ module \output$100 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 19 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -324998,7 +327593,7 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:155164$8393 + cell $and $and$libresoc.v:157064$8438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325006,10 +327601,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:155164$8393_Y + connect \Y $and$libresoc.v:157064$8438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:155170$8400 + cell $and $and$libresoc.v:157070$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325017,10 +327612,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 - connect \Y $and$libresoc.v:155170$8400_Y + connect \Y $and$libresoc.v:157070$8445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:155173$8403 + cell $and $and$libresoc.v:157073$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325028,10 +327623,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:155173$8403_Y + connect \Y $and$libresoc.v:157073$8448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:155166$8396 + cell $eq $eq$libresoc.v:157066$8441 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -325039,10 +327634,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:155166$8396_Y + connect \Y $eq$libresoc.v:157066$8441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:155167$8397 + cell $eq $eq$libresoc.v:157067$8442 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -325050,34 +327645,34 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:155167$8397_Y + connect \Y $eq$libresoc.v:157067$8442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:155165$8394 + cell $pos $extend$libresoc.v:157065$8439 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:155165$8394_Y + connect \Y $extend$libresoc.v:157065$8439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:155169$8399 + cell $not $not$libresoc.v:157069$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:155169$8399_Y + connect \Y $not$libresoc.v:157069$8444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:155172$8402 + cell $not $not$libresoc.v:157072$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:155172$8402_Y + connect \Y $not$libresoc.v:157072$8447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:155171$8401 + cell $or $or$libresoc.v:157071$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325085,10 +327680,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:155171$8401_Y + connect \Y $or$libresoc.v:157071$8446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:155174$8404 + cell $or $or$libresoc.v:157074$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325096,39 +327691,39 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:155174$8404_Y + connect \Y $or$libresoc.v:157074$8449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:155165$8395 + cell $pos $pos$libresoc.v:157065$8440 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:155165$8394_Y - connect \Y $pos$libresoc.v:155165$8395_Y + connect \A $extend$libresoc.v:157065$8439_Y + connect \Y $pos$libresoc.v:157065$8440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:155168$8398 + cell $reduce_or $reduce_or$libresoc.v:157068$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:155168$8398_Y + connect \Y $reduce_or$libresoc.v:157068$8443_Y end - attribute \src "libresoc.v:154859.7-154859.20" - process $proc$libresoc.v:154859$8415 + attribute \src "libresoc.v:156755.7-156755.20" + process $proc$libresoc.v:156755$8460 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155175.3-155186.6" - process $proc$libresoc.v:155175$8405 + attribute \src "libresoc.v:157075.3-157086.6" + process $proc$libresoc.v:157075$8450 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:155176.5-155176.29" + attribute \src "libresoc.v:157076.5-157076.29" switch \initial - attribute \src "libresoc.v:155176.9-155176.17" + attribute \src "libresoc.v:157076.9-157076.17" case 1'1 case end @@ -325146,13 +327741,13 @@ module \output$100 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:155187.3-155198.6" - process $proc$libresoc.v:155187$8406 + attribute \src "libresoc.v:157087.3-157098.6" + process $proc$libresoc.v:157087$8451 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:155188.5-155188.29" + attribute \src "libresoc.v:157088.5-157088.29" switch \initial - attribute \src "libresoc.v:155188.9-155188.17" + attribute \src "libresoc.v:157088.9-157088.17" case 1'1 case end @@ -325170,14 +327765,14 @@ module \output$100 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:155199.3-155208.6" - process $proc$libresoc.v:155199$8407 + attribute \src "libresoc.v:157099.3-157108.6" + process $proc$libresoc.v:157099$8452 assign { } { } assign { } { } - assign $0\xer_so$18[0:0]$8408 $1\xer_so$18[0:0]$8409 - attribute \src "libresoc.v:155200.5-155200.29" + assign $0\xer_so$18[0:0]$8453 $1\xer_so$18[0:0]$8454 + attribute \src "libresoc.v:157100.5-157100.29" switch \initial - attribute \src "libresoc.v:155200.9-155200.17" + attribute \src "libresoc.v:157100.9-157100.17" case 1'1 case end @@ -325186,21 +327781,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$18[0:0]$8409 \$41 + assign $1\xer_so$18[0:0]$8454 \$41 case - assign $1\xer_so$18[0:0]$8409 1'0 + assign $1\xer_so$18[0:0]$8454 1'0 end sync always - update \xer_so$18 $0\xer_so$18[0:0]$8408 + update \xer_so$18 $0\xer_so$18[0:0]$8453 end - attribute \src "libresoc.v:155209.3-155218.6" - process $proc$libresoc.v:155209$8410 + attribute \src "libresoc.v:157109.3-157118.6" + process $proc$libresoc.v:157109$8455 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:155210.5-155210.29" + attribute \src "libresoc.v:157110.5-157110.29" switch \initial - attribute \src "libresoc.v:155210.9-155210.17" + attribute \src "libresoc.v:157110.9-157110.17" case 1'1 case end @@ -325216,14 +327811,14 @@ module \output$100 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:155219.3-155228.6" - process $proc$libresoc.v:155219$8411 + attribute \src "libresoc.v:157119.3-157128.6" + process $proc$libresoc.v:157119$8456 assign { } { } assign { } { } - assign $0\xer_ov$17[1:0]$8412 $1\xer_ov$17[1:0]$8413 - attribute \src "libresoc.v:155220.5-155220.29" + assign $0\xer_ov$17[1:0]$8457 $1\xer_ov$17[1:0]$8458 + attribute \src "libresoc.v:157120.5-157120.29" switch \initial - attribute \src "libresoc.v:155220.9-155220.17" + attribute \src "libresoc.v:157120.9-157120.17" case 1'1 case end @@ -325232,21 +327827,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$17[1:0]$8413 \xer_ov + assign $1\xer_ov$17[1:0]$8458 \xer_ov case - assign $1\xer_ov$17[1:0]$8413 2'00 + assign $1\xer_ov$17[1:0]$8458 2'00 end sync always - update \xer_ov$17 $0\xer_ov$17[1:0]$8412 + update \xer_ov$17 $0\xer_ov$17[1:0]$8457 end - attribute \src "libresoc.v:155229.3-155238.6" - process $proc$libresoc.v:155229$8414 + attribute \src "libresoc.v:157129.3-157138.6" + process $proc$libresoc.v:157129$8459 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:155230.5-155230.29" + attribute \src "libresoc.v:157130.5-157130.29" switch \initial - attribute \src "libresoc.v:155230.9-155230.17" + attribute \src "libresoc.v:157130.9-157130.17" case 1'1 case end @@ -325262,17 +327857,17 @@ module \output$100 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$19 $and$libresoc.v:155164$8393_Y - connect \$22 $pos$libresoc.v:155165$8395_Y - connect \$24 $eq$libresoc.v:155166$8396_Y - connect \$26 $eq$libresoc.v:155167$8397_Y - connect \$28 $reduce_or$libresoc.v:155168$8398_Y - connect \$30 $not$libresoc.v:155169$8399_Y - connect \$32 $and$libresoc.v:155170$8400_Y - connect \$34 $or$libresoc.v:155171$8401_Y - connect \$36 $not$libresoc.v:155172$8402_Y - connect \$39 $and$libresoc.v:155173$8403_Y - connect \$41 $or$libresoc.v:155174$8404_Y + connect \$19 $and$libresoc.v:157064$8438_Y + connect \$22 $pos$libresoc.v:157065$8440_Y + connect \$24 $eq$libresoc.v:157066$8441_Y + connect \$26 $eq$libresoc.v:157067$8442_Y + connect \$28 $reduce_or$libresoc.v:157068$8443_Y + connect \$30 $not$libresoc.v:157069$8444_Y + connect \$32 $and$libresoc.v:157070$8445_Y + connect \$34 $or$libresoc.v:157071$8446_Y + connect \$36 $not$libresoc.v:157072$8447_Y + connect \$39 $and$libresoc.v:157073$8448_Y + connect \$41 $or$libresoc.v:157074$8449_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -325290,35 +327885,35 @@ module \output$100 connect \o$21 \$22 connect \oe \$19 end -attribute \src "libresoc.v:155259.1-155609.10" +attribute \src "libresoc.v:157159.1-157513.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 - attribute \src "libresoc.v:155581.3-155592.6" + attribute \src "libresoc.v:157485.3-157496.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:155260.7-155260.20" + attribute \src "libresoc.v:157160.7-157160.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155581.3-155592.6" + attribute \src "libresoc.v:157485.3-157496.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:155578.18-155578.112" - wire $and$libresoc.v:155578$8422_Y - attribute \src "libresoc.v:155574.18-155574.122" - wire $eq$libresoc.v:155574$8418_Y - attribute \src "libresoc.v:155575.18-155575.122" - wire $eq$libresoc.v:155575$8419_Y - attribute \src "libresoc.v:155573.18-155573.101" - wire width 65 $extend$libresoc.v:155573$8416_Y - attribute \src "libresoc.v:155577.18-155577.107" - wire $not$libresoc.v:155577$8421_Y - attribute \src "libresoc.v:155580.18-155580.107" - wire $not$libresoc.v:155580$8424_Y - attribute \src "libresoc.v:155579.18-155579.115" - wire $or$libresoc.v:155579$8423_Y - attribute \src "libresoc.v:155573.18-155573.101" - wire width 65 $pos$libresoc.v:155573$8417_Y - attribute \src "libresoc.v:155576.18-155576.105" - wire $reduce_or$libresoc.v:155576$8420_Y + attribute \src "libresoc.v:157482.18-157482.112" + wire $and$libresoc.v:157482$8467_Y + attribute \src "libresoc.v:157478.18-157478.122" + wire $eq$libresoc.v:157478$8463_Y + attribute \src "libresoc.v:157479.18-157479.122" + wire $eq$libresoc.v:157479$8464_Y + attribute \src "libresoc.v:157477.18-157477.101" + wire width 65 $extend$libresoc.v:157477$8461_Y + attribute \src "libresoc.v:157481.18-157481.107" + wire $not$libresoc.v:157481$8466_Y + attribute \src "libresoc.v:157484.18-157484.107" + wire $not$libresoc.v:157484$8469_Y + attribute \src "libresoc.v:157483.18-157483.115" + wire $or$libresoc.v:157483$8468_Y + attribute \src "libresoc.v:157477.18-157477.101" + wire width 65 $pos$libresoc.v:157477$8462_Y + attribute \src "libresoc.v:157480.18-157480.105" + wire $reduce_or$libresoc.v:157480$8465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" @@ -325343,7 +327938,7 @@ module \output$118 wire width 4 output 43 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \cr_a_ok - attribute \src "libresoc.v:155260.7-155260.15" + attribute \src "libresoc.v:157160.7-157160.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -325372,37 +327967,39 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \o_ok$20 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \sr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -325505,6 +328102,7 @@ module \output$118 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -325581,6 +328179,7 @@ module \output$118 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -325634,7 +328233,7 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:155578$8422 + cell $and $and$libresoc.v:157482$8467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325642,10 +328241,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 - connect \Y $and$libresoc.v:155578$8422_Y + connect \Y $and$libresoc.v:157482$8467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:155574$8418 + cell $eq $eq$libresoc.v:157478$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -325653,10 +328252,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:155574$8418_Y + connect \Y $eq$libresoc.v:157478$8463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:155575$8419 + cell $eq $eq$libresoc.v:157479$8464 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -325664,34 +328263,34 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:155575$8419_Y + connect \Y $eq$libresoc.v:157479$8464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:155573$8416 + cell $pos $extend$libresoc.v:157477$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:155573$8416_Y + connect \Y $extend$libresoc.v:157477$8461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:155577$8421 + cell $not $not$libresoc.v:157481$8466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:155577$8421_Y + connect \Y $not$libresoc.v:157481$8466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:155580$8424 + cell $not $not$libresoc.v:157484$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:155580$8424_Y + connect \Y $not$libresoc.v:157484$8469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:155579$8423 + cell $or $or$libresoc.v:157483$8468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325699,39 +328298,39 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:155579$8423_Y + connect \Y $or$libresoc.v:157483$8468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:155573$8417 + cell $pos $pos$libresoc.v:157477$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:155573$8416_Y - connect \Y $pos$libresoc.v:155573$8417_Y + connect \A $extend$libresoc.v:157477$8461_Y + connect \Y $pos$libresoc.v:157477$8462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:155576$8420 + cell $reduce_or $reduce_or$libresoc.v:157480$8465 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:155576$8420_Y + connect \Y $reduce_or$libresoc.v:157480$8465_Y end - attribute \src "libresoc.v:155260.7-155260.20" - process $proc$libresoc.v:155260$8426 + attribute \src "libresoc.v:157160.7-157160.20" + process $proc$libresoc.v:157160$8471 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155581.3-155592.6" - process $proc$libresoc.v:155581$8425 + attribute \src "libresoc.v:157485.3-157496.6" + process $proc$libresoc.v:157485$8470 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:155582.5-155582.29" + attribute \src "libresoc.v:157486.5-157486.29" switch \initial - attribute \src "libresoc.v:155582.9-155582.17" + attribute \src "libresoc.v:157486.9-157486.17" case 1'1 case end @@ -325749,14 +328348,14 @@ module \output$118 sync always update \cr0 $0\cr0[3:0] end - connect \$24 $pos$libresoc.v:155573$8417_Y - connect \$26 $eq$libresoc.v:155574$8418_Y - connect \$28 $eq$libresoc.v:155575$8419_Y - connect \$30 $reduce_or$libresoc.v:155576$8420_Y - connect \$32 $not$libresoc.v:155577$8421_Y - connect \$34 $and$libresoc.v:155578$8422_Y - connect \$36 $or$libresoc.v:155579$8423_Y - connect \$38 $not$libresoc.v:155580$8424_Y + connect \$24 $pos$libresoc.v:157477$8462_Y + connect \$26 $eq$libresoc.v:157478$8463_Y + connect \$28 $eq$libresoc.v:157479$8464_Y + connect \$30 $reduce_or$libresoc.v:157480$8465_Y + connect \$32 $not$libresoc.v:157481$8466_Y + connect \$34 $and$libresoc.v:157482$8467_Y + connect \$36 $or$libresoc.v:157483$8468_Y + connect \$38 $not$libresoc.v:157484$8469_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 @@ -325774,45 +328373,45 @@ module \output$118 connect \target \o$23 [63:0] connect \o$23 \$24 end -attribute \src "libresoc.v:155613.1-155976.10" +attribute \src "libresoc.v:157517.1-157884.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 - attribute \src "libresoc.v:155951.3-155962.6" + attribute \src "libresoc.v:157859.3-157870.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:155614.7-155614.20" + attribute \src "libresoc.v:157518.7-157518.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155939.3-155950.6" - wire width 65 $0\o$23[64:0]$8440 - attribute \src "libresoc.v:155951.3-155962.6" + attribute \src "libresoc.v:157847.3-157858.6" + wire width 65 $0\o$23[64:0]$8485 + attribute \src "libresoc.v:157859.3-157870.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:155939.3-155950.6" - wire width 65 $1\o$23[64:0]$8441 - attribute \src "libresoc.v:155936.18-155936.112" - wire $and$libresoc.v:155936$8436_Y - attribute \src "libresoc.v:155932.18-155932.127" - wire $eq$libresoc.v:155932$8432_Y - attribute \src "libresoc.v:155933.18-155933.127" - wire $eq$libresoc.v:155933$8433_Y - attribute \src "libresoc.v:155930.18-155930.103" - wire width 65 $extend$libresoc.v:155930$8428_Y - attribute \src "libresoc.v:155931.18-155931.101" - wire width 65 $extend$libresoc.v:155931$8430_Y - attribute \src "libresoc.v:155929.18-155929.100" - wire width 64 $not$libresoc.v:155929$8427_Y - attribute \src "libresoc.v:155935.18-155935.107" - wire $not$libresoc.v:155935$8435_Y - attribute \src "libresoc.v:155938.18-155938.107" - wire $not$libresoc.v:155938$8438_Y - attribute \src "libresoc.v:155937.18-155937.115" - wire $or$libresoc.v:155937$8437_Y - attribute \src "libresoc.v:155930.18-155930.103" - wire width 65 $pos$libresoc.v:155930$8429_Y - attribute \src "libresoc.v:155931.18-155931.101" - wire width 65 $pos$libresoc.v:155931$8431_Y - attribute \src "libresoc.v:155934.18-155934.105" - wire $reduce_or$libresoc.v:155934$8434_Y + attribute \src "libresoc.v:157847.3-157858.6" + wire width 65 $1\o$23[64:0]$8486 + attribute \src "libresoc.v:157844.18-157844.112" + wire $and$libresoc.v:157844$8481_Y + attribute \src "libresoc.v:157840.18-157840.127" + wire $eq$libresoc.v:157840$8477_Y + attribute \src "libresoc.v:157841.18-157841.127" + wire $eq$libresoc.v:157841$8478_Y + attribute \src "libresoc.v:157838.18-157838.103" + wire width 65 $extend$libresoc.v:157838$8473_Y + attribute \src "libresoc.v:157839.18-157839.101" + wire width 65 $extend$libresoc.v:157839$8475_Y + attribute \src "libresoc.v:157837.18-157837.100" + wire width 64 $not$libresoc.v:157837$8472_Y + attribute \src "libresoc.v:157843.18-157843.107" + wire $not$libresoc.v:157843$8480_Y + attribute \src "libresoc.v:157846.18-157846.107" + wire $not$libresoc.v:157846$8483_Y + attribute \src "libresoc.v:157845.18-157845.115" + wire $or$libresoc.v:157845$8482_Y + attribute \src "libresoc.v:157838.18-157838.103" + wire width 65 $pos$libresoc.v:157838$8474_Y + attribute \src "libresoc.v:157839.18-157839.101" + wire width 65 $pos$libresoc.v:157839$8476_Y + attribute \src "libresoc.v:157842.18-157842.105" + wire $reduce_or$libresoc.v:157842$8479_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -325841,7 +328440,7 @@ module \output$54 wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \cr_a_ok - attribute \src "libresoc.v:155614.7-155614.15" + attribute \src "libresoc.v:157518.7-157518.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -325858,37 +328457,39 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 25 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -325987,6 +328588,7 @@ module \output$54 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -326063,6 +328665,7 @@ module \output$54 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -326130,7 +328733,7 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:155936$8436 + cell $and $and$libresoc.v:157844$8481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326138,10 +328741,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:155936$8436_Y + connect \Y $and$libresoc.v:157844$8481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:155932$8432 + cell $eq $eq$libresoc.v:157840$8477 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326149,10 +328752,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:155932$8432_Y + connect \Y $eq$libresoc.v:157840$8477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:155933$8433 + cell $eq $eq$libresoc.v:157841$8478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326160,50 +328763,50 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:155933$8433_Y + connect \Y $eq$libresoc.v:157841$8478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:155930$8428 + cell $pos $extend$libresoc.v:157838$8473 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:155930$8428_Y + connect \Y $extend$libresoc.v:157838$8473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:155931$8430 + cell $pos $extend$libresoc.v:157839$8475 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:155931$8430_Y + connect \Y $extend$libresoc.v:157839$8475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:155929$8427 + cell $not $not$libresoc.v:157837$8472 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:155929$8427_Y + connect \Y $not$libresoc.v:157837$8472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:155935$8435 + cell $not $not$libresoc.v:157843$8480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:155935$8435_Y + connect \Y $not$libresoc.v:157843$8480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:155938$8438 + cell $not $not$libresoc.v:157846$8483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:155938$8438_Y + connect \Y $not$libresoc.v:157846$8483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:155937$8437 + cell $or $or$libresoc.v:157845$8482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326211,47 +328814,47 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:155937$8437_Y + connect \Y $or$libresoc.v:157845$8482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:155930$8429 + cell $pos $pos$libresoc.v:157838$8474 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:155930$8428_Y - connect \Y $pos$libresoc.v:155930$8429_Y + connect \A $extend$libresoc.v:157838$8473_Y + connect \Y $pos$libresoc.v:157838$8474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:155931$8431 + cell $pos $pos$libresoc.v:157839$8476 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:155931$8430_Y - connect \Y $pos$libresoc.v:155931$8431_Y + connect \A $extend$libresoc.v:157839$8475_Y + connect \Y $pos$libresoc.v:157839$8476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:155934$8434 + cell $reduce_or $reduce_or$libresoc.v:157842$8479 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:155934$8434_Y + connect \Y $reduce_or$libresoc.v:157842$8479_Y end - attribute \src "libresoc.v:155614.7-155614.20" - process $proc$libresoc.v:155614$8443 + attribute \src "libresoc.v:157518.7-157518.20" + process $proc$libresoc.v:157518$8488 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155939.3-155950.6" - process $proc$libresoc.v:155939$8439 + attribute \src "libresoc.v:157847.3-157858.6" + process $proc$libresoc.v:157847$8484 assign { } { } - assign $0\o$23[64:0]$8440 $1\o$23[64:0]$8441 - attribute \src "libresoc.v:155940.5-155940.29" + assign $0\o$23[64:0]$8485 $1\o$23[64:0]$8486 + attribute \src "libresoc.v:157848.5-157848.29" switch \initial - attribute \src "libresoc.v:155940.9-155940.17" + attribute \src "libresoc.v:157848.9-157848.17" case 1'1 case end @@ -326260,22 +328863,22 @@ module \output$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$23[64:0]$8441 \$24 + assign $1\o$23[64:0]$8486 \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$23[64:0]$8441 \$28 + assign $1\o$23[64:0]$8486 \$28 end sync always - update \o$23 $0\o$23[64:0]$8440 + update \o$23 $0\o$23[64:0]$8485 end - attribute \src "libresoc.v:155951.3-155962.6" - process $proc$libresoc.v:155951$8442 + attribute \src "libresoc.v:157859.3-157870.6" + process $proc$libresoc.v:157859$8487 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:155952.5-155952.29" + attribute \src "libresoc.v:157860.5-157860.29" switch \initial - attribute \src "libresoc.v:155952.9-155952.17" + attribute \src "libresoc.v:157860.9-157860.17" case 1'1 case end @@ -326293,16 +328896,16 @@ module \output$54 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:155929$8427_Y - connect \$24 $pos$libresoc.v:155930$8429_Y - connect \$28 $pos$libresoc.v:155931$8431_Y - connect \$30 $eq$libresoc.v:155932$8432_Y - connect \$32 $eq$libresoc.v:155933$8433_Y - connect \$34 $reduce_or$libresoc.v:155934$8434_Y - connect \$36 $not$libresoc.v:155935$8435_Y - connect \$38 $and$libresoc.v:155936$8436_Y - connect \$40 $or$libresoc.v:155937$8437_Y - connect \$42 $not$libresoc.v:155938$8438_Y + connect \$25 $not$libresoc.v:157837$8472_Y + connect \$24 $pos$libresoc.v:157838$8474_Y + connect \$28 $pos$libresoc.v:157839$8476_Y + connect \$30 $eq$libresoc.v:157840$8477_Y + connect \$32 $eq$libresoc.v:157841$8478_Y + connect \$34 $reduce_or$libresoc.v:157842$8479_Y + connect \$36 $not$libresoc.v:157843$8480_Y + connect \$38 $and$libresoc.v:157844$8481_Y + connect \$40 $or$libresoc.v:157845$8482_Y + connect \$42 $not$libresoc.v:157846$8483_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -326317,71 +328920,71 @@ module \output$54 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:155980.1-156426.10" +attribute \src "libresoc.v:157888.1-158338.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 - attribute \src "libresoc.v:156347.3-156358.6" + attribute \src "libresoc.v:158259.3-158270.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:155981.7-155981.20" + attribute \src "libresoc.v:157889.7-157889.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156359.3-156370.6" - wire width 65 $0\o$27[64:0]$8462 - attribute \src "libresoc.v:156335.3-156346.6" + attribute \src "libresoc.v:158271.3-158282.6" + wire width 65 $0\o$27[64:0]$8507 + attribute \src "libresoc.v:158247.3-158258.6" wire $0\so[0:0] - attribute \src "libresoc.v:156391.3-156400.6" - wire width 2 $0\xer_ov$23[1:0]$8469 - attribute \src "libresoc.v:156401.3-156410.6" + attribute \src "libresoc.v:158303.3-158312.6" + wire width 2 $0\xer_ov$23[1:0]$8514 + attribute \src "libresoc.v:158313.3-158322.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:156371.3-156380.6" - wire $0\xer_so$24[0:0]$8465 - attribute \src "libresoc.v:156381.3-156390.6" + attribute \src "libresoc.v:158283.3-158292.6" + wire $0\xer_so$24[0:0]$8510 + attribute \src "libresoc.v:158293.3-158302.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:156347.3-156358.6" + attribute \src "libresoc.v:158259.3-158270.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:156359.3-156370.6" - wire width 65 $1\o$27[64:0]$8463 - attribute \src "libresoc.v:156335.3-156346.6" + attribute \src "libresoc.v:158271.3-158282.6" + wire width 65 $1\o$27[64:0]$8508 + attribute \src "libresoc.v:158247.3-158258.6" wire $1\so[0:0] - attribute \src "libresoc.v:156391.3-156400.6" - wire width 2 $1\xer_ov$23[1:0]$8470 - attribute \src "libresoc.v:156401.3-156410.6" + attribute \src "libresoc.v:158303.3-158312.6" + wire width 2 $1\xer_ov$23[1:0]$8515 + attribute \src "libresoc.v:158313.3-158322.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156371.3-156380.6" - wire $1\xer_so$24[0:0]$8466 - attribute \src "libresoc.v:156381.3-156390.6" + attribute \src "libresoc.v:158283.3-158292.6" + wire $1\xer_so$24[0:0]$8511 + attribute \src "libresoc.v:158293.3-158302.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156322.18-156322.136" - wire $and$libresoc.v:156322$8444_Y - attribute \src "libresoc.v:156330.18-156330.112" - wire $and$libresoc.v:156330$8454_Y - attribute \src "libresoc.v:156333.18-156333.133" - wire $and$libresoc.v:156333$8457_Y - attribute \src "libresoc.v:156326.18-156326.127" - wire $eq$libresoc.v:156326$8450_Y - attribute \src "libresoc.v:156327.18-156327.127" - wire $eq$libresoc.v:156327$8451_Y - attribute \src "libresoc.v:156324.18-156324.103" - wire width 65 $extend$libresoc.v:156324$8446_Y - attribute \src "libresoc.v:156325.18-156325.101" - wire width 65 $extend$libresoc.v:156325$8448_Y - attribute \src "libresoc.v:156323.18-156323.100" - wire width 64 $not$libresoc.v:156323$8445_Y - attribute \src "libresoc.v:156329.18-156329.107" - wire $not$libresoc.v:156329$8453_Y - attribute \src "libresoc.v:156332.18-156332.107" - wire $not$libresoc.v:156332$8456_Y - attribute \src "libresoc.v:156331.18-156331.115" - wire $or$libresoc.v:156331$8455_Y - attribute \src "libresoc.v:156334.18-156334.112" - wire $or$libresoc.v:156334$8458_Y - attribute \src "libresoc.v:156324.18-156324.103" - wire width 65 $pos$libresoc.v:156324$8447_Y - attribute \src "libresoc.v:156325.18-156325.101" - wire width 65 $pos$libresoc.v:156325$8449_Y - attribute \src "libresoc.v:156328.18-156328.105" - wire $reduce_or$libresoc.v:156328$8452_Y + attribute \src "libresoc.v:158234.18-158234.136" + wire $and$libresoc.v:158234$8489_Y + attribute \src "libresoc.v:158242.18-158242.112" + wire $and$libresoc.v:158242$8499_Y + attribute \src "libresoc.v:158245.18-158245.133" + wire $and$libresoc.v:158245$8502_Y + attribute \src "libresoc.v:158238.18-158238.127" + wire $eq$libresoc.v:158238$8495_Y + attribute \src "libresoc.v:158239.18-158239.127" + wire $eq$libresoc.v:158239$8496_Y + attribute \src "libresoc.v:158236.18-158236.103" + wire width 65 $extend$libresoc.v:158236$8491_Y + attribute \src "libresoc.v:158237.18-158237.101" + wire width 65 $extend$libresoc.v:158237$8493_Y + attribute \src "libresoc.v:158235.18-158235.100" + wire width 64 $not$libresoc.v:158235$8490_Y + attribute \src "libresoc.v:158241.18-158241.107" + wire $not$libresoc.v:158241$8498_Y + attribute \src "libresoc.v:158244.18-158244.107" + wire $not$libresoc.v:158244$8501_Y + attribute \src "libresoc.v:158243.18-158243.115" + wire $or$libresoc.v:158243$8500_Y + attribute \src "libresoc.v:158246.18-158246.112" + wire $or$libresoc.v:158246$8503_Y + attribute \src "libresoc.v:158236.18-158236.103" + wire width 65 $pos$libresoc.v:158236$8492_Y + attribute \src "libresoc.v:158237.18-158237.101" + wire width 65 $pos$libresoc.v:158237$8494_Y + attribute \src "libresoc.v:158240.18-158240.105" + wire $reduce_or$libresoc.v:158240$8497_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -326416,7 +329019,7 @@ module \output$83 wire width 4 output 45 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \cr_a_ok - attribute \src "libresoc.v:155981.7-155981.15" + attribute \src "libresoc.v:157889.7-157889.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -326433,37 +329036,39 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 41 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 26 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 26 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -326562,6 +329167,7 @@ module \output$83 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -326638,6 +329244,7 @@ module \output$83 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 25 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -326721,7 +329328,7 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:156322$8444 + cell $and $and$libresoc.v:158234$8489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326729,10 +329336,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:156322$8444_Y + connect \Y $and$libresoc.v:158234$8489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:156330$8454 + cell $and $and$libresoc.v:158242$8499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326740,10 +329347,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:156330$8454_Y + connect \Y $and$libresoc.v:158242$8499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:156333$8457 + cell $and $and$libresoc.v:158245$8502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326751,10 +329358,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:156333$8457_Y + connect \Y $and$libresoc.v:158245$8502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:156326$8450 + cell $eq $eq$libresoc.v:158238$8495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326762,10 +329369,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:156326$8450_Y + connect \Y $eq$libresoc.v:158238$8495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:156327$8451 + cell $eq $eq$libresoc.v:158239$8496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326773,50 +329380,50 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:156327$8451_Y + connect \Y $eq$libresoc.v:158239$8496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:156324$8446 + cell $pos $extend$libresoc.v:158236$8491 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:156324$8446_Y + connect \Y $extend$libresoc.v:158236$8491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:156325$8448 + cell $pos $extend$libresoc.v:158237$8493 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:156325$8448_Y + connect \Y $extend$libresoc.v:158237$8493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:156323$8445 + cell $not $not$libresoc.v:158235$8490 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:156323$8445_Y + connect \Y $not$libresoc.v:158235$8490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:156329$8453 + cell $not $not$libresoc.v:158241$8498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:156329$8453_Y + connect \Y $not$libresoc.v:158241$8498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:156332$8456 + cell $not $not$libresoc.v:158244$8501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:156332$8456_Y + connect \Y $not$libresoc.v:158244$8501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:156331$8455 + cell $or $or$libresoc.v:158243$8500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326824,10 +329431,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:156331$8455_Y + connect \Y $or$libresoc.v:158243$8500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:156334$8458 + cell $or $or$libresoc.v:158246$8503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326835,47 +329442,47 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:156334$8458_Y + connect \Y $or$libresoc.v:158246$8503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:156324$8447 + cell $pos $pos$libresoc.v:158236$8492 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156324$8446_Y - connect \Y $pos$libresoc.v:156324$8447_Y + connect \A $extend$libresoc.v:158236$8491_Y + connect \Y $pos$libresoc.v:158236$8492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:156325$8449 + cell $pos $pos$libresoc.v:158237$8494 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156325$8448_Y - connect \Y $pos$libresoc.v:156325$8449_Y + connect \A $extend$libresoc.v:158237$8493_Y + connect \Y $pos$libresoc.v:158237$8494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:156328$8452 + cell $reduce_or $reduce_or$libresoc.v:158240$8497 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:156328$8452_Y + connect \Y $reduce_or$libresoc.v:158240$8497_Y end - attribute \src "libresoc.v:155981.7-155981.20" - process $proc$libresoc.v:155981$8472 + attribute \src "libresoc.v:157889.7-157889.20" + process $proc$libresoc.v:157889$8517 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156335.3-156346.6" - process $proc$libresoc.v:156335$8459 + attribute \src "libresoc.v:158247.3-158258.6" + process $proc$libresoc.v:158247$8504 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:156336.5-156336.29" + attribute \src "libresoc.v:158248.5-158248.29" switch \initial - attribute \src "libresoc.v:156336.9-156336.17" + attribute \src "libresoc.v:158248.9-158248.17" case 1'1 case end @@ -326893,13 +329500,13 @@ module \output$83 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:156347.3-156358.6" - process $proc$libresoc.v:156347$8460 + attribute \src "libresoc.v:158259.3-158270.6" + process $proc$libresoc.v:158259$8505 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:156348.5-156348.29" + attribute \src "libresoc.v:158260.5-158260.29" switch \initial - attribute \src "libresoc.v:156348.9-156348.17" + attribute \src "libresoc.v:158260.9-158260.17" case 1'1 case end @@ -326917,13 +329524,13 @@ module \output$83 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:156359.3-156370.6" - process $proc$libresoc.v:156359$8461 + attribute \src "libresoc.v:158271.3-158282.6" + process $proc$libresoc.v:158271$8506 assign { } { } - assign $0\o$27[64:0]$8462 $1\o$27[64:0]$8463 - attribute \src "libresoc.v:156360.5-156360.29" + assign $0\o$27[64:0]$8507 $1\o$27[64:0]$8508 + attribute \src "libresoc.v:158272.5-158272.29" switch \initial - attribute \src "libresoc.v:156360.9-156360.17" + attribute \src "libresoc.v:158272.9-158272.17" case 1'1 case end @@ -326932,23 +329539,23 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$27[64:0]$8463 \$28 + assign $1\o$27[64:0]$8508 \$28 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$27[64:0]$8463 \$32 + assign $1\o$27[64:0]$8508 \$32 end sync always - update \o$27 $0\o$27[64:0]$8462 + update \o$27 $0\o$27[64:0]$8507 end - attribute \src "libresoc.v:156371.3-156380.6" - process $proc$libresoc.v:156371$8464 + attribute \src "libresoc.v:158283.3-158292.6" + process $proc$libresoc.v:158283$8509 assign { } { } assign { } { } - assign $0\xer_so$24[0:0]$8465 $1\xer_so$24[0:0]$8466 - attribute \src "libresoc.v:156372.5-156372.29" + assign $0\xer_so$24[0:0]$8510 $1\xer_so$24[0:0]$8511 + attribute \src "libresoc.v:158284.5-158284.29" switch \initial - attribute \src "libresoc.v:156372.9-156372.17" + attribute \src "libresoc.v:158284.9-158284.17" case 1'1 case end @@ -326957,21 +329564,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$24[0:0]$8466 \$51 + assign $1\xer_so$24[0:0]$8511 \$51 case - assign $1\xer_so$24[0:0]$8466 1'0 + assign $1\xer_so$24[0:0]$8511 1'0 end sync always - update \xer_so$24 $0\xer_so$24[0:0]$8465 + update \xer_so$24 $0\xer_so$24[0:0]$8510 end - attribute \src "libresoc.v:156381.3-156390.6" - process $proc$libresoc.v:156381$8467 + attribute \src "libresoc.v:158293.3-158302.6" + process $proc$libresoc.v:158293$8512 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156382.5-156382.29" + attribute \src "libresoc.v:158294.5-158294.29" switch \initial - attribute \src "libresoc.v:156382.9-156382.17" + attribute \src "libresoc.v:158294.9-158294.17" case 1'1 case end @@ -326987,14 +329594,14 @@ module \output$83 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:156391.3-156400.6" - process $proc$libresoc.v:156391$8468 + attribute \src "libresoc.v:158303.3-158312.6" + process $proc$libresoc.v:158303$8513 assign { } { } assign { } { } - assign $0\xer_ov$23[1:0]$8469 $1\xer_ov$23[1:0]$8470 - attribute \src "libresoc.v:156392.5-156392.29" + assign $0\xer_ov$23[1:0]$8514 $1\xer_ov$23[1:0]$8515 + attribute \src "libresoc.v:158304.5-158304.29" switch \initial - attribute \src "libresoc.v:156392.9-156392.17" + attribute \src "libresoc.v:158304.9-158304.17" case 1'1 case end @@ -327003,21 +329610,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$23[1:0]$8470 \xer_ov + assign $1\xer_ov$23[1:0]$8515 \xer_ov case - assign $1\xer_ov$23[1:0]$8470 2'00 + assign $1\xer_ov$23[1:0]$8515 2'00 end sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$8469 + update \xer_ov$23 $0\xer_ov$23[1:0]$8514 end - attribute \src "libresoc.v:156401.3-156410.6" - process $proc$libresoc.v:156401$8471 + attribute \src "libresoc.v:158313.3-158322.6" + process $proc$libresoc.v:158313$8516 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156402.5-156402.29" + attribute \src "libresoc.v:158314.5-158314.29" switch \initial - attribute \src "libresoc.v:156402.9-156402.17" + attribute \src "libresoc.v:158314.9-158314.17" case 1'1 case end @@ -327033,19 +329640,19 @@ module \output$83 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:156322$8444_Y - connect \$29 $not$libresoc.v:156323$8445_Y - connect \$28 $pos$libresoc.v:156324$8447_Y - connect \$32 $pos$libresoc.v:156325$8449_Y - connect \$34 $eq$libresoc.v:156326$8450_Y - connect \$36 $eq$libresoc.v:156327$8451_Y - connect \$38 $reduce_or$libresoc.v:156328$8452_Y - connect \$40 $not$libresoc.v:156329$8453_Y - connect \$42 $and$libresoc.v:156330$8454_Y - connect \$44 $or$libresoc.v:156331$8455_Y - connect \$46 $not$libresoc.v:156332$8456_Y - connect \$49 $and$libresoc.v:156333$8457_Y - connect \$51 $or$libresoc.v:156334$8458_Y + connect \$25 $and$libresoc.v:158234$8489_Y + connect \$29 $not$libresoc.v:158235$8490_Y + connect \$28 $pos$libresoc.v:158236$8492_Y + connect \$32 $pos$libresoc.v:158237$8494_Y + connect \$34 $eq$libresoc.v:158238$8495_Y + connect \$36 $eq$libresoc.v:158239$8496_Y + connect \$38 $reduce_or$libresoc.v:158240$8497_Y + connect \$40 $not$libresoc.v:158241$8498_Y + connect \$42 $and$libresoc.v:158242$8499_Y + connect \$44 $or$libresoc.v:158243$8500_Y + connect \$46 $not$libresoc.v:158244$8501_Y + connect \$49 $and$libresoc.v:158245$8502_Y + connect \$51 $or$libresoc.v:158246$8503_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -327062,93 +329669,93 @@ module \output$83 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:156430.1-156908.10" +attribute \src "libresoc.v:158342.1-158824.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage - attribute \src "libresoc.v:156431.7-156431.20" + attribute \src "libresoc.v:158343.7-158343.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:156861.3-156894.6" + attribute \src "libresoc.v:158777.3-158810.6" wire $0\ov[0:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:156861.3-156894.6" + attribute \src "libresoc.v:158777.3-158810.6" wire $1\ov[0:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:156861.3-156894.6" + attribute \src "libresoc.v:158777.3-158810.6" wire $2\ov[0:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:156861.3-156894.6" + attribute \src "libresoc.v:158777.3-158810.6" wire $3\ov[0:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $5\o[63:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:156789.3-156860.6" + attribute \src "libresoc.v:158705.3-158776.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:156780.18-156780.122" - wire $and$libresoc.v:156780$8486_Y - attribute \src "libresoc.v:156772.18-156772.109" - wire width 65 $extend$libresoc.v:156772$8474_Y - attribute \src "libresoc.v:156773.18-156773.100" - wire width 65 $extend$libresoc.v:156773$8476_Y - attribute \src "libresoc.v:156775.18-156775.113" - wire width 65 $extend$libresoc.v:156775$8479_Y - attribute \src "libresoc.v:156776.18-156776.104" - wire width 65 $extend$libresoc.v:156776$8481_Y - attribute \src "libresoc.v:156784.18-156784.114" - wire width 64 $extend$libresoc.v:156784$8490_Y - attribute \src "libresoc.v:156785.18-156785.114" - wire width 64 $extend$libresoc.v:156785$8492_Y - attribute \src "libresoc.v:156786.18-156786.114" - wire width 64 $extend$libresoc.v:156786$8494_Y - attribute \src "libresoc.v:156787.18-156787.114" - wire width 64 $extend$libresoc.v:156787$8496_Y - attribute \src "libresoc.v:156788.18-156788.115" - wire width 64 $extend$libresoc.v:156788$8498_Y - attribute \src "libresoc.v:156781.18-156781.128" - wire $ne$libresoc.v:156781$8487_Y - attribute \src "libresoc.v:156772.18-156772.109" - wire width 65 $neg$libresoc.v:156772$8475_Y - attribute \src "libresoc.v:156775.18-156775.113" - wire width 65 $neg$libresoc.v:156775$8480_Y - attribute \src "libresoc.v:156778.18-156778.116" - wire $not$libresoc.v:156778$8484_Y - attribute \src "libresoc.v:156783.18-156783.99" - wire $not$libresoc.v:156783$8489_Y - attribute \src "libresoc.v:156773.18-156773.100" - wire width 65 $pos$libresoc.v:156773$8477_Y - attribute \src "libresoc.v:156776.18-156776.104" - wire width 65 $pos$libresoc.v:156776$8482_Y - attribute \src "libresoc.v:156782.18-156782.118" - wire width 64 $pos$libresoc.v:156782$8488_Y - attribute \src "libresoc.v:156784.18-156784.114" - wire width 64 $pos$libresoc.v:156784$8491_Y - attribute \src "libresoc.v:156785.18-156785.114" - wire width 64 $pos$libresoc.v:156785$8493_Y - attribute \src "libresoc.v:156786.18-156786.114" - wire width 64 $pos$libresoc.v:156786$8495_Y - attribute \src "libresoc.v:156787.18-156787.114" - wire width 64 $pos$libresoc.v:156787$8497_Y - attribute \src "libresoc.v:156788.18-156788.115" - wire width 64 $pos$libresoc.v:156788$8499_Y - attribute \src "libresoc.v:156774.18-156774.121" - wire width 65 $ternary$libresoc.v:156774$8478_Y - attribute \src "libresoc.v:156777.18-156777.122" - wire width 65 $ternary$libresoc.v:156777$8483_Y - attribute \src "libresoc.v:156771.18-156771.120" - wire $xor$libresoc.v:156771$8473_Y - attribute \src "libresoc.v:156779.18-156779.127" - wire $xor$libresoc.v:156779$8485_Y + attribute \src "libresoc.v:158696.18-158696.122" + wire $and$libresoc.v:158696$8531_Y + attribute \src "libresoc.v:158688.18-158688.109" + wire width 65 $extend$libresoc.v:158688$8519_Y + attribute \src "libresoc.v:158689.18-158689.100" + wire width 65 $extend$libresoc.v:158689$8521_Y + attribute \src "libresoc.v:158691.18-158691.113" + wire width 65 $extend$libresoc.v:158691$8524_Y + attribute \src "libresoc.v:158692.18-158692.104" + wire width 65 $extend$libresoc.v:158692$8526_Y + attribute \src "libresoc.v:158700.18-158700.114" + wire width 64 $extend$libresoc.v:158700$8535_Y + attribute \src "libresoc.v:158701.18-158701.114" + wire width 64 $extend$libresoc.v:158701$8537_Y + attribute \src "libresoc.v:158702.18-158702.114" + wire width 64 $extend$libresoc.v:158702$8539_Y + attribute \src "libresoc.v:158703.18-158703.114" + wire width 64 $extend$libresoc.v:158703$8541_Y + attribute \src "libresoc.v:158704.18-158704.115" + wire width 64 $extend$libresoc.v:158704$8543_Y + attribute \src "libresoc.v:158697.18-158697.128" + wire $ne$libresoc.v:158697$8532_Y + attribute \src "libresoc.v:158688.18-158688.109" + wire width 65 $neg$libresoc.v:158688$8520_Y + attribute \src "libresoc.v:158691.18-158691.113" + wire width 65 $neg$libresoc.v:158691$8525_Y + attribute \src "libresoc.v:158694.18-158694.116" + wire $not$libresoc.v:158694$8529_Y + attribute \src "libresoc.v:158699.18-158699.99" + wire $not$libresoc.v:158699$8534_Y + attribute \src "libresoc.v:158689.18-158689.100" + wire width 65 $pos$libresoc.v:158689$8522_Y + attribute \src "libresoc.v:158692.18-158692.104" + wire width 65 $pos$libresoc.v:158692$8527_Y + attribute \src "libresoc.v:158698.18-158698.118" + wire width 64 $pos$libresoc.v:158698$8533_Y + attribute \src "libresoc.v:158700.18-158700.114" + wire width 64 $pos$libresoc.v:158700$8536_Y + attribute \src "libresoc.v:158701.18-158701.114" + wire width 64 $pos$libresoc.v:158701$8538_Y + attribute \src "libresoc.v:158702.18-158702.114" + wire width 64 $pos$libresoc.v:158702$8540_Y + attribute \src "libresoc.v:158703.18-158703.114" + wire width 64 $pos$libresoc.v:158703$8542_Y + attribute \src "libresoc.v:158704.18-158704.115" + wire width 64 $pos$libresoc.v:158704$8544_Y + attribute \src "libresoc.v:158690.18-158690.121" + wire width 65 $ternary$libresoc.v:158690$8523_Y + attribute \src "libresoc.v:158693.18-158693.122" + wire width 65 $ternary$libresoc.v:158693$8528_Y + attribute \src "libresoc.v:158687.18-158687.120" + wire $xor$libresoc.v:158687$8518_Y + attribute \src "libresoc.v:158695.18-158695.127" + wire $xor$libresoc.v:158695$8530_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -327197,44 +329804,46 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:156431.7-156431.15" + attribute \src "libresoc.v:158343.7-158343.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 44 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 29 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 29 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -327333,6 +329942,7 @@ module \output_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -327409,6 +330019,7 @@ module \output_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 28 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -327490,7 +330101,7 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:156780$8486 + cell $and $and$libresoc.v:158696$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327498,82 +330109,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:156780$8486_Y + connect \Y $and$libresoc.v:158696$8531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:156772$8474 + cell $pos $extend$libresoc.v:158688$8519 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:156772$8474_Y + connect \Y $extend$libresoc.v:158688$8519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:156773$8476 + cell $pos $extend$libresoc.v:158689$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:156773$8476_Y + connect \Y $extend$libresoc.v:158689$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:156775$8479 + cell $pos $extend$libresoc.v:158691$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:156775$8479_Y + connect \Y $extend$libresoc.v:158691$8524_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:156776$8481 + cell $pos $extend$libresoc.v:158692$8526 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:156776$8481_Y + connect \Y $extend$libresoc.v:158692$8526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:156784$8490 + cell $pos $extend$libresoc.v:158700$8535 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:156784$8490_Y + connect \Y $extend$libresoc.v:158700$8535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:156785$8492 + cell $pos $extend$libresoc.v:158701$8537 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:156785$8492_Y + connect \Y $extend$libresoc.v:158701$8537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:156786$8494 + cell $pos $extend$libresoc.v:158702$8539 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:156786$8494_Y + connect \Y $extend$libresoc.v:158702$8539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:156787$8496 + cell $pos $extend$libresoc.v:158703$8541 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:156787$8496_Y + connect \Y $extend$libresoc.v:158703$8541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:156788$8498 + cell $pos $extend$libresoc.v:158704$8543 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:156788$8498_Y + connect \Y $extend$libresoc.v:158704$8543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:156781$8487 + cell $ne $ne$libresoc.v:158697$8532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327581,122 +330192,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:156781$8487_Y + connect \Y $ne$libresoc.v:158697$8532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:156772$8475 + cell $neg $neg$libresoc.v:158688$8520 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156772$8474_Y - connect \Y $neg$libresoc.v:156772$8475_Y + connect \A $extend$libresoc.v:158688$8519_Y + connect \Y $neg$libresoc.v:158688$8520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:156775$8480 + cell $neg $neg$libresoc.v:158691$8525 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156775$8479_Y - connect \Y $neg$libresoc.v:156775$8480_Y + connect \A $extend$libresoc.v:158691$8524_Y + connect \Y $neg$libresoc.v:158691$8525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:156778$8484 + cell $not $not$libresoc.v:158694$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:156778$8484_Y + connect \Y $not$libresoc.v:158694$8529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:156783$8489 + cell $not $not$libresoc.v:158699$8534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:156783$8489_Y + connect \Y $not$libresoc.v:158699$8534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:156773$8477 + cell $pos $pos$libresoc.v:158689$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156773$8476_Y - connect \Y $pos$libresoc.v:156773$8477_Y + connect \A $extend$libresoc.v:158689$8521_Y + connect \Y $pos$libresoc.v:158689$8522_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:156776$8482 + cell $pos $pos$libresoc.v:158692$8527 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156776$8481_Y - connect \Y $pos$libresoc.v:156776$8482_Y + connect \A $extend$libresoc.v:158692$8526_Y + connect \Y $pos$libresoc.v:158692$8527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:156782$8488 + cell $pos $pos$libresoc.v:158698$8533 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:156782$8488_Y + connect \Y $pos$libresoc.v:158698$8533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:156784$8491 + cell $pos $pos$libresoc.v:158700$8536 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:156784$8490_Y - connect \Y $pos$libresoc.v:156784$8491_Y + connect \A $extend$libresoc.v:158700$8535_Y + connect \Y $pos$libresoc.v:158700$8536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:156785$8493 + cell $pos $pos$libresoc.v:158701$8538 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:156785$8492_Y - connect \Y $pos$libresoc.v:156785$8493_Y + connect \A $extend$libresoc.v:158701$8537_Y + connect \Y $pos$libresoc.v:158701$8538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:156786$8495 + cell $pos $pos$libresoc.v:158702$8540 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:156786$8494_Y - connect \Y $pos$libresoc.v:156786$8495_Y + connect \A $extend$libresoc.v:158702$8539_Y + connect \Y $pos$libresoc.v:158702$8540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:156787$8497 + cell $pos $pos$libresoc.v:158703$8542 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:156787$8496_Y - connect \Y $pos$libresoc.v:156787$8497_Y + connect \A $extend$libresoc.v:158703$8541_Y + connect \Y $pos$libresoc.v:158703$8542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:156788$8499 + cell $pos $pos$libresoc.v:158704$8544 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:156788$8498_Y - connect \Y $pos$libresoc.v:156788$8499_Y + connect \A $extend$libresoc.v:158704$8543_Y + connect \Y $pos$libresoc.v:158704$8544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:156774$8478 + cell $mux $ternary$libresoc.v:158690$8523 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:156774$8478_Y + connect \Y $ternary$libresoc.v:158690$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:156777$8483 + cell $mux $ternary$libresoc.v:158693$8528 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:156777$8483_Y + connect \Y $ternary$libresoc.v:158693$8528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:156771$8473 + cell $xor $xor$libresoc.v:158687$8518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327704,10 +330315,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:156771$8473_Y + connect \Y $xor$libresoc.v:158687$8518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:156779$8485 + cell $xor $xor$libresoc.v:158695$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327715,24 +330326,24 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:156779$8485_Y + connect \Y $xor$libresoc.v:158695$8530_Y end - attribute \src "libresoc.v:156431.7-156431.20" - process $proc$libresoc.v:156431$8502 + attribute \src "libresoc.v:158343.7-158343.20" + process $proc$libresoc.v:158343$8547 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156789.3-156860.6" - process $proc$libresoc.v:156789$8500 + attribute \src "libresoc.v:158705.3-158776.6" + process $proc$libresoc.v:158705$8545 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:156790.5-156790.29" + attribute \src "libresoc.v:158706.5-158706.29" switch \initial - attribute \src "libresoc.v:156790.9-156790.17" + attribute \src "libresoc.v:158706.9-158706.17" case 1'1 case end @@ -327831,13 +330442,13 @@ module \output_stage sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:156861.3-156894.6" - process $proc$libresoc.v:156861$8501 + attribute \src "libresoc.v:158777.3-158810.6" + process $proc$libresoc.v:158777$8546 assign { } { } assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:156862.5-156862.29" + attribute \src "libresoc.v:158778.5-158778.29" switch \initial - attribute \src "libresoc.v:156862.9-156862.17" + attribute \src "libresoc.v:158778.9-158778.17" case 1'1 case end @@ -327883,24 +330494,24 @@ module \output_stage sync always update \ov $0\ov[0:0] end - connect \$21 $xor$libresoc.v:156771$8473_Y - connect \$23 $neg$libresoc.v:156772$8475_Y - connect \$25 $pos$libresoc.v:156773$8477_Y - connect \$27 $ternary$libresoc.v:156774$8478_Y - connect \$30 $neg$libresoc.v:156775$8480_Y - connect \$32 $pos$libresoc.v:156776$8482_Y - connect \$34 $ternary$libresoc.v:156777$8483_Y - connect \$36 $not$libresoc.v:156778$8484_Y - connect \$38 $xor$libresoc.v:156779$8485_Y - connect \$40 $and$libresoc.v:156780$8486_Y - connect \$42 $ne$libresoc.v:156781$8487_Y - connect \$44 $pos$libresoc.v:156782$8488_Y - connect \$46 $not$libresoc.v:156783$8489_Y - connect \$48 $pos$libresoc.v:156784$8491_Y - connect \$50 $pos$libresoc.v:156785$8493_Y - connect \$52 $pos$libresoc.v:156786$8495_Y - connect \$54 $pos$libresoc.v:156787$8497_Y - connect \$56 $pos$libresoc.v:156788$8499_Y + connect \$21 $xor$libresoc.v:158687$8518_Y + connect \$23 $neg$libresoc.v:158688$8520_Y + connect \$25 $pos$libresoc.v:158689$8522_Y + connect \$27 $ternary$libresoc.v:158690$8523_Y + connect \$30 $neg$libresoc.v:158691$8525_Y + connect \$32 $pos$libresoc.v:158692$8527_Y + connect \$34 $ternary$libresoc.v:158693$8528_Y + connect \$36 $not$libresoc.v:158694$8529_Y + connect \$38 $xor$libresoc.v:158695$8530_Y + connect \$40 $and$libresoc.v:158696$8531_Y + connect \$42 $ne$libresoc.v:158697$8532_Y + connect \$44 $pos$libresoc.v:158698$8533_Y + connect \$46 $not$libresoc.v:158699$8534_Y + connect \$48 $pos$libresoc.v:158700$8536_Y + connect \$50 $pos$libresoc.v:158701$8538_Y + connect \$52 $pos$libresoc.v:158702$8540_Y + connect \$54 $pos$libresoc.v:158703$8542_Y + connect \$56 $pos$libresoc.v:158704$8544_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -327915,13 +330526,13 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:156912.1-156923.10" +attribute \src "libresoc.v:158828.1-158839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:156921.17-156921.111" - wire $and$libresoc.v:156921$8503_Y + attribute \src "libresoc.v:158837.17-158837.111" + wire $and$libresoc.v:158837$8548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -327931,7 +330542,7 @@ module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:156921$8503 + cell $and $and$libresoc.v:158837$8548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327939,18 +330550,18 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:156921$8503_Y + connect \Y $and$libresoc.v:158837$8548_Y end - connect \$1 $and$libresoc.v:156921$8503_Y + connect \$1 $and$libresoc.v:158837$8548_Y connect \trigger \$1 end -attribute \src "libresoc.v:156927.1-156938.10" +attribute \src "libresoc.v:158843.1-158854.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:156936.17-156936.111" - wire $and$libresoc.v:156936$8504_Y + attribute \src "libresoc.v:158852.17-158852.111" + wire $and$libresoc.v:158852$8549_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -327960,7 +330571,7 @@ module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:156936$8504 + cell $and $and$libresoc.v:158852$8549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327968,18 +330579,18 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:156936$8504_Y + connect \Y $and$libresoc.v:158852$8549_Y end - connect \$1 $and$libresoc.v:156936$8504_Y + connect \$1 $and$libresoc.v:158852$8549_Y connect \trigger \$1 end -attribute \src "libresoc.v:156942.1-156953.10" +attribute \src "libresoc.v:158858.1-158869.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 - attribute \src "libresoc.v:156951.17-156951.111" - wire $and$libresoc.v:156951$8505_Y + attribute \src "libresoc.v:158867.17-158867.111" + wire $and$libresoc.v:158867$8550_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -327989,7 +330600,7 @@ module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:156951$8505 + cell $and $and$libresoc.v:158867$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327997,18 +330608,18 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:156951$8505_Y + connect \Y $and$libresoc.v:158867$8550_Y end - connect \$1 $and$libresoc.v:156951$8505_Y + connect \$1 $and$libresoc.v:158867$8550_Y connect \trigger \$1 end -attribute \src "libresoc.v:156957.1-156968.10" +attribute \src "libresoc.v:158873.1-158884.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 - attribute \src "libresoc.v:156966.17-156966.111" - wire $and$libresoc.v:156966$8506_Y + attribute \src "libresoc.v:158882.17-158882.111" + wire $and$libresoc.v:158882$8551_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328018,7 +330629,7 @@ module \p$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:156966$8506 + cell $and $and$libresoc.v:158882$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328026,18 +330637,18 @@ module \p$111 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:156966$8506_Y + connect \Y $and$libresoc.v:158882$8551_Y end - connect \$1 $and$libresoc.v:156966$8506_Y + connect \$1 $and$libresoc.v:158882$8551_Y connect \trigger \$1 end -attribute \src "libresoc.v:156972.1-156983.10" +attribute \src "libresoc.v:158888.1-158899.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 - attribute \src "libresoc.v:156981.17-156981.111" - wire $and$libresoc.v:156981$8507_Y + attribute \src "libresoc.v:158897.17-158897.111" + wire $and$libresoc.v:158897$8552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328047,7 +330658,7 @@ module \p$116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:156981$8507 + cell $and $and$libresoc.v:158897$8552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328055,18 +330666,18 @@ module \p$116 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:156981$8507_Y + connect \Y $and$libresoc.v:158897$8552_Y end - connect \$1 $and$libresoc.v:156981$8507_Y + connect \$1 $and$libresoc.v:158897$8552_Y connect \trigger \$1 end -attribute \src "libresoc.v:156987.1-156998.10" +attribute \src "libresoc.v:158903.1-158914.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:156996.17-156996.111" - wire $and$libresoc.v:156996$8508_Y + attribute \src "libresoc.v:158912.17-158912.111" + wire $and$libresoc.v:158912$8553_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328076,7 +330687,7 @@ module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:156996$8508 + cell $and $and$libresoc.v:158912$8553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328084,18 +330695,18 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:156996$8508_Y + connect \Y $and$libresoc.v:158912$8553_Y end - connect \$1 $and$libresoc.v:156996$8508_Y + connect \$1 $and$libresoc.v:158912$8553_Y connect \trigger \$1 end -attribute \src "libresoc.v:157002.1-157013.10" +attribute \src "libresoc.v:158918.1-158929.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:157011.17-157011.111" - wire $and$libresoc.v:157011$8509_Y + attribute \src "libresoc.v:158927.17-158927.111" + wire $and$libresoc.v:158927$8554_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328105,7 +330716,7 @@ module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157011$8509 + cell $and $and$libresoc.v:158927$8554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328113,18 +330724,18 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157011$8509_Y + connect \Y $and$libresoc.v:158927$8554_Y end - connect \$1 $and$libresoc.v:157011$8509_Y + connect \$1 $and$libresoc.v:158927$8554_Y connect \trigger \$1 end -attribute \src "libresoc.v:157017.1-157028.10" +attribute \src "libresoc.v:158933.1-158944.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:157026.17-157026.111" - wire $and$libresoc.v:157026$8510_Y + attribute \src "libresoc.v:158942.17-158942.111" + wire $and$libresoc.v:158942$8555_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328134,7 +330745,7 @@ module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157026$8510 + cell $and $and$libresoc.v:158942$8555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328142,18 +330753,18 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157026$8510_Y + connect \Y $and$libresoc.v:158942$8555_Y end - connect \$1 $and$libresoc.v:157026$8510_Y + connect \$1 $and$libresoc.v:158942$8555_Y connect \trigger \$1 end -attribute \src "libresoc.v:157032.1-157043.10" +attribute \src "libresoc.v:158948.1-158959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:157041.17-157041.111" - wire $and$libresoc.v:157041$8511_Y + attribute \src "libresoc.v:158957.17-158957.111" + wire $and$libresoc.v:158957$8556_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328163,7 +330774,7 @@ module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157041$8511 + cell $and $and$libresoc.v:158957$8556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328171,18 +330782,18 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157041$8511_Y + connect \Y $and$libresoc.v:158957$8556_Y end - connect \$1 $and$libresoc.v:157041$8511_Y + connect \$1 $and$libresoc.v:158957$8556_Y connect \trigger \$1 end -attribute \src "libresoc.v:157047.1-157058.10" +attribute \src "libresoc.v:158963.1-158974.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:157056.17-157056.111" - wire $and$libresoc.v:157056$8512_Y + attribute \src "libresoc.v:158972.17-158972.111" + wire $and$libresoc.v:158972$8557_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328192,7 +330803,7 @@ module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157056$8512 + cell $and $and$libresoc.v:158972$8557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328200,18 +330811,18 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157056$8512_Y + connect \Y $and$libresoc.v:158972$8557_Y end - connect \$1 $and$libresoc.v:157056$8512_Y + connect \$1 $and$libresoc.v:158972$8557_Y connect \trigger \$1 end -attribute \src "libresoc.v:157062.1-157073.10" +attribute \src "libresoc.v:158978.1-158989.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 - attribute \src "libresoc.v:157071.17-157071.111" - wire $and$libresoc.v:157071$8513_Y + attribute \src "libresoc.v:158987.17-158987.111" + wire $and$libresoc.v:158987$8558_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328221,7 +330832,7 @@ module \p$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157071$8513 + cell $and $and$libresoc.v:158987$8558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328229,18 +330840,18 @@ module \p$36 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157071$8513_Y + connect \Y $and$libresoc.v:158987$8558_Y end - connect \$1 $and$libresoc.v:157071$8513_Y + connect \$1 $and$libresoc.v:158987$8558_Y connect \trigger \$1 end -attribute \src "libresoc.v:157077.1-157088.10" +attribute \src "libresoc.v:158993.1-159004.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 - attribute \src "libresoc.v:157086.17-157086.111" - wire $and$libresoc.v:157086$8514_Y + attribute \src "libresoc.v:159002.17-159002.111" + wire $and$libresoc.v:159002$8559_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328250,7 +330861,7 @@ module \p$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157086$8514 + cell $and $and$libresoc.v:159002$8559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328258,18 +330869,18 @@ module \p$46 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157086$8514_Y + connect \Y $and$libresoc.v:159002$8559_Y end - connect \$1 $and$libresoc.v:157086$8514_Y + connect \$1 $and$libresoc.v:159002$8559_Y connect \trigger \$1 end -attribute \src "libresoc.v:157092.1-157103.10" +attribute \src "libresoc.v:159008.1-159019.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 - attribute \src "libresoc.v:157101.17-157101.111" - wire $and$libresoc.v:157101$8515_Y + attribute \src "libresoc.v:159017.17-159017.111" + wire $and$libresoc.v:159017$8560_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328279,7 +330890,7 @@ module \p$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157101$8515 + cell $and $and$libresoc.v:159017$8560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328287,18 +330898,18 @@ module \p$48 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157101$8515_Y + connect \Y $and$libresoc.v:159017$8560_Y end - connect \$1 $and$libresoc.v:157101$8515_Y + connect \$1 $and$libresoc.v:159017$8560_Y connect \trigger \$1 end -attribute \src "libresoc.v:157107.1-157118.10" +attribute \src "libresoc.v:159023.1-159034.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:157116.17-157116.111" - wire $and$libresoc.v:157116$8516_Y + attribute \src "libresoc.v:159032.17-159032.111" + wire $and$libresoc.v:159032$8561_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328308,7 +330919,7 @@ module \p$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157116$8516 + cell $and $and$libresoc.v:159032$8561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328316,18 +330927,18 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157116$8516_Y + connect \Y $and$libresoc.v:159032$8561_Y end - connect \$1 $and$libresoc.v:157116$8516_Y + connect \$1 $and$libresoc.v:159032$8561_Y connect \trigger \$1 end -attribute \src "libresoc.v:157122.1-157133.10" +attribute \src "libresoc.v:159038.1-159049.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 - attribute \src "libresoc.v:157131.17-157131.111" - wire $and$libresoc.v:157131$8517_Y + attribute \src "libresoc.v:159047.17-159047.111" + wire $and$libresoc.v:159047$8562_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328337,7 +330948,7 @@ module \p$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157131$8517 + cell $and $and$libresoc.v:159047$8562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328345,18 +330956,18 @@ module \p$52 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157131$8517_Y + connect \Y $and$libresoc.v:159047$8562_Y end - connect \$1 $and$libresoc.v:157131$8517_Y + connect \$1 $and$libresoc.v:159047$8562_Y connect \trigger \$1 end -attribute \src "libresoc.v:157137.1-157148.10" +attribute \src "libresoc.v:159053.1-159064.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:157146.17-157146.111" - wire $and$libresoc.v:157146$8518_Y + attribute \src "libresoc.v:159062.17-159062.111" + wire $and$libresoc.v:159062$8563_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328366,7 +330977,7 @@ module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157146$8518 + cell $and $and$libresoc.v:159062$8563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328374,18 +330985,18 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157146$8518_Y + connect \Y $and$libresoc.v:159062$8563_Y end - connect \$1 $and$libresoc.v:157146$8518_Y + connect \$1 $and$libresoc.v:159062$8563_Y connect \trigger \$1 end -attribute \src "libresoc.v:157152.1-157163.10" +attribute \src "libresoc.v:159068.1-159079.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 - attribute \src "libresoc.v:157161.17-157161.111" - wire $and$libresoc.v:157161$8519_Y + attribute \src "libresoc.v:159077.17-159077.111" + wire $and$libresoc.v:159077$8564_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328395,7 +331006,7 @@ module \p$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157161$8519 + cell $and $and$libresoc.v:159077$8564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328403,18 +331014,18 @@ module \p$65 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157161$8519_Y + connect \Y $and$libresoc.v:159077$8564_Y end - connect \$1 $and$libresoc.v:157161$8519_Y + connect \$1 $and$libresoc.v:159077$8564_Y connect \trigger \$1 end -attribute \src "libresoc.v:157167.1-157178.10" +attribute \src "libresoc.v:159083.1-159094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 - attribute \src "libresoc.v:157176.17-157176.111" - wire $and$libresoc.v:157176$8520_Y + attribute \src "libresoc.v:159092.17-159092.111" + wire $and$libresoc.v:159092$8565_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328424,7 +331035,7 @@ module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157176$8520 + cell $and $and$libresoc.v:159092$8565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328432,18 +331043,18 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157176$8520_Y + connect \Y $and$libresoc.v:159092$8565_Y end - connect \$1 $and$libresoc.v:157176$8520_Y + connect \$1 $and$libresoc.v:159092$8565_Y connect \trigger \$1 end -attribute \src "libresoc.v:157182.1-157193.10" +attribute \src "libresoc.v:159098.1-159109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 - attribute \src "libresoc.v:157191.17-157191.111" - wire $and$libresoc.v:157191$8521_Y + attribute \src "libresoc.v:159107.17-159107.111" + wire $and$libresoc.v:159107$8566_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328453,7 +331064,7 @@ module \p$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157191$8521 + cell $and $and$libresoc.v:159107$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328461,18 +331072,18 @@ module \p$74 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157191$8521_Y + connect \Y $and$libresoc.v:159107$8566_Y end - connect \$1 $and$libresoc.v:157191$8521_Y + connect \$1 $and$libresoc.v:159107$8566_Y connect \trigger \$1 end -attribute \src "libresoc.v:157197.1-157208.10" +attribute \src "libresoc.v:159113.1-159124.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:157206.17-157206.111" - wire $and$libresoc.v:157206$8522_Y + attribute \src "libresoc.v:159122.17-159122.111" + wire $and$libresoc.v:159122$8567_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328482,7 +331093,7 @@ module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157206$8522 + cell $and $and$libresoc.v:159122$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328490,18 +331101,18 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157206$8522_Y + connect \Y $and$libresoc.v:159122$8567_Y end - connect \$1 $and$libresoc.v:157206$8522_Y + connect \$1 $and$libresoc.v:159122$8567_Y connect \trigger \$1 end -attribute \src "libresoc.v:157212.1-157223.10" +attribute \src "libresoc.v:159128.1-159139.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 - attribute \src "libresoc.v:157221.17-157221.111" - wire $and$libresoc.v:157221$8523_Y + attribute \src "libresoc.v:159137.17-159137.111" + wire $and$libresoc.v:159137$8568_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328511,7 +331122,7 @@ module \p$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157221$8523 + cell $and $and$libresoc.v:159137$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328519,18 +331130,18 @@ module \p$79 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157221$8523_Y + connect \Y $and$libresoc.v:159137$8568_Y end - connect \$1 $and$libresoc.v:157221$8523_Y + connect \$1 $and$libresoc.v:159137$8568_Y connect \trigger \$1 end -attribute \src "libresoc.v:157227.1-157238.10" +attribute \src "libresoc.v:159143.1-159154.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 - attribute \src "libresoc.v:157236.17-157236.111" - wire $and$libresoc.v:157236$8524_Y + attribute \src "libresoc.v:159152.17-159152.111" + wire $and$libresoc.v:159152$8569_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328540,7 +331151,7 @@ module \p$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157236$8524 + cell $and $and$libresoc.v:159152$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328548,18 +331159,18 @@ module \p$81 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157236$8524_Y + connect \Y $and$libresoc.v:159152$8569_Y end - connect \$1 $and$libresoc.v:157236$8524_Y + connect \$1 $and$libresoc.v:159152$8569_Y connect \trigger \$1 end -attribute \src "libresoc.v:157242.1-157253.10" +attribute \src "libresoc.v:159158.1-159169.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 - attribute \src "libresoc.v:157251.17-157251.111" - wire $and$libresoc.v:157251$8525_Y + attribute \src "libresoc.v:159167.17-159167.111" + wire $and$libresoc.v:159167$8570_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328569,7 +331180,7 @@ module \p$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157251$8525 + cell $and $and$libresoc.v:159167$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328577,18 +331188,18 @@ module \p$91 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157251$8525_Y + connect \Y $and$libresoc.v:159167$8570_Y end - connect \$1 $and$libresoc.v:157251$8525_Y + connect \$1 $and$libresoc.v:159167$8570_Y connect \trigger \$1 end -attribute \src "libresoc.v:157257.1-157268.10" +attribute \src "libresoc.v:159173.1-159184.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:157266.17-157266.111" - wire $and$libresoc.v:157266$8526_Y + attribute \src "libresoc.v:159182.17-159182.111" + wire $and$libresoc.v:159182$8571_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328598,7 +331209,7 @@ module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157266$8526 + cell $and $and$libresoc.v:159182$8571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328606,18 +331217,18 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157266$8526_Y + connect \Y $and$libresoc.v:159182$8571_Y end - connect \$1 $and$libresoc.v:157266$8526_Y + connect \$1 $and$libresoc.v:159182$8571_Y connect \trigger \$1 end -attribute \src "libresoc.v:157272.1-157283.10" +attribute \src "libresoc.v:159188.1-159199.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 - attribute \src "libresoc.v:157281.17-157281.111" - wire $and$libresoc.v:157281$8527_Y + attribute \src "libresoc.v:159197.17-159197.111" + wire $and$libresoc.v:159197$8572_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328627,7 +331238,7 @@ module \p$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157281$8527 + cell $and $and$libresoc.v:159197$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328635,18 +331246,18 @@ module \p$96 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157281$8527_Y + connect \Y $and$libresoc.v:159197$8572_Y end - connect \$1 $and$libresoc.v:157281$8527_Y + connect \$1 $and$libresoc.v:159197$8572_Y connect \trigger \$1 end -attribute \src "libresoc.v:157287.1-157298.10" +attribute \src "libresoc.v:159203.1-159214.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 - attribute \src "libresoc.v:157296.17-157296.111" - wire $and$libresoc.v:157296$8528_Y + attribute \src "libresoc.v:159212.17-159212.111" + wire $and$libresoc.v:159212$8573_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -328656,7 +331267,7 @@ module \p$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:157296$8528 + cell $and $and$libresoc.v:159212$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328664,36 +331275,36 @@ module \p$98 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:157296$8528_Y + connect \Y $and$libresoc.v:159212$8573_Y end - connect \$1 $and$libresoc.v:157296$8528_Y + connect \$1 $and$libresoc.v:159212$8573_Y connect \trigger \$1 end -attribute \src "libresoc.v:157302.1-157325.10" +attribute \src "libresoc.v:159218.1-159241.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:157303.7-157303.20" + attribute \src "libresoc.v:159219.7-159219.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157314.3-157323.6" + attribute \src "libresoc.v:159230.3-159239.6" wire $0\o[0:0] - attribute \src "libresoc.v:157314.3-157323.6" + attribute \src "libresoc.v:159230.3-159239.6" wire $1\o[0:0] - attribute \src "libresoc.v:157313.17-157313.95" - wire $eq$libresoc.v:157313$8529_Y + attribute \src "libresoc.v:159229.17-159229.95" + wire $eq$libresoc.v:159229$8574_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:157303.7-157303.15" + attribute \src "libresoc.v:159219.7-159219.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:157313$8529 + cell $eq $eq$libresoc.v:159229$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328701,24 +331312,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:157313$8529_Y + connect \Y $eq$libresoc.v:159229$8574_Y end - attribute \src "libresoc.v:157303.7-157303.20" - process $proc$libresoc.v:157303$8531 + attribute \src "libresoc.v:159219.7-159219.20" + process $proc$libresoc.v:159219$8576 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157314.3-157323.6" - process $proc$libresoc.v:157314$8530 + attribute \src "libresoc.v:159230.3-159239.6" + process $proc$libresoc.v:159230$8575 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:157315.5-157315.29" + attribute \src "libresoc.v:159231.5-159231.29" switch \initial - attribute \src "libresoc.v:157315.9-157315.17" + attribute \src "libresoc.v:159231.9-159231.17" case 1'1 case end @@ -328734,296 +331345,296 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:157313$8529_Y + connect \$1 $eq$libresoc.v:159229$8574_Y connect \n \$1 end -attribute \src "libresoc.v:157329.1-158143.10" +attribute \src "libresoc.v:159245.1-160059.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:158106.3-158121.6" + attribute \src "libresoc.v:160022.3-160037.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:158070.3-158105.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8621 - attribute \src "libresoc.v:157628.3-157629.57" + attribute \src "libresoc.v:159986.3-160021.6" + wire $0\adrok_l_s_addr_acked$next[0:0]$8666 + attribute \src "libresoc.v:159544.3-159545.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:157720.3-157728.6" - wire $0\busy_delay$next[0:0]$8589 - attribute \src "libresoc.v:157626.3-157627.37" + attribute \src "libresoc.v:159636.3-159644.6" + wire $0\busy_delay$next[0:0]$8634 + attribute \src "libresoc.v:159542.3-159543.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:158054.3-158069.6" + attribute \src "libresoc.v:159970.3-159985.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:158044.3-158053.6" + attribute \src "libresoc.v:159960.3-159969.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:158034.3-158043.6" + attribute \src "libresoc.v:159950.3-159959.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:158015.3-158024.6" + attribute \src "libresoc.v:159931.3-159940.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:157976.3-158014.6" - wire width 2 $0\fsm_state$next[1:0]$8607 - attribute \src "libresoc.v:157618.3-157619.35" + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $0\fsm_state$next[1:0]$8652 + attribute \src "libresoc.v:159534.3-159535.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:157330.7-157330.20" + attribute \src "libresoc.v:159246.7-159246.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157916.3-157925.6" + attribute \src "libresoc.v:159832.3-159841.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:157624.3-157625.35" + attribute \src "libresoc.v:159540.3-159541.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:157849.3-157879.6" + attribute \src "libresoc.v:159765.3-159795.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:157906.3-157915.6" + attribute \src "libresoc.v:159822.3-159831.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:157926.3-157935.6" + attribute \src "libresoc.v:159842.3-159851.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:157755.3-157770.6" + attribute \src "libresoc.v:159671.3-159686.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:157739.3-157754.6" + attribute \src "libresoc.v:159655.3-159670.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:158025.3-158033.6" - wire $0\lsui_active_dly$next[0:0]$8615 - attribute \src "libresoc.v:157616.3-157617.47" + attribute \src "libresoc.v:159941.3-159949.6" + wire $0\lsui_active_dly$next[0:0]$8660 + attribute \src "libresoc.v:159532.3-159533.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:157956.3-157975.6" + attribute \src "libresoc.v:159872.3-159891.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:157620.3-157621.36" + attribute \src "libresoc.v:159536.3-159537.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:157896.3-157905.6" + attribute \src "libresoc.v:159812.3-159821.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:157880.3-157895.6" + attribute \src "libresoc.v:159796.3-159811.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:157729.3-157738.6" + attribute \src "libresoc.v:159645.3-159654.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:157710.3-157719.6" + attribute \src "libresoc.v:159626.3-159635.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:157695.3-157709.6" - wire $0\st_done_s_st_done$next[0:0]$8584 - attribute \src "libresoc.v:157630.3-157631.51" + attribute \src "libresoc.v:159611.3-159625.6" + wire $0\st_done_s_st_done$next[0:0]$8629 + attribute \src "libresoc.v:159546.3-159547.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:157936.3-157945.6" + attribute \src "libresoc.v:159852.3-159861.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:157622.3-157623.35" + attribute \src "libresoc.v:159538.3-159539.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:157771.3-157796.6" + attribute \src "libresoc.v:159687.3-159712.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:157823.3-157848.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:157797.3-157822.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:157946.3-157955.6" + attribute \src "libresoc.v:159862.3-159871.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:158106.3-158121.6" + attribute \src "libresoc.v:160022.3-160037.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:158070.3-158105.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8622 - attribute \src "libresoc.v:157424.7-157424.34" + attribute \src "libresoc.v:159986.3-160021.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8667 + attribute \src "libresoc.v:159340.7-159340.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:157720.3-157728.6" - wire $1\busy_delay$next[0:0]$8590 - attribute \src "libresoc.v:157428.7-157428.24" + attribute \src "libresoc.v:159636.3-159644.6" + wire $1\busy_delay$next[0:0]$8635 + attribute \src "libresoc.v:159344.7-159344.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:158054.3-158069.6" + attribute \src "libresoc.v:159970.3-159985.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:158044.3-158053.6" + attribute \src "libresoc.v:159960.3-159969.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:158034.3-158043.6" + attribute \src "libresoc.v:159950.3-159959.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:158015.3-158024.6" + attribute \src "libresoc.v:159931.3-159940.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:157976.3-158014.6" - wire width 2 $1\fsm_state$next[1:0]$8608 - attribute \src "libresoc.v:157450.13-157450.29" + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $1\fsm_state$next[1:0]$8653 + attribute \src "libresoc.v:159366.13-159366.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:157916.3-157925.6" + attribute \src "libresoc.v:159832.3-159841.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:157464.7-157464.21" + attribute \src "libresoc.v:159380.7-159380.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:157849.3-157879.6" + attribute \src "libresoc.v:159765.3-159795.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:157906.3-157915.6" + attribute \src "libresoc.v:159822.3-159831.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:157926.3-157935.6" + attribute \src "libresoc.v:159842.3-159851.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:157755.3-157770.6" + attribute \src "libresoc.v:159671.3-159686.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:157739.3-157754.6" + attribute \src "libresoc.v:159655.3-159670.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:158025.3-158033.6" - wire $1\lsui_active_dly$next[0:0]$8616 - attribute \src "libresoc.v:157507.7-157507.29" + attribute \src "libresoc.v:159941.3-159949.6" + wire $1\lsui_active_dly$next[0:0]$8661 + attribute \src "libresoc.v:159423.7-159423.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:157956.3-157975.6" + attribute \src "libresoc.v:159872.3-159891.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:157519.7-157519.25" + attribute \src "libresoc.v:159435.7-159435.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:157896.3-157905.6" + attribute \src "libresoc.v:159812.3-159821.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:157880.3-157895.6" + attribute \src "libresoc.v:159796.3-159811.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:157729.3-157738.6" + attribute \src "libresoc.v:159645.3-159654.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:157710.3-157719.6" + attribute \src "libresoc.v:159626.3-159635.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:157695.3-157709.6" - wire $1\st_done_s_st_done$next[0:0]$8585 - attribute \src "libresoc.v:157539.7-157539.31" + attribute \src "libresoc.v:159611.3-159625.6" + wire $1\st_done_s_st_done$next[0:0]$8630 + attribute \src "libresoc.v:159455.7-159455.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:157936.3-157945.6" + attribute \src "libresoc.v:159852.3-159861.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:157547.7-157547.21" + attribute \src "libresoc.v:159463.7-159463.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:157771.3-157796.6" + attribute \src "libresoc.v:159687.3-159712.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:157823.3-157848.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:157797.3-157822.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:157946.3-157955.6" + attribute \src "libresoc.v:159862.3-159871.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:158106.3-158121.6" + attribute \src "libresoc.v:160022.3-160037.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:158070.3-158105.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8623 - attribute \src "libresoc.v:158054.3-158069.6" + attribute \src "libresoc.v:159986.3-160021.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8668 + attribute \src "libresoc.v:159970.3-159985.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:157976.3-158014.6" - wire width 2 $2\fsm_state$next[1:0]$8609 - attribute \src "libresoc.v:157849.3-157879.6" + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $2\fsm_state$next[1:0]$8654 + attribute \src "libresoc.v:159765.3-159795.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:157755.3-157770.6" + attribute \src "libresoc.v:159671.3-159686.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:157739.3-157754.6" + attribute \src "libresoc.v:159655.3-159670.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:157956.3-157975.6" + attribute \src "libresoc.v:159872.3-159891.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:157880.3-157895.6" + attribute \src "libresoc.v:159796.3-159811.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:157695.3-157709.6" - wire $2\st_done_s_st_done$next[0:0]$8586 - attribute \src "libresoc.v:157771.3-157796.6" + attribute \src "libresoc.v:159611.3-159625.6" + wire $2\st_done_s_st_done$next[0:0]$8631 + attribute \src "libresoc.v:159687.3-159712.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:157823.3-157848.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:157797.3-157822.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:158070.3-158105.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8624 - attribute \src "libresoc.v:157976.3-158014.6" - wire width 2 $3\fsm_state$next[1:0]$8610 - attribute \src "libresoc.v:157849.3-157879.6" + attribute \src "libresoc.v:159986.3-160021.6" + wire $3\adrok_l_s_addr_acked$next[0:0]$8669 + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $3\fsm_state$next[1:0]$8655 + attribute \src "libresoc.v:159765.3-159795.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:157771.3-157796.6" + attribute \src "libresoc.v:159687.3-159712.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:157823.3-157848.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:157797.3-157822.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:158070.3-158105.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8625 - attribute \src "libresoc.v:157976.3-158014.6" - wire width 2 $4\fsm_state$next[1:0]$8611 - attribute \src "libresoc.v:157849.3-157879.6" + attribute \src "libresoc.v:159986.3-160021.6" + wire $4\adrok_l_s_addr_acked$next[0:0]$8670 + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $4\fsm_state$next[1:0]$8656 + attribute \src "libresoc.v:159765.3-159795.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:157771.3-157796.6" + attribute \src "libresoc.v:159687.3-159712.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:157823.3-157848.6" + attribute \src "libresoc.v:159739.3-159764.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:157797.3-157822.6" + attribute \src "libresoc.v:159713.3-159738.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:158070.3-158105.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$8626 - attribute \src "libresoc.v:157976.3-158014.6" - wire width 2 $5\fsm_state$next[1:0]$8612 - attribute \src "libresoc.v:157849.3-157879.6" + attribute \src "libresoc.v:159986.3-160021.6" + wire $5\adrok_l_s_addr_acked$next[0:0]$8671 + attribute \src "libresoc.v:159892.3-159930.6" + wire width 2 $5\fsm_state$next[1:0]$8657 + attribute \src "libresoc.v:159765.3-159795.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:158070.3-158105.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$8627 - attribute \src "libresoc.v:157576.18-157576.115" - wire $and$libresoc.v:157576$8533_Y - attribute \src "libresoc.v:157578.18-157578.95" - wire $and$libresoc.v:157578$8535_Y - attribute \src "libresoc.v:157580.17-157580.138" - wire $and$libresoc.v:157580$8537_Y - attribute \src "libresoc.v:157581.18-157581.95" - wire $and$libresoc.v:157581$8538_Y - attribute \src "libresoc.v:157584.18-157584.136" - wire $and$libresoc.v:157584$8543_Y - attribute \src "libresoc.v:157585.18-157585.136" - wire $and$libresoc.v:157585$8544_Y - attribute \src "libresoc.v:157586.18-157586.136" - wire $and$libresoc.v:157586$8545_Y - attribute \src "libresoc.v:157587.18-157587.136" - wire $and$libresoc.v:157587$8546_Y - attribute \src "libresoc.v:157588.18-157588.136" - wire $and$libresoc.v:157588$8547_Y - attribute \src "libresoc.v:157593.18-157593.119" - wire width 176 $and$libresoc.v:157593$8552_Y - attribute \src "libresoc.v:157596.18-157596.136" - wire $and$libresoc.v:157596$8555_Y - attribute \src "libresoc.v:157597.18-157597.136" - wire $and$libresoc.v:157597$8556_Y - attribute \src "libresoc.v:157599.18-157599.139" - wire $and$libresoc.v:157599$8558_Y - attribute \src "libresoc.v:157603.18-157603.139" - wire $and$libresoc.v:157603$8562_Y - attribute \src "libresoc.v:157605.18-157605.114" - wire $and$libresoc.v:157605$8564_Y - attribute \src "libresoc.v:157607.18-157607.114" - wire $and$libresoc.v:157607$8566_Y - attribute \src "libresoc.v:157611.18-157611.103" - wire $and$libresoc.v:157611$8570_Y - attribute \src "libresoc.v:157612.17-157612.135" - wire $and$libresoc.v:157612$8571_Y - attribute \src "libresoc.v:157615.18-157615.103" - wire $and$libresoc.v:157615$8574_Y - attribute \src "libresoc.v:157582.18-157582.109" - wire width 4 $extend$libresoc.v:157582$8539_Y - attribute \src "libresoc.v:157583.18-157583.109" - wire width 4 $extend$libresoc.v:157583$8541_Y - attribute \src "libresoc.v:157594.18-157594.112" - wire width 8 $mul$libresoc.v:157594$8553_Y - attribute \src "libresoc.v:157600.18-157600.112" - wire width 8 $mul$libresoc.v:157600$8559_Y - attribute \src "libresoc.v:157575.17-157575.103" - wire $not$libresoc.v:157575$8532_Y - attribute \src "libresoc.v:157577.18-157577.94" - wire $not$libresoc.v:157577$8534_Y - attribute \src "libresoc.v:157579.18-157579.94" - wire $not$libresoc.v:157579$8536_Y - attribute \src "libresoc.v:157589.18-157589.102" - wire $not$libresoc.v:157589$8548_Y - attribute \src "libresoc.v:157592.18-157592.97" - wire $not$libresoc.v:157592$8551_Y - attribute \src "libresoc.v:157598.18-157598.102" - wire $not$libresoc.v:157598$8557_Y - attribute \src "libresoc.v:157601.17-157601.103" - wire $not$libresoc.v:157601$8560_Y - attribute \src "libresoc.v:157608.18-157608.101" - wire $not$libresoc.v:157608$8567_Y - attribute \src "libresoc.v:157609.18-157609.111" - wire $not$libresoc.v:157609$8568_Y - attribute \src "libresoc.v:157610.18-157610.110" - wire $not$libresoc.v:157610$8569_Y - attribute \src "libresoc.v:157613.18-157613.102" - wire $not$libresoc.v:157613$8572_Y - attribute \src "libresoc.v:157614.18-157614.102" - wire $not$libresoc.v:157614$8573_Y - attribute \src "libresoc.v:157590.18-157590.111" - wire $or$libresoc.v:157590$8549_Y - attribute \src "libresoc.v:157591.17-157591.130" - wire $or$libresoc.v:157591$8550_Y - attribute \src "libresoc.v:157604.18-157604.130" - wire $or$libresoc.v:157604$8563_Y - attribute \src "libresoc.v:157606.18-157606.130" - wire $or$libresoc.v:157606$8565_Y - attribute \src "libresoc.v:157582.18-157582.109" - wire width 4 $pos$libresoc.v:157582$8540_Y - attribute \src "libresoc.v:157583.18-157583.109" - wire width 4 $pos$libresoc.v:157583$8542_Y - attribute \src "libresoc.v:157602.18-157602.121" - wire width 319 $sshl$libresoc.v:157602$8561_Y - attribute \src "libresoc.v:157595.18-157595.106" - wire width 176 $sshr$libresoc.v:157595$8554_Y + attribute \src "libresoc.v:159986.3-160021.6" + wire $6\adrok_l_s_addr_acked$next[0:0]$8672 + attribute \src "libresoc.v:159492.18-159492.115" + wire $and$libresoc.v:159492$8578_Y + attribute \src "libresoc.v:159494.18-159494.95" + wire $and$libresoc.v:159494$8580_Y + attribute \src "libresoc.v:159496.17-159496.138" + wire $and$libresoc.v:159496$8582_Y + attribute \src "libresoc.v:159497.18-159497.95" + wire $and$libresoc.v:159497$8583_Y + attribute \src "libresoc.v:159500.18-159500.136" + wire $and$libresoc.v:159500$8588_Y + attribute \src "libresoc.v:159501.18-159501.136" + wire $and$libresoc.v:159501$8589_Y + attribute \src "libresoc.v:159502.18-159502.136" + wire $and$libresoc.v:159502$8590_Y + attribute \src "libresoc.v:159503.18-159503.136" + wire $and$libresoc.v:159503$8591_Y + attribute \src "libresoc.v:159504.18-159504.136" + wire $and$libresoc.v:159504$8592_Y + attribute \src "libresoc.v:159509.18-159509.119" + wire width 176 $and$libresoc.v:159509$8597_Y + attribute \src "libresoc.v:159512.18-159512.136" + wire $and$libresoc.v:159512$8600_Y + attribute \src "libresoc.v:159513.18-159513.136" + wire $and$libresoc.v:159513$8601_Y + attribute \src "libresoc.v:159515.18-159515.139" + wire $and$libresoc.v:159515$8603_Y + attribute \src "libresoc.v:159519.18-159519.139" + wire $and$libresoc.v:159519$8607_Y + attribute \src "libresoc.v:159521.18-159521.114" + wire $and$libresoc.v:159521$8609_Y + attribute \src "libresoc.v:159523.18-159523.114" + wire $and$libresoc.v:159523$8611_Y + attribute \src "libresoc.v:159527.18-159527.103" + wire $and$libresoc.v:159527$8615_Y + attribute \src "libresoc.v:159528.17-159528.135" + wire $and$libresoc.v:159528$8616_Y + attribute \src "libresoc.v:159531.18-159531.103" + wire $and$libresoc.v:159531$8619_Y + attribute \src "libresoc.v:159498.18-159498.109" + wire width 4 $extend$libresoc.v:159498$8584_Y + attribute \src "libresoc.v:159499.18-159499.109" + wire width 4 $extend$libresoc.v:159499$8586_Y + attribute \src "libresoc.v:159510.18-159510.112" + wire width 8 $mul$libresoc.v:159510$8598_Y + attribute \src "libresoc.v:159516.18-159516.112" + wire width 8 $mul$libresoc.v:159516$8604_Y + attribute \src "libresoc.v:159491.17-159491.103" + wire $not$libresoc.v:159491$8577_Y + attribute \src "libresoc.v:159493.18-159493.94" + wire $not$libresoc.v:159493$8579_Y + attribute \src "libresoc.v:159495.18-159495.94" + wire $not$libresoc.v:159495$8581_Y + attribute \src "libresoc.v:159505.18-159505.102" + wire $not$libresoc.v:159505$8593_Y + attribute \src "libresoc.v:159508.18-159508.97" + wire $not$libresoc.v:159508$8596_Y + attribute \src "libresoc.v:159514.18-159514.102" + wire $not$libresoc.v:159514$8602_Y + attribute \src "libresoc.v:159517.17-159517.103" + wire $not$libresoc.v:159517$8605_Y + attribute \src "libresoc.v:159524.18-159524.101" + wire $not$libresoc.v:159524$8612_Y + attribute \src "libresoc.v:159525.18-159525.111" + wire $not$libresoc.v:159525$8613_Y + attribute \src "libresoc.v:159526.18-159526.110" + wire $not$libresoc.v:159526$8614_Y + attribute \src "libresoc.v:159529.18-159529.102" + wire $not$libresoc.v:159529$8617_Y + attribute \src "libresoc.v:159530.18-159530.102" + wire $not$libresoc.v:159530$8618_Y + attribute \src "libresoc.v:159506.18-159506.111" + wire $or$libresoc.v:159506$8594_Y + attribute \src "libresoc.v:159507.17-159507.130" + wire $or$libresoc.v:159507$8595_Y + attribute \src "libresoc.v:159520.18-159520.130" + wire $or$libresoc.v:159520$8608_Y + attribute \src "libresoc.v:159522.18-159522.130" + wire $or$libresoc.v:159522$8610_Y + attribute \src "libresoc.v:159498.18-159498.109" + wire width 4 $pos$libresoc.v:159498$8585_Y + attribute \src "libresoc.v:159499.18-159499.109" + wire width 4 $pos$libresoc.v:159499$8587_Y + attribute \src "libresoc.v:159518.18-159518.121" + wire width 319 $sshl$libresoc.v:159518$8606_Y + attribute \src "libresoc.v:159511.18-159511.106" + wire width 176 $sshr$libresoc.v:159511$8599_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" @@ -329132,9 +331743,9 @@ module \pimem wire \busy_l_r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \cyc_l_q_cyc @@ -329146,7 +331757,7 @@ module \pimem wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:157330.7-157330.15" + attribute \src "libresoc.v:159246.7-159246.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active @@ -329265,7 +331876,7 @@ module \pimem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:157576$8533 + cell $and $and$libresoc.v:159492$8578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329273,10 +331884,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:157576$8533_Y + connect \Y $and$libresoc.v:159492$8578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:157578$8535 + cell $and $and$libresoc.v:159494$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329284,10 +331895,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:157578$8535_Y + connect \Y $and$libresoc.v:159494$8580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:157580$8537 + cell $and $and$libresoc.v:159496$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329295,10 +331906,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:157580$8537_Y + connect \Y $and$libresoc.v:159496$8582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:157581$8538 + cell $and $and$libresoc.v:159497$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329306,10 +331917,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:157581$8538_Y + connect \Y $and$libresoc.v:159497$8583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:157584$8543 + cell $and $and$libresoc.v:159500$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329317,10 +331928,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:157584$8543_Y + connect \Y $and$libresoc.v:159500$8588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:157585$8544 + cell $and $and$libresoc.v:159501$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329328,10 +331939,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:157585$8544_Y + connect \Y $and$libresoc.v:159501$8589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:157586$8545 + cell $and $and$libresoc.v:159502$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329339,10 +331950,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:157586$8545_Y + connect \Y $and$libresoc.v:159502$8590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:157587$8546 + cell $and $and$libresoc.v:159503$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329350,10 +331961,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:157587$8546_Y + connect \Y $and$libresoc.v:159503$8591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:157588$8547 + cell $and $and$libresoc.v:159504$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329361,10 +331972,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:157588$8547_Y + connect \Y $and$libresoc.v:159504$8592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:157593$8552 + cell $and $and$libresoc.v:159509$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -329372,10 +331983,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:157593$8552_Y + connect \Y $and$libresoc.v:159509$8597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:157596$8555 + cell $and $and$libresoc.v:159512$8600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329383,10 +331994,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:157596$8555_Y + connect \Y $and$libresoc.v:159512$8600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:157597$8556 + cell $and $and$libresoc.v:159513$8601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329394,10 +332005,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:157597$8556_Y + connect \Y $and$libresoc.v:159513$8601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:157599$8558 + cell $and $and$libresoc.v:159515$8603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329405,10 +332016,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:157599$8558_Y + connect \Y $and$libresoc.v:159515$8603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:157603$8562 + cell $and $and$libresoc.v:159519$8607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329416,10 +332027,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:157603$8562_Y + connect \Y $and$libresoc.v:159519$8607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:157605$8564 + cell $and $and$libresoc.v:159521$8609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329427,10 +332038,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:157605$8564_Y + connect \Y $and$libresoc.v:159521$8609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:157607$8566 + cell $and $and$libresoc.v:159523$8611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329438,10 +332049,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:157607$8566_Y + connect \Y $and$libresoc.v:159523$8611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:157611$8570 + cell $and $and$libresoc.v:159527$8615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329449,10 +332060,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:157611$8570_Y + connect \Y $and$libresoc.v:159527$8615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:157612$8571 + cell $and $and$libresoc.v:159528$8616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329460,10 +332071,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:157612$8571_Y + connect \Y $and$libresoc.v:159528$8616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:157615$8574 + cell $and $and$libresoc.v:159531$8619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329471,26 +332082,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:157615$8574_Y + connect \Y $and$libresoc.v:159531$8619_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:157582$8539 + cell $pos $extend$libresoc.v:159498$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:157582$8539_Y + connect \Y $extend$libresoc.v:159498$8584_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:157583$8541 + cell $pos $extend$libresoc.v:159499$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:157583$8541_Y + connect \Y $extend$libresoc.v:159499$8586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:157594$8553 + cell $mul $mul$libresoc.v:159510$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329498,10 +332109,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:157594$8553_Y + connect \Y $mul$libresoc.v:159510$8598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:157600$8559 + cell $mul $mul$libresoc.v:159516$8604 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329509,106 +332120,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:157600$8559_Y + connect \Y $mul$libresoc.v:159516$8604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:157575$8532 + cell $not $not$libresoc.v:159491$8577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:157575$8532_Y + connect \Y $not$libresoc.v:159491$8577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:157577$8534 + cell $not $not$libresoc.v:159493$8579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:157577$8534_Y + connect \Y $not$libresoc.v:159493$8579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:157579$8536 + cell $not $not$libresoc.v:159495$8581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:157579$8536_Y + connect \Y $not$libresoc.v:159495$8581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:157589$8548 + cell $not $not$libresoc.v:159505$8593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:157589$8548_Y + connect \Y $not$libresoc.v:159505$8593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:157592$8551 + cell $not $not$libresoc.v:159508$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:157592$8551_Y + connect \Y $not$libresoc.v:159508$8596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:157598$8557 + cell $not $not$libresoc.v:159514$8602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:157598$8557_Y + connect \Y $not$libresoc.v:159514$8602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:157601$8560 + cell $not $not$libresoc.v:159517$8605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:157601$8560_Y + connect \Y $not$libresoc.v:159517$8605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:157608$8567 + cell $not $not$libresoc.v:159524$8612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:157608$8567_Y + connect \Y $not$libresoc.v:159524$8612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:157609$8568 + cell $not $not$libresoc.v:159525$8613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:157609$8568_Y + connect \Y $not$libresoc.v:159525$8613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:157610$8569 + cell $not $not$libresoc.v:159526$8614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:157610$8569_Y + connect \Y $not$libresoc.v:159526$8614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:157613$8572 + cell $not $not$libresoc.v:159529$8617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:157613$8572_Y + connect \Y $not$libresoc.v:159529$8617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:157614$8573 + cell $not $not$libresoc.v:159530$8618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:157614$8573_Y + connect \Y $not$libresoc.v:159530$8618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:157590$8549 + cell $or $or$libresoc.v:159506$8594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329616,10 +332227,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:157590$8549_Y + connect \Y $or$libresoc.v:159506$8594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:157591$8550 + cell $or $or$libresoc.v:159507$8595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329627,10 +332238,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:157591$8550_Y + connect \Y $or$libresoc.v:159507$8595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:157604$8563 + cell $or $or$libresoc.v:159520$8608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329638,10 +332249,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:157604$8563_Y + connect \Y $or$libresoc.v:159520$8608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:157606$8565 + cell $or $or$libresoc.v:159522$8610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329649,26 +332260,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:157606$8565_Y + connect \Y $or$libresoc.v:159522$8610_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:157582$8540 + cell $pos $pos$libresoc.v:159498$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:157582$8539_Y - connect \Y $pos$libresoc.v:157582$8540_Y + connect \A $extend$libresoc.v:159498$8584_Y + connect \Y $pos$libresoc.v:159498$8585_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:157583$8542 + cell $pos $pos$libresoc.v:159499$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:157583$8541_Y - connect \Y $pos$libresoc.v:157583$8542_Y + connect \A $extend$libresoc.v:159499$8586_Y + connect \Y $pos$libresoc.v:159499$8587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:157602$8561 + cell $sshl $sshl$libresoc.v:159518$8606 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -329676,10 +332287,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:157602$8561_Y + connect \Y $sshl$libresoc.v:159518$8606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:157595$8554 + cell $sshr $sshr$libresoc.v:159511$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -329687,10 +332298,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:157595$8554_Y + connect \Y $sshr$libresoc.v:159511$8599_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:157632.11-157639.4" + attribute \src "libresoc.v:159548.11-159555.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -329700,7 +332311,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:157640.10-157646.4" + attribute \src "libresoc.v:159556.10-159562.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -329709,7 +332320,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:157647.9-157653.4" + attribute \src "libresoc.v:159563.9-159569.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -329718,7 +332329,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:157654.13-157660.4" + attribute \src "libresoc.v:159570.13-159576.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -329727,7 +332338,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:157661.10-157666.4" + attribute \src "libresoc.v:159577.10-159582.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -329735,7 +332346,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:157667.11-157673.4" + attribute \src "libresoc.v:159583.11-159589.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -329744,7 +332355,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:157674.13-157680.4" + attribute \src "libresoc.v:159590.13-159596.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -329753,7 +332364,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:157681.11-157687.4" + attribute \src "libresoc.v:159597.11-159603.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -329762,7 +332373,7 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:157688.11-157694.4" + attribute \src "libresoc.v:159604.11-159610.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -329770,143 +332381,143 @@ module \pimem connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:157330.7-157330.20" - process $proc$libresoc.v:157330$8629 + attribute \src "libresoc.v:159246.7-159246.20" + process $proc$libresoc.v:159246$8674 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157424.7-157424.34" - process $proc$libresoc.v:157424$8630 + attribute \src "libresoc.v:159340.7-159340.34" + process $proc$libresoc.v:159340$8675 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:157428.7-157428.24" - process $proc$libresoc.v:157428$8631 + attribute \src "libresoc.v:159344.7-159344.24" + process $proc$libresoc.v:159344$8676 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:157450.13-157450.29" - process $proc$libresoc.v:157450$8632 + attribute \src "libresoc.v:159366.13-159366.29" + process $proc$libresoc.v:159366$8677 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:157464.7-157464.21" - process $proc$libresoc.v:157464$8633 + attribute \src "libresoc.v:159380.7-159380.21" + process $proc$libresoc.v:159380$8678 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:157507.7-157507.29" - process $proc$libresoc.v:157507$8634 + attribute \src "libresoc.v:159423.7-159423.29" + process $proc$libresoc.v:159423$8679 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:157519.7-157519.25" - process $proc$libresoc.v:157519$8635 + attribute \src "libresoc.v:159435.7-159435.25" + process $proc$libresoc.v:159435$8680 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:157539.7-157539.31" - process $proc$libresoc.v:157539$8636 + attribute \src "libresoc.v:159455.7-159455.31" + process $proc$libresoc.v:159455$8681 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:157547.7-157547.21" - process $proc$libresoc.v:157547$8637 + attribute \src "libresoc.v:159463.7-159463.21" + process $proc$libresoc.v:159463$8682 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:157616.3-157617.47" - process $proc$libresoc.v:157616$8575 + attribute \src "libresoc.v:159532.3-159533.47" + process $proc$libresoc.v:159532$8620 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:157618.3-157619.35" - process $proc$libresoc.v:157618$8576 + attribute \src "libresoc.v:159534.3-159535.35" + process $proc$libresoc.v:159534$8621 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:157620.3-157621.36" - process $proc$libresoc.v:157620$8577 + attribute \src "libresoc.v:159536.3-159537.36" + process $proc$libresoc.v:159536$8622 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:157622.3-157623.35" - process $proc$libresoc.v:157622$8578 + attribute \src "libresoc.v:159538.3-159539.35" + process $proc$libresoc.v:159538$8623 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:157624.3-157625.35" - process $proc$libresoc.v:157624$8579 + attribute \src "libresoc.v:159540.3-159541.35" + process $proc$libresoc.v:159540$8624 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end - attribute \src "libresoc.v:157626.3-157627.37" - process $proc$libresoc.v:157626$8580 + attribute \src "libresoc.v:159542.3-159543.37" + process $proc$libresoc.v:159542$8625 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:157628.3-157629.57" - process $proc$libresoc.v:157628$8581 + attribute \src "libresoc.v:159544.3-159545.57" + process $proc$libresoc.v:159544$8626 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:157630.3-157631.51" - process $proc$libresoc.v:157630$8582 + attribute \src "libresoc.v:159546.3-159547.51" + process $proc$libresoc.v:159546$8627 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:157695.3-157709.6" - process $proc$libresoc.v:157695$8583 + attribute \src "libresoc.v:159611.3-159625.6" + process $proc$libresoc.v:159611$8628 assign { } { } assign { } { } assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8584 $2\st_done_s_st_done$next[0:0]$8586 - attribute \src "libresoc.v:157696.5-157696.29" + assign $0\st_done_s_st_done$next[0:0]$8629 $2\st_done_s_st_done$next[0:0]$8631 + attribute \src "libresoc.v:159612.5-159612.29" switch \initial - attribute \src "libresoc.v:157696.9-157696.17" + attribute \src "libresoc.v:159612.9-159612.17" case 1'1 case end @@ -329915,30 +332526,30 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8585 1'1 + assign $1\st_done_s_st_done$next[0:0]$8630 1'1 case - assign $1\st_done_s_st_done$next[0:0]$8585 1'0 + assign $1\st_done_s_st_done$next[0:0]$8630 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8586 1'0 + assign $2\st_done_s_st_done$next[0:0]$8631 1'0 case - assign $2\st_done_s_st_done$next[0:0]$8586 $1\st_done_s_st_done$next[0:0]$8585 + assign $2\st_done_s_st_done$next[0:0]$8631 $1\st_done_s_st_done$next[0:0]$8630 end sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8584 + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8629 end - attribute \src "libresoc.v:157710.3-157719.6" - process $proc$libresoc.v:157710$8587 + attribute \src "libresoc.v:159626.3-159635.6" + process $proc$libresoc.v:159626$8632 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:157711.5-157711.29" + attribute \src "libresoc.v:159627.5-159627.29" switch \initial - attribute \src "libresoc.v:157711.9-157711.17" + attribute \src "libresoc.v:159627.9-159627.17" case 1'1 case end @@ -329954,14 +332565,14 @@ module \pimem sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:157720.3-157728.6" - process $proc$libresoc.v:157720$8588 + attribute \src "libresoc.v:159636.3-159644.6" + process $proc$libresoc.v:159636$8633 assign { } { } assign { } { } - assign $0\busy_delay$next[0:0]$8589 $1\busy_delay$next[0:0]$8590 - attribute \src "libresoc.v:157721.5-157721.29" + assign $0\busy_delay$next[0:0]$8634 $1\busy_delay$next[0:0]$8635 + attribute \src "libresoc.v:159637.5-159637.29" switch \initial - attribute \src "libresoc.v:157721.9-157721.17" + attribute \src "libresoc.v:159637.9-159637.17" case 1'1 case end @@ -329970,21 +332581,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_delay$next[0:0]$8590 1'0 + assign $1\busy_delay$next[0:0]$8635 1'0 case - assign $1\busy_delay$next[0:0]$8590 \ldst_port0_busy_o + assign $1\busy_delay$next[0:0]$8635 \ldst_port0_busy_o end sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8589 + update \busy_delay$next $0\busy_delay$next[0:0]$8634 end - attribute \src "libresoc.v:157729.3-157738.6" - process $proc$libresoc.v:157729$8591 + attribute \src "libresoc.v:159645.3-159654.6" + process $proc$libresoc.v:159645$8636 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:157730.5-157730.29" + attribute \src "libresoc.v:159646.5-159646.29" switch \initial - attribute \src "libresoc.v:157730.9-157730.17" + attribute \src "libresoc.v:159646.9-159646.17" case 1'1 case end @@ -330000,15 +332611,15 @@ module \pimem sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:157739.3-157754.6" - process $proc$libresoc.v:157739$8592 + attribute \src "libresoc.v:159655.3-159670.6" + process $proc$libresoc.v:159655$8637 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:157740.5-157740.29" + attribute \src "libresoc.v:159656.5-159656.29" switch \initial - attribute \src "libresoc.v:157740.9-157740.17" + attribute \src "libresoc.v:159656.9-159656.17" case 1'1 case end @@ -330033,15 +332644,15 @@ module \pimem sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:157755.3-157770.6" - process $proc$libresoc.v:157755$8593 + attribute \src "libresoc.v:159671.3-159686.6" + process $proc$libresoc.v:159671$8638 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:157756.5-157756.29" + attribute \src "libresoc.v:159672.5-159672.29" switch \initial - attribute \src "libresoc.v:157756.9-157756.17" + attribute \src "libresoc.v:159672.9-159672.17" case 1'1 case end @@ -330066,15 +332677,15 @@ module \pimem sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:157771.3-157796.6" - process $proc$libresoc.v:157771$8594 + attribute \src "libresoc.v:159687.3-159712.6" + process $proc$libresoc.v:159687$8639 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:157772.5-157772.29" + attribute \src "libresoc.v:159688.5-159688.29" switch \initial - attribute \src "libresoc.v:157772.9-157772.17" + attribute \src "libresoc.v:159688.9-159688.17" case 1'1 case end @@ -330117,15 +332728,15 @@ module \pimem sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:157797.3-157822.6" - process $proc$libresoc.v:157797$8595 + attribute \src "libresoc.v:159713.3-159738.6" + process $proc$libresoc.v:159713$8640 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:157798.5-157798.29" + attribute \src "libresoc.v:159714.5-159714.29" switch \initial - attribute \src "libresoc.v:157798.9-157798.17" + attribute \src "libresoc.v:159714.9-159714.17" case 1'1 case end @@ -330168,15 +332779,15 @@ module \pimem sync always update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:157823.3-157848.6" - process $proc$libresoc.v:157823$8596 + attribute \src "libresoc.v:159739.3-159764.6" + process $proc$libresoc.v:159739$8641 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:157824.5-157824.29" + attribute \src "libresoc.v:159740.5-159740.29" switch \initial - attribute \src "libresoc.v:157824.9-157824.17" + attribute \src "libresoc.v:159740.9-159740.17" case 1'1 case end @@ -330219,15 +332830,15 @@ module \pimem sync always update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:157849.3-157879.6" - process $proc$libresoc.v:157849$8597 + attribute \src "libresoc.v:159765.3-159795.6" + process $proc$libresoc.v:159765$8642 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:157850.5-157850.29" + attribute \src "libresoc.v:159766.5-159766.29" switch \initial - attribute \src "libresoc.v:157850.9-157850.17" + attribute \src "libresoc.v:159766.9-159766.17" case 1'1 case end @@ -330279,15 +332890,15 @@ module \pimem sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:157880.3-157895.6" - process $proc$libresoc.v:157880$8598 + attribute \src "libresoc.v:159796.3-159811.6" + process $proc$libresoc.v:159796$8643 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:157881.5-157881.29" + attribute \src "libresoc.v:159797.5-159797.29" switch \initial - attribute \src "libresoc.v:157881.9-157881.17" + attribute \src "libresoc.v:159797.9-159797.17" case 1'1 case end @@ -330312,14 +332923,14 @@ module \pimem sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:157896.3-157905.6" - process $proc$libresoc.v:157896$8599 + attribute \src "libresoc.v:159812.3-159821.6" + process $proc$libresoc.v:159812$8644 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:157897.5-157897.29" + attribute \src "libresoc.v:159813.5-159813.29" switch \initial - attribute \src "libresoc.v:157897.9-157897.17" + attribute \src "libresoc.v:159813.9-159813.17" case 1'1 case end @@ -330335,14 +332946,14 @@ module \pimem sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:157906.3-157915.6" - process $proc$libresoc.v:157906$8600 + attribute \src "libresoc.v:159822.3-159831.6" + process $proc$libresoc.v:159822$8645 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:157907.5-157907.29" + attribute \src "libresoc.v:159823.5-159823.29" switch \initial - attribute \src "libresoc.v:157907.9-157907.17" + attribute \src "libresoc.v:159823.9-159823.17" case 1'1 case end @@ -330358,14 +332969,14 @@ module \pimem sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:157916.3-157925.6" - process $proc$libresoc.v:157916$8601 + attribute \src "libresoc.v:159832.3-159841.6" + process $proc$libresoc.v:159832$8646 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:157917.5-157917.29" + attribute \src "libresoc.v:159833.5-159833.29" switch \initial - attribute \src "libresoc.v:157917.9-157917.17" + attribute \src "libresoc.v:159833.9-159833.17" case 1'1 case end @@ -330381,14 +332992,14 @@ module \pimem sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:157926.3-157935.6" - process $proc$libresoc.v:157926$8602 + attribute \src "libresoc.v:159842.3-159851.6" + process $proc$libresoc.v:159842$8647 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:157927.5-157927.29" + attribute \src "libresoc.v:159843.5-159843.29" switch \initial - attribute \src "libresoc.v:157927.9-157927.17" + attribute \src "libresoc.v:159843.9-159843.17" case 1'1 case end @@ -330404,14 +333015,14 @@ module \pimem sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:157936.3-157945.6" - process $proc$libresoc.v:157936$8603 + attribute \src "libresoc.v:159852.3-159861.6" + process $proc$libresoc.v:159852$8648 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:157937.5-157937.29" + attribute \src "libresoc.v:159853.5-159853.29" switch \initial - attribute \src "libresoc.v:157937.9-157937.17" + attribute \src "libresoc.v:159853.9-159853.17" case 1'1 case end @@ -330427,14 +333038,14 @@ module \pimem sync always update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:157946.3-157955.6" - process $proc$libresoc.v:157946$8604 + attribute \src "libresoc.v:159862.3-159871.6" + process $proc$libresoc.v:159862$8649 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:157947.5-157947.29" + attribute \src "libresoc.v:159863.5-159863.29" switch \initial - attribute \src "libresoc.v:157947.9-157947.17" + attribute \src "libresoc.v:159863.9-159863.17" case 1'1 case end @@ -330450,14 +333061,14 @@ module \pimem sync always update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:157956.3-157975.6" - process $proc$libresoc.v:157956$8605 + attribute \src "libresoc.v:159872.3-159891.6" + process $proc$libresoc.v:159872$8650 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:157957.5-157957.29" + attribute \src "libresoc.v:159873.5-159873.29" switch \initial - attribute \src "libresoc.v:157957.9-157957.17" + attribute \src "libresoc.v:159873.9-159873.17" case 1'1 case end @@ -330486,15 +333097,15 @@ module \pimem sync always update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:157976.3-158014.6" - process $proc$libresoc.v:157976$8606 + attribute \src "libresoc.v:159892.3-159930.6" + process $proc$libresoc.v:159892$8651 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$8607 $5\fsm_state$next[1:0]$8612 - attribute \src "libresoc.v:157977.5-157977.29" + assign $0\fsm_state$next[1:0]$8652 $5\fsm_state$next[1:0]$8657 + attribute \src "libresoc.v:159893.5-159893.29" switch \initial - attribute \src "libresoc.v:157977.9-157977.17" + attribute \src "libresoc.v:159893.9-159893.17" case 1'1 case end @@ -330503,65 +333114,65 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$8608 $2\fsm_state$next[1:0]$8609 + assign $1\fsm_state$next[1:0]$8653 $2\fsm_state$next[1:0]$8654 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$8609 2'01 + assign $2\fsm_state$next[1:0]$8654 2'01 case - assign $2\fsm_state$next[1:0]$8609 \fsm_state + assign $2\fsm_state$next[1:0]$8654 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$8608 $3\fsm_state$next[1:0]$8610 + assign $1\fsm_state$next[1:0]$8653 $3\fsm_state$next[1:0]$8655 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[1:0]$8610 2'10 + assign $3\fsm_state$next[1:0]$8655 2'10 case - assign $3\fsm_state$next[1:0]$8610 \fsm_state + assign $3\fsm_state$next[1:0]$8655 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$8608 $4\fsm_state$next[1:0]$8611 + assign $1\fsm_state$next[1:0]$8653 $4\fsm_state$next[1:0]$8656 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[1:0]$8611 2'00 + assign $4\fsm_state$next[1:0]$8656 2'00 case - assign $4\fsm_state$next[1:0]$8611 \fsm_state + assign $4\fsm_state$next[1:0]$8656 \fsm_state end case - assign $1\fsm_state$next[1:0]$8608 \fsm_state + assign $1\fsm_state$next[1:0]$8653 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$8612 2'00 + assign $5\fsm_state$next[1:0]$8657 2'00 case - assign $5\fsm_state$next[1:0]$8612 $1\fsm_state$next[1:0]$8608 + assign $5\fsm_state$next[1:0]$8657 $1\fsm_state$next[1:0]$8653 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8607 + update \fsm_state$next $0\fsm_state$next[1:0]$8652 end - attribute \src "libresoc.v:158015.3-158024.6" - process $proc$libresoc.v:158015$8613 + attribute \src "libresoc.v:159931.3-159940.6" + process $proc$libresoc.v:159931$8658 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:158016.5-158016.29" + attribute \src "libresoc.v:159932.5-159932.29" switch \initial - attribute \src "libresoc.v:158016.9-158016.17" + attribute \src "libresoc.v:159932.9-159932.17" case 1'1 case end @@ -330577,14 +333188,14 @@ module \pimem sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:158025.3-158033.6" - process $proc$libresoc.v:158025$8614 + attribute \src "libresoc.v:159941.3-159949.6" + process $proc$libresoc.v:159941$8659 assign { } { } assign { } { } - assign $0\lsui_active_dly$next[0:0]$8615 $1\lsui_active_dly$next[0:0]$8616 - attribute \src "libresoc.v:158026.5-158026.29" + assign $0\lsui_active_dly$next[0:0]$8660 $1\lsui_active_dly$next[0:0]$8661 + attribute \src "libresoc.v:159942.5-159942.29" switch \initial - attribute \src "libresoc.v:158026.9-158026.17" + attribute \src "libresoc.v:159942.9-159942.17" case 1'1 case end @@ -330593,21 +333204,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsui_active_dly$next[0:0]$8616 1'0 + assign $1\lsui_active_dly$next[0:0]$8661 1'0 case - assign $1\lsui_active_dly$next[0:0]$8616 \lsui_active + assign $1\lsui_active_dly$next[0:0]$8661 \lsui_active end sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8615 + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8660 end - attribute \src "libresoc.v:158034.3-158043.6" - process $proc$libresoc.v:158034$8617 + attribute \src "libresoc.v:159950.3-159959.6" + process $proc$libresoc.v:159950$8662 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:158035.5-158035.29" + attribute \src "libresoc.v:159951.5-159951.29" switch \initial - attribute \src "libresoc.v:158035.9-158035.17" + attribute \src "libresoc.v:159951.9-159951.17" case 1'1 case end @@ -330623,14 +333234,14 @@ module \pimem sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:158044.3-158053.6" - process $proc$libresoc.v:158044$8618 + attribute \src "libresoc.v:159960.3-159969.6" + process $proc$libresoc.v:159960$8663 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:158045.5-158045.29" + attribute \src "libresoc.v:159961.5-159961.29" switch \initial - attribute \src "libresoc.v:158045.9-158045.17" + attribute \src "libresoc.v:159961.9-159961.17" case 1'1 case end @@ -330646,15 +333257,15 @@ module \pimem sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end - attribute \src "libresoc.v:158054.3-158069.6" - process $proc$libresoc.v:158054$8619 + attribute \src "libresoc.v:159970.3-159985.6" + process $proc$libresoc.v:159970$8664 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:158055.5-158055.29" + attribute \src "libresoc.v:159971.5-159971.29" switch \initial - attribute \src "libresoc.v:158055.9-158055.17" + attribute \src "libresoc.v:159971.9-159971.17" case 1'1 case end @@ -330679,16 +333290,16 @@ module \pimem sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:158070.3-158105.6" - process $proc$libresoc.v:158070$8620 + attribute \src "libresoc.v:159986.3-160021.6" + process $proc$libresoc.v:159986$8665 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8621 $6\adrok_l_s_addr_acked$next[0:0]$8627 - attribute \src "libresoc.v:158071.5-158071.29" + assign $0\adrok_l_s_addr_acked$next[0:0]$8666 $6\adrok_l_s_addr_acked$next[0:0]$8672 + attribute \src "libresoc.v:159987.5-159987.29" switch \initial - attribute \src "libresoc.v:158071.9-158071.17" + attribute \src "libresoc.v:159987.9-159987.17" case 1'1 case end @@ -330697,67 +333308,67 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8622 $2\adrok_l_s_addr_acked$next[0:0]$8623 + assign $1\adrok_l_s_addr_acked$next[0:0]$8667 $2\adrok_l_s_addr_acked$next[0:0]$8668 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8623 1'1 + assign $2\adrok_l_s_addr_acked$next[0:0]$8668 1'1 case - assign $2\adrok_l_s_addr_acked$next[0:0]$8623 1'0 + assign $2\adrok_l_s_addr_acked$next[0:0]$8668 1'0 end case - assign $1\adrok_l_s_addr_acked$next[0:0]$8622 1'0 + assign $1\adrok_l_s_addr_acked$next[0:0]$8667 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8624 $4\adrok_l_s_addr_acked$next[0:0]$8625 + assign $3\adrok_l_s_addr_acked$next[0:0]$8669 $4\adrok_l_s_addr_acked$next[0:0]$8670 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8625 $5\adrok_l_s_addr_acked$next[0:0]$8626 + assign $4\adrok_l_s_addr_acked$next[0:0]$8670 $5\adrok_l_s_addr_acked$next[0:0]$8671 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$8626 1'1 + assign $5\adrok_l_s_addr_acked$next[0:0]$8671 1'1 case - assign $5\adrok_l_s_addr_acked$next[0:0]$8626 $1\adrok_l_s_addr_acked$next[0:0]$8622 + assign $5\adrok_l_s_addr_acked$next[0:0]$8671 $1\adrok_l_s_addr_acked$next[0:0]$8667 end case - assign $4\adrok_l_s_addr_acked$next[0:0]$8625 $1\adrok_l_s_addr_acked$next[0:0]$8622 + assign $4\adrok_l_s_addr_acked$next[0:0]$8670 $1\adrok_l_s_addr_acked$next[0:0]$8667 end case - assign $3\adrok_l_s_addr_acked$next[0:0]$8624 $1\adrok_l_s_addr_acked$next[0:0]$8622 + assign $3\adrok_l_s_addr_acked$next[0:0]$8669 $1\adrok_l_s_addr_acked$next[0:0]$8667 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8627 1'0 + assign $6\adrok_l_s_addr_acked$next[0:0]$8672 1'0 case - assign $6\adrok_l_s_addr_acked$next[0:0]$8627 $3\adrok_l_s_addr_acked$next[0:0]$8624 + assign $6\adrok_l_s_addr_acked$next[0:0]$8672 $3\adrok_l_s_addr_acked$next[0:0]$8669 end sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8621 + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8666 end - attribute \src "libresoc.v:158106.3-158121.6" - process $proc$libresoc.v:158106$8628 + attribute \src "libresoc.v:160022.3-160037.6" + process $proc$libresoc.v:160022$8673 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:158107.5-158107.29" + attribute \src "libresoc.v:160023.5-160023.29" switch \initial - attribute \src "libresoc.v:158107.9-158107.17" + attribute \src "libresoc.v:160023.9-160023.17" case 1'1 case end @@ -330782,47 +333393,47 @@ module \pimem sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$9 $not$libresoc.v:157575$8532_Y - connect \$11 $and$libresoc.v:157576$8533_Y - connect \$13 $not$libresoc.v:157577$8534_Y - connect \$15 $and$libresoc.v:157578$8535_Y - connect \$17 $not$libresoc.v:157579$8536_Y - connect \$1 $and$libresoc.v:157580$8537_Y - connect \$19 $and$libresoc.v:157581$8538_Y - connect \$21 $pos$libresoc.v:157582$8540_Y - connect \$23 $pos$libresoc.v:157583$8542_Y - connect \$25 $and$libresoc.v:157584$8543_Y - connect \$27 $and$libresoc.v:157585$8544_Y - connect \$29 $and$libresoc.v:157586$8545_Y - connect \$31 $and$libresoc.v:157587$8546_Y - connect \$33 $and$libresoc.v:157588$8547_Y - connect \$35 $not$libresoc.v:157589$8548_Y - connect \$38 $or$libresoc.v:157590$8549_Y - connect \$3 $or$libresoc.v:157591$8550_Y - connect \$37 $not$libresoc.v:157592$8551_Y - connect \$42 $and$libresoc.v:157593$8552_Y - connect \$44 $mul$libresoc.v:157594$8553_Y - connect \$46 $sshr$libresoc.v:157595$8554_Y - connect \$48 $and$libresoc.v:157596$8555_Y - connect \$50 $and$libresoc.v:157597$8556_Y - connect \$52 $not$libresoc.v:157598$8557_Y - connect \$54 $and$libresoc.v:157599$8558_Y - connect \$57 $mul$libresoc.v:157600$8559_Y - connect \$5 $not$libresoc.v:157601$8560_Y - connect \$59 $sshl$libresoc.v:157602$8561_Y - connect \$61 $and$libresoc.v:157603$8562_Y - connect \$63 $or$libresoc.v:157604$8563_Y - connect \$65 $and$libresoc.v:157605$8564_Y - connect \$67 $or$libresoc.v:157606$8565_Y - connect \$69 $and$libresoc.v:157607$8566_Y - connect \$71 $not$libresoc.v:157608$8567_Y - connect \$73 $not$libresoc.v:157609$8568_Y - connect \$75 $not$libresoc.v:157610$8569_Y - connect \$77 $and$libresoc.v:157611$8570_Y - connect \$7 $and$libresoc.v:157612$8571_Y - connect \$79 $not$libresoc.v:157613$8572_Y - connect \$81 $not$libresoc.v:157614$8573_Y - connect \$83 $and$libresoc.v:157615$8574_Y + connect \$9 $not$libresoc.v:159491$8577_Y + connect \$11 $and$libresoc.v:159492$8578_Y + connect \$13 $not$libresoc.v:159493$8579_Y + connect \$15 $and$libresoc.v:159494$8580_Y + connect \$17 $not$libresoc.v:159495$8581_Y + connect \$1 $and$libresoc.v:159496$8582_Y + connect \$19 $and$libresoc.v:159497$8583_Y + connect \$21 $pos$libresoc.v:159498$8585_Y + connect \$23 $pos$libresoc.v:159499$8587_Y + connect \$25 $and$libresoc.v:159500$8588_Y + connect \$27 $and$libresoc.v:159501$8589_Y + connect \$29 $and$libresoc.v:159502$8590_Y + connect \$31 $and$libresoc.v:159503$8591_Y + connect \$33 $and$libresoc.v:159504$8592_Y + connect \$35 $not$libresoc.v:159505$8593_Y + connect \$38 $or$libresoc.v:159506$8594_Y + connect \$3 $or$libresoc.v:159507$8595_Y + connect \$37 $not$libresoc.v:159508$8596_Y + connect \$42 $and$libresoc.v:159509$8597_Y + connect \$44 $mul$libresoc.v:159510$8598_Y + connect \$46 $sshr$libresoc.v:159511$8599_Y + connect \$48 $and$libresoc.v:159512$8600_Y + connect \$50 $and$libresoc.v:159513$8601_Y + connect \$52 $not$libresoc.v:159514$8602_Y + connect \$54 $and$libresoc.v:159515$8603_Y + connect \$57 $mul$libresoc.v:159516$8604_Y + connect \$5 $not$libresoc.v:159517$8605_Y + connect \$59 $sshl$libresoc.v:159518$8606_Y + connect \$61 $and$libresoc.v:159519$8607_Y + connect \$63 $or$libresoc.v:159520$8608_Y + connect \$65 $and$libresoc.v:159521$8609_Y + connect \$67 $or$libresoc.v:159522$8610_Y + connect \$69 $and$libresoc.v:159523$8611_Y + connect \$71 $not$libresoc.v:159524$8612_Y + connect \$73 $not$libresoc.v:159525$8613_Y + connect \$75 $not$libresoc.v:159526$8614_Y + connect \$77 $and$libresoc.v:159527$8615_Y + connect \$7 $and$libresoc.v:159528$8616_Y + connect \$79 $not$libresoc.v:159529$8617_Y + connect \$81 $not$libresoc.v:159530$8618_Y + connect \$83 $and$libresoc.v:159531$8619_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise @@ -330845,116 +333456,116 @@ module \pimem connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:158147.1-158917.10" +attribute \src "libresoc.v:160063.1-160843.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe - attribute \src "libresoc.v:158880.3-158898.6" - wire width 4 $0\cr_a$6$next[3:0]$8684 - attribute \src "libresoc.v:158744.3-158745.31" - wire width 4 $0\cr_a$6[3:0]$8640 - attribute \src "libresoc.v:158161.13-158161.28" - wire width 4 $0\cr_a$6[3:0]$8690 - attribute \src "libresoc.v:158880.3-158898.6" - wire $0\cr_a_ok$next[0:0]$8683 - attribute \src "libresoc.v:158746.3-158747.31" + attribute \src "libresoc.v:160806.3-160824.6" + wire width 4 $0\cr_a$6$next[3:0]$8729 + attribute \src "libresoc.v:160670.3-160671.31" + wire width 4 $0\cr_a$6[3:0]$8685 + attribute \src "libresoc.v:160077.13-160077.28" + wire width 4 $0\cr_a$6[3:0]$8735 + attribute \src "libresoc.v:160806.3-160824.6" + wire $0\cr_a_ok$next[0:0]$8728 + attribute \src "libresoc.v:160672.3-160673.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:158827.3-158841.6" - wire width 13 $0\cr_op__fn_unit$3$next[12:0]$8664 - attribute \src "libresoc.v:158758.3-158759.51" - wire width 13 $0\cr_op__fn_unit$3[12:0]$8650 - attribute \src "libresoc.v:158223.14-158223.43" - wire width 13 $0\cr_op__fn_unit$3[12:0]$8693 - attribute \src "libresoc.v:158827.3-158841.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$8665 - attribute \src "libresoc.v:158760.3-158761.45" - wire width 32 $0\cr_op__insn$4[31:0]$8652 - attribute \src "libresoc.v:158232.14-158232.37" - wire width 32 $0\cr_op__insn$4[31:0]$8695 - attribute \src "libresoc.v:158827.3-158841.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$8666 - attribute \src "libresoc.v:158756.3-158757.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$8648 - attribute \src "libresoc.v:158463.13-158463.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$8697 - attribute \src "libresoc.v:158861.3-158879.6" - wire width 32 $0\full_cr$5$next[31:0]$8677 - attribute \src "libresoc.v:158748.3-158749.37" - wire width 32 $0\full_cr$5[31:0]$8643 - attribute \src "libresoc.v:158472.14-158472.33" - wire width 32 $0\full_cr$5[31:0]$8699 - attribute \src "libresoc.v:158861.3-158879.6" - wire $0\full_cr_ok$next[0:0]$8678 - attribute \src "libresoc.v:158750.3-158751.37" + attribute \src "libresoc.v:160753.3-160767.6" + wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8709 + attribute \src "libresoc.v:160684.3-160685.51" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8695 + attribute \src "libresoc.v:160142.14-160142.43" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8738 + attribute \src "libresoc.v:160753.3-160767.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8710 + attribute \src "libresoc.v:160686.3-160687.45" + wire width 32 $0\cr_op__insn$4[31:0]$8697 + attribute \src "libresoc.v:160151.14-160151.37" + wire width 32 $0\cr_op__insn$4[31:0]$8740 + attribute \src "libresoc.v:160753.3-160767.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8711 + attribute \src "libresoc.v:160682.3-160683.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8693 + attribute \src "libresoc.v:160385.13-160385.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8742 + attribute \src "libresoc.v:160787.3-160805.6" + wire width 32 $0\full_cr$5$next[31:0]$8722 + attribute \src "libresoc.v:160674.3-160675.37" + wire width 32 $0\full_cr$5[31:0]$8688 + attribute \src "libresoc.v:160394.14-160394.33" + wire width 32 $0\full_cr$5[31:0]$8744 + attribute \src "libresoc.v:160787.3-160805.6" + wire $0\full_cr_ok$next[0:0]$8723 + attribute \src "libresoc.v:160676.3-160677.37" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:158148.7-158148.20" + attribute \src "libresoc.v:160064.7-160064.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158814.3-158826.6" - wire width 2 $0\muxid$1$next[1:0]$8661 - attribute \src "libresoc.v:158762.3-158763.33" - wire width 2 $0\muxid$1[1:0]$8654 - attribute \src "libresoc.v:158702.13-158702.29" - wire width 2 $0\muxid$1[1:0]$8702 - attribute \src "libresoc.v:158842.3-158860.6" - wire width 64 $0\o$next[63:0]$8671 - attribute \src "libresoc.v:158752.3-158753.19" + attribute \src "libresoc.v:160740.3-160752.6" + wire width 2 $0\muxid$1$next[1:0]$8706 + attribute \src "libresoc.v:160688.3-160689.33" + wire width 2 $0\muxid$1[1:0]$8699 + attribute \src "libresoc.v:160628.13-160628.29" + wire width 2 $0\muxid$1[1:0]$8747 + attribute \src "libresoc.v:160768.3-160786.6" + wire width 64 $0\o$next[63:0]$8716 + attribute \src "libresoc.v:160678.3-160679.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:158842.3-158860.6" - wire $0\o_ok$next[0:0]$8672 - attribute \src "libresoc.v:158754.3-158755.25" + attribute \src "libresoc.v:160768.3-160786.6" + wire $0\o_ok$next[0:0]$8717 + attribute \src "libresoc.v:160680.3-160681.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:158796.3-158813.6" - wire $0\r_busy$next[0:0]$8657 - attribute \src "libresoc.v:158764.3-158765.29" + attribute \src "libresoc.v:160722.3-160739.6" + wire $0\r_busy$next[0:0]$8702 + attribute \src "libresoc.v:160690.3-160691.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:158880.3-158898.6" - wire width 4 $1\cr_a$6$next[3:0]$8686 - attribute \src "libresoc.v:158880.3-158898.6" - wire $1\cr_a_ok$next[0:0]$8685 - attribute \src "libresoc.v:158166.7-158166.21" + attribute \src "libresoc.v:160806.3-160824.6" + wire width 4 $1\cr_a$6$next[3:0]$8731 + attribute \src "libresoc.v:160806.3-160824.6" + wire $1\cr_a_ok$next[0:0]$8730 + attribute \src "libresoc.v:160082.7-160082.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:158827.3-158841.6" - wire width 13 $1\cr_op__fn_unit$3$next[12:0]$8667 - attribute \src "libresoc.v:158827.3-158841.6" - wire width 32 $1\cr_op__insn$4$next[31:0]$8668 - attribute \src "libresoc.v:158827.3-158841.6" - wire width 7 $1\cr_op__insn_type$2$next[6:0]$8669 - attribute \src "libresoc.v:158861.3-158879.6" - wire width 32 $1\full_cr$5$next[31:0]$8679 - attribute \src "libresoc.v:158861.3-158879.6" - wire $1\full_cr_ok$next[0:0]$8680 - attribute \src "libresoc.v:158477.7-158477.24" + attribute \src "libresoc.v:160753.3-160767.6" + wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8712 + attribute \src "libresoc.v:160753.3-160767.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8713 + attribute \src "libresoc.v:160753.3-160767.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8714 + attribute \src "libresoc.v:160787.3-160805.6" + wire width 32 $1\full_cr$5$next[31:0]$8724 + attribute \src "libresoc.v:160787.3-160805.6" + wire $1\full_cr_ok$next[0:0]$8725 + attribute \src "libresoc.v:160399.7-160399.24" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:158814.3-158826.6" - wire width 2 $1\muxid$1$next[1:0]$8662 - attribute \src "libresoc.v:158842.3-158860.6" - wire width 64 $1\o$next[63:0]$8673 - attribute \src "libresoc.v:158715.14-158715.38" + attribute \src "libresoc.v:160740.3-160752.6" + wire width 2 $1\muxid$1$next[1:0]$8707 + attribute \src "libresoc.v:160768.3-160786.6" + wire width 64 $1\o$next[63:0]$8718 + attribute \src "libresoc.v:160641.14-160641.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:158842.3-158860.6" - wire $1\o_ok$next[0:0]$8674 - attribute \src "libresoc.v:158722.7-158722.18" + attribute \src "libresoc.v:160768.3-160786.6" + wire $1\o_ok$next[0:0]$8719 + attribute \src "libresoc.v:160648.7-160648.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:158796.3-158813.6" - wire $1\r_busy$next[0:0]$8658 - attribute \src "libresoc.v:158736.7-158736.20" + attribute \src "libresoc.v:160722.3-160739.6" + wire $1\r_busy$next[0:0]$8703 + attribute \src "libresoc.v:160662.7-160662.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:158880.3-158898.6" - wire $2\cr_a_ok$next[0:0]$8687 - attribute \src "libresoc.v:158861.3-158879.6" - wire $2\full_cr_ok$next[0:0]$8681 - attribute \src "libresoc.v:158842.3-158860.6" - wire $2\o_ok$next[0:0]$8675 - attribute \src "libresoc.v:158796.3-158813.6" - wire $2\r_busy$next[0:0]$8659 - attribute \src "libresoc.v:158743.18-158743.118" - wire $and$libresoc.v:158743$8638_Y + attribute \src "libresoc.v:160806.3-160824.6" + wire $2\cr_a_ok$next[0:0]$8732 + attribute \src "libresoc.v:160787.3-160805.6" + wire $2\full_cr_ok$next[0:0]$8726 + attribute \src "libresoc.v:160768.3-160786.6" + wire $2\o_ok$next[0:0]$8720 + attribute \src "libresoc.v:160722.3-160739.6" + wire $2\r_busy$next[0:0]$8704 + attribute \src "libresoc.v:160669.18-160669.118" + wire $and$libresoc.v:160669$8683_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a @@ -330975,55 +333586,58 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 13 \cr_c attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \cr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \cr_op__fn_unit$18 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \cr_op__fn_unit$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 18 \cr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \cr_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 18 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \cr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 7 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -331106,6 +333720,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \cr_op__insn_type attribute \enum_base_type "MicrOp" @@ -331182,6 +333797,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$17 attribute \enum_base_type "MicrOp" @@ -331258,6 +333874,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -331276,7 +333893,7 @@ module \pipe wire \full_cr_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \full_cr_ok$next - attribute \src "libresoc.v:158148.7-158148.15" + attribute \src "libresoc.v:160064.7-160064.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a @@ -331289,37 +333906,39 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_c attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_cr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_cr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_cr_op__fn_unit$9 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_cr_op__fn_unit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -331398,6 +334017,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_cr_op__insn_type attribute \enum_base_type "MicrOp" @@ -331474,6 +334094,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_cr_op__insn_type$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -331537,7 +334158,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:158743$8638 + cell $and $and$libresoc.v:160669$8683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331545,10 +334166,10 @@ module \pipe parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:158743$8638_Y + connect \Y $and$libresoc.v:160669$8683_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:158766.12-158787.4" + attribute \src "libresoc.v:160692.12-160713.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 @@ -331572,199 +334193,199 @@ module \pipe connect \rb \main_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:158788.9-158791.4" + attribute \src "libresoc.v:160714.9-160717.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:158792.9-158795.4" + attribute \src "libresoc.v:160718.9-160721.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:158148.7-158148.20" - process $proc$libresoc.v:158148$8688 + attribute \src "libresoc.v:160064.7-160064.20" + process $proc$libresoc.v:160064$8733 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158161.13-158161.28" - process $proc$libresoc.v:158161$8689 + attribute \src "libresoc.v:160077.13-160077.28" + process $proc$libresoc.v:160077$8734 assign { } { } - assign $0\cr_a$6[3:0]$8690 4'0000 + assign $0\cr_a$6[3:0]$8735 4'0000 sync always sync init - update \cr_a$6 $0\cr_a$6[3:0]$8690 + update \cr_a$6 $0\cr_a$6[3:0]$8735 end - attribute \src "libresoc.v:158166.7-158166.21" - process $proc$libresoc.v:158166$8691 + attribute \src "libresoc.v:160082.7-160082.21" + process $proc$libresoc.v:160082$8736 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:158223.14-158223.43" - process $proc$libresoc.v:158223$8692 + attribute \src "libresoc.v:160142.14-160142.43" + process $proc$libresoc.v:160142$8737 assign { } { } - assign $0\cr_op__fn_unit$3[12:0]$8693 13'0000000000000 + assign $0\cr_op__fn_unit$3[13:0]$8738 14'00000000000000 sync always sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8693 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8738 end - attribute \src "libresoc.v:158232.14-158232.37" - process $proc$libresoc.v:158232$8694 + attribute \src "libresoc.v:160151.14-160151.37" + process $proc$libresoc.v:160151$8739 assign { } { } - assign $0\cr_op__insn$4[31:0]$8695 0 + assign $0\cr_op__insn$4[31:0]$8740 0 sync always sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8695 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8740 end - attribute \src "libresoc.v:158463.13-158463.41" - process $proc$libresoc.v:158463$8696 + attribute \src "libresoc.v:160385.13-160385.41" + process $proc$libresoc.v:160385$8741 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8697 7'0000000 + assign $0\cr_op__insn_type$2[6:0]$8742 7'0000000 sync always sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8697 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8742 end - attribute \src "libresoc.v:158472.14-158472.33" - process $proc$libresoc.v:158472$8698 + attribute \src "libresoc.v:160394.14-160394.33" + process $proc$libresoc.v:160394$8743 assign { } { } - assign $0\full_cr$5[31:0]$8699 0 + assign $0\full_cr$5[31:0]$8744 0 sync always sync init - update \full_cr$5 $0\full_cr$5[31:0]$8699 + update \full_cr$5 $0\full_cr$5[31:0]$8744 end - attribute \src "libresoc.v:158477.7-158477.24" - process $proc$libresoc.v:158477$8700 + attribute \src "libresoc.v:160399.7-160399.24" + process $proc$libresoc.v:160399$8745 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:158702.13-158702.29" - process $proc$libresoc.v:158702$8701 + attribute \src "libresoc.v:160628.13-160628.29" + process $proc$libresoc.v:160628$8746 assign { } { } - assign $0\muxid$1[1:0]$8702 2'00 + assign $0\muxid$1[1:0]$8747 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8702 + update \muxid$1 $0\muxid$1[1:0]$8747 end - attribute \src "libresoc.v:158715.14-158715.38" - process $proc$libresoc.v:158715$8703 + attribute \src "libresoc.v:160641.14-160641.38" + process $proc$libresoc.v:160641$8748 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:158722.7-158722.18" - process $proc$libresoc.v:158722$8704 + attribute \src "libresoc.v:160648.7-160648.18" + process $proc$libresoc.v:160648$8749 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:158736.7-158736.20" - process $proc$libresoc.v:158736$8705 + attribute \src "libresoc.v:160662.7-160662.20" + process $proc$libresoc.v:160662$8750 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:158744.3-158745.31" - process $proc$libresoc.v:158744$8639 + attribute \src "libresoc.v:160670.3-160671.31" + process $proc$libresoc.v:160670$8684 assign { } { } - assign $0\cr_a$6[3:0]$8640 \cr_a$6$next + assign $0\cr_a$6[3:0]$8685 \cr_a$6$next sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8640 + update \cr_a$6 $0\cr_a$6[3:0]$8685 end - attribute \src "libresoc.v:158746.3-158747.31" - process $proc$libresoc.v:158746$8641 + attribute \src "libresoc.v:160672.3-160673.31" + process $proc$libresoc.v:160672$8686 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:158748.3-158749.37" - process $proc$libresoc.v:158748$8642 + attribute \src "libresoc.v:160674.3-160675.37" + process $proc$libresoc.v:160674$8687 assign { } { } - assign $0\full_cr$5[31:0]$8643 \full_cr$5$next + assign $0\full_cr$5[31:0]$8688 \full_cr$5$next sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8643 + update \full_cr$5 $0\full_cr$5[31:0]$8688 end - attribute \src "libresoc.v:158750.3-158751.37" - process $proc$libresoc.v:158750$8644 + attribute \src "libresoc.v:160676.3-160677.37" + process $proc$libresoc.v:160676$8689 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:158752.3-158753.19" - process $proc$libresoc.v:158752$8645 + attribute \src "libresoc.v:160678.3-160679.19" + process $proc$libresoc.v:160678$8690 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:158754.3-158755.25" - process $proc$libresoc.v:158754$8646 + attribute \src "libresoc.v:160680.3-160681.25" + process $proc$libresoc.v:160680$8691 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:158756.3-158757.55" - process $proc$libresoc.v:158756$8647 + attribute \src "libresoc.v:160682.3-160683.55" + process $proc$libresoc.v:160682$8692 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8648 \cr_op__insn_type$2$next + assign $0\cr_op__insn_type$2[6:0]$8693 \cr_op__insn_type$2$next sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8648 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8693 end - attribute \src "libresoc.v:158758.3-158759.51" - process $proc$libresoc.v:158758$8649 + attribute \src "libresoc.v:160684.3-160685.51" + process $proc$libresoc.v:160684$8694 assign { } { } - assign $0\cr_op__fn_unit$3[12:0]$8650 \cr_op__fn_unit$3$next + assign $0\cr_op__fn_unit$3[13:0]$8695 \cr_op__fn_unit$3$next sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8650 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8695 end - attribute \src "libresoc.v:158760.3-158761.45" - process $proc$libresoc.v:158760$8651 + attribute \src "libresoc.v:160686.3-160687.45" + process $proc$libresoc.v:160686$8696 assign { } { } - assign $0\cr_op__insn$4[31:0]$8652 \cr_op__insn$4$next + assign $0\cr_op__insn$4[31:0]$8697 \cr_op__insn$4$next sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8652 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8697 end - attribute \src "libresoc.v:158762.3-158763.33" - process $proc$libresoc.v:158762$8653 + attribute \src "libresoc.v:160688.3-160689.33" + process $proc$libresoc.v:160688$8698 assign { } { } - assign $0\muxid$1[1:0]$8654 \muxid$1$next + assign $0\muxid$1[1:0]$8699 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8654 + update \muxid$1 $0\muxid$1[1:0]$8699 end - attribute \src "libresoc.v:158764.3-158765.29" - process $proc$libresoc.v:158764$8655 + attribute \src "libresoc.v:160690.3-160691.29" + process $proc$libresoc.v:160690$8700 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:158796.3-158813.6" - process $proc$libresoc.v:158796$8656 + attribute \src "libresoc.v:160722.3-160739.6" + process $proc$libresoc.v:160722$8701 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8657 $2\r_busy$next[0:0]$8659 - attribute \src "libresoc.v:158797.5-158797.29" + assign $0\r_busy$next[0:0]$8702 $2\r_busy$next[0:0]$8704 + attribute \src "libresoc.v:160723.5-160723.29" switch \initial - attribute \src "libresoc.v:158797.9-158797.17" + attribute \src "libresoc.v:160723.9-160723.17" case 1'1 case end @@ -331773,34 +334394,34 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8658 1'1 + assign $1\r_busy$next[0:0]$8703 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8658 1'0 + assign $1\r_busy$next[0:0]$8703 1'0 case - assign $1\r_busy$next[0:0]$8658 \r_busy + assign $1\r_busy$next[0:0]$8703 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8659 1'0 + assign $2\r_busy$next[0:0]$8704 1'0 case - assign $2\r_busy$next[0:0]$8659 $1\r_busy$next[0:0]$8658 + assign $2\r_busy$next[0:0]$8704 $1\r_busy$next[0:0]$8703 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8657 + update \r_busy$next $0\r_busy$next[0:0]$8702 end - attribute \src "libresoc.v:158814.3-158826.6" - process $proc$libresoc.v:158814$8660 + attribute \src "libresoc.v:160740.3-160752.6" + process $proc$libresoc.v:160740$8705 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8661 $1\muxid$1$next[1:0]$8662 - attribute \src "libresoc.v:158815.5-158815.29" + assign $0\muxid$1$next[1:0]$8706 $1\muxid$1$next[1:0]$8707 + attribute \src "libresoc.v:160741.5-160741.29" switch \initial - attribute \src "libresoc.v:158815.9-158815.17" + attribute \src "libresoc.v:160741.9-160741.17" case 1'1 case end @@ -331809,31 +334430,31 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8662 \muxid$16 + assign $1\muxid$1$next[1:0]$8707 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8662 \muxid$16 + assign $1\muxid$1$next[1:0]$8707 \muxid$16 case - assign $1\muxid$1$next[1:0]$8662 \muxid$1 + assign $1\muxid$1$next[1:0]$8707 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8661 + update \muxid$1$next $0\muxid$1$next[1:0]$8706 end - attribute \src "libresoc.v:158827.3-158841.6" - process $proc$libresoc.v:158827$8663 + attribute \src "libresoc.v:160753.3-160767.6" + process $proc$libresoc.v:160753$8708 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_op__fn_unit$3$next[12:0]$8664 $1\cr_op__fn_unit$3$next[12:0]$8667 - assign $0\cr_op__insn$4$next[31:0]$8665 $1\cr_op__insn$4$next[31:0]$8668 - assign $0\cr_op__insn_type$2$next[6:0]$8666 $1\cr_op__insn_type$2$next[6:0]$8669 - attribute \src "libresoc.v:158828.5-158828.29" + assign $0\cr_op__fn_unit$3$next[13:0]$8709 $1\cr_op__fn_unit$3$next[13:0]$8712 + assign $0\cr_op__insn$4$next[31:0]$8710 $1\cr_op__insn$4$next[31:0]$8713 + assign $0\cr_op__insn_type$2$next[6:0]$8711 $1\cr_op__insn_type$2$next[6:0]$8714 + attribute \src "libresoc.v:160754.5-160754.29" switch \initial - attribute \src "libresoc.v:158828.9-158828.17" + attribute \src "libresoc.v:160754.9-160754.17" case 1'1 case end @@ -331844,35 +334465,35 @@ module \pipe assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8668 $1\cr_op__fn_unit$3$next[12:0]$8667 $1\cr_op__insn_type$2$next[6:0]$8669 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8713 $1\cr_op__fn_unit$3$next[13:0]$8712 $1\cr_op__insn_type$2$next[6:0]$8714 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8668 $1\cr_op__fn_unit$3$next[12:0]$8667 $1\cr_op__insn_type$2$next[6:0]$8669 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8713 $1\cr_op__fn_unit$3$next[13:0]$8712 $1\cr_op__insn_type$2$next[6:0]$8714 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case - assign $1\cr_op__fn_unit$3$next[12:0]$8667 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8668 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8669 \cr_op__insn_type$2 + assign $1\cr_op__fn_unit$3$next[13:0]$8712 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8713 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8714 \cr_op__insn_type$2 end sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[12:0]$8664 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8665 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8666 + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8709 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8710 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8711 end - attribute \src "libresoc.v:158842.3-158860.6" - process $proc$libresoc.v:158842$8670 + attribute \src "libresoc.v:160768.3-160786.6" + process $proc$libresoc.v:160768$8715 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8671 $1\o$next[63:0]$8673 + assign $0\o$next[63:0]$8716 $1\o$next[63:0]$8718 assign { } { } - assign $0\o_ok$next[0:0]$8672 $2\o_ok$next[0:0]$8675 - attribute \src "libresoc.v:158843.5-158843.29" + assign $0\o_ok$next[0:0]$8717 $2\o_ok$next[0:0]$8720 + attribute \src "libresoc.v:160769.5-160769.29" switch \initial - attribute \src "libresoc.v:158843.9-158843.17" + attribute \src "libresoc.v:160769.9-160769.17" case 1'1 case end @@ -331882,41 +334503,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8674 $1\o$next[63:0]$8673 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8719 $1\o$next[63:0]$8718 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8674 $1\o$next[63:0]$8673 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8719 $1\o$next[63:0]$8718 } { \o_ok$21 \o$20 } case - assign $1\o$next[63:0]$8673 \o - assign $1\o_ok$next[0:0]$8674 \o_ok + assign $1\o$next[63:0]$8718 \o + assign $1\o_ok$next[0:0]$8719 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8675 1'0 + assign $2\o_ok$next[0:0]$8720 1'0 case - assign $2\o_ok$next[0:0]$8675 $1\o_ok$next[0:0]$8674 + assign $2\o_ok$next[0:0]$8720 $1\o_ok$next[0:0]$8719 end sync always - update \o$next $0\o$next[63:0]$8671 - update \o_ok$next $0\o_ok$next[0:0]$8672 + update \o$next $0\o$next[63:0]$8716 + update \o_ok$next $0\o_ok$next[0:0]$8717 end - attribute \src "libresoc.v:158861.3-158879.6" - process $proc$libresoc.v:158861$8676 + attribute \src "libresoc.v:160787.3-160805.6" + process $proc$libresoc.v:160787$8721 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\full_cr$5$next[31:0]$8677 $1\full_cr$5$next[31:0]$8679 + assign $0\full_cr$5$next[31:0]$8722 $1\full_cr$5$next[31:0]$8724 assign { } { } - assign $0\full_cr_ok$next[0:0]$8678 $2\full_cr_ok$next[0:0]$8681 - attribute \src "libresoc.v:158862.5-158862.29" + assign $0\full_cr_ok$next[0:0]$8723 $2\full_cr_ok$next[0:0]$8726 + attribute \src "libresoc.v:160788.5-160788.29" switch \initial - attribute \src "libresoc.v:158862.9-158862.17" + attribute \src "libresoc.v:160788.9-160788.17" case 1'1 case end @@ -331926,41 +334547,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8680 $1\full_cr$5$next[31:0]$8679 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8725 $1\full_cr$5$next[31:0]$8724 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8680 $1\full_cr$5$next[31:0]$8679 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8725 $1\full_cr$5$next[31:0]$8724 } { \full_cr_ok$23 \full_cr$22 } case - assign $1\full_cr$5$next[31:0]$8679 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8680 \full_cr_ok + assign $1\full_cr$5$next[31:0]$8724 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8725 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\full_cr_ok$next[0:0]$8681 1'0 + assign $2\full_cr_ok$next[0:0]$8726 1'0 case - assign $2\full_cr_ok$next[0:0]$8681 $1\full_cr_ok$next[0:0]$8680 + assign $2\full_cr_ok$next[0:0]$8726 $1\full_cr_ok$next[0:0]$8725 end sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8677 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8678 + update \full_cr$5$next $0\full_cr$5$next[31:0]$8722 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8723 end - attribute \src "libresoc.v:158880.3-158898.6" - process $proc$libresoc.v:158880$8682 + attribute \src "libresoc.v:160806.3-160824.6" + process $proc$libresoc.v:160806$8727 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$6$next[3:0]$8684 $1\cr_a$6$next[3:0]$8686 - assign $0\cr_a_ok$next[0:0]$8683 $2\cr_a_ok$next[0:0]$8687 - attribute \src "libresoc.v:158881.5-158881.29" + assign $0\cr_a$6$next[3:0]$8729 $1\cr_a$6$next[3:0]$8731 + assign $0\cr_a_ok$next[0:0]$8728 $2\cr_a_ok$next[0:0]$8732 + attribute \src "libresoc.v:160807.5-160807.29" switch \initial - attribute \src "libresoc.v:158881.9-158881.17" + attribute \src "libresoc.v:160807.9-160807.17" case 1'1 case end @@ -331970,30 +334591,30 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8685 $1\cr_a$6$next[3:0]$8686 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8730 $1\cr_a$6$next[3:0]$8731 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8685 $1\cr_a$6$next[3:0]$8686 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8730 $1\cr_a$6$next[3:0]$8731 } { \cr_a_ok$25 \cr_a$24 } case - assign $1\cr_a_ok$next[0:0]$8685 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8686 \cr_a$6 + assign $1\cr_a_ok$next[0:0]$8730 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8731 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8687 1'0 + assign $2\cr_a_ok$next[0:0]$8732 1'0 case - assign $2\cr_a_ok$next[0:0]$8687 $1\cr_a_ok$next[0:0]$8685 + assign $2\cr_a_ok$next[0:0]$8732 $1\cr_a_ok$next[0:0]$8730 end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8683 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8684 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8728 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8729 end - connect \$14 $and$libresoc.v:158743$8638_Y + connect \$14 $and$libresoc.v:160669$8683_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } @@ -332013,155 +334634,155 @@ module \pipe connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:158921.1-159771.10" +attribute \src "libresoc.v:160847.1-161707.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 64 $0\br_op__cia$2$next[63:0]$8742 - attribute \src "libresoc.v:159583.3-159584.43" - wire width 64 $0\br_op__cia$2[63:0]$8716 - attribute \src "libresoc.v:158929.14-158929.51" - wire width 64 $0\br_op__cia$2[63:0]$8780 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 13 $0\br_op__fn_unit$4$next[12:0]$8743 - attribute \src "libresoc.v:159587.3-159588.51" - wire width 13 $0\br_op__fn_unit$4[12:0]$8720 - attribute \src "libresoc.v:158982.14-158982.43" - wire width 13 $0\br_op__fn_unit$4[12:0]$8782 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8744 - attribute \src "libresoc.v:159591.3-159592.65" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8724 - attribute \src "libresoc.v:158991.14-158991.62" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8784 - attribute \src "libresoc.v:159671.3-159698.6" - wire $0\br_op__imm_data__ok$7$next[0:0]$8745 - attribute \src "libresoc.v:159593.3-159594.61" - wire $0\br_op__imm_data__ok$7[0:0]$8726 - attribute \src "libresoc.v:159000.7-159000.37" - wire $0\br_op__imm_data__ok$7[0:0]$8786 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 32 $0\br_op__insn$5$next[31:0]$8746 - attribute \src "libresoc.v:159589.3-159590.45" - wire width 32 $0\br_op__insn$5[31:0]$8722 - attribute \src "libresoc.v:159009.14-159009.37" - wire width 32 $0\br_op__insn$5[31:0]$8788 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 7 $0\br_op__insn_type$3$next[6:0]$8747 - attribute \src "libresoc.v:159585.3-159586.55" - wire width 7 $0\br_op__insn_type$3[6:0]$8718 - attribute \src "libresoc.v:159240.13-159240.41" - wire width 7 $0\br_op__insn_type$3[6:0]$8790 - attribute \src "libresoc.v:159671.3-159698.6" - wire $0\br_op__is_32bit$9$next[0:0]$8748 - attribute \src "libresoc.v:159597.3-159598.53" - wire $0\br_op__is_32bit$9[0:0]$8730 - attribute \src "libresoc.v:159249.7-159249.33" - wire $0\br_op__is_32bit$9[0:0]$8792 - attribute \src "libresoc.v:159671.3-159698.6" - wire $0\br_op__lk$8$next[0:0]$8749 - attribute \src "libresoc.v:159595.3-159596.41" - wire $0\br_op__lk$8[0:0]$8728 - attribute \src "libresoc.v:159258.7-159258.27" - wire $0\br_op__lk$8[0:0]$8794 - attribute \src "libresoc.v:159699.3-159717.6" - wire width 64 $0\fast1$10$next[63:0]$8761 - attribute \src "libresoc.v:159579.3-159580.35" - wire width 64 $0\fast1$10[63:0]$8713 - attribute \src "libresoc.v:159271.14-159271.47" - wire width 64 $0\fast1$10[63:0]$8796 - attribute \src "libresoc.v:159699.3-159717.6" - wire $0\fast1_ok$next[0:0]$8762 - attribute \src "libresoc.v:159581.3-159582.33" + attribute \src "libresoc.v:161607.3-161634.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8787 + attribute \src "libresoc.v:161519.3-161520.43" + wire width 64 $0\br_op__cia$2[63:0]$8761 + attribute \src "libresoc.v:160855.14-160855.51" + wire width 64 $0\br_op__cia$2[63:0]$8825 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 14 $0\br_op__fn_unit$4$next[13:0]$8788 + attribute \src "libresoc.v:161523.3-161524.51" + wire width 14 $0\br_op__fn_unit$4[13:0]$8765 + attribute \src "libresoc.v:160911.14-160911.43" + wire width 14 $0\br_op__fn_unit$4[13:0]$8827 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8789 + attribute \src "libresoc.v:161527.3-161528.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8769 + attribute \src "libresoc.v:160920.14-160920.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8829 + attribute \src "libresoc.v:161607.3-161634.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8790 + attribute \src "libresoc.v:161529.3-161530.61" + wire $0\br_op__imm_data__ok$7[0:0]$8771 + attribute \src "libresoc.v:160929.7-160929.37" + wire $0\br_op__imm_data__ok$7[0:0]$8831 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8791 + attribute \src "libresoc.v:161525.3-161526.45" + wire width 32 $0\br_op__insn$5[31:0]$8767 + attribute \src "libresoc.v:160938.14-160938.37" + wire width 32 $0\br_op__insn$5[31:0]$8833 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8792 + attribute \src "libresoc.v:161521.3-161522.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8763 + attribute \src "libresoc.v:161172.13-161172.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8835 + attribute \src "libresoc.v:161607.3-161634.6" + wire $0\br_op__is_32bit$9$next[0:0]$8793 + attribute \src "libresoc.v:161533.3-161534.53" + wire $0\br_op__is_32bit$9[0:0]$8775 + attribute \src "libresoc.v:161181.7-161181.33" + wire $0\br_op__is_32bit$9[0:0]$8837 + attribute \src "libresoc.v:161607.3-161634.6" + wire $0\br_op__lk$8$next[0:0]$8794 + attribute \src "libresoc.v:161531.3-161532.41" + wire $0\br_op__lk$8[0:0]$8773 + attribute \src "libresoc.v:161190.7-161190.27" + wire $0\br_op__lk$8[0:0]$8839 + attribute \src "libresoc.v:161635.3-161653.6" + wire width 64 $0\fast1$10$next[63:0]$8806 + attribute \src "libresoc.v:161515.3-161516.35" + wire width 64 $0\fast1$10[63:0]$8758 + attribute \src "libresoc.v:161203.14-161203.47" + wire width 64 $0\fast1$10[63:0]$8841 + attribute \src "libresoc.v:161635.3-161653.6" + wire $0\fast1_ok$next[0:0]$8807 + attribute \src "libresoc.v:161517.3-161518.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:159718.3-159736.6" - wire width 64 $0\fast2$11$next[63:0]$8767 - attribute \src "libresoc.v:159575.3-159576.35" - wire width 64 $0\fast2$11[63:0]$8710 - attribute \src "libresoc.v:159287.14-159287.47" - wire width 64 $0\fast2$11[63:0]$8799 - attribute \src "libresoc.v:159718.3-159736.6" - wire $0\fast2_ok$next[0:0]$8768 - attribute \src "libresoc.v:159577.3-159578.33" + attribute \src "libresoc.v:161654.3-161672.6" + wire width 64 $0\fast2$11$next[63:0]$8812 + attribute \src "libresoc.v:161511.3-161512.35" + wire width 64 $0\fast2$11[63:0]$8755 + attribute \src "libresoc.v:161219.14-161219.47" + wire width 64 $0\fast2$11[63:0]$8844 + attribute \src "libresoc.v:161654.3-161672.6" + wire $0\fast2_ok$next[0:0]$8813 + attribute \src "libresoc.v:161513.3-161514.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:158922.7-158922.20" + attribute \src "libresoc.v:160848.7-160848.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159658.3-159670.6" - wire width 2 $0\muxid$1$next[1:0]$8739 - attribute \src "libresoc.v:159599.3-159600.33" - wire width 2 $0\muxid$1[1:0]$8732 - attribute \src "libresoc.v:159533.13-159533.29" - wire width 2 $0\muxid$1[1:0]$8802 - attribute \src "libresoc.v:159737.3-159755.6" - wire width 64 $0\nia$next[63:0]$8773 - attribute \src "libresoc.v:159571.3-159572.23" + attribute \src "libresoc.v:161594.3-161606.6" + wire width 2 $0\muxid$1$next[1:0]$8784 + attribute \src "libresoc.v:161535.3-161536.33" + wire width 2 $0\muxid$1[1:0]$8777 + attribute \src "libresoc.v:161469.13-161469.29" + wire width 2 $0\muxid$1[1:0]$8847 + attribute \src "libresoc.v:161673.3-161691.6" + wire width 64 $0\nia$next[63:0]$8818 + attribute \src "libresoc.v:161507.3-161508.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:159737.3-159755.6" - wire $0\nia_ok$next[0:0]$8774 - attribute \src "libresoc.v:159573.3-159574.29" + attribute \src "libresoc.v:161673.3-161691.6" + wire $0\nia_ok$next[0:0]$8819 + attribute \src "libresoc.v:161509.3-161510.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:159640.3-159657.6" - wire $0\r_busy$next[0:0]$8735 - attribute \src "libresoc.v:159601.3-159602.29" + attribute \src "libresoc.v:161576.3-161593.6" + wire $0\r_busy$next[0:0]$8780 + attribute \src "libresoc.v:161537.3-161538.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:159671.3-159698.6" - wire width 64 $1\br_op__cia$2$next[63:0]$8750 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 13 $1\br_op__fn_unit$4$next[12:0]$8751 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8752 - attribute \src "libresoc.v:159671.3-159698.6" - wire $1\br_op__imm_data__ok$7$next[0:0]$8753 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 32 $1\br_op__insn$5$next[31:0]$8754 - attribute \src "libresoc.v:159671.3-159698.6" - wire width 7 $1\br_op__insn_type$3$next[6:0]$8755 - attribute \src "libresoc.v:159671.3-159698.6" - wire $1\br_op__is_32bit$9$next[0:0]$8756 - attribute \src "libresoc.v:159671.3-159698.6" - wire $1\br_op__lk$8$next[0:0]$8757 - attribute \src "libresoc.v:159699.3-159717.6" - wire width 64 $1\fast1$10$next[63:0]$8763 - attribute \src "libresoc.v:159699.3-159717.6" - wire $1\fast1_ok$next[0:0]$8764 - attribute \src "libresoc.v:159278.7-159278.22" + attribute \src "libresoc.v:161607.3-161634.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8795 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 14 $1\br_op__fn_unit$4$next[13:0]$8796 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8797 + attribute \src "libresoc.v:161607.3-161634.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8798 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8799 + attribute \src "libresoc.v:161607.3-161634.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8800 + attribute \src "libresoc.v:161607.3-161634.6" + wire $1\br_op__is_32bit$9$next[0:0]$8801 + attribute \src "libresoc.v:161607.3-161634.6" + wire $1\br_op__lk$8$next[0:0]$8802 + attribute \src "libresoc.v:161635.3-161653.6" + wire width 64 $1\fast1$10$next[63:0]$8808 + attribute \src "libresoc.v:161635.3-161653.6" + wire $1\fast1_ok$next[0:0]$8809 + attribute \src "libresoc.v:161210.7-161210.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:159718.3-159736.6" - wire width 64 $1\fast2$11$next[63:0]$8769 - attribute \src "libresoc.v:159718.3-159736.6" - wire $1\fast2_ok$next[0:0]$8770 - attribute \src "libresoc.v:159294.7-159294.22" + attribute \src "libresoc.v:161654.3-161672.6" + wire width 64 $1\fast2$11$next[63:0]$8814 + attribute \src "libresoc.v:161654.3-161672.6" + wire $1\fast2_ok$next[0:0]$8815 + attribute \src "libresoc.v:161226.7-161226.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:159658.3-159670.6" - wire width 2 $1\muxid$1$next[1:0]$8740 - attribute \src "libresoc.v:159737.3-159755.6" - wire width 64 $1\nia$next[63:0]$8775 - attribute \src "libresoc.v:159546.14-159546.40" + attribute \src "libresoc.v:161594.3-161606.6" + wire width 2 $1\muxid$1$next[1:0]$8785 + attribute \src "libresoc.v:161673.3-161691.6" + wire width 64 $1\nia$next[63:0]$8820 + attribute \src "libresoc.v:161482.14-161482.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:159737.3-159755.6" - wire $1\nia_ok$next[0:0]$8776 - attribute \src "libresoc.v:159553.7-159553.20" + attribute \src "libresoc.v:161673.3-161691.6" + wire $1\nia_ok$next[0:0]$8821 + attribute \src "libresoc.v:161489.7-161489.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:159640.3-159657.6" - wire $1\r_busy$next[0:0]$8736 - attribute \src "libresoc.v:159567.7-159567.20" + attribute \src "libresoc.v:161576.3-161593.6" + wire $1\r_busy$next[0:0]$8781 + attribute \src "libresoc.v:161503.7-161503.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:159671.3-159698.6" - wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8758 - attribute \src "libresoc.v:159671.3-159698.6" - wire $2\br_op__imm_data__ok$7$next[0:0]$8759 - attribute \src "libresoc.v:159699.3-159717.6" - wire $2\fast1_ok$next[0:0]$8765 - attribute \src "libresoc.v:159718.3-159736.6" - wire $2\fast2_ok$next[0:0]$8771 - attribute \src "libresoc.v:159737.3-159755.6" - wire $2\nia_ok$next[0:0]$8777 - attribute \src "libresoc.v:159640.3-159657.6" - wire $2\r_busy$next[0:0]$8737 - attribute \src "libresoc.v:159570.18-159570.118" - wire $and$libresoc.v:159570$8706_Y + attribute \src "libresoc.v:161607.3-161634.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8803 + attribute \src "libresoc.v:161607.3-161634.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8804 + attribute \src "libresoc.v:161635.3-161653.6" + wire $2\fast1_ok$next[0:0]$8810 + attribute \src "libresoc.v:161654.3-161672.6" + wire $2\fast2_ok$next[0:0]$8816 + attribute \src "libresoc.v:161673.3-161691.6" + wire $2\nia_ok$next[0:0]$8822 + attribute \src "libresoc.v:161576.3-161593.6" + wire $2\r_busy$next[0:0]$8782 + attribute \src "libresoc.v:161506.18-161506.118" + wire $and$libresoc.v:161506$8751_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -332173,55 +334794,58 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__cia$27 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 7 \br_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 7 \br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \br_op__fn_unit$29 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$29 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 21 \br_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \br_op__fn_unit$4$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 21 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \br_op__fn_unit$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 9 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -332320,6 +334944,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \br_op__insn_type attribute \enum_base_type "MicrOp" @@ -332396,6 +335021,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \br_op__insn_type$28 attribute \enum_base_type "MicrOp" @@ -332472,6 +335098,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 20 \br_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -332492,9 +335119,9 @@ module \pipe$19 wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 15 \cr_a @@ -332526,44 +335153,46 @@ module \pipe$19 wire \fast2_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:158922.7-158922.15" + attribute \src "libresoc.v:160848.7-160848.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia$13 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_br_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_br_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_br_op__fn_unit$15 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_br_op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -332650,6 +335279,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_br_op__insn_type attribute \enum_base_type "MicrOp" @@ -332726,6 +335356,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_br_op__insn_type$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -332797,7 +335428,7 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:159570$8706 + cell $and $and$libresoc.v:161506$8751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332805,10 +335436,10 @@ module \pipe$19 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:159570$8706_Y + connect \Y $and$libresoc.v:161506$8751_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:159603.13-159631.4" + attribute \src "libresoc.v:161539.13-161567.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 @@ -332839,274 +335470,274 @@ module \pipe$19 connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:159632.10-159635.4" + attribute \src "libresoc.v:161568.10-161571.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:159636.10-159639.4" + attribute \src "libresoc.v:161572.10-161575.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:158922.7-158922.20" - process $proc$libresoc.v:158922$8778 + attribute \src "libresoc.v:160848.7-160848.20" + process $proc$libresoc.v:160848$8823 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158929.14-158929.51" - process $proc$libresoc.v:158929$8779 + attribute \src "libresoc.v:160855.14-160855.51" + process $proc$libresoc.v:160855$8824 assign { } { } - assign $0\br_op__cia$2[63:0]$8780 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__cia$2[63:0]$8825 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8780 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8825 end - attribute \src "libresoc.v:158982.14-158982.43" - process $proc$libresoc.v:158982$8781 + attribute \src "libresoc.v:160911.14-160911.43" + process $proc$libresoc.v:160911$8826 assign { } { } - assign $0\br_op__fn_unit$4[12:0]$8782 13'0000000000000 + assign $0\br_op__fn_unit$4[13:0]$8827 14'00000000000000 sync always sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8782 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8827 end - attribute \src "libresoc.v:158991.14-158991.62" - process $proc$libresoc.v:158991$8783 + attribute \src "libresoc.v:160920.14-160920.62" + process $proc$libresoc.v:160920$8828 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8784 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__imm_data__data$6[63:0]$8829 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8784 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8829 end - attribute \src "libresoc.v:159000.7-159000.37" - process $proc$libresoc.v:159000$8785 + attribute \src "libresoc.v:160929.7-160929.37" + process $proc$libresoc.v:160929$8830 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8786 1'0 + assign $0\br_op__imm_data__ok$7[0:0]$8831 1'0 sync always sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8786 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8831 end - attribute \src "libresoc.v:159009.14-159009.37" - process $proc$libresoc.v:159009$8787 + attribute \src "libresoc.v:160938.14-160938.37" + process $proc$libresoc.v:160938$8832 assign { } { } - assign $0\br_op__insn$5[31:0]$8788 0 + assign $0\br_op__insn$5[31:0]$8833 0 sync always sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8788 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8833 end - attribute \src "libresoc.v:159240.13-159240.41" - process $proc$libresoc.v:159240$8789 + attribute \src "libresoc.v:161172.13-161172.41" + process $proc$libresoc.v:161172$8834 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8790 7'0000000 + assign $0\br_op__insn_type$3[6:0]$8835 7'0000000 sync always sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8790 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8835 end - attribute \src "libresoc.v:159249.7-159249.33" - process $proc$libresoc.v:159249$8791 + attribute \src "libresoc.v:161181.7-161181.33" + process $proc$libresoc.v:161181$8836 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8792 1'0 + assign $0\br_op__is_32bit$9[0:0]$8837 1'0 sync always sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8792 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8837 end - attribute \src "libresoc.v:159258.7-159258.27" - process $proc$libresoc.v:159258$8793 + attribute \src "libresoc.v:161190.7-161190.27" + process $proc$libresoc.v:161190$8838 assign { } { } - assign $0\br_op__lk$8[0:0]$8794 1'0 + assign $0\br_op__lk$8[0:0]$8839 1'0 sync always sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8794 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8839 end - attribute \src "libresoc.v:159271.14-159271.47" - process $proc$libresoc.v:159271$8795 + attribute \src "libresoc.v:161203.14-161203.47" + process $proc$libresoc.v:161203$8840 assign { } { } - assign $0\fast1$10[63:0]$8796 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$10[63:0]$8841 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$10 $0\fast1$10[63:0]$8796 + update \fast1$10 $0\fast1$10[63:0]$8841 end - attribute \src "libresoc.v:159278.7-159278.22" - process $proc$libresoc.v:159278$8797 + attribute \src "libresoc.v:161210.7-161210.22" + process $proc$libresoc.v:161210$8842 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:159287.14-159287.47" - process $proc$libresoc.v:159287$8798 + attribute \src "libresoc.v:161219.14-161219.47" + process $proc$libresoc.v:161219$8843 assign { } { } - assign $0\fast2$11[63:0]$8799 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$11[63:0]$8844 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$11 $0\fast2$11[63:0]$8799 + update \fast2$11 $0\fast2$11[63:0]$8844 end - attribute \src "libresoc.v:159294.7-159294.22" - process $proc$libresoc.v:159294$8800 + attribute \src "libresoc.v:161226.7-161226.22" + process $proc$libresoc.v:161226$8845 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:159533.13-159533.29" - process $proc$libresoc.v:159533$8801 + attribute \src "libresoc.v:161469.13-161469.29" + process $proc$libresoc.v:161469$8846 assign { } { } - assign $0\muxid$1[1:0]$8802 2'00 + assign $0\muxid$1[1:0]$8847 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8802 + update \muxid$1 $0\muxid$1[1:0]$8847 end - attribute \src "libresoc.v:159546.14-159546.40" - process $proc$libresoc.v:159546$8803 + attribute \src "libresoc.v:161482.14-161482.40" + process $proc$libresoc.v:161482$8848 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:159553.7-159553.20" - process $proc$libresoc.v:159553$8804 + attribute \src "libresoc.v:161489.7-161489.20" + process $proc$libresoc.v:161489$8849 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:159567.7-159567.20" - process $proc$libresoc.v:159567$8805 + attribute \src "libresoc.v:161503.7-161503.20" + process $proc$libresoc.v:161503$8850 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:159571.3-159572.23" - process $proc$libresoc.v:159571$8707 + attribute \src "libresoc.v:161507.3-161508.23" + process $proc$libresoc.v:161507$8752 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:159573.3-159574.29" - process $proc$libresoc.v:159573$8708 + attribute \src "libresoc.v:161509.3-161510.29" + process $proc$libresoc.v:161509$8753 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:159575.3-159576.35" - process $proc$libresoc.v:159575$8709 + attribute \src "libresoc.v:161511.3-161512.35" + process $proc$libresoc.v:161511$8754 assign { } { } - assign $0\fast2$11[63:0]$8710 \fast2$11$next + assign $0\fast2$11[63:0]$8755 \fast2$11$next sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8710 + update \fast2$11 $0\fast2$11[63:0]$8755 end - attribute \src "libresoc.v:159577.3-159578.33" - process $proc$libresoc.v:159577$8711 + attribute \src "libresoc.v:161513.3-161514.33" + process $proc$libresoc.v:161513$8756 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:159579.3-159580.35" - process $proc$libresoc.v:159579$8712 + attribute \src "libresoc.v:161515.3-161516.35" + process $proc$libresoc.v:161515$8757 assign { } { } - assign $0\fast1$10[63:0]$8713 \fast1$10$next + assign $0\fast1$10[63:0]$8758 \fast1$10$next sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8713 + update \fast1$10 $0\fast1$10[63:0]$8758 end - attribute \src "libresoc.v:159581.3-159582.33" - process $proc$libresoc.v:159581$8714 + attribute \src "libresoc.v:161517.3-161518.33" + process $proc$libresoc.v:161517$8759 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:159583.3-159584.43" - process $proc$libresoc.v:159583$8715 + attribute \src "libresoc.v:161519.3-161520.43" + process $proc$libresoc.v:161519$8760 assign { } { } - assign $0\br_op__cia$2[63:0]$8716 \br_op__cia$2$next + assign $0\br_op__cia$2[63:0]$8761 \br_op__cia$2$next sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8716 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8761 end - attribute \src "libresoc.v:159585.3-159586.55" - process $proc$libresoc.v:159585$8717 + attribute \src "libresoc.v:161521.3-161522.55" + process $proc$libresoc.v:161521$8762 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8718 \br_op__insn_type$3$next + assign $0\br_op__insn_type$3[6:0]$8763 \br_op__insn_type$3$next sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8718 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8763 end - attribute \src "libresoc.v:159587.3-159588.51" - process $proc$libresoc.v:159587$8719 + attribute \src "libresoc.v:161523.3-161524.51" + process $proc$libresoc.v:161523$8764 assign { } { } - assign $0\br_op__fn_unit$4[12:0]$8720 \br_op__fn_unit$4$next + assign $0\br_op__fn_unit$4[13:0]$8765 \br_op__fn_unit$4$next sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8720 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8765 end - attribute \src "libresoc.v:159589.3-159590.45" - process $proc$libresoc.v:159589$8721 + attribute \src "libresoc.v:161525.3-161526.45" + process $proc$libresoc.v:161525$8766 assign { } { } - assign $0\br_op__insn$5[31:0]$8722 \br_op__insn$5$next + assign $0\br_op__insn$5[31:0]$8767 \br_op__insn$5$next sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8722 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8767 end - attribute \src "libresoc.v:159591.3-159592.65" - process $proc$libresoc.v:159591$8723 + attribute \src "libresoc.v:161527.3-161528.65" + process $proc$libresoc.v:161527$8768 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8724 \br_op__imm_data__data$6$next + assign $0\br_op__imm_data__data$6[63:0]$8769 \br_op__imm_data__data$6$next sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8724 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8769 end - attribute \src "libresoc.v:159593.3-159594.61" - process $proc$libresoc.v:159593$8725 + attribute \src "libresoc.v:161529.3-161530.61" + process $proc$libresoc.v:161529$8770 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8726 \br_op__imm_data__ok$7$next + assign $0\br_op__imm_data__ok$7[0:0]$8771 \br_op__imm_data__ok$7$next sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8726 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8771 end - attribute \src "libresoc.v:159595.3-159596.41" - process $proc$libresoc.v:159595$8727 + attribute \src "libresoc.v:161531.3-161532.41" + process $proc$libresoc.v:161531$8772 assign { } { } - assign $0\br_op__lk$8[0:0]$8728 \br_op__lk$8$next + assign $0\br_op__lk$8[0:0]$8773 \br_op__lk$8$next sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8728 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8773 end - attribute \src "libresoc.v:159597.3-159598.53" - process $proc$libresoc.v:159597$8729 + attribute \src "libresoc.v:161533.3-161534.53" + process $proc$libresoc.v:161533$8774 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8730 \br_op__is_32bit$9$next + assign $0\br_op__is_32bit$9[0:0]$8775 \br_op__is_32bit$9$next sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8730 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8775 end - attribute \src "libresoc.v:159599.3-159600.33" - process $proc$libresoc.v:159599$8731 + attribute \src "libresoc.v:161535.3-161536.33" + process $proc$libresoc.v:161535$8776 assign { } { } - assign $0\muxid$1[1:0]$8732 \muxid$1$next + assign $0\muxid$1[1:0]$8777 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8732 + update \muxid$1 $0\muxid$1[1:0]$8777 end - attribute \src "libresoc.v:159601.3-159602.29" - process $proc$libresoc.v:159601$8733 + attribute \src "libresoc.v:161537.3-161538.29" + process $proc$libresoc.v:161537$8778 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:159640.3-159657.6" - process $proc$libresoc.v:159640$8734 + attribute \src "libresoc.v:161576.3-161593.6" + process $proc$libresoc.v:161576$8779 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8735 $2\r_busy$next[0:0]$8737 - attribute \src "libresoc.v:159641.5-159641.29" + assign $0\r_busy$next[0:0]$8780 $2\r_busy$next[0:0]$8782 + attribute \src "libresoc.v:161577.5-161577.29" switch \initial - attribute \src "libresoc.v:159641.9-159641.17" + attribute \src "libresoc.v:161577.9-161577.17" case 1'1 case end @@ -333115,34 +335746,34 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8736 1'1 + assign $1\r_busy$next[0:0]$8781 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8736 1'0 + assign $1\r_busy$next[0:0]$8781 1'0 case - assign $1\r_busy$next[0:0]$8736 \r_busy + assign $1\r_busy$next[0:0]$8781 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8737 1'0 + assign $2\r_busy$next[0:0]$8782 1'0 case - assign $2\r_busy$next[0:0]$8737 $1\r_busy$next[0:0]$8736 + assign $2\r_busy$next[0:0]$8782 $1\r_busy$next[0:0]$8781 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8735 + update \r_busy$next $0\r_busy$next[0:0]$8780 end - attribute \src "libresoc.v:159658.3-159670.6" - process $proc$libresoc.v:159658$8738 + attribute \src "libresoc.v:161594.3-161606.6" + process $proc$libresoc.v:161594$8783 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8739 $1\muxid$1$next[1:0]$8740 - attribute \src "libresoc.v:159659.5-159659.29" + assign $0\muxid$1$next[1:0]$8784 $1\muxid$1$next[1:0]$8785 + attribute \src "libresoc.v:161595.5-161595.29" switch \initial - attribute \src "libresoc.v:159659.9-159659.17" + attribute \src "libresoc.v:161595.9-161595.17" case 1'1 case end @@ -333151,19 +335782,19 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8740 \muxid$26 + assign $1\muxid$1$next[1:0]$8785 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8740 \muxid$26 + assign $1\muxid$1$next[1:0]$8785 \muxid$26 case - assign $1\muxid$1$next[1:0]$8740 \muxid$1 + assign $1\muxid$1$next[1:0]$8785 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8739 + update \muxid$1$next $0\muxid$1$next[1:0]$8784 end - attribute \src "libresoc.v:159671.3-159698.6" - process $proc$libresoc.v:159671$8741 + attribute \src "libresoc.v:161607.3-161634.6" + process $proc$libresoc.v:161607$8786 assign { } { } assign { } { } assign { } { } @@ -333180,19 +335811,19 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign $0\br_op__cia$2$next[63:0]$8742 $1\br_op__cia$2$next[63:0]$8750 - assign $0\br_op__fn_unit$4$next[12:0]$8743 $1\br_op__fn_unit$4$next[12:0]$8751 + assign $0\br_op__cia$2$next[63:0]$8787 $1\br_op__cia$2$next[63:0]$8795 + assign $0\br_op__fn_unit$4$next[13:0]$8788 $1\br_op__fn_unit$4$next[13:0]$8796 assign { } { } assign { } { } - assign $0\br_op__insn$5$next[31:0]$8746 $1\br_op__insn$5$next[31:0]$8754 - assign $0\br_op__insn_type$3$next[6:0]$8747 $1\br_op__insn_type$3$next[6:0]$8755 - assign $0\br_op__is_32bit$9$next[0:0]$8748 $1\br_op__is_32bit$9$next[0:0]$8756 - assign $0\br_op__lk$8$next[0:0]$8749 $1\br_op__lk$8$next[0:0]$8757 - assign $0\br_op__imm_data__data$6$next[63:0]$8744 $2\br_op__imm_data__data$6$next[63:0]$8758 - assign $0\br_op__imm_data__ok$7$next[0:0]$8745 $2\br_op__imm_data__ok$7$next[0:0]$8759 - attribute \src "libresoc.v:159672.5-159672.29" + assign $0\br_op__insn$5$next[31:0]$8791 $1\br_op__insn$5$next[31:0]$8799 + assign $0\br_op__insn_type$3$next[6:0]$8792 $1\br_op__insn_type$3$next[6:0]$8800 + assign $0\br_op__is_32bit$9$next[0:0]$8793 $1\br_op__is_32bit$9$next[0:0]$8801 + assign $0\br_op__lk$8$next[0:0]$8794 $1\br_op__lk$8$next[0:0]$8802 + assign $0\br_op__imm_data__data$6$next[63:0]$8789 $2\br_op__imm_data__data$6$next[63:0]$8803 + assign $0\br_op__imm_data__ok$7$next[0:0]$8790 $2\br_op__imm_data__ok$7$next[0:0]$8804 + attribute \src "libresoc.v:161608.5-161608.29" switch \initial - attribute \src "libresoc.v:159672.9-159672.17" + attribute \src "libresoc.v:161608.9-161608.17" case 1'1 case end @@ -333208,7 +335839,7 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8756 $1\br_op__lk$8$next[0:0]$8757 $1\br_op__imm_data__ok$7$next[0:0]$8753 $1\br_op__imm_data__data$6$next[63:0]$8752 $1\br_op__insn$5$next[31:0]$8754 $1\br_op__fn_unit$4$next[12:0]$8751 $1\br_op__insn_type$3$next[6:0]$8755 $1\br_op__cia$2$next[63:0]$8750 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8801 $1\br_op__lk$8$next[0:0]$8802 $1\br_op__imm_data__ok$7$next[0:0]$8798 $1\br_op__imm_data__data$6$next[63:0]$8797 $1\br_op__insn$5$next[31:0]$8799 $1\br_op__fn_unit$4$next[13:0]$8796 $1\br_op__insn_type$3$next[6:0]$8800 $1\br_op__cia$2$next[63:0]$8795 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -333219,16 +335850,16 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8756 $1\br_op__lk$8$next[0:0]$8757 $1\br_op__imm_data__ok$7$next[0:0]$8753 $1\br_op__imm_data__data$6$next[63:0]$8752 $1\br_op__insn$5$next[31:0]$8754 $1\br_op__fn_unit$4$next[12:0]$8751 $1\br_op__insn_type$3$next[6:0]$8755 $1\br_op__cia$2$next[63:0]$8750 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8801 $1\br_op__lk$8$next[0:0]$8802 $1\br_op__imm_data__ok$7$next[0:0]$8798 $1\br_op__imm_data__data$6$next[63:0]$8797 $1\br_op__insn$5$next[31:0]$8799 $1\br_op__fn_unit$4$next[13:0]$8796 $1\br_op__insn_type$3$next[6:0]$8800 $1\br_op__cia$2$next[63:0]$8795 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case - assign $1\br_op__cia$2$next[63:0]$8750 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[12:0]$8751 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8752 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8753 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8754 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8755 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8756 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8757 \br_op__lk$8 + assign $1\br_op__cia$2$next[63:0]$8795 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[13:0]$8796 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8797 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8798 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8799 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8800 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8801 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8802 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -333236,34 +335867,34 @@ module \pipe$19 case 1'1 assign { } { } assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8758 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8759 1'0 + assign $2\br_op__imm_data__data$6$next[63:0]$8803 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8804 1'0 case - assign $2\br_op__imm_data__data$6$next[63:0]$8758 $1\br_op__imm_data__data$6$next[63:0]$8752 - assign $2\br_op__imm_data__ok$7$next[0:0]$8759 $1\br_op__imm_data__ok$7$next[0:0]$8753 + assign $2\br_op__imm_data__data$6$next[63:0]$8803 $1\br_op__imm_data__data$6$next[63:0]$8797 + assign $2\br_op__imm_data__ok$7$next[0:0]$8804 $1\br_op__imm_data__ok$7$next[0:0]$8798 end sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8742 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[12:0]$8743 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8744 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8745 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8746 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8747 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8748 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8749 + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8787 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8788 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8789 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8790 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8791 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8792 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8793 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8794 end - attribute \src "libresoc.v:159699.3-159717.6" - process $proc$libresoc.v:159699$8760 + attribute \src "libresoc.v:161635.3-161653.6" + process $proc$libresoc.v:161635$8805 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$10$next[63:0]$8761 $1\fast1$10$next[63:0]$8763 + assign $0\fast1$10$next[63:0]$8806 $1\fast1$10$next[63:0]$8808 assign { } { } - assign $0\fast1_ok$next[0:0]$8762 $2\fast1_ok$next[0:0]$8765 - attribute \src "libresoc.v:159700.5-159700.29" + assign $0\fast1_ok$next[0:0]$8807 $2\fast1_ok$next[0:0]$8810 + attribute \src "libresoc.v:161636.5-161636.29" switch \initial - attribute \src "libresoc.v:159700.9-159700.17" + attribute \src "libresoc.v:161636.9-161636.17" case 1'1 case end @@ -333273,41 +335904,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8764 $1\fast1$10$next[63:0]$8763 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8809 $1\fast1$10$next[63:0]$8808 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8764 $1\fast1$10$next[63:0]$8763 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8809 $1\fast1$10$next[63:0]$8808 } { \fast1_ok$36 \fast1$35 } case - assign $1\fast1$10$next[63:0]$8763 \fast1$10 - assign $1\fast1_ok$next[0:0]$8764 \fast1_ok + assign $1\fast1$10$next[63:0]$8808 \fast1$10 + assign $1\fast1_ok$next[0:0]$8809 \fast1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8765 1'0 + assign $2\fast1_ok$next[0:0]$8810 1'0 case - assign $2\fast1_ok$next[0:0]$8765 $1\fast1_ok$next[0:0]$8764 + assign $2\fast1_ok$next[0:0]$8810 $1\fast1_ok$next[0:0]$8809 end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8761 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8762 + update \fast1$10$next $0\fast1$10$next[63:0]$8806 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8807 end - attribute \src "libresoc.v:159718.3-159736.6" - process $proc$libresoc.v:159718$8766 + attribute \src "libresoc.v:161654.3-161672.6" + process $proc$libresoc.v:161654$8811 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8767 $1\fast2$11$next[63:0]$8769 + assign $0\fast2$11$next[63:0]$8812 $1\fast2$11$next[63:0]$8814 assign { } { } - assign $0\fast2_ok$next[0:0]$8768 $2\fast2_ok$next[0:0]$8771 - attribute \src "libresoc.v:159719.5-159719.29" + assign $0\fast2_ok$next[0:0]$8813 $2\fast2_ok$next[0:0]$8816 + attribute \src "libresoc.v:161655.5-161655.29" switch \initial - attribute \src "libresoc.v:159719.9-159719.17" + attribute \src "libresoc.v:161655.9-161655.17" case 1'1 case end @@ -333317,41 +335948,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8770 $1\fast2$11$next[63:0]$8769 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8815 $1\fast2$11$next[63:0]$8814 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8770 $1\fast2$11$next[63:0]$8769 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8815 $1\fast2$11$next[63:0]$8814 } { \fast2_ok$38 \fast2$37 } case - assign $1\fast2$11$next[63:0]$8769 \fast2$11 - assign $1\fast2_ok$next[0:0]$8770 \fast2_ok + assign $1\fast2$11$next[63:0]$8814 \fast2$11 + assign $1\fast2_ok$next[0:0]$8815 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8771 1'0 + assign $2\fast2_ok$next[0:0]$8816 1'0 case - assign $2\fast2_ok$next[0:0]$8771 $1\fast2_ok$next[0:0]$8770 + assign $2\fast2_ok$next[0:0]$8816 $1\fast2_ok$next[0:0]$8815 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8767 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8768 + update \fast2$11$next $0\fast2$11$next[63:0]$8812 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8813 end - attribute \src "libresoc.v:159737.3-159755.6" - process $proc$libresoc.v:159737$8772 + attribute \src "libresoc.v:161673.3-161691.6" + process $proc$libresoc.v:161673$8817 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8773 $1\nia$next[63:0]$8775 + assign $0\nia$next[63:0]$8818 $1\nia$next[63:0]$8820 assign { } { } - assign $0\nia_ok$next[0:0]$8774 $2\nia_ok$next[0:0]$8777 - attribute \src "libresoc.v:159738.5-159738.29" + assign $0\nia_ok$next[0:0]$8819 $2\nia_ok$next[0:0]$8822 + attribute \src "libresoc.v:161674.5-161674.29" switch \initial - attribute \src "libresoc.v:159738.9-159738.17" + attribute \src "libresoc.v:161674.9-161674.17" case 1'1 case end @@ -333361,30 +335992,30 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8776 $1\nia$next[63:0]$8775 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8821 $1\nia$next[63:0]$8820 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8776 $1\nia$next[63:0]$8775 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8821 $1\nia$next[63:0]$8820 } { \nia_ok$40 \nia$39 } case - assign $1\nia$next[63:0]$8775 \nia - assign $1\nia_ok$next[0:0]$8776 \nia_ok + assign $1\nia$next[63:0]$8820 \nia + assign $1\nia_ok$next[0:0]$8821 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8777 1'0 + assign $2\nia_ok$next[0:0]$8822 1'0 case - assign $2\nia_ok$next[0:0]$8777 $1\nia_ok$next[0:0]$8776 + assign $2\nia_ok$next[0:0]$8822 $1\nia_ok$next[0:0]$8821 end sync always - update \nia$next $0\nia$next[63:0]$8773 - update \nia_ok$next $0\nia_ok$next[0:0]$8774 + update \nia$next $0\nia$next[63:0]$8818 + update \nia_ok$next $0\nia_ok$next[0:0]$8819 end - connect \$24 $and$libresoc.v:159570$8706_Y + connect \$24 $and$libresoc.v:161506$8751_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } @@ -333401,178 +336032,178 @@ module \pipe$19 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end -attribute \src "libresoc.v:159775.1-160695.10" +attribute \src "libresoc.v:161711.1-162641.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" module \pipe$64 - attribute \src "libresoc.v:160598.3-160616.6" - wire width 64 $0\fast1$7$next[63:0]$8865 - attribute \src "libresoc.v:160451.3-160452.33" - wire width 64 $0\fast1$7[63:0]$8817 - attribute \src "libresoc.v:159789.14-159789.46" - wire width 64 $0\fast1$7[63:0]$8889 - attribute \src "libresoc.v:160598.3-160616.6" - wire $0\fast1_ok$next[0:0]$8864 - attribute \src "libresoc.v:160453.3-160454.33" + attribute \src "libresoc.v:162544.3-162562.6" + wire width 64 $0\fast1$7$next[63:0]$8910 + attribute \src "libresoc.v:162397.3-162398.33" + wire width 64 $0\fast1$7[63:0]$8862 + attribute \src "libresoc.v:161725.14-161725.46" + wire width 64 $0\fast1$7[63:0]$8934 + attribute \src "libresoc.v:162544.3-162562.6" + wire $0\fast1_ok$next[0:0]$8909 + attribute \src "libresoc.v:162399.3-162400.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:159776.7-159776.20" + attribute \src "libresoc.v:161712.7-161712.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160531.3-160543.6" - wire width 2 $0\muxid$1$next[1:0]$8840 - attribute \src "libresoc.v:160471.3-160472.33" - wire width 2 $0\muxid$1[1:0]$8833 - attribute \src "libresoc.v:159803.13-159803.29" - wire width 2 $0\muxid$1[1:0]$8892 - attribute \src "libresoc.v:160560.3-160578.6" - wire width 64 $0\o$next[63:0]$8852 - attribute \src "libresoc.v:160459.3-160460.19" + attribute \src "libresoc.v:162477.3-162489.6" + wire width 2 $0\muxid$1$next[1:0]$8885 + attribute \src "libresoc.v:162417.3-162418.33" + wire width 2 $0\muxid$1[1:0]$8878 + attribute \src "libresoc.v:161739.13-161739.29" + wire width 2 $0\muxid$1[1:0]$8937 + attribute \src "libresoc.v:162506.3-162524.6" + wire width 64 $0\o$next[63:0]$8897 + attribute \src "libresoc.v:162405.3-162406.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:160560.3-160578.6" - wire $0\o_ok$next[0:0]$8853 - attribute \src "libresoc.v:160461.3-160462.25" + attribute \src "libresoc.v:162506.3-162524.6" + wire $0\o_ok$next[0:0]$8898 + attribute \src "libresoc.v:162407.3-162408.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:160513.3-160530.6" - wire $0\r_busy$next[0:0]$8836 - attribute \src "libresoc.v:160473.3-160474.29" + attribute \src "libresoc.v:162459.3-162476.6" + wire $0\r_busy$next[0:0]$8881 + attribute \src "libresoc.v:162419.3-162420.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:160579.3-160597.6" - wire width 64 $0\spr1$6$next[63:0]$8858 - attribute \src "libresoc.v:160455.3-160456.31" - wire width 64 $0\spr1$6[63:0]$8820 - attribute \src "libresoc.v:159848.14-159848.45" - wire width 64 $0\spr1$6[63:0]$8897 - attribute \src "libresoc.v:160579.3-160597.6" - wire $0\spr1_ok$next[0:0]$8859 - attribute \src "libresoc.v:160457.3-160458.31" + attribute \src "libresoc.v:162525.3-162543.6" + wire width 64 $0\spr1$6$next[63:0]$8903 + attribute \src "libresoc.v:162401.3-162402.31" + wire width 64 $0\spr1$6[63:0]$8865 + attribute \src "libresoc.v:161784.14-161784.45" + wire width 64 $0\spr1$6[63:0]$8942 + attribute \src "libresoc.v:162525.3-162543.6" + wire $0\spr1_ok$next[0:0]$8904 + attribute \src "libresoc.v:162403.3-162404.31" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:160544.3-160559.6" - wire width 13 $0\spr_op__fn_unit$3$next[12:0]$8843 - attribute \src "libresoc.v:160465.3-160466.53" - wire width 13 $0\spr_op__fn_unit$3[12:0]$8827 - attribute \src "libresoc.v:160138.14-160138.44" - wire width 13 $0\spr_op__fn_unit$3[12:0]$8900 - attribute \src "libresoc.v:160544.3-160559.6" - wire width 32 $0\spr_op__insn$4$next[31:0]$8844 - attribute \src "libresoc.v:160467.3-160468.47" - wire width 32 $0\spr_op__insn$4[31:0]$8829 - attribute \src "libresoc.v:160147.14-160147.38" - wire width 32 $0\spr_op__insn$4[31:0]$8902 - attribute \src "libresoc.v:160544.3-160559.6" - wire width 7 $0\spr_op__insn_type$2$next[6:0]$8845 - attribute \src "libresoc.v:160463.3-160464.57" - wire width 7 $0\spr_op__insn_type$2[6:0]$8825 - attribute \src "libresoc.v:160302.13-160302.42" - wire width 7 $0\spr_op__insn_type$2[6:0]$8904 - attribute \src "libresoc.v:160544.3-160559.6" - wire $0\spr_op__is_32bit$5$next[0:0]$8846 - attribute \src "libresoc.v:160469.3-160470.55" - wire $0\spr_op__is_32bit$5[0:0]$8831 - attribute \src "libresoc.v:160387.7-160387.34" - wire $0\spr_op__is_32bit$5[0:0]$8906 - attribute \src "libresoc.v:160655.3-160673.6" - wire width 2 $0\xer_ca$10$next[1:0]$8882 - attribute \src "libresoc.v:160439.3-160440.37" - wire width 2 $0\xer_ca$10[1:0]$8808 - attribute \src "libresoc.v:160394.13-160394.31" - wire width 2 $0\xer_ca$10[1:0]$8908 - attribute \src "libresoc.v:160655.3-160673.6" - wire $0\xer_ca_ok$next[0:0]$8883 - attribute \src "libresoc.v:160441.3-160442.35" + attribute \src "libresoc.v:162490.3-162505.6" + wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8888 + attribute \src "libresoc.v:162411.3-162412.53" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8872 + attribute \src "libresoc.v:162081.14-162081.44" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8945 + attribute \src "libresoc.v:162490.3-162505.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8889 + attribute \src "libresoc.v:162413.3-162414.47" + wire width 32 $0\spr_op__insn$4[31:0]$8874 + attribute \src "libresoc.v:162090.14-162090.38" + wire width 32 $0\spr_op__insn$4[31:0]$8947 + attribute \src "libresoc.v:162490.3-162505.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8890 + attribute \src "libresoc.v:162409.3-162410.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8870 + attribute \src "libresoc.v:162247.13-162247.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8949 + attribute \src "libresoc.v:162490.3-162505.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8891 + attribute \src "libresoc.v:162415.3-162416.55" + wire $0\spr_op__is_32bit$5[0:0]$8876 + attribute \src "libresoc.v:162333.7-162333.34" + wire $0\spr_op__is_32bit$5[0:0]$8951 + attribute \src "libresoc.v:162601.3-162619.6" + wire width 2 $0\xer_ca$10$next[1:0]$8927 + attribute \src "libresoc.v:162385.3-162386.37" + wire width 2 $0\xer_ca$10[1:0]$8853 + attribute \src "libresoc.v:162340.13-162340.31" + wire width 2 $0\xer_ca$10[1:0]$8953 + attribute \src "libresoc.v:162601.3-162619.6" + wire $0\xer_ca_ok$next[0:0]$8928 + attribute \src "libresoc.v:162387.3-162388.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:160636.3-160654.6" - wire width 2 $0\xer_ov$9$next[1:0]$8877 - attribute \src "libresoc.v:160443.3-160444.35" - wire width 2 $0\xer_ov$9[1:0]$8811 - attribute \src "libresoc.v:160412.13-160412.30" - wire width 2 $0\xer_ov$9[1:0]$8911 - attribute \src "libresoc.v:160636.3-160654.6" - wire $0\xer_ov_ok$next[0:0]$8876 - attribute \src "libresoc.v:160445.3-160446.35" + attribute \src "libresoc.v:162582.3-162600.6" + wire width 2 $0\xer_ov$9$next[1:0]$8922 + attribute \src "libresoc.v:162389.3-162390.35" + wire width 2 $0\xer_ov$9[1:0]$8856 + attribute \src "libresoc.v:162358.13-162358.30" + wire width 2 $0\xer_ov$9[1:0]$8956 + attribute \src "libresoc.v:162582.3-162600.6" + wire $0\xer_ov_ok$next[0:0]$8921 + attribute \src "libresoc.v:162391.3-162392.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:160617.3-160635.6" - wire $0\xer_so$8$next[0:0]$8871 - attribute \src "libresoc.v:160447.3-160448.35" - wire $0\xer_so$8[0:0]$8814 - attribute \src "libresoc.v:160428.7-160428.24" - wire $0\xer_so$8[0:0]$8914 - attribute \src "libresoc.v:160617.3-160635.6" - wire $0\xer_so_ok$next[0:0]$8870 - attribute \src "libresoc.v:160449.3-160450.35" + attribute \src "libresoc.v:162563.3-162581.6" + wire $0\xer_so$8$next[0:0]$8916 + attribute \src "libresoc.v:162393.3-162394.35" + wire $0\xer_so$8[0:0]$8859 + attribute \src "libresoc.v:162374.7-162374.24" + wire $0\xer_so$8[0:0]$8959 + attribute \src "libresoc.v:162563.3-162581.6" + wire $0\xer_so_ok$next[0:0]$8915 + attribute \src "libresoc.v:162395.3-162396.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:160598.3-160616.6" - wire width 64 $1\fast1$7$next[63:0]$8867 - attribute \src "libresoc.v:160598.3-160616.6" - wire $1\fast1_ok$next[0:0]$8866 - attribute \src "libresoc.v:159794.7-159794.22" + attribute \src "libresoc.v:162544.3-162562.6" + wire width 64 $1\fast1$7$next[63:0]$8912 + attribute \src "libresoc.v:162544.3-162562.6" + wire $1\fast1_ok$next[0:0]$8911 + attribute \src "libresoc.v:161730.7-161730.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:160531.3-160543.6" - wire width 2 $1\muxid$1$next[1:0]$8841 - attribute \src "libresoc.v:160560.3-160578.6" - wire width 64 $1\o$next[63:0]$8854 - attribute \src "libresoc.v:159816.14-159816.38" + attribute \src "libresoc.v:162477.3-162489.6" + wire width 2 $1\muxid$1$next[1:0]$8886 + attribute \src "libresoc.v:162506.3-162524.6" + wire width 64 $1\o$next[63:0]$8899 + attribute \src "libresoc.v:161752.14-161752.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:160560.3-160578.6" - wire $1\o_ok$next[0:0]$8855 - attribute \src "libresoc.v:159823.7-159823.18" + attribute \src "libresoc.v:162506.3-162524.6" + wire $1\o_ok$next[0:0]$8900 + attribute \src "libresoc.v:161759.7-161759.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:160513.3-160530.6" - wire $1\r_busy$next[0:0]$8837 - attribute \src "libresoc.v:159837.7-159837.20" + attribute \src "libresoc.v:162459.3-162476.6" + wire $1\r_busy$next[0:0]$8882 + attribute \src "libresoc.v:161773.7-161773.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:160579.3-160597.6" - wire width 64 $1\spr1$6$next[63:0]$8860 - attribute \src "libresoc.v:160579.3-160597.6" - wire $1\spr1_ok$next[0:0]$8861 - attribute \src "libresoc.v:159853.7-159853.21" + attribute \src "libresoc.v:162525.3-162543.6" + wire width 64 $1\spr1$6$next[63:0]$8905 + attribute \src "libresoc.v:162525.3-162543.6" + wire $1\spr1_ok$next[0:0]$8906 + attribute \src "libresoc.v:161789.7-161789.21" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:160544.3-160559.6" - wire width 13 $1\spr_op__fn_unit$3$next[12:0]$8847 - attribute \src "libresoc.v:160544.3-160559.6" - wire width 32 $1\spr_op__insn$4$next[31:0]$8848 - attribute \src "libresoc.v:160544.3-160559.6" - wire width 7 $1\spr_op__insn_type$2$next[6:0]$8849 - attribute \src "libresoc.v:160544.3-160559.6" - wire $1\spr_op__is_32bit$5$next[0:0]$8850 - attribute \src "libresoc.v:160655.3-160673.6" - wire width 2 $1\xer_ca$10$next[1:0]$8884 - attribute \src "libresoc.v:160655.3-160673.6" - wire $1\xer_ca_ok$next[0:0]$8885 - attribute \src "libresoc.v:160401.7-160401.23" + attribute \src "libresoc.v:162490.3-162505.6" + wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8892 + attribute \src "libresoc.v:162490.3-162505.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8893 + attribute \src "libresoc.v:162490.3-162505.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8894 + attribute \src "libresoc.v:162490.3-162505.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8895 + attribute \src "libresoc.v:162601.3-162619.6" + wire width 2 $1\xer_ca$10$next[1:0]$8929 + attribute \src "libresoc.v:162601.3-162619.6" + wire $1\xer_ca_ok$next[0:0]$8930 + attribute \src "libresoc.v:162347.7-162347.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:160636.3-160654.6" - wire width 2 $1\xer_ov$9$next[1:0]$8879 - attribute \src "libresoc.v:160636.3-160654.6" - wire $1\xer_ov_ok$next[0:0]$8878 - attribute \src "libresoc.v:160417.7-160417.23" + attribute \src "libresoc.v:162582.3-162600.6" + wire width 2 $1\xer_ov$9$next[1:0]$8924 + attribute \src "libresoc.v:162582.3-162600.6" + wire $1\xer_ov_ok$next[0:0]$8923 + attribute \src "libresoc.v:162363.7-162363.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:160617.3-160635.6" - wire $1\xer_so$8$next[0:0]$8873 - attribute \src "libresoc.v:160617.3-160635.6" - wire $1\xer_so_ok$next[0:0]$8872 - attribute \src "libresoc.v:160433.7-160433.23" + attribute \src "libresoc.v:162563.3-162581.6" + wire $1\xer_so$8$next[0:0]$8918 + attribute \src "libresoc.v:162563.3-162581.6" + wire $1\xer_so_ok$next[0:0]$8917 + attribute \src "libresoc.v:162379.7-162379.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:160598.3-160616.6" - wire $2\fast1_ok$next[0:0]$8868 - attribute \src "libresoc.v:160560.3-160578.6" - wire $2\o_ok$next[0:0]$8856 - attribute \src "libresoc.v:160513.3-160530.6" - wire $2\r_busy$next[0:0]$8838 - attribute \src "libresoc.v:160579.3-160597.6" - wire $2\spr1_ok$next[0:0]$8862 - attribute \src "libresoc.v:160655.3-160673.6" - wire $2\xer_ca_ok$next[0:0]$8886 - attribute \src "libresoc.v:160636.3-160654.6" - wire $2\xer_ov_ok$next[0:0]$8880 - attribute \src "libresoc.v:160617.3-160635.6" - wire $2\xer_so_ok$next[0:0]$8874 - attribute \src "libresoc.v:160438.18-160438.118" - wire $and$libresoc.v:160438$8806_Y + attribute \src "libresoc.v:162544.3-162562.6" + wire $2\fast1_ok$next[0:0]$8913 + attribute \src "libresoc.v:162506.3-162524.6" + wire $2\o_ok$next[0:0]$8901 + attribute \src "libresoc.v:162459.3-162476.6" + wire $2\r_busy$next[0:0]$8883 + attribute \src "libresoc.v:162525.3-162543.6" + wire $2\spr1_ok$next[0:0]$8907 + attribute \src "libresoc.v:162601.3-162619.6" + wire $2\xer_ca_ok$next[0:0]$8931 + attribute \src "libresoc.v:162582.3-162600.6" + wire $2\xer_ov_ok$next[0:0]$8925 + attribute \src "libresoc.v:162563.3-162581.6" + wire $2\xer_so_ok$next[0:0]$8919 + attribute \src "libresoc.v:162384.18-162384.118" + wire $and$libresoc.v:162384$8851_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \fast1 @@ -333588,7 +336219,7 @@ module \pipe$64 wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast1_ok$next - attribute \src "libresoc.v:159776.7-159776.15" + attribute \src "libresoc.v:161712.7-161712.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -333667,37 +336298,39 @@ module \pipe$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \spr_main_spr1_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_main_spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_main_spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_main_spr_op__fn_unit$13 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_main_spr_op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \spr_main_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -333776,6 +336409,7 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_main_spr_op__insn_type attribute \enum_base_type "MicrOp" @@ -333852,6 +336486,7 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_main_spr_op__insn_type$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -333877,55 +336512,58 @@ module \pipe$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \spr_main_xer_so_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_op__fn_unit$26 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_op__fn_unit$26 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 19 \spr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 19 \spr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \spr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 7 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -334008,6 +336646,7 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \spr_op__insn_type attribute \enum_base_type "MicrOp" @@ -334084,6 +336723,7 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 18 \spr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -334162,6 +336802,7 @@ module \pipe$64 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -334215,7 +336856,7 @@ module \pipe$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:160438$8806 + cell $and $and$libresoc.v:162384$8851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334223,22 +336864,22 @@ module \pipe$64 parameter \Y_WIDTH 1 connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:160438$8806_Y + connect \Y $and$libresoc.v:162384$8851_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:160475.10-160478.4" + attribute \src "libresoc.v:162421.10-162424.4" cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:160479.10-160482.4" + attribute \src "libresoc.v:162425.10-162428.4" cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:160483.12-160512.4" + attribute \src "libresoc.v:162429.12-162458.4" cell \spr_main \spr_main connect \fast1 \spr_main_fast1 connect \fast1$7 \spr_main_fast1$17 @@ -334269,293 +336910,293 @@ module \pipe$64 connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok end - attribute \src "libresoc.v:159776.7-159776.20" - process $proc$libresoc.v:159776$8887 + attribute \src "libresoc.v:161712.7-161712.20" + process $proc$libresoc.v:161712$8932 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159789.14-159789.46" - process $proc$libresoc.v:159789$8888 + attribute \src "libresoc.v:161725.14-161725.46" + process $proc$libresoc.v:161725$8933 assign { } { } - assign $0\fast1$7[63:0]$8889 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$7[63:0]$8934 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$7 $0\fast1$7[63:0]$8889 + update \fast1$7 $0\fast1$7[63:0]$8934 end - attribute \src "libresoc.v:159794.7-159794.22" - process $proc$libresoc.v:159794$8890 + attribute \src "libresoc.v:161730.7-161730.22" + process $proc$libresoc.v:161730$8935 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:159803.13-159803.29" - process $proc$libresoc.v:159803$8891 + attribute \src "libresoc.v:161739.13-161739.29" + process $proc$libresoc.v:161739$8936 assign { } { } - assign $0\muxid$1[1:0]$8892 2'00 + assign $0\muxid$1[1:0]$8937 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8892 + update \muxid$1 $0\muxid$1[1:0]$8937 end - attribute \src "libresoc.v:159816.14-159816.38" - process $proc$libresoc.v:159816$8893 + attribute \src "libresoc.v:161752.14-161752.38" + process $proc$libresoc.v:161752$8938 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:159823.7-159823.18" - process $proc$libresoc.v:159823$8894 + attribute \src "libresoc.v:161759.7-161759.18" + process $proc$libresoc.v:161759$8939 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:159837.7-159837.20" - process $proc$libresoc.v:159837$8895 + attribute \src "libresoc.v:161773.7-161773.20" + process $proc$libresoc.v:161773$8940 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:159848.14-159848.45" - process $proc$libresoc.v:159848$8896 + attribute \src "libresoc.v:161784.14-161784.45" + process $proc$libresoc.v:161784$8941 assign { } { } - assign $0\spr1$6[63:0]$8897 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\spr1$6[63:0]$8942 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \spr1$6 $0\spr1$6[63:0]$8897 + update \spr1$6 $0\spr1$6[63:0]$8942 end - attribute \src "libresoc.v:159853.7-159853.21" - process $proc$libresoc.v:159853$8898 + attribute \src "libresoc.v:161789.7-161789.21" + process $proc$libresoc.v:161789$8943 assign { } { } assign $1\spr1_ok[0:0] 1'0 sync always sync init update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:160138.14-160138.44" - process $proc$libresoc.v:160138$8899 + attribute \src "libresoc.v:162081.14-162081.44" + process $proc$libresoc.v:162081$8944 assign { } { } - assign $0\spr_op__fn_unit$3[12:0]$8900 13'0000000000000 + assign $0\spr_op__fn_unit$3[13:0]$8945 14'00000000000000 sync always sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8900 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8945 end - attribute \src "libresoc.v:160147.14-160147.38" - process $proc$libresoc.v:160147$8901 + attribute \src "libresoc.v:162090.14-162090.38" + process $proc$libresoc.v:162090$8946 assign { } { } - assign $0\spr_op__insn$4[31:0]$8902 0 + assign $0\spr_op__insn$4[31:0]$8947 0 sync always sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8902 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8947 end - attribute \src "libresoc.v:160302.13-160302.42" - process $proc$libresoc.v:160302$8903 + attribute \src "libresoc.v:162247.13-162247.42" + process $proc$libresoc.v:162247$8948 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8904 7'0000000 + assign $0\spr_op__insn_type$2[6:0]$8949 7'0000000 sync always sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8904 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8949 end - attribute \src "libresoc.v:160387.7-160387.34" - process $proc$libresoc.v:160387$8905 + attribute \src "libresoc.v:162333.7-162333.34" + process $proc$libresoc.v:162333$8950 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8906 1'0 + assign $0\spr_op__is_32bit$5[0:0]$8951 1'0 sync always sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8906 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8951 end - attribute \src "libresoc.v:160394.13-160394.31" - process $proc$libresoc.v:160394$8907 + attribute \src "libresoc.v:162340.13-162340.31" + process $proc$libresoc.v:162340$8952 assign { } { } - assign $0\xer_ca$10[1:0]$8908 2'00 + assign $0\xer_ca$10[1:0]$8953 2'00 sync always sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$8908 + update \xer_ca$10 $0\xer_ca$10[1:0]$8953 end - attribute \src "libresoc.v:160401.7-160401.23" - process $proc$libresoc.v:160401$8909 + attribute \src "libresoc.v:162347.7-162347.23" + process $proc$libresoc.v:162347$8954 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:160412.13-160412.30" - process $proc$libresoc.v:160412$8910 + attribute \src "libresoc.v:162358.13-162358.30" + process $proc$libresoc.v:162358$8955 assign { } { } - assign $0\xer_ov$9[1:0]$8911 2'00 + assign $0\xer_ov$9[1:0]$8956 2'00 sync always sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$8911 + update \xer_ov$9 $0\xer_ov$9[1:0]$8956 end - attribute \src "libresoc.v:160417.7-160417.23" - process $proc$libresoc.v:160417$8912 + attribute \src "libresoc.v:162363.7-162363.23" + process $proc$libresoc.v:162363$8957 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:160428.7-160428.24" - process $proc$libresoc.v:160428$8913 + attribute \src "libresoc.v:162374.7-162374.24" + process $proc$libresoc.v:162374$8958 assign { } { } - assign $0\xer_so$8[0:0]$8914 1'0 + assign $0\xer_so$8[0:0]$8959 1'0 sync always sync init - update \xer_so$8 $0\xer_so$8[0:0]$8914 + update \xer_so$8 $0\xer_so$8[0:0]$8959 end - attribute \src "libresoc.v:160433.7-160433.23" - process $proc$libresoc.v:160433$8915 + attribute \src "libresoc.v:162379.7-162379.23" + process $proc$libresoc.v:162379$8960 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:160439.3-160440.37" - process $proc$libresoc.v:160439$8807 + attribute \src "libresoc.v:162385.3-162386.37" + process $proc$libresoc.v:162385$8852 assign { } { } - assign $0\xer_ca$10[1:0]$8808 \xer_ca$10$next + assign $0\xer_ca$10[1:0]$8853 \xer_ca$10$next sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8808 + update \xer_ca$10 $0\xer_ca$10[1:0]$8853 end - attribute \src "libresoc.v:160441.3-160442.35" - process $proc$libresoc.v:160441$8809 + attribute \src "libresoc.v:162387.3-162388.35" + process $proc$libresoc.v:162387$8854 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:160443.3-160444.35" - process $proc$libresoc.v:160443$8810 + attribute \src "libresoc.v:162389.3-162390.35" + process $proc$libresoc.v:162389$8855 assign { } { } - assign $0\xer_ov$9[1:0]$8811 \xer_ov$9$next + assign $0\xer_ov$9[1:0]$8856 \xer_ov$9$next sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8811 + update \xer_ov$9 $0\xer_ov$9[1:0]$8856 end - attribute \src "libresoc.v:160445.3-160446.35" - process $proc$libresoc.v:160445$8812 + attribute \src "libresoc.v:162391.3-162392.35" + process $proc$libresoc.v:162391$8857 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:160447.3-160448.35" - process $proc$libresoc.v:160447$8813 + attribute \src "libresoc.v:162393.3-162394.35" + process $proc$libresoc.v:162393$8858 assign { } { } - assign $0\xer_so$8[0:0]$8814 \xer_so$8$next + assign $0\xer_so$8[0:0]$8859 \xer_so$8$next sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8814 + update \xer_so$8 $0\xer_so$8[0:0]$8859 end - attribute \src "libresoc.v:160449.3-160450.35" - process $proc$libresoc.v:160449$8815 + attribute \src "libresoc.v:162395.3-162396.35" + process $proc$libresoc.v:162395$8860 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:160451.3-160452.33" - process $proc$libresoc.v:160451$8816 + attribute \src "libresoc.v:162397.3-162398.33" + process $proc$libresoc.v:162397$8861 assign { } { } - assign $0\fast1$7[63:0]$8817 \fast1$7$next + assign $0\fast1$7[63:0]$8862 \fast1$7$next sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8817 + update \fast1$7 $0\fast1$7[63:0]$8862 end - attribute \src "libresoc.v:160453.3-160454.33" - process $proc$libresoc.v:160453$8818 + attribute \src "libresoc.v:162399.3-162400.33" + process $proc$libresoc.v:162399$8863 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:160455.3-160456.31" - process $proc$libresoc.v:160455$8819 + attribute \src "libresoc.v:162401.3-162402.31" + process $proc$libresoc.v:162401$8864 assign { } { } - assign $0\spr1$6[63:0]$8820 \spr1$6$next + assign $0\spr1$6[63:0]$8865 \spr1$6$next sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8820 + update \spr1$6 $0\spr1$6[63:0]$8865 end - attribute \src "libresoc.v:160457.3-160458.31" - process $proc$libresoc.v:160457$8821 + attribute \src "libresoc.v:162403.3-162404.31" + process $proc$libresoc.v:162403$8866 assign { } { } assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:160459.3-160460.19" - process $proc$libresoc.v:160459$8822 + attribute \src "libresoc.v:162405.3-162406.19" + process $proc$libresoc.v:162405$8867 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:160461.3-160462.25" - process $proc$libresoc.v:160461$8823 + attribute \src "libresoc.v:162407.3-162408.25" + process $proc$libresoc.v:162407$8868 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:160463.3-160464.57" - process $proc$libresoc.v:160463$8824 + attribute \src "libresoc.v:162409.3-162410.57" + process $proc$libresoc.v:162409$8869 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8825 \spr_op__insn_type$2$next + assign $0\spr_op__insn_type$2[6:0]$8870 \spr_op__insn_type$2$next sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8825 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8870 end - attribute \src "libresoc.v:160465.3-160466.53" - process $proc$libresoc.v:160465$8826 + attribute \src "libresoc.v:162411.3-162412.53" + process $proc$libresoc.v:162411$8871 assign { } { } - assign $0\spr_op__fn_unit$3[12:0]$8827 \spr_op__fn_unit$3$next + assign $0\spr_op__fn_unit$3[13:0]$8872 \spr_op__fn_unit$3$next sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8827 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8872 end - attribute \src "libresoc.v:160467.3-160468.47" - process $proc$libresoc.v:160467$8828 + attribute \src "libresoc.v:162413.3-162414.47" + process $proc$libresoc.v:162413$8873 assign { } { } - assign $0\spr_op__insn$4[31:0]$8829 \spr_op__insn$4$next + assign $0\spr_op__insn$4[31:0]$8874 \spr_op__insn$4$next sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8829 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8874 end - attribute \src "libresoc.v:160469.3-160470.55" - process $proc$libresoc.v:160469$8830 + attribute \src "libresoc.v:162415.3-162416.55" + process $proc$libresoc.v:162415$8875 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8831 \spr_op__is_32bit$5$next + assign $0\spr_op__is_32bit$5[0:0]$8876 \spr_op__is_32bit$5$next sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8831 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8876 end - attribute \src "libresoc.v:160471.3-160472.33" - process $proc$libresoc.v:160471$8832 + attribute \src "libresoc.v:162417.3-162418.33" + process $proc$libresoc.v:162417$8877 assign { } { } - assign $0\muxid$1[1:0]$8833 \muxid$1$next + assign $0\muxid$1[1:0]$8878 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8833 + update \muxid$1 $0\muxid$1[1:0]$8878 end - attribute \src "libresoc.v:160473.3-160474.29" - process $proc$libresoc.v:160473$8834 + attribute \src "libresoc.v:162419.3-162420.29" + process $proc$libresoc.v:162419$8879 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:160513.3-160530.6" - process $proc$libresoc.v:160513$8835 + attribute \src "libresoc.v:162459.3-162476.6" + process $proc$libresoc.v:162459$8880 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8836 $2\r_busy$next[0:0]$8838 - attribute \src "libresoc.v:160514.5-160514.29" + assign $0\r_busy$next[0:0]$8881 $2\r_busy$next[0:0]$8883 + attribute \src "libresoc.v:162460.5-162460.29" switch \initial - attribute \src "libresoc.v:160514.9-160514.17" + attribute \src "libresoc.v:162460.9-162460.17" case 1'1 case end @@ -334564,34 +337205,34 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8837 1'1 + assign $1\r_busy$next[0:0]$8882 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8837 1'0 + assign $1\r_busy$next[0:0]$8882 1'0 case - assign $1\r_busy$next[0:0]$8837 \r_busy + assign $1\r_busy$next[0:0]$8882 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8838 1'0 + assign $2\r_busy$next[0:0]$8883 1'0 case - assign $2\r_busy$next[0:0]$8838 $1\r_busy$next[0:0]$8837 + assign $2\r_busy$next[0:0]$8883 $1\r_busy$next[0:0]$8882 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8836 + update \r_busy$next $0\r_busy$next[0:0]$8881 end - attribute \src "libresoc.v:160531.3-160543.6" - process $proc$libresoc.v:160531$8839 + attribute \src "libresoc.v:162477.3-162489.6" + process $proc$libresoc.v:162477$8884 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8840 $1\muxid$1$next[1:0]$8841 - attribute \src "libresoc.v:160532.5-160532.29" + assign $0\muxid$1$next[1:0]$8885 $1\muxid$1$next[1:0]$8886 + attribute \src "libresoc.v:162478.5-162478.29" switch \initial - attribute \src "libresoc.v:160532.9-160532.17" + attribute \src "libresoc.v:162478.9-162478.17" case 1'1 case end @@ -334600,19 +337241,19 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8841 \muxid$24 + assign $1\muxid$1$next[1:0]$8886 \muxid$24 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8841 \muxid$24 + assign $1\muxid$1$next[1:0]$8886 \muxid$24 case - assign $1\muxid$1$next[1:0]$8841 \muxid$1 + assign $1\muxid$1$next[1:0]$8886 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8840 + update \muxid$1$next $0\muxid$1$next[1:0]$8885 end - attribute \src "libresoc.v:160544.3-160559.6" - process $proc$libresoc.v:160544$8842 + attribute \src "libresoc.v:162490.3-162505.6" + process $proc$libresoc.v:162490$8887 assign { } { } assign { } { } assign { } { } @@ -334621,13 +337262,13 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign $0\spr_op__fn_unit$3$next[12:0]$8843 $1\spr_op__fn_unit$3$next[12:0]$8847 - assign $0\spr_op__insn$4$next[31:0]$8844 $1\spr_op__insn$4$next[31:0]$8848 - assign $0\spr_op__insn_type$2$next[6:0]$8845 $1\spr_op__insn_type$2$next[6:0]$8849 - assign $0\spr_op__is_32bit$5$next[0:0]$8846 $1\spr_op__is_32bit$5$next[0:0]$8850 - attribute \src "libresoc.v:160545.5-160545.29" + assign $0\spr_op__fn_unit$3$next[13:0]$8888 $1\spr_op__fn_unit$3$next[13:0]$8892 + assign $0\spr_op__insn$4$next[31:0]$8889 $1\spr_op__insn$4$next[31:0]$8893 + assign $0\spr_op__insn_type$2$next[6:0]$8890 $1\spr_op__insn_type$2$next[6:0]$8894 + assign $0\spr_op__is_32bit$5$next[0:0]$8891 $1\spr_op__is_32bit$5$next[0:0]$8895 + attribute \src "libresoc.v:162491.5-162491.29" switch \initial - attribute \src "libresoc.v:160545.9-160545.17" + attribute \src "libresoc.v:162491.9-162491.17" case 1'1 case end @@ -334639,38 +337280,38 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8850 $1\spr_op__insn$4$next[31:0]$8848 $1\spr_op__fn_unit$3$next[12:0]$8847 $1\spr_op__insn_type$2$next[6:0]$8849 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8895 $1\spr_op__insn$4$next[31:0]$8893 $1\spr_op__fn_unit$3$next[13:0]$8892 $1\spr_op__insn_type$2$next[6:0]$8894 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8850 $1\spr_op__insn$4$next[31:0]$8848 $1\spr_op__fn_unit$3$next[12:0]$8847 $1\spr_op__insn_type$2$next[6:0]$8849 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8895 $1\spr_op__insn$4$next[31:0]$8893 $1\spr_op__fn_unit$3$next[13:0]$8892 $1\spr_op__insn_type$2$next[6:0]$8894 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } case - assign $1\spr_op__fn_unit$3$next[12:0]$8847 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8848 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8849 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8850 \spr_op__is_32bit$5 + assign $1\spr_op__fn_unit$3$next[13:0]$8892 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8893 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8894 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8895 \spr_op__is_32bit$5 end sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[12:0]$8843 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8844 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8845 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8846 + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8888 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8889 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8890 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8891 end - attribute \src "libresoc.v:160560.3-160578.6" - process $proc$libresoc.v:160560$8851 + attribute \src "libresoc.v:162506.3-162524.6" + process $proc$libresoc.v:162506$8896 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8852 $1\o$next[63:0]$8854 + assign $0\o$next[63:0]$8897 $1\o$next[63:0]$8899 assign { } { } - assign $0\o_ok$next[0:0]$8853 $2\o_ok$next[0:0]$8856 - attribute \src "libresoc.v:160561.5-160561.29" + assign $0\o_ok$next[0:0]$8898 $2\o_ok$next[0:0]$8901 + attribute \src "libresoc.v:162507.5-162507.29" switch \initial - attribute \src "libresoc.v:160561.9-160561.17" + attribute \src "libresoc.v:162507.9-162507.17" case 1'1 case end @@ -334680,41 +337321,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8855 $1\o$next[63:0]$8854 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8900 $1\o$next[63:0]$8899 } { \o_ok$30 \o$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8855 $1\o$next[63:0]$8854 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8900 $1\o$next[63:0]$8899 } { \o_ok$30 \o$29 } case - assign $1\o$next[63:0]$8854 \o - assign $1\o_ok$next[0:0]$8855 \o_ok + assign $1\o$next[63:0]$8899 \o + assign $1\o_ok$next[0:0]$8900 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8856 1'0 + assign $2\o_ok$next[0:0]$8901 1'0 case - assign $2\o_ok$next[0:0]$8856 $1\o_ok$next[0:0]$8855 + assign $2\o_ok$next[0:0]$8901 $1\o_ok$next[0:0]$8900 end sync always - update \o$next $0\o$next[63:0]$8852 - update \o_ok$next $0\o_ok$next[0:0]$8853 + update \o$next $0\o$next[63:0]$8897 + update \o_ok$next $0\o_ok$next[0:0]$8898 end - attribute \src "libresoc.v:160579.3-160597.6" - process $proc$libresoc.v:160579$8857 + attribute \src "libresoc.v:162525.3-162543.6" + process $proc$libresoc.v:162525$8902 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\spr1$6$next[63:0]$8858 $1\spr1$6$next[63:0]$8860 + assign $0\spr1$6$next[63:0]$8903 $1\spr1$6$next[63:0]$8905 assign { } { } - assign $0\spr1_ok$next[0:0]$8859 $2\spr1_ok$next[0:0]$8862 - attribute \src "libresoc.v:160580.5-160580.29" + assign $0\spr1_ok$next[0:0]$8904 $2\spr1_ok$next[0:0]$8907 + attribute \src "libresoc.v:162526.5-162526.29" switch \initial - attribute \src "libresoc.v:160580.9-160580.17" + attribute \src "libresoc.v:162526.9-162526.17" case 1'1 case end @@ -334724,41 +337365,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8861 $1\spr1$6$next[63:0]$8860 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8906 $1\spr1$6$next[63:0]$8905 } { \spr1_ok$32 \spr1$31 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8861 $1\spr1$6$next[63:0]$8860 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8906 $1\spr1$6$next[63:0]$8905 } { \spr1_ok$32 \spr1$31 } case - assign $1\spr1$6$next[63:0]$8860 \spr1$6 - assign $1\spr1_ok$next[0:0]$8861 \spr1_ok + assign $1\spr1$6$next[63:0]$8905 \spr1$6 + assign $1\spr1_ok$next[0:0]$8906 \spr1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\spr1_ok$next[0:0]$8862 1'0 + assign $2\spr1_ok$next[0:0]$8907 1'0 case - assign $2\spr1_ok$next[0:0]$8862 $1\spr1_ok$next[0:0]$8861 + assign $2\spr1_ok$next[0:0]$8907 $1\spr1_ok$next[0:0]$8906 end sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8858 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8859 + update \spr1$6$next $0\spr1$6$next[63:0]$8903 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8904 end - attribute \src "libresoc.v:160598.3-160616.6" - process $proc$libresoc.v:160598$8863 + attribute \src "libresoc.v:162544.3-162562.6" + process $proc$libresoc.v:162544$8908 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$7$next[63:0]$8865 $1\fast1$7$next[63:0]$8867 - assign $0\fast1_ok$next[0:0]$8864 $2\fast1_ok$next[0:0]$8868 - attribute \src "libresoc.v:160599.5-160599.29" + assign $0\fast1$7$next[63:0]$8910 $1\fast1$7$next[63:0]$8912 + assign $0\fast1_ok$next[0:0]$8909 $2\fast1_ok$next[0:0]$8913 + attribute \src "libresoc.v:162545.5-162545.29" switch \initial - attribute \src "libresoc.v:160599.9-160599.17" + attribute \src "libresoc.v:162545.9-162545.17" case 1'1 case end @@ -334768,41 +337409,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8866 $1\fast1$7$next[63:0]$8867 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8911 $1\fast1$7$next[63:0]$8912 } { \fast1_ok$34 \fast1$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8866 $1\fast1$7$next[63:0]$8867 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8911 $1\fast1$7$next[63:0]$8912 } { \fast1_ok$34 \fast1$33 } case - assign $1\fast1_ok$next[0:0]$8866 \fast1_ok - assign $1\fast1$7$next[63:0]$8867 \fast1$7 + assign $1\fast1_ok$next[0:0]$8911 \fast1_ok + assign $1\fast1$7$next[63:0]$8912 \fast1$7 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8868 1'0 + assign $2\fast1_ok$next[0:0]$8913 1'0 case - assign $2\fast1_ok$next[0:0]$8868 $1\fast1_ok$next[0:0]$8866 + assign $2\fast1_ok$next[0:0]$8913 $1\fast1_ok$next[0:0]$8911 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8864 - update \fast1$7$next $0\fast1$7$next[63:0]$8865 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8909 + update \fast1$7$next $0\fast1$7$next[63:0]$8910 end - attribute \src "libresoc.v:160617.3-160635.6" - process $proc$libresoc.v:160617$8869 + attribute \src "libresoc.v:162563.3-162581.6" + process $proc$libresoc.v:162563$8914 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$8$next[0:0]$8871 $1\xer_so$8$next[0:0]$8873 - assign $0\xer_so_ok$next[0:0]$8870 $2\xer_so_ok$next[0:0]$8874 - attribute \src "libresoc.v:160618.5-160618.29" + assign $0\xer_so$8$next[0:0]$8916 $1\xer_so$8$next[0:0]$8918 + assign $0\xer_so_ok$next[0:0]$8915 $2\xer_so_ok$next[0:0]$8919 + attribute \src "libresoc.v:162564.5-162564.29" switch \initial - attribute \src "libresoc.v:160618.9-160618.17" + attribute \src "libresoc.v:162564.9-162564.17" case 1'1 case end @@ -334812,41 +337453,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8872 $1\xer_so$8$next[0:0]$8873 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8917 $1\xer_so$8$next[0:0]$8918 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8872 $1\xer_so$8$next[0:0]$8873 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8917 $1\xer_so$8$next[0:0]$8918 } { \xer_so_ok$36 \xer_so$35 } case - assign $1\xer_so_ok$next[0:0]$8872 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8873 \xer_so$8 + assign $1\xer_so_ok$next[0:0]$8917 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8918 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8874 1'0 + assign $2\xer_so_ok$next[0:0]$8919 1'0 case - assign $2\xer_so_ok$next[0:0]$8874 $1\xer_so_ok$next[0:0]$8872 + assign $2\xer_so_ok$next[0:0]$8919 $1\xer_so_ok$next[0:0]$8917 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8870 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8871 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8915 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8916 end - attribute \src "libresoc.v:160636.3-160654.6" - process $proc$libresoc.v:160636$8875 + attribute \src "libresoc.v:162582.3-162600.6" + process $proc$libresoc.v:162582$8920 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$9$next[1:0]$8877 $1\xer_ov$9$next[1:0]$8879 - assign $0\xer_ov_ok$next[0:0]$8876 $2\xer_ov_ok$next[0:0]$8880 - attribute \src "libresoc.v:160637.5-160637.29" + assign $0\xer_ov$9$next[1:0]$8922 $1\xer_ov$9$next[1:0]$8924 + assign $0\xer_ov_ok$next[0:0]$8921 $2\xer_ov_ok$next[0:0]$8925 + attribute \src "libresoc.v:162583.5-162583.29" switch \initial - attribute \src "libresoc.v:160637.9-160637.17" + attribute \src "libresoc.v:162583.9-162583.17" case 1'1 case end @@ -334856,41 +337497,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8878 $1\xer_ov$9$next[1:0]$8879 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8923 $1\xer_ov$9$next[1:0]$8924 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8878 $1\xer_ov$9$next[1:0]$8879 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8923 $1\xer_ov$9$next[1:0]$8924 } { \xer_ov_ok$38 \xer_ov$37 } case - assign $1\xer_ov_ok$next[0:0]$8878 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8879 \xer_ov$9 + assign $1\xer_ov_ok$next[0:0]$8923 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8924 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8880 1'0 + assign $2\xer_ov_ok$next[0:0]$8925 1'0 case - assign $2\xer_ov_ok$next[0:0]$8880 $1\xer_ov_ok$next[0:0]$8878 + assign $2\xer_ov_ok$next[0:0]$8925 $1\xer_ov_ok$next[0:0]$8923 end sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8876 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8877 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8921 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8922 end - attribute \src "libresoc.v:160655.3-160673.6" - process $proc$libresoc.v:160655$8881 + attribute \src "libresoc.v:162601.3-162619.6" + process $proc$libresoc.v:162601$8926 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$10$next[1:0]$8882 $1\xer_ca$10$next[1:0]$8884 + assign $0\xer_ca$10$next[1:0]$8927 $1\xer_ca$10$next[1:0]$8929 assign { } { } - assign $0\xer_ca_ok$next[0:0]$8883 $2\xer_ca_ok$next[0:0]$8886 - attribute \src "libresoc.v:160656.5-160656.29" + assign $0\xer_ca_ok$next[0:0]$8928 $2\xer_ca_ok$next[0:0]$8931 + attribute \src "libresoc.v:162602.5-162602.29" switch \initial - attribute \src "libresoc.v:160656.9-160656.17" + attribute \src "libresoc.v:162602.9-162602.17" case 1'1 case end @@ -334900,30 +337541,30 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8885 $1\xer_ca$10$next[1:0]$8884 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8930 $1\xer_ca$10$next[1:0]$8929 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8885 $1\xer_ca$10$next[1:0]$8884 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8930 $1\xer_ca$10$next[1:0]$8929 } { \xer_ca_ok$40 \xer_ca$39 } case - assign $1\xer_ca$10$next[1:0]$8884 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8885 \xer_ca_ok + assign $1\xer_ca$10$next[1:0]$8929 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8930 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8886 1'0 + assign $2\xer_ca_ok$next[0:0]$8931 1'0 case - assign $2\xer_ca_ok$next[0:0]$8886 $1\xer_ca_ok$next[0:0]$8885 + assign $2\xer_ca_ok$next[0:0]$8931 $1\xer_ca_ok$next[0:0]$8930 end sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8882 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8883 + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8927 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8928 end - connect \$22 $and$libresoc.v:160438$8806_Y + connect \$22 $and$libresoc.v:162384$8851_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } @@ -334946,279 +337587,279 @@ module \pipe$64 connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:160699.1-162177.10" +attribute \src "libresoc.v:162645.1-164137.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" module \pipe1 - attribute \src "libresoc.v:162091.3-162132.6" - wire width 4 $0\alu_op__data_len$next[3:0]$8979 - attribute \src "libresoc.v:161867.3-161868.49" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9024 + attribute \src "libresoc.v:163827.3-163828.49" wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 13 $0\alu_op__fn_unit$next[12:0]$8980 - attribute \src "libresoc.v:161837.3-161838.47" - wire width 13 $0\alu_op__fn_unit[12:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$8981 - attribute \src "libresoc.v:161839.3-161840.61" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 14 $0\alu_op__fn_unit$next[13:0]$9025 + attribute \src "libresoc.v:163797.3-163798.47" + wire width 14 $0\alu_op__fn_unit[13:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9026 + attribute \src "libresoc.v:163799.3-163800.61" wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__imm_data__ok$next[0:0]$8982 - attribute \src "libresoc.v:161841.3-161842.57" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9027 + attribute \src "libresoc.v:163801.3-163802.57" wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$8983 - attribute \src "libresoc.v:161859.3-161860.55" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9028 + attribute \src "libresoc.v:163819.3-163820.55" wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 32 $0\alu_op__insn$next[31:0]$8984 - attribute \src "libresoc.v:161869.3-161870.41" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 32 $0\alu_op__insn$next[31:0]$9029 + attribute \src "libresoc.v:163829.3-163830.41" wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$8985 - attribute \src "libresoc.v:161835.3-161836.51" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9030 + attribute \src "libresoc.v:163795.3-163796.51" wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__invert_in$next[0:0]$8986 - attribute \src "libresoc.v:161851.3-161852.51" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__invert_in$next[0:0]$9031 + attribute \src "libresoc.v:163811.3-163812.51" wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__invert_out$next[0:0]$8987 - attribute \src "libresoc.v:161855.3-161856.53" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__invert_out$next[0:0]$9032 + attribute \src "libresoc.v:163815.3-163816.53" wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__is_32bit$next[0:0]$8988 - attribute \src "libresoc.v:161863.3-161864.49" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__is_32bit$next[0:0]$9033 + attribute \src "libresoc.v:163823.3-163824.49" wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__is_signed$next[0:0]$8989 - attribute \src "libresoc.v:161865.3-161866.51" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__is_signed$next[0:0]$9034 + attribute \src "libresoc.v:163825.3-163826.51" wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__oe__oe$next[0:0]$8990 - attribute \src "libresoc.v:161847.3-161848.45" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__oe__oe$next[0:0]$9035 + attribute \src "libresoc.v:163807.3-163808.45" wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__oe__ok$next[0:0]$8991 - attribute \src "libresoc.v:161849.3-161850.45" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__oe__ok$next[0:0]$9036 + attribute \src "libresoc.v:163809.3-163810.45" wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__output_carry$next[0:0]$8992 - attribute \src "libresoc.v:161861.3-161862.57" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__output_carry$next[0:0]$9037 + attribute \src "libresoc.v:163821.3-163822.57" wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__rc__ok$next[0:0]$8993 - attribute \src "libresoc.v:161845.3-161846.45" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__rc__ok$next[0:0]$9038 + attribute \src "libresoc.v:163805.3-163806.45" wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__rc__rc$next[0:0]$8994 - attribute \src "libresoc.v:161843.3-161844.45" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__rc__rc$next[0:0]$9039 + attribute \src "libresoc.v:163803.3-163804.45" wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__write_cr0$next[0:0]$8995 - attribute \src "libresoc.v:161857.3-161858.51" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__write_cr0$next[0:0]$9040 + attribute \src "libresoc.v:163817.3-163818.51" wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $0\alu_op__zero_a$next[0:0]$8996 - attribute \src "libresoc.v:161853.3-161854.45" + attribute \src "libresoc.v:164051.3-164092.6" + wire $0\alu_op__zero_a$next[0:0]$9041 + attribute \src "libresoc.v:163813.3-163814.45" wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:161984.3-162002.6" - wire width 4 $0\cr_a$next[3:0]$8948 - attribute \src "libresoc.v:161827.3-161828.25" + attribute \src "libresoc.v:163944.3-163962.6" + wire width 4 $0\cr_a$next[3:0]$8993 + attribute \src "libresoc.v:163787.3-163788.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:161984.3-162002.6" - wire $0\cr_a_ok$next[0:0]$8949 - attribute \src "libresoc.v:161829.3-161830.31" + attribute \src "libresoc.v:163944.3-163962.6" + wire $0\cr_a_ok$next[0:0]$8994 + attribute \src "libresoc.v:163789.3-163790.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:160700.7-160700.20" + attribute \src "libresoc.v:162646.7-162646.20" wire $0\initial[0:0] - attribute \src "libresoc.v:162078.3-162090.6" - wire width 2 $0\muxid$next[1:0]$8976 - attribute \src "libresoc.v:161871.3-161872.27" + attribute \src "libresoc.v:164038.3-164050.6" + wire width 2 $0\muxid$next[1:0]$9021 + attribute \src "libresoc.v:163831.3-163832.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:162133.3-162151.6" - wire width 64 $0\o$next[63:0]$9022 - attribute \src "libresoc.v:161831.3-161832.19" + attribute \src "libresoc.v:164093.3-164111.6" + wire width 64 $0\o$next[63:0]$9067 + attribute \src "libresoc.v:163791.3-163792.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:162133.3-162151.6" - wire $0\o_ok$next[0:0]$9023 - attribute \src "libresoc.v:161833.3-161834.25" + attribute \src "libresoc.v:164093.3-164111.6" + wire $0\o_ok$next[0:0]$9068 + attribute \src "libresoc.v:163793.3-163794.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:162060.3-162077.6" - wire $0\r_busy$next[0:0]$8972 - attribute \src "libresoc.v:161873.3-161874.29" + attribute \src "libresoc.v:164020.3-164037.6" + wire $0\r_busy$next[0:0]$9017 + attribute \src "libresoc.v:163833.3-163834.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:162003.3-162021.6" - wire width 2 $0\xer_ca$next[1:0]$8955 - attribute \src "libresoc.v:161823.3-161824.29" + attribute \src "libresoc.v:163963.3-163981.6" + wire width 2 $0\xer_ca$next[1:0]$9000 + attribute \src "libresoc.v:163783.3-163784.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:162003.3-162021.6" - wire $0\xer_ca_ok$next[0:0]$8954 - attribute \src "libresoc.v:161825.3-161826.35" + attribute \src "libresoc.v:163963.3-163981.6" + wire $0\xer_ca_ok$next[0:0]$8999 + attribute \src "libresoc.v:163785.3-163786.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:162022.3-162040.6" - wire width 2 $0\xer_ov$next[1:0]$8960 - attribute \src "libresoc.v:161819.3-161820.29" + attribute \src "libresoc.v:163982.3-164000.6" + wire width 2 $0\xer_ov$next[1:0]$9005 + attribute \src "libresoc.v:163779.3-163780.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:162022.3-162040.6" - wire $0\xer_ov_ok$next[0:0]$8961 - attribute \src "libresoc.v:161821.3-161822.35" + attribute \src "libresoc.v:163982.3-164000.6" + wire $0\xer_ov_ok$next[0:0]$9006 + attribute \src "libresoc.v:163781.3-163782.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:162041.3-162059.6" - wire $0\xer_so$next[0:0]$8966 - attribute \src "libresoc.v:161815.3-161816.29" + attribute \src "libresoc.v:164001.3-164019.6" + wire $0\xer_so$next[0:0]$9011 + attribute \src "libresoc.v:163775.3-163776.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:162041.3-162059.6" - wire $0\xer_so_ok$next[0:0]$8967 - attribute \src "libresoc.v:161817.3-161818.35" + attribute \src "libresoc.v:164001.3-164019.6" + wire $0\xer_so_ok$next[0:0]$9012 + attribute \src "libresoc.v:163777.3-163778.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 4 $1\alu_op__data_len$next[3:0]$8997 - attribute \src "libresoc.v:160705.13-160705.36" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9042 + attribute \src "libresoc.v:162651.13-162651.36" wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 13 $1\alu_op__fn_unit$next[12:0]$8998 - attribute \src "libresoc.v:160728.14-160728.40" - wire width 13 $1\alu_op__fn_unit[12:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$8999 - attribute \src "libresoc.v:160765.14-160765.59" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 14 $1\alu_op__fn_unit$next[13:0]$9043 + attribute \src "libresoc.v:162675.14-162675.40" + wire width 14 $1\alu_op__fn_unit[13:0] + attribute \src "libresoc.v:164051.3-164092.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9044 + attribute \src "libresoc.v:162714.14-162714.59" wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__imm_data__ok$next[0:0]$9000 - attribute \src "libresoc.v:160774.7-160774.34" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9045 + attribute \src "libresoc.v:162723.7-162723.34" wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$9001 - attribute \src "libresoc.v:160787.13-160787.39" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9046 + attribute \src "libresoc.v:162736.13-162736.39" wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 32 $1\alu_op__insn$next[31:0]$9002 - attribute \src "libresoc.v:160804.14-160804.34" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 32 $1\alu_op__insn$next[31:0]$9047 + attribute \src "libresoc.v:162753.14-162753.34" wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$9003 - attribute \src "libresoc.v:160887.13-160887.38" + attribute \src "libresoc.v:164051.3-164092.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9048 + attribute \src "libresoc.v:162837.13-162837.38" wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__invert_in$next[0:0]$9004 - attribute \src "libresoc.v:161044.7-161044.31" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__invert_in$next[0:0]$9049 + attribute \src "libresoc.v:162996.7-162996.31" wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__invert_out$next[0:0]$9005 - attribute \src "libresoc.v:161053.7-161053.32" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__invert_out$next[0:0]$9050 + attribute \src "libresoc.v:163005.7-163005.32" wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__is_32bit$next[0:0]$9006 - attribute \src "libresoc.v:161062.7-161062.30" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__is_32bit$next[0:0]$9051 + attribute \src "libresoc.v:163014.7-163014.30" wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__is_signed$next[0:0]$9007 - attribute \src "libresoc.v:161071.7-161071.31" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__is_signed$next[0:0]$9052 + attribute \src "libresoc.v:163023.7-163023.31" wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__oe__oe$next[0:0]$9008 - attribute \src "libresoc.v:161080.7-161080.28" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__oe__oe$next[0:0]$9053 + attribute \src "libresoc.v:163032.7-163032.28" wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__oe__ok$next[0:0]$9009 - attribute \src "libresoc.v:161089.7-161089.28" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__oe__ok$next[0:0]$9054 + attribute \src "libresoc.v:163041.7-163041.28" wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__output_carry$next[0:0]$9010 - attribute \src "libresoc.v:161098.7-161098.34" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__output_carry$next[0:0]$9055 + attribute \src "libresoc.v:163050.7-163050.34" wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__rc__ok$next[0:0]$9011 - attribute \src "libresoc.v:161107.7-161107.28" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__rc__ok$next[0:0]$9056 + attribute \src "libresoc.v:163059.7-163059.28" wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__rc__rc$next[0:0]$9012 - attribute \src "libresoc.v:161116.7-161116.28" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__rc__rc$next[0:0]$9057 + attribute \src "libresoc.v:163068.7-163068.28" wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__write_cr0$next[0:0]$9013 - attribute \src "libresoc.v:161125.7-161125.31" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__write_cr0$next[0:0]$9058 + attribute \src "libresoc.v:163077.7-163077.31" wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire $1\alu_op__zero_a$next[0:0]$9014 - attribute \src "libresoc.v:161134.7-161134.28" + attribute \src "libresoc.v:164051.3-164092.6" + wire $1\alu_op__zero_a$next[0:0]$9059 + attribute \src "libresoc.v:163086.7-163086.28" wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:161984.3-162002.6" - wire width 4 $1\cr_a$next[3:0]$8950 - attribute \src "libresoc.v:161147.13-161147.24" + attribute \src "libresoc.v:163944.3-163962.6" + wire width 4 $1\cr_a$next[3:0]$8995 + attribute \src "libresoc.v:163099.13-163099.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:161984.3-162002.6" - wire $1\cr_a_ok$next[0:0]$8951 - attribute \src "libresoc.v:161154.7-161154.21" + attribute \src "libresoc.v:163944.3-163962.6" + wire $1\cr_a_ok$next[0:0]$8996 + attribute \src "libresoc.v:163106.7-163106.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:162078.3-162090.6" - wire width 2 $1\muxid$next[1:0]$8977 - attribute \src "libresoc.v:161723.13-161723.25" + attribute \src "libresoc.v:164038.3-164050.6" + wire width 2 $1\muxid$next[1:0]$9022 + attribute \src "libresoc.v:163683.13-163683.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:162133.3-162151.6" - wire width 64 $1\o$next[63:0]$9024 - attribute \src "libresoc.v:161738.14-161738.38" + attribute \src "libresoc.v:164093.3-164111.6" + wire width 64 $1\o$next[63:0]$9069 + attribute \src "libresoc.v:163698.14-163698.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:162133.3-162151.6" - wire $1\o_ok$next[0:0]$9025 - attribute \src "libresoc.v:161745.7-161745.18" + attribute \src "libresoc.v:164093.3-164111.6" + wire $1\o_ok$next[0:0]$9070 + attribute \src "libresoc.v:163705.7-163705.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:162060.3-162077.6" - wire $1\r_busy$next[0:0]$8973 - attribute \src "libresoc.v:161759.7-161759.20" + attribute \src "libresoc.v:164020.3-164037.6" + wire $1\r_busy$next[0:0]$9018 + attribute \src "libresoc.v:163719.7-163719.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:162003.3-162021.6" - wire width 2 $1\xer_ca$next[1:0]$8957 - attribute \src "libresoc.v:161768.13-161768.26" + attribute \src "libresoc.v:163963.3-163981.6" + wire width 2 $1\xer_ca$next[1:0]$9002 + attribute \src "libresoc.v:163728.13-163728.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:162003.3-162021.6" - wire $1\xer_ca_ok$next[0:0]$8956 - attribute \src "libresoc.v:161777.7-161777.23" + attribute \src "libresoc.v:163963.3-163981.6" + wire $1\xer_ca_ok$next[0:0]$9001 + attribute \src "libresoc.v:163737.7-163737.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:162022.3-162040.6" - wire width 2 $1\xer_ov$next[1:0]$8962 - attribute \src "libresoc.v:161784.13-161784.26" + attribute \src "libresoc.v:163982.3-164000.6" + wire width 2 $1\xer_ov$next[1:0]$9007 + attribute \src "libresoc.v:163744.13-163744.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:162022.3-162040.6" - wire $1\xer_ov_ok$next[0:0]$8963 - attribute \src "libresoc.v:161791.7-161791.23" + attribute \src "libresoc.v:163982.3-164000.6" + wire $1\xer_ov_ok$next[0:0]$9008 + attribute \src "libresoc.v:163751.7-163751.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:162041.3-162059.6" - wire $1\xer_so$next[0:0]$8968 - attribute \src "libresoc.v:161798.7-161798.20" + attribute \src "libresoc.v:164001.3-164019.6" + wire $1\xer_so$next[0:0]$9013 + attribute \src "libresoc.v:163758.7-163758.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:162041.3-162059.6" - wire $1\xer_so_ok$next[0:0]$8969 - attribute \src "libresoc.v:161807.7-161807.23" + attribute \src "libresoc.v:164001.3-164019.6" + wire $1\xer_so_ok$next[0:0]$9014 + attribute \src "libresoc.v:163767.7-163767.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:162091.3-162132.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$9015 - attribute \src "libresoc.v:162091.3-162132.6" - wire $2\alu_op__imm_data__ok$next[0:0]$9016 - attribute \src "libresoc.v:162091.3-162132.6" - wire $2\alu_op__oe__oe$next[0:0]$9017 - attribute \src "libresoc.v:162091.3-162132.6" - wire $2\alu_op__oe__ok$next[0:0]$9018 - attribute \src "libresoc.v:162091.3-162132.6" - wire $2\alu_op__rc__ok$next[0:0]$9019 - attribute \src "libresoc.v:162091.3-162132.6" - wire $2\alu_op__rc__rc$next[0:0]$9020 - attribute \src "libresoc.v:161984.3-162002.6" - wire $2\cr_a_ok$next[0:0]$8952 - attribute \src "libresoc.v:162133.3-162151.6" - wire $2\o_ok$next[0:0]$9026 - attribute \src "libresoc.v:162060.3-162077.6" - wire $2\r_busy$next[0:0]$8974 - attribute \src "libresoc.v:162003.3-162021.6" - wire $2\xer_ca_ok$next[0:0]$8958 - attribute \src "libresoc.v:162022.3-162040.6" - wire $2\xer_ov_ok$next[0:0]$8964 - attribute \src "libresoc.v:162041.3-162059.6" - wire $2\xer_so_ok$next[0:0]$8970 - attribute \src "libresoc.v:161814.18-161814.118" - wire $and$libresoc.v:161814$8916_Y + attribute \src "libresoc.v:164051.3-164092.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$9060 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__imm_data__ok$next[0:0]$9061 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__oe__oe$next[0:0]$9062 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__oe__ok$next[0:0]$9063 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__rc__ok$next[0:0]$9064 + attribute \src "libresoc.v:164051.3-164092.6" + wire $2\alu_op__rc__rc$next[0:0]$9065 + attribute \src "libresoc.v:163944.3-163962.6" + wire $2\cr_a_ok$next[0:0]$8997 + attribute \src "libresoc.v:164093.3-164111.6" + wire $2\o_ok$next[0:0]$9071 + attribute \src "libresoc.v:164020.3-164037.6" + wire $2\r_busy$next[0:0]$9019 + attribute \src "libresoc.v:163963.3-163981.6" + wire $2\xer_ca_ok$next[0:0]$9003 + attribute \src "libresoc.v:163982.3-164000.6" + wire $2\xer_ov_ok$next[0:0]$9009 + attribute \src "libresoc.v:164001.3-164019.6" + wire $2\xer_so_ok$next[0:0]$9015 + attribute \src "libresoc.v:163774.18-163774.118" + wire $and$libresoc.v:163774$8961_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -335230,55 +337871,58 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 37 \alu_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 37 \alu_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -335397,6 +338041,7 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -335473,6 +338118,7 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 36 \alu_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -335549,6 +338195,7 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -335641,9 +338288,9 @@ module \pipe1 wire \alu_op__zero_a$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -335657,44 +338304,46 @@ module \pipe1 wire \cr_a_ok$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:160700.7-160700.15" + attribute \src "libresoc.v:162646.7-162646.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len$39 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_alu_op__fn_unit$24 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_alu_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -335793,6 +338442,7 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -335869,6 +338519,7 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_alu_op__insn_type$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -335940,37 +338591,39 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \main_alu_op__data_len$62 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_alu_op__fn_unit$47 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_alu_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -336069,6 +338722,7 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -336145,6 +338799,7 @@ module \pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_alu_op__insn_type$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -336306,7 +338961,7 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:161814$8916 + cell $and $and$libresoc.v:163774$8961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -336314,10 +338969,10 @@ module \pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:161814$8916_Y + connect \Y $and$libresoc.v:163774$8961_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:161875.11-161922.4" + attribute \src "libresoc.v:163835.11-163882.4" cell \input \input connect \alu_op__data_len \input_alu_op__data_len connect \alu_op__data_len$18 \input_alu_op__data_len$39 @@ -336367,7 +339022,7 @@ module \pipe1 connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:161923.8-161975.4" + attribute \src "libresoc.v:163883.8-163935.4" cell \main \main connect \alu_op__data_len \main_alu_op__data_len connect \alu_op__data_len$18 \main_alu_op__data_len$62 @@ -336422,487 +339077,487 @@ module \pipe1 connect \xer_so$21 \main_xer_so$65 end attribute \module_not_derived 1 - attribute \src "libresoc.v:161976.9-161979.4" + attribute \src "libresoc.v:163936.9-163939.4" cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:161980.9-161983.4" + attribute \src "libresoc.v:163940.9-163943.4" cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:160700.7-160700.20" - process $proc$libresoc.v:160700$9027 + attribute \src "libresoc.v:162646.7-162646.20" + process $proc$libresoc.v:162646$9072 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160705.13-160705.36" - process $proc$libresoc.v:160705$9028 + attribute \src "libresoc.v:162651.13-162651.36" + process $proc$libresoc.v:162651$9073 assign { } { } assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:160728.14-160728.40" - process $proc$libresoc.v:160728$9029 + attribute \src "libresoc.v:162675.14-162675.40" + process $proc$libresoc.v:162675$9074 assign { } { } - assign $1\alu_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_op__fn_unit $1\alu_op__fn_unit[12:0] + update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:160765.14-160765.59" - process $proc$libresoc.v:160765$9030 + attribute \src "libresoc.v:162714.14-162714.59" + process $proc$libresoc.v:162714$9075 assign { } { } assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:160774.7-160774.34" - process $proc$libresoc.v:160774$9031 + attribute \src "libresoc.v:162723.7-162723.34" + process $proc$libresoc.v:162723$9076 assign { } { } assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:160787.13-160787.39" - process $proc$libresoc.v:160787$9032 + attribute \src "libresoc.v:162736.13-162736.39" + process $proc$libresoc.v:162736$9077 assign { } { } assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:160804.14-160804.34" - process $proc$libresoc.v:160804$9033 + attribute \src "libresoc.v:162753.14-162753.34" + process $proc$libresoc.v:162753$9078 assign { } { } assign $1\alu_op__insn[31:0] 0 sync always sync init update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:160887.13-160887.38" - process $proc$libresoc.v:160887$9034 + attribute \src "libresoc.v:162837.13-162837.38" + process $proc$libresoc.v:162837$9079 assign { } { } assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:161044.7-161044.31" - process $proc$libresoc.v:161044$9035 + attribute \src "libresoc.v:162996.7-162996.31" + process $proc$libresoc.v:162996$9080 assign { } { } assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:161053.7-161053.32" - process $proc$libresoc.v:161053$9036 + attribute \src "libresoc.v:163005.7-163005.32" + process $proc$libresoc.v:163005$9081 assign { } { } assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:161062.7-161062.30" - process $proc$libresoc.v:161062$9037 + attribute \src "libresoc.v:163014.7-163014.30" + process $proc$libresoc.v:163014$9082 assign { } { } assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:161071.7-161071.31" - process $proc$libresoc.v:161071$9038 + attribute \src "libresoc.v:163023.7-163023.31" + process $proc$libresoc.v:163023$9083 assign { } { } assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:161080.7-161080.28" - process $proc$libresoc.v:161080$9039 + attribute \src "libresoc.v:163032.7-163032.28" + process $proc$libresoc.v:163032$9084 assign { } { } assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:161089.7-161089.28" - process $proc$libresoc.v:161089$9040 + attribute \src "libresoc.v:163041.7-163041.28" + process $proc$libresoc.v:163041$9085 assign { } { } assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:161098.7-161098.34" - process $proc$libresoc.v:161098$9041 + attribute \src "libresoc.v:163050.7-163050.34" + process $proc$libresoc.v:163050$9086 assign { } { } assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:161107.7-161107.28" - process $proc$libresoc.v:161107$9042 + attribute \src "libresoc.v:163059.7-163059.28" + process $proc$libresoc.v:163059$9087 assign { } { } assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:161116.7-161116.28" - process $proc$libresoc.v:161116$9043 + attribute \src "libresoc.v:163068.7-163068.28" + process $proc$libresoc.v:163068$9088 assign { } { } assign $1\alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:161125.7-161125.31" - process $proc$libresoc.v:161125$9044 + attribute \src "libresoc.v:163077.7-163077.31" + process $proc$libresoc.v:163077$9089 assign { } { } assign $1\alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:161134.7-161134.28" - process $proc$libresoc.v:161134$9045 + attribute \src "libresoc.v:163086.7-163086.28" + process $proc$libresoc.v:163086$9090 assign { } { } assign $1\alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_op__zero_a $1\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:161147.13-161147.24" - process $proc$libresoc.v:161147$9046 + attribute \src "libresoc.v:163099.13-163099.24" + process $proc$libresoc.v:163099$9091 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:161154.7-161154.21" - process $proc$libresoc.v:161154$9047 + attribute \src "libresoc.v:163106.7-163106.21" + process $proc$libresoc.v:163106$9092 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:161723.13-161723.25" - process $proc$libresoc.v:161723$9048 + attribute \src "libresoc.v:163683.13-163683.25" + process $proc$libresoc.v:163683$9093 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:161738.14-161738.38" - process $proc$libresoc.v:161738$9049 + attribute \src "libresoc.v:163698.14-163698.38" + process $proc$libresoc.v:163698$9094 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:161745.7-161745.18" - process $proc$libresoc.v:161745$9050 + attribute \src "libresoc.v:163705.7-163705.18" + process $proc$libresoc.v:163705$9095 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:161759.7-161759.20" - process $proc$libresoc.v:161759$9051 + attribute \src "libresoc.v:163719.7-163719.20" + process $proc$libresoc.v:163719$9096 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:161768.13-161768.26" - process $proc$libresoc.v:161768$9052 + attribute \src "libresoc.v:163728.13-163728.26" + process $proc$libresoc.v:163728$9097 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:161777.7-161777.23" - process $proc$libresoc.v:161777$9053 + attribute \src "libresoc.v:163737.7-163737.23" + process $proc$libresoc.v:163737$9098 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:161784.13-161784.26" - process $proc$libresoc.v:161784$9054 + attribute \src "libresoc.v:163744.13-163744.26" + process $proc$libresoc.v:163744$9099 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:161791.7-161791.23" - process $proc$libresoc.v:161791$9055 + attribute \src "libresoc.v:163751.7-163751.23" + process $proc$libresoc.v:163751$9100 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:161798.7-161798.20" - process $proc$libresoc.v:161798$9056 + attribute \src "libresoc.v:163758.7-163758.20" + process $proc$libresoc.v:163758$9101 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:161807.7-161807.23" - process $proc$libresoc.v:161807$9057 + attribute \src "libresoc.v:163767.7-163767.23" + process $proc$libresoc.v:163767$9102 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:161815.3-161816.29" - process $proc$libresoc.v:161815$8917 + attribute \src "libresoc.v:163775.3-163776.29" + process $proc$libresoc.v:163775$8962 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:161817.3-161818.35" - process $proc$libresoc.v:161817$8918 + attribute \src "libresoc.v:163777.3-163778.35" + process $proc$libresoc.v:163777$8963 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:161819.3-161820.29" - process $proc$libresoc.v:161819$8919 + attribute \src "libresoc.v:163779.3-163780.29" + process $proc$libresoc.v:163779$8964 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:161821.3-161822.35" - process $proc$libresoc.v:161821$8920 + attribute \src "libresoc.v:163781.3-163782.35" + process $proc$libresoc.v:163781$8965 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:161823.3-161824.29" - process $proc$libresoc.v:161823$8921 + attribute \src "libresoc.v:163783.3-163784.29" + process $proc$libresoc.v:163783$8966 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:161825.3-161826.35" - process $proc$libresoc.v:161825$8922 + attribute \src "libresoc.v:163785.3-163786.35" + process $proc$libresoc.v:163785$8967 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:161827.3-161828.25" - process $proc$libresoc.v:161827$8923 + attribute \src "libresoc.v:163787.3-163788.25" + process $proc$libresoc.v:163787$8968 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:161829.3-161830.31" - process $proc$libresoc.v:161829$8924 + attribute \src "libresoc.v:163789.3-163790.31" + process $proc$libresoc.v:163789$8969 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:161831.3-161832.19" - process $proc$libresoc.v:161831$8925 + attribute \src "libresoc.v:163791.3-163792.19" + process $proc$libresoc.v:163791$8970 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:161833.3-161834.25" - process $proc$libresoc.v:161833$8926 + attribute \src "libresoc.v:163793.3-163794.25" + process $proc$libresoc.v:163793$8971 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:161835.3-161836.51" - process $proc$libresoc.v:161835$8927 + attribute \src "libresoc.v:163795.3-163796.51" + process $proc$libresoc.v:163795$8972 assign { } { } assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:161837.3-161838.47" - process $proc$libresoc.v:161837$8928 + attribute \src "libresoc.v:163797.3-163798.47" + process $proc$libresoc.v:163797$8973 assign { } { } - assign $0\alu_op__fn_unit[12:0] \alu_op__fn_unit$next + assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk - update \alu_op__fn_unit $0\alu_op__fn_unit[12:0] + update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:161839.3-161840.61" - process $proc$libresoc.v:161839$8929 + attribute \src "libresoc.v:163799.3-163800.61" + process $proc$libresoc.v:163799$8974 assign { } { } assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:161841.3-161842.57" - process $proc$libresoc.v:161841$8930 + attribute \src "libresoc.v:163801.3-163802.57" + process $proc$libresoc.v:163801$8975 assign { } { } assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:161843.3-161844.45" - process $proc$libresoc.v:161843$8931 + attribute \src "libresoc.v:163803.3-163804.45" + process $proc$libresoc.v:163803$8976 assign { } { } assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next sync posedge \coresync_clk update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:161845.3-161846.45" - process $proc$libresoc.v:161845$8932 + attribute \src "libresoc.v:163805.3-163806.45" + process $proc$libresoc.v:163805$8977 assign { } { } assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next sync posedge \coresync_clk update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:161847.3-161848.45" - process $proc$libresoc.v:161847$8933 + attribute \src "libresoc.v:163807.3-163808.45" + process $proc$libresoc.v:163807$8978 assign { } { } assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next sync posedge \coresync_clk update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:161849.3-161850.45" - process $proc$libresoc.v:161849$8934 + attribute \src "libresoc.v:163809.3-163810.45" + process $proc$libresoc.v:163809$8979 assign { } { } assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next sync posedge \coresync_clk update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:161851.3-161852.51" - process $proc$libresoc.v:161851$8935 + attribute \src "libresoc.v:163811.3-163812.51" + process $proc$libresoc.v:163811$8980 assign { } { } assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next sync posedge \coresync_clk update \alu_op__invert_in $0\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:161853.3-161854.45" - process $proc$libresoc.v:161853$8936 + attribute \src "libresoc.v:163813.3-163814.45" + process $proc$libresoc.v:163813$8981 assign { } { } assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next sync posedge \coresync_clk update \alu_op__zero_a $0\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:161855.3-161856.53" - process $proc$libresoc.v:161855$8937 + attribute \src "libresoc.v:163815.3-163816.53" + process $proc$libresoc.v:163815$8982 assign { } { } assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next sync posedge \coresync_clk update \alu_op__invert_out $0\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:161857.3-161858.51" - process $proc$libresoc.v:161857$8938 + attribute \src "libresoc.v:163817.3-163818.51" + process $proc$libresoc.v:163817$8983 assign { } { } assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next sync posedge \coresync_clk update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:161859.3-161860.55" - process $proc$libresoc.v:161859$8939 + attribute \src "libresoc.v:163819.3-163820.55" + process $proc$libresoc.v:163819$8984 assign { } { } assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next sync posedge \coresync_clk update \alu_op__input_carry $0\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:161861.3-161862.57" - process $proc$libresoc.v:161861$8940 + attribute \src "libresoc.v:163821.3-163822.57" + process $proc$libresoc.v:163821$8985 assign { } { } assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next sync posedge \coresync_clk update \alu_op__output_carry $0\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:161863.3-161864.49" - process $proc$libresoc.v:161863$8941 + attribute \src "libresoc.v:163823.3-163824.49" + process $proc$libresoc.v:163823$8986 assign { } { } assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next sync posedge \coresync_clk update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:161865.3-161866.51" - process $proc$libresoc.v:161865$8942 + attribute \src "libresoc.v:163825.3-163826.51" + process $proc$libresoc.v:163825$8987 assign { } { } assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next sync posedge \coresync_clk update \alu_op__is_signed $0\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:161867.3-161868.49" - process $proc$libresoc.v:161867$8943 + attribute \src "libresoc.v:163827.3-163828.49" + process $proc$libresoc.v:163827$8988 assign { } { } assign $0\alu_op__data_len[3:0] \alu_op__data_len$next sync posedge \coresync_clk update \alu_op__data_len $0\alu_op__data_len[3:0] end - attribute \src "libresoc.v:161869.3-161870.41" - process $proc$libresoc.v:161869$8944 + attribute \src "libresoc.v:163829.3-163830.41" + process $proc$libresoc.v:163829$8989 assign { } { } assign $0\alu_op__insn[31:0] \alu_op__insn$next sync posedge \coresync_clk update \alu_op__insn $0\alu_op__insn[31:0] end - attribute \src "libresoc.v:161871.3-161872.27" - process $proc$libresoc.v:161871$8945 + attribute \src "libresoc.v:163831.3-163832.27" + process $proc$libresoc.v:163831$8990 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:161873.3-161874.29" - process $proc$libresoc.v:161873$8946 + attribute \src "libresoc.v:163833.3-163834.29" + process $proc$libresoc.v:163833$8991 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:161984.3-162002.6" - process $proc$libresoc.v:161984$8947 + attribute \src "libresoc.v:163944.3-163962.6" + process $proc$libresoc.v:163944$8992 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8948 $1\cr_a$next[3:0]$8950 + assign $0\cr_a$next[3:0]$8993 $1\cr_a$next[3:0]$8995 assign { } { } - assign $0\cr_a_ok$next[0:0]$8949 $2\cr_a_ok$next[0:0]$8952 - attribute \src "libresoc.v:161985.5-161985.29" + assign $0\cr_a_ok$next[0:0]$8994 $2\cr_a_ok$next[0:0]$8997 + attribute \src "libresoc.v:163945.5-163945.29" switch \initial - attribute \src "libresoc.v:161985.9-161985.17" + attribute \src "libresoc.v:163945.9-163945.17" case 1'1 case end @@ -336912,41 +339567,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8951 $1\cr_a$next[3:0]$8950 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$8996 $1\cr_a$next[3:0]$8995 } { \cr_a_ok$91 \cr_a$90 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8951 $1\cr_a$next[3:0]$8950 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$8996 $1\cr_a$next[3:0]$8995 } { \cr_a_ok$91 \cr_a$90 } case - assign $1\cr_a$next[3:0]$8950 \cr_a - assign $1\cr_a_ok$next[0:0]$8951 \cr_a_ok + assign $1\cr_a$next[3:0]$8995 \cr_a + assign $1\cr_a_ok$next[0:0]$8996 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8952 1'0 + assign $2\cr_a_ok$next[0:0]$8997 1'0 case - assign $2\cr_a_ok$next[0:0]$8952 $1\cr_a_ok$next[0:0]$8951 + assign $2\cr_a_ok$next[0:0]$8997 $1\cr_a_ok$next[0:0]$8996 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8948 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8949 + update \cr_a$next $0\cr_a$next[3:0]$8993 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8994 end - attribute \src "libresoc.v:162003.3-162021.6" - process $proc$libresoc.v:162003$8953 + attribute \src "libresoc.v:163963.3-163981.6" + process $proc$libresoc.v:163963$8998 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$8955 $1\xer_ca$next[1:0]$8957 - assign $0\xer_ca_ok$next[0:0]$8954 $2\xer_ca_ok$next[0:0]$8958 - attribute \src "libresoc.v:162004.5-162004.29" + assign $0\xer_ca$next[1:0]$9000 $1\xer_ca$next[1:0]$9002 + assign $0\xer_ca_ok$next[0:0]$8999 $2\xer_ca_ok$next[0:0]$9003 + attribute \src "libresoc.v:163964.5-163964.29" switch \initial - attribute \src "libresoc.v:162004.9-162004.17" + attribute \src "libresoc.v:163964.9-163964.17" case 1'1 case end @@ -336956,41 +339611,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8956 $1\xer_ca$next[1:0]$8957 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$9001 $1\xer_ca$next[1:0]$9002 } { \xer_ca_ok$93 \xer_ca$92 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8956 $1\xer_ca$next[1:0]$8957 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$9001 $1\xer_ca$next[1:0]$9002 } { \xer_ca_ok$93 \xer_ca$92 } case - assign $1\xer_ca_ok$next[0:0]$8956 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8957 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9001 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9002 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8958 1'0 + assign $2\xer_ca_ok$next[0:0]$9003 1'0 case - assign $2\xer_ca_ok$next[0:0]$8958 $1\xer_ca_ok$next[0:0]$8956 + assign $2\xer_ca_ok$next[0:0]$9003 $1\xer_ca_ok$next[0:0]$9001 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8954 - update \xer_ca$next $0\xer_ca$next[1:0]$8955 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8999 + update \xer_ca$next $0\xer_ca$next[1:0]$9000 end - attribute \src "libresoc.v:162022.3-162040.6" - process $proc$libresoc.v:162022$8959 + attribute \src "libresoc.v:163982.3-164000.6" + process $proc$libresoc.v:163982$9004 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8960 $1\xer_ov$next[1:0]$8962 + assign $0\xer_ov$next[1:0]$9005 $1\xer_ov$next[1:0]$9007 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8961 $2\xer_ov_ok$next[0:0]$8964 - attribute \src "libresoc.v:162023.5-162023.29" + assign $0\xer_ov_ok$next[0:0]$9006 $2\xer_ov_ok$next[0:0]$9009 + attribute \src "libresoc.v:163983.5-163983.29" switch \initial - attribute \src "libresoc.v:162023.9-162023.17" + attribute \src "libresoc.v:163983.9-163983.17" case 1'1 case end @@ -337000,41 +339655,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8963 $1\xer_ov$next[1:0]$8962 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$9008 $1\xer_ov$next[1:0]$9007 } { \xer_ov_ok$95 \xer_ov$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8963 $1\xer_ov$next[1:0]$8962 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$9008 $1\xer_ov$next[1:0]$9007 } { \xer_ov_ok$95 \xer_ov$94 } case - assign $1\xer_ov$next[1:0]$8962 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8963 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9007 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9008 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8964 1'0 + assign $2\xer_ov_ok$next[0:0]$9009 1'0 case - assign $2\xer_ov_ok$next[0:0]$8964 $1\xer_ov_ok$next[0:0]$8963 + assign $2\xer_ov_ok$next[0:0]$9009 $1\xer_ov_ok$next[0:0]$9008 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8960 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8961 + update \xer_ov$next $0\xer_ov$next[1:0]$9005 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9006 end - attribute \src "libresoc.v:162041.3-162059.6" - process $proc$libresoc.v:162041$8965 + attribute \src "libresoc.v:164001.3-164019.6" + process $proc$libresoc.v:164001$9010 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8966 $1\xer_so$next[0:0]$8968 + assign $0\xer_so$next[0:0]$9011 $1\xer_so$next[0:0]$9013 assign { } { } - assign $0\xer_so_ok$next[0:0]$8967 $2\xer_so_ok$next[0:0]$8970 - attribute \src "libresoc.v:162042.5-162042.29" + assign $0\xer_so_ok$next[0:0]$9012 $2\xer_so_ok$next[0:0]$9015 + attribute \src "libresoc.v:164002.5-164002.29" switch \initial - attribute \src "libresoc.v:162042.9-162042.17" + attribute \src "libresoc.v:164002.9-164002.17" case 1'1 case end @@ -337044,38 +339699,38 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8969 $1\xer_so$next[0:0]$8968 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$9014 $1\xer_so$next[0:0]$9013 } { \xer_so_ok$97 \xer_so$96 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8969 $1\xer_so$next[0:0]$8968 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$9014 $1\xer_so$next[0:0]$9013 } { \xer_so_ok$97 \xer_so$96 } case - assign $1\xer_so$next[0:0]$8968 \xer_so - assign $1\xer_so_ok$next[0:0]$8969 \xer_so_ok + assign $1\xer_so$next[0:0]$9013 \xer_so + assign $1\xer_so_ok$next[0:0]$9014 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8970 1'0 + assign $2\xer_so_ok$next[0:0]$9015 1'0 case - assign $2\xer_so_ok$next[0:0]$8970 $1\xer_so_ok$next[0:0]$8969 + assign $2\xer_so_ok$next[0:0]$9015 $1\xer_so_ok$next[0:0]$9014 end sync always - update \xer_so$next $0\xer_so$next[0:0]$8966 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8967 + update \xer_so$next $0\xer_so$next[0:0]$9011 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9012 end - attribute \src "libresoc.v:162060.3-162077.6" - process $proc$libresoc.v:162060$8971 + attribute \src "libresoc.v:164020.3-164037.6" + process $proc$libresoc.v:164020$9016 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8972 $2\r_busy$next[0:0]$8974 - attribute \src "libresoc.v:162061.5-162061.29" + assign $0\r_busy$next[0:0]$9017 $2\r_busy$next[0:0]$9019 + attribute \src "libresoc.v:164021.5-164021.29" switch \initial - attribute \src "libresoc.v:162061.9-162061.17" + attribute \src "libresoc.v:164021.9-164021.17" case 1'1 case end @@ -337084,34 +339739,34 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8973 1'1 + assign $1\r_busy$next[0:0]$9018 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8973 1'0 + assign $1\r_busy$next[0:0]$9018 1'0 case - assign $1\r_busy$next[0:0]$8973 \r_busy + assign $1\r_busy$next[0:0]$9018 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8974 1'0 + assign $2\r_busy$next[0:0]$9019 1'0 case - assign $2\r_busy$next[0:0]$8974 $1\r_busy$next[0:0]$8973 + assign $2\r_busy$next[0:0]$9019 $1\r_busy$next[0:0]$9018 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8972 + update \r_busy$next $0\r_busy$next[0:0]$9017 end - attribute \src "libresoc.v:162078.3-162090.6" - process $proc$libresoc.v:162078$8975 + attribute \src "libresoc.v:164038.3-164050.6" + process $proc$libresoc.v:164038$9020 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$8976 $1\muxid$next[1:0]$8977 - attribute \src "libresoc.v:162079.5-162079.29" + assign $0\muxid$next[1:0]$9021 $1\muxid$next[1:0]$9022 + attribute \src "libresoc.v:164039.5-164039.29" switch \initial - attribute \src "libresoc.v:162079.9-162079.17" + attribute \src "libresoc.v:164039.9-164039.17" case 1'1 case end @@ -337120,19 +339775,19 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$8977 \muxid$69 + assign $1\muxid$next[1:0]$9022 \muxid$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$8977 \muxid$69 + assign $1\muxid$next[1:0]$9022 \muxid$69 case - assign $1\muxid$next[1:0]$8977 \muxid + assign $1\muxid$next[1:0]$9022 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$8976 + update \muxid$next $0\muxid$next[1:0]$9021 end - attribute \src "libresoc.v:162091.3-162132.6" - process $proc$libresoc.v:162091$8978 + attribute \src "libresoc.v:164051.3-164092.6" + process $proc$libresoc.v:164051$9023 assign { } { } assign { } { } assign { } { } @@ -337169,33 +339824,33 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$next[3:0]$8979 $1\alu_op__data_len$next[3:0]$8997 - assign $0\alu_op__fn_unit$next[12:0]$8980 $1\alu_op__fn_unit$next[12:0]$8998 + assign $0\alu_op__data_len$next[3:0]$9024 $1\alu_op__data_len$next[3:0]$9042 + assign $0\alu_op__fn_unit$next[13:0]$9025 $1\alu_op__fn_unit$next[13:0]$9043 assign { } { } assign { } { } - assign $0\alu_op__input_carry$next[1:0]$8983 $1\alu_op__input_carry$next[1:0]$9001 - assign $0\alu_op__insn$next[31:0]$8984 $1\alu_op__insn$next[31:0]$9002 - assign $0\alu_op__insn_type$next[6:0]$8985 $1\alu_op__insn_type$next[6:0]$9003 - assign $0\alu_op__invert_in$next[0:0]$8986 $1\alu_op__invert_in$next[0:0]$9004 - assign $0\alu_op__invert_out$next[0:0]$8987 $1\alu_op__invert_out$next[0:0]$9005 - assign $0\alu_op__is_32bit$next[0:0]$8988 $1\alu_op__is_32bit$next[0:0]$9006 - assign $0\alu_op__is_signed$next[0:0]$8989 $1\alu_op__is_signed$next[0:0]$9007 + assign $0\alu_op__input_carry$next[1:0]$9028 $1\alu_op__input_carry$next[1:0]$9046 + assign $0\alu_op__insn$next[31:0]$9029 $1\alu_op__insn$next[31:0]$9047 + assign $0\alu_op__insn_type$next[6:0]$9030 $1\alu_op__insn_type$next[6:0]$9048 + assign $0\alu_op__invert_in$next[0:0]$9031 $1\alu_op__invert_in$next[0:0]$9049 + assign $0\alu_op__invert_out$next[0:0]$9032 $1\alu_op__invert_out$next[0:0]$9050 + assign $0\alu_op__is_32bit$next[0:0]$9033 $1\alu_op__is_32bit$next[0:0]$9051 + assign $0\alu_op__is_signed$next[0:0]$9034 $1\alu_op__is_signed$next[0:0]$9052 assign { } { } assign { } { } - assign $0\alu_op__output_carry$next[0:0]$8992 $1\alu_op__output_carry$next[0:0]$9010 + assign $0\alu_op__output_carry$next[0:0]$9037 $1\alu_op__output_carry$next[0:0]$9055 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$8995 $1\alu_op__write_cr0$next[0:0]$9013 - assign $0\alu_op__zero_a$next[0:0]$8996 $1\alu_op__zero_a$next[0:0]$9014 - assign $0\alu_op__imm_data__data$next[63:0]$8981 $2\alu_op__imm_data__data$next[63:0]$9015 - assign $0\alu_op__imm_data__ok$next[0:0]$8982 $2\alu_op__imm_data__ok$next[0:0]$9016 - assign $0\alu_op__oe__oe$next[0:0]$8990 $2\alu_op__oe__oe$next[0:0]$9017 - assign $0\alu_op__oe__ok$next[0:0]$8991 $2\alu_op__oe__ok$next[0:0]$9018 - assign $0\alu_op__rc__ok$next[0:0]$8993 $2\alu_op__rc__ok$next[0:0]$9019 - assign $0\alu_op__rc__rc$next[0:0]$8994 $2\alu_op__rc__rc$next[0:0]$9020 - attribute \src "libresoc.v:162092.5-162092.29" + assign $0\alu_op__write_cr0$next[0:0]$9040 $1\alu_op__write_cr0$next[0:0]$9058 + assign $0\alu_op__zero_a$next[0:0]$9041 $1\alu_op__zero_a$next[0:0]$9059 + assign $0\alu_op__imm_data__data$next[63:0]$9026 $2\alu_op__imm_data__data$next[63:0]$9060 + assign $0\alu_op__imm_data__ok$next[0:0]$9027 $2\alu_op__imm_data__ok$next[0:0]$9061 + assign $0\alu_op__oe__oe$next[0:0]$9035 $2\alu_op__oe__oe$next[0:0]$9062 + assign $0\alu_op__oe__ok$next[0:0]$9036 $2\alu_op__oe__ok$next[0:0]$9063 + assign $0\alu_op__rc__ok$next[0:0]$9038 $2\alu_op__rc__ok$next[0:0]$9064 + assign $0\alu_op__rc__rc$next[0:0]$9039 $2\alu_op__rc__rc$next[0:0]$9065 + attribute \src "libresoc.v:164052.5-164052.29" switch \initial - attribute \src "libresoc.v:162092.9-162092.17" + attribute \src "libresoc.v:164052.9-164052.17" case 1'1 case end @@ -337221,7 +339876,7 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9002 $1\alu_op__data_len$next[3:0]$8997 $1\alu_op__is_signed$next[0:0]$9007 $1\alu_op__is_32bit$next[0:0]$9006 $1\alu_op__output_carry$next[0:0]$9010 $1\alu_op__input_carry$next[1:0]$9001 $1\alu_op__write_cr0$next[0:0]$9013 $1\alu_op__invert_out$next[0:0]$9005 $1\alu_op__zero_a$next[0:0]$9014 $1\alu_op__invert_in$next[0:0]$9004 $1\alu_op__oe__ok$next[0:0]$9009 $1\alu_op__oe__oe$next[0:0]$9008 $1\alu_op__rc__ok$next[0:0]$9011 $1\alu_op__rc__rc$next[0:0]$9012 $1\alu_op__imm_data__ok$next[0:0]$9000 $1\alu_op__imm_data__data$next[63:0]$8999 $1\alu_op__fn_unit$next[12:0]$8998 $1\alu_op__insn_type$next[6:0]$9003 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9047 $1\alu_op__data_len$next[3:0]$9042 $1\alu_op__is_signed$next[0:0]$9052 $1\alu_op__is_32bit$next[0:0]$9051 $1\alu_op__output_carry$next[0:0]$9055 $1\alu_op__input_carry$next[1:0]$9046 $1\alu_op__write_cr0$next[0:0]$9058 $1\alu_op__invert_out$next[0:0]$9050 $1\alu_op__zero_a$next[0:0]$9059 $1\alu_op__invert_in$next[0:0]$9049 $1\alu_op__oe__ok$next[0:0]$9054 $1\alu_op__oe__oe$next[0:0]$9053 $1\alu_op__rc__ok$next[0:0]$9056 $1\alu_op__rc__rc$next[0:0]$9057 $1\alu_op__imm_data__ok$next[0:0]$9045 $1\alu_op__imm_data__data$next[63:0]$9044 $1\alu_op__fn_unit$next[13:0]$9043 $1\alu_op__insn_type$next[6:0]$9048 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -337242,26 +339897,26 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9002 $1\alu_op__data_len$next[3:0]$8997 $1\alu_op__is_signed$next[0:0]$9007 $1\alu_op__is_32bit$next[0:0]$9006 $1\alu_op__output_carry$next[0:0]$9010 $1\alu_op__input_carry$next[1:0]$9001 $1\alu_op__write_cr0$next[0:0]$9013 $1\alu_op__invert_out$next[0:0]$9005 $1\alu_op__zero_a$next[0:0]$9014 $1\alu_op__invert_in$next[0:0]$9004 $1\alu_op__oe__ok$next[0:0]$9009 $1\alu_op__oe__oe$next[0:0]$9008 $1\alu_op__rc__ok$next[0:0]$9011 $1\alu_op__rc__rc$next[0:0]$9012 $1\alu_op__imm_data__ok$next[0:0]$9000 $1\alu_op__imm_data__data$next[63:0]$8999 $1\alu_op__fn_unit$next[12:0]$8998 $1\alu_op__insn_type$next[6:0]$9003 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9047 $1\alu_op__data_len$next[3:0]$9042 $1\alu_op__is_signed$next[0:0]$9052 $1\alu_op__is_32bit$next[0:0]$9051 $1\alu_op__output_carry$next[0:0]$9055 $1\alu_op__input_carry$next[1:0]$9046 $1\alu_op__write_cr0$next[0:0]$9058 $1\alu_op__invert_out$next[0:0]$9050 $1\alu_op__zero_a$next[0:0]$9059 $1\alu_op__invert_in$next[0:0]$9049 $1\alu_op__oe__ok$next[0:0]$9054 $1\alu_op__oe__oe$next[0:0]$9053 $1\alu_op__rc__ok$next[0:0]$9056 $1\alu_op__rc__rc$next[0:0]$9057 $1\alu_op__imm_data__ok$next[0:0]$9045 $1\alu_op__imm_data__data$next[63:0]$9044 $1\alu_op__fn_unit$next[13:0]$9043 $1\alu_op__insn_type$next[6:0]$9048 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } case - assign $1\alu_op__data_len$next[3:0]$8997 \alu_op__data_len - assign $1\alu_op__fn_unit$next[12:0]$8998 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$8999 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$9000 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$9001 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$9002 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$9003 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$9004 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$9005 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$9006 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$9007 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$9008 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$9009 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$9010 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$9011 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$9012 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$9013 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$9014 \alu_op__zero_a + assign $1\alu_op__data_len$next[3:0]$9042 \alu_op__data_len + assign $1\alu_op__fn_unit$next[13:0]$9043 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9044 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9045 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9046 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9047 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9048 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9049 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9050 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9051 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9052 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9053 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9054 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9055 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9056 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9057 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9058 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9059 \alu_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -337273,52 +339928,52 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$9015 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$9016 1'0 - assign $2\alu_op__rc__rc$next[0:0]$9020 1'0 - assign $2\alu_op__rc__ok$next[0:0]$9019 1'0 - assign $2\alu_op__oe__oe$next[0:0]$9017 1'0 - assign $2\alu_op__oe__ok$next[0:0]$9018 1'0 + assign $2\alu_op__imm_data__data$next[63:0]$9060 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9061 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9065 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9064 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9062 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9063 1'0 case - assign $2\alu_op__imm_data__data$next[63:0]$9015 $1\alu_op__imm_data__data$next[63:0]$8999 - assign $2\alu_op__imm_data__ok$next[0:0]$9016 $1\alu_op__imm_data__ok$next[0:0]$9000 - assign $2\alu_op__oe__oe$next[0:0]$9017 $1\alu_op__oe__oe$next[0:0]$9008 - assign $2\alu_op__oe__ok$next[0:0]$9018 $1\alu_op__oe__ok$next[0:0]$9009 - assign $2\alu_op__rc__ok$next[0:0]$9019 $1\alu_op__rc__ok$next[0:0]$9011 - assign $2\alu_op__rc__rc$next[0:0]$9020 $1\alu_op__rc__rc$next[0:0]$9012 + assign $2\alu_op__imm_data__data$next[63:0]$9060 $1\alu_op__imm_data__data$next[63:0]$9044 + assign $2\alu_op__imm_data__ok$next[0:0]$9061 $1\alu_op__imm_data__ok$next[0:0]$9045 + assign $2\alu_op__oe__oe$next[0:0]$9062 $1\alu_op__oe__oe$next[0:0]$9053 + assign $2\alu_op__oe__ok$next[0:0]$9063 $1\alu_op__oe__ok$next[0:0]$9054 + assign $2\alu_op__rc__ok$next[0:0]$9064 $1\alu_op__rc__ok$next[0:0]$9056 + assign $2\alu_op__rc__rc$next[0:0]$9065 $1\alu_op__rc__rc$next[0:0]$9057 end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8979 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[12:0]$8980 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8981 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8982 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8983 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8984 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8985 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8986 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8987 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8988 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8989 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8990 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8991 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8992 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8993 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8994 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8995 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8996 + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9024 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9025 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9026 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9027 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9028 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9029 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9030 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9031 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9032 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9033 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9034 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9035 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9036 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9037 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9038 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9039 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9040 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9041 end - attribute \src "libresoc.v:162133.3-162151.6" - process $proc$libresoc.v:162133$9021 + attribute \src "libresoc.v:164093.3-164111.6" + process $proc$libresoc.v:164093$9066 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9022 $1\o$next[63:0]$9024 + assign $0\o$next[63:0]$9067 $1\o$next[63:0]$9069 assign { } { } - assign $0\o_ok$next[0:0]$9023 $2\o_ok$next[0:0]$9026 - attribute \src "libresoc.v:162134.5-162134.29" + assign $0\o_ok$next[0:0]$9068 $2\o_ok$next[0:0]$9071 + attribute \src "libresoc.v:164094.5-164094.29" switch \initial - attribute \src "libresoc.v:162134.9-162134.17" + attribute \src "libresoc.v:164094.9-164094.17" case 1'1 case end @@ -337328,30 +339983,30 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9025 $1\o$next[63:0]$9024 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9070 $1\o$next[63:0]$9069 } { \o_ok$89 \o$88 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9025 $1\o$next[63:0]$9024 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9070 $1\o$next[63:0]$9069 } { \o_ok$89 \o$88 } case - assign $1\o$next[63:0]$9024 \o - assign $1\o_ok$next[0:0]$9025 \o_ok + assign $1\o$next[63:0]$9069 \o + assign $1\o_ok$next[0:0]$9070 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9026 1'0 + assign $2\o_ok$next[0:0]$9071 1'0 case - assign $2\o_ok$next[0:0]$9026 $1\o_ok$next[0:0]$9025 + assign $2\o_ok$next[0:0]$9071 $1\o_ok$next[0:0]$9070 end sync always - update \o$next $0\o$next[63:0]$9022 - update \o_ok$next $0\o_ok$next[0:0]$9023 + update \o$next $0\o$next[63:0]$9067 + update \o_ok$next $0\o_ok$next[0:0]$9068 end - connect \$67 $and$libresoc.v:161814$8916_Y + connect \$67 $and$libresoc.v:163774$8961_Y connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy @@ -337378,258 +340033,258 @@ module \pipe1 connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:162181.1-163603.10" +attribute \src "libresoc.v:164141.1-165577.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" module \pipe1$110 - attribute \src "libresoc.v:163536.3-163554.6" - wire width 4 $0\cr_a$next[3:0]$9147 - attribute \src "libresoc.v:163278.3-163279.25" + attribute \src "libresoc.v:165510.3-165528.6" + wire width 4 $0\cr_a$next[3:0]$9192 + attribute \src "libresoc.v:165252.3-165253.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:163536.3-163554.6" - wire $0\cr_a_ok$next[0:0]$9148 - attribute \src "libresoc.v:163280.3-163281.31" + attribute \src "libresoc.v:165510.3-165528.6" + wire $0\cr_a_ok$next[0:0]$9193 + attribute \src "libresoc.v:165254.3-165255.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:162182.7-162182.20" + attribute \src "libresoc.v:164142.7-164142.20" wire $0\initial[0:0] - attribute \src "libresoc.v:163463.3-163475.6" - wire width 2 $0\muxid$next[1:0]$9097 - attribute \src "libresoc.v:163320.3-163321.27" + attribute \src "libresoc.v:165437.3-165449.6" + wire width 2 $0\muxid$next[1:0]$9142 + attribute \src "libresoc.v:165294.3-165295.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:163517.3-163535.6" - wire width 64 $0\o$next[63:0]$9141 - attribute \src "libresoc.v:163282.3-163283.19" + attribute \src "libresoc.v:165491.3-165509.6" + wire width 64 $0\o$next[63:0]$9186 + attribute \src "libresoc.v:165256.3-165257.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:163517.3-163535.6" - wire $0\o_ok$next[0:0]$9142 - attribute \src "libresoc.v:163284.3-163285.25" + attribute \src "libresoc.v:165491.3-165509.6" + wire $0\o_ok$next[0:0]$9187 + attribute \src "libresoc.v:165258.3-165259.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:163445.3-163462.6" - wire $0\r_busy$next[0:0]$9093 - attribute \src "libresoc.v:163322.3-163323.29" + attribute \src "libresoc.v:165419.3-165436.6" + wire $0\r_busy$next[0:0]$9138 + attribute \src "libresoc.v:165296.3-165297.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 13 $0\sr_op__fn_unit$next[12:0]$9100 - attribute \src "libresoc.v:163288.3-163289.45" - wire width 13 $0\sr_op__fn_unit[12:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$9101 - attribute \src "libresoc.v:163290.3-163291.59" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 14 $0\sr_op__fn_unit$next[13:0]$9145 + attribute \src "libresoc.v:165262.3-165263.45" + wire width 14 $0\sr_op__fn_unit[13:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9146 + attribute \src "libresoc.v:165264.3-165265.59" wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__imm_data__ok$next[0:0]$9102 - attribute \src "libresoc.v:163292.3-163293.55" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9147 + attribute \src "libresoc.v:165266.3-165267.55" wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$9103 - attribute \src "libresoc.v:163306.3-163307.53" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9148 + attribute \src "libresoc.v:165280.3-165281.53" wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__input_cr$next[0:0]$9104 - attribute \src "libresoc.v:163310.3-163311.47" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__input_cr$next[0:0]$9149 + attribute \src "libresoc.v:165284.3-165285.47" wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 32 $0\sr_op__insn$next[31:0]$9105 - attribute \src "libresoc.v:163318.3-163319.39" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 32 $0\sr_op__insn$next[31:0]$9150 + attribute \src "libresoc.v:165292.3-165293.39" wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$9106 - attribute \src "libresoc.v:163286.3-163287.49" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9151 + attribute \src "libresoc.v:165260.3-165261.49" wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__invert_in$next[0:0]$9107 - attribute \src "libresoc.v:163304.3-163305.49" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__invert_in$next[0:0]$9152 + attribute \src "libresoc.v:165278.3-165279.49" wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__is_32bit$next[0:0]$9108 - attribute \src "libresoc.v:163314.3-163315.47" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__is_32bit$next[0:0]$9153 + attribute \src "libresoc.v:165288.3-165289.47" wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__is_signed$next[0:0]$9109 - attribute \src "libresoc.v:163316.3-163317.49" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__is_signed$next[0:0]$9154 + attribute \src "libresoc.v:165290.3-165291.49" wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__oe__oe$next[0:0]$9110 - attribute \src "libresoc.v:163298.3-163299.43" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__oe__oe$next[0:0]$9155 + attribute \src "libresoc.v:165272.3-165273.43" wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__oe__ok$next[0:0]$9111 - attribute \src "libresoc.v:163300.3-163301.43" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__oe__ok$next[0:0]$9156 + attribute \src "libresoc.v:165274.3-165275.43" wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__output_carry$next[0:0]$9112 - attribute \src "libresoc.v:163308.3-163309.55" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__output_carry$next[0:0]$9157 + attribute \src "libresoc.v:165282.3-165283.55" wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__output_cr$next[0:0]$9113 - attribute \src "libresoc.v:163312.3-163313.49" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__output_cr$next[0:0]$9158 + attribute \src "libresoc.v:165286.3-165287.49" wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__rc__ok$next[0:0]$9114 - attribute \src "libresoc.v:163296.3-163297.43" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__rc__ok$next[0:0]$9159 + attribute \src "libresoc.v:165270.3-165271.43" wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__rc__rc$next[0:0]$9115 - attribute \src "libresoc.v:163294.3-163295.43" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__rc__rc$next[0:0]$9160 + attribute \src "libresoc.v:165268.3-165269.43" wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $0\sr_op__write_cr0$next[0:0]$9116 - attribute \src "libresoc.v:163302.3-163303.49" + attribute \src "libresoc.v:165450.3-165490.6" + wire $0\sr_op__write_cr0$next[0:0]$9161 + attribute \src "libresoc.v:165276.3-165277.49" wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:163426.3-163444.6" - wire width 2 $0\xer_ca$next[1:0]$9088 - attribute \src "libresoc.v:163270.3-163271.29" + attribute \src "libresoc.v:165400.3-165418.6" + wire width 2 $0\xer_ca$next[1:0]$9133 + attribute \src "libresoc.v:165244.3-165245.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:163426.3-163444.6" - wire $0\xer_ca_ok$next[0:0]$9087 - attribute \src "libresoc.v:163272.3-163273.35" + attribute \src "libresoc.v:165400.3-165418.6" + wire $0\xer_ca_ok$next[0:0]$9132 + attribute \src "libresoc.v:165246.3-165247.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:163555.3-163573.6" - wire $0\xer_so$next[0:0]$9153 - attribute \src "libresoc.v:163274.3-163275.29" + attribute \src "libresoc.v:165529.3-165547.6" + wire $0\xer_so$next[0:0]$9198 + attribute \src "libresoc.v:165248.3-165249.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:163555.3-163573.6" - wire $0\xer_so_ok$next[0:0]$9154 - attribute \src "libresoc.v:163276.3-163277.35" + attribute \src "libresoc.v:165529.3-165547.6" + wire $0\xer_so_ok$next[0:0]$9199 + attribute \src "libresoc.v:165250.3-165251.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:163536.3-163554.6" - wire width 4 $1\cr_a$next[3:0]$9149 - attribute \src "libresoc.v:162191.13-162191.24" + attribute \src "libresoc.v:165510.3-165528.6" + wire width 4 $1\cr_a$next[3:0]$9194 + attribute \src "libresoc.v:164151.13-164151.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:163536.3-163554.6" - wire $1\cr_a_ok$next[0:0]$9150 - attribute \src "libresoc.v:162200.7-162200.21" + attribute \src "libresoc.v:165510.3-165528.6" + wire $1\cr_a_ok$next[0:0]$9195 + attribute \src "libresoc.v:164160.7-164160.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:163463.3-163475.6" - wire width 2 $1\muxid$next[1:0]$9098 - attribute \src "libresoc.v:162757.13-162757.25" + attribute \src "libresoc.v:165437.3-165449.6" + wire width 2 $1\muxid$next[1:0]$9143 + attribute \src "libresoc.v:164725.13-164725.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:163517.3-163535.6" - wire width 64 $1\o$next[63:0]$9143 - attribute \src "libresoc.v:162772.14-162772.38" + attribute \src "libresoc.v:165491.3-165509.6" + wire width 64 $1\o$next[63:0]$9188 + attribute \src "libresoc.v:164740.14-164740.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:163517.3-163535.6" - wire $1\o_ok$next[0:0]$9144 - attribute \src "libresoc.v:162779.7-162779.18" + attribute \src "libresoc.v:165491.3-165509.6" + wire $1\o_ok$next[0:0]$9189 + attribute \src "libresoc.v:164747.7-164747.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:163445.3-163462.6" - wire $1\r_busy$next[0:0]$9094 - attribute \src "libresoc.v:162793.7-162793.20" + attribute \src "libresoc.v:165419.3-165436.6" + wire $1\r_busy$next[0:0]$9139 + attribute \src "libresoc.v:164761.7-164761.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 13 $1\sr_op__fn_unit$next[12:0]$9117 - attribute \src "libresoc.v:162818.14-162818.39" - wire width 13 $1\sr_op__fn_unit[12:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$9118 - attribute \src "libresoc.v:162855.14-162855.58" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 14 $1\sr_op__fn_unit$next[13:0]$9162 + attribute \src "libresoc.v:164787.14-164787.39" + wire width 14 $1\sr_op__fn_unit[13:0] + attribute \src "libresoc.v:165450.3-165490.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9163 + attribute \src "libresoc.v:164826.14-164826.58" wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__imm_data__ok$next[0:0]$9119 - attribute \src "libresoc.v:162864.7-162864.33" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9164 + attribute \src "libresoc.v:164835.7-164835.33" wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$9120 - attribute \src "libresoc.v:162877.13-162877.38" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9165 + attribute \src "libresoc.v:164848.13-164848.38" wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__input_cr$next[0:0]$9121 - attribute \src "libresoc.v:162894.7-162894.29" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__input_cr$next[0:0]$9166 + attribute \src "libresoc.v:164865.7-164865.29" wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 32 $1\sr_op__insn$next[31:0]$9122 - attribute \src "libresoc.v:162903.14-162903.33" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 32 $1\sr_op__insn$next[31:0]$9167 + attribute \src "libresoc.v:164874.14-164874.33" wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$9123 - attribute \src "libresoc.v:162986.13-162986.37" + attribute \src "libresoc.v:165450.3-165490.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9168 + attribute \src "libresoc.v:164958.13-164958.37" wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__invert_in$next[0:0]$9124 - attribute \src "libresoc.v:163143.7-163143.30" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__invert_in$next[0:0]$9169 + attribute \src "libresoc.v:165117.7-165117.30" wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__is_32bit$next[0:0]$9125 - attribute \src "libresoc.v:163152.7-163152.29" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__is_32bit$next[0:0]$9170 + attribute \src "libresoc.v:165126.7-165126.29" wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__is_signed$next[0:0]$9126 - attribute \src "libresoc.v:163161.7-163161.30" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__is_signed$next[0:0]$9171 + attribute \src "libresoc.v:165135.7-165135.30" wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__oe__oe$next[0:0]$9127 - attribute \src "libresoc.v:163170.7-163170.27" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__oe__oe$next[0:0]$9172 + attribute \src "libresoc.v:165144.7-165144.27" wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__oe__ok$next[0:0]$9128 - attribute \src "libresoc.v:163179.7-163179.27" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__oe__ok$next[0:0]$9173 + attribute \src "libresoc.v:165153.7-165153.27" wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__output_carry$next[0:0]$9129 - attribute \src "libresoc.v:163188.7-163188.33" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__output_carry$next[0:0]$9174 + attribute \src "libresoc.v:165162.7-165162.33" wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__output_cr$next[0:0]$9130 - attribute \src "libresoc.v:163197.7-163197.30" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__output_cr$next[0:0]$9175 + attribute \src "libresoc.v:165171.7-165171.30" wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__rc__ok$next[0:0]$9131 - attribute \src "libresoc.v:163206.7-163206.27" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__rc__ok$next[0:0]$9176 + attribute \src "libresoc.v:165180.7-165180.27" wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__rc__rc$next[0:0]$9132 - attribute \src "libresoc.v:163215.7-163215.27" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__rc__rc$next[0:0]$9177 + attribute \src "libresoc.v:165189.7-165189.27" wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:163476.3-163516.6" - wire $1\sr_op__write_cr0$next[0:0]$9133 - attribute \src "libresoc.v:163224.7-163224.30" + attribute \src "libresoc.v:165450.3-165490.6" + wire $1\sr_op__write_cr0$next[0:0]$9178 + attribute \src "libresoc.v:165198.7-165198.30" wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:163426.3-163444.6" - wire width 2 $1\xer_ca$next[1:0]$9090 - attribute \src "libresoc.v:163233.13-163233.26" + attribute \src "libresoc.v:165400.3-165418.6" + wire width 2 $1\xer_ca$next[1:0]$9135 + attribute \src "libresoc.v:165207.13-165207.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:163426.3-163444.6" - wire $1\xer_ca_ok$next[0:0]$9089 - attribute \src "libresoc.v:163244.7-163244.23" + attribute \src "libresoc.v:165400.3-165418.6" + wire $1\xer_ca_ok$next[0:0]$9134 + attribute \src "libresoc.v:165218.7-165218.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:163555.3-163573.6" - wire $1\xer_so$next[0:0]$9155 - attribute \src "libresoc.v:163253.7-163253.20" + attribute \src "libresoc.v:165529.3-165547.6" + wire $1\xer_so$next[0:0]$9200 + attribute \src "libresoc.v:165227.7-165227.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:163555.3-163573.6" - wire $1\xer_so_ok$next[0:0]$9156 - attribute \src "libresoc.v:163262.7-163262.23" + attribute \src "libresoc.v:165529.3-165547.6" + wire $1\xer_so_ok$next[0:0]$9201 + attribute \src "libresoc.v:165236.7-165236.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:163536.3-163554.6" - wire $2\cr_a_ok$next[0:0]$9151 - attribute \src "libresoc.v:163517.3-163535.6" - wire $2\o_ok$next[0:0]$9145 - attribute \src "libresoc.v:163445.3-163462.6" - wire $2\r_busy$next[0:0]$9095 - attribute \src "libresoc.v:163476.3-163516.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$9134 - attribute \src "libresoc.v:163476.3-163516.6" - wire $2\sr_op__imm_data__ok$next[0:0]$9135 - attribute \src "libresoc.v:163476.3-163516.6" - wire $2\sr_op__oe__oe$next[0:0]$9136 - attribute \src "libresoc.v:163476.3-163516.6" - wire $2\sr_op__oe__ok$next[0:0]$9137 - attribute \src "libresoc.v:163476.3-163516.6" - wire $2\sr_op__rc__ok$next[0:0]$9138 - attribute \src "libresoc.v:163476.3-163516.6" - wire $2\sr_op__rc__rc$next[0:0]$9139 - attribute \src "libresoc.v:163426.3-163444.6" - wire $2\xer_ca_ok$next[0:0]$9091 - attribute \src "libresoc.v:163555.3-163573.6" - wire $2\xer_so_ok$next[0:0]$9157 - attribute \src "libresoc.v:163269.18-163269.118" - wire $and$libresoc.v:163269$9058_Y + attribute \src "libresoc.v:165510.3-165528.6" + wire $2\cr_a_ok$next[0:0]$9196 + attribute \src "libresoc.v:165491.3-165509.6" + wire $2\o_ok$next[0:0]$9190 + attribute \src "libresoc.v:165419.3-165436.6" + wire $2\r_busy$next[0:0]$9140 + attribute \src "libresoc.v:165450.3-165490.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9179 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9180 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__oe__oe$next[0:0]$9181 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__oe__ok$next[0:0]$9182 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__rc__ok$next[0:0]$9183 + attribute \src "libresoc.v:165450.3-165490.6" + wire $2\sr_op__rc__rc$next[0:0]$9184 + attribute \src "libresoc.v:165400.3-165418.6" + wire $2\xer_ca_ok$next[0:0]$9136 + attribute \src "libresoc.v:165529.3-165547.6" + wire $2\xer_so_ok$next[0:0]$9202 + attribute \src "libresoc.v:165243.18-165243.118" + wire $and$libresoc.v:165243$9103_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 24 \cr_a @@ -337647,7 +340302,7 @@ module \pipe1$110 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:162182.7-162182.15" + attribute \src "libresoc.v:164142.7-164142.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid @@ -337666,37 +340321,39 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rc$41 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_sr_op__fn_unit$23 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_sr_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -337799,6 +340456,7 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -337875,6 +340533,7 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_sr_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -337940,37 +340599,39 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rc attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_sr_op__fn_unit$46 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_sr_op__fn_unit$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -338073,6 +340734,7 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -338149,6 +340811,7 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_sr_op__insn_type$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -338242,55 +340905,58 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 52 \rc attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 34 \sr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 34 \sr_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -338417,6 +341083,7 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -338493,6 +341160,7 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 33 \sr_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -338569,6 +341237,7 @@ module \pipe1$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -338688,7 +341357,7 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:163269$9058 + cell $and $and$libresoc.v:165243$9103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -338696,10 +341365,10 @@ module \pipe1$110 parameter \Y_WIDTH 1 connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:163269$9058_Y + connect \Y $and$libresoc.v:165243$9103_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:163324.15-163371.4" + attribute \src "libresoc.v:165298.15-165345.4" cell \input$113 \input connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 @@ -338749,7 +341418,7 @@ module \pipe1$110 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:163372.14-163417.4" + attribute \src "libresoc.v:165346.14-165391.4" cell \main$114 \main connect \muxid \main_muxid connect \muxid$1 \main_muxid$44 @@ -338797,442 +341466,442 @@ module \pipe1$110 connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:163418.11-163421.4" + attribute \src "libresoc.v:165392.11-165395.4" cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:163422.11-163425.4" + attribute \src "libresoc.v:165396.11-165399.4" cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:162182.7-162182.20" - process $proc$libresoc.v:162182$9158 + attribute \src "libresoc.v:164142.7-164142.20" + process $proc$libresoc.v:164142$9203 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:162191.13-162191.24" - process $proc$libresoc.v:162191$9159 + attribute \src "libresoc.v:164151.13-164151.24" + process $proc$libresoc.v:164151$9204 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:162200.7-162200.21" - process $proc$libresoc.v:162200$9160 + attribute \src "libresoc.v:164160.7-164160.21" + process $proc$libresoc.v:164160$9205 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:162757.13-162757.25" - process $proc$libresoc.v:162757$9161 + attribute \src "libresoc.v:164725.13-164725.25" + process $proc$libresoc.v:164725$9206 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:162772.14-162772.38" - process $proc$libresoc.v:162772$9162 + attribute \src "libresoc.v:164740.14-164740.38" + process $proc$libresoc.v:164740$9207 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:162779.7-162779.18" - process $proc$libresoc.v:162779$9163 + attribute \src "libresoc.v:164747.7-164747.18" + process $proc$libresoc.v:164747$9208 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:162793.7-162793.20" - process $proc$libresoc.v:162793$9164 + attribute \src "libresoc.v:164761.7-164761.20" + process $proc$libresoc.v:164761$9209 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:162818.14-162818.39" - process $proc$libresoc.v:162818$9165 + attribute \src "libresoc.v:164787.14-164787.39" + process $proc$libresoc.v:164787$9210 assign { } { } - assign $1\sr_op__fn_unit[12:0] 13'0000000000000 + assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \sr_op__fn_unit $1\sr_op__fn_unit[12:0] + update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:162855.14-162855.58" - process $proc$libresoc.v:162855$9166 + attribute \src "libresoc.v:164826.14-164826.58" + process $proc$libresoc.v:164826$9211 assign { } { } assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:162864.7-162864.33" - process $proc$libresoc.v:162864$9167 + attribute \src "libresoc.v:164835.7-164835.33" + process $proc$libresoc.v:164835$9212 assign { } { } assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:162877.13-162877.38" - process $proc$libresoc.v:162877$9168 + attribute \src "libresoc.v:164848.13-164848.38" + process $proc$libresoc.v:164848$9213 assign { } { } assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:162894.7-162894.29" - process $proc$libresoc.v:162894$9169 + attribute \src "libresoc.v:164865.7-164865.29" + process $proc$libresoc.v:164865$9214 assign { } { } assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:162903.14-162903.33" - process $proc$libresoc.v:162903$9170 + attribute \src "libresoc.v:164874.14-164874.33" + process $proc$libresoc.v:164874$9215 assign { } { } assign $1\sr_op__insn[31:0] 0 sync always sync init update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:162986.13-162986.37" - process $proc$libresoc.v:162986$9171 + attribute \src "libresoc.v:164958.13-164958.37" + process $proc$libresoc.v:164958$9216 assign { } { } assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:163143.7-163143.30" - process $proc$libresoc.v:163143$9172 + attribute \src "libresoc.v:165117.7-165117.30" + process $proc$libresoc.v:165117$9217 assign { } { } assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:163152.7-163152.29" - process $proc$libresoc.v:163152$9173 + attribute \src "libresoc.v:165126.7-165126.29" + process $proc$libresoc.v:165126$9218 assign { } { } assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:163161.7-163161.30" - process $proc$libresoc.v:163161$9174 + attribute \src "libresoc.v:165135.7-165135.30" + process $proc$libresoc.v:165135$9219 assign { } { } assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:163170.7-163170.27" - process $proc$libresoc.v:163170$9175 + attribute \src "libresoc.v:165144.7-165144.27" + process $proc$libresoc.v:165144$9220 assign { } { } assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:163179.7-163179.27" - process $proc$libresoc.v:163179$9176 + attribute \src "libresoc.v:165153.7-165153.27" + process $proc$libresoc.v:165153$9221 assign { } { } assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:163188.7-163188.33" - process $proc$libresoc.v:163188$9177 + attribute \src "libresoc.v:165162.7-165162.33" + process $proc$libresoc.v:165162$9222 assign { } { } assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:163197.7-163197.30" - process $proc$libresoc.v:163197$9178 + attribute \src "libresoc.v:165171.7-165171.30" + process $proc$libresoc.v:165171$9223 assign { } { } assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:163206.7-163206.27" - process $proc$libresoc.v:163206$9179 + attribute \src "libresoc.v:165180.7-165180.27" + process $proc$libresoc.v:165180$9224 assign { } { } assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:163215.7-163215.27" - process $proc$libresoc.v:163215$9180 + attribute \src "libresoc.v:165189.7-165189.27" + process $proc$libresoc.v:165189$9225 assign { } { } assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:163224.7-163224.30" - process $proc$libresoc.v:163224$9181 + attribute \src "libresoc.v:165198.7-165198.30" + process $proc$libresoc.v:165198$9226 assign { } { } assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:163233.13-163233.26" - process $proc$libresoc.v:163233$9182 + attribute \src "libresoc.v:165207.13-165207.26" + process $proc$libresoc.v:165207$9227 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:163244.7-163244.23" - process $proc$libresoc.v:163244$9183 + attribute \src "libresoc.v:165218.7-165218.23" + process $proc$libresoc.v:165218$9228 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163253.7-163253.20" - process $proc$libresoc.v:163253$9184 + attribute \src "libresoc.v:165227.7-165227.20" + process $proc$libresoc.v:165227$9229 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:163262.7-163262.23" - process $proc$libresoc.v:163262$9185 + attribute \src "libresoc.v:165236.7-165236.23" + process $proc$libresoc.v:165236$9230 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:163270.3-163271.29" - process $proc$libresoc.v:163270$9059 + attribute \src "libresoc.v:165244.3-165245.29" + process $proc$libresoc.v:165244$9104 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:163272.3-163273.35" - process $proc$libresoc.v:163272$9060 + attribute \src "libresoc.v:165246.3-165247.35" + process $proc$libresoc.v:165246$9105 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163274.3-163275.29" - process $proc$libresoc.v:163274$9061 + attribute \src "libresoc.v:165248.3-165249.29" + process $proc$libresoc.v:165248$9106 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:163276.3-163277.35" - process $proc$libresoc.v:163276$9062 + attribute \src "libresoc.v:165250.3-165251.35" + process $proc$libresoc.v:165250$9107 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:163278.3-163279.25" - process $proc$libresoc.v:163278$9063 + attribute \src "libresoc.v:165252.3-165253.25" + process $proc$libresoc.v:165252$9108 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:163280.3-163281.31" - process $proc$libresoc.v:163280$9064 + attribute \src "libresoc.v:165254.3-165255.31" + process $proc$libresoc.v:165254$9109 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:163282.3-163283.19" - process $proc$libresoc.v:163282$9065 + attribute \src "libresoc.v:165256.3-165257.19" + process $proc$libresoc.v:165256$9110 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:163284.3-163285.25" - process $proc$libresoc.v:163284$9066 + attribute \src "libresoc.v:165258.3-165259.25" + process $proc$libresoc.v:165258$9111 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:163286.3-163287.49" - process $proc$libresoc.v:163286$9067 + attribute \src "libresoc.v:165260.3-165261.49" + process $proc$libresoc.v:165260$9112 assign { } { } assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:163288.3-163289.45" - process $proc$libresoc.v:163288$9068 + attribute \src "libresoc.v:165262.3-165263.45" + process $proc$libresoc.v:165262$9113 assign { } { } - assign $0\sr_op__fn_unit[12:0] \sr_op__fn_unit$next + assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk - update \sr_op__fn_unit $0\sr_op__fn_unit[12:0] + update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:163290.3-163291.59" - process $proc$libresoc.v:163290$9069 + attribute \src "libresoc.v:165264.3-165265.59" + process $proc$libresoc.v:165264$9114 assign { } { } assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:163292.3-163293.55" - process $proc$libresoc.v:163292$9070 + attribute \src "libresoc.v:165266.3-165267.55" + process $proc$libresoc.v:165266$9115 assign { } { } assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:163294.3-163295.43" - process $proc$libresoc.v:163294$9071 + attribute \src "libresoc.v:165268.3-165269.43" + process $proc$libresoc.v:165268$9116 assign { } { } assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:163296.3-163297.43" - process $proc$libresoc.v:163296$9072 + attribute \src "libresoc.v:165270.3-165271.43" + process $proc$libresoc.v:165270$9117 assign { } { } assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:163298.3-163299.43" - process $proc$libresoc.v:163298$9073 + attribute \src "libresoc.v:165272.3-165273.43" + process $proc$libresoc.v:165272$9118 assign { } { } assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:163300.3-163301.43" - process $proc$libresoc.v:163300$9074 + attribute \src "libresoc.v:165274.3-165275.43" + process $proc$libresoc.v:165274$9119 assign { } { } assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:163302.3-163303.49" - process $proc$libresoc.v:163302$9075 + attribute \src "libresoc.v:165276.3-165277.49" + process $proc$libresoc.v:165276$9120 assign { } { } assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:163304.3-163305.49" - process $proc$libresoc.v:163304$9076 + attribute \src "libresoc.v:165278.3-165279.49" + process $proc$libresoc.v:165278$9121 assign { } { } assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:163306.3-163307.53" - process $proc$libresoc.v:163306$9077 + attribute \src "libresoc.v:165280.3-165281.53" + process $proc$libresoc.v:165280$9122 assign { } { } assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:163308.3-163309.55" - process $proc$libresoc.v:163308$9078 + attribute \src "libresoc.v:165282.3-165283.55" + process $proc$libresoc.v:165282$9123 assign { } { } assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:163310.3-163311.47" - process $proc$libresoc.v:163310$9079 + attribute \src "libresoc.v:165284.3-165285.47" + process $proc$libresoc.v:165284$9124 assign { } { } assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:163312.3-163313.49" - process $proc$libresoc.v:163312$9080 + attribute \src "libresoc.v:165286.3-165287.49" + process $proc$libresoc.v:165286$9125 assign { } { } assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:163314.3-163315.47" - process $proc$libresoc.v:163314$9081 + attribute \src "libresoc.v:165288.3-165289.47" + process $proc$libresoc.v:165288$9126 assign { } { } assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:163316.3-163317.49" - process $proc$libresoc.v:163316$9082 + attribute \src "libresoc.v:165290.3-165291.49" + process $proc$libresoc.v:165290$9127 assign { } { } assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:163318.3-163319.39" - process $proc$libresoc.v:163318$9083 + attribute \src "libresoc.v:165292.3-165293.39" + process $proc$libresoc.v:165292$9128 assign { } { } assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:163320.3-163321.27" - process $proc$libresoc.v:163320$9084 + attribute \src "libresoc.v:165294.3-165295.27" + process $proc$libresoc.v:165294$9129 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:163322.3-163323.29" - process $proc$libresoc.v:163322$9085 + attribute \src "libresoc.v:165296.3-165297.29" + process $proc$libresoc.v:165296$9130 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:163426.3-163444.6" - process $proc$libresoc.v:163426$9086 + attribute \src "libresoc.v:165400.3-165418.6" + process $proc$libresoc.v:165400$9131 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9088 $1\xer_ca$next[1:0]$9090 - assign $0\xer_ca_ok$next[0:0]$9087 $2\xer_ca_ok$next[0:0]$9091 - attribute \src "libresoc.v:163427.5-163427.29" + assign $0\xer_ca$next[1:0]$9133 $1\xer_ca$next[1:0]$9135 + assign $0\xer_ca_ok$next[0:0]$9132 $2\xer_ca_ok$next[0:0]$9136 + attribute \src "libresoc.v:165401.5-165401.29" switch \initial - attribute \src "libresoc.v:163427.9-163427.17" + attribute \src "libresoc.v:165401.9-165401.17" case 1'1 case end @@ -339242,38 +341911,38 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9089 $1\xer_ca$next[1:0]$9090 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9134 $1\xer_ca$next[1:0]$9135 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9089 $1\xer_ca$next[1:0]$9090 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9134 $1\xer_ca$next[1:0]$9135 } { \xer_ca_ok$95 \xer_ca$94 } case - assign $1\xer_ca_ok$next[0:0]$9089 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9090 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9134 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9135 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9091 1'0 + assign $2\xer_ca_ok$next[0:0]$9136 1'0 case - assign $2\xer_ca_ok$next[0:0]$9091 $1\xer_ca_ok$next[0:0]$9089 + assign $2\xer_ca_ok$next[0:0]$9136 $1\xer_ca_ok$next[0:0]$9134 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9087 - update \xer_ca$next $0\xer_ca$next[1:0]$9088 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9132 + update \xer_ca$next $0\xer_ca$next[1:0]$9133 end - attribute \src "libresoc.v:163445.3-163462.6" - process $proc$libresoc.v:163445$9092 + attribute \src "libresoc.v:165419.3-165436.6" + process $proc$libresoc.v:165419$9137 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9093 $2\r_busy$next[0:0]$9095 - attribute \src "libresoc.v:163446.5-163446.29" + assign $0\r_busy$next[0:0]$9138 $2\r_busy$next[0:0]$9140 + attribute \src "libresoc.v:165420.5-165420.29" switch \initial - attribute \src "libresoc.v:163446.9-163446.17" + attribute \src "libresoc.v:165420.9-165420.17" case 1'1 case end @@ -339282,34 +341951,34 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9094 1'1 + assign $1\r_busy$next[0:0]$9139 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9094 1'0 + assign $1\r_busy$next[0:0]$9139 1'0 case - assign $1\r_busy$next[0:0]$9094 \r_busy + assign $1\r_busy$next[0:0]$9139 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9095 1'0 + assign $2\r_busy$next[0:0]$9140 1'0 case - assign $2\r_busy$next[0:0]$9095 $1\r_busy$next[0:0]$9094 + assign $2\r_busy$next[0:0]$9140 $1\r_busy$next[0:0]$9139 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9093 + update \r_busy$next $0\r_busy$next[0:0]$9138 end - attribute \src "libresoc.v:163463.3-163475.6" - process $proc$libresoc.v:163463$9096 + attribute \src "libresoc.v:165437.3-165449.6" + process $proc$libresoc.v:165437$9141 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9097 $1\muxid$next[1:0]$9098 - attribute \src "libresoc.v:163464.5-163464.29" + assign $0\muxid$next[1:0]$9142 $1\muxid$next[1:0]$9143 + attribute \src "libresoc.v:165438.5-165438.29" switch \initial - attribute \src "libresoc.v:163464.9-163464.17" + attribute \src "libresoc.v:165438.9-165438.17" case 1'1 case end @@ -339318,19 +341987,19 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9098 \muxid$67 + assign $1\muxid$next[1:0]$9143 \muxid$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9098 \muxid$67 + assign $1\muxid$next[1:0]$9143 \muxid$67 case - assign $1\muxid$next[1:0]$9098 \muxid + assign $1\muxid$next[1:0]$9143 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9097 + update \muxid$next $0\muxid$next[1:0]$9142 end - attribute \src "libresoc.v:163476.3-163516.6" - process $proc$libresoc.v:163476$9099 + attribute \src "libresoc.v:165450.3-165490.6" + process $proc$libresoc.v:165450$9144 assign { } { } assign { } { } assign { } { } @@ -339365,32 +342034,32 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$next[12:0]$9100 $1\sr_op__fn_unit$next[12:0]$9117 + assign $0\sr_op__fn_unit$next[13:0]$9145 $1\sr_op__fn_unit$next[13:0]$9162 assign { } { } assign { } { } - assign $0\sr_op__input_carry$next[1:0]$9103 $1\sr_op__input_carry$next[1:0]$9120 - assign $0\sr_op__input_cr$next[0:0]$9104 $1\sr_op__input_cr$next[0:0]$9121 - assign $0\sr_op__insn$next[31:0]$9105 $1\sr_op__insn$next[31:0]$9122 - assign $0\sr_op__insn_type$next[6:0]$9106 $1\sr_op__insn_type$next[6:0]$9123 - assign $0\sr_op__invert_in$next[0:0]$9107 $1\sr_op__invert_in$next[0:0]$9124 - assign $0\sr_op__is_32bit$next[0:0]$9108 $1\sr_op__is_32bit$next[0:0]$9125 - assign $0\sr_op__is_signed$next[0:0]$9109 $1\sr_op__is_signed$next[0:0]$9126 + assign $0\sr_op__input_carry$next[1:0]$9148 $1\sr_op__input_carry$next[1:0]$9165 + assign $0\sr_op__input_cr$next[0:0]$9149 $1\sr_op__input_cr$next[0:0]$9166 + assign $0\sr_op__insn$next[31:0]$9150 $1\sr_op__insn$next[31:0]$9167 + assign $0\sr_op__insn_type$next[6:0]$9151 $1\sr_op__insn_type$next[6:0]$9168 + assign $0\sr_op__invert_in$next[0:0]$9152 $1\sr_op__invert_in$next[0:0]$9169 + assign $0\sr_op__is_32bit$next[0:0]$9153 $1\sr_op__is_32bit$next[0:0]$9170 + assign $0\sr_op__is_signed$next[0:0]$9154 $1\sr_op__is_signed$next[0:0]$9171 assign { } { } assign { } { } - assign $0\sr_op__output_carry$next[0:0]$9112 $1\sr_op__output_carry$next[0:0]$9129 - assign $0\sr_op__output_cr$next[0:0]$9113 $1\sr_op__output_cr$next[0:0]$9130 + assign $0\sr_op__output_carry$next[0:0]$9157 $1\sr_op__output_carry$next[0:0]$9174 + assign $0\sr_op__output_cr$next[0:0]$9158 $1\sr_op__output_cr$next[0:0]$9175 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$9116 $1\sr_op__write_cr0$next[0:0]$9133 - assign $0\sr_op__imm_data__data$next[63:0]$9101 $2\sr_op__imm_data__data$next[63:0]$9134 - assign $0\sr_op__imm_data__ok$next[0:0]$9102 $2\sr_op__imm_data__ok$next[0:0]$9135 - assign $0\sr_op__oe__oe$next[0:0]$9110 $2\sr_op__oe__oe$next[0:0]$9136 - assign $0\sr_op__oe__ok$next[0:0]$9111 $2\sr_op__oe__ok$next[0:0]$9137 - assign $0\sr_op__rc__ok$next[0:0]$9114 $2\sr_op__rc__ok$next[0:0]$9138 - assign $0\sr_op__rc__rc$next[0:0]$9115 $2\sr_op__rc__rc$next[0:0]$9139 - attribute \src "libresoc.v:163477.5-163477.29" + assign $0\sr_op__write_cr0$next[0:0]$9161 $1\sr_op__write_cr0$next[0:0]$9178 + assign $0\sr_op__imm_data__data$next[63:0]$9146 $2\sr_op__imm_data__data$next[63:0]$9179 + assign $0\sr_op__imm_data__ok$next[0:0]$9147 $2\sr_op__imm_data__ok$next[0:0]$9180 + assign $0\sr_op__oe__oe$next[0:0]$9155 $2\sr_op__oe__oe$next[0:0]$9181 + assign $0\sr_op__oe__ok$next[0:0]$9156 $2\sr_op__oe__ok$next[0:0]$9182 + assign $0\sr_op__rc__ok$next[0:0]$9159 $2\sr_op__rc__ok$next[0:0]$9183 + assign $0\sr_op__rc__rc$next[0:0]$9160 $2\sr_op__rc__rc$next[0:0]$9184 + attribute \src "libresoc.v:165451.5-165451.29" switch \initial - attribute \src "libresoc.v:163477.9-163477.17" + attribute \src "libresoc.v:165451.9-165451.17" case 1'1 case end @@ -339415,7 +342084,7 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9122 $1\sr_op__is_signed$next[0:0]$9126 $1\sr_op__is_32bit$next[0:0]$9125 $1\sr_op__output_cr$next[0:0]$9130 $1\sr_op__input_cr$next[0:0]$9121 $1\sr_op__output_carry$next[0:0]$9129 $1\sr_op__input_carry$next[1:0]$9120 $1\sr_op__invert_in$next[0:0]$9124 $1\sr_op__write_cr0$next[0:0]$9133 $1\sr_op__oe__ok$next[0:0]$9128 $1\sr_op__oe__oe$next[0:0]$9127 $1\sr_op__rc__ok$next[0:0]$9131 $1\sr_op__rc__rc$next[0:0]$9132 $1\sr_op__imm_data__ok$next[0:0]$9119 $1\sr_op__imm_data__data$next[63:0]$9118 $1\sr_op__fn_unit$next[12:0]$9117 $1\sr_op__insn_type$next[6:0]$9123 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9167 $1\sr_op__is_signed$next[0:0]$9171 $1\sr_op__is_32bit$next[0:0]$9170 $1\sr_op__output_cr$next[0:0]$9175 $1\sr_op__input_cr$next[0:0]$9166 $1\sr_op__output_carry$next[0:0]$9174 $1\sr_op__input_carry$next[1:0]$9165 $1\sr_op__invert_in$next[0:0]$9169 $1\sr_op__write_cr0$next[0:0]$9178 $1\sr_op__oe__ok$next[0:0]$9173 $1\sr_op__oe__oe$next[0:0]$9172 $1\sr_op__rc__ok$next[0:0]$9176 $1\sr_op__rc__rc$next[0:0]$9177 $1\sr_op__imm_data__ok$next[0:0]$9164 $1\sr_op__imm_data__data$next[63:0]$9163 $1\sr_op__fn_unit$next[13:0]$9162 $1\sr_op__insn_type$next[6:0]$9168 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -339435,25 +342104,25 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9122 $1\sr_op__is_signed$next[0:0]$9126 $1\sr_op__is_32bit$next[0:0]$9125 $1\sr_op__output_cr$next[0:0]$9130 $1\sr_op__input_cr$next[0:0]$9121 $1\sr_op__output_carry$next[0:0]$9129 $1\sr_op__input_carry$next[1:0]$9120 $1\sr_op__invert_in$next[0:0]$9124 $1\sr_op__write_cr0$next[0:0]$9133 $1\sr_op__oe__ok$next[0:0]$9128 $1\sr_op__oe__oe$next[0:0]$9127 $1\sr_op__rc__ok$next[0:0]$9131 $1\sr_op__rc__rc$next[0:0]$9132 $1\sr_op__imm_data__ok$next[0:0]$9119 $1\sr_op__imm_data__data$next[63:0]$9118 $1\sr_op__fn_unit$next[12:0]$9117 $1\sr_op__insn_type$next[6:0]$9123 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9167 $1\sr_op__is_signed$next[0:0]$9171 $1\sr_op__is_32bit$next[0:0]$9170 $1\sr_op__output_cr$next[0:0]$9175 $1\sr_op__input_cr$next[0:0]$9166 $1\sr_op__output_carry$next[0:0]$9174 $1\sr_op__input_carry$next[1:0]$9165 $1\sr_op__invert_in$next[0:0]$9169 $1\sr_op__write_cr0$next[0:0]$9178 $1\sr_op__oe__ok$next[0:0]$9173 $1\sr_op__oe__oe$next[0:0]$9172 $1\sr_op__rc__ok$next[0:0]$9176 $1\sr_op__rc__rc$next[0:0]$9177 $1\sr_op__imm_data__ok$next[0:0]$9164 $1\sr_op__imm_data__data$next[63:0]$9163 $1\sr_op__fn_unit$next[13:0]$9162 $1\sr_op__insn_type$next[6:0]$9168 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case - assign $1\sr_op__fn_unit$next[12:0]$9117 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$9118 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$9119 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$9120 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$9121 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$9122 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$9123 \sr_op__insn_type - assign $1\sr_op__invert_in$next[0:0]$9124 \sr_op__invert_in - assign $1\sr_op__is_32bit$next[0:0]$9125 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$9126 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$9127 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$9128 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$9129 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$9130 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$9131 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$9132 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$9133 \sr_op__write_cr0 + assign $1\sr_op__fn_unit$next[13:0]$9162 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9163 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9164 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9165 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9166 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9167 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9168 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9169 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9170 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9171 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9172 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9173 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9174 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9175 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9176 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9177 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9178 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -339465,51 +342134,51 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$9134 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$9135 1'0 - assign $2\sr_op__rc__rc$next[0:0]$9139 1'0 - assign $2\sr_op__rc__ok$next[0:0]$9138 1'0 - assign $2\sr_op__oe__oe$next[0:0]$9136 1'0 - assign $2\sr_op__oe__ok$next[0:0]$9137 1'0 + assign $2\sr_op__imm_data__data$next[63:0]$9179 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9180 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9184 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9183 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9181 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9182 1'0 case - assign $2\sr_op__imm_data__data$next[63:0]$9134 $1\sr_op__imm_data__data$next[63:0]$9118 - assign $2\sr_op__imm_data__ok$next[0:0]$9135 $1\sr_op__imm_data__ok$next[0:0]$9119 - assign $2\sr_op__oe__oe$next[0:0]$9136 $1\sr_op__oe__oe$next[0:0]$9127 - assign $2\sr_op__oe__ok$next[0:0]$9137 $1\sr_op__oe__ok$next[0:0]$9128 - assign $2\sr_op__rc__ok$next[0:0]$9138 $1\sr_op__rc__ok$next[0:0]$9131 - assign $2\sr_op__rc__rc$next[0:0]$9139 $1\sr_op__rc__rc$next[0:0]$9132 + assign $2\sr_op__imm_data__data$next[63:0]$9179 $1\sr_op__imm_data__data$next[63:0]$9163 + assign $2\sr_op__imm_data__ok$next[0:0]$9180 $1\sr_op__imm_data__ok$next[0:0]$9164 + assign $2\sr_op__oe__oe$next[0:0]$9181 $1\sr_op__oe__oe$next[0:0]$9172 + assign $2\sr_op__oe__ok$next[0:0]$9182 $1\sr_op__oe__ok$next[0:0]$9173 + assign $2\sr_op__rc__ok$next[0:0]$9183 $1\sr_op__rc__ok$next[0:0]$9176 + assign $2\sr_op__rc__rc$next[0:0]$9184 $1\sr_op__rc__rc$next[0:0]$9177 end sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[12:0]$9100 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9101 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9102 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9103 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9104 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9105 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9106 - update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9107 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9108 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9109 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9110 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9111 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9112 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9113 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9114 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9115 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9116 + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9145 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9146 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9147 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9148 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9149 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9150 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9151 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9152 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9153 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9154 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9155 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9156 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9157 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9158 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9159 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9160 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9161 end - attribute \src "libresoc.v:163517.3-163535.6" - process $proc$libresoc.v:163517$9140 + attribute \src "libresoc.v:165491.3-165509.6" + process $proc$libresoc.v:165491$9185 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9141 $1\o$next[63:0]$9143 + assign $0\o$next[63:0]$9186 $1\o$next[63:0]$9188 assign { } { } - assign $0\o_ok$next[0:0]$9142 $2\o_ok$next[0:0]$9145 - attribute \src "libresoc.v:163518.5-163518.29" + assign $0\o_ok$next[0:0]$9187 $2\o_ok$next[0:0]$9190 + attribute \src "libresoc.v:165492.5-165492.29" switch \initial - attribute \src "libresoc.v:163518.9-163518.17" + attribute \src "libresoc.v:165492.9-165492.17" case 1'1 case end @@ -339519,41 +342188,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9144 $1\o$next[63:0]$9143 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9189 $1\o$next[63:0]$9188 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9144 $1\o$next[63:0]$9143 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9189 $1\o$next[63:0]$9188 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$9143 \o - assign $1\o_ok$next[0:0]$9144 \o_ok + assign $1\o$next[63:0]$9188 \o + assign $1\o_ok$next[0:0]$9189 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9145 1'0 + assign $2\o_ok$next[0:0]$9190 1'0 case - assign $2\o_ok$next[0:0]$9145 $1\o_ok$next[0:0]$9144 + assign $2\o_ok$next[0:0]$9190 $1\o_ok$next[0:0]$9189 end sync always - update \o$next $0\o$next[63:0]$9141 - update \o_ok$next $0\o_ok$next[0:0]$9142 + update \o$next $0\o$next[63:0]$9186 + update \o_ok$next $0\o_ok$next[0:0]$9187 end - attribute \src "libresoc.v:163536.3-163554.6" - process $proc$libresoc.v:163536$9146 + attribute \src "libresoc.v:165510.3-165528.6" + process $proc$libresoc.v:165510$9191 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9147 $1\cr_a$next[3:0]$9149 + assign $0\cr_a$next[3:0]$9192 $1\cr_a$next[3:0]$9194 assign { } { } - assign $0\cr_a_ok$next[0:0]$9148 $2\cr_a_ok$next[0:0]$9151 - attribute \src "libresoc.v:163537.5-163537.29" + assign $0\cr_a_ok$next[0:0]$9193 $2\cr_a_ok$next[0:0]$9196 + attribute \src "libresoc.v:165511.5-165511.29" switch \initial - attribute \src "libresoc.v:163537.9-163537.17" + attribute \src "libresoc.v:165511.9-165511.17" case 1'1 case end @@ -339563,41 +342232,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9150 $1\cr_a$next[3:0]$9149 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9195 $1\cr_a$next[3:0]$9194 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9150 $1\cr_a$next[3:0]$9149 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9195 $1\cr_a$next[3:0]$9194 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$9149 \cr_a - assign $1\cr_a_ok$next[0:0]$9150 \cr_a_ok + assign $1\cr_a$next[3:0]$9194 \cr_a + assign $1\cr_a_ok$next[0:0]$9195 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9151 1'0 + assign $2\cr_a_ok$next[0:0]$9196 1'0 case - assign $2\cr_a_ok$next[0:0]$9151 $1\cr_a_ok$next[0:0]$9150 + assign $2\cr_a_ok$next[0:0]$9196 $1\cr_a_ok$next[0:0]$9195 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9147 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9148 + update \cr_a$next $0\cr_a$next[3:0]$9192 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9193 end - attribute \src "libresoc.v:163555.3-163573.6" - process $proc$libresoc.v:163555$9152 + attribute \src "libresoc.v:165529.3-165547.6" + process $proc$libresoc.v:165529$9197 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9153 $1\xer_so$next[0:0]$9155 + assign $0\xer_so$next[0:0]$9198 $1\xer_so$next[0:0]$9200 assign { } { } - assign $0\xer_so_ok$next[0:0]$9154 $2\xer_so_ok$next[0:0]$9157 - attribute \src "libresoc.v:163556.5-163556.29" + assign $0\xer_so_ok$next[0:0]$9199 $2\xer_so_ok$next[0:0]$9202 + attribute \src "libresoc.v:165530.5-165530.29" switch \initial - attribute \src "libresoc.v:163556.9-163556.17" + attribute \src "libresoc.v:165530.9-165530.17" case 1'1 case end @@ -339607,30 +342276,30 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9156 $1\xer_so$next[0:0]$9155 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9201 $1\xer_so$next[0:0]$9200 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9156 $1\xer_so$next[0:0]$9155 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9201 $1\xer_so$next[0:0]$9200 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$9155 \xer_so - assign $1\xer_so_ok$next[0:0]$9156 \xer_so_ok + assign $1\xer_so$next[0:0]$9200 \xer_so + assign $1\xer_so_ok$next[0:0]$9201 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9157 1'0 + assign $2\xer_so_ok$next[0:0]$9202 1'0 case - assign $2\xer_so_ok$next[0:0]$9157 $1\xer_so_ok$next[0:0]$9156 + assign $2\xer_so_ok$next[0:0]$9202 $1\xer_so_ok$next[0:0]$9201 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9153 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9154 + update \xer_so$next $0\xer_so$next[0:0]$9198 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9199 end - connect \$65 $and$libresoc.v:163269$9058_Y + connect \$65 $and$libresoc.v:165243$9103_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -339661,142 +342330,142 @@ module \pipe1$110 connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:163607.1-164445.10" +attribute \src "libresoc.v:165581.1-166429.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" module \pipe1$32 - attribute \src "libresoc.v:164402.3-164414.6" - wire width 64 $0\fast1$next[63:0]$9235 - attribute \src "libresoc.v:164258.3-164259.27" + attribute \src "libresoc.v:166386.3-166398.6" + wire width 64 $0\fast1$next[63:0]$9280 + attribute \src "libresoc.v:166242.3-166243.27" wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:164415.3-164427.6" - wire width 64 $0\fast2$next[63:0]$9238 - attribute \src "libresoc.v:164256.3-164257.27" + attribute \src "libresoc.v:166399.3-166411.6" + wire width 64 $0\fast2$next[63:0]$9283 + attribute \src "libresoc.v:166240.3-166241.27" wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:163608.7-163608.20" + attribute \src "libresoc.v:165582.7-165582.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164342.3-164354.6" - wire width 2 $0\muxid$next[1:0]$9207 - attribute \src "libresoc.v:164282.3-164283.27" + attribute \src "libresoc.v:166326.3-166338.6" + wire width 2 $0\muxid$next[1:0]$9252 + attribute \src "libresoc.v:166266.3-166267.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:164324.3-164341.6" - wire $0\r_busy$next[0:0]$9203 - attribute \src "libresoc.v:164284.3-164285.29" + attribute \src "libresoc.v:166308.3-166325.6" + wire $0\r_busy$next[0:0]$9248 + attribute \src "libresoc.v:166268.3-166269.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:164376.3-164388.6" - wire width 64 $0\ra$next[63:0]$9229 - attribute \src "libresoc.v:164262.3-164263.21" + attribute \src "libresoc.v:166360.3-166372.6" + wire width 64 $0\ra$next[63:0]$9274 + attribute \src "libresoc.v:166246.3-166247.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:164389.3-164401.6" - wire width 64 $0\rb$next[63:0]$9232 - attribute \src "libresoc.v:164260.3-164261.21" + attribute \src "libresoc.v:166373.3-166385.6" + wire width 64 $0\rb$next[63:0]$9277 + attribute \src "libresoc.v:166244.3-166245.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 64 $0\trap_op__cia$next[63:0]$9210 - attribute \src "libresoc.v:164272.3-164273.41" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 64 $0\trap_op__cia$next[63:0]$9255 + attribute \src "libresoc.v:166256.3-166257.41" wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 13 $0\trap_op__fn_unit$next[12:0]$9211 - attribute \src "libresoc.v:164266.3-164267.49" - wire width 13 $0\trap_op__fn_unit[12:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 32 $0\trap_op__insn$next[31:0]$9212 - attribute \src "libresoc.v:164268.3-164269.43" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 14 $0\trap_op__fn_unit$next[13:0]$9256 + attribute \src "libresoc.v:166250.3-166251.49" + wire width 14 $0\trap_op__fn_unit[13:0] + attribute \src "libresoc.v:166339.3-166359.6" + wire width 32 $0\trap_op__insn$next[31:0]$9257 + attribute \src "libresoc.v:166252.3-166253.43" wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 7 $0\trap_op__insn_type$next[6:0]$9213 - attribute \src "libresoc.v:164264.3-164265.53" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$9258 + attribute \src "libresoc.v:166248.3-166249.53" wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire $0\trap_op__is_32bit$next[0:0]$9214 - attribute \src "libresoc.v:164274.3-164275.51" + attribute \src "libresoc.v:166339.3-166359.6" + wire $0\trap_op__is_32bit$next[0:0]$9259 + attribute \src "libresoc.v:166258.3-166259.51" wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 8 $0\trap_op__ldst_exc$next[7:0]$9215 - attribute \src "libresoc.v:164280.3-164281.51" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$9260 + attribute \src "libresoc.v:166264.3-166265.51" wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 64 $0\trap_op__msr$next[63:0]$9216 - attribute \src "libresoc.v:164270.3-164271.41" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 64 $0\trap_op__msr$next[63:0]$9261 + attribute \src "libresoc.v:166254.3-166255.41" wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 13 $0\trap_op__trapaddr$next[12:0]$9217 - attribute \src "libresoc.v:164278.3-164279.51" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$9262 + attribute \src "libresoc.v:166262.3-166263.51" wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 8 $0\trap_op__traptype$next[7:0]$9218 - attribute \src "libresoc.v:164276.3-164277.51" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 8 $0\trap_op__traptype$next[7:0]$9263 + attribute \src "libresoc.v:166260.3-166261.51" wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:164402.3-164414.6" - wire width 64 $1\fast1$next[63:0]$9236 - attribute \src "libresoc.v:163849.14-163849.42" + attribute \src "libresoc.v:166386.3-166398.6" + wire width 64 $1\fast1$next[63:0]$9281 + attribute \src "libresoc.v:165827.14-165827.42" wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:164415.3-164427.6" - wire width 64 $1\fast2$next[63:0]$9239 - attribute \src "libresoc.v:163858.14-163858.42" + attribute \src "libresoc.v:166399.3-166411.6" + wire width 64 $1\fast2$next[63:0]$9284 + attribute \src "libresoc.v:165836.14-165836.42" wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:164342.3-164354.6" - wire width 2 $1\muxid$next[1:0]$9208 - attribute \src "libresoc.v:163867.13-163867.25" + attribute \src "libresoc.v:166326.3-166338.6" + wire width 2 $1\muxid$next[1:0]$9253 + attribute \src "libresoc.v:165845.13-165845.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:164324.3-164341.6" - wire $1\r_busy$next[0:0]$9204 - attribute \src "libresoc.v:163889.7-163889.20" + attribute \src "libresoc.v:166308.3-166325.6" + wire $1\r_busy$next[0:0]$9249 + attribute \src "libresoc.v:165867.7-165867.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:164376.3-164388.6" - wire width 64 $1\ra$next[63:0]$9230 - attribute \src "libresoc.v:163894.14-163894.39" + attribute \src "libresoc.v:166360.3-166372.6" + wire width 64 $1\ra$next[63:0]$9275 + attribute \src "libresoc.v:165872.14-165872.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:164389.3-164401.6" - wire width 64 $1\rb$next[63:0]$9233 - attribute \src "libresoc.v:163903.14-163903.39" + attribute \src "libresoc.v:166373.3-166385.6" + wire width 64 $1\rb$next[63:0]$9278 + attribute \src "libresoc.v:165881.14-165881.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 64 $1\trap_op__cia$next[63:0]$9219 - attribute \src "libresoc.v:163912.14-163912.49" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 64 $1\trap_op__cia$next[63:0]$9264 + attribute \src "libresoc.v:165890.14-165890.49" wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 13 $1\trap_op__fn_unit$next[12:0]$9220 - attribute \src "libresoc.v:163935.14-163935.41" - wire width 13 $1\trap_op__fn_unit[12:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 32 $1\trap_op__insn$next[31:0]$9221 - attribute \src "libresoc.v:163972.14-163972.35" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 14 $1\trap_op__fn_unit$next[13:0]$9265 + attribute \src "libresoc.v:165914.14-165914.41" + wire width 14 $1\trap_op__fn_unit[13:0] + attribute \src "libresoc.v:166339.3-166359.6" + wire width 32 $1\trap_op__insn$next[31:0]$9266 + attribute \src "libresoc.v:165953.14-165953.35" wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 7 $1\trap_op__insn_type$next[6:0]$9222 - attribute \src "libresoc.v:164055.13-164055.39" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$9267 + attribute \src "libresoc.v:166037.13-166037.39" wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire $1\trap_op__is_32bit$next[0:0]$9223 - attribute \src "libresoc.v:164212.7-164212.31" + attribute \src "libresoc.v:166339.3-166359.6" + wire $1\trap_op__is_32bit$next[0:0]$9268 + attribute \src "libresoc.v:166196.7-166196.31" wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 8 $1\trap_op__ldst_exc$next[7:0]$9224 - attribute \src "libresoc.v:164221.13-164221.38" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$9269 + attribute \src "libresoc.v:166205.13-166205.38" wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 64 $1\trap_op__msr$next[63:0]$9225 - attribute \src "libresoc.v:164230.14-164230.49" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 64 $1\trap_op__msr$next[63:0]$9270 + attribute \src "libresoc.v:166214.14-166214.49" wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 13 $1\trap_op__trapaddr$next[12:0]$9226 - attribute \src "libresoc.v:164239.14-164239.42" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$9271 + attribute \src "libresoc.v:166223.14-166223.42" wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:164355.3-164375.6" - wire width 8 $1\trap_op__traptype$next[7:0]$9227 - attribute \src "libresoc.v:164248.13-164248.38" + attribute \src "libresoc.v:166339.3-166359.6" + wire width 8 $1\trap_op__traptype$next[7:0]$9272 + attribute \src "libresoc.v:166232.13-166232.38" wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:164324.3-164341.6" - wire $2\r_busy$next[0:0]$9205 - attribute \src "libresoc.v:164255.18-164255.118" - wire $and$libresoc.v:164255$9186_Y + attribute \src "libresoc.v:166308.3-166325.6" + wire $2\r_busy$next[0:0]$9250 + attribute \src "libresoc.v:166239.18-166239.118" + wire $and$libresoc.v:166239$9231_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast1 @@ -339823,37 +342492,39 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dummy_trap_op__cia$20 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dummy_trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dummy_trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dummy_trap_op__fn_unit$17 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \dummy_trap_op__fn_unit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dummy_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -339932,6 +342603,7 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dummy_trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -340008,6 +342680,7 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dummy_trap_op__insn_type$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -340046,7 +342719,7 @@ module \pipe1$32 wire width 64 \fast2$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$next - attribute \src "libresoc.v:163608.7-163608.15" + attribute \src "libresoc.v:165582.7-165582.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -340099,55 +342772,58 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__cia$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 22 \trap_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 22 \trap_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -340230,6 +342906,7 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -340306,6 +342983,7 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 21 \trap_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -340382,6 +343060,7 @@ module \pipe1$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -340427,7 +343106,7 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:164255$9186 + cell $and $and$libresoc.v:166239$9231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -340435,10 +343114,10 @@ module \pipe1$32 parameter \Y_WIDTH 1 connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:164255$9186_Y + connect \Y $and$libresoc.v:166239$9231_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:164286.9-164315.4" + attribute \src "libresoc.v:166270.9-166299.4" cell \dummy \dummy connect \fast1 \dummy_fast1 connect \fast1$13 \dummy_fast1$27 @@ -340470,259 +343149,259 @@ module \pipe1$32 connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:164316.10-164319.4" + attribute \src "libresoc.v:166300.10-166303.4" cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:164320.10-164323.4" + attribute \src "libresoc.v:166304.10-166307.4" cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:163608.7-163608.20" - process $proc$libresoc.v:163608$9240 + attribute \src "libresoc.v:165582.7-165582.20" + process $proc$libresoc.v:165582$9285 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163849.14-163849.42" - process $proc$libresoc.v:163849$9241 + attribute \src "libresoc.v:165827.14-165827.42" + process $proc$libresoc.v:165827$9286 assign { } { } assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:163858.14-163858.42" - process $proc$libresoc.v:163858$9242 + attribute \src "libresoc.v:165836.14-165836.42" + process $proc$libresoc.v:165836$9287 assign { } { } assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:163867.13-163867.25" - process $proc$libresoc.v:163867$9243 + attribute \src "libresoc.v:165845.13-165845.25" + process $proc$libresoc.v:165845$9288 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:163889.7-163889.20" - process $proc$libresoc.v:163889$9244 + attribute \src "libresoc.v:165867.7-165867.20" + process $proc$libresoc.v:165867$9289 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163894.14-163894.39" - process $proc$libresoc.v:163894$9245 + attribute \src "libresoc.v:165872.14-165872.39" + process $proc$libresoc.v:165872$9290 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:163903.14-163903.39" - process $proc$libresoc.v:163903$9246 + attribute \src "libresoc.v:165881.14-165881.39" + process $proc$libresoc.v:165881$9291 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:163912.14-163912.49" - process $proc$libresoc.v:163912$9247 + attribute \src "libresoc.v:165890.14-165890.49" + process $proc$libresoc.v:165890$9292 assign { } { } assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:163935.14-163935.41" - process $proc$libresoc.v:163935$9248 + attribute \src "libresoc.v:165914.14-165914.41" + process $proc$libresoc.v:165914$9293 assign { } { } - assign $1\trap_op__fn_unit[12:0] 13'0000000000000 + assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \trap_op__fn_unit $1\trap_op__fn_unit[12:0] + update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:163972.14-163972.35" - process $proc$libresoc.v:163972$9249 + attribute \src "libresoc.v:165953.14-165953.35" + process $proc$libresoc.v:165953$9294 assign { } { } assign $1\trap_op__insn[31:0] 0 sync always sync init update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:164055.13-164055.39" - process $proc$libresoc.v:164055$9250 + attribute \src "libresoc.v:166037.13-166037.39" + process $proc$libresoc.v:166037$9295 assign { } { } assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:164212.7-164212.31" - process $proc$libresoc.v:164212$9251 + attribute \src "libresoc.v:166196.7-166196.31" + process $proc$libresoc.v:166196$9296 assign { } { } assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:164221.13-164221.38" - process $proc$libresoc.v:164221$9252 + attribute \src "libresoc.v:166205.13-166205.38" + process $proc$libresoc.v:166205$9297 assign { } { } assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:164230.14-164230.49" - process $proc$libresoc.v:164230$9253 + attribute \src "libresoc.v:166214.14-166214.49" + process $proc$libresoc.v:166214$9298 assign { } { } assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:164239.14-164239.42" - process $proc$libresoc.v:164239$9254 + attribute \src "libresoc.v:166223.14-166223.42" + process $proc$libresoc.v:166223$9299 assign { } { } assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:164248.13-164248.38" - process $proc$libresoc.v:164248$9255 + attribute \src "libresoc.v:166232.13-166232.38" + process $proc$libresoc.v:166232$9300 assign { } { } assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:164256.3-164257.27" - process $proc$libresoc.v:164256$9187 + attribute \src "libresoc.v:166240.3-166241.27" + process $proc$libresoc.v:166240$9232 assign { } { } assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:164258.3-164259.27" - process $proc$libresoc.v:164258$9188 + attribute \src "libresoc.v:166242.3-166243.27" + process $proc$libresoc.v:166242$9233 assign { } { } assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:164260.3-164261.21" - process $proc$libresoc.v:164260$9189 + attribute \src "libresoc.v:166244.3-166245.21" + process $proc$libresoc.v:166244$9234 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:164262.3-164263.21" - process $proc$libresoc.v:164262$9190 + attribute \src "libresoc.v:166246.3-166247.21" + process $proc$libresoc.v:166246$9235 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:164264.3-164265.53" - process $proc$libresoc.v:164264$9191 + attribute \src "libresoc.v:166248.3-166249.53" + process $proc$libresoc.v:166248$9236 assign { } { } assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:164266.3-164267.49" - process $proc$libresoc.v:164266$9192 + attribute \src "libresoc.v:166250.3-166251.49" + process $proc$libresoc.v:166250$9237 assign { } { } - assign $0\trap_op__fn_unit[12:0] \trap_op__fn_unit$next + assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk - update \trap_op__fn_unit $0\trap_op__fn_unit[12:0] + update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:164268.3-164269.43" - process $proc$libresoc.v:164268$9193 + attribute \src "libresoc.v:166252.3-166253.43" + process $proc$libresoc.v:166252$9238 assign { } { } assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:164270.3-164271.41" - process $proc$libresoc.v:164270$9194 + attribute \src "libresoc.v:166254.3-166255.41" + process $proc$libresoc.v:166254$9239 assign { } { } assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:164272.3-164273.41" - process $proc$libresoc.v:164272$9195 + attribute \src "libresoc.v:166256.3-166257.41" + process $proc$libresoc.v:166256$9240 assign { } { } assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:164274.3-164275.51" - process $proc$libresoc.v:164274$9196 + attribute \src "libresoc.v:166258.3-166259.51" + process $proc$libresoc.v:166258$9241 assign { } { } assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:164276.3-164277.51" - process $proc$libresoc.v:164276$9197 + attribute \src "libresoc.v:166260.3-166261.51" + process $proc$libresoc.v:166260$9242 assign { } { } assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:164278.3-164279.51" - process $proc$libresoc.v:164278$9198 + attribute \src "libresoc.v:166262.3-166263.51" + process $proc$libresoc.v:166262$9243 assign { } { } assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:164280.3-164281.51" - process $proc$libresoc.v:164280$9199 + attribute \src "libresoc.v:166264.3-166265.51" + process $proc$libresoc.v:166264$9244 assign { } { } assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:164282.3-164283.27" - process $proc$libresoc.v:164282$9200 + attribute \src "libresoc.v:166266.3-166267.27" + process $proc$libresoc.v:166266$9245 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:164284.3-164285.29" - process $proc$libresoc.v:164284$9201 + attribute \src "libresoc.v:166268.3-166269.29" + process $proc$libresoc.v:166268$9246 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:164324.3-164341.6" - process $proc$libresoc.v:164324$9202 + attribute \src "libresoc.v:166308.3-166325.6" + process $proc$libresoc.v:166308$9247 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9203 $2\r_busy$next[0:0]$9205 - attribute \src "libresoc.v:164325.5-164325.29" + assign $0\r_busy$next[0:0]$9248 $2\r_busy$next[0:0]$9250 + attribute \src "libresoc.v:166309.5-166309.29" switch \initial - attribute \src "libresoc.v:164325.9-164325.17" + attribute \src "libresoc.v:166309.9-166309.17" case 1'1 case end @@ -340731,34 +343410,34 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9204 1'1 + assign $1\r_busy$next[0:0]$9249 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9204 1'0 + assign $1\r_busy$next[0:0]$9249 1'0 case - assign $1\r_busy$next[0:0]$9204 \r_busy + assign $1\r_busy$next[0:0]$9249 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9205 1'0 + assign $2\r_busy$next[0:0]$9250 1'0 case - assign $2\r_busy$next[0:0]$9205 $1\r_busy$next[0:0]$9204 + assign $2\r_busy$next[0:0]$9250 $1\r_busy$next[0:0]$9249 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9203 + update \r_busy$next $0\r_busy$next[0:0]$9248 end - attribute \src "libresoc.v:164342.3-164354.6" - process $proc$libresoc.v:164342$9206 + attribute \src "libresoc.v:166326.3-166338.6" + process $proc$libresoc.v:166326$9251 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9207 $1\muxid$next[1:0]$9208 - attribute \src "libresoc.v:164343.5-164343.29" + assign $0\muxid$next[1:0]$9252 $1\muxid$next[1:0]$9253 + attribute \src "libresoc.v:166327.5-166327.29" switch \initial - attribute \src "libresoc.v:164343.9-164343.17" + attribute \src "libresoc.v:166327.9-166327.17" case 1'1 case end @@ -340767,19 +343446,19 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9208 \muxid$32 + assign $1\muxid$next[1:0]$9253 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9208 \muxid$32 + assign $1\muxid$next[1:0]$9253 \muxid$32 case - assign $1\muxid$next[1:0]$9208 \muxid + assign $1\muxid$next[1:0]$9253 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9207 + update \muxid$next $0\muxid$next[1:0]$9252 end - attribute \src "libresoc.v:164355.3-164375.6" - process $proc$libresoc.v:164355$9209 + attribute \src "libresoc.v:166339.3-166359.6" + process $proc$libresoc.v:166339$9254 assign { } { } assign { } { } assign { } { } @@ -340798,18 +343477,18 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$next[63:0]$9210 $1\trap_op__cia$next[63:0]$9219 - assign $0\trap_op__fn_unit$next[12:0]$9211 $1\trap_op__fn_unit$next[12:0]$9220 - assign $0\trap_op__insn$next[31:0]$9212 $1\trap_op__insn$next[31:0]$9221 - assign $0\trap_op__insn_type$next[6:0]$9213 $1\trap_op__insn_type$next[6:0]$9222 - assign $0\trap_op__is_32bit$next[0:0]$9214 $1\trap_op__is_32bit$next[0:0]$9223 - assign $0\trap_op__ldst_exc$next[7:0]$9215 $1\trap_op__ldst_exc$next[7:0]$9224 - assign $0\trap_op__msr$next[63:0]$9216 $1\trap_op__msr$next[63:0]$9225 - assign $0\trap_op__trapaddr$next[12:0]$9217 $1\trap_op__trapaddr$next[12:0]$9226 - assign $0\trap_op__traptype$next[7:0]$9218 $1\trap_op__traptype$next[7:0]$9227 - attribute \src "libresoc.v:164356.5-164356.29" + assign $0\trap_op__cia$next[63:0]$9255 $1\trap_op__cia$next[63:0]$9264 + assign $0\trap_op__fn_unit$next[13:0]$9256 $1\trap_op__fn_unit$next[13:0]$9265 + assign $0\trap_op__insn$next[31:0]$9257 $1\trap_op__insn$next[31:0]$9266 + assign $0\trap_op__insn_type$next[6:0]$9258 $1\trap_op__insn_type$next[6:0]$9267 + assign $0\trap_op__is_32bit$next[0:0]$9259 $1\trap_op__is_32bit$next[0:0]$9268 + assign $0\trap_op__ldst_exc$next[7:0]$9260 $1\trap_op__ldst_exc$next[7:0]$9269 + assign $0\trap_op__msr$next[63:0]$9261 $1\trap_op__msr$next[63:0]$9270 + assign $0\trap_op__trapaddr$next[12:0]$9262 $1\trap_op__trapaddr$next[12:0]$9271 + assign $0\trap_op__traptype$next[7:0]$9263 $1\trap_op__traptype$next[7:0]$9272 + attribute \src "libresoc.v:166340.5-166340.29" switch \initial - attribute \src "libresoc.v:164356.9-164356.17" + attribute \src "libresoc.v:166340.9-166340.17" case 1'1 case end @@ -340826,7 +343505,7 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9224 $1\trap_op__trapaddr$next[12:0]$9226 $1\trap_op__traptype$next[7:0]$9227 $1\trap_op__is_32bit$next[0:0]$9223 $1\trap_op__cia$next[63:0]$9219 $1\trap_op__msr$next[63:0]$9225 $1\trap_op__insn$next[31:0]$9221 $1\trap_op__fn_unit$next[12:0]$9220 $1\trap_op__insn_type$next[6:0]$9222 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9269 $1\trap_op__trapaddr$next[12:0]$9271 $1\trap_op__traptype$next[7:0]$9272 $1\trap_op__is_32bit$next[0:0]$9268 $1\trap_op__cia$next[63:0]$9264 $1\trap_op__msr$next[63:0]$9270 $1\trap_op__insn$next[31:0]$9266 $1\trap_op__fn_unit$next[13:0]$9265 $1\trap_op__insn_type$next[6:0]$9267 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -340838,37 +343517,37 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9224 $1\trap_op__trapaddr$next[12:0]$9226 $1\trap_op__traptype$next[7:0]$9227 $1\trap_op__is_32bit$next[0:0]$9223 $1\trap_op__cia$next[63:0]$9219 $1\trap_op__msr$next[63:0]$9225 $1\trap_op__insn$next[31:0]$9221 $1\trap_op__fn_unit$next[12:0]$9220 $1\trap_op__insn_type$next[6:0]$9222 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9269 $1\trap_op__trapaddr$next[12:0]$9271 $1\trap_op__traptype$next[7:0]$9272 $1\trap_op__is_32bit$next[0:0]$9268 $1\trap_op__cia$next[63:0]$9264 $1\trap_op__msr$next[63:0]$9270 $1\trap_op__insn$next[31:0]$9266 $1\trap_op__fn_unit$next[13:0]$9265 $1\trap_op__insn_type$next[6:0]$9267 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case - assign $1\trap_op__cia$next[63:0]$9219 \trap_op__cia - assign $1\trap_op__fn_unit$next[12:0]$9220 \trap_op__fn_unit - assign $1\trap_op__insn$next[31:0]$9221 \trap_op__insn - assign $1\trap_op__insn_type$next[6:0]$9222 \trap_op__insn_type - assign $1\trap_op__is_32bit$next[0:0]$9223 \trap_op__is_32bit - assign $1\trap_op__ldst_exc$next[7:0]$9224 \trap_op__ldst_exc - assign $1\trap_op__msr$next[63:0]$9225 \trap_op__msr - assign $1\trap_op__trapaddr$next[12:0]$9226 \trap_op__trapaddr - assign $1\trap_op__traptype$next[7:0]$9227 \trap_op__traptype + assign $1\trap_op__cia$next[63:0]$9264 \trap_op__cia + assign $1\trap_op__fn_unit$next[13:0]$9265 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9266 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9267 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9268 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9269 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9270 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9271 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9272 \trap_op__traptype end sync always - update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9210 - update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[12:0]$9211 - update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9212 - update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9213 - update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9214 - update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9215 - update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9216 - update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9217 - update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9218 + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9255 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9256 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9257 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9258 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9259 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9260 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9261 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9262 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9263 end - attribute \src "libresoc.v:164376.3-164388.6" - process $proc$libresoc.v:164376$9228 + attribute \src "libresoc.v:166360.3-166372.6" + process $proc$libresoc.v:166360$9273 assign { } { } assign { } { } - assign $0\ra$next[63:0]$9229 $1\ra$next[63:0]$9230 - attribute \src "libresoc.v:164377.5-164377.29" + assign $0\ra$next[63:0]$9274 $1\ra$next[63:0]$9275 + attribute \src "libresoc.v:166361.5-166361.29" switch \initial - attribute \src "libresoc.v:164377.9-164377.17" + attribute \src "libresoc.v:166361.9-166361.17" case 1'1 case end @@ -340877,25 +343556,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$9230 \ra$42 + assign $1\ra$next[63:0]$9275 \ra$42 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$9230 \ra$42 + assign $1\ra$next[63:0]$9275 \ra$42 case - assign $1\ra$next[63:0]$9230 \ra + assign $1\ra$next[63:0]$9275 \ra end sync always - update \ra$next $0\ra$next[63:0]$9229 + update \ra$next $0\ra$next[63:0]$9274 end - attribute \src "libresoc.v:164389.3-164401.6" - process $proc$libresoc.v:164389$9231 + attribute \src "libresoc.v:166373.3-166385.6" + process $proc$libresoc.v:166373$9276 assign { } { } assign { } { } - assign $0\rb$next[63:0]$9232 $1\rb$next[63:0]$9233 - attribute \src "libresoc.v:164390.5-164390.29" + assign $0\rb$next[63:0]$9277 $1\rb$next[63:0]$9278 + attribute \src "libresoc.v:166374.5-166374.29" switch \initial - attribute \src "libresoc.v:164390.9-164390.17" + attribute \src "libresoc.v:166374.9-166374.17" case 1'1 case end @@ -340904,25 +343583,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$9233 \rb$43 + assign $1\rb$next[63:0]$9278 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$9233 \rb$43 + assign $1\rb$next[63:0]$9278 \rb$43 case - assign $1\rb$next[63:0]$9233 \rb + assign $1\rb$next[63:0]$9278 \rb end sync always - update \rb$next $0\rb$next[63:0]$9232 + update \rb$next $0\rb$next[63:0]$9277 end - attribute \src "libresoc.v:164402.3-164414.6" - process $proc$libresoc.v:164402$9234 + attribute \src "libresoc.v:166386.3-166398.6" + process $proc$libresoc.v:166386$9279 assign { } { } assign { } { } - assign $0\fast1$next[63:0]$9235 $1\fast1$next[63:0]$9236 - attribute \src "libresoc.v:164403.5-164403.29" + assign $0\fast1$next[63:0]$9280 $1\fast1$next[63:0]$9281 + attribute \src "libresoc.v:166387.5-166387.29" switch \initial - attribute \src "libresoc.v:164403.9-164403.17" + attribute \src "libresoc.v:166387.9-166387.17" case 1'1 case end @@ -340931,25 +343610,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast1$next[63:0]$9236 \fast1$44 + assign $1\fast1$next[63:0]$9281 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast1$next[63:0]$9236 \fast1$44 + assign $1\fast1$next[63:0]$9281 \fast1$44 case - assign $1\fast1$next[63:0]$9236 \fast1 + assign $1\fast1$next[63:0]$9281 \fast1 end sync always - update \fast1$next $0\fast1$next[63:0]$9235 + update \fast1$next $0\fast1$next[63:0]$9280 end - attribute \src "libresoc.v:164415.3-164427.6" - process $proc$libresoc.v:164415$9237 + attribute \src "libresoc.v:166399.3-166411.6" + process $proc$libresoc.v:166399$9282 assign { } { } assign { } { } - assign $0\fast2$next[63:0]$9238 $1\fast2$next[63:0]$9239 - attribute \src "libresoc.v:164416.5-164416.29" + assign $0\fast2$next[63:0]$9283 $1\fast2$next[63:0]$9284 + attribute \src "libresoc.v:166400.5-166400.29" switch \initial - attribute \src "libresoc.v:164416.9-164416.17" + attribute \src "libresoc.v:166400.9-166400.17" case 1'1 case end @@ -340958,18 +343637,18 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast2$next[63:0]$9239 \fast2$45 + assign $1\fast2$next[63:0]$9284 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast2$next[63:0]$9239 \fast2$45 + assign $1\fast2$next[63:0]$9284 \fast2$45 case - assign $1\fast2$next[63:0]$9239 \fast2 + assign $1\fast2$next[63:0]$9284 \fast2 end sync always - update \fast2$next $0\fast2$next[63:0]$9238 + update \fast2$next $0\fast2$next[63:0]$9283 end - connect \$30 $and$libresoc.v:164255$9186_Y + connect \$30 $and$libresoc.v:166239$9231_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \fast2$45 \dummy_fast2$28 @@ -340988,279 +343667,279 @@ module \pipe1$32 connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:164449.1-165624.10" +attribute \src "libresoc.v:166433.1-167618.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" module \pipe2 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$9324 - attribute \src "libresoc.v:165365.3-165366.57" - wire width 4 $0\alu_op__data_len$18[3:0]$9310 - attribute \src "libresoc.v:164457.13-164457.41" - wire width 4 $0\alu_op__data_len$18[3:0]$9398 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 13 $0\alu_op__fn_unit$3$next[12:0]$9325 - attribute \src "libresoc.v:165335.3-165336.53" - wire width 13 $0\alu_op__fn_unit$3[12:0]$9280 - attribute \src "libresoc.v:164494.14-164494.44" - wire width 13 $0\alu_op__fn_unit$3[12:0]$9400 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9326 - attribute \src "libresoc.v:165337.3-165338.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9282 - attribute \src "libresoc.v:164517.14-164517.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9402 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$9327 - attribute \src "libresoc.v:165339.3-165340.63" - wire $0\alu_op__imm_data__ok$5[0:0]$9284 - attribute \src "libresoc.v:164526.7-164526.38" - wire $0\alu_op__imm_data__ok$5[0:0]$9404 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$9328 - attribute \src "libresoc.v:165357.3-165358.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$9302 - attribute \src "libresoc.v:164543.13-164543.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$9406 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$9329 - attribute \src "libresoc.v:165367.3-165368.49" - wire width 32 $0\alu_op__insn$19[31:0]$9312 - attribute \src "libresoc.v:164556.14-164556.39" - wire width 32 $0\alu_op__insn$19[31:0]$9408 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$9330 - attribute \src "libresoc.v:165333.3-165334.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$9278 - attribute \src "libresoc.v:164713.13-164713.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$9410 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__invert_in$10$next[0:0]$9331 - attribute \src "libresoc.v:165349.3-165350.59" - wire $0\alu_op__invert_in$10[0:0]$9294 - attribute \src "libresoc.v:164796.7-164796.36" - wire $0\alu_op__invert_in$10[0:0]$9412 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__invert_out$12$next[0:0]$9332 - attribute \src "libresoc.v:165353.3-165354.61" - wire $0\alu_op__invert_out$12[0:0]$9298 - attribute \src "libresoc.v:164805.7-164805.37" - wire $0\alu_op__invert_out$12[0:0]$9414 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__is_32bit$16$next[0:0]$9333 - attribute \src "libresoc.v:165361.3-165362.57" - wire $0\alu_op__is_32bit$16[0:0]$9306 - attribute \src "libresoc.v:164814.7-164814.35" - wire $0\alu_op__is_32bit$16[0:0]$9416 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__is_signed$17$next[0:0]$9334 - attribute \src "libresoc.v:165363.3-165364.59" - wire $0\alu_op__is_signed$17[0:0]$9308 - attribute \src "libresoc.v:164823.7-164823.36" - wire $0\alu_op__is_signed$17[0:0]$9418 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__oe__oe$8$next[0:0]$9335 - attribute \src "libresoc.v:165345.3-165346.51" - wire $0\alu_op__oe__oe$8[0:0]$9290 - attribute \src "libresoc.v:164834.7-164834.32" - wire $0\alu_op__oe__oe$8[0:0]$9420 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__oe__ok$9$next[0:0]$9336 - attribute \src "libresoc.v:165347.3-165348.51" - wire $0\alu_op__oe__ok$9[0:0]$9292 - attribute \src "libresoc.v:164843.7-164843.32" - wire $0\alu_op__oe__ok$9[0:0]$9422 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__output_carry$15$next[0:0]$9337 - attribute \src "libresoc.v:165359.3-165360.65" - wire $0\alu_op__output_carry$15[0:0]$9304 - attribute \src "libresoc.v:164850.7-164850.39" - wire $0\alu_op__output_carry$15[0:0]$9424 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__rc__ok$7$next[0:0]$9338 - attribute \src "libresoc.v:165343.3-165344.51" - wire $0\alu_op__rc__ok$7[0:0]$9288 - attribute \src "libresoc.v:164861.7-164861.32" - wire $0\alu_op__rc__ok$7[0:0]$9426 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__rc__rc$6$next[0:0]$9339 - attribute \src "libresoc.v:165341.3-165342.51" - wire $0\alu_op__rc__rc$6[0:0]$9286 - attribute \src "libresoc.v:164868.7-164868.32" - wire $0\alu_op__rc__rc$6[0:0]$9428 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__write_cr0$13$next[0:0]$9340 - attribute \src "libresoc.v:165355.3-165356.59" - wire $0\alu_op__write_cr0$13[0:0]$9300 - attribute \src "libresoc.v:164877.7-164877.36" - wire $0\alu_op__write_cr0$13[0:0]$9430 - attribute \src "libresoc.v:165468.3-165509.6" - wire $0\alu_op__zero_a$11$next[0:0]$9341 - attribute \src "libresoc.v:165351.3-165352.53" - wire $0\alu_op__zero_a$11[0:0]$9296 - attribute \src "libresoc.v:164886.7-164886.33" - wire $0\alu_op__zero_a$11[0:0]$9432 - attribute \src "libresoc.v:165529.3-165547.6" - wire width 4 $0\cr_a$22$next[3:0]$9373 - attribute \src "libresoc.v:165325.3-165326.33" - wire width 4 $0\cr_a$22[3:0]$9270 - attribute \src "libresoc.v:164899.13-164899.29" - wire width 4 $0\cr_a$22[3:0]$9434 - attribute \src "libresoc.v:165529.3-165547.6" - wire $0\cr_a_ok$23$next[0:0]$9374 - attribute \src "libresoc.v:165327.3-165328.39" - wire $0\cr_a_ok$23[0:0]$9272 - attribute \src "libresoc.v:164908.7-164908.26" - wire $0\cr_a_ok$23[0:0]$9436 - attribute \src "libresoc.v:164450.7-164450.20" + attribute \src "libresoc.v:167462.3-167503.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9369 + attribute \src "libresoc.v:167359.3-167360.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9355 + attribute \src "libresoc.v:166441.13-166441.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9443 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9370 + attribute \src "libresoc.v:167329.3-167330.53" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9325 + attribute \src "libresoc.v:166480.14-166480.44" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9445 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9371 + attribute \src "libresoc.v:167331.3-167332.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9327 + attribute \src "libresoc.v:166504.14-166504.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9447 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9372 + attribute \src "libresoc.v:167333.3-167334.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9329 + attribute \src "libresoc.v:166513.7-166513.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9449 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9373 + attribute \src "libresoc.v:167351.3-167352.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9347 + attribute \src "libresoc.v:166530.13-166530.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9451 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9374 + attribute \src "libresoc.v:167361.3-167362.49" + wire width 32 $0\alu_op__insn$19[31:0]$9357 + attribute \src "libresoc.v:166543.14-166543.39" + wire width 32 $0\alu_op__insn$19[31:0]$9453 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9375 + attribute \src "libresoc.v:167327.3-167328.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9323 + attribute \src "libresoc.v:166702.13-166702.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9455 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__invert_in$10$next[0:0]$9376 + attribute \src "libresoc.v:167343.3-167344.59" + wire $0\alu_op__invert_in$10[0:0]$9339 + attribute \src "libresoc.v:166786.7-166786.36" + wire $0\alu_op__invert_in$10[0:0]$9457 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__invert_out$12$next[0:0]$9377 + attribute \src "libresoc.v:167347.3-167348.61" + wire $0\alu_op__invert_out$12[0:0]$9343 + attribute \src "libresoc.v:166795.7-166795.37" + wire $0\alu_op__invert_out$12[0:0]$9459 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9378 + attribute \src "libresoc.v:167355.3-167356.57" + wire $0\alu_op__is_32bit$16[0:0]$9351 + attribute \src "libresoc.v:166804.7-166804.35" + wire $0\alu_op__is_32bit$16[0:0]$9461 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__is_signed$17$next[0:0]$9379 + attribute \src "libresoc.v:167357.3-167358.59" + wire $0\alu_op__is_signed$17[0:0]$9353 + attribute \src "libresoc.v:166813.7-166813.36" + wire $0\alu_op__is_signed$17[0:0]$9463 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9380 + attribute \src "libresoc.v:167339.3-167340.51" + wire $0\alu_op__oe__oe$8[0:0]$9335 + attribute \src "libresoc.v:166824.7-166824.32" + wire $0\alu_op__oe__oe$8[0:0]$9465 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9381 + attribute \src "libresoc.v:167341.3-167342.51" + wire $0\alu_op__oe__ok$9[0:0]$9337 + attribute \src "libresoc.v:166833.7-166833.32" + wire $0\alu_op__oe__ok$9[0:0]$9467 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__output_carry$15$next[0:0]$9382 + attribute \src "libresoc.v:167353.3-167354.65" + wire $0\alu_op__output_carry$15[0:0]$9349 + attribute \src "libresoc.v:166840.7-166840.39" + wire $0\alu_op__output_carry$15[0:0]$9469 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9383 + attribute \src "libresoc.v:167337.3-167338.51" + wire $0\alu_op__rc__ok$7[0:0]$9333 + attribute \src "libresoc.v:166851.7-166851.32" + wire $0\alu_op__rc__ok$7[0:0]$9471 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9384 + attribute \src "libresoc.v:167335.3-167336.51" + wire $0\alu_op__rc__rc$6[0:0]$9331 + attribute \src "libresoc.v:166858.7-166858.32" + wire $0\alu_op__rc__rc$6[0:0]$9473 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9385 + attribute \src "libresoc.v:167349.3-167350.59" + wire $0\alu_op__write_cr0$13[0:0]$9345 + attribute \src "libresoc.v:166867.7-166867.36" + wire $0\alu_op__write_cr0$13[0:0]$9475 + attribute \src "libresoc.v:167462.3-167503.6" + wire $0\alu_op__zero_a$11$next[0:0]$9386 + attribute \src "libresoc.v:167345.3-167346.53" + wire $0\alu_op__zero_a$11[0:0]$9341 + attribute \src "libresoc.v:166876.7-166876.33" + wire $0\alu_op__zero_a$11[0:0]$9477 + attribute \src "libresoc.v:167523.3-167541.6" + wire width 4 $0\cr_a$22$next[3:0]$9418 + attribute \src "libresoc.v:167319.3-167320.33" + wire width 4 $0\cr_a$22[3:0]$9315 + attribute \src "libresoc.v:166889.13-166889.29" + wire width 4 $0\cr_a$22[3:0]$9479 + attribute \src "libresoc.v:167523.3-167541.6" + wire $0\cr_a_ok$23$next[0:0]$9419 + attribute \src "libresoc.v:167321.3-167322.39" + wire $0\cr_a_ok$23[0:0]$9317 + attribute \src "libresoc.v:166898.7-166898.26" + wire $0\cr_a_ok$23[0:0]$9481 + attribute \src "libresoc.v:166434.7-166434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165455.3-165467.6" - wire width 2 $0\muxid$1$next[1:0]$9321 - attribute \src "libresoc.v:165369.3-165370.33" - wire width 2 $0\muxid$1[1:0]$9314 - attribute \src "libresoc.v:164919.13-164919.29" - wire width 2 $0\muxid$1[1:0]$9438 - attribute \src "libresoc.v:165510.3-165528.6" - wire width 64 $0\o$20$next[63:0]$9367 - attribute \src "libresoc.v:165329.3-165330.27" - wire width 64 $0\o$20[63:0]$9274 - attribute \src "libresoc.v:164934.14-164934.43" - wire width 64 $0\o$20[63:0]$9440 - attribute \src "libresoc.v:165510.3-165528.6" - wire $0\o_ok$21$next[0:0]$9368 - attribute \src "libresoc.v:165331.3-165332.33" - wire $0\o_ok$21[0:0]$9276 - attribute \src "libresoc.v:164943.7-164943.23" - wire $0\o_ok$21[0:0]$9442 - attribute \src "libresoc.v:165437.3-165454.6" - wire $0\r_busy$next[0:0]$9317 - attribute \src "libresoc.v:165371.3-165372.29" + attribute \src "libresoc.v:167449.3-167461.6" + wire width 2 $0\muxid$1$next[1:0]$9366 + attribute \src "libresoc.v:167363.3-167364.33" + wire width 2 $0\muxid$1[1:0]$9359 + attribute \src "libresoc.v:166909.13-166909.29" + wire width 2 $0\muxid$1[1:0]$9483 + attribute \src "libresoc.v:167504.3-167522.6" + wire width 64 $0\o$20$next[63:0]$9412 + attribute \src "libresoc.v:167323.3-167324.27" + wire width 64 $0\o$20[63:0]$9319 + attribute \src "libresoc.v:166924.14-166924.43" + wire width 64 $0\o$20[63:0]$9485 + attribute \src "libresoc.v:167504.3-167522.6" + wire $0\o_ok$21$next[0:0]$9413 + attribute \src "libresoc.v:167325.3-167326.33" + wire $0\o_ok$21[0:0]$9321 + attribute \src "libresoc.v:166933.7-166933.23" + wire $0\o_ok$21[0:0]$9487 + attribute \src "libresoc.v:167431.3-167448.6" + wire $0\r_busy$next[0:0]$9362 + attribute \src "libresoc.v:167365.3-167366.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:165548.3-165566.6" - wire width 2 $0\xer_ca$24$next[1:0]$9379 - attribute \src "libresoc.v:165321.3-165322.37" - wire width 2 $0\xer_ca$24[1:0]$9266 - attribute \src "libresoc.v:165256.13-165256.31" - wire width 2 $0\xer_ca$24[1:0]$9445 - attribute \src "libresoc.v:165548.3-165566.6" - wire $0\xer_ca_ok$25$next[0:0]$9380 - attribute \src "libresoc.v:165323.3-165324.43" - wire $0\xer_ca_ok$25[0:0]$9268 - attribute \src "libresoc.v:165265.7-165265.28" - wire $0\xer_ca_ok$25[0:0]$9447 - attribute \src "libresoc.v:165567.3-165585.6" - wire width 2 $0\xer_ov$26$next[1:0]$9385 - attribute \src "libresoc.v:165317.3-165318.37" - wire width 2 $0\xer_ov$26[1:0]$9262 - attribute \src "libresoc.v:165276.13-165276.31" - wire width 2 $0\xer_ov$26[1:0]$9449 - attribute \src "libresoc.v:165567.3-165585.6" - wire $0\xer_ov_ok$27$next[0:0]$9386 - attribute \src "libresoc.v:165319.3-165320.43" - wire $0\xer_ov_ok$27[0:0]$9264 - attribute \src "libresoc.v:165285.7-165285.28" - wire $0\xer_ov_ok$27[0:0]$9451 - attribute \src "libresoc.v:165586.3-165604.6" - wire $0\xer_so$28$next[0:0]$9391 - attribute \src "libresoc.v:165313.3-165314.37" - wire $0\xer_so$28[0:0]$9258 - attribute \src "libresoc.v:165296.7-165296.25" - wire $0\xer_so$28[0:0]$9453 - attribute \src "libresoc.v:165586.3-165604.6" - wire $0\xer_so_ok$29$next[0:0]$9392 - attribute \src "libresoc.v:165315.3-165316.43" - wire $0\xer_so_ok$29[0:0]$9260 - attribute \src "libresoc.v:165305.7-165305.28" - wire $0\xer_so_ok$29[0:0]$9455 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$9342 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 13 $1\alu_op__fn_unit$3$next[12:0]$9343 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9344 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$9345 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$9346 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$9347 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$9348 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__invert_in$10$next[0:0]$9349 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__invert_out$12$next[0:0]$9350 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__is_32bit$16$next[0:0]$9351 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__is_signed$17$next[0:0]$9352 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__oe__oe$8$next[0:0]$9353 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__oe__ok$9$next[0:0]$9354 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__output_carry$15$next[0:0]$9355 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__rc__ok$7$next[0:0]$9356 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__rc__rc$6$next[0:0]$9357 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__write_cr0$13$next[0:0]$9358 - attribute \src "libresoc.v:165468.3-165509.6" - wire $1\alu_op__zero_a$11$next[0:0]$9359 - attribute \src "libresoc.v:165529.3-165547.6" - wire width 4 $1\cr_a$22$next[3:0]$9375 - attribute \src "libresoc.v:165529.3-165547.6" - wire $1\cr_a_ok$23$next[0:0]$9376 - attribute \src "libresoc.v:165455.3-165467.6" - wire width 2 $1\muxid$1$next[1:0]$9322 - attribute \src "libresoc.v:165510.3-165528.6" - wire width 64 $1\o$20$next[63:0]$9369 - attribute \src "libresoc.v:165510.3-165528.6" - wire $1\o_ok$21$next[0:0]$9370 - attribute \src "libresoc.v:165437.3-165454.6" - wire $1\r_busy$next[0:0]$9318 - attribute \src "libresoc.v:165249.7-165249.20" + attribute \src "libresoc.v:167542.3-167560.6" + wire width 2 $0\xer_ca$24$next[1:0]$9424 + attribute \src "libresoc.v:167315.3-167316.37" + wire width 2 $0\xer_ca$24[1:0]$9311 + attribute \src "libresoc.v:167250.13-167250.31" + wire width 2 $0\xer_ca$24[1:0]$9490 + attribute \src "libresoc.v:167542.3-167560.6" + wire $0\xer_ca_ok$25$next[0:0]$9425 + attribute \src "libresoc.v:167317.3-167318.43" + wire $0\xer_ca_ok$25[0:0]$9313 + attribute \src "libresoc.v:167259.7-167259.28" + wire $0\xer_ca_ok$25[0:0]$9492 + attribute \src "libresoc.v:167561.3-167579.6" + wire width 2 $0\xer_ov$26$next[1:0]$9430 + attribute \src "libresoc.v:167311.3-167312.37" + wire width 2 $0\xer_ov$26[1:0]$9307 + attribute \src "libresoc.v:167270.13-167270.31" + wire width 2 $0\xer_ov$26[1:0]$9494 + attribute \src "libresoc.v:167561.3-167579.6" + wire $0\xer_ov_ok$27$next[0:0]$9431 + attribute \src "libresoc.v:167313.3-167314.43" + wire $0\xer_ov_ok$27[0:0]$9309 + attribute \src "libresoc.v:167279.7-167279.28" + wire $0\xer_ov_ok$27[0:0]$9496 + attribute \src "libresoc.v:167580.3-167598.6" + wire $0\xer_so$28$next[0:0]$9436 + attribute \src "libresoc.v:167307.3-167308.37" + wire $0\xer_so$28[0:0]$9303 + attribute \src "libresoc.v:167290.7-167290.25" + wire $0\xer_so$28[0:0]$9498 + attribute \src "libresoc.v:167580.3-167598.6" + wire $0\xer_so_ok$29$next[0:0]$9437 + attribute \src "libresoc.v:167309.3-167310.43" + wire $0\xer_so_ok$29[0:0]$9305 + attribute \src "libresoc.v:167299.7-167299.28" + wire $0\xer_so_ok$29[0:0]$9500 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9387 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9388 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9389 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9390 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9391 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9392 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9393 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__invert_in$10$next[0:0]$9394 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__invert_out$12$next[0:0]$9395 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9396 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__is_signed$17$next[0:0]$9397 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9398 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9399 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__output_carry$15$next[0:0]$9400 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9401 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9402 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9403 + attribute \src "libresoc.v:167462.3-167503.6" + wire $1\alu_op__zero_a$11$next[0:0]$9404 + attribute \src "libresoc.v:167523.3-167541.6" + wire width 4 $1\cr_a$22$next[3:0]$9420 + attribute \src "libresoc.v:167523.3-167541.6" + wire $1\cr_a_ok$23$next[0:0]$9421 + attribute \src "libresoc.v:167449.3-167461.6" + wire width 2 $1\muxid$1$next[1:0]$9367 + attribute \src "libresoc.v:167504.3-167522.6" + wire width 64 $1\o$20$next[63:0]$9414 + attribute \src "libresoc.v:167504.3-167522.6" + wire $1\o_ok$21$next[0:0]$9415 + attribute \src "libresoc.v:167431.3-167448.6" + wire $1\r_busy$next[0:0]$9363 + attribute \src "libresoc.v:167243.7-167243.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:165548.3-165566.6" - wire width 2 $1\xer_ca$24$next[1:0]$9381 - attribute \src "libresoc.v:165548.3-165566.6" - wire $1\xer_ca_ok$25$next[0:0]$9382 - attribute \src "libresoc.v:165567.3-165585.6" - wire width 2 $1\xer_ov$26$next[1:0]$9387 - attribute \src "libresoc.v:165567.3-165585.6" - wire $1\xer_ov_ok$27$next[0:0]$9388 - attribute \src "libresoc.v:165586.3-165604.6" - wire $1\xer_so$28$next[0:0]$9393 - attribute \src "libresoc.v:165586.3-165604.6" - wire $1\xer_so_ok$29$next[0:0]$9394 - attribute \src "libresoc.v:165468.3-165509.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9360 - attribute \src "libresoc.v:165468.3-165509.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$9361 - attribute \src "libresoc.v:165468.3-165509.6" - wire $2\alu_op__oe__oe$8$next[0:0]$9362 - attribute \src "libresoc.v:165468.3-165509.6" - wire $2\alu_op__oe__ok$9$next[0:0]$9363 - attribute \src "libresoc.v:165468.3-165509.6" - wire $2\alu_op__rc__ok$7$next[0:0]$9364 - attribute \src "libresoc.v:165468.3-165509.6" - wire $2\alu_op__rc__rc$6$next[0:0]$9365 - attribute \src "libresoc.v:165529.3-165547.6" - wire $2\cr_a_ok$23$next[0:0]$9377 - attribute \src "libresoc.v:165510.3-165528.6" - wire $2\o_ok$21$next[0:0]$9371 - attribute \src "libresoc.v:165437.3-165454.6" - wire $2\r_busy$next[0:0]$9319 - attribute \src "libresoc.v:165548.3-165566.6" - wire $2\xer_ca_ok$25$next[0:0]$9383 - attribute \src "libresoc.v:165567.3-165585.6" - wire $2\xer_ov_ok$27$next[0:0]$9389 - attribute \src "libresoc.v:165586.3-165604.6" - wire $2\xer_so_ok$29$next[0:0]$9395 - attribute \src "libresoc.v:165312.18-165312.118" - wire $and$libresoc.v:165312$9256_Y + attribute \src "libresoc.v:167542.3-167560.6" + wire width 2 $1\xer_ca$24$next[1:0]$9426 + attribute \src "libresoc.v:167542.3-167560.6" + wire $1\xer_ca_ok$25$next[0:0]$9427 + attribute \src "libresoc.v:167561.3-167579.6" + wire width 2 $1\xer_ov$26$next[1:0]$9432 + attribute \src "libresoc.v:167561.3-167579.6" + wire $1\xer_ov_ok$27$next[0:0]$9433 + attribute \src "libresoc.v:167580.3-167598.6" + wire $1\xer_so$28$next[0:0]$9438 + attribute \src "libresoc.v:167580.3-167598.6" + wire $1\xer_so_ok$29$next[0:0]$9439 + attribute \src "libresoc.v:167462.3-167503.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9405 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9406 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9407 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9408 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9409 + attribute \src "libresoc.v:167462.3-167503.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9410 + attribute \src "libresoc.v:167523.3-167541.6" + wire $2\cr_a_ok$23$next[0:0]$9422 + attribute \src "libresoc.v:167504.3-167522.6" + wire $2\o_ok$21$next[0:0]$9416 + attribute \src "libresoc.v:167431.3-167448.6" + wire $2\r_busy$next[0:0]$9364 + attribute \src "libresoc.v:167542.3-167560.6" + wire $2\xer_ca_ok$25$next[0:0]$9428 + attribute \src "libresoc.v:167561.3-167579.6" + wire $2\xer_ov_ok$27$next[0:0]$9434 + attribute \src "libresoc.v:167580.3-167598.6" + wire $2\xer_so_ok$29$next[0:0]$9440 + attribute \src "libresoc.v:167306.18-167306.118" + wire $and$libresoc.v:167306$9301_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -341272,55 +343951,58 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$79 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 37 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$64 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_op__fn_unit$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -341439,6 +344121,7 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -341515,6 +344198,7 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 36 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -341593,6 +344277,7 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -341683,9 +344368,9 @@ module \pipe2 wire \alu_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -341705,7 +344390,7 @@ module \pipe2 wire \cr_a_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$84 - attribute \src "libresoc.v:164450.7-164450.15" + attribute \src "libresoc.v:166434.7-166434.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -341742,37 +344427,39 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_alu_op__data_len$47 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_alu_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_alu_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_alu_op__fn_unit$32 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_alu_op__fn_unit$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -341871,6 +344558,7 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_alu_op__insn_type attribute \enum_base_type "MicrOp" @@ -341947,6 +344635,7 @@ module \pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_alu_op__insn_type$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -342096,7 +344785,7 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:165312$9256 + cell $and $and$libresoc.v:167306$9301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -342104,16 +344793,16 @@ module \pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$59 connect \B \p_ready_o - connect \Y $and$libresoc.v:165312$9256_Y + connect \Y $and$libresoc.v:167306$9301_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:165373.9-165376.4" + attribute \src "libresoc.v:167367.9-167370.4" cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:165377.12-165432.4" + attribute \src "libresoc.v:167371.12-167426.4" cell \output \output connect \alu_op__data_len \output_alu_op__data_len connect \alu_op__data_len$18 \output_alu_op__data_len$47 @@ -342171,478 +344860,478 @@ module \pipe2 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:165433.9-165436.4" + attribute \src "libresoc.v:167427.9-167430.4" cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:164450.7-164450.20" - process $proc$libresoc.v:164450$9396 + attribute \src "libresoc.v:166434.7-166434.20" + process $proc$libresoc.v:166434$9441 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164457.13-164457.41" - process $proc$libresoc.v:164457$9397 + attribute \src "libresoc.v:166441.13-166441.41" + process $proc$libresoc.v:166441$9442 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9398 4'0000 + assign $0\alu_op__data_len$18[3:0]$9443 4'0000 sync always sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9398 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9443 end - attribute \src "libresoc.v:164494.14-164494.44" - process $proc$libresoc.v:164494$9399 + attribute \src "libresoc.v:166480.14-166480.44" + process $proc$libresoc.v:166480$9444 assign { } { } - assign $0\alu_op__fn_unit$3[12:0]$9400 13'0000000000000 + assign $0\alu_op__fn_unit$3[13:0]$9445 14'00000000000000 sync always sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9400 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9445 end - attribute \src "libresoc.v:164517.14-164517.63" - process $proc$libresoc.v:164517$9401 + attribute \src "libresoc.v:166504.14-166504.63" + process $proc$libresoc.v:166504$9446 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9402 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__imm_data__data$4[63:0]$9447 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9402 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9447 end - attribute \src "libresoc.v:164526.7-164526.38" - process $proc$libresoc.v:164526$9403 + attribute \src "libresoc.v:166513.7-166513.38" + process $proc$libresoc.v:166513$9448 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9404 1'0 + assign $0\alu_op__imm_data__ok$5[0:0]$9449 1'0 sync always sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9404 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9449 end - attribute \src "libresoc.v:164543.13-164543.44" - process $proc$libresoc.v:164543$9405 + attribute \src "libresoc.v:166530.13-166530.44" + process $proc$libresoc.v:166530$9450 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9406 2'00 + assign $0\alu_op__input_carry$14[1:0]$9451 2'00 sync always sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9406 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9451 end - attribute \src "libresoc.v:164556.14-164556.39" - process $proc$libresoc.v:164556$9407 + attribute \src "libresoc.v:166543.14-166543.39" + process $proc$libresoc.v:166543$9452 assign { } { } - assign $0\alu_op__insn$19[31:0]$9408 0 + assign $0\alu_op__insn$19[31:0]$9453 0 sync always sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9408 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9453 end - attribute \src "libresoc.v:164713.13-164713.42" - process $proc$libresoc.v:164713$9409 + attribute \src "libresoc.v:166702.13-166702.42" + process $proc$libresoc.v:166702$9454 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9410 7'0000000 + assign $0\alu_op__insn_type$2[6:0]$9455 7'0000000 sync always sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9410 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9455 end - attribute \src "libresoc.v:164796.7-164796.36" - process $proc$libresoc.v:164796$9411 + attribute \src "libresoc.v:166786.7-166786.36" + process $proc$libresoc.v:166786$9456 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9412 1'0 + assign $0\alu_op__invert_in$10[0:0]$9457 1'0 sync always sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9412 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9457 end - attribute \src "libresoc.v:164805.7-164805.37" - process $proc$libresoc.v:164805$9413 + attribute \src "libresoc.v:166795.7-166795.37" + process $proc$libresoc.v:166795$9458 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9414 1'0 + assign $0\alu_op__invert_out$12[0:0]$9459 1'0 sync always sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9414 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9459 end - attribute \src "libresoc.v:164814.7-164814.35" - process $proc$libresoc.v:164814$9415 + attribute \src "libresoc.v:166804.7-166804.35" + process $proc$libresoc.v:166804$9460 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9416 1'0 + assign $0\alu_op__is_32bit$16[0:0]$9461 1'0 sync always sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9416 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9461 end - attribute \src "libresoc.v:164823.7-164823.36" - process $proc$libresoc.v:164823$9417 + attribute \src "libresoc.v:166813.7-166813.36" + process $proc$libresoc.v:166813$9462 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9418 1'0 + assign $0\alu_op__is_signed$17[0:0]$9463 1'0 sync always sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9418 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9463 end - attribute \src "libresoc.v:164834.7-164834.32" - process $proc$libresoc.v:164834$9419 + attribute \src "libresoc.v:166824.7-166824.32" + process $proc$libresoc.v:166824$9464 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9420 1'0 + assign $0\alu_op__oe__oe$8[0:0]$9465 1'0 sync always sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9420 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9465 end - attribute \src "libresoc.v:164843.7-164843.32" - process $proc$libresoc.v:164843$9421 + attribute \src "libresoc.v:166833.7-166833.32" + process $proc$libresoc.v:166833$9466 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9422 1'0 + assign $0\alu_op__oe__ok$9[0:0]$9467 1'0 sync always sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9422 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9467 end - attribute \src "libresoc.v:164850.7-164850.39" - process $proc$libresoc.v:164850$9423 + attribute \src "libresoc.v:166840.7-166840.39" + process $proc$libresoc.v:166840$9468 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9424 1'0 + assign $0\alu_op__output_carry$15[0:0]$9469 1'0 sync always sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9424 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9469 end - attribute \src "libresoc.v:164861.7-164861.32" - process $proc$libresoc.v:164861$9425 + attribute \src "libresoc.v:166851.7-166851.32" + process $proc$libresoc.v:166851$9470 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9426 1'0 + assign $0\alu_op__rc__ok$7[0:0]$9471 1'0 sync always sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9426 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9471 end - attribute \src "libresoc.v:164868.7-164868.32" - process $proc$libresoc.v:164868$9427 + attribute \src "libresoc.v:166858.7-166858.32" + process $proc$libresoc.v:166858$9472 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9428 1'0 + assign $0\alu_op__rc__rc$6[0:0]$9473 1'0 sync always sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9428 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9473 end - attribute \src "libresoc.v:164877.7-164877.36" - process $proc$libresoc.v:164877$9429 + attribute \src "libresoc.v:166867.7-166867.36" + process $proc$libresoc.v:166867$9474 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9430 1'0 + assign $0\alu_op__write_cr0$13[0:0]$9475 1'0 sync always sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9430 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9475 end - attribute \src "libresoc.v:164886.7-164886.33" - process $proc$libresoc.v:164886$9431 + attribute \src "libresoc.v:166876.7-166876.33" + process $proc$libresoc.v:166876$9476 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9432 1'0 + assign $0\alu_op__zero_a$11[0:0]$9477 1'0 sync always sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9432 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9477 end - attribute \src "libresoc.v:164899.13-164899.29" - process $proc$libresoc.v:164899$9433 + attribute \src "libresoc.v:166889.13-166889.29" + process $proc$libresoc.v:166889$9478 assign { } { } - assign $0\cr_a$22[3:0]$9434 4'0000 + assign $0\cr_a$22[3:0]$9479 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$9434 + update \cr_a$22 $0\cr_a$22[3:0]$9479 end - attribute \src "libresoc.v:164908.7-164908.26" - process $proc$libresoc.v:164908$9435 + attribute \src "libresoc.v:166898.7-166898.26" + process $proc$libresoc.v:166898$9480 assign { } { } - assign $0\cr_a_ok$23[0:0]$9436 1'0 + assign $0\cr_a_ok$23[0:0]$9481 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9436 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9481 end - attribute \src "libresoc.v:164919.13-164919.29" - process $proc$libresoc.v:164919$9437 + attribute \src "libresoc.v:166909.13-166909.29" + process $proc$libresoc.v:166909$9482 assign { } { } - assign $0\muxid$1[1:0]$9438 2'00 + assign $0\muxid$1[1:0]$9483 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9438 + update \muxid$1 $0\muxid$1[1:0]$9483 end - attribute \src "libresoc.v:164934.14-164934.43" - process $proc$libresoc.v:164934$9439 + attribute \src "libresoc.v:166924.14-166924.43" + process $proc$libresoc.v:166924$9484 assign { } { } - assign $0\o$20[63:0]$9440 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$9485 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$9440 + update \o$20 $0\o$20[63:0]$9485 end - attribute \src "libresoc.v:164943.7-164943.23" - process $proc$libresoc.v:164943$9441 + attribute \src "libresoc.v:166933.7-166933.23" + process $proc$libresoc.v:166933$9486 assign { } { } - assign $0\o_ok$21[0:0]$9442 1'0 + assign $0\o_ok$21[0:0]$9487 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$9442 + update \o_ok$21 $0\o_ok$21[0:0]$9487 end - attribute \src "libresoc.v:165249.7-165249.20" - process $proc$libresoc.v:165249$9443 + attribute \src "libresoc.v:167243.7-167243.20" + process $proc$libresoc.v:167243$9488 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:165256.13-165256.31" - process $proc$libresoc.v:165256$9444 + attribute \src "libresoc.v:167250.13-167250.31" + process $proc$libresoc.v:167250$9489 assign { } { } - assign $0\xer_ca$24[1:0]$9445 2'00 + assign $0\xer_ca$24[1:0]$9490 2'00 sync always sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$9445 + update \xer_ca$24 $0\xer_ca$24[1:0]$9490 end - attribute \src "libresoc.v:165265.7-165265.28" - process $proc$libresoc.v:165265$9446 + attribute \src "libresoc.v:167259.7-167259.28" + process $proc$libresoc.v:167259$9491 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9447 1'0 + assign $0\xer_ca_ok$25[0:0]$9492 1'0 sync always sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9447 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9492 end - attribute \src "libresoc.v:165276.13-165276.31" - process $proc$libresoc.v:165276$9448 + attribute \src "libresoc.v:167270.13-167270.31" + process $proc$libresoc.v:167270$9493 assign { } { } - assign $0\xer_ov$26[1:0]$9449 2'00 + assign $0\xer_ov$26[1:0]$9494 2'00 sync always sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$9449 + update \xer_ov$26 $0\xer_ov$26[1:0]$9494 end - attribute \src "libresoc.v:165285.7-165285.28" - process $proc$libresoc.v:165285$9450 + attribute \src "libresoc.v:167279.7-167279.28" + process $proc$libresoc.v:167279$9495 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9451 1'0 + assign $0\xer_ov_ok$27[0:0]$9496 1'0 sync always sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9451 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9496 end - attribute \src "libresoc.v:165296.7-165296.25" - process $proc$libresoc.v:165296$9452 + attribute \src "libresoc.v:167290.7-167290.25" + process $proc$libresoc.v:167290$9497 assign { } { } - assign $0\xer_so$28[0:0]$9453 1'0 + assign $0\xer_so$28[0:0]$9498 1'0 sync always sync init - update \xer_so$28 $0\xer_so$28[0:0]$9453 + update \xer_so$28 $0\xer_so$28[0:0]$9498 end - attribute \src "libresoc.v:165305.7-165305.28" - process $proc$libresoc.v:165305$9454 + attribute \src "libresoc.v:167299.7-167299.28" + process $proc$libresoc.v:167299$9499 assign { } { } - assign $0\xer_so_ok$29[0:0]$9455 1'0 + assign $0\xer_so_ok$29[0:0]$9500 1'0 sync always sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9455 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9500 end - attribute \src "libresoc.v:165313.3-165314.37" - process $proc$libresoc.v:165313$9257 + attribute \src "libresoc.v:167307.3-167308.37" + process $proc$libresoc.v:167307$9302 assign { } { } - assign $0\xer_so$28[0:0]$9258 \xer_so$28$next + assign $0\xer_so$28[0:0]$9303 \xer_so$28$next sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$9258 + update \xer_so$28 $0\xer_so$28[0:0]$9303 end - attribute \src "libresoc.v:165315.3-165316.43" - process $proc$libresoc.v:165315$9259 + attribute \src "libresoc.v:167309.3-167310.43" + process $proc$libresoc.v:167309$9304 assign { } { } - assign $0\xer_so_ok$29[0:0]$9260 \xer_so_ok$29$next + assign $0\xer_so_ok$29[0:0]$9305 \xer_so_ok$29$next sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9260 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9305 end - attribute \src "libresoc.v:165317.3-165318.37" - process $proc$libresoc.v:165317$9261 + attribute \src "libresoc.v:167311.3-167312.37" + process $proc$libresoc.v:167311$9306 assign { } { } - assign $0\xer_ov$26[1:0]$9262 \xer_ov$26$next + assign $0\xer_ov$26[1:0]$9307 \xer_ov$26$next sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$9262 + update \xer_ov$26 $0\xer_ov$26[1:0]$9307 end - attribute \src "libresoc.v:165319.3-165320.43" - process $proc$libresoc.v:165319$9263 + attribute \src "libresoc.v:167313.3-167314.43" + process $proc$libresoc.v:167313$9308 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9264 \xer_ov_ok$27$next + assign $0\xer_ov_ok$27[0:0]$9309 \xer_ov_ok$27$next sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9264 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9309 end - attribute \src "libresoc.v:165321.3-165322.37" - process $proc$libresoc.v:165321$9265 + attribute \src "libresoc.v:167315.3-167316.37" + process $proc$libresoc.v:167315$9310 assign { } { } - assign $0\xer_ca$24[1:0]$9266 \xer_ca$24$next + assign $0\xer_ca$24[1:0]$9311 \xer_ca$24$next sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$9266 + update \xer_ca$24 $0\xer_ca$24[1:0]$9311 end - attribute \src "libresoc.v:165323.3-165324.43" - process $proc$libresoc.v:165323$9267 + attribute \src "libresoc.v:167317.3-167318.43" + process $proc$libresoc.v:167317$9312 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9268 \xer_ca_ok$25$next + assign $0\xer_ca_ok$25[0:0]$9313 \xer_ca_ok$25$next sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9268 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9313 end - attribute \src "libresoc.v:165325.3-165326.33" - process $proc$libresoc.v:165325$9269 + attribute \src "libresoc.v:167319.3-167320.33" + process $proc$libresoc.v:167319$9314 assign { } { } - assign $0\cr_a$22[3:0]$9270 \cr_a$22$next + assign $0\cr_a$22[3:0]$9315 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$9270 + update \cr_a$22 $0\cr_a$22[3:0]$9315 end - attribute \src "libresoc.v:165327.3-165328.39" - process $proc$libresoc.v:165327$9271 + attribute \src "libresoc.v:167321.3-167322.39" + process $proc$libresoc.v:167321$9316 assign { } { } - assign $0\cr_a_ok$23[0:0]$9272 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$9317 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9272 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9317 end - attribute \src "libresoc.v:165329.3-165330.27" - process $proc$libresoc.v:165329$9273 + attribute \src "libresoc.v:167323.3-167324.27" + process $proc$libresoc.v:167323$9318 assign { } { } - assign $0\o$20[63:0]$9274 \o$20$next + assign $0\o$20[63:0]$9319 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$9274 + update \o$20 $0\o$20[63:0]$9319 end - attribute \src "libresoc.v:165331.3-165332.33" - process $proc$libresoc.v:165331$9275 + attribute \src "libresoc.v:167325.3-167326.33" + process $proc$libresoc.v:167325$9320 assign { } { } - assign $0\o_ok$21[0:0]$9276 \o_ok$21$next + assign $0\o_ok$21[0:0]$9321 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$9276 + update \o_ok$21 $0\o_ok$21[0:0]$9321 end - attribute \src "libresoc.v:165333.3-165334.57" - process $proc$libresoc.v:165333$9277 + attribute \src "libresoc.v:167327.3-167328.57" + process $proc$libresoc.v:167327$9322 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9278 \alu_op__insn_type$2$next + assign $0\alu_op__insn_type$2[6:0]$9323 \alu_op__insn_type$2$next sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9278 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9323 end - attribute \src "libresoc.v:165335.3-165336.53" - process $proc$libresoc.v:165335$9279 + attribute \src "libresoc.v:167329.3-167330.53" + process $proc$libresoc.v:167329$9324 assign { } { } - assign $0\alu_op__fn_unit$3[12:0]$9280 \alu_op__fn_unit$3$next + assign $0\alu_op__fn_unit$3[13:0]$9325 \alu_op__fn_unit$3$next sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9280 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9325 end - attribute \src "libresoc.v:165337.3-165338.67" - process $proc$libresoc.v:165337$9281 + attribute \src "libresoc.v:167331.3-167332.67" + process $proc$libresoc.v:167331$9326 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9282 \alu_op__imm_data__data$4$next + assign $0\alu_op__imm_data__data$4[63:0]$9327 \alu_op__imm_data__data$4$next sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9282 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9327 end - attribute \src "libresoc.v:165339.3-165340.63" - process $proc$libresoc.v:165339$9283 + attribute \src "libresoc.v:167333.3-167334.63" + process $proc$libresoc.v:167333$9328 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9284 \alu_op__imm_data__ok$5$next + assign $0\alu_op__imm_data__ok$5[0:0]$9329 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9284 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9329 end - attribute \src "libresoc.v:165341.3-165342.51" - process $proc$libresoc.v:165341$9285 + attribute \src "libresoc.v:167335.3-167336.51" + process $proc$libresoc.v:167335$9330 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9286 \alu_op__rc__rc$6$next + assign $0\alu_op__rc__rc$6[0:0]$9331 \alu_op__rc__rc$6$next sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9286 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9331 end - attribute \src "libresoc.v:165343.3-165344.51" - process $proc$libresoc.v:165343$9287 + attribute \src "libresoc.v:167337.3-167338.51" + process $proc$libresoc.v:167337$9332 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9288 \alu_op__rc__ok$7$next + assign $0\alu_op__rc__ok$7[0:0]$9333 \alu_op__rc__ok$7$next sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9288 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9333 end - attribute \src "libresoc.v:165345.3-165346.51" - process $proc$libresoc.v:165345$9289 + attribute \src "libresoc.v:167339.3-167340.51" + process $proc$libresoc.v:167339$9334 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9290 \alu_op__oe__oe$8$next + assign $0\alu_op__oe__oe$8[0:0]$9335 \alu_op__oe__oe$8$next sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9290 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9335 end - attribute \src "libresoc.v:165347.3-165348.51" - process $proc$libresoc.v:165347$9291 + attribute \src "libresoc.v:167341.3-167342.51" + process $proc$libresoc.v:167341$9336 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9292 \alu_op__oe__ok$9$next + assign $0\alu_op__oe__ok$9[0:0]$9337 \alu_op__oe__ok$9$next sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9292 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9337 end - attribute \src "libresoc.v:165349.3-165350.59" - process $proc$libresoc.v:165349$9293 + attribute \src "libresoc.v:167343.3-167344.59" + process $proc$libresoc.v:167343$9338 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9294 \alu_op__invert_in$10$next + assign $0\alu_op__invert_in$10[0:0]$9339 \alu_op__invert_in$10$next sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9294 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9339 end - attribute \src "libresoc.v:165351.3-165352.53" - process $proc$libresoc.v:165351$9295 + attribute \src "libresoc.v:167345.3-167346.53" + process $proc$libresoc.v:167345$9340 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9296 \alu_op__zero_a$11$next + assign $0\alu_op__zero_a$11[0:0]$9341 \alu_op__zero_a$11$next sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9296 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9341 end - attribute \src "libresoc.v:165353.3-165354.61" - process $proc$libresoc.v:165353$9297 + attribute \src "libresoc.v:167347.3-167348.61" + process $proc$libresoc.v:167347$9342 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9298 \alu_op__invert_out$12$next + assign $0\alu_op__invert_out$12[0:0]$9343 \alu_op__invert_out$12$next sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9298 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9343 end - attribute \src "libresoc.v:165355.3-165356.59" - process $proc$libresoc.v:165355$9299 + attribute \src "libresoc.v:167349.3-167350.59" + process $proc$libresoc.v:167349$9344 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9300 \alu_op__write_cr0$13$next + assign $0\alu_op__write_cr0$13[0:0]$9345 \alu_op__write_cr0$13$next sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9300 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9345 end - attribute \src "libresoc.v:165357.3-165358.63" - process $proc$libresoc.v:165357$9301 + attribute \src "libresoc.v:167351.3-167352.63" + process $proc$libresoc.v:167351$9346 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9302 \alu_op__input_carry$14$next + assign $0\alu_op__input_carry$14[1:0]$9347 \alu_op__input_carry$14$next sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9302 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9347 end - attribute \src "libresoc.v:165359.3-165360.65" - process $proc$libresoc.v:165359$9303 + attribute \src "libresoc.v:167353.3-167354.65" + process $proc$libresoc.v:167353$9348 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9304 \alu_op__output_carry$15$next + assign $0\alu_op__output_carry$15[0:0]$9349 \alu_op__output_carry$15$next sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9304 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9349 end - attribute \src "libresoc.v:165361.3-165362.57" - process $proc$libresoc.v:165361$9305 + attribute \src "libresoc.v:167355.3-167356.57" + process $proc$libresoc.v:167355$9350 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9306 \alu_op__is_32bit$16$next + assign $0\alu_op__is_32bit$16[0:0]$9351 \alu_op__is_32bit$16$next sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9306 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9351 end - attribute \src "libresoc.v:165363.3-165364.59" - process $proc$libresoc.v:165363$9307 + attribute \src "libresoc.v:167357.3-167358.59" + process $proc$libresoc.v:167357$9352 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9308 \alu_op__is_signed$17$next + assign $0\alu_op__is_signed$17[0:0]$9353 \alu_op__is_signed$17$next sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9308 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9353 end - attribute \src "libresoc.v:165365.3-165366.57" - process $proc$libresoc.v:165365$9309 + attribute \src "libresoc.v:167359.3-167360.57" + process $proc$libresoc.v:167359$9354 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9310 \alu_op__data_len$18$next + assign $0\alu_op__data_len$18[3:0]$9355 \alu_op__data_len$18$next sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9310 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9355 end - attribute \src "libresoc.v:165367.3-165368.49" - process $proc$libresoc.v:165367$9311 + attribute \src "libresoc.v:167361.3-167362.49" + process $proc$libresoc.v:167361$9356 assign { } { } - assign $0\alu_op__insn$19[31:0]$9312 \alu_op__insn$19$next + assign $0\alu_op__insn$19[31:0]$9357 \alu_op__insn$19$next sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9312 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9357 end - attribute \src "libresoc.v:165369.3-165370.33" - process $proc$libresoc.v:165369$9313 + attribute \src "libresoc.v:167363.3-167364.33" + process $proc$libresoc.v:167363$9358 assign { } { } - assign $0\muxid$1[1:0]$9314 \muxid$1$next + assign $0\muxid$1[1:0]$9359 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9314 + update \muxid$1 $0\muxid$1[1:0]$9359 end - attribute \src "libresoc.v:165371.3-165372.29" - process $proc$libresoc.v:165371$9315 + attribute \src "libresoc.v:167365.3-167366.29" + process $proc$libresoc.v:167365$9360 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:165437.3-165454.6" - process $proc$libresoc.v:165437$9316 + attribute \src "libresoc.v:167431.3-167448.6" + process $proc$libresoc.v:167431$9361 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9317 $2\r_busy$next[0:0]$9319 - attribute \src "libresoc.v:165438.5-165438.29" + assign $0\r_busy$next[0:0]$9362 $2\r_busy$next[0:0]$9364 + attribute \src "libresoc.v:167432.5-167432.29" switch \initial - attribute \src "libresoc.v:165438.9-165438.17" + attribute \src "libresoc.v:167432.9-167432.17" case 1'1 case end @@ -342651,34 +345340,34 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9318 1'1 + assign $1\r_busy$next[0:0]$9363 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9318 1'0 + assign $1\r_busy$next[0:0]$9363 1'0 case - assign $1\r_busy$next[0:0]$9318 \r_busy + assign $1\r_busy$next[0:0]$9363 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9319 1'0 + assign $2\r_busy$next[0:0]$9364 1'0 case - assign $2\r_busy$next[0:0]$9319 $1\r_busy$next[0:0]$9318 + assign $2\r_busy$next[0:0]$9364 $1\r_busy$next[0:0]$9363 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9317 + update \r_busy$next $0\r_busy$next[0:0]$9362 end - attribute \src "libresoc.v:165455.3-165467.6" - process $proc$libresoc.v:165455$9320 + attribute \src "libresoc.v:167449.3-167461.6" + process $proc$libresoc.v:167449$9365 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9321 $1\muxid$1$next[1:0]$9322 - attribute \src "libresoc.v:165456.5-165456.29" + assign $0\muxid$1$next[1:0]$9366 $1\muxid$1$next[1:0]$9367 + attribute \src "libresoc.v:167450.5-167450.29" switch \initial - attribute \src "libresoc.v:165456.9-165456.17" + attribute \src "libresoc.v:167450.9-167450.17" case 1'1 case end @@ -342687,19 +345376,19 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9322 \muxid$62 + assign $1\muxid$1$next[1:0]$9367 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9322 \muxid$62 + assign $1\muxid$1$next[1:0]$9367 \muxid$62 case - assign $1\muxid$1$next[1:0]$9322 \muxid$1 + assign $1\muxid$1$next[1:0]$9367 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9321 + update \muxid$1$next $0\muxid$1$next[1:0]$9366 end - attribute \src "libresoc.v:165468.3-165509.6" - process $proc$libresoc.v:165468$9323 + attribute \src "libresoc.v:167462.3-167503.6" + process $proc$libresoc.v:167462$9368 assign { } { } assign { } { } assign { } { } @@ -342736,33 +345425,33 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$9324 $1\alu_op__data_len$18$next[3:0]$9342 - assign $0\alu_op__fn_unit$3$next[12:0]$9325 $1\alu_op__fn_unit$3$next[12:0]$9343 + assign $0\alu_op__data_len$18$next[3:0]$9369 $1\alu_op__data_len$18$next[3:0]$9387 + assign $0\alu_op__fn_unit$3$next[13:0]$9370 $1\alu_op__fn_unit$3$next[13:0]$9388 assign { } { } assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$9328 $1\alu_op__input_carry$14$next[1:0]$9346 - assign $0\alu_op__insn$19$next[31:0]$9329 $1\alu_op__insn$19$next[31:0]$9347 - assign $0\alu_op__insn_type$2$next[6:0]$9330 $1\alu_op__insn_type$2$next[6:0]$9348 - assign $0\alu_op__invert_in$10$next[0:0]$9331 $1\alu_op__invert_in$10$next[0:0]$9349 - assign $0\alu_op__invert_out$12$next[0:0]$9332 $1\alu_op__invert_out$12$next[0:0]$9350 - assign $0\alu_op__is_32bit$16$next[0:0]$9333 $1\alu_op__is_32bit$16$next[0:0]$9351 - assign $0\alu_op__is_signed$17$next[0:0]$9334 $1\alu_op__is_signed$17$next[0:0]$9352 + assign $0\alu_op__input_carry$14$next[1:0]$9373 $1\alu_op__input_carry$14$next[1:0]$9391 + assign $0\alu_op__insn$19$next[31:0]$9374 $1\alu_op__insn$19$next[31:0]$9392 + assign $0\alu_op__insn_type$2$next[6:0]$9375 $1\alu_op__insn_type$2$next[6:0]$9393 + assign $0\alu_op__invert_in$10$next[0:0]$9376 $1\alu_op__invert_in$10$next[0:0]$9394 + assign $0\alu_op__invert_out$12$next[0:0]$9377 $1\alu_op__invert_out$12$next[0:0]$9395 + assign $0\alu_op__is_32bit$16$next[0:0]$9378 $1\alu_op__is_32bit$16$next[0:0]$9396 + assign $0\alu_op__is_signed$17$next[0:0]$9379 $1\alu_op__is_signed$17$next[0:0]$9397 assign { } { } assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$9337 $1\alu_op__output_carry$15$next[0:0]$9355 + assign $0\alu_op__output_carry$15$next[0:0]$9382 $1\alu_op__output_carry$15$next[0:0]$9400 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$9340 $1\alu_op__write_cr0$13$next[0:0]$9358 - assign $0\alu_op__zero_a$11$next[0:0]$9341 $1\alu_op__zero_a$11$next[0:0]$9359 - assign $0\alu_op__imm_data__data$4$next[63:0]$9326 $2\alu_op__imm_data__data$4$next[63:0]$9360 - assign $0\alu_op__imm_data__ok$5$next[0:0]$9327 $2\alu_op__imm_data__ok$5$next[0:0]$9361 - assign $0\alu_op__oe__oe$8$next[0:0]$9335 $2\alu_op__oe__oe$8$next[0:0]$9362 - assign $0\alu_op__oe__ok$9$next[0:0]$9336 $2\alu_op__oe__ok$9$next[0:0]$9363 - assign $0\alu_op__rc__ok$7$next[0:0]$9338 $2\alu_op__rc__ok$7$next[0:0]$9364 - assign $0\alu_op__rc__rc$6$next[0:0]$9339 $2\alu_op__rc__rc$6$next[0:0]$9365 - attribute \src "libresoc.v:165469.5-165469.29" + assign $0\alu_op__write_cr0$13$next[0:0]$9385 $1\alu_op__write_cr0$13$next[0:0]$9403 + assign $0\alu_op__zero_a$11$next[0:0]$9386 $1\alu_op__zero_a$11$next[0:0]$9404 + assign $0\alu_op__imm_data__data$4$next[63:0]$9371 $2\alu_op__imm_data__data$4$next[63:0]$9405 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9372 $2\alu_op__imm_data__ok$5$next[0:0]$9406 + assign $0\alu_op__oe__oe$8$next[0:0]$9380 $2\alu_op__oe__oe$8$next[0:0]$9407 + assign $0\alu_op__oe__ok$9$next[0:0]$9381 $2\alu_op__oe__ok$9$next[0:0]$9408 + assign $0\alu_op__rc__ok$7$next[0:0]$9383 $2\alu_op__rc__ok$7$next[0:0]$9409 + assign $0\alu_op__rc__rc$6$next[0:0]$9384 $2\alu_op__rc__rc$6$next[0:0]$9410 + attribute \src "libresoc.v:167463.5-167463.29" switch \initial - attribute \src "libresoc.v:165469.9-165469.17" + attribute \src "libresoc.v:167463.9-167463.17" case 1'1 case end @@ -342788,7 +345477,7 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9347 $1\alu_op__data_len$18$next[3:0]$9342 $1\alu_op__is_signed$17$next[0:0]$9352 $1\alu_op__is_32bit$16$next[0:0]$9351 $1\alu_op__output_carry$15$next[0:0]$9355 $1\alu_op__input_carry$14$next[1:0]$9346 $1\alu_op__write_cr0$13$next[0:0]$9358 $1\alu_op__invert_out$12$next[0:0]$9350 $1\alu_op__zero_a$11$next[0:0]$9359 $1\alu_op__invert_in$10$next[0:0]$9349 $1\alu_op__oe__ok$9$next[0:0]$9354 $1\alu_op__oe__oe$8$next[0:0]$9353 $1\alu_op__rc__ok$7$next[0:0]$9356 $1\alu_op__rc__rc$6$next[0:0]$9357 $1\alu_op__imm_data__ok$5$next[0:0]$9345 $1\alu_op__imm_data__data$4$next[63:0]$9344 $1\alu_op__fn_unit$3$next[12:0]$9343 $1\alu_op__insn_type$2$next[6:0]$9348 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9392 $1\alu_op__data_len$18$next[3:0]$9387 $1\alu_op__is_signed$17$next[0:0]$9397 $1\alu_op__is_32bit$16$next[0:0]$9396 $1\alu_op__output_carry$15$next[0:0]$9400 $1\alu_op__input_carry$14$next[1:0]$9391 $1\alu_op__write_cr0$13$next[0:0]$9403 $1\alu_op__invert_out$12$next[0:0]$9395 $1\alu_op__zero_a$11$next[0:0]$9404 $1\alu_op__invert_in$10$next[0:0]$9394 $1\alu_op__oe__ok$9$next[0:0]$9399 $1\alu_op__oe__oe$8$next[0:0]$9398 $1\alu_op__rc__ok$7$next[0:0]$9401 $1\alu_op__rc__rc$6$next[0:0]$9402 $1\alu_op__imm_data__ok$5$next[0:0]$9390 $1\alu_op__imm_data__data$4$next[63:0]$9389 $1\alu_op__fn_unit$3$next[13:0]$9388 $1\alu_op__insn_type$2$next[6:0]$9393 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -342809,26 +345498,26 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9347 $1\alu_op__data_len$18$next[3:0]$9342 $1\alu_op__is_signed$17$next[0:0]$9352 $1\alu_op__is_32bit$16$next[0:0]$9351 $1\alu_op__output_carry$15$next[0:0]$9355 $1\alu_op__input_carry$14$next[1:0]$9346 $1\alu_op__write_cr0$13$next[0:0]$9358 $1\alu_op__invert_out$12$next[0:0]$9350 $1\alu_op__zero_a$11$next[0:0]$9359 $1\alu_op__invert_in$10$next[0:0]$9349 $1\alu_op__oe__ok$9$next[0:0]$9354 $1\alu_op__oe__oe$8$next[0:0]$9353 $1\alu_op__rc__ok$7$next[0:0]$9356 $1\alu_op__rc__rc$6$next[0:0]$9357 $1\alu_op__imm_data__ok$5$next[0:0]$9345 $1\alu_op__imm_data__data$4$next[63:0]$9344 $1\alu_op__fn_unit$3$next[12:0]$9343 $1\alu_op__insn_type$2$next[6:0]$9348 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9392 $1\alu_op__data_len$18$next[3:0]$9387 $1\alu_op__is_signed$17$next[0:0]$9397 $1\alu_op__is_32bit$16$next[0:0]$9396 $1\alu_op__output_carry$15$next[0:0]$9400 $1\alu_op__input_carry$14$next[1:0]$9391 $1\alu_op__write_cr0$13$next[0:0]$9403 $1\alu_op__invert_out$12$next[0:0]$9395 $1\alu_op__zero_a$11$next[0:0]$9404 $1\alu_op__invert_in$10$next[0:0]$9394 $1\alu_op__oe__ok$9$next[0:0]$9399 $1\alu_op__oe__oe$8$next[0:0]$9398 $1\alu_op__rc__ok$7$next[0:0]$9401 $1\alu_op__rc__rc$6$next[0:0]$9402 $1\alu_op__imm_data__ok$5$next[0:0]$9390 $1\alu_op__imm_data__data$4$next[63:0]$9389 $1\alu_op__fn_unit$3$next[13:0]$9388 $1\alu_op__insn_type$2$next[6:0]$9393 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } case - assign $1\alu_op__data_len$18$next[3:0]$9342 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[12:0]$9343 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$9344 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$9345 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$9346 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$9347 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$9348 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$9349 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$9350 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$9351 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$9352 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$9353 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$9354 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$9355 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$9356 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$9357 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$9358 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$9359 \alu_op__zero_a$11 + assign $1\alu_op__data_len$18$next[3:0]$9387 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[13:0]$9388 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9389 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9390 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9391 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9392 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9393 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9394 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9395 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9396 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9397 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9398 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9399 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9400 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9401 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9402 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9403 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9404 \alu_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -342840,52 +345529,52 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$9360 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9361 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$9365 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$9364 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$9362 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$9363 1'0 + assign $2\alu_op__imm_data__data$4$next[63:0]$9405 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9406 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9410 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9409 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9407 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9408 1'0 case - assign $2\alu_op__imm_data__data$4$next[63:0]$9360 $1\alu_op__imm_data__data$4$next[63:0]$9344 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9361 $1\alu_op__imm_data__ok$5$next[0:0]$9345 - assign $2\alu_op__oe__oe$8$next[0:0]$9362 $1\alu_op__oe__oe$8$next[0:0]$9353 - assign $2\alu_op__oe__ok$9$next[0:0]$9363 $1\alu_op__oe__ok$9$next[0:0]$9354 - assign $2\alu_op__rc__ok$7$next[0:0]$9364 $1\alu_op__rc__ok$7$next[0:0]$9356 - assign $2\alu_op__rc__rc$6$next[0:0]$9365 $1\alu_op__rc__rc$6$next[0:0]$9357 + assign $2\alu_op__imm_data__data$4$next[63:0]$9405 $1\alu_op__imm_data__data$4$next[63:0]$9389 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9406 $1\alu_op__imm_data__ok$5$next[0:0]$9390 + assign $2\alu_op__oe__oe$8$next[0:0]$9407 $1\alu_op__oe__oe$8$next[0:0]$9398 + assign $2\alu_op__oe__ok$9$next[0:0]$9408 $1\alu_op__oe__ok$9$next[0:0]$9399 + assign $2\alu_op__rc__ok$7$next[0:0]$9409 $1\alu_op__rc__ok$7$next[0:0]$9401 + assign $2\alu_op__rc__rc$6$next[0:0]$9410 $1\alu_op__rc__rc$6$next[0:0]$9402 end sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9324 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[12:0]$9325 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9326 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9327 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9328 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9329 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9330 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9331 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9332 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9333 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9334 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9335 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9336 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9337 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9338 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9339 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9340 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9341 + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9369 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9370 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9371 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9372 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9373 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9374 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9375 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9376 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9377 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9378 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9379 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9380 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9381 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9382 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9383 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9384 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9385 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9386 end - attribute \src "libresoc.v:165510.3-165528.6" - process $proc$libresoc.v:165510$9366 + attribute \src "libresoc.v:167504.3-167522.6" + process $proc$libresoc.v:167504$9411 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$9367 $1\o$20$next[63:0]$9369 + assign $0\o$20$next[63:0]$9412 $1\o$20$next[63:0]$9414 assign { } { } - assign $0\o_ok$21$next[0:0]$9368 $2\o_ok$21$next[0:0]$9371 - attribute \src "libresoc.v:165511.5-165511.29" + assign $0\o_ok$21$next[0:0]$9413 $2\o_ok$21$next[0:0]$9416 + attribute \src "libresoc.v:167505.5-167505.29" switch \initial - attribute \src "libresoc.v:165511.9-165511.17" + attribute \src "libresoc.v:167505.9-167505.17" case 1'1 case end @@ -342895,41 +345584,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9370 $1\o$20$next[63:0]$9369 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9415 $1\o$20$next[63:0]$9414 } { \o_ok$82 \o$81 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9370 $1\o$20$next[63:0]$9369 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9415 $1\o$20$next[63:0]$9414 } { \o_ok$82 \o$81 } case - assign $1\o$20$next[63:0]$9369 \o$20 - assign $1\o_ok$21$next[0:0]$9370 \o_ok$21 + assign $1\o$20$next[63:0]$9414 \o$20 + assign $1\o_ok$21$next[0:0]$9415 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$9371 1'0 + assign $2\o_ok$21$next[0:0]$9416 1'0 case - assign $2\o_ok$21$next[0:0]$9371 $1\o_ok$21$next[0:0]$9370 + assign $2\o_ok$21$next[0:0]$9416 $1\o_ok$21$next[0:0]$9415 end sync always - update \o$20$next $0\o$20$next[63:0]$9367 - update \o_ok$21$next $0\o_ok$21$next[0:0]$9368 + update \o$20$next $0\o$20$next[63:0]$9412 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9413 end - attribute \src "libresoc.v:165529.3-165547.6" - process $proc$libresoc.v:165529$9372 + attribute \src "libresoc.v:167523.3-167541.6" + process $proc$libresoc.v:167523$9417 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$9373 $1\cr_a$22$next[3:0]$9375 + assign $0\cr_a$22$next[3:0]$9418 $1\cr_a$22$next[3:0]$9420 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$9374 $2\cr_a_ok$23$next[0:0]$9377 - attribute \src "libresoc.v:165530.5-165530.29" + assign $0\cr_a_ok$23$next[0:0]$9419 $2\cr_a_ok$23$next[0:0]$9422 + attribute \src "libresoc.v:167524.5-167524.29" switch \initial - attribute \src "libresoc.v:165530.9-165530.17" + attribute \src "libresoc.v:167524.9-167524.17" case 1'1 case end @@ -342939,41 +345628,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9376 $1\cr_a$22$next[3:0]$9375 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9421 $1\cr_a$22$next[3:0]$9420 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9376 $1\cr_a$22$next[3:0]$9375 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9421 $1\cr_a$22$next[3:0]$9420 } { \cr_a_ok$84 \cr_a$83 } case - assign $1\cr_a$22$next[3:0]$9375 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$9376 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$9420 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9421 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$9377 1'0 + assign $2\cr_a_ok$23$next[0:0]$9422 1'0 case - assign $2\cr_a_ok$23$next[0:0]$9377 $1\cr_a_ok$23$next[0:0]$9376 + assign $2\cr_a_ok$23$next[0:0]$9422 $1\cr_a_ok$23$next[0:0]$9421 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$9373 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9374 + update \cr_a$22$next $0\cr_a$22$next[3:0]$9418 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9419 end - attribute \src "libresoc.v:165548.3-165566.6" - process $proc$libresoc.v:165548$9378 + attribute \src "libresoc.v:167542.3-167560.6" + process $proc$libresoc.v:167542$9423 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$24$next[1:0]$9379 $1\xer_ca$24$next[1:0]$9381 + assign $0\xer_ca$24$next[1:0]$9424 $1\xer_ca$24$next[1:0]$9426 assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$9380 $2\xer_ca_ok$25$next[0:0]$9383 - attribute \src "libresoc.v:165549.5-165549.29" + assign $0\xer_ca_ok$25$next[0:0]$9425 $2\xer_ca_ok$25$next[0:0]$9428 + attribute \src "libresoc.v:167543.5-167543.29" switch \initial - attribute \src "libresoc.v:165549.9-165549.17" + attribute \src "libresoc.v:167543.9-167543.17" case 1'1 case end @@ -342983,41 +345672,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9382 $1\xer_ca$24$next[1:0]$9381 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9427 $1\xer_ca$24$next[1:0]$9426 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9382 $1\xer_ca$24$next[1:0]$9381 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9427 $1\xer_ca$24$next[1:0]$9426 } { \xer_ca_ok$86 \xer_ca$85 } case - assign $1\xer_ca$24$next[1:0]$9381 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$9382 \xer_ca_ok$25 + assign $1\xer_ca$24$next[1:0]$9426 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9427 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$9383 1'0 + assign $2\xer_ca_ok$25$next[0:0]$9428 1'0 case - assign $2\xer_ca_ok$25$next[0:0]$9383 $1\xer_ca_ok$25$next[0:0]$9382 + assign $2\xer_ca_ok$25$next[0:0]$9428 $1\xer_ca_ok$25$next[0:0]$9427 end sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9379 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9380 + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9424 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9425 end - attribute \src "libresoc.v:165567.3-165585.6" - process $proc$libresoc.v:165567$9384 + attribute \src "libresoc.v:167561.3-167579.6" + process $proc$libresoc.v:167561$9429 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$26$next[1:0]$9385 $1\xer_ov$26$next[1:0]$9387 + assign $0\xer_ov$26$next[1:0]$9430 $1\xer_ov$26$next[1:0]$9432 assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$9386 $2\xer_ov_ok$27$next[0:0]$9389 - attribute \src "libresoc.v:165568.5-165568.29" + assign $0\xer_ov_ok$27$next[0:0]$9431 $2\xer_ov_ok$27$next[0:0]$9434 + attribute \src "libresoc.v:167562.5-167562.29" switch \initial - attribute \src "libresoc.v:165568.9-165568.17" + attribute \src "libresoc.v:167562.9-167562.17" case 1'1 case end @@ -343027,41 +345716,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9388 $1\xer_ov$26$next[1:0]$9387 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9433 $1\xer_ov$26$next[1:0]$9432 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9388 $1\xer_ov$26$next[1:0]$9387 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9433 $1\xer_ov$26$next[1:0]$9432 } { \xer_ov_ok$88 \xer_ov$87 } case - assign $1\xer_ov$26$next[1:0]$9387 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$9388 \xer_ov_ok$27 + assign $1\xer_ov$26$next[1:0]$9432 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9433 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$9389 1'0 + assign $2\xer_ov_ok$27$next[0:0]$9434 1'0 case - assign $2\xer_ov_ok$27$next[0:0]$9389 $1\xer_ov_ok$27$next[0:0]$9388 + assign $2\xer_ov_ok$27$next[0:0]$9434 $1\xer_ov_ok$27$next[0:0]$9433 end sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9385 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9386 + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9430 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9431 end - attribute \src "libresoc.v:165586.3-165604.6" - process $proc$libresoc.v:165586$9390 + attribute \src "libresoc.v:167580.3-167598.6" + process $proc$libresoc.v:167580$9435 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$28$next[0:0]$9391 $1\xer_so$28$next[0:0]$9393 + assign $0\xer_so$28$next[0:0]$9436 $1\xer_so$28$next[0:0]$9438 assign { } { } - assign $0\xer_so_ok$29$next[0:0]$9392 $2\xer_so_ok$29$next[0:0]$9395 - attribute \src "libresoc.v:165587.5-165587.29" + assign $0\xer_so_ok$29$next[0:0]$9437 $2\xer_so_ok$29$next[0:0]$9440 + attribute \src "libresoc.v:167581.5-167581.29" switch \initial - attribute \src "libresoc.v:165587.9-165587.17" + attribute \src "libresoc.v:167581.9-167581.17" case 1'1 case end @@ -343071,30 +345760,30 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9394 $1\xer_so$28$next[0:0]$9393 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9439 $1\xer_so$28$next[0:0]$9438 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9394 $1\xer_so$28$next[0:0]$9393 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9439 $1\xer_so$28$next[0:0]$9438 } { \xer_so_ok$90 \xer_so$89 } case - assign $1\xer_so$28$next[0:0]$9393 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$9394 \xer_so_ok$29 + assign $1\xer_so$28$next[0:0]$9438 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9439 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$29$next[0:0]$9395 1'0 + assign $2\xer_so_ok$29$next[0:0]$9440 1'0 case - assign $2\xer_so_ok$29$next[0:0]$9395 $1\xer_so_ok$29$next[0:0]$9394 + assign $2\xer_so_ok$29$next[0:0]$9440 $1\xer_so_ok$29$next[0:0]$9439 end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$9391 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9392 + update \xer_so$28$next $0\xer_so$28$next[0:0]$9436 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9437 end - connect \$60 $and$libresoc.v:165312$9256_Y + connect \$60 $and$libresoc.v:167306$9301_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } @@ -343115,240 +345804,240 @@ module \pipe2 connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:165628.1-166687.10" +attribute \src "libresoc.v:167622.1-168691.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" module \pipe2$115 - attribute \src "libresoc.v:166633.3-166651.6" - wire width 4 $0\cr_a$21$next[3:0]$9561 - attribute \src "libresoc.v:166439.3-166440.33" - wire width 4 $0\cr_a$21[3:0]$9462 - attribute \src "libresoc.v:165640.13-165640.29" - wire width 4 $0\cr_a$21[3:0]$9574 - attribute \src "libresoc.v:166633.3-166651.6" - wire $0\cr_a_ok$22$next[0:0]$9562 - attribute \src "libresoc.v:166441.3-166442.39" - wire $0\cr_a_ok$22[0:0]$9464 - attribute \src "libresoc.v:165649.7-165649.26" - wire $0\cr_a_ok$22[0:0]$9576 - attribute \src "libresoc.v:165629.7-165629.20" + attribute \src "libresoc.v:168637.3-168655.6" + wire width 4 $0\cr_a$21$next[3:0]$9606 + attribute \src "libresoc.v:168443.3-168444.33" + wire width 4 $0\cr_a$21[3:0]$9507 + attribute \src "libresoc.v:167634.13-167634.29" + wire width 4 $0\cr_a$21[3:0]$9619 + attribute \src "libresoc.v:168637.3-168655.6" + wire $0\cr_a_ok$22$next[0:0]$9607 + attribute \src "libresoc.v:168445.3-168446.39" + wire $0\cr_a_ok$22[0:0]$9509 + attribute \src "libresoc.v:167643.7-167643.26" + wire $0\cr_a_ok$22[0:0]$9621 + attribute \src "libresoc.v:167623.7-167623.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166560.3-166572.6" - wire width 2 $0\muxid$1$next[1:0]$9511 - attribute \src "libresoc.v:166481.3-166482.33" - wire width 2 $0\muxid$1[1:0]$9504 - attribute \src "libresoc.v:165660.13-165660.29" - wire width 2 $0\muxid$1[1:0]$9578 - attribute \src "libresoc.v:166614.3-166632.6" - wire width 64 $0\o$19$next[63:0]$9555 - attribute \src "libresoc.v:166443.3-166444.27" - wire width 64 $0\o$19[63:0]$9466 - attribute \src "libresoc.v:165675.14-165675.43" - wire width 64 $0\o$19[63:0]$9580 - attribute \src "libresoc.v:166614.3-166632.6" - wire $0\o_ok$20$next[0:0]$9556 - attribute \src "libresoc.v:166445.3-166446.33" - wire $0\o_ok$20[0:0]$9468 - attribute \src "libresoc.v:165684.7-165684.23" - wire $0\o_ok$20[0:0]$9582 - attribute \src "libresoc.v:166542.3-166559.6" - wire $0\r_busy$next[0:0]$9507 - attribute \src "libresoc.v:166483.3-166484.29" + attribute \src "libresoc.v:168564.3-168576.6" + wire width 2 $0\muxid$1$next[1:0]$9556 + attribute \src "libresoc.v:168485.3-168486.33" + wire width 2 $0\muxid$1[1:0]$9549 + attribute \src "libresoc.v:167654.13-167654.29" + wire width 2 $0\muxid$1[1:0]$9623 + attribute \src "libresoc.v:168618.3-168636.6" + wire width 64 $0\o$19$next[63:0]$9600 + attribute \src "libresoc.v:168447.3-168448.27" + wire width 64 $0\o$19[63:0]$9511 + attribute \src "libresoc.v:167669.14-167669.43" + wire width 64 $0\o$19[63:0]$9625 + attribute \src "libresoc.v:168618.3-168636.6" + wire $0\o_ok$20$next[0:0]$9601 + attribute \src "libresoc.v:168449.3-168450.33" + wire $0\o_ok$20[0:0]$9513 + attribute \src "libresoc.v:167678.7-167678.23" + wire $0\o_ok$20[0:0]$9627 + attribute \src "libresoc.v:168546.3-168563.6" + wire $0\r_busy$next[0:0]$9552 + attribute \src "libresoc.v:168487.3-168488.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:166573.3-166613.6" - wire width 13 $0\sr_op__fn_unit$3$next[12:0]$9514 - attribute \src "libresoc.v:166449.3-166450.51" - wire width 13 $0\sr_op__fn_unit$3[12:0]$9472 - attribute \src "libresoc.v:166011.14-166011.43" - wire width 13 $0\sr_op__fn_unit$3[12:0]$9585 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9515 - attribute \src "libresoc.v:166451.3-166452.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9474 - attribute \src "libresoc.v:166034.14-166034.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9587 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9516 - attribute \src "libresoc.v:166453.3-166454.61" - wire $0\sr_op__imm_data__ok$5[0:0]$9476 - attribute \src "libresoc.v:166043.7-166043.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9589 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 2 $0\sr_op__input_carry$12$next[1:0]$9517 - attribute \src "libresoc.v:166467.3-166468.61" - wire width 2 $0\sr_op__input_carry$12[1:0]$9490 - attribute \src "libresoc.v:166060.13-166060.43" - wire width 2 $0\sr_op__input_carry$12[1:0]$9591 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__input_cr$14$next[0:0]$9518 - attribute \src "libresoc.v:166471.3-166472.55" - wire $0\sr_op__input_cr$14[0:0]$9494 - attribute \src "libresoc.v:166073.7-166073.34" - wire $0\sr_op__input_cr$14[0:0]$9593 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 32 $0\sr_op__insn$18$next[31:0]$9519 - attribute \src "libresoc.v:166479.3-166480.47" - wire width 32 $0\sr_op__insn$18[31:0]$9502 - attribute \src "libresoc.v:166082.14-166082.38" - wire width 32 $0\sr_op__insn$18[31:0]$9595 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$9520 - attribute \src "libresoc.v:166447.3-166448.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$9470 - attribute \src "libresoc.v:166239.13-166239.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$9597 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__invert_in$11$next[0:0]$9521 - attribute \src "libresoc.v:166465.3-166466.57" - wire $0\sr_op__invert_in$11[0:0]$9488 - attribute \src "libresoc.v:166322.7-166322.35" - wire $0\sr_op__invert_in$11[0:0]$9599 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__is_32bit$16$next[0:0]$9522 - attribute \src "libresoc.v:166475.3-166476.55" - wire $0\sr_op__is_32bit$16[0:0]$9498 - attribute \src "libresoc.v:166331.7-166331.34" - wire $0\sr_op__is_32bit$16[0:0]$9601 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__is_signed$17$next[0:0]$9523 - attribute \src "libresoc.v:166477.3-166478.57" - wire $0\sr_op__is_signed$17[0:0]$9500 - attribute \src "libresoc.v:166340.7-166340.35" - wire $0\sr_op__is_signed$17[0:0]$9603 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__oe__oe$8$next[0:0]$9524 - attribute \src "libresoc.v:166459.3-166460.49" - wire $0\sr_op__oe__oe$8[0:0]$9482 - attribute \src "libresoc.v:166351.7-166351.31" - wire $0\sr_op__oe__oe$8[0:0]$9605 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__oe__ok$9$next[0:0]$9525 - attribute \src "libresoc.v:166461.3-166462.49" - wire $0\sr_op__oe__ok$9[0:0]$9484 - attribute \src "libresoc.v:166360.7-166360.31" - wire $0\sr_op__oe__ok$9[0:0]$9607 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__output_carry$13$next[0:0]$9526 - attribute \src "libresoc.v:166469.3-166470.63" - wire $0\sr_op__output_carry$13[0:0]$9492 - attribute \src "libresoc.v:166367.7-166367.38" - wire $0\sr_op__output_carry$13[0:0]$9609 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__output_cr$15$next[0:0]$9527 - attribute \src "libresoc.v:166473.3-166474.57" - wire $0\sr_op__output_cr$15[0:0]$9496 - attribute \src "libresoc.v:166376.7-166376.35" - wire $0\sr_op__output_cr$15[0:0]$9611 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__rc__ok$7$next[0:0]$9528 - attribute \src "libresoc.v:166457.3-166458.49" - wire $0\sr_op__rc__ok$7[0:0]$9480 - attribute \src "libresoc.v:166387.7-166387.31" - wire $0\sr_op__rc__ok$7[0:0]$9613 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__rc__rc$6$next[0:0]$9529 - attribute \src "libresoc.v:166455.3-166456.49" - wire $0\sr_op__rc__rc$6[0:0]$9478 - attribute \src "libresoc.v:166396.7-166396.31" - wire $0\sr_op__rc__rc$6[0:0]$9615 - attribute \src "libresoc.v:166573.3-166613.6" - wire $0\sr_op__write_cr0$10$next[0:0]$9530 - attribute \src "libresoc.v:166463.3-166464.57" - wire $0\sr_op__write_cr0$10[0:0]$9486 - attribute \src "libresoc.v:166403.7-166403.35" - wire $0\sr_op__write_cr0$10[0:0]$9617 - attribute \src "libresoc.v:166652.3-166670.6" - wire width 2 $0\xer_ca$23$next[1:0]$9567 - attribute \src "libresoc.v:166435.3-166436.37" - wire width 2 $0\xer_ca$23[1:0]$9458 - attribute \src "libresoc.v:166412.13-166412.31" - wire width 2 $0\xer_ca$23[1:0]$9619 - attribute \src "libresoc.v:166652.3-166670.6" - wire $0\xer_ca_ok$24$next[0:0]$9568 - attribute \src "libresoc.v:166437.3-166438.43" - wire $0\xer_ca_ok$24[0:0]$9460 - attribute \src "libresoc.v:166421.7-166421.28" - wire $0\xer_ca_ok$24[0:0]$9621 - attribute \src "libresoc.v:166633.3-166651.6" - wire width 4 $1\cr_a$21$next[3:0]$9563 - attribute \src "libresoc.v:166633.3-166651.6" - wire $1\cr_a_ok$22$next[0:0]$9564 - attribute \src "libresoc.v:166560.3-166572.6" - wire width 2 $1\muxid$1$next[1:0]$9512 - attribute \src "libresoc.v:166614.3-166632.6" - wire width 64 $1\o$19$next[63:0]$9557 - attribute \src "libresoc.v:166614.3-166632.6" - wire $1\o_ok$20$next[0:0]$9558 - attribute \src "libresoc.v:166542.3-166559.6" - wire $1\r_busy$next[0:0]$9508 - attribute \src "libresoc.v:165976.7-165976.20" + attribute \src "libresoc.v:168577.3-168617.6" + wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9559 + attribute \src "libresoc.v:168453.3-168454.51" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9517 + attribute \src "libresoc.v:168011.14-168011.43" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9630 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9560 + attribute \src "libresoc.v:168455.3-168456.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9519 + attribute \src "libresoc.v:168035.14-168035.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9632 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9561 + attribute \src "libresoc.v:168457.3-168458.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9521 + attribute \src "libresoc.v:168044.7-168044.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9634 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9562 + attribute \src "libresoc.v:168471.3-168472.61" + wire width 2 $0\sr_op__input_carry$12[1:0]$9535 + attribute \src "libresoc.v:168061.13-168061.43" + wire width 2 $0\sr_op__input_carry$12[1:0]$9636 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__input_cr$14$next[0:0]$9563 + attribute \src "libresoc.v:168475.3-168476.55" + wire $0\sr_op__input_cr$14[0:0]$9539 + attribute \src "libresoc.v:168074.7-168074.34" + wire $0\sr_op__input_cr$14[0:0]$9638 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 32 $0\sr_op__insn$18$next[31:0]$9564 + attribute \src "libresoc.v:168483.3-168484.47" + wire width 32 $0\sr_op__insn$18[31:0]$9547 + attribute \src "libresoc.v:168083.14-168083.38" + wire width 32 $0\sr_op__insn$18[31:0]$9640 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9565 + attribute \src "libresoc.v:168451.3-168452.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$9515 + attribute \src "libresoc.v:168242.13-168242.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9642 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__invert_in$11$next[0:0]$9566 + attribute \src "libresoc.v:168469.3-168470.57" + wire $0\sr_op__invert_in$11[0:0]$9533 + attribute \src "libresoc.v:168326.7-168326.35" + wire $0\sr_op__invert_in$11[0:0]$9644 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__is_32bit$16$next[0:0]$9567 + attribute \src "libresoc.v:168479.3-168480.55" + wire $0\sr_op__is_32bit$16[0:0]$9543 + attribute \src "libresoc.v:168335.7-168335.34" + wire $0\sr_op__is_32bit$16[0:0]$9646 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__is_signed$17$next[0:0]$9568 + attribute \src "libresoc.v:168481.3-168482.57" + wire $0\sr_op__is_signed$17[0:0]$9545 + attribute \src "libresoc.v:168344.7-168344.35" + wire $0\sr_op__is_signed$17[0:0]$9648 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__oe__oe$8$next[0:0]$9569 + attribute \src "libresoc.v:168463.3-168464.49" + wire $0\sr_op__oe__oe$8[0:0]$9527 + attribute \src "libresoc.v:168355.7-168355.31" + wire $0\sr_op__oe__oe$8[0:0]$9650 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__oe__ok$9$next[0:0]$9570 + attribute \src "libresoc.v:168465.3-168466.49" + wire $0\sr_op__oe__ok$9[0:0]$9529 + attribute \src "libresoc.v:168364.7-168364.31" + wire $0\sr_op__oe__ok$9[0:0]$9652 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__output_carry$13$next[0:0]$9571 + attribute \src "libresoc.v:168473.3-168474.63" + wire $0\sr_op__output_carry$13[0:0]$9537 + attribute \src "libresoc.v:168371.7-168371.38" + wire $0\sr_op__output_carry$13[0:0]$9654 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__output_cr$15$next[0:0]$9572 + attribute \src "libresoc.v:168477.3-168478.57" + wire $0\sr_op__output_cr$15[0:0]$9541 + attribute \src "libresoc.v:168380.7-168380.35" + wire $0\sr_op__output_cr$15[0:0]$9656 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__rc__ok$7$next[0:0]$9573 + attribute \src "libresoc.v:168461.3-168462.49" + wire $0\sr_op__rc__ok$7[0:0]$9525 + attribute \src "libresoc.v:168391.7-168391.31" + wire $0\sr_op__rc__ok$7[0:0]$9658 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__rc__rc$6$next[0:0]$9574 + attribute \src "libresoc.v:168459.3-168460.49" + wire $0\sr_op__rc__rc$6[0:0]$9523 + attribute \src "libresoc.v:168400.7-168400.31" + wire $0\sr_op__rc__rc$6[0:0]$9660 + attribute \src "libresoc.v:168577.3-168617.6" + wire $0\sr_op__write_cr0$10$next[0:0]$9575 + attribute \src "libresoc.v:168467.3-168468.57" + wire $0\sr_op__write_cr0$10[0:0]$9531 + attribute \src "libresoc.v:168407.7-168407.35" + wire $0\sr_op__write_cr0$10[0:0]$9662 + attribute \src "libresoc.v:168656.3-168674.6" + wire width 2 $0\xer_ca$23$next[1:0]$9612 + attribute \src "libresoc.v:168439.3-168440.37" + wire width 2 $0\xer_ca$23[1:0]$9503 + attribute \src "libresoc.v:168416.13-168416.31" + wire width 2 $0\xer_ca$23[1:0]$9664 + attribute \src "libresoc.v:168656.3-168674.6" + wire $0\xer_ca_ok$24$next[0:0]$9613 + attribute \src "libresoc.v:168441.3-168442.43" + wire $0\xer_ca_ok$24[0:0]$9505 + attribute \src "libresoc.v:168425.7-168425.28" + wire $0\xer_ca_ok$24[0:0]$9666 + attribute \src "libresoc.v:168637.3-168655.6" + wire width 4 $1\cr_a$21$next[3:0]$9608 + attribute \src "libresoc.v:168637.3-168655.6" + wire $1\cr_a_ok$22$next[0:0]$9609 + attribute \src "libresoc.v:168564.3-168576.6" + wire width 2 $1\muxid$1$next[1:0]$9557 + attribute \src "libresoc.v:168618.3-168636.6" + wire width 64 $1\o$19$next[63:0]$9602 + attribute \src "libresoc.v:168618.3-168636.6" + wire $1\o_ok$20$next[0:0]$9603 + attribute \src "libresoc.v:168546.3-168563.6" + wire $1\r_busy$next[0:0]$9553 + attribute \src "libresoc.v:167974.7-167974.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:166573.3-166613.6" - wire width 13 $1\sr_op__fn_unit$3$next[12:0]$9531 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9532 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__imm_data__ok$5$next[0:0]$9533 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 2 $1\sr_op__input_carry$12$next[1:0]$9534 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__input_cr$14$next[0:0]$9535 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 32 $1\sr_op__insn$18$next[31:0]$9536 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 7 $1\sr_op__insn_type$2$next[6:0]$9537 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__invert_in$11$next[0:0]$9538 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__is_32bit$16$next[0:0]$9539 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__is_signed$17$next[0:0]$9540 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__oe__oe$8$next[0:0]$9541 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__oe__ok$9$next[0:0]$9542 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__output_carry$13$next[0:0]$9543 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__output_cr$15$next[0:0]$9544 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__rc__ok$7$next[0:0]$9545 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__rc__rc$6$next[0:0]$9546 - attribute \src "libresoc.v:166573.3-166613.6" - wire $1\sr_op__write_cr0$10$next[0:0]$9547 - attribute \src "libresoc.v:166652.3-166670.6" - wire width 2 $1\xer_ca$23$next[1:0]$9569 - attribute \src "libresoc.v:166652.3-166670.6" - wire $1\xer_ca_ok$24$next[0:0]$9570 - attribute \src "libresoc.v:166633.3-166651.6" - wire $2\cr_a_ok$22$next[0:0]$9565 - attribute \src "libresoc.v:166614.3-166632.6" - wire $2\o_ok$20$next[0:0]$9559 - attribute \src "libresoc.v:166542.3-166559.6" - wire $2\r_busy$next[0:0]$9509 - attribute \src "libresoc.v:166573.3-166613.6" - wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9548 - attribute \src "libresoc.v:166573.3-166613.6" - wire $2\sr_op__imm_data__ok$5$next[0:0]$9549 - attribute \src "libresoc.v:166573.3-166613.6" - wire $2\sr_op__oe__oe$8$next[0:0]$9550 - attribute \src "libresoc.v:166573.3-166613.6" - wire $2\sr_op__oe__ok$9$next[0:0]$9551 - attribute \src "libresoc.v:166573.3-166613.6" - wire $2\sr_op__rc__ok$7$next[0:0]$9552 - attribute \src "libresoc.v:166573.3-166613.6" - wire $2\sr_op__rc__rc$6$next[0:0]$9553 - attribute \src "libresoc.v:166652.3-166670.6" - wire $2\xer_ca_ok$24$next[0:0]$9571 - attribute \src "libresoc.v:166434.18-166434.118" - wire $and$libresoc.v:166434$9456_Y + attribute \src "libresoc.v:168577.3-168617.6" + wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9576 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9577 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9578 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 2 $1\sr_op__input_carry$12$next[1:0]$9579 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__input_cr$14$next[0:0]$9580 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 32 $1\sr_op__insn$18$next[31:0]$9581 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9582 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__invert_in$11$next[0:0]$9583 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__is_32bit$16$next[0:0]$9584 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__is_signed$17$next[0:0]$9585 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9586 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9587 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__output_carry$13$next[0:0]$9588 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__output_cr$15$next[0:0]$9589 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9590 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9591 + attribute \src "libresoc.v:168577.3-168617.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9592 + attribute \src "libresoc.v:168656.3-168674.6" + wire width 2 $1\xer_ca$23$next[1:0]$9614 + attribute \src "libresoc.v:168656.3-168674.6" + wire $1\xer_ca_ok$24$next[0:0]$9615 + attribute \src "libresoc.v:168637.3-168655.6" + wire $2\cr_a_ok$22$next[0:0]$9610 + attribute \src "libresoc.v:168618.3-168636.6" + wire $2\o_ok$20$next[0:0]$9604 + attribute \src "libresoc.v:168546.3-168563.6" + wire $2\r_busy$next[0:0]$9554 + attribute \src "libresoc.v:168577.3-168617.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9593 + attribute \src "libresoc.v:168577.3-168617.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9594 + attribute \src "libresoc.v:168577.3-168617.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9595 + attribute \src "libresoc.v:168577.3-168617.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9596 + attribute \src "libresoc.v:168577.3-168617.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9597 + attribute \src "libresoc.v:168577.3-168617.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9598 + attribute \src "libresoc.v:168656.3-168674.6" + wire $2\xer_ca_ok$24$next[0:0]$9616 + attribute \src "libresoc.v:168438.18-168438.118" + wire $and$libresoc.v:168438$9501_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 56 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 24 \cr_a @@ -343368,7 +346057,7 @@ module \pipe2$115 wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$74 - attribute \src "libresoc.v:165629.7-165629.15" + attribute \src "libresoc.v:167623.7-167623.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -343419,37 +346108,39 @@ module \pipe2$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_o_ok$44 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_sr_op__fn_unit$27 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_sr_op__fn_unit$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -343552,6 +346243,7 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -343628,6 +346320,7 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_sr_op__insn_type$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -343691,55 +346384,58 @@ module \pipe2$115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \sr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \sr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 34 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 34 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$55 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \sr_op__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -343866,6 +346562,7 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" @@ -343942,6 +346639,7 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 33 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -344020,6 +346718,7 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -344127,7 +346826,7 @@ module \pipe2$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:166434$9456 + cell $and $and$libresoc.v:168438$9501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -344135,16 +346834,16 @@ module \pipe2$115 parameter \Y_WIDTH 1 connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:166434$9456_Y + connect \Y $and$libresoc.v:168438$9501_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166485.11-166488.4" + attribute \src "libresoc.v:168489.11-168492.4" cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:166489.16-166537.4" + attribute \src "libresoc.v:168493.16-168541.4" cell \output$118 \output connect \cr_a \output_cr_a connect \cr_a$21 \output_cr_a$45 @@ -344195,403 +346894,403 @@ module \pipe2$115 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:166538.11-166541.4" + attribute \src "libresoc.v:168542.11-168545.4" cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:165629.7-165629.20" - process $proc$libresoc.v:165629$9572 + attribute \src "libresoc.v:167623.7-167623.20" + process $proc$libresoc.v:167623$9617 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165640.13-165640.29" - process $proc$libresoc.v:165640$9573 + attribute \src "libresoc.v:167634.13-167634.29" + process $proc$libresoc.v:167634$9618 assign { } { } - assign $0\cr_a$21[3:0]$9574 4'0000 + assign $0\cr_a$21[3:0]$9619 4'0000 sync always sync init - update \cr_a$21 $0\cr_a$21[3:0]$9574 + update \cr_a$21 $0\cr_a$21[3:0]$9619 end - attribute \src "libresoc.v:165649.7-165649.26" - process $proc$libresoc.v:165649$9575 + attribute \src "libresoc.v:167643.7-167643.26" + process $proc$libresoc.v:167643$9620 assign { } { } - assign $0\cr_a_ok$22[0:0]$9576 1'0 + assign $0\cr_a_ok$22[0:0]$9621 1'0 sync always sync init - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9576 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9621 end - attribute \src "libresoc.v:165660.13-165660.29" - process $proc$libresoc.v:165660$9577 + attribute \src "libresoc.v:167654.13-167654.29" + process $proc$libresoc.v:167654$9622 assign { } { } - assign $0\muxid$1[1:0]$9578 2'00 + assign $0\muxid$1[1:0]$9623 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9578 + update \muxid$1 $0\muxid$1[1:0]$9623 end - attribute \src "libresoc.v:165675.14-165675.43" - process $proc$libresoc.v:165675$9579 + attribute \src "libresoc.v:167669.14-167669.43" + process $proc$libresoc.v:167669$9624 assign { } { } - assign $0\o$19[63:0]$9580 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$19[63:0]$9625 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$19 $0\o$19[63:0]$9580 + update \o$19 $0\o$19[63:0]$9625 end - attribute \src "libresoc.v:165684.7-165684.23" - process $proc$libresoc.v:165684$9581 + attribute \src "libresoc.v:167678.7-167678.23" + process $proc$libresoc.v:167678$9626 assign { } { } - assign $0\o_ok$20[0:0]$9582 1'0 + assign $0\o_ok$20[0:0]$9627 1'0 sync always sync init - update \o_ok$20 $0\o_ok$20[0:0]$9582 + update \o_ok$20 $0\o_ok$20[0:0]$9627 end - attribute \src "libresoc.v:165976.7-165976.20" - process $proc$libresoc.v:165976$9583 + attribute \src "libresoc.v:167974.7-167974.20" + process $proc$libresoc.v:167974$9628 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:166011.14-166011.43" - process $proc$libresoc.v:166011$9584 + attribute \src "libresoc.v:168011.14-168011.43" + process $proc$libresoc.v:168011$9629 assign { } { } - assign $0\sr_op__fn_unit$3[12:0]$9585 13'0000000000000 + assign $0\sr_op__fn_unit$3[13:0]$9630 14'00000000000000 sync always sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9585 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9630 end - attribute \src "libresoc.v:166034.14-166034.62" - process $proc$libresoc.v:166034$9586 + attribute \src "libresoc.v:168035.14-168035.62" + process $proc$libresoc.v:168035$9631 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9587 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\sr_op__imm_data__data$4[63:0]$9632 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9587 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9632 end - attribute \src "libresoc.v:166043.7-166043.37" - process $proc$libresoc.v:166043$9588 + attribute \src "libresoc.v:168044.7-168044.37" + process $proc$libresoc.v:168044$9633 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9589 1'0 + assign $0\sr_op__imm_data__ok$5[0:0]$9634 1'0 sync always sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9589 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9634 end - attribute \src "libresoc.v:166060.13-166060.43" - process $proc$libresoc.v:166060$9590 + attribute \src "libresoc.v:168061.13-168061.43" + process $proc$libresoc.v:168061$9635 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9591 2'00 + assign $0\sr_op__input_carry$12[1:0]$9636 2'00 sync always sync init - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9591 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9636 end - attribute \src "libresoc.v:166073.7-166073.34" - process $proc$libresoc.v:166073$9592 + attribute \src "libresoc.v:168074.7-168074.34" + process $proc$libresoc.v:168074$9637 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9593 1'0 + assign $0\sr_op__input_cr$14[0:0]$9638 1'0 sync always sync init - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9593 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9638 end - attribute \src "libresoc.v:166082.14-166082.38" - process $proc$libresoc.v:166082$9594 + attribute \src "libresoc.v:168083.14-168083.38" + process $proc$libresoc.v:168083$9639 assign { } { } - assign $0\sr_op__insn$18[31:0]$9595 0 + assign $0\sr_op__insn$18[31:0]$9640 0 sync always sync init - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9595 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9640 end - attribute \src "libresoc.v:166239.13-166239.41" - process $proc$libresoc.v:166239$9596 + attribute \src "libresoc.v:168242.13-168242.41" + process $proc$libresoc.v:168242$9641 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9597 7'0000000 + assign $0\sr_op__insn_type$2[6:0]$9642 7'0000000 sync always sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9597 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9642 end - attribute \src "libresoc.v:166322.7-166322.35" - process $proc$libresoc.v:166322$9598 + attribute \src "libresoc.v:168326.7-168326.35" + process $proc$libresoc.v:168326$9643 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9599 1'0 + assign $0\sr_op__invert_in$11[0:0]$9644 1'0 sync always sync init - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9599 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9644 end - attribute \src "libresoc.v:166331.7-166331.34" - process $proc$libresoc.v:166331$9600 + attribute \src "libresoc.v:168335.7-168335.34" + process $proc$libresoc.v:168335$9645 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9601 1'0 + assign $0\sr_op__is_32bit$16[0:0]$9646 1'0 sync always sync init - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9601 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9646 end - attribute \src "libresoc.v:166340.7-166340.35" - process $proc$libresoc.v:166340$9602 + attribute \src "libresoc.v:168344.7-168344.35" + process $proc$libresoc.v:168344$9647 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9603 1'0 + assign $0\sr_op__is_signed$17[0:0]$9648 1'0 sync always sync init - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9603 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9648 end - attribute \src "libresoc.v:166351.7-166351.31" - process $proc$libresoc.v:166351$9604 + attribute \src "libresoc.v:168355.7-168355.31" + process $proc$libresoc.v:168355$9649 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9605 1'0 + assign $0\sr_op__oe__oe$8[0:0]$9650 1'0 sync always sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9605 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9650 end - attribute \src "libresoc.v:166360.7-166360.31" - process $proc$libresoc.v:166360$9606 + attribute \src "libresoc.v:168364.7-168364.31" + process $proc$libresoc.v:168364$9651 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9607 1'0 + assign $0\sr_op__oe__ok$9[0:0]$9652 1'0 sync always sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9607 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9652 end - attribute \src "libresoc.v:166367.7-166367.38" - process $proc$libresoc.v:166367$9608 + attribute \src "libresoc.v:168371.7-168371.38" + process $proc$libresoc.v:168371$9653 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9609 1'0 + assign $0\sr_op__output_carry$13[0:0]$9654 1'0 sync always sync init - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9609 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9654 end - attribute \src "libresoc.v:166376.7-166376.35" - process $proc$libresoc.v:166376$9610 + attribute \src "libresoc.v:168380.7-168380.35" + process $proc$libresoc.v:168380$9655 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9611 1'0 + assign $0\sr_op__output_cr$15[0:0]$9656 1'0 sync always sync init - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9611 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9656 end - attribute \src "libresoc.v:166387.7-166387.31" - process $proc$libresoc.v:166387$9612 + attribute \src "libresoc.v:168391.7-168391.31" + process $proc$libresoc.v:168391$9657 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9613 1'0 + assign $0\sr_op__rc__ok$7[0:0]$9658 1'0 sync always sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9613 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9658 end - attribute \src "libresoc.v:166396.7-166396.31" - process $proc$libresoc.v:166396$9614 + attribute \src "libresoc.v:168400.7-168400.31" + process $proc$libresoc.v:168400$9659 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9615 1'0 + assign $0\sr_op__rc__rc$6[0:0]$9660 1'0 sync always sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9615 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9660 end - attribute \src "libresoc.v:166403.7-166403.35" - process $proc$libresoc.v:166403$9616 + attribute \src "libresoc.v:168407.7-168407.35" + process $proc$libresoc.v:168407$9661 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9617 1'0 + assign $0\sr_op__write_cr0$10[0:0]$9662 1'0 sync always sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9617 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9662 end - attribute \src "libresoc.v:166412.13-166412.31" - process $proc$libresoc.v:166412$9618 + attribute \src "libresoc.v:168416.13-168416.31" + process $proc$libresoc.v:168416$9663 assign { } { } - assign $0\xer_ca$23[1:0]$9619 2'00 + assign $0\xer_ca$23[1:0]$9664 2'00 sync always sync init - update \xer_ca$23 $0\xer_ca$23[1:0]$9619 + update \xer_ca$23 $0\xer_ca$23[1:0]$9664 end - attribute \src "libresoc.v:166421.7-166421.28" - process $proc$libresoc.v:166421$9620 + attribute \src "libresoc.v:168425.7-168425.28" + process $proc$libresoc.v:168425$9665 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9621 1'0 + assign $0\xer_ca_ok$24[0:0]$9666 1'0 sync always sync init - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9621 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9666 end - attribute \src "libresoc.v:166435.3-166436.37" - process $proc$libresoc.v:166435$9457 + attribute \src "libresoc.v:168439.3-168440.37" + process $proc$libresoc.v:168439$9502 assign { } { } - assign $0\xer_ca$23[1:0]$9458 \xer_ca$23$next + assign $0\xer_ca$23[1:0]$9503 \xer_ca$23$next sync posedge \coresync_clk - update \xer_ca$23 $0\xer_ca$23[1:0]$9458 + update \xer_ca$23 $0\xer_ca$23[1:0]$9503 end - attribute \src "libresoc.v:166437.3-166438.43" - process $proc$libresoc.v:166437$9459 + attribute \src "libresoc.v:168441.3-168442.43" + process $proc$libresoc.v:168441$9504 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9460 \xer_ca_ok$24$next + assign $0\xer_ca_ok$24[0:0]$9505 \xer_ca_ok$24$next sync posedge \coresync_clk - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9460 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9505 end - attribute \src "libresoc.v:166439.3-166440.33" - process $proc$libresoc.v:166439$9461 + attribute \src "libresoc.v:168443.3-168444.33" + process $proc$libresoc.v:168443$9506 assign { } { } - assign $0\cr_a$21[3:0]$9462 \cr_a$21$next + assign $0\cr_a$21[3:0]$9507 \cr_a$21$next sync posedge \coresync_clk - update \cr_a$21 $0\cr_a$21[3:0]$9462 + update \cr_a$21 $0\cr_a$21[3:0]$9507 end - attribute \src "libresoc.v:166441.3-166442.39" - process $proc$libresoc.v:166441$9463 + attribute \src "libresoc.v:168445.3-168446.39" + process $proc$libresoc.v:168445$9508 assign { } { } - assign $0\cr_a_ok$22[0:0]$9464 \cr_a_ok$22$next + assign $0\cr_a_ok$22[0:0]$9509 \cr_a_ok$22$next sync posedge \coresync_clk - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9464 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9509 end - attribute \src "libresoc.v:166443.3-166444.27" - process $proc$libresoc.v:166443$9465 + attribute \src "libresoc.v:168447.3-168448.27" + process $proc$libresoc.v:168447$9510 assign { } { } - assign $0\o$19[63:0]$9466 \o$19$next + assign $0\o$19[63:0]$9511 \o$19$next sync posedge \coresync_clk - update \o$19 $0\o$19[63:0]$9466 + update \o$19 $0\o$19[63:0]$9511 end - attribute \src "libresoc.v:166445.3-166446.33" - process $proc$libresoc.v:166445$9467 + attribute \src "libresoc.v:168449.3-168450.33" + process $proc$libresoc.v:168449$9512 assign { } { } - assign $0\o_ok$20[0:0]$9468 \o_ok$20$next + assign $0\o_ok$20[0:0]$9513 \o_ok$20$next sync posedge \coresync_clk - update \o_ok$20 $0\o_ok$20[0:0]$9468 + update \o_ok$20 $0\o_ok$20[0:0]$9513 end - attribute \src "libresoc.v:166447.3-166448.55" - process $proc$libresoc.v:166447$9469 + attribute \src "libresoc.v:168451.3-168452.55" + process $proc$libresoc.v:168451$9514 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9470 \sr_op__insn_type$2$next + assign $0\sr_op__insn_type$2[6:0]$9515 \sr_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9470 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9515 end - attribute \src "libresoc.v:166449.3-166450.51" - process $proc$libresoc.v:166449$9471 + attribute \src "libresoc.v:168453.3-168454.51" + process $proc$libresoc.v:168453$9516 assign { } { } - assign $0\sr_op__fn_unit$3[12:0]$9472 \sr_op__fn_unit$3$next + assign $0\sr_op__fn_unit$3[13:0]$9517 \sr_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9472 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9517 end - attribute \src "libresoc.v:166451.3-166452.65" - process $proc$libresoc.v:166451$9473 + attribute \src "libresoc.v:168455.3-168456.65" + process $proc$libresoc.v:168455$9518 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9474 \sr_op__imm_data__data$4$next + assign $0\sr_op__imm_data__data$4[63:0]$9519 \sr_op__imm_data__data$4$next sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9474 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9519 end - attribute \src "libresoc.v:166453.3-166454.61" - process $proc$libresoc.v:166453$9475 + attribute \src "libresoc.v:168457.3-168458.61" + process $proc$libresoc.v:168457$9520 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9476 \sr_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__ok$5[0:0]$9521 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9476 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9521 end - attribute \src "libresoc.v:166455.3-166456.49" - process $proc$libresoc.v:166455$9477 + attribute \src "libresoc.v:168459.3-168460.49" + process $proc$libresoc.v:168459$9522 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9478 \sr_op__rc__rc$6$next + assign $0\sr_op__rc__rc$6[0:0]$9523 \sr_op__rc__rc$6$next sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9478 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9523 end - attribute \src "libresoc.v:166457.3-166458.49" - process $proc$libresoc.v:166457$9479 + attribute \src "libresoc.v:168461.3-168462.49" + process $proc$libresoc.v:168461$9524 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9480 \sr_op__rc__ok$7$next + assign $0\sr_op__rc__ok$7[0:0]$9525 \sr_op__rc__ok$7$next sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9480 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9525 end - attribute \src "libresoc.v:166459.3-166460.49" - process $proc$libresoc.v:166459$9481 + attribute \src "libresoc.v:168463.3-168464.49" + process $proc$libresoc.v:168463$9526 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9482 \sr_op__oe__oe$8$next + assign $0\sr_op__oe__oe$8[0:0]$9527 \sr_op__oe__oe$8$next sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9482 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9527 end - attribute \src "libresoc.v:166461.3-166462.49" - process $proc$libresoc.v:166461$9483 + attribute \src "libresoc.v:168465.3-168466.49" + process $proc$libresoc.v:168465$9528 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9484 \sr_op__oe__ok$9$next + assign $0\sr_op__oe__ok$9[0:0]$9529 \sr_op__oe__ok$9$next sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9484 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9529 end - attribute \src "libresoc.v:166463.3-166464.57" - process $proc$libresoc.v:166463$9485 + attribute \src "libresoc.v:168467.3-168468.57" + process $proc$libresoc.v:168467$9530 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9486 \sr_op__write_cr0$10$next + assign $0\sr_op__write_cr0$10[0:0]$9531 \sr_op__write_cr0$10$next sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9486 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9531 end - attribute \src "libresoc.v:166465.3-166466.57" - process $proc$libresoc.v:166465$9487 + attribute \src "libresoc.v:168469.3-168470.57" + process $proc$libresoc.v:168469$9532 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9488 \sr_op__invert_in$11$next + assign $0\sr_op__invert_in$11[0:0]$9533 \sr_op__invert_in$11$next sync posedge \coresync_clk - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9488 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9533 end - attribute \src "libresoc.v:166467.3-166468.61" - process $proc$libresoc.v:166467$9489 + attribute \src "libresoc.v:168471.3-168472.61" + process $proc$libresoc.v:168471$9534 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9490 \sr_op__input_carry$12$next + assign $0\sr_op__input_carry$12[1:0]$9535 \sr_op__input_carry$12$next sync posedge \coresync_clk - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9490 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9535 end - attribute \src "libresoc.v:166469.3-166470.63" - process $proc$libresoc.v:166469$9491 + attribute \src "libresoc.v:168473.3-168474.63" + process $proc$libresoc.v:168473$9536 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9492 \sr_op__output_carry$13$next + assign $0\sr_op__output_carry$13[0:0]$9537 \sr_op__output_carry$13$next sync posedge \coresync_clk - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9492 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9537 end - attribute \src "libresoc.v:166471.3-166472.55" - process $proc$libresoc.v:166471$9493 + attribute \src "libresoc.v:168475.3-168476.55" + process $proc$libresoc.v:168475$9538 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9494 \sr_op__input_cr$14$next + assign $0\sr_op__input_cr$14[0:0]$9539 \sr_op__input_cr$14$next sync posedge \coresync_clk - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9494 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9539 end - attribute \src "libresoc.v:166473.3-166474.57" - process $proc$libresoc.v:166473$9495 + attribute \src "libresoc.v:168477.3-168478.57" + process $proc$libresoc.v:168477$9540 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9496 \sr_op__output_cr$15$next + assign $0\sr_op__output_cr$15[0:0]$9541 \sr_op__output_cr$15$next sync posedge \coresync_clk - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9496 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9541 end - attribute \src "libresoc.v:166475.3-166476.55" - process $proc$libresoc.v:166475$9497 + attribute \src "libresoc.v:168479.3-168480.55" + process $proc$libresoc.v:168479$9542 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9498 \sr_op__is_32bit$16$next + assign $0\sr_op__is_32bit$16[0:0]$9543 \sr_op__is_32bit$16$next sync posedge \coresync_clk - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9498 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9543 end - attribute \src "libresoc.v:166477.3-166478.57" - process $proc$libresoc.v:166477$9499 + attribute \src "libresoc.v:168481.3-168482.57" + process $proc$libresoc.v:168481$9544 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9500 \sr_op__is_signed$17$next + assign $0\sr_op__is_signed$17[0:0]$9545 \sr_op__is_signed$17$next sync posedge \coresync_clk - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9500 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9545 end - attribute \src "libresoc.v:166479.3-166480.47" - process $proc$libresoc.v:166479$9501 + attribute \src "libresoc.v:168483.3-168484.47" + process $proc$libresoc.v:168483$9546 assign { } { } - assign $0\sr_op__insn$18[31:0]$9502 \sr_op__insn$18$next + assign $0\sr_op__insn$18[31:0]$9547 \sr_op__insn$18$next sync posedge \coresync_clk - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9502 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9547 end - attribute \src "libresoc.v:166481.3-166482.33" - process $proc$libresoc.v:166481$9503 + attribute \src "libresoc.v:168485.3-168486.33" + process $proc$libresoc.v:168485$9548 assign { } { } - assign $0\muxid$1[1:0]$9504 \muxid$1$next + assign $0\muxid$1[1:0]$9549 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9504 + update \muxid$1 $0\muxid$1[1:0]$9549 end - attribute \src "libresoc.v:166483.3-166484.29" - process $proc$libresoc.v:166483$9505 + attribute \src "libresoc.v:168487.3-168488.29" + process $proc$libresoc.v:168487$9550 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:166542.3-166559.6" - process $proc$libresoc.v:166542$9506 + attribute \src "libresoc.v:168546.3-168563.6" + process $proc$libresoc.v:168546$9551 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9507 $2\r_busy$next[0:0]$9509 - attribute \src "libresoc.v:166543.5-166543.29" + assign $0\r_busy$next[0:0]$9552 $2\r_busy$next[0:0]$9554 + attribute \src "libresoc.v:168547.5-168547.29" switch \initial - attribute \src "libresoc.v:166543.9-166543.17" + attribute \src "libresoc.v:168547.9-168547.17" case 1'1 case end @@ -344600,34 +347299,34 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9508 1'1 + assign $1\r_busy$next[0:0]$9553 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9508 1'0 + assign $1\r_busy$next[0:0]$9553 1'0 case - assign $1\r_busy$next[0:0]$9508 \r_busy + assign $1\r_busy$next[0:0]$9553 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9509 1'0 + assign $2\r_busy$next[0:0]$9554 1'0 case - assign $2\r_busy$next[0:0]$9509 $1\r_busy$next[0:0]$9508 + assign $2\r_busy$next[0:0]$9554 $1\r_busy$next[0:0]$9553 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9507 + update \r_busy$next $0\r_busy$next[0:0]$9552 end - attribute \src "libresoc.v:166560.3-166572.6" - process $proc$libresoc.v:166560$9510 + attribute \src "libresoc.v:168564.3-168576.6" + process $proc$libresoc.v:168564$9555 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9511 $1\muxid$1$next[1:0]$9512 - attribute \src "libresoc.v:166561.5-166561.29" + assign $0\muxid$1$next[1:0]$9556 $1\muxid$1$next[1:0]$9557 + attribute \src "libresoc.v:168565.5-168565.29" switch \initial - attribute \src "libresoc.v:166561.9-166561.17" + attribute \src "libresoc.v:168565.9-168565.17" case 1'1 case end @@ -344636,19 +347335,19 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9512 \muxid$53 + assign $1\muxid$1$next[1:0]$9557 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9512 \muxid$53 + assign $1\muxid$1$next[1:0]$9557 \muxid$53 case - assign $1\muxid$1$next[1:0]$9512 \muxid$1 + assign $1\muxid$1$next[1:0]$9557 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9511 + update \muxid$1$next $0\muxid$1$next[1:0]$9556 end - attribute \src "libresoc.v:166573.3-166613.6" - process $proc$libresoc.v:166573$9513 + attribute \src "libresoc.v:168577.3-168617.6" + process $proc$libresoc.v:168577$9558 assign { } { } assign { } { } assign { } { } @@ -344683,32 +347382,32 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$3$next[12:0]$9514 $1\sr_op__fn_unit$3$next[12:0]$9531 + assign $0\sr_op__fn_unit$3$next[13:0]$9559 $1\sr_op__fn_unit$3$next[13:0]$9576 assign { } { } assign { } { } - assign $0\sr_op__input_carry$12$next[1:0]$9517 $1\sr_op__input_carry$12$next[1:0]$9534 - assign $0\sr_op__input_cr$14$next[0:0]$9518 $1\sr_op__input_cr$14$next[0:0]$9535 - assign $0\sr_op__insn$18$next[31:0]$9519 $1\sr_op__insn$18$next[31:0]$9536 - assign $0\sr_op__insn_type$2$next[6:0]$9520 $1\sr_op__insn_type$2$next[6:0]$9537 - assign $0\sr_op__invert_in$11$next[0:0]$9521 $1\sr_op__invert_in$11$next[0:0]$9538 - assign $0\sr_op__is_32bit$16$next[0:0]$9522 $1\sr_op__is_32bit$16$next[0:0]$9539 - assign $0\sr_op__is_signed$17$next[0:0]$9523 $1\sr_op__is_signed$17$next[0:0]$9540 + assign $0\sr_op__input_carry$12$next[1:0]$9562 $1\sr_op__input_carry$12$next[1:0]$9579 + assign $0\sr_op__input_cr$14$next[0:0]$9563 $1\sr_op__input_cr$14$next[0:0]$9580 + assign $0\sr_op__insn$18$next[31:0]$9564 $1\sr_op__insn$18$next[31:0]$9581 + assign $0\sr_op__insn_type$2$next[6:0]$9565 $1\sr_op__insn_type$2$next[6:0]$9582 + assign $0\sr_op__invert_in$11$next[0:0]$9566 $1\sr_op__invert_in$11$next[0:0]$9583 + assign $0\sr_op__is_32bit$16$next[0:0]$9567 $1\sr_op__is_32bit$16$next[0:0]$9584 + assign $0\sr_op__is_signed$17$next[0:0]$9568 $1\sr_op__is_signed$17$next[0:0]$9585 assign { } { } assign { } { } - assign $0\sr_op__output_carry$13$next[0:0]$9526 $1\sr_op__output_carry$13$next[0:0]$9543 - assign $0\sr_op__output_cr$15$next[0:0]$9527 $1\sr_op__output_cr$15$next[0:0]$9544 + assign $0\sr_op__output_carry$13$next[0:0]$9571 $1\sr_op__output_carry$13$next[0:0]$9588 + assign $0\sr_op__output_cr$15$next[0:0]$9572 $1\sr_op__output_cr$15$next[0:0]$9589 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9530 $1\sr_op__write_cr0$10$next[0:0]$9547 - assign $0\sr_op__imm_data__data$4$next[63:0]$9515 $2\sr_op__imm_data__data$4$next[63:0]$9548 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9516 $2\sr_op__imm_data__ok$5$next[0:0]$9549 - assign $0\sr_op__oe__oe$8$next[0:0]$9524 $2\sr_op__oe__oe$8$next[0:0]$9550 - assign $0\sr_op__oe__ok$9$next[0:0]$9525 $2\sr_op__oe__ok$9$next[0:0]$9551 - assign $0\sr_op__rc__ok$7$next[0:0]$9528 $2\sr_op__rc__ok$7$next[0:0]$9552 - assign $0\sr_op__rc__rc$6$next[0:0]$9529 $2\sr_op__rc__rc$6$next[0:0]$9553 - attribute \src "libresoc.v:166574.5-166574.29" + assign $0\sr_op__write_cr0$10$next[0:0]$9575 $1\sr_op__write_cr0$10$next[0:0]$9592 + assign $0\sr_op__imm_data__data$4$next[63:0]$9560 $2\sr_op__imm_data__data$4$next[63:0]$9593 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9561 $2\sr_op__imm_data__ok$5$next[0:0]$9594 + assign $0\sr_op__oe__oe$8$next[0:0]$9569 $2\sr_op__oe__oe$8$next[0:0]$9595 + assign $0\sr_op__oe__ok$9$next[0:0]$9570 $2\sr_op__oe__ok$9$next[0:0]$9596 + assign $0\sr_op__rc__ok$7$next[0:0]$9573 $2\sr_op__rc__ok$7$next[0:0]$9597 + assign $0\sr_op__rc__rc$6$next[0:0]$9574 $2\sr_op__rc__rc$6$next[0:0]$9598 + attribute \src "libresoc.v:168578.5-168578.29" switch \initial - attribute \src "libresoc.v:166574.9-166574.17" + attribute \src "libresoc.v:168578.9-168578.17" case 1'1 case end @@ -344733,7 +347432,7 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9536 $1\sr_op__is_signed$17$next[0:0]$9540 $1\sr_op__is_32bit$16$next[0:0]$9539 $1\sr_op__output_cr$15$next[0:0]$9544 $1\sr_op__input_cr$14$next[0:0]$9535 $1\sr_op__output_carry$13$next[0:0]$9543 $1\sr_op__input_carry$12$next[1:0]$9534 $1\sr_op__invert_in$11$next[0:0]$9538 $1\sr_op__write_cr0$10$next[0:0]$9547 $1\sr_op__oe__ok$9$next[0:0]$9542 $1\sr_op__oe__oe$8$next[0:0]$9541 $1\sr_op__rc__ok$7$next[0:0]$9545 $1\sr_op__rc__rc$6$next[0:0]$9546 $1\sr_op__imm_data__ok$5$next[0:0]$9533 $1\sr_op__imm_data__data$4$next[63:0]$9532 $1\sr_op__fn_unit$3$next[12:0]$9531 $1\sr_op__insn_type$2$next[6:0]$9537 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9581 $1\sr_op__is_signed$17$next[0:0]$9585 $1\sr_op__is_32bit$16$next[0:0]$9584 $1\sr_op__output_cr$15$next[0:0]$9589 $1\sr_op__input_cr$14$next[0:0]$9580 $1\sr_op__output_carry$13$next[0:0]$9588 $1\sr_op__input_carry$12$next[1:0]$9579 $1\sr_op__invert_in$11$next[0:0]$9583 $1\sr_op__write_cr0$10$next[0:0]$9592 $1\sr_op__oe__ok$9$next[0:0]$9587 $1\sr_op__oe__oe$8$next[0:0]$9586 $1\sr_op__rc__ok$7$next[0:0]$9590 $1\sr_op__rc__rc$6$next[0:0]$9591 $1\sr_op__imm_data__ok$5$next[0:0]$9578 $1\sr_op__imm_data__data$4$next[63:0]$9577 $1\sr_op__fn_unit$3$next[13:0]$9576 $1\sr_op__insn_type$2$next[6:0]$9582 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -344753,25 +347452,25 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9536 $1\sr_op__is_signed$17$next[0:0]$9540 $1\sr_op__is_32bit$16$next[0:0]$9539 $1\sr_op__output_cr$15$next[0:0]$9544 $1\sr_op__input_cr$14$next[0:0]$9535 $1\sr_op__output_carry$13$next[0:0]$9543 $1\sr_op__input_carry$12$next[1:0]$9534 $1\sr_op__invert_in$11$next[0:0]$9538 $1\sr_op__write_cr0$10$next[0:0]$9547 $1\sr_op__oe__ok$9$next[0:0]$9542 $1\sr_op__oe__oe$8$next[0:0]$9541 $1\sr_op__rc__ok$7$next[0:0]$9545 $1\sr_op__rc__rc$6$next[0:0]$9546 $1\sr_op__imm_data__ok$5$next[0:0]$9533 $1\sr_op__imm_data__data$4$next[63:0]$9532 $1\sr_op__fn_unit$3$next[12:0]$9531 $1\sr_op__insn_type$2$next[6:0]$9537 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9581 $1\sr_op__is_signed$17$next[0:0]$9585 $1\sr_op__is_32bit$16$next[0:0]$9584 $1\sr_op__output_cr$15$next[0:0]$9589 $1\sr_op__input_cr$14$next[0:0]$9580 $1\sr_op__output_carry$13$next[0:0]$9588 $1\sr_op__input_carry$12$next[1:0]$9579 $1\sr_op__invert_in$11$next[0:0]$9583 $1\sr_op__write_cr0$10$next[0:0]$9592 $1\sr_op__oe__ok$9$next[0:0]$9587 $1\sr_op__oe__oe$8$next[0:0]$9586 $1\sr_op__rc__ok$7$next[0:0]$9590 $1\sr_op__rc__rc$6$next[0:0]$9591 $1\sr_op__imm_data__ok$5$next[0:0]$9578 $1\sr_op__imm_data__data$4$next[63:0]$9577 $1\sr_op__fn_unit$3$next[13:0]$9576 $1\sr_op__insn_type$2$next[6:0]$9582 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case - assign $1\sr_op__fn_unit$3$next[12:0]$9531 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9532 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9533 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$12$next[1:0]$9534 \sr_op__input_carry$12 - assign $1\sr_op__input_cr$14$next[0:0]$9535 \sr_op__input_cr$14 - assign $1\sr_op__insn$18$next[31:0]$9536 \sr_op__insn$18 - assign $1\sr_op__insn_type$2$next[6:0]$9537 \sr_op__insn_type$2 - assign $1\sr_op__invert_in$11$next[0:0]$9538 \sr_op__invert_in$11 - assign $1\sr_op__is_32bit$16$next[0:0]$9539 \sr_op__is_32bit$16 - assign $1\sr_op__is_signed$17$next[0:0]$9540 \sr_op__is_signed$17 - assign $1\sr_op__oe__oe$8$next[0:0]$9541 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9542 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$13$next[0:0]$9543 \sr_op__output_carry$13 - assign $1\sr_op__output_cr$15$next[0:0]$9544 \sr_op__output_cr$15 - assign $1\sr_op__rc__ok$7$next[0:0]$9545 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9546 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9547 \sr_op__write_cr0$10 + assign $1\sr_op__fn_unit$3$next[13:0]$9576 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9577 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9578 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9579 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9580 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9581 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9582 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9583 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9584 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9585 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9586 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9587 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9588 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9589 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9590 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9591 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9592 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -344783,51 +347482,51 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9548 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9549 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9553 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9552 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9550 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9551 1'0 + assign $2\sr_op__imm_data__data$4$next[63:0]$9593 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9594 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9598 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9597 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9595 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9596 1'0 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9548 $1\sr_op__imm_data__data$4$next[63:0]$9532 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9549 $1\sr_op__imm_data__ok$5$next[0:0]$9533 - assign $2\sr_op__oe__oe$8$next[0:0]$9550 $1\sr_op__oe__oe$8$next[0:0]$9541 - assign $2\sr_op__oe__ok$9$next[0:0]$9551 $1\sr_op__oe__ok$9$next[0:0]$9542 - assign $2\sr_op__rc__ok$7$next[0:0]$9552 $1\sr_op__rc__ok$7$next[0:0]$9545 - assign $2\sr_op__rc__rc$6$next[0:0]$9553 $1\sr_op__rc__rc$6$next[0:0]$9546 + assign $2\sr_op__imm_data__data$4$next[63:0]$9593 $1\sr_op__imm_data__data$4$next[63:0]$9577 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9594 $1\sr_op__imm_data__ok$5$next[0:0]$9578 + assign $2\sr_op__oe__oe$8$next[0:0]$9595 $1\sr_op__oe__oe$8$next[0:0]$9586 + assign $2\sr_op__oe__ok$9$next[0:0]$9596 $1\sr_op__oe__ok$9$next[0:0]$9587 + assign $2\sr_op__rc__ok$7$next[0:0]$9597 $1\sr_op__rc__ok$7$next[0:0]$9590 + assign $2\sr_op__rc__rc$6$next[0:0]$9598 $1\sr_op__rc__rc$6$next[0:0]$9591 end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[12:0]$9514 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9515 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9516 - update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9517 - update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9518 - update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9519 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9520 - update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9521 - update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9522 - update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9523 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9524 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9525 - update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9526 - update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9527 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9528 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9529 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9530 + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9559 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9560 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9561 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9562 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9563 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9564 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9565 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9566 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9567 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9568 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9569 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9570 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9571 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9572 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9573 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9574 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9575 end - attribute \src "libresoc.v:166614.3-166632.6" - process $proc$libresoc.v:166614$9554 + attribute \src "libresoc.v:168618.3-168636.6" + process $proc$libresoc.v:168618$9599 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$19$next[63:0]$9555 $1\o$19$next[63:0]$9557 + assign $0\o$19$next[63:0]$9600 $1\o$19$next[63:0]$9602 assign { } { } - assign $0\o_ok$20$next[0:0]$9556 $2\o_ok$20$next[0:0]$9559 - attribute \src "libresoc.v:166615.5-166615.29" + assign $0\o_ok$20$next[0:0]$9601 $2\o_ok$20$next[0:0]$9604 + attribute \src "libresoc.v:168619.5-168619.29" switch \initial - attribute \src "libresoc.v:166615.9-166615.17" + attribute \src "libresoc.v:168619.9-168619.17" case 1'1 case end @@ -344837,41 +347536,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9558 $1\o$19$next[63:0]$9557 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9603 $1\o$19$next[63:0]$9602 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9558 $1\o$19$next[63:0]$9557 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9603 $1\o$19$next[63:0]$9602 } { \o_ok$72 \o$71 } case - assign $1\o$19$next[63:0]$9557 \o$19 - assign $1\o_ok$20$next[0:0]$9558 \o_ok$20 + assign $1\o$19$next[63:0]$9602 \o$19 + assign $1\o_ok$20$next[0:0]$9603 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$20$next[0:0]$9559 1'0 + assign $2\o_ok$20$next[0:0]$9604 1'0 case - assign $2\o_ok$20$next[0:0]$9559 $1\o_ok$20$next[0:0]$9558 + assign $2\o_ok$20$next[0:0]$9604 $1\o_ok$20$next[0:0]$9603 end sync always - update \o$19$next $0\o$19$next[63:0]$9555 - update \o_ok$20$next $0\o_ok$20$next[0:0]$9556 + update \o$19$next $0\o$19$next[63:0]$9600 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9601 end - attribute \src "libresoc.v:166633.3-166651.6" - process $proc$libresoc.v:166633$9560 + attribute \src "libresoc.v:168637.3-168655.6" + process $proc$libresoc.v:168637$9605 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$21$next[3:0]$9561 $1\cr_a$21$next[3:0]$9563 + assign $0\cr_a$21$next[3:0]$9606 $1\cr_a$21$next[3:0]$9608 assign { } { } - assign $0\cr_a_ok$22$next[0:0]$9562 $2\cr_a_ok$22$next[0:0]$9565 - attribute \src "libresoc.v:166634.5-166634.29" + assign $0\cr_a_ok$22$next[0:0]$9607 $2\cr_a_ok$22$next[0:0]$9610 + attribute \src "libresoc.v:168638.5-168638.29" switch \initial - attribute \src "libresoc.v:166634.9-166634.17" + attribute \src "libresoc.v:168638.9-168638.17" case 1'1 case end @@ -344881,41 +347580,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9564 $1\cr_a$21$next[3:0]$9563 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9609 $1\cr_a$21$next[3:0]$9608 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9564 $1\cr_a$21$next[3:0]$9563 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9609 $1\cr_a$21$next[3:0]$9608 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$21$next[3:0]$9563 \cr_a$21 - assign $1\cr_a_ok$22$next[0:0]$9564 \cr_a_ok$22 + assign $1\cr_a$21$next[3:0]$9608 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9609 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$22$next[0:0]$9565 1'0 + assign $2\cr_a_ok$22$next[0:0]$9610 1'0 case - assign $2\cr_a_ok$22$next[0:0]$9565 $1\cr_a_ok$22$next[0:0]$9564 + assign $2\cr_a_ok$22$next[0:0]$9610 $1\cr_a_ok$22$next[0:0]$9609 end sync always - update \cr_a$21$next $0\cr_a$21$next[3:0]$9561 - update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9562 + update \cr_a$21$next $0\cr_a$21$next[3:0]$9606 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9607 end - attribute \src "libresoc.v:166652.3-166670.6" - process $proc$libresoc.v:166652$9566 + attribute \src "libresoc.v:168656.3-168674.6" + process $proc$libresoc.v:168656$9611 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$23$next[1:0]$9567 $1\xer_ca$23$next[1:0]$9569 + assign $0\xer_ca$23$next[1:0]$9612 $1\xer_ca$23$next[1:0]$9614 assign { } { } - assign $0\xer_ca_ok$24$next[0:0]$9568 $2\xer_ca_ok$24$next[0:0]$9571 - attribute \src "libresoc.v:166653.5-166653.29" + assign $0\xer_ca_ok$24$next[0:0]$9613 $2\xer_ca_ok$24$next[0:0]$9616 + attribute \src "libresoc.v:168657.5-168657.29" switch \initial - attribute \src "libresoc.v:166653.9-166653.17" + attribute \src "libresoc.v:168657.9-168657.17" case 1'1 case end @@ -344925,30 +347624,30 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9570 $1\xer_ca$23$next[1:0]$9569 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9615 $1\xer_ca$23$next[1:0]$9614 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9570 $1\xer_ca$23$next[1:0]$9569 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9615 $1\xer_ca$23$next[1:0]$9614 } { \xer_ca_ok$76 \xer_ca$75 } case - assign $1\xer_ca$23$next[1:0]$9569 \xer_ca$23 - assign $1\xer_ca_ok$24$next[0:0]$9570 \xer_ca_ok$24 + assign $1\xer_ca$23$next[1:0]$9614 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9615 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$24$next[0:0]$9571 1'0 + assign $2\xer_ca_ok$24$next[0:0]$9616 1'0 case - assign $2\xer_ca_ok$24$next[0:0]$9571 $1\xer_ca_ok$24$next[0:0]$9570 + assign $2\xer_ca_ok$24$next[0:0]$9616 $1\xer_ca_ok$24$next[0:0]$9615 end sync always - update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9567 - update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9568 + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9612 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9613 end - connect \$51 $and$libresoc.v:166434$9456_Y + connect \$51 $and$libresoc.v:168438$9501_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } @@ -344966,200 +347665,200 @@ module \pipe2$115 connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:166691.1-167645.10" +attribute \src "libresoc.v:168695.1-169659.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" module \pipe2$35 - attribute \src "libresoc.v:167551.3-167569.6" - wire width 64 $0\fast1$11$next[63:0]$9690 - attribute \src "libresoc.v:167432.3-167433.35" - wire width 64 $0\fast1$11[63:0]$9654 - attribute \src "libresoc.v:166703.14-166703.47" - wire width 64 $0\fast1$11[63:0]$9714 - attribute \src "libresoc.v:167551.3-167569.6" - wire $0\fast1_ok$next[0:0]$9689 - attribute \src "libresoc.v:167434.3-167435.33" + attribute \src "libresoc.v:169565.3-169583.6" + wire width 64 $0\fast1$11$next[63:0]$9735 + attribute \src "libresoc.v:169414.3-169415.35" + wire width 64 $0\fast1$11[63:0]$9673 + attribute \src "libresoc.v:168707.14-168707.47" + wire width 64 $0\fast1$11[63:0]$9759 + attribute \src "libresoc.v:169565.3-169583.6" + wire $0\fast1_ok$next[0:0]$9734 + attribute \src "libresoc.v:169416.3-169417.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:167570.3-167588.6" - wire width 64 $0\fast2$12$next[63:0]$9696 - attribute \src "libresoc.v:167428.3-167429.35" - wire width 64 $0\fast2$12[63:0]$9651 - attribute \src "libresoc.v:166719.14-166719.47" - wire width 64 $0\fast2$12[63:0]$9717 - attribute \src "libresoc.v:167570.3-167588.6" - wire $0\fast2_ok$next[0:0]$9695 - attribute \src "libresoc.v:167430.3-167431.33" + attribute \src "libresoc.v:169584.3-169602.6" + wire width 64 $0\fast2$12$next[63:0]$9741 + attribute \src "libresoc.v:169410.3-169411.35" + wire width 64 $0\fast2$12[63:0]$9670 + attribute \src "libresoc.v:168723.14-168723.47" + wire width 64 $0\fast2$12[63:0]$9762 + attribute \src "libresoc.v:169584.3-169602.6" + wire $0\fast2_ok$next[0:0]$9740 + attribute \src "libresoc.v:169412.3-169413.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:166692.7-166692.20" + attribute \src "libresoc.v:168696.7-168696.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167608.3-167626.6" - wire width 64 $0\msr$next[63:0]$9707 - attribute \src "libresoc.v:167420.3-167421.23" + attribute \src "libresoc.v:169622.3-169640.6" + wire width 64 $0\msr$next[63:0]$9752 + attribute \src "libresoc.v:169444.3-169445.23" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:167608.3-167626.6" - wire $0\msr_ok$next[0:0]$9708 - attribute \src "libresoc.v:167422.3-167423.29" + attribute \src "libresoc.v:169622.3-169640.6" + wire $0\msr_ok$next[0:0]$9753 + attribute \src "libresoc.v:169446.3-169447.29" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:167498.3-167510.6" - wire width 2 $0\muxid$1$next[1:0]$9661 - attribute \src "libresoc.v:167416.3-167417.33" - wire width 2 $0\muxid$1[1:0]$9644 - attribute \src "libresoc.v:166993.13-166993.29" - wire width 2 $0\muxid$1[1:0]$9722 - attribute \src "libresoc.v:167589.3-167607.6" - wire width 64 $0\nia$next[63:0]$9701 - attribute \src "libresoc.v:167424.3-167425.23" + attribute \src "libresoc.v:169512.3-169524.6" + wire width 2 $0\muxid$1$next[1:0]$9706 + attribute \src "libresoc.v:169440.3-169441.33" + wire width 2 $0\muxid$1[1:0]$9696 + attribute \src "libresoc.v:169001.13-169001.29" + wire width 2 $0\muxid$1[1:0]$9767 + attribute \src "libresoc.v:169603.3-169621.6" + wire width 64 $0\nia$next[63:0]$9746 + attribute \src "libresoc.v:169448.3-169449.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:167589.3-167607.6" - wire $0\nia_ok$next[0:0]$9702 - attribute \src "libresoc.v:167426.3-167427.29" + attribute \src "libresoc.v:169603.3-169621.6" + wire $0\nia_ok$next[0:0]$9747 + attribute \src "libresoc.v:169408.3-169409.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:167532.3-167550.6" - wire width 64 $0\o$next[63:0]$9683 - attribute \src "libresoc.v:167394.3-167395.19" + attribute \src "libresoc.v:169546.3-169564.6" + wire width 64 $0\o$next[63:0]$9728 + attribute \src "libresoc.v:169418.3-169419.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:167532.3-167550.6" - wire $0\o_ok$next[0:0]$9684 - attribute \src "libresoc.v:167396.3-167397.25" + attribute \src "libresoc.v:169546.3-169564.6" + wire $0\o_ok$next[0:0]$9729 + attribute \src "libresoc.v:169420.3-169421.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:167480.3-167497.6" - wire $0\r_busy$next[0:0]$9657 - attribute \src "libresoc.v:167418.3-167419.29" + attribute \src "libresoc.v:169494.3-169511.6" + wire $0\r_busy$next[0:0]$9702 + attribute \src "libresoc.v:169442.3-169443.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167511.3-167531.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$9664 - attribute \src "libresoc.v:167406.3-167407.47" - wire width 64 $0\trap_op__cia$6[63:0]$9634 - attribute \src "libresoc.v:167054.14-167054.53" - wire width 64 $0\trap_op__cia$6[63:0]$9729 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 13 $0\trap_op__fn_unit$3$next[12:0]$9665 - attribute \src "libresoc.v:167400.3-167401.55" - wire width 13 $0\trap_op__fn_unit$3[12:0]$9628 - attribute \src "libresoc.v:167089.14-167089.45" - wire width 13 $0\trap_op__fn_unit$3[12:0]$9731 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 32 $0\trap_op__insn$4$next[31:0]$9666 - attribute \src "libresoc.v:167402.3-167403.49" - wire width 32 $0\trap_op__insn$4[31:0]$9630 - attribute \src "libresoc.v:167114.14-167114.39" - wire width 32 $0\trap_op__insn$4[31:0]$9733 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 7 $0\trap_op__insn_type$2$next[6:0]$9667 - attribute \src "libresoc.v:167398.3-167399.59" - wire width 7 $0\trap_op__insn_type$2[6:0]$9626 - attribute \src "libresoc.v:167269.13-167269.43" - wire width 7 $0\trap_op__insn_type$2[6:0]$9735 - attribute \src "libresoc.v:167511.3-167531.6" - wire $0\trap_op__is_32bit$7$next[0:0]$9668 - attribute \src "libresoc.v:167408.3-167409.57" - wire $0\trap_op__is_32bit$7[0:0]$9636 - attribute \src "libresoc.v:167354.7-167354.35" - wire $0\trap_op__is_32bit$7[0:0]$9737 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9669 - attribute \src "libresoc.v:167414.3-167415.59" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9642 - attribute \src "libresoc.v:167361.13-167361.43" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9739 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 64 $0\trap_op__msr$5$next[63:0]$9670 - attribute \src "libresoc.v:167404.3-167405.47" - wire width 64 $0\trap_op__msr$5[63:0]$9632 - attribute \src "libresoc.v:167372.14-167372.53" - wire width 64 $0\trap_op__msr$5[63:0]$9741 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9671 - attribute \src "libresoc.v:167412.3-167413.57" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9640 - attribute \src "libresoc.v:167381.14-167381.46" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9743 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 8 $0\trap_op__traptype$8$next[7:0]$9672 - attribute \src "libresoc.v:167410.3-167411.57" - wire width 8 $0\trap_op__traptype$8[7:0]$9638 - attribute \src "libresoc.v:167390.13-167390.42" - wire width 8 $0\trap_op__traptype$8[7:0]$9745 - attribute \src "libresoc.v:167551.3-167569.6" - wire width 64 $1\fast1$11$next[63:0]$9692 - attribute \src "libresoc.v:167551.3-167569.6" - wire $1\fast1_ok$next[0:0]$9691 - attribute \src "libresoc.v:166710.7-166710.22" + attribute \src "libresoc.v:169525.3-169545.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$9709 + attribute \src "libresoc.v:169430.3-169431.47" + wire width 64 $0\trap_op__cia$6[63:0]$9686 + attribute \src "libresoc.v:169062.14-169062.53" + wire width 64 $0\trap_op__cia$6[63:0]$9774 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9710 + attribute \src "libresoc.v:169424.3-169425.55" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9680 + attribute \src "libresoc.v:169099.14-169099.45" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9776 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$9711 + attribute \src "libresoc.v:169426.3-169427.49" + wire width 32 $0\trap_op__insn$4[31:0]$9682 + attribute \src "libresoc.v:169125.14-169125.39" + wire width 32 $0\trap_op__insn$4[31:0]$9778 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$9712 + attribute \src "libresoc.v:169422.3-169423.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$9678 + attribute \src "libresoc.v:169282.13-169282.43" + wire width 7 $0\trap_op__insn_type$2[6:0]$9780 + attribute \src "libresoc.v:169525.3-169545.6" + wire $0\trap_op__is_32bit$7$next[0:0]$9713 + attribute \src "libresoc.v:169432.3-169433.57" + wire $0\trap_op__is_32bit$7[0:0]$9688 + attribute \src "libresoc.v:169368.7-169368.35" + wire $0\trap_op__is_32bit$7[0:0]$9782 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9714 + attribute \src "libresoc.v:169438.3-169439.59" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9694 + attribute \src "libresoc.v:169375.13-169375.43" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9784 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 64 $0\trap_op__msr$5$next[63:0]$9715 + attribute \src "libresoc.v:169428.3-169429.47" + wire width 64 $0\trap_op__msr$5[63:0]$9684 + attribute \src "libresoc.v:169386.14-169386.53" + wire width 64 $0\trap_op__msr$5[63:0]$9786 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9716 + attribute \src "libresoc.v:169436.3-169437.57" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9692 + attribute \src "libresoc.v:169395.14-169395.46" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9788 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 8 $0\trap_op__traptype$8$next[7:0]$9717 + attribute \src "libresoc.v:169434.3-169435.57" + wire width 8 $0\trap_op__traptype$8[7:0]$9690 + attribute \src "libresoc.v:169404.13-169404.42" + wire width 8 $0\trap_op__traptype$8[7:0]$9790 + attribute \src "libresoc.v:169565.3-169583.6" + wire width 64 $1\fast1$11$next[63:0]$9737 + attribute \src "libresoc.v:169565.3-169583.6" + wire $1\fast1_ok$next[0:0]$9736 + attribute \src "libresoc.v:168714.7-168714.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:167570.3-167588.6" - wire width 64 $1\fast2$12$next[63:0]$9698 - attribute \src "libresoc.v:167570.3-167588.6" - wire $1\fast2_ok$next[0:0]$9697 - attribute \src "libresoc.v:166726.7-166726.22" + attribute \src "libresoc.v:169584.3-169602.6" + wire width 64 $1\fast2$12$next[63:0]$9743 + attribute \src "libresoc.v:169584.3-169602.6" + wire $1\fast2_ok$next[0:0]$9742 + attribute \src "libresoc.v:168730.7-168730.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:167608.3-167626.6" - wire width 64 $1\msr$next[63:0]$9709 - attribute \src "libresoc.v:166977.14-166977.40" + attribute \src "libresoc.v:169622.3-169640.6" + wire width 64 $1\msr$next[63:0]$9754 + attribute \src "libresoc.v:168985.14-168985.40" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:167608.3-167626.6" - wire $1\msr_ok$next[0:0]$9710 - attribute \src "libresoc.v:166984.7-166984.20" + attribute \src "libresoc.v:169622.3-169640.6" + wire $1\msr_ok$next[0:0]$9755 + attribute \src "libresoc.v:168992.7-168992.20" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:167498.3-167510.6" - wire width 2 $1\muxid$1$next[1:0]$9662 - attribute \src "libresoc.v:167589.3-167607.6" - wire width 64 $1\nia$next[63:0]$9703 - attribute \src "libresoc.v:167006.14-167006.40" + attribute \src "libresoc.v:169512.3-169524.6" + wire width 2 $1\muxid$1$next[1:0]$9707 + attribute \src "libresoc.v:169603.3-169621.6" + wire width 64 $1\nia$next[63:0]$9748 + attribute \src "libresoc.v:169014.14-169014.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:167589.3-167607.6" - wire $1\nia_ok$next[0:0]$9704 - attribute \src "libresoc.v:167013.7-167013.20" + attribute \src "libresoc.v:169603.3-169621.6" + wire $1\nia_ok$next[0:0]$9749 + attribute \src "libresoc.v:169021.7-169021.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:167532.3-167550.6" - wire width 64 $1\o$next[63:0]$9685 - attribute \src "libresoc.v:167020.14-167020.38" + attribute \src "libresoc.v:169546.3-169564.6" + wire width 64 $1\o$next[63:0]$9730 + attribute \src "libresoc.v:169028.14-169028.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:167532.3-167550.6" - wire $1\o_ok$next[0:0]$9686 - attribute \src "libresoc.v:167027.7-167027.18" + attribute \src "libresoc.v:169546.3-169564.6" + wire $1\o_ok$next[0:0]$9731 + attribute \src "libresoc.v:169035.7-169035.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:167480.3-167497.6" - wire $1\r_busy$next[0:0]$9658 - attribute \src "libresoc.v:167041.7-167041.20" + attribute \src "libresoc.v:169494.3-169511.6" + wire $1\r_busy$next[0:0]$9703 + attribute \src "libresoc.v:169049.7-169049.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167511.3-167531.6" - wire width 64 $1\trap_op__cia$6$next[63:0]$9673 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 13 $1\trap_op__fn_unit$3$next[12:0]$9674 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 32 $1\trap_op__insn$4$next[31:0]$9675 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 7 $1\trap_op__insn_type$2$next[6:0]$9676 - attribute \src "libresoc.v:167511.3-167531.6" - wire $1\trap_op__is_32bit$7$next[0:0]$9677 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9678 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 64 $1\trap_op__msr$5$next[63:0]$9679 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9680 - attribute \src "libresoc.v:167511.3-167531.6" - wire width 8 $1\trap_op__traptype$8$next[7:0]$9681 - attribute \src "libresoc.v:167551.3-167569.6" - wire $2\fast1_ok$next[0:0]$9693 - attribute \src "libresoc.v:167570.3-167588.6" - wire $2\fast2_ok$next[0:0]$9699 - attribute \src "libresoc.v:167608.3-167626.6" - wire $2\msr_ok$next[0:0]$9711 - attribute \src "libresoc.v:167589.3-167607.6" - wire $2\nia_ok$next[0:0]$9705 - attribute \src "libresoc.v:167532.3-167550.6" - wire $2\o_ok$next[0:0]$9687 - attribute \src "libresoc.v:167480.3-167497.6" - wire $2\r_busy$next[0:0]$9659 - attribute \src "libresoc.v:167393.18-167393.118" - wire $and$libresoc.v:167393$9622_Y + attribute \src "libresoc.v:169525.3-169545.6" + wire width 64 $1\trap_op__cia$6$next[63:0]$9718 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9719 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 32 $1\trap_op__insn$4$next[31:0]$9720 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 7 $1\trap_op__insn_type$2$next[6:0]$9721 + attribute \src "libresoc.v:169525.3-169545.6" + wire $1\trap_op__is_32bit$7$next[0:0]$9722 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9723 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 64 $1\trap_op__msr$5$next[63:0]$9724 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9725 + attribute \src "libresoc.v:169525.3-169545.6" + wire width 8 $1\trap_op__traptype$8$next[7:0]$9726 + attribute \src "libresoc.v:169565.3-169583.6" + wire $2\fast1_ok$next[0:0]$9738 + attribute \src "libresoc.v:169584.3-169602.6" + wire $2\fast2_ok$next[0:0]$9744 + attribute \src "libresoc.v:169622.3-169640.6" + wire $2\msr_ok$next[0:0]$9756 + attribute \src "libresoc.v:169603.3-169621.6" + wire $2\nia_ok$next[0:0]$9750 + attribute \src "libresoc.v:169546.3-169564.6" + wire $2\o_ok$next[0:0]$9732 + attribute \src "libresoc.v:169494.3-169511.6" + wire $2\r_busy$next[0:0]$9704 + attribute \src "libresoc.v:169407.18-169407.118" + wire $and$libresoc.v:169407$9667_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 16 \fast1 @@ -345189,7 +347888,7 @@ module \pipe2$35 wire \fast2_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:166692.7-166692.15" + attribute \src "libresoc.v:168696.7-168696.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 @@ -345228,37 +347927,39 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_trap_op__cia$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__fn_unit$15 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \main_trap_op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -345337,6 +348038,7 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -345413,6 +348115,7 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_trap_op__insn_type$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -345510,55 +348213,58 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__cia$6$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \trap_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \trap_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 22 \trap_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 22 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$30 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \trap_op__fn_unit$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -345641,6 +348347,7 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" @@ -345717,6 +348424,7 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 21 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -345795,6 +348503,7 @@ module \pipe2$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -345838,7 +348547,7 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:167393$9622 + cell $and $and$libresoc.v:169407$9667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345846,10 +348555,10 @@ module \pipe2$35 parameter \Y_WIDTH 1 connect \A \p_valid_i$25 connect \B \p_ready_o - connect \Y $and$libresoc.v:167393$9622_Y + connect \Y $and$libresoc.v:169407$9667_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:167436.13-167471.4" + attribute \src "libresoc.v:169450.13-169485.4" cell \main$38 \main connect \fast1 \main_fast1 connect \fast1$11 \main_fast1$23 @@ -345887,349 +348596,349 @@ module \pipe2$35 connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167472.10-167475.4" + attribute \src "libresoc.v:169486.10-169489.4" cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167476.10-167479.4" + attribute \src "libresoc.v:169490.10-169493.4" cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:166692.7-166692.20" - process $proc$libresoc.v:166692$9712 + attribute \src "libresoc.v:168696.7-168696.20" + process $proc$libresoc.v:168696$9757 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166703.14-166703.47" - process $proc$libresoc.v:166703$9713 + attribute \src "libresoc.v:168707.14-168707.47" + process $proc$libresoc.v:168707$9758 assign { } { } - assign $0\fast1$11[63:0]$9714 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$11[63:0]$9759 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$11 $0\fast1$11[63:0]$9714 + update \fast1$11 $0\fast1$11[63:0]$9759 end - attribute \src "libresoc.v:166710.7-166710.22" - process $proc$libresoc.v:166710$9715 + attribute \src "libresoc.v:168714.7-168714.22" + process $proc$libresoc.v:168714$9760 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:166719.14-166719.47" - process $proc$libresoc.v:166719$9716 + attribute \src "libresoc.v:168723.14-168723.47" + process $proc$libresoc.v:168723$9761 assign { } { } - assign $0\fast2$12[63:0]$9717 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$12[63:0]$9762 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$12 $0\fast2$12[63:0]$9717 + update \fast2$12 $0\fast2$12[63:0]$9762 end - attribute \src "libresoc.v:166726.7-166726.22" - process $proc$libresoc.v:166726$9718 + attribute \src "libresoc.v:168730.7-168730.22" + process $proc$libresoc.v:168730$9763 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:166977.14-166977.40" - process $proc$libresoc.v:166977$9719 + attribute \src "libresoc.v:168985.14-168985.40" + process $proc$libresoc.v:168985$9764 assign { } { } assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr $1\msr[63:0] end - attribute \src "libresoc.v:166984.7-166984.20" - process $proc$libresoc.v:166984$9720 + attribute \src "libresoc.v:168992.7-168992.20" + process $proc$libresoc.v:168992$9765 assign { } { } assign $1\msr_ok[0:0] 1'0 sync always sync init update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:166993.13-166993.29" - process $proc$libresoc.v:166993$9721 + attribute \src "libresoc.v:169001.13-169001.29" + process $proc$libresoc.v:169001$9766 assign { } { } - assign $0\muxid$1[1:0]$9722 2'00 + assign $0\muxid$1[1:0]$9767 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9722 + update \muxid$1 $0\muxid$1[1:0]$9767 end - attribute \src "libresoc.v:167006.14-167006.40" - process $proc$libresoc.v:167006$9723 + attribute \src "libresoc.v:169014.14-169014.40" + process $proc$libresoc.v:169014$9768 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:167013.7-167013.20" - process $proc$libresoc.v:167013$9724 + attribute \src "libresoc.v:169021.7-169021.20" + process $proc$libresoc.v:169021$9769 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:167020.14-167020.38" - process $proc$libresoc.v:167020$9725 + attribute \src "libresoc.v:169028.14-169028.38" + process $proc$libresoc.v:169028$9770 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:167027.7-167027.18" - process $proc$libresoc.v:167027$9726 + attribute \src "libresoc.v:169035.7-169035.18" + process $proc$libresoc.v:169035$9771 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:167041.7-167041.20" - process $proc$libresoc.v:167041$9727 + attribute \src "libresoc.v:169049.7-169049.20" + process $proc$libresoc.v:169049$9772 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:167054.14-167054.53" - process $proc$libresoc.v:167054$9728 + attribute \src "libresoc.v:169062.14-169062.53" + process $proc$libresoc.v:169062$9773 assign { } { } - assign $0\trap_op__cia$6[63:0]$9729 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__cia$6[63:0]$9774 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9729 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9774 end - attribute \src "libresoc.v:167089.14-167089.45" - process $proc$libresoc.v:167089$9730 + attribute \src "libresoc.v:169099.14-169099.45" + process $proc$libresoc.v:169099$9775 assign { } { } - assign $0\trap_op__fn_unit$3[12:0]$9731 13'0000000000000 + assign $0\trap_op__fn_unit$3[13:0]$9776 14'00000000000000 sync always sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9731 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9776 end - attribute \src "libresoc.v:167114.14-167114.39" - process $proc$libresoc.v:167114$9732 + attribute \src "libresoc.v:169125.14-169125.39" + process $proc$libresoc.v:169125$9777 assign { } { } - assign $0\trap_op__insn$4[31:0]$9733 0 + assign $0\trap_op__insn$4[31:0]$9778 0 sync always sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9733 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9778 end - attribute \src "libresoc.v:167269.13-167269.43" - process $proc$libresoc.v:167269$9734 + attribute \src "libresoc.v:169282.13-169282.43" + process $proc$libresoc.v:169282$9779 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9735 7'0000000 + assign $0\trap_op__insn_type$2[6:0]$9780 7'0000000 sync always sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9735 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9780 end - attribute \src "libresoc.v:167354.7-167354.35" - process $proc$libresoc.v:167354$9736 + attribute \src "libresoc.v:169368.7-169368.35" + process $proc$libresoc.v:169368$9781 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9737 1'0 + assign $0\trap_op__is_32bit$7[0:0]$9782 1'0 sync always sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9737 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9782 end - attribute \src "libresoc.v:167361.13-167361.43" - process $proc$libresoc.v:167361$9738 + attribute \src "libresoc.v:169375.13-169375.43" + process $proc$libresoc.v:169375$9783 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9739 8'00000000 + assign $0\trap_op__ldst_exc$10[7:0]$9784 8'00000000 sync always sync init - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9739 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9784 end - attribute \src "libresoc.v:167372.14-167372.53" - process $proc$libresoc.v:167372$9740 + attribute \src "libresoc.v:169386.14-169386.53" + process $proc$libresoc.v:169386$9785 assign { } { } - assign $0\trap_op__msr$5[63:0]$9741 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__msr$5[63:0]$9786 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9741 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9786 end - attribute \src "libresoc.v:167381.14-167381.46" - process $proc$libresoc.v:167381$9742 + attribute \src "libresoc.v:169395.14-169395.46" + process $proc$libresoc.v:169395$9787 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9743 13'0000000000000 + assign $0\trap_op__trapaddr$9[12:0]$9788 13'0000000000000 sync always sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9743 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9788 end - attribute \src "libresoc.v:167390.13-167390.42" - process $proc$libresoc.v:167390$9744 + attribute \src "libresoc.v:169404.13-169404.42" + process $proc$libresoc.v:169404$9789 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9745 8'00000000 + assign $0\trap_op__traptype$8[7:0]$9790 8'00000000 sync always sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9745 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9790 end - attribute \src "libresoc.v:167394.3-167395.19" - process $proc$libresoc.v:167394$9623 + attribute \src "libresoc.v:169408.3-169409.29" + process $proc$libresoc.v:169408$9668 assign { } { } - assign $0\o[63:0] \o$next + assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:167396.3-167397.25" - process $proc$libresoc.v:167396$9624 + attribute \src "libresoc.v:169410.3-169411.35" + process $proc$libresoc.v:169410$9669 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\fast2$12[63:0]$9670 \fast2$12$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \fast2$12 $0\fast2$12[63:0]$9670 end - attribute \src "libresoc.v:167398.3-167399.59" - process $proc$libresoc.v:167398$9625 + attribute \src "libresoc.v:169412.3-169413.33" + process $proc$libresoc.v:169412$9671 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9626 \trap_op__insn_type$2$next + assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9626 + update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:167400.3-167401.55" - process $proc$libresoc.v:167400$9627 + attribute \src "libresoc.v:169414.3-169415.35" + process $proc$libresoc.v:169414$9672 assign { } { } - assign $0\trap_op__fn_unit$3[12:0]$9628 \trap_op__fn_unit$3$next + assign $0\fast1$11[63:0]$9673 \fast1$11$next sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9628 + update \fast1$11 $0\fast1$11[63:0]$9673 end - attribute \src "libresoc.v:167402.3-167403.49" - process $proc$libresoc.v:167402$9629 + attribute \src "libresoc.v:169416.3-169417.33" + process $proc$libresoc.v:169416$9674 assign { } { } - assign $0\trap_op__insn$4[31:0]$9630 \trap_op__insn$4$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9630 + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:167404.3-167405.47" - process $proc$libresoc.v:167404$9631 + attribute \src "libresoc.v:169418.3-169419.19" + process $proc$libresoc.v:169418$9675 assign { } { } - assign $0\trap_op__msr$5[63:0]$9632 \trap_op__msr$5$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9632 + update \o $0\o[63:0] end - attribute \src "libresoc.v:167406.3-167407.47" - process $proc$libresoc.v:167406$9633 + attribute \src "libresoc.v:169420.3-169421.25" + process $proc$libresoc.v:169420$9676 assign { } { } - assign $0\trap_op__cia$6[63:0]$9634 \trap_op__cia$6$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9634 + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:167408.3-167409.57" - process $proc$libresoc.v:167408$9635 + attribute \src "libresoc.v:169422.3-169423.59" + process $proc$libresoc.v:169422$9677 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9636 \trap_op__is_32bit$7$next + assign $0\trap_op__insn_type$2[6:0]$9678 \trap_op__insn_type$2$next sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9636 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9678 end - attribute \src "libresoc.v:167410.3-167411.57" - process $proc$libresoc.v:167410$9637 + attribute \src "libresoc.v:169424.3-169425.55" + process $proc$libresoc.v:169424$9679 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9638 \trap_op__traptype$8$next + assign $0\trap_op__fn_unit$3[13:0]$9680 \trap_op__fn_unit$3$next sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9638 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9680 end - attribute \src "libresoc.v:167412.3-167413.57" - process $proc$libresoc.v:167412$9639 + attribute \src "libresoc.v:169426.3-169427.49" + process $proc$libresoc.v:169426$9681 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9640 \trap_op__trapaddr$9$next + assign $0\trap_op__insn$4[31:0]$9682 \trap_op__insn$4$next sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9640 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9682 end - attribute \src "libresoc.v:167414.3-167415.59" - process $proc$libresoc.v:167414$9641 + attribute \src "libresoc.v:169428.3-169429.47" + process $proc$libresoc.v:169428$9683 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9642 \trap_op__ldst_exc$10$next + assign $0\trap_op__msr$5[63:0]$9684 \trap_op__msr$5$next sync posedge \coresync_clk - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9642 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9684 end - attribute \src "libresoc.v:167416.3-167417.33" - process $proc$libresoc.v:167416$9643 + attribute \src "libresoc.v:169430.3-169431.47" + process $proc$libresoc.v:169430$9685 assign { } { } - assign $0\muxid$1[1:0]$9644 \muxid$1$next + assign $0\trap_op__cia$6[63:0]$9686 \trap_op__cia$6$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9644 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9686 end - attribute \src "libresoc.v:167418.3-167419.29" - process $proc$libresoc.v:167418$9645 + attribute \src "libresoc.v:169432.3-169433.57" + process $proc$libresoc.v:169432$9687 assign { } { } - assign $0\r_busy[0:0] \r_busy$next + assign $0\trap_op__is_32bit$7[0:0]$9688 \trap_op__is_32bit$7$next sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9688 end - attribute \src "libresoc.v:167420.3-167421.23" - process $proc$libresoc.v:167420$9646 + attribute \src "libresoc.v:169434.3-169435.57" + process $proc$libresoc.v:169434$9689 assign { } { } - assign $0\msr[63:0] \msr$next + assign $0\trap_op__traptype$8[7:0]$9690 \trap_op__traptype$8$next sync posedge \coresync_clk - update \msr $0\msr[63:0] + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9690 end - attribute \src "libresoc.v:167422.3-167423.29" - process $proc$libresoc.v:167422$9647 + attribute \src "libresoc.v:169436.3-169437.57" + process $proc$libresoc.v:169436$9691 assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next + assign $0\trap_op__trapaddr$9[12:0]$9692 \trap_op__trapaddr$9$next sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9692 end - attribute \src "libresoc.v:167424.3-167425.23" - process $proc$libresoc.v:167424$9648 + attribute \src "libresoc.v:169438.3-169439.59" + process $proc$libresoc.v:169438$9693 assign { } { } - assign $0\nia[63:0] \nia$next + assign $0\trap_op__ldst_exc$10[7:0]$9694 \trap_op__ldst_exc$10$next sync posedge \coresync_clk - update \nia $0\nia[63:0] + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9694 end - attribute \src "libresoc.v:167426.3-167427.29" - process $proc$libresoc.v:167426$9649 + attribute \src "libresoc.v:169440.3-169441.33" + process $proc$libresoc.v:169440$9695 assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next + assign $0\muxid$1[1:0]$9696 \muxid$1$next sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] + update \muxid$1 $0\muxid$1[1:0]$9696 end - attribute \src "libresoc.v:167428.3-167429.35" - process $proc$libresoc.v:167428$9650 + attribute \src "libresoc.v:169442.3-169443.29" + process $proc$libresoc.v:169442$9697 assign { } { } - assign $0\fast2$12[63:0]$9651 \fast2$12$next + assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk - update \fast2$12 $0\fast2$12[63:0]$9651 + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167430.3-167431.33" - process $proc$libresoc.v:167430$9652 + attribute \src "libresoc.v:169444.3-169445.23" + process $proc$libresoc.v:169444$9698 assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next + assign $0\msr[63:0] \msr$next sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] + update \msr $0\msr[63:0] end - attribute \src "libresoc.v:167432.3-167433.35" - process $proc$libresoc.v:167432$9653 + attribute \src "libresoc.v:169446.3-169447.29" + process $proc$libresoc.v:169446$9699 assign { } { } - assign $0\fast1$11[63:0]$9654 \fast1$11$next + assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk - update \fast1$11 $0\fast1$11[63:0]$9654 + update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:167434.3-167435.33" - process $proc$libresoc.v:167434$9655 + attribute \src "libresoc.v:169448.3-169449.23" + process $proc$libresoc.v:169448$9700 assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next + assign $0\nia[63:0] \nia$next sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:167480.3-167497.6" - process $proc$libresoc.v:167480$9656 + attribute \src "libresoc.v:169494.3-169511.6" + process $proc$libresoc.v:169494$9701 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9657 $2\r_busy$next[0:0]$9659 - attribute \src "libresoc.v:167481.5-167481.29" + assign $0\r_busy$next[0:0]$9702 $2\r_busy$next[0:0]$9704 + attribute \src "libresoc.v:169495.5-169495.29" switch \initial - attribute \src "libresoc.v:167481.9-167481.17" + attribute \src "libresoc.v:169495.9-169495.17" case 1'1 case end @@ -346238,34 +348947,34 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9658 1'1 + assign $1\r_busy$next[0:0]$9703 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9658 1'0 + assign $1\r_busy$next[0:0]$9703 1'0 case - assign $1\r_busy$next[0:0]$9658 \r_busy + assign $1\r_busy$next[0:0]$9703 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9659 1'0 + assign $2\r_busy$next[0:0]$9704 1'0 case - assign $2\r_busy$next[0:0]$9659 $1\r_busy$next[0:0]$9658 + assign $2\r_busy$next[0:0]$9704 $1\r_busy$next[0:0]$9703 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9657 + update \r_busy$next $0\r_busy$next[0:0]$9702 end - attribute \src "libresoc.v:167498.3-167510.6" - process $proc$libresoc.v:167498$9660 + attribute \src "libresoc.v:169512.3-169524.6" + process $proc$libresoc.v:169512$9705 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9661 $1\muxid$1$next[1:0]$9662 - attribute \src "libresoc.v:167499.5-167499.29" + assign $0\muxid$1$next[1:0]$9706 $1\muxid$1$next[1:0]$9707 + attribute \src "libresoc.v:169513.5-169513.29" switch \initial - attribute \src "libresoc.v:167499.9-167499.17" + attribute \src "libresoc.v:169513.9-169513.17" case 1'1 case end @@ -346274,19 +348983,19 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9662 \muxid$28 + assign $1\muxid$1$next[1:0]$9707 \muxid$28 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9662 \muxid$28 + assign $1\muxid$1$next[1:0]$9707 \muxid$28 case - assign $1\muxid$1$next[1:0]$9662 \muxid$1 + assign $1\muxid$1$next[1:0]$9707 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9661 + update \muxid$1$next $0\muxid$1$next[1:0]$9706 end - attribute \src "libresoc.v:167511.3-167531.6" - process $proc$libresoc.v:167511$9663 + attribute \src "libresoc.v:169525.3-169545.6" + process $proc$libresoc.v:169525$9708 assign { } { } assign { } { } assign { } { } @@ -346305,18 +349014,18 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$6$next[63:0]$9664 $1\trap_op__cia$6$next[63:0]$9673 - assign $0\trap_op__fn_unit$3$next[12:0]$9665 $1\trap_op__fn_unit$3$next[12:0]$9674 - assign $0\trap_op__insn$4$next[31:0]$9666 $1\trap_op__insn$4$next[31:0]$9675 - assign $0\trap_op__insn_type$2$next[6:0]$9667 $1\trap_op__insn_type$2$next[6:0]$9676 - assign $0\trap_op__is_32bit$7$next[0:0]$9668 $1\trap_op__is_32bit$7$next[0:0]$9677 - assign $0\trap_op__ldst_exc$10$next[7:0]$9669 $1\trap_op__ldst_exc$10$next[7:0]$9678 - assign $0\trap_op__msr$5$next[63:0]$9670 $1\trap_op__msr$5$next[63:0]$9679 - assign $0\trap_op__trapaddr$9$next[12:0]$9671 $1\trap_op__trapaddr$9$next[12:0]$9680 - assign $0\trap_op__traptype$8$next[7:0]$9672 $1\trap_op__traptype$8$next[7:0]$9681 - attribute \src "libresoc.v:167512.5-167512.29" + assign $0\trap_op__cia$6$next[63:0]$9709 $1\trap_op__cia$6$next[63:0]$9718 + assign $0\trap_op__fn_unit$3$next[13:0]$9710 $1\trap_op__fn_unit$3$next[13:0]$9719 + assign $0\trap_op__insn$4$next[31:0]$9711 $1\trap_op__insn$4$next[31:0]$9720 + assign $0\trap_op__insn_type$2$next[6:0]$9712 $1\trap_op__insn_type$2$next[6:0]$9721 + assign $0\trap_op__is_32bit$7$next[0:0]$9713 $1\trap_op__is_32bit$7$next[0:0]$9722 + assign $0\trap_op__ldst_exc$10$next[7:0]$9714 $1\trap_op__ldst_exc$10$next[7:0]$9723 + assign $0\trap_op__msr$5$next[63:0]$9715 $1\trap_op__msr$5$next[63:0]$9724 + assign $0\trap_op__trapaddr$9$next[12:0]$9716 $1\trap_op__trapaddr$9$next[12:0]$9725 + assign $0\trap_op__traptype$8$next[7:0]$9717 $1\trap_op__traptype$8$next[7:0]$9726 + attribute \src "libresoc.v:169526.5-169526.29" switch \initial - attribute \src "libresoc.v:167512.9-167512.17" + attribute \src "libresoc.v:169526.9-169526.17" case 1'1 case end @@ -346333,7 +349042,7 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9678 $1\trap_op__trapaddr$9$next[12:0]$9680 $1\trap_op__traptype$8$next[7:0]$9681 $1\trap_op__is_32bit$7$next[0:0]$9677 $1\trap_op__cia$6$next[63:0]$9673 $1\trap_op__msr$5$next[63:0]$9679 $1\trap_op__insn$4$next[31:0]$9675 $1\trap_op__fn_unit$3$next[12:0]$9674 $1\trap_op__insn_type$2$next[6:0]$9676 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9723 $1\trap_op__trapaddr$9$next[12:0]$9725 $1\trap_op__traptype$8$next[7:0]$9726 $1\trap_op__is_32bit$7$next[0:0]$9722 $1\trap_op__cia$6$next[63:0]$9718 $1\trap_op__msr$5$next[63:0]$9724 $1\trap_op__insn$4$next[31:0]$9720 $1\trap_op__fn_unit$3$next[13:0]$9719 $1\trap_op__insn_type$2$next[6:0]$9721 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -346345,41 +349054,41 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9678 $1\trap_op__trapaddr$9$next[12:0]$9680 $1\trap_op__traptype$8$next[7:0]$9681 $1\trap_op__is_32bit$7$next[0:0]$9677 $1\trap_op__cia$6$next[63:0]$9673 $1\trap_op__msr$5$next[63:0]$9679 $1\trap_op__insn$4$next[31:0]$9675 $1\trap_op__fn_unit$3$next[12:0]$9674 $1\trap_op__insn_type$2$next[6:0]$9676 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9723 $1\trap_op__trapaddr$9$next[12:0]$9725 $1\trap_op__traptype$8$next[7:0]$9726 $1\trap_op__is_32bit$7$next[0:0]$9722 $1\trap_op__cia$6$next[63:0]$9718 $1\trap_op__msr$5$next[63:0]$9724 $1\trap_op__insn$4$next[31:0]$9720 $1\trap_op__fn_unit$3$next[13:0]$9719 $1\trap_op__insn_type$2$next[6:0]$9721 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } case - assign $1\trap_op__cia$6$next[63:0]$9673 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[12:0]$9674 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$9675 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$9676 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$9677 \trap_op__is_32bit$7 - assign $1\trap_op__ldst_exc$10$next[7:0]$9678 \trap_op__ldst_exc$10 - assign $1\trap_op__msr$5$next[63:0]$9679 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$9680 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[7:0]$9681 \trap_op__traptype$8 + assign $1\trap_op__cia$6$next[63:0]$9718 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[13:0]$9719 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9720 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9721 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9722 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9723 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9724 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9725 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9726 \trap_op__traptype$8 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9664 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[12:0]$9665 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9666 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9667 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9668 - update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9669 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9670 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9671 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9672 + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9709 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9710 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9711 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9712 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9713 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9714 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9715 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9716 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9717 end - attribute \src "libresoc.v:167532.3-167550.6" - process $proc$libresoc.v:167532$9682 + attribute \src "libresoc.v:169546.3-169564.6" + process $proc$libresoc.v:169546$9727 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9683 $1\o$next[63:0]$9685 + assign $0\o$next[63:0]$9728 $1\o$next[63:0]$9730 assign { } { } - assign $0\o_ok$next[0:0]$9684 $2\o_ok$next[0:0]$9687 - attribute \src "libresoc.v:167533.5-167533.29" + assign $0\o_ok$next[0:0]$9729 $2\o_ok$next[0:0]$9732 + attribute \src "libresoc.v:169547.5-169547.29" switch \initial - attribute \src "libresoc.v:167533.9-167533.17" + attribute \src "libresoc.v:169547.9-169547.17" case 1'1 case end @@ -346389,41 +349098,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9686 $1\o$next[63:0]$9685 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9731 $1\o$next[63:0]$9730 } { \o_ok$39 \o$38 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9686 $1\o$next[63:0]$9685 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9731 $1\o$next[63:0]$9730 } { \o_ok$39 \o$38 } case - assign $1\o$next[63:0]$9685 \o - assign $1\o_ok$next[0:0]$9686 \o_ok + assign $1\o$next[63:0]$9730 \o + assign $1\o_ok$next[0:0]$9731 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9687 1'0 + assign $2\o_ok$next[0:0]$9732 1'0 case - assign $2\o_ok$next[0:0]$9687 $1\o_ok$next[0:0]$9686 + assign $2\o_ok$next[0:0]$9732 $1\o_ok$next[0:0]$9731 end sync always - update \o$next $0\o$next[63:0]$9683 - update \o_ok$next $0\o_ok$next[0:0]$9684 + update \o$next $0\o$next[63:0]$9728 + update \o_ok$next $0\o_ok$next[0:0]$9729 end - attribute \src "libresoc.v:167551.3-167569.6" - process $proc$libresoc.v:167551$9688 + attribute \src "libresoc.v:169565.3-169583.6" + process $proc$libresoc.v:169565$9733 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$11$next[63:0]$9690 $1\fast1$11$next[63:0]$9692 - assign $0\fast1_ok$next[0:0]$9689 $2\fast1_ok$next[0:0]$9693 - attribute \src "libresoc.v:167552.5-167552.29" + assign $0\fast1$11$next[63:0]$9735 $1\fast1$11$next[63:0]$9737 + assign $0\fast1_ok$next[0:0]$9734 $2\fast1_ok$next[0:0]$9738 + attribute \src "libresoc.v:169566.5-169566.29" switch \initial - attribute \src "libresoc.v:167552.9-167552.17" + attribute \src "libresoc.v:169566.9-169566.17" case 1'1 case end @@ -346433,41 +349142,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9691 $1\fast1$11$next[63:0]$9692 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9736 $1\fast1$11$next[63:0]$9737 } { \fast1_ok$41 \fast1$40 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9691 $1\fast1$11$next[63:0]$9692 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9736 $1\fast1$11$next[63:0]$9737 } { \fast1_ok$41 \fast1$40 } case - assign $1\fast1_ok$next[0:0]$9691 \fast1_ok - assign $1\fast1$11$next[63:0]$9692 \fast1$11 + assign $1\fast1_ok$next[0:0]$9736 \fast1_ok + assign $1\fast1$11$next[63:0]$9737 \fast1$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$9693 1'0 + assign $2\fast1_ok$next[0:0]$9738 1'0 case - assign $2\fast1_ok$next[0:0]$9693 $1\fast1_ok$next[0:0]$9691 + assign $2\fast1_ok$next[0:0]$9738 $1\fast1_ok$next[0:0]$9736 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$9689 - update \fast1$11$next $0\fast1$11$next[63:0]$9690 + update \fast1_ok$next $0\fast1_ok$next[0:0]$9734 + update \fast1$11$next $0\fast1$11$next[63:0]$9735 end - attribute \src "libresoc.v:167570.3-167588.6" - process $proc$libresoc.v:167570$9694 + attribute \src "libresoc.v:169584.3-169602.6" + process $proc$libresoc.v:169584$9739 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$12$next[63:0]$9696 $1\fast2$12$next[63:0]$9698 - assign $0\fast2_ok$next[0:0]$9695 $2\fast2_ok$next[0:0]$9699 - attribute \src "libresoc.v:167571.5-167571.29" + assign $0\fast2$12$next[63:0]$9741 $1\fast2$12$next[63:0]$9743 + assign $0\fast2_ok$next[0:0]$9740 $2\fast2_ok$next[0:0]$9744 + attribute \src "libresoc.v:169585.5-169585.29" switch \initial - attribute \src "libresoc.v:167571.9-167571.17" + attribute \src "libresoc.v:169585.9-169585.17" case 1'1 case end @@ -346477,41 +349186,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9697 $1\fast2$12$next[63:0]$9698 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9742 $1\fast2$12$next[63:0]$9743 } { \fast2_ok$43 \fast2$42 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9697 $1\fast2$12$next[63:0]$9698 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9742 $1\fast2$12$next[63:0]$9743 } { \fast2_ok$43 \fast2$42 } case - assign $1\fast2_ok$next[0:0]$9697 \fast2_ok - assign $1\fast2$12$next[63:0]$9698 \fast2$12 + assign $1\fast2_ok$next[0:0]$9742 \fast2_ok + assign $1\fast2$12$next[63:0]$9743 \fast2$12 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$9699 1'0 + assign $2\fast2_ok$next[0:0]$9744 1'0 case - assign $2\fast2_ok$next[0:0]$9699 $1\fast2_ok$next[0:0]$9697 + assign $2\fast2_ok$next[0:0]$9744 $1\fast2_ok$next[0:0]$9742 end sync always - update \fast2_ok$next $0\fast2_ok$next[0:0]$9695 - update \fast2$12$next $0\fast2$12$next[63:0]$9696 + update \fast2_ok$next $0\fast2_ok$next[0:0]$9740 + update \fast2$12$next $0\fast2$12$next[63:0]$9741 end - attribute \src "libresoc.v:167589.3-167607.6" - process $proc$libresoc.v:167589$9700 + attribute \src "libresoc.v:169603.3-169621.6" + process $proc$libresoc.v:169603$9745 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$9701 $1\nia$next[63:0]$9703 + assign $0\nia$next[63:0]$9746 $1\nia$next[63:0]$9748 assign { } { } - assign $0\nia_ok$next[0:0]$9702 $2\nia_ok$next[0:0]$9705 - attribute \src "libresoc.v:167590.5-167590.29" + assign $0\nia_ok$next[0:0]$9747 $2\nia_ok$next[0:0]$9750 + attribute \src "libresoc.v:169604.5-169604.29" switch \initial - attribute \src "libresoc.v:167590.9-167590.17" + attribute \src "libresoc.v:169604.9-169604.17" case 1'1 case end @@ -346521,41 +349230,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9704 $1\nia$next[63:0]$9703 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9749 $1\nia$next[63:0]$9748 } { \nia_ok$45 \nia$44 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9704 $1\nia$next[63:0]$9703 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9749 $1\nia$next[63:0]$9748 } { \nia_ok$45 \nia$44 } case - assign $1\nia$next[63:0]$9703 \nia - assign $1\nia_ok$next[0:0]$9704 \nia_ok + assign $1\nia$next[63:0]$9748 \nia + assign $1\nia_ok$next[0:0]$9749 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$9705 1'0 + assign $2\nia_ok$next[0:0]$9750 1'0 case - assign $2\nia_ok$next[0:0]$9705 $1\nia_ok$next[0:0]$9704 + assign $2\nia_ok$next[0:0]$9750 $1\nia_ok$next[0:0]$9749 end sync always - update \nia$next $0\nia$next[63:0]$9701 - update \nia_ok$next $0\nia_ok$next[0:0]$9702 + update \nia$next $0\nia$next[63:0]$9746 + update \nia_ok$next $0\nia_ok$next[0:0]$9747 end - attribute \src "libresoc.v:167608.3-167626.6" - process $proc$libresoc.v:167608$9706 + attribute \src "libresoc.v:169622.3-169640.6" + process $proc$libresoc.v:169622$9751 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr$next[63:0]$9707 $1\msr$next[63:0]$9709 + assign $0\msr$next[63:0]$9752 $1\msr$next[63:0]$9754 assign { } { } - assign $0\msr_ok$next[0:0]$9708 $2\msr_ok$next[0:0]$9711 - attribute \src "libresoc.v:167609.5-167609.29" + assign $0\msr_ok$next[0:0]$9753 $2\msr_ok$next[0:0]$9756 + attribute \src "libresoc.v:169623.5-169623.29" switch \initial - attribute \src "libresoc.v:167609.9-167609.17" + attribute \src "libresoc.v:169623.9-169623.17" case 1'1 case end @@ -346565,30 +349274,30 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9710 $1\msr$next[63:0]$9709 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9755 $1\msr$next[63:0]$9754 } { \msr_ok$47 \msr$46 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9710 $1\msr$next[63:0]$9709 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9755 $1\msr$next[63:0]$9754 } { \msr_ok$47 \msr$46 } case - assign $1\msr$next[63:0]$9709 \msr - assign $1\msr_ok$next[0:0]$9710 \msr_ok + assign $1\msr$next[63:0]$9754 \msr + assign $1\msr_ok$next[0:0]$9755 \msr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_ok$next[0:0]$9711 1'0 + assign $2\msr_ok$next[0:0]$9756 1'0 case - assign $2\msr_ok$next[0:0]$9711 $1\msr_ok$next[0:0]$9710 + assign $2\msr_ok$next[0:0]$9756 $1\msr_ok$next[0:0]$9755 end sync always - update \msr$next $0\msr$next[63:0]$9707 - update \msr_ok$next $0\msr_ok$next[0:0]$9708 + update \msr$next $0\msr$next[63:0]$9752 + update \msr_ok$next $0\msr_ok$next[0:0]$9753 end - connect \$26 $and$libresoc.v:167393$9622_Y + connect \$26 $and$libresoc.v:169407$9667_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } @@ -346608,266 +349317,266 @@ module \pipe2$35 connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:167649.1-169138.10" +attribute \src "libresoc.v:169663.1-171166.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end - attribute \src "libresoc.v:168976.3-168994.6" - wire width 4 $0\cr_a$next[3:0]$9802 - attribute \src "libresoc.v:168795.3-168796.25" + attribute \src "libresoc.v:171004.3-171022.6" + wire width 4 $0\cr_a$next[3:0]$9847 + attribute \src "libresoc.v:170823.3-170824.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:168976.3-168994.6" - wire $0\cr_a_ok$next[0:0]$9803 - attribute \src "libresoc.v:168797.3-168798.31" + attribute \src "libresoc.v:171004.3-171022.6" + wire $0\cr_a_ok$next[0:0]$9848 + attribute \src "libresoc.v:170825.3-170826.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:167650.7-167650.20" + attribute \src "libresoc.v:169664.7-169664.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169064.3-169105.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9827 - attribute \src "libresoc.v:168835.3-168836.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9789 - attribute \src "libresoc.v:167691.13-167691.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9873 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 13 $0\logical_op__fn_unit$3$next[12:0]$9828 - attribute \src "libresoc.v:168805.3-168806.61" - wire width 13 $0\logical_op__fn_unit$3[12:0]$9759 - attribute \src "libresoc.v:167728.14-167728.48" - wire width 13 $0\logical_op__fn_unit$3[12:0]$9875 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9829 - attribute \src "libresoc.v:168807.3-168808.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9761 - attribute \src "libresoc.v:167751.14-167751.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9877 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9830 - attribute \src "libresoc.v:168809.3-168810.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9763 - attribute \src "libresoc.v:167760.7-167760.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9879 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9831 - attribute \src "libresoc.v:168823.3-168824.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9777 - attribute \src "libresoc.v:167777.13-167777.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9881 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9832 - attribute \src "libresoc.v:168837.3-168838.57" - wire width 32 $0\logical_op__insn$19[31:0]$9791 - attribute \src "libresoc.v:167790.14-167790.43" - wire width 32 $0\logical_op__insn$19[31:0]$9883 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9833 - attribute \src "libresoc.v:168803.3-168804.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9757 - attribute \src "libresoc.v:167947.13-167947.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9885 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__invert_in$10$next[0:0]$9834 - attribute \src "libresoc.v:168819.3-168820.67" - wire $0\logical_op__invert_in$10[0:0]$9773 - attribute \src "libresoc.v:168030.7-168030.40" - wire $0\logical_op__invert_in$10[0:0]$9887 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__invert_out$13$next[0:0]$9835 - attribute \src "libresoc.v:168825.3-168826.69" - wire $0\logical_op__invert_out$13[0:0]$9779 - attribute \src "libresoc.v:168039.7-168039.41" - wire $0\logical_op__invert_out$13[0:0]$9889 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9836 - attribute \src "libresoc.v:168831.3-168832.65" - wire $0\logical_op__is_32bit$16[0:0]$9785 - attribute \src "libresoc.v:168048.7-168048.39" - wire $0\logical_op__is_32bit$16[0:0]$9891 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__is_signed$17$next[0:0]$9837 - attribute \src "libresoc.v:168833.3-168834.67" - wire $0\logical_op__is_signed$17[0:0]$9787 - attribute \src "libresoc.v:168057.7-168057.40" - wire $0\logical_op__is_signed$17[0:0]$9893 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9838 - attribute \src "libresoc.v:168815.3-168816.59" - wire $0\logical_op__oe__oe$8[0:0]$9769 - attribute \src "libresoc.v:168066.7-168066.36" - wire $0\logical_op__oe__oe$8[0:0]$9895 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9839 - attribute \src "libresoc.v:168817.3-168818.59" - wire $0\logical_op__oe__ok$9[0:0]$9771 - attribute \src "libresoc.v:168077.7-168077.36" - wire $0\logical_op__oe__ok$9[0:0]$9897 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__output_carry$15$next[0:0]$9840 - attribute \src "libresoc.v:168829.3-168830.73" - wire $0\logical_op__output_carry$15[0:0]$9783 - attribute \src "libresoc.v:168084.7-168084.43" - wire $0\logical_op__output_carry$15[0:0]$9899 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9841 - attribute \src "libresoc.v:168813.3-168814.59" - wire $0\logical_op__rc__ok$7[0:0]$9767 - attribute \src "libresoc.v:168093.7-168093.36" - wire $0\logical_op__rc__ok$7[0:0]$9901 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9842 - attribute \src "libresoc.v:168811.3-168812.59" - wire $0\logical_op__rc__rc$6[0:0]$9765 - attribute \src "libresoc.v:168102.7-168102.36" - wire $0\logical_op__rc__rc$6[0:0]$9903 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9843 - attribute \src "libresoc.v:168827.3-168828.67" - wire $0\logical_op__write_cr0$14[0:0]$9781 - attribute \src "libresoc.v:168111.7-168111.40" - wire $0\logical_op__write_cr0$14[0:0]$9905 - attribute \src "libresoc.v:169064.3-169105.6" - wire $0\logical_op__zero_a$11$next[0:0]$9844 - attribute \src "libresoc.v:168821.3-168822.61" - wire $0\logical_op__zero_a$11[0:0]$9775 - attribute \src "libresoc.v:168120.7-168120.37" - wire $0\logical_op__zero_a$11[0:0]$9907 - attribute \src "libresoc.v:169051.3-169063.6" - wire width 2 $0\muxid$1$next[1:0]$9824 - attribute \src "libresoc.v:168839.3-168840.33" - wire width 2 $0\muxid$1[1:0]$9793 - attribute \src "libresoc.v:168129.13-168129.29" - wire width 2 $0\muxid$1[1:0]$9909 - attribute \src "libresoc.v:168957.3-168975.6" - wire width 64 $0\o$next[63:0]$9796 - attribute \src "libresoc.v:168799.3-168800.19" + attribute \src "libresoc.v:171092.3-171133.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9872 + attribute \src "libresoc.v:170863.3-170864.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9834 + attribute \src "libresoc.v:169705.13-169705.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9918 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9873 + attribute \src "libresoc.v:170833.3-170834.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9804 + attribute \src "libresoc.v:169744.14-169744.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9920 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9874 + attribute \src "libresoc.v:170835.3-170836.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9806 + attribute \src "libresoc.v:169768.14-169768.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9922 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9875 + attribute \src "libresoc.v:170837.3-170838.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9808 + attribute \src "libresoc.v:169777.7-169777.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9924 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9876 + attribute \src "libresoc.v:170851.3-170852.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9822 + attribute \src "libresoc.v:169794.13-169794.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9926 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9877 + attribute \src "libresoc.v:170865.3-170866.57" + wire width 32 $0\logical_op__insn$19[31:0]$9836 + attribute \src "libresoc.v:169807.14-169807.43" + wire width 32 $0\logical_op__insn$19[31:0]$9928 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9878 + attribute \src "libresoc.v:170831.3-170832.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9802 + attribute \src "libresoc.v:169966.13-169966.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9930 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__invert_in$10$next[0:0]$9879 + attribute \src "libresoc.v:170847.3-170848.67" + wire $0\logical_op__invert_in$10[0:0]$9818 + attribute \src "libresoc.v:170050.7-170050.40" + wire $0\logical_op__invert_in$10[0:0]$9932 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__invert_out$13$next[0:0]$9880 + attribute \src "libresoc.v:170853.3-170854.69" + wire $0\logical_op__invert_out$13[0:0]$9824 + attribute \src "libresoc.v:170059.7-170059.41" + wire $0\logical_op__invert_out$13[0:0]$9934 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9881 + attribute \src "libresoc.v:170859.3-170860.65" + wire $0\logical_op__is_32bit$16[0:0]$9830 + attribute \src "libresoc.v:170068.7-170068.39" + wire $0\logical_op__is_32bit$16[0:0]$9936 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__is_signed$17$next[0:0]$9882 + attribute \src "libresoc.v:170861.3-170862.67" + wire $0\logical_op__is_signed$17[0:0]$9832 + attribute \src "libresoc.v:170077.7-170077.40" + wire $0\logical_op__is_signed$17[0:0]$9938 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9883 + attribute \src "libresoc.v:170843.3-170844.59" + wire $0\logical_op__oe__oe$8[0:0]$9814 + attribute \src "libresoc.v:170086.7-170086.36" + wire $0\logical_op__oe__oe$8[0:0]$9940 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9884 + attribute \src "libresoc.v:170845.3-170846.59" + wire $0\logical_op__oe__ok$9[0:0]$9816 + attribute \src "libresoc.v:170097.7-170097.36" + wire $0\logical_op__oe__ok$9[0:0]$9942 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__output_carry$15$next[0:0]$9885 + attribute \src "libresoc.v:170857.3-170858.73" + wire $0\logical_op__output_carry$15[0:0]$9828 + attribute \src "libresoc.v:170104.7-170104.43" + wire $0\logical_op__output_carry$15[0:0]$9944 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9886 + attribute \src "libresoc.v:170841.3-170842.59" + wire $0\logical_op__rc__ok$7[0:0]$9812 + attribute \src "libresoc.v:170113.7-170113.36" + wire $0\logical_op__rc__ok$7[0:0]$9946 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9887 + attribute \src "libresoc.v:170839.3-170840.59" + wire $0\logical_op__rc__rc$6[0:0]$9810 + attribute \src "libresoc.v:170122.7-170122.36" + wire $0\logical_op__rc__rc$6[0:0]$9948 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9888 + attribute \src "libresoc.v:170855.3-170856.67" + wire $0\logical_op__write_cr0$14[0:0]$9826 + attribute \src "libresoc.v:170131.7-170131.40" + wire $0\logical_op__write_cr0$14[0:0]$9950 + attribute \src "libresoc.v:171092.3-171133.6" + wire $0\logical_op__zero_a$11$next[0:0]$9889 + attribute \src "libresoc.v:170849.3-170850.61" + wire $0\logical_op__zero_a$11[0:0]$9820 + attribute \src "libresoc.v:170140.7-170140.37" + wire $0\logical_op__zero_a$11[0:0]$9952 + attribute \src "libresoc.v:171079.3-171091.6" + wire width 2 $0\muxid$1$next[1:0]$9869 + attribute \src "libresoc.v:170867.3-170868.33" + wire width 2 $0\muxid$1[1:0]$9838 + attribute \src "libresoc.v:170149.13-170149.29" + wire width 2 $0\muxid$1[1:0]$9954 + attribute \src "libresoc.v:170985.3-171003.6" + wire width 64 $0\o$next[63:0]$9841 + attribute \src "libresoc.v:170827.3-170828.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:168957.3-168975.6" - wire $0\o_ok$next[0:0]$9797 - attribute \src "libresoc.v:168801.3-168802.25" + attribute \src "libresoc.v:170985.3-171003.6" + wire $0\o_ok$next[0:0]$9842 + attribute \src "libresoc.v:170829.3-170830.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:169033.3-169050.6" - wire $0\r_busy$next[0:0]$9820 - attribute \src "libresoc.v:168841.3-168842.29" + attribute \src "libresoc.v:171061.3-171078.6" + wire $0\r_busy$next[0:0]$9865 + attribute \src "libresoc.v:170869.3-170870.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:168995.3-169013.6" - wire width 2 $0\xer_ov$next[1:0]$9808 - attribute \src "libresoc.v:168791.3-168792.29" + attribute \src "libresoc.v:171023.3-171041.6" + wire width 2 $0\xer_ov$next[1:0]$9853 + attribute \src "libresoc.v:170819.3-170820.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:168995.3-169013.6" - wire $0\xer_ov_ok$next[0:0]$9809 - attribute \src "libresoc.v:168793.3-168794.35" + attribute \src "libresoc.v:171023.3-171041.6" + wire $0\xer_ov_ok$next[0:0]$9854 + attribute \src "libresoc.v:170821.3-170822.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:169014.3-169032.6" - wire $0\xer_so$20$next[0:0]$9815 - attribute \src "libresoc.v:168787.3-168788.37" - wire $0\xer_so$20[0:0]$9748 - attribute \src "libresoc.v:168772.7-168772.25" - wire $0\xer_so$20[0:0]$9916 - attribute \src "libresoc.v:169014.3-169032.6" - wire $0\xer_so_ok$next[0:0]$9814 - attribute \src "libresoc.v:168789.3-168790.35" + attribute \src "libresoc.v:171042.3-171060.6" + wire $0\xer_so$20$next[0:0]$9860 + attribute \src "libresoc.v:170815.3-170816.37" + wire $0\xer_so$20[0:0]$9793 + attribute \src "libresoc.v:170800.7-170800.25" + wire $0\xer_so$20[0:0]$9961 + attribute \src "libresoc.v:171042.3-171060.6" + wire $0\xer_so_ok$next[0:0]$9859 + attribute \src "libresoc.v:170817.3-170818.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:168976.3-168994.6" - wire width 4 $1\cr_a$next[3:0]$9804 - attribute \src "libresoc.v:167659.13-167659.24" + attribute \src "libresoc.v:171004.3-171022.6" + wire width 4 $1\cr_a$next[3:0]$9849 + attribute \src "libresoc.v:169673.13-169673.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:168976.3-168994.6" - wire $1\cr_a_ok$next[0:0]$9805 - attribute \src "libresoc.v:167668.7-167668.21" + attribute \src "libresoc.v:171004.3-171022.6" + wire $1\cr_a_ok$next[0:0]$9850 + attribute \src "libresoc.v:169682.7-169682.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:169064.3-169105.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9845 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 13 $1\logical_op__fn_unit$3$next[12:0]$9846 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9847 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$9848 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$9849 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$9850 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$9851 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__invert_in$10$next[0:0]$9852 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__invert_out$13$next[0:0]$9853 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__is_32bit$16$next[0:0]$9854 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__is_signed$17$next[0:0]$9855 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__oe__oe$8$next[0:0]$9856 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__oe__ok$9$next[0:0]$9857 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__output_carry$15$next[0:0]$9858 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__rc__ok$7$next[0:0]$9859 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__rc__rc$6$next[0:0]$9860 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__write_cr0$14$next[0:0]$9861 - attribute \src "libresoc.v:169064.3-169105.6" - wire $1\logical_op__zero_a$11$next[0:0]$9862 - attribute \src "libresoc.v:169051.3-169063.6" - wire width 2 $1\muxid$1$next[1:0]$9825 - attribute \src "libresoc.v:168957.3-168975.6" - wire width 64 $1\o$next[63:0]$9798 - attribute \src "libresoc.v:168142.14-168142.38" + attribute \src "libresoc.v:171092.3-171133.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9890 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9891 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9892 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9893 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9894 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9895 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9896 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__invert_in$10$next[0:0]$9897 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__invert_out$13$next[0:0]$9898 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9899 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__is_signed$17$next[0:0]$9900 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9901 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9902 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__output_carry$15$next[0:0]$9903 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9904 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9905 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9906 + attribute \src "libresoc.v:171092.3-171133.6" + wire $1\logical_op__zero_a$11$next[0:0]$9907 + attribute \src "libresoc.v:171079.3-171091.6" + wire width 2 $1\muxid$1$next[1:0]$9870 + attribute \src "libresoc.v:170985.3-171003.6" + wire width 64 $1\o$next[63:0]$9843 + attribute \src "libresoc.v:170162.14-170162.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:168957.3-168975.6" - wire $1\o_ok$next[0:0]$9799 - attribute \src "libresoc.v:168149.7-168149.18" + attribute \src "libresoc.v:170985.3-171003.6" + wire $1\o_ok$next[0:0]$9844 + attribute \src "libresoc.v:170169.7-170169.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:169033.3-169050.6" - wire $1\r_busy$next[0:0]$9821 - attribute \src "libresoc.v:168737.7-168737.20" + attribute \src "libresoc.v:171061.3-171078.6" + wire $1\r_busy$next[0:0]$9866 + attribute \src "libresoc.v:170765.7-170765.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:168995.3-169013.6" - wire width 2 $1\xer_ov$next[1:0]$9810 - attribute \src "libresoc.v:168752.13-168752.26" + attribute \src "libresoc.v:171023.3-171041.6" + wire width 2 $1\xer_ov$next[1:0]$9855 + attribute \src "libresoc.v:170780.13-170780.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:168995.3-169013.6" - wire $1\xer_ov_ok$next[0:0]$9811 - attribute \src "libresoc.v:168759.7-168759.23" + attribute \src "libresoc.v:171023.3-171041.6" + wire $1\xer_ov_ok$next[0:0]$9856 + attribute \src "libresoc.v:170787.7-170787.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:169014.3-169032.6" - wire $1\xer_so$20$next[0:0]$9817 - attribute \src "libresoc.v:169014.3-169032.6" - wire $1\xer_so_ok$next[0:0]$9816 - attribute \src "libresoc.v:168777.7-168777.23" + attribute \src "libresoc.v:171042.3-171060.6" + wire $1\xer_so$20$next[0:0]$9862 + attribute \src "libresoc.v:171042.3-171060.6" + wire $1\xer_so_ok$next[0:0]$9861 + attribute \src "libresoc.v:170805.7-170805.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:168976.3-168994.6" - wire $2\cr_a_ok$next[0:0]$9806 - attribute \src "libresoc.v:169064.3-169105.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9863 - attribute \src "libresoc.v:169064.3-169105.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$9864 - attribute \src "libresoc.v:169064.3-169105.6" - wire $2\logical_op__oe__oe$8$next[0:0]$9865 - attribute \src "libresoc.v:169064.3-169105.6" - wire $2\logical_op__oe__ok$9$next[0:0]$9866 - attribute \src "libresoc.v:169064.3-169105.6" - wire $2\logical_op__rc__ok$7$next[0:0]$9867 - attribute \src "libresoc.v:169064.3-169105.6" - wire $2\logical_op__rc__rc$6$next[0:0]$9868 - attribute \src "libresoc.v:168957.3-168975.6" - wire $2\o_ok$next[0:0]$9800 - attribute \src "libresoc.v:169033.3-169050.6" - wire $2\r_busy$next[0:0]$9822 - attribute \src "libresoc.v:168995.3-169013.6" - wire $2\xer_ov_ok$next[0:0]$9812 - attribute \src "libresoc.v:169014.3-169032.6" - wire $2\xer_so_ok$next[0:0]$9818 - attribute \src "libresoc.v:168786.18-168786.118" - wire $and$libresoc.v:168786$9746_Y + attribute \src "libresoc.v:171004.3-171022.6" + wire $2\cr_a_ok$next[0:0]$9851 + attribute \src "libresoc.v:171092.3-171133.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9908 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9909 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9910 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9911 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9912 + attribute \src "libresoc.v:171092.3-171133.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9913 + attribute \src "libresoc.v:170985.3-171003.6" + wire $2\o_ok$next[0:0]$9845 + attribute \src "libresoc.v:171061.3-171078.6" + wire $2\r_busy$next[0:0]$9867 + attribute \src "libresoc.v:171023.3-171041.6" + wire $2\xer_ov_ok$next[0:0]$9857 + attribute \src "libresoc.v:171042.3-171060.6" + wire $2\xer_so_ok$next[0:0]$9863 + attribute \src "libresoc.v:170814.18-170814.118" + wire $and$libresoc.v:170814$9791_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 56 \cr_a @@ -346897,7 +349606,7 @@ module \pipe_end wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg - attribute \src "libresoc.v:167650.7-167650.15" + attribute \src "libresoc.v:169664.7-169664.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -346908,55 +349617,58 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$93 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 37 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$3$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 37 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$3$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$78 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -347075,6 +349787,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -347151,6 +349864,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 36 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -347229,6 +349943,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -347356,37 +350071,39 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len$58 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_logical_op__fn_unit$43 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_logical_op__fn_unit$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -347485,6 +350202,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -347561,6 +350279,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -347634,37 +350353,39 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_stage_logical_op__data_len$38 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_stage_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_stage_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_stage_logical_op__fn_unit$23 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \output_stage_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_stage_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -347763,6 +350484,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_stage_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -347839,6 +350561,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_stage_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -347974,7 +350697,7 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:168786$9746 + cell $and $and$libresoc.v:170814$9791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347982,16 +350705,16 @@ module \pipe_end parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o - connect \Y $and$libresoc.v:168786$9746_Y + connect \Y $and$libresoc.v:170814$9791_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:168843.10-168846.4" + attribute \src "libresoc.v:170871.10-170874.4" cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:168847.15-168899.4" + attribute \src "libresoc.v:170875.15-170927.4" cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 @@ -348046,7 +350769,7 @@ module \pipe_end connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:168900.16-168952.4" + attribute \src "libresoc.v:170928.16-170980.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 @@ -348101,451 +350824,451 @@ module \pipe_end connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:168953.10-168956.4" + attribute \src "libresoc.v:170981.10-170984.4" cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:167650.7-167650.20" - process $proc$libresoc.v:167650$9869 + attribute \src "libresoc.v:169664.7-169664.20" + process $proc$libresoc.v:169664$9914 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167659.13-167659.24" - process $proc$libresoc.v:167659$9870 + attribute \src "libresoc.v:169673.13-169673.24" + process $proc$libresoc.v:169673$9915 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:167668.7-167668.21" - process $proc$libresoc.v:167668$9871 + attribute \src "libresoc.v:169682.7-169682.21" + process $proc$libresoc.v:169682$9916 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:167691.13-167691.45" - process $proc$libresoc.v:167691$9872 + attribute \src "libresoc.v:169705.13-169705.45" + process $proc$libresoc.v:169705$9917 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9873 4'0000 + assign $0\logical_op__data_len$18[3:0]$9918 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9873 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9918 end - attribute \src "libresoc.v:167728.14-167728.48" - process $proc$libresoc.v:167728$9874 + attribute \src "libresoc.v:169744.14-169744.48" + process $proc$libresoc.v:169744$9919 assign { } { } - assign $0\logical_op__fn_unit$3[12:0]$9875 13'0000000000000 + assign $0\logical_op__fn_unit$3[13:0]$9920 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9875 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9920 end - attribute \src "libresoc.v:167751.14-167751.67" - process $proc$libresoc.v:167751$9876 + attribute \src "libresoc.v:169768.14-169768.67" + process $proc$libresoc.v:169768$9921 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9877 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$9922 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9877 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9922 end - attribute \src "libresoc.v:167760.7-167760.42" - process $proc$libresoc.v:167760$9878 + attribute \src "libresoc.v:169777.7-169777.42" + process $proc$libresoc.v:169777$9923 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9879 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$9924 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9879 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9924 end - attribute \src "libresoc.v:167777.13-167777.48" - process $proc$libresoc.v:167777$9880 + attribute \src "libresoc.v:169794.13-169794.48" + process $proc$libresoc.v:169794$9925 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9881 2'00 + assign $0\logical_op__input_carry$12[1:0]$9926 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9881 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9926 end - attribute \src "libresoc.v:167790.14-167790.43" - process $proc$libresoc.v:167790$9882 + attribute \src "libresoc.v:169807.14-169807.43" + process $proc$libresoc.v:169807$9927 assign { } { } - assign $0\logical_op__insn$19[31:0]$9883 0 + assign $0\logical_op__insn$19[31:0]$9928 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9883 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9928 end - attribute \src "libresoc.v:167947.13-167947.46" - process $proc$libresoc.v:167947$9884 + attribute \src "libresoc.v:169966.13-169966.46" + process $proc$libresoc.v:169966$9929 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9885 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$9930 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9885 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9930 end - attribute \src "libresoc.v:168030.7-168030.40" - process $proc$libresoc.v:168030$9886 + attribute \src "libresoc.v:170050.7-170050.40" + process $proc$libresoc.v:170050$9931 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9887 1'0 + assign $0\logical_op__invert_in$10[0:0]$9932 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9887 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9932 end - attribute \src "libresoc.v:168039.7-168039.41" - process $proc$libresoc.v:168039$9888 + attribute \src "libresoc.v:170059.7-170059.41" + process $proc$libresoc.v:170059$9933 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9889 1'0 + assign $0\logical_op__invert_out$13[0:0]$9934 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9889 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9934 end - attribute \src "libresoc.v:168048.7-168048.39" - process $proc$libresoc.v:168048$9890 + attribute \src "libresoc.v:170068.7-170068.39" + process $proc$libresoc.v:170068$9935 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9891 1'0 + assign $0\logical_op__is_32bit$16[0:0]$9936 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9891 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9936 end - attribute \src "libresoc.v:168057.7-168057.40" - process $proc$libresoc.v:168057$9892 + attribute \src "libresoc.v:170077.7-170077.40" + process $proc$libresoc.v:170077$9937 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9893 1'0 + assign $0\logical_op__is_signed$17[0:0]$9938 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9893 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9938 end - attribute \src "libresoc.v:168066.7-168066.36" - process $proc$libresoc.v:168066$9894 + attribute \src "libresoc.v:170086.7-170086.36" + process $proc$libresoc.v:170086$9939 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9895 1'0 + assign $0\logical_op__oe__oe$8[0:0]$9940 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9895 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9940 end - attribute \src "libresoc.v:168077.7-168077.36" - process $proc$libresoc.v:168077$9896 + attribute \src "libresoc.v:170097.7-170097.36" + process $proc$libresoc.v:170097$9941 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9897 1'0 + assign $0\logical_op__oe__ok$9[0:0]$9942 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9897 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9942 end - attribute \src "libresoc.v:168084.7-168084.43" - process $proc$libresoc.v:168084$9898 + attribute \src "libresoc.v:170104.7-170104.43" + process $proc$libresoc.v:170104$9943 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9899 1'0 + assign $0\logical_op__output_carry$15[0:0]$9944 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9899 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9944 end - attribute \src "libresoc.v:168093.7-168093.36" - process $proc$libresoc.v:168093$9900 + attribute \src "libresoc.v:170113.7-170113.36" + process $proc$libresoc.v:170113$9945 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9901 1'0 + assign $0\logical_op__rc__ok$7[0:0]$9946 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9901 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9946 end - attribute \src "libresoc.v:168102.7-168102.36" - process $proc$libresoc.v:168102$9902 + attribute \src "libresoc.v:170122.7-170122.36" + process $proc$libresoc.v:170122$9947 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9903 1'0 + assign $0\logical_op__rc__rc$6[0:0]$9948 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9903 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9948 end - attribute \src "libresoc.v:168111.7-168111.40" - process $proc$libresoc.v:168111$9904 + attribute \src "libresoc.v:170131.7-170131.40" + process $proc$libresoc.v:170131$9949 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9905 1'0 + assign $0\logical_op__write_cr0$14[0:0]$9950 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9905 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9950 end - attribute \src "libresoc.v:168120.7-168120.37" - process $proc$libresoc.v:168120$9906 + attribute \src "libresoc.v:170140.7-170140.37" + process $proc$libresoc.v:170140$9951 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9907 1'0 + assign $0\logical_op__zero_a$11[0:0]$9952 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9907 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9952 end - attribute \src "libresoc.v:168129.13-168129.29" - process $proc$libresoc.v:168129$9908 + attribute \src "libresoc.v:170149.13-170149.29" + process $proc$libresoc.v:170149$9953 assign { } { } - assign $0\muxid$1[1:0]$9909 2'00 + assign $0\muxid$1[1:0]$9954 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9909 + update \muxid$1 $0\muxid$1[1:0]$9954 end - attribute \src "libresoc.v:168142.14-168142.38" - process $proc$libresoc.v:168142$9910 + attribute \src "libresoc.v:170162.14-170162.38" + process $proc$libresoc.v:170162$9955 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:168149.7-168149.18" - process $proc$libresoc.v:168149$9911 + attribute \src "libresoc.v:170169.7-170169.18" + process $proc$libresoc.v:170169$9956 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:168737.7-168737.20" - process $proc$libresoc.v:168737$9912 + attribute \src "libresoc.v:170765.7-170765.20" + process $proc$libresoc.v:170765$9957 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:168752.13-168752.26" - process $proc$libresoc.v:168752$9913 + attribute \src "libresoc.v:170780.13-170780.26" + process $proc$libresoc.v:170780$9958 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:168759.7-168759.23" - process $proc$libresoc.v:168759$9914 + attribute \src "libresoc.v:170787.7-170787.23" + process $proc$libresoc.v:170787$9959 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:168772.7-168772.25" - process $proc$libresoc.v:168772$9915 + attribute \src "libresoc.v:170800.7-170800.25" + process $proc$libresoc.v:170800$9960 assign { } { } - assign $0\xer_so$20[0:0]$9916 1'0 + assign $0\xer_so$20[0:0]$9961 1'0 sync always sync init - update \xer_so$20 $0\xer_so$20[0:0]$9916 + update \xer_so$20 $0\xer_so$20[0:0]$9961 end - attribute \src "libresoc.v:168777.7-168777.23" - process $proc$libresoc.v:168777$9917 + attribute \src "libresoc.v:170805.7-170805.23" + process $proc$libresoc.v:170805$9962 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:168787.3-168788.37" - process $proc$libresoc.v:168787$9747 + attribute \src "libresoc.v:170815.3-170816.37" + process $proc$libresoc.v:170815$9792 assign { } { } - assign $0\xer_so$20[0:0]$9748 \xer_so$20$next + assign $0\xer_so$20[0:0]$9793 \xer_so$20$next sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9748 + update \xer_so$20 $0\xer_so$20[0:0]$9793 end - attribute \src "libresoc.v:168789.3-168790.35" - process $proc$libresoc.v:168789$9749 + attribute \src "libresoc.v:170817.3-170818.35" + process $proc$libresoc.v:170817$9794 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:168791.3-168792.29" - process $proc$libresoc.v:168791$9750 + attribute \src "libresoc.v:170819.3-170820.29" + process $proc$libresoc.v:170819$9795 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:168793.3-168794.35" - process $proc$libresoc.v:168793$9751 + attribute \src "libresoc.v:170821.3-170822.35" + process $proc$libresoc.v:170821$9796 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:168795.3-168796.25" - process $proc$libresoc.v:168795$9752 + attribute \src "libresoc.v:170823.3-170824.25" + process $proc$libresoc.v:170823$9797 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:168797.3-168798.31" - process $proc$libresoc.v:168797$9753 + attribute \src "libresoc.v:170825.3-170826.31" + process $proc$libresoc.v:170825$9798 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:168799.3-168800.19" - process $proc$libresoc.v:168799$9754 + attribute \src "libresoc.v:170827.3-170828.19" + process $proc$libresoc.v:170827$9799 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:168801.3-168802.25" - process $proc$libresoc.v:168801$9755 + attribute \src "libresoc.v:170829.3-170830.25" + process $proc$libresoc.v:170829$9800 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:168803.3-168804.65" - process $proc$libresoc.v:168803$9756 + attribute \src "libresoc.v:170831.3-170832.65" + process $proc$libresoc.v:170831$9801 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9757 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$9802 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9757 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9802 end - attribute \src "libresoc.v:168805.3-168806.61" - process $proc$libresoc.v:168805$9758 + attribute \src "libresoc.v:170833.3-170834.61" + process $proc$libresoc.v:170833$9803 assign { } { } - assign $0\logical_op__fn_unit$3[12:0]$9759 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$9804 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9759 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9804 end - attribute \src "libresoc.v:168807.3-168808.75" - process $proc$libresoc.v:168807$9760 + attribute \src "libresoc.v:170835.3-170836.75" + process $proc$libresoc.v:170835$9805 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9761 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$9806 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9761 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9806 end - attribute \src "libresoc.v:168809.3-168810.71" - process $proc$libresoc.v:168809$9762 + attribute \src "libresoc.v:170837.3-170838.71" + process $proc$libresoc.v:170837$9807 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9763 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$9808 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9763 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9808 end - attribute \src "libresoc.v:168811.3-168812.59" - process $proc$libresoc.v:168811$9764 + attribute \src "libresoc.v:170839.3-170840.59" + process $proc$libresoc.v:170839$9809 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9765 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$9810 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9765 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9810 end - attribute \src "libresoc.v:168813.3-168814.59" - process $proc$libresoc.v:168813$9766 + attribute \src "libresoc.v:170841.3-170842.59" + process $proc$libresoc.v:170841$9811 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9767 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$9812 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9767 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9812 end - attribute \src "libresoc.v:168815.3-168816.59" - process $proc$libresoc.v:168815$9768 + attribute \src "libresoc.v:170843.3-170844.59" + process $proc$libresoc.v:170843$9813 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9769 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$9814 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9769 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9814 end - attribute \src "libresoc.v:168817.3-168818.59" - process $proc$libresoc.v:168817$9770 + attribute \src "libresoc.v:170845.3-170846.59" + process $proc$libresoc.v:170845$9815 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9771 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$9816 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9771 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9816 end - attribute \src "libresoc.v:168819.3-168820.67" - process $proc$libresoc.v:168819$9772 + attribute \src "libresoc.v:170847.3-170848.67" + process $proc$libresoc.v:170847$9817 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9773 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$9818 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9773 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9818 end - attribute \src "libresoc.v:168821.3-168822.61" - process $proc$libresoc.v:168821$9774 + attribute \src "libresoc.v:170849.3-170850.61" + process $proc$libresoc.v:170849$9819 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9775 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$9820 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9775 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9820 end - attribute \src "libresoc.v:168823.3-168824.71" - process $proc$libresoc.v:168823$9776 + attribute \src "libresoc.v:170851.3-170852.71" + process $proc$libresoc.v:170851$9821 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9777 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$9822 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9777 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9822 end - attribute \src "libresoc.v:168825.3-168826.69" - process $proc$libresoc.v:168825$9778 + attribute \src "libresoc.v:170853.3-170854.69" + process $proc$libresoc.v:170853$9823 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9779 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$9824 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9779 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9824 end - attribute \src "libresoc.v:168827.3-168828.67" - process $proc$libresoc.v:168827$9780 + attribute \src "libresoc.v:170855.3-170856.67" + process $proc$libresoc.v:170855$9825 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9781 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$9826 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9781 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9826 end - attribute \src "libresoc.v:168829.3-168830.73" - process $proc$libresoc.v:168829$9782 + attribute \src "libresoc.v:170857.3-170858.73" + process $proc$libresoc.v:170857$9827 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9783 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$9828 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9783 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9828 end - attribute \src "libresoc.v:168831.3-168832.65" - process $proc$libresoc.v:168831$9784 + attribute \src "libresoc.v:170859.3-170860.65" + process $proc$libresoc.v:170859$9829 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9785 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$9830 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9785 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9830 end - attribute \src "libresoc.v:168833.3-168834.67" - process $proc$libresoc.v:168833$9786 + attribute \src "libresoc.v:170861.3-170862.67" + process $proc$libresoc.v:170861$9831 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9787 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$9832 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9787 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9832 end - attribute \src "libresoc.v:168835.3-168836.65" - process $proc$libresoc.v:168835$9788 + attribute \src "libresoc.v:170863.3-170864.65" + process $proc$libresoc.v:170863$9833 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9789 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$9834 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9789 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9834 end - attribute \src "libresoc.v:168837.3-168838.57" - process $proc$libresoc.v:168837$9790 + attribute \src "libresoc.v:170865.3-170866.57" + process $proc$libresoc.v:170865$9835 assign { } { } - assign $0\logical_op__insn$19[31:0]$9791 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$9836 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9791 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9836 end - attribute \src "libresoc.v:168839.3-168840.33" - process $proc$libresoc.v:168839$9792 + attribute \src "libresoc.v:170867.3-170868.33" + process $proc$libresoc.v:170867$9837 assign { } { } - assign $0\muxid$1[1:0]$9793 \muxid$1$next + assign $0\muxid$1[1:0]$9838 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9793 + update \muxid$1 $0\muxid$1[1:0]$9838 end - attribute \src "libresoc.v:168841.3-168842.29" - process $proc$libresoc.v:168841$9794 + attribute \src "libresoc.v:170869.3-170870.29" + process $proc$libresoc.v:170869$9839 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:168957.3-168975.6" - process $proc$libresoc.v:168957$9795 + attribute \src "libresoc.v:170985.3-171003.6" + process $proc$libresoc.v:170985$9840 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9796 $1\o$next[63:0]$9798 + assign $0\o$next[63:0]$9841 $1\o$next[63:0]$9843 assign { } { } - assign $0\o_ok$next[0:0]$9797 $2\o_ok$next[0:0]$9800 - attribute \src "libresoc.v:168958.5-168958.29" + assign $0\o_ok$next[0:0]$9842 $2\o_ok$next[0:0]$9845 + attribute \src "libresoc.v:170986.5-170986.29" switch \initial - attribute \src "libresoc.v:168958.9-168958.17" + attribute \src "libresoc.v:170986.9-170986.17" case 1'1 case end @@ -348555,41 +351278,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9799 $1\o$next[63:0]$9798 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9844 $1\o$next[63:0]$9843 } { \o_ok$96 \o$95 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9799 $1\o$next[63:0]$9798 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9844 $1\o$next[63:0]$9843 } { \o_ok$96 \o$95 } case - assign $1\o$next[63:0]$9798 \o - assign $1\o_ok$next[0:0]$9799 \o_ok + assign $1\o$next[63:0]$9843 \o + assign $1\o_ok$next[0:0]$9844 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9800 1'0 + assign $2\o_ok$next[0:0]$9845 1'0 case - assign $2\o_ok$next[0:0]$9800 $1\o_ok$next[0:0]$9799 + assign $2\o_ok$next[0:0]$9845 $1\o_ok$next[0:0]$9844 end sync always - update \o$next $0\o$next[63:0]$9796 - update \o_ok$next $0\o_ok$next[0:0]$9797 + update \o$next $0\o$next[63:0]$9841 + update \o_ok$next $0\o_ok$next[0:0]$9842 end - attribute \src "libresoc.v:168976.3-168994.6" - process $proc$libresoc.v:168976$9801 + attribute \src "libresoc.v:171004.3-171022.6" + process $proc$libresoc.v:171004$9846 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9802 $1\cr_a$next[3:0]$9804 + assign $0\cr_a$next[3:0]$9847 $1\cr_a$next[3:0]$9849 assign { } { } - assign $0\cr_a_ok$next[0:0]$9803 $2\cr_a_ok$next[0:0]$9806 - attribute \src "libresoc.v:168977.5-168977.29" + assign $0\cr_a_ok$next[0:0]$9848 $2\cr_a_ok$next[0:0]$9851 + attribute \src "libresoc.v:171005.5-171005.29" switch \initial - attribute \src "libresoc.v:168977.9-168977.17" + attribute \src "libresoc.v:171005.9-171005.17" case 1'1 case end @@ -348599,41 +351322,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9805 $1\cr_a$next[3:0]$9804 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9850 $1\cr_a$next[3:0]$9849 } { \cr_a_ok$98 \cr_a$97 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9805 $1\cr_a$next[3:0]$9804 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9850 $1\cr_a$next[3:0]$9849 } { \cr_a_ok$98 \cr_a$97 } case - assign $1\cr_a$next[3:0]$9804 \cr_a - assign $1\cr_a_ok$next[0:0]$9805 \cr_a_ok + assign $1\cr_a$next[3:0]$9849 \cr_a + assign $1\cr_a_ok$next[0:0]$9850 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9806 1'0 + assign $2\cr_a_ok$next[0:0]$9851 1'0 case - assign $2\cr_a_ok$next[0:0]$9806 $1\cr_a_ok$next[0:0]$9805 + assign $2\cr_a_ok$next[0:0]$9851 $1\cr_a_ok$next[0:0]$9850 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9802 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9803 + update \cr_a$next $0\cr_a$next[3:0]$9847 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9848 end - attribute \src "libresoc.v:168995.3-169013.6" - process $proc$libresoc.v:168995$9807 + attribute \src "libresoc.v:171023.3-171041.6" + process $proc$libresoc.v:171023$9852 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9808 $1\xer_ov$next[1:0]$9810 + assign $0\xer_ov$next[1:0]$9853 $1\xer_ov$next[1:0]$9855 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9809 $2\xer_ov_ok$next[0:0]$9812 - attribute \src "libresoc.v:168996.5-168996.29" + assign $0\xer_ov_ok$next[0:0]$9854 $2\xer_ov_ok$next[0:0]$9857 + attribute \src "libresoc.v:171024.5-171024.29" switch \initial - attribute \src "libresoc.v:168996.9-168996.17" + attribute \src "libresoc.v:171024.9-171024.17" case 1'1 case end @@ -348643,41 +351366,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9811 $1\xer_ov$next[1:0]$9810 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9856 $1\xer_ov$next[1:0]$9855 } { \xer_ov_ok$100 \xer_ov$99 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9811 $1\xer_ov$next[1:0]$9810 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9856 $1\xer_ov$next[1:0]$9855 } { \xer_ov_ok$100 \xer_ov$99 } case - assign $1\xer_ov$next[1:0]$9810 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9811 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9855 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9856 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9812 1'0 + assign $2\xer_ov_ok$next[0:0]$9857 1'0 case - assign $2\xer_ov_ok$next[0:0]$9812 $1\xer_ov_ok$next[0:0]$9811 + assign $2\xer_ov_ok$next[0:0]$9857 $1\xer_ov_ok$next[0:0]$9856 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9808 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9809 + update \xer_ov$next $0\xer_ov$next[1:0]$9853 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9854 end - attribute \src "libresoc.v:169014.3-169032.6" - process $proc$libresoc.v:169014$9813 + attribute \src "libresoc.v:171042.3-171060.6" + process $proc$libresoc.v:171042$9858 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$20$next[0:0]$9815 $1\xer_so$20$next[0:0]$9817 - assign $0\xer_so_ok$next[0:0]$9814 $2\xer_so_ok$next[0:0]$9818 - attribute \src "libresoc.v:169015.5-169015.29" + assign $0\xer_so$20$next[0:0]$9860 $1\xer_so$20$next[0:0]$9862 + assign $0\xer_so_ok$next[0:0]$9859 $2\xer_so_ok$next[0:0]$9863 + attribute \src "libresoc.v:171043.5-171043.29" switch \initial - attribute \src "libresoc.v:169015.9-169015.17" + attribute \src "libresoc.v:171043.9-171043.17" case 1'1 case end @@ -348687,38 +351410,38 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9816 $1\xer_so$20$next[0:0]$9817 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9861 $1\xer_so$20$next[0:0]$9862 } { \xer_so_ok$102 \xer_so$101 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9816 $1\xer_so$20$next[0:0]$9817 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9861 $1\xer_so$20$next[0:0]$9862 } { \xer_so_ok$102 \xer_so$101 } case - assign $1\xer_so_ok$next[0:0]$9816 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9817 \xer_so$20 + assign $1\xer_so_ok$next[0:0]$9861 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9862 \xer_so$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9818 1'0 + assign $2\xer_so_ok$next[0:0]$9863 1'0 case - assign $2\xer_so_ok$next[0:0]$9818 $1\xer_so_ok$next[0:0]$9816 + assign $2\xer_so_ok$next[0:0]$9863 $1\xer_so_ok$next[0:0]$9861 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9814 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9815 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9859 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9860 end - attribute \src "libresoc.v:169033.3-169050.6" - process $proc$libresoc.v:169033$9819 + attribute \src "libresoc.v:171061.3-171078.6" + process $proc$libresoc.v:171061$9864 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9820 $2\r_busy$next[0:0]$9822 - attribute \src "libresoc.v:169034.5-169034.29" + assign $0\r_busy$next[0:0]$9865 $2\r_busy$next[0:0]$9867 + attribute \src "libresoc.v:171062.5-171062.29" switch \initial - attribute \src "libresoc.v:169034.9-169034.17" + attribute \src "libresoc.v:171062.9-171062.17" case 1'1 case end @@ -348727,34 +351450,34 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9821 1'1 + assign $1\r_busy$next[0:0]$9866 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9821 1'0 + assign $1\r_busy$next[0:0]$9866 1'0 case - assign $1\r_busy$next[0:0]$9821 \r_busy + assign $1\r_busy$next[0:0]$9866 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9822 1'0 + assign $2\r_busy$next[0:0]$9867 1'0 case - assign $2\r_busy$next[0:0]$9822 $1\r_busy$next[0:0]$9821 + assign $2\r_busy$next[0:0]$9867 $1\r_busy$next[0:0]$9866 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9820 + update \r_busy$next $0\r_busy$next[0:0]$9865 end - attribute \src "libresoc.v:169051.3-169063.6" - process $proc$libresoc.v:169051$9823 + attribute \src "libresoc.v:171079.3-171091.6" + process $proc$libresoc.v:171079$9868 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9824 $1\muxid$1$next[1:0]$9825 - attribute \src "libresoc.v:169052.5-169052.29" + assign $0\muxid$1$next[1:0]$9869 $1\muxid$1$next[1:0]$9870 + attribute \src "libresoc.v:171080.5-171080.29" switch \initial - attribute \src "libresoc.v:169052.9-169052.17" + attribute \src "libresoc.v:171080.9-171080.17" case 1'1 case end @@ -348763,19 +351486,19 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9825 \muxid$76 + assign $1\muxid$1$next[1:0]$9870 \muxid$76 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9825 \muxid$76 + assign $1\muxid$1$next[1:0]$9870 \muxid$76 case - assign $1\muxid$1$next[1:0]$9825 \muxid$1 + assign $1\muxid$1$next[1:0]$9870 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9824 + update \muxid$1$next $0\muxid$1$next[1:0]$9869 end - attribute \src "libresoc.v:169064.3-169105.6" - process $proc$libresoc.v:169064$9826 + attribute \src "libresoc.v:171092.3-171133.6" + process $proc$libresoc.v:171092$9871 assign { } { } assign { } { } assign { } { } @@ -348812,33 +351535,33 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9827 $1\logical_op__data_len$18$next[3:0]$9845 - assign $0\logical_op__fn_unit$3$next[12:0]$9828 $1\logical_op__fn_unit$3$next[12:0]$9846 + assign $0\logical_op__data_len$18$next[3:0]$9872 $1\logical_op__data_len$18$next[3:0]$9890 + assign $0\logical_op__fn_unit$3$next[13:0]$9873 $1\logical_op__fn_unit$3$next[13:0]$9891 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9831 $1\logical_op__input_carry$12$next[1:0]$9849 - assign $0\logical_op__insn$19$next[31:0]$9832 $1\logical_op__insn$19$next[31:0]$9850 - assign $0\logical_op__insn_type$2$next[6:0]$9833 $1\logical_op__insn_type$2$next[6:0]$9851 - assign $0\logical_op__invert_in$10$next[0:0]$9834 $1\logical_op__invert_in$10$next[0:0]$9852 - assign $0\logical_op__invert_out$13$next[0:0]$9835 $1\logical_op__invert_out$13$next[0:0]$9853 - assign $0\logical_op__is_32bit$16$next[0:0]$9836 $1\logical_op__is_32bit$16$next[0:0]$9854 - assign $0\logical_op__is_signed$17$next[0:0]$9837 $1\logical_op__is_signed$17$next[0:0]$9855 + assign $0\logical_op__input_carry$12$next[1:0]$9876 $1\logical_op__input_carry$12$next[1:0]$9894 + assign $0\logical_op__insn$19$next[31:0]$9877 $1\logical_op__insn$19$next[31:0]$9895 + assign $0\logical_op__insn_type$2$next[6:0]$9878 $1\logical_op__insn_type$2$next[6:0]$9896 + assign $0\logical_op__invert_in$10$next[0:0]$9879 $1\logical_op__invert_in$10$next[0:0]$9897 + assign $0\logical_op__invert_out$13$next[0:0]$9880 $1\logical_op__invert_out$13$next[0:0]$9898 + assign $0\logical_op__is_32bit$16$next[0:0]$9881 $1\logical_op__is_32bit$16$next[0:0]$9899 + assign $0\logical_op__is_signed$17$next[0:0]$9882 $1\logical_op__is_signed$17$next[0:0]$9900 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9840 $1\logical_op__output_carry$15$next[0:0]$9858 + assign $0\logical_op__output_carry$15$next[0:0]$9885 $1\logical_op__output_carry$15$next[0:0]$9903 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9843 $1\logical_op__write_cr0$14$next[0:0]$9861 - assign $0\logical_op__zero_a$11$next[0:0]$9844 $1\logical_op__zero_a$11$next[0:0]$9862 - assign $0\logical_op__imm_data__data$4$next[63:0]$9829 $2\logical_op__imm_data__data$4$next[63:0]$9863 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9830 $2\logical_op__imm_data__ok$5$next[0:0]$9864 - assign $0\logical_op__oe__oe$8$next[0:0]$9838 $2\logical_op__oe__oe$8$next[0:0]$9865 - assign $0\logical_op__oe__ok$9$next[0:0]$9839 $2\logical_op__oe__ok$9$next[0:0]$9866 - assign $0\logical_op__rc__ok$7$next[0:0]$9841 $2\logical_op__rc__ok$7$next[0:0]$9867 - assign $0\logical_op__rc__rc$6$next[0:0]$9842 $2\logical_op__rc__rc$6$next[0:0]$9868 - attribute \src "libresoc.v:169065.5-169065.29" + assign $0\logical_op__write_cr0$14$next[0:0]$9888 $1\logical_op__write_cr0$14$next[0:0]$9906 + assign $0\logical_op__zero_a$11$next[0:0]$9889 $1\logical_op__zero_a$11$next[0:0]$9907 + assign $0\logical_op__imm_data__data$4$next[63:0]$9874 $2\logical_op__imm_data__data$4$next[63:0]$9908 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9875 $2\logical_op__imm_data__ok$5$next[0:0]$9909 + assign $0\logical_op__oe__oe$8$next[0:0]$9883 $2\logical_op__oe__oe$8$next[0:0]$9910 + assign $0\logical_op__oe__ok$9$next[0:0]$9884 $2\logical_op__oe__ok$9$next[0:0]$9911 + assign $0\logical_op__rc__ok$7$next[0:0]$9886 $2\logical_op__rc__ok$7$next[0:0]$9912 + assign $0\logical_op__rc__rc$6$next[0:0]$9887 $2\logical_op__rc__rc$6$next[0:0]$9913 + attribute \src "libresoc.v:171093.5-171093.29" switch \initial - attribute \src "libresoc.v:169065.9-169065.17" + attribute \src "libresoc.v:171093.9-171093.17" case 1'1 case end @@ -348864,7 +351587,7 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9850 $1\logical_op__data_len$18$next[3:0]$9845 $1\logical_op__is_signed$17$next[0:0]$9855 $1\logical_op__is_32bit$16$next[0:0]$9854 $1\logical_op__output_carry$15$next[0:0]$9858 $1\logical_op__write_cr0$14$next[0:0]$9861 $1\logical_op__invert_out$13$next[0:0]$9853 $1\logical_op__input_carry$12$next[1:0]$9849 $1\logical_op__zero_a$11$next[0:0]$9862 $1\logical_op__invert_in$10$next[0:0]$9852 $1\logical_op__oe__ok$9$next[0:0]$9857 $1\logical_op__oe__oe$8$next[0:0]$9856 $1\logical_op__rc__ok$7$next[0:0]$9859 $1\logical_op__rc__rc$6$next[0:0]$9860 $1\logical_op__imm_data__ok$5$next[0:0]$9848 $1\logical_op__imm_data__data$4$next[63:0]$9847 $1\logical_op__fn_unit$3$next[12:0]$9846 $1\logical_op__insn_type$2$next[6:0]$9851 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9895 $1\logical_op__data_len$18$next[3:0]$9890 $1\logical_op__is_signed$17$next[0:0]$9900 $1\logical_op__is_32bit$16$next[0:0]$9899 $1\logical_op__output_carry$15$next[0:0]$9903 $1\logical_op__write_cr0$14$next[0:0]$9906 $1\logical_op__invert_out$13$next[0:0]$9898 $1\logical_op__input_carry$12$next[1:0]$9894 $1\logical_op__zero_a$11$next[0:0]$9907 $1\logical_op__invert_in$10$next[0:0]$9897 $1\logical_op__oe__ok$9$next[0:0]$9902 $1\logical_op__oe__oe$8$next[0:0]$9901 $1\logical_op__rc__ok$7$next[0:0]$9904 $1\logical_op__rc__rc$6$next[0:0]$9905 $1\logical_op__imm_data__ok$5$next[0:0]$9893 $1\logical_op__imm_data__data$4$next[63:0]$9892 $1\logical_op__fn_unit$3$next[13:0]$9891 $1\logical_op__insn_type$2$next[6:0]$9896 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -348885,26 +351608,26 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9850 $1\logical_op__data_len$18$next[3:0]$9845 $1\logical_op__is_signed$17$next[0:0]$9855 $1\logical_op__is_32bit$16$next[0:0]$9854 $1\logical_op__output_carry$15$next[0:0]$9858 $1\logical_op__write_cr0$14$next[0:0]$9861 $1\logical_op__invert_out$13$next[0:0]$9853 $1\logical_op__input_carry$12$next[1:0]$9849 $1\logical_op__zero_a$11$next[0:0]$9862 $1\logical_op__invert_in$10$next[0:0]$9852 $1\logical_op__oe__ok$9$next[0:0]$9857 $1\logical_op__oe__oe$8$next[0:0]$9856 $1\logical_op__rc__ok$7$next[0:0]$9859 $1\logical_op__rc__rc$6$next[0:0]$9860 $1\logical_op__imm_data__ok$5$next[0:0]$9848 $1\logical_op__imm_data__data$4$next[63:0]$9847 $1\logical_op__fn_unit$3$next[12:0]$9846 $1\logical_op__insn_type$2$next[6:0]$9851 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9895 $1\logical_op__data_len$18$next[3:0]$9890 $1\logical_op__is_signed$17$next[0:0]$9900 $1\logical_op__is_32bit$16$next[0:0]$9899 $1\logical_op__output_carry$15$next[0:0]$9903 $1\logical_op__write_cr0$14$next[0:0]$9906 $1\logical_op__invert_out$13$next[0:0]$9898 $1\logical_op__input_carry$12$next[1:0]$9894 $1\logical_op__zero_a$11$next[0:0]$9907 $1\logical_op__invert_in$10$next[0:0]$9897 $1\logical_op__oe__ok$9$next[0:0]$9902 $1\logical_op__oe__oe$8$next[0:0]$9901 $1\logical_op__rc__ok$7$next[0:0]$9904 $1\logical_op__rc__rc$6$next[0:0]$9905 $1\logical_op__imm_data__ok$5$next[0:0]$9893 $1\logical_op__imm_data__data$4$next[63:0]$9892 $1\logical_op__fn_unit$3$next[13:0]$9891 $1\logical_op__insn_type$2$next[6:0]$9896 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } case - assign $1\logical_op__data_len$18$next[3:0]$9845 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[12:0]$9846 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9847 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9848 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9849 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9850 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9851 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9852 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9853 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9854 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9855 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9856 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9857 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9858 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9859 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9860 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9861 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9862 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$9890 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$9891 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9892 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9893 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9894 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9895 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9896 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9897 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9898 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9899 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9900 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9901 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9902 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9903 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9904 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9905 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9906 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9907 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -348916,41 +351639,41 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9863 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9864 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9868 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9867 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9865 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9866 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$9908 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9909 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9913 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9912 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9910 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9911 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$9863 $1\logical_op__imm_data__data$4$next[63:0]$9847 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9864 $1\logical_op__imm_data__ok$5$next[0:0]$9848 - assign $2\logical_op__oe__oe$8$next[0:0]$9865 $1\logical_op__oe__oe$8$next[0:0]$9856 - assign $2\logical_op__oe__ok$9$next[0:0]$9866 $1\logical_op__oe__ok$9$next[0:0]$9857 - assign $2\logical_op__rc__ok$7$next[0:0]$9867 $1\logical_op__rc__ok$7$next[0:0]$9859 - assign $2\logical_op__rc__rc$6$next[0:0]$9868 $1\logical_op__rc__rc$6$next[0:0]$9860 + assign $2\logical_op__imm_data__data$4$next[63:0]$9908 $1\logical_op__imm_data__data$4$next[63:0]$9892 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9909 $1\logical_op__imm_data__ok$5$next[0:0]$9893 + assign $2\logical_op__oe__oe$8$next[0:0]$9910 $1\logical_op__oe__oe$8$next[0:0]$9901 + assign $2\logical_op__oe__ok$9$next[0:0]$9911 $1\logical_op__oe__ok$9$next[0:0]$9902 + assign $2\logical_op__rc__ok$7$next[0:0]$9912 $1\logical_op__rc__ok$7$next[0:0]$9904 + assign $2\logical_op__rc__rc$6$next[0:0]$9913 $1\logical_op__rc__rc$6$next[0:0]$9905 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9827 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$9828 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9829 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9830 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9831 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9832 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9833 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9834 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9835 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9836 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9837 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9838 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9839 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9840 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9841 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9842 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9843 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9844 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9872 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9873 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9874 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9875 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9876 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9877 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9878 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9879 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9880 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9881 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9882 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9883 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9884 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9885 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9886 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9887 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9888 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9889 end - connect \$74 $and$libresoc.v:168786$9746_Y + connect \$74 $and$libresoc.v:170814$9791_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 @@ -348984,381 +351707,381 @@ module \pipe_end connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end -attribute \src "libresoc.v:169142.1-170123.10" +attribute \src "libresoc.v:171170.1-172157.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 - attribute \src "libresoc.v:170048.3-170062.6" - wire $0\div_by_zero$54$next[0:0]$10097 - attribute \src "libresoc.v:169165.7-169165.30" - wire $0\div_by_zero$54[0:0]$10114 - attribute \src "libresoc.v:169722.3-169723.47" - wire $0\div_by_zero$54[0:0]$9932 - attribute \src "libresoc.v:169844.3-169855.6" + attribute \src "libresoc.v:172082.3-172096.6" + wire $0\div_by_zero$54$next[0:0]$10142 + attribute \src "libresoc.v:171193.7-171193.30" + wire $0\div_by_zero$54[0:0]$10159 + attribute \src "libresoc.v:171756.3-171757.47" + wire $0\div_by_zero$54[0:0]$9977 + attribute \src "libresoc.v:171878.3-171889.6" wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:169832.3-169843.6" + attribute \src "libresoc.v:171866.3-171877.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:169820.3-169831.6" + attribute \src "libresoc.v:171854.3-171865.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:170018.3-170032.6" - wire $0\dive_abs_ov32$52$next[0:0]$10089 - attribute \src "libresoc.v:169189.7-169189.32" - wire $0\dive_abs_ov32$52[0:0]$10116 - attribute \src "libresoc.v:169726.3-169727.51" - wire $0\dive_abs_ov32$52[0:0]$9936 - attribute \src "libresoc.v:170033.3-170047.6" - wire $0\dive_abs_ov64$53$next[0:0]$10093 - attribute \src "libresoc.v:169197.7-169197.32" - wire $0\dive_abs_ov64$53[0:0]$10118 - attribute \src "libresoc.v:169724.3-169725.51" - wire $0\dive_abs_ov64$53[0:0]$9934 - attribute \src "libresoc.v:170063.3-170077.6" - wire width 128 $0\dividend$68$next[127:0]$10101 - attribute \src "libresoc.v:169203.15-169203.68" - wire width 128 $0\dividend$68[127:0]$10120 - attribute \src "libresoc.v:169720.3-169721.41" - wire width 128 $0\dividend$68[127:0]$9930 - attribute \src "libresoc.v:170003.3-170017.6" - wire $0\dividend_neg$51$next[0:0]$10085 - attribute \src "libresoc.v:169211.7-169211.31" - wire $0\dividend_neg$51[0:0]$10122 - attribute \src "libresoc.v:169728.3-169729.49" - wire $0\dividend_neg$51[0:0]$9938 - attribute \src "libresoc.v:169988.3-170002.6" - wire $0\divisor_neg$50$next[0:0]$10081 - attribute \src "libresoc.v:169219.7-169219.30" - wire $0\divisor_neg$50[0:0]$10124 - attribute \src "libresoc.v:169730.3-169731.47" - wire $0\divisor_neg$50[0:0]$9940 - attribute \src "libresoc.v:170078.3-170092.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$10105 - attribute \src "libresoc.v:169225.14-169225.58" - wire width 64 $0\divisor_radicand$65[63:0]$10126 - attribute \src "libresoc.v:169718.3-169719.57" - wire width 64 $0\divisor_radicand$65[63:0]$9928 - attribute \src "libresoc.v:169856.3-169883.6" - wire $0\empty$next[0:0]$9998 - attribute \src "libresoc.v:169776.3-169777.27" + attribute \src "libresoc.v:172052.3-172066.6" + wire $0\dive_abs_ov32$52$next[0:0]$10134 + attribute \src "libresoc.v:171217.7-171217.32" + wire $0\dive_abs_ov32$52[0:0]$10161 + attribute \src "libresoc.v:171760.3-171761.51" + wire $0\dive_abs_ov32$52[0:0]$9981 + attribute \src "libresoc.v:172067.3-172081.6" + wire $0\dive_abs_ov64$53$next[0:0]$10138 + attribute \src "libresoc.v:171225.7-171225.32" + wire $0\dive_abs_ov64$53[0:0]$10163 + attribute \src "libresoc.v:171758.3-171759.51" + wire $0\dive_abs_ov64$53[0:0]$9979 + attribute \src "libresoc.v:172097.3-172111.6" + wire width 128 $0\dividend$68$next[127:0]$10146 + attribute \src "libresoc.v:171231.15-171231.68" + wire width 128 $0\dividend$68[127:0]$10165 + attribute \src "libresoc.v:171754.3-171755.41" + wire width 128 $0\dividend$68[127:0]$9975 + attribute \src "libresoc.v:172037.3-172051.6" + wire $0\dividend_neg$51$next[0:0]$10130 + attribute \src "libresoc.v:171239.7-171239.31" + wire $0\dividend_neg$51[0:0]$10167 + attribute \src "libresoc.v:171762.3-171763.49" + wire $0\dividend_neg$51[0:0]$9983 + attribute \src "libresoc.v:172022.3-172036.6" + wire $0\divisor_neg$50$next[0:0]$10126 + attribute \src "libresoc.v:171247.7-171247.30" + wire $0\divisor_neg$50[0:0]$10169 + attribute \src "libresoc.v:171764.3-171765.47" + wire $0\divisor_neg$50[0:0]$9985 + attribute \src "libresoc.v:172112.3-172126.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10150 + attribute \src "libresoc.v:171253.14-171253.58" + wire width 64 $0\divisor_radicand$65[63:0]$10171 + attribute \src "libresoc.v:171752.3-171753.57" + wire width 64 $0\divisor_radicand$65[63:0]$9973 + attribute \src "libresoc.v:171890.3-171917.6" + wire $0\empty$next[0:0]$10043 + attribute \src "libresoc.v:171810.3-171811.27" wire $0\empty[0:0] - attribute \src "libresoc.v:169143.7-169143.20" + attribute \src "libresoc.v:171171.7-171171.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169899.3-169942.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$10008 - attribute \src "libresoc.v:169237.13-169237.45" - wire width 4 $0\logical_op__data_len$45[3:0]$10129 - attribute \src "libresoc.v:169770.3-169771.65" - wire width 4 $0\logical_op__data_len$45[3:0]$9980 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 13 $0\logical_op__fn_unit$30$next[12:0]$10009 - attribute \src "libresoc.v:169287.14-169287.49" - wire width 13 $0\logical_op__fn_unit$30[12:0]$10131 - attribute \src "libresoc.v:169740.3-169741.63" - wire width 13 $0\logical_op__fn_unit$30[12:0]$9950 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10010 - attribute \src "libresoc.v:169293.14-169293.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10133 - attribute \src "libresoc.v:169742.3-169743.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9952 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$10011 - attribute \src "libresoc.v:169301.7-169301.43" - wire $0\logical_op__imm_data__ok$32[0:0]$10135 - attribute \src "libresoc.v:169744.3-169745.73" - wire $0\logical_op__imm_data__ok$32[0:0]$9954 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$10012 - attribute \src "libresoc.v:169323.13-169323.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$10137 - attribute \src "libresoc.v:169758.3-169759.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$9968 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$10013 - attribute \src "libresoc.v:169331.14-169331.43" - wire width 32 $0\logical_op__insn$46[31:0]$10139 - attribute \src "libresoc.v:169772.3-169773.57" - wire width 32 $0\logical_op__insn$46[31:0]$9982 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$10014 - attribute \src "libresoc.v:169561.13-169561.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$10141 - attribute \src "libresoc.v:169738.3-169739.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$9948 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__invert_in$37$next[0:0]$10015 - attribute \src "libresoc.v:169569.7-169569.40" - wire $0\logical_op__invert_in$37[0:0]$10143 - attribute \src "libresoc.v:169754.3-169755.67" - wire $0\logical_op__invert_in$37[0:0]$9964 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__invert_out$40$next[0:0]$10016 - attribute \src "libresoc.v:169577.7-169577.41" - wire $0\logical_op__invert_out$40[0:0]$10145 - attribute \src "libresoc.v:169760.3-169761.69" - wire $0\logical_op__invert_out$40[0:0]$9970 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__is_32bit$43$next[0:0]$10017 - attribute \src "libresoc.v:169585.7-169585.39" - wire $0\logical_op__is_32bit$43[0:0]$10147 - attribute \src "libresoc.v:169766.3-169767.65" - wire $0\logical_op__is_32bit$43[0:0]$9976 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__is_signed$44$next[0:0]$10018 - attribute \src "libresoc.v:169593.7-169593.40" - wire $0\logical_op__is_signed$44[0:0]$10149 - attribute \src "libresoc.v:169768.3-169769.67" - wire $0\logical_op__is_signed$44[0:0]$9978 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__oe__oe$35$next[0:0]$10019 - attribute \src "libresoc.v:169599.7-169599.37" - wire $0\logical_op__oe__oe$35[0:0]$10151 - attribute \src "libresoc.v:169750.3-169751.61" - wire $0\logical_op__oe__oe$35[0:0]$9960 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__oe__ok$36$next[0:0]$10020 - attribute \src "libresoc.v:169607.7-169607.37" - wire $0\logical_op__oe__ok$36[0:0]$10153 - attribute \src "libresoc.v:169752.3-169753.61" - wire $0\logical_op__oe__ok$36[0:0]$9962 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__output_carry$42$next[0:0]$10021 - attribute \src "libresoc.v:169617.7-169617.43" - wire $0\logical_op__output_carry$42[0:0]$10155 - attribute \src "libresoc.v:169764.3-169765.73" - wire $0\logical_op__output_carry$42[0:0]$9974 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__rc__ok$34$next[0:0]$10022 - attribute \src "libresoc.v:169623.7-169623.37" - wire $0\logical_op__rc__ok$34[0:0]$10157 - attribute \src "libresoc.v:169748.3-169749.61" - wire $0\logical_op__rc__ok$34[0:0]$9958 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__rc__rc$33$next[0:0]$10023 - attribute \src "libresoc.v:169631.7-169631.37" - wire $0\logical_op__rc__rc$33[0:0]$10159 - attribute \src "libresoc.v:169746.3-169747.61" - wire $0\logical_op__rc__rc$33[0:0]$9956 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__write_cr0$41$next[0:0]$10024 - attribute \src "libresoc.v:169641.7-169641.40" - wire $0\logical_op__write_cr0$41[0:0]$10161 - attribute \src "libresoc.v:169762.3-169763.67" - wire $0\logical_op__write_cr0$41[0:0]$9972 - attribute \src "libresoc.v:169899.3-169942.6" - wire $0\logical_op__zero_a$38$next[0:0]$10025 - attribute \src "libresoc.v:169649.7-169649.37" - wire $0\logical_op__zero_a$38[0:0]$10163 - attribute \src "libresoc.v:169756.3-169757.61" - wire $0\logical_op__zero_a$38[0:0]$9966 - attribute \src "libresoc.v:169884.3-169898.6" - wire width 2 $0\muxid$28$next[1:0]$10004 - attribute \src "libresoc.v:169657.13-169657.30" - wire width 2 $0\muxid$28[1:0]$10165 - attribute \src "libresoc.v:169774.3-169775.35" - wire width 2 $0\muxid$28[1:0]$9984 - attribute \src "libresoc.v:170093.3-170107.6" - wire width 2 $0\operation$69$next[1:0]$10109 - attribute \src "libresoc.v:169667.13-169667.34" - wire width 2 $0\operation$69[1:0]$10167 - attribute \src "libresoc.v:169716.3-169717.43" - wire width 2 $0\operation$69[1:0]$9926 - attribute \src "libresoc.v:169943.3-169957.6" - wire width 64 $0\ra$47$next[63:0]$10069 - attribute \src "libresoc.v:169681.14-169681.44" - wire width 64 $0\ra$47[63:0]$10169 - attribute \src "libresoc.v:169736.3-169737.29" - wire width 64 $0\ra$47[63:0]$9946 - attribute \src "libresoc.v:169958.3-169972.6" - wire width 64 $0\rb$48$next[63:0]$10073 - attribute \src "libresoc.v:169689.14-169689.44" - wire width 64 $0\rb$48[63:0]$10171 - attribute \src "libresoc.v:169734.3-169735.29" - wire width 64 $0\rb$48[63:0]$9944 - attribute \src "libresoc.v:169811.3-169819.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$9992 - attribute \src "libresoc.v:169778.3-169779.75" + attribute \src "libresoc.v:171933.3-171976.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10053 + attribute \src "libresoc.v:171804.3-171805.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10025 + attribute \src "libresoc.v:171265.13-171265.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10174 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10054 + attribute \src "libresoc.v:171318.14-171318.49" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10176 + attribute \src "libresoc.v:171774.3-171775.63" + wire width 14 $0\logical_op__fn_unit$30[13:0]$9995 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10055 + attribute \src "libresoc.v:171324.14-171324.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10178 + attribute \src "libresoc.v:171776.3-171777.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9997 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10056 + attribute \src "libresoc.v:171332.7-171332.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10180 + attribute \src "libresoc.v:171778.3-171779.73" + wire $0\logical_op__imm_data__ok$32[0:0]$9999 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10057 + attribute \src "libresoc.v:171792.3-171793.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$10013 + attribute \src "libresoc.v:171354.13-171354.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10182 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10058 + attribute \src "libresoc.v:171806.3-171807.57" + wire width 32 $0\logical_op__insn$46[31:0]$10027 + attribute \src "libresoc.v:171362.14-171362.43" + wire width 32 $0\logical_op__insn$46[31:0]$10184 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10059 + attribute \src "libresoc.v:171595.13-171595.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10186 + attribute \src "libresoc.v:171772.3-171773.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$9993 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__invert_in$37$next[0:0]$10060 + attribute \src "libresoc.v:171788.3-171789.67" + wire $0\logical_op__invert_in$37[0:0]$10009 + attribute \src "libresoc.v:171603.7-171603.40" + wire $0\logical_op__invert_in$37[0:0]$10188 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__invert_out$40$next[0:0]$10061 + attribute \src "libresoc.v:171794.3-171795.69" + wire $0\logical_op__invert_out$40[0:0]$10015 + attribute \src "libresoc.v:171611.7-171611.41" + wire $0\logical_op__invert_out$40[0:0]$10190 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10062 + attribute \src "libresoc.v:171800.3-171801.65" + wire $0\logical_op__is_32bit$43[0:0]$10021 + attribute \src "libresoc.v:171619.7-171619.39" + wire $0\logical_op__is_32bit$43[0:0]$10192 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__is_signed$44$next[0:0]$10063 + attribute \src "libresoc.v:171802.3-171803.67" + wire $0\logical_op__is_signed$44[0:0]$10023 + attribute \src "libresoc.v:171627.7-171627.40" + wire $0\logical_op__is_signed$44[0:0]$10194 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10064 + attribute \src "libresoc.v:171784.3-171785.61" + wire $0\logical_op__oe__oe$35[0:0]$10005 + attribute \src "libresoc.v:171633.7-171633.37" + wire $0\logical_op__oe__oe$35[0:0]$10196 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10065 + attribute \src "libresoc.v:171786.3-171787.61" + wire $0\logical_op__oe__ok$36[0:0]$10007 + attribute \src "libresoc.v:171641.7-171641.37" + wire $0\logical_op__oe__ok$36[0:0]$10198 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__output_carry$42$next[0:0]$10066 + attribute \src "libresoc.v:171798.3-171799.73" + wire $0\logical_op__output_carry$42[0:0]$10019 + attribute \src "libresoc.v:171651.7-171651.43" + wire $0\logical_op__output_carry$42[0:0]$10200 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10067 + attribute \src "libresoc.v:171782.3-171783.61" + wire $0\logical_op__rc__ok$34[0:0]$10003 + attribute \src "libresoc.v:171657.7-171657.37" + wire $0\logical_op__rc__ok$34[0:0]$10202 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10068 + attribute \src "libresoc.v:171780.3-171781.61" + wire $0\logical_op__rc__rc$33[0:0]$10001 + attribute \src "libresoc.v:171665.7-171665.37" + wire $0\logical_op__rc__rc$33[0:0]$10204 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10069 + attribute \src "libresoc.v:171796.3-171797.67" + wire $0\logical_op__write_cr0$41[0:0]$10017 + attribute \src "libresoc.v:171675.7-171675.40" + wire $0\logical_op__write_cr0$41[0:0]$10206 + attribute \src "libresoc.v:171933.3-171976.6" + wire $0\logical_op__zero_a$38$next[0:0]$10070 + attribute \src "libresoc.v:171790.3-171791.61" + wire $0\logical_op__zero_a$38[0:0]$10011 + attribute \src "libresoc.v:171683.7-171683.37" + wire $0\logical_op__zero_a$38[0:0]$10208 + attribute \src "libresoc.v:171918.3-171932.6" + wire width 2 $0\muxid$28$next[1:0]$10049 + attribute \src "libresoc.v:171808.3-171809.35" + wire width 2 $0\muxid$28[1:0]$10029 + attribute \src "libresoc.v:171691.13-171691.30" + wire width 2 $0\muxid$28[1:0]$10210 + attribute \src "libresoc.v:172127.3-172141.6" + wire width 2 $0\operation$69$next[1:0]$10154 + attribute \src "libresoc.v:171701.13-171701.34" + wire width 2 $0\operation$69[1:0]$10212 + attribute \src "libresoc.v:171750.3-171751.43" + wire width 2 $0\operation$69[1:0]$9971 + attribute \src "libresoc.v:171977.3-171991.6" + wire width 64 $0\ra$47$next[63:0]$10114 + attribute \src "libresoc.v:171715.14-171715.44" + wire width 64 $0\ra$47[63:0]$10214 + attribute \src "libresoc.v:171770.3-171771.29" + wire width 64 $0\ra$47[63:0]$9991 + attribute \src "libresoc.v:171992.3-172006.6" + wire width 64 $0\rb$48$next[63:0]$10118 + attribute \src "libresoc.v:171723.14-171723.44" + wire width 64 $0\rb$48[63:0]$10216 + attribute \src "libresoc.v:171768.3-171769.29" + wire width 64 $0\rb$48[63:0]$9989 + attribute \src "libresoc.v:171845.3-171853.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10037 + attribute \src "libresoc.v:171812.3-171813.75" wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:169802.3-169810.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$9989 - attribute \src "libresoc.v:169780.3-169781.65" + attribute \src "libresoc.v:171836.3-171844.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10034 + attribute \src "libresoc.v:171814.3-171815.65" wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:169973.3-169987.6" - wire $0\xer_so$49$next[0:0]$10077 - attribute \src "libresoc.v:169707.7-169707.25" - wire $0\xer_so$49[0:0]$10175 - attribute \src "libresoc.v:169732.3-169733.37" - wire $0\xer_so$49[0:0]$9942 - attribute \src "libresoc.v:170048.3-170062.6" - wire $1\div_by_zero$54$next[0:0]$10098 - attribute \src "libresoc.v:169844.3-169855.6" + attribute \src "libresoc.v:172007.3-172021.6" + wire $0\xer_so$49$next[0:0]$10122 + attribute \src "libresoc.v:171741.7-171741.25" + wire $0\xer_so$49[0:0]$10220 + attribute \src "libresoc.v:171766.3-171767.37" + wire $0\xer_so$49[0:0]$9987 + attribute \src "libresoc.v:172082.3-172096.6" + wire $1\div_by_zero$54$next[0:0]$10143 + attribute \src "libresoc.v:171878.3-171889.6" wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:169832.3-169843.6" + attribute \src "libresoc.v:171866.3-171877.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:169820.3-169831.6" + attribute \src "libresoc.v:171854.3-171865.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:170018.3-170032.6" - wire $1\dive_abs_ov32$52$next[0:0]$10090 - attribute \src "libresoc.v:170033.3-170047.6" - wire $1\dive_abs_ov64$53$next[0:0]$10094 - attribute \src "libresoc.v:170063.3-170077.6" - wire width 128 $1\dividend$68$next[127:0]$10102 - attribute \src "libresoc.v:170003.3-170017.6" - wire $1\dividend_neg$51$next[0:0]$10086 - attribute \src "libresoc.v:169988.3-170002.6" - wire $1\divisor_neg$50$next[0:0]$10082 - attribute \src "libresoc.v:170078.3-170092.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$10106 - attribute \src "libresoc.v:169856.3-169883.6" - wire $1\empty$next[0:0]$9999 - attribute \src "libresoc.v:169229.7-169229.19" + attribute \src "libresoc.v:172052.3-172066.6" + wire $1\dive_abs_ov32$52$next[0:0]$10135 + attribute \src "libresoc.v:172067.3-172081.6" + wire $1\dive_abs_ov64$53$next[0:0]$10139 + attribute \src "libresoc.v:172097.3-172111.6" + wire width 128 $1\dividend$68$next[127:0]$10147 + attribute \src "libresoc.v:172037.3-172051.6" + wire $1\dividend_neg$51$next[0:0]$10131 + attribute \src "libresoc.v:172022.3-172036.6" + wire $1\divisor_neg$50$next[0:0]$10127 + attribute \src "libresoc.v:172112.3-172126.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10151 + attribute \src "libresoc.v:171890.3-171917.6" + wire $1\empty$next[0:0]$10044 + attribute \src "libresoc.v:171257.7-171257.19" wire $1\empty[0:0] - attribute \src "libresoc.v:169899.3-169942.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$10026 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 13 $1\logical_op__fn_unit$30$next[12:0]$10027 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10028 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$10029 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$10030 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$10031 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$10032 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__invert_in$37$next[0:0]$10033 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__invert_out$40$next[0:0]$10034 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__is_32bit$43$next[0:0]$10035 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__is_signed$44$next[0:0]$10036 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__oe__oe$35$next[0:0]$10037 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__oe__ok$36$next[0:0]$10038 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__output_carry$42$next[0:0]$10039 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__rc__ok$34$next[0:0]$10040 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__rc__rc$33$next[0:0]$10041 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__write_cr0$41$next[0:0]$10042 - attribute \src "libresoc.v:169899.3-169942.6" - wire $1\logical_op__zero_a$38$next[0:0]$10043 - attribute \src "libresoc.v:169884.3-169898.6" - wire width 2 $1\muxid$28$next[1:0]$10005 - attribute \src "libresoc.v:170093.3-170107.6" - wire width 2 $1\operation$69$next[1:0]$10110 - attribute \src "libresoc.v:169943.3-169957.6" - wire width 64 $1\ra$47$next[63:0]$10070 - attribute \src "libresoc.v:169958.3-169972.6" - wire width 64 $1\rb$48$next[63:0]$10074 - attribute \src "libresoc.v:169811.3-169819.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$9993 - attribute \src "libresoc.v:169695.15-169695.84" + attribute \src "libresoc.v:171933.3-171976.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10071 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10072 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10073 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10074 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10075 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10076 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10077 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__invert_in$37$next[0:0]$10078 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__invert_out$40$next[0:0]$10079 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10080 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__is_signed$44$next[0:0]$10081 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10082 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10083 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__output_carry$42$next[0:0]$10084 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10085 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10086 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10087 + attribute \src "libresoc.v:171933.3-171976.6" + wire $1\logical_op__zero_a$38$next[0:0]$10088 + attribute \src "libresoc.v:171918.3-171932.6" + wire width 2 $1\muxid$28$next[1:0]$10050 + attribute \src "libresoc.v:172127.3-172141.6" + wire width 2 $1\operation$69$next[1:0]$10155 + attribute \src "libresoc.v:171977.3-171991.6" + wire width 64 $1\ra$47$next[63:0]$10115 + attribute \src "libresoc.v:171992.3-172006.6" + wire width 64 $1\rb$48$next[63:0]$10119 + attribute \src "libresoc.v:171845.3-171853.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10038 + attribute \src "libresoc.v:171729.15-171729.84" wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:169802.3-169810.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$9990 - attribute \src "libresoc.v:169699.13-169699.45" + attribute \src "libresoc.v:171836.3-171844.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10035 + attribute \src "libresoc.v:171733.13-171733.45" wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:169973.3-169987.6" - wire $1\xer_so$49$next[0:0]$10078 - attribute \src "libresoc.v:170048.3-170062.6" - wire $2\div_by_zero$54$next[0:0]$10099 - attribute \src "libresoc.v:170018.3-170032.6" - wire $2\dive_abs_ov32$52$next[0:0]$10091 - attribute \src "libresoc.v:170033.3-170047.6" - wire $2\dive_abs_ov64$53$next[0:0]$10095 - attribute \src "libresoc.v:170063.3-170077.6" - wire width 128 $2\dividend$68$next[127:0]$10103 - attribute \src "libresoc.v:170003.3-170017.6" - wire $2\dividend_neg$51$next[0:0]$10087 - attribute \src "libresoc.v:169988.3-170002.6" - wire $2\divisor_neg$50$next[0:0]$10083 - attribute \src "libresoc.v:170078.3-170092.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$10107 - attribute \src "libresoc.v:169856.3-169883.6" - wire $2\empty$next[0:0]$10000 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$10044 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 13 $2\logical_op__fn_unit$30$next[12:0]$10045 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10046 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$10047 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 2 $2\logical_op__input_carry$39$next[1:0]$10048 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 32 $2\logical_op__insn$46$next[31:0]$10049 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 7 $2\logical_op__insn_type$29$next[6:0]$10050 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__invert_in$37$next[0:0]$10051 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__invert_out$40$next[0:0]$10052 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__is_32bit$43$next[0:0]$10053 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__is_signed$44$next[0:0]$10054 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__oe__oe$35$next[0:0]$10055 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__oe__ok$36$next[0:0]$10056 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__output_carry$42$next[0:0]$10057 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__rc__ok$34$next[0:0]$10058 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__rc__rc$33$next[0:0]$10059 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__write_cr0$41$next[0:0]$10060 - attribute \src "libresoc.v:169899.3-169942.6" - wire $2\logical_op__zero_a$38$next[0:0]$10061 - attribute \src "libresoc.v:169884.3-169898.6" - wire width 2 $2\muxid$28$next[1:0]$10006 - attribute \src "libresoc.v:170093.3-170107.6" - wire width 2 $2\operation$69$next[1:0]$10111 - attribute \src "libresoc.v:169943.3-169957.6" - wire width 64 $2\ra$47$next[63:0]$10071 - attribute \src "libresoc.v:169958.3-169972.6" - wire width 64 $2\rb$48$next[63:0]$10075 - attribute \src "libresoc.v:169973.3-169987.6" - wire $2\xer_so$49$next[0:0]$10079 - attribute \src "libresoc.v:169856.3-169883.6" - wire $3\empty$next[0:0]$10001 - attribute \src "libresoc.v:169899.3-169942.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10062 - attribute \src "libresoc.v:169899.3-169942.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$10063 - attribute \src "libresoc.v:169899.3-169942.6" - wire $3\logical_op__oe__oe$35$next[0:0]$10064 - attribute \src "libresoc.v:169899.3-169942.6" - wire $3\logical_op__oe__ok$36$next[0:0]$10065 - attribute \src "libresoc.v:169899.3-169942.6" - wire $3\logical_op__rc__ok$34$next[0:0]$10066 - attribute \src "libresoc.v:169899.3-169942.6" - wire $3\logical_op__rc__rc$33$next[0:0]$10067 - attribute \src "libresoc.v:169856.3-169883.6" - wire $4\empty$next[0:0]$10002 - attribute \src "libresoc.v:169714.18-169714.98" - wire $and$libresoc.v:169714$9923_Y - attribute \src "libresoc.v:169715.18-169715.107" - wire $and$libresoc.v:169715$9924_Y - attribute \src "libresoc.v:169711.18-169711.92" - wire width 192 $extend$libresoc.v:169711$9919_Y - attribute \src "libresoc.v:169713.18-169713.119" - wire $ge$libresoc.v:169713$9922_Y - attribute \src "libresoc.v:169712.18-169712.93" - wire $not$libresoc.v:169712$9921_Y - attribute \src "libresoc.v:169711.18-169711.92" - wire width 192 $pos$libresoc.v:169711$9920_Y - attribute \src "libresoc.v:169710.18-169710.138" - wire width 191 $sshl$libresoc.v:169710$9918_Y + attribute \src "libresoc.v:172007.3-172021.6" + wire $1\xer_so$49$next[0:0]$10123 + attribute \src "libresoc.v:172082.3-172096.6" + wire $2\div_by_zero$54$next[0:0]$10144 + attribute \src "libresoc.v:172052.3-172066.6" + wire $2\dive_abs_ov32$52$next[0:0]$10136 + attribute \src "libresoc.v:172067.3-172081.6" + wire $2\dive_abs_ov64$53$next[0:0]$10140 + attribute \src "libresoc.v:172097.3-172111.6" + wire width 128 $2\dividend$68$next[127:0]$10148 + attribute \src "libresoc.v:172037.3-172051.6" + wire $2\dividend_neg$51$next[0:0]$10132 + attribute \src "libresoc.v:172022.3-172036.6" + wire $2\divisor_neg$50$next[0:0]$10128 + attribute \src "libresoc.v:172112.3-172126.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10152 + attribute \src "libresoc.v:171890.3-171917.6" + wire $2\empty$next[0:0]$10045 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10089 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10090 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10091 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10092 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10093 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10094 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10095 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__invert_in$37$next[0:0]$10096 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__invert_out$40$next[0:0]$10097 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10098 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__is_signed$44$next[0:0]$10099 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10100 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10101 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__output_carry$42$next[0:0]$10102 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10103 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10104 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10105 + attribute \src "libresoc.v:171933.3-171976.6" + wire $2\logical_op__zero_a$38$next[0:0]$10106 + attribute \src "libresoc.v:171918.3-171932.6" + wire width 2 $2\muxid$28$next[1:0]$10051 + attribute \src "libresoc.v:172127.3-172141.6" + wire width 2 $2\operation$69$next[1:0]$10156 + attribute \src "libresoc.v:171977.3-171991.6" + wire width 64 $2\ra$47$next[63:0]$10116 + attribute \src "libresoc.v:171992.3-172006.6" + wire width 64 $2\rb$48$next[63:0]$10120 + attribute \src "libresoc.v:172007.3-172021.6" + wire $2\xer_so$49$next[0:0]$10124 + attribute \src "libresoc.v:171890.3-171917.6" + wire $3\empty$next[0:0]$10046 + attribute \src "libresoc.v:171933.3-171976.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10107 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10108 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10109 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10110 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10111 + attribute \src "libresoc.v:171933.3-171976.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10112 + attribute \src "libresoc.v:171890.3-171917.6" + wire $4\empty$next[0:0]$10047 + attribute \src "libresoc.v:171748.18-171748.98" + wire $and$libresoc.v:171748$9968_Y + attribute \src "libresoc.v:171749.18-171749.107" + wire $and$libresoc.v:171749$9969_Y + attribute \src "libresoc.v:171745.18-171745.92" + wire width 192 $extend$libresoc.v:171745$9964_Y + attribute \src "libresoc.v:171747.18-171747.119" + wire $ge$libresoc.v:171747$9967_Y + attribute \src "libresoc.v:171746.18-171746.93" + wire $not$libresoc.v:171746$9966_Y + attribute \src "libresoc.v:171745.18-171745.92" + wire width 192 $pos$libresoc.v:171745$9965_Y + attribute \src "libresoc.v:171744.18-171744.138" + wire width 191 $sshl$libresoc.v:171744$9963_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" @@ -349371,9 +352094,9 @@ module \pipe_middle_0 wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -349447,7 +352170,7 @@ module \pipe_middle_0 wire \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next - attribute \src "libresoc.v:169143.7-169143.15" + attribute \src "libresoc.v:171171.7-171171.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -349458,55 +352181,58 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$45$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 38 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 38 \logical_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$30$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$30$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -349625,6 +352351,7 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -349701,6 +352428,7 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 37 \logical_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -349777,6 +352505,7 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -349928,7 +352657,7 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:169714$9923 + cell $and $and$libresoc.v:171748$9968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349936,10 +352665,10 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:169714$9923_Y + connect \Y $and$libresoc.v:171748$9968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:169715$9924 + cell $and $and$libresoc.v:171749$9969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349947,18 +352676,18 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:169715$9924_Y + connect \Y $and$libresoc.v:171749$9969_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:169711$9919 + cell $pos $extend$libresoc.v:171745$9964 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 - connect \Y $extend$libresoc.v:169711$9919_Y + connect \Y $extend$libresoc.v:171745$9964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:169713$9922 + cell $ge $ge$libresoc.v:171747$9967 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -349966,26 +352695,26 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \saved_state_q_bits_known connect \B 6'111111 - connect \Y $ge$libresoc.v:169713$9922_Y + connect \Y $ge$libresoc.v:171747$9967_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:169712$9921 + cell $not $not$libresoc.v:171746$9966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $not$libresoc.v:169712$9921_Y + connect \Y $not$libresoc.v:171746$9966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:169711$9920 + cell $pos $pos$libresoc.v:171745$9965 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:169711$9919_Y - connect \Y $pos$libresoc.v:169711$9920_Y + connect \A $extend$libresoc.v:171745$9964_Y + connect \Y $pos$libresoc.v:171745$9965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:169710$9918 + cell $sshl $sshl$libresoc.v:171744$9963 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -349993,17 +352722,17 @@ module \pipe_middle_0 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 - connect \Y $sshl$libresoc.v:169710$9918_Y + connect \Y $sshl$libresoc.v:171744$9963_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:169782.18-169786.4" + attribute \src "libresoc.v:171816.18-171820.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:169787.18-169793.4" + attribute \src "libresoc.v:171821.18-171827.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient @@ -350012,528 +352741,528 @@ module \pipe_middle_0 connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:169794.10-169797.4" + attribute \src "libresoc.v:171828.10-171831.4" cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:169798.10-169801.4" + attribute \src "libresoc.v:171832.10-171835.4" cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:169143.7-169143.20" - process $proc$libresoc.v:169143$10112 + attribute \src "libresoc.v:171171.7-171171.20" + process $proc$libresoc.v:171171$10157 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169165.7-169165.30" - process $proc$libresoc.v:169165$10113 + attribute \src "libresoc.v:171193.7-171193.30" + process $proc$libresoc.v:171193$10158 assign { } { } - assign $0\div_by_zero$54[0:0]$10114 1'0 + assign $0\div_by_zero$54[0:0]$10159 1'0 sync always sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10114 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10159 end - attribute \src "libresoc.v:169189.7-169189.32" - process $proc$libresoc.v:169189$10115 + attribute \src "libresoc.v:171217.7-171217.32" + process $proc$libresoc.v:171217$10160 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10116 1'0 + assign $0\dive_abs_ov32$52[0:0]$10161 1'0 sync always sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10116 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10161 end - attribute \src "libresoc.v:169197.7-169197.32" - process $proc$libresoc.v:169197$10117 + attribute \src "libresoc.v:171225.7-171225.32" + process $proc$libresoc.v:171225$10162 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10118 1'0 + assign $0\dive_abs_ov64$53[0:0]$10163 1'0 sync always sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10118 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10163 end - attribute \src "libresoc.v:169203.15-169203.68" - process $proc$libresoc.v:169203$10119 + attribute \src "libresoc.v:171231.15-171231.68" + process $proc$libresoc.v:171231$10164 assign { } { } - assign $0\dividend$68[127:0]$10120 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\dividend$68[127:0]$10165 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \dividend$68 $0\dividend$68[127:0]$10120 + update \dividend$68 $0\dividend$68[127:0]$10165 end - attribute \src "libresoc.v:169211.7-169211.31" - process $proc$libresoc.v:169211$10121 + attribute \src "libresoc.v:171239.7-171239.31" + process $proc$libresoc.v:171239$10166 assign { } { } - assign $0\dividend_neg$51[0:0]$10122 1'0 + assign $0\dividend_neg$51[0:0]$10167 1'0 sync always sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10122 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10167 end - attribute \src "libresoc.v:169219.7-169219.30" - process $proc$libresoc.v:169219$10123 + attribute \src "libresoc.v:171247.7-171247.30" + process $proc$libresoc.v:171247$10168 assign { } { } - assign $0\divisor_neg$50[0:0]$10124 1'0 + assign $0\divisor_neg$50[0:0]$10169 1'0 sync always sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10124 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10169 end - attribute \src "libresoc.v:169225.14-169225.58" - process $proc$libresoc.v:169225$10125 + attribute \src "libresoc.v:171253.14-171253.58" + process $proc$libresoc.v:171253$10170 assign { } { } - assign $0\divisor_radicand$65[63:0]$10126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\divisor_radicand$65[63:0]$10171 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10126 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10171 end - attribute \src "libresoc.v:169229.7-169229.19" - process $proc$libresoc.v:169229$10127 + attribute \src "libresoc.v:171257.7-171257.19" + process $proc$libresoc.v:171257$10172 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end - attribute \src "libresoc.v:169237.13-169237.45" - process $proc$libresoc.v:169237$10128 + attribute \src "libresoc.v:171265.13-171265.45" + process $proc$libresoc.v:171265$10173 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10129 4'0000 + assign $0\logical_op__data_len$45[3:0]$10174 4'0000 sync always sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10129 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10174 end - attribute \src "libresoc.v:169287.14-169287.49" - process $proc$libresoc.v:169287$10130 + attribute \src "libresoc.v:171318.14-171318.49" + process $proc$libresoc.v:171318$10175 assign { } { } - assign $0\logical_op__fn_unit$30[12:0]$10131 13'0000000000000 + assign $0\logical_op__fn_unit$30[13:0]$10176 14'00000000000000 sync always sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10131 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10176 end - attribute \src "libresoc.v:169293.14-169293.68" - process $proc$libresoc.v:169293$10132 + attribute \src "libresoc.v:171324.14-171324.68" + process $proc$libresoc.v:171324$10177 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10133 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$31[63:0]$10178 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10133 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10178 end - attribute \src "libresoc.v:169301.7-169301.43" - process $proc$libresoc.v:169301$10134 + attribute \src "libresoc.v:171332.7-171332.43" + process $proc$libresoc.v:171332$10179 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10135 1'0 + assign $0\logical_op__imm_data__ok$32[0:0]$10180 1'0 sync always sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10135 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10180 end - attribute \src "libresoc.v:169323.13-169323.48" - process $proc$libresoc.v:169323$10136 + attribute \src "libresoc.v:171354.13-171354.48" + process $proc$libresoc.v:171354$10181 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10137 2'00 + assign $0\logical_op__input_carry$39[1:0]$10182 2'00 sync always sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10137 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10182 end - attribute \src "libresoc.v:169331.14-169331.43" - process $proc$libresoc.v:169331$10138 + attribute \src "libresoc.v:171362.14-171362.43" + process $proc$libresoc.v:171362$10183 assign { } { } - assign $0\logical_op__insn$46[31:0]$10139 0 + assign $0\logical_op__insn$46[31:0]$10184 0 sync always sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10139 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10184 end - attribute \src "libresoc.v:169561.13-169561.47" - process $proc$libresoc.v:169561$10140 + attribute \src "libresoc.v:171595.13-171595.47" + process $proc$libresoc.v:171595$10185 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10141 7'0000000 + assign $0\logical_op__insn_type$29[6:0]$10186 7'0000000 sync always sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10141 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10186 end - attribute \src "libresoc.v:169569.7-169569.40" - process $proc$libresoc.v:169569$10142 + attribute \src "libresoc.v:171603.7-171603.40" + process $proc$libresoc.v:171603$10187 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10143 1'0 + assign $0\logical_op__invert_in$37[0:0]$10188 1'0 sync always sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10143 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10188 end - attribute \src "libresoc.v:169577.7-169577.41" - process $proc$libresoc.v:169577$10144 + attribute \src "libresoc.v:171611.7-171611.41" + process $proc$libresoc.v:171611$10189 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10145 1'0 + assign $0\logical_op__invert_out$40[0:0]$10190 1'0 sync always sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10145 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10190 end - attribute \src "libresoc.v:169585.7-169585.39" - process $proc$libresoc.v:169585$10146 + attribute \src "libresoc.v:171619.7-171619.39" + process $proc$libresoc.v:171619$10191 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10147 1'0 + assign $0\logical_op__is_32bit$43[0:0]$10192 1'0 sync always sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10147 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10192 end - attribute \src "libresoc.v:169593.7-169593.40" - process $proc$libresoc.v:169593$10148 + attribute \src "libresoc.v:171627.7-171627.40" + process $proc$libresoc.v:171627$10193 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10149 1'0 + assign $0\logical_op__is_signed$44[0:0]$10194 1'0 sync always sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10149 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10194 end - attribute \src "libresoc.v:169599.7-169599.37" - process $proc$libresoc.v:169599$10150 + attribute \src "libresoc.v:171633.7-171633.37" + process $proc$libresoc.v:171633$10195 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10151 1'0 + assign $0\logical_op__oe__oe$35[0:0]$10196 1'0 sync always sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10151 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10196 end - attribute \src "libresoc.v:169607.7-169607.37" - process $proc$libresoc.v:169607$10152 + attribute \src "libresoc.v:171641.7-171641.37" + process $proc$libresoc.v:171641$10197 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10153 1'0 + assign $0\logical_op__oe__ok$36[0:0]$10198 1'0 sync always sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10153 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10198 end - attribute \src "libresoc.v:169617.7-169617.43" - process $proc$libresoc.v:169617$10154 + attribute \src "libresoc.v:171651.7-171651.43" + process $proc$libresoc.v:171651$10199 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10155 1'0 + assign $0\logical_op__output_carry$42[0:0]$10200 1'0 sync always sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10155 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10200 end - attribute \src "libresoc.v:169623.7-169623.37" - process $proc$libresoc.v:169623$10156 + attribute \src "libresoc.v:171657.7-171657.37" + process $proc$libresoc.v:171657$10201 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10157 1'0 + assign $0\logical_op__rc__ok$34[0:0]$10202 1'0 sync always sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10157 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10202 end - attribute \src "libresoc.v:169631.7-169631.37" - process $proc$libresoc.v:169631$10158 + attribute \src "libresoc.v:171665.7-171665.37" + process $proc$libresoc.v:171665$10203 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10159 1'0 + assign $0\logical_op__rc__rc$33[0:0]$10204 1'0 sync always sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10159 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10204 end - attribute \src "libresoc.v:169641.7-169641.40" - process $proc$libresoc.v:169641$10160 + attribute \src "libresoc.v:171675.7-171675.40" + process $proc$libresoc.v:171675$10205 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10161 1'0 + assign $0\logical_op__write_cr0$41[0:0]$10206 1'0 sync always sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10161 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10206 end - attribute \src "libresoc.v:169649.7-169649.37" - process $proc$libresoc.v:169649$10162 + attribute \src "libresoc.v:171683.7-171683.37" + process $proc$libresoc.v:171683$10207 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10163 1'0 + assign $0\logical_op__zero_a$38[0:0]$10208 1'0 sync always sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10163 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10208 end - attribute \src "libresoc.v:169657.13-169657.30" - process $proc$libresoc.v:169657$10164 + attribute \src "libresoc.v:171691.13-171691.30" + process $proc$libresoc.v:171691$10209 assign { } { } - assign $0\muxid$28[1:0]$10165 2'00 + assign $0\muxid$28[1:0]$10210 2'00 sync always sync init - update \muxid$28 $0\muxid$28[1:0]$10165 + update \muxid$28 $0\muxid$28[1:0]$10210 end - attribute \src "libresoc.v:169667.13-169667.34" - process $proc$libresoc.v:169667$10166 + attribute \src "libresoc.v:171701.13-171701.34" + process $proc$libresoc.v:171701$10211 assign { } { } - assign $0\operation$69[1:0]$10167 2'00 + assign $0\operation$69[1:0]$10212 2'00 sync always sync init - update \operation$69 $0\operation$69[1:0]$10167 + update \operation$69 $0\operation$69[1:0]$10212 end - attribute \src "libresoc.v:169681.14-169681.44" - process $proc$libresoc.v:169681$10168 + attribute \src "libresoc.v:171715.14-171715.44" + process $proc$libresoc.v:171715$10213 assign { } { } - assign $0\ra$47[63:0]$10169 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\ra$47[63:0]$10214 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \ra$47 $0\ra$47[63:0]$10169 + update \ra$47 $0\ra$47[63:0]$10214 end - attribute \src "libresoc.v:169689.14-169689.44" - process $proc$libresoc.v:169689$10170 + attribute \src "libresoc.v:171723.14-171723.44" + process $proc$libresoc.v:171723$10215 assign { } { } - assign $0\rb$48[63:0]$10171 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\rb$48[63:0]$10216 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \rb$48 $0\rb$48[63:0]$10171 + update \rb$48 $0\rb$48[63:0]$10216 end - attribute \src "libresoc.v:169695.15-169695.84" - process $proc$libresoc.v:169695$10172 + attribute \src "libresoc.v:171729.15-171729.84" + process $proc$libresoc.v:171729$10217 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:169699.13-169699.45" - process $proc$libresoc.v:169699$10173 + attribute \src "libresoc.v:171733.13-171733.45" + process $proc$libresoc.v:171733$10218 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:169707.7-169707.25" - process $proc$libresoc.v:169707$10174 + attribute \src "libresoc.v:171741.7-171741.25" + process $proc$libresoc.v:171741$10219 assign { } { } - assign $0\xer_so$49[0:0]$10175 1'0 + assign $0\xer_so$49[0:0]$10220 1'0 sync always sync init - update \xer_so$49 $0\xer_so$49[0:0]$10175 + update \xer_so$49 $0\xer_so$49[0:0]$10220 end - attribute \src "libresoc.v:169716.3-169717.43" - process $proc$libresoc.v:169716$9925 + attribute \src "libresoc.v:171750.3-171751.43" + process $proc$libresoc.v:171750$9970 assign { } { } - assign $0\operation$69[1:0]$9926 \operation$69$next + assign $0\operation$69[1:0]$9971 \operation$69$next sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$9926 + update \operation$69 $0\operation$69[1:0]$9971 end - attribute \src "libresoc.v:169718.3-169719.57" - process $proc$libresoc.v:169718$9927 + attribute \src "libresoc.v:171752.3-171753.57" + process $proc$libresoc.v:171752$9972 assign { } { } - assign $0\divisor_radicand$65[63:0]$9928 \divisor_radicand$65$next + assign $0\divisor_radicand$65[63:0]$9973 \divisor_radicand$65$next sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9928 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9973 end - attribute \src "libresoc.v:169720.3-169721.41" - process $proc$libresoc.v:169720$9929 + attribute \src "libresoc.v:171754.3-171755.41" + process $proc$libresoc.v:171754$9974 assign { } { } - assign $0\dividend$68[127:0]$9930 \dividend$68$next + assign $0\dividend$68[127:0]$9975 \dividend$68$next sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$9930 + update \dividend$68 $0\dividend$68[127:0]$9975 end - attribute \src "libresoc.v:169722.3-169723.47" - process $proc$libresoc.v:169722$9931 + attribute \src "libresoc.v:171756.3-171757.47" + process $proc$libresoc.v:171756$9976 assign { } { } - assign $0\div_by_zero$54[0:0]$9932 \div_by_zero$54$next + assign $0\div_by_zero$54[0:0]$9977 \div_by_zero$54$next sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9932 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9977 end - attribute \src "libresoc.v:169724.3-169725.51" - process $proc$libresoc.v:169724$9933 + attribute \src "libresoc.v:171758.3-171759.51" + process $proc$libresoc.v:171758$9978 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9934 \dive_abs_ov64$53$next + assign $0\dive_abs_ov64$53[0:0]$9979 \dive_abs_ov64$53$next sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9934 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9979 end - attribute \src "libresoc.v:169726.3-169727.51" - process $proc$libresoc.v:169726$9935 + attribute \src "libresoc.v:171760.3-171761.51" + process $proc$libresoc.v:171760$9980 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9936 \dive_abs_ov32$52$next + assign $0\dive_abs_ov32$52[0:0]$9981 \dive_abs_ov32$52$next sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9936 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9981 end - attribute \src "libresoc.v:169728.3-169729.49" - process $proc$libresoc.v:169728$9937 + attribute \src "libresoc.v:171762.3-171763.49" + process $proc$libresoc.v:171762$9982 assign { } { } - assign $0\dividend_neg$51[0:0]$9938 \dividend_neg$51$next + assign $0\dividend_neg$51[0:0]$9983 \dividend_neg$51$next sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9938 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9983 end - attribute \src "libresoc.v:169730.3-169731.47" - process $proc$libresoc.v:169730$9939 + attribute \src "libresoc.v:171764.3-171765.47" + process $proc$libresoc.v:171764$9984 assign { } { } - assign $0\divisor_neg$50[0:0]$9940 \divisor_neg$50$next + assign $0\divisor_neg$50[0:0]$9985 \divisor_neg$50$next sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9940 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9985 end - attribute \src "libresoc.v:169732.3-169733.37" - process $proc$libresoc.v:169732$9941 + attribute \src "libresoc.v:171766.3-171767.37" + process $proc$libresoc.v:171766$9986 assign { } { } - assign $0\xer_so$49[0:0]$9942 \xer_so$49$next + assign $0\xer_so$49[0:0]$9987 \xer_so$49$next sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$9942 + update \xer_so$49 $0\xer_so$49[0:0]$9987 end - attribute \src "libresoc.v:169734.3-169735.29" - process $proc$libresoc.v:169734$9943 + attribute \src "libresoc.v:171768.3-171769.29" + process $proc$libresoc.v:171768$9988 assign { } { } - assign $0\rb$48[63:0]$9944 \rb$48$next + assign $0\rb$48[63:0]$9989 \rb$48$next sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$9944 + update \rb$48 $0\rb$48[63:0]$9989 end - attribute \src "libresoc.v:169736.3-169737.29" - process $proc$libresoc.v:169736$9945 + attribute \src "libresoc.v:171770.3-171771.29" + process $proc$libresoc.v:171770$9990 assign { } { } - assign $0\ra$47[63:0]$9946 \ra$47$next + assign $0\ra$47[63:0]$9991 \ra$47$next sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$9946 + update \ra$47 $0\ra$47[63:0]$9991 end - attribute \src "libresoc.v:169738.3-169739.67" - process $proc$libresoc.v:169738$9947 + attribute \src "libresoc.v:171772.3-171773.67" + process $proc$libresoc.v:171772$9992 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9948 \logical_op__insn_type$29$next + assign $0\logical_op__insn_type$29[6:0]$9993 \logical_op__insn_type$29$next sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9948 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9993 end - attribute \src "libresoc.v:169740.3-169741.63" - process $proc$libresoc.v:169740$9949 + attribute \src "libresoc.v:171774.3-171775.63" + process $proc$libresoc.v:171774$9994 assign { } { } - assign $0\logical_op__fn_unit$30[12:0]$9950 \logical_op__fn_unit$30$next + assign $0\logical_op__fn_unit$30[13:0]$9995 \logical_op__fn_unit$30$next sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$9950 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$9995 end - attribute \src "libresoc.v:169742.3-169743.77" - process $proc$libresoc.v:169742$9951 + attribute \src "libresoc.v:171776.3-171777.77" + process $proc$libresoc.v:171776$9996 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9952 \logical_op__imm_data__data$31$next + assign $0\logical_op__imm_data__data$31[63:0]$9997 \logical_op__imm_data__data$31$next sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9952 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9997 end - attribute \src "libresoc.v:169744.3-169745.73" - process $proc$libresoc.v:169744$9953 + attribute \src "libresoc.v:171778.3-171779.73" + process $proc$libresoc.v:171778$9998 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9954 \logical_op__imm_data__ok$32$next + assign $0\logical_op__imm_data__ok$32[0:0]$9999 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9954 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9999 end - attribute \src "libresoc.v:169746.3-169747.61" - process $proc$libresoc.v:169746$9955 + attribute \src "libresoc.v:171780.3-171781.61" + process $proc$libresoc.v:171780$10000 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$9956 \logical_op__rc__rc$33$next + assign $0\logical_op__rc__rc$33[0:0]$10001 \logical_op__rc__rc$33$next sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9956 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10001 end - attribute \src "libresoc.v:169748.3-169749.61" - process $proc$libresoc.v:169748$9957 + attribute \src "libresoc.v:171782.3-171783.61" + process $proc$libresoc.v:171782$10002 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$9958 \logical_op__rc__ok$34$next + assign $0\logical_op__rc__ok$34[0:0]$10003 \logical_op__rc__ok$34$next sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9958 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10003 end - attribute \src "libresoc.v:169750.3-169751.61" - process $proc$libresoc.v:169750$9959 + attribute \src "libresoc.v:171784.3-171785.61" + process $proc$libresoc.v:171784$10004 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$9960 \logical_op__oe__oe$35$next + assign $0\logical_op__oe__oe$35[0:0]$10005 \logical_op__oe__oe$35$next sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9960 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10005 end - attribute \src "libresoc.v:169752.3-169753.61" - process $proc$libresoc.v:169752$9961 + attribute \src "libresoc.v:171786.3-171787.61" + process $proc$libresoc.v:171786$10006 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$9962 \logical_op__oe__ok$36$next + assign $0\logical_op__oe__ok$36[0:0]$10007 \logical_op__oe__ok$36$next sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9962 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10007 end - attribute \src "libresoc.v:169754.3-169755.67" - process $proc$libresoc.v:169754$9963 + attribute \src "libresoc.v:171788.3-171789.67" + process $proc$libresoc.v:171788$10008 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$9964 \logical_op__invert_in$37$next + assign $0\logical_op__invert_in$37[0:0]$10009 \logical_op__invert_in$37$next sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9964 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10009 end - attribute \src "libresoc.v:169756.3-169757.61" - process $proc$libresoc.v:169756$9965 + attribute \src "libresoc.v:171790.3-171791.61" + process $proc$libresoc.v:171790$10010 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$9966 \logical_op__zero_a$38$next + assign $0\logical_op__zero_a$38[0:0]$10011 \logical_op__zero_a$38$next sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9966 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10011 end - attribute \src "libresoc.v:169758.3-169759.71" - process $proc$libresoc.v:169758$9967 + attribute \src "libresoc.v:171792.3-171793.71" + process $proc$libresoc.v:171792$10012 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$9968 \logical_op__input_carry$39$next + assign $0\logical_op__input_carry$39[1:0]$10013 \logical_op__input_carry$39$next sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9968 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10013 end - attribute \src "libresoc.v:169760.3-169761.69" - process $proc$libresoc.v:169760$9969 + attribute \src "libresoc.v:171794.3-171795.69" + process $proc$libresoc.v:171794$10014 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$9970 \logical_op__invert_out$40$next + assign $0\logical_op__invert_out$40[0:0]$10015 \logical_op__invert_out$40$next sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9970 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10015 end - attribute \src "libresoc.v:169762.3-169763.67" - process $proc$libresoc.v:169762$9971 + attribute \src "libresoc.v:171796.3-171797.67" + process $proc$libresoc.v:171796$10016 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$9972 \logical_op__write_cr0$41$next + assign $0\logical_op__write_cr0$41[0:0]$10017 \logical_op__write_cr0$41$next sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9972 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10017 end - attribute \src "libresoc.v:169764.3-169765.73" - process $proc$libresoc.v:169764$9973 + attribute \src "libresoc.v:171798.3-171799.73" + process $proc$libresoc.v:171798$10018 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$9974 \logical_op__output_carry$42$next + assign $0\logical_op__output_carry$42[0:0]$10019 \logical_op__output_carry$42$next sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9974 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10019 end - attribute \src "libresoc.v:169766.3-169767.65" - process $proc$libresoc.v:169766$9975 + attribute \src "libresoc.v:171800.3-171801.65" + process $proc$libresoc.v:171800$10020 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$9976 \logical_op__is_32bit$43$next + assign $0\logical_op__is_32bit$43[0:0]$10021 \logical_op__is_32bit$43$next sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9976 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10021 end - attribute \src "libresoc.v:169768.3-169769.67" - process $proc$libresoc.v:169768$9977 + attribute \src "libresoc.v:171802.3-171803.67" + process $proc$libresoc.v:171802$10022 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$9978 \logical_op__is_signed$44$next + assign $0\logical_op__is_signed$44[0:0]$10023 \logical_op__is_signed$44$next sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9978 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10023 end - attribute \src "libresoc.v:169770.3-169771.65" - process $proc$libresoc.v:169770$9979 + attribute \src "libresoc.v:171804.3-171805.65" + process $proc$libresoc.v:171804$10024 assign { } { } - assign $0\logical_op__data_len$45[3:0]$9980 \logical_op__data_len$45$next + assign $0\logical_op__data_len$45[3:0]$10025 \logical_op__data_len$45$next sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9980 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10025 end - attribute \src "libresoc.v:169772.3-169773.57" - process $proc$libresoc.v:169772$9981 + attribute \src "libresoc.v:171806.3-171807.57" + process $proc$libresoc.v:171806$10026 assign { } { } - assign $0\logical_op__insn$46[31:0]$9982 \logical_op__insn$46$next + assign $0\logical_op__insn$46[31:0]$10027 \logical_op__insn$46$next sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9982 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10027 end - attribute \src "libresoc.v:169774.3-169775.35" - process $proc$libresoc.v:169774$9983 + attribute \src "libresoc.v:171808.3-171809.35" + process $proc$libresoc.v:171808$10028 assign { } { } - assign $0\muxid$28[1:0]$9984 \muxid$28$next + assign $0\muxid$28[1:0]$10029 \muxid$28$next sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$9984 + update \muxid$28 $0\muxid$28[1:0]$10029 end - attribute \src "libresoc.v:169776.3-169777.27" - process $proc$libresoc.v:169776$9985 + attribute \src "libresoc.v:171810.3-171811.27" + process $proc$libresoc.v:171810$10030 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end - attribute \src "libresoc.v:169778.3-169779.75" - process $proc$libresoc.v:169778$9986 + attribute \src "libresoc.v:171812.3-171813.75" + process $proc$libresoc.v:171812$10031 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:169780.3-169781.65" - process $proc$libresoc.v:169780$9987 + attribute \src "libresoc.v:171814.3-171815.65" + process $proc$libresoc.v:171814$10032 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:169802.3-169810.6" - process $proc$libresoc.v:169802$9988 + attribute \src "libresoc.v:171836.3-171844.6" + process $proc$libresoc.v:171836$10033 assign { } { } assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$9989 $1\saved_state_q_bits_known$next[6:0]$9990 - attribute \src "libresoc.v:169803.5-169803.29" + assign $0\saved_state_q_bits_known$next[6:0]$10034 $1\saved_state_q_bits_known$next[6:0]$10035 + attribute \src "libresoc.v:171837.5-171837.29" switch \initial - attribute \src "libresoc.v:169803.9-169803.17" + attribute \src "libresoc.v:171837.9-171837.17" case 1'1 case end @@ -350542,21 +353271,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$9990 7'0000000 + assign $1\saved_state_q_bits_known$next[6:0]$10035 7'0000000 case - assign $1\saved_state_q_bits_known$next[6:0]$9990 \div_state_next_o_q_bits_known + assign $1\saved_state_q_bits_known$next[6:0]$10035 \div_state_next_o_q_bits_known end sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$9989 + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10034 end - attribute \src "libresoc.v:169811.3-169819.6" - process $proc$libresoc.v:169811$9991 + attribute \src "libresoc.v:171845.3-171853.6" + process $proc$libresoc.v:171845$10036 assign { } { } assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$9992 $1\saved_state_dividend_quotient$next[127:0]$9993 - attribute \src "libresoc.v:169812.5-169812.29" + assign $0\saved_state_dividend_quotient$next[127:0]$10037 $1\saved_state_dividend_quotient$next[127:0]$10038 + attribute \src "libresoc.v:171846.5-171846.29" switch \initial - attribute \src "libresoc.v:169812.9-169812.17" + attribute \src "libresoc.v:171846.9-171846.17" case 1'1 case end @@ -350565,20 +353294,20 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$9993 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\saved_state_dividend_quotient$next[127:0]$10038 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $1\saved_state_dividend_quotient$next[127:0]$9993 \div_state_next_o_dividend_quotient + assign $1\saved_state_dividend_quotient$next[127:0]$10038 \div_state_next_o_dividend_quotient end sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$9992 + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10037 end - attribute \src "libresoc.v:169820.3-169831.6" - process $proc$libresoc.v:169820$9994 + attribute \src "libresoc.v:171854.3-171865.6" + process $proc$libresoc.v:171854$10039 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:169821.5-169821.29" + attribute \src "libresoc.v:171855.5-171855.29" switch \initial - attribute \src "libresoc.v:169821.9-169821.17" + attribute \src "libresoc.v:171855.9-171855.17" case 1'1 case end @@ -350596,13 +353325,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "libresoc.v:169832.3-169843.6" - process $proc$libresoc.v:169832$9995 + attribute \src "libresoc.v:171866.3-171877.6" + process $proc$libresoc.v:171866$10040 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:169833.5-169833.29" + attribute \src "libresoc.v:171867.5-171867.29" switch \initial - attribute \src "libresoc.v:169833.9-169833.17" + attribute \src "libresoc.v:171867.9-171867.17" case 1'1 case end @@ -350620,13 +353349,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "libresoc.v:169844.3-169855.6" - process $proc$libresoc.v:169844$9996 + attribute \src "libresoc.v:171878.3-171889.6" + process $proc$libresoc.v:171878$10041 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:169845.5-169845.29" + attribute \src "libresoc.v:171879.5-171879.29" switch \initial - attribute \src "libresoc.v:169845.9-169845.17" + attribute \src "libresoc.v:171879.9-171879.17" case 1'1 case end @@ -350644,15 +353373,15 @@ module \pipe_middle_0 sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "libresoc.v:169856.3-169883.6" - process $proc$libresoc.v:169856$9997 + attribute \src "libresoc.v:171890.3-171917.6" + process $proc$libresoc.v:171890$10042 assign { } { } assign { } { } assign { } { } - assign $0\empty$next[0:0]$9998 $4\empty$next[0:0]$10002 - attribute \src "libresoc.v:169857.5-169857.29" + assign $0\empty$next[0:0]$10043 $4\empty$next[0:0]$10047 + attribute \src "libresoc.v:171891.5-171891.29" switch \initial - attribute \src "libresoc.v:169857.9-169857.17" + attribute \src "libresoc.v:171891.9-171891.17" case 1'1 case end @@ -350661,28 +353390,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\empty$next[0:0]$9999 $2\empty$next[0:0]$10000 + assign $1\empty$next[0:0]$10044 $2\empty$next[0:0]$10045 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\empty$next[0:0]$10000 1'0 + assign $2\empty$next[0:0]$10045 1'0 case - assign $2\empty$next[0:0]$10000 \empty + assign $2\empty$next[0:0]$10045 \empty end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\empty$next[0:0]$9999 $3\empty$next[0:0]$10001 + assign $1\empty$next[0:0]$10044 $3\empty$next[0:0]$10046 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch \$66 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\empty$next[0:0]$10001 1'1 + assign $3\empty$next[0:0]$10046 1'1 case - assign $3\empty$next[0:0]$10001 \empty + assign $3\empty$next[0:0]$10046 \empty end end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" @@ -350690,21 +353419,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\empty$next[0:0]$10002 1'1 + assign $4\empty$next[0:0]$10047 1'1 case - assign $4\empty$next[0:0]$10002 $1\empty$next[0:0]$9999 + assign $4\empty$next[0:0]$10047 $1\empty$next[0:0]$10044 end sync always - update \empty$next $0\empty$next[0:0]$9998 + update \empty$next $0\empty$next[0:0]$10043 end - attribute \src "libresoc.v:169884.3-169898.6" - process $proc$libresoc.v:169884$10003 + attribute \src "libresoc.v:171918.3-171932.6" + process $proc$libresoc.v:171918$10048 assign { } { } assign { } { } - assign $0\muxid$28$next[1:0]$10004 $1\muxid$28$next[1:0]$10005 - attribute \src "libresoc.v:169885.5-169885.29" + assign $0\muxid$28$next[1:0]$10049 $1\muxid$28$next[1:0]$10050 + attribute \src "libresoc.v:171919.5-171919.29" switch \initial - attribute \src "libresoc.v:169885.9-169885.17" + attribute \src "libresoc.v:171919.9-171919.17" case 1'1 case end @@ -350713,24 +353442,24 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\muxid$28$next[1:0]$10005 $2\muxid$28$next[1:0]$10006 + assign $1\muxid$28$next[1:0]$10050 $2\muxid$28$next[1:0]$10051 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\muxid$28$next[1:0]$10006 \muxid + assign $2\muxid$28$next[1:0]$10051 \muxid case - assign $2\muxid$28$next[1:0]$10006 \muxid$28 + assign $2\muxid$28$next[1:0]$10051 \muxid$28 end case - assign $1\muxid$28$next[1:0]$10005 \muxid$28 + assign $1\muxid$28$next[1:0]$10050 \muxid$28 end sync always - update \muxid$28$next $0\muxid$28$next[1:0]$10004 + update \muxid$28$next $0\muxid$28$next[1:0]$10049 end - attribute \src "libresoc.v:169899.3-169942.6" - process $proc$libresoc.v:169899$10007 + attribute \src "libresoc.v:171933.3-171976.6" + process $proc$libresoc.v:171933$10052 assign { } { } assign { } { } assign { } { } @@ -350767,33 +353496,33 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$10008 $1\logical_op__data_len$45$next[3:0]$10026 - assign $0\logical_op__fn_unit$30$next[12:0]$10009 $1\logical_op__fn_unit$30$next[12:0]$10027 + assign $0\logical_op__data_len$45$next[3:0]$10053 $1\logical_op__data_len$45$next[3:0]$10071 + assign $0\logical_op__fn_unit$30$next[13:0]$10054 $1\logical_op__fn_unit$30$next[13:0]$10072 assign { } { } assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$10012 $1\logical_op__input_carry$39$next[1:0]$10030 - assign $0\logical_op__insn$46$next[31:0]$10013 $1\logical_op__insn$46$next[31:0]$10031 - assign $0\logical_op__insn_type$29$next[6:0]$10014 $1\logical_op__insn_type$29$next[6:0]$10032 - assign $0\logical_op__invert_in$37$next[0:0]$10015 $1\logical_op__invert_in$37$next[0:0]$10033 - assign $0\logical_op__invert_out$40$next[0:0]$10016 $1\logical_op__invert_out$40$next[0:0]$10034 - assign $0\logical_op__is_32bit$43$next[0:0]$10017 $1\logical_op__is_32bit$43$next[0:0]$10035 - assign $0\logical_op__is_signed$44$next[0:0]$10018 $1\logical_op__is_signed$44$next[0:0]$10036 + assign $0\logical_op__input_carry$39$next[1:0]$10057 $1\logical_op__input_carry$39$next[1:0]$10075 + assign $0\logical_op__insn$46$next[31:0]$10058 $1\logical_op__insn$46$next[31:0]$10076 + assign $0\logical_op__insn_type$29$next[6:0]$10059 $1\logical_op__insn_type$29$next[6:0]$10077 + assign $0\logical_op__invert_in$37$next[0:0]$10060 $1\logical_op__invert_in$37$next[0:0]$10078 + assign $0\logical_op__invert_out$40$next[0:0]$10061 $1\logical_op__invert_out$40$next[0:0]$10079 + assign $0\logical_op__is_32bit$43$next[0:0]$10062 $1\logical_op__is_32bit$43$next[0:0]$10080 + assign $0\logical_op__is_signed$44$next[0:0]$10063 $1\logical_op__is_signed$44$next[0:0]$10081 assign { } { } assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$10021 $1\logical_op__output_carry$42$next[0:0]$10039 + assign $0\logical_op__output_carry$42$next[0:0]$10066 $1\logical_op__output_carry$42$next[0:0]$10084 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$10024 $1\logical_op__write_cr0$41$next[0:0]$10042 - assign $0\logical_op__zero_a$38$next[0:0]$10025 $1\logical_op__zero_a$38$next[0:0]$10043 - assign $0\logical_op__imm_data__data$31$next[63:0]$10010 $3\logical_op__imm_data__data$31$next[63:0]$10062 - assign $0\logical_op__imm_data__ok$32$next[0:0]$10011 $3\logical_op__imm_data__ok$32$next[0:0]$10063 - assign $0\logical_op__oe__oe$35$next[0:0]$10019 $3\logical_op__oe__oe$35$next[0:0]$10064 - assign $0\logical_op__oe__ok$36$next[0:0]$10020 $3\logical_op__oe__ok$36$next[0:0]$10065 - assign $0\logical_op__rc__ok$34$next[0:0]$10022 $3\logical_op__rc__ok$34$next[0:0]$10066 - assign $0\logical_op__rc__rc$33$next[0:0]$10023 $3\logical_op__rc__rc$33$next[0:0]$10067 - attribute \src "libresoc.v:169900.5-169900.29" + assign $0\logical_op__write_cr0$41$next[0:0]$10069 $1\logical_op__write_cr0$41$next[0:0]$10087 + assign $0\logical_op__zero_a$38$next[0:0]$10070 $1\logical_op__zero_a$38$next[0:0]$10088 + assign $0\logical_op__imm_data__data$31$next[63:0]$10055 $3\logical_op__imm_data__data$31$next[63:0]$10107 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10056 $3\logical_op__imm_data__ok$32$next[0:0]$10108 + assign $0\logical_op__oe__oe$35$next[0:0]$10064 $3\logical_op__oe__oe$35$next[0:0]$10109 + assign $0\logical_op__oe__ok$36$next[0:0]$10065 $3\logical_op__oe__ok$36$next[0:0]$10110 + assign $0\logical_op__rc__ok$34$next[0:0]$10067 $3\logical_op__rc__ok$34$next[0:0]$10111 + assign $0\logical_op__rc__rc$33$next[0:0]$10068 $3\logical_op__rc__rc$33$next[0:0]$10112 + attribute \src "libresoc.v:171934.5-171934.29" switch \initial - attribute \src "libresoc.v:169900.9-169900.17" + attribute \src "libresoc.v:171934.9-171934.17" case 1'1 case end @@ -350819,24 +353548,24 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$10026 $2\logical_op__data_len$45$next[3:0]$10044 - assign $1\logical_op__fn_unit$30$next[12:0]$10027 $2\logical_op__fn_unit$30$next[12:0]$10045 - assign $1\logical_op__imm_data__data$31$next[63:0]$10028 $2\logical_op__imm_data__data$31$next[63:0]$10046 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10029 $2\logical_op__imm_data__ok$32$next[0:0]$10047 - assign $1\logical_op__input_carry$39$next[1:0]$10030 $2\logical_op__input_carry$39$next[1:0]$10048 - assign $1\logical_op__insn$46$next[31:0]$10031 $2\logical_op__insn$46$next[31:0]$10049 - assign $1\logical_op__insn_type$29$next[6:0]$10032 $2\logical_op__insn_type$29$next[6:0]$10050 - assign $1\logical_op__invert_in$37$next[0:0]$10033 $2\logical_op__invert_in$37$next[0:0]$10051 - assign $1\logical_op__invert_out$40$next[0:0]$10034 $2\logical_op__invert_out$40$next[0:0]$10052 - assign $1\logical_op__is_32bit$43$next[0:0]$10035 $2\logical_op__is_32bit$43$next[0:0]$10053 - assign $1\logical_op__is_signed$44$next[0:0]$10036 $2\logical_op__is_signed$44$next[0:0]$10054 - assign $1\logical_op__oe__oe$35$next[0:0]$10037 $2\logical_op__oe__oe$35$next[0:0]$10055 - assign $1\logical_op__oe__ok$36$next[0:0]$10038 $2\logical_op__oe__ok$36$next[0:0]$10056 - assign $1\logical_op__output_carry$42$next[0:0]$10039 $2\logical_op__output_carry$42$next[0:0]$10057 - assign $1\logical_op__rc__ok$34$next[0:0]$10040 $2\logical_op__rc__ok$34$next[0:0]$10058 - assign $1\logical_op__rc__rc$33$next[0:0]$10041 $2\logical_op__rc__rc$33$next[0:0]$10059 - assign $1\logical_op__write_cr0$41$next[0:0]$10042 $2\logical_op__write_cr0$41$next[0:0]$10060 - assign $1\logical_op__zero_a$38$next[0:0]$10043 $2\logical_op__zero_a$38$next[0:0]$10061 + assign $1\logical_op__data_len$45$next[3:0]$10071 $2\logical_op__data_len$45$next[3:0]$10089 + assign $1\logical_op__fn_unit$30$next[13:0]$10072 $2\logical_op__fn_unit$30$next[13:0]$10090 + assign $1\logical_op__imm_data__data$31$next[63:0]$10073 $2\logical_op__imm_data__data$31$next[63:0]$10091 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10074 $2\logical_op__imm_data__ok$32$next[0:0]$10092 + assign $1\logical_op__input_carry$39$next[1:0]$10075 $2\logical_op__input_carry$39$next[1:0]$10093 + assign $1\logical_op__insn$46$next[31:0]$10076 $2\logical_op__insn$46$next[31:0]$10094 + assign $1\logical_op__insn_type$29$next[6:0]$10077 $2\logical_op__insn_type$29$next[6:0]$10095 + assign $1\logical_op__invert_in$37$next[0:0]$10078 $2\logical_op__invert_in$37$next[0:0]$10096 + assign $1\logical_op__invert_out$40$next[0:0]$10079 $2\logical_op__invert_out$40$next[0:0]$10097 + assign $1\logical_op__is_32bit$43$next[0:0]$10080 $2\logical_op__is_32bit$43$next[0:0]$10098 + assign $1\logical_op__is_signed$44$next[0:0]$10081 $2\logical_op__is_signed$44$next[0:0]$10099 + assign $1\logical_op__oe__oe$35$next[0:0]$10082 $2\logical_op__oe__oe$35$next[0:0]$10100 + assign $1\logical_op__oe__ok$36$next[0:0]$10083 $2\logical_op__oe__ok$36$next[0:0]$10101 + assign $1\logical_op__output_carry$42$next[0:0]$10084 $2\logical_op__output_carry$42$next[0:0]$10102 + assign $1\logical_op__rc__ok$34$next[0:0]$10085 $2\logical_op__rc__ok$34$next[0:0]$10103 + assign $1\logical_op__rc__rc$33$next[0:0]$10086 $2\logical_op__rc__rc$33$next[0:0]$10104 + assign $1\logical_op__write_cr0$41$next[0:0]$10087 $2\logical_op__write_cr0$41$next[0:0]$10105 + assign $1\logical_op__zero_a$38$next[0:0]$10088 $2\logical_op__zero_a$38$next[0:0]$10106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" @@ -350859,46 +353588,46 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$10049 $2\logical_op__data_len$45$next[3:0]$10044 $2\logical_op__is_signed$44$next[0:0]$10054 $2\logical_op__is_32bit$43$next[0:0]$10053 $2\logical_op__output_carry$42$next[0:0]$10057 $2\logical_op__write_cr0$41$next[0:0]$10060 $2\logical_op__invert_out$40$next[0:0]$10052 $2\logical_op__input_carry$39$next[1:0]$10048 $2\logical_op__zero_a$38$next[0:0]$10061 $2\logical_op__invert_in$37$next[0:0]$10051 $2\logical_op__oe__ok$36$next[0:0]$10056 $2\logical_op__oe__oe$35$next[0:0]$10055 $2\logical_op__rc__ok$34$next[0:0]$10058 $2\logical_op__rc__rc$33$next[0:0]$10059 $2\logical_op__imm_data__ok$32$next[0:0]$10047 $2\logical_op__imm_data__data$31$next[63:0]$10046 $2\logical_op__fn_unit$30$next[12:0]$10045 $2\logical_op__insn_type$29$next[6:0]$10050 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + assign { $2\logical_op__insn$46$next[31:0]$10094 $2\logical_op__data_len$45$next[3:0]$10089 $2\logical_op__is_signed$44$next[0:0]$10099 $2\logical_op__is_32bit$43$next[0:0]$10098 $2\logical_op__output_carry$42$next[0:0]$10102 $2\logical_op__write_cr0$41$next[0:0]$10105 $2\logical_op__invert_out$40$next[0:0]$10097 $2\logical_op__input_carry$39$next[1:0]$10093 $2\logical_op__zero_a$38$next[0:0]$10106 $2\logical_op__invert_in$37$next[0:0]$10096 $2\logical_op__oe__ok$36$next[0:0]$10101 $2\logical_op__oe__oe$35$next[0:0]$10100 $2\logical_op__rc__ok$34$next[0:0]$10103 $2\logical_op__rc__rc$33$next[0:0]$10104 $2\logical_op__imm_data__ok$32$next[0:0]$10092 $2\logical_op__imm_data__data$31$next[63:0]$10091 $2\logical_op__fn_unit$30$next[13:0]$10090 $2\logical_op__insn_type$29$next[6:0]$10095 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } case - assign $2\logical_op__data_len$45$next[3:0]$10044 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[12:0]$10045 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$10046 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$10047 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$10048 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$10049 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$10050 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$10051 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$10052 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$10053 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$10054 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$10055 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$10056 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$10057 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$10058 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$10059 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$10060 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$10061 \logical_op__zero_a$38 + assign $2\logical_op__data_len$45$next[3:0]$10089 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[13:0]$10090 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10091 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10092 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10093 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10094 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10095 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10096 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10097 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10098 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10099 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10100 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10101 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10102 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10103 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10104 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10105 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10106 \logical_op__zero_a$38 end case - assign $1\logical_op__data_len$45$next[3:0]$10026 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[12:0]$10027 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$10028 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10029 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$10030 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$10031 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$10032 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$10033 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$10034 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$10035 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$10036 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$10037 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$10038 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$10039 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$10040 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$10041 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$10042 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$10043 \logical_op__zero_a$38 + assign $1\logical_op__data_len$45$next[3:0]$10071 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[13:0]$10072 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10073 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10074 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10075 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10076 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10077 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10078 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10079 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10080 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10081 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10082 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10083 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10084 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10085 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10086 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10087 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10088 \logical_op__zero_a$38 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -350910,48 +353639,48 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$10062 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10063 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$10067 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$10066 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$10064 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$10065 1'0 + assign $3\logical_op__imm_data__data$31$next[63:0]$10107 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10108 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10112 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10111 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10109 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10110 1'0 case - assign $3\logical_op__imm_data__data$31$next[63:0]$10062 $1\logical_op__imm_data__data$31$next[63:0]$10028 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10063 $1\logical_op__imm_data__ok$32$next[0:0]$10029 - assign $3\logical_op__oe__oe$35$next[0:0]$10064 $1\logical_op__oe__oe$35$next[0:0]$10037 - assign $3\logical_op__oe__ok$36$next[0:0]$10065 $1\logical_op__oe__ok$36$next[0:0]$10038 - assign $3\logical_op__rc__ok$34$next[0:0]$10066 $1\logical_op__rc__ok$34$next[0:0]$10040 - assign $3\logical_op__rc__rc$33$next[0:0]$10067 $1\logical_op__rc__rc$33$next[0:0]$10041 + assign $3\logical_op__imm_data__data$31$next[63:0]$10107 $1\logical_op__imm_data__data$31$next[63:0]$10073 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10108 $1\logical_op__imm_data__ok$32$next[0:0]$10074 + assign $3\logical_op__oe__oe$35$next[0:0]$10109 $1\logical_op__oe__oe$35$next[0:0]$10082 + assign $3\logical_op__oe__ok$36$next[0:0]$10110 $1\logical_op__oe__ok$36$next[0:0]$10083 + assign $3\logical_op__rc__ok$34$next[0:0]$10111 $1\logical_op__rc__ok$34$next[0:0]$10085 + assign $3\logical_op__rc__rc$33$next[0:0]$10112 $1\logical_op__rc__rc$33$next[0:0]$10086 end sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10008 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[12:0]$10009 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10010 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10011 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10012 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10013 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10014 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10015 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10016 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10017 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10018 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10019 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10020 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10021 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10022 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10023 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10024 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10025 + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10053 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10054 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10055 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10056 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10057 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10058 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10059 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10060 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10061 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10062 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10063 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10064 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10065 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10066 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10067 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10068 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10069 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10070 end - attribute \src "libresoc.v:169943.3-169957.6" - process $proc$libresoc.v:169943$10068 + attribute \src "libresoc.v:171977.3-171991.6" + process $proc$libresoc.v:171977$10113 assign { } { } assign { } { } - assign $0\ra$47$next[63:0]$10069 $1\ra$47$next[63:0]$10070 - attribute \src "libresoc.v:169944.5-169944.29" + assign $0\ra$47$next[63:0]$10114 $1\ra$47$next[63:0]$10115 + attribute \src "libresoc.v:171978.5-171978.29" switch \initial - attribute \src "libresoc.v:169944.9-169944.17" + attribute \src "libresoc.v:171978.9-171978.17" case 1'1 case end @@ -350960,30 +353689,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ra$47$next[63:0]$10070 $2\ra$47$next[63:0]$10071 + assign $1\ra$47$next[63:0]$10115 $2\ra$47$next[63:0]$10116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ra$47$next[63:0]$10071 \ra + assign $2\ra$47$next[63:0]$10116 \ra case - assign $2\ra$47$next[63:0]$10071 \ra$47 + assign $2\ra$47$next[63:0]$10116 \ra$47 end case - assign $1\ra$47$next[63:0]$10070 \ra$47 + assign $1\ra$47$next[63:0]$10115 \ra$47 end sync always - update \ra$47$next $0\ra$47$next[63:0]$10069 + update \ra$47$next $0\ra$47$next[63:0]$10114 end - attribute \src "libresoc.v:169958.3-169972.6" - process $proc$libresoc.v:169958$10072 + attribute \src "libresoc.v:171992.3-172006.6" + process $proc$libresoc.v:171992$10117 assign { } { } assign { } { } - assign $0\rb$48$next[63:0]$10073 $1\rb$48$next[63:0]$10074 - attribute \src "libresoc.v:169959.5-169959.29" + assign $0\rb$48$next[63:0]$10118 $1\rb$48$next[63:0]$10119 + attribute \src "libresoc.v:171993.5-171993.29" switch \initial - attribute \src "libresoc.v:169959.9-169959.17" + attribute \src "libresoc.v:171993.9-171993.17" case 1'1 case end @@ -350992,30 +353721,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rb$48$next[63:0]$10074 $2\rb$48$next[63:0]$10075 + assign $1\rb$48$next[63:0]$10119 $2\rb$48$next[63:0]$10120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\rb$48$next[63:0]$10075 \rb + assign $2\rb$48$next[63:0]$10120 \rb case - assign $2\rb$48$next[63:0]$10075 \rb$48 + assign $2\rb$48$next[63:0]$10120 \rb$48 end case - assign $1\rb$48$next[63:0]$10074 \rb$48 + assign $1\rb$48$next[63:0]$10119 \rb$48 end sync always - update \rb$48$next $0\rb$48$next[63:0]$10073 + update \rb$48$next $0\rb$48$next[63:0]$10118 end - attribute \src "libresoc.v:169973.3-169987.6" - process $proc$libresoc.v:169973$10076 + attribute \src "libresoc.v:172007.3-172021.6" + process $proc$libresoc.v:172007$10121 assign { } { } assign { } { } - assign $0\xer_so$49$next[0:0]$10077 $1\xer_so$49$next[0:0]$10078 - attribute \src "libresoc.v:169974.5-169974.29" + assign $0\xer_so$49$next[0:0]$10122 $1\xer_so$49$next[0:0]$10123 + attribute \src "libresoc.v:172008.5-172008.29" switch \initial - attribute \src "libresoc.v:169974.9-169974.17" + attribute \src "libresoc.v:172008.9-172008.17" case 1'1 case end @@ -351024,30 +353753,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$10078 $2\xer_so$49$next[0:0]$10079 + assign $1\xer_so$49$next[0:0]$10123 $2\xer_so$49$next[0:0]$10124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so$49$next[0:0]$10079 \xer_so + assign $2\xer_so$49$next[0:0]$10124 \xer_so case - assign $2\xer_so$49$next[0:0]$10079 \xer_so$49 + assign $2\xer_so$49$next[0:0]$10124 \xer_so$49 end case - assign $1\xer_so$49$next[0:0]$10078 \xer_so$49 + assign $1\xer_so$49$next[0:0]$10123 \xer_so$49 end sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$10077 + update \xer_so$49$next $0\xer_so$49$next[0:0]$10122 end - attribute \src "libresoc.v:169988.3-170002.6" - process $proc$libresoc.v:169988$10080 + attribute \src "libresoc.v:172022.3-172036.6" + process $proc$libresoc.v:172022$10125 assign { } { } assign { } { } - assign $0\divisor_neg$50$next[0:0]$10081 $1\divisor_neg$50$next[0:0]$10082 - attribute \src "libresoc.v:169989.5-169989.29" + assign $0\divisor_neg$50$next[0:0]$10126 $1\divisor_neg$50$next[0:0]$10127 + attribute \src "libresoc.v:172023.5-172023.29" switch \initial - attribute \src "libresoc.v:169989.9-169989.17" + attribute \src "libresoc.v:172023.9-172023.17" case 1'1 case end @@ -351056,30 +353785,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$10082 $2\divisor_neg$50$next[0:0]$10083 + assign $1\divisor_neg$50$next[0:0]$10127 $2\divisor_neg$50$next[0:0]$10128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_neg$50$next[0:0]$10083 \divisor_neg + assign $2\divisor_neg$50$next[0:0]$10128 \divisor_neg case - assign $2\divisor_neg$50$next[0:0]$10083 \divisor_neg$50 + assign $2\divisor_neg$50$next[0:0]$10128 \divisor_neg$50 end case - assign $1\divisor_neg$50$next[0:0]$10082 \divisor_neg$50 + assign $1\divisor_neg$50$next[0:0]$10127 \divisor_neg$50 end sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10081 + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10126 end - attribute \src "libresoc.v:170003.3-170017.6" - process $proc$libresoc.v:170003$10084 + attribute \src "libresoc.v:172037.3-172051.6" + process $proc$libresoc.v:172037$10129 assign { } { } assign { } { } - assign $0\dividend_neg$51$next[0:0]$10085 $1\dividend_neg$51$next[0:0]$10086 - attribute \src "libresoc.v:170004.5-170004.29" + assign $0\dividend_neg$51$next[0:0]$10130 $1\dividend_neg$51$next[0:0]$10131 + attribute \src "libresoc.v:172038.5-172038.29" switch \initial - attribute \src "libresoc.v:170004.9-170004.17" + attribute \src "libresoc.v:172038.9-172038.17" case 1'1 case end @@ -351088,30 +353817,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$10086 $2\dividend_neg$51$next[0:0]$10087 + assign $1\dividend_neg$51$next[0:0]$10131 $2\dividend_neg$51$next[0:0]$10132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend_neg$51$next[0:0]$10087 \dividend_neg + assign $2\dividend_neg$51$next[0:0]$10132 \dividend_neg case - assign $2\dividend_neg$51$next[0:0]$10087 \dividend_neg$51 + assign $2\dividend_neg$51$next[0:0]$10132 \dividend_neg$51 end case - assign $1\dividend_neg$51$next[0:0]$10086 \dividend_neg$51 + assign $1\dividend_neg$51$next[0:0]$10131 \dividend_neg$51 end sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10085 + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10130 end - attribute \src "libresoc.v:170018.3-170032.6" - process $proc$libresoc.v:170018$10088 + attribute \src "libresoc.v:172052.3-172066.6" + process $proc$libresoc.v:172052$10133 assign { } { } assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$10089 $1\dive_abs_ov32$52$next[0:0]$10090 - attribute \src "libresoc.v:170019.5-170019.29" + assign $0\dive_abs_ov32$52$next[0:0]$10134 $1\dive_abs_ov32$52$next[0:0]$10135 + attribute \src "libresoc.v:172053.5-172053.29" switch \initial - attribute \src "libresoc.v:170019.9-170019.17" + attribute \src "libresoc.v:172053.9-172053.17" case 1'1 case end @@ -351120,30 +353849,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$10090 $2\dive_abs_ov32$52$next[0:0]$10091 + assign $1\dive_abs_ov32$52$next[0:0]$10135 $2\dive_abs_ov32$52$next[0:0]$10136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$10091 \dive_abs_ov32 + assign $2\dive_abs_ov32$52$next[0:0]$10136 \dive_abs_ov32 case - assign $2\dive_abs_ov32$52$next[0:0]$10091 \dive_abs_ov32$52 + assign $2\dive_abs_ov32$52$next[0:0]$10136 \dive_abs_ov32$52 end case - assign $1\dive_abs_ov32$52$next[0:0]$10090 \dive_abs_ov32$52 + assign $1\dive_abs_ov32$52$next[0:0]$10135 \dive_abs_ov32$52 end sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10089 + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10134 end - attribute \src "libresoc.v:170033.3-170047.6" - process $proc$libresoc.v:170033$10092 + attribute \src "libresoc.v:172067.3-172081.6" + process $proc$libresoc.v:172067$10137 assign { } { } assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$10093 $1\dive_abs_ov64$53$next[0:0]$10094 - attribute \src "libresoc.v:170034.5-170034.29" + assign $0\dive_abs_ov64$53$next[0:0]$10138 $1\dive_abs_ov64$53$next[0:0]$10139 + attribute \src "libresoc.v:172068.5-172068.29" switch \initial - attribute \src "libresoc.v:170034.9-170034.17" + attribute \src "libresoc.v:172068.9-172068.17" case 1'1 case end @@ -351152,30 +353881,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$10094 $2\dive_abs_ov64$53$next[0:0]$10095 + assign $1\dive_abs_ov64$53$next[0:0]$10139 $2\dive_abs_ov64$53$next[0:0]$10140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$10095 \dive_abs_ov64 + assign $2\dive_abs_ov64$53$next[0:0]$10140 \dive_abs_ov64 case - assign $2\dive_abs_ov64$53$next[0:0]$10095 \dive_abs_ov64$53 + assign $2\dive_abs_ov64$53$next[0:0]$10140 \dive_abs_ov64$53 end case - assign $1\dive_abs_ov64$53$next[0:0]$10094 \dive_abs_ov64$53 + assign $1\dive_abs_ov64$53$next[0:0]$10139 \dive_abs_ov64$53 end sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10093 + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10138 end - attribute \src "libresoc.v:170048.3-170062.6" - process $proc$libresoc.v:170048$10096 + attribute \src "libresoc.v:172082.3-172096.6" + process $proc$libresoc.v:172082$10141 assign { } { } assign { } { } - assign $0\div_by_zero$54$next[0:0]$10097 $1\div_by_zero$54$next[0:0]$10098 - attribute \src "libresoc.v:170049.5-170049.29" + assign $0\div_by_zero$54$next[0:0]$10142 $1\div_by_zero$54$next[0:0]$10143 + attribute \src "libresoc.v:172083.5-172083.29" switch \initial - attribute \src "libresoc.v:170049.9-170049.17" + attribute \src "libresoc.v:172083.9-172083.17" case 1'1 case end @@ -351184,30 +353913,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$10098 $2\div_by_zero$54$next[0:0]$10099 + assign $1\div_by_zero$54$next[0:0]$10143 $2\div_by_zero$54$next[0:0]$10144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\div_by_zero$54$next[0:0]$10099 \div_by_zero + assign $2\div_by_zero$54$next[0:0]$10144 \div_by_zero case - assign $2\div_by_zero$54$next[0:0]$10099 \div_by_zero$54 + assign $2\div_by_zero$54$next[0:0]$10144 \div_by_zero$54 end case - assign $1\div_by_zero$54$next[0:0]$10098 \div_by_zero$54 + assign $1\div_by_zero$54$next[0:0]$10143 \div_by_zero$54 end sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10097 + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10142 end - attribute \src "libresoc.v:170063.3-170077.6" - process $proc$libresoc.v:170063$10100 + attribute \src "libresoc.v:172097.3-172111.6" + process $proc$libresoc.v:172097$10145 assign { } { } assign { } { } - assign $0\dividend$68$next[127:0]$10101 $1\dividend$68$next[127:0]$10102 - attribute \src "libresoc.v:170064.5-170064.29" + assign $0\dividend$68$next[127:0]$10146 $1\dividend$68$next[127:0]$10147 + attribute \src "libresoc.v:172098.5-172098.29" switch \initial - attribute \src "libresoc.v:170064.9-170064.17" + attribute \src "libresoc.v:172098.9-172098.17" case 1'1 case end @@ -351216,30 +353945,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$10102 $2\dividend$68$next[127:0]$10103 + assign $1\dividend$68$next[127:0]$10147 $2\dividend$68$next[127:0]$10148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend$68$next[127:0]$10103 \dividend + assign $2\dividend$68$next[127:0]$10148 \dividend case - assign $2\dividend$68$next[127:0]$10103 \dividend$68 + assign $2\dividend$68$next[127:0]$10148 \dividend$68 end case - assign $1\dividend$68$next[127:0]$10102 \dividend$68 + assign $1\dividend$68$next[127:0]$10147 \dividend$68 end sync always - update \dividend$68$next $0\dividend$68$next[127:0]$10101 + update \dividend$68$next $0\dividend$68$next[127:0]$10146 end - attribute \src "libresoc.v:170078.3-170092.6" - process $proc$libresoc.v:170078$10104 + attribute \src "libresoc.v:172112.3-172126.6" + process $proc$libresoc.v:172112$10149 assign { } { } assign { } { } - assign $0\divisor_radicand$65$next[63:0]$10105 $1\divisor_radicand$65$next[63:0]$10106 - attribute \src "libresoc.v:170079.5-170079.29" + assign $0\divisor_radicand$65$next[63:0]$10150 $1\divisor_radicand$65$next[63:0]$10151 + attribute \src "libresoc.v:172113.5-172113.29" switch \initial - attribute \src "libresoc.v:170079.9-170079.17" + attribute \src "libresoc.v:172113.9-172113.17" case 1'1 case end @@ -351248,30 +353977,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$10106 $2\divisor_radicand$65$next[63:0]$10107 + assign $1\divisor_radicand$65$next[63:0]$10151 $2\divisor_radicand$65$next[63:0]$10152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_radicand$65$next[63:0]$10107 \divisor_radicand + assign $2\divisor_radicand$65$next[63:0]$10152 \divisor_radicand case - assign $2\divisor_radicand$65$next[63:0]$10107 \divisor_radicand$65 + assign $2\divisor_radicand$65$next[63:0]$10152 \divisor_radicand$65 end case - assign $1\divisor_radicand$65$next[63:0]$10106 \divisor_radicand$65 + assign $1\divisor_radicand$65$next[63:0]$10151 \divisor_radicand$65 end sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10105 + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10150 end - attribute \src "libresoc.v:170093.3-170107.6" - process $proc$libresoc.v:170093$10108 + attribute \src "libresoc.v:172127.3-172141.6" + process $proc$libresoc.v:172127$10153 assign { } { } assign { } { } - assign $0\operation$69$next[1:0]$10109 $1\operation$69$next[1:0]$10110 - attribute \src "libresoc.v:170094.5-170094.29" + assign $0\operation$69$next[1:0]$10154 $1\operation$69$next[1:0]$10155 + attribute \src "libresoc.v:172128.5-172128.29" switch \initial - attribute \src "libresoc.v:170094.9-170094.17" + attribute \src "libresoc.v:172128.9-172128.17" case 1'1 case end @@ -351280,28 +354009,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\operation$69$next[1:0]$10110 $2\operation$69$next[1:0]$10111 + assign $1\operation$69$next[1:0]$10155 $2\operation$69$next[1:0]$10156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\operation$69$next[1:0]$10111 \operation + assign $2\operation$69$next[1:0]$10156 \operation case - assign $2\operation$69$next[1:0]$10111 \operation$69 + assign $2\operation$69$next[1:0]$10156 \operation$69 end case - assign $1\operation$69$next[1:0]$10110 \operation$69 + assign $1\operation$69$next[1:0]$10155 \operation$69 end sync always - update \operation$69$next $0\operation$69$next[1:0]$10109 + update \operation$69$next $0\operation$69$next[1:0]$10154 end - connect \$56 $sshl$libresoc.v:169710$9918_Y - connect \$55 $pos$libresoc.v:169711$9920_Y - connect \$59 $not$libresoc.v:169712$9921_Y - connect \$61 $ge$libresoc.v:169713$9922_Y - connect \$63 $and$libresoc.v:169714$9923_Y - connect \$66 $and$libresoc.v:169715$9924_Y + connect \$56 $sshl$libresoc.v:171744$9963_Y + connect \$55 $pos$libresoc.v:171745$9965_Y + connect \$59 $not$libresoc.v:171746$9966_Y + connect \$61 $ge$libresoc.v:171747$9967_Y + connect \$63 $and$libresoc.v:171748$9968_Y + connect \$66 $and$libresoc.v:171749$9969_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 @@ -351318,282 +354047,282 @@ module \pipe_middle_0 connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:170127.1-171658.10" +attribute \src "libresoc.v:172161.1-173706.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start - attribute \src "libresoc.v:171464.3-171476.6" - wire $0\div_by_zero$next[0:0]$10221 - attribute \src "libresoc.v:171250.3-171251.39" + attribute \src "libresoc.v:173512.3-173524.6" + wire $0\div_by_zero$next[0:0]$10266 + attribute \src "libresoc.v:173298.3-173299.39" wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:171438.3-171450.6" - wire $0\dive_abs_ov32$next[0:0]$10215 - attribute \src "libresoc.v:171254.3-171255.43" + attribute \src "libresoc.v:173486.3-173498.6" + wire $0\dive_abs_ov32$next[0:0]$10260 + attribute \src "libresoc.v:173302.3-173303.43" wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:171451.3-171463.6" - wire $0\dive_abs_ov64$next[0:0]$10218 - attribute \src "libresoc.v:171252.3-171253.43" + attribute \src "libresoc.v:173499.3-173511.6" + wire $0\dive_abs_ov64$next[0:0]$10263 + attribute \src "libresoc.v:173300.3-173301.43" wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:171477.3-171489.6" - wire width 128 $0\dividend$next[127:0]$10224 - attribute \src "libresoc.v:171248.3-171249.33" + attribute \src "libresoc.v:173525.3-173537.6" + wire width 128 $0\dividend$next[127:0]$10269 + attribute \src "libresoc.v:173296.3-173297.33" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:171425.3-171437.6" - wire $0\dividend_neg$next[0:0]$10212 - attribute \src "libresoc.v:171256.3-171257.41" + attribute \src "libresoc.v:173473.3-173485.6" + wire $0\dividend_neg$next[0:0]$10257 + attribute \src "libresoc.v:173304.3-173305.41" wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:171412.3-171424.6" - wire $0\divisor_neg$next[0:0]$10209 - attribute \src "libresoc.v:171258.3-171259.39" + attribute \src "libresoc.v:173460.3-173472.6" + wire $0\divisor_neg$next[0:0]$10254 + attribute \src "libresoc.v:173306.3-173307.39" wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:171490.3-171502.6" - wire width 64 $0\divisor_radicand$next[63:0]$10227 - attribute \src "libresoc.v:171246.3-171247.49" + attribute \src "libresoc.v:173538.3-173550.6" + wire width 64 $0\divisor_radicand$next[63:0]$10272 + attribute \src "libresoc.v:173294.3-173295.49" wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:170128.7-170128.20" + attribute \src "libresoc.v:172162.7-172162.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 4 $0\logical_op__data_len$next[3:0]$10240 - attribute \src "libresoc.v:171298.3-171299.57" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10285 + attribute \src "libresoc.v:173346.3-173347.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 13 $0\logical_op__fn_unit$next[12:0]$10241 - attribute \src "libresoc.v:171268.3-171269.55" - wire width 13 $0\logical_op__fn_unit[12:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$10242 - attribute \src "libresoc.v:171270.3-171271.69" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$10286 + attribute \src "libresoc.v:173316.3-173317.55" + wire width 14 $0\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10287 + attribute \src "libresoc.v:173318.3-173319.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__imm_data__ok$next[0:0]$10243 - attribute \src "libresoc.v:171272.3-171273.65" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10288 + attribute \src "libresoc.v:173320.3-173321.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$10244 - attribute \src "libresoc.v:171286.3-171287.63" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10289 + attribute \src "libresoc.v:173334.3-173335.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 32 $0\logical_op__insn$next[31:0]$10245 - attribute \src "libresoc.v:171300.3-171301.49" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 32 $0\logical_op__insn$next[31:0]$10290 + attribute \src "libresoc.v:173348.3-173349.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$10246 - attribute \src "libresoc.v:171266.3-171267.59" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10291 + attribute \src "libresoc.v:173314.3-173315.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__invert_in$next[0:0]$10247 - attribute \src "libresoc.v:171282.3-171283.59" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__invert_in$next[0:0]$10292 + attribute \src "libresoc.v:173330.3-173331.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__invert_out$next[0:0]$10248 - attribute \src "libresoc.v:171288.3-171289.61" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__invert_out$next[0:0]$10293 + attribute \src "libresoc.v:173336.3-173337.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__is_32bit$next[0:0]$10249 - attribute \src "libresoc.v:171294.3-171295.57" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__is_32bit$next[0:0]$10294 + attribute \src "libresoc.v:173342.3-173343.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__is_signed$next[0:0]$10250 - attribute \src "libresoc.v:171296.3-171297.59" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__is_signed$next[0:0]$10295 + attribute \src "libresoc.v:173344.3-173345.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__oe__oe$next[0:0]$10251 - attribute \src "libresoc.v:171278.3-171279.53" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__oe__oe$next[0:0]$10296 + attribute \src "libresoc.v:173326.3-173327.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__oe__ok$next[0:0]$10252 - attribute \src "libresoc.v:171280.3-171281.53" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__oe__ok$next[0:0]$10297 + attribute \src "libresoc.v:173328.3-173329.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__output_carry$next[0:0]$10253 - attribute \src "libresoc.v:171292.3-171293.65" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__output_carry$next[0:0]$10298 + attribute \src "libresoc.v:173340.3-173341.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__rc__ok$next[0:0]$10254 - attribute \src "libresoc.v:171276.3-171277.53" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__rc__ok$next[0:0]$10299 + attribute \src "libresoc.v:173324.3-173325.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__rc__rc$next[0:0]$10255 - attribute \src "libresoc.v:171274.3-171275.53" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__rc__rc$next[0:0]$10300 + attribute \src "libresoc.v:173322.3-173323.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__write_cr0$next[0:0]$10256 - attribute \src "libresoc.v:171290.3-171291.59" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__write_cr0$next[0:0]$10301 + attribute \src "libresoc.v:173338.3-173339.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $0\logical_op__zero_a$next[0:0]$10257 - attribute \src "libresoc.v:171284.3-171285.53" + attribute \src "libresoc.v:173595.3-173636.6" + wire $0\logical_op__zero_a$next[0:0]$10302 + attribute \src "libresoc.v:173332.3-173333.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:171534.3-171546.6" - wire width 2 $0\muxid$next[1:0]$10237 - attribute \src "libresoc.v:171302.3-171303.27" + attribute \src "libresoc.v:173582.3-173594.6" + wire width 2 $0\muxid$next[1:0]$10282 + attribute \src "libresoc.v:173350.3-173351.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:171503.3-171515.6" - wire width 2 $0\operation$next[1:0]$10230 - attribute \src "libresoc.v:171244.3-171245.35" + attribute \src "libresoc.v:173551.3-173563.6" + wire width 2 $0\operation$next[1:0]$10275 + attribute \src "libresoc.v:173292.3-173293.35" wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:171516.3-171533.6" - wire $0\r_busy$next[0:0]$10233 - attribute \src "libresoc.v:171304.3-171305.29" + attribute \src "libresoc.v:173564.3-173581.6" + wire $0\r_busy$next[0:0]$10278 + attribute \src "libresoc.v:173352.3-173353.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:171589.3-171601.6" - wire width 64 $0\ra$next[63:0]$10283 - attribute \src "libresoc.v:171264.3-171265.21" + attribute \src "libresoc.v:173637.3-173649.6" + wire width 64 $0\ra$next[63:0]$10328 + attribute \src "libresoc.v:173312.3-173313.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:171602.3-171614.6" - wire width 64 $0\rb$next[63:0]$10286 - attribute \src "libresoc.v:171262.3-171263.21" + attribute \src "libresoc.v:173650.3-173662.6" + wire width 64 $0\rb$next[63:0]$10331 + attribute \src "libresoc.v:173310.3-173311.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:171615.3-171627.6" - wire $0\xer_so$next[0:0]$10289 - attribute \src "libresoc.v:171260.3-171261.29" + attribute \src "libresoc.v:173663.3-173675.6" + wire $0\xer_so$next[0:0]$10334 + attribute \src "libresoc.v:173308.3-173309.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:171464.3-171476.6" - wire $1\div_by_zero$next[0:0]$10222 - attribute \src "libresoc.v:170137.7-170137.25" + attribute \src "libresoc.v:173512.3-173524.6" + wire $1\div_by_zero$next[0:0]$10267 + attribute \src "libresoc.v:172171.7-172171.25" wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:171438.3-171450.6" - wire $1\dive_abs_ov32$next[0:0]$10216 - attribute \src "libresoc.v:170144.7-170144.27" + attribute \src "libresoc.v:173486.3-173498.6" + wire $1\dive_abs_ov32$next[0:0]$10261 + attribute \src "libresoc.v:172178.7-172178.27" wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:171451.3-171463.6" - wire $1\dive_abs_ov64$next[0:0]$10219 - attribute \src "libresoc.v:170151.7-170151.27" + attribute \src "libresoc.v:173499.3-173511.6" + wire $1\dive_abs_ov64$next[0:0]$10264 + attribute \src "libresoc.v:172185.7-172185.27" wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:171477.3-171489.6" - wire width 128 $1\dividend$next[127:0]$10225 - attribute \src "libresoc.v:170158.15-170158.63" + attribute \src "libresoc.v:173525.3-173537.6" + wire width 128 $1\dividend$next[127:0]$10270 + attribute \src "libresoc.v:172192.15-172192.63" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:171425.3-171437.6" - wire $1\dividend_neg$next[0:0]$10213 - attribute \src "libresoc.v:170165.7-170165.26" + attribute \src "libresoc.v:173473.3-173485.6" + wire $1\dividend_neg$next[0:0]$10258 + attribute \src "libresoc.v:172199.7-172199.26" wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:171412.3-171424.6" - wire $1\divisor_neg$next[0:0]$10210 - attribute \src "libresoc.v:170172.7-170172.25" + attribute \src "libresoc.v:173460.3-173472.6" + wire $1\divisor_neg$next[0:0]$10255 + attribute \src "libresoc.v:172206.7-172206.25" wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:171490.3-171502.6" - wire width 64 $1\divisor_radicand$next[63:0]$10228 - attribute \src "libresoc.v:170179.14-170179.53" + attribute \src "libresoc.v:173538.3-173550.6" + wire width 64 $1\divisor_radicand$next[63:0]$10273 + attribute \src "libresoc.v:172213.14-172213.53" wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 4 $1\logical_op__data_len$next[3:0]$10258 - attribute \src "libresoc.v:170458.13-170458.40" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10303 + attribute \src "libresoc.v:172496.13-172496.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 13 $1\logical_op__fn_unit$next[12:0]$10259 - attribute \src "libresoc.v:170481.14-170481.44" - wire width 13 $1\logical_op__fn_unit[12:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$10260 - attribute \src "libresoc.v:170518.14-170518.63" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$10304 + attribute \src "libresoc.v:172520.14-172520.44" + wire width 14 $1\logical_op__fn_unit[13:0] + attribute \src "libresoc.v:173595.3-173636.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10305 + attribute \src "libresoc.v:172559.14-172559.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__imm_data__ok$next[0:0]$10261 - attribute \src "libresoc.v:170527.7-170527.38" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10306 + attribute \src "libresoc.v:172568.7-172568.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$10262 - attribute \src "libresoc.v:170540.13-170540.43" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10307 + attribute \src "libresoc.v:172581.13-172581.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 32 $1\logical_op__insn$next[31:0]$10263 - attribute \src "libresoc.v:170557.14-170557.38" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 32 $1\logical_op__insn$next[31:0]$10308 + attribute \src "libresoc.v:172598.14-172598.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$10264 - attribute \src "libresoc.v:170640.13-170640.42" + attribute \src "libresoc.v:173595.3-173636.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10309 + attribute \src "libresoc.v:172682.13-172682.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__invert_in$next[0:0]$10265 - attribute \src "libresoc.v:170797.7-170797.35" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__invert_in$next[0:0]$10310 + attribute \src "libresoc.v:172841.7-172841.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__invert_out$next[0:0]$10266 - attribute \src "libresoc.v:170806.7-170806.36" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__invert_out$next[0:0]$10311 + attribute \src "libresoc.v:172850.7-172850.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__is_32bit$next[0:0]$10267 - attribute \src "libresoc.v:170815.7-170815.34" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__is_32bit$next[0:0]$10312 + attribute \src "libresoc.v:172859.7-172859.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__is_signed$next[0:0]$10268 - attribute \src "libresoc.v:170824.7-170824.35" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__is_signed$next[0:0]$10313 + attribute \src "libresoc.v:172868.7-172868.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__oe__oe$next[0:0]$10269 - attribute \src "libresoc.v:170833.7-170833.32" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__oe__oe$next[0:0]$10314 + attribute \src "libresoc.v:172877.7-172877.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__oe__ok$next[0:0]$10270 - attribute \src "libresoc.v:170842.7-170842.32" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__oe__ok$next[0:0]$10315 + attribute \src "libresoc.v:172886.7-172886.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__output_carry$next[0:0]$10271 - attribute \src "libresoc.v:170851.7-170851.38" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__output_carry$next[0:0]$10316 + attribute \src "libresoc.v:172895.7-172895.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__rc__ok$next[0:0]$10272 - attribute \src "libresoc.v:170860.7-170860.32" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__rc__ok$next[0:0]$10317 + attribute \src "libresoc.v:172904.7-172904.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__rc__rc$next[0:0]$10273 - attribute \src "libresoc.v:170869.7-170869.32" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__rc__rc$next[0:0]$10318 + attribute \src "libresoc.v:172913.7-172913.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__write_cr0$next[0:0]$10274 - attribute \src "libresoc.v:170878.7-170878.35" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__write_cr0$next[0:0]$10319 + attribute \src "libresoc.v:172922.7-172922.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire $1\logical_op__zero_a$next[0:0]$10275 - attribute \src "libresoc.v:170887.7-170887.32" + attribute \src "libresoc.v:173595.3-173636.6" + wire $1\logical_op__zero_a$next[0:0]$10320 + attribute \src "libresoc.v:172931.7-172931.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:171534.3-171546.6" - wire width 2 $1\muxid$next[1:0]$10238 - attribute \src "libresoc.v:170896.13-170896.25" + attribute \src "libresoc.v:173582.3-173594.6" + wire width 2 $1\muxid$next[1:0]$10283 + attribute \src "libresoc.v:172940.13-172940.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:171503.3-171515.6" - wire width 2 $1\operation$next[1:0]$10231 - attribute \src "libresoc.v:170911.13-170911.29" + attribute \src "libresoc.v:173551.3-173563.6" + wire width 2 $1\operation$next[1:0]$10276 + attribute \src "libresoc.v:172955.13-172955.29" wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:171516.3-171533.6" - wire $1\r_busy$next[0:0]$10234 - attribute \src "libresoc.v:170925.7-170925.20" + attribute \src "libresoc.v:173564.3-173581.6" + wire $1\r_busy$next[0:0]$10279 + attribute \src "libresoc.v:172969.7-172969.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:171589.3-171601.6" - wire width 64 $1\ra$next[63:0]$10284 - attribute \src "libresoc.v:170930.14-170930.39" + attribute \src "libresoc.v:173637.3-173649.6" + wire width 64 $1\ra$next[63:0]$10329 + attribute \src "libresoc.v:172974.14-172974.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:171602.3-171614.6" - wire width 64 $1\rb$next[63:0]$10287 - attribute \src "libresoc.v:170941.14-170941.39" + attribute \src "libresoc.v:173650.3-173662.6" + wire width 64 $1\rb$next[63:0]$10332 + attribute \src "libresoc.v:172985.14-172985.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:171615.3-171627.6" - wire $1\xer_so$next[0:0]$10290 - attribute \src "libresoc.v:171236.7-171236.20" + attribute \src "libresoc.v:173663.3-173675.6" + wire $1\xer_so$next[0:0]$10335 + attribute \src "libresoc.v:173284.7-173284.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:171547.3-171588.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$10276 - attribute \src "libresoc.v:171547.3-171588.6" - wire $2\logical_op__imm_data__ok$next[0:0]$10277 - attribute \src "libresoc.v:171547.3-171588.6" - wire $2\logical_op__oe__oe$next[0:0]$10278 - attribute \src "libresoc.v:171547.3-171588.6" - wire $2\logical_op__oe__ok$next[0:0]$10279 - attribute \src "libresoc.v:171547.3-171588.6" - wire $2\logical_op__rc__ok$next[0:0]$10280 - attribute \src "libresoc.v:171547.3-171588.6" - wire $2\logical_op__rc__rc$next[0:0]$10281 - attribute \src "libresoc.v:171516.3-171533.6" - wire $2\r_busy$next[0:0]$10235 - attribute \src "libresoc.v:171243.18-171243.118" - wire $and$libresoc.v:171243$10176_Y + attribute \src "libresoc.v:173595.3-173636.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10321 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10322 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__oe__oe$next[0:0]$10323 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__oe__ok$next[0:0]$10324 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__rc__ok$next[0:0]$10325 + attribute \src "libresoc.v:173595.3-173636.6" + wire $2\logical_op__rc__rc$next[0:0]$10326 + attribute \src "libresoc.v:173564.3-173581.6" + wire $2\r_busy$next[0:0]$10280 + attribute \src "libresoc.v:173291.18-173291.118" + wire $and$libresoc.v:173291$10221_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 30 \div_by_zero @@ -351637,44 +354366,46 @@ module \pipe_start wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:170128.7-170128.15" + attribute \src "libresoc.v:172162.7-172162.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len$40 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_logical_op__fn_unit$25 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \input_logical_op__fn_unit$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -351773,6 +354504,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -351849,6 +354581,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -351920,55 +354653,58 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 6 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 38 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 38 \logical_op__fn_unit$3 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -352087,6 +354823,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -352163,6 +354900,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 37 \logical_op__insn_type$2 attribute \enum_base_type "MicrOp" @@ -352239,6 +354977,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -352402,37 +355141,39 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \setup_stage_logical_op__data_len$62 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \setup_stage_logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \setup_stage_logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \setup_stage_logical_op__fn_unit$47 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \setup_stage_logical_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \setup_stage_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -352531,6 +355272,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \setup_stage_logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -352607,6 +355349,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \setup_stage_logical_op__insn_type$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -352676,7 +355419,7 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:171243$10176 + cell $and $and$libresoc.v:173291$10221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352684,10 +355427,10 @@ module \pipe_start parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $and$libresoc.v:171243$10176_Y + connect \Y $and$libresoc.v:173291$10221_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:171306.14-171351.4" + attribute \src "libresoc.v:173354.14-173399.4" cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 @@ -352735,19 +355478,19 @@ module \pipe_start connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 - attribute \src "libresoc.v:171352.10-171355.4" + attribute \src "libresoc.v:173400.10-173403.4" cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:171356.10-171359.4" + attribute \src "libresoc.v:173404.10-173407.4" cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:171360.15-171411.4" + attribute \src "libresoc.v:173408.15-173459.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 @@ -352800,487 +355543,487 @@ module \pipe_start connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "libresoc.v:170128.7-170128.20" - process $proc$libresoc.v:170128$10291 + attribute \src "libresoc.v:172162.7-172162.20" + process $proc$libresoc.v:172162$10336 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170137.7-170137.25" - process $proc$libresoc.v:170137$10292 + attribute \src "libresoc.v:172171.7-172171.25" + process $proc$libresoc.v:172171$10337 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "libresoc.v:170144.7-170144.27" - process $proc$libresoc.v:170144$10293 + attribute \src "libresoc.v:172178.7-172178.27" + process $proc$libresoc.v:172178$10338 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:170151.7-170151.27" - process $proc$libresoc.v:170151$10294 + attribute \src "libresoc.v:172185.7-172185.27" + process $proc$libresoc.v:172185$10339 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:170158.15-170158.63" - process $proc$libresoc.v:170158$10295 + attribute \src "libresoc.v:172192.15-172192.63" + process $proc$libresoc.v:172192$10340 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end - attribute \src "libresoc.v:170165.7-170165.26" - process $proc$libresoc.v:170165$10296 + attribute \src "libresoc.v:172199.7-172199.26" + process $proc$libresoc.v:172199$10341 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "libresoc.v:170172.7-170172.25" - process $proc$libresoc.v:170172$10297 + attribute \src "libresoc.v:172206.7-172206.25" + process $proc$libresoc.v:172206$10342 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "libresoc.v:170179.14-170179.53" - process $proc$libresoc.v:170179$10298 + attribute \src "libresoc.v:172213.14-172213.53" + process $proc$libresoc.v:172213$10343 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "libresoc.v:170458.13-170458.40" - process $proc$libresoc.v:170458$10299 + attribute \src "libresoc.v:172496.13-172496.40" + process $proc$libresoc.v:172496$10344 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:170481.14-170481.44" - process $proc$libresoc.v:170481$10300 + attribute \src "libresoc.v:172520.14-172520.44" + process $proc$libresoc.v:172520$10345 assign { } { } - assign $1\logical_op__fn_unit[12:0] 13'0000000000000 + assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[12:0] + update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:170518.14-170518.63" - process $proc$libresoc.v:170518$10301 + attribute \src "libresoc.v:172559.14-172559.63" + process $proc$libresoc.v:172559$10346 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:170527.7-170527.38" - process $proc$libresoc.v:170527$10302 + attribute \src "libresoc.v:172568.7-172568.38" + process $proc$libresoc.v:172568$10347 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:170540.13-170540.43" - process $proc$libresoc.v:170540$10303 + attribute \src "libresoc.v:172581.13-172581.43" + process $proc$libresoc.v:172581$10348 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:170557.14-170557.38" - process $proc$libresoc.v:170557$10304 + attribute \src "libresoc.v:172598.14-172598.38" + process $proc$libresoc.v:172598$10349 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:170640.13-170640.42" - process $proc$libresoc.v:170640$10305 + attribute \src "libresoc.v:172682.13-172682.42" + process $proc$libresoc.v:172682$10350 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:170797.7-170797.35" - process $proc$libresoc.v:170797$10306 + attribute \src "libresoc.v:172841.7-172841.35" + process $proc$libresoc.v:172841$10351 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:170806.7-170806.36" - process $proc$libresoc.v:170806$10307 + attribute \src "libresoc.v:172850.7-172850.36" + process $proc$libresoc.v:172850$10352 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:170815.7-170815.34" - process $proc$libresoc.v:170815$10308 + attribute \src "libresoc.v:172859.7-172859.34" + process $proc$libresoc.v:172859$10353 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:170824.7-170824.35" - process $proc$libresoc.v:170824$10309 + attribute \src "libresoc.v:172868.7-172868.35" + process $proc$libresoc.v:172868$10354 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:170833.7-170833.32" - process $proc$libresoc.v:170833$10310 + attribute \src "libresoc.v:172877.7-172877.32" + process $proc$libresoc.v:172877$10355 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:170842.7-170842.32" - process $proc$libresoc.v:170842$10311 + attribute \src "libresoc.v:172886.7-172886.32" + process $proc$libresoc.v:172886$10356 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:170851.7-170851.38" - process $proc$libresoc.v:170851$10312 + attribute \src "libresoc.v:172895.7-172895.38" + process $proc$libresoc.v:172895$10357 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:170860.7-170860.32" - process $proc$libresoc.v:170860$10313 + attribute \src "libresoc.v:172904.7-172904.32" + process $proc$libresoc.v:172904$10358 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:170869.7-170869.32" - process $proc$libresoc.v:170869$10314 + attribute \src "libresoc.v:172913.7-172913.32" + process $proc$libresoc.v:172913$10359 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:170878.7-170878.35" - process $proc$libresoc.v:170878$10315 + attribute \src "libresoc.v:172922.7-172922.35" + process $proc$libresoc.v:172922$10360 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:170887.7-170887.32" - process $proc$libresoc.v:170887$10316 + attribute \src "libresoc.v:172931.7-172931.32" + process $proc$libresoc.v:172931$10361 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:170896.13-170896.25" - process $proc$libresoc.v:170896$10317 + attribute \src "libresoc.v:172940.13-172940.25" + process $proc$libresoc.v:172940$10362 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:170911.13-170911.29" - process $proc$libresoc.v:170911$10318 + attribute \src "libresoc.v:172955.13-172955.29" + process $proc$libresoc.v:172955$10363 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end - attribute \src "libresoc.v:170925.7-170925.20" - process $proc$libresoc.v:170925$10319 + attribute \src "libresoc.v:172969.7-172969.20" + process $proc$libresoc.v:172969$10364 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:170930.14-170930.39" - process $proc$libresoc.v:170930$10320 + attribute \src "libresoc.v:172974.14-172974.39" + process $proc$libresoc.v:172974$10365 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:170941.14-170941.39" - process $proc$libresoc.v:170941$10321 + attribute \src "libresoc.v:172985.14-172985.39" + process $proc$libresoc.v:172985$10366 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:171236.7-171236.20" - process $proc$libresoc.v:171236$10322 + attribute \src "libresoc.v:173284.7-173284.20" + process $proc$libresoc.v:173284$10367 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:171244.3-171245.35" - process $proc$libresoc.v:171244$10177 + attribute \src "libresoc.v:173292.3-173293.35" + process $proc$libresoc.v:173292$10222 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end - attribute \src "libresoc.v:171246.3-171247.49" - process $proc$libresoc.v:171246$10178 + attribute \src "libresoc.v:173294.3-173295.49" + process $proc$libresoc.v:173294$10223 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "libresoc.v:171248.3-171249.33" - process $proc$libresoc.v:171248$10179 + attribute \src "libresoc.v:173296.3-173297.33" + process $proc$libresoc.v:173296$10224 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end - attribute \src "libresoc.v:171250.3-171251.39" - process $proc$libresoc.v:171250$10180 + attribute \src "libresoc.v:173298.3-173299.39" + process $proc$libresoc.v:173298$10225 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "libresoc.v:171252.3-171253.43" - process $proc$libresoc.v:171252$10181 + attribute \src "libresoc.v:173300.3-173301.43" + process $proc$libresoc.v:173300$10226 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:171254.3-171255.43" - process $proc$libresoc.v:171254$10182 + attribute \src "libresoc.v:173302.3-173303.43" + process $proc$libresoc.v:173302$10227 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:171256.3-171257.41" - process $proc$libresoc.v:171256$10183 + attribute \src "libresoc.v:173304.3-173305.41" + process $proc$libresoc.v:173304$10228 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "libresoc.v:171258.3-171259.39" - process $proc$libresoc.v:171258$10184 + attribute \src "libresoc.v:173306.3-173307.39" + process $proc$libresoc.v:173306$10229 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "libresoc.v:171260.3-171261.29" - process $proc$libresoc.v:171260$10185 + attribute \src "libresoc.v:173308.3-173309.29" + process $proc$libresoc.v:173308$10230 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:171262.3-171263.21" - process $proc$libresoc.v:171262$10186 + attribute \src "libresoc.v:173310.3-173311.21" + process $proc$libresoc.v:173310$10231 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:171264.3-171265.21" - process $proc$libresoc.v:171264$10187 + attribute \src "libresoc.v:173312.3-173313.21" + process $proc$libresoc.v:173312$10232 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:171266.3-171267.59" - process $proc$libresoc.v:171266$10188 + attribute \src "libresoc.v:173314.3-173315.59" + process $proc$libresoc.v:173314$10233 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:171268.3-171269.55" - process $proc$libresoc.v:171268$10189 + attribute \src "libresoc.v:173316.3-173317.55" + process $proc$libresoc.v:173316$10234 assign { } { } - assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next + assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[12:0] + update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:171270.3-171271.69" - process $proc$libresoc.v:171270$10190 + attribute \src "libresoc.v:173318.3-173319.69" + process $proc$libresoc.v:173318$10235 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:171272.3-171273.65" - process $proc$libresoc.v:171272$10191 + attribute \src "libresoc.v:173320.3-173321.65" + process $proc$libresoc.v:173320$10236 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:171274.3-171275.53" - process $proc$libresoc.v:171274$10192 + attribute \src "libresoc.v:173322.3-173323.53" + process $proc$libresoc.v:173322$10237 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:171276.3-171277.53" - process $proc$libresoc.v:171276$10193 + attribute \src "libresoc.v:173324.3-173325.53" + process $proc$libresoc.v:173324$10238 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:171278.3-171279.53" - process $proc$libresoc.v:171278$10194 + attribute \src "libresoc.v:173326.3-173327.53" + process $proc$libresoc.v:173326$10239 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:171280.3-171281.53" - process $proc$libresoc.v:171280$10195 + attribute \src "libresoc.v:173328.3-173329.53" + process $proc$libresoc.v:173328$10240 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:171282.3-171283.59" - process $proc$libresoc.v:171282$10196 + attribute \src "libresoc.v:173330.3-173331.59" + process $proc$libresoc.v:173330$10241 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:171284.3-171285.53" - process $proc$libresoc.v:171284$10197 + attribute \src "libresoc.v:173332.3-173333.53" + process $proc$libresoc.v:173332$10242 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:171286.3-171287.63" - process $proc$libresoc.v:171286$10198 + attribute \src "libresoc.v:173334.3-173335.63" + process $proc$libresoc.v:173334$10243 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:171288.3-171289.61" - process $proc$libresoc.v:171288$10199 + attribute \src "libresoc.v:173336.3-173337.61" + process $proc$libresoc.v:173336$10244 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:171290.3-171291.59" - process $proc$libresoc.v:171290$10200 + attribute \src "libresoc.v:173338.3-173339.59" + process $proc$libresoc.v:173338$10245 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:171292.3-171293.65" - process $proc$libresoc.v:171292$10201 + attribute \src "libresoc.v:173340.3-173341.65" + process $proc$libresoc.v:173340$10246 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:171294.3-171295.57" - process $proc$libresoc.v:171294$10202 + attribute \src "libresoc.v:173342.3-173343.57" + process $proc$libresoc.v:173342$10247 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:171296.3-171297.59" - process $proc$libresoc.v:171296$10203 + attribute \src "libresoc.v:173344.3-173345.59" + process $proc$libresoc.v:173344$10248 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:171298.3-171299.57" - process $proc$libresoc.v:171298$10204 + attribute \src "libresoc.v:173346.3-173347.57" + process $proc$libresoc.v:173346$10249 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:171300.3-171301.49" - process $proc$libresoc.v:171300$10205 + attribute \src "libresoc.v:173348.3-173349.49" + process $proc$libresoc.v:173348$10250 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:171302.3-171303.27" - process $proc$libresoc.v:171302$10206 + attribute \src "libresoc.v:173350.3-173351.27" + process $proc$libresoc.v:173350$10251 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:171304.3-171305.29" - process $proc$libresoc.v:171304$10207 + attribute \src "libresoc.v:173352.3-173353.29" + process $proc$libresoc.v:173352$10252 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:171412.3-171424.6" - process $proc$libresoc.v:171412$10208 + attribute \src "libresoc.v:173460.3-173472.6" + process $proc$libresoc.v:173460$10253 assign { } { } assign { } { } - assign $0\divisor_neg$next[0:0]$10209 $1\divisor_neg$next[0:0]$10210 - attribute \src "libresoc.v:171413.5-171413.29" + assign $0\divisor_neg$next[0:0]$10254 $1\divisor_neg$next[0:0]$10255 + attribute \src "libresoc.v:173461.5-173461.29" switch \initial - attribute \src "libresoc.v:171413.9-171413.17" + attribute \src "libresoc.v:173461.9-173461.17" case 1'1 case end @@ -353289,25 +356032,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_neg$next[0:0]$10210 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10255 \divisor_neg$92 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_neg$next[0:0]$10210 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10255 \divisor_neg$92 case - assign $1\divisor_neg$next[0:0]$10210 \divisor_neg + assign $1\divisor_neg$next[0:0]$10255 \divisor_neg end sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$10209 + update \divisor_neg$next $0\divisor_neg$next[0:0]$10254 end - attribute \src "libresoc.v:171425.3-171437.6" - process $proc$libresoc.v:171425$10211 + attribute \src "libresoc.v:173473.3-173485.6" + process $proc$libresoc.v:173473$10256 assign { } { } assign { } { } - assign $0\dividend_neg$next[0:0]$10212 $1\dividend_neg$next[0:0]$10213 - attribute \src "libresoc.v:171426.5-171426.29" + assign $0\dividend_neg$next[0:0]$10257 $1\dividend_neg$next[0:0]$10258 + attribute \src "libresoc.v:173474.5-173474.29" switch \initial - attribute \src "libresoc.v:171426.9-171426.17" + attribute \src "libresoc.v:173474.9-173474.17" case 1'1 case end @@ -353316,25 +356059,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend_neg$next[0:0]$10213 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10258 \dividend_neg$93 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend_neg$next[0:0]$10213 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10258 \dividend_neg$93 case - assign $1\dividend_neg$next[0:0]$10213 \dividend_neg + assign $1\dividend_neg$next[0:0]$10258 \dividend_neg end sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$10212 + update \dividend_neg$next $0\dividend_neg$next[0:0]$10257 end - attribute \src "libresoc.v:171438.3-171450.6" - process $proc$libresoc.v:171438$10214 + attribute \src "libresoc.v:173486.3-173498.6" + process $proc$libresoc.v:173486$10259 assign { } { } assign { } { } - assign $0\dive_abs_ov32$next[0:0]$10215 $1\dive_abs_ov32$next[0:0]$10216 - attribute \src "libresoc.v:171439.5-171439.29" + assign $0\dive_abs_ov32$next[0:0]$10260 $1\dive_abs_ov32$next[0:0]$10261 + attribute \src "libresoc.v:173487.5-173487.29" switch \initial - attribute \src "libresoc.v:171439.9-171439.17" + attribute \src "libresoc.v:173487.9-173487.17" case 1'1 case end @@ -353343,25 +356086,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10216 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32$94 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10216 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32$94 case - assign $1\dive_abs_ov32$next[0:0]$10216 \dive_abs_ov32 + assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32 end sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10215 + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10260 end - attribute \src "libresoc.v:171451.3-171463.6" - process $proc$libresoc.v:171451$10217 + attribute \src "libresoc.v:173499.3-173511.6" + process $proc$libresoc.v:173499$10262 assign { } { } assign { } { } - assign $0\dive_abs_ov64$next[0:0]$10218 $1\dive_abs_ov64$next[0:0]$10219 - attribute \src "libresoc.v:171452.5-171452.29" + assign $0\dive_abs_ov64$next[0:0]$10263 $1\dive_abs_ov64$next[0:0]$10264 + attribute \src "libresoc.v:173500.5-173500.29" switch \initial - attribute \src "libresoc.v:171452.9-171452.17" + attribute \src "libresoc.v:173500.9-173500.17" case 1'1 case end @@ -353370,25 +356113,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10219 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64$95 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10219 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64$95 case - assign $1\dive_abs_ov64$next[0:0]$10219 \dive_abs_ov64 + assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64 end sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10218 + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10263 end - attribute \src "libresoc.v:171464.3-171476.6" - process $proc$libresoc.v:171464$10220 + attribute \src "libresoc.v:173512.3-173524.6" + process $proc$libresoc.v:173512$10265 assign { } { } assign { } { } - assign $0\div_by_zero$next[0:0]$10221 $1\div_by_zero$next[0:0]$10222 - attribute \src "libresoc.v:171465.5-171465.29" + assign $0\div_by_zero$next[0:0]$10266 $1\div_by_zero$next[0:0]$10267 + attribute \src "libresoc.v:173513.5-173513.29" switch \initial - attribute \src "libresoc.v:171465.9-171465.17" + attribute \src "libresoc.v:173513.9-173513.17" case 1'1 case end @@ -353397,25 +356140,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\div_by_zero$next[0:0]$10222 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10267 \div_by_zero$96 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\div_by_zero$next[0:0]$10222 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10267 \div_by_zero$96 case - assign $1\div_by_zero$next[0:0]$10222 \div_by_zero + assign $1\div_by_zero$next[0:0]$10267 \div_by_zero end sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$10221 + update \div_by_zero$next $0\div_by_zero$next[0:0]$10266 end - attribute \src "libresoc.v:171477.3-171489.6" - process $proc$libresoc.v:171477$10223 + attribute \src "libresoc.v:173525.3-173537.6" + process $proc$libresoc.v:173525$10268 assign { } { } assign { } { } - assign $0\dividend$next[127:0]$10224 $1\dividend$next[127:0]$10225 - attribute \src "libresoc.v:171478.5-171478.29" + assign $0\dividend$next[127:0]$10269 $1\dividend$next[127:0]$10270 + attribute \src "libresoc.v:173526.5-173526.29" switch \initial - attribute \src "libresoc.v:171478.9-171478.17" + attribute \src "libresoc.v:173526.9-173526.17" case 1'1 case end @@ -353424,25 +356167,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend$next[127:0]$10225 \dividend$97 + assign $1\dividend$next[127:0]$10270 \dividend$97 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend$next[127:0]$10225 \dividend$97 + assign $1\dividend$next[127:0]$10270 \dividend$97 case - assign $1\dividend$next[127:0]$10225 \dividend + assign $1\dividend$next[127:0]$10270 \dividend end sync always - update \dividend$next $0\dividend$next[127:0]$10224 + update \dividend$next $0\dividend$next[127:0]$10269 end - attribute \src "libresoc.v:171490.3-171502.6" - process $proc$libresoc.v:171490$10226 + attribute \src "libresoc.v:173538.3-173550.6" + process $proc$libresoc.v:173538$10271 assign { } { } assign { } { } - assign $0\divisor_radicand$next[63:0]$10227 $1\divisor_radicand$next[63:0]$10228 - attribute \src "libresoc.v:171491.5-171491.29" + assign $0\divisor_radicand$next[63:0]$10272 $1\divisor_radicand$next[63:0]$10273 + attribute \src "libresoc.v:173539.5-173539.29" switch \initial - attribute \src "libresoc.v:171491.9-171491.17" + attribute \src "libresoc.v:173539.9-173539.17" case 1'1 case end @@ -353451,25 +356194,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_radicand$next[63:0]$10228 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand$98 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_radicand$next[63:0]$10228 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand$98 case - assign $1\divisor_radicand$next[63:0]$10228 \divisor_radicand + assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand end sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10227 + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10272 end - attribute \src "libresoc.v:171503.3-171515.6" - process $proc$libresoc.v:171503$10229 + attribute \src "libresoc.v:173551.3-173563.6" + process $proc$libresoc.v:173551$10274 assign { } { } assign { } { } - assign $0\operation$next[1:0]$10230 $1\operation$next[1:0]$10231 - attribute \src "libresoc.v:171504.5-171504.29" + assign $0\operation$next[1:0]$10275 $1\operation$next[1:0]$10276 + attribute \src "libresoc.v:173552.5-173552.29" switch \initial - attribute \src "libresoc.v:171504.9-171504.17" + attribute \src "libresoc.v:173552.9-173552.17" case 1'1 case end @@ -353478,26 +356221,26 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\operation$next[1:0]$10231 \operation$99 + assign $1\operation$next[1:0]$10276 \operation$99 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\operation$next[1:0]$10231 \operation$99 + assign $1\operation$next[1:0]$10276 \operation$99 case - assign $1\operation$next[1:0]$10231 \operation + assign $1\operation$next[1:0]$10276 \operation end sync always - update \operation$next $0\operation$next[1:0]$10230 + update \operation$next $0\operation$next[1:0]$10275 end - attribute \src "libresoc.v:171516.3-171533.6" - process $proc$libresoc.v:171516$10232 + attribute \src "libresoc.v:173564.3-173581.6" + process $proc$libresoc.v:173564$10277 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$10233 $2\r_busy$next[0:0]$10235 - attribute \src "libresoc.v:171517.5-171517.29" + assign $0\r_busy$next[0:0]$10278 $2\r_busy$next[0:0]$10280 + attribute \src "libresoc.v:173565.5-173565.29" switch \initial - attribute \src "libresoc.v:171517.9-171517.17" + attribute \src "libresoc.v:173565.9-173565.17" case 1'1 case end @@ -353506,34 +356249,34 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$10234 1'1 + assign $1\r_busy$next[0:0]$10279 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$10234 1'0 + assign $1\r_busy$next[0:0]$10279 1'0 case - assign $1\r_busy$next[0:0]$10234 \r_busy + assign $1\r_busy$next[0:0]$10279 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$10235 1'0 + assign $2\r_busy$next[0:0]$10280 1'0 case - assign $2\r_busy$next[0:0]$10235 $1\r_busy$next[0:0]$10234 + assign $2\r_busy$next[0:0]$10280 $1\r_busy$next[0:0]$10279 end sync always - update \r_busy$next $0\r_busy$next[0:0]$10233 + update \r_busy$next $0\r_busy$next[0:0]$10278 end - attribute \src "libresoc.v:171534.3-171546.6" - process $proc$libresoc.v:171534$10236 + attribute \src "libresoc.v:173582.3-173594.6" + process $proc$libresoc.v:173582$10281 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$10237 $1\muxid$next[1:0]$10238 - attribute \src "libresoc.v:171535.5-171535.29" + assign $0\muxid$next[1:0]$10282 $1\muxid$next[1:0]$10283 + attribute \src "libresoc.v:173583.5-173583.29" switch \initial - attribute \src "libresoc.v:171535.9-171535.17" + attribute \src "libresoc.v:173583.9-173583.17" case 1'1 case end @@ -353542,19 +356285,19 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$10238 \muxid$68 + assign $1\muxid$next[1:0]$10283 \muxid$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$10238 \muxid$68 + assign $1\muxid$next[1:0]$10283 \muxid$68 case - assign $1\muxid$next[1:0]$10238 \muxid + assign $1\muxid$next[1:0]$10283 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$10237 + update \muxid$next $0\muxid$next[1:0]$10282 end - attribute \src "libresoc.v:171547.3-171588.6" - process $proc$libresoc.v:171547$10239 + attribute \src "libresoc.v:173595.3-173636.6" + process $proc$libresoc.v:173595$10284 assign { } { } assign { } { } assign { } { } @@ -353591,33 +356334,33 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$10240 $1\logical_op__data_len$next[3:0]$10258 - assign $0\logical_op__fn_unit$next[12:0]$10241 $1\logical_op__fn_unit$next[12:0]$10259 + assign $0\logical_op__data_len$next[3:0]$10285 $1\logical_op__data_len$next[3:0]$10303 + assign $0\logical_op__fn_unit$next[13:0]$10286 $1\logical_op__fn_unit$next[13:0]$10304 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$10244 $1\logical_op__input_carry$next[1:0]$10262 - assign $0\logical_op__insn$next[31:0]$10245 $1\logical_op__insn$next[31:0]$10263 - assign $0\logical_op__insn_type$next[6:0]$10246 $1\logical_op__insn_type$next[6:0]$10264 - assign $0\logical_op__invert_in$next[0:0]$10247 $1\logical_op__invert_in$next[0:0]$10265 - assign $0\logical_op__invert_out$next[0:0]$10248 $1\logical_op__invert_out$next[0:0]$10266 - assign $0\logical_op__is_32bit$next[0:0]$10249 $1\logical_op__is_32bit$next[0:0]$10267 - assign $0\logical_op__is_signed$next[0:0]$10250 $1\logical_op__is_signed$next[0:0]$10268 + assign $0\logical_op__input_carry$next[1:0]$10289 $1\logical_op__input_carry$next[1:0]$10307 + assign $0\logical_op__insn$next[31:0]$10290 $1\logical_op__insn$next[31:0]$10308 + assign $0\logical_op__insn_type$next[6:0]$10291 $1\logical_op__insn_type$next[6:0]$10309 + assign $0\logical_op__invert_in$next[0:0]$10292 $1\logical_op__invert_in$next[0:0]$10310 + assign $0\logical_op__invert_out$next[0:0]$10293 $1\logical_op__invert_out$next[0:0]$10311 + assign $0\logical_op__is_32bit$next[0:0]$10294 $1\logical_op__is_32bit$next[0:0]$10312 + assign $0\logical_op__is_signed$next[0:0]$10295 $1\logical_op__is_signed$next[0:0]$10313 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$10253 $1\logical_op__output_carry$next[0:0]$10271 + assign $0\logical_op__output_carry$next[0:0]$10298 $1\logical_op__output_carry$next[0:0]$10316 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$10256 $1\logical_op__write_cr0$next[0:0]$10274 - assign $0\logical_op__zero_a$next[0:0]$10257 $1\logical_op__zero_a$next[0:0]$10275 - assign $0\logical_op__imm_data__data$next[63:0]$10242 $2\logical_op__imm_data__data$next[63:0]$10276 - assign $0\logical_op__imm_data__ok$next[0:0]$10243 $2\logical_op__imm_data__ok$next[0:0]$10277 - assign $0\logical_op__oe__oe$next[0:0]$10251 $2\logical_op__oe__oe$next[0:0]$10278 - assign $0\logical_op__oe__ok$next[0:0]$10252 $2\logical_op__oe__ok$next[0:0]$10279 - assign $0\logical_op__rc__ok$next[0:0]$10254 $2\logical_op__rc__ok$next[0:0]$10280 - assign $0\logical_op__rc__rc$next[0:0]$10255 $2\logical_op__rc__rc$next[0:0]$10281 - attribute \src "libresoc.v:171548.5-171548.29" + assign $0\logical_op__write_cr0$next[0:0]$10301 $1\logical_op__write_cr0$next[0:0]$10319 + assign $0\logical_op__zero_a$next[0:0]$10302 $1\logical_op__zero_a$next[0:0]$10320 + assign $0\logical_op__imm_data__data$next[63:0]$10287 $2\logical_op__imm_data__data$next[63:0]$10321 + assign $0\logical_op__imm_data__ok$next[0:0]$10288 $2\logical_op__imm_data__ok$next[0:0]$10322 + assign $0\logical_op__oe__oe$next[0:0]$10296 $2\logical_op__oe__oe$next[0:0]$10323 + assign $0\logical_op__oe__ok$next[0:0]$10297 $2\logical_op__oe__ok$next[0:0]$10324 + assign $0\logical_op__rc__ok$next[0:0]$10299 $2\logical_op__rc__ok$next[0:0]$10325 + assign $0\logical_op__rc__rc$next[0:0]$10300 $2\logical_op__rc__rc$next[0:0]$10326 + attribute \src "libresoc.v:173596.5-173596.29" switch \initial - attribute \src "libresoc.v:171548.9-171548.17" + attribute \src "libresoc.v:173596.9-173596.17" case 1'1 case end @@ -353643,7 +356386,7 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10263 $1\logical_op__data_len$next[3:0]$10258 $1\logical_op__is_signed$next[0:0]$10268 $1\logical_op__is_32bit$next[0:0]$10267 $1\logical_op__output_carry$next[0:0]$10271 $1\logical_op__write_cr0$next[0:0]$10274 $1\logical_op__invert_out$next[0:0]$10266 $1\logical_op__input_carry$next[1:0]$10262 $1\logical_op__zero_a$next[0:0]$10275 $1\logical_op__invert_in$next[0:0]$10265 $1\logical_op__oe__ok$next[0:0]$10270 $1\logical_op__oe__oe$next[0:0]$10269 $1\logical_op__rc__ok$next[0:0]$10272 $1\logical_op__rc__rc$next[0:0]$10273 $1\logical_op__imm_data__ok$next[0:0]$10261 $1\logical_op__imm_data__data$next[63:0]$10260 $1\logical_op__fn_unit$next[12:0]$10259 $1\logical_op__insn_type$next[6:0]$10264 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10308 $1\logical_op__data_len$next[3:0]$10303 $1\logical_op__is_signed$next[0:0]$10313 $1\logical_op__is_32bit$next[0:0]$10312 $1\logical_op__output_carry$next[0:0]$10316 $1\logical_op__write_cr0$next[0:0]$10319 $1\logical_op__invert_out$next[0:0]$10311 $1\logical_op__input_carry$next[1:0]$10307 $1\logical_op__zero_a$next[0:0]$10320 $1\logical_op__invert_in$next[0:0]$10310 $1\logical_op__oe__ok$next[0:0]$10315 $1\logical_op__oe__oe$next[0:0]$10314 $1\logical_op__rc__ok$next[0:0]$10317 $1\logical_op__rc__rc$next[0:0]$10318 $1\logical_op__imm_data__ok$next[0:0]$10306 $1\logical_op__imm_data__data$next[63:0]$10305 $1\logical_op__fn_unit$next[13:0]$10304 $1\logical_op__insn_type$next[6:0]$10309 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -353664,26 +356407,26 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10263 $1\logical_op__data_len$next[3:0]$10258 $1\logical_op__is_signed$next[0:0]$10268 $1\logical_op__is_32bit$next[0:0]$10267 $1\logical_op__output_carry$next[0:0]$10271 $1\logical_op__write_cr0$next[0:0]$10274 $1\logical_op__invert_out$next[0:0]$10266 $1\logical_op__input_carry$next[1:0]$10262 $1\logical_op__zero_a$next[0:0]$10275 $1\logical_op__invert_in$next[0:0]$10265 $1\logical_op__oe__ok$next[0:0]$10270 $1\logical_op__oe__oe$next[0:0]$10269 $1\logical_op__rc__ok$next[0:0]$10272 $1\logical_op__rc__rc$next[0:0]$10273 $1\logical_op__imm_data__ok$next[0:0]$10261 $1\logical_op__imm_data__data$next[63:0]$10260 $1\logical_op__fn_unit$next[12:0]$10259 $1\logical_op__insn_type$next[6:0]$10264 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10308 $1\logical_op__data_len$next[3:0]$10303 $1\logical_op__is_signed$next[0:0]$10313 $1\logical_op__is_32bit$next[0:0]$10312 $1\logical_op__output_carry$next[0:0]$10316 $1\logical_op__write_cr0$next[0:0]$10319 $1\logical_op__invert_out$next[0:0]$10311 $1\logical_op__input_carry$next[1:0]$10307 $1\logical_op__zero_a$next[0:0]$10320 $1\logical_op__invert_in$next[0:0]$10310 $1\logical_op__oe__ok$next[0:0]$10315 $1\logical_op__oe__oe$next[0:0]$10314 $1\logical_op__rc__ok$next[0:0]$10317 $1\logical_op__rc__rc$next[0:0]$10318 $1\logical_op__imm_data__ok$next[0:0]$10306 $1\logical_op__imm_data__data$next[63:0]$10305 $1\logical_op__fn_unit$next[13:0]$10304 $1\logical_op__insn_type$next[6:0]$10309 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } case - assign $1\logical_op__data_len$next[3:0]$10258 \logical_op__data_len - assign $1\logical_op__fn_unit$next[12:0]$10259 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$10260 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$10261 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$10262 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$10263 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$10264 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$10265 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$10266 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$10267 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$10268 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$10269 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$10270 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$10271 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$10272 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$10273 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$10274 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$10275 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$10303 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$10304 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10305 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10306 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10307 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10308 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10309 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10310 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10311 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10312 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10313 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10314 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10315 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10316 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10317 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10318 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10319 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10320 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -353695,48 +356438,48 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$10276 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$10277 1'0 - assign $2\logical_op__rc__rc$next[0:0]$10281 1'0 - assign $2\logical_op__rc__ok$next[0:0]$10280 1'0 - assign $2\logical_op__oe__oe$next[0:0]$10278 1'0 - assign $2\logical_op__oe__ok$next[0:0]$10279 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$10321 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10322 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10326 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10325 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10323 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10324 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$10276 $1\logical_op__imm_data__data$next[63:0]$10260 - assign $2\logical_op__imm_data__ok$next[0:0]$10277 $1\logical_op__imm_data__ok$next[0:0]$10261 - assign $2\logical_op__oe__oe$next[0:0]$10278 $1\logical_op__oe__oe$next[0:0]$10269 - assign $2\logical_op__oe__ok$next[0:0]$10279 $1\logical_op__oe__ok$next[0:0]$10270 - assign $2\logical_op__rc__ok$next[0:0]$10280 $1\logical_op__rc__ok$next[0:0]$10272 - assign $2\logical_op__rc__rc$next[0:0]$10281 $1\logical_op__rc__rc$next[0:0]$10273 + assign $2\logical_op__imm_data__data$next[63:0]$10321 $1\logical_op__imm_data__data$next[63:0]$10305 + assign $2\logical_op__imm_data__ok$next[0:0]$10322 $1\logical_op__imm_data__ok$next[0:0]$10306 + assign $2\logical_op__oe__oe$next[0:0]$10323 $1\logical_op__oe__oe$next[0:0]$10314 + assign $2\logical_op__oe__ok$next[0:0]$10324 $1\logical_op__oe__ok$next[0:0]$10315 + assign $2\logical_op__rc__ok$next[0:0]$10325 $1\logical_op__rc__ok$next[0:0]$10317 + assign $2\logical_op__rc__rc$next[0:0]$10326 $1\logical_op__rc__rc$next[0:0]$10318 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10240 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$10241 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10242 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10243 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10244 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10245 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10246 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10247 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10248 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10249 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10250 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10251 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10252 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10253 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10254 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10255 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10256 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10257 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10285 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10286 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10287 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10288 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10289 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10290 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10291 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10292 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10293 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10294 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10295 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10296 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10297 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10298 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10299 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10300 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10301 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10302 end - attribute \src "libresoc.v:171589.3-171601.6" - process $proc$libresoc.v:171589$10282 + attribute \src "libresoc.v:173637.3-173649.6" + process $proc$libresoc.v:173637$10327 assign { } { } assign { } { } - assign $0\ra$next[63:0]$10283 $1\ra$next[63:0]$10284 - attribute \src "libresoc.v:171590.5-171590.29" + assign $0\ra$next[63:0]$10328 $1\ra$next[63:0]$10329 + attribute \src "libresoc.v:173638.5-173638.29" switch \initial - attribute \src "libresoc.v:171590.9-171590.17" + attribute \src "libresoc.v:173638.9-173638.17" case 1'1 case end @@ -353745,25 +356488,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$10284 \ra$87 + assign $1\ra$next[63:0]$10329 \ra$87 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$10284 \ra$87 + assign $1\ra$next[63:0]$10329 \ra$87 case - assign $1\ra$next[63:0]$10284 \ra + assign $1\ra$next[63:0]$10329 \ra end sync always - update \ra$next $0\ra$next[63:0]$10283 + update \ra$next $0\ra$next[63:0]$10328 end - attribute \src "libresoc.v:171602.3-171614.6" - process $proc$libresoc.v:171602$10285 + attribute \src "libresoc.v:173650.3-173662.6" + process $proc$libresoc.v:173650$10330 assign { } { } assign { } { } - assign $0\rb$next[63:0]$10286 $1\rb$next[63:0]$10287 - attribute \src "libresoc.v:171603.5-171603.29" + assign $0\rb$next[63:0]$10331 $1\rb$next[63:0]$10332 + attribute \src "libresoc.v:173651.5-173651.29" switch \initial - attribute \src "libresoc.v:171603.9-171603.17" + attribute \src "libresoc.v:173651.9-173651.17" case 1'1 case end @@ -353772,25 +356515,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$10287 \rb$89 + assign $1\rb$next[63:0]$10332 \rb$89 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$10287 \rb$89 + assign $1\rb$next[63:0]$10332 \rb$89 case - assign $1\rb$next[63:0]$10287 \rb + assign $1\rb$next[63:0]$10332 \rb end sync always - update \rb$next $0\rb$next[63:0]$10286 + update \rb$next $0\rb$next[63:0]$10331 end - attribute \src "libresoc.v:171615.3-171627.6" - process $proc$libresoc.v:171615$10288 + attribute \src "libresoc.v:173663.3-173675.6" + process $proc$libresoc.v:173663$10333 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$10289 $1\xer_so$next[0:0]$10290 - attribute \src "libresoc.v:171616.5-171616.29" + assign $0\xer_so$next[0:0]$10334 $1\xer_so$next[0:0]$10335 + attribute \src "libresoc.v:173664.5-173664.29" switch \initial - attribute \src "libresoc.v:171616.9-171616.17" + attribute \src "libresoc.v:173664.9-173664.17" case 1'1 case end @@ -353799,18 +356542,18 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$10290 \xer_so$91 + assign $1\xer_so$next[0:0]$10335 \xer_so$91 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$10290 \xer_so$91 + assign $1\xer_so$next[0:0]$10335 \xer_so$91 case - assign $1\xer_so$next[0:0]$10290 \xer_so + assign $1\xer_so$next[0:0]$10335 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$10289 + update \xer_so$next $0\xer_so$next[0:0]$10334 end - connect \$66 $and$libresoc.v:171243$10176_Y + connect \$66 $and$libresoc.v:173291$10221_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data @@ -353842,191 +356585,319 @@ module \pipe_start connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:171662.1-172304.10" +attribute \src "libresoc.v:173710.1-173754.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.pll" +attribute \generator "nMigen" +module \pll + attribute \src "libresoc.v:173711.7-173711.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173743.3-173752.6" + wire $0\pll_18_o[0:0] + attribute \src "libresoc.v:173733.3-173742.6" + wire $0\pll_lck_o[0:0] + attribute \src "libresoc.v:173743.3-173752.6" + wire $1\pll_18_o[0:0] + attribute \src "libresoc.v:173733.3-173742.6" + wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:173730.17-173730.105" + wire $eq$libresoc.v:173730$10368_Y + attribute \src "libresoc.v:173731.17-173731.105" + wire $eq$libresoc.v:173731$10369_Y + attribute \src "libresoc.v:173732.17-173732.98" + wire $not$libresoc.v:173732$10370_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire output 5 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 3 \clk_sel_i + attribute \src "libresoc.v:173711.7-173711.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 2 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 4 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:173730$10368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:173730$10368_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:173731$10369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:173731$10369_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + cell $not $not$libresoc.v:173732$10370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk_24_i + connect \Y $not$libresoc.v:173732$10370_Y + end + attribute \src "libresoc.v:173711.7-173711.20" + process $proc$libresoc.v:173711$10373 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173733.3-173742.6" + process $proc$libresoc.v:173733$10371 + assign { } { } + assign { } { } + assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] + attribute \src "libresoc.v:173734.5-173734.29" + switch \initial + attribute \src "libresoc.v:173734.9-173734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_lck_o[0:0] \clk_24_i + case + assign $1\pll_lck_o[0:0] 1'0 + end + sync always + update \pll_lck_o $0\pll_lck_o[0:0] + end + attribute \src "libresoc.v:173743.3-173752.6" + process $proc$libresoc.v:173743$10372 + assign { } { } + assign { } { } + assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] + attribute \src "libresoc.v:173744.5-173744.29" + switch \initial + attribute \src "libresoc.v:173744.9-173744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_18_o[0:0] \$5 + case + assign $1\pll_18_o[0:0] 1'0 + end + sync always + update \pll_18_o $0\pll_18_o[0:0] + end + connect \$1 $eq$libresoc.v:173730$10368_Y + connect \$3 $eq$libresoc.v:173731$10369_Y + connect \$5 $not$libresoc.v:173732$10370_Y + connect \clk_pll_o \clk_24_i +end +attribute \src "libresoc.v:173758.1-174400.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount - attribute \src "libresoc.v:171663.7-171663.20" + attribute \src "libresoc.v:173759.7-173759.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172151.3-172177.6" + attribute \src "libresoc.v:174247.3-174273.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:172151.3-172177.6" + attribute \src "libresoc.v:174247.3-174273.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:172075.19-172075.132" - wire width 4 $add$libresoc.v:172075$10323_Y - attribute \src "libresoc.v:172076.19-172076.132" - wire width 4 $add$libresoc.v:172076$10324_Y - attribute \src "libresoc.v:172077.19-172077.132" - wire width 4 $add$libresoc.v:172077$10325_Y - attribute \src "libresoc.v:172078.19-172078.132" - wire width 4 $add$libresoc.v:172078$10326_Y - attribute \src "libresoc.v:172079.19-172079.134" - wire width 4 $add$libresoc.v:172079$10327_Y - attribute \src "libresoc.v:172080.19-172080.134" - wire width 4 $add$libresoc.v:172080$10328_Y - attribute \src "libresoc.v:172081.18-172081.125" - wire width 3 $add$libresoc.v:172081$10329_Y - attribute \src "libresoc.v:172082.19-172082.134" - wire width 4 $add$libresoc.v:172082$10330_Y - attribute \src "libresoc.v:172083.19-172083.134" - wire width 4 $add$libresoc.v:172083$10331_Y - attribute \src "libresoc.v:172084.19-172084.134" - wire width 4 $add$libresoc.v:172084$10332_Y - attribute \src "libresoc.v:172085.19-172085.134" - wire width 4 $add$libresoc.v:172085$10333_Y - attribute \src "libresoc.v:172086.19-172086.134" - wire width 4 $add$libresoc.v:172086$10334_Y - attribute \src "libresoc.v:172087.19-172087.134" - wire width 4 $add$libresoc.v:172087$10335_Y - attribute \src "libresoc.v:172088.19-172088.134" - wire width 4 $add$libresoc.v:172088$10336_Y - attribute \src "libresoc.v:172089.19-172089.134" - wire width 4 $add$libresoc.v:172089$10337_Y - attribute \src "libresoc.v:172090.19-172090.134" - wire width 4 $add$libresoc.v:172090$10338_Y - attribute \src "libresoc.v:172091.19-172091.132" - wire width 5 $add$libresoc.v:172091$10339_Y - attribute \src "libresoc.v:172092.18-172092.125" - wire width 3 $add$libresoc.v:172092$10340_Y - attribute \src "libresoc.v:172093.19-172093.132" - wire width 5 $add$libresoc.v:172093$10341_Y - attribute \src "libresoc.v:172094.19-172094.132" - wire width 5 $add$libresoc.v:172094$10342_Y - attribute \src "libresoc.v:172095.19-172095.132" - wire width 5 $add$libresoc.v:172095$10343_Y - attribute \src "libresoc.v:172096.19-172096.132" - wire width 5 $add$libresoc.v:172096$10344_Y - attribute \src "libresoc.v:172097.19-172097.134" - wire width 5 $add$libresoc.v:172097$10345_Y - attribute \src "libresoc.v:172098.19-172098.134" - wire width 5 $add$libresoc.v:172098$10346_Y - attribute \src "libresoc.v:172099.19-172099.134" - wire width 5 $add$libresoc.v:172099$10347_Y - attribute \src "libresoc.v:172100.19-172100.132" - wire width 6 $add$libresoc.v:172100$10348_Y - attribute \src "libresoc.v:172101.19-172101.132" - wire width 6 $add$libresoc.v:172101$10349_Y - attribute \src "libresoc.v:172102.19-172102.132" - wire width 6 $add$libresoc.v:172102$10350_Y - attribute \src "libresoc.v:172103.18-172103.127" - wire width 3 $add$libresoc.v:172103$10351_Y - attribute \src "libresoc.v:172104.19-172104.132" - wire width 6 $add$libresoc.v:172104$10352_Y - attribute \src "libresoc.v:172105.19-172105.132" - wire width 7 $add$libresoc.v:172105$10353_Y - attribute \src "libresoc.v:172106.19-172106.132" - wire width 7 $add$libresoc.v:172106$10354_Y - attribute \src "libresoc.v:172107.19-172107.132" - wire width 8 $add$libresoc.v:172107$10355_Y - attribute \src "libresoc.v:172118.18-172118.127" - wire width 3 $add$libresoc.v:172118$10374_Y - attribute \src "libresoc.v:172122.18-172122.127" - wire width 3 $add$libresoc.v:172122$10381_Y - attribute \src "libresoc.v:172123.18-172123.127" - wire width 3 $add$libresoc.v:172123$10382_Y - attribute \src "libresoc.v:172124.17-172124.124" - wire width 3 $add$libresoc.v:172124$10383_Y - attribute \src "libresoc.v:172125.18-172125.127" - wire width 3 $add$libresoc.v:172125$10384_Y - attribute \src "libresoc.v:172126.18-172126.127" - wire width 3 $add$libresoc.v:172126$10385_Y - attribute \src "libresoc.v:172127.18-172127.127" - wire width 3 $add$libresoc.v:172127$10386_Y - attribute \src "libresoc.v:172128.18-172128.127" - wire width 3 $add$libresoc.v:172128$10387_Y - attribute \src "libresoc.v:172129.18-172129.127" - wire width 3 $add$libresoc.v:172129$10388_Y - attribute \src "libresoc.v:172130.18-172130.127" - wire width 3 $add$libresoc.v:172130$10389_Y - attribute \src "libresoc.v:172131.18-172131.127" - wire width 3 $add$libresoc.v:172131$10390_Y - attribute \src "libresoc.v:172132.18-172132.127" - wire width 3 $add$libresoc.v:172132$10391_Y - attribute \src "libresoc.v:172133.18-172133.127" - wire width 3 $add$libresoc.v:172133$10392_Y - attribute \src "libresoc.v:172134.18-172134.127" - wire width 3 $add$libresoc.v:172134$10393_Y - attribute \src "libresoc.v:172135.17-172135.124" - wire width 3 $add$libresoc.v:172135$10394_Y - attribute \src "libresoc.v:172136.18-172136.127" - wire width 3 $add$libresoc.v:172136$10395_Y - attribute \src "libresoc.v:172137.18-172137.127" - wire width 3 $add$libresoc.v:172137$10396_Y - attribute \src "libresoc.v:172138.18-172138.127" - wire width 3 $add$libresoc.v:172138$10397_Y - attribute \src "libresoc.v:172139.18-172139.127" - wire width 3 $add$libresoc.v:172139$10398_Y - attribute \src "libresoc.v:172140.18-172140.127" - wire width 3 $add$libresoc.v:172140$10399_Y - attribute \src "libresoc.v:172141.18-172141.127" - wire width 3 $add$libresoc.v:172141$10400_Y - attribute \src "libresoc.v:172142.18-172142.127" - wire width 3 $add$libresoc.v:172142$10401_Y - attribute \src "libresoc.v:172143.18-172143.127" - wire width 3 $add$libresoc.v:172143$10402_Y - attribute \src "libresoc.v:172144.18-172144.127" - wire width 3 $add$libresoc.v:172144$10403_Y - attribute \src "libresoc.v:172145.18-172145.127" - wire width 3 $add$libresoc.v:172145$10404_Y - attribute \src "libresoc.v:172146.17-172146.124" - wire width 3 $add$libresoc.v:172146$10405_Y - attribute \src "libresoc.v:172147.18-172147.127" - wire width 3 $add$libresoc.v:172147$10406_Y - attribute \src "libresoc.v:172148.18-172148.127" - wire width 3 $add$libresoc.v:172148$10407_Y - attribute \src "libresoc.v:172149.18-172149.127" - wire width 3 $add$libresoc.v:172149$10408_Y - attribute \src "libresoc.v:172150.18-172150.131" - wire width 4 $add$libresoc.v:172150$10409_Y - attribute \src "libresoc.v:172108.19-172108.111" - wire $eq$libresoc.v:172108$10356_Y - attribute \src "libresoc.v:172109.19-172109.111" - wire $eq$libresoc.v:172109$10357_Y - attribute \src "libresoc.v:172110.19-172110.104" - wire width 8 $extend$libresoc.v:172110$10358_Y - attribute \src "libresoc.v:172111.19-172111.104" - wire width 8 $extend$libresoc.v:172111$10360_Y - attribute \src "libresoc.v:172112.19-172112.104" - wire width 8 $extend$libresoc.v:172112$10362_Y - attribute \src "libresoc.v:172113.19-172113.104" - wire width 8 $extend$libresoc.v:172113$10364_Y - attribute \src "libresoc.v:172114.19-172114.104" - wire width 8 $extend$libresoc.v:172114$10366_Y - attribute \src "libresoc.v:172115.19-172115.104" - wire width 8 $extend$libresoc.v:172115$10368_Y - attribute \src "libresoc.v:172116.19-172116.104" - wire width 8 $extend$libresoc.v:172116$10370_Y - attribute \src "libresoc.v:172117.19-172117.104" - wire width 8 $extend$libresoc.v:172117$10372_Y - attribute \src "libresoc.v:172119.19-172119.104" - wire width 32 $extend$libresoc.v:172119$10375_Y - attribute \src "libresoc.v:172120.19-172120.104" - wire width 32 $extend$libresoc.v:172120$10377_Y - attribute \src "libresoc.v:172121.19-172121.104" - wire width 64 $extend$libresoc.v:172121$10379_Y - attribute \src "libresoc.v:172110.19-172110.104" - wire width 8 $pos$libresoc.v:172110$10359_Y - attribute \src "libresoc.v:172111.19-172111.104" - wire width 8 $pos$libresoc.v:172111$10361_Y - attribute \src "libresoc.v:172112.19-172112.104" - wire width 8 $pos$libresoc.v:172112$10363_Y - attribute \src "libresoc.v:172113.19-172113.104" - wire width 8 $pos$libresoc.v:172113$10365_Y - attribute \src "libresoc.v:172114.19-172114.104" - wire width 8 $pos$libresoc.v:172114$10367_Y - attribute \src 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wire $eq$libresoc.v:174205$10408_Y + attribute \src "libresoc.v:174206.19-174206.104" + wire width 8 $extend$libresoc.v:174206$10409_Y + attribute \src "libresoc.v:174207.19-174207.104" + wire width 8 $extend$libresoc.v:174207$10411_Y + attribute \src "libresoc.v:174208.19-174208.104" + wire width 8 $extend$libresoc.v:174208$10413_Y + attribute \src "libresoc.v:174209.19-174209.104" + wire width 8 $extend$libresoc.v:174209$10415_Y + attribute \src "libresoc.v:174210.19-174210.104" + wire width 8 $extend$libresoc.v:174210$10417_Y + attribute \src "libresoc.v:174211.19-174211.104" + wire width 8 $extend$libresoc.v:174211$10419_Y + attribute \src "libresoc.v:174212.19-174212.104" + wire width 8 $extend$libresoc.v:174212$10421_Y + attribute \src "libresoc.v:174213.19-174213.104" + wire width 8 $extend$libresoc.v:174213$10423_Y + attribute \src "libresoc.v:174215.19-174215.104" + wire width 32 $extend$libresoc.v:174215$10426_Y + attribute \src "libresoc.v:174216.19-174216.104" + wire width 32 $extend$libresoc.v:174216$10428_Y + attribute \src "libresoc.v:174217.19-174217.104" + wire width 64 $extend$libresoc.v:174217$10430_Y + attribute \src "libresoc.v:174206.19-174206.104" + wire width 8 $pos$libresoc.v:174206$10410_Y + attribute \src "libresoc.v:174207.19-174207.104" + wire width 8 $pos$libresoc.v:174207$10412_Y + attribute \src "libresoc.v:174208.19-174208.104" + wire width 8 $pos$libresoc.v:174208$10414_Y + attribute \src "libresoc.v:174209.19-174209.104" + wire width 8 $pos$libresoc.v:174209$10416_Y + attribute \src "libresoc.v:174210.19-174210.104" + wire width 8 $pos$libresoc.v:174210$10418_Y + attribute \src "libresoc.v:174211.19-174211.104" + wire width 8 $pos$libresoc.v:174211$10420_Y + attribute \src "libresoc.v:174212.19-174212.104" + wire width 8 $pos$libresoc.v:174212$10422_Y + attribute \src "libresoc.v:174213.19-174213.104" + wire width 8 $pos$libresoc.v:174213$10424_Y + attribute \src "libresoc.v:174215.19-174215.104" + wire width 32 $pos$libresoc.v:174215$10427_Y + attribute \src "libresoc.v:174216.19-174216.104" + wire width 32 $pos$libresoc.v:174216$10429_Y + attribute \src "libresoc.v:174217.19-174217.104" + wire width 64 $pos$libresoc.v:174217$10431_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" @@ -354309,7 +357180,7 @@ module \popcount wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len - attribute \src "libresoc.v:171663.7-171663.15" + attribute \src "libresoc.v:173759.7-173759.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o @@ -354440,7 +357311,7 @@ module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172075$10323 + cell $add $add$libresoc.v:174171$10374 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354448,10 +357319,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:172075$10323_Y + connect \Y $add$libresoc.v:174171$10374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172076$10324 + cell $add $add$libresoc.v:174172$10375 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354459,10 +357330,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:172076$10324_Y + connect \Y $add$libresoc.v:174172$10375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172077$10325 + cell $add $add$libresoc.v:174173$10376 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354470,10 +357341,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:172077$10325_Y + connect \Y $add$libresoc.v:174173$10376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172078$10326 + cell $add $add$libresoc.v:174174$10377 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354481,10 +357352,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:172078$10326_Y + connect \Y $add$libresoc.v:174174$10377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172079$10327 + cell $add $add$libresoc.v:174175$10378 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354492,10 +357363,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:172079$10327_Y + connect \Y $add$libresoc.v:174175$10378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172080$10328 + cell $add $add$libresoc.v:174176$10379 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354503,10 +357374,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:172080$10328_Y + connect \Y $add$libresoc.v:174176$10379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172081$10329 + cell $add $add$libresoc.v:174177$10380 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354514,10 +357385,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:172081$10329_Y + connect \Y $add$libresoc.v:174177$10380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172082$10330 + cell $add $add$libresoc.v:174178$10381 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354525,10 +357396,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:172082$10330_Y + connect \Y $add$libresoc.v:174178$10381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172083$10331 + cell $add $add$libresoc.v:174179$10382 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354536,10 +357407,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:172083$10331_Y + connect \Y $add$libresoc.v:174179$10382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172084$10332 + cell $add $add$libresoc.v:174180$10383 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354547,10 +357418,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:172084$10332_Y + connect \Y $add$libresoc.v:174180$10383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172085$10333 + cell $add $add$libresoc.v:174181$10384 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354558,10 +357429,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:172085$10333_Y + connect \Y $add$libresoc.v:174181$10384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172086$10334 + cell $add $add$libresoc.v:174182$10385 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354569,10 +357440,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:172086$10334_Y + connect \Y $add$libresoc.v:174182$10385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172087$10335 + cell $add $add$libresoc.v:174183$10386 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354580,10 +357451,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:172087$10335_Y + connect \Y $add$libresoc.v:174183$10386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172088$10336 + cell $add $add$libresoc.v:174184$10387 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354591,10 +357462,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:172088$10336_Y + connect \Y $add$libresoc.v:174184$10387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172089$10337 + cell $add $add$libresoc.v:174185$10388 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354602,10 +357473,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:172089$10337_Y + connect \Y $add$libresoc.v:174185$10388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172090$10338 + cell $add $add$libresoc.v:174186$10389 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -354613,10 +357484,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:172090$10338_Y + connect \Y $add$libresoc.v:174186$10389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172091$10339 + cell $add $add$libresoc.v:174187$10390 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354624,10 +357495,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:172091$10339_Y + connect \Y $add$libresoc.v:174187$10390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172092$10340 + cell $add $add$libresoc.v:174188$10391 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354635,10 +357506,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:172092$10340_Y + connect \Y $add$libresoc.v:174188$10391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172093$10341 + cell $add $add$libresoc.v:174189$10392 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354646,10 +357517,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:172093$10341_Y + connect \Y $add$libresoc.v:174189$10392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172094$10342 + cell $add $add$libresoc.v:174190$10393 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354657,10 +357528,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:172094$10342_Y + connect \Y $add$libresoc.v:174190$10393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172095$10343 + cell $add $add$libresoc.v:174191$10394 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354668,10 +357539,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:172095$10343_Y + connect \Y $add$libresoc.v:174191$10394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172096$10344 + cell $add $add$libresoc.v:174192$10395 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354679,10 +357550,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:172096$10344_Y + connect \Y $add$libresoc.v:174192$10395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172097$10345 + cell $add $add$libresoc.v:174193$10396 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354690,10 +357561,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:172097$10345_Y + connect \Y $add$libresoc.v:174193$10396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172098$10346 + cell $add $add$libresoc.v:174194$10397 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354701,10 +357572,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:172098$10346_Y + connect \Y $add$libresoc.v:174194$10397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172099$10347 + cell $add $add$libresoc.v:174195$10398 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -354712,10 +357583,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:172099$10347_Y + connect \Y $add$libresoc.v:174195$10398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172100$10348 + cell $add $add$libresoc.v:174196$10399 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -354723,10 +357594,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:172100$10348_Y + connect \Y $add$libresoc.v:174196$10399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172101$10349 + cell $add $add$libresoc.v:174197$10400 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -354734,10 +357605,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:172101$10349_Y + connect \Y $add$libresoc.v:174197$10400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172102$10350 + cell $add $add$libresoc.v:174198$10401 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -354745,10 +357616,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:172102$10350_Y + connect \Y $add$libresoc.v:174198$10401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172103$10351 + cell $add $add$libresoc.v:174199$10402 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354756,10 +357627,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:172103$10351_Y + connect \Y $add$libresoc.v:174199$10402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172104$10352 + cell $add $add$libresoc.v:174200$10403 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -354767,10 +357638,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:172104$10352_Y + connect \Y $add$libresoc.v:174200$10403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172105$10353 + cell $add $add$libresoc.v:174201$10404 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -354778,10 +357649,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:172105$10353_Y + connect \Y $add$libresoc.v:174201$10404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172106$10354 + cell $add $add$libresoc.v:174202$10405 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -354789,10 +357660,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:172106$10354_Y + connect \Y $add$libresoc.v:174202$10405_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172107$10355 + cell $add $add$libresoc.v:174203$10406 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -354800,10 +357671,10 @@ module \popcount parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:172107$10355_Y + connect \Y $add$libresoc.v:174203$10406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172118$10374 + cell $add $add$libresoc.v:174214$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354811,10 +357682,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:172118$10374_Y + connect \Y $add$libresoc.v:174214$10425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172122$10381 + cell $add $add$libresoc.v:174218$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354822,10 +357693,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:172122$10381_Y + connect \Y $add$libresoc.v:174218$10432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172123$10382 + cell $add $add$libresoc.v:174219$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354833,10 +357704,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:172123$10382_Y + connect \Y $add$libresoc.v:174219$10433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172124$10383 + cell $add $add$libresoc.v:174220$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354844,10 +357715,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:172124$10383_Y + connect \Y $add$libresoc.v:174220$10434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172125$10384 + cell $add $add$libresoc.v:174221$10435 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354855,10 +357726,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:172125$10384_Y + connect \Y $add$libresoc.v:174221$10435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172126$10385 + cell $add $add$libresoc.v:174222$10436 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354866,10 +357737,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:172126$10385_Y + connect \Y $add$libresoc.v:174222$10436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172127$10386 + cell $add $add$libresoc.v:174223$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354877,10 +357748,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:172127$10386_Y + connect \Y $add$libresoc.v:174223$10437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172128$10387 + cell $add $add$libresoc.v:174224$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354888,10 +357759,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:172128$10387_Y + connect \Y $add$libresoc.v:174224$10438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172129$10388 + cell $add $add$libresoc.v:174225$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354899,10 +357770,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:172129$10388_Y + connect \Y $add$libresoc.v:174225$10439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172130$10389 + cell $add $add$libresoc.v:174226$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354910,10 +357781,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:172130$10389_Y + connect \Y $add$libresoc.v:174226$10440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172131$10390 + cell $add $add$libresoc.v:174227$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354921,10 +357792,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:172131$10390_Y + connect \Y $add$libresoc.v:174227$10441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172132$10391 + cell $add $add$libresoc.v:174228$10442 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354932,10 +357803,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:172132$10391_Y + connect \Y $add$libresoc.v:174228$10442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172133$10392 + cell $add $add$libresoc.v:174229$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354943,10 +357814,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:172133$10392_Y + connect \Y $add$libresoc.v:174229$10443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172134$10393 + cell $add $add$libresoc.v:174230$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354954,10 +357825,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:172134$10393_Y + connect \Y $add$libresoc.v:174230$10444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172135$10394 + cell $add $add$libresoc.v:174231$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354965,10 +357836,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:172135$10394_Y + connect \Y $add$libresoc.v:174231$10445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172136$10395 + cell $add $add$libresoc.v:174232$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354976,10 +357847,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:172136$10395_Y + connect \Y $add$libresoc.v:174232$10446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172137$10396 + cell $add $add$libresoc.v:174233$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354987,10 +357858,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:172137$10396_Y + connect \Y $add$libresoc.v:174233$10447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172138$10397 + cell $add $add$libresoc.v:174234$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -354998,10 +357869,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:172138$10397_Y + connect \Y $add$libresoc.v:174234$10448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172139$10398 + cell $add $add$libresoc.v:174235$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355009,10 +357880,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:172139$10398_Y + connect \Y $add$libresoc.v:174235$10449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172140$10399 + cell $add $add$libresoc.v:174236$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355020,10 +357891,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:172140$10399_Y + connect \Y $add$libresoc.v:174236$10450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172141$10400 + cell $add $add$libresoc.v:174237$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355031,10 +357902,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:172141$10400_Y + connect \Y $add$libresoc.v:174237$10451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172142$10401 + cell $add $add$libresoc.v:174238$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355042,10 +357913,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:172142$10401_Y + connect \Y $add$libresoc.v:174238$10452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172143$10402 + cell $add $add$libresoc.v:174239$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355053,10 +357924,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:172143$10402_Y + connect \Y $add$libresoc.v:174239$10453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172144$10403 + cell $add $add$libresoc.v:174240$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355064,10 +357935,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:172144$10403_Y + connect \Y $add$libresoc.v:174240$10454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172145$10404 + cell $add $add$libresoc.v:174241$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355075,10 +357946,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:172145$10404_Y + connect \Y $add$libresoc.v:174241$10455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172146$10405 + cell $add $add$libresoc.v:174242$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355086,10 +357957,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:172146$10405_Y + connect \Y $add$libresoc.v:174242$10456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172147$10406 + cell $add $add$libresoc.v:174243$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355097,10 +357968,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:172147$10406_Y + connect \Y $add$libresoc.v:174243$10457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172148$10407 + cell $add $add$libresoc.v:174244$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355108,10 +357979,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:172148$10407_Y + connect \Y $add$libresoc.v:174244$10458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172149$10408 + cell $add $add$libresoc.v:174245$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -355119,10 +357990,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:172149$10408_Y + connect \Y $add$libresoc.v:174245$10459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:172150$10409 + cell $add $add$libresoc.v:174246$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -355130,10 +358001,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:172150$10409_Y + connect \Y $add$libresoc.v:174246$10460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:172108$10356 + cell $eq $eq$libresoc.v:174204$10407 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -355141,10 +358012,10 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 - connect \Y $eq$libresoc.v:172108$10356_Y + connect \Y $eq$libresoc.v:174204$10407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:172109$10357 + cell $eq $eq$libresoc.v:174205$10408 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -355152,199 +358023,199 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 - connect \Y $eq$libresoc.v:172109$10357_Y + connect \Y $eq$libresoc.v:174205$10408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172110$10358 + cell $pos $extend$libresoc.v:174206$10409 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 - connect \Y $extend$libresoc.v:172110$10358_Y + connect \Y $extend$libresoc.v:174206$10409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172111$10360 + cell $pos $extend$libresoc.v:174207$10411 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 - connect \Y $extend$libresoc.v:172111$10360_Y + connect \Y $extend$libresoc.v:174207$10411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172112$10362 + cell $pos $extend$libresoc.v:174208$10413 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 - connect \Y $extend$libresoc.v:172112$10362_Y + connect \Y $extend$libresoc.v:174208$10413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172113$10364 + cell $pos $extend$libresoc.v:174209$10415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 - connect \Y $extend$libresoc.v:172113$10364_Y + connect \Y $extend$libresoc.v:174209$10415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172114$10366 + cell $pos $extend$libresoc.v:174210$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 - connect \Y $extend$libresoc.v:172114$10366_Y + connect \Y $extend$libresoc.v:174210$10417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172115$10368 + cell $pos $extend$libresoc.v:174211$10419 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 - connect \Y $extend$libresoc.v:172115$10368_Y + connect \Y $extend$libresoc.v:174211$10419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172116$10370 + cell $pos $extend$libresoc.v:174212$10421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 - connect \Y $extend$libresoc.v:172116$10370_Y + connect \Y $extend$libresoc.v:174212$10421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172117$10372 + cell $pos $extend$libresoc.v:174213$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 - connect \Y $extend$libresoc.v:172117$10372_Y + connect \Y $extend$libresoc.v:174213$10423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172119$10375 + cell $pos $extend$libresoc.v:174215$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 - connect \Y $extend$libresoc.v:172119$10375_Y + connect \Y $extend$libresoc.v:174215$10426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172120$10377 + cell $pos $extend$libresoc.v:174216$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 - connect \Y $extend$libresoc.v:172120$10377_Y + connect \Y $extend$libresoc.v:174216$10428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:172121$10379 + cell $pos $extend$libresoc.v:174217$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 - connect \Y $extend$libresoc.v:172121$10379_Y + connect \Y $extend$libresoc.v:174217$10430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172110$10359 + cell $pos $pos$libresoc.v:174206$10410 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:172110$10358_Y - connect \Y $pos$libresoc.v:172110$10359_Y + connect \A $extend$libresoc.v:174206$10409_Y + connect \Y $pos$libresoc.v:174206$10410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172111$10361 + cell $pos $pos$libresoc.v:174207$10412 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:172111$10360_Y - connect \Y $pos$libresoc.v:172111$10361_Y + connect \A $extend$libresoc.v:174207$10411_Y + connect \Y $pos$libresoc.v:174207$10412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172112$10363 + cell $pos $pos$libresoc.v:174208$10414 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:172112$10362_Y - connect \Y $pos$libresoc.v:172112$10363_Y + connect \A $extend$libresoc.v:174208$10413_Y + connect \Y $pos$libresoc.v:174208$10414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172113$10365 + cell $pos $pos$libresoc.v:174209$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:172113$10364_Y - connect \Y $pos$libresoc.v:172113$10365_Y + connect \A $extend$libresoc.v:174209$10415_Y + connect \Y $pos$libresoc.v:174209$10416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172114$10367 + cell $pos $pos$libresoc.v:174210$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:172114$10366_Y - connect \Y $pos$libresoc.v:172114$10367_Y + connect \A $extend$libresoc.v:174210$10417_Y + connect \Y $pos$libresoc.v:174210$10418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172115$10369 + cell $pos $pos$libresoc.v:174211$10420 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:172115$10368_Y - connect \Y $pos$libresoc.v:172115$10369_Y + connect \A $extend$libresoc.v:174211$10419_Y + connect \Y $pos$libresoc.v:174211$10420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172116$10371 + cell $pos $pos$libresoc.v:174212$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:172116$10370_Y - connect \Y $pos$libresoc.v:172116$10371_Y + connect \A $extend$libresoc.v:174212$10421_Y + connect \Y $pos$libresoc.v:174212$10422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172117$10373 + cell $pos $pos$libresoc.v:174213$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:172117$10372_Y - connect \Y $pos$libresoc.v:172117$10373_Y + connect \A $extend$libresoc.v:174213$10423_Y + connect \Y $pos$libresoc.v:174213$10424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172119$10376 + cell $pos $pos$libresoc.v:174215$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:172119$10375_Y - connect \Y $pos$libresoc.v:172119$10376_Y + connect \A $extend$libresoc.v:174215$10426_Y + connect \Y $pos$libresoc.v:174215$10427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172120$10378 + cell $pos $pos$libresoc.v:174216$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:172120$10377_Y - connect \Y $pos$libresoc.v:172120$10378_Y + connect \A $extend$libresoc.v:174216$10428_Y + connect \Y $pos$libresoc.v:174216$10429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:172121$10380 + cell $pos $pos$libresoc.v:174217$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:172121$10379_Y - connect \Y $pos$libresoc.v:172121$10380_Y + connect \A $extend$libresoc.v:174217$10430_Y + connect \Y $pos$libresoc.v:174217$10431_Y end - attribute \src "libresoc.v:171663.7-171663.20" - process $proc$libresoc.v:171663$10411 + attribute \src "libresoc.v:173759.7-173759.20" + process $proc$libresoc.v:173759$10462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172151.3-172177.6" - process $proc$libresoc.v:172151$10410 + attribute \src "libresoc.v:174247.3-174273.6" + process $proc$libresoc.v:174247$10461 assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:172152.5-172152.29" + attribute \src "libresoc.v:174248.5-174248.29" switch \initial - attribute \src "libresoc.v:172152.9-172152.17" + attribute \src "libresoc.v:174248.9-174248.17" case 1'1 case end @@ -355374,82 +358245,82 @@ module \popcount sync always update \o $0\o[63:0] end - connect \$101 $add$libresoc.v:172075$10323_Y - connect \$104 $add$libresoc.v:172076$10324_Y - connect \$107 $add$libresoc.v:172077$10325_Y - connect \$110 $add$libresoc.v:172078$10326_Y - connect \$113 $add$libresoc.v:172079$10327_Y - connect \$116 $add$libresoc.v:172080$10328_Y - connect \$11 $add$libresoc.v:172081$10329_Y - connect \$119 $add$libresoc.v:172082$10330_Y - connect \$122 $add$libresoc.v:172083$10331_Y - connect \$125 $add$libresoc.v:172084$10332_Y - connect \$128 $add$libresoc.v:172085$10333_Y - connect \$131 $add$libresoc.v:172086$10334_Y - connect \$134 $add$libresoc.v:172087$10335_Y - connect \$137 $add$libresoc.v:172088$10336_Y - connect \$140 $add$libresoc.v:172089$10337_Y - connect \$143 $add$libresoc.v:172090$10338_Y - connect \$146 $add$libresoc.v:172091$10339_Y - connect \$14 $add$libresoc.v:172092$10340_Y - connect \$149 $add$libresoc.v:172093$10341_Y - connect \$152 $add$libresoc.v:172094$10342_Y - connect \$155 $add$libresoc.v:172095$10343_Y - connect \$158 $add$libresoc.v:172096$10344_Y - connect \$161 $add$libresoc.v:172097$10345_Y - connect \$164 $add$libresoc.v:172098$10346_Y - connect \$167 $add$libresoc.v:172099$10347_Y - connect \$170 $add$libresoc.v:172100$10348_Y - connect \$173 $add$libresoc.v:172101$10349_Y - connect \$176 $add$libresoc.v:172102$10350_Y - connect \$17 $add$libresoc.v:172103$10351_Y - connect \$179 $add$libresoc.v:172104$10352_Y - connect \$182 $add$libresoc.v:172105$10353_Y - connect \$185 $add$libresoc.v:172106$10354_Y - connect \$188 $add$libresoc.v:172107$10355_Y - connect \$190 $eq$libresoc.v:172108$10356_Y - connect \$192 $eq$libresoc.v:172109$10357_Y - connect \$194 $pos$libresoc.v:172110$10359_Y - connect \$196 $pos$libresoc.v:172111$10361_Y - connect \$198 $pos$libresoc.v:172112$10363_Y - connect \$200 $pos$libresoc.v:172113$10365_Y - connect \$202 $pos$libresoc.v:172114$10367_Y - connect \$204 $pos$libresoc.v:172115$10369_Y - connect \$206 $pos$libresoc.v:172116$10371_Y - connect \$208 $pos$libresoc.v:172117$10373_Y - connect \$20 $add$libresoc.v:172118$10374_Y - connect \$210 $pos$libresoc.v:172119$10376_Y - connect \$212 $pos$libresoc.v:172120$10378_Y - connect \$214 $pos$libresoc.v:172121$10380_Y - connect \$23 $add$libresoc.v:172122$10381_Y - connect \$26 $add$libresoc.v:172123$10382_Y - connect \$2 $add$libresoc.v:172124$10383_Y - connect \$29 $add$libresoc.v:172125$10384_Y - connect \$32 $add$libresoc.v:172126$10385_Y - connect \$35 $add$libresoc.v:172127$10386_Y - connect \$38 $add$libresoc.v:172128$10387_Y - connect \$41 $add$libresoc.v:172129$10388_Y - connect \$44 $add$libresoc.v:172130$10389_Y - connect \$47 $add$libresoc.v:172131$10390_Y - connect \$50 $add$libresoc.v:172132$10391_Y - connect \$53 $add$libresoc.v:172133$10392_Y - connect \$56 $add$libresoc.v:172134$10393_Y - connect \$5 $add$libresoc.v:172135$10394_Y - connect \$59 $add$libresoc.v:172136$10395_Y - connect \$62 $add$libresoc.v:172137$10396_Y - connect \$65 $add$libresoc.v:172138$10397_Y - connect \$68 $add$libresoc.v:172139$10398_Y - connect \$71 $add$libresoc.v:172140$10399_Y - connect \$74 $add$libresoc.v:172141$10400_Y - connect \$77 $add$libresoc.v:172142$10401_Y - connect \$80 $add$libresoc.v:172143$10402_Y - connect \$83 $add$libresoc.v:172144$10403_Y - connect \$86 $add$libresoc.v:172145$10404_Y - connect \$8 $add$libresoc.v:172146$10405_Y - connect \$89 $add$libresoc.v:172147$10406_Y - connect \$92 $add$libresoc.v:172148$10407_Y - connect \$95 $add$libresoc.v:172149$10408_Y - connect \$98 $add$libresoc.v:172150$10409_Y + connect \$101 $add$libresoc.v:174171$10374_Y + connect \$104 $add$libresoc.v:174172$10375_Y + connect \$107 $add$libresoc.v:174173$10376_Y + connect \$110 $add$libresoc.v:174174$10377_Y + connect \$113 $add$libresoc.v:174175$10378_Y + connect \$116 $add$libresoc.v:174176$10379_Y + connect \$11 $add$libresoc.v:174177$10380_Y + connect \$119 $add$libresoc.v:174178$10381_Y + connect \$122 $add$libresoc.v:174179$10382_Y + connect \$125 $add$libresoc.v:174180$10383_Y + connect \$128 $add$libresoc.v:174181$10384_Y + connect \$131 $add$libresoc.v:174182$10385_Y + connect \$134 $add$libresoc.v:174183$10386_Y + connect \$137 $add$libresoc.v:174184$10387_Y + connect \$140 $add$libresoc.v:174185$10388_Y + connect \$143 $add$libresoc.v:174186$10389_Y + connect \$146 $add$libresoc.v:174187$10390_Y + connect \$14 $add$libresoc.v:174188$10391_Y + connect \$149 $add$libresoc.v:174189$10392_Y + connect \$152 $add$libresoc.v:174190$10393_Y + connect \$155 $add$libresoc.v:174191$10394_Y + connect \$158 $add$libresoc.v:174192$10395_Y + connect \$161 $add$libresoc.v:174193$10396_Y + connect \$164 $add$libresoc.v:174194$10397_Y + connect \$167 $add$libresoc.v:174195$10398_Y + connect \$170 $add$libresoc.v:174196$10399_Y + connect \$173 $add$libresoc.v:174197$10400_Y + connect \$176 $add$libresoc.v:174198$10401_Y + connect \$17 $add$libresoc.v:174199$10402_Y + connect \$179 $add$libresoc.v:174200$10403_Y + connect \$182 $add$libresoc.v:174201$10404_Y + connect \$185 $add$libresoc.v:174202$10405_Y + connect \$188 $add$libresoc.v:174203$10406_Y + connect \$190 $eq$libresoc.v:174204$10407_Y + connect \$192 $eq$libresoc.v:174205$10408_Y + connect \$194 $pos$libresoc.v:174206$10410_Y + connect \$196 $pos$libresoc.v:174207$10412_Y + connect \$198 $pos$libresoc.v:174208$10414_Y + connect \$200 $pos$libresoc.v:174209$10416_Y + connect \$202 $pos$libresoc.v:174210$10418_Y + connect \$204 $pos$libresoc.v:174211$10420_Y + connect \$206 $pos$libresoc.v:174212$10422_Y + connect \$208 $pos$libresoc.v:174213$10424_Y + connect \$20 $add$libresoc.v:174214$10425_Y + connect \$210 $pos$libresoc.v:174215$10427_Y + connect \$212 $pos$libresoc.v:174216$10429_Y + connect \$214 $pos$libresoc.v:174217$10431_Y + connect \$23 $add$libresoc.v:174218$10432_Y + connect \$26 $add$libresoc.v:174219$10433_Y + connect \$2 $add$libresoc.v:174220$10434_Y + connect \$29 $add$libresoc.v:174221$10435_Y + connect \$32 $add$libresoc.v:174222$10436_Y + connect \$35 $add$libresoc.v:174223$10437_Y + connect \$38 $add$libresoc.v:174224$10438_Y + connect \$41 $add$libresoc.v:174225$10439_Y + connect \$44 $add$libresoc.v:174226$10440_Y + connect \$47 $add$libresoc.v:174227$10441_Y + connect \$50 $add$libresoc.v:174228$10442_Y + connect \$53 $add$libresoc.v:174229$10443_Y + connect \$56 $add$libresoc.v:174230$10444_Y + connect \$5 $add$libresoc.v:174231$10445_Y + connect \$59 $add$libresoc.v:174232$10446_Y + connect \$62 $add$libresoc.v:174233$10447_Y + connect \$65 $add$libresoc.v:174234$10448_Y + connect \$68 $add$libresoc.v:174235$10449_Y + connect \$71 $add$libresoc.v:174236$10450_Y + connect \$74 $add$libresoc.v:174237$10451_Y + connect \$77 $add$libresoc.v:174238$10452_Y + connect \$80 $add$libresoc.v:174239$10453_Y + connect \$83 $add$libresoc.v:174240$10454_Y + connect \$86 $add$libresoc.v:174241$10455_Y + connect \$8 $add$libresoc.v:174242$10456_Y + connect \$89 $add$libresoc.v:174243$10457_Y + connect \$92 $add$libresoc.v:174244$10458_Y + connect \$95 $add$libresoc.v:174245$10459_Y + connect \$98 $add$libresoc.v:174246$10460_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 @@ -355577,43 +358448,43 @@ module \popcount connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:172308.1-172392.10" +attribute \src "libresoc.v:174404.1-174488.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick - attribute \src "libresoc.v:172365.17-172365.91" - wire $not$libresoc.v:172365$10412_Y - attribute \src "libresoc.v:172367.18-172367.93" - wire $not$libresoc.v:172367$10414_Y - attribute \src "libresoc.v:172369.18-172369.93" - wire $not$libresoc.v:172369$10416_Y - attribute \src "libresoc.v:172370.17-172370.138" - wire width 8 $not$libresoc.v:172370$10417_Y - attribute \src "libresoc.v:172372.18-172372.93" - wire $not$libresoc.v:172372$10419_Y - attribute \src "libresoc.v:172374.18-172374.93" - wire $not$libresoc.v:172374$10421_Y - attribute \src "libresoc.v:172376.18-172376.93" - wire $not$libresoc.v:172376$10423_Y - attribute \src "libresoc.v:172379.17-172379.91" - wire $not$libresoc.v:172379$10426_Y - attribute \src "libresoc.v:172366.18-172366.116" - wire $reduce_or$libresoc.v:172366$10413_Y - attribute \src "libresoc.v:172368.18-172368.122" - wire $reduce_or$libresoc.v:172368$10415_Y - attribute \src "libresoc.v:172371.18-172371.128" - wire $reduce_or$libresoc.v:172371$10418_Y - attribute \src "libresoc.v:172373.18-172373.134" - wire $reduce_or$libresoc.v:172373$10420_Y - attribute \src "libresoc.v:172375.18-172375.140" - wire $reduce_or$libresoc.v:172375$10422_Y - attribute \src "libresoc.v:172377.18-172377.90" - wire $reduce_or$libresoc.v:172377$10424_Y - attribute \src "libresoc.v:172378.17-172378.103" - wire $reduce_or$libresoc.v:172378$10425_Y - attribute \src "libresoc.v:172380.17-172380.109" - wire $reduce_or$libresoc.v:172380$10427_Y + attribute \src "libresoc.v:174461.17-174461.91" + wire $not$libresoc.v:174461$10463_Y + attribute \src "libresoc.v:174463.18-174463.93" + wire $not$libresoc.v:174463$10465_Y + attribute \src "libresoc.v:174465.18-174465.93" + wire $not$libresoc.v:174465$10467_Y + attribute \src "libresoc.v:174466.17-174466.138" + wire width 8 $not$libresoc.v:174466$10468_Y + attribute \src "libresoc.v:174468.18-174468.93" + wire $not$libresoc.v:174468$10470_Y + attribute \src "libresoc.v:174470.18-174470.93" + wire $not$libresoc.v:174470$10472_Y + attribute \src "libresoc.v:174472.18-174472.93" + wire $not$libresoc.v:174472$10474_Y + attribute \src "libresoc.v:174475.17-174475.91" + wire $not$libresoc.v:174475$10477_Y + attribute \src "libresoc.v:174462.18-174462.116" + wire $reduce_or$libresoc.v:174462$10464_Y + attribute \src "libresoc.v:174464.18-174464.122" + wire $reduce_or$libresoc.v:174464$10466_Y + attribute \src "libresoc.v:174467.18-174467.128" + wire $reduce_or$libresoc.v:174467$10469_Y + attribute \src "libresoc.v:174469.18-174469.134" + wire $reduce_or$libresoc.v:174469$10471_Y + attribute \src "libresoc.v:174471.18-174471.140" + wire $reduce_or$libresoc.v:174471$10473_Y + attribute \src "libresoc.v:174473.18-174473.90" + wire $reduce_or$libresoc.v:174473$10475_Y + attribute \src "libresoc.v:174474.17-174474.103" + wire $reduce_or$libresoc.v:174474$10476_Y + attribute \src "libresoc.v:174476.17-174476.109" + wire $reduce_or$libresoc.v:174476$10478_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -355671,149 +358542,149 @@ module \ppick attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172365$10412 + cell $not $not$libresoc.v:174461$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:172365$10412_Y + connect \Y $not$libresoc.v:174461$10463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172367$10414 + cell $not $not$libresoc.v:174463$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:172367$10414_Y + connect \Y $not$libresoc.v:174463$10465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172369$10416 + cell $not $not$libresoc.v:174465$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:172369$10416_Y + connect \Y $not$libresoc.v:174465$10467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172370$10417 + cell $not $not$libresoc.v:174466$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:172370$10417_Y + connect \Y $not$libresoc.v:174466$10468_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172372$10419 + cell $not $not$libresoc.v:174468$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:172372$10419_Y + connect \Y $not$libresoc.v:174468$10470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172374$10421 + cell $not $not$libresoc.v:174470$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:172374$10421_Y + connect \Y $not$libresoc.v:174470$10472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172376$10423 + cell $not $not$libresoc.v:174472$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:172376$10423_Y + connect \Y $not$libresoc.v:174472$10474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172379$10426 + cell $not $not$libresoc.v:174475$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172379$10426_Y + connect \Y $not$libresoc.v:174475$10477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172366$10413 + cell $reduce_or $reduce_or$libresoc.v:174462$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:172366$10413_Y + connect \Y $reduce_or$libresoc.v:174462$10464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172368$10415 + cell $reduce_or $reduce_or$libresoc.v:174464$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:172368$10415_Y + connect \Y $reduce_or$libresoc.v:174464$10466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172371$10418 + cell $reduce_or $reduce_or$libresoc.v:174467$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:172371$10418_Y + connect \Y $reduce_or$libresoc.v:174467$10469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172373$10420 + cell $reduce_or $reduce_or$libresoc.v:174469$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:172373$10420_Y + connect \Y $reduce_or$libresoc.v:174469$10471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172375$10422 + cell $reduce_or $reduce_or$libresoc.v:174471$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:172375$10422_Y + connect \Y $reduce_or$libresoc.v:174471$10473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172377$10424 + cell $reduce_or $reduce_or$libresoc.v:174473$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172377$10424_Y + connect \Y $reduce_or$libresoc.v:174473$10475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172378$10425 + cell $reduce_or $reduce_or$libresoc.v:174474$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:172378$10425_Y + connect \Y $reduce_or$libresoc.v:174474$10476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172380$10427 + cell $reduce_or $reduce_or$libresoc.v:174476$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:172380$10427_Y - end - connect \$7 $not$libresoc.v:172365$10412_Y - connect \$12 $reduce_or$libresoc.v:172366$10413_Y - connect \$11 $not$libresoc.v:172367$10414_Y - connect \$16 $reduce_or$libresoc.v:172368$10415_Y - connect \$15 $not$libresoc.v:172369$10416_Y - connect \$1 $not$libresoc.v:172370$10417_Y - connect \$20 $reduce_or$libresoc.v:172371$10418_Y - connect \$19 $not$libresoc.v:172372$10419_Y - connect \$24 $reduce_or$libresoc.v:172373$10420_Y - connect \$23 $not$libresoc.v:172374$10421_Y - connect \$28 $reduce_or$libresoc.v:172375$10422_Y - connect \$27 $not$libresoc.v:172376$10423_Y - connect \$31 $reduce_or$libresoc.v:172377$10424_Y - connect \$4 $reduce_or$libresoc.v:172378$10425_Y - connect \$3 $not$libresoc.v:172379$10426_Y - connect \$8 $reduce_or$libresoc.v:172380$10427_Y + connect \Y $reduce_or$libresoc.v:174476$10478_Y + end + connect \$7 $not$libresoc.v:174461$10463_Y + connect \$12 $reduce_or$libresoc.v:174462$10464_Y + connect \$11 $not$libresoc.v:174463$10465_Y + connect \$16 $reduce_or$libresoc.v:174464$10466_Y + connect \$15 $not$libresoc.v:174465$10467_Y + connect \$1 $not$libresoc.v:174466$10468_Y + connect \$20 $reduce_or$libresoc.v:174467$10469_Y + connect \$19 $not$libresoc.v:174468$10470_Y + connect \$24 $reduce_or$libresoc.v:174469$10471_Y + connect \$23 $not$libresoc.v:174470$10472_Y + connect \$28 $reduce_or$libresoc.v:174471$10473_Y + connect \$27 $not$libresoc.v:174472$10474_Y + connect \$31 $reduce_or$libresoc.v:174473$10475_Y + connect \$4 $reduce_or$libresoc.v:174474$10476_Y + connect \$3 $not$libresoc.v:174475$10477_Y + connect \$8 $reduce_or$libresoc.v:174476$10478_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -355826,43 +358697,43 @@ module \ppick connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:172396.1-172480.10" +attribute \src "libresoc.v:174492.1-174576.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" module \ppick$175 - attribute \src "libresoc.v:172453.17-172453.91" - wire $not$libresoc.v:172453$10428_Y - attribute \src "libresoc.v:172455.18-172455.93" - wire $not$libresoc.v:172455$10430_Y - attribute \src "libresoc.v:172457.18-172457.93" - wire $not$libresoc.v:172457$10432_Y - attribute \src "libresoc.v:172458.17-172458.138" - wire width 8 $not$libresoc.v:172458$10433_Y - attribute \src "libresoc.v:172460.18-172460.93" - wire $not$libresoc.v:172460$10435_Y - attribute \src "libresoc.v:172462.18-172462.93" - wire $not$libresoc.v:172462$10437_Y - attribute \src "libresoc.v:172464.18-172464.93" - wire $not$libresoc.v:172464$10439_Y - attribute \src "libresoc.v:172467.17-172467.91" - wire $not$libresoc.v:172467$10442_Y - attribute \src "libresoc.v:172454.18-172454.116" - wire $reduce_or$libresoc.v:172454$10429_Y - attribute \src "libresoc.v:172456.18-172456.122" - wire $reduce_or$libresoc.v:172456$10431_Y - attribute \src "libresoc.v:172459.18-172459.128" - wire $reduce_or$libresoc.v:172459$10434_Y - attribute \src "libresoc.v:172461.18-172461.134" - wire $reduce_or$libresoc.v:172461$10436_Y - attribute \src "libresoc.v:172463.18-172463.140" - wire $reduce_or$libresoc.v:172463$10438_Y - attribute \src "libresoc.v:172465.18-172465.90" - wire $reduce_or$libresoc.v:172465$10440_Y - attribute \src "libresoc.v:172466.17-172466.103" - wire $reduce_or$libresoc.v:172466$10441_Y - attribute \src "libresoc.v:172468.17-172468.109" - wire $reduce_or$libresoc.v:172468$10443_Y + attribute \src "libresoc.v:174549.17-174549.91" + wire $not$libresoc.v:174549$10479_Y + attribute \src "libresoc.v:174551.18-174551.93" + wire $not$libresoc.v:174551$10481_Y + attribute \src "libresoc.v:174553.18-174553.93" + wire $not$libresoc.v:174553$10483_Y + attribute \src "libresoc.v:174554.17-174554.138" + wire width 8 $not$libresoc.v:174554$10484_Y + attribute \src "libresoc.v:174556.18-174556.93" + wire $not$libresoc.v:174556$10486_Y + attribute \src "libresoc.v:174558.18-174558.93" + wire $not$libresoc.v:174558$10488_Y + attribute \src "libresoc.v:174560.18-174560.93" + wire $not$libresoc.v:174560$10490_Y + attribute \src "libresoc.v:174563.17-174563.91" + wire $not$libresoc.v:174563$10493_Y + attribute \src "libresoc.v:174550.18-174550.116" + wire $reduce_or$libresoc.v:174550$10480_Y + attribute \src "libresoc.v:174552.18-174552.122" + wire $reduce_or$libresoc.v:174552$10482_Y + attribute \src "libresoc.v:174555.18-174555.128" + wire $reduce_or$libresoc.v:174555$10485_Y + attribute \src "libresoc.v:174557.18-174557.134" + wire $reduce_or$libresoc.v:174557$10487_Y + attribute \src "libresoc.v:174559.18-174559.140" + wire $reduce_or$libresoc.v:174559$10489_Y + attribute \src "libresoc.v:174561.18-174561.90" + wire $reduce_or$libresoc.v:174561$10491_Y + attribute \src "libresoc.v:174562.17-174562.103" + wire $reduce_or$libresoc.v:174562$10492_Y + attribute \src "libresoc.v:174564.17-174564.109" + wire $reduce_or$libresoc.v:174564$10494_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -355920,149 +358791,149 @@ module \ppick$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172453$10428 + cell $not $not$libresoc.v:174549$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:172453$10428_Y + connect \Y $not$libresoc.v:174549$10479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172455$10430 + cell $not $not$libresoc.v:174551$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:172455$10430_Y + connect \Y $not$libresoc.v:174551$10481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172457$10432 + cell $not $not$libresoc.v:174553$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:172457$10432_Y + connect \Y $not$libresoc.v:174553$10483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172458$10433 + cell $not $not$libresoc.v:174554$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:172458$10433_Y + connect \Y $not$libresoc.v:174554$10484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172460$10435 + cell $not $not$libresoc.v:174556$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:172460$10435_Y + connect \Y $not$libresoc.v:174556$10486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172462$10437 + cell $not $not$libresoc.v:174558$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:172462$10437_Y + connect \Y $not$libresoc.v:174558$10488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172464$10439 + cell $not $not$libresoc.v:174560$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:172464$10439_Y + connect \Y $not$libresoc.v:174560$10490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172467$10442 + cell $not $not$libresoc.v:174563$10493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172467$10442_Y + connect \Y $not$libresoc.v:174563$10493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172454$10429 + cell $reduce_or $reduce_or$libresoc.v:174550$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:172454$10429_Y + connect \Y $reduce_or$libresoc.v:174550$10480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172456$10431 + cell $reduce_or $reduce_or$libresoc.v:174552$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:172456$10431_Y + connect \Y $reduce_or$libresoc.v:174552$10482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172459$10434 + cell $reduce_or $reduce_or$libresoc.v:174555$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:172459$10434_Y + connect \Y $reduce_or$libresoc.v:174555$10485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172461$10436 + cell $reduce_or $reduce_or$libresoc.v:174557$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:172461$10436_Y + connect \Y $reduce_or$libresoc.v:174557$10487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172463$10438 + cell $reduce_or $reduce_or$libresoc.v:174559$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:172463$10438_Y + connect \Y $reduce_or$libresoc.v:174559$10489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172465$10440 + cell $reduce_or $reduce_or$libresoc.v:174561$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172465$10440_Y + connect \Y $reduce_or$libresoc.v:174561$10491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172466$10441 + cell $reduce_or $reduce_or$libresoc.v:174562$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:172466$10441_Y + connect \Y $reduce_or$libresoc.v:174562$10492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172468$10443 + cell $reduce_or $reduce_or$libresoc.v:174564$10494 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:172468$10443_Y - end - connect \$7 $not$libresoc.v:172453$10428_Y - connect \$12 $reduce_or$libresoc.v:172454$10429_Y - connect \$11 $not$libresoc.v:172455$10430_Y - connect \$16 $reduce_or$libresoc.v:172456$10431_Y - connect \$15 $not$libresoc.v:172457$10432_Y - connect \$1 $not$libresoc.v:172458$10433_Y - connect \$20 $reduce_or$libresoc.v:172459$10434_Y - connect \$19 $not$libresoc.v:172460$10435_Y - connect \$24 $reduce_or$libresoc.v:172461$10436_Y - connect \$23 $not$libresoc.v:172462$10437_Y - connect \$28 $reduce_or$libresoc.v:172463$10438_Y - connect \$27 $not$libresoc.v:172464$10439_Y - connect \$31 $reduce_or$libresoc.v:172465$10440_Y - connect \$4 $reduce_or$libresoc.v:172466$10441_Y - connect \$3 $not$libresoc.v:172467$10442_Y - connect \$8 $reduce_or$libresoc.v:172468$10443_Y + connect \Y $reduce_or$libresoc.v:174564$10494_Y + end + connect \$7 $not$libresoc.v:174549$10479_Y + connect \$12 $reduce_or$libresoc.v:174550$10480_Y + connect \$11 $not$libresoc.v:174551$10481_Y + connect \$16 $reduce_or$libresoc.v:174552$10482_Y + connect \$15 $not$libresoc.v:174553$10483_Y + connect \$1 $not$libresoc.v:174554$10484_Y + connect \$20 $reduce_or$libresoc.v:174555$10485_Y + connect \$19 $not$libresoc.v:174556$10486_Y + connect \$24 $reduce_or$libresoc.v:174557$10487_Y + connect \$23 $not$libresoc.v:174558$10488_Y + connect \$28 $reduce_or$libresoc.v:174559$10489_Y + connect \$27 $not$libresoc.v:174560$10490_Y + connect \$31 $reduce_or$libresoc.v:174561$10491_Y + connect \$4 $reduce_or$libresoc.v:174562$10492_Y + connect \$3 $not$libresoc.v:174563$10493_Y + connect \$8 $reduce_or$libresoc.v:174564$10494_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -356075,19 +358946,19 @@ module \ppick$175 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:172484.1-172514.10" +attribute \src "libresoc.v:174580.1-174610.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:172505.17-172505.89" - wire width 2 $not$libresoc.v:172505$10444_Y - attribute \src "libresoc.v:172507.17-172507.91" - wire $not$libresoc.v:172507$10446_Y - attribute \src "libresoc.v:172506.17-172506.103" - wire $reduce_or$libresoc.v:172506$10445_Y - attribute \src "libresoc.v:172508.17-172508.89" - wire $reduce_or$libresoc.v:172508$10447_Y + attribute \src "libresoc.v:174601.17-174601.89" + wire width 2 $not$libresoc.v:174601$10495_Y + attribute \src "libresoc.v:174603.17-174603.91" + wire $not$libresoc.v:174603$10497_Y + attribute \src "libresoc.v:174602.17-174602.103" + wire $reduce_or$libresoc.v:174602$10496_Y + attribute \src "libresoc.v:174604.17-174604.89" + wire $reduce_or$libresoc.v:174604$10498_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -356109,56 +358980,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172505$10444 + cell $not $not$libresoc.v:174601$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:172505$10444_Y + connect \Y $not$libresoc.v:174601$10495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172507$10446 + cell $not $not$libresoc.v:174603$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172507$10446_Y + connect \Y $not$libresoc.v:174603$10497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172506$10445 + cell $reduce_or $reduce_or$libresoc.v:174602$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:172506$10445_Y + connect \Y $reduce_or$libresoc.v:174602$10496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172508$10447 + cell $reduce_or $reduce_or$libresoc.v:174604$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172508$10447_Y + connect \Y $reduce_or$libresoc.v:174604$10498_Y end - connect \$1 $not$libresoc.v:172505$10444_Y - connect \$4 $reduce_or$libresoc.v:172506$10445_Y - connect \$3 $not$libresoc.v:172507$10446_Y - connect \$7 $reduce_or$libresoc.v:172508$10447_Y + connect \$1 $not$libresoc.v:174601$10495_Y + connect \$4 $reduce_or$libresoc.v:174602$10496_Y + connect \$3 $not$libresoc.v:174603$10497_Y + connect \$7 $reduce_or$libresoc.v:174604$10498_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:172518.1-172539.10" +attribute \src "libresoc.v:174614.1-174635.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:172533.17-172533.89" - wire $not$libresoc.v:172533$10448_Y - attribute \src "libresoc.v:172534.17-172534.89" - wire $reduce_or$libresoc.v:172534$10449_Y + attribute \src "libresoc.v:174629.17-174629.89" + wire $not$libresoc.v:174629$10499_Y + attribute \src "libresoc.v:174630.17-174630.89" + wire $reduce_or$libresoc.v:174630$10500_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -356174,37 +359045,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172533$10448 + cell $not $not$libresoc.v:174629$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:172533$10448_Y + connect \Y $not$libresoc.v:174629$10499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172534$10449 + cell $reduce_or $reduce_or$libresoc.v:174630$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172534$10449_Y + connect \Y $reduce_or$libresoc.v:174630$10500_Y end - connect \$1 $not$libresoc.v:172533$10448_Y - connect \$3 $reduce_or$libresoc.v:172534$10449_Y + connect \$1 $not$libresoc.v:174629$10499_Y + connect \$3 $reduce_or$libresoc.v:174630$10500_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:172543.1-172564.10" +attribute \src "libresoc.v:174639.1-174660.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:172558.17-172558.89" - wire $not$libresoc.v:172558$10450_Y - attribute \src "libresoc.v:172559.17-172559.89" - wire $reduce_or$libresoc.v:172559$10451_Y + attribute \src "libresoc.v:174654.17-174654.89" + wire $not$libresoc.v:174654$10501_Y + attribute \src "libresoc.v:174655.17-174655.89" + wire $reduce_or$libresoc.v:174655$10502_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -356220,37 +359091,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172558$10450 + cell $not $not$libresoc.v:174654$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:172558$10450_Y + connect \Y $not$libresoc.v:174654$10501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172559$10451 + cell $reduce_or $reduce_or$libresoc.v:174655$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172559$10451_Y + connect \Y $reduce_or$libresoc.v:174655$10502_Y end - connect \$1 $not$libresoc.v:172558$10450_Y - connect \$3 $reduce_or$libresoc.v:172559$10451_Y + connect \$1 $not$libresoc.v:174654$10501_Y + connect \$3 $reduce_or$libresoc.v:174655$10502_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:172568.1-172589.10" +attribute \src "libresoc.v:174664.1-174685.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:172583.17-172583.89" - wire $not$libresoc.v:172583$10452_Y - attribute \src "libresoc.v:172584.17-172584.89" - wire $reduce_or$libresoc.v:172584$10453_Y + attribute \src "libresoc.v:174679.17-174679.89" + wire $not$libresoc.v:174679$10503_Y + attribute \src "libresoc.v:174680.17-174680.89" + wire $reduce_or$libresoc.v:174680$10504_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -356266,45 +359137,45 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172583$10452 + cell $not $not$libresoc.v:174679$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:172583$10452_Y + connect \Y $not$libresoc.v:174679$10503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172584$10453 + cell $reduce_or $reduce_or$libresoc.v:174680$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172584$10453_Y + connect \Y $reduce_or$libresoc.v:174680$10504_Y end - connect \$1 $not$libresoc.v:172583$10452_Y - connect \$3 $reduce_or$libresoc.v:172584$10453_Y + connect \$1 $not$libresoc.v:174679$10503_Y + connect \$3 $reduce_or$libresoc.v:174680$10504_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:172593.1-172632.10" +attribute \src "libresoc.v:174689.1-174728.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:172620.17-172620.91" - wire $not$libresoc.v:172620$10454_Y - attribute \src "libresoc.v:172622.17-172622.89" - wire width 3 $not$libresoc.v:172622$10456_Y - attribute \src "libresoc.v:172624.17-172624.91" - wire $not$libresoc.v:172624$10458_Y - attribute \src "libresoc.v:172621.18-172621.90" - wire $reduce_or$libresoc.v:172621$10455_Y - attribute \src "libresoc.v:172623.17-172623.103" - wire $reduce_or$libresoc.v:172623$10457_Y - attribute \src "libresoc.v:172625.17-172625.105" - wire $reduce_or$libresoc.v:172625$10459_Y + attribute \src "libresoc.v:174716.17-174716.91" + wire $not$libresoc.v:174716$10505_Y + attribute \src "libresoc.v:174718.17-174718.89" + wire width 3 $not$libresoc.v:174718$10507_Y + attribute \src "libresoc.v:174720.17-174720.91" + wire $not$libresoc.v:174720$10509_Y + attribute \src "libresoc.v:174717.18-174717.90" + wire $reduce_or$libresoc.v:174717$10506_Y + attribute \src "libresoc.v:174719.17-174719.103" + wire $reduce_or$libresoc.v:174719$10508_Y + attribute \src "libresoc.v:174721.17-174721.105" + wire $reduce_or$libresoc.v:174721$10510_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -356332,59 +359203,59 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172620$10454 + cell $not $not$libresoc.v:174716$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:172620$10454_Y + connect \Y $not$libresoc.v:174716$10505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172622$10456 + cell $not $not$libresoc.v:174718$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:172622$10456_Y + connect \Y $not$libresoc.v:174718$10507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172624$10458 + cell $not $not$libresoc.v:174720$10509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172624$10458_Y + connect \Y $not$libresoc.v:174720$10509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172621$10455 + cell $reduce_or $reduce_or$libresoc.v:174717$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172621$10455_Y + connect \Y $reduce_or$libresoc.v:174717$10506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172623$10457 + cell $reduce_or $reduce_or$libresoc.v:174719$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:172623$10457_Y + connect \Y $reduce_or$libresoc.v:174719$10508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172625$10459 + cell $reduce_or $reduce_or$libresoc.v:174721$10510 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:172625$10459_Y - end - connect \$7 $not$libresoc.v:172620$10454_Y - connect \$11 $reduce_or$libresoc.v:172621$10455_Y - connect \$1 $not$libresoc.v:172622$10456_Y - connect \$4 $reduce_or$libresoc.v:172623$10457_Y - connect \$3 $not$libresoc.v:172624$10458_Y - connect \$8 $reduce_or$libresoc.v:172625$10459_Y + connect \Y $reduce_or$libresoc.v:174721$10510_Y + end + connect \$7 $not$libresoc.v:174716$10505_Y + connect \$11 $reduce_or$libresoc.v:174717$10506_Y + connect \$1 $not$libresoc.v:174718$10507_Y + connect \$4 $reduce_or$libresoc.v:174719$10508_Y + connect \$3 $not$libresoc.v:174720$10509_Y + connect \$8 $reduce_or$libresoc.v:174721$10510_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -356392,19 +359263,19 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:172636.1-172666.10" +attribute \src "libresoc.v:174732.1-174762.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" attribute \generator "nMigen" module \rdpick_FAST_fast2 - attribute \src "libresoc.v:172657.17-172657.89" - wire width 2 $not$libresoc.v:172657$10460_Y - attribute \src "libresoc.v:172659.17-172659.91" - wire $not$libresoc.v:172659$10462_Y - attribute \src "libresoc.v:172658.17-172658.103" - wire $reduce_or$libresoc.v:172658$10461_Y - attribute \src "libresoc.v:172660.17-172660.89" - wire $reduce_or$libresoc.v:172660$10463_Y + attribute \src "libresoc.v:174753.17-174753.89" + wire width 2 $not$libresoc.v:174753$10511_Y + attribute \src "libresoc.v:174755.17-174755.91" + wire $not$libresoc.v:174755$10513_Y + attribute \src "libresoc.v:174754.17-174754.103" + wire $reduce_or$libresoc.v:174754$10512_Y + attribute \src "libresoc.v:174756.17-174756.89" + wire $reduce_or$libresoc.v:174756$10514_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -356426,88 +359297,88 @@ module \rdpick_FAST_fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172657$10460 + cell $not $not$libresoc.v:174753$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:172657$10460_Y + connect \Y $not$libresoc.v:174753$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172659$10462 + cell $not $not$libresoc.v:174755$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172659$10462_Y + connect \Y $not$libresoc.v:174755$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172658$10461 + cell $reduce_or $reduce_or$libresoc.v:174754$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:172658$10461_Y + connect \Y $reduce_or$libresoc.v:174754$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172660$10463 + cell $reduce_or $reduce_or$libresoc.v:174756$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172660$10463_Y + connect \Y $reduce_or$libresoc.v:174756$10514_Y end - connect \$1 $not$libresoc.v:172657$10460_Y - connect \$4 $reduce_or$libresoc.v:172658$10461_Y - connect \$3 $not$libresoc.v:172659$10462_Y - connect \$7 $reduce_or$libresoc.v:172660$10463_Y + connect \$1 $not$libresoc.v:174753$10511_Y + connect \$4 $reduce_or$libresoc.v:174754$10512_Y + connect \$3 $not$libresoc.v:174755$10513_Y + connect \$7 $reduce_or$libresoc.v:174756$10514_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:172670.1-172763.10" +attribute \src "libresoc.v:174766.1-174859.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" attribute \generator "nMigen" module \rdpick_INT_ra - attribute \src "libresoc.v:172733.17-172733.91" - wire $not$libresoc.v:172733$10464_Y - attribute \src "libresoc.v:172735.18-172735.93" - wire $not$libresoc.v:172735$10466_Y - attribute \src "libresoc.v:172737.18-172737.93" - wire $not$libresoc.v:172737$10468_Y - attribute \src "libresoc.v:172738.17-172738.89" - wire width 9 $not$libresoc.v:172738$10469_Y - attribute \src "libresoc.v:172740.18-172740.93" - wire $not$libresoc.v:172740$10471_Y - attribute \src "libresoc.v:172742.18-172742.93" - wire $not$libresoc.v:172742$10473_Y - attribute \src "libresoc.v:172744.18-172744.93" - wire $not$libresoc.v:172744$10475_Y - attribute \src "libresoc.v:172746.18-172746.93" - wire $not$libresoc.v:172746$10477_Y - attribute \src "libresoc.v:172749.17-172749.91" - wire $not$libresoc.v:172749$10480_Y - attribute \src "libresoc.v:172734.18-172734.106" - wire $reduce_or$libresoc.v:172734$10465_Y - attribute \src "libresoc.v:172736.18-172736.106" - wire $reduce_or$libresoc.v:172736$10467_Y - attribute \src "libresoc.v:172739.18-172739.106" - wire $reduce_or$libresoc.v:172739$10470_Y - attribute \src "libresoc.v:172741.18-172741.106" - wire $reduce_or$libresoc.v:172741$10472_Y - attribute \src "libresoc.v:172743.18-172743.106" - wire $reduce_or$libresoc.v:172743$10474_Y - attribute \src "libresoc.v:172745.18-172745.106" - wire $reduce_or$libresoc.v:172745$10476_Y - attribute \src "libresoc.v:172747.18-172747.90" - wire $reduce_or$libresoc.v:172747$10478_Y - attribute \src "libresoc.v:172748.17-172748.103" - wire $reduce_or$libresoc.v:172748$10479_Y - attribute \src "libresoc.v:172750.17-172750.105" - wire $reduce_or$libresoc.v:172750$10481_Y + attribute \src "libresoc.v:174829.17-174829.91" + wire $not$libresoc.v:174829$10515_Y + attribute \src "libresoc.v:174831.18-174831.93" + wire $not$libresoc.v:174831$10517_Y + attribute \src "libresoc.v:174833.18-174833.93" + wire $not$libresoc.v:174833$10519_Y + attribute \src "libresoc.v:174834.17-174834.89" + wire width 9 $not$libresoc.v:174834$10520_Y + attribute \src "libresoc.v:174836.18-174836.93" + wire $not$libresoc.v:174836$10522_Y + attribute \src "libresoc.v:174838.18-174838.93" + wire $not$libresoc.v:174838$10524_Y + attribute \src "libresoc.v:174840.18-174840.93" + wire $not$libresoc.v:174840$10526_Y + attribute \src "libresoc.v:174842.18-174842.93" + wire $not$libresoc.v:174842$10528_Y + attribute \src "libresoc.v:174845.17-174845.91" + wire $not$libresoc.v:174845$10531_Y + attribute \src "libresoc.v:174830.18-174830.106" + wire $reduce_or$libresoc.v:174830$10516_Y + attribute \src "libresoc.v:174832.18-174832.106" + wire $reduce_or$libresoc.v:174832$10518_Y + attribute \src "libresoc.v:174835.18-174835.106" + wire $reduce_or$libresoc.v:174835$10521_Y + attribute \src "libresoc.v:174837.18-174837.106" + wire $reduce_or$libresoc.v:174837$10523_Y + attribute \src "libresoc.v:174839.18-174839.106" + wire $reduce_or$libresoc.v:174839$10525_Y + attribute \src "libresoc.v:174841.18-174841.106" + wire $reduce_or$libresoc.v:174841$10527_Y + attribute \src "libresoc.v:174843.18-174843.90" + wire $reduce_or$libresoc.v:174843$10529_Y + attribute \src "libresoc.v:174844.17-174844.103" + wire $reduce_or$libresoc.v:174844$10530_Y + attribute \src "libresoc.v:174846.17-174846.105" + wire $reduce_or$libresoc.v:174846$10532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 9 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -356571,167 +359442,167 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172733$10464 + cell $not $not$libresoc.v:174829$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:172733$10464_Y + connect \Y $not$libresoc.v:174829$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172735$10466 + cell $not $not$libresoc.v:174831$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:172735$10466_Y + connect \Y $not$libresoc.v:174831$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172737$10468 + cell $not $not$libresoc.v:174833$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:172737$10468_Y + connect \Y $not$libresoc.v:174833$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172738$10469 + cell $not $not$libresoc.v:174834$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 9 connect \A \i - connect \Y $not$libresoc.v:172738$10469_Y + connect \Y $not$libresoc.v:174834$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172740$10471 + cell $not $not$libresoc.v:174836$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:172740$10471_Y + connect \Y $not$libresoc.v:174836$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172742$10473 + cell $not $not$libresoc.v:174838$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:172742$10473_Y + connect \Y $not$libresoc.v:174838$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172744$10475 + cell $not $not$libresoc.v:174840$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:172744$10475_Y + connect \Y $not$libresoc.v:174840$10526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172746$10477 + cell $not $not$libresoc.v:174842$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:172746$10477_Y + connect \Y $not$libresoc.v:174842$10528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172749$10480 + cell $not $not$libresoc.v:174845$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172749$10480_Y + connect \Y $not$libresoc.v:174845$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172734$10465 + cell $reduce_or $reduce_or$libresoc.v:174830$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:172734$10465_Y + connect \Y $reduce_or$libresoc.v:174830$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172736$10467 + cell $reduce_or $reduce_or$libresoc.v:174832$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:172736$10467_Y + connect \Y $reduce_or$libresoc.v:174832$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172739$10470 + cell $reduce_or $reduce_or$libresoc.v:174835$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:172739$10470_Y + connect \Y $reduce_or$libresoc.v:174835$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172741$10472 + cell $reduce_or $reduce_or$libresoc.v:174837$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:172741$10472_Y + connect \Y $reduce_or$libresoc.v:174837$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172743$10474 + cell $reduce_or $reduce_or$libresoc.v:174839$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:172743$10474_Y + connect \Y $reduce_or$libresoc.v:174839$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172745$10476 + cell $reduce_or $reduce_or$libresoc.v:174841$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:172745$10476_Y + connect \Y $reduce_or$libresoc.v:174841$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172747$10478 + cell $reduce_or $reduce_or$libresoc.v:174843$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172747$10478_Y + connect \Y $reduce_or$libresoc.v:174843$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172748$10479 + cell $reduce_or $reduce_or$libresoc.v:174844$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:172748$10479_Y + connect \Y $reduce_or$libresoc.v:174844$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172750$10481 + cell $reduce_or $reduce_or$libresoc.v:174846$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:172750$10481_Y - end - connect \$7 $not$libresoc.v:172733$10464_Y - connect \$12 $reduce_or$libresoc.v:172734$10465_Y - connect \$11 $not$libresoc.v:172735$10466_Y - connect \$16 $reduce_or$libresoc.v:172736$10467_Y - connect \$15 $not$libresoc.v:172737$10468_Y - connect \$1 $not$libresoc.v:172738$10469_Y - connect \$20 $reduce_or$libresoc.v:172739$10470_Y - connect \$19 $not$libresoc.v:172740$10471_Y - connect \$24 $reduce_or$libresoc.v:172741$10472_Y - connect \$23 $not$libresoc.v:172742$10473_Y - connect \$28 $reduce_or$libresoc.v:172743$10474_Y - connect \$27 $not$libresoc.v:172744$10475_Y - connect \$32 $reduce_or$libresoc.v:172745$10476_Y - connect \$31 $not$libresoc.v:172746$10477_Y - connect \$35 $reduce_or$libresoc.v:172747$10478_Y - connect \$4 $reduce_or$libresoc.v:172748$10479_Y - connect \$3 $not$libresoc.v:172749$10480_Y - connect \$8 $reduce_or$libresoc.v:172750$10481_Y + connect \Y $reduce_or$libresoc.v:174846$10532_Y + end + connect \$7 $not$libresoc.v:174829$10515_Y + connect \$12 $reduce_or$libresoc.v:174830$10516_Y + connect \$11 $not$libresoc.v:174831$10517_Y + connect \$16 $reduce_or$libresoc.v:174832$10518_Y + connect \$15 $not$libresoc.v:174833$10519_Y + connect \$1 $not$libresoc.v:174834$10520_Y + connect \$20 $reduce_or$libresoc.v:174835$10521_Y + connect \$19 $not$libresoc.v:174836$10522_Y + connect \$24 $reduce_or$libresoc.v:174837$10523_Y + connect \$23 $not$libresoc.v:174838$10524_Y + connect \$28 $reduce_or$libresoc.v:174839$10525_Y + connect \$27 $not$libresoc.v:174840$10526_Y + connect \$32 $reduce_or$libresoc.v:174841$10527_Y + connect \$31 $not$libresoc.v:174842$10528_Y + connect \$35 $reduce_or$libresoc.v:174843$10529_Y + connect \$4 $reduce_or$libresoc.v:174844$10530_Y + connect \$3 $not$libresoc.v:174845$10531_Y + connect \$8 $reduce_or$libresoc.v:174846$10532_Y connect \en_o \$35 connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t8 \$31 @@ -356745,43 +359616,43 @@ module \rdpick_INT_ra connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:172767.1-172851.10" +attribute \src "libresoc.v:174863.1-174947.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" attribute \generator "nMigen" module \rdpick_INT_rb - attribute \src "libresoc.v:172824.17-172824.91" - wire $not$libresoc.v:172824$10482_Y - attribute \src "libresoc.v:172826.18-172826.93" - wire $not$libresoc.v:172826$10484_Y - attribute \src "libresoc.v:172828.18-172828.93" - wire $not$libresoc.v:172828$10486_Y - attribute \src "libresoc.v:172829.17-172829.89" - wire width 8 $not$libresoc.v:172829$10487_Y - attribute \src "libresoc.v:172831.18-172831.93" - wire $not$libresoc.v:172831$10489_Y - attribute \src "libresoc.v:172833.18-172833.93" - wire $not$libresoc.v:172833$10491_Y - attribute \src "libresoc.v:172835.18-172835.93" - wire $not$libresoc.v:172835$10493_Y - attribute \src "libresoc.v:172838.17-172838.91" - wire $not$libresoc.v:172838$10496_Y - attribute \src "libresoc.v:172825.18-172825.106" - wire $reduce_or$libresoc.v:172825$10483_Y - attribute \src "libresoc.v:172827.18-172827.106" - wire $reduce_or$libresoc.v:172827$10485_Y - attribute \src "libresoc.v:172830.18-172830.106" - wire $reduce_or$libresoc.v:172830$10488_Y - attribute \src "libresoc.v:172832.18-172832.106" - wire $reduce_or$libresoc.v:172832$10490_Y - attribute \src "libresoc.v:172834.18-172834.106" - wire $reduce_or$libresoc.v:172834$10492_Y - attribute \src "libresoc.v:172836.18-172836.90" - wire $reduce_or$libresoc.v:172836$10494_Y - attribute \src "libresoc.v:172837.17-172837.103" - wire $reduce_or$libresoc.v:172837$10495_Y - attribute \src "libresoc.v:172839.17-172839.105" - wire $reduce_or$libresoc.v:172839$10497_Y + attribute \src "libresoc.v:174920.17-174920.91" + wire $not$libresoc.v:174920$10533_Y + attribute \src "libresoc.v:174922.18-174922.93" + wire $not$libresoc.v:174922$10535_Y + attribute \src "libresoc.v:174924.18-174924.93" + wire $not$libresoc.v:174924$10537_Y + attribute \src "libresoc.v:174925.17-174925.89" + wire width 8 $not$libresoc.v:174925$10538_Y + attribute \src "libresoc.v:174927.18-174927.93" + wire $not$libresoc.v:174927$10540_Y + attribute \src "libresoc.v:174929.18-174929.93" + wire $not$libresoc.v:174929$10542_Y + attribute \src "libresoc.v:174931.18-174931.93" + wire $not$libresoc.v:174931$10544_Y + attribute \src "libresoc.v:174934.17-174934.91" + wire $not$libresoc.v:174934$10547_Y + attribute \src "libresoc.v:174921.18-174921.106" + wire $reduce_or$libresoc.v:174921$10534_Y + attribute \src "libresoc.v:174923.18-174923.106" + wire $reduce_or$libresoc.v:174923$10536_Y + attribute \src "libresoc.v:174926.18-174926.106" + wire $reduce_or$libresoc.v:174926$10539_Y + attribute \src "libresoc.v:174928.18-174928.106" + wire $reduce_or$libresoc.v:174928$10541_Y + attribute \src "libresoc.v:174930.18-174930.106" + wire $reduce_or$libresoc.v:174930$10543_Y + attribute \src "libresoc.v:174932.18-174932.90" + wire $reduce_or$libresoc.v:174932$10545_Y + attribute \src "libresoc.v:174933.17-174933.103" + wire $reduce_or$libresoc.v:174933$10546_Y + attribute \src "libresoc.v:174935.17-174935.105" + wire $reduce_or$libresoc.v:174935$10548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -356839,149 +359710,149 @@ module \rdpick_INT_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172824$10482 + cell $not $not$libresoc.v:174920$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:172824$10482_Y + connect \Y $not$libresoc.v:174920$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172826$10484 + cell $not $not$libresoc.v:174922$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:172826$10484_Y + connect \Y $not$libresoc.v:174922$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172828$10486 + cell $not $not$libresoc.v:174924$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:172828$10486_Y + connect \Y $not$libresoc.v:174924$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172829$10487 + cell $not $not$libresoc.v:174925$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A \i - connect \Y $not$libresoc.v:172829$10487_Y + connect \Y $not$libresoc.v:174925$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172831$10489 + cell $not $not$libresoc.v:174927$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:172831$10489_Y + connect \Y $not$libresoc.v:174927$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172833$10491 + cell $not $not$libresoc.v:174929$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:172833$10491_Y + connect \Y $not$libresoc.v:174929$10542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172835$10493 + cell $not $not$libresoc.v:174931$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:172835$10493_Y + connect \Y $not$libresoc.v:174931$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172838$10496 + cell $not $not$libresoc.v:174934$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172838$10496_Y + connect \Y $not$libresoc.v:174934$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172825$10483 + cell $reduce_or $reduce_or$libresoc.v:174921$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:172825$10483_Y + connect \Y $reduce_or$libresoc.v:174921$10534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172827$10485 + cell $reduce_or $reduce_or$libresoc.v:174923$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:172827$10485_Y + connect \Y $reduce_or$libresoc.v:174923$10536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172830$10488 + cell $reduce_or $reduce_or$libresoc.v:174926$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:172830$10488_Y + connect \Y $reduce_or$libresoc.v:174926$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172832$10490 + cell $reduce_or $reduce_or$libresoc.v:174928$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:172832$10490_Y + connect \Y $reduce_or$libresoc.v:174928$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172834$10492 + cell $reduce_or $reduce_or$libresoc.v:174930$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:172834$10492_Y + connect \Y $reduce_or$libresoc.v:174930$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172836$10494 + cell $reduce_or $reduce_or$libresoc.v:174932$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172836$10494_Y + connect \Y $reduce_or$libresoc.v:174932$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172837$10495 + cell $reduce_or $reduce_or$libresoc.v:174933$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:172837$10495_Y + connect \Y $reduce_or$libresoc.v:174933$10546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172839$10497 + cell $reduce_or $reduce_or$libresoc.v:174935$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:172839$10497_Y - end - connect \$7 $not$libresoc.v:172824$10482_Y - connect \$12 $reduce_or$libresoc.v:172825$10483_Y - connect \$11 $not$libresoc.v:172826$10484_Y - connect \$16 $reduce_or$libresoc.v:172827$10485_Y - connect \$15 $not$libresoc.v:172828$10486_Y - connect \$1 $not$libresoc.v:172829$10487_Y - connect \$20 $reduce_or$libresoc.v:172830$10488_Y - connect \$19 $not$libresoc.v:172831$10489_Y - connect \$24 $reduce_or$libresoc.v:172832$10490_Y - connect \$23 $not$libresoc.v:172833$10491_Y - connect \$28 $reduce_or$libresoc.v:172834$10492_Y - connect \$27 $not$libresoc.v:172835$10493_Y - connect \$31 $reduce_or$libresoc.v:172836$10494_Y - connect \$4 $reduce_or$libresoc.v:172837$10495_Y - connect \$3 $not$libresoc.v:172838$10496_Y - connect \$8 $reduce_or$libresoc.v:172839$10497_Y + connect \Y $reduce_or$libresoc.v:174935$10548_Y + end + connect \$7 $not$libresoc.v:174920$10533_Y + connect \$12 $reduce_or$libresoc.v:174921$10534_Y + connect \$11 $not$libresoc.v:174922$10535_Y + connect \$16 $reduce_or$libresoc.v:174923$10536_Y + connect \$15 $not$libresoc.v:174924$10537_Y + connect \$1 $not$libresoc.v:174925$10538_Y + connect \$20 $reduce_or$libresoc.v:174926$10539_Y + connect \$19 $not$libresoc.v:174927$10540_Y + connect \$24 $reduce_or$libresoc.v:174928$10541_Y + connect \$23 $not$libresoc.v:174929$10542_Y + connect \$28 $reduce_or$libresoc.v:174930$10543_Y + connect \$27 $not$libresoc.v:174931$10544_Y + connect \$31 $reduce_or$libresoc.v:174932$10545_Y + connect \$4 $reduce_or$libresoc.v:174933$10546_Y + connect \$3 $not$libresoc.v:174934$10547_Y + connect \$8 $reduce_or$libresoc.v:174935$10548_Y connect \en_o \$31 connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t7 \$27 @@ -356994,19 +359865,19 @@ module \rdpick_INT_rb connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:172855.1-172885.10" +attribute \src "libresoc.v:174951.1-174981.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" attribute \generator "nMigen" module \rdpick_INT_rc - attribute \src "libresoc.v:172876.17-172876.89" - wire width 2 $not$libresoc.v:172876$10498_Y - attribute \src "libresoc.v:172878.17-172878.91" - wire $not$libresoc.v:172878$10500_Y - attribute \src "libresoc.v:172877.17-172877.103" - wire $reduce_or$libresoc.v:172877$10499_Y - attribute \src "libresoc.v:172879.17-172879.89" - wire $reduce_or$libresoc.v:172879$10501_Y + attribute \src "libresoc.v:174972.17-174972.89" + wire width 2 $not$libresoc.v:174972$10549_Y + attribute \src "libresoc.v:174974.17-174974.91" + wire $not$libresoc.v:174974$10551_Y + attribute \src "libresoc.v:174973.17-174973.103" + wire $reduce_or$libresoc.v:174973$10550_Y + attribute \src "libresoc.v:174975.17-174975.89" + wire $reduce_or$libresoc.v:174975$10552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -357028,56 +359899,56 @@ module \rdpick_INT_rc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172876$10498 + cell $not $not$libresoc.v:174972$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:172876$10498_Y + connect \Y $not$libresoc.v:174972$10549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172878$10500 + cell $not $not$libresoc.v:174974$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172878$10500_Y + connect \Y $not$libresoc.v:174974$10551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172877$10499 + cell $reduce_or $reduce_or$libresoc.v:174973$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:172877$10499_Y + connect \Y $reduce_or$libresoc.v:174973$10550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172879$10501 + cell $reduce_or $reduce_or$libresoc.v:174975$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172879$10501_Y + connect \Y $reduce_or$libresoc.v:174975$10552_Y end - connect \$1 $not$libresoc.v:172876$10498_Y - connect \$4 $reduce_or$libresoc.v:172877$10499_Y - connect \$3 $not$libresoc.v:172878$10500_Y - connect \$7 $reduce_or$libresoc.v:172879$10501_Y + connect \$1 $not$libresoc.v:174972$10549_Y + connect \$4 $reduce_or$libresoc.v:174973$10550_Y + connect \$3 $not$libresoc.v:174974$10551_Y + connect \$7 $reduce_or$libresoc.v:174975$10552_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:172889.1-172910.10" +attribute \src "libresoc.v:174985.1-175006.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:172904.17-172904.89" - wire $not$libresoc.v:172904$10502_Y - attribute \src "libresoc.v:172905.17-172905.89" - wire $reduce_or$libresoc.v:172905$10503_Y + attribute \src "libresoc.v:175000.17-175000.89" + wire $not$libresoc.v:175000$10553_Y + attribute \src "libresoc.v:175001.17-175001.89" + wire $reduce_or$libresoc.v:175001$10554_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -357093,45 +359964,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172904$10502 + cell $not $not$libresoc.v:175000$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:172904$10502_Y + connect \Y $not$libresoc.v:175000$10553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172905$10503 + cell $reduce_or $reduce_or$libresoc.v:175001$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172905$10503_Y + connect \Y $reduce_or$libresoc.v:175001$10554_Y end - connect \$1 $not$libresoc.v:172904$10502_Y - connect \$3 $reduce_or$libresoc.v:172905$10503_Y + connect \$1 $not$libresoc.v:175000$10553_Y + connect \$3 $reduce_or$libresoc.v:175001$10554_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:172914.1-172953.10" +attribute \src "libresoc.v:175010.1-175049.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:172941.17-172941.91" - wire $not$libresoc.v:172941$10504_Y - attribute \src "libresoc.v:172943.17-172943.89" - wire width 3 $not$libresoc.v:172943$10506_Y - attribute \src "libresoc.v:172945.17-172945.91" - wire $not$libresoc.v:172945$10508_Y - attribute \src "libresoc.v:172942.18-172942.90" - wire $reduce_or$libresoc.v:172942$10505_Y - attribute \src "libresoc.v:172944.17-172944.103" - wire $reduce_or$libresoc.v:172944$10507_Y - attribute \src "libresoc.v:172946.17-172946.105" - wire $reduce_or$libresoc.v:172946$10509_Y + attribute \src "libresoc.v:175037.17-175037.91" + wire $not$libresoc.v:175037$10555_Y + attribute \src "libresoc.v:175039.17-175039.89" + wire width 3 $not$libresoc.v:175039$10557_Y + attribute \src "libresoc.v:175041.17-175041.91" + wire $not$libresoc.v:175041$10559_Y + attribute \src "libresoc.v:175038.18-175038.90" + wire $reduce_or$libresoc.v:175038$10556_Y + attribute \src "libresoc.v:175040.17-175040.103" + wire $reduce_or$libresoc.v:175040$10558_Y + attribute \src "libresoc.v:175042.17-175042.105" + wire $reduce_or$libresoc.v:175042$10560_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -357159,59 +360030,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172941$10504 + cell $not $not$libresoc.v:175037$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:172941$10504_Y + connect \Y $not$libresoc.v:175037$10555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172943$10506 + cell $not $not$libresoc.v:175039$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:172943$10506_Y + connect \Y $not$libresoc.v:175039$10557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:172945$10508 + cell $not $not$libresoc.v:175041$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:172945$10508_Y + connect \Y $not$libresoc.v:175041$10559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172942$10505 + cell $reduce_or $reduce_or$libresoc.v:175038$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172942$10505_Y + connect \Y $reduce_or$libresoc.v:175038$10556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172944$10507 + cell $reduce_or $reduce_or$libresoc.v:175040$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:172944$10507_Y + connect \Y $reduce_or$libresoc.v:175040$10558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:172946$10509 + cell $reduce_or $reduce_or$libresoc.v:175042$10560 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:172946$10509_Y - end - connect \$7 $not$libresoc.v:172941$10504_Y - connect \$11 $reduce_or$libresoc.v:172942$10505_Y - connect \$1 $not$libresoc.v:172943$10506_Y - connect \$4 $reduce_or$libresoc.v:172944$10507_Y - connect \$3 $not$libresoc.v:172945$10508_Y - connect \$8 $reduce_or$libresoc.v:172946$10509_Y + connect \Y $reduce_or$libresoc.v:175042$10560_Y + end + connect \$7 $not$libresoc.v:175037$10555_Y + connect \$11 $reduce_or$libresoc.v:175038$10556_Y + connect \$1 $not$libresoc.v:175039$10557_Y + connect \$4 $reduce_or$libresoc.v:175040$10558_Y + connect \$3 $not$libresoc.v:175041$10559_Y + connect \$8 $reduce_or$libresoc.v:175042$10560_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -357219,15 +360090,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:172957.1-172978.10" +attribute \src "libresoc.v:175053.1-175074.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:172972.17-172972.89" - wire $not$libresoc.v:172972$10510_Y - attribute \src "libresoc.v:172973.17-172973.89" - wire $reduce_or$libresoc.v:172973$10511_Y + attribute \src "libresoc.v:175068.17-175068.89" + wire $not$libresoc.v:175068$10561_Y + attribute \src "libresoc.v:175069.17-175069.89" + wire $reduce_or$libresoc.v:175069$10562_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -357243,57 +360114,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:172972$10510 + cell $not $not$libresoc.v:175068$10561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:172972$10510_Y + connect \Y $not$libresoc.v:175068$10561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:172973$10511 + cell $reduce_or $reduce_or$libresoc.v:175069$10562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:172973$10511_Y + connect \Y $reduce_or$libresoc.v:175069$10562_Y end - connect \$1 $not$libresoc.v:172972$10510_Y - connect \$3 $reduce_or$libresoc.v:172973$10511_Y + connect \$1 $not$libresoc.v:175068$10561_Y + connect \$3 $reduce_or$libresoc.v:175069$10562_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:172982.1-173048.10" +attribute \src "libresoc.v:175078.1-175144.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:173027.17-173027.91" - wire $not$libresoc.v:173027$10512_Y - attribute \src "libresoc.v:173029.18-173029.93" - wire $not$libresoc.v:173029$10514_Y - attribute \src "libresoc.v:173031.18-173031.93" - wire $not$libresoc.v:173031$10516_Y - attribute \src "libresoc.v:173032.17-173032.89" - wire width 6 $not$libresoc.v:173032$10517_Y - attribute \src "libresoc.v:173034.18-173034.93" - wire $not$libresoc.v:173034$10519_Y - attribute \src "libresoc.v:173037.17-173037.91" - wire $not$libresoc.v:173037$10522_Y - attribute \src "libresoc.v:173028.18-173028.106" - wire $reduce_or$libresoc.v:173028$10513_Y - attribute \src "libresoc.v:173030.18-173030.106" - wire $reduce_or$libresoc.v:173030$10515_Y - attribute \src "libresoc.v:173033.18-173033.106" - wire $reduce_or$libresoc.v:173033$10518_Y - attribute \src "libresoc.v:173035.18-173035.90" - wire $reduce_or$libresoc.v:173035$10520_Y - attribute \src "libresoc.v:173036.17-173036.103" - wire $reduce_or$libresoc.v:173036$10521_Y - attribute \src "libresoc.v:173038.17-173038.105" - wire $reduce_or$libresoc.v:173038$10523_Y + attribute \src "libresoc.v:175123.17-175123.91" + wire $not$libresoc.v:175123$10563_Y + attribute \src "libresoc.v:175125.18-175125.93" + wire $not$libresoc.v:175125$10565_Y + attribute \src "libresoc.v:175127.18-175127.93" + wire $not$libresoc.v:175127$10567_Y + attribute \src "libresoc.v:175128.17-175128.89" + wire width 6 $not$libresoc.v:175128$10568_Y + attribute \src "libresoc.v:175130.18-175130.93" + wire $not$libresoc.v:175130$10570_Y + attribute \src "libresoc.v:175133.17-175133.91" + wire $not$libresoc.v:175133$10573_Y + attribute \src "libresoc.v:175124.18-175124.106" + wire $reduce_or$libresoc.v:175124$10564_Y + attribute \src "libresoc.v:175126.18-175126.106" + wire $reduce_or$libresoc.v:175126$10566_Y + attribute \src "libresoc.v:175129.18-175129.106" + wire $reduce_or$libresoc.v:175129$10569_Y + attribute \src "libresoc.v:175131.18-175131.90" + wire $reduce_or$libresoc.v:175131$10571_Y + attribute \src "libresoc.v:175132.17-175132.103" + wire $reduce_or$libresoc.v:175132$10572_Y + attribute \src "libresoc.v:175134.17-175134.105" + wire $reduce_or$libresoc.v:175134$10574_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -357339,113 +360210,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:173027$10512 + cell $not $not$libresoc.v:175123$10563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:173027$10512_Y + connect \Y $not$libresoc.v:175123$10563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:173029$10514 + cell $not $not$libresoc.v:175125$10565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:173029$10514_Y + connect \Y $not$libresoc.v:175125$10565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:173031$10516 + cell $not $not$libresoc.v:175127$10567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:173031$10516_Y + connect \Y $not$libresoc.v:175127$10567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:173032$10517 + cell $not $not$libresoc.v:175128$10568 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:173032$10517_Y + connect \Y $not$libresoc.v:175128$10568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:173034$10519 + cell $not $not$libresoc.v:175130$10570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:173034$10519_Y + connect \Y $not$libresoc.v:175130$10570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:173037$10522 + cell $not $not$libresoc.v:175133$10573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:173037$10522_Y + connect \Y $not$libresoc.v:175133$10573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:173028$10513 + cell $reduce_or $reduce_or$libresoc.v:175124$10564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:173028$10513_Y + connect \Y $reduce_or$libresoc.v:175124$10564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:173030$10515 + cell $reduce_or $reduce_or$libresoc.v:175126$10566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:173030$10515_Y + connect \Y $reduce_or$libresoc.v:175126$10566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:173033$10518 + cell $reduce_or $reduce_or$libresoc.v:175129$10569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:173033$10518_Y + connect \Y $reduce_or$libresoc.v:175129$10569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:173035$10520 + cell $reduce_or $reduce_or$libresoc.v:175131$10571 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:173035$10520_Y + connect \Y $reduce_or$libresoc.v:175131$10571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:173036$10521 + cell $reduce_or $reduce_or$libresoc.v:175132$10572 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:173036$10521_Y + connect \Y $reduce_or$libresoc.v:175132$10572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:173038$10523 + cell $reduce_or $reduce_or$libresoc.v:175134$10574 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:173038$10523_Y - end - connect \$7 $not$libresoc.v:173027$10512_Y - connect \$12 $reduce_or$libresoc.v:173028$10513_Y - connect \$11 $not$libresoc.v:173029$10514_Y - connect \$16 $reduce_or$libresoc.v:173030$10515_Y - connect \$15 $not$libresoc.v:173031$10516_Y - connect \$1 $not$libresoc.v:173032$10517_Y - connect \$20 $reduce_or$libresoc.v:173033$10518_Y - connect \$19 $not$libresoc.v:173034$10519_Y - connect \$23 $reduce_or$libresoc.v:173035$10520_Y - connect \$4 $reduce_or$libresoc.v:173036$10521_Y - connect \$3 $not$libresoc.v:173037$10522_Y - connect \$8 $reduce_or$libresoc.v:173038$10523_Y + connect \Y $reduce_or$libresoc.v:175134$10574_Y + end + connect \$7 $not$libresoc.v:175123$10563_Y + connect \$12 $reduce_or$libresoc.v:175124$10564_Y + connect \$11 $not$libresoc.v:175125$10565_Y + connect \$16 $reduce_or$libresoc.v:175126$10566_Y + connect \$15 $not$libresoc.v:175127$10567_Y + connect \$1 $not$libresoc.v:175128$10568_Y + connect \$20 $reduce_or$libresoc.v:175129$10569_Y + connect \$19 $not$libresoc.v:175130$10570_Y + connect \$23 $reduce_or$libresoc.v:175131$10571_Y + connect \$4 $reduce_or$libresoc.v:175132$10572_Y + connect \$3 $not$libresoc.v:175133$10573_Y + connect \$8 $reduce_or$libresoc.v:175134$10574_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -357456,177 +360327,177 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:173052.1-173523.10" +attribute \src "libresoc.v:175148.1-175619.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:173053.7-173053.20" + attribute \src "libresoc.v:175149.7-175149.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173383.3-173422.6" - wire width 4 $0\r0__data_o$next[3:0]$10579 - attribute \src "libresoc.v:173138.3-173139.37" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $0\r0__data_o$next[3:0]$10630 + attribute \src "libresoc.v:175234.3-175235.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:173453.3-173492.6" - wire width 4 $0\r20__data_o$next[3:0]$10593 - attribute \src "libresoc.v:173136.3-173137.39" + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $0\r20__data_o$next[3:0]$10644 + attribute \src "libresoc.v:175232.3-175233.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:173216.3-173242.6" - wire width 4 $0\reg$next[3:0]$10545 - attribute \src "libresoc.v:173134.3-173135.25" + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $0\reg$next[3:0]$10596 + attribute \src "libresoc.v:175230.3-175231.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:173146.3-173185.6" - wire width 4 $0\src10__data_o$next[3:0]$10536 - attribute \src "libresoc.v:173144.3-173145.43" + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $0\src10__data_o$next[3:0]$10587 + attribute \src "libresoc.v:175240.3-175241.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:173243.3-173282.6" - wire width 4 $0\src20__data_o$next[3:0]$10551 - attribute \src "libresoc.v:173142.3-173143.43" + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $0\src20__data_o$next[3:0]$10602 + attribute \src "libresoc.v:175238.3-175239.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:173313.3-173352.6" - wire width 4 $0\src30__data_o$next[3:0]$10565 - attribute \src "libresoc.v:173140.3-173141.43" + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $0\src30__data_o$next[3:0]$10616 + attribute \src "libresoc.v:175236.3-175237.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:173423.3-173452.6" - wire $0\wr_detect$10[0:0]$10587 - attribute \src "libresoc.v:173493.3-173522.6" - wire $0\wr_detect$13[0:0]$10601 - attribute \src "libresoc.v:173283.3-173312.6" - wire $0\wr_detect$4[0:0]$10559 - attribute \src "libresoc.v:173353.3-173382.6" - wire $0\wr_detect$7[0:0]$10573 - attribute \src "libresoc.v:173186.3-173215.6" + attribute \src "libresoc.v:175519.3-175548.6" + wire $0\wr_detect$10[0:0]$10638 + attribute \src "libresoc.v:175589.3-175618.6" + wire $0\wr_detect$13[0:0]$10652 + attribute \src "libresoc.v:175379.3-175408.6" + wire $0\wr_detect$4[0:0]$10610 + attribute \src "libresoc.v:175449.3-175478.6" + wire $0\wr_detect$7[0:0]$10624 + attribute \src "libresoc.v:175282.3-175311.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:173383.3-173422.6" - wire width 4 $1\r0__data_o$next[3:0]$10580 - attribute \src "libresoc.v:173078.13-173078.30" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $1\r0__data_o$next[3:0]$10631 + attribute \src "libresoc.v:175174.13-175174.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:173453.3-173492.6" - wire width 4 $1\r20__data_o$next[3:0]$10594 - attribute \src "libresoc.v:173085.13-173085.31" + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $1\r20__data_o$next[3:0]$10645 + attribute \src "libresoc.v:175181.13-175181.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:173216.3-173242.6" - wire width 4 $1\reg$next[3:0]$10546 - attribute \src "libresoc.v:173091.13-173091.25" + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $1\reg$next[3:0]$10597 + attribute \src "libresoc.v:175187.13-175187.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:173146.3-173185.6" - wire width 4 $1\src10__data_o$next[3:0]$10537 - attribute \src "libresoc.v:173096.13-173096.33" + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $1\src10__data_o$next[3:0]$10588 + attribute \src "libresoc.v:175192.13-175192.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:173243.3-173282.6" - wire width 4 $1\src20__data_o$next[3:0]$10552 - attribute \src "libresoc.v:173103.13-173103.33" + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $1\src20__data_o$next[3:0]$10603 + attribute \src "libresoc.v:175199.13-175199.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:173313.3-173352.6" - wire width 4 $1\src30__data_o$next[3:0]$10566 - attribute \src "libresoc.v:173110.13-173110.33" + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $1\src30__data_o$next[3:0]$10617 + attribute \src "libresoc.v:175206.13-175206.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:173423.3-173452.6" - wire $1\wr_detect$10[0:0]$10588 - attribute \src "libresoc.v:173493.3-173522.6" - wire $1\wr_detect$13[0:0]$10602 - attribute \src "libresoc.v:173283.3-173312.6" - wire $1\wr_detect$4[0:0]$10560 - attribute \src "libresoc.v:173353.3-173382.6" - wire $1\wr_detect$7[0:0]$10574 - attribute \src "libresoc.v:173186.3-173215.6" + attribute \src "libresoc.v:175519.3-175548.6" + wire $1\wr_detect$10[0:0]$10639 + attribute \src "libresoc.v:175589.3-175618.6" + wire $1\wr_detect$13[0:0]$10653 + attribute \src "libresoc.v:175379.3-175408.6" + wire $1\wr_detect$4[0:0]$10611 + attribute \src "libresoc.v:175449.3-175478.6" + wire $1\wr_detect$7[0:0]$10625 + attribute \src "libresoc.v:175282.3-175311.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:173383.3-173422.6" - wire width 4 $2\r0__data_o$next[3:0]$10581 - attribute \src "libresoc.v:173453.3-173492.6" - wire width 4 $2\r20__data_o$next[3:0]$10595 - attribute \src "libresoc.v:173216.3-173242.6" - wire width 4 $2\reg$next[3:0]$10547 - attribute \src "libresoc.v:173146.3-173185.6" - wire width 4 $2\src10__data_o$next[3:0]$10538 - attribute \src "libresoc.v:173243.3-173282.6" - wire width 4 $2\src20__data_o$next[3:0]$10553 - attribute \src "libresoc.v:173313.3-173352.6" - wire width 4 $2\src30__data_o$next[3:0]$10567 - attribute \src "libresoc.v:173423.3-173452.6" - wire $2\wr_detect$10[0:0]$10589 - attribute \src "libresoc.v:173493.3-173522.6" - wire $2\wr_detect$13[0:0]$10603 - attribute \src "libresoc.v:173283.3-173312.6" - wire $2\wr_detect$4[0:0]$10561 - attribute \src "libresoc.v:173353.3-173382.6" - wire $2\wr_detect$7[0:0]$10575 - attribute \src "libresoc.v:173186.3-173215.6" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $2\r0__data_o$next[3:0]$10632 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $2\r20__data_o$next[3:0]$10646 + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $2\reg$next[3:0]$10598 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $2\src10__data_o$next[3:0]$10589 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $2\src20__data_o$next[3:0]$10604 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $2\src30__data_o$next[3:0]$10618 + attribute \src "libresoc.v:175519.3-175548.6" + wire $2\wr_detect$10[0:0]$10640 + attribute \src "libresoc.v:175589.3-175618.6" + wire $2\wr_detect$13[0:0]$10654 + attribute \src "libresoc.v:175379.3-175408.6" + wire $2\wr_detect$4[0:0]$10612 + attribute \src "libresoc.v:175449.3-175478.6" + wire $2\wr_detect$7[0:0]$10626 + attribute \src "libresoc.v:175282.3-175311.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:173383.3-173422.6" - wire width 4 $3\r0__data_o$next[3:0]$10582 - attribute \src "libresoc.v:173453.3-173492.6" - wire width 4 $3\r20__data_o$next[3:0]$10596 - attribute \src "libresoc.v:173216.3-173242.6" - wire width 4 $3\reg$next[3:0]$10548 - attribute \src "libresoc.v:173146.3-173185.6" - wire width 4 $3\src10__data_o$next[3:0]$10539 - attribute \src "libresoc.v:173243.3-173282.6" - wire width 4 $3\src20__data_o$next[3:0]$10554 - attribute \src "libresoc.v:173313.3-173352.6" - wire width 4 $3\src30__data_o$next[3:0]$10568 - attribute \src "libresoc.v:173423.3-173452.6" - wire $3\wr_detect$10[0:0]$10590 - attribute \src "libresoc.v:173493.3-173522.6" - wire $3\wr_detect$13[0:0]$10604 - attribute \src "libresoc.v:173283.3-173312.6" - wire $3\wr_detect$4[0:0]$10562 - attribute \src "libresoc.v:173353.3-173382.6" - wire $3\wr_detect$7[0:0]$10576 - attribute \src "libresoc.v:173186.3-173215.6" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $3\r0__data_o$next[3:0]$10633 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $3\r20__data_o$next[3:0]$10647 + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $3\reg$next[3:0]$10599 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $3\src10__data_o$next[3:0]$10590 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $3\src20__data_o$next[3:0]$10605 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $3\src30__data_o$next[3:0]$10619 + attribute \src "libresoc.v:175519.3-175548.6" + wire $3\wr_detect$10[0:0]$10641 + attribute \src "libresoc.v:175589.3-175618.6" + wire $3\wr_detect$13[0:0]$10655 + attribute \src "libresoc.v:175379.3-175408.6" + wire $3\wr_detect$4[0:0]$10613 + attribute \src "libresoc.v:175449.3-175478.6" + wire $3\wr_detect$7[0:0]$10627 + attribute \src "libresoc.v:175282.3-175311.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:173383.3-173422.6" - wire width 4 $4\r0__data_o$next[3:0]$10583 - attribute \src "libresoc.v:173453.3-173492.6" - wire width 4 $4\r20__data_o$next[3:0]$10597 - attribute \src "libresoc.v:173216.3-173242.6" - wire width 4 $4\reg$next[3:0]$10549 - attribute \src "libresoc.v:173146.3-173185.6" - wire width 4 $4\src10__data_o$next[3:0]$10540 - attribute \src "libresoc.v:173243.3-173282.6" - wire width 4 $4\src20__data_o$next[3:0]$10555 - attribute \src "libresoc.v:173313.3-173352.6" - wire width 4 $4\src30__data_o$next[3:0]$10569 - attribute \src "libresoc.v:173423.3-173452.6" - wire $4\wr_detect$10[0:0]$10591 - attribute \src "libresoc.v:173493.3-173522.6" - wire $4\wr_detect$13[0:0]$10605 - attribute \src "libresoc.v:173283.3-173312.6" - wire $4\wr_detect$4[0:0]$10563 - attribute \src "libresoc.v:173353.3-173382.6" - wire $4\wr_detect$7[0:0]$10577 - attribute \src "libresoc.v:173186.3-173215.6" + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $4\r0__data_o$next[3:0]$10634 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $4\r20__data_o$next[3:0]$10648 + attribute \src "libresoc.v:175312.3-175338.6" + wire width 4 $4\reg$next[3:0]$10600 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $4\src10__data_o$next[3:0]$10591 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $4\src20__data_o$next[3:0]$10606 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $4\src30__data_o$next[3:0]$10620 + attribute \src "libresoc.v:175519.3-175548.6" + wire $4\wr_detect$10[0:0]$10642 + attribute \src "libresoc.v:175589.3-175618.6" + wire $4\wr_detect$13[0:0]$10656 + attribute \src "libresoc.v:175379.3-175408.6" + wire $4\wr_detect$4[0:0]$10614 + attribute \src "libresoc.v:175449.3-175478.6" + wire $4\wr_detect$7[0:0]$10628 + attribute \src "libresoc.v:175282.3-175311.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:173383.3-173422.6" - wire width 4 $5\r0__data_o$next[3:0]$10584 - attribute \src "libresoc.v:173453.3-173492.6" - wire width 4 $5\r20__data_o$next[3:0]$10598 - attribute \src "libresoc.v:173146.3-173185.6" - wire width 4 $5\src10__data_o$next[3:0]$10541 - attribute \src "libresoc.v:173243.3-173282.6" - wire width 4 $5\src20__data_o$next[3:0]$10556 - attribute \src "libresoc.v:173313.3-173352.6" - wire width 4 $5\src30__data_o$next[3:0]$10570 - attribute \src "libresoc.v:173383.3-173422.6" - wire width 4 $6\r0__data_o$next[3:0]$10585 - attribute \src "libresoc.v:173453.3-173492.6" - wire width 4 $6\r20__data_o$next[3:0]$10599 - attribute \src "libresoc.v:173146.3-173185.6" - wire width 4 $6\src10__data_o$next[3:0]$10542 - attribute \src "libresoc.v:173243.3-173282.6" - wire width 4 $6\src20__data_o$next[3:0]$10557 - attribute \src "libresoc.v:173313.3-173352.6" - wire width 4 $6\src30__data_o$next[3:0]$10571 - attribute \src "libresoc.v:173129.17-173129.104" - wire $not$libresoc.v:173129$10524_Y - attribute \src "libresoc.v:173130.18-173130.105" - wire $not$libresoc.v:173130$10525_Y - attribute \src "libresoc.v:173131.17-173131.100" - wire $not$libresoc.v:173131$10526_Y - attribute \src "libresoc.v:173132.17-173132.103" - wire $not$libresoc.v:173132$10527_Y - attribute \src "libresoc.v:173133.17-173133.103" - wire $not$libresoc.v:173133$10528_Y + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $5\r0__data_o$next[3:0]$10635 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $5\r20__data_o$next[3:0]$10649 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $5\src10__data_o$next[3:0]$10592 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $5\src20__data_o$next[3:0]$10607 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $5\src30__data_o$next[3:0]$10621 + attribute \src "libresoc.v:175479.3-175518.6" + wire width 4 $6\r0__data_o$next[3:0]$10636 + attribute \src "libresoc.v:175549.3-175588.6" + wire width 4 $6\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:175242.3-175281.6" + wire width 4 $6\src10__data_o$next[3:0]$10593 + attribute \src "libresoc.v:175339.3-175378.6" + wire width 4 $6\src20__data_o$next[3:0]$10608 + attribute \src "libresoc.v:175409.3-175448.6" + wire width 4 $6\src30__data_o$next[3:0]$10622 + attribute \src "libresoc.v:175225.17-175225.104" + wire $not$libresoc.v:175225$10575_Y + attribute \src "libresoc.v:175226.18-175226.105" + wire $not$libresoc.v:175226$10576_Y + attribute \src "libresoc.v:175227.17-175227.100" + wire $not$libresoc.v:175227$10577_Y + attribute \src "libresoc.v:175228.17-175228.103" + wire $not$libresoc.v:175228$10578_Y + attribute \src "libresoc.v:175229.17-175229.103" + wire $not$libresoc.v:175229$10579_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -357637,9 +360508,9 @@ module \reg_0 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest10__data_i @@ -357649,7 +360520,7 @@ module \reg_0 wire width 4 input 11 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest20__wen - attribute \src "libresoc.v:173053.7-173053.15" + attribute \src "libresoc.v:175149.7-175149.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r0__data_o @@ -357700,152 +360571,152 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173129$10524 + cell $not $not$libresoc.v:175225$10575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:173129$10524_Y + connect \Y $not$libresoc.v:175225$10575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173130$10525 + cell $not $not$libresoc.v:175226$10576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:173130$10525_Y + connect \Y $not$libresoc.v:175226$10576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173131$10526 + cell $not $not$libresoc.v:175227$10577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:173131$10526_Y + connect \Y $not$libresoc.v:175227$10577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173132$10527 + cell $not $not$libresoc.v:175228$10578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:173132$10527_Y + connect \Y $not$libresoc.v:175228$10578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173133$10528 + cell $not $not$libresoc.v:175229$10579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:173133$10528_Y + connect \Y $not$libresoc.v:175229$10579_Y end - attribute \src "libresoc.v:173053.7-173053.20" - process $proc$libresoc.v:173053$10606 + attribute \src "libresoc.v:175149.7-175149.20" + process $proc$libresoc.v:175149$10657 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173078.13-173078.30" - process $proc$libresoc.v:173078$10607 + attribute \src "libresoc.v:175174.13-175174.30" + process $proc$libresoc.v:175174$10658 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:173085.13-173085.31" - process $proc$libresoc.v:173085$10608 + attribute \src "libresoc.v:175181.13-175181.31" + process $proc$libresoc.v:175181$10659 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:173091.13-173091.25" - process $proc$libresoc.v:173091$10609 + attribute \src "libresoc.v:175187.13-175187.25" + process $proc$libresoc.v:175187$10660 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:173096.13-173096.33" - process $proc$libresoc.v:173096$10610 + attribute \src "libresoc.v:175192.13-175192.33" + process $proc$libresoc.v:175192$10661 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:173103.13-173103.33" - process $proc$libresoc.v:173103$10611 + attribute \src "libresoc.v:175199.13-175199.33" + process $proc$libresoc.v:175199$10662 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:173110.13-173110.33" - process $proc$libresoc.v:173110$10612 + attribute \src "libresoc.v:175206.13-175206.33" + process $proc$libresoc.v:175206$10663 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:173134.3-173135.25" - process $proc$libresoc.v:173134$10529 + attribute \src "libresoc.v:175230.3-175231.25" + process $proc$libresoc.v:175230$10580 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:173136.3-173137.39" - process $proc$libresoc.v:173136$10530 + attribute \src "libresoc.v:175232.3-175233.39" + process $proc$libresoc.v:175232$10581 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:173138.3-173139.37" - process $proc$libresoc.v:173138$10531 + attribute \src "libresoc.v:175234.3-175235.37" + process $proc$libresoc.v:175234$10582 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:173140.3-173141.43" - process $proc$libresoc.v:173140$10532 + attribute \src "libresoc.v:175236.3-175237.43" + process $proc$libresoc.v:175236$10583 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:173142.3-173143.43" - process $proc$libresoc.v:173142$10533 + attribute \src "libresoc.v:175238.3-175239.43" + process $proc$libresoc.v:175238$10584 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:173144.3-173145.43" - process $proc$libresoc.v:173144$10534 + attribute \src "libresoc.v:175240.3-175241.43" + process $proc$libresoc.v:175240$10585 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:173146.3-173185.6" - process $proc$libresoc.v:173146$10535 + attribute \src "libresoc.v:175242.3-175281.6" + process $proc$libresoc.v:175242$10586 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10536 $6\src10__data_o$next[3:0]$10542 - attribute \src "libresoc.v:173147.5-173147.29" + assign $0\src10__data_o$next[3:0]$10587 $6\src10__data_o$next[3:0]$10593 + attribute \src "libresoc.v:175243.5-175243.29" switch \initial - attribute \src "libresoc.v:173147.9-173147.17" + attribute \src "libresoc.v:175243.9-175243.17" case 1'1 case end @@ -357857,66 +360728,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10537 $5\src10__data_o$next[3:0]$10541 + assign $1\src10__data_o$next[3:0]$10588 $5\src10__data_o$next[3:0]$10592 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10538 \dest10__data_i + assign $2\src10__data_o$next[3:0]$10589 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10538 4'0000 + assign $2\src10__data_o$next[3:0]$10589 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10539 \dest20__data_i + assign $3\src10__data_o$next[3:0]$10590 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10539 $2\src10__data_o$next[3:0]$10538 + assign $3\src10__data_o$next[3:0]$10590 $2\src10__data_o$next[3:0]$10589 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10540 \w0__data_i + assign $4\src10__data_o$next[3:0]$10591 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10540 $3\src10__data_o$next[3:0]$10539 + assign $4\src10__data_o$next[3:0]$10591 $3\src10__data_o$next[3:0]$10590 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10541 \reg + assign $5\src10__data_o$next[3:0]$10592 \reg case - assign $5\src10__data_o$next[3:0]$10541 $4\src10__data_o$next[3:0]$10540 + assign $5\src10__data_o$next[3:0]$10592 $4\src10__data_o$next[3:0]$10591 end case - assign $1\src10__data_o$next[3:0]$10537 4'0000 + assign $1\src10__data_o$next[3:0]$10588 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10542 4'0000 + assign $6\src10__data_o$next[3:0]$10593 4'0000 case - assign $6\src10__data_o$next[3:0]$10542 $1\src10__data_o$next[3:0]$10537 + assign $6\src10__data_o$next[3:0]$10593 $1\src10__data_o$next[3:0]$10588 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10536 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10587 end - attribute \src "libresoc.v:173186.3-173215.6" - process $proc$libresoc.v:173186$10543 + attribute \src "libresoc.v:175282.3-175311.6" + process $proc$libresoc.v:175282$10594 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:173187.5-173187.29" + attribute \src "libresoc.v:175283.5-175283.29" switch \initial - attribute \src "libresoc.v:173187.9-173187.17" + attribute \src "libresoc.v:175283.9-175283.17" case 1'1 case end @@ -357962,17 +360833,17 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:173216.3-173242.6" - process $proc$libresoc.v:173216$10544 + attribute \src "libresoc.v:175312.3-175338.6" + process $proc$libresoc.v:175312$10595 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10545 $4\reg$next[3:0]$10549 - attribute \src "libresoc.v:173217.5-173217.29" + assign $0\reg$next[3:0]$10596 $4\reg$next[3:0]$10600 + attribute \src "libresoc.v:175313.5-175313.29" switch \initial - attribute \src "libresoc.v:173217.9-173217.17" + attribute \src "libresoc.v:175313.9-175313.17" case 1'1 case end @@ -357981,49 +360852,49 @@ module \reg_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10546 \dest10__data_i + assign $1\reg$next[3:0]$10597 \dest10__data_i case - assign $1\reg$next[3:0]$10546 \reg + assign $1\reg$next[3:0]$10597 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10547 \dest20__data_i + assign $2\reg$next[3:0]$10598 \dest20__data_i case - assign $2\reg$next[3:0]$10547 $1\reg$next[3:0]$10546 + assign $2\reg$next[3:0]$10598 $1\reg$next[3:0]$10597 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10548 \w0__data_i + assign $3\reg$next[3:0]$10599 \w0__data_i case - assign $3\reg$next[3:0]$10548 $2\reg$next[3:0]$10547 + assign $3\reg$next[3:0]$10599 $2\reg$next[3:0]$10598 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10549 4'0000 + assign $4\reg$next[3:0]$10600 4'0000 case - assign $4\reg$next[3:0]$10549 $3\reg$next[3:0]$10548 + assign $4\reg$next[3:0]$10600 $3\reg$next[3:0]$10599 end sync always - update \reg$next $0\reg$next[3:0]$10545 + update \reg$next $0\reg$next[3:0]$10596 end - attribute \src "libresoc.v:173243.3-173282.6" - process $proc$libresoc.v:173243$10550 + attribute \src "libresoc.v:175339.3-175378.6" + process $proc$libresoc.v:175339$10601 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10551 $6\src20__data_o$next[3:0]$10557 - attribute \src "libresoc.v:173244.5-173244.29" + assign $0\src20__data_o$next[3:0]$10602 $6\src20__data_o$next[3:0]$10608 + attribute \src "libresoc.v:175340.5-175340.29" switch \initial - attribute \src "libresoc.v:173244.9-173244.17" + attribute \src "libresoc.v:175340.9-175340.17" case 1'1 case end @@ -358035,66 +360906,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10552 $5\src20__data_o$next[3:0]$10556 + assign $1\src20__data_o$next[3:0]$10603 $5\src20__data_o$next[3:0]$10607 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10553 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10604 \dest10__data_i case - assign $2\src20__data_o$next[3:0]$10553 4'0000 + assign $2\src20__data_o$next[3:0]$10604 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10554 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10605 \dest20__data_i case - assign $3\src20__data_o$next[3:0]$10554 $2\src20__data_o$next[3:0]$10553 + assign $3\src20__data_o$next[3:0]$10605 $2\src20__data_o$next[3:0]$10604 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10555 \w0__data_i + assign $4\src20__data_o$next[3:0]$10606 \w0__data_i case - assign $4\src20__data_o$next[3:0]$10555 $3\src20__data_o$next[3:0]$10554 + assign $4\src20__data_o$next[3:0]$10606 $3\src20__data_o$next[3:0]$10605 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10556 \reg + assign $5\src20__data_o$next[3:0]$10607 \reg case - assign $5\src20__data_o$next[3:0]$10556 $4\src20__data_o$next[3:0]$10555 + assign $5\src20__data_o$next[3:0]$10607 $4\src20__data_o$next[3:0]$10606 end case - assign $1\src20__data_o$next[3:0]$10552 4'0000 + assign $1\src20__data_o$next[3:0]$10603 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10557 4'0000 + assign $6\src20__data_o$next[3:0]$10608 4'0000 case - assign $6\src20__data_o$next[3:0]$10557 $1\src20__data_o$next[3:0]$10552 + assign $6\src20__data_o$next[3:0]$10608 $1\src20__data_o$next[3:0]$10603 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10551 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10602 end - attribute \src "libresoc.v:173283.3-173312.6" - process $proc$libresoc.v:173283$10558 + attribute \src "libresoc.v:175379.3-175408.6" + process $proc$libresoc.v:175379$10609 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10559 $1\wr_detect$4[0:0]$10560 - attribute \src "libresoc.v:173284.5-173284.29" + assign $0\wr_detect$4[0:0]$10610 $1\wr_detect$4[0:0]$10611 + attribute \src "libresoc.v:175380.5-175380.29" switch \initial - attribute \src "libresoc.v:173284.9-173284.17" + attribute \src "libresoc.v:175380.9-175380.17" case 1'1 case end @@ -358106,49 +360977,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10560 $4\wr_detect$4[0:0]$10563 + assign $1\wr_detect$4[0:0]$10611 $4\wr_detect$4[0:0]$10614 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10561 1'1 + assign $2\wr_detect$4[0:0]$10612 1'1 case - assign $2\wr_detect$4[0:0]$10561 1'0 + assign $2\wr_detect$4[0:0]$10612 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10562 1'1 + assign $3\wr_detect$4[0:0]$10613 1'1 case - assign $3\wr_detect$4[0:0]$10562 $2\wr_detect$4[0:0]$10561 + assign $3\wr_detect$4[0:0]$10613 $2\wr_detect$4[0:0]$10612 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10563 1'1 + assign $4\wr_detect$4[0:0]$10614 1'1 case - assign $4\wr_detect$4[0:0]$10563 $3\wr_detect$4[0:0]$10562 + assign $4\wr_detect$4[0:0]$10614 $3\wr_detect$4[0:0]$10613 end case - assign $1\wr_detect$4[0:0]$10560 1'0 + assign $1\wr_detect$4[0:0]$10611 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10559 + update \wr_detect$4 $0\wr_detect$4[0:0]$10610 end - attribute \src "libresoc.v:173313.3-173352.6" - process $proc$libresoc.v:173313$10564 + attribute \src "libresoc.v:175409.3-175448.6" + process $proc$libresoc.v:175409$10615 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10565 $6\src30__data_o$next[3:0]$10571 - attribute \src "libresoc.v:173314.5-173314.29" + assign $0\src30__data_o$next[3:0]$10616 $6\src30__data_o$next[3:0]$10622 + attribute \src "libresoc.v:175410.5-175410.29" switch \initial - attribute \src "libresoc.v:173314.9-173314.17" + attribute \src "libresoc.v:175410.9-175410.17" case 1'1 case end @@ -358160,66 +361031,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10566 $5\src30__data_o$next[3:0]$10570 + assign $1\src30__data_o$next[3:0]$10617 $5\src30__data_o$next[3:0]$10621 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10567 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10618 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10567 4'0000 + assign $2\src30__data_o$next[3:0]$10618 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10568 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10619 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10568 $2\src30__data_o$next[3:0]$10567 + assign $3\src30__data_o$next[3:0]$10619 $2\src30__data_o$next[3:0]$10618 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10569 \w0__data_i + assign $4\src30__data_o$next[3:0]$10620 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10569 $3\src30__data_o$next[3:0]$10568 + assign $4\src30__data_o$next[3:0]$10620 $3\src30__data_o$next[3:0]$10619 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10570 \reg + assign $5\src30__data_o$next[3:0]$10621 \reg case - assign $5\src30__data_o$next[3:0]$10570 $4\src30__data_o$next[3:0]$10569 + assign $5\src30__data_o$next[3:0]$10621 $4\src30__data_o$next[3:0]$10620 end case - assign $1\src30__data_o$next[3:0]$10566 4'0000 + assign $1\src30__data_o$next[3:0]$10617 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10571 4'0000 + assign $6\src30__data_o$next[3:0]$10622 4'0000 case - assign $6\src30__data_o$next[3:0]$10571 $1\src30__data_o$next[3:0]$10566 + assign $6\src30__data_o$next[3:0]$10622 $1\src30__data_o$next[3:0]$10617 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10565 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10616 end - attribute \src "libresoc.v:173353.3-173382.6" - process $proc$libresoc.v:173353$10572 + attribute \src "libresoc.v:175449.3-175478.6" + process $proc$libresoc.v:175449$10623 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10573 $1\wr_detect$7[0:0]$10574 - attribute \src "libresoc.v:173354.5-173354.29" + assign $0\wr_detect$7[0:0]$10624 $1\wr_detect$7[0:0]$10625 + attribute \src "libresoc.v:175450.5-175450.29" switch \initial - attribute \src "libresoc.v:173354.9-173354.17" + attribute \src "libresoc.v:175450.9-175450.17" case 1'1 case end @@ -358231,49 +361102,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10574 $4\wr_detect$7[0:0]$10577 + assign $1\wr_detect$7[0:0]$10625 $4\wr_detect$7[0:0]$10628 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10575 1'1 + assign $2\wr_detect$7[0:0]$10626 1'1 case - assign $2\wr_detect$7[0:0]$10575 1'0 + assign $2\wr_detect$7[0:0]$10626 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10576 1'1 + assign $3\wr_detect$7[0:0]$10627 1'1 case - assign $3\wr_detect$7[0:0]$10576 $2\wr_detect$7[0:0]$10575 + assign $3\wr_detect$7[0:0]$10627 $2\wr_detect$7[0:0]$10626 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10577 1'1 + assign $4\wr_detect$7[0:0]$10628 1'1 case - assign $4\wr_detect$7[0:0]$10577 $3\wr_detect$7[0:0]$10576 + assign $4\wr_detect$7[0:0]$10628 $3\wr_detect$7[0:0]$10627 end case - assign $1\wr_detect$7[0:0]$10574 1'0 + assign $1\wr_detect$7[0:0]$10625 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10573 + update \wr_detect$7 $0\wr_detect$7[0:0]$10624 end - attribute \src "libresoc.v:173383.3-173422.6" - process $proc$libresoc.v:173383$10578 + attribute \src "libresoc.v:175479.3-175518.6" + process $proc$libresoc.v:175479$10629 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10579 $6\r0__data_o$next[3:0]$10585 - attribute \src "libresoc.v:173384.5-173384.29" + assign $0\r0__data_o$next[3:0]$10630 $6\r0__data_o$next[3:0]$10636 + attribute \src "libresoc.v:175480.5-175480.29" switch \initial - attribute \src "libresoc.v:173384.9-173384.17" + attribute \src "libresoc.v:175480.9-175480.17" case 1'1 case end @@ -358285,66 +361156,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10580 $5\r0__data_o$next[3:0]$10584 + assign $1\r0__data_o$next[3:0]$10631 $5\r0__data_o$next[3:0]$10635 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10581 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10632 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10581 4'0000 + assign $2\r0__data_o$next[3:0]$10632 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10582 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10633 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10582 $2\r0__data_o$next[3:0]$10581 + assign $3\r0__data_o$next[3:0]$10633 $2\r0__data_o$next[3:0]$10632 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10583 \w0__data_i + assign $4\r0__data_o$next[3:0]$10634 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10583 $3\r0__data_o$next[3:0]$10582 + assign $4\r0__data_o$next[3:0]$10634 $3\r0__data_o$next[3:0]$10633 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10584 \reg + assign $5\r0__data_o$next[3:0]$10635 \reg case - assign $5\r0__data_o$next[3:0]$10584 $4\r0__data_o$next[3:0]$10583 + assign $5\r0__data_o$next[3:0]$10635 $4\r0__data_o$next[3:0]$10634 end case - assign $1\r0__data_o$next[3:0]$10580 4'0000 + assign $1\r0__data_o$next[3:0]$10631 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10585 4'0000 + assign $6\r0__data_o$next[3:0]$10636 4'0000 case - assign $6\r0__data_o$next[3:0]$10585 $1\r0__data_o$next[3:0]$10580 + assign $6\r0__data_o$next[3:0]$10636 $1\r0__data_o$next[3:0]$10631 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10579 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10630 end - attribute \src "libresoc.v:173423.3-173452.6" - process $proc$libresoc.v:173423$10586 + attribute \src "libresoc.v:175519.3-175548.6" + process $proc$libresoc.v:175519$10637 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10587 $1\wr_detect$10[0:0]$10588 - attribute \src "libresoc.v:173424.5-173424.29" + assign $0\wr_detect$10[0:0]$10638 $1\wr_detect$10[0:0]$10639 + attribute \src "libresoc.v:175520.5-175520.29" switch \initial - attribute \src "libresoc.v:173424.9-173424.17" + attribute \src "libresoc.v:175520.9-175520.17" case 1'1 case end @@ -358356,49 +361227,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10588 $4\wr_detect$10[0:0]$10591 + assign $1\wr_detect$10[0:0]$10639 $4\wr_detect$10[0:0]$10642 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10589 1'1 + assign $2\wr_detect$10[0:0]$10640 1'1 case - assign $2\wr_detect$10[0:0]$10589 1'0 + assign $2\wr_detect$10[0:0]$10640 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10590 1'1 + assign $3\wr_detect$10[0:0]$10641 1'1 case - assign $3\wr_detect$10[0:0]$10590 $2\wr_detect$10[0:0]$10589 + assign $3\wr_detect$10[0:0]$10641 $2\wr_detect$10[0:0]$10640 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10591 1'1 + assign $4\wr_detect$10[0:0]$10642 1'1 case - assign $4\wr_detect$10[0:0]$10591 $3\wr_detect$10[0:0]$10590 + assign $4\wr_detect$10[0:0]$10642 $3\wr_detect$10[0:0]$10641 end case - assign $1\wr_detect$10[0:0]$10588 1'0 + assign $1\wr_detect$10[0:0]$10639 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10587 + update \wr_detect$10 $0\wr_detect$10[0:0]$10638 end - attribute \src "libresoc.v:173453.3-173492.6" - process $proc$libresoc.v:173453$10592 + attribute \src "libresoc.v:175549.3-175588.6" + process $proc$libresoc.v:175549$10643 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10593 $6\r20__data_o$next[3:0]$10599 - attribute \src "libresoc.v:173454.5-173454.29" + assign $0\r20__data_o$next[3:0]$10644 $6\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:175550.5-175550.29" switch \initial - attribute \src "libresoc.v:173454.9-173454.17" + attribute \src "libresoc.v:175550.9-175550.17" case 1'1 case end @@ -358410,66 +361281,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r20__data_o$next[3:0]$10594 $5\r20__data_o$next[3:0]$10598 + assign $1\r20__data_o$next[3:0]$10645 $5\r20__data_o$next[3:0]$10649 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r20__data_o$next[3:0]$10595 \dest10__data_i + assign $2\r20__data_o$next[3:0]$10646 \dest10__data_i case - assign $2\r20__data_o$next[3:0]$10595 4'0000 + assign $2\r20__data_o$next[3:0]$10646 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r20__data_o$next[3:0]$10596 \dest20__data_i + assign $3\r20__data_o$next[3:0]$10647 \dest20__data_i case - assign $3\r20__data_o$next[3:0]$10596 $2\r20__data_o$next[3:0]$10595 + assign $3\r20__data_o$next[3:0]$10647 $2\r20__data_o$next[3:0]$10646 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r20__data_o$next[3:0]$10597 \w0__data_i + assign $4\r20__data_o$next[3:0]$10648 \w0__data_i case - assign $4\r20__data_o$next[3:0]$10597 $3\r20__data_o$next[3:0]$10596 + assign $4\r20__data_o$next[3:0]$10648 $3\r20__data_o$next[3:0]$10647 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r20__data_o$next[3:0]$10598 \reg + assign $5\r20__data_o$next[3:0]$10649 \reg case - assign $5\r20__data_o$next[3:0]$10598 $4\r20__data_o$next[3:0]$10597 + assign $5\r20__data_o$next[3:0]$10649 $4\r20__data_o$next[3:0]$10648 end case - assign $1\r20__data_o$next[3:0]$10594 4'0000 + assign $1\r20__data_o$next[3:0]$10645 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r20__data_o$next[3:0]$10599 4'0000 + assign $6\r20__data_o$next[3:0]$10650 4'0000 case - assign $6\r20__data_o$next[3:0]$10599 $1\r20__data_o$next[3:0]$10594 + assign $6\r20__data_o$next[3:0]$10650 $1\r20__data_o$next[3:0]$10645 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10593 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10644 end - attribute \src "libresoc.v:173493.3-173522.6" - process $proc$libresoc.v:173493$10600 + attribute \src "libresoc.v:175589.3-175618.6" + process $proc$libresoc.v:175589$10651 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10601 $1\wr_detect$13[0:0]$10602 - attribute \src "libresoc.v:173494.5-173494.29" + assign $0\wr_detect$13[0:0]$10652 $1\wr_detect$13[0:0]$10653 + attribute \src "libresoc.v:175590.5-175590.29" switch \initial - attribute \src "libresoc.v:173494.9-173494.17" + attribute \src "libresoc.v:175590.9-175590.17" case 1'1 case end @@ -358481,205 +361352,205 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10602 $4\wr_detect$13[0:0]$10605 + assign $1\wr_detect$13[0:0]$10653 $4\wr_detect$13[0:0]$10656 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10603 1'1 + assign $2\wr_detect$13[0:0]$10654 1'1 case - assign $2\wr_detect$13[0:0]$10603 1'0 + assign $2\wr_detect$13[0:0]$10654 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10604 1'1 + assign $3\wr_detect$13[0:0]$10655 1'1 case - assign $3\wr_detect$13[0:0]$10604 $2\wr_detect$13[0:0]$10603 + assign $3\wr_detect$13[0:0]$10655 $2\wr_detect$13[0:0]$10654 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10605 1'1 + assign $4\wr_detect$13[0:0]$10656 1'1 case - assign $4\wr_detect$13[0:0]$10605 $3\wr_detect$13[0:0]$10604 + assign $4\wr_detect$13[0:0]$10656 $3\wr_detect$13[0:0]$10655 end case - assign $1\wr_detect$13[0:0]$10602 1'0 + assign $1\wr_detect$13[0:0]$10653 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10601 + update \wr_detect$13 $0\wr_detect$13[0:0]$10652 end - connect \$9 $not$libresoc.v:173129$10524_Y - connect \$12 $not$libresoc.v:173130$10525_Y - connect \$1 $not$libresoc.v:173131$10526_Y - connect \$3 $not$libresoc.v:173132$10527_Y - connect \$6 $not$libresoc.v:173133$10528_Y + connect \$9 $not$libresoc.v:175225$10575_Y + connect \$12 $not$libresoc.v:175226$10576_Y + connect \$1 $not$libresoc.v:175227$10577_Y + connect \$3 $not$libresoc.v:175228$10578_Y + connect \$6 $not$libresoc.v:175229$10579_Y end -attribute \src "libresoc.v:173527.1-173972.10" +attribute \src "libresoc.v:175623.1-176068.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:173528.7-173528.20" + attribute \src "libresoc.v:175624.7-175624.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173857.3-173902.6" - wire width 2 $0\r0__data_o$next[1:0]$10665 - attribute \src "libresoc.v:173603.3-173604.37" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $0\r0__data_o$next[1:0]$10716 + attribute \src "libresoc.v:175699.3-175700.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:173939.3-173971.6" - wire width 2 $0\reg$next[1:0]$10681 - attribute \src "libresoc.v:173601.3-173602.25" + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $0\reg$next[1:0]$10732 + attribute \src "libresoc.v:175697.3-175698.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:173611.3-173656.6" - wire width 2 $0\src10__data_o$next[1:0]$10623 - attribute \src "libresoc.v:173609.3-173610.43" + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $0\src10__data_o$next[1:0]$10674 + attribute \src "libresoc.v:175705.3-175706.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:173693.3-173738.6" - wire width 2 $0\src20__data_o$next[1:0]$10633 - attribute \src "libresoc.v:173607.3-173608.43" + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $0\src20__data_o$next[1:0]$10684 + attribute \src "libresoc.v:175703.3-175704.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:173775.3-173820.6" - wire width 2 $0\src30__data_o$next[1:0]$10649 - attribute \src "libresoc.v:173605.3-173606.43" + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $0\src30__data_o$next[1:0]$10700 + attribute \src "libresoc.v:175701.3-175702.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:173903.3-173938.6" - wire $0\wr_detect$10[0:0]$10674 - attribute \src "libresoc.v:173739.3-173774.6" - wire $0\wr_detect$4[0:0]$10642 - attribute \src "libresoc.v:173821.3-173856.6" - wire $0\wr_detect$7[0:0]$10658 - attribute \src "libresoc.v:173657.3-173692.6" + attribute \src "libresoc.v:175999.3-176034.6" + wire $0\wr_detect$10[0:0]$10725 + attribute \src "libresoc.v:175835.3-175870.6" + wire $0\wr_detect$4[0:0]$10693 + attribute \src "libresoc.v:175917.3-175952.6" + wire $0\wr_detect$7[0:0]$10709 + attribute \src "libresoc.v:175753.3-175788.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:173857.3-173902.6" - wire width 2 $1\r0__data_o$next[1:0]$10666 - attribute \src "libresoc.v:173555.13-173555.30" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $1\r0__data_o$next[1:0]$10717 + attribute \src "libresoc.v:175651.13-175651.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:173939.3-173971.6" - wire width 2 $1\reg$next[1:0]$10682 - attribute \src "libresoc.v:173561.13-173561.25" + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $1\reg$next[1:0]$10733 + attribute \src "libresoc.v:175657.13-175657.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:173611.3-173656.6" - wire width 2 $1\src10__data_o$next[1:0]$10624 - attribute \src "libresoc.v:173566.13-173566.33" + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $1\src10__data_o$next[1:0]$10675 + attribute \src "libresoc.v:175662.13-175662.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:173693.3-173738.6" - wire width 2 $1\src20__data_o$next[1:0]$10634 - attribute \src "libresoc.v:173573.13-173573.33" + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $1\src20__data_o$next[1:0]$10685 + attribute \src "libresoc.v:175669.13-175669.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:173775.3-173820.6" - wire width 2 $1\src30__data_o$next[1:0]$10650 - attribute \src "libresoc.v:173580.13-173580.33" + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $1\src30__data_o$next[1:0]$10701 + attribute \src "libresoc.v:175676.13-175676.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:173903.3-173938.6" - wire $1\wr_detect$10[0:0]$10675 - attribute \src "libresoc.v:173739.3-173774.6" - wire $1\wr_detect$4[0:0]$10643 - attribute \src "libresoc.v:173821.3-173856.6" - wire $1\wr_detect$7[0:0]$10659 - attribute \src "libresoc.v:173657.3-173692.6" + attribute \src "libresoc.v:175999.3-176034.6" + wire $1\wr_detect$10[0:0]$10726 + attribute \src "libresoc.v:175835.3-175870.6" + wire $1\wr_detect$4[0:0]$10694 + attribute \src "libresoc.v:175917.3-175952.6" + wire $1\wr_detect$7[0:0]$10710 + attribute \src "libresoc.v:175753.3-175788.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:173857.3-173902.6" - wire width 2 $2\r0__data_o$next[1:0]$10667 - attribute \src "libresoc.v:173939.3-173971.6" - wire width 2 $2\reg$next[1:0]$10683 - attribute \src "libresoc.v:173611.3-173656.6" - wire width 2 $2\src10__data_o$next[1:0]$10625 - attribute \src "libresoc.v:173693.3-173738.6" - wire width 2 $2\src20__data_o$next[1:0]$10635 - attribute \src "libresoc.v:173775.3-173820.6" - wire width 2 $2\src30__data_o$next[1:0]$10651 - attribute \src "libresoc.v:173903.3-173938.6" - wire $2\wr_detect$10[0:0]$10676 - attribute \src "libresoc.v:173739.3-173774.6" - wire $2\wr_detect$4[0:0]$10644 - attribute \src "libresoc.v:173821.3-173856.6" - wire $2\wr_detect$7[0:0]$10660 - attribute \src "libresoc.v:173657.3-173692.6" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $2\r0__data_o$next[1:0]$10718 + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $2\reg$next[1:0]$10734 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $2\src10__data_o$next[1:0]$10676 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $2\src20__data_o$next[1:0]$10686 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $2\src30__data_o$next[1:0]$10702 + attribute \src "libresoc.v:175999.3-176034.6" + wire $2\wr_detect$10[0:0]$10727 + attribute \src "libresoc.v:175835.3-175870.6" + wire $2\wr_detect$4[0:0]$10695 + attribute \src "libresoc.v:175917.3-175952.6" + wire $2\wr_detect$7[0:0]$10711 + attribute \src "libresoc.v:175753.3-175788.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:173857.3-173902.6" - wire width 2 $3\r0__data_o$next[1:0]$10668 - attribute \src "libresoc.v:173939.3-173971.6" - wire width 2 $3\reg$next[1:0]$10684 - attribute \src "libresoc.v:173611.3-173656.6" - wire width 2 $3\src10__data_o$next[1:0]$10626 - attribute \src "libresoc.v:173693.3-173738.6" - wire width 2 $3\src20__data_o$next[1:0]$10636 - attribute \src "libresoc.v:173775.3-173820.6" - wire width 2 $3\src30__data_o$next[1:0]$10652 - attribute \src "libresoc.v:173903.3-173938.6" - wire $3\wr_detect$10[0:0]$10677 - attribute \src "libresoc.v:173739.3-173774.6" - wire $3\wr_detect$4[0:0]$10645 - attribute \src "libresoc.v:173821.3-173856.6" - wire $3\wr_detect$7[0:0]$10661 - attribute \src "libresoc.v:173657.3-173692.6" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $3\r0__data_o$next[1:0]$10719 + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $3\reg$next[1:0]$10735 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $3\src10__data_o$next[1:0]$10677 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $3\src20__data_o$next[1:0]$10687 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $3\src30__data_o$next[1:0]$10703 + attribute \src "libresoc.v:175999.3-176034.6" + wire $3\wr_detect$10[0:0]$10728 + attribute \src "libresoc.v:175835.3-175870.6" + wire $3\wr_detect$4[0:0]$10696 + attribute \src "libresoc.v:175917.3-175952.6" + wire $3\wr_detect$7[0:0]$10712 + attribute \src "libresoc.v:175753.3-175788.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:173857.3-173902.6" - wire width 2 $4\r0__data_o$next[1:0]$10669 - attribute \src "libresoc.v:173939.3-173971.6" - wire width 2 $4\reg$next[1:0]$10685 - attribute \src "libresoc.v:173611.3-173656.6" - wire width 2 $4\src10__data_o$next[1:0]$10627 - attribute \src "libresoc.v:173693.3-173738.6" - wire width 2 $4\src20__data_o$next[1:0]$10637 - attribute \src "libresoc.v:173775.3-173820.6" - wire width 2 $4\src30__data_o$next[1:0]$10653 - attribute \src "libresoc.v:173903.3-173938.6" - wire $4\wr_detect$10[0:0]$10678 - attribute \src "libresoc.v:173739.3-173774.6" - wire $4\wr_detect$4[0:0]$10646 - attribute \src "libresoc.v:173821.3-173856.6" - wire $4\wr_detect$7[0:0]$10662 - attribute \src "libresoc.v:173657.3-173692.6" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $4\r0__data_o$next[1:0]$10720 + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $4\reg$next[1:0]$10736 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $4\src10__data_o$next[1:0]$10678 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $4\src20__data_o$next[1:0]$10688 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $4\src30__data_o$next[1:0]$10704 + attribute \src "libresoc.v:175999.3-176034.6" + wire $4\wr_detect$10[0:0]$10729 + attribute \src "libresoc.v:175835.3-175870.6" + wire $4\wr_detect$4[0:0]$10697 + attribute \src "libresoc.v:175917.3-175952.6" + wire $4\wr_detect$7[0:0]$10713 + attribute \src "libresoc.v:175753.3-175788.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:173857.3-173902.6" - wire width 2 $5\r0__data_o$next[1:0]$10670 - attribute \src "libresoc.v:173939.3-173971.6" - wire width 2 $5\reg$next[1:0]$10686 - attribute \src "libresoc.v:173611.3-173656.6" - wire width 2 $5\src10__data_o$next[1:0]$10628 - attribute \src "libresoc.v:173693.3-173738.6" - wire width 2 $5\src20__data_o$next[1:0]$10638 - attribute \src "libresoc.v:173775.3-173820.6" - wire width 2 $5\src30__data_o$next[1:0]$10654 - attribute \src "libresoc.v:173903.3-173938.6" - wire $5\wr_detect$10[0:0]$10679 - attribute \src "libresoc.v:173739.3-173774.6" - wire $5\wr_detect$4[0:0]$10647 - attribute \src "libresoc.v:173821.3-173856.6" - wire $5\wr_detect$7[0:0]$10663 - attribute \src "libresoc.v:173657.3-173692.6" + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $5\r0__data_o$next[1:0]$10721 + attribute \src "libresoc.v:176035.3-176067.6" + wire width 2 $5\reg$next[1:0]$10737 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $5\src10__data_o$next[1:0]$10679 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $5\src20__data_o$next[1:0]$10689 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $5\src30__data_o$next[1:0]$10705 + attribute \src "libresoc.v:175999.3-176034.6" + wire $5\wr_detect$10[0:0]$10730 + attribute \src "libresoc.v:175835.3-175870.6" + wire $5\wr_detect$4[0:0]$10698 + attribute \src "libresoc.v:175917.3-175952.6" + wire $5\wr_detect$7[0:0]$10714 + attribute \src "libresoc.v:175753.3-175788.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:173857.3-173902.6" - wire width 2 $6\r0__data_o$next[1:0]$10671 - attribute \src "libresoc.v:173611.3-173656.6" - wire width 2 $6\src10__data_o$next[1:0]$10629 - attribute \src "libresoc.v:173693.3-173738.6" - wire width 2 $6\src20__data_o$next[1:0]$10639 - attribute \src "libresoc.v:173775.3-173820.6" - wire width 2 $6\src30__data_o$next[1:0]$10655 - attribute \src "libresoc.v:173857.3-173902.6" - wire width 2 $7\r0__data_o$next[1:0]$10672 - attribute \src "libresoc.v:173611.3-173656.6" - wire width 2 $7\src10__data_o$next[1:0]$10630 - attribute \src "libresoc.v:173693.3-173738.6" - wire width 2 $7\src20__data_o$next[1:0]$10640 - attribute \src "libresoc.v:173775.3-173820.6" - wire width 2 $7\src30__data_o$next[1:0]$10656 - attribute \src "libresoc.v:173597.17-173597.104" - wire $not$libresoc.v:173597$10613_Y - attribute \src "libresoc.v:173598.17-173598.100" - wire $not$libresoc.v:173598$10614_Y - attribute \src "libresoc.v:173599.17-173599.103" - wire $not$libresoc.v:173599$10615_Y - attribute \src "libresoc.v:173600.17-173600.103" - wire $not$libresoc.v:173600$10616_Y + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $6\r0__data_o$next[1:0]$10722 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $6\src10__data_o$next[1:0]$10680 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $6\src20__data_o$next[1:0]$10690 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $6\src30__data_o$next[1:0]$10706 + attribute \src "libresoc.v:175953.3-175998.6" + wire width 2 $7\r0__data_o$next[1:0]$10723 + attribute \src "libresoc.v:175707.3-175752.6" + wire width 2 $7\src10__data_o$next[1:0]$10681 + attribute \src "libresoc.v:175789.3-175834.6" + wire width 2 $7\src20__data_o$next[1:0]$10691 + attribute \src "libresoc.v:175871.3-175916.6" + wire width 2 $7\src30__data_o$next[1:0]$10707 + attribute \src "libresoc.v:175693.17-175693.104" + wire $not$libresoc.v:175693$10664_Y + attribute \src "libresoc.v:175694.17-175694.100" + wire $not$libresoc.v:175694$10665_Y + attribute \src "libresoc.v:175695.17-175695.103" + wire $not$libresoc.v:175695$10666_Y + attribute \src "libresoc.v:175696.17-175696.103" + wire $not$libresoc.v:175696$10667_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -358688,9 +361559,9 @@ module \reg_0$132 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i @@ -358704,7 +361575,7 @@ module \reg_0$132 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:173528.7-173528.15" + attribute \src "libresoc.v:175624.7-175624.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o @@ -358747,129 +361618,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173597$10613 + cell $not $not$libresoc.v:175693$10664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:173597$10613_Y + connect \Y $not$libresoc.v:175693$10664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173598$10614 + cell $not $not$libresoc.v:175694$10665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:173598$10614_Y + connect \Y $not$libresoc.v:175694$10665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173599$10615 + cell $not $not$libresoc.v:175695$10666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:173599$10615_Y + connect \Y $not$libresoc.v:175695$10666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:173600$10616 + cell $not $not$libresoc.v:175696$10667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:173600$10616_Y + connect \Y $not$libresoc.v:175696$10667_Y end - attribute \src "libresoc.v:173528.7-173528.20" - process $proc$libresoc.v:173528$10687 + attribute \src "libresoc.v:175624.7-175624.20" + process $proc$libresoc.v:175624$10738 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173555.13-173555.30" - process $proc$libresoc.v:173555$10688 + attribute \src "libresoc.v:175651.13-175651.30" + process $proc$libresoc.v:175651$10739 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:173561.13-173561.25" - process $proc$libresoc.v:173561$10689 + attribute \src "libresoc.v:175657.13-175657.25" + process $proc$libresoc.v:175657$10740 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:173566.13-173566.33" - process $proc$libresoc.v:173566$10690 + attribute \src "libresoc.v:175662.13-175662.33" + process $proc$libresoc.v:175662$10741 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:173573.13-173573.33" - process $proc$libresoc.v:173573$10691 + attribute \src "libresoc.v:175669.13-175669.33" + process $proc$libresoc.v:175669$10742 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:173580.13-173580.33" - process $proc$libresoc.v:173580$10692 + attribute \src "libresoc.v:175676.13-175676.33" + process $proc$libresoc.v:175676$10743 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:173601.3-173602.25" - process $proc$libresoc.v:173601$10617 + attribute \src "libresoc.v:175697.3-175698.25" + process $proc$libresoc.v:175697$10668 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:173603.3-173604.37" - process $proc$libresoc.v:173603$10618 + attribute \src "libresoc.v:175699.3-175700.37" + process $proc$libresoc.v:175699$10669 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:173605.3-173606.43" - process $proc$libresoc.v:173605$10619 + attribute \src "libresoc.v:175701.3-175702.43" + process $proc$libresoc.v:175701$10670 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:173607.3-173608.43" - process $proc$libresoc.v:173607$10620 + attribute \src "libresoc.v:175703.3-175704.43" + process $proc$libresoc.v:175703$10671 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:173609.3-173610.43" - process $proc$libresoc.v:173609$10621 + attribute \src "libresoc.v:175705.3-175706.43" + process $proc$libresoc.v:175705$10672 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:173611.3-173656.6" - process $proc$libresoc.v:173611$10622 + attribute \src "libresoc.v:175707.3-175752.6" + process $proc$libresoc.v:175707$10673 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$10623 $7\src10__data_o$next[1:0]$10630 - attribute \src "libresoc.v:173612.5-173612.29" + assign $0\src10__data_o$next[1:0]$10674 $7\src10__data_o$next[1:0]$10681 + attribute \src "libresoc.v:175708.5-175708.29" switch \initial - attribute \src "libresoc.v:173612.9-173612.17" + attribute \src "libresoc.v:175708.9-175708.17" case 1'1 case end @@ -358882,75 +361753,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$10624 $6\src10__data_o$next[1:0]$10629 + assign $1\src10__data_o$next[1:0]$10675 $6\src10__data_o$next[1:0]$10680 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$10625 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10676 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$10625 2'00 + assign $2\src10__data_o$next[1:0]$10676 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$10626 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10677 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$10626 $2\src10__data_o$next[1:0]$10625 + assign $3\src10__data_o$next[1:0]$10677 $2\src10__data_o$next[1:0]$10676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$10627 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10678 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$10627 $3\src10__data_o$next[1:0]$10626 + assign $4\src10__data_o$next[1:0]$10678 $3\src10__data_o$next[1:0]$10677 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$10628 \w0__data_i + assign $5\src10__data_o$next[1:0]$10679 \w0__data_i case - assign $5\src10__data_o$next[1:0]$10628 $4\src10__data_o$next[1:0]$10627 + assign $5\src10__data_o$next[1:0]$10679 $4\src10__data_o$next[1:0]$10678 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$10629 \reg + assign $6\src10__data_o$next[1:0]$10680 \reg case - assign $6\src10__data_o$next[1:0]$10629 $5\src10__data_o$next[1:0]$10628 + assign $6\src10__data_o$next[1:0]$10680 $5\src10__data_o$next[1:0]$10679 end case - assign $1\src10__data_o$next[1:0]$10624 2'00 + assign $1\src10__data_o$next[1:0]$10675 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$10630 2'00 + assign $7\src10__data_o$next[1:0]$10681 2'00 case - assign $7\src10__data_o$next[1:0]$10630 $1\src10__data_o$next[1:0]$10624 + assign $7\src10__data_o$next[1:0]$10681 $1\src10__data_o$next[1:0]$10675 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10623 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10674 end - attribute \src "libresoc.v:173657.3-173692.6" - process $proc$libresoc.v:173657$10631 + attribute \src "libresoc.v:175753.3-175788.6" + process $proc$libresoc.v:175753$10682 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:173658.5-173658.29" + attribute \src "libresoc.v:175754.5-175754.29" switch \initial - attribute \src "libresoc.v:173658.9-173658.17" + attribute \src "libresoc.v:175754.9-175754.17" case 1'1 case end @@ -359006,15 +361877,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:173693.3-173738.6" - process $proc$libresoc.v:173693$10632 + attribute \src "libresoc.v:175789.3-175834.6" + process $proc$libresoc.v:175789$10683 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$10633 $7\src20__data_o$next[1:0]$10640 - attribute \src "libresoc.v:173694.5-173694.29" + assign $0\src20__data_o$next[1:0]$10684 $7\src20__data_o$next[1:0]$10691 + attribute \src "libresoc.v:175790.5-175790.29" switch \initial - attribute \src "libresoc.v:173694.9-173694.17" + attribute \src "libresoc.v:175790.9-175790.17" case 1'1 case end @@ -359027,75 +361898,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$10634 $6\src20__data_o$next[1:0]$10639 + assign $1\src20__data_o$next[1:0]$10685 $6\src20__data_o$next[1:0]$10690 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$10635 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10686 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$10635 2'00 + assign $2\src20__data_o$next[1:0]$10686 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$10636 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10687 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$10636 $2\src20__data_o$next[1:0]$10635 + assign $3\src20__data_o$next[1:0]$10687 $2\src20__data_o$next[1:0]$10686 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$10637 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10688 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$10637 $3\src20__data_o$next[1:0]$10636 + assign $4\src20__data_o$next[1:0]$10688 $3\src20__data_o$next[1:0]$10687 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$10638 \w0__data_i + assign $5\src20__data_o$next[1:0]$10689 \w0__data_i case - assign $5\src20__data_o$next[1:0]$10638 $4\src20__data_o$next[1:0]$10637 + assign $5\src20__data_o$next[1:0]$10689 $4\src20__data_o$next[1:0]$10688 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$10639 \reg + assign $6\src20__data_o$next[1:0]$10690 \reg case - assign $6\src20__data_o$next[1:0]$10639 $5\src20__data_o$next[1:0]$10638 + assign $6\src20__data_o$next[1:0]$10690 $5\src20__data_o$next[1:0]$10689 end case - assign $1\src20__data_o$next[1:0]$10634 2'00 + assign $1\src20__data_o$next[1:0]$10685 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$10640 2'00 + assign $7\src20__data_o$next[1:0]$10691 2'00 case - assign $7\src20__data_o$next[1:0]$10640 $1\src20__data_o$next[1:0]$10634 + assign $7\src20__data_o$next[1:0]$10691 $1\src20__data_o$next[1:0]$10685 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10633 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10684 end - attribute \src "libresoc.v:173739.3-173774.6" - process $proc$libresoc.v:173739$10641 + attribute \src "libresoc.v:175835.3-175870.6" + process $proc$libresoc.v:175835$10692 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10642 $1\wr_detect$4[0:0]$10643 - attribute \src "libresoc.v:173740.5-173740.29" + assign $0\wr_detect$4[0:0]$10693 $1\wr_detect$4[0:0]$10694 + attribute \src "libresoc.v:175836.5-175836.29" switch \initial - attribute \src "libresoc.v:173740.9-173740.17" + attribute \src "libresoc.v:175836.9-175836.17" case 1'1 case end @@ -359108,58 +361979,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10643 $5\wr_detect$4[0:0]$10647 + assign $1\wr_detect$4[0:0]$10694 $5\wr_detect$4[0:0]$10698 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10644 1'1 + assign $2\wr_detect$4[0:0]$10695 1'1 case - assign $2\wr_detect$4[0:0]$10644 1'0 + assign $2\wr_detect$4[0:0]$10695 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10645 1'1 + assign $3\wr_detect$4[0:0]$10696 1'1 case - assign $3\wr_detect$4[0:0]$10645 $2\wr_detect$4[0:0]$10644 + assign $3\wr_detect$4[0:0]$10696 $2\wr_detect$4[0:0]$10695 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10646 1'1 + assign $4\wr_detect$4[0:0]$10697 1'1 case - assign $4\wr_detect$4[0:0]$10646 $3\wr_detect$4[0:0]$10645 + assign $4\wr_detect$4[0:0]$10697 $3\wr_detect$4[0:0]$10696 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10647 1'1 + assign $5\wr_detect$4[0:0]$10698 1'1 case - assign $5\wr_detect$4[0:0]$10647 $4\wr_detect$4[0:0]$10646 + assign $5\wr_detect$4[0:0]$10698 $4\wr_detect$4[0:0]$10697 end case - assign $1\wr_detect$4[0:0]$10643 1'0 + assign $1\wr_detect$4[0:0]$10694 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10642 + update \wr_detect$4 $0\wr_detect$4[0:0]$10693 end - attribute \src "libresoc.v:173775.3-173820.6" - process $proc$libresoc.v:173775$10648 + attribute \src "libresoc.v:175871.3-175916.6" + process $proc$libresoc.v:175871$10699 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$10649 $7\src30__data_o$next[1:0]$10656 - attribute \src "libresoc.v:173776.5-173776.29" + assign $0\src30__data_o$next[1:0]$10700 $7\src30__data_o$next[1:0]$10707 + attribute \src "libresoc.v:175872.5-175872.29" switch \initial - attribute \src "libresoc.v:173776.9-173776.17" + attribute \src "libresoc.v:175872.9-175872.17" case 1'1 case end @@ -359172,75 +362043,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$10650 $6\src30__data_o$next[1:0]$10655 + assign $1\src30__data_o$next[1:0]$10701 $6\src30__data_o$next[1:0]$10706 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$10651 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10702 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$10651 2'00 + assign $2\src30__data_o$next[1:0]$10702 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$10652 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10703 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$10652 $2\src30__data_o$next[1:0]$10651 + assign $3\src30__data_o$next[1:0]$10703 $2\src30__data_o$next[1:0]$10702 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$10653 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10704 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$10653 $3\src30__data_o$next[1:0]$10652 + assign $4\src30__data_o$next[1:0]$10704 $3\src30__data_o$next[1:0]$10703 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$10654 \w0__data_i + assign $5\src30__data_o$next[1:0]$10705 \w0__data_i case - assign $5\src30__data_o$next[1:0]$10654 $4\src30__data_o$next[1:0]$10653 + assign $5\src30__data_o$next[1:0]$10705 $4\src30__data_o$next[1:0]$10704 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$10655 \reg + assign $6\src30__data_o$next[1:0]$10706 \reg case - assign $6\src30__data_o$next[1:0]$10655 $5\src30__data_o$next[1:0]$10654 + assign $6\src30__data_o$next[1:0]$10706 $5\src30__data_o$next[1:0]$10705 end case - assign $1\src30__data_o$next[1:0]$10650 2'00 + assign $1\src30__data_o$next[1:0]$10701 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$10656 2'00 + assign $7\src30__data_o$next[1:0]$10707 2'00 case - assign $7\src30__data_o$next[1:0]$10656 $1\src30__data_o$next[1:0]$10650 + assign $7\src30__data_o$next[1:0]$10707 $1\src30__data_o$next[1:0]$10701 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10649 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10700 end - attribute \src "libresoc.v:173821.3-173856.6" - process $proc$libresoc.v:173821$10657 + attribute \src "libresoc.v:175917.3-175952.6" + process $proc$libresoc.v:175917$10708 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10658 $1\wr_detect$7[0:0]$10659 - attribute \src "libresoc.v:173822.5-173822.29" + assign $0\wr_detect$7[0:0]$10709 $1\wr_detect$7[0:0]$10710 + attribute \src "libresoc.v:175918.5-175918.29" switch \initial - attribute \src "libresoc.v:173822.9-173822.17" + attribute \src "libresoc.v:175918.9-175918.17" case 1'1 case end @@ -359253,58 +362124,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10659 $5\wr_detect$7[0:0]$10663 + assign $1\wr_detect$7[0:0]$10710 $5\wr_detect$7[0:0]$10714 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10660 1'1 + assign $2\wr_detect$7[0:0]$10711 1'1 case - assign $2\wr_detect$7[0:0]$10660 1'0 + assign $2\wr_detect$7[0:0]$10711 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10661 1'1 + assign $3\wr_detect$7[0:0]$10712 1'1 case - assign $3\wr_detect$7[0:0]$10661 $2\wr_detect$7[0:0]$10660 + assign $3\wr_detect$7[0:0]$10712 $2\wr_detect$7[0:0]$10711 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10662 1'1 + assign $4\wr_detect$7[0:0]$10713 1'1 case - assign $4\wr_detect$7[0:0]$10662 $3\wr_detect$7[0:0]$10661 + assign $4\wr_detect$7[0:0]$10713 $3\wr_detect$7[0:0]$10712 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10663 1'1 + assign $5\wr_detect$7[0:0]$10714 1'1 case - assign $5\wr_detect$7[0:0]$10663 $4\wr_detect$7[0:0]$10662 + assign $5\wr_detect$7[0:0]$10714 $4\wr_detect$7[0:0]$10713 end case - assign $1\wr_detect$7[0:0]$10659 1'0 + assign $1\wr_detect$7[0:0]$10710 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10658 + update \wr_detect$7 $0\wr_detect$7[0:0]$10709 end - attribute \src "libresoc.v:173857.3-173902.6" - process $proc$libresoc.v:173857$10664 + attribute \src "libresoc.v:175953.3-175998.6" + process $proc$libresoc.v:175953$10715 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$10665 $7\r0__data_o$next[1:0]$10672 - attribute \src "libresoc.v:173858.5-173858.29" + assign $0\r0__data_o$next[1:0]$10716 $7\r0__data_o$next[1:0]$10723 + attribute \src "libresoc.v:175954.5-175954.29" switch \initial - attribute \src "libresoc.v:173858.9-173858.17" + attribute \src "libresoc.v:175954.9-175954.17" case 1'1 case end @@ -359317,75 +362188,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$10666 $6\r0__data_o$next[1:0]$10671 + assign $1\r0__data_o$next[1:0]$10717 $6\r0__data_o$next[1:0]$10722 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$10667 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10718 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$10667 2'00 + assign $2\r0__data_o$next[1:0]$10718 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$10668 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10719 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$10668 $2\r0__data_o$next[1:0]$10667 + assign $3\r0__data_o$next[1:0]$10719 $2\r0__data_o$next[1:0]$10718 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$10669 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10720 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$10669 $3\r0__data_o$next[1:0]$10668 + assign $4\r0__data_o$next[1:0]$10720 $3\r0__data_o$next[1:0]$10719 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$10670 \w0__data_i + assign $5\r0__data_o$next[1:0]$10721 \w0__data_i case - assign $5\r0__data_o$next[1:0]$10670 $4\r0__data_o$next[1:0]$10669 + assign $5\r0__data_o$next[1:0]$10721 $4\r0__data_o$next[1:0]$10720 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$10671 \reg + assign $6\r0__data_o$next[1:0]$10722 \reg case - assign $6\r0__data_o$next[1:0]$10671 $5\r0__data_o$next[1:0]$10670 + assign $6\r0__data_o$next[1:0]$10722 $5\r0__data_o$next[1:0]$10721 end case - assign $1\r0__data_o$next[1:0]$10666 2'00 + assign $1\r0__data_o$next[1:0]$10717 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$10672 2'00 + assign $7\r0__data_o$next[1:0]$10723 2'00 case - assign $7\r0__data_o$next[1:0]$10672 $1\r0__data_o$next[1:0]$10666 + assign $7\r0__data_o$next[1:0]$10723 $1\r0__data_o$next[1:0]$10717 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10665 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10716 end - attribute \src "libresoc.v:173903.3-173938.6" - process $proc$libresoc.v:173903$10673 + attribute \src "libresoc.v:175999.3-176034.6" + process $proc$libresoc.v:175999$10724 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10674 $1\wr_detect$10[0:0]$10675 - attribute \src "libresoc.v:173904.5-173904.29" + assign $0\wr_detect$10[0:0]$10725 $1\wr_detect$10[0:0]$10726 + attribute \src "libresoc.v:176000.5-176000.29" switch \initial - attribute \src "libresoc.v:173904.9-173904.17" + attribute \src "libresoc.v:176000.9-176000.17" case 1'1 case end @@ -359398,61 +362269,61 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10675 $5\wr_detect$10[0:0]$10679 + assign $1\wr_detect$10[0:0]$10726 $5\wr_detect$10[0:0]$10730 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10676 1'1 + assign $2\wr_detect$10[0:0]$10727 1'1 case - assign $2\wr_detect$10[0:0]$10676 1'0 + assign $2\wr_detect$10[0:0]$10727 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10677 1'1 + assign $3\wr_detect$10[0:0]$10728 1'1 case - assign $3\wr_detect$10[0:0]$10677 $2\wr_detect$10[0:0]$10676 + assign $3\wr_detect$10[0:0]$10728 $2\wr_detect$10[0:0]$10727 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10678 1'1 + assign $4\wr_detect$10[0:0]$10729 1'1 case - assign $4\wr_detect$10[0:0]$10678 $3\wr_detect$10[0:0]$10677 + assign $4\wr_detect$10[0:0]$10729 $3\wr_detect$10[0:0]$10728 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10679 1'1 + assign $5\wr_detect$10[0:0]$10730 1'1 case - assign $5\wr_detect$10[0:0]$10679 $4\wr_detect$10[0:0]$10678 + assign $5\wr_detect$10[0:0]$10730 $4\wr_detect$10[0:0]$10729 end case - assign $1\wr_detect$10[0:0]$10675 1'0 + assign $1\wr_detect$10[0:0]$10726 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10674 + update \wr_detect$10 $0\wr_detect$10[0:0]$10725 end - attribute \src "libresoc.v:173939.3-173971.6" - process $proc$libresoc.v:173939$10680 + attribute \src "libresoc.v:176035.3-176067.6" + process $proc$libresoc.v:176035$10731 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10681 $5\reg$next[1:0]$10686 - attribute \src "libresoc.v:173940.5-173940.29" + assign $0\reg$next[1:0]$10732 $5\reg$next[1:0]$10737 + attribute \src "libresoc.v:176036.5-176036.29" switch \initial - attribute \src "libresoc.v:173940.9-173940.17" + attribute \src "libresoc.v:176036.9-176036.17" case 1'1 case end @@ -359461,179 +362332,179 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10682 \dest10__data_i + assign $1\reg$next[1:0]$10733 \dest10__data_i case - assign $1\reg$next[1:0]$10682 \reg + assign $1\reg$next[1:0]$10733 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10683 \dest20__data_i + assign $2\reg$next[1:0]$10734 \dest20__data_i case - assign $2\reg$next[1:0]$10683 $1\reg$next[1:0]$10682 + assign $2\reg$next[1:0]$10734 $1\reg$next[1:0]$10733 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10684 \dest30__data_i + assign $3\reg$next[1:0]$10735 \dest30__data_i case - assign $3\reg$next[1:0]$10684 $2\reg$next[1:0]$10683 + assign $3\reg$next[1:0]$10735 $2\reg$next[1:0]$10734 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10685 \w0__data_i + assign $4\reg$next[1:0]$10736 \w0__data_i case - assign $4\reg$next[1:0]$10685 $3\reg$next[1:0]$10684 + assign $4\reg$next[1:0]$10736 $3\reg$next[1:0]$10735 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10686 2'00 + assign $5\reg$next[1:0]$10737 2'00 case - assign $5\reg$next[1:0]$10686 $4\reg$next[1:0]$10685 + assign $5\reg$next[1:0]$10737 $4\reg$next[1:0]$10736 end sync always - update \reg$next $0\reg$next[1:0]$10681 + update \reg$next $0\reg$next[1:0]$10732 end - connect \$9 $not$libresoc.v:173597$10613_Y - connect \$1 $not$libresoc.v:173598$10614_Y - connect \$3 $not$libresoc.v:173599$10615_Y - connect \$6 $not$libresoc.v:173600$10616_Y + connect \$9 $not$libresoc.v:175693$10664_Y + connect \$1 $not$libresoc.v:175694$10665_Y + connect \$3 $not$libresoc.v:175695$10666_Y + connect \$6 $not$libresoc.v:175696$10667_Y end -attribute \src "libresoc.v:173976.1-174325.10" +attribute \src "libresoc.v:176072.1-176421.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:174046.3-174091.6" - wire width 64 $0\cia0__data_o$next[63:0]$10701 - attribute \src "libresoc.v:174044.3-174045.41" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $0\cia0__data_o$next[63:0]$10752 + attribute \src "libresoc.v:176140.3-176141.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:173977.7-173977.20" + attribute \src "libresoc.v:176073.7-176073.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174128.3-174173.6" - wire width 64 $0\msr0__data_o$next[63:0]$10711 - attribute \src "libresoc.v:174042.3-174043.41" + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $0\msr0__data_o$next[63:0]$10762 + attribute \src "libresoc.v:176138.3-176139.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:174292.3-174324.6" - wire width 64 $0\reg$next[63:0]$10743 - attribute \src "libresoc.v:174038.3-174039.25" + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $0\reg$next[63:0]$10794 + attribute \src "libresoc.v:176134.3-176135.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:174210.3-174255.6" - wire width 64 $0\sv0__data_o$next[63:0]$10727 - attribute \src "libresoc.v:174040.3-174041.39" + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $0\sv0__data_o$next[63:0]$10778 + attribute \src "libresoc.v:176136.3-176137.39" wire width 64 $0\sv0__data_o[63:0] - attribute \src "libresoc.v:174174.3-174209.6" - wire $0\wr_detect$4[0:0]$10720 - attribute \src "libresoc.v:174256.3-174291.6" - wire $0\wr_detect$7[0:0]$10736 - attribute \src "libresoc.v:174092.3-174127.6" + attribute \src "libresoc.v:176270.3-176305.6" + wire $0\wr_detect$4[0:0]$10771 + attribute \src "libresoc.v:176352.3-176387.6" + wire $0\wr_detect$7[0:0]$10787 + attribute \src "libresoc.v:176188.3-176223.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:174046.3-174091.6" - wire width 64 $1\cia0__data_o$next[63:0]$10702 - attribute \src "libresoc.v:173986.14-173986.49" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $1\cia0__data_o$next[63:0]$10753 + attribute \src "libresoc.v:176082.14-176082.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:174128.3-174173.6" - wire width 64 $1\msr0__data_o$next[63:0]$10712 - attribute \src "libresoc.v:174003.14-174003.49" + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $1\msr0__data_o$next[63:0]$10763 + attribute \src "libresoc.v:176099.14-176099.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:174292.3-174324.6" - wire width 64 $1\reg$next[63:0]$10744 - attribute \src "libresoc.v:174015.14-174015.42" + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $1\reg$next[63:0]$10795 + attribute \src "libresoc.v:176111.14-176111.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:174210.3-174255.6" - wire width 64 $1\sv0__data_o$next[63:0]$10728 - attribute \src "libresoc.v:174022.14-174022.48" + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $1\sv0__data_o$next[63:0]$10779 + attribute \src "libresoc.v:176118.14-176118.48" wire width 64 $1\sv0__data_o[63:0] - attribute \src "libresoc.v:174174.3-174209.6" - wire $1\wr_detect$4[0:0]$10721 - attribute \src "libresoc.v:174256.3-174291.6" - wire $1\wr_detect$7[0:0]$10737 - attribute \src "libresoc.v:174092.3-174127.6" + attribute \src "libresoc.v:176270.3-176305.6" + wire $1\wr_detect$4[0:0]$10772 + attribute \src "libresoc.v:176352.3-176387.6" + wire $1\wr_detect$7[0:0]$10788 + attribute \src "libresoc.v:176188.3-176223.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:174046.3-174091.6" - wire width 64 $2\cia0__data_o$next[63:0]$10703 - attribute \src "libresoc.v:174128.3-174173.6" - wire width 64 $2\msr0__data_o$next[63:0]$10713 - attribute \src "libresoc.v:174292.3-174324.6" - wire width 64 $2\reg$next[63:0]$10745 - attribute \src "libresoc.v:174210.3-174255.6" - wire width 64 $2\sv0__data_o$next[63:0]$10729 - attribute \src "libresoc.v:174174.3-174209.6" - wire $2\wr_detect$4[0:0]$10722 - attribute \src "libresoc.v:174256.3-174291.6" - wire $2\wr_detect$7[0:0]$10738 - attribute \src "libresoc.v:174092.3-174127.6" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $2\cia0__data_o$next[63:0]$10754 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $2\msr0__data_o$next[63:0]$10764 + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $2\reg$next[63:0]$10796 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $2\sv0__data_o$next[63:0]$10780 + attribute \src "libresoc.v:176270.3-176305.6" + wire $2\wr_detect$4[0:0]$10773 + attribute \src "libresoc.v:176352.3-176387.6" + wire $2\wr_detect$7[0:0]$10789 + attribute \src "libresoc.v:176188.3-176223.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:174046.3-174091.6" - wire width 64 $3\cia0__data_o$next[63:0]$10704 - attribute \src "libresoc.v:174128.3-174173.6" - wire width 64 $3\msr0__data_o$next[63:0]$10714 - attribute \src "libresoc.v:174292.3-174324.6" - wire width 64 $3\reg$next[63:0]$10746 - attribute \src "libresoc.v:174210.3-174255.6" - wire width 64 $3\sv0__data_o$next[63:0]$10730 - attribute \src "libresoc.v:174174.3-174209.6" - wire $3\wr_detect$4[0:0]$10723 - attribute \src "libresoc.v:174256.3-174291.6" - wire $3\wr_detect$7[0:0]$10739 - attribute \src "libresoc.v:174092.3-174127.6" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $3\cia0__data_o$next[63:0]$10755 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $3\msr0__data_o$next[63:0]$10765 + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $3\reg$next[63:0]$10797 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $3\sv0__data_o$next[63:0]$10781 + attribute \src "libresoc.v:176270.3-176305.6" + wire $3\wr_detect$4[0:0]$10774 + attribute \src "libresoc.v:176352.3-176387.6" + wire $3\wr_detect$7[0:0]$10790 + attribute \src "libresoc.v:176188.3-176223.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:174046.3-174091.6" - wire width 64 $4\cia0__data_o$next[63:0]$10705 - attribute \src "libresoc.v:174128.3-174173.6" - wire width 64 $4\msr0__data_o$next[63:0]$10715 - attribute \src "libresoc.v:174292.3-174324.6" - wire width 64 $4\reg$next[63:0]$10747 - attribute \src "libresoc.v:174210.3-174255.6" - wire width 64 $4\sv0__data_o$next[63:0]$10731 - attribute \src "libresoc.v:174174.3-174209.6" - wire $4\wr_detect$4[0:0]$10724 - attribute \src "libresoc.v:174256.3-174291.6" - wire $4\wr_detect$7[0:0]$10740 - attribute \src "libresoc.v:174092.3-174127.6" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $4\cia0__data_o$next[63:0]$10756 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $4\msr0__data_o$next[63:0]$10766 + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $4\reg$next[63:0]$10798 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $4\sv0__data_o$next[63:0]$10782 + attribute \src "libresoc.v:176270.3-176305.6" + wire $4\wr_detect$4[0:0]$10775 + attribute \src "libresoc.v:176352.3-176387.6" + wire $4\wr_detect$7[0:0]$10791 + attribute \src "libresoc.v:176188.3-176223.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:174046.3-174091.6" - wire width 64 $5\cia0__data_o$next[63:0]$10706 - attribute \src "libresoc.v:174128.3-174173.6" - wire width 64 $5\msr0__data_o$next[63:0]$10716 - attribute \src "libresoc.v:174292.3-174324.6" - wire width 64 $5\reg$next[63:0]$10748 - attribute \src "libresoc.v:174210.3-174255.6" - wire width 64 $5\sv0__data_o$next[63:0]$10732 - attribute \src "libresoc.v:174174.3-174209.6" - wire $5\wr_detect$4[0:0]$10725 - attribute \src "libresoc.v:174256.3-174291.6" - wire $5\wr_detect$7[0:0]$10741 - attribute \src "libresoc.v:174092.3-174127.6" + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $5\cia0__data_o$next[63:0]$10757 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $5\msr0__data_o$next[63:0]$10767 + attribute \src "libresoc.v:176388.3-176420.6" + wire width 64 $5\reg$next[63:0]$10799 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $5\sv0__data_o$next[63:0]$10783 + attribute \src "libresoc.v:176270.3-176305.6" + wire $5\wr_detect$4[0:0]$10776 + attribute \src "libresoc.v:176352.3-176387.6" + wire $5\wr_detect$7[0:0]$10792 + attribute \src "libresoc.v:176188.3-176223.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:174046.3-174091.6" - wire width 64 $6\cia0__data_o$next[63:0]$10707 - attribute \src "libresoc.v:174128.3-174173.6" - wire width 64 $6\msr0__data_o$next[63:0]$10717 - attribute \src "libresoc.v:174210.3-174255.6" - wire width 64 $6\sv0__data_o$next[63:0]$10733 - attribute \src "libresoc.v:174046.3-174091.6" - wire width 64 $7\cia0__data_o$next[63:0]$10708 - attribute \src "libresoc.v:174128.3-174173.6" - wire width 64 $7\msr0__data_o$next[63:0]$10718 - attribute \src "libresoc.v:174210.3-174255.6" - wire width 64 $7\sv0__data_o$next[63:0]$10734 - attribute \src "libresoc.v:174035.17-174035.100" - wire $not$libresoc.v:174035$10693_Y - attribute \src "libresoc.v:174036.17-174036.103" - wire $not$libresoc.v:174036$10694_Y - attribute \src "libresoc.v:174037.17-174037.103" - wire $not$libresoc.v:174037$10695_Y + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $6\cia0__data_o$next[63:0]$10758 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $6\msr0__data_o$next[63:0]$10768 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $6\sv0__data_o$next[63:0]$10784 + attribute \src "libresoc.v:176142.3-176187.6" + wire width 64 $7\cia0__data_o$next[63:0]$10759 + attribute \src "libresoc.v:176224.3-176269.6" + wire width 64 $7\msr0__data_o$next[63:0]$10769 + attribute \src "libresoc.v:176306.3-176351.6" + wire width 64 $7\sv0__data_o$next[63:0]$10785 + attribute \src "libresoc.v:176131.17-176131.100" + wire $not$libresoc.v:176131$10744_Y + attribute \src "libresoc.v:176132.17-176132.103" + wire $not$libresoc.v:176132$10745_Y + attribute \src "libresoc.v:176133.17-176133.103" + wire $not$libresoc.v:176133$10746_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -359646,15 +362517,15 @@ module \reg_0$135 wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen - attribute \src "libresoc.v:173977.7-173977.15" + attribute \src "libresoc.v:176073.7-176073.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i @@ -359691,106 +362562,106 @@ module \reg_0$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174035$10693 + cell $not $not$libresoc.v:176131$10744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:174035$10693_Y + connect \Y $not$libresoc.v:176131$10744_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174036$10694 + cell $not $not$libresoc.v:176132$10745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:174036$10694_Y + connect \Y $not$libresoc.v:176132$10745_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174037$10695 + cell $not $not$libresoc.v:176133$10746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:174037$10695_Y + connect \Y $not$libresoc.v:176133$10746_Y end - attribute \src "libresoc.v:173977.7-173977.20" - process $proc$libresoc.v:173977$10749 + attribute \src "libresoc.v:176073.7-176073.20" + process $proc$libresoc.v:176073$10800 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173986.14-173986.49" - process $proc$libresoc.v:173986$10750 + attribute \src "libresoc.v:176082.14-176082.49" + process $proc$libresoc.v:176082$10801 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:174003.14-174003.49" - process $proc$libresoc.v:174003$10751 + attribute \src "libresoc.v:176099.14-176099.49" + process $proc$libresoc.v:176099$10802 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:174015.14-174015.42" - process $proc$libresoc.v:174015$10752 + attribute \src "libresoc.v:176111.14-176111.42" + process $proc$libresoc.v:176111$10803 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:174022.14-174022.48" - process $proc$libresoc.v:174022$10753 + attribute \src "libresoc.v:176118.14-176118.48" + process $proc$libresoc.v:176118$10804 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end - attribute \src "libresoc.v:174038.3-174039.25" - process $proc$libresoc.v:174038$10696 + attribute \src "libresoc.v:176134.3-176135.25" + process $proc$libresoc.v:176134$10747 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:174040.3-174041.39" - process $proc$libresoc.v:174040$10697 + attribute \src "libresoc.v:176136.3-176137.39" + process $proc$libresoc.v:176136$10748 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end - attribute \src "libresoc.v:174042.3-174043.41" - process $proc$libresoc.v:174042$10698 + attribute \src "libresoc.v:176138.3-176139.41" + process $proc$libresoc.v:176138$10749 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:174044.3-174045.41" - process $proc$libresoc.v:174044$10699 + attribute \src "libresoc.v:176140.3-176141.41" + process $proc$libresoc.v:176140$10750 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:174046.3-174091.6" - process $proc$libresoc.v:174046$10700 + attribute \src "libresoc.v:176142.3-176187.6" + process $proc$libresoc.v:176142$10751 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10701 $7\cia0__data_o$next[63:0]$10708 - attribute \src "libresoc.v:174047.5-174047.29" + assign $0\cia0__data_o$next[63:0]$10752 $7\cia0__data_o$next[63:0]$10759 + attribute \src "libresoc.v:176143.5-176143.29" switch \initial - attribute \src "libresoc.v:174047.9-174047.17" + attribute \src "libresoc.v:176143.9-176143.17" case 1'1 case end @@ -359803,75 +362674,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$10702 $6\cia0__data_o$next[63:0]$10707 + assign $1\cia0__data_o$next[63:0]$10753 $6\cia0__data_o$next[63:0]$10758 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$10703 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10754 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$10703 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10754 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$10704 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10755 \msr0__data_i case - assign $3\cia0__data_o$next[63:0]$10704 $2\cia0__data_o$next[63:0]$10703 + assign $3\cia0__data_o$next[63:0]$10755 $2\cia0__data_o$next[63:0]$10754 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$10705 \sv0__data_i + assign $4\cia0__data_o$next[63:0]$10756 \sv0__data_i case - assign $4\cia0__data_o$next[63:0]$10705 $3\cia0__data_o$next[63:0]$10704 + assign $4\cia0__data_o$next[63:0]$10756 $3\cia0__data_o$next[63:0]$10755 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$10706 \d_wr10__data_i + assign $5\cia0__data_o$next[63:0]$10757 \d_wr10__data_i case - assign $5\cia0__data_o$next[63:0]$10706 $4\cia0__data_o$next[63:0]$10705 + assign $5\cia0__data_o$next[63:0]$10757 $4\cia0__data_o$next[63:0]$10756 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$10707 \reg + assign $6\cia0__data_o$next[63:0]$10758 \reg case - assign $6\cia0__data_o$next[63:0]$10707 $5\cia0__data_o$next[63:0]$10706 + assign $6\cia0__data_o$next[63:0]$10758 $5\cia0__data_o$next[63:0]$10757 end case - assign $1\cia0__data_o$next[63:0]$10702 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10753 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia0__data_o$next[63:0]$10708 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia0__data_o$next[63:0]$10708 $1\cia0__data_o$next[63:0]$10702 + assign $7\cia0__data_o$next[63:0]$10759 $1\cia0__data_o$next[63:0]$10753 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10701 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10752 end - attribute \src "libresoc.v:174092.3-174127.6" - process $proc$libresoc.v:174092$10709 + attribute \src "libresoc.v:176188.3-176223.6" + process $proc$libresoc.v:176188$10760 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:174093.5-174093.29" + attribute \src "libresoc.v:176189.5-176189.29" switch \initial - attribute \src "libresoc.v:174093.9-174093.17" + attribute \src "libresoc.v:176189.9-176189.17" case 1'1 case end @@ -359927,15 +362798,15 @@ module \reg_0$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:174128.3-174173.6" - process $proc$libresoc.v:174128$10710 + attribute \src "libresoc.v:176224.3-176269.6" + process $proc$libresoc.v:176224$10761 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10711 $7\msr0__data_o$next[63:0]$10718 - attribute \src "libresoc.v:174129.5-174129.29" + assign $0\msr0__data_o$next[63:0]$10762 $7\msr0__data_o$next[63:0]$10769 + attribute \src "libresoc.v:176225.5-176225.29" switch \initial - attribute \src "libresoc.v:174129.9-174129.17" + attribute \src "libresoc.v:176225.9-176225.17" case 1'1 case end @@ -359948,75 +362819,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$10712 $6\msr0__data_o$next[63:0]$10717 + assign $1\msr0__data_o$next[63:0]$10763 $6\msr0__data_o$next[63:0]$10768 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$10713 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10764 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$10713 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10764 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$10714 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10765 \msr0__data_i case - assign $3\msr0__data_o$next[63:0]$10714 $2\msr0__data_o$next[63:0]$10713 + assign $3\msr0__data_o$next[63:0]$10765 $2\msr0__data_o$next[63:0]$10764 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$10715 \sv0__data_i + assign $4\msr0__data_o$next[63:0]$10766 \sv0__data_i case - assign $4\msr0__data_o$next[63:0]$10715 $3\msr0__data_o$next[63:0]$10714 + assign $4\msr0__data_o$next[63:0]$10766 $3\msr0__data_o$next[63:0]$10765 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$10716 \d_wr10__data_i + assign $5\msr0__data_o$next[63:0]$10767 \d_wr10__data_i case - assign $5\msr0__data_o$next[63:0]$10716 $4\msr0__data_o$next[63:0]$10715 + assign $5\msr0__data_o$next[63:0]$10767 $4\msr0__data_o$next[63:0]$10766 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$10717 \reg + assign $6\msr0__data_o$next[63:0]$10768 \reg case - assign $6\msr0__data_o$next[63:0]$10717 $5\msr0__data_o$next[63:0]$10716 + assign $6\msr0__data_o$next[63:0]$10768 $5\msr0__data_o$next[63:0]$10767 end case - assign $1\msr0__data_o$next[63:0]$10712 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10763 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr0__data_o$next[63:0]$10718 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr0__data_o$next[63:0]$10769 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr0__data_o$next[63:0]$10718 $1\msr0__data_o$next[63:0]$10712 + assign $7\msr0__data_o$next[63:0]$10769 $1\msr0__data_o$next[63:0]$10763 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10711 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10762 end - attribute \src "libresoc.v:174174.3-174209.6" - process $proc$libresoc.v:174174$10719 + attribute \src "libresoc.v:176270.3-176305.6" + process $proc$libresoc.v:176270$10770 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10720 $1\wr_detect$4[0:0]$10721 - attribute \src "libresoc.v:174175.5-174175.29" + assign $0\wr_detect$4[0:0]$10771 $1\wr_detect$4[0:0]$10772 + attribute \src "libresoc.v:176271.5-176271.29" switch \initial - attribute \src "libresoc.v:174175.9-174175.17" + attribute \src "libresoc.v:176271.9-176271.17" case 1'1 case end @@ -360029,58 +362900,58 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10721 $5\wr_detect$4[0:0]$10725 + assign $1\wr_detect$4[0:0]$10772 $5\wr_detect$4[0:0]$10776 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10722 1'1 + assign $2\wr_detect$4[0:0]$10773 1'1 case - assign $2\wr_detect$4[0:0]$10722 1'0 + assign $2\wr_detect$4[0:0]$10773 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10723 1'1 + assign $3\wr_detect$4[0:0]$10774 1'1 case - assign $3\wr_detect$4[0:0]$10723 $2\wr_detect$4[0:0]$10722 + assign $3\wr_detect$4[0:0]$10774 $2\wr_detect$4[0:0]$10773 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10724 1'1 + assign $4\wr_detect$4[0:0]$10775 1'1 case - assign $4\wr_detect$4[0:0]$10724 $3\wr_detect$4[0:0]$10723 + assign $4\wr_detect$4[0:0]$10775 $3\wr_detect$4[0:0]$10774 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10725 1'1 + assign $5\wr_detect$4[0:0]$10776 1'1 case - assign $5\wr_detect$4[0:0]$10725 $4\wr_detect$4[0:0]$10724 + assign $5\wr_detect$4[0:0]$10776 $4\wr_detect$4[0:0]$10775 end case - assign $1\wr_detect$4[0:0]$10721 1'0 + assign $1\wr_detect$4[0:0]$10772 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10720 + update \wr_detect$4 $0\wr_detect$4[0:0]$10771 end - attribute \src "libresoc.v:174210.3-174255.6" - process $proc$libresoc.v:174210$10726 + attribute \src "libresoc.v:176306.3-176351.6" + process $proc$libresoc.v:176306$10777 assign { } { } assign { } { } assign { } { } - assign $0\sv0__data_o$next[63:0]$10727 $7\sv0__data_o$next[63:0]$10734 - attribute \src "libresoc.v:174211.5-174211.29" + assign $0\sv0__data_o$next[63:0]$10778 $7\sv0__data_o$next[63:0]$10785 + attribute \src "libresoc.v:176307.5-176307.29" switch \initial - attribute \src "libresoc.v:174211.9-174211.17" + attribute \src "libresoc.v:176307.9-176307.17" case 1'1 case end @@ -360093,75 +362964,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\sv0__data_o$next[63:0]$10728 $6\sv0__data_o$next[63:0]$10733 + assign $1\sv0__data_o$next[63:0]$10779 $6\sv0__data_o$next[63:0]$10784 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv0__data_o$next[63:0]$10729 \nia0__data_i + assign $2\sv0__data_o$next[63:0]$10780 \nia0__data_i case - assign $2\sv0__data_o$next[63:0]$10729 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv0__data_o$next[63:0]$10780 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv0__data_o$next[63:0]$10730 \msr0__data_i + assign $3\sv0__data_o$next[63:0]$10781 \msr0__data_i case - assign $3\sv0__data_o$next[63:0]$10730 $2\sv0__data_o$next[63:0]$10729 + assign $3\sv0__data_o$next[63:0]$10781 $2\sv0__data_o$next[63:0]$10780 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv0__data_o$next[63:0]$10731 \sv0__data_i + assign $4\sv0__data_o$next[63:0]$10782 \sv0__data_i case - assign $4\sv0__data_o$next[63:0]$10731 $3\sv0__data_o$next[63:0]$10730 + assign $4\sv0__data_o$next[63:0]$10782 $3\sv0__data_o$next[63:0]$10781 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv0__data_o$next[63:0]$10732 \d_wr10__data_i + assign $5\sv0__data_o$next[63:0]$10783 \d_wr10__data_i case - assign $5\sv0__data_o$next[63:0]$10732 $4\sv0__data_o$next[63:0]$10731 + assign $5\sv0__data_o$next[63:0]$10783 $4\sv0__data_o$next[63:0]$10782 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv0__data_o$next[63:0]$10733 \reg + assign $6\sv0__data_o$next[63:0]$10784 \reg case - assign $6\sv0__data_o$next[63:0]$10733 $5\sv0__data_o$next[63:0]$10732 + assign $6\sv0__data_o$next[63:0]$10784 $5\sv0__data_o$next[63:0]$10783 end case - assign $1\sv0__data_o$next[63:0]$10728 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv0__data_o$next[63:0]$10779 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv0__data_o$next[63:0]$10734 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv0__data_o$next[63:0]$10785 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv0__data_o$next[63:0]$10734 $1\sv0__data_o$next[63:0]$10728 + assign $7\sv0__data_o$next[63:0]$10785 $1\sv0__data_o$next[63:0]$10779 end sync always - update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10727 + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10778 end - attribute \src "libresoc.v:174256.3-174291.6" - process $proc$libresoc.v:174256$10735 + attribute \src "libresoc.v:176352.3-176387.6" + process $proc$libresoc.v:176352$10786 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10736 $1\wr_detect$7[0:0]$10737 - attribute \src "libresoc.v:174257.5-174257.29" + assign $0\wr_detect$7[0:0]$10787 $1\wr_detect$7[0:0]$10788 + attribute \src "libresoc.v:176353.5-176353.29" switch \initial - attribute \src "libresoc.v:174257.9-174257.17" + attribute \src "libresoc.v:176353.9-176353.17" case 1'1 case end @@ -360174,61 +363045,61 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10737 $5\wr_detect$7[0:0]$10741 + assign $1\wr_detect$7[0:0]$10788 $5\wr_detect$7[0:0]$10792 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10738 1'1 + assign $2\wr_detect$7[0:0]$10789 1'1 case - assign $2\wr_detect$7[0:0]$10738 1'0 + assign $2\wr_detect$7[0:0]$10789 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10739 1'1 + assign $3\wr_detect$7[0:0]$10790 1'1 case - assign $3\wr_detect$7[0:0]$10739 $2\wr_detect$7[0:0]$10738 + assign $3\wr_detect$7[0:0]$10790 $2\wr_detect$7[0:0]$10789 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10740 1'1 + assign $4\wr_detect$7[0:0]$10791 1'1 case - assign $4\wr_detect$7[0:0]$10740 $3\wr_detect$7[0:0]$10739 + assign $4\wr_detect$7[0:0]$10791 $3\wr_detect$7[0:0]$10790 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10741 1'1 + assign $5\wr_detect$7[0:0]$10792 1'1 case - assign $5\wr_detect$7[0:0]$10741 $4\wr_detect$7[0:0]$10740 + assign $5\wr_detect$7[0:0]$10792 $4\wr_detect$7[0:0]$10791 end case - assign $1\wr_detect$7[0:0]$10737 1'0 + assign $1\wr_detect$7[0:0]$10788 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10736 + update \wr_detect$7 $0\wr_detect$7[0:0]$10787 end - attribute \src "libresoc.v:174292.3-174324.6" - process $proc$libresoc.v:174292$10742 + attribute \src "libresoc.v:176388.3-176420.6" + process $proc$libresoc.v:176388$10793 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10743 $5\reg$next[63:0]$10748 - attribute \src "libresoc.v:174293.5-174293.29" + assign $0\reg$next[63:0]$10794 $5\reg$next[63:0]$10799 + attribute \src "libresoc.v:176389.5-176389.29" switch \initial - attribute \src "libresoc.v:174293.9-174293.17" + attribute \src "libresoc.v:176389.9-176389.17" case 1'1 case end @@ -360237,224 +363108,224 @@ module \reg_0$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10744 \nia0__data_i + assign $1\reg$next[63:0]$10795 \nia0__data_i case - assign $1\reg$next[63:0]$10744 \reg + assign $1\reg$next[63:0]$10795 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10745 \msr0__data_i + assign $2\reg$next[63:0]$10796 \msr0__data_i case - assign $2\reg$next[63:0]$10745 $1\reg$next[63:0]$10744 + assign $2\reg$next[63:0]$10796 $1\reg$next[63:0]$10795 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10746 \sv0__data_i + assign $3\reg$next[63:0]$10797 \sv0__data_i case - assign $3\reg$next[63:0]$10746 $2\reg$next[63:0]$10745 + assign $3\reg$next[63:0]$10797 $2\reg$next[63:0]$10796 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10747 \d_wr10__data_i + assign $4\reg$next[63:0]$10798 \d_wr10__data_i case - assign $4\reg$next[63:0]$10747 $3\reg$next[63:0]$10746 + assign $4\reg$next[63:0]$10798 $3\reg$next[63:0]$10797 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$10748 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$10799 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$10748 $4\reg$next[63:0]$10747 + assign $5\reg$next[63:0]$10799 $4\reg$next[63:0]$10798 end sync always - update \reg$next $0\reg$next[63:0]$10743 + update \reg$next $0\reg$next[63:0]$10794 end - connect \$1 $not$libresoc.v:174035$10693_Y - connect \$3 $not$libresoc.v:174036$10694_Y - connect \$6 $not$libresoc.v:174037$10695_Y + connect \$1 $not$libresoc.v:176131$10744_Y + connect \$3 $not$libresoc.v:176132$10745_Y + connect \$6 $not$libresoc.v:176133$10746_Y end -attribute \src "libresoc.v:174329.1-174800.10" +attribute \src "libresoc.v:176425.1-176896.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:174330.7-174330.20" + attribute \src "libresoc.v:176426.7-176426.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174660.3-174699.6" - wire width 4 $0\r1__data_o$next[3:0]$10809 - attribute \src "libresoc.v:174415.3-174416.37" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $0\r1__data_o$next[3:0]$10860 + attribute \src "libresoc.v:176511.3-176512.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:174730.3-174769.6" - wire width 4 $0\r21__data_o$next[3:0]$10823 - attribute \src "libresoc.v:174413.3-174414.39" + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $0\r21__data_o$next[3:0]$10874 + attribute \src "libresoc.v:176509.3-176510.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:174493.3-174519.6" - wire width 4 $0\reg$next[3:0]$10775 - attribute \src "libresoc.v:174411.3-174412.25" + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $0\reg$next[3:0]$10826 + attribute \src "libresoc.v:176507.3-176508.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:174423.3-174462.6" - wire width 4 $0\src11__data_o$next[3:0]$10766 - attribute \src "libresoc.v:174421.3-174422.43" + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $0\src11__data_o$next[3:0]$10817 + attribute \src "libresoc.v:176517.3-176518.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:174520.3-174559.6" - wire width 4 $0\src21__data_o$next[3:0]$10781 - attribute \src "libresoc.v:174419.3-174420.43" + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $0\src21__data_o$next[3:0]$10832 + attribute \src "libresoc.v:176515.3-176516.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:174590.3-174629.6" - wire width 4 $0\src31__data_o$next[3:0]$10795 - attribute \src "libresoc.v:174417.3-174418.43" + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $0\src31__data_o$next[3:0]$10846 + attribute \src "libresoc.v:176513.3-176514.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:174700.3-174729.6" - wire $0\wr_detect$10[0:0]$10817 - attribute \src "libresoc.v:174770.3-174799.6" - wire $0\wr_detect$13[0:0]$10831 - attribute \src "libresoc.v:174560.3-174589.6" - wire $0\wr_detect$4[0:0]$10789 - attribute \src "libresoc.v:174630.3-174659.6" - wire $0\wr_detect$7[0:0]$10803 - attribute \src "libresoc.v:174463.3-174492.6" + attribute \src "libresoc.v:176796.3-176825.6" + wire $0\wr_detect$10[0:0]$10868 + attribute \src "libresoc.v:176866.3-176895.6" + wire $0\wr_detect$13[0:0]$10882 + attribute \src "libresoc.v:176656.3-176685.6" + wire $0\wr_detect$4[0:0]$10840 + attribute \src "libresoc.v:176726.3-176755.6" + wire $0\wr_detect$7[0:0]$10854 + attribute \src "libresoc.v:176559.3-176588.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:174660.3-174699.6" - wire width 4 $1\r1__data_o$next[3:0]$10810 - attribute \src "libresoc.v:174355.13-174355.30" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $1\r1__data_o$next[3:0]$10861 + attribute \src "libresoc.v:176451.13-176451.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:174730.3-174769.6" - wire width 4 $1\r21__data_o$next[3:0]$10824 - attribute \src "libresoc.v:174362.13-174362.31" + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $1\r21__data_o$next[3:0]$10875 + attribute \src "libresoc.v:176458.13-176458.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:174493.3-174519.6" - wire width 4 $1\reg$next[3:0]$10776 - attribute \src "libresoc.v:174368.13-174368.25" + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $1\reg$next[3:0]$10827 + attribute \src "libresoc.v:176464.13-176464.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:174423.3-174462.6" - wire width 4 $1\src11__data_o$next[3:0]$10767 - attribute \src "libresoc.v:174373.13-174373.33" + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $1\src11__data_o$next[3:0]$10818 + attribute \src "libresoc.v:176469.13-176469.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:174520.3-174559.6" - wire width 4 $1\src21__data_o$next[3:0]$10782 - attribute \src "libresoc.v:174380.13-174380.33" + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $1\src21__data_o$next[3:0]$10833 + attribute \src "libresoc.v:176476.13-176476.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:174590.3-174629.6" - wire width 4 $1\src31__data_o$next[3:0]$10796 - attribute \src "libresoc.v:174387.13-174387.33" + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $1\src31__data_o$next[3:0]$10847 + attribute \src "libresoc.v:176483.13-176483.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:174700.3-174729.6" - wire $1\wr_detect$10[0:0]$10818 - attribute \src "libresoc.v:174770.3-174799.6" - wire $1\wr_detect$13[0:0]$10832 - attribute \src "libresoc.v:174560.3-174589.6" - wire $1\wr_detect$4[0:0]$10790 - attribute \src "libresoc.v:174630.3-174659.6" - wire $1\wr_detect$7[0:0]$10804 - attribute \src "libresoc.v:174463.3-174492.6" + attribute \src "libresoc.v:176796.3-176825.6" + wire $1\wr_detect$10[0:0]$10869 + attribute \src "libresoc.v:176866.3-176895.6" + wire $1\wr_detect$13[0:0]$10883 + attribute \src "libresoc.v:176656.3-176685.6" + wire $1\wr_detect$4[0:0]$10841 + attribute \src "libresoc.v:176726.3-176755.6" + wire $1\wr_detect$7[0:0]$10855 + attribute \src "libresoc.v:176559.3-176588.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:174660.3-174699.6" - wire width 4 $2\r1__data_o$next[3:0]$10811 - attribute \src "libresoc.v:174730.3-174769.6" - wire width 4 $2\r21__data_o$next[3:0]$10825 - attribute \src "libresoc.v:174493.3-174519.6" - wire width 4 $2\reg$next[3:0]$10777 - attribute \src "libresoc.v:174423.3-174462.6" - wire width 4 $2\src11__data_o$next[3:0]$10768 - attribute \src "libresoc.v:174520.3-174559.6" - wire width 4 $2\src21__data_o$next[3:0]$10783 - attribute \src "libresoc.v:174590.3-174629.6" - wire width 4 $2\src31__data_o$next[3:0]$10797 - attribute \src "libresoc.v:174700.3-174729.6" - wire $2\wr_detect$10[0:0]$10819 - attribute \src "libresoc.v:174770.3-174799.6" - wire $2\wr_detect$13[0:0]$10833 - attribute \src "libresoc.v:174560.3-174589.6" - wire $2\wr_detect$4[0:0]$10791 - attribute \src "libresoc.v:174630.3-174659.6" - wire $2\wr_detect$7[0:0]$10805 - attribute \src "libresoc.v:174463.3-174492.6" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $2\r1__data_o$next[3:0]$10862 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $2\r21__data_o$next[3:0]$10876 + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $2\reg$next[3:0]$10828 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $2\src11__data_o$next[3:0]$10819 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $2\src21__data_o$next[3:0]$10834 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $2\src31__data_o$next[3:0]$10848 + attribute \src "libresoc.v:176796.3-176825.6" + wire $2\wr_detect$10[0:0]$10870 + attribute \src "libresoc.v:176866.3-176895.6" + wire $2\wr_detect$13[0:0]$10884 + attribute \src "libresoc.v:176656.3-176685.6" + wire $2\wr_detect$4[0:0]$10842 + attribute \src "libresoc.v:176726.3-176755.6" + wire $2\wr_detect$7[0:0]$10856 + attribute \src "libresoc.v:176559.3-176588.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:174660.3-174699.6" - wire width 4 $3\r1__data_o$next[3:0]$10812 - attribute \src "libresoc.v:174730.3-174769.6" - wire width 4 $3\r21__data_o$next[3:0]$10826 - attribute \src "libresoc.v:174493.3-174519.6" - wire width 4 $3\reg$next[3:0]$10778 - attribute \src "libresoc.v:174423.3-174462.6" - wire width 4 $3\src11__data_o$next[3:0]$10769 - attribute \src "libresoc.v:174520.3-174559.6" - wire width 4 $3\src21__data_o$next[3:0]$10784 - attribute \src "libresoc.v:174590.3-174629.6" - wire width 4 $3\src31__data_o$next[3:0]$10798 - attribute \src "libresoc.v:174700.3-174729.6" - wire $3\wr_detect$10[0:0]$10820 - attribute \src "libresoc.v:174770.3-174799.6" - wire $3\wr_detect$13[0:0]$10834 - attribute \src "libresoc.v:174560.3-174589.6" - wire $3\wr_detect$4[0:0]$10792 - attribute \src "libresoc.v:174630.3-174659.6" - wire $3\wr_detect$7[0:0]$10806 - attribute \src "libresoc.v:174463.3-174492.6" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $3\r1__data_o$next[3:0]$10863 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $3\r21__data_o$next[3:0]$10877 + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $3\reg$next[3:0]$10829 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $3\src11__data_o$next[3:0]$10820 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $3\src21__data_o$next[3:0]$10835 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $3\src31__data_o$next[3:0]$10849 + attribute \src "libresoc.v:176796.3-176825.6" + wire $3\wr_detect$10[0:0]$10871 + attribute \src "libresoc.v:176866.3-176895.6" + wire $3\wr_detect$13[0:0]$10885 + attribute \src "libresoc.v:176656.3-176685.6" + wire $3\wr_detect$4[0:0]$10843 + attribute \src "libresoc.v:176726.3-176755.6" + wire $3\wr_detect$7[0:0]$10857 + attribute \src "libresoc.v:176559.3-176588.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:174660.3-174699.6" - wire width 4 $4\r1__data_o$next[3:0]$10813 - attribute \src "libresoc.v:174730.3-174769.6" - wire width 4 $4\r21__data_o$next[3:0]$10827 - attribute \src "libresoc.v:174493.3-174519.6" - wire width 4 $4\reg$next[3:0]$10779 - attribute \src "libresoc.v:174423.3-174462.6" - wire width 4 $4\src11__data_o$next[3:0]$10770 - attribute \src "libresoc.v:174520.3-174559.6" - wire width 4 $4\src21__data_o$next[3:0]$10785 - attribute \src "libresoc.v:174590.3-174629.6" - wire width 4 $4\src31__data_o$next[3:0]$10799 - attribute \src "libresoc.v:174700.3-174729.6" - wire $4\wr_detect$10[0:0]$10821 - attribute \src "libresoc.v:174770.3-174799.6" - wire $4\wr_detect$13[0:0]$10835 - attribute \src "libresoc.v:174560.3-174589.6" - wire $4\wr_detect$4[0:0]$10793 - attribute \src "libresoc.v:174630.3-174659.6" - wire $4\wr_detect$7[0:0]$10807 - attribute \src "libresoc.v:174463.3-174492.6" + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $4\r1__data_o$next[3:0]$10864 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $4\r21__data_o$next[3:0]$10878 + attribute \src "libresoc.v:176589.3-176615.6" + wire width 4 $4\reg$next[3:0]$10830 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $4\src11__data_o$next[3:0]$10821 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $4\src21__data_o$next[3:0]$10836 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $4\src31__data_o$next[3:0]$10850 + attribute \src "libresoc.v:176796.3-176825.6" + wire $4\wr_detect$10[0:0]$10872 + attribute \src "libresoc.v:176866.3-176895.6" + wire $4\wr_detect$13[0:0]$10886 + attribute \src "libresoc.v:176656.3-176685.6" + wire $4\wr_detect$4[0:0]$10844 + attribute \src "libresoc.v:176726.3-176755.6" + wire $4\wr_detect$7[0:0]$10858 + attribute \src "libresoc.v:176559.3-176588.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:174660.3-174699.6" - wire width 4 $5\r1__data_o$next[3:0]$10814 - attribute \src "libresoc.v:174730.3-174769.6" - wire width 4 $5\r21__data_o$next[3:0]$10828 - attribute \src "libresoc.v:174423.3-174462.6" - wire width 4 $5\src11__data_o$next[3:0]$10771 - attribute \src "libresoc.v:174520.3-174559.6" - wire width 4 $5\src21__data_o$next[3:0]$10786 - attribute \src "libresoc.v:174590.3-174629.6" - wire width 4 $5\src31__data_o$next[3:0]$10800 - attribute \src "libresoc.v:174660.3-174699.6" - wire width 4 $6\r1__data_o$next[3:0]$10815 - attribute \src "libresoc.v:174730.3-174769.6" - wire width 4 $6\r21__data_o$next[3:0]$10829 - attribute \src "libresoc.v:174423.3-174462.6" - wire width 4 $6\src11__data_o$next[3:0]$10772 - attribute \src "libresoc.v:174520.3-174559.6" - wire width 4 $6\src21__data_o$next[3:0]$10787 - attribute \src "libresoc.v:174590.3-174629.6" - wire width 4 $6\src31__data_o$next[3:0]$10801 - attribute \src "libresoc.v:174406.17-174406.104" - wire $not$libresoc.v:174406$10754_Y - attribute \src "libresoc.v:174407.18-174407.105" - wire $not$libresoc.v:174407$10755_Y - attribute \src "libresoc.v:174408.17-174408.100" - wire $not$libresoc.v:174408$10756_Y - attribute \src "libresoc.v:174409.17-174409.103" - wire $not$libresoc.v:174409$10757_Y - attribute \src "libresoc.v:174410.17-174410.103" - wire $not$libresoc.v:174410$10758_Y + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $5\r1__data_o$next[3:0]$10865 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $5\r21__data_o$next[3:0]$10879 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $5\src11__data_o$next[3:0]$10822 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $5\src21__data_o$next[3:0]$10837 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $5\src31__data_o$next[3:0]$10851 + attribute \src "libresoc.v:176756.3-176795.6" + wire width 4 $6\r1__data_o$next[3:0]$10866 + attribute \src "libresoc.v:176826.3-176865.6" + wire width 4 $6\r21__data_o$next[3:0]$10880 + attribute \src "libresoc.v:176519.3-176558.6" + wire width 4 $6\src11__data_o$next[3:0]$10823 + attribute \src "libresoc.v:176616.3-176655.6" + wire width 4 $6\src21__data_o$next[3:0]$10838 + attribute \src "libresoc.v:176686.3-176725.6" + wire width 4 $6\src31__data_o$next[3:0]$10852 + attribute \src "libresoc.v:176502.17-176502.104" + wire $not$libresoc.v:176502$10805_Y + attribute \src "libresoc.v:176503.18-176503.105" + wire $not$libresoc.v:176503$10806_Y + attribute \src "libresoc.v:176504.17-176504.100" + wire $not$libresoc.v:176504$10807_Y + attribute \src "libresoc.v:176505.17-176505.103" + wire $not$libresoc.v:176505$10808_Y + attribute \src "libresoc.v:176506.17-176506.103" + wire $not$libresoc.v:176506$10809_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -360465,9 +363336,9 @@ module \reg_1 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest11__data_i @@ -360477,7 +363348,7 @@ module \reg_1 wire width 4 input 11 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest21__wen - attribute \src "libresoc.v:174330.7-174330.15" + attribute \src "libresoc.v:176426.7-176426.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r1__data_o @@ -360528,152 +363399,152 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174406$10754 + cell $not $not$libresoc.v:176502$10805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:174406$10754_Y + connect \Y $not$libresoc.v:176502$10805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174407$10755 + cell $not $not$libresoc.v:176503$10806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:174407$10755_Y + connect \Y $not$libresoc.v:176503$10806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174408$10756 + cell $not $not$libresoc.v:176504$10807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:174408$10756_Y + connect \Y $not$libresoc.v:176504$10807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174409$10757 + cell $not $not$libresoc.v:176505$10808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:174409$10757_Y + connect \Y $not$libresoc.v:176505$10808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174410$10758 + cell $not $not$libresoc.v:176506$10809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:174410$10758_Y + connect \Y $not$libresoc.v:176506$10809_Y end - attribute \src "libresoc.v:174330.7-174330.20" - process $proc$libresoc.v:174330$10836 + attribute \src "libresoc.v:176426.7-176426.20" + process $proc$libresoc.v:176426$10887 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174355.13-174355.30" - process $proc$libresoc.v:174355$10837 + attribute \src "libresoc.v:176451.13-176451.30" + process $proc$libresoc.v:176451$10888 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:174362.13-174362.31" - process $proc$libresoc.v:174362$10838 + attribute \src "libresoc.v:176458.13-176458.31" + process $proc$libresoc.v:176458$10889 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:174368.13-174368.25" - process $proc$libresoc.v:174368$10839 + attribute \src "libresoc.v:176464.13-176464.25" + process $proc$libresoc.v:176464$10890 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:174373.13-174373.33" - process $proc$libresoc.v:174373$10840 + attribute \src "libresoc.v:176469.13-176469.33" + process $proc$libresoc.v:176469$10891 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:174380.13-174380.33" - process $proc$libresoc.v:174380$10841 + attribute \src "libresoc.v:176476.13-176476.33" + process $proc$libresoc.v:176476$10892 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:174387.13-174387.33" - process $proc$libresoc.v:174387$10842 + attribute \src "libresoc.v:176483.13-176483.33" + process $proc$libresoc.v:176483$10893 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:174411.3-174412.25" - process $proc$libresoc.v:174411$10759 + attribute \src "libresoc.v:176507.3-176508.25" + process $proc$libresoc.v:176507$10810 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:174413.3-174414.39" - process $proc$libresoc.v:174413$10760 + attribute \src "libresoc.v:176509.3-176510.39" + process $proc$libresoc.v:176509$10811 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:174415.3-174416.37" - process $proc$libresoc.v:174415$10761 + attribute \src "libresoc.v:176511.3-176512.37" + process $proc$libresoc.v:176511$10812 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:174417.3-174418.43" - process $proc$libresoc.v:174417$10762 + attribute \src "libresoc.v:176513.3-176514.43" + process $proc$libresoc.v:176513$10813 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:174419.3-174420.43" - process $proc$libresoc.v:174419$10763 + attribute \src "libresoc.v:176515.3-176516.43" + process $proc$libresoc.v:176515$10814 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:174421.3-174422.43" - process $proc$libresoc.v:174421$10764 + attribute \src "libresoc.v:176517.3-176518.43" + process $proc$libresoc.v:176517$10815 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:174423.3-174462.6" - process $proc$libresoc.v:174423$10765 + attribute \src "libresoc.v:176519.3-176558.6" + process $proc$libresoc.v:176519$10816 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$10766 $6\src11__data_o$next[3:0]$10772 - attribute \src "libresoc.v:174424.5-174424.29" + assign $0\src11__data_o$next[3:0]$10817 $6\src11__data_o$next[3:0]$10823 + attribute \src "libresoc.v:176520.5-176520.29" switch \initial - attribute \src "libresoc.v:174424.9-174424.17" + attribute \src "libresoc.v:176520.9-176520.17" case 1'1 case end @@ -360685,66 +363556,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$10767 $5\src11__data_o$next[3:0]$10771 + assign $1\src11__data_o$next[3:0]$10818 $5\src11__data_o$next[3:0]$10822 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$10768 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10819 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$10768 4'0000 + assign $2\src11__data_o$next[3:0]$10819 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$10769 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10820 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$10769 $2\src11__data_o$next[3:0]$10768 + assign $3\src11__data_o$next[3:0]$10820 $2\src11__data_o$next[3:0]$10819 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$10770 \w1__data_i + assign $4\src11__data_o$next[3:0]$10821 \w1__data_i case - assign $4\src11__data_o$next[3:0]$10770 $3\src11__data_o$next[3:0]$10769 + assign $4\src11__data_o$next[3:0]$10821 $3\src11__data_o$next[3:0]$10820 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$10771 \reg + assign $5\src11__data_o$next[3:0]$10822 \reg case - assign $5\src11__data_o$next[3:0]$10771 $4\src11__data_o$next[3:0]$10770 + assign $5\src11__data_o$next[3:0]$10822 $4\src11__data_o$next[3:0]$10821 end case - assign $1\src11__data_o$next[3:0]$10767 4'0000 + assign $1\src11__data_o$next[3:0]$10818 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$10772 4'0000 + assign $6\src11__data_o$next[3:0]$10823 4'0000 case - assign $6\src11__data_o$next[3:0]$10772 $1\src11__data_o$next[3:0]$10767 + assign $6\src11__data_o$next[3:0]$10823 $1\src11__data_o$next[3:0]$10818 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10766 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10817 end - attribute \src "libresoc.v:174463.3-174492.6" - process $proc$libresoc.v:174463$10773 + attribute \src "libresoc.v:176559.3-176588.6" + process $proc$libresoc.v:176559$10824 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:174464.5-174464.29" + attribute \src "libresoc.v:176560.5-176560.29" switch \initial - attribute \src "libresoc.v:174464.9-174464.17" + attribute \src "libresoc.v:176560.9-176560.17" case 1'1 case end @@ -360790,17 +363661,17 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:174493.3-174519.6" - process $proc$libresoc.v:174493$10774 + attribute \src "libresoc.v:176589.3-176615.6" + process $proc$libresoc.v:176589$10825 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10775 $4\reg$next[3:0]$10779 - attribute \src "libresoc.v:174494.5-174494.29" + assign $0\reg$next[3:0]$10826 $4\reg$next[3:0]$10830 + attribute \src "libresoc.v:176590.5-176590.29" switch \initial - attribute \src "libresoc.v:174494.9-174494.17" + attribute \src "libresoc.v:176590.9-176590.17" case 1'1 case end @@ -360809,49 +363680,49 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10776 \dest11__data_i + assign $1\reg$next[3:0]$10827 \dest11__data_i case - assign $1\reg$next[3:0]$10776 \reg + assign $1\reg$next[3:0]$10827 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10777 \dest21__data_i + assign $2\reg$next[3:0]$10828 \dest21__data_i case - assign $2\reg$next[3:0]$10777 $1\reg$next[3:0]$10776 + assign $2\reg$next[3:0]$10828 $1\reg$next[3:0]$10827 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10778 \w1__data_i + assign $3\reg$next[3:0]$10829 \w1__data_i case - assign $3\reg$next[3:0]$10778 $2\reg$next[3:0]$10777 + assign $3\reg$next[3:0]$10829 $2\reg$next[3:0]$10828 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10779 4'0000 + assign $4\reg$next[3:0]$10830 4'0000 case - assign $4\reg$next[3:0]$10779 $3\reg$next[3:0]$10778 + assign $4\reg$next[3:0]$10830 $3\reg$next[3:0]$10829 end sync always - update \reg$next $0\reg$next[3:0]$10775 + update \reg$next $0\reg$next[3:0]$10826 end - attribute \src "libresoc.v:174520.3-174559.6" - process $proc$libresoc.v:174520$10780 + attribute \src "libresoc.v:176616.3-176655.6" + process $proc$libresoc.v:176616$10831 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$10781 $6\src21__data_o$next[3:0]$10787 - attribute \src "libresoc.v:174521.5-174521.29" + assign $0\src21__data_o$next[3:0]$10832 $6\src21__data_o$next[3:0]$10838 + attribute \src "libresoc.v:176617.5-176617.29" switch \initial - attribute \src "libresoc.v:174521.9-174521.17" + attribute \src "libresoc.v:176617.9-176617.17" case 1'1 case end @@ -360863,66 +363734,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$10782 $5\src21__data_o$next[3:0]$10786 + assign $1\src21__data_o$next[3:0]$10833 $5\src21__data_o$next[3:0]$10837 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$10783 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10834 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$10783 4'0000 + assign $2\src21__data_o$next[3:0]$10834 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$10784 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10835 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$10784 $2\src21__data_o$next[3:0]$10783 + assign $3\src21__data_o$next[3:0]$10835 $2\src21__data_o$next[3:0]$10834 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$10785 \w1__data_i + assign $4\src21__data_o$next[3:0]$10836 \w1__data_i case - assign $4\src21__data_o$next[3:0]$10785 $3\src21__data_o$next[3:0]$10784 + assign $4\src21__data_o$next[3:0]$10836 $3\src21__data_o$next[3:0]$10835 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$10786 \reg + assign $5\src21__data_o$next[3:0]$10837 \reg case - assign $5\src21__data_o$next[3:0]$10786 $4\src21__data_o$next[3:0]$10785 + assign $5\src21__data_o$next[3:0]$10837 $4\src21__data_o$next[3:0]$10836 end case - assign $1\src21__data_o$next[3:0]$10782 4'0000 + assign $1\src21__data_o$next[3:0]$10833 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$10787 4'0000 + assign $6\src21__data_o$next[3:0]$10838 4'0000 case - assign $6\src21__data_o$next[3:0]$10787 $1\src21__data_o$next[3:0]$10782 + assign $6\src21__data_o$next[3:0]$10838 $1\src21__data_o$next[3:0]$10833 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10781 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10832 end - attribute \src "libresoc.v:174560.3-174589.6" - process $proc$libresoc.v:174560$10788 + attribute \src "libresoc.v:176656.3-176685.6" + process $proc$libresoc.v:176656$10839 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10789 $1\wr_detect$4[0:0]$10790 - attribute \src "libresoc.v:174561.5-174561.29" + assign $0\wr_detect$4[0:0]$10840 $1\wr_detect$4[0:0]$10841 + attribute \src "libresoc.v:176657.5-176657.29" switch \initial - attribute \src "libresoc.v:174561.9-174561.17" + attribute \src "libresoc.v:176657.9-176657.17" case 1'1 case end @@ -360934,49 +363805,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10790 $4\wr_detect$4[0:0]$10793 + assign $1\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10844 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10791 1'1 + assign $2\wr_detect$4[0:0]$10842 1'1 case - assign $2\wr_detect$4[0:0]$10791 1'0 + assign $2\wr_detect$4[0:0]$10842 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10792 1'1 + assign $3\wr_detect$4[0:0]$10843 1'1 case - assign $3\wr_detect$4[0:0]$10792 $2\wr_detect$4[0:0]$10791 + assign $3\wr_detect$4[0:0]$10843 $2\wr_detect$4[0:0]$10842 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10793 1'1 + assign $4\wr_detect$4[0:0]$10844 1'1 case - assign $4\wr_detect$4[0:0]$10793 $3\wr_detect$4[0:0]$10792 + assign $4\wr_detect$4[0:0]$10844 $3\wr_detect$4[0:0]$10843 end case - assign $1\wr_detect$4[0:0]$10790 1'0 + assign $1\wr_detect$4[0:0]$10841 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10789 + update \wr_detect$4 $0\wr_detect$4[0:0]$10840 end - attribute \src "libresoc.v:174590.3-174629.6" - process $proc$libresoc.v:174590$10794 + attribute \src "libresoc.v:176686.3-176725.6" + process $proc$libresoc.v:176686$10845 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$10795 $6\src31__data_o$next[3:0]$10801 - attribute \src "libresoc.v:174591.5-174591.29" + assign $0\src31__data_o$next[3:0]$10846 $6\src31__data_o$next[3:0]$10852 + attribute \src "libresoc.v:176687.5-176687.29" switch \initial - attribute \src "libresoc.v:174591.9-174591.17" + attribute \src "libresoc.v:176687.9-176687.17" case 1'1 case end @@ -360988,66 +363859,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$10796 $5\src31__data_o$next[3:0]$10800 + assign $1\src31__data_o$next[3:0]$10847 $5\src31__data_o$next[3:0]$10851 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$10797 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10848 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$10797 4'0000 + assign $2\src31__data_o$next[3:0]$10848 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$10798 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10849 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$10798 $2\src31__data_o$next[3:0]$10797 + assign $3\src31__data_o$next[3:0]$10849 $2\src31__data_o$next[3:0]$10848 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$10799 \w1__data_i + assign $4\src31__data_o$next[3:0]$10850 \w1__data_i case - assign $4\src31__data_o$next[3:0]$10799 $3\src31__data_o$next[3:0]$10798 + assign $4\src31__data_o$next[3:0]$10850 $3\src31__data_o$next[3:0]$10849 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$10800 \reg + assign $5\src31__data_o$next[3:0]$10851 \reg case - assign $5\src31__data_o$next[3:0]$10800 $4\src31__data_o$next[3:0]$10799 + assign $5\src31__data_o$next[3:0]$10851 $4\src31__data_o$next[3:0]$10850 end case - assign $1\src31__data_o$next[3:0]$10796 4'0000 + assign $1\src31__data_o$next[3:0]$10847 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$10801 4'0000 + assign $6\src31__data_o$next[3:0]$10852 4'0000 case - assign $6\src31__data_o$next[3:0]$10801 $1\src31__data_o$next[3:0]$10796 + assign $6\src31__data_o$next[3:0]$10852 $1\src31__data_o$next[3:0]$10847 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10795 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10846 end - attribute \src "libresoc.v:174630.3-174659.6" - process $proc$libresoc.v:174630$10802 + attribute \src "libresoc.v:176726.3-176755.6" + process $proc$libresoc.v:176726$10853 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10803 $1\wr_detect$7[0:0]$10804 - attribute \src "libresoc.v:174631.5-174631.29" + assign $0\wr_detect$7[0:0]$10854 $1\wr_detect$7[0:0]$10855 + attribute \src "libresoc.v:176727.5-176727.29" switch \initial - attribute \src "libresoc.v:174631.9-174631.17" + attribute \src "libresoc.v:176727.9-176727.17" case 1'1 case end @@ -361059,49 +363930,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10804 $4\wr_detect$7[0:0]$10807 + assign $1\wr_detect$7[0:0]$10855 $4\wr_detect$7[0:0]$10858 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10805 1'1 + assign $2\wr_detect$7[0:0]$10856 1'1 case - assign $2\wr_detect$7[0:0]$10805 1'0 + assign $2\wr_detect$7[0:0]$10856 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10806 1'1 + assign $3\wr_detect$7[0:0]$10857 1'1 case - assign $3\wr_detect$7[0:0]$10806 $2\wr_detect$7[0:0]$10805 + assign $3\wr_detect$7[0:0]$10857 $2\wr_detect$7[0:0]$10856 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10807 1'1 + assign $4\wr_detect$7[0:0]$10858 1'1 case - assign $4\wr_detect$7[0:0]$10807 $3\wr_detect$7[0:0]$10806 + assign $4\wr_detect$7[0:0]$10858 $3\wr_detect$7[0:0]$10857 end case - assign $1\wr_detect$7[0:0]$10804 1'0 + assign $1\wr_detect$7[0:0]$10855 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10803 + update \wr_detect$7 $0\wr_detect$7[0:0]$10854 end - attribute \src "libresoc.v:174660.3-174699.6" - process $proc$libresoc.v:174660$10808 + attribute \src "libresoc.v:176756.3-176795.6" + process $proc$libresoc.v:176756$10859 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10809 $6\r1__data_o$next[3:0]$10815 - attribute \src "libresoc.v:174661.5-174661.29" + assign $0\r1__data_o$next[3:0]$10860 $6\r1__data_o$next[3:0]$10866 + attribute \src "libresoc.v:176757.5-176757.29" switch \initial - attribute \src "libresoc.v:174661.9-174661.17" + attribute \src "libresoc.v:176757.9-176757.17" case 1'1 case end @@ -361113,66 +363984,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$10810 $5\r1__data_o$next[3:0]$10814 + assign $1\r1__data_o$next[3:0]$10861 $5\r1__data_o$next[3:0]$10865 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$10811 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10862 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$10811 4'0000 + assign $2\r1__data_o$next[3:0]$10862 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$10812 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10863 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$10812 $2\r1__data_o$next[3:0]$10811 + assign $3\r1__data_o$next[3:0]$10863 $2\r1__data_o$next[3:0]$10862 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$10813 \w1__data_i + assign $4\r1__data_o$next[3:0]$10864 \w1__data_i case - assign $4\r1__data_o$next[3:0]$10813 $3\r1__data_o$next[3:0]$10812 + assign $4\r1__data_o$next[3:0]$10864 $3\r1__data_o$next[3:0]$10863 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$10814 \reg + assign $5\r1__data_o$next[3:0]$10865 \reg case - assign $5\r1__data_o$next[3:0]$10814 $4\r1__data_o$next[3:0]$10813 + assign $5\r1__data_o$next[3:0]$10865 $4\r1__data_o$next[3:0]$10864 end case - assign $1\r1__data_o$next[3:0]$10810 4'0000 + assign $1\r1__data_o$next[3:0]$10861 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$10815 4'0000 + assign $6\r1__data_o$next[3:0]$10866 4'0000 case - assign $6\r1__data_o$next[3:0]$10815 $1\r1__data_o$next[3:0]$10810 + assign $6\r1__data_o$next[3:0]$10866 $1\r1__data_o$next[3:0]$10861 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10809 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10860 end - attribute \src "libresoc.v:174700.3-174729.6" - process $proc$libresoc.v:174700$10816 + attribute \src "libresoc.v:176796.3-176825.6" + process $proc$libresoc.v:176796$10867 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10817 $1\wr_detect$10[0:0]$10818 - attribute \src "libresoc.v:174701.5-174701.29" + assign $0\wr_detect$10[0:0]$10868 $1\wr_detect$10[0:0]$10869 + attribute \src "libresoc.v:176797.5-176797.29" switch \initial - attribute \src "libresoc.v:174701.9-174701.17" + attribute \src "libresoc.v:176797.9-176797.17" case 1'1 case end @@ -361184,49 +364055,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10818 $4\wr_detect$10[0:0]$10821 + assign $1\wr_detect$10[0:0]$10869 $4\wr_detect$10[0:0]$10872 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10819 1'1 + assign $2\wr_detect$10[0:0]$10870 1'1 case - assign $2\wr_detect$10[0:0]$10819 1'0 + assign $2\wr_detect$10[0:0]$10870 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10820 1'1 + assign $3\wr_detect$10[0:0]$10871 1'1 case - assign $3\wr_detect$10[0:0]$10820 $2\wr_detect$10[0:0]$10819 + assign $3\wr_detect$10[0:0]$10871 $2\wr_detect$10[0:0]$10870 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10821 1'1 + assign $4\wr_detect$10[0:0]$10872 1'1 case - assign $4\wr_detect$10[0:0]$10821 $3\wr_detect$10[0:0]$10820 + assign $4\wr_detect$10[0:0]$10872 $3\wr_detect$10[0:0]$10871 end case - assign $1\wr_detect$10[0:0]$10818 1'0 + assign $1\wr_detect$10[0:0]$10869 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10817 + update \wr_detect$10 $0\wr_detect$10[0:0]$10868 end - attribute \src "libresoc.v:174730.3-174769.6" - process $proc$libresoc.v:174730$10822 + attribute \src "libresoc.v:176826.3-176865.6" + process $proc$libresoc.v:176826$10873 assign { } { } assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$10823 $6\r21__data_o$next[3:0]$10829 - attribute \src "libresoc.v:174731.5-174731.29" + assign $0\r21__data_o$next[3:0]$10874 $6\r21__data_o$next[3:0]$10880 + attribute \src "libresoc.v:176827.5-176827.29" switch \initial - attribute \src "libresoc.v:174731.9-174731.17" + attribute \src "libresoc.v:176827.9-176827.17" case 1'1 case end @@ -361238,66 +364109,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$10824 $5\r21__data_o$next[3:0]$10828 + assign $1\r21__data_o$next[3:0]$10875 $5\r21__data_o$next[3:0]$10879 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$10825 \dest11__data_i + assign $2\r21__data_o$next[3:0]$10876 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$10825 4'0000 + assign $2\r21__data_o$next[3:0]$10876 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$10826 \dest21__data_i + assign $3\r21__data_o$next[3:0]$10877 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$10826 $2\r21__data_o$next[3:0]$10825 + assign $3\r21__data_o$next[3:0]$10877 $2\r21__data_o$next[3:0]$10876 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$10827 \w1__data_i + assign $4\r21__data_o$next[3:0]$10878 \w1__data_i case - assign $4\r21__data_o$next[3:0]$10827 $3\r21__data_o$next[3:0]$10826 + assign $4\r21__data_o$next[3:0]$10878 $3\r21__data_o$next[3:0]$10877 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$10828 \reg + assign $5\r21__data_o$next[3:0]$10879 \reg case - assign $5\r21__data_o$next[3:0]$10828 $4\r21__data_o$next[3:0]$10827 + assign $5\r21__data_o$next[3:0]$10879 $4\r21__data_o$next[3:0]$10878 end case - assign $1\r21__data_o$next[3:0]$10824 4'0000 + assign $1\r21__data_o$next[3:0]$10875 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$10829 4'0000 + assign $6\r21__data_o$next[3:0]$10880 4'0000 case - assign $6\r21__data_o$next[3:0]$10829 $1\r21__data_o$next[3:0]$10824 + assign $6\r21__data_o$next[3:0]$10880 $1\r21__data_o$next[3:0]$10875 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10823 + update \r21__data_o$next $0\r21__data_o$next[3:0]$10874 end - attribute \src "libresoc.v:174770.3-174799.6" - process $proc$libresoc.v:174770$10830 + attribute \src "libresoc.v:176866.3-176895.6" + process $proc$libresoc.v:176866$10881 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10831 $1\wr_detect$13[0:0]$10832 - attribute \src "libresoc.v:174771.5-174771.29" + assign $0\wr_detect$13[0:0]$10882 $1\wr_detect$13[0:0]$10883 + attribute \src "libresoc.v:176867.5-176867.29" switch \initial - attribute \src "libresoc.v:174771.9-174771.17" + attribute \src "libresoc.v:176867.9-176867.17" case 1'1 case end @@ -361309,205 +364180,205 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10832 $4\wr_detect$13[0:0]$10835 + assign $1\wr_detect$13[0:0]$10883 $4\wr_detect$13[0:0]$10886 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10833 1'1 + assign $2\wr_detect$13[0:0]$10884 1'1 case - assign $2\wr_detect$13[0:0]$10833 1'0 + assign $2\wr_detect$13[0:0]$10884 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10834 1'1 + assign $3\wr_detect$13[0:0]$10885 1'1 case - assign $3\wr_detect$13[0:0]$10834 $2\wr_detect$13[0:0]$10833 + assign $3\wr_detect$13[0:0]$10885 $2\wr_detect$13[0:0]$10884 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10835 1'1 + assign $4\wr_detect$13[0:0]$10886 1'1 case - assign $4\wr_detect$13[0:0]$10835 $3\wr_detect$13[0:0]$10834 + assign $4\wr_detect$13[0:0]$10886 $3\wr_detect$13[0:0]$10885 end case - assign $1\wr_detect$13[0:0]$10832 1'0 + assign $1\wr_detect$13[0:0]$10883 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10831 + update \wr_detect$13 $0\wr_detect$13[0:0]$10882 end - connect \$9 $not$libresoc.v:174406$10754_Y - connect \$12 $not$libresoc.v:174407$10755_Y - connect \$1 $not$libresoc.v:174408$10756_Y - connect \$3 $not$libresoc.v:174409$10757_Y - connect \$6 $not$libresoc.v:174410$10758_Y + connect \$9 $not$libresoc.v:176502$10805_Y + connect \$12 $not$libresoc.v:176503$10806_Y + connect \$1 $not$libresoc.v:176504$10807_Y + connect \$3 $not$libresoc.v:176505$10808_Y + connect \$6 $not$libresoc.v:176506$10809_Y end -attribute \src "libresoc.v:174804.1-175249.10" +attribute \src "libresoc.v:176900.1-177345.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:174805.7-174805.20" + attribute \src "libresoc.v:176901.7-176901.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175134.3-175179.6" - wire width 2 $0\r1__data_o$next[1:0]$10895 - attribute \src "libresoc.v:174880.3-174881.37" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $0\r1__data_o$next[1:0]$10946 + attribute \src "libresoc.v:176976.3-176977.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:175216.3-175248.6" - wire width 2 $0\reg$next[1:0]$10911 - attribute \src "libresoc.v:174878.3-174879.25" + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $0\reg$next[1:0]$10962 + attribute \src "libresoc.v:176974.3-176975.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:174888.3-174933.6" - wire width 2 $0\src11__data_o$next[1:0]$10853 - attribute \src "libresoc.v:174886.3-174887.43" + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $0\src11__data_o$next[1:0]$10904 + attribute \src "libresoc.v:176982.3-176983.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:174970.3-175015.6" - wire width 2 $0\src21__data_o$next[1:0]$10863 - attribute \src "libresoc.v:174884.3-174885.43" + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $0\src21__data_o$next[1:0]$10914 + attribute \src "libresoc.v:176980.3-176981.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:175052.3-175097.6" - wire width 2 $0\src31__data_o$next[1:0]$10879 - attribute \src "libresoc.v:174882.3-174883.43" + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $0\src31__data_o$next[1:0]$10930 + attribute \src "libresoc.v:176978.3-176979.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:175180.3-175215.6" - wire $0\wr_detect$10[0:0]$10904 - attribute \src "libresoc.v:175016.3-175051.6" - wire $0\wr_detect$4[0:0]$10872 - attribute \src "libresoc.v:175098.3-175133.6" - wire $0\wr_detect$7[0:0]$10888 - attribute \src "libresoc.v:174934.3-174969.6" + attribute \src "libresoc.v:177276.3-177311.6" + wire $0\wr_detect$10[0:0]$10955 + attribute \src "libresoc.v:177112.3-177147.6" + wire $0\wr_detect$4[0:0]$10923 + attribute \src "libresoc.v:177194.3-177229.6" + wire $0\wr_detect$7[0:0]$10939 + attribute \src "libresoc.v:177030.3-177065.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:175134.3-175179.6" - wire width 2 $1\r1__data_o$next[1:0]$10896 - attribute \src "libresoc.v:174832.13-174832.30" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $1\r1__data_o$next[1:0]$10947 + attribute \src "libresoc.v:176928.13-176928.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:175216.3-175248.6" - wire width 2 $1\reg$next[1:0]$10912 - attribute \src "libresoc.v:174838.13-174838.25" + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $1\reg$next[1:0]$10963 + attribute \src "libresoc.v:176934.13-176934.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:174888.3-174933.6" - wire width 2 $1\src11__data_o$next[1:0]$10854 - attribute \src "libresoc.v:174843.13-174843.33" + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $1\src11__data_o$next[1:0]$10905 + attribute \src "libresoc.v:176939.13-176939.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:174970.3-175015.6" - wire width 2 $1\src21__data_o$next[1:0]$10864 - attribute \src "libresoc.v:174850.13-174850.33" + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $1\src21__data_o$next[1:0]$10915 + attribute \src "libresoc.v:176946.13-176946.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:175052.3-175097.6" - wire width 2 $1\src31__data_o$next[1:0]$10880 - attribute \src "libresoc.v:174857.13-174857.33" + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $1\src31__data_o$next[1:0]$10931 + attribute \src "libresoc.v:176953.13-176953.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:175180.3-175215.6" - wire $1\wr_detect$10[0:0]$10905 - attribute \src "libresoc.v:175016.3-175051.6" - wire $1\wr_detect$4[0:0]$10873 - attribute \src "libresoc.v:175098.3-175133.6" - wire $1\wr_detect$7[0:0]$10889 - attribute \src "libresoc.v:174934.3-174969.6" + attribute \src "libresoc.v:177276.3-177311.6" + wire $1\wr_detect$10[0:0]$10956 + attribute \src "libresoc.v:177112.3-177147.6" + wire $1\wr_detect$4[0:0]$10924 + attribute \src "libresoc.v:177194.3-177229.6" + wire $1\wr_detect$7[0:0]$10940 + attribute \src "libresoc.v:177030.3-177065.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:175134.3-175179.6" - wire width 2 $2\r1__data_o$next[1:0]$10897 - attribute \src "libresoc.v:175216.3-175248.6" - wire width 2 $2\reg$next[1:0]$10913 - attribute \src "libresoc.v:174888.3-174933.6" - wire width 2 $2\src11__data_o$next[1:0]$10855 - attribute \src "libresoc.v:174970.3-175015.6" - wire width 2 $2\src21__data_o$next[1:0]$10865 - attribute \src "libresoc.v:175052.3-175097.6" - wire width 2 $2\src31__data_o$next[1:0]$10881 - attribute \src "libresoc.v:175180.3-175215.6" - wire $2\wr_detect$10[0:0]$10906 - attribute \src "libresoc.v:175016.3-175051.6" - wire $2\wr_detect$4[0:0]$10874 - attribute \src "libresoc.v:175098.3-175133.6" - wire $2\wr_detect$7[0:0]$10890 - attribute \src "libresoc.v:174934.3-174969.6" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $2\r1__data_o$next[1:0]$10948 + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $2\reg$next[1:0]$10964 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $2\src11__data_o$next[1:0]$10906 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $2\src21__data_o$next[1:0]$10916 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $2\src31__data_o$next[1:0]$10932 + attribute \src "libresoc.v:177276.3-177311.6" + wire $2\wr_detect$10[0:0]$10957 + attribute \src "libresoc.v:177112.3-177147.6" + wire $2\wr_detect$4[0:0]$10925 + attribute \src "libresoc.v:177194.3-177229.6" + wire $2\wr_detect$7[0:0]$10941 + attribute \src "libresoc.v:177030.3-177065.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:175134.3-175179.6" - wire width 2 $3\r1__data_o$next[1:0]$10898 - attribute \src "libresoc.v:175216.3-175248.6" - wire width 2 $3\reg$next[1:0]$10914 - attribute \src "libresoc.v:174888.3-174933.6" - wire width 2 $3\src11__data_o$next[1:0]$10856 - attribute \src "libresoc.v:174970.3-175015.6" - wire width 2 $3\src21__data_o$next[1:0]$10866 - attribute \src "libresoc.v:175052.3-175097.6" - wire width 2 $3\src31__data_o$next[1:0]$10882 - attribute \src "libresoc.v:175180.3-175215.6" - wire $3\wr_detect$10[0:0]$10907 - attribute \src "libresoc.v:175016.3-175051.6" - wire $3\wr_detect$4[0:0]$10875 - attribute \src "libresoc.v:175098.3-175133.6" - wire $3\wr_detect$7[0:0]$10891 - attribute \src "libresoc.v:174934.3-174969.6" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $3\r1__data_o$next[1:0]$10949 + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $3\reg$next[1:0]$10965 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $3\src11__data_o$next[1:0]$10907 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $3\src21__data_o$next[1:0]$10917 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $3\src31__data_o$next[1:0]$10933 + attribute \src "libresoc.v:177276.3-177311.6" + wire $3\wr_detect$10[0:0]$10958 + attribute \src "libresoc.v:177112.3-177147.6" + wire $3\wr_detect$4[0:0]$10926 + attribute \src "libresoc.v:177194.3-177229.6" + wire $3\wr_detect$7[0:0]$10942 + attribute \src "libresoc.v:177030.3-177065.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:175134.3-175179.6" - wire width 2 $4\r1__data_o$next[1:0]$10899 - attribute \src "libresoc.v:175216.3-175248.6" - wire width 2 $4\reg$next[1:0]$10915 - attribute \src "libresoc.v:174888.3-174933.6" - wire width 2 $4\src11__data_o$next[1:0]$10857 - attribute \src "libresoc.v:174970.3-175015.6" - wire width 2 $4\src21__data_o$next[1:0]$10867 - attribute \src "libresoc.v:175052.3-175097.6" - wire width 2 $4\src31__data_o$next[1:0]$10883 - attribute \src "libresoc.v:175180.3-175215.6" - wire $4\wr_detect$10[0:0]$10908 - attribute \src "libresoc.v:175016.3-175051.6" - wire $4\wr_detect$4[0:0]$10876 - attribute \src "libresoc.v:175098.3-175133.6" - wire $4\wr_detect$7[0:0]$10892 - attribute \src "libresoc.v:174934.3-174969.6" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $4\r1__data_o$next[1:0]$10950 + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $4\reg$next[1:0]$10966 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $4\src11__data_o$next[1:0]$10908 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $4\src21__data_o$next[1:0]$10918 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $4\src31__data_o$next[1:0]$10934 + attribute \src "libresoc.v:177276.3-177311.6" + wire $4\wr_detect$10[0:0]$10959 + attribute \src "libresoc.v:177112.3-177147.6" + wire $4\wr_detect$4[0:0]$10927 + attribute \src "libresoc.v:177194.3-177229.6" + wire $4\wr_detect$7[0:0]$10943 + attribute \src "libresoc.v:177030.3-177065.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:175134.3-175179.6" - wire width 2 $5\r1__data_o$next[1:0]$10900 - attribute \src "libresoc.v:175216.3-175248.6" - wire width 2 $5\reg$next[1:0]$10916 - attribute \src "libresoc.v:174888.3-174933.6" - wire width 2 $5\src11__data_o$next[1:0]$10858 - attribute \src "libresoc.v:174970.3-175015.6" - wire width 2 $5\src21__data_o$next[1:0]$10868 - attribute \src "libresoc.v:175052.3-175097.6" - wire width 2 $5\src31__data_o$next[1:0]$10884 - attribute \src "libresoc.v:175180.3-175215.6" - wire $5\wr_detect$10[0:0]$10909 - attribute \src "libresoc.v:175016.3-175051.6" - wire $5\wr_detect$4[0:0]$10877 - attribute \src "libresoc.v:175098.3-175133.6" - wire $5\wr_detect$7[0:0]$10893 - attribute \src "libresoc.v:174934.3-174969.6" + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $5\r1__data_o$next[1:0]$10951 + attribute \src "libresoc.v:177312.3-177344.6" + wire width 2 $5\reg$next[1:0]$10967 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $5\src11__data_o$next[1:0]$10909 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $5\src21__data_o$next[1:0]$10919 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $5\src31__data_o$next[1:0]$10935 + attribute \src "libresoc.v:177276.3-177311.6" + wire $5\wr_detect$10[0:0]$10960 + attribute \src "libresoc.v:177112.3-177147.6" + wire $5\wr_detect$4[0:0]$10928 + attribute \src "libresoc.v:177194.3-177229.6" + wire $5\wr_detect$7[0:0]$10944 + attribute \src "libresoc.v:177030.3-177065.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:175134.3-175179.6" - wire width 2 $6\r1__data_o$next[1:0]$10901 - attribute \src "libresoc.v:174888.3-174933.6" - wire width 2 $6\src11__data_o$next[1:0]$10859 - attribute \src "libresoc.v:174970.3-175015.6" - wire width 2 $6\src21__data_o$next[1:0]$10869 - attribute \src "libresoc.v:175052.3-175097.6" - wire width 2 $6\src31__data_o$next[1:0]$10885 - attribute \src "libresoc.v:175134.3-175179.6" - wire width 2 $7\r1__data_o$next[1:0]$10902 - attribute \src "libresoc.v:174888.3-174933.6" - wire width 2 $7\src11__data_o$next[1:0]$10860 - attribute \src "libresoc.v:174970.3-175015.6" - wire width 2 $7\src21__data_o$next[1:0]$10870 - attribute \src "libresoc.v:175052.3-175097.6" - wire width 2 $7\src31__data_o$next[1:0]$10886 - attribute \src "libresoc.v:174874.17-174874.104" - wire $not$libresoc.v:174874$10843_Y - attribute \src "libresoc.v:174875.17-174875.100" - wire $not$libresoc.v:174875$10844_Y - attribute \src "libresoc.v:174876.17-174876.103" - wire $not$libresoc.v:174876$10845_Y - attribute \src "libresoc.v:174877.17-174877.103" - wire $not$libresoc.v:174877$10846_Y + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $6\r1__data_o$next[1:0]$10952 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $6\src11__data_o$next[1:0]$10910 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $6\src21__data_o$next[1:0]$10920 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $6\src31__data_o$next[1:0]$10936 + attribute \src "libresoc.v:177230.3-177275.6" + wire width 2 $7\r1__data_o$next[1:0]$10953 + attribute \src "libresoc.v:176984.3-177029.6" + wire width 2 $7\src11__data_o$next[1:0]$10911 + attribute \src "libresoc.v:177066.3-177111.6" + wire width 2 $7\src21__data_o$next[1:0]$10921 + attribute \src "libresoc.v:177148.3-177193.6" + wire width 2 $7\src31__data_o$next[1:0]$10937 + attribute \src "libresoc.v:176970.17-176970.104" + wire $not$libresoc.v:176970$10894_Y + attribute \src "libresoc.v:176971.17-176971.100" + wire $not$libresoc.v:176971$10895_Y + attribute \src "libresoc.v:176972.17-176972.103" + wire $not$libresoc.v:176972$10896_Y + attribute \src "libresoc.v:176973.17-176973.103" + wire $not$libresoc.v:176973$10897_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -361516,9 +364387,9 @@ module \reg_1$133 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i @@ -361532,7 +364403,7 @@ module \reg_1$133 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:174805.7-174805.15" + attribute \src "libresoc.v:176901.7-176901.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o @@ -361575,129 +364446,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174874$10843 + cell $not $not$libresoc.v:176970$10894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:174874$10843_Y + connect \Y $not$libresoc.v:176970$10894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174875$10844 + cell $not $not$libresoc.v:176971$10895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:174875$10844_Y + connect \Y $not$libresoc.v:176971$10895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174876$10845 + cell $not $not$libresoc.v:176972$10896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:174876$10845_Y + connect \Y $not$libresoc.v:176972$10896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:174877$10846 + cell $not $not$libresoc.v:176973$10897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:174877$10846_Y + connect \Y $not$libresoc.v:176973$10897_Y end - attribute \src "libresoc.v:174805.7-174805.20" - process $proc$libresoc.v:174805$10917 + attribute \src "libresoc.v:176901.7-176901.20" + process $proc$libresoc.v:176901$10968 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174832.13-174832.30" - process $proc$libresoc.v:174832$10918 + attribute \src "libresoc.v:176928.13-176928.30" + process $proc$libresoc.v:176928$10969 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:174838.13-174838.25" - process $proc$libresoc.v:174838$10919 + attribute \src "libresoc.v:176934.13-176934.25" + process $proc$libresoc.v:176934$10970 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:174843.13-174843.33" - process $proc$libresoc.v:174843$10920 + attribute \src "libresoc.v:176939.13-176939.33" + process $proc$libresoc.v:176939$10971 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:174850.13-174850.33" - process $proc$libresoc.v:174850$10921 + attribute \src "libresoc.v:176946.13-176946.33" + process $proc$libresoc.v:176946$10972 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:174857.13-174857.33" - process $proc$libresoc.v:174857$10922 + attribute \src "libresoc.v:176953.13-176953.33" + process $proc$libresoc.v:176953$10973 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:174878.3-174879.25" - process $proc$libresoc.v:174878$10847 + attribute \src "libresoc.v:176974.3-176975.25" + process $proc$libresoc.v:176974$10898 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:174880.3-174881.37" - process $proc$libresoc.v:174880$10848 + attribute \src "libresoc.v:176976.3-176977.37" + process $proc$libresoc.v:176976$10899 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:174882.3-174883.43" - process $proc$libresoc.v:174882$10849 + attribute \src "libresoc.v:176978.3-176979.43" + process $proc$libresoc.v:176978$10900 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:174884.3-174885.43" - process $proc$libresoc.v:174884$10850 + attribute \src "libresoc.v:176980.3-176981.43" + process $proc$libresoc.v:176980$10901 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:174886.3-174887.43" - process $proc$libresoc.v:174886$10851 + attribute \src "libresoc.v:176982.3-176983.43" + process $proc$libresoc.v:176982$10902 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:174888.3-174933.6" - process $proc$libresoc.v:174888$10852 + attribute \src "libresoc.v:176984.3-177029.6" + process $proc$libresoc.v:176984$10903 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$10853 $7\src11__data_o$next[1:0]$10860 - attribute \src "libresoc.v:174889.5-174889.29" + assign $0\src11__data_o$next[1:0]$10904 $7\src11__data_o$next[1:0]$10911 + attribute \src "libresoc.v:176985.5-176985.29" switch \initial - attribute \src "libresoc.v:174889.9-174889.17" + attribute \src "libresoc.v:176985.9-176985.17" case 1'1 case end @@ -361710,75 +364581,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$10854 $6\src11__data_o$next[1:0]$10859 + assign $1\src11__data_o$next[1:0]$10905 $6\src11__data_o$next[1:0]$10910 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$10855 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10906 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$10855 2'00 + assign $2\src11__data_o$next[1:0]$10906 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$10856 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10907 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$10856 $2\src11__data_o$next[1:0]$10855 + assign $3\src11__data_o$next[1:0]$10907 $2\src11__data_o$next[1:0]$10906 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$10857 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10908 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$10857 $3\src11__data_o$next[1:0]$10856 + assign $4\src11__data_o$next[1:0]$10908 $3\src11__data_o$next[1:0]$10907 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$10858 \w1__data_i + assign $5\src11__data_o$next[1:0]$10909 \w1__data_i case - assign $5\src11__data_o$next[1:0]$10858 $4\src11__data_o$next[1:0]$10857 + assign $5\src11__data_o$next[1:0]$10909 $4\src11__data_o$next[1:0]$10908 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$10859 \reg + assign $6\src11__data_o$next[1:0]$10910 \reg case - assign $6\src11__data_o$next[1:0]$10859 $5\src11__data_o$next[1:0]$10858 + assign $6\src11__data_o$next[1:0]$10910 $5\src11__data_o$next[1:0]$10909 end case - assign $1\src11__data_o$next[1:0]$10854 2'00 + assign $1\src11__data_o$next[1:0]$10905 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$10860 2'00 + assign $7\src11__data_o$next[1:0]$10911 2'00 case - assign $7\src11__data_o$next[1:0]$10860 $1\src11__data_o$next[1:0]$10854 + assign $7\src11__data_o$next[1:0]$10911 $1\src11__data_o$next[1:0]$10905 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10853 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10904 end - attribute \src "libresoc.v:174934.3-174969.6" - process $proc$libresoc.v:174934$10861 + attribute \src "libresoc.v:177030.3-177065.6" + process $proc$libresoc.v:177030$10912 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:174935.5-174935.29" + attribute \src "libresoc.v:177031.5-177031.29" switch \initial - attribute \src "libresoc.v:174935.9-174935.17" + attribute \src "libresoc.v:177031.9-177031.17" case 1'1 case end @@ -361834,15 +364705,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:174970.3-175015.6" - process $proc$libresoc.v:174970$10862 + attribute \src "libresoc.v:177066.3-177111.6" + process $proc$libresoc.v:177066$10913 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$10863 $7\src21__data_o$next[1:0]$10870 - attribute \src "libresoc.v:174971.5-174971.29" + assign $0\src21__data_o$next[1:0]$10914 $7\src21__data_o$next[1:0]$10921 + attribute \src "libresoc.v:177067.5-177067.29" switch \initial - attribute \src "libresoc.v:174971.9-174971.17" + attribute \src "libresoc.v:177067.9-177067.17" case 1'1 case end @@ -361855,75 +364726,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$10864 $6\src21__data_o$next[1:0]$10869 + assign $1\src21__data_o$next[1:0]$10915 $6\src21__data_o$next[1:0]$10920 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$10865 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10916 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$10865 2'00 + assign $2\src21__data_o$next[1:0]$10916 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$10866 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10917 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$10866 $2\src21__data_o$next[1:0]$10865 + assign $3\src21__data_o$next[1:0]$10917 $2\src21__data_o$next[1:0]$10916 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$10867 \dest31__data_i + assign $4\src21__data_o$next[1:0]$10918 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$10867 $3\src21__data_o$next[1:0]$10866 + assign $4\src21__data_o$next[1:0]$10918 $3\src21__data_o$next[1:0]$10917 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$10868 \w1__data_i + assign $5\src21__data_o$next[1:0]$10919 \w1__data_i case - assign $5\src21__data_o$next[1:0]$10868 $4\src21__data_o$next[1:0]$10867 + assign $5\src21__data_o$next[1:0]$10919 $4\src21__data_o$next[1:0]$10918 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$10869 \reg + assign $6\src21__data_o$next[1:0]$10920 \reg case - assign $6\src21__data_o$next[1:0]$10869 $5\src21__data_o$next[1:0]$10868 + assign $6\src21__data_o$next[1:0]$10920 $5\src21__data_o$next[1:0]$10919 end case - assign $1\src21__data_o$next[1:0]$10864 2'00 + assign $1\src21__data_o$next[1:0]$10915 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$10870 2'00 + assign $7\src21__data_o$next[1:0]$10921 2'00 case - assign $7\src21__data_o$next[1:0]$10870 $1\src21__data_o$next[1:0]$10864 + assign $7\src21__data_o$next[1:0]$10921 $1\src21__data_o$next[1:0]$10915 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10863 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10914 end - attribute \src "libresoc.v:175016.3-175051.6" - process $proc$libresoc.v:175016$10871 + attribute \src "libresoc.v:177112.3-177147.6" + process $proc$libresoc.v:177112$10922 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10872 $1\wr_detect$4[0:0]$10873 - attribute \src "libresoc.v:175017.5-175017.29" + assign $0\wr_detect$4[0:0]$10923 $1\wr_detect$4[0:0]$10924 + attribute \src "libresoc.v:177113.5-177113.29" switch \initial - attribute \src "libresoc.v:175017.9-175017.17" + attribute \src "libresoc.v:177113.9-177113.17" case 1'1 case end @@ -361936,58 +364807,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10873 $5\wr_detect$4[0:0]$10877 + assign $1\wr_detect$4[0:0]$10924 $5\wr_detect$4[0:0]$10928 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10874 1'1 + assign $2\wr_detect$4[0:0]$10925 1'1 case - assign $2\wr_detect$4[0:0]$10874 1'0 + assign $2\wr_detect$4[0:0]$10925 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10875 1'1 + assign $3\wr_detect$4[0:0]$10926 1'1 case - assign $3\wr_detect$4[0:0]$10875 $2\wr_detect$4[0:0]$10874 + assign $3\wr_detect$4[0:0]$10926 $2\wr_detect$4[0:0]$10925 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10876 1'1 + assign $4\wr_detect$4[0:0]$10927 1'1 case - assign $4\wr_detect$4[0:0]$10876 $3\wr_detect$4[0:0]$10875 + assign $4\wr_detect$4[0:0]$10927 $3\wr_detect$4[0:0]$10926 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10877 1'1 + assign $5\wr_detect$4[0:0]$10928 1'1 case - assign $5\wr_detect$4[0:0]$10877 $4\wr_detect$4[0:0]$10876 + assign $5\wr_detect$4[0:0]$10928 $4\wr_detect$4[0:0]$10927 end case - assign $1\wr_detect$4[0:0]$10873 1'0 + assign $1\wr_detect$4[0:0]$10924 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10872 + update \wr_detect$4 $0\wr_detect$4[0:0]$10923 end - attribute \src "libresoc.v:175052.3-175097.6" - process $proc$libresoc.v:175052$10878 + attribute \src "libresoc.v:177148.3-177193.6" + process $proc$libresoc.v:177148$10929 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$10879 $7\src31__data_o$next[1:0]$10886 - attribute \src "libresoc.v:175053.5-175053.29" + assign $0\src31__data_o$next[1:0]$10930 $7\src31__data_o$next[1:0]$10937 + attribute \src "libresoc.v:177149.5-177149.29" switch \initial - attribute \src "libresoc.v:175053.9-175053.17" + attribute \src "libresoc.v:177149.9-177149.17" case 1'1 case end @@ -362000,75 +364871,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$10880 $6\src31__data_o$next[1:0]$10885 + assign $1\src31__data_o$next[1:0]$10931 $6\src31__data_o$next[1:0]$10936 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$10881 \dest11__data_i + assign $2\src31__data_o$next[1:0]$10932 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$10881 2'00 + assign $2\src31__data_o$next[1:0]$10932 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$10882 \dest21__data_i + assign $3\src31__data_o$next[1:0]$10933 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$10882 $2\src31__data_o$next[1:0]$10881 + assign $3\src31__data_o$next[1:0]$10933 $2\src31__data_o$next[1:0]$10932 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$10883 \dest31__data_i + assign $4\src31__data_o$next[1:0]$10934 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$10883 $3\src31__data_o$next[1:0]$10882 + assign $4\src31__data_o$next[1:0]$10934 $3\src31__data_o$next[1:0]$10933 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$10884 \w1__data_i + assign $5\src31__data_o$next[1:0]$10935 \w1__data_i case - assign $5\src31__data_o$next[1:0]$10884 $4\src31__data_o$next[1:0]$10883 + assign $5\src31__data_o$next[1:0]$10935 $4\src31__data_o$next[1:0]$10934 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$10885 \reg + assign $6\src31__data_o$next[1:0]$10936 \reg case - assign $6\src31__data_o$next[1:0]$10885 $5\src31__data_o$next[1:0]$10884 + assign $6\src31__data_o$next[1:0]$10936 $5\src31__data_o$next[1:0]$10935 end case - assign $1\src31__data_o$next[1:0]$10880 2'00 + assign $1\src31__data_o$next[1:0]$10931 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$10886 2'00 + assign $7\src31__data_o$next[1:0]$10937 2'00 case - assign $7\src31__data_o$next[1:0]$10886 $1\src31__data_o$next[1:0]$10880 + assign $7\src31__data_o$next[1:0]$10937 $1\src31__data_o$next[1:0]$10931 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$10879 + update \src31__data_o$next $0\src31__data_o$next[1:0]$10930 end - attribute \src "libresoc.v:175098.3-175133.6" - process $proc$libresoc.v:175098$10887 + attribute \src "libresoc.v:177194.3-177229.6" + process $proc$libresoc.v:177194$10938 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10888 $1\wr_detect$7[0:0]$10889 - attribute \src "libresoc.v:175099.5-175099.29" + assign $0\wr_detect$7[0:0]$10939 $1\wr_detect$7[0:0]$10940 + attribute \src "libresoc.v:177195.5-177195.29" switch \initial - attribute \src "libresoc.v:175099.9-175099.17" + attribute \src "libresoc.v:177195.9-177195.17" case 1'1 case end @@ -362081,58 +364952,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10889 $5\wr_detect$7[0:0]$10893 + assign $1\wr_detect$7[0:0]$10940 $5\wr_detect$7[0:0]$10944 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10890 1'1 + assign $2\wr_detect$7[0:0]$10941 1'1 case - assign $2\wr_detect$7[0:0]$10890 1'0 + assign $2\wr_detect$7[0:0]$10941 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10891 1'1 + assign $3\wr_detect$7[0:0]$10942 1'1 case - assign $3\wr_detect$7[0:0]$10891 $2\wr_detect$7[0:0]$10890 + assign $3\wr_detect$7[0:0]$10942 $2\wr_detect$7[0:0]$10941 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10892 1'1 + assign $4\wr_detect$7[0:0]$10943 1'1 case - assign $4\wr_detect$7[0:0]$10892 $3\wr_detect$7[0:0]$10891 + assign $4\wr_detect$7[0:0]$10943 $3\wr_detect$7[0:0]$10942 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10893 1'1 + assign $5\wr_detect$7[0:0]$10944 1'1 case - assign $5\wr_detect$7[0:0]$10893 $4\wr_detect$7[0:0]$10892 + assign $5\wr_detect$7[0:0]$10944 $4\wr_detect$7[0:0]$10943 end case - assign $1\wr_detect$7[0:0]$10889 1'0 + assign $1\wr_detect$7[0:0]$10940 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10888 + update \wr_detect$7 $0\wr_detect$7[0:0]$10939 end - attribute \src "libresoc.v:175134.3-175179.6" - process $proc$libresoc.v:175134$10894 + attribute \src "libresoc.v:177230.3-177275.6" + process $proc$libresoc.v:177230$10945 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$10895 $7\r1__data_o$next[1:0]$10902 - attribute \src "libresoc.v:175135.5-175135.29" + assign $0\r1__data_o$next[1:0]$10946 $7\r1__data_o$next[1:0]$10953 + attribute \src "libresoc.v:177231.5-177231.29" switch \initial - attribute \src "libresoc.v:175135.9-175135.17" + attribute \src "libresoc.v:177231.9-177231.17" case 1'1 case end @@ -362145,75 +365016,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$10896 $6\r1__data_o$next[1:0]$10901 + assign $1\r1__data_o$next[1:0]$10947 $6\r1__data_o$next[1:0]$10952 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$10897 \dest11__data_i + assign $2\r1__data_o$next[1:0]$10948 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$10897 2'00 + assign $2\r1__data_o$next[1:0]$10948 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$10898 \dest21__data_i + assign $3\r1__data_o$next[1:0]$10949 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$10898 $2\r1__data_o$next[1:0]$10897 + assign $3\r1__data_o$next[1:0]$10949 $2\r1__data_o$next[1:0]$10948 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$10899 \dest31__data_i + assign $4\r1__data_o$next[1:0]$10950 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$10899 $3\r1__data_o$next[1:0]$10898 + assign $4\r1__data_o$next[1:0]$10950 $3\r1__data_o$next[1:0]$10949 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$10900 \w1__data_i + assign $5\r1__data_o$next[1:0]$10951 \w1__data_i case - assign $5\r1__data_o$next[1:0]$10900 $4\r1__data_o$next[1:0]$10899 + assign $5\r1__data_o$next[1:0]$10951 $4\r1__data_o$next[1:0]$10950 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$10901 \reg + assign $6\r1__data_o$next[1:0]$10952 \reg case - assign $6\r1__data_o$next[1:0]$10901 $5\r1__data_o$next[1:0]$10900 + assign $6\r1__data_o$next[1:0]$10952 $5\r1__data_o$next[1:0]$10951 end case - assign $1\r1__data_o$next[1:0]$10896 2'00 + assign $1\r1__data_o$next[1:0]$10947 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$10902 2'00 + assign $7\r1__data_o$next[1:0]$10953 2'00 case - assign $7\r1__data_o$next[1:0]$10902 $1\r1__data_o$next[1:0]$10896 + assign $7\r1__data_o$next[1:0]$10953 $1\r1__data_o$next[1:0]$10947 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$10895 + update \r1__data_o$next $0\r1__data_o$next[1:0]$10946 end - attribute \src "libresoc.v:175180.3-175215.6" - process $proc$libresoc.v:175180$10903 + attribute \src "libresoc.v:177276.3-177311.6" + process $proc$libresoc.v:177276$10954 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10904 $1\wr_detect$10[0:0]$10905 - attribute \src "libresoc.v:175181.5-175181.29" + assign $0\wr_detect$10[0:0]$10955 $1\wr_detect$10[0:0]$10956 + attribute \src "libresoc.v:177277.5-177277.29" switch \initial - attribute \src "libresoc.v:175181.9-175181.17" + attribute \src "libresoc.v:177277.9-177277.17" case 1'1 case end @@ -362226,61 +365097,61 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10905 $5\wr_detect$10[0:0]$10909 + assign $1\wr_detect$10[0:0]$10956 $5\wr_detect$10[0:0]$10960 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10906 1'1 + assign $2\wr_detect$10[0:0]$10957 1'1 case - assign $2\wr_detect$10[0:0]$10906 1'0 + assign $2\wr_detect$10[0:0]$10957 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10907 1'1 + assign $3\wr_detect$10[0:0]$10958 1'1 case - assign $3\wr_detect$10[0:0]$10907 $2\wr_detect$10[0:0]$10906 + assign $3\wr_detect$10[0:0]$10958 $2\wr_detect$10[0:0]$10957 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10908 1'1 + assign $4\wr_detect$10[0:0]$10959 1'1 case - assign $4\wr_detect$10[0:0]$10908 $3\wr_detect$10[0:0]$10907 + assign $4\wr_detect$10[0:0]$10959 $3\wr_detect$10[0:0]$10958 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10909 1'1 + assign $5\wr_detect$10[0:0]$10960 1'1 case - assign $5\wr_detect$10[0:0]$10909 $4\wr_detect$10[0:0]$10908 + assign $5\wr_detect$10[0:0]$10960 $4\wr_detect$10[0:0]$10959 end case - assign $1\wr_detect$10[0:0]$10905 1'0 + assign $1\wr_detect$10[0:0]$10956 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10904 + update \wr_detect$10 $0\wr_detect$10[0:0]$10955 end - attribute \src "libresoc.v:175216.3-175248.6" - process $proc$libresoc.v:175216$10910 + attribute \src "libresoc.v:177312.3-177344.6" + process $proc$libresoc.v:177312$10961 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10911 $5\reg$next[1:0]$10916 - attribute \src "libresoc.v:175217.5-175217.29" + assign $0\reg$next[1:0]$10962 $5\reg$next[1:0]$10967 + attribute \src "libresoc.v:177313.5-177313.29" switch \initial - attribute \src "libresoc.v:175217.9-175217.17" + attribute \src "libresoc.v:177313.9-177313.17" case 1'1 case end @@ -362289,179 +365160,179 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10912 \dest11__data_i + assign $1\reg$next[1:0]$10963 \dest11__data_i case - assign $1\reg$next[1:0]$10912 \reg + assign $1\reg$next[1:0]$10963 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10913 \dest21__data_i + assign $2\reg$next[1:0]$10964 \dest21__data_i case - assign $2\reg$next[1:0]$10913 $1\reg$next[1:0]$10912 + assign $2\reg$next[1:0]$10964 $1\reg$next[1:0]$10963 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10914 \dest31__data_i + assign $3\reg$next[1:0]$10965 \dest31__data_i case - assign $3\reg$next[1:0]$10914 $2\reg$next[1:0]$10913 + assign $3\reg$next[1:0]$10965 $2\reg$next[1:0]$10964 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10915 \w1__data_i + assign $4\reg$next[1:0]$10966 \w1__data_i case - assign $4\reg$next[1:0]$10915 $3\reg$next[1:0]$10914 + assign $4\reg$next[1:0]$10966 $3\reg$next[1:0]$10965 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10916 2'00 + assign $5\reg$next[1:0]$10967 2'00 case - assign $5\reg$next[1:0]$10916 $4\reg$next[1:0]$10915 + assign $5\reg$next[1:0]$10967 $4\reg$next[1:0]$10966 end sync always - update \reg$next $0\reg$next[1:0]$10911 + update \reg$next $0\reg$next[1:0]$10962 end - connect \$9 $not$libresoc.v:174874$10843_Y - connect \$1 $not$libresoc.v:174875$10844_Y - connect \$3 $not$libresoc.v:174876$10845_Y - connect \$6 $not$libresoc.v:174877$10846_Y + connect \$9 $not$libresoc.v:176970$10894_Y + connect \$1 $not$libresoc.v:176971$10895_Y + connect \$3 $not$libresoc.v:176972$10896_Y + connect \$6 $not$libresoc.v:176973$10897_Y end -attribute \src "libresoc.v:175253.1-175602.10" +attribute \src "libresoc.v:177349.1-177698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:175323.3-175368.6" - wire width 64 $0\cia1__data_o$next[63:0]$10931 - attribute \src "libresoc.v:175321.3-175322.41" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $0\cia1__data_o$next[63:0]$10982 + attribute \src "libresoc.v:177417.3-177418.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:175254.7-175254.20" + attribute \src "libresoc.v:177350.7-177350.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175405.3-175450.6" - wire width 64 $0\msr1__data_o$next[63:0]$10941 - attribute \src "libresoc.v:175319.3-175320.41" + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $0\msr1__data_o$next[63:0]$10992 + attribute \src "libresoc.v:177415.3-177416.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:175569.3-175601.6" - wire width 64 $0\reg$next[63:0]$10973 - attribute \src "libresoc.v:175315.3-175316.25" + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $0\reg$next[63:0]$11024 + attribute \src "libresoc.v:177411.3-177412.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:175487.3-175532.6" - wire width 64 $0\sv1__data_o$next[63:0]$10957 - attribute \src "libresoc.v:175317.3-175318.39" + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $0\sv1__data_o$next[63:0]$11008 + attribute \src "libresoc.v:177413.3-177414.39" wire width 64 $0\sv1__data_o[63:0] - attribute \src "libresoc.v:175451.3-175486.6" - wire $0\wr_detect$4[0:0]$10950 - attribute \src "libresoc.v:175533.3-175568.6" - wire $0\wr_detect$7[0:0]$10966 - attribute \src "libresoc.v:175369.3-175404.6" + attribute \src "libresoc.v:177547.3-177582.6" + wire $0\wr_detect$4[0:0]$11001 + attribute \src "libresoc.v:177629.3-177664.6" + wire $0\wr_detect$7[0:0]$11017 + attribute \src "libresoc.v:177465.3-177500.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:175323.3-175368.6" - wire width 64 $1\cia1__data_o$next[63:0]$10932 - attribute \src "libresoc.v:175263.14-175263.49" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $1\cia1__data_o$next[63:0]$10983 + attribute \src "libresoc.v:177359.14-177359.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:175405.3-175450.6" - wire width 64 $1\msr1__data_o$next[63:0]$10942 - attribute \src "libresoc.v:175280.14-175280.49" + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $1\msr1__data_o$next[63:0]$10993 + attribute \src "libresoc.v:177376.14-177376.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:175569.3-175601.6" - wire width 64 $1\reg$next[63:0]$10974 - attribute \src "libresoc.v:175292.14-175292.42" + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $1\reg$next[63:0]$11025 + attribute \src "libresoc.v:177388.14-177388.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:175487.3-175532.6" - wire width 64 $1\sv1__data_o$next[63:0]$10958 - attribute \src "libresoc.v:175299.14-175299.48" + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $1\sv1__data_o$next[63:0]$11009 + attribute \src "libresoc.v:177395.14-177395.48" wire width 64 $1\sv1__data_o[63:0] - attribute \src "libresoc.v:175451.3-175486.6" - wire $1\wr_detect$4[0:0]$10951 - attribute \src "libresoc.v:175533.3-175568.6" - wire $1\wr_detect$7[0:0]$10967 - attribute \src "libresoc.v:175369.3-175404.6" + attribute \src "libresoc.v:177547.3-177582.6" + wire $1\wr_detect$4[0:0]$11002 + attribute \src "libresoc.v:177629.3-177664.6" + wire $1\wr_detect$7[0:0]$11018 + attribute \src "libresoc.v:177465.3-177500.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:175323.3-175368.6" - wire width 64 $2\cia1__data_o$next[63:0]$10933 - attribute \src "libresoc.v:175405.3-175450.6" - wire width 64 $2\msr1__data_o$next[63:0]$10943 - attribute \src "libresoc.v:175569.3-175601.6" - wire width 64 $2\reg$next[63:0]$10975 - attribute \src "libresoc.v:175487.3-175532.6" - wire width 64 $2\sv1__data_o$next[63:0]$10959 - attribute \src "libresoc.v:175451.3-175486.6" - wire $2\wr_detect$4[0:0]$10952 - attribute \src "libresoc.v:175533.3-175568.6" - wire $2\wr_detect$7[0:0]$10968 - attribute \src "libresoc.v:175369.3-175404.6" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $2\cia1__data_o$next[63:0]$10984 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $2\msr1__data_o$next[63:0]$10994 + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $2\reg$next[63:0]$11026 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $2\sv1__data_o$next[63:0]$11010 + attribute \src "libresoc.v:177547.3-177582.6" + wire $2\wr_detect$4[0:0]$11003 + attribute \src "libresoc.v:177629.3-177664.6" + wire $2\wr_detect$7[0:0]$11019 + attribute \src "libresoc.v:177465.3-177500.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:175323.3-175368.6" - wire width 64 $3\cia1__data_o$next[63:0]$10934 - attribute \src "libresoc.v:175405.3-175450.6" - wire width 64 $3\msr1__data_o$next[63:0]$10944 - attribute \src "libresoc.v:175569.3-175601.6" - wire width 64 $3\reg$next[63:0]$10976 - attribute \src "libresoc.v:175487.3-175532.6" - wire width 64 $3\sv1__data_o$next[63:0]$10960 - attribute \src "libresoc.v:175451.3-175486.6" - wire $3\wr_detect$4[0:0]$10953 - attribute \src "libresoc.v:175533.3-175568.6" - wire $3\wr_detect$7[0:0]$10969 - attribute \src "libresoc.v:175369.3-175404.6" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $3\cia1__data_o$next[63:0]$10985 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $3\msr1__data_o$next[63:0]$10995 + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $3\reg$next[63:0]$11027 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $3\sv1__data_o$next[63:0]$11011 + attribute \src "libresoc.v:177547.3-177582.6" + wire $3\wr_detect$4[0:0]$11004 + attribute \src "libresoc.v:177629.3-177664.6" + wire $3\wr_detect$7[0:0]$11020 + attribute \src "libresoc.v:177465.3-177500.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:175323.3-175368.6" - wire width 64 $4\cia1__data_o$next[63:0]$10935 - attribute \src "libresoc.v:175405.3-175450.6" - wire width 64 $4\msr1__data_o$next[63:0]$10945 - attribute \src "libresoc.v:175569.3-175601.6" - wire width 64 $4\reg$next[63:0]$10977 - attribute \src "libresoc.v:175487.3-175532.6" - wire width 64 $4\sv1__data_o$next[63:0]$10961 - attribute \src "libresoc.v:175451.3-175486.6" - wire $4\wr_detect$4[0:0]$10954 - attribute \src "libresoc.v:175533.3-175568.6" - wire $4\wr_detect$7[0:0]$10970 - attribute \src "libresoc.v:175369.3-175404.6" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $4\cia1__data_o$next[63:0]$10986 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $4\msr1__data_o$next[63:0]$10996 + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $4\reg$next[63:0]$11028 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $4\sv1__data_o$next[63:0]$11012 + attribute \src "libresoc.v:177547.3-177582.6" + wire $4\wr_detect$4[0:0]$11005 + attribute \src "libresoc.v:177629.3-177664.6" + wire $4\wr_detect$7[0:0]$11021 + attribute \src "libresoc.v:177465.3-177500.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:175323.3-175368.6" - wire width 64 $5\cia1__data_o$next[63:0]$10936 - attribute \src "libresoc.v:175405.3-175450.6" - wire width 64 $5\msr1__data_o$next[63:0]$10946 - attribute \src "libresoc.v:175569.3-175601.6" - wire width 64 $5\reg$next[63:0]$10978 - attribute \src "libresoc.v:175487.3-175532.6" - wire width 64 $5\sv1__data_o$next[63:0]$10962 - attribute \src "libresoc.v:175451.3-175486.6" - wire $5\wr_detect$4[0:0]$10955 - attribute \src "libresoc.v:175533.3-175568.6" - wire $5\wr_detect$7[0:0]$10971 - attribute \src "libresoc.v:175369.3-175404.6" + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $5\cia1__data_o$next[63:0]$10987 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $5\msr1__data_o$next[63:0]$10997 + attribute \src "libresoc.v:177665.3-177697.6" + wire width 64 $5\reg$next[63:0]$11029 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $5\sv1__data_o$next[63:0]$11013 + attribute \src "libresoc.v:177547.3-177582.6" + wire $5\wr_detect$4[0:0]$11006 + attribute \src "libresoc.v:177629.3-177664.6" + wire $5\wr_detect$7[0:0]$11022 + attribute \src "libresoc.v:177465.3-177500.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:175323.3-175368.6" - wire width 64 $6\cia1__data_o$next[63:0]$10937 - attribute \src "libresoc.v:175405.3-175450.6" - wire width 64 $6\msr1__data_o$next[63:0]$10947 - attribute \src "libresoc.v:175487.3-175532.6" - wire width 64 $6\sv1__data_o$next[63:0]$10963 - attribute \src "libresoc.v:175323.3-175368.6" - wire width 64 $7\cia1__data_o$next[63:0]$10938 - attribute \src "libresoc.v:175405.3-175450.6" - wire width 64 $7\msr1__data_o$next[63:0]$10948 - attribute \src "libresoc.v:175487.3-175532.6" - wire width 64 $7\sv1__data_o$next[63:0]$10964 - attribute \src "libresoc.v:175312.17-175312.100" - wire $not$libresoc.v:175312$10923_Y - attribute \src "libresoc.v:175313.17-175313.103" - wire $not$libresoc.v:175313$10924_Y - attribute \src "libresoc.v:175314.17-175314.103" - wire $not$libresoc.v:175314$10925_Y + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $6\cia1__data_o$next[63:0]$10988 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $6\msr1__data_o$next[63:0]$10998 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $6\sv1__data_o$next[63:0]$11014 + attribute \src "libresoc.v:177419.3-177464.6" + wire width 64 $7\cia1__data_o$next[63:0]$10989 + attribute \src "libresoc.v:177501.3-177546.6" + wire width 64 $7\msr1__data_o$next[63:0]$10999 + attribute \src "libresoc.v:177583.3-177628.6" + wire width 64 $7\sv1__data_o$next[63:0]$11015 + attribute \src "libresoc.v:177408.17-177408.100" + wire $not$libresoc.v:177408$10974_Y + attribute \src "libresoc.v:177409.17-177409.103" + wire $not$libresoc.v:177409$10975_Y + attribute \src "libresoc.v:177410.17-177410.103" + wire $not$libresoc.v:177410$10976_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -362474,15 +365345,15 @@ module \reg_1$136 wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen - attribute \src "libresoc.v:175254.7-175254.15" + attribute \src "libresoc.v:177350.7-177350.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i @@ -362519,106 +365390,106 @@ module \reg_1$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175312$10923 + cell $not $not$libresoc.v:177408$10974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:175312$10923_Y + connect \Y $not$libresoc.v:177408$10974_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175313$10924 + cell $not $not$libresoc.v:177409$10975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:175313$10924_Y + connect \Y $not$libresoc.v:177409$10975_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175314$10925 + cell $not $not$libresoc.v:177410$10976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:175314$10925_Y + connect \Y $not$libresoc.v:177410$10976_Y end - attribute \src "libresoc.v:175254.7-175254.20" - process $proc$libresoc.v:175254$10979 + attribute \src "libresoc.v:177350.7-177350.20" + process $proc$libresoc.v:177350$11030 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175263.14-175263.49" - process $proc$libresoc.v:175263$10980 + attribute \src "libresoc.v:177359.14-177359.49" + process $proc$libresoc.v:177359$11031 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:175280.14-175280.49" - process $proc$libresoc.v:175280$10981 + attribute \src "libresoc.v:177376.14-177376.49" + process $proc$libresoc.v:177376$11032 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:175292.14-175292.42" - process $proc$libresoc.v:175292$10982 + attribute \src "libresoc.v:177388.14-177388.42" + process $proc$libresoc.v:177388$11033 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:175299.14-175299.48" - process $proc$libresoc.v:175299$10983 + attribute \src "libresoc.v:177395.14-177395.48" + process $proc$libresoc.v:177395$11034 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end - attribute \src "libresoc.v:175315.3-175316.25" - process $proc$libresoc.v:175315$10926 + attribute \src "libresoc.v:177411.3-177412.25" + process $proc$libresoc.v:177411$10977 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:175317.3-175318.39" - process $proc$libresoc.v:175317$10927 + attribute \src "libresoc.v:177413.3-177414.39" + process $proc$libresoc.v:177413$10978 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end - attribute \src "libresoc.v:175319.3-175320.41" - process $proc$libresoc.v:175319$10928 + attribute \src "libresoc.v:177415.3-177416.41" + process $proc$libresoc.v:177415$10979 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:175321.3-175322.41" - process $proc$libresoc.v:175321$10929 + attribute \src "libresoc.v:177417.3-177418.41" + process $proc$libresoc.v:177417$10980 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:175323.3-175368.6" - process $proc$libresoc.v:175323$10930 + attribute \src "libresoc.v:177419.3-177464.6" + process $proc$libresoc.v:177419$10981 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$10931 $7\cia1__data_o$next[63:0]$10938 - attribute \src "libresoc.v:175324.5-175324.29" + assign $0\cia1__data_o$next[63:0]$10982 $7\cia1__data_o$next[63:0]$10989 + attribute \src "libresoc.v:177420.5-177420.29" switch \initial - attribute \src "libresoc.v:175324.9-175324.17" + attribute \src "libresoc.v:177420.9-177420.17" case 1'1 case end @@ -362631,75 +365502,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$10932 $6\cia1__data_o$next[63:0]$10937 + assign $1\cia1__data_o$next[63:0]$10983 $6\cia1__data_o$next[63:0]$10988 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$10933 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$10984 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$10933 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$10984 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$10934 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$10985 \msr1__data_i case - assign $3\cia1__data_o$next[63:0]$10934 $2\cia1__data_o$next[63:0]$10933 + assign $3\cia1__data_o$next[63:0]$10985 $2\cia1__data_o$next[63:0]$10984 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$10935 \sv1__data_i + assign $4\cia1__data_o$next[63:0]$10986 \sv1__data_i case - assign $4\cia1__data_o$next[63:0]$10935 $3\cia1__data_o$next[63:0]$10934 + assign $4\cia1__data_o$next[63:0]$10986 $3\cia1__data_o$next[63:0]$10985 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$10936 \d_wr11__data_i + assign $5\cia1__data_o$next[63:0]$10987 \d_wr11__data_i case - assign $5\cia1__data_o$next[63:0]$10936 $4\cia1__data_o$next[63:0]$10935 + assign $5\cia1__data_o$next[63:0]$10987 $4\cia1__data_o$next[63:0]$10986 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$10937 \reg + assign $6\cia1__data_o$next[63:0]$10988 \reg case - assign $6\cia1__data_o$next[63:0]$10937 $5\cia1__data_o$next[63:0]$10936 + assign $6\cia1__data_o$next[63:0]$10988 $5\cia1__data_o$next[63:0]$10987 end case - assign $1\cia1__data_o$next[63:0]$10932 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$10983 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia1__data_o$next[63:0]$10938 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia1__data_o$next[63:0]$10938 $1\cia1__data_o$next[63:0]$10932 + assign $7\cia1__data_o$next[63:0]$10989 $1\cia1__data_o$next[63:0]$10983 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10931 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10982 end - attribute \src "libresoc.v:175369.3-175404.6" - process $proc$libresoc.v:175369$10939 + attribute \src "libresoc.v:177465.3-177500.6" + process $proc$libresoc.v:177465$10990 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:175370.5-175370.29" + attribute \src "libresoc.v:177466.5-177466.29" switch \initial - attribute \src "libresoc.v:175370.9-175370.17" + attribute \src "libresoc.v:177466.9-177466.17" case 1'1 case end @@ -362755,15 +365626,15 @@ module \reg_1$136 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:175405.3-175450.6" - process $proc$libresoc.v:175405$10940 + attribute \src "libresoc.v:177501.3-177546.6" + process $proc$libresoc.v:177501$10991 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$10941 $7\msr1__data_o$next[63:0]$10948 - attribute \src "libresoc.v:175406.5-175406.29" + assign $0\msr1__data_o$next[63:0]$10992 $7\msr1__data_o$next[63:0]$10999 + attribute \src "libresoc.v:177502.5-177502.29" switch \initial - attribute \src "libresoc.v:175406.9-175406.17" + attribute \src "libresoc.v:177502.9-177502.17" case 1'1 case end @@ -362776,75 +365647,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$10942 $6\msr1__data_o$next[63:0]$10947 + assign $1\msr1__data_o$next[63:0]$10993 $6\msr1__data_o$next[63:0]$10998 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$10943 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$10994 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$10943 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$10994 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$10944 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$10995 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$10944 $2\msr1__data_o$next[63:0]$10943 + assign $3\msr1__data_o$next[63:0]$10995 $2\msr1__data_o$next[63:0]$10994 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$10945 \sv1__data_i + assign $4\msr1__data_o$next[63:0]$10996 \sv1__data_i case - assign $4\msr1__data_o$next[63:0]$10945 $3\msr1__data_o$next[63:0]$10944 + assign $4\msr1__data_o$next[63:0]$10996 $3\msr1__data_o$next[63:0]$10995 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$10946 \d_wr11__data_i + assign $5\msr1__data_o$next[63:0]$10997 \d_wr11__data_i case - assign $5\msr1__data_o$next[63:0]$10946 $4\msr1__data_o$next[63:0]$10945 + assign $5\msr1__data_o$next[63:0]$10997 $4\msr1__data_o$next[63:0]$10996 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$10947 \reg + assign $6\msr1__data_o$next[63:0]$10998 \reg case - assign $6\msr1__data_o$next[63:0]$10947 $5\msr1__data_o$next[63:0]$10946 + assign $6\msr1__data_o$next[63:0]$10998 $5\msr1__data_o$next[63:0]$10997 end case - assign $1\msr1__data_o$next[63:0]$10942 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$10993 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr1__data_o$next[63:0]$10948 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr1__data_o$next[63:0]$10999 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr1__data_o$next[63:0]$10948 $1\msr1__data_o$next[63:0]$10942 + assign $7\msr1__data_o$next[63:0]$10999 $1\msr1__data_o$next[63:0]$10993 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10941 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10992 end - attribute \src "libresoc.v:175451.3-175486.6" - process $proc$libresoc.v:175451$10949 + attribute \src "libresoc.v:177547.3-177582.6" + process $proc$libresoc.v:177547$11000 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10950 $1\wr_detect$4[0:0]$10951 - attribute \src "libresoc.v:175452.5-175452.29" + assign $0\wr_detect$4[0:0]$11001 $1\wr_detect$4[0:0]$11002 + attribute \src "libresoc.v:177548.5-177548.29" switch \initial - attribute \src "libresoc.v:175452.9-175452.17" + attribute \src "libresoc.v:177548.9-177548.17" case 1'1 case end @@ -362857,58 +365728,58 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10951 $5\wr_detect$4[0:0]$10955 + assign $1\wr_detect$4[0:0]$11002 $5\wr_detect$4[0:0]$11006 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10952 1'1 + assign $2\wr_detect$4[0:0]$11003 1'1 case - assign $2\wr_detect$4[0:0]$10952 1'0 + assign $2\wr_detect$4[0:0]$11003 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10953 1'1 + assign $3\wr_detect$4[0:0]$11004 1'1 case - assign $3\wr_detect$4[0:0]$10953 $2\wr_detect$4[0:0]$10952 + assign $3\wr_detect$4[0:0]$11004 $2\wr_detect$4[0:0]$11003 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10954 1'1 + assign $4\wr_detect$4[0:0]$11005 1'1 case - assign $4\wr_detect$4[0:0]$10954 $3\wr_detect$4[0:0]$10953 + assign $4\wr_detect$4[0:0]$11005 $3\wr_detect$4[0:0]$11004 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10955 1'1 + assign $5\wr_detect$4[0:0]$11006 1'1 case - assign $5\wr_detect$4[0:0]$10955 $4\wr_detect$4[0:0]$10954 + assign $5\wr_detect$4[0:0]$11006 $4\wr_detect$4[0:0]$11005 end case - assign $1\wr_detect$4[0:0]$10951 1'0 + assign $1\wr_detect$4[0:0]$11002 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10950 + update \wr_detect$4 $0\wr_detect$4[0:0]$11001 end - attribute \src "libresoc.v:175487.3-175532.6" - process $proc$libresoc.v:175487$10956 + attribute \src "libresoc.v:177583.3-177628.6" + process $proc$libresoc.v:177583$11007 assign { } { } assign { } { } assign { } { } - assign $0\sv1__data_o$next[63:0]$10957 $7\sv1__data_o$next[63:0]$10964 - attribute \src "libresoc.v:175488.5-175488.29" + assign $0\sv1__data_o$next[63:0]$11008 $7\sv1__data_o$next[63:0]$11015 + attribute \src "libresoc.v:177584.5-177584.29" switch \initial - attribute \src "libresoc.v:175488.9-175488.17" + attribute \src "libresoc.v:177584.9-177584.17" case 1'1 case end @@ -362921,75 +365792,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\sv1__data_o$next[63:0]$10958 $6\sv1__data_o$next[63:0]$10963 + assign $1\sv1__data_o$next[63:0]$11009 $6\sv1__data_o$next[63:0]$11014 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv1__data_o$next[63:0]$10959 \nia1__data_i + assign $2\sv1__data_o$next[63:0]$11010 \nia1__data_i case - assign $2\sv1__data_o$next[63:0]$10959 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv1__data_o$next[63:0]$11010 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv1__data_o$next[63:0]$10960 \msr1__data_i + assign $3\sv1__data_o$next[63:0]$11011 \msr1__data_i case - assign $3\sv1__data_o$next[63:0]$10960 $2\sv1__data_o$next[63:0]$10959 + assign $3\sv1__data_o$next[63:0]$11011 $2\sv1__data_o$next[63:0]$11010 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv1__data_o$next[63:0]$10961 \sv1__data_i + assign $4\sv1__data_o$next[63:0]$11012 \sv1__data_i case - assign $4\sv1__data_o$next[63:0]$10961 $3\sv1__data_o$next[63:0]$10960 + assign $4\sv1__data_o$next[63:0]$11012 $3\sv1__data_o$next[63:0]$11011 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv1__data_o$next[63:0]$10962 \d_wr11__data_i + assign $5\sv1__data_o$next[63:0]$11013 \d_wr11__data_i case - assign $5\sv1__data_o$next[63:0]$10962 $4\sv1__data_o$next[63:0]$10961 + assign $5\sv1__data_o$next[63:0]$11013 $4\sv1__data_o$next[63:0]$11012 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv1__data_o$next[63:0]$10963 \reg + assign $6\sv1__data_o$next[63:0]$11014 \reg case - assign $6\sv1__data_o$next[63:0]$10963 $5\sv1__data_o$next[63:0]$10962 + assign $6\sv1__data_o$next[63:0]$11014 $5\sv1__data_o$next[63:0]$11013 end case - assign $1\sv1__data_o$next[63:0]$10958 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv1__data_o$next[63:0]$11009 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv1__data_o$next[63:0]$10964 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv1__data_o$next[63:0]$11015 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv1__data_o$next[63:0]$10964 $1\sv1__data_o$next[63:0]$10958 + assign $7\sv1__data_o$next[63:0]$11015 $1\sv1__data_o$next[63:0]$11009 end sync always - update \sv1__data_o$next $0\sv1__data_o$next[63:0]$10957 + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11008 end - attribute \src "libresoc.v:175533.3-175568.6" - process $proc$libresoc.v:175533$10965 + attribute \src "libresoc.v:177629.3-177664.6" + process $proc$libresoc.v:177629$11016 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10966 $1\wr_detect$7[0:0]$10967 - attribute \src "libresoc.v:175534.5-175534.29" + assign $0\wr_detect$7[0:0]$11017 $1\wr_detect$7[0:0]$11018 + attribute \src "libresoc.v:177630.5-177630.29" switch \initial - attribute \src "libresoc.v:175534.9-175534.17" + attribute \src "libresoc.v:177630.9-177630.17" case 1'1 case end @@ -363002,61 +365873,61 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10967 $5\wr_detect$7[0:0]$10971 + assign $1\wr_detect$7[0:0]$11018 $5\wr_detect$7[0:0]$11022 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10968 1'1 + assign $2\wr_detect$7[0:0]$11019 1'1 case - assign $2\wr_detect$7[0:0]$10968 1'0 + assign $2\wr_detect$7[0:0]$11019 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10969 1'1 + assign $3\wr_detect$7[0:0]$11020 1'1 case - assign $3\wr_detect$7[0:0]$10969 $2\wr_detect$7[0:0]$10968 + assign $3\wr_detect$7[0:0]$11020 $2\wr_detect$7[0:0]$11019 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10970 1'1 + assign $4\wr_detect$7[0:0]$11021 1'1 case - assign $4\wr_detect$7[0:0]$10970 $3\wr_detect$7[0:0]$10969 + assign $4\wr_detect$7[0:0]$11021 $3\wr_detect$7[0:0]$11020 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10971 1'1 + assign $5\wr_detect$7[0:0]$11022 1'1 case - assign $5\wr_detect$7[0:0]$10971 $4\wr_detect$7[0:0]$10970 + assign $5\wr_detect$7[0:0]$11022 $4\wr_detect$7[0:0]$11021 end case - assign $1\wr_detect$7[0:0]$10967 1'0 + assign $1\wr_detect$7[0:0]$11018 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10966 + update \wr_detect$7 $0\wr_detect$7[0:0]$11017 end - attribute \src "libresoc.v:175569.3-175601.6" - process $proc$libresoc.v:175569$10972 + attribute \src "libresoc.v:177665.3-177697.6" + process $proc$libresoc.v:177665$11023 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10973 $5\reg$next[63:0]$10978 - attribute \src "libresoc.v:175570.5-175570.29" + assign $0\reg$next[63:0]$11024 $5\reg$next[63:0]$11029 + attribute \src "libresoc.v:177666.5-177666.29" switch \initial - attribute \src "libresoc.v:175570.9-175570.17" + attribute \src "libresoc.v:177666.9-177666.17" case 1'1 case end @@ -363065,224 +365936,224 @@ module \reg_1$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10974 \nia1__data_i + assign $1\reg$next[63:0]$11025 \nia1__data_i case - assign $1\reg$next[63:0]$10974 \reg + assign $1\reg$next[63:0]$11025 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10975 \msr1__data_i + assign $2\reg$next[63:0]$11026 \msr1__data_i case - assign $2\reg$next[63:0]$10975 $1\reg$next[63:0]$10974 + assign $2\reg$next[63:0]$11026 $1\reg$next[63:0]$11025 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10976 \sv1__data_i + assign $3\reg$next[63:0]$11027 \sv1__data_i case - assign $3\reg$next[63:0]$10976 $2\reg$next[63:0]$10975 + assign $3\reg$next[63:0]$11027 $2\reg$next[63:0]$11026 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10977 \d_wr11__data_i + assign $4\reg$next[63:0]$11028 \d_wr11__data_i case - assign $4\reg$next[63:0]$10977 $3\reg$next[63:0]$10976 + assign $4\reg$next[63:0]$11028 $3\reg$next[63:0]$11027 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$10978 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11029 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$10978 $4\reg$next[63:0]$10977 + assign $5\reg$next[63:0]$11029 $4\reg$next[63:0]$11028 end sync always - update \reg$next $0\reg$next[63:0]$10973 + update \reg$next $0\reg$next[63:0]$11024 end - connect \$1 $not$libresoc.v:175312$10923_Y - connect \$3 $not$libresoc.v:175313$10924_Y - connect \$6 $not$libresoc.v:175314$10925_Y + connect \$1 $not$libresoc.v:177408$10974_Y + connect \$3 $not$libresoc.v:177409$10975_Y + connect \$6 $not$libresoc.v:177410$10976_Y end -attribute \src "libresoc.v:175606.1-176077.10" +attribute \src "libresoc.v:177702.1-178173.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:175607.7-175607.20" + attribute \src "libresoc.v:177703.7-177703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176007.3-176046.6" - wire width 4 $0\r22__data_o$next[3:0]$11053 - attribute \src "libresoc.v:175690.3-175691.39" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $0\r22__data_o$next[3:0]$11104 + attribute \src "libresoc.v:177786.3-177787.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:175937.3-175976.6" - wire width 4 $0\r2__data_o$next[3:0]$11039 - attribute \src "libresoc.v:175692.3-175693.37" + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $0\r2__data_o$next[3:0]$11090 + attribute \src "libresoc.v:177788.3-177789.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:175770.3-175796.6" - wire width 4 $0\reg$next[3:0]$11005 - attribute \src "libresoc.v:175688.3-175689.25" + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $0\reg$next[3:0]$11056 + attribute \src "libresoc.v:177784.3-177785.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:175700.3-175739.6" - wire width 4 $0\src12__data_o$next[3:0]$10996 - attribute \src "libresoc.v:175698.3-175699.43" + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $0\src12__data_o$next[3:0]$11047 + attribute \src "libresoc.v:177794.3-177795.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:175797.3-175836.6" - wire width 4 $0\src22__data_o$next[3:0]$11011 - attribute \src "libresoc.v:175696.3-175697.43" + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $0\src22__data_o$next[3:0]$11062 + attribute \src "libresoc.v:177792.3-177793.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:175867.3-175906.6" - wire width 4 $0\src32__data_o$next[3:0]$11025 - attribute \src "libresoc.v:175694.3-175695.43" + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $0\src32__data_o$next[3:0]$11076 + attribute \src "libresoc.v:177790.3-177791.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:175977.3-176006.6" - wire $0\wr_detect$10[0:0]$11047 - attribute \src "libresoc.v:176047.3-176076.6" - wire $0\wr_detect$13[0:0]$11061 - attribute \src "libresoc.v:175837.3-175866.6" - wire $0\wr_detect$4[0:0]$11019 - attribute \src "libresoc.v:175907.3-175936.6" - wire $0\wr_detect$7[0:0]$11033 - attribute \src "libresoc.v:175740.3-175769.6" + attribute \src "libresoc.v:178073.3-178102.6" + wire $0\wr_detect$10[0:0]$11098 + attribute \src "libresoc.v:178143.3-178172.6" + wire $0\wr_detect$13[0:0]$11112 + attribute \src "libresoc.v:177933.3-177962.6" + wire $0\wr_detect$4[0:0]$11070 + attribute \src "libresoc.v:178003.3-178032.6" + wire $0\wr_detect$7[0:0]$11084 + attribute \src "libresoc.v:177836.3-177865.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176007.3-176046.6" - wire width 4 $1\r22__data_o$next[3:0]$11054 - attribute \src "libresoc.v:175632.13-175632.31" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $1\r22__data_o$next[3:0]$11105 + attribute \src "libresoc.v:177728.13-177728.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:175937.3-175976.6" - wire width 4 $1\r2__data_o$next[3:0]$11040 - attribute \src "libresoc.v:175639.13-175639.30" + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $1\r2__data_o$next[3:0]$11091 + attribute \src "libresoc.v:177735.13-177735.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:175770.3-175796.6" - wire width 4 $1\reg$next[3:0]$11006 - attribute \src "libresoc.v:175645.13-175645.25" + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $1\reg$next[3:0]$11057 + attribute \src "libresoc.v:177741.13-177741.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:175700.3-175739.6" - wire width 4 $1\src12__data_o$next[3:0]$10997 - attribute \src "libresoc.v:175650.13-175650.33" + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $1\src12__data_o$next[3:0]$11048 + attribute \src "libresoc.v:177746.13-177746.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:175797.3-175836.6" - wire width 4 $1\src22__data_o$next[3:0]$11012 - attribute \src "libresoc.v:175657.13-175657.33" + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $1\src22__data_o$next[3:0]$11063 + attribute \src "libresoc.v:177753.13-177753.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:175867.3-175906.6" - wire width 4 $1\src32__data_o$next[3:0]$11026 - attribute \src "libresoc.v:175664.13-175664.33" + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $1\src32__data_o$next[3:0]$11077 + attribute \src "libresoc.v:177760.13-177760.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:175977.3-176006.6" - wire $1\wr_detect$10[0:0]$11048 - attribute \src "libresoc.v:176047.3-176076.6" - wire $1\wr_detect$13[0:0]$11062 - attribute \src "libresoc.v:175837.3-175866.6" - wire $1\wr_detect$4[0:0]$11020 - attribute \src "libresoc.v:175907.3-175936.6" - wire $1\wr_detect$7[0:0]$11034 - attribute \src "libresoc.v:175740.3-175769.6" + attribute \src "libresoc.v:178073.3-178102.6" + wire $1\wr_detect$10[0:0]$11099 + attribute \src "libresoc.v:178143.3-178172.6" + wire $1\wr_detect$13[0:0]$11113 + attribute \src "libresoc.v:177933.3-177962.6" + wire $1\wr_detect$4[0:0]$11071 + attribute \src "libresoc.v:178003.3-178032.6" + wire $1\wr_detect$7[0:0]$11085 + attribute \src "libresoc.v:177836.3-177865.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176007.3-176046.6" - wire width 4 $2\r22__data_o$next[3:0]$11055 - attribute \src "libresoc.v:175937.3-175976.6" - wire width 4 $2\r2__data_o$next[3:0]$11041 - attribute \src "libresoc.v:175770.3-175796.6" - wire width 4 $2\reg$next[3:0]$11007 - attribute \src "libresoc.v:175700.3-175739.6" - wire width 4 $2\src12__data_o$next[3:0]$10998 - attribute \src "libresoc.v:175797.3-175836.6" - wire width 4 $2\src22__data_o$next[3:0]$11013 - attribute \src "libresoc.v:175867.3-175906.6" - wire width 4 $2\src32__data_o$next[3:0]$11027 - attribute \src "libresoc.v:175977.3-176006.6" - wire $2\wr_detect$10[0:0]$11049 - attribute \src "libresoc.v:176047.3-176076.6" - wire $2\wr_detect$13[0:0]$11063 - attribute \src "libresoc.v:175837.3-175866.6" - wire $2\wr_detect$4[0:0]$11021 - attribute \src "libresoc.v:175907.3-175936.6" - wire $2\wr_detect$7[0:0]$11035 - attribute \src "libresoc.v:175740.3-175769.6" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $2\r22__data_o$next[3:0]$11106 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $2\r2__data_o$next[3:0]$11092 + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $2\reg$next[3:0]$11058 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $2\src12__data_o$next[3:0]$11049 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $2\src22__data_o$next[3:0]$11064 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $2\src32__data_o$next[3:0]$11078 + attribute \src "libresoc.v:178073.3-178102.6" + wire $2\wr_detect$10[0:0]$11100 + attribute \src "libresoc.v:178143.3-178172.6" + wire $2\wr_detect$13[0:0]$11114 + attribute \src "libresoc.v:177933.3-177962.6" + wire $2\wr_detect$4[0:0]$11072 + attribute \src "libresoc.v:178003.3-178032.6" + wire $2\wr_detect$7[0:0]$11086 + attribute \src "libresoc.v:177836.3-177865.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176007.3-176046.6" - wire width 4 $3\r22__data_o$next[3:0]$11056 - attribute \src "libresoc.v:175937.3-175976.6" - wire width 4 $3\r2__data_o$next[3:0]$11042 - attribute \src "libresoc.v:175770.3-175796.6" - wire width 4 $3\reg$next[3:0]$11008 - attribute \src "libresoc.v:175700.3-175739.6" - wire width 4 $3\src12__data_o$next[3:0]$10999 - attribute \src "libresoc.v:175797.3-175836.6" - wire width 4 $3\src22__data_o$next[3:0]$11014 - attribute \src "libresoc.v:175867.3-175906.6" - wire width 4 $3\src32__data_o$next[3:0]$11028 - attribute \src "libresoc.v:175977.3-176006.6" - wire $3\wr_detect$10[0:0]$11050 - attribute \src "libresoc.v:176047.3-176076.6" - wire $3\wr_detect$13[0:0]$11064 - attribute \src "libresoc.v:175837.3-175866.6" - wire $3\wr_detect$4[0:0]$11022 - attribute \src "libresoc.v:175907.3-175936.6" - wire $3\wr_detect$7[0:0]$11036 - attribute \src "libresoc.v:175740.3-175769.6" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $3\r22__data_o$next[3:0]$11107 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $3\r2__data_o$next[3:0]$11093 + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $3\reg$next[3:0]$11059 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $3\src12__data_o$next[3:0]$11050 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $3\src22__data_o$next[3:0]$11065 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $3\src32__data_o$next[3:0]$11079 + attribute \src "libresoc.v:178073.3-178102.6" + wire $3\wr_detect$10[0:0]$11101 + attribute \src "libresoc.v:178143.3-178172.6" + wire $3\wr_detect$13[0:0]$11115 + attribute \src "libresoc.v:177933.3-177962.6" + wire $3\wr_detect$4[0:0]$11073 + attribute \src "libresoc.v:178003.3-178032.6" + wire $3\wr_detect$7[0:0]$11087 + attribute \src "libresoc.v:177836.3-177865.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176007.3-176046.6" - wire width 4 $4\r22__data_o$next[3:0]$11057 - attribute \src "libresoc.v:175937.3-175976.6" - wire width 4 $4\r2__data_o$next[3:0]$11043 - attribute \src "libresoc.v:175770.3-175796.6" - wire width 4 $4\reg$next[3:0]$11009 - attribute \src "libresoc.v:175700.3-175739.6" - wire width 4 $4\src12__data_o$next[3:0]$11000 - attribute \src "libresoc.v:175797.3-175836.6" - wire width 4 $4\src22__data_o$next[3:0]$11015 - attribute \src "libresoc.v:175867.3-175906.6" - wire width 4 $4\src32__data_o$next[3:0]$11029 - attribute \src "libresoc.v:175977.3-176006.6" - wire $4\wr_detect$10[0:0]$11051 - attribute \src "libresoc.v:176047.3-176076.6" - wire $4\wr_detect$13[0:0]$11065 - attribute \src "libresoc.v:175837.3-175866.6" - wire $4\wr_detect$4[0:0]$11023 - attribute \src "libresoc.v:175907.3-175936.6" - wire $4\wr_detect$7[0:0]$11037 - attribute \src "libresoc.v:175740.3-175769.6" + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $4\r22__data_o$next[3:0]$11108 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $4\r2__data_o$next[3:0]$11094 + attribute \src "libresoc.v:177866.3-177892.6" + wire width 4 $4\reg$next[3:0]$11060 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $4\src12__data_o$next[3:0]$11051 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $4\src22__data_o$next[3:0]$11066 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $4\src32__data_o$next[3:0]$11080 + attribute \src "libresoc.v:178073.3-178102.6" + wire $4\wr_detect$10[0:0]$11102 + attribute \src "libresoc.v:178143.3-178172.6" + wire $4\wr_detect$13[0:0]$11116 + attribute \src "libresoc.v:177933.3-177962.6" + wire $4\wr_detect$4[0:0]$11074 + attribute \src "libresoc.v:178003.3-178032.6" + wire $4\wr_detect$7[0:0]$11088 + attribute \src "libresoc.v:177836.3-177865.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176007.3-176046.6" - wire width 4 $5\r22__data_o$next[3:0]$11058 - attribute \src "libresoc.v:175937.3-175976.6" - wire width 4 $5\r2__data_o$next[3:0]$11044 - attribute \src "libresoc.v:175700.3-175739.6" - wire width 4 $5\src12__data_o$next[3:0]$11001 - attribute \src "libresoc.v:175797.3-175836.6" - wire width 4 $5\src22__data_o$next[3:0]$11016 - attribute \src "libresoc.v:175867.3-175906.6" - wire width 4 $5\src32__data_o$next[3:0]$11030 - attribute \src "libresoc.v:176007.3-176046.6" - wire width 4 $6\r22__data_o$next[3:0]$11059 - attribute \src "libresoc.v:175937.3-175976.6" - wire width 4 $6\r2__data_o$next[3:0]$11045 - attribute \src "libresoc.v:175700.3-175739.6" - wire width 4 $6\src12__data_o$next[3:0]$11002 - attribute \src "libresoc.v:175797.3-175836.6" - wire width 4 $6\src22__data_o$next[3:0]$11017 - attribute \src "libresoc.v:175867.3-175906.6" - wire width 4 $6\src32__data_o$next[3:0]$11031 - attribute \src "libresoc.v:175683.17-175683.104" - wire $not$libresoc.v:175683$10984_Y - attribute \src "libresoc.v:175684.18-175684.105" - wire $not$libresoc.v:175684$10985_Y - attribute \src "libresoc.v:175685.17-175685.100" - wire $not$libresoc.v:175685$10986_Y - attribute \src "libresoc.v:175686.17-175686.103" - wire $not$libresoc.v:175686$10987_Y - attribute \src "libresoc.v:175687.17-175687.103" - wire $not$libresoc.v:175687$10988_Y + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $5\r22__data_o$next[3:0]$11109 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $5\r2__data_o$next[3:0]$11095 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $5\src12__data_o$next[3:0]$11052 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $5\src22__data_o$next[3:0]$11067 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $5\src32__data_o$next[3:0]$11081 + attribute \src "libresoc.v:178103.3-178142.6" + wire width 4 $6\r22__data_o$next[3:0]$11110 + attribute \src "libresoc.v:178033.3-178072.6" + wire width 4 $6\r2__data_o$next[3:0]$11096 + attribute \src "libresoc.v:177796.3-177835.6" + wire width 4 $6\src12__data_o$next[3:0]$11053 + attribute \src "libresoc.v:177893.3-177932.6" + wire width 4 $6\src22__data_o$next[3:0]$11068 + attribute \src "libresoc.v:177963.3-178002.6" + wire width 4 $6\src32__data_o$next[3:0]$11082 + attribute \src "libresoc.v:177779.17-177779.104" + wire $not$libresoc.v:177779$11035_Y + attribute \src "libresoc.v:177780.18-177780.105" + wire $not$libresoc.v:177780$11036_Y + attribute \src "libresoc.v:177781.17-177781.100" + wire $not$libresoc.v:177781$11037_Y + attribute \src "libresoc.v:177782.17-177782.103" + wire $not$libresoc.v:177782$11038_Y + attribute \src "libresoc.v:177783.17-177783.103" + wire $not$libresoc.v:177783$11039_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -363293,9 +366164,9 @@ module \reg_2 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest12__data_i @@ -363305,7 +366176,7 @@ module \reg_2 wire width 4 input 11 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest22__wen - attribute \src "libresoc.v:175607.7-175607.15" + attribute \src "libresoc.v:177703.7-177703.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r22__data_o @@ -363356,152 +366227,152 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175683$10984 + cell $not $not$libresoc.v:177779$11035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:175683$10984_Y + connect \Y $not$libresoc.v:177779$11035_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175684$10985 + cell $not $not$libresoc.v:177780$11036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:175684$10985_Y + connect \Y $not$libresoc.v:177780$11036_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175685$10986 + cell $not $not$libresoc.v:177781$11037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:175685$10986_Y + connect \Y $not$libresoc.v:177781$11037_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175686$10987 + cell $not $not$libresoc.v:177782$11038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:175686$10987_Y + connect \Y $not$libresoc.v:177782$11038_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175687$10988 + cell $not $not$libresoc.v:177783$11039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:175687$10988_Y + connect \Y $not$libresoc.v:177783$11039_Y end - attribute \src "libresoc.v:175607.7-175607.20" - process $proc$libresoc.v:175607$11066 + attribute \src "libresoc.v:177703.7-177703.20" + process $proc$libresoc.v:177703$11117 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175632.13-175632.31" - process $proc$libresoc.v:175632$11067 + attribute \src "libresoc.v:177728.13-177728.31" + process $proc$libresoc.v:177728$11118 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:175639.13-175639.30" - process $proc$libresoc.v:175639$11068 + attribute \src "libresoc.v:177735.13-177735.30" + process $proc$libresoc.v:177735$11119 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:175645.13-175645.25" - process $proc$libresoc.v:175645$11069 + attribute \src "libresoc.v:177741.13-177741.25" + process $proc$libresoc.v:177741$11120 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:175650.13-175650.33" - process $proc$libresoc.v:175650$11070 + attribute \src "libresoc.v:177746.13-177746.33" + process $proc$libresoc.v:177746$11121 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:175657.13-175657.33" - process $proc$libresoc.v:175657$11071 + attribute \src "libresoc.v:177753.13-177753.33" + process $proc$libresoc.v:177753$11122 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:175664.13-175664.33" - process $proc$libresoc.v:175664$11072 + attribute \src "libresoc.v:177760.13-177760.33" + process $proc$libresoc.v:177760$11123 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:175688.3-175689.25" - process $proc$libresoc.v:175688$10989 + attribute \src "libresoc.v:177784.3-177785.25" + process $proc$libresoc.v:177784$11040 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:175690.3-175691.39" - process $proc$libresoc.v:175690$10990 + attribute \src "libresoc.v:177786.3-177787.39" + process $proc$libresoc.v:177786$11041 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:175692.3-175693.37" - process $proc$libresoc.v:175692$10991 + attribute \src "libresoc.v:177788.3-177789.37" + process $proc$libresoc.v:177788$11042 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:175694.3-175695.43" - process $proc$libresoc.v:175694$10992 + attribute \src "libresoc.v:177790.3-177791.43" + process $proc$libresoc.v:177790$11043 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:175696.3-175697.43" - process $proc$libresoc.v:175696$10993 + attribute \src "libresoc.v:177792.3-177793.43" + process $proc$libresoc.v:177792$11044 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:175698.3-175699.43" - process $proc$libresoc.v:175698$10994 + attribute \src "libresoc.v:177794.3-177795.43" + process $proc$libresoc.v:177794$11045 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:175700.3-175739.6" - process $proc$libresoc.v:175700$10995 + attribute \src "libresoc.v:177796.3-177835.6" + process $proc$libresoc.v:177796$11046 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[3:0]$10996 $6\src12__data_o$next[3:0]$11002 - attribute \src "libresoc.v:175701.5-175701.29" + assign $0\src12__data_o$next[3:0]$11047 $6\src12__data_o$next[3:0]$11053 + attribute \src "libresoc.v:177797.5-177797.29" switch \initial - attribute \src "libresoc.v:175701.9-175701.17" + attribute \src "libresoc.v:177797.9-177797.17" case 1'1 case end @@ -363513,66 +366384,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[3:0]$10997 $5\src12__data_o$next[3:0]$11001 + assign $1\src12__data_o$next[3:0]$11048 $5\src12__data_o$next[3:0]$11052 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[3:0]$10998 \dest12__data_i + assign $2\src12__data_o$next[3:0]$11049 \dest12__data_i case - assign $2\src12__data_o$next[3:0]$10998 4'0000 + assign $2\src12__data_o$next[3:0]$11049 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[3:0]$10999 \dest22__data_i + assign $3\src12__data_o$next[3:0]$11050 \dest22__data_i case - assign $3\src12__data_o$next[3:0]$10999 $2\src12__data_o$next[3:0]$10998 + assign $3\src12__data_o$next[3:0]$11050 $2\src12__data_o$next[3:0]$11049 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[3:0]$11000 \w2__data_i + assign $4\src12__data_o$next[3:0]$11051 \w2__data_i case - assign $4\src12__data_o$next[3:0]$11000 $3\src12__data_o$next[3:0]$10999 + assign $4\src12__data_o$next[3:0]$11051 $3\src12__data_o$next[3:0]$11050 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[3:0]$11001 \reg + assign $5\src12__data_o$next[3:0]$11052 \reg case - assign $5\src12__data_o$next[3:0]$11001 $4\src12__data_o$next[3:0]$11000 + assign $5\src12__data_o$next[3:0]$11052 $4\src12__data_o$next[3:0]$11051 end case - assign $1\src12__data_o$next[3:0]$10997 4'0000 + assign $1\src12__data_o$next[3:0]$11048 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$11002 4'0000 + assign $6\src12__data_o$next[3:0]$11053 4'0000 case - assign $6\src12__data_o$next[3:0]$11002 $1\src12__data_o$next[3:0]$10997 + assign $6\src12__data_o$next[3:0]$11053 $1\src12__data_o$next[3:0]$11048 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$10996 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11047 end - attribute \src "libresoc.v:175740.3-175769.6" - process $proc$libresoc.v:175740$11003 + attribute \src "libresoc.v:177836.3-177865.6" + process $proc$libresoc.v:177836$11054 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:175741.5-175741.29" + attribute \src "libresoc.v:177837.5-177837.29" switch \initial - attribute \src "libresoc.v:175741.9-175741.17" + attribute \src "libresoc.v:177837.9-177837.17" case 1'1 case end @@ -363618,17 +366489,17 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:175770.3-175796.6" - process $proc$libresoc.v:175770$11004 + attribute \src "libresoc.v:177866.3-177892.6" + process $proc$libresoc.v:177866$11055 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11005 $4\reg$next[3:0]$11009 - attribute \src "libresoc.v:175771.5-175771.29" + assign $0\reg$next[3:0]$11056 $4\reg$next[3:0]$11060 + attribute \src "libresoc.v:177867.5-177867.29" switch \initial - attribute \src "libresoc.v:175771.9-175771.17" + attribute \src "libresoc.v:177867.9-177867.17" case 1'1 case end @@ -363637,49 +366508,49 @@ module \reg_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11006 \dest12__data_i + assign $1\reg$next[3:0]$11057 \dest12__data_i case - assign $1\reg$next[3:0]$11006 \reg + assign $1\reg$next[3:0]$11057 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11007 \dest22__data_i + assign $2\reg$next[3:0]$11058 \dest22__data_i case - assign $2\reg$next[3:0]$11007 $1\reg$next[3:0]$11006 + assign $2\reg$next[3:0]$11058 $1\reg$next[3:0]$11057 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11008 \w2__data_i + assign $3\reg$next[3:0]$11059 \w2__data_i case - assign $3\reg$next[3:0]$11008 $2\reg$next[3:0]$11007 + assign $3\reg$next[3:0]$11059 $2\reg$next[3:0]$11058 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11009 4'0000 + assign $4\reg$next[3:0]$11060 4'0000 case - assign $4\reg$next[3:0]$11009 $3\reg$next[3:0]$11008 + assign $4\reg$next[3:0]$11060 $3\reg$next[3:0]$11059 end sync always - update \reg$next $0\reg$next[3:0]$11005 + update \reg$next $0\reg$next[3:0]$11056 end - attribute \src "libresoc.v:175797.3-175836.6" - process $proc$libresoc.v:175797$11010 + attribute \src "libresoc.v:177893.3-177932.6" + process $proc$libresoc.v:177893$11061 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$11011 $6\src22__data_o$next[3:0]$11017 - attribute \src "libresoc.v:175798.5-175798.29" + assign $0\src22__data_o$next[3:0]$11062 $6\src22__data_o$next[3:0]$11068 + attribute \src "libresoc.v:177894.5-177894.29" switch \initial - attribute \src "libresoc.v:175798.9-175798.17" + attribute \src "libresoc.v:177894.9-177894.17" case 1'1 case end @@ -363691,66 +366562,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$11012 $5\src22__data_o$next[3:0]$11016 + assign $1\src22__data_o$next[3:0]$11063 $5\src22__data_o$next[3:0]$11067 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$11013 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11064 \dest12__data_i case - assign $2\src22__data_o$next[3:0]$11013 4'0000 + assign $2\src22__data_o$next[3:0]$11064 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$11014 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11065 \dest22__data_i case - assign $3\src22__data_o$next[3:0]$11014 $2\src22__data_o$next[3:0]$11013 + assign $3\src22__data_o$next[3:0]$11065 $2\src22__data_o$next[3:0]$11064 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$11015 \w2__data_i + assign $4\src22__data_o$next[3:0]$11066 \w2__data_i case - assign $4\src22__data_o$next[3:0]$11015 $3\src22__data_o$next[3:0]$11014 + assign $4\src22__data_o$next[3:0]$11066 $3\src22__data_o$next[3:0]$11065 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$11016 \reg + assign $5\src22__data_o$next[3:0]$11067 \reg case - assign $5\src22__data_o$next[3:0]$11016 $4\src22__data_o$next[3:0]$11015 + assign $5\src22__data_o$next[3:0]$11067 $4\src22__data_o$next[3:0]$11066 end case - assign $1\src22__data_o$next[3:0]$11012 4'0000 + assign $1\src22__data_o$next[3:0]$11063 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$11017 4'0000 + assign $6\src22__data_o$next[3:0]$11068 4'0000 case - assign $6\src22__data_o$next[3:0]$11017 $1\src22__data_o$next[3:0]$11012 + assign $6\src22__data_o$next[3:0]$11068 $1\src22__data_o$next[3:0]$11063 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$11011 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11062 end - attribute \src "libresoc.v:175837.3-175866.6" - process $proc$libresoc.v:175837$11018 + attribute \src "libresoc.v:177933.3-177962.6" + process $proc$libresoc.v:177933$11069 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11019 $1\wr_detect$4[0:0]$11020 - attribute \src "libresoc.v:175838.5-175838.29" + assign $0\wr_detect$4[0:0]$11070 $1\wr_detect$4[0:0]$11071 + attribute \src "libresoc.v:177934.5-177934.29" switch \initial - attribute \src "libresoc.v:175838.9-175838.17" + attribute \src "libresoc.v:177934.9-177934.17" case 1'1 case end @@ -363762,49 +366633,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11020 $4\wr_detect$4[0:0]$11023 + assign $1\wr_detect$4[0:0]$11071 $4\wr_detect$4[0:0]$11074 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11021 1'1 + assign $2\wr_detect$4[0:0]$11072 1'1 case - assign $2\wr_detect$4[0:0]$11021 1'0 + assign $2\wr_detect$4[0:0]$11072 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11022 1'1 + assign $3\wr_detect$4[0:0]$11073 1'1 case - assign $3\wr_detect$4[0:0]$11022 $2\wr_detect$4[0:0]$11021 + assign $3\wr_detect$4[0:0]$11073 $2\wr_detect$4[0:0]$11072 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11023 1'1 + assign $4\wr_detect$4[0:0]$11074 1'1 case - assign $4\wr_detect$4[0:0]$11023 $3\wr_detect$4[0:0]$11022 + assign $4\wr_detect$4[0:0]$11074 $3\wr_detect$4[0:0]$11073 end case - assign $1\wr_detect$4[0:0]$11020 1'0 + assign $1\wr_detect$4[0:0]$11071 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11019 + update \wr_detect$4 $0\wr_detect$4[0:0]$11070 end - attribute \src "libresoc.v:175867.3-175906.6" - process $proc$libresoc.v:175867$11024 + attribute \src "libresoc.v:177963.3-178002.6" + process $proc$libresoc.v:177963$11075 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$11025 $6\src32__data_o$next[3:0]$11031 - attribute \src "libresoc.v:175868.5-175868.29" + assign $0\src32__data_o$next[3:0]$11076 $6\src32__data_o$next[3:0]$11082 + attribute \src "libresoc.v:177964.5-177964.29" switch \initial - attribute \src "libresoc.v:175868.9-175868.17" + attribute \src "libresoc.v:177964.9-177964.17" case 1'1 case end @@ -363816,66 +366687,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$11026 $5\src32__data_o$next[3:0]$11030 + assign $1\src32__data_o$next[3:0]$11077 $5\src32__data_o$next[3:0]$11081 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$11027 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11078 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$11027 4'0000 + assign $2\src32__data_o$next[3:0]$11078 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$11028 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11079 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$11028 $2\src32__data_o$next[3:0]$11027 + assign $3\src32__data_o$next[3:0]$11079 $2\src32__data_o$next[3:0]$11078 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$11029 \w2__data_i + assign $4\src32__data_o$next[3:0]$11080 \w2__data_i case - assign $4\src32__data_o$next[3:0]$11029 $3\src32__data_o$next[3:0]$11028 + assign $4\src32__data_o$next[3:0]$11080 $3\src32__data_o$next[3:0]$11079 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$11030 \reg + assign $5\src32__data_o$next[3:0]$11081 \reg case - assign $5\src32__data_o$next[3:0]$11030 $4\src32__data_o$next[3:0]$11029 + assign $5\src32__data_o$next[3:0]$11081 $4\src32__data_o$next[3:0]$11080 end case - assign $1\src32__data_o$next[3:0]$11026 4'0000 + assign $1\src32__data_o$next[3:0]$11077 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$11031 4'0000 + assign $6\src32__data_o$next[3:0]$11082 4'0000 case - assign $6\src32__data_o$next[3:0]$11031 $1\src32__data_o$next[3:0]$11026 + assign $6\src32__data_o$next[3:0]$11082 $1\src32__data_o$next[3:0]$11077 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$11025 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11076 end - attribute \src "libresoc.v:175907.3-175936.6" - process $proc$libresoc.v:175907$11032 + attribute \src "libresoc.v:178003.3-178032.6" + process $proc$libresoc.v:178003$11083 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11033 $1\wr_detect$7[0:0]$11034 - attribute \src "libresoc.v:175908.5-175908.29" + assign $0\wr_detect$7[0:0]$11084 $1\wr_detect$7[0:0]$11085 + attribute \src "libresoc.v:178004.5-178004.29" switch \initial - attribute \src "libresoc.v:175908.9-175908.17" + attribute \src "libresoc.v:178004.9-178004.17" case 1'1 case end @@ -363887,49 +366758,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11034 $4\wr_detect$7[0:0]$11037 + assign $1\wr_detect$7[0:0]$11085 $4\wr_detect$7[0:0]$11088 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11035 1'1 + assign $2\wr_detect$7[0:0]$11086 1'1 case - assign $2\wr_detect$7[0:0]$11035 1'0 + assign $2\wr_detect$7[0:0]$11086 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11036 1'1 + assign $3\wr_detect$7[0:0]$11087 1'1 case - assign $3\wr_detect$7[0:0]$11036 $2\wr_detect$7[0:0]$11035 + assign $3\wr_detect$7[0:0]$11087 $2\wr_detect$7[0:0]$11086 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11037 1'1 + assign $4\wr_detect$7[0:0]$11088 1'1 case - assign $4\wr_detect$7[0:0]$11037 $3\wr_detect$7[0:0]$11036 + assign $4\wr_detect$7[0:0]$11088 $3\wr_detect$7[0:0]$11087 end case - assign $1\wr_detect$7[0:0]$11034 1'0 + assign $1\wr_detect$7[0:0]$11085 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11033 + update \wr_detect$7 $0\wr_detect$7[0:0]$11084 end - attribute \src "libresoc.v:175937.3-175976.6" - process $proc$libresoc.v:175937$11038 + attribute \src "libresoc.v:178033.3-178072.6" + process $proc$libresoc.v:178033$11089 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11039 $6\r2__data_o$next[3:0]$11045 - attribute \src "libresoc.v:175938.5-175938.29" + assign $0\r2__data_o$next[3:0]$11090 $6\r2__data_o$next[3:0]$11096 + attribute \src "libresoc.v:178034.5-178034.29" switch \initial - attribute \src "libresoc.v:175938.9-175938.17" + attribute \src "libresoc.v:178034.9-178034.17" case 1'1 case end @@ -363941,66 +366812,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$11040 $5\r2__data_o$next[3:0]$11044 + assign $1\r2__data_o$next[3:0]$11091 $5\r2__data_o$next[3:0]$11095 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$11041 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11092 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$11041 4'0000 + assign $2\r2__data_o$next[3:0]$11092 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$11042 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11093 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$11042 $2\r2__data_o$next[3:0]$11041 + assign $3\r2__data_o$next[3:0]$11093 $2\r2__data_o$next[3:0]$11092 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$11043 \w2__data_i + assign $4\r2__data_o$next[3:0]$11094 \w2__data_i case - assign $4\r2__data_o$next[3:0]$11043 $3\r2__data_o$next[3:0]$11042 + assign $4\r2__data_o$next[3:0]$11094 $3\r2__data_o$next[3:0]$11093 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$11044 \reg + assign $5\r2__data_o$next[3:0]$11095 \reg case - assign $5\r2__data_o$next[3:0]$11044 $4\r2__data_o$next[3:0]$11043 + assign $5\r2__data_o$next[3:0]$11095 $4\r2__data_o$next[3:0]$11094 end case - assign $1\r2__data_o$next[3:0]$11040 4'0000 + assign $1\r2__data_o$next[3:0]$11091 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$11045 4'0000 + assign $6\r2__data_o$next[3:0]$11096 4'0000 case - assign $6\r2__data_o$next[3:0]$11045 $1\r2__data_o$next[3:0]$11040 + assign $6\r2__data_o$next[3:0]$11096 $1\r2__data_o$next[3:0]$11091 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11039 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11090 end - attribute \src "libresoc.v:175977.3-176006.6" - process $proc$libresoc.v:175977$11046 + attribute \src "libresoc.v:178073.3-178102.6" + process $proc$libresoc.v:178073$11097 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11047 $1\wr_detect$10[0:0]$11048 - attribute \src "libresoc.v:175978.5-175978.29" + assign $0\wr_detect$10[0:0]$11098 $1\wr_detect$10[0:0]$11099 + attribute \src "libresoc.v:178074.5-178074.29" switch \initial - attribute \src "libresoc.v:175978.9-175978.17" + attribute \src "libresoc.v:178074.9-178074.17" case 1'1 case end @@ -364012,49 +366883,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11048 $4\wr_detect$10[0:0]$11051 + assign $1\wr_detect$10[0:0]$11099 $4\wr_detect$10[0:0]$11102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11049 1'1 + assign $2\wr_detect$10[0:0]$11100 1'1 case - assign $2\wr_detect$10[0:0]$11049 1'0 + assign $2\wr_detect$10[0:0]$11100 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11050 1'1 + assign $3\wr_detect$10[0:0]$11101 1'1 case - assign $3\wr_detect$10[0:0]$11050 $2\wr_detect$10[0:0]$11049 + assign $3\wr_detect$10[0:0]$11101 $2\wr_detect$10[0:0]$11100 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11051 1'1 + assign $4\wr_detect$10[0:0]$11102 1'1 case - assign $4\wr_detect$10[0:0]$11051 $3\wr_detect$10[0:0]$11050 + assign $4\wr_detect$10[0:0]$11102 $3\wr_detect$10[0:0]$11101 end case - assign $1\wr_detect$10[0:0]$11048 1'0 + assign $1\wr_detect$10[0:0]$11099 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11047 + update \wr_detect$10 $0\wr_detect$10[0:0]$11098 end - attribute \src "libresoc.v:176007.3-176046.6" - process $proc$libresoc.v:176007$11052 + attribute \src "libresoc.v:178103.3-178142.6" + process $proc$libresoc.v:178103$11103 assign { } { } assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$11053 $6\r22__data_o$next[3:0]$11059 - attribute \src "libresoc.v:176008.5-176008.29" + assign $0\r22__data_o$next[3:0]$11104 $6\r22__data_o$next[3:0]$11110 + attribute \src "libresoc.v:178104.5-178104.29" switch \initial - attribute \src "libresoc.v:176008.9-176008.17" + attribute \src "libresoc.v:178104.9-178104.17" case 1'1 case end @@ -364066,66 +366937,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r22__data_o$next[3:0]$11054 $5\r22__data_o$next[3:0]$11058 + assign $1\r22__data_o$next[3:0]$11105 $5\r22__data_o$next[3:0]$11109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r22__data_o$next[3:0]$11055 \dest12__data_i + assign $2\r22__data_o$next[3:0]$11106 \dest12__data_i case - assign $2\r22__data_o$next[3:0]$11055 4'0000 + assign $2\r22__data_o$next[3:0]$11106 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r22__data_o$next[3:0]$11056 \dest22__data_i + assign $3\r22__data_o$next[3:0]$11107 \dest22__data_i case - assign $3\r22__data_o$next[3:0]$11056 $2\r22__data_o$next[3:0]$11055 + assign $3\r22__data_o$next[3:0]$11107 $2\r22__data_o$next[3:0]$11106 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r22__data_o$next[3:0]$11057 \w2__data_i + assign $4\r22__data_o$next[3:0]$11108 \w2__data_i case - assign $4\r22__data_o$next[3:0]$11057 $3\r22__data_o$next[3:0]$11056 + assign $4\r22__data_o$next[3:0]$11108 $3\r22__data_o$next[3:0]$11107 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r22__data_o$next[3:0]$11058 \reg + assign $5\r22__data_o$next[3:0]$11109 \reg case - assign $5\r22__data_o$next[3:0]$11058 $4\r22__data_o$next[3:0]$11057 + assign $5\r22__data_o$next[3:0]$11109 $4\r22__data_o$next[3:0]$11108 end case - assign $1\r22__data_o$next[3:0]$11054 4'0000 + assign $1\r22__data_o$next[3:0]$11105 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r22__data_o$next[3:0]$11059 4'0000 + assign $6\r22__data_o$next[3:0]$11110 4'0000 case - assign $6\r22__data_o$next[3:0]$11059 $1\r22__data_o$next[3:0]$11054 + assign $6\r22__data_o$next[3:0]$11110 $1\r22__data_o$next[3:0]$11105 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11053 + update \r22__data_o$next $0\r22__data_o$next[3:0]$11104 end - attribute \src "libresoc.v:176047.3-176076.6" - process $proc$libresoc.v:176047$11060 + attribute \src "libresoc.v:178143.3-178172.6" + process $proc$libresoc.v:178143$11111 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11061 $1\wr_detect$13[0:0]$11062 - attribute \src "libresoc.v:176048.5-176048.29" + assign $0\wr_detect$13[0:0]$11112 $1\wr_detect$13[0:0]$11113 + attribute \src "libresoc.v:178144.5-178144.29" switch \initial - attribute \src "libresoc.v:176048.9-176048.17" + attribute \src "libresoc.v:178144.9-178144.17" case 1'1 case end @@ -364137,205 +367008,205 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11062 $4\wr_detect$13[0:0]$11065 + assign $1\wr_detect$13[0:0]$11113 $4\wr_detect$13[0:0]$11116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11063 1'1 + assign $2\wr_detect$13[0:0]$11114 1'1 case - assign $2\wr_detect$13[0:0]$11063 1'0 + assign $2\wr_detect$13[0:0]$11114 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11064 1'1 + assign $3\wr_detect$13[0:0]$11115 1'1 case - assign $3\wr_detect$13[0:0]$11064 $2\wr_detect$13[0:0]$11063 + assign $3\wr_detect$13[0:0]$11115 $2\wr_detect$13[0:0]$11114 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11065 1'1 + assign $4\wr_detect$13[0:0]$11116 1'1 case - assign $4\wr_detect$13[0:0]$11065 $3\wr_detect$13[0:0]$11064 + assign $4\wr_detect$13[0:0]$11116 $3\wr_detect$13[0:0]$11115 end case - assign $1\wr_detect$13[0:0]$11062 1'0 + assign $1\wr_detect$13[0:0]$11113 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11061 + update \wr_detect$13 $0\wr_detect$13[0:0]$11112 end - connect \$9 $not$libresoc.v:175683$10984_Y - connect \$12 $not$libresoc.v:175684$10985_Y - connect \$1 $not$libresoc.v:175685$10986_Y - connect \$3 $not$libresoc.v:175686$10987_Y - connect \$6 $not$libresoc.v:175687$10988_Y + connect \$9 $not$libresoc.v:177779$11035_Y + connect \$12 $not$libresoc.v:177780$11036_Y + connect \$1 $not$libresoc.v:177781$11037_Y + connect \$3 $not$libresoc.v:177782$11038_Y + connect \$6 $not$libresoc.v:177783$11039_Y end -attribute \src "libresoc.v:176081.1-176526.10" +attribute \src "libresoc.v:178177.1-178622.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:176082.7-176082.20" + attribute \src "libresoc.v:178178.7-178178.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176411.3-176456.6" - wire width 2 $0\r2__data_o$next[1:0]$11125 - attribute \src "libresoc.v:176157.3-176158.37" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $0\r2__data_o$next[1:0]$11176 + attribute \src "libresoc.v:178253.3-178254.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:176493.3-176525.6" - wire width 2 $0\reg$next[1:0]$11141 - attribute \src "libresoc.v:176155.3-176156.25" + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $0\reg$next[1:0]$11192 + attribute \src "libresoc.v:178251.3-178252.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:176165.3-176210.6" - wire width 2 $0\src12__data_o$next[1:0]$11083 - attribute \src "libresoc.v:176163.3-176164.43" + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $0\src12__data_o$next[1:0]$11134 + attribute \src "libresoc.v:178259.3-178260.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:176247.3-176292.6" - wire width 2 $0\src22__data_o$next[1:0]$11093 - attribute \src "libresoc.v:176161.3-176162.43" + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $0\src22__data_o$next[1:0]$11144 + attribute \src "libresoc.v:178257.3-178258.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:176329.3-176374.6" - wire width 2 $0\src32__data_o$next[1:0]$11109 - attribute \src "libresoc.v:176159.3-176160.43" + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $0\src32__data_o$next[1:0]$11160 + attribute \src "libresoc.v:178255.3-178256.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:176457.3-176492.6" - wire $0\wr_detect$10[0:0]$11134 - attribute \src "libresoc.v:176293.3-176328.6" - wire $0\wr_detect$4[0:0]$11102 - attribute \src "libresoc.v:176375.3-176410.6" - wire $0\wr_detect$7[0:0]$11118 - attribute \src "libresoc.v:176211.3-176246.6" + attribute \src "libresoc.v:178553.3-178588.6" + wire $0\wr_detect$10[0:0]$11185 + attribute \src "libresoc.v:178389.3-178424.6" + wire $0\wr_detect$4[0:0]$11153 + attribute \src "libresoc.v:178471.3-178506.6" + wire $0\wr_detect$7[0:0]$11169 + attribute \src "libresoc.v:178307.3-178342.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176411.3-176456.6" - wire width 2 $1\r2__data_o$next[1:0]$11126 - attribute \src "libresoc.v:176109.13-176109.30" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $1\r2__data_o$next[1:0]$11177 + attribute \src "libresoc.v:178205.13-178205.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:176493.3-176525.6" - wire width 2 $1\reg$next[1:0]$11142 - attribute \src "libresoc.v:176115.13-176115.25" + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $1\reg$next[1:0]$11193 + attribute \src "libresoc.v:178211.13-178211.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:176165.3-176210.6" - wire width 2 $1\src12__data_o$next[1:0]$11084 - attribute \src "libresoc.v:176120.13-176120.33" + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $1\src12__data_o$next[1:0]$11135 + attribute \src "libresoc.v:178216.13-178216.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:176247.3-176292.6" - wire width 2 $1\src22__data_o$next[1:0]$11094 - attribute \src "libresoc.v:176127.13-176127.33" + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $1\src22__data_o$next[1:0]$11145 + attribute \src "libresoc.v:178223.13-178223.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:176329.3-176374.6" - wire width 2 $1\src32__data_o$next[1:0]$11110 - attribute \src "libresoc.v:176134.13-176134.33" + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $1\src32__data_o$next[1:0]$11161 + attribute \src "libresoc.v:178230.13-178230.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:176457.3-176492.6" - wire $1\wr_detect$10[0:0]$11135 - attribute \src "libresoc.v:176293.3-176328.6" - wire $1\wr_detect$4[0:0]$11103 - attribute \src "libresoc.v:176375.3-176410.6" - wire $1\wr_detect$7[0:0]$11119 - attribute \src "libresoc.v:176211.3-176246.6" + attribute \src "libresoc.v:178553.3-178588.6" + wire $1\wr_detect$10[0:0]$11186 + attribute \src "libresoc.v:178389.3-178424.6" + wire $1\wr_detect$4[0:0]$11154 + attribute \src "libresoc.v:178471.3-178506.6" + wire $1\wr_detect$7[0:0]$11170 + attribute \src "libresoc.v:178307.3-178342.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176411.3-176456.6" - wire width 2 $2\r2__data_o$next[1:0]$11127 - attribute \src "libresoc.v:176493.3-176525.6" - wire width 2 $2\reg$next[1:0]$11143 - attribute \src "libresoc.v:176165.3-176210.6" - wire width 2 $2\src12__data_o$next[1:0]$11085 - attribute \src "libresoc.v:176247.3-176292.6" - wire width 2 $2\src22__data_o$next[1:0]$11095 - attribute \src "libresoc.v:176329.3-176374.6" - wire width 2 $2\src32__data_o$next[1:0]$11111 - attribute \src "libresoc.v:176457.3-176492.6" - wire $2\wr_detect$10[0:0]$11136 - attribute \src "libresoc.v:176293.3-176328.6" - wire $2\wr_detect$4[0:0]$11104 - attribute \src "libresoc.v:176375.3-176410.6" - wire $2\wr_detect$7[0:0]$11120 - attribute \src "libresoc.v:176211.3-176246.6" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $2\r2__data_o$next[1:0]$11178 + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $2\reg$next[1:0]$11194 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $2\src12__data_o$next[1:0]$11136 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $2\src22__data_o$next[1:0]$11146 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $2\src32__data_o$next[1:0]$11162 + attribute \src "libresoc.v:178553.3-178588.6" + wire $2\wr_detect$10[0:0]$11187 + attribute \src "libresoc.v:178389.3-178424.6" + wire $2\wr_detect$4[0:0]$11155 + attribute \src "libresoc.v:178471.3-178506.6" + wire $2\wr_detect$7[0:0]$11171 + attribute \src "libresoc.v:178307.3-178342.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176411.3-176456.6" - wire width 2 $3\r2__data_o$next[1:0]$11128 - attribute \src "libresoc.v:176493.3-176525.6" - wire width 2 $3\reg$next[1:0]$11144 - attribute \src "libresoc.v:176165.3-176210.6" - wire width 2 $3\src12__data_o$next[1:0]$11086 - attribute \src "libresoc.v:176247.3-176292.6" - wire width 2 $3\src22__data_o$next[1:0]$11096 - attribute \src "libresoc.v:176329.3-176374.6" - wire width 2 $3\src32__data_o$next[1:0]$11112 - attribute \src "libresoc.v:176457.3-176492.6" - wire $3\wr_detect$10[0:0]$11137 - attribute \src "libresoc.v:176293.3-176328.6" - wire $3\wr_detect$4[0:0]$11105 - attribute \src "libresoc.v:176375.3-176410.6" - wire $3\wr_detect$7[0:0]$11121 - attribute \src "libresoc.v:176211.3-176246.6" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $3\r2__data_o$next[1:0]$11179 + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $3\reg$next[1:0]$11195 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $3\src12__data_o$next[1:0]$11137 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $3\src22__data_o$next[1:0]$11147 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $3\src32__data_o$next[1:0]$11163 + attribute \src "libresoc.v:178553.3-178588.6" + wire $3\wr_detect$10[0:0]$11188 + attribute \src "libresoc.v:178389.3-178424.6" + wire $3\wr_detect$4[0:0]$11156 + attribute \src "libresoc.v:178471.3-178506.6" + wire $3\wr_detect$7[0:0]$11172 + attribute \src "libresoc.v:178307.3-178342.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176411.3-176456.6" - wire width 2 $4\r2__data_o$next[1:0]$11129 - attribute \src "libresoc.v:176493.3-176525.6" - wire width 2 $4\reg$next[1:0]$11145 - attribute \src "libresoc.v:176165.3-176210.6" - wire width 2 $4\src12__data_o$next[1:0]$11087 - attribute \src "libresoc.v:176247.3-176292.6" - wire width 2 $4\src22__data_o$next[1:0]$11097 - attribute \src "libresoc.v:176329.3-176374.6" - wire width 2 $4\src32__data_o$next[1:0]$11113 - attribute \src "libresoc.v:176457.3-176492.6" - wire $4\wr_detect$10[0:0]$11138 - attribute \src "libresoc.v:176293.3-176328.6" - wire $4\wr_detect$4[0:0]$11106 - attribute \src "libresoc.v:176375.3-176410.6" - wire $4\wr_detect$7[0:0]$11122 - attribute \src "libresoc.v:176211.3-176246.6" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $4\r2__data_o$next[1:0]$11180 + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $4\reg$next[1:0]$11196 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $4\src12__data_o$next[1:0]$11138 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $4\src22__data_o$next[1:0]$11148 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $4\src32__data_o$next[1:0]$11164 + attribute \src "libresoc.v:178553.3-178588.6" + wire $4\wr_detect$10[0:0]$11189 + attribute \src "libresoc.v:178389.3-178424.6" + wire $4\wr_detect$4[0:0]$11157 + attribute \src "libresoc.v:178471.3-178506.6" + wire $4\wr_detect$7[0:0]$11173 + attribute \src "libresoc.v:178307.3-178342.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176411.3-176456.6" - wire width 2 $5\r2__data_o$next[1:0]$11130 - attribute \src "libresoc.v:176493.3-176525.6" - wire width 2 $5\reg$next[1:0]$11146 - attribute \src "libresoc.v:176165.3-176210.6" - wire width 2 $5\src12__data_o$next[1:0]$11088 - attribute \src "libresoc.v:176247.3-176292.6" - wire width 2 $5\src22__data_o$next[1:0]$11098 - attribute \src "libresoc.v:176329.3-176374.6" - wire width 2 $5\src32__data_o$next[1:0]$11114 - attribute \src "libresoc.v:176457.3-176492.6" - wire $5\wr_detect$10[0:0]$11139 - attribute \src "libresoc.v:176293.3-176328.6" - wire $5\wr_detect$4[0:0]$11107 - attribute \src "libresoc.v:176375.3-176410.6" - wire $5\wr_detect$7[0:0]$11123 - attribute \src "libresoc.v:176211.3-176246.6" + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $5\r2__data_o$next[1:0]$11181 + attribute \src "libresoc.v:178589.3-178621.6" + wire width 2 $5\reg$next[1:0]$11197 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $5\src12__data_o$next[1:0]$11139 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $5\src22__data_o$next[1:0]$11149 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $5\src32__data_o$next[1:0]$11165 + attribute \src "libresoc.v:178553.3-178588.6" + wire $5\wr_detect$10[0:0]$11190 + attribute \src "libresoc.v:178389.3-178424.6" + wire $5\wr_detect$4[0:0]$11158 + attribute \src "libresoc.v:178471.3-178506.6" + wire $5\wr_detect$7[0:0]$11174 + attribute \src "libresoc.v:178307.3-178342.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:176411.3-176456.6" - wire width 2 $6\r2__data_o$next[1:0]$11131 - attribute \src "libresoc.v:176165.3-176210.6" - wire width 2 $6\src12__data_o$next[1:0]$11089 - attribute \src "libresoc.v:176247.3-176292.6" - wire width 2 $6\src22__data_o$next[1:0]$11099 - attribute \src "libresoc.v:176329.3-176374.6" - wire width 2 $6\src32__data_o$next[1:0]$11115 - attribute \src "libresoc.v:176411.3-176456.6" - wire width 2 $7\r2__data_o$next[1:0]$11132 - attribute \src "libresoc.v:176165.3-176210.6" - wire width 2 $7\src12__data_o$next[1:0]$11090 - attribute \src "libresoc.v:176247.3-176292.6" - wire width 2 $7\src22__data_o$next[1:0]$11100 - attribute \src "libresoc.v:176329.3-176374.6" - wire width 2 $7\src32__data_o$next[1:0]$11116 - attribute \src "libresoc.v:176151.17-176151.104" - wire $not$libresoc.v:176151$11073_Y - attribute \src "libresoc.v:176152.17-176152.100" - wire $not$libresoc.v:176152$11074_Y - attribute \src "libresoc.v:176153.17-176153.103" - wire $not$libresoc.v:176153$11075_Y - attribute \src "libresoc.v:176154.17-176154.103" - wire $not$libresoc.v:176154$11076_Y + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $6\r2__data_o$next[1:0]$11182 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $6\src12__data_o$next[1:0]$11140 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $6\src22__data_o$next[1:0]$11150 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $6\src32__data_o$next[1:0]$11166 + attribute \src "libresoc.v:178507.3-178552.6" + wire width 2 $7\r2__data_o$next[1:0]$11183 + attribute \src "libresoc.v:178261.3-178306.6" + wire width 2 $7\src12__data_o$next[1:0]$11141 + attribute \src "libresoc.v:178343.3-178388.6" + wire width 2 $7\src22__data_o$next[1:0]$11151 + attribute \src "libresoc.v:178425.3-178470.6" + wire width 2 $7\src32__data_o$next[1:0]$11167 + attribute \src "libresoc.v:178247.17-178247.104" + wire $not$libresoc.v:178247$11124_Y + attribute \src "libresoc.v:178248.17-178248.100" + wire $not$libresoc.v:178248$11125_Y + attribute \src "libresoc.v:178249.17-178249.103" + wire $not$libresoc.v:178249$11126_Y + attribute \src "libresoc.v:178250.17-178250.103" + wire $not$libresoc.v:178250$11127_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -364344,9 +367215,9 @@ module \reg_2$134 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i @@ -364360,7 +367231,7 @@ module \reg_2$134 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:176082.7-176082.15" + attribute \src "libresoc.v:178178.7-178178.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o @@ -364403,129 +367274,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176151$11073 + cell $not $not$libresoc.v:178247$11124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176151$11073_Y + connect \Y $not$libresoc.v:178247$11124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176152$11074 + cell $not $not$libresoc.v:178248$11125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176152$11074_Y + connect \Y $not$libresoc.v:178248$11125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176153$11075 + cell $not $not$libresoc.v:178249$11126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176153$11075_Y + connect \Y $not$libresoc.v:178249$11126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176154$11076 + cell $not $not$libresoc.v:178250$11127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176154$11076_Y + connect \Y $not$libresoc.v:178250$11127_Y end - attribute \src "libresoc.v:176082.7-176082.20" - process $proc$libresoc.v:176082$11147 + attribute \src "libresoc.v:178178.7-178178.20" + process $proc$libresoc.v:178178$11198 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176109.13-176109.30" - process $proc$libresoc.v:176109$11148 + attribute \src "libresoc.v:178205.13-178205.30" + process $proc$libresoc.v:178205$11199 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:176115.13-176115.25" - process $proc$libresoc.v:176115$11149 + attribute \src "libresoc.v:178211.13-178211.25" + process $proc$libresoc.v:178211$11200 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:176120.13-176120.33" - process $proc$libresoc.v:176120$11150 + attribute \src "libresoc.v:178216.13-178216.33" + process $proc$libresoc.v:178216$11201 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:176127.13-176127.33" - process $proc$libresoc.v:176127$11151 + attribute \src "libresoc.v:178223.13-178223.33" + process $proc$libresoc.v:178223$11202 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:176134.13-176134.33" - process $proc$libresoc.v:176134$11152 + attribute \src "libresoc.v:178230.13-178230.33" + process $proc$libresoc.v:178230$11203 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:176155.3-176156.25" - process $proc$libresoc.v:176155$11077 + attribute \src "libresoc.v:178251.3-178252.25" + process $proc$libresoc.v:178251$11128 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:176157.3-176158.37" - process $proc$libresoc.v:176157$11078 + attribute \src "libresoc.v:178253.3-178254.37" + process $proc$libresoc.v:178253$11129 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:176159.3-176160.43" - process $proc$libresoc.v:176159$11079 + attribute \src "libresoc.v:178255.3-178256.43" + process $proc$libresoc.v:178255$11130 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:176161.3-176162.43" - process $proc$libresoc.v:176161$11080 + attribute \src "libresoc.v:178257.3-178258.43" + process $proc$libresoc.v:178257$11131 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:176163.3-176164.43" - process $proc$libresoc.v:176163$11081 + attribute \src "libresoc.v:178259.3-178260.43" + process $proc$libresoc.v:178259$11132 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:176165.3-176210.6" - process $proc$libresoc.v:176165$11082 + attribute \src "libresoc.v:178261.3-178306.6" + process $proc$libresoc.v:178261$11133 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$11083 $7\src12__data_o$next[1:0]$11090 - attribute \src "libresoc.v:176166.5-176166.29" + assign $0\src12__data_o$next[1:0]$11134 $7\src12__data_o$next[1:0]$11141 + attribute \src "libresoc.v:178262.5-178262.29" switch \initial - attribute \src "libresoc.v:176166.9-176166.17" + attribute \src "libresoc.v:178262.9-178262.17" case 1'1 case end @@ -364538,75 +367409,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$11084 $6\src12__data_o$next[1:0]$11089 + assign $1\src12__data_o$next[1:0]$11135 $6\src12__data_o$next[1:0]$11140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$11085 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11136 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$11085 2'00 + assign $2\src12__data_o$next[1:0]$11136 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$11086 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11137 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$11086 $2\src12__data_o$next[1:0]$11085 + assign $3\src12__data_o$next[1:0]$11137 $2\src12__data_o$next[1:0]$11136 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$11087 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11138 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$11087 $3\src12__data_o$next[1:0]$11086 + assign $4\src12__data_o$next[1:0]$11138 $3\src12__data_o$next[1:0]$11137 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$11088 \w2__data_i + assign $5\src12__data_o$next[1:0]$11139 \w2__data_i case - assign $5\src12__data_o$next[1:0]$11088 $4\src12__data_o$next[1:0]$11087 + assign $5\src12__data_o$next[1:0]$11139 $4\src12__data_o$next[1:0]$11138 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$11089 \reg + assign $6\src12__data_o$next[1:0]$11140 \reg case - assign $6\src12__data_o$next[1:0]$11089 $5\src12__data_o$next[1:0]$11088 + assign $6\src12__data_o$next[1:0]$11140 $5\src12__data_o$next[1:0]$11139 end case - assign $1\src12__data_o$next[1:0]$11084 2'00 + assign $1\src12__data_o$next[1:0]$11135 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$11090 2'00 + assign $7\src12__data_o$next[1:0]$11141 2'00 case - assign $7\src12__data_o$next[1:0]$11090 $1\src12__data_o$next[1:0]$11084 + assign $7\src12__data_o$next[1:0]$11141 $1\src12__data_o$next[1:0]$11135 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11083 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11134 end - attribute \src "libresoc.v:176211.3-176246.6" - process $proc$libresoc.v:176211$11091 + attribute \src "libresoc.v:178307.3-178342.6" + process $proc$libresoc.v:178307$11142 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176212.5-176212.29" + attribute \src "libresoc.v:178308.5-178308.29" switch \initial - attribute \src "libresoc.v:176212.9-176212.17" + attribute \src "libresoc.v:178308.9-178308.17" case 1'1 case end @@ -364662,15 +367533,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176247.3-176292.6" - process $proc$libresoc.v:176247$11092 + attribute \src "libresoc.v:178343.3-178388.6" + process $proc$libresoc.v:178343$11143 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$11093 $7\src22__data_o$next[1:0]$11100 - attribute \src "libresoc.v:176248.5-176248.29" + assign $0\src22__data_o$next[1:0]$11144 $7\src22__data_o$next[1:0]$11151 + attribute \src "libresoc.v:178344.5-178344.29" switch \initial - attribute \src "libresoc.v:176248.9-176248.17" + attribute \src "libresoc.v:178344.9-178344.17" case 1'1 case end @@ -364683,75 +367554,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$11094 $6\src22__data_o$next[1:0]$11099 + assign $1\src22__data_o$next[1:0]$11145 $6\src22__data_o$next[1:0]$11150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$11095 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11146 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$11095 2'00 + assign $2\src22__data_o$next[1:0]$11146 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$11096 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11147 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$11096 $2\src22__data_o$next[1:0]$11095 + assign $3\src22__data_o$next[1:0]$11147 $2\src22__data_o$next[1:0]$11146 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$11097 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11148 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$11097 $3\src22__data_o$next[1:0]$11096 + assign $4\src22__data_o$next[1:0]$11148 $3\src22__data_o$next[1:0]$11147 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$11098 \w2__data_i + assign $5\src22__data_o$next[1:0]$11149 \w2__data_i case - assign $5\src22__data_o$next[1:0]$11098 $4\src22__data_o$next[1:0]$11097 + assign $5\src22__data_o$next[1:0]$11149 $4\src22__data_o$next[1:0]$11148 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$11099 \reg + assign $6\src22__data_o$next[1:0]$11150 \reg case - assign $6\src22__data_o$next[1:0]$11099 $5\src22__data_o$next[1:0]$11098 + assign $6\src22__data_o$next[1:0]$11150 $5\src22__data_o$next[1:0]$11149 end case - assign $1\src22__data_o$next[1:0]$11094 2'00 + assign $1\src22__data_o$next[1:0]$11145 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$11100 2'00 + assign $7\src22__data_o$next[1:0]$11151 2'00 case - assign $7\src22__data_o$next[1:0]$11100 $1\src22__data_o$next[1:0]$11094 + assign $7\src22__data_o$next[1:0]$11151 $1\src22__data_o$next[1:0]$11145 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11093 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11144 end - attribute \src "libresoc.v:176293.3-176328.6" - process $proc$libresoc.v:176293$11101 + attribute \src "libresoc.v:178389.3-178424.6" + process $proc$libresoc.v:178389$11152 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11102 $1\wr_detect$4[0:0]$11103 - attribute \src "libresoc.v:176294.5-176294.29" + assign $0\wr_detect$4[0:0]$11153 $1\wr_detect$4[0:0]$11154 + attribute \src "libresoc.v:178390.5-178390.29" switch \initial - attribute \src "libresoc.v:176294.9-176294.17" + attribute \src "libresoc.v:178390.9-178390.17" case 1'1 case end @@ -364764,58 +367635,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11103 $5\wr_detect$4[0:0]$11107 + assign $1\wr_detect$4[0:0]$11154 $5\wr_detect$4[0:0]$11158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11104 1'1 + assign $2\wr_detect$4[0:0]$11155 1'1 case - assign $2\wr_detect$4[0:0]$11104 1'0 + assign $2\wr_detect$4[0:0]$11155 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11105 1'1 + assign $3\wr_detect$4[0:0]$11156 1'1 case - assign $3\wr_detect$4[0:0]$11105 $2\wr_detect$4[0:0]$11104 + assign $3\wr_detect$4[0:0]$11156 $2\wr_detect$4[0:0]$11155 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11106 1'1 + assign $4\wr_detect$4[0:0]$11157 1'1 case - assign $4\wr_detect$4[0:0]$11106 $3\wr_detect$4[0:0]$11105 + assign $4\wr_detect$4[0:0]$11157 $3\wr_detect$4[0:0]$11156 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11107 1'1 + assign $5\wr_detect$4[0:0]$11158 1'1 case - assign $5\wr_detect$4[0:0]$11107 $4\wr_detect$4[0:0]$11106 + assign $5\wr_detect$4[0:0]$11158 $4\wr_detect$4[0:0]$11157 end case - assign $1\wr_detect$4[0:0]$11103 1'0 + assign $1\wr_detect$4[0:0]$11154 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11102 + update \wr_detect$4 $0\wr_detect$4[0:0]$11153 end - attribute \src "libresoc.v:176329.3-176374.6" - process $proc$libresoc.v:176329$11108 + attribute \src "libresoc.v:178425.3-178470.6" + process $proc$libresoc.v:178425$11159 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$11109 $7\src32__data_o$next[1:0]$11116 - attribute \src "libresoc.v:176330.5-176330.29" + assign $0\src32__data_o$next[1:0]$11160 $7\src32__data_o$next[1:0]$11167 + attribute \src "libresoc.v:178426.5-178426.29" switch \initial - attribute \src "libresoc.v:176330.9-176330.17" + attribute \src "libresoc.v:178426.9-178426.17" case 1'1 case end @@ -364828,75 +367699,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$11110 $6\src32__data_o$next[1:0]$11115 + assign $1\src32__data_o$next[1:0]$11161 $6\src32__data_o$next[1:0]$11166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$11111 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11162 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$11111 2'00 + assign $2\src32__data_o$next[1:0]$11162 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$11112 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11163 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$11112 $2\src32__data_o$next[1:0]$11111 + assign $3\src32__data_o$next[1:0]$11163 $2\src32__data_o$next[1:0]$11162 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$11113 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11164 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$11113 $3\src32__data_o$next[1:0]$11112 + assign $4\src32__data_o$next[1:0]$11164 $3\src32__data_o$next[1:0]$11163 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$11114 \w2__data_i + assign $5\src32__data_o$next[1:0]$11165 \w2__data_i case - assign $5\src32__data_o$next[1:0]$11114 $4\src32__data_o$next[1:0]$11113 + assign $5\src32__data_o$next[1:0]$11165 $4\src32__data_o$next[1:0]$11164 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$11115 \reg + assign $6\src32__data_o$next[1:0]$11166 \reg case - assign $6\src32__data_o$next[1:0]$11115 $5\src32__data_o$next[1:0]$11114 + assign $6\src32__data_o$next[1:0]$11166 $5\src32__data_o$next[1:0]$11165 end case - assign $1\src32__data_o$next[1:0]$11110 2'00 + assign $1\src32__data_o$next[1:0]$11161 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$11116 2'00 + assign $7\src32__data_o$next[1:0]$11167 2'00 case - assign $7\src32__data_o$next[1:0]$11116 $1\src32__data_o$next[1:0]$11110 + assign $7\src32__data_o$next[1:0]$11167 $1\src32__data_o$next[1:0]$11161 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11109 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11160 end - attribute \src "libresoc.v:176375.3-176410.6" - process $proc$libresoc.v:176375$11117 + attribute \src "libresoc.v:178471.3-178506.6" + process $proc$libresoc.v:178471$11168 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11118 $1\wr_detect$7[0:0]$11119 - attribute \src "libresoc.v:176376.5-176376.29" + assign $0\wr_detect$7[0:0]$11169 $1\wr_detect$7[0:0]$11170 + attribute \src "libresoc.v:178472.5-178472.29" switch \initial - attribute \src "libresoc.v:176376.9-176376.17" + attribute \src "libresoc.v:178472.9-178472.17" case 1'1 case end @@ -364909,58 +367780,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11119 $5\wr_detect$7[0:0]$11123 + assign $1\wr_detect$7[0:0]$11170 $5\wr_detect$7[0:0]$11174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11120 1'1 + assign $2\wr_detect$7[0:0]$11171 1'1 case - assign $2\wr_detect$7[0:0]$11120 1'0 + assign $2\wr_detect$7[0:0]$11171 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11121 1'1 + assign $3\wr_detect$7[0:0]$11172 1'1 case - assign $3\wr_detect$7[0:0]$11121 $2\wr_detect$7[0:0]$11120 + assign $3\wr_detect$7[0:0]$11172 $2\wr_detect$7[0:0]$11171 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11122 1'1 + assign $4\wr_detect$7[0:0]$11173 1'1 case - assign $4\wr_detect$7[0:0]$11122 $3\wr_detect$7[0:0]$11121 + assign $4\wr_detect$7[0:0]$11173 $3\wr_detect$7[0:0]$11172 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11123 1'1 + assign $5\wr_detect$7[0:0]$11174 1'1 case - assign $5\wr_detect$7[0:0]$11123 $4\wr_detect$7[0:0]$11122 + assign $5\wr_detect$7[0:0]$11174 $4\wr_detect$7[0:0]$11173 end case - assign $1\wr_detect$7[0:0]$11119 1'0 + assign $1\wr_detect$7[0:0]$11170 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11118 + update \wr_detect$7 $0\wr_detect$7[0:0]$11169 end - attribute \src "libresoc.v:176411.3-176456.6" - process $proc$libresoc.v:176411$11124 + attribute \src "libresoc.v:178507.3-178552.6" + process $proc$libresoc.v:178507$11175 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$11125 $7\r2__data_o$next[1:0]$11132 - attribute \src "libresoc.v:176412.5-176412.29" + assign $0\r2__data_o$next[1:0]$11176 $7\r2__data_o$next[1:0]$11183 + attribute \src "libresoc.v:178508.5-178508.29" switch \initial - attribute \src "libresoc.v:176412.9-176412.17" + attribute \src "libresoc.v:178508.9-178508.17" case 1'1 case end @@ -364973,75 +367844,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$11126 $6\r2__data_o$next[1:0]$11131 + assign $1\r2__data_o$next[1:0]$11177 $6\r2__data_o$next[1:0]$11182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$11127 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11178 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$11127 2'00 + assign $2\r2__data_o$next[1:0]$11178 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$11128 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11179 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$11128 $2\r2__data_o$next[1:0]$11127 + assign $3\r2__data_o$next[1:0]$11179 $2\r2__data_o$next[1:0]$11178 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$11129 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11180 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$11129 $3\r2__data_o$next[1:0]$11128 + assign $4\r2__data_o$next[1:0]$11180 $3\r2__data_o$next[1:0]$11179 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$11130 \w2__data_i + assign $5\r2__data_o$next[1:0]$11181 \w2__data_i case - assign $5\r2__data_o$next[1:0]$11130 $4\r2__data_o$next[1:0]$11129 + assign $5\r2__data_o$next[1:0]$11181 $4\r2__data_o$next[1:0]$11180 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$11131 \reg + assign $6\r2__data_o$next[1:0]$11182 \reg case - assign $6\r2__data_o$next[1:0]$11131 $5\r2__data_o$next[1:0]$11130 + assign $6\r2__data_o$next[1:0]$11182 $5\r2__data_o$next[1:0]$11181 end case - assign $1\r2__data_o$next[1:0]$11126 2'00 + assign $1\r2__data_o$next[1:0]$11177 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$11132 2'00 + assign $7\r2__data_o$next[1:0]$11183 2'00 case - assign $7\r2__data_o$next[1:0]$11132 $1\r2__data_o$next[1:0]$11126 + assign $7\r2__data_o$next[1:0]$11183 $1\r2__data_o$next[1:0]$11177 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11125 + update \r2__data_o$next $0\r2__data_o$next[1:0]$11176 end - attribute \src "libresoc.v:176457.3-176492.6" - process $proc$libresoc.v:176457$11133 + attribute \src "libresoc.v:178553.3-178588.6" + process $proc$libresoc.v:178553$11184 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11134 $1\wr_detect$10[0:0]$11135 - attribute \src "libresoc.v:176458.5-176458.29" + assign $0\wr_detect$10[0:0]$11185 $1\wr_detect$10[0:0]$11186 + attribute \src "libresoc.v:178554.5-178554.29" switch \initial - attribute \src "libresoc.v:176458.9-176458.17" + attribute \src "libresoc.v:178554.9-178554.17" case 1'1 case end @@ -365054,61 +367925,61 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11135 $5\wr_detect$10[0:0]$11139 + assign $1\wr_detect$10[0:0]$11186 $5\wr_detect$10[0:0]$11190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11136 1'1 + assign $2\wr_detect$10[0:0]$11187 1'1 case - assign $2\wr_detect$10[0:0]$11136 1'0 + assign $2\wr_detect$10[0:0]$11187 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11137 1'1 + assign $3\wr_detect$10[0:0]$11188 1'1 case - assign $3\wr_detect$10[0:0]$11137 $2\wr_detect$10[0:0]$11136 + assign $3\wr_detect$10[0:0]$11188 $2\wr_detect$10[0:0]$11187 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11138 1'1 + assign $4\wr_detect$10[0:0]$11189 1'1 case - assign $4\wr_detect$10[0:0]$11138 $3\wr_detect$10[0:0]$11137 + assign $4\wr_detect$10[0:0]$11189 $3\wr_detect$10[0:0]$11188 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11139 1'1 + assign $5\wr_detect$10[0:0]$11190 1'1 case - assign $5\wr_detect$10[0:0]$11139 $4\wr_detect$10[0:0]$11138 + assign $5\wr_detect$10[0:0]$11190 $4\wr_detect$10[0:0]$11189 end case - assign $1\wr_detect$10[0:0]$11135 1'0 + assign $1\wr_detect$10[0:0]$11186 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11134 + update \wr_detect$10 $0\wr_detect$10[0:0]$11185 end - attribute \src "libresoc.v:176493.3-176525.6" - process $proc$libresoc.v:176493$11140 + attribute \src "libresoc.v:178589.3-178621.6" + process $proc$libresoc.v:178589$11191 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11141 $5\reg$next[1:0]$11146 - attribute \src "libresoc.v:176494.5-176494.29" + assign $0\reg$next[1:0]$11192 $5\reg$next[1:0]$11197 + attribute \src "libresoc.v:178590.5-178590.29" switch \initial - attribute \src "libresoc.v:176494.9-176494.17" + attribute \src "libresoc.v:178590.9-178590.17" case 1'1 case end @@ -365117,179 +367988,179 @@ module \reg_2$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11142 \dest12__data_i + assign $1\reg$next[1:0]$11193 \dest12__data_i case - assign $1\reg$next[1:0]$11142 \reg + assign $1\reg$next[1:0]$11193 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11143 \dest22__data_i + assign $2\reg$next[1:0]$11194 \dest22__data_i case - assign $2\reg$next[1:0]$11143 $1\reg$next[1:0]$11142 + assign $2\reg$next[1:0]$11194 $1\reg$next[1:0]$11193 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11144 \dest32__data_i + assign $3\reg$next[1:0]$11195 \dest32__data_i case - assign $3\reg$next[1:0]$11144 $2\reg$next[1:0]$11143 + assign $3\reg$next[1:0]$11195 $2\reg$next[1:0]$11194 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11145 \w2__data_i + assign $4\reg$next[1:0]$11196 \w2__data_i case - assign $4\reg$next[1:0]$11145 $3\reg$next[1:0]$11144 + assign $4\reg$next[1:0]$11196 $3\reg$next[1:0]$11195 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11146 2'00 + assign $5\reg$next[1:0]$11197 2'00 case - assign $5\reg$next[1:0]$11146 $4\reg$next[1:0]$11145 + assign $5\reg$next[1:0]$11197 $4\reg$next[1:0]$11196 end sync always - update \reg$next $0\reg$next[1:0]$11141 + update \reg$next $0\reg$next[1:0]$11192 end - connect \$9 $not$libresoc.v:176151$11073_Y - connect \$1 $not$libresoc.v:176152$11074_Y - connect \$3 $not$libresoc.v:176153$11075_Y - connect \$6 $not$libresoc.v:176154$11076_Y + connect \$9 $not$libresoc.v:178247$11124_Y + connect \$1 $not$libresoc.v:178248$11125_Y + connect \$3 $not$libresoc.v:178249$11126_Y + connect \$6 $not$libresoc.v:178250$11127_Y end -attribute \src "libresoc.v:176530.1-176879.10" +attribute \src "libresoc.v:178626.1-178975.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 - attribute \src "libresoc.v:176600.3-176645.6" - wire width 64 $0\cia2__data_o$next[63:0]$11161 - attribute \src "libresoc.v:176598.3-176599.41" + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $0\cia2__data_o$next[63:0]$11212 + attribute \src "libresoc.v:178694.3-178695.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:176531.7-176531.20" + attribute \src "libresoc.v:178627.7-178627.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176682.3-176727.6" - wire width 64 $0\msr2__data_o$next[63:0]$11171 - attribute \src "libresoc.v:176596.3-176597.41" + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $0\msr2__data_o$next[63:0]$11222 + attribute \src "libresoc.v:178692.3-178693.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:176846.3-176878.6" - wire width 64 $0\reg$next[63:0]$11203 - attribute \src "libresoc.v:176592.3-176593.25" + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $0\reg$next[63:0]$11254 + attribute \src "libresoc.v:178688.3-178689.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:176764.3-176809.6" - wire width 64 $0\sv2__data_o$next[63:0]$11187 - attribute \src "libresoc.v:176594.3-176595.39" + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $0\sv2__data_o$next[63:0]$11238 + attribute \src "libresoc.v:178690.3-178691.39" wire width 64 $0\sv2__data_o[63:0] - attribute \src "libresoc.v:176728.3-176763.6" - wire $0\wr_detect$4[0:0]$11180 - attribute \src "libresoc.v:176810.3-176845.6" - wire $0\wr_detect$7[0:0]$11196 - attribute \src "libresoc.v:176646.3-176681.6" + attribute \src "libresoc.v:178824.3-178859.6" + wire $0\wr_detect$4[0:0]$11231 + attribute \src "libresoc.v:178906.3-178941.6" + wire $0\wr_detect$7[0:0]$11247 + attribute \src "libresoc.v:178742.3-178777.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176600.3-176645.6" - wire width 64 $1\cia2__data_o$next[63:0]$11162 - attribute \src "libresoc.v:176540.14-176540.49" + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $1\cia2__data_o$next[63:0]$11213 + attribute \src "libresoc.v:178636.14-178636.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:176682.3-176727.6" - wire width 64 $1\msr2__data_o$next[63:0]$11172 - attribute \src "libresoc.v:176557.14-176557.49" + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $1\msr2__data_o$next[63:0]$11223 + attribute \src "libresoc.v:178653.14-178653.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:176846.3-176878.6" - wire width 64 $1\reg$next[63:0]$11204 - attribute \src "libresoc.v:176569.14-176569.42" + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $1\reg$next[63:0]$11255 + attribute \src "libresoc.v:178665.14-178665.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:176764.3-176809.6" - wire width 64 $1\sv2__data_o$next[63:0]$11188 - attribute \src "libresoc.v:176576.14-176576.48" + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $1\sv2__data_o$next[63:0]$11239 + attribute \src "libresoc.v:178672.14-178672.48" wire width 64 $1\sv2__data_o[63:0] - attribute \src "libresoc.v:176728.3-176763.6" - wire $1\wr_detect$4[0:0]$11181 - attribute \src "libresoc.v:176810.3-176845.6" - wire $1\wr_detect$7[0:0]$11197 - attribute \src "libresoc.v:176646.3-176681.6" + attribute \src "libresoc.v:178824.3-178859.6" + wire $1\wr_detect$4[0:0]$11232 + attribute \src "libresoc.v:178906.3-178941.6" + wire $1\wr_detect$7[0:0]$11248 + attribute \src "libresoc.v:178742.3-178777.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176600.3-176645.6" - wire width 64 $2\cia2__data_o$next[63:0]$11163 - attribute \src "libresoc.v:176682.3-176727.6" - wire width 64 $2\msr2__data_o$next[63:0]$11173 - attribute \src "libresoc.v:176846.3-176878.6" - wire width 64 $2\reg$next[63:0]$11205 - attribute \src "libresoc.v:176764.3-176809.6" - wire width 64 $2\sv2__data_o$next[63:0]$11189 - attribute \src "libresoc.v:176728.3-176763.6" - wire $2\wr_detect$4[0:0]$11182 - attribute \src "libresoc.v:176810.3-176845.6" - wire $2\wr_detect$7[0:0]$11198 - attribute \src "libresoc.v:176646.3-176681.6" + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $2\cia2__data_o$next[63:0]$11214 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $2\msr2__data_o$next[63:0]$11224 + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $2\reg$next[63:0]$11256 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $2\sv2__data_o$next[63:0]$11240 + attribute \src "libresoc.v:178824.3-178859.6" + wire $2\wr_detect$4[0:0]$11233 + attribute \src "libresoc.v:178906.3-178941.6" + wire $2\wr_detect$7[0:0]$11249 + attribute \src "libresoc.v:178742.3-178777.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176600.3-176645.6" - wire width 64 $3\cia2__data_o$next[63:0]$11164 - attribute \src "libresoc.v:176682.3-176727.6" - wire width 64 $3\msr2__data_o$next[63:0]$11174 - attribute \src "libresoc.v:176846.3-176878.6" - wire width 64 $3\reg$next[63:0]$11206 - attribute \src "libresoc.v:176764.3-176809.6" - wire width 64 $3\sv2__data_o$next[63:0]$11190 - attribute \src "libresoc.v:176728.3-176763.6" - wire $3\wr_detect$4[0:0]$11183 - attribute \src "libresoc.v:176810.3-176845.6" - wire $3\wr_detect$7[0:0]$11199 - attribute \src "libresoc.v:176646.3-176681.6" + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $3\cia2__data_o$next[63:0]$11215 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $3\msr2__data_o$next[63:0]$11225 + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $3\reg$next[63:0]$11257 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $3\sv2__data_o$next[63:0]$11241 + attribute \src "libresoc.v:178824.3-178859.6" + wire $3\wr_detect$4[0:0]$11234 + attribute \src "libresoc.v:178906.3-178941.6" + wire $3\wr_detect$7[0:0]$11250 + attribute \src "libresoc.v:178742.3-178777.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176600.3-176645.6" - wire width 64 $4\cia2__data_o$next[63:0]$11165 - attribute \src "libresoc.v:176682.3-176727.6" - wire width 64 $4\msr2__data_o$next[63:0]$11175 - attribute \src "libresoc.v:176846.3-176878.6" - wire width 64 $4\reg$next[63:0]$11207 - attribute \src "libresoc.v:176764.3-176809.6" - wire width 64 $4\sv2__data_o$next[63:0]$11191 - attribute \src "libresoc.v:176728.3-176763.6" - wire $4\wr_detect$4[0:0]$11184 - attribute \src "libresoc.v:176810.3-176845.6" - wire $4\wr_detect$7[0:0]$11200 - attribute \src "libresoc.v:176646.3-176681.6" + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $4\cia2__data_o$next[63:0]$11216 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $4\msr2__data_o$next[63:0]$11226 + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $4\reg$next[63:0]$11258 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $4\sv2__data_o$next[63:0]$11242 + attribute \src "libresoc.v:178824.3-178859.6" + wire $4\wr_detect$4[0:0]$11235 + attribute \src "libresoc.v:178906.3-178941.6" + wire $4\wr_detect$7[0:0]$11251 + attribute \src "libresoc.v:178742.3-178777.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176600.3-176645.6" - wire width 64 $5\cia2__data_o$next[63:0]$11166 - attribute \src "libresoc.v:176682.3-176727.6" - wire width 64 $5\msr2__data_o$next[63:0]$11176 - attribute \src "libresoc.v:176846.3-176878.6" - wire width 64 $5\reg$next[63:0]$11208 - attribute \src "libresoc.v:176764.3-176809.6" - wire width 64 $5\sv2__data_o$next[63:0]$11192 - attribute \src "libresoc.v:176728.3-176763.6" - wire $5\wr_detect$4[0:0]$11185 - attribute \src "libresoc.v:176810.3-176845.6" - wire $5\wr_detect$7[0:0]$11201 - attribute \src "libresoc.v:176646.3-176681.6" + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $5\cia2__data_o$next[63:0]$11217 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $5\msr2__data_o$next[63:0]$11227 + attribute \src "libresoc.v:178942.3-178974.6" + wire width 64 $5\reg$next[63:0]$11259 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $5\sv2__data_o$next[63:0]$11243 + attribute \src "libresoc.v:178824.3-178859.6" + wire $5\wr_detect$4[0:0]$11236 + attribute \src "libresoc.v:178906.3-178941.6" + wire $5\wr_detect$7[0:0]$11252 + attribute \src "libresoc.v:178742.3-178777.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:176600.3-176645.6" - wire width 64 $6\cia2__data_o$next[63:0]$11167 - attribute \src "libresoc.v:176682.3-176727.6" - wire width 64 $6\msr2__data_o$next[63:0]$11177 - attribute \src "libresoc.v:176764.3-176809.6" - wire width 64 $6\sv2__data_o$next[63:0]$11193 - attribute \src "libresoc.v:176600.3-176645.6" - wire width 64 $7\cia2__data_o$next[63:0]$11168 - attribute \src "libresoc.v:176682.3-176727.6" - wire width 64 $7\msr2__data_o$next[63:0]$11178 - attribute \src "libresoc.v:176764.3-176809.6" - wire width 64 $7\sv2__data_o$next[63:0]$11194 - attribute \src "libresoc.v:176589.17-176589.100" - wire $not$libresoc.v:176589$11153_Y - attribute \src "libresoc.v:176590.17-176590.103" - wire $not$libresoc.v:176590$11154_Y - attribute \src "libresoc.v:176591.17-176591.103" - wire $not$libresoc.v:176591$11155_Y + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $6\cia2__data_o$next[63:0]$11218 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $6\msr2__data_o$next[63:0]$11228 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $6\sv2__data_o$next[63:0]$11244 + attribute \src "libresoc.v:178696.3-178741.6" + wire width 64 $7\cia2__data_o$next[63:0]$11219 + attribute \src "libresoc.v:178778.3-178823.6" + wire width 64 $7\msr2__data_o$next[63:0]$11229 + attribute \src "libresoc.v:178860.3-178905.6" + wire width 64 $7\sv2__data_o$next[63:0]$11245 + attribute \src "libresoc.v:178685.17-178685.100" + wire $not$libresoc.v:178685$11204_Y + attribute \src "libresoc.v:178686.17-178686.103" + wire $not$libresoc.v:178686$11205_Y + attribute \src "libresoc.v:178687.17-178687.103" + wire $not$libresoc.v:178687$11206_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -365302,15 +368173,15 @@ module \reg_2$137 wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen - attribute \src "libresoc.v:176531.7-176531.15" + attribute \src "libresoc.v:178627.7-178627.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i @@ -365347,106 +368218,106 @@ module \reg_2$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176589$11153 + cell $not $not$libresoc.v:178685$11204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176589$11153_Y + connect \Y $not$libresoc.v:178685$11204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176590$11154 + cell $not $not$libresoc.v:178686$11205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176590$11154_Y + connect \Y $not$libresoc.v:178686$11205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176591$11155 + cell $not $not$libresoc.v:178687$11206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176591$11155_Y + connect \Y $not$libresoc.v:178687$11206_Y end - attribute \src "libresoc.v:176531.7-176531.20" - process $proc$libresoc.v:176531$11209 + attribute \src "libresoc.v:178627.7-178627.20" + process $proc$libresoc.v:178627$11260 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176540.14-176540.49" - process $proc$libresoc.v:176540$11210 + attribute \src "libresoc.v:178636.14-178636.49" + process $proc$libresoc.v:178636$11261 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:176557.14-176557.49" - process $proc$libresoc.v:176557$11211 + attribute \src "libresoc.v:178653.14-178653.49" + process $proc$libresoc.v:178653$11262 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:176569.14-176569.42" - process $proc$libresoc.v:176569$11212 + attribute \src "libresoc.v:178665.14-178665.42" + process $proc$libresoc.v:178665$11263 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:176576.14-176576.48" - process $proc$libresoc.v:176576$11213 + attribute \src "libresoc.v:178672.14-178672.48" + process $proc$libresoc.v:178672$11264 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end - attribute \src "libresoc.v:176592.3-176593.25" - process $proc$libresoc.v:176592$11156 + attribute \src "libresoc.v:178688.3-178689.25" + process $proc$libresoc.v:178688$11207 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:176594.3-176595.39" - process $proc$libresoc.v:176594$11157 + attribute \src "libresoc.v:178690.3-178691.39" + process $proc$libresoc.v:178690$11208 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end - attribute \src "libresoc.v:176596.3-176597.41" - process $proc$libresoc.v:176596$11158 + attribute \src "libresoc.v:178692.3-178693.41" + process $proc$libresoc.v:178692$11209 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:176598.3-176599.41" - process $proc$libresoc.v:176598$11159 + attribute \src "libresoc.v:178694.3-178695.41" + process $proc$libresoc.v:178694$11210 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:176600.3-176645.6" - process $proc$libresoc.v:176600$11160 + attribute \src "libresoc.v:178696.3-178741.6" + process $proc$libresoc.v:178696$11211 assign { } { } assign { } { } assign { } { } - assign $0\cia2__data_o$next[63:0]$11161 $7\cia2__data_o$next[63:0]$11168 - attribute \src "libresoc.v:176601.5-176601.29" + assign $0\cia2__data_o$next[63:0]$11212 $7\cia2__data_o$next[63:0]$11219 + attribute \src "libresoc.v:178697.5-178697.29" switch \initial - attribute \src "libresoc.v:176601.9-176601.17" + attribute \src "libresoc.v:178697.9-178697.17" case 1'1 case end @@ -365459,75 +368330,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\cia2__data_o$next[63:0]$11162 $6\cia2__data_o$next[63:0]$11167 + assign $1\cia2__data_o$next[63:0]$11213 $6\cia2__data_o$next[63:0]$11218 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia2__data_o$next[63:0]$11163 \nia2__data_i + assign $2\cia2__data_o$next[63:0]$11214 \nia2__data_i case - assign $2\cia2__data_o$next[63:0]$11163 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia2__data_o$next[63:0]$11214 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia2__data_o$next[63:0]$11164 \msr2__data_i + assign $3\cia2__data_o$next[63:0]$11215 \msr2__data_i case - assign $3\cia2__data_o$next[63:0]$11164 $2\cia2__data_o$next[63:0]$11163 + assign $3\cia2__data_o$next[63:0]$11215 $2\cia2__data_o$next[63:0]$11214 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia2__data_o$next[63:0]$11165 \sv2__data_i + assign $4\cia2__data_o$next[63:0]$11216 \sv2__data_i case - assign $4\cia2__data_o$next[63:0]$11165 $3\cia2__data_o$next[63:0]$11164 + assign $4\cia2__data_o$next[63:0]$11216 $3\cia2__data_o$next[63:0]$11215 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia2__data_o$next[63:0]$11166 \d_wr12__data_i + assign $5\cia2__data_o$next[63:0]$11217 \d_wr12__data_i case - assign $5\cia2__data_o$next[63:0]$11166 $4\cia2__data_o$next[63:0]$11165 + assign $5\cia2__data_o$next[63:0]$11217 $4\cia2__data_o$next[63:0]$11216 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$11167 \reg + assign $6\cia2__data_o$next[63:0]$11218 \reg case - assign $6\cia2__data_o$next[63:0]$11167 $5\cia2__data_o$next[63:0]$11166 + assign $6\cia2__data_o$next[63:0]$11218 $5\cia2__data_o$next[63:0]$11217 end case - assign $1\cia2__data_o$next[63:0]$11162 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia2__data_o$next[63:0]$11213 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia2__data_o$next[63:0]$11168 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia2__data_o$next[63:0]$11168 $1\cia2__data_o$next[63:0]$11162 + assign $7\cia2__data_o$next[63:0]$11219 $1\cia2__data_o$next[63:0]$11213 end sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11161 + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11212 end - attribute \src "libresoc.v:176646.3-176681.6" - process $proc$libresoc.v:176646$11169 + attribute \src "libresoc.v:178742.3-178777.6" + process $proc$libresoc.v:178742$11220 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176647.5-176647.29" + attribute \src "libresoc.v:178743.5-178743.29" switch \initial - attribute \src "libresoc.v:176647.9-176647.17" + attribute \src "libresoc.v:178743.9-178743.17" case 1'1 case end @@ -365583,15 +368454,15 @@ module \reg_2$137 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176682.3-176727.6" - process $proc$libresoc.v:176682$11170 + attribute \src "libresoc.v:178778.3-178823.6" + process $proc$libresoc.v:178778$11221 assign { } { } assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$11171 $7\msr2__data_o$next[63:0]$11178 - attribute \src "libresoc.v:176683.5-176683.29" + assign $0\msr2__data_o$next[63:0]$11222 $7\msr2__data_o$next[63:0]$11229 + attribute \src "libresoc.v:178779.5-178779.29" switch \initial - attribute \src "libresoc.v:176683.9-176683.17" + attribute \src "libresoc.v:178779.9-178779.17" case 1'1 case end @@ -365604,75 +368475,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\msr2__data_o$next[63:0]$11172 $6\msr2__data_o$next[63:0]$11177 + assign $1\msr2__data_o$next[63:0]$11223 $6\msr2__data_o$next[63:0]$11228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr2__data_o$next[63:0]$11173 \nia2__data_i + assign $2\msr2__data_o$next[63:0]$11224 \nia2__data_i case - assign $2\msr2__data_o$next[63:0]$11173 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr2__data_o$next[63:0]$11224 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr2__data_o$next[63:0]$11174 \msr2__data_i + assign $3\msr2__data_o$next[63:0]$11225 \msr2__data_i case - assign $3\msr2__data_o$next[63:0]$11174 $2\msr2__data_o$next[63:0]$11173 + assign $3\msr2__data_o$next[63:0]$11225 $2\msr2__data_o$next[63:0]$11224 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$11175 \sv2__data_i + assign $4\msr2__data_o$next[63:0]$11226 \sv2__data_i case - assign $4\msr2__data_o$next[63:0]$11175 $3\msr2__data_o$next[63:0]$11174 + assign $4\msr2__data_o$next[63:0]$11226 $3\msr2__data_o$next[63:0]$11225 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$11176 \d_wr12__data_i + assign $5\msr2__data_o$next[63:0]$11227 \d_wr12__data_i case - assign $5\msr2__data_o$next[63:0]$11176 $4\msr2__data_o$next[63:0]$11175 + assign $5\msr2__data_o$next[63:0]$11227 $4\msr2__data_o$next[63:0]$11226 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$11177 \reg + assign $6\msr2__data_o$next[63:0]$11228 \reg case - assign $6\msr2__data_o$next[63:0]$11177 $5\msr2__data_o$next[63:0]$11176 + assign $6\msr2__data_o$next[63:0]$11228 $5\msr2__data_o$next[63:0]$11227 end case - assign $1\msr2__data_o$next[63:0]$11172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr2__data_o$next[63:0]$11223 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr2__data_o$next[63:0]$11178 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr2__data_o$next[63:0]$11229 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr2__data_o$next[63:0]$11178 $1\msr2__data_o$next[63:0]$11172 + assign $7\msr2__data_o$next[63:0]$11229 $1\msr2__data_o$next[63:0]$11223 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11171 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11222 end - attribute \src "libresoc.v:176728.3-176763.6" - process $proc$libresoc.v:176728$11179 + attribute \src "libresoc.v:178824.3-178859.6" + process $proc$libresoc.v:178824$11230 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11180 $1\wr_detect$4[0:0]$11181 - attribute \src "libresoc.v:176729.5-176729.29" + assign $0\wr_detect$4[0:0]$11231 $1\wr_detect$4[0:0]$11232 + attribute \src "libresoc.v:178825.5-178825.29" switch \initial - attribute \src "libresoc.v:176729.9-176729.17" + attribute \src "libresoc.v:178825.9-178825.17" case 1'1 case end @@ -365685,58 +368556,58 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11181 $5\wr_detect$4[0:0]$11185 + assign $1\wr_detect$4[0:0]$11232 $5\wr_detect$4[0:0]$11236 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11182 1'1 + assign $2\wr_detect$4[0:0]$11233 1'1 case - assign $2\wr_detect$4[0:0]$11182 1'0 + assign $2\wr_detect$4[0:0]$11233 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11183 1'1 + assign $3\wr_detect$4[0:0]$11234 1'1 case - assign $3\wr_detect$4[0:0]$11183 $2\wr_detect$4[0:0]$11182 + assign $3\wr_detect$4[0:0]$11234 $2\wr_detect$4[0:0]$11233 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11184 1'1 + assign $4\wr_detect$4[0:0]$11235 1'1 case - assign $4\wr_detect$4[0:0]$11184 $3\wr_detect$4[0:0]$11183 + assign $4\wr_detect$4[0:0]$11235 $3\wr_detect$4[0:0]$11234 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11185 1'1 + assign $5\wr_detect$4[0:0]$11236 1'1 case - assign $5\wr_detect$4[0:0]$11185 $4\wr_detect$4[0:0]$11184 + assign $5\wr_detect$4[0:0]$11236 $4\wr_detect$4[0:0]$11235 end case - assign $1\wr_detect$4[0:0]$11181 1'0 + assign $1\wr_detect$4[0:0]$11232 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11180 + update \wr_detect$4 $0\wr_detect$4[0:0]$11231 end - attribute \src "libresoc.v:176764.3-176809.6" - process $proc$libresoc.v:176764$11186 + attribute \src "libresoc.v:178860.3-178905.6" + process $proc$libresoc.v:178860$11237 assign { } { } assign { } { } assign { } { } - assign $0\sv2__data_o$next[63:0]$11187 $7\sv2__data_o$next[63:0]$11194 - attribute \src "libresoc.v:176765.5-176765.29" + assign $0\sv2__data_o$next[63:0]$11238 $7\sv2__data_o$next[63:0]$11245 + attribute \src "libresoc.v:178861.5-178861.29" switch \initial - attribute \src "libresoc.v:176765.9-176765.17" + attribute \src "libresoc.v:178861.9-178861.17" case 1'1 case end @@ -365749,75 +368620,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\sv2__data_o$next[63:0]$11188 $6\sv2__data_o$next[63:0]$11193 + assign $1\sv2__data_o$next[63:0]$11239 $6\sv2__data_o$next[63:0]$11244 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv2__data_o$next[63:0]$11189 \nia2__data_i + assign $2\sv2__data_o$next[63:0]$11240 \nia2__data_i case - assign $2\sv2__data_o$next[63:0]$11189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv2__data_o$next[63:0]$11240 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv2__data_o$next[63:0]$11190 \msr2__data_i + assign $3\sv2__data_o$next[63:0]$11241 \msr2__data_i case - assign $3\sv2__data_o$next[63:0]$11190 $2\sv2__data_o$next[63:0]$11189 + assign $3\sv2__data_o$next[63:0]$11241 $2\sv2__data_o$next[63:0]$11240 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv2__data_o$next[63:0]$11191 \sv2__data_i + assign $4\sv2__data_o$next[63:0]$11242 \sv2__data_i case - assign $4\sv2__data_o$next[63:0]$11191 $3\sv2__data_o$next[63:0]$11190 + assign $4\sv2__data_o$next[63:0]$11242 $3\sv2__data_o$next[63:0]$11241 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv2__data_o$next[63:0]$11192 \d_wr12__data_i + assign $5\sv2__data_o$next[63:0]$11243 \d_wr12__data_i case - assign $5\sv2__data_o$next[63:0]$11192 $4\sv2__data_o$next[63:0]$11191 + assign $5\sv2__data_o$next[63:0]$11243 $4\sv2__data_o$next[63:0]$11242 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv2__data_o$next[63:0]$11193 \reg + assign $6\sv2__data_o$next[63:0]$11244 \reg case - assign $6\sv2__data_o$next[63:0]$11193 $5\sv2__data_o$next[63:0]$11192 + assign $6\sv2__data_o$next[63:0]$11244 $5\sv2__data_o$next[63:0]$11243 end case - assign $1\sv2__data_o$next[63:0]$11188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv2__data_o$next[63:0]$11239 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv2__data_o$next[63:0]$11194 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv2__data_o$next[63:0]$11245 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv2__data_o$next[63:0]$11194 $1\sv2__data_o$next[63:0]$11188 + assign $7\sv2__data_o$next[63:0]$11245 $1\sv2__data_o$next[63:0]$11239 end sync always - update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11187 + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11238 end - attribute \src "libresoc.v:176810.3-176845.6" - process $proc$libresoc.v:176810$11195 + attribute \src "libresoc.v:178906.3-178941.6" + process $proc$libresoc.v:178906$11246 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11196 $1\wr_detect$7[0:0]$11197 - attribute \src "libresoc.v:176811.5-176811.29" + assign $0\wr_detect$7[0:0]$11247 $1\wr_detect$7[0:0]$11248 + attribute \src "libresoc.v:178907.5-178907.29" switch \initial - attribute \src "libresoc.v:176811.9-176811.17" + attribute \src "libresoc.v:178907.9-178907.17" case 1'1 case end @@ -365830,61 +368701,61 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11197 $5\wr_detect$7[0:0]$11201 + assign $1\wr_detect$7[0:0]$11248 $5\wr_detect$7[0:0]$11252 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11198 1'1 + assign $2\wr_detect$7[0:0]$11249 1'1 case - assign $2\wr_detect$7[0:0]$11198 1'0 + assign $2\wr_detect$7[0:0]$11249 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11199 1'1 + assign $3\wr_detect$7[0:0]$11250 1'1 case - assign $3\wr_detect$7[0:0]$11199 $2\wr_detect$7[0:0]$11198 + assign $3\wr_detect$7[0:0]$11250 $2\wr_detect$7[0:0]$11249 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11200 1'1 + assign $4\wr_detect$7[0:0]$11251 1'1 case - assign $4\wr_detect$7[0:0]$11200 $3\wr_detect$7[0:0]$11199 + assign $4\wr_detect$7[0:0]$11251 $3\wr_detect$7[0:0]$11250 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11201 1'1 + assign $5\wr_detect$7[0:0]$11252 1'1 case - assign $5\wr_detect$7[0:0]$11201 $4\wr_detect$7[0:0]$11200 + assign $5\wr_detect$7[0:0]$11252 $4\wr_detect$7[0:0]$11251 end case - assign $1\wr_detect$7[0:0]$11197 1'0 + assign $1\wr_detect$7[0:0]$11248 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11196 + update \wr_detect$7 $0\wr_detect$7[0:0]$11247 end - attribute \src "libresoc.v:176846.3-176878.6" - process $proc$libresoc.v:176846$11202 + attribute \src "libresoc.v:178942.3-178974.6" + process $proc$libresoc.v:178942$11253 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11203 $5\reg$next[63:0]$11208 - attribute \src "libresoc.v:176847.5-176847.29" + assign $0\reg$next[63:0]$11254 $5\reg$next[63:0]$11259 + attribute \src "libresoc.v:178943.5-178943.29" switch \initial - attribute \src "libresoc.v:176847.9-176847.17" + attribute \src "libresoc.v:178943.9-178943.17" case 1'1 case end @@ -365893,224 +368764,224 @@ module \reg_2$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11204 \nia2__data_i + assign $1\reg$next[63:0]$11255 \nia2__data_i case - assign $1\reg$next[63:0]$11204 \reg + assign $1\reg$next[63:0]$11255 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11205 \msr2__data_i + assign $2\reg$next[63:0]$11256 \msr2__data_i case - assign $2\reg$next[63:0]$11205 $1\reg$next[63:0]$11204 + assign $2\reg$next[63:0]$11256 $1\reg$next[63:0]$11255 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11206 \sv2__data_i + assign $3\reg$next[63:0]$11257 \sv2__data_i case - assign $3\reg$next[63:0]$11206 $2\reg$next[63:0]$11205 + assign $3\reg$next[63:0]$11257 $2\reg$next[63:0]$11256 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11207 \d_wr12__data_i + assign $4\reg$next[63:0]$11258 \d_wr12__data_i case - assign $4\reg$next[63:0]$11207 $3\reg$next[63:0]$11206 + assign $4\reg$next[63:0]$11258 $3\reg$next[63:0]$11257 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11208 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11259 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11208 $4\reg$next[63:0]$11207 + assign $5\reg$next[63:0]$11259 $4\reg$next[63:0]$11258 end sync always - update \reg$next $0\reg$next[63:0]$11203 + update \reg$next $0\reg$next[63:0]$11254 end - connect \$1 $not$libresoc.v:176589$11153_Y - connect \$3 $not$libresoc.v:176590$11154_Y - connect \$6 $not$libresoc.v:176591$11155_Y + connect \$1 $not$libresoc.v:178685$11204_Y + connect \$3 $not$libresoc.v:178686$11205_Y + connect \$6 $not$libresoc.v:178687$11206_Y end -attribute \src "libresoc.v:176883.1-177354.10" +attribute \src "libresoc.v:178979.1-179450.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:176884.7-176884.20" + attribute \src "libresoc.v:178980.7-178980.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177284.3-177323.6" - wire width 4 $0\r23__data_o$next[3:0]$11283 - attribute \src "libresoc.v:176967.3-176968.39" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $0\r23__data_o$next[3:0]$11334 + attribute \src "libresoc.v:179063.3-179064.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:177214.3-177253.6" - wire width 4 $0\r3__data_o$next[3:0]$11269 - attribute \src "libresoc.v:176969.3-176970.37" + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $0\r3__data_o$next[3:0]$11320 + attribute \src "libresoc.v:179065.3-179066.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:177047.3-177073.6" - wire width 4 $0\reg$next[3:0]$11235 - attribute \src "libresoc.v:176965.3-176966.25" + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $0\reg$next[3:0]$11286 + attribute \src "libresoc.v:179061.3-179062.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:176977.3-177016.6" - wire width 4 $0\src13__data_o$next[3:0]$11226 - attribute \src "libresoc.v:176975.3-176976.43" + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $0\src13__data_o$next[3:0]$11277 + attribute \src "libresoc.v:179071.3-179072.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:177074.3-177113.6" - wire width 4 $0\src23__data_o$next[3:0]$11241 - attribute \src "libresoc.v:176973.3-176974.43" + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $0\src23__data_o$next[3:0]$11292 + attribute \src "libresoc.v:179069.3-179070.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:177144.3-177183.6" - wire width 4 $0\src33__data_o$next[3:0]$11255 - attribute \src "libresoc.v:176971.3-176972.43" + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $0\src33__data_o$next[3:0]$11306 + attribute \src "libresoc.v:179067.3-179068.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:177254.3-177283.6" - wire $0\wr_detect$10[0:0]$11277 - attribute \src "libresoc.v:177324.3-177353.6" - wire $0\wr_detect$13[0:0]$11291 - attribute \src "libresoc.v:177114.3-177143.6" - wire $0\wr_detect$4[0:0]$11249 - attribute \src "libresoc.v:177184.3-177213.6" - wire $0\wr_detect$7[0:0]$11263 - attribute \src "libresoc.v:177017.3-177046.6" + attribute \src "libresoc.v:179350.3-179379.6" + wire $0\wr_detect$10[0:0]$11328 + attribute \src "libresoc.v:179420.3-179449.6" + wire $0\wr_detect$13[0:0]$11342 + attribute \src "libresoc.v:179210.3-179239.6" + wire $0\wr_detect$4[0:0]$11300 + attribute \src "libresoc.v:179280.3-179309.6" + wire $0\wr_detect$7[0:0]$11314 + attribute \src "libresoc.v:179113.3-179142.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177284.3-177323.6" - wire width 4 $1\r23__data_o$next[3:0]$11284 - attribute \src "libresoc.v:176909.13-176909.31" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $1\r23__data_o$next[3:0]$11335 + attribute \src "libresoc.v:179005.13-179005.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:177214.3-177253.6" - wire width 4 $1\r3__data_o$next[3:0]$11270 - attribute \src "libresoc.v:176916.13-176916.30" + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $1\r3__data_o$next[3:0]$11321 + attribute \src "libresoc.v:179012.13-179012.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:177047.3-177073.6" - wire width 4 $1\reg$next[3:0]$11236 - attribute \src "libresoc.v:176922.13-176922.25" + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $1\reg$next[3:0]$11287 + attribute \src "libresoc.v:179018.13-179018.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:176977.3-177016.6" - wire width 4 $1\src13__data_o$next[3:0]$11227 - attribute \src "libresoc.v:176927.13-176927.33" + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $1\src13__data_o$next[3:0]$11278 + attribute \src "libresoc.v:179023.13-179023.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:177074.3-177113.6" - wire width 4 $1\src23__data_o$next[3:0]$11242 - attribute \src "libresoc.v:176934.13-176934.33" + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $1\src23__data_o$next[3:0]$11293 + attribute \src "libresoc.v:179030.13-179030.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:177144.3-177183.6" - wire width 4 $1\src33__data_o$next[3:0]$11256 - attribute \src "libresoc.v:176941.13-176941.33" + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $1\src33__data_o$next[3:0]$11307 + attribute \src "libresoc.v:179037.13-179037.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:177254.3-177283.6" - wire $1\wr_detect$10[0:0]$11278 - attribute \src "libresoc.v:177324.3-177353.6" - wire $1\wr_detect$13[0:0]$11292 - attribute \src "libresoc.v:177114.3-177143.6" - wire $1\wr_detect$4[0:0]$11250 - attribute \src "libresoc.v:177184.3-177213.6" - wire $1\wr_detect$7[0:0]$11264 - attribute \src "libresoc.v:177017.3-177046.6" + attribute \src "libresoc.v:179350.3-179379.6" + wire $1\wr_detect$10[0:0]$11329 + attribute \src "libresoc.v:179420.3-179449.6" + wire $1\wr_detect$13[0:0]$11343 + attribute \src "libresoc.v:179210.3-179239.6" + wire $1\wr_detect$4[0:0]$11301 + attribute \src "libresoc.v:179280.3-179309.6" + wire $1\wr_detect$7[0:0]$11315 + attribute \src "libresoc.v:179113.3-179142.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177284.3-177323.6" - wire width 4 $2\r23__data_o$next[3:0]$11285 - attribute \src "libresoc.v:177214.3-177253.6" - wire width 4 $2\r3__data_o$next[3:0]$11271 - attribute \src "libresoc.v:177047.3-177073.6" - wire width 4 $2\reg$next[3:0]$11237 - attribute \src "libresoc.v:176977.3-177016.6" - wire width 4 $2\src13__data_o$next[3:0]$11228 - attribute \src "libresoc.v:177074.3-177113.6" - wire width 4 $2\src23__data_o$next[3:0]$11243 - attribute \src "libresoc.v:177144.3-177183.6" - wire width 4 $2\src33__data_o$next[3:0]$11257 - attribute \src "libresoc.v:177254.3-177283.6" - wire $2\wr_detect$10[0:0]$11279 - attribute \src "libresoc.v:177324.3-177353.6" - wire $2\wr_detect$13[0:0]$11293 - attribute \src "libresoc.v:177114.3-177143.6" - wire $2\wr_detect$4[0:0]$11251 - attribute \src "libresoc.v:177184.3-177213.6" - wire $2\wr_detect$7[0:0]$11265 - attribute \src "libresoc.v:177017.3-177046.6" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $2\r23__data_o$next[3:0]$11336 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $2\r3__data_o$next[3:0]$11322 + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $2\reg$next[3:0]$11288 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $2\src13__data_o$next[3:0]$11279 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $2\src23__data_o$next[3:0]$11294 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $2\src33__data_o$next[3:0]$11308 + attribute \src "libresoc.v:179350.3-179379.6" + wire $2\wr_detect$10[0:0]$11330 + attribute \src "libresoc.v:179420.3-179449.6" + wire $2\wr_detect$13[0:0]$11344 + attribute \src "libresoc.v:179210.3-179239.6" + wire $2\wr_detect$4[0:0]$11302 + attribute \src "libresoc.v:179280.3-179309.6" + wire $2\wr_detect$7[0:0]$11316 + attribute \src "libresoc.v:179113.3-179142.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177284.3-177323.6" - wire width 4 $3\r23__data_o$next[3:0]$11286 - attribute \src "libresoc.v:177214.3-177253.6" - wire width 4 $3\r3__data_o$next[3:0]$11272 - attribute \src "libresoc.v:177047.3-177073.6" - wire width 4 $3\reg$next[3:0]$11238 - attribute \src "libresoc.v:176977.3-177016.6" - wire width 4 $3\src13__data_o$next[3:0]$11229 - attribute \src "libresoc.v:177074.3-177113.6" - wire width 4 $3\src23__data_o$next[3:0]$11244 - attribute \src "libresoc.v:177144.3-177183.6" - wire width 4 $3\src33__data_o$next[3:0]$11258 - attribute \src "libresoc.v:177254.3-177283.6" - wire $3\wr_detect$10[0:0]$11280 - attribute \src "libresoc.v:177324.3-177353.6" - wire $3\wr_detect$13[0:0]$11294 - attribute \src "libresoc.v:177114.3-177143.6" - wire $3\wr_detect$4[0:0]$11252 - attribute \src "libresoc.v:177184.3-177213.6" - wire $3\wr_detect$7[0:0]$11266 - attribute \src "libresoc.v:177017.3-177046.6" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $3\r23__data_o$next[3:0]$11337 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $3\r3__data_o$next[3:0]$11323 + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $3\reg$next[3:0]$11289 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $3\src13__data_o$next[3:0]$11280 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $3\src23__data_o$next[3:0]$11295 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $3\src33__data_o$next[3:0]$11309 + attribute \src "libresoc.v:179350.3-179379.6" + wire $3\wr_detect$10[0:0]$11331 + attribute \src "libresoc.v:179420.3-179449.6" + wire $3\wr_detect$13[0:0]$11345 + attribute \src "libresoc.v:179210.3-179239.6" + wire $3\wr_detect$4[0:0]$11303 + attribute \src "libresoc.v:179280.3-179309.6" + wire $3\wr_detect$7[0:0]$11317 + attribute \src "libresoc.v:179113.3-179142.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177284.3-177323.6" - wire width 4 $4\r23__data_o$next[3:0]$11287 - attribute \src "libresoc.v:177214.3-177253.6" - wire width 4 $4\r3__data_o$next[3:0]$11273 - attribute \src "libresoc.v:177047.3-177073.6" - wire width 4 $4\reg$next[3:0]$11239 - attribute \src "libresoc.v:176977.3-177016.6" - wire width 4 $4\src13__data_o$next[3:0]$11230 - attribute \src "libresoc.v:177074.3-177113.6" - wire width 4 $4\src23__data_o$next[3:0]$11245 - attribute \src "libresoc.v:177144.3-177183.6" - wire width 4 $4\src33__data_o$next[3:0]$11259 - attribute \src "libresoc.v:177254.3-177283.6" - wire $4\wr_detect$10[0:0]$11281 - attribute \src "libresoc.v:177324.3-177353.6" - wire $4\wr_detect$13[0:0]$11295 - attribute \src "libresoc.v:177114.3-177143.6" - wire $4\wr_detect$4[0:0]$11253 - attribute \src "libresoc.v:177184.3-177213.6" - wire $4\wr_detect$7[0:0]$11267 - attribute \src "libresoc.v:177017.3-177046.6" + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $4\r23__data_o$next[3:0]$11338 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $4\r3__data_o$next[3:0]$11324 + attribute \src "libresoc.v:179143.3-179169.6" + wire width 4 $4\reg$next[3:0]$11290 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $4\src13__data_o$next[3:0]$11281 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $4\src23__data_o$next[3:0]$11296 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $4\src33__data_o$next[3:0]$11310 + attribute \src "libresoc.v:179350.3-179379.6" + wire $4\wr_detect$10[0:0]$11332 + attribute \src "libresoc.v:179420.3-179449.6" + wire $4\wr_detect$13[0:0]$11346 + attribute \src "libresoc.v:179210.3-179239.6" + wire $4\wr_detect$4[0:0]$11304 + attribute \src "libresoc.v:179280.3-179309.6" + wire $4\wr_detect$7[0:0]$11318 + attribute \src "libresoc.v:179113.3-179142.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177284.3-177323.6" - wire width 4 $5\r23__data_o$next[3:0]$11288 - attribute \src "libresoc.v:177214.3-177253.6" - wire width 4 $5\r3__data_o$next[3:0]$11274 - attribute \src "libresoc.v:176977.3-177016.6" - wire width 4 $5\src13__data_o$next[3:0]$11231 - attribute \src "libresoc.v:177074.3-177113.6" - wire width 4 $5\src23__data_o$next[3:0]$11246 - attribute \src "libresoc.v:177144.3-177183.6" - wire width 4 $5\src33__data_o$next[3:0]$11260 - attribute \src "libresoc.v:177284.3-177323.6" - wire width 4 $6\r23__data_o$next[3:0]$11289 - attribute \src "libresoc.v:177214.3-177253.6" - wire width 4 $6\r3__data_o$next[3:0]$11275 - attribute \src "libresoc.v:176977.3-177016.6" - wire width 4 $6\src13__data_o$next[3:0]$11232 - attribute \src "libresoc.v:177074.3-177113.6" - wire width 4 $6\src23__data_o$next[3:0]$11247 - attribute \src "libresoc.v:177144.3-177183.6" - wire width 4 $6\src33__data_o$next[3:0]$11261 - attribute \src "libresoc.v:176960.17-176960.104" - wire $not$libresoc.v:176960$11214_Y - attribute \src "libresoc.v:176961.18-176961.105" - wire $not$libresoc.v:176961$11215_Y - attribute \src "libresoc.v:176962.17-176962.100" - wire $not$libresoc.v:176962$11216_Y - attribute \src "libresoc.v:176963.17-176963.103" - wire $not$libresoc.v:176963$11217_Y - attribute \src "libresoc.v:176964.17-176964.103" - wire $not$libresoc.v:176964$11218_Y + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $5\r23__data_o$next[3:0]$11339 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $5\r3__data_o$next[3:0]$11325 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $5\src13__data_o$next[3:0]$11282 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $5\src23__data_o$next[3:0]$11297 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $5\src33__data_o$next[3:0]$11311 + attribute \src "libresoc.v:179380.3-179419.6" + wire width 4 $6\r23__data_o$next[3:0]$11340 + attribute \src "libresoc.v:179310.3-179349.6" + wire width 4 $6\r3__data_o$next[3:0]$11326 + attribute \src "libresoc.v:179073.3-179112.6" + wire width 4 $6\src13__data_o$next[3:0]$11283 + attribute \src "libresoc.v:179170.3-179209.6" + wire width 4 $6\src23__data_o$next[3:0]$11298 + attribute \src "libresoc.v:179240.3-179279.6" + wire width 4 $6\src33__data_o$next[3:0]$11312 + attribute \src "libresoc.v:179056.17-179056.104" + wire $not$libresoc.v:179056$11265_Y + attribute \src "libresoc.v:179057.18-179057.105" + wire $not$libresoc.v:179057$11266_Y + attribute \src "libresoc.v:179058.17-179058.100" + wire $not$libresoc.v:179058$11267_Y + attribute \src "libresoc.v:179059.17-179059.103" + wire $not$libresoc.v:179059$11268_Y + attribute \src "libresoc.v:179060.17-179060.103" + wire $not$libresoc.v:179060$11269_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -366121,9 +368992,9 @@ module \reg_3 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest13__data_i @@ -366133,7 +369004,7 @@ module \reg_3 wire width 4 input 11 \dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest23__wen - attribute \src "libresoc.v:176884.7-176884.15" + attribute \src "libresoc.v:178980.7-178980.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r23__data_o @@ -366184,152 +369055,152 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176960$11214 + cell $not $not$libresoc.v:179056$11265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176960$11214_Y + connect \Y $not$libresoc.v:179056$11265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176961$11215 + cell $not $not$libresoc.v:179057$11266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:176961$11215_Y + connect \Y $not$libresoc.v:179057$11266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176962$11216 + cell $not $not$libresoc.v:179058$11267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176962$11216_Y + connect \Y $not$libresoc.v:179058$11267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176963$11217 + cell $not $not$libresoc.v:179059$11268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176963$11217_Y + connect \Y $not$libresoc.v:179059$11268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176964$11218 + cell $not $not$libresoc.v:179060$11269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176964$11218_Y + connect \Y $not$libresoc.v:179060$11269_Y end - attribute \src "libresoc.v:176884.7-176884.20" - process $proc$libresoc.v:176884$11296 + attribute \src "libresoc.v:178980.7-178980.20" + process $proc$libresoc.v:178980$11347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176909.13-176909.31" - process $proc$libresoc.v:176909$11297 + attribute \src "libresoc.v:179005.13-179005.31" + process $proc$libresoc.v:179005$11348 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:176916.13-176916.30" - process $proc$libresoc.v:176916$11298 + attribute \src "libresoc.v:179012.13-179012.30" + process $proc$libresoc.v:179012$11349 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:176922.13-176922.25" - process $proc$libresoc.v:176922$11299 + attribute \src "libresoc.v:179018.13-179018.25" + process $proc$libresoc.v:179018$11350 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:176927.13-176927.33" - process $proc$libresoc.v:176927$11300 + attribute \src "libresoc.v:179023.13-179023.33" + process $proc$libresoc.v:179023$11351 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:176934.13-176934.33" - process $proc$libresoc.v:176934$11301 + attribute \src "libresoc.v:179030.13-179030.33" + process $proc$libresoc.v:179030$11352 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:176941.13-176941.33" - process $proc$libresoc.v:176941$11302 + attribute \src "libresoc.v:179037.13-179037.33" + process $proc$libresoc.v:179037$11353 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:176965.3-176966.25" - process $proc$libresoc.v:176965$11219 + attribute \src "libresoc.v:179061.3-179062.25" + process $proc$libresoc.v:179061$11270 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:176967.3-176968.39" - process $proc$libresoc.v:176967$11220 + attribute \src "libresoc.v:179063.3-179064.39" + process $proc$libresoc.v:179063$11271 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:176969.3-176970.37" - process $proc$libresoc.v:176969$11221 + attribute \src "libresoc.v:179065.3-179066.37" + process $proc$libresoc.v:179065$11272 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:176971.3-176972.43" - process $proc$libresoc.v:176971$11222 + attribute \src "libresoc.v:179067.3-179068.43" + process $proc$libresoc.v:179067$11273 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:176973.3-176974.43" - process $proc$libresoc.v:176973$11223 + attribute \src "libresoc.v:179069.3-179070.43" + process $proc$libresoc.v:179069$11274 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:176975.3-176976.43" - process $proc$libresoc.v:176975$11224 + attribute \src "libresoc.v:179071.3-179072.43" + process $proc$libresoc.v:179071$11275 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:176977.3-177016.6" - process $proc$libresoc.v:176977$11225 + attribute \src "libresoc.v:179073.3-179112.6" + process $proc$libresoc.v:179073$11276 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$11226 $6\src13__data_o$next[3:0]$11232 - attribute \src "libresoc.v:176978.5-176978.29" + assign $0\src13__data_o$next[3:0]$11277 $6\src13__data_o$next[3:0]$11283 + attribute \src "libresoc.v:179074.5-179074.29" switch \initial - attribute \src "libresoc.v:176978.9-176978.17" + attribute \src "libresoc.v:179074.9-179074.17" case 1'1 case end @@ -366341,66 +369212,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$11227 $5\src13__data_o$next[3:0]$11231 + assign $1\src13__data_o$next[3:0]$11278 $5\src13__data_o$next[3:0]$11282 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$11228 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11279 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$11228 4'0000 + assign $2\src13__data_o$next[3:0]$11279 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$11229 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11280 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$11229 $2\src13__data_o$next[3:0]$11228 + assign $3\src13__data_o$next[3:0]$11280 $2\src13__data_o$next[3:0]$11279 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$11230 \w3__data_i + assign $4\src13__data_o$next[3:0]$11281 \w3__data_i case - assign $4\src13__data_o$next[3:0]$11230 $3\src13__data_o$next[3:0]$11229 + assign $4\src13__data_o$next[3:0]$11281 $3\src13__data_o$next[3:0]$11280 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$11231 \reg + assign $5\src13__data_o$next[3:0]$11282 \reg case - assign $5\src13__data_o$next[3:0]$11231 $4\src13__data_o$next[3:0]$11230 + assign $5\src13__data_o$next[3:0]$11282 $4\src13__data_o$next[3:0]$11281 end case - assign $1\src13__data_o$next[3:0]$11227 4'0000 + assign $1\src13__data_o$next[3:0]$11278 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$11232 4'0000 + assign $6\src13__data_o$next[3:0]$11283 4'0000 case - assign $6\src13__data_o$next[3:0]$11232 $1\src13__data_o$next[3:0]$11227 + assign $6\src13__data_o$next[3:0]$11283 $1\src13__data_o$next[3:0]$11278 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11226 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11277 end - attribute \src "libresoc.v:177017.3-177046.6" - process $proc$libresoc.v:177017$11233 + attribute \src "libresoc.v:179113.3-179142.6" + process $proc$libresoc.v:179113$11284 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177018.5-177018.29" + attribute \src "libresoc.v:179114.5-179114.29" switch \initial - attribute \src "libresoc.v:177018.9-177018.17" + attribute \src "libresoc.v:179114.9-179114.17" case 1'1 case end @@ -366446,17 +369317,17 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177047.3-177073.6" - process $proc$libresoc.v:177047$11234 + attribute \src "libresoc.v:179143.3-179169.6" + process $proc$libresoc.v:179143$11285 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11235 $4\reg$next[3:0]$11239 - attribute \src "libresoc.v:177048.5-177048.29" + assign $0\reg$next[3:0]$11286 $4\reg$next[3:0]$11290 + attribute \src "libresoc.v:179144.5-179144.29" switch \initial - attribute \src "libresoc.v:177048.9-177048.17" + attribute \src "libresoc.v:179144.9-179144.17" case 1'1 case end @@ -366465,49 +369336,49 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11236 \dest13__data_i + assign $1\reg$next[3:0]$11287 \dest13__data_i case - assign $1\reg$next[3:0]$11236 \reg + assign $1\reg$next[3:0]$11287 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11237 \dest23__data_i + assign $2\reg$next[3:0]$11288 \dest23__data_i case - assign $2\reg$next[3:0]$11237 $1\reg$next[3:0]$11236 + assign $2\reg$next[3:0]$11288 $1\reg$next[3:0]$11287 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11238 \w3__data_i + assign $3\reg$next[3:0]$11289 \w3__data_i case - assign $3\reg$next[3:0]$11238 $2\reg$next[3:0]$11237 + assign $3\reg$next[3:0]$11289 $2\reg$next[3:0]$11288 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11239 4'0000 + assign $4\reg$next[3:0]$11290 4'0000 case - assign $4\reg$next[3:0]$11239 $3\reg$next[3:0]$11238 + assign $4\reg$next[3:0]$11290 $3\reg$next[3:0]$11289 end sync always - update \reg$next $0\reg$next[3:0]$11235 + update \reg$next $0\reg$next[3:0]$11286 end - attribute \src "libresoc.v:177074.3-177113.6" - process $proc$libresoc.v:177074$11240 + attribute \src "libresoc.v:179170.3-179209.6" + process $proc$libresoc.v:179170$11291 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$11241 $6\src23__data_o$next[3:0]$11247 - attribute \src "libresoc.v:177075.5-177075.29" + assign $0\src23__data_o$next[3:0]$11292 $6\src23__data_o$next[3:0]$11298 + attribute \src "libresoc.v:179171.5-179171.29" switch \initial - attribute \src "libresoc.v:177075.9-177075.17" + attribute \src "libresoc.v:179171.9-179171.17" case 1'1 case end @@ -366519,66 +369390,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$11242 $5\src23__data_o$next[3:0]$11246 + assign $1\src23__data_o$next[3:0]$11293 $5\src23__data_o$next[3:0]$11297 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$11243 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11294 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$11243 4'0000 + assign $2\src23__data_o$next[3:0]$11294 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$11244 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11295 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$11244 $2\src23__data_o$next[3:0]$11243 + assign $3\src23__data_o$next[3:0]$11295 $2\src23__data_o$next[3:0]$11294 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$11245 \w3__data_i + assign $4\src23__data_o$next[3:0]$11296 \w3__data_i case - assign $4\src23__data_o$next[3:0]$11245 $3\src23__data_o$next[3:0]$11244 + assign $4\src23__data_o$next[3:0]$11296 $3\src23__data_o$next[3:0]$11295 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$11246 \reg + assign $5\src23__data_o$next[3:0]$11297 \reg case - assign $5\src23__data_o$next[3:0]$11246 $4\src23__data_o$next[3:0]$11245 + assign $5\src23__data_o$next[3:0]$11297 $4\src23__data_o$next[3:0]$11296 end case - assign $1\src23__data_o$next[3:0]$11242 4'0000 + assign $1\src23__data_o$next[3:0]$11293 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$11247 4'0000 + assign $6\src23__data_o$next[3:0]$11298 4'0000 case - assign $6\src23__data_o$next[3:0]$11247 $1\src23__data_o$next[3:0]$11242 + assign $6\src23__data_o$next[3:0]$11298 $1\src23__data_o$next[3:0]$11293 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11241 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11292 end - attribute \src "libresoc.v:177114.3-177143.6" - process $proc$libresoc.v:177114$11248 + attribute \src "libresoc.v:179210.3-179239.6" + process $proc$libresoc.v:179210$11299 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11249 $1\wr_detect$4[0:0]$11250 - attribute \src "libresoc.v:177115.5-177115.29" + assign $0\wr_detect$4[0:0]$11300 $1\wr_detect$4[0:0]$11301 + attribute \src "libresoc.v:179211.5-179211.29" switch \initial - attribute \src "libresoc.v:177115.9-177115.17" + attribute \src "libresoc.v:179211.9-179211.17" case 1'1 case end @@ -366590,49 +369461,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11250 $4\wr_detect$4[0:0]$11253 + assign $1\wr_detect$4[0:0]$11301 $4\wr_detect$4[0:0]$11304 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11251 1'1 + assign $2\wr_detect$4[0:0]$11302 1'1 case - assign $2\wr_detect$4[0:0]$11251 1'0 + assign $2\wr_detect$4[0:0]$11302 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11252 1'1 + assign $3\wr_detect$4[0:0]$11303 1'1 case - assign $3\wr_detect$4[0:0]$11252 $2\wr_detect$4[0:0]$11251 + assign $3\wr_detect$4[0:0]$11303 $2\wr_detect$4[0:0]$11302 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11253 1'1 + assign $4\wr_detect$4[0:0]$11304 1'1 case - assign $4\wr_detect$4[0:0]$11253 $3\wr_detect$4[0:0]$11252 + assign $4\wr_detect$4[0:0]$11304 $3\wr_detect$4[0:0]$11303 end case - assign $1\wr_detect$4[0:0]$11250 1'0 + assign $1\wr_detect$4[0:0]$11301 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11249 + update \wr_detect$4 $0\wr_detect$4[0:0]$11300 end - attribute \src "libresoc.v:177144.3-177183.6" - process $proc$libresoc.v:177144$11254 + attribute \src "libresoc.v:179240.3-179279.6" + process $proc$libresoc.v:179240$11305 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11255 $6\src33__data_o$next[3:0]$11261 - attribute \src "libresoc.v:177145.5-177145.29" + assign $0\src33__data_o$next[3:0]$11306 $6\src33__data_o$next[3:0]$11312 + attribute \src "libresoc.v:179241.5-179241.29" switch \initial - attribute \src "libresoc.v:177145.9-177145.17" + attribute \src "libresoc.v:179241.9-179241.17" case 1'1 case end @@ -366644,66 +369515,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$11256 $5\src33__data_o$next[3:0]$11260 + assign $1\src33__data_o$next[3:0]$11307 $5\src33__data_o$next[3:0]$11311 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$11257 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11308 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$11257 4'0000 + assign $2\src33__data_o$next[3:0]$11308 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$11258 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11309 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$11258 $2\src33__data_o$next[3:0]$11257 + assign $3\src33__data_o$next[3:0]$11309 $2\src33__data_o$next[3:0]$11308 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$11259 \w3__data_i + assign $4\src33__data_o$next[3:0]$11310 \w3__data_i case - assign $4\src33__data_o$next[3:0]$11259 $3\src33__data_o$next[3:0]$11258 + assign $4\src33__data_o$next[3:0]$11310 $3\src33__data_o$next[3:0]$11309 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$11260 \reg + assign $5\src33__data_o$next[3:0]$11311 \reg case - assign $5\src33__data_o$next[3:0]$11260 $4\src33__data_o$next[3:0]$11259 + assign $5\src33__data_o$next[3:0]$11311 $4\src33__data_o$next[3:0]$11310 end case - assign $1\src33__data_o$next[3:0]$11256 4'0000 + assign $1\src33__data_o$next[3:0]$11307 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$11261 4'0000 + assign $6\src33__data_o$next[3:0]$11312 4'0000 case - assign $6\src33__data_o$next[3:0]$11261 $1\src33__data_o$next[3:0]$11256 + assign $6\src33__data_o$next[3:0]$11312 $1\src33__data_o$next[3:0]$11307 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11255 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11306 end - attribute \src "libresoc.v:177184.3-177213.6" - process $proc$libresoc.v:177184$11262 + attribute \src "libresoc.v:179280.3-179309.6" + process $proc$libresoc.v:179280$11313 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11263 $1\wr_detect$7[0:0]$11264 - attribute \src "libresoc.v:177185.5-177185.29" + assign $0\wr_detect$7[0:0]$11314 $1\wr_detect$7[0:0]$11315 + attribute \src "libresoc.v:179281.5-179281.29" switch \initial - attribute \src "libresoc.v:177185.9-177185.17" + attribute \src "libresoc.v:179281.9-179281.17" case 1'1 case end @@ -366715,49 +369586,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11264 $4\wr_detect$7[0:0]$11267 + assign $1\wr_detect$7[0:0]$11315 $4\wr_detect$7[0:0]$11318 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11265 1'1 + assign $2\wr_detect$7[0:0]$11316 1'1 case - assign $2\wr_detect$7[0:0]$11265 1'0 + assign $2\wr_detect$7[0:0]$11316 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11266 1'1 + assign $3\wr_detect$7[0:0]$11317 1'1 case - assign $3\wr_detect$7[0:0]$11266 $2\wr_detect$7[0:0]$11265 + assign $3\wr_detect$7[0:0]$11317 $2\wr_detect$7[0:0]$11316 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11267 1'1 + assign $4\wr_detect$7[0:0]$11318 1'1 case - assign $4\wr_detect$7[0:0]$11267 $3\wr_detect$7[0:0]$11266 + assign $4\wr_detect$7[0:0]$11318 $3\wr_detect$7[0:0]$11317 end case - assign $1\wr_detect$7[0:0]$11264 1'0 + assign $1\wr_detect$7[0:0]$11315 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11263 + update \wr_detect$7 $0\wr_detect$7[0:0]$11314 end - attribute \src "libresoc.v:177214.3-177253.6" - process $proc$libresoc.v:177214$11268 + attribute \src "libresoc.v:179310.3-179349.6" + process $proc$libresoc.v:179310$11319 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$11269 $6\r3__data_o$next[3:0]$11275 - attribute \src "libresoc.v:177215.5-177215.29" + assign $0\r3__data_o$next[3:0]$11320 $6\r3__data_o$next[3:0]$11326 + attribute \src "libresoc.v:179311.5-179311.29" switch \initial - attribute \src "libresoc.v:177215.9-177215.17" + attribute \src "libresoc.v:179311.9-179311.17" case 1'1 case end @@ -366769,66 +369640,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$11270 $5\r3__data_o$next[3:0]$11274 + assign $1\r3__data_o$next[3:0]$11321 $5\r3__data_o$next[3:0]$11325 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$11271 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11322 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$11271 4'0000 + assign $2\r3__data_o$next[3:0]$11322 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$11272 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11323 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$11272 $2\r3__data_o$next[3:0]$11271 + assign $3\r3__data_o$next[3:0]$11323 $2\r3__data_o$next[3:0]$11322 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$11273 \w3__data_i + assign $4\r3__data_o$next[3:0]$11324 \w3__data_i case - assign $4\r3__data_o$next[3:0]$11273 $3\r3__data_o$next[3:0]$11272 + assign $4\r3__data_o$next[3:0]$11324 $3\r3__data_o$next[3:0]$11323 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$11274 \reg + assign $5\r3__data_o$next[3:0]$11325 \reg case - assign $5\r3__data_o$next[3:0]$11274 $4\r3__data_o$next[3:0]$11273 + assign $5\r3__data_o$next[3:0]$11325 $4\r3__data_o$next[3:0]$11324 end case - assign $1\r3__data_o$next[3:0]$11270 4'0000 + assign $1\r3__data_o$next[3:0]$11321 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$11275 4'0000 + assign $6\r3__data_o$next[3:0]$11326 4'0000 case - assign $6\r3__data_o$next[3:0]$11275 $1\r3__data_o$next[3:0]$11270 + assign $6\r3__data_o$next[3:0]$11326 $1\r3__data_o$next[3:0]$11321 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11269 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11320 end - attribute \src "libresoc.v:177254.3-177283.6" - process $proc$libresoc.v:177254$11276 + attribute \src "libresoc.v:179350.3-179379.6" + process $proc$libresoc.v:179350$11327 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11277 $1\wr_detect$10[0:0]$11278 - attribute \src "libresoc.v:177255.5-177255.29" + assign $0\wr_detect$10[0:0]$11328 $1\wr_detect$10[0:0]$11329 + attribute \src "libresoc.v:179351.5-179351.29" switch \initial - attribute \src "libresoc.v:177255.9-177255.17" + attribute \src "libresoc.v:179351.9-179351.17" case 1'1 case end @@ -366840,49 +369711,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11278 $4\wr_detect$10[0:0]$11281 + assign $1\wr_detect$10[0:0]$11329 $4\wr_detect$10[0:0]$11332 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11279 1'1 + assign $2\wr_detect$10[0:0]$11330 1'1 case - assign $2\wr_detect$10[0:0]$11279 1'0 + assign $2\wr_detect$10[0:0]$11330 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11280 1'1 + assign $3\wr_detect$10[0:0]$11331 1'1 case - assign $3\wr_detect$10[0:0]$11280 $2\wr_detect$10[0:0]$11279 + assign $3\wr_detect$10[0:0]$11331 $2\wr_detect$10[0:0]$11330 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11281 1'1 + assign $4\wr_detect$10[0:0]$11332 1'1 case - assign $4\wr_detect$10[0:0]$11281 $3\wr_detect$10[0:0]$11280 + assign $4\wr_detect$10[0:0]$11332 $3\wr_detect$10[0:0]$11331 end case - assign $1\wr_detect$10[0:0]$11278 1'0 + assign $1\wr_detect$10[0:0]$11329 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11277 + update \wr_detect$10 $0\wr_detect$10[0:0]$11328 end - attribute \src "libresoc.v:177284.3-177323.6" - process $proc$libresoc.v:177284$11282 + attribute \src "libresoc.v:179380.3-179419.6" + process $proc$libresoc.v:179380$11333 assign { } { } assign { } { } assign { } { } - assign $0\r23__data_o$next[3:0]$11283 $6\r23__data_o$next[3:0]$11289 - attribute \src "libresoc.v:177285.5-177285.29" + assign $0\r23__data_o$next[3:0]$11334 $6\r23__data_o$next[3:0]$11340 + attribute \src "libresoc.v:179381.5-179381.29" switch \initial - attribute \src "libresoc.v:177285.9-177285.17" + attribute \src "libresoc.v:179381.9-179381.17" case 1'1 case end @@ -366894,66 +369765,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r23__data_o$next[3:0]$11284 $5\r23__data_o$next[3:0]$11288 + assign $1\r23__data_o$next[3:0]$11335 $5\r23__data_o$next[3:0]$11339 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r23__data_o$next[3:0]$11285 \dest13__data_i + assign $2\r23__data_o$next[3:0]$11336 \dest13__data_i case - assign $2\r23__data_o$next[3:0]$11285 4'0000 + assign $2\r23__data_o$next[3:0]$11336 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r23__data_o$next[3:0]$11286 \dest23__data_i + assign $3\r23__data_o$next[3:0]$11337 \dest23__data_i case - assign $3\r23__data_o$next[3:0]$11286 $2\r23__data_o$next[3:0]$11285 + assign $3\r23__data_o$next[3:0]$11337 $2\r23__data_o$next[3:0]$11336 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r23__data_o$next[3:0]$11287 \w3__data_i + assign $4\r23__data_o$next[3:0]$11338 \w3__data_i case - assign $4\r23__data_o$next[3:0]$11287 $3\r23__data_o$next[3:0]$11286 + assign $4\r23__data_o$next[3:0]$11338 $3\r23__data_o$next[3:0]$11337 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r23__data_o$next[3:0]$11288 \reg + assign $5\r23__data_o$next[3:0]$11339 \reg case - assign $5\r23__data_o$next[3:0]$11288 $4\r23__data_o$next[3:0]$11287 + assign $5\r23__data_o$next[3:0]$11339 $4\r23__data_o$next[3:0]$11338 end case - assign $1\r23__data_o$next[3:0]$11284 4'0000 + assign $1\r23__data_o$next[3:0]$11335 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r23__data_o$next[3:0]$11289 4'0000 + assign $6\r23__data_o$next[3:0]$11340 4'0000 case - assign $6\r23__data_o$next[3:0]$11289 $1\r23__data_o$next[3:0]$11284 + assign $6\r23__data_o$next[3:0]$11340 $1\r23__data_o$next[3:0]$11335 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11283 + update \r23__data_o$next $0\r23__data_o$next[3:0]$11334 end - attribute \src "libresoc.v:177324.3-177353.6" - process $proc$libresoc.v:177324$11290 + attribute \src "libresoc.v:179420.3-179449.6" + process $proc$libresoc.v:179420$11341 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11291 $1\wr_detect$13[0:0]$11292 - attribute \src "libresoc.v:177325.5-177325.29" + assign $0\wr_detect$13[0:0]$11342 $1\wr_detect$13[0:0]$11343 + attribute \src "libresoc.v:179421.5-179421.29" switch \initial - attribute \src "libresoc.v:177325.9-177325.17" + attribute \src "libresoc.v:179421.9-179421.17" case 1'1 case end @@ -366965,217 +369836,217 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11292 $4\wr_detect$13[0:0]$11295 + assign $1\wr_detect$13[0:0]$11343 $4\wr_detect$13[0:0]$11346 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11293 1'1 + assign $2\wr_detect$13[0:0]$11344 1'1 case - assign $2\wr_detect$13[0:0]$11293 1'0 + assign $2\wr_detect$13[0:0]$11344 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11294 1'1 + assign $3\wr_detect$13[0:0]$11345 1'1 case - assign $3\wr_detect$13[0:0]$11294 $2\wr_detect$13[0:0]$11293 + assign $3\wr_detect$13[0:0]$11345 $2\wr_detect$13[0:0]$11344 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11295 1'1 + assign $4\wr_detect$13[0:0]$11346 1'1 case - assign $4\wr_detect$13[0:0]$11295 $3\wr_detect$13[0:0]$11294 + assign $4\wr_detect$13[0:0]$11346 $3\wr_detect$13[0:0]$11345 end case - assign $1\wr_detect$13[0:0]$11292 1'0 + assign $1\wr_detect$13[0:0]$11343 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11291 + update \wr_detect$13 $0\wr_detect$13[0:0]$11342 end - connect \$9 $not$libresoc.v:176960$11214_Y - connect \$12 $not$libresoc.v:176961$11215_Y - connect \$1 $not$libresoc.v:176962$11216_Y - connect \$3 $not$libresoc.v:176963$11217_Y - connect \$6 $not$libresoc.v:176964$11218_Y + connect \$9 $not$libresoc.v:179056$11265_Y + connect \$12 $not$libresoc.v:179057$11266_Y + connect \$1 $not$libresoc.v:179058$11267_Y + connect \$3 $not$libresoc.v:179059$11268_Y + connect \$6 $not$libresoc.v:179060$11269_Y end -attribute \src "libresoc.v:177358.1-177829.10" +attribute \src "libresoc.v:179454.1-179925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:177359.7-177359.20" + attribute \src "libresoc.v:179455.7-179455.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177759.3-177798.6" - wire width 4 $0\r24__data_o$next[3:0]$11372 - attribute \src "libresoc.v:177442.3-177443.39" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $0\r24__data_o$next[3:0]$11423 + attribute \src "libresoc.v:179538.3-179539.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:177689.3-177728.6" - wire width 4 $0\r4__data_o$next[3:0]$11358 - attribute \src "libresoc.v:177444.3-177445.37" + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $0\r4__data_o$next[3:0]$11409 + attribute \src "libresoc.v:179540.3-179541.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:177522.3-177548.6" - wire width 4 $0\reg$next[3:0]$11324 - attribute \src "libresoc.v:177440.3-177441.25" + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $0\reg$next[3:0]$11375 + attribute \src "libresoc.v:179536.3-179537.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:177452.3-177491.6" - wire width 4 $0\src14__data_o$next[3:0]$11315 - attribute \src "libresoc.v:177450.3-177451.43" + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $0\src14__data_o$next[3:0]$11366 + attribute \src "libresoc.v:179546.3-179547.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:177549.3-177588.6" - wire width 4 $0\src24__data_o$next[3:0]$11330 - attribute \src "libresoc.v:177448.3-177449.43" + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $0\src24__data_o$next[3:0]$11381 + attribute \src "libresoc.v:179544.3-179545.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:177619.3-177658.6" - wire width 4 $0\src34__data_o$next[3:0]$11344 - attribute \src "libresoc.v:177446.3-177447.43" + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $0\src34__data_o$next[3:0]$11395 + attribute \src "libresoc.v:179542.3-179543.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:177729.3-177758.6" - wire $0\wr_detect$10[0:0]$11366 - attribute \src "libresoc.v:177799.3-177828.6" - wire $0\wr_detect$13[0:0]$11380 - attribute \src "libresoc.v:177589.3-177618.6" - wire $0\wr_detect$4[0:0]$11338 - attribute \src "libresoc.v:177659.3-177688.6" - wire $0\wr_detect$7[0:0]$11352 - attribute \src "libresoc.v:177492.3-177521.6" + attribute \src "libresoc.v:179825.3-179854.6" + wire $0\wr_detect$10[0:0]$11417 + attribute \src "libresoc.v:179895.3-179924.6" + wire $0\wr_detect$13[0:0]$11431 + attribute \src "libresoc.v:179685.3-179714.6" + wire $0\wr_detect$4[0:0]$11389 + attribute \src "libresoc.v:179755.3-179784.6" + wire $0\wr_detect$7[0:0]$11403 + attribute \src "libresoc.v:179588.3-179617.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177759.3-177798.6" - wire width 4 $1\r24__data_o$next[3:0]$11373 - attribute \src "libresoc.v:177384.13-177384.31" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $1\r24__data_o$next[3:0]$11424 + attribute \src "libresoc.v:179480.13-179480.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:177689.3-177728.6" - wire width 4 $1\r4__data_o$next[3:0]$11359 - attribute \src "libresoc.v:177391.13-177391.30" + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $1\r4__data_o$next[3:0]$11410 + attribute \src "libresoc.v:179487.13-179487.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:177522.3-177548.6" - wire width 4 $1\reg$next[3:0]$11325 - attribute \src "libresoc.v:177397.13-177397.25" + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $1\reg$next[3:0]$11376 + attribute \src "libresoc.v:179493.13-179493.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:177452.3-177491.6" - wire width 4 $1\src14__data_o$next[3:0]$11316 - attribute \src "libresoc.v:177402.13-177402.33" + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $1\src14__data_o$next[3:0]$11367 + attribute \src "libresoc.v:179498.13-179498.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:177549.3-177588.6" - wire width 4 $1\src24__data_o$next[3:0]$11331 - attribute \src "libresoc.v:177409.13-177409.33" + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $1\src24__data_o$next[3:0]$11382 + attribute \src "libresoc.v:179505.13-179505.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:177619.3-177658.6" - wire width 4 $1\src34__data_o$next[3:0]$11345 - attribute \src "libresoc.v:177416.13-177416.33" + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $1\src34__data_o$next[3:0]$11396 + attribute \src "libresoc.v:179512.13-179512.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:177729.3-177758.6" - wire $1\wr_detect$10[0:0]$11367 - attribute \src "libresoc.v:177799.3-177828.6" - wire $1\wr_detect$13[0:0]$11381 - attribute \src "libresoc.v:177589.3-177618.6" - wire $1\wr_detect$4[0:0]$11339 - attribute \src "libresoc.v:177659.3-177688.6" - wire $1\wr_detect$7[0:0]$11353 - attribute \src "libresoc.v:177492.3-177521.6" + attribute \src "libresoc.v:179825.3-179854.6" + wire $1\wr_detect$10[0:0]$11418 + attribute \src "libresoc.v:179895.3-179924.6" + wire $1\wr_detect$13[0:0]$11432 + attribute \src "libresoc.v:179685.3-179714.6" + wire $1\wr_detect$4[0:0]$11390 + attribute \src "libresoc.v:179755.3-179784.6" + wire $1\wr_detect$7[0:0]$11404 + attribute \src "libresoc.v:179588.3-179617.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177759.3-177798.6" - wire width 4 $2\r24__data_o$next[3:0]$11374 - attribute \src "libresoc.v:177689.3-177728.6" - wire width 4 $2\r4__data_o$next[3:0]$11360 - attribute \src "libresoc.v:177522.3-177548.6" - wire width 4 $2\reg$next[3:0]$11326 - attribute \src "libresoc.v:177452.3-177491.6" - wire width 4 $2\src14__data_o$next[3:0]$11317 - attribute \src "libresoc.v:177549.3-177588.6" - wire width 4 $2\src24__data_o$next[3:0]$11332 - attribute \src "libresoc.v:177619.3-177658.6" - wire width 4 $2\src34__data_o$next[3:0]$11346 - attribute \src "libresoc.v:177729.3-177758.6" - wire $2\wr_detect$10[0:0]$11368 - attribute \src "libresoc.v:177799.3-177828.6" - wire $2\wr_detect$13[0:0]$11382 - attribute \src "libresoc.v:177589.3-177618.6" - wire $2\wr_detect$4[0:0]$11340 - attribute \src "libresoc.v:177659.3-177688.6" - wire $2\wr_detect$7[0:0]$11354 - attribute \src "libresoc.v:177492.3-177521.6" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $2\r24__data_o$next[3:0]$11425 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $2\r4__data_o$next[3:0]$11411 + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $2\reg$next[3:0]$11377 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $2\src14__data_o$next[3:0]$11368 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $2\src24__data_o$next[3:0]$11383 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $2\src34__data_o$next[3:0]$11397 + attribute \src "libresoc.v:179825.3-179854.6" + wire $2\wr_detect$10[0:0]$11419 + attribute \src "libresoc.v:179895.3-179924.6" + wire $2\wr_detect$13[0:0]$11433 + attribute \src "libresoc.v:179685.3-179714.6" + wire $2\wr_detect$4[0:0]$11391 + attribute \src "libresoc.v:179755.3-179784.6" + wire $2\wr_detect$7[0:0]$11405 + attribute \src "libresoc.v:179588.3-179617.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177759.3-177798.6" - wire width 4 $3\r24__data_o$next[3:0]$11375 - attribute \src "libresoc.v:177689.3-177728.6" - wire width 4 $3\r4__data_o$next[3:0]$11361 - attribute \src "libresoc.v:177522.3-177548.6" - wire width 4 $3\reg$next[3:0]$11327 - attribute \src "libresoc.v:177452.3-177491.6" - wire width 4 $3\src14__data_o$next[3:0]$11318 - attribute \src "libresoc.v:177549.3-177588.6" - wire width 4 $3\src24__data_o$next[3:0]$11333 - attribute \src "libresoc.v:177619.3-177658.6" - wire width 4 $3\src34__data_o$next[3:0]$11347 - attribute \src "libresoc.v:177729.3-177758.6" - wire $3\wr_detect$10[0:0]$11369 - attribute \src "libresoc.v:177799.3-177828.6" - wire $3\wr_detect$13[0:0]$11383 - attribute \src "libresoc.v:177589.3-177618.6" - wire $3\wr_detect$4[0:0]$11341 - attribute \src "libresoc.v:177659.3-177688.6" - wire $3\wr_detect$7[0:0]$11355 - attribute \src "libresoc.v:177492.3-177521.6" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $3\r24__data_o$next[3:0]$11426 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $3\r4__data_o$next[3:0]$11412 + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $3\reg$next[3:0]$11378 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $3\src14__data_o$next[3:0]$11369 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $3\src24__data_o$next[3:0]$11384 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $3\src34__data_o$next[3:0]$11398 + attribute \src "libresoc.v:179825.3-179854.6" + wire $3\wr_detect$10[0:0]$11420 + attribute \src "libresoc.v:179895.3-179924.6" + wire $3\wr_detect$13[0:0]$11434 + attribute \src "libresoc.v:179685.3-179714.6" + wire $3\wr_detect$4[0:0]$11392 + attribute \src "libresoc.v:179755.3-179784.6" + wire $3\wr_detect$7[0:0]$11406 + attribute \src "libresoc.v:179588.3-179617.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177759.3-177798.6" - wire width 4 $4\r24__data_o$next[3:0]$11376 - attribute \src "libresoc.v:177689.3-177728.6" - wire width 4 $4\r4__data_o$next[3:0]$11362 - attribute \src "libresoc.v:177522.3-177548.6" - wire width 4 $4\reg$next[3:0]$11328 - attribute \src "libresoc.v:177452.3-177491.6" - wire width 4 $4\src14__data_o$next[3:0]$11319 - attribute \src "libresoc.v:177549.3-177588.6" - wire width 4 $4\src24__data_o$next[3:0]$11334 - attribute \src "libresoc.v:177619.3-177658.6" - wire width 4 $4\src34__data_o$next[3:0]$11348 - attribute \src "libresoc.v:177729.3-177758.6" - wire $4\wr_detect$10[0:0]$11370 - attribute \src "libresoc.v:177799.3-177828.6" - wire $4\wr_detect$13[0:0]$11384 - attribute \src "libresoc.v:177589.3-177618.6" - wire $4\wr_detect$4[0:0]$11342 - attribute \src "libresoc.v:177659.3-177688.6" - wire $4\wr_detect$7[0:0]$11356 - attribute \src "libresoc.v:177492.3-177521.6" + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $4\r24__data_o$next[3:0]$11427 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $4\r4__data_o$next[3:0]$11413 + attribute \src "libresoc.v:179618.3-179644.6" + wire width 4 $4\reg$next[3:0]$11379 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $4\src14__data_o$next[3:0]$11370 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $4\src24__data_o$next[3:0]$11385 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $4\src34__data_o$next[3:0]$11399 + attribute \src "libresoc.v:179825.3-179854.6" + wire $4\wr_detect$10[0:0]$11421 + attribute \src "libresoc.v:179895.3-179924.6" + wire $4\wr_detect$13[0:0]$11435 + attribute \src "libresoc.v:179685.3-179714.6" + wire $4\wr_detect$4[0:0]$11393 + attribute \src "libresoc.v:179755.3-179784.6" + wire $4\wr_detect$7[0:0]$11407 + attribute \src "libresoc.v:179588.3-179617.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177759.3-177798.6" - wire width 4 $5\r24__data_o$next[3:0]$11377 - attribute \src "libresoc.v:177689.3-177728.6" - wire width 4 $5\r4__data_o$next[3:0]$11363 - attribute \src "libresoc.v:177452.3-177491.6" - wire width 4 $5\src14__data_o$next[3:0]$11320 - attribute \src "libresoc.v:177549.3-177588.6" - wire width 4 $5\src24__data_o$next[3:0]$11335 - attribute \src "libresoc.v:177619.3-177658.6" - wire width 4 $5\src34__data_o$next[3:0]$11349 - attribute \src "libresoc.v:177759.3-177798.6" - wire width 4 $6\r24__data_o$next[3:0]$11378 - attribute \src "libresoc.v:177689.3-177728.6" - wire width 4 $6\r4__data_o$next[3:0]$11364 - attribute \src "libresoc.v:177452.3-177491.6" - wire width 4 $6\src14__data_o$next[3:0]$11321 - attribute \src "libresoc.v:177549.3-177588.6" - wire width 4 $6\src24__data_o$next[3:0]$11336 - attribute \src "libresoc.v:177619.3-177658.6" - wire width 4 $6\src34__data_o$next[3:0]$11350 - attribute \src "libresoc.v:177435.17-177435.104" - wire $not$libresoc.v:177435$11303_Y - attribute \src "libresoc.v:177436.18-177436.105" - wire $not$libresoc.v:177436$11304_Y - attribute \src "libresoc.v:177437.17-177437.100" - wire $not$libresoc.v:177437$11305_Y - attribute \src "libresoc.v:177438.17-177438.103" - wire $not$libresoc.v:177438$11306_Y - attribute \src "libresoc.v:177439.17-177439.103" - wire $not$libresoc.v:177439$11307_Y + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $5\r24__data_o$next[3:0]$11428 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $5\r4__data_o$next[3:0]$11414 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $5\src14__data_o$next[3:0]$11371 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $5\src24__data_o$next[3:0]$11386 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $5\src34__data_o$next[3:0]$11400 + attribute \src "libresoc.v:179855.3-179894.6" + wire width 4 $6\r24__data_o$next[3:0]$11429 + attribute \src "libresoc.v:179785.3-179824.6" + wire width 4 $6\r4__data_o$next[3:0]$11415 + attribute \src "libresoc.v:179548.3-179587.6" + wire width 4 $6\src14__data_o$next[3:0]$11372 + attribute \src "libresoc.v:179645.3-179684.6" + wire width 4 $6\src24__data_o$next[3:0]$11387 + attribute \src "libresoc.v:179715.3-179754.6" + wire width 4 $6\src34__data_o$next[3:0]$11401 + attribute \src "libresoc.v:179531.17-179531.104" + wire $not$libresoc.v:179531$11354_Y + attribute \src "libresoc.v:179532.18-179532.105" + wire $not$libresoc.v:179532$11355_Y + attribute \src "libresoc.v:179533.17-179533.100" + wire $not$libresoc.v:179533$11356_Y + attribute \src "libresoc.v:179534.17-179534.103" + wire $not$libresoc.v:179534$11357_Y + attribute \src "libresoc.v:179535.17-179535.103" + wire $not$libresoc.v:179535$11358_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -367186,9 +370057,9 @@ module \reg_4 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest14__data_i @@ -367198,7 +370069,7 @@ module \reg_4 wire width 4 input 11 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest24__wen - attribute \src "libresoc.v:177359.7-177359.15" + attribute \src "libresoc.v:179455.7-179455.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r24__data_o @@ -367249,152 +370120,152 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177435$11303 + cell $not $not$libresoc.v:179531$11354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:177435$11303_Y + connect \Y $not$libresoc.v:179531$11354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177436$11304 + cell $not $not$libresoc.v:179532$11355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:177436$11304_Y + connect \Y $not$libresoc.v:179532$11355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177437$11305 + cell $not $not$libresoc.v:179533$11356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177437$11305_Y + connect \Y $not$libresoc.v:179533$11356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177438$11306 + cell $not $not$libresoc.v:179534$11357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177438$11306_Y + connect \Y $not$libresoc.v:179534$11357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177439$11307 + cell $not $not$libresoc.v:179535$11358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177439$11307_Y + connect \Y $not$libresoc.v:179535$11358_Y end - attribute \src "libresoc.v:177359.7-177359.20" - process $proc$libresoc.v:177359$11385 + attribute \src "libresoc.v:179455.7-179455.20" + process $proc$libresoc.v:179455$11436 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177384.13-177384.31" - process $proc$libresoc.v:177384$11386 + attribute \src "libresoc.v:179480.13-179480.31" + process $proc$libresoc.v:179480$11437 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:177391.13-177391.30" - process $proc$libresoc.v:177391$11387 + attribute \src "libresoc.v:179487.13-179487.30" + process $proc$libresoc.v:179487$11438 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:177397.13-177397.25" - process $proc$libresoc.v:177397$11388 + attribute \src "libresoc.v:179493.13-179493.25" + process $proc$libresoc.v:179493$11439 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:177402.13-177402.33" - process $proc$libresoc.v:177402$11389 + attribute \src "libresoc.v:179498.13-179498.33" + process $proc$libresoc.v:179498$11440 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:177409.13-177409.33" - process $proc$libresoc.v:177409$11390 + attribute \src "libresoc.v:179505.13-179505.33" + process $proc$libresoc.v:179505$11441 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:177416.13-177416.33" - process $proc$libresoc.v:177416$11391 + attribute \src "libresoc.v:179512.13-179512.33" + process $proc$libresoc.v:179512$11442 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:177440.3-177441.25" - process $proc$libresoc.v:177440$11308 + attribute \src "libresoc.v:179536.3-179537.25" + process $proc$libresoc.v:179536$11359 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:177442.3-177443.39" - process $proc$libresoc.v:177442$11309 + attribute \src "libresoc.v:179538.3-179539.39" + process $proc$libresoc.v:179538$11360 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:177444.3-177445.37" - process $proc$libresoc.v:177444$11310 + attribute \src "libresoc.v:179540.3-179541.37" + process $proc$libresoc.v:179540$11361 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:177446.3-177447.43" - process $proc$libresoc.v:177446$11311 + attribute \src "libresoc.v:179542.3-179543.43" + process $proc$libresoc.v:179542$11362 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:177448.3-177449.43" - process $proc$libresoc.v:177448$11312 + attribute \src "libresoc.v:179544.3-179545.43" + process $proc$libresoc.v:179544$11363 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:177450.3-177451.43" - process $proc$libresoc.v:177450$11313 + attribute \src "libresoc.v:179546.3-179547.43" + process $proc$libresoc.v:179546$11364 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:177452.3-177491.6" - process $proc$libresoc.v:177452$11314 + attribute \src "libresoc.v:179548.3-179587.6" + process $proc$libresoc.v:179548$11365 assign { } { } assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$11315 $6\src14__data_o$next[3:0]$11321 - attribute \src "libresoc.v:177453.5-177453.29" + assign $0\src14__data_o$next[3:0]$11366 $6\src14__data_o$next[3:0]$11372 + attribute \src "libresoc.v:179549.5-179549.29" switch \initial - attribute \src "libresoc.v:177453.9-177453.17" + attribute \src "libresoc.v:179549.9-179549.17" case 1'1 case end @@ -367406,66 +370277,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src14__data_o$next[3:0]$11316 $5\src14__data_o$next[3:0]$11320 + assign $1\src14__data_o$next[3:0]$11367 $5\src14__data_o$next[3:0]$11371 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src14__data_o$next[3:0]$11317 \dest14__data_i + assign $2\src14__data_o$next[3:0]$11368 \dest14__data_i case - assign $2\src14__data_o$next[3:0]$11317 4'0000 + assign $2\src14__data_o$next[3:0]$11368 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src14__data_o$next[3:0]$11318 \dest24__data_i + assign $3\src14__data_o$next[3:0]$11369 \dest24__data_i case - assign $3\src14__data_o$next[3:0]$11318 $2\src14__data_o$next[3:0]$11317 + assign $3\src14__data_o$next[3:0]$11369 $2\src14__data_o$next[3:0]$11368 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src14__data_o$next[3:0]$11319 \w4__data_i + assign $4\src14__data_o$next[3:0]$11370 \w4__data_i case - assign $4\src14__data_o$next[3:0]$11319 $3\src14__data_o$next[3:0]$11318 + assign $4\src14__data_o$next[3:0]$11370 $3\src14__data_o$next[3:0]$11369 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$11320 \reg + assign $5\src14__data_o$next[3:0]$11371 \reg case - assign $5\src14__data_o$next[3:0]$11320 $4\src14__data_o$next[3:0]$11319 + assign $5\src14__data_o$next[3:0]$11371 $4\src14__data_o$next[3:0]$11370 end case - assign $1\src14__data_o$next[3:0]$11316 4'0000 + assign $1\src14__data_o$next[3:0]$11367 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$11321 4'0000 + assign $6\src14__data_o$next[3:0]$11372 4'0000 case - assign $6\src14__data_o$next[3:0]$11321 $1\src14__data_o$next[3:0]$11316 + assign $6\src14__data_o$next[3:0]$11372 $1\src14__data_o$next[3:0]$11367 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11315 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11366 end - attribute \src "libresoc.v:177492.3-177521.6" - process $proc$libresoc.v:177492$11322 + attribute \src "libresoc.v:179588.3-179617.6" + process $proc$libresoc.v:179588$11373 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177493.5-177493.29" + attribute \src "libresoc.v:179589.5-179589.29" switch \initial - attribute \src "libresoc.v:177493.9-177493.17" + attribute \src "libresoc.v:179589.9-179589.17" case 1'1 case end @@ -367511,17 +370382,17 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177522.3-177548.6" - process $proc$libresoc.v:177522$11323 + attribute \src "libresoc.v:179618.3-179644.6" + process $proc$libresoc.v:179618$11374 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11324 $4\reg$next[3:0]$11328 - attribute \src "libresoc.v:177523.5-177523.29" + assign $0\reg$next[3:0]$11375 $4\reg$next[3:0]$11379 + attribute \src "libresoc.v:179619.5-179619.29" switch \initial - attribute \src "libresoc.v:177523.9-177523.17" + attribute \src "libresoc.v:179619.9-179619.17" case 1'1 case end @@ -367530,49 +370401,49 @@ module \reg_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11325 \dest14__data_i + assign $1\reg$next[3:0]$11376 \dest14__data_i case - assign $1\reg$next[3:0]$11325 \reg + assign $1\reg$next[3:0]$11376 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11326 \dest24__data_i + assign $2\reg$next[3:0]$11377 \dest24__data_i case - assign $2\reg$next[3:0]$11326 $1\reg$next[3:0]$11325 + assign $2\reg$next[3:0]$11377 $1\reg$next[3:0]$11376 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11327 \w4__data_i + assign $3\reg$next[3:0]$11378 \w4__data_i case - assign $3\reg$next[3:0]$11327 $2\reg$next[3:0]$11326 + assign $3\reg$next[3:0]$11378 $2\reg$next[3:0]$11377 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11328 4'0000 + assign $4\reg$next[3:0]$11379 4'0000 case - assign $4\reg$next[3:0]$11328 $3\reg$next[3:0]$11327 + assign $4\reg$next[3:0]$11379 $3\reg$next[3:0]$11378 end sync always - update \reg$next $0\reg$next[3:0]$11324 + update \reg$next $0\reg$next[3:0]$11375 end - attribute \src "libresoc.v:177549.3-177588.6" - process $proc$libresoc.v:177549$11329 + attribute \src "libresoc.v:179645.3-179684.6" + process $proc$libresoc.v:179645$11380 assign { } { } assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11330 $6\src24__data_o$next[3:0]$11336 - attribute \src "libresoc.v:177550.5-177550.29" + assign $0\src24__data_o$next[3:0]$11381 $6\src24__data_o$next[3:0]$11387 + attribute \src "libresoc.v:179646.5-179646.29" switch \initial - attribute \src "libresoc.v:177550.9-177550.17" + attribute \src "libresoc.v:179646.9-179646.17" case 1'1 case end @@ -367584,66 +370455,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$11331 $5\src24__data_o$next[3:0]$11335 + assign $1\src24__data_o$next[3:0]$11382 $5\src24__data_o$next[3:0]$11386 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$11332 \dest14__data_i + assign $2\src24__data_o$next[3:0]$11383 \dest14__data_i case - assign $2\src24__data_o$next[3:0]$11332 4'0000 + assign $2\src24__data_o$next[3:0]$11383 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$11333 \dest24__data_i + assign $3\src24__data_o$next[3:0]$11384 \dest24__data_i case - assign $3\src24__data_o$next[3:0]$11333 $2\src24__data_o$next[3:0]$11332 + assign $3\src24__data_o$next[3:0]$11384 $2\src24__data_o$next[3:0]$11383 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$11334 \w4__data_i + assign $4\src24__data_o$next[3:0]$11385 \w4__data_i case - assign $4\src24__data_o$next[3:0]$11334 $3\src24__data_o$next[3:0]$11333 + assign $4\src24__data_o$next[3:0]$11385 $3\src24__data_o$next[3:0]$11384 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$11335 \reg + assign $5\src24__data_o$next[3:0]$11386 \reg case - assign $5\src24__data_o$next[3:0]$11335 $4\src24__data_o$next[3:0]$11334 + assign $5\src24__data_o$next[3:0]$11386 $4\src24__data_o$next[3:0]$11385 end case - assign $1\src24__data_o$next[3:0]$11331 4'0000 + assign $1\src24__data_o$next[3:0]$11382 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$11336 4'0000 + assign $6\src24__data_o$next[3:0]$11387 4'0000 case - assign $6\src24__data_o$next[3:0]$11336 $1\src24__data_o$next[3:0]$11331 + assign $6\src24__data_o$next[3:0]$11387 $1\src24__data_o$next[3:0]$11382 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11330 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11381 end - attribute \src "libresoc.v:177589.3-177618.6" - process $proc$libresoc.v:177589$11337 + attribute \src "libresoc.v:179685.3-179714.6" + process $proc$libresoc.v:179685$11388 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11338 $1\wr_detect$4[0:0]$11339 - attribute \src "libresoc.v:177590.5-177590.29" + assign $0\wr_detect$4[0:0]$11389 $1\wr_detect$4[0:0]$11390 + attribute \src "libresoc.v:179686.5-179686.29" switch \initial - attribute \src "libresoc.v:177590.9-177590.17" + attribute \src "libresoc.v:179686.9-179686.17" case 1'1 case end @@ -367655,49 +370526,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11339 $4\wr_detect$4[0:0]$11342 + assign $1\wr_detect$4[0:0]$11390 $4\wr_detect$4[0:0]$11393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11340 1'1 + assign $2\wr_detect$4[0:0]$11391 1'1 case - assign $2\wr_detect$4[0:0]$11340 1'0 + assign $2\wr_detect$4[0:0]$11391 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11341 1'1 + assign $3\wr_detect$4[0:0]$11392 1'1 case - assign $3\wr_detect$4[0:0]$11341 $2\wr_detect$4[0:0]$11340 + assign $3\wr_detect$4[0:0]$11392 $2\wr_detect$4[0:0]$11391 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11342 1'1 + assign $4\wr_detect$4[0:0]$11393 1'1 case - assign $4\wr_detect$4[0:0]$11342 $3\wr_detect$4[0:0]$11341 + assign $4\wr_detect$4[0:0]$11393 $3\wr_detect$4[0:0]$11392 end case - assign $1\wr_detect$4[0:0]$11339 1'0 + assign $1\wr_detect$4[0:0]$11390 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11338 + update \wr_detect$4 $0\wr_detect$4[0:0]$11389 end - attribute \src "libresoc.v:177619.3-177658.6" - process $proc$libresoc.v:177619$11343 + attribute \src "libresoc.v:179715.3-179754.6" + process $proc$libresoc.v:179715$11394 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11344 $6\src34__data_o$next[3:0]$11350 - attribute \src "libresoc.v:177620.5-177620.29" + assign $0\src34__data_o$next[3:0]$11395 $6\src34__data_o$next[3:0]$11401 + attribute \src "libresoc.v:179716.5-179716.29" switch \initial - attribute \src "libresoc.v:177620.9-177620.17" + attribute \src "libresoc.v:179716.9-179716.17" case 1'1 case end @@ -367709,66 +370580,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$11345 $5\src34__data_o$next[3:0]$11349 + assign $1\src34__data_o$next[3:0]$11396 $5\src34__data_o$next[3:0]$11400 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$11346 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11397 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$11346 4'0000 + assign $2\src34__data_o$next[3:0]$11397 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$11347 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11398 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$11347 $2\src34__data_o$next[3:0]$11346 + assign $3\src34__data_o$next[3:0]$11398 $2\src34__data_o$next[3:0]$11397 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$11348 \w4__data_i + assign $4\src34__data_o$next[3:0]$11399 \w4__data_i case - assign $4\src34__data_o$next[3:0]$11348 $3\src34__data_o$next[3:0]$11347 + assign $4\src34__data_o$next[3:0]$11399 $3\src34__data_o$next[3:0]$11398 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$11349 \reg + assign $5\src34__data_o$next[3:0]$11400 \reg case - assign $5\src34__data_o$next[3:0]$11349 $4\src34__data_o$next[3:0]$11348 + assign $5\src34__data_o$next[3:0]$11400 $4\src34__data_o$next[3:0]$11399 end case - assign $1\src34__data_o$next[3:0]$11345 4'0000 + assign $1\src34__data_o$next[3:0]$11396 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$11350 4'0000 + assign $6\src34__data_o$next[3:0]$11401 4'0000 case - assign $6\src34__data_o$next[3:0]$11350 $1\src34__data_o$next[3:0]$11345 + assign $6\src34__data_o$next[3:0]$11401 $1\src34__data_o$next[3:0]$11396 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11344 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11395 end - attribute \src "libresoc.v:177659.3-177688.6" - process $proc$libresoc.v:177659$11351 + attribute \src "libresoc.v:179755.3-179784.6" + process $proc$libresoc.v:179755$11402 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11352 $1\wr_detect$7[0:0]$11353 - attribute \src "libresoc.v:177660.5-177660.29" + assign $0\wr_detect$7[0:0]$11403 $1\wr_detect$7[0:0]$11404 + attribute \src "libresoc.v:179756.5-179756.29" switch \initial - attribute \src "libresoc.v:177660.9-177660.17" + attribute \src "libresoc.v:179756.9-179756.17" case 1'1 case end @@ -367780,49 +370651,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11353 $4\wr_detect$7[0:0]$11356 + assign $1\wr_detect$7[0:0]$11404 $4\wr_detect$7[0:0]$11407 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11354 1'1 + assign $2\wr_detect$7[0:0]$11405 1'1 case - assign $2\wr_detect$7[0:0]$11354 1'0 + assign $2\wr_detect$7[0:0]$11405 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11355 1'1 + assign $3\wr_detect$7[0:0]$11406 1'1 case - assign $3\wr_detect$7[0:0]$11355 $2\wr_detect$7[0:0]$11354 + assign $3\wr_detect$7[0:0]$11406 $2\wr_detect$7[0:0]$11405 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11356 1'1 + assign $4\wr_detect$7[0:0]$11407 1'1 case - assign $4\wr_detect$7[0:0]$11356 $3\wr_detect$7[0:0]$11355 + assign $4\wr_detect$7[0:0]$11407 $3\wr_detect$7[0:0]$11406 end case - assign $1\wr_detect$7[0:0]$11353 1'0 + assign $1\wr_detect$7[0:0]$11404 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11352 + update \wr_detect$7 $0\wr_detect$7[0:0]$11403 end - attribute \src "libresoc.v:177689.3-177728.6" - process $proc$libresoc.v:177689$11357 + attribute \src "libresoc.v:179785.3-179824.6" + process $proc$libresoc.v:179785$11408 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11358 $6\r4__data_o$next[3:0]$11364 - attribute \src "libresoc.v:177690.5-177690.29" + assign $0\r4__data_o$next[3:0]$11409 $6\r4__data_o$next[3:0]$11415 + attribute \src "libresoc.v:179786.5-179786.29" switch \initial - attribute \src "libresoc.v:177690.9-177690.17" + attribute \src "libresoc.v:179786.9-179786.17" case 1'1 case end @@ -367834,66 +370705,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$11359 $5\r4__data_o$next[3:0]$11363 + assign $1\r4__data_o$next[3:0]$11410 $5\r4__data_o$next[3:0]$11414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$11360 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11411 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$11360 4'0000 + assign $2\r4__data_o$next[3:0]$11411 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$11361 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11412 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$11361 $2\r4__data_o$next[3:0]$11360 + assign $3\r4__data_o$next[3:0]$11412 $2\r4__data_o$next[3:0]$11411 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$11362 \w4__data_i + assign $4\r4__data_o$next[3:0]$11413 \w4__data_i case - assign $4\r4__data_o$next[3:0]$11362 $3\r4__data_o$next[3:0]$11361 + assign $4\r4__data_o$next[3:0]$11413 $3\r4__data_o$next[3:0]$11412 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$11363 \reg + assign $5\r4__data_o$next[3:0]$11414 \reg case - assign $5\r4__data_o$next[3:0]$11363 $4\r4__data_o$next[3:0]$11362 + assign $5\r4__data_o$next[3:0]$11414 $4\r4__data_o$next[3:0]$11413 end case - assign $1\r4__data_o$next[3:0]$11359 4'0000 + assign $1\r4__data_o$next[3:0]$11410 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$11364 4'0000 + assign $6\r4__data_o$next[3:0]$11415 4'0000 case - assign $6\r4__data_o$next[3:0]$11364 $1\r4__data_o$next[3:0]$11359 + assign $6\r4__data_o$next[3:0]$11415 $1\r4__data_o$next[3:0]$11410 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11358 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11409 end - attribute \src "libresoc.v:177729.3-177758.6" - process $proc$libresoc.v:177729$11365 + attribute \src "libresoc.v:179825.3-179854.6" + process $proc$libresoc.v:179825$11416 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11366 $1\wr_detect$10[0:0]$11367 - attribute \src "libresoc.v:177730.5-177730.29" + assign $0\wr_detect$10[0:0]$11417 $1\wr_detect$10[0:0]$11418 + attribute \src "libresoc.v:179826.5-179826.29" switch \initial - attribute \src "libresoc.v:177730.9-177730.17" + attribute \src "libresoc.v:179826.9-179826.17" case 1'1 case end @@ -367905,49 +370776,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11367 $4\wr_detect$10[0:0]$11370 + assign $1\wr_detect$10[0:0]$11418 $4\wr_detect$10[0:0]$11421 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11368 1'1 + assign $2\wr_detect$10[0:0]$11419 1'1 case - assign $2\wr_detect$10[0:0]$11368 1'0 + assign $2\wr_detect$10[0:0]$11419 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11369 1'1 + assign $3\wr_detect$10[0:0]$11420 1'1 case - assign $3\wr_detect$10[0:0]$11369 $2\wr_detect$10[0:0]$11368 + assign $3\wr_detect$10[0:0]$11420 $2\wr_detect$10[0:0]$11419 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11370 1'1 + assign $4\wr_detect$10[0:0]$11421 1'1 case - assign $4\wr_detect$10[0:0]$11370 $3\wr_detect$10[0:0]$11369 + assign $4\wr_detect$10[0:0]$11421 $3\wr_detect$10[0:0]$11420 end case - assign $1\wr_detect$10[0:0]$11367 1'0 + assign $1\wr_detect$10[0:0]$11418 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11366 + update \wr_detect$10 $0\wr_detect$10[0:0]$11417 end - attribute \src "libresoc.v:177759.3-177798.6" - process $proc$libresoc.v:177759$11371 + attribute \src "libresoc.v:179855.3-179894.6" + process $proc$libresoc.v:179855$11422 assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$11372 $6\r24__data_o$next[3:0]$11378 - attribute \src "libresoc.v:177760.5-177760.29" + assign $0\r24__data_o$next[3:0]$11423 $6\r24__data_o$next[3:0]$11429 + attribute \src "libresoc.v:179856.5-179856.29" switch \initial - attribute \src "libresoc.v:177760.9-177760.17" + attribute \src "libresoc.v:179856.9-179856.17" case 1'1 case end @@ -367959,66 +370830,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r24__data_o$next[3:0]$11373 $5\r24__data_o$next[3:0]$11377 + assign $1\r24__data_o$next[3:0]$11424 $5\r24__data_o$next[3:0]$11428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r24__data_o$next[3:0]$11374 \dest14__data_i + assign $2\r24__data_o$next[3:0]$11425 \dest14__data_i case - assign $2\r24__data_o$next[3:0]$11374 4'0000 + assign $2\r24__data_o$next[3:0]$11425 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r24__data_o$next[3:0]$11375 \dest24__data_i + assign $3\r24__data_o$next[3:0]$11426 \dest24__data_i case - assign $3\r24__data_o$next[3:0]$11375 $2\r24__data_o$next[3:0]$11374 + assign $3\r24__data_o$next[3:0]$11426 $2\r24__data_o$next[3:0]$11425 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r24__data_o$next[3:0]$11376 \w4__data_i + assign $4\r24__data_o$next[3:0]$11427 \w4__data_i case - assign $4\r24__data_o$next[3:0]$11376 $3\r24__data_o$next[3:0]$11375 + assign $4\r24__data_o$next[3:0]$11427 $3\r24__data_o$next[3:0]$11426 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r24__data_o$next[3:0]$11377 \reg + assign $5\r24__data_o$next[3:0]$11428 \reg case - assign $5\r24__data_o$next[3:0]$11377 $4\r24__data_o$next[3:0]$11376 + assign $5\r24__data_o$next[3:0]$11428 $4\r24__data_o$next[3:0]$11427 end case - assign $1\r24__data_o$next[3:0]$11373 4'0000 + assign $1\r24__data_o$next[3:0]$11424 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11378 4'0000 + assign $6\r24__data_o$next[3:0]$11429 4'0000 case - assign $6\r24__data_o$next[3:0]$11378 $1\r24__data_o$next[3:0]$11373 + assign $6\r24__data_o$next[3:0]$11429 $1\r24__data_o$next[3:0]$11424 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11372 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11423 end - attribute \src "libresoc.v:177799.3-177828.6" - process $proc$libresoc.v:177799$11379 + attribute \src "libresoc.v:179895.3-179924.6" + process $proc$libresoc.v:179895$11430 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11380 $1\wr_detect$13[0:0]$11381 - attribute \src "libresoc.v:177800.5-177800.29" + assign $0\wr_detect$13[0:0]$11431 $1\wr_detect$13[0:0]$11432 + attribute \src "libresoc.v:179896.5-179896.29" switch \initial - attribute \src "libresoc.v:177800.9-177800.17" + attribute \src "libresoc.v:179896.9-179896.17" case 1'1 case end @@ -368030,217 +370901,217 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11381 $4\wr_detect$13[0:0]$11384 + assign $1\wr_detect$13[0:0]$11432 $4\wr_detect$13[0:0]$11435 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11382 1'1 + assign $2\wr_detect$13[0:0]$11433 1'1 case - assign $2\wr_detect$13[0:0]$11382 1'0 + assign $2\wr_detect$13[0:0]$11433 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11383 1'1 + assign $3\wr_detect$13[0:0]$11434 1'1 case - assign $3\wr_detect$13[0:0]$11383 $2\wr_detect$13[0:0]$11382 + assign $3\wr_detect$13[0:0]$11434 $2\wr_detect$13[0:0]$11433 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11384 1'1 + assign $4\wr_detect$13[0:0]$11435 1'1 case - assign $4\wr_detect$13[0:0]$11384 $3\wr_detect$13[0:0]$11383 + assign $4\wr_detect$13[0:0]$11435 $3\wr_detect$13[0:0]$11434 end case - assign $1\wr_detect$13[0:0]$11381 1'0 + assign $1\wr_detect$13[0:0]$11432 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11380 + update \wr_detect$13 $0\wr_detect$13[0:0]$11431 end - connect \$9 $not$libresoc.v:177435$11303_Y - connect \$12 $not$libresoc.v:177436$11304_Y - connect \$1 $not$libresoc.v:177437$11305_Y - connect \$3 $not$libresoc.v:177438$11306_Y - connect \$6 $not$libresoc.v:177439$11307_Y + connect \$9 $not$libresoc.v:179531$11354_Y + connect \$12 $not$libresoc.v:179532$11355_Y + connect \$1 $not$libresoc.v:179533$11356_Y + connect \$3 $not$libresoc.v:179534$11357_Y + connect \$6 $not$libresoc.v:179535$11358_Y end -attribute \src "libresoc.v:177833.1-178304.10" +attribute \src "libresoc.v:179929.1-180400.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:177834.7-177834.20" + attribute \src "libresoc.v:179930.7-179930.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178234.3-178273.6" - wire width 4 $0\r25__data_o$next[3:0]$11461 - attribute \src "libresoc.v:177917.3-177918.39" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $0\r25__data_o$next[3:0]$11512 + attribute \src "libresoc.v:180013.3-180014.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:178164.3-178203.6" - wire width 4 $0\r5__data_o$next[3:0]$11447 - attribute \src "libresoc.v:177919.3-177920.37" + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $0\r5__data_o$next[3:0]$11498 + attribute \src "libresoc.v:180015.3-180016.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:177997.3-178023.6" - wire width 4 $0\reg$next[3:0]$11413 - attribute \src "libresoc.v:177915.3-177916.25" + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $0\reg$next[3:0]$11464 + attribute \src "libresoc.v:180011.3-180012.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:177927.3-177966.6" - wire width 4 $0\src15__data_o$next[3:0]$11404 - attribute \src "libresoc.v:177925.3-177926.43" + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $0\src15__data_o$next[3:0]$11455 + attribute \src "libresoc.v:180021.3-180022.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:178024.3-178063.6" - wire width 4 $0\src25__data_o$next[3:0]$11419 - attribute \src "libresoc.v:177923.3-177924.43" + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $0\src25__data_o$next[3:0]$11470 + attribute \src "libresoc.v:180019.3-180020.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:178094.3-178133.6" - wire width 4 $0\src35__data_o$next[3:0]$11433 - attribute \src "libresoc.v:177921.3-177922.43" + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $0\src35__data_o$next[3:0]$11484 + attribute \src "libresoc.v:180017.3-180018.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:178204.3-178233.6" - wire $0\wr_detect$10[0:0]$11455 - attribute \src "libresoc.v:178274.3-178303.6" - wire $0\wr_detect$13[0:0]$11469 - attribute \src "libresoc.v:178064.3-178093.6" - wire $0\wr_detect$4[0:0]$11427 - attribute \src "libresoc.v:178134.3-178163.6" - wire $0\wr_detect$7[0:0]$11441 - attribute \src "libresoc.v:177967.3-177996.6" + attribute \src "libresoc.v:180300.3-180329.6" + wire $0\wr_detect$10[0:0]$11506 + attribute \src "libresoc.v:180370.3-180399.6" + wire $0\wr_detect$13[0:0]$11520 + attribute \src "libresoc.v:180160.3-180189.6" + wire $0\wr_detect$4[0:0]$11478 + attribute \src "libresoc.v:180230.3-180259.6" + wire $0\wr_detect$7[0:0]$11492 + attribute \src "libresoc.v:180063.3-180092.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178234.3-178273.6" - wire width 4 $1\r25__data_o$next[3:0]$11462 - attribute \src "libresoc.v:177859.13-177859.31" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $1\r25__data_o$next[3:0]$11513 + attribute \src "libresoc.v:179955.13-179955.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:178164.3-178203.6" - wire width 4 $1\r5__data_o$next[3:0]$11448 - attribute \src "libresoc.v:177866.13-177866.30" + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $1\r5__data_o$next[3:0]$11499 + attribute \src "libresoc.v:179962.13-179962.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:177997.3-178023.6" - wire width 4 $1\reg$next[3:0]$11414 - attribute \src "libresoc.v:177872.13-177872.25" + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $1\reg$next[3:0]$11465 + attribute \src "libresoc.v:179968.13-179968.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:177927.3-177966.6" - wire width 4 $1\src15__data_o$next[3:0]$11405 - attribute \src "libresoc.v:177877.13-177877.33" + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $1\src15__data_o$next[3:0]$11456 + attribute \src "libresoc.v:179973.13-179973.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:178024.3-178063.6" - wire width 4 $1\src25__data_o$next[3:0]$11420 - attribute \src "libresoc.v:177884.13-177884.33" + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $1\src25__data_o$next[3:0]$11471 + attribute \src "libresoc.v:179980.13-179980.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:178094.3-178133.6" - wire width 4 $1\src35__data_o$next[3:0]$11434 - attribute \src "libresoc.v:177891.13-177891.33" + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $1\src35__data_o$next[3:0]$11485 + attribute \src "libresoc.v:179987.13-179987.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:178204.3-178233.6" - wire $1\wr_detect$10[0:0]$11456 - attribute \src "libresoc.v:178274.3-178303.6" - wire $1\wr_detect$13[0:0]$11470 - attribute \src "libresoc.v:178064.3-178093.6" - wire $1\wr_detect$4[0:0]$11428 - attribute \src "libresoc.v:178134.3-178163.6" - wire $1\wr_detect$7[0:0]$11442 - attribute \src "libresoc.v:177967.3-177996.6" + attribute \src "libresoc.v:180300.3-180329.6" + wire $1\wr_detect$10[0:0]$11507 + attribute \src "libresoc.v:180370.3-180399.6" + wire $1\wr_detect$13[0:0]$11521 + attribute \src "libresoc.v:180160.3-180189.6" + wire $1\wr_detect$4[0:0]$11479 + attribute \src "libresoc.v:180230.3-180259.6" + wire $1\wr_detect$7[0:0]$11493 + attribute \src "libresoc.v:180063.3-180092.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178234.3-178273.6" - wire width 4 $2\r25__data_o$next[3:0]$11463 - attribute \src "libresoc.v:178164.3-178203.6" - wire width 4 $2\r5__data_o$next[3:0]$11449 - attribute \src "libresoc.v:177997.3-178023.6" - wire width 4 $2\reg$next[3:0]$11415 - attribute \src "libresoc.v:177927.3-177966.6" - wire width 4 $2\src15__data_o$next[3:0]$11406 - attribute \src "libresoc.v:178024.3-178063.6" - wire width 4 $2\src25__data_o$next[3:0]$11421 - attribute \src "libresoc.v:178094.3-178133.6" - wire width 4 $2\src35__data_o$next[3:0]$11435 - attribute \src "libresoc.v:178204.3-178233.6" - wire $2\wr_detect$10[0:0]$11457 - attribute \src "libresoc.v:178274.3-178303.6" - wire $2\wr_detect$13[0:0]$11471 - attribute \src "libresoc.v:178064.3-178093.6" - wire $2\wr_detect$4[0:0]$11429 - attribute \src "libresoc.v:178134.3-178163.6" - wire $2\wr_detect$7[0:0]$11443 - attribute \src "libresoc.v:177967.3-177996.6" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $2\r25__data_o$next[3:0]$11514 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $2\r5__data_o$next[3:0]$11500 + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $2\reg$next[3:0]$11466 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $2\src15__data_o$next[3:0]$11457 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $2\src25__data_o$next[3:0]$11472 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $2\src35__data_o$next[3:0]$11486 + attribute \src "libresoc.v:180300.3-180329.6" + wire $2\wr_detect$10[0:0]$11508 + attribute \src "libresoc.v:180370.3-180399.6" + wire $2\wr_detect$13[0:0]$11522 + attribute \src "libresoc.v:180160.3-180189.6" + wire $2\wr_detect$4[0:0]$11480 + attribute \src "libresoc.v:180230.3-180259.6" + wire $2\wr_detect$7[0:0]$11494 + attribute \src "libresoc.v:180063.3-180092.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178234.3-178273.6" - wire width 4 $3\r25__data_o$next[3:0]$11464 - attribute \src "libresoc.v:178164.3-178203.6" - wire width 4 $3\r5__data_o$next[3:0]$11450 - attribute \src "libresoc.v:177997.3-178023.6" - wire width 4 $3\reg$next[3:0]$11416 - attribute \src "libresoc.v:177927.3-177966.6" - wire width 4 $3\src15__data_o$next[3:0]$11407 - attribute \src "libresoc.v:178024.3-178063.6" - wire width 4 $3\src25__data_o$next[3:0]$11422 - attribute \src "libresoc.v:178094.3-178133.6" - wire width 4 $3\src35__data_o$next[3:0]$11436 - attribute \src "libresoc.v:178204.3-178233.6" - wire $3\wr_detect$10[0:0]$11458 - attribute \src "libresoc.v:178274.3-178303.6" - wire $3\wr_detect$13[0:0]$11472 - attribute \src "libresoc.v:178064.3-178093.6" - wire $3\wr_detect$4[0:0]$11430 - attribute \src "libresoc.v:178134.3-178163.6" - wire $3\wr_detect$7[0:0]$11444 - attribute \src "libresoc.v:177967.3-177996.6" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $3\r25__data_o$next[3:0]$11515 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $3\r5__data_o$next[3:0]$11501 + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $3\reg$next[3:0]$11467 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $3\src15__data_o$next[3:0]$11458 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $3\src25__data_o$next[3:0]$11473 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $3\src35__data_o$next[3:0]$11487 + attribute \src "libresoc.v:180300.3-180329.6" + wire $3\wr_detect$10[0:0]$11509 + attribute \src "libresoc.v:180370.3-180399.6" + wire $3\wr_detect$13[0:0]$11523 + attribute \src "libresoc.v:180160.3-180189.6" + wire $3\wr_detect$4[0:0]$11481 + attribute \src "libresoc.v:180230.3-180259.6" + wire $3\wr_detect$7[0:0]$11495 + attribute \src "libresoc.v:180063.3-180092.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178234.3-178273.6" - wire width 4 $4\r25__data_o$next[3:0]$11465 - attribute \src "libresoc.v:178164.3-178203.6" - wire width 4 $4\r5__data_o$next[3:0]$11451 - attribute \src "libresoc.v:177997.3-178023.6" - wire width 4 $4\reg$next[3:0]$11417 - attribute \src "libresoc.v:177927.3-177966.6" - wire width 4 $4\src15__data_o$next[3:0]$11408 - attribute \src "libresoc.v:178024.3-178063.6" - wire width 4 $4\src25__data_o$next[3:0]$11423 - attribute \src "libresoc.v:178094.3-178133.6" - wire width 4 $4\src35__data_o$next[3:0]$11437 - attribute \src "libresoc.v:178204.3-178233.6" - wire $4\wr_detect$10[0:0]$11459 - attribute \src "libresoc.v:178274.3-178303.6" - wire $4\wr_detect$13[0:0]$11473 - attribute \src "libresoc.v:178064.3-178093.6" - wire $4\wr_detect$4[0:0]$11431 - attribute \src "libresoc.v:178134.3-178163.6" - wire $4\wr_detect$7[0:0]$11445 - attribute \src "libresoc.v:177967.3-177996.6" + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $4\r25__data_o$next[3:0]$11516 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $4\r5__data_o$next[3:0]$11502 + attribute \src "libresoc.v:180093.3-180119.6" + wire width 4 $4\reg$next[3:0]$11468 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $4\src15__data_o$next[3:0]$11459 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $4\src25__data_o$next[3:0]$11474 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $4\src35__data_o$next[3:0]$11488 + attribute \src "libresoc.v:180300.3-180329.6" + wire $4\wr_detect$10[0:0]$11510 + attribute \src "libresoc.v:180370.3-180399.6" + wire $4\wr_detect$13[0:0]$11524 + attribute \src "libresoc.v:180160.3-180189.6" + wire $4\wr_detect$4[0:0]$11482 + attribute \src "libresoc.v:180230.3-180259.6" + wire $4\wr_detect$7[0:0]$11496 + attribute \src "libresoc.v:180063.3-180092.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178234.3-178273.6" - wire width 4 $5\r25__data_o$next[3:0]$11466 - attribute \src "libresoc.v:178164.3-178203.6" - wire width 4 $5\r5__data_o$next[3:0]$11452 - attribute \src "libresoc.v:177927.3-177966.6" - wire width 4 $5\src15__data_o$next[3:0]$11409 - attribute \src "libresoc.v:178024.3-178063.6" - wire width 4 $5\src25__data_o$next[3:0]$11424 - attribute \src "libresoc.v:178094.3-178133.6" - wire width 4 $5\src35__data_o$next[3:0]$11438 - attribute \src "libresoc.v:178234.3-178273.6" - wire width 4 $6\r25__data_o$next[3:0]$11467 - attribute \src "libresoc.v:178164.3-178203.6" - wire width 4 $6\r5__data_o$next[3:0]$11453 - attribute \src "libresoc.v:177927.3-177966.6" - wire width 4 $6\src15__data_o$next[3:0]$11410 - attribute \src "libresoc.v:178024.3-178063.6" - wire width 4 $6\src25__data_o$next[3:0]$11425 - attribute \src "libresoc.v:178094.3-178133.6" - wire width 4 $6\src35__data_o$next[3:0]$11439 - attribute \src "libresoc.v:177910.17-177910.104" - wire $not$libresoc.v:177910$11392_Y - attribute \src "libresoc.v:177911.18-177911.105" - wire $not$libresoc.v:177911$11393_Y - attribute \src "libresoc.v:177912.17-177912.100" - wire $not$libresoc.v:177912$11394_Y - attribute \src "libresoc.v:177913.17-177913.103" - wire $not$libresoc.v:177913$11395_Y - attribute \src "libresoc.v:177914.17-177914.103" - wire $not$libresoc.v:177914$11396_Y + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $5\r25__data_o$next[3:0]$11517 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $5\r5__data_o$next[3:0]$11503 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $5\src15__data_o$next[3:0]$11460 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $5\src25__data_o$next[3:0]$11475 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $5\src35__data_o$next[3:0]$11489 + attribute \src "libresoc.v:180330.3-180369.6" + wire width 4 $6\r25__data_o$next[3:0]$11518 + attribute \src "libresoc.v:180260.3-180299.6" + wire width 4 $6\r5__data_o$next[3:0]$11504 + attribute \src "libresoc.v:180023.3-180062.6" + wire width 4 $6\src15__data_o$next[3:0]$11461 + attribute \src "libresoc.v:180120.3-180159.6" + wire width 4 $6\src25__data_o$next[3:0]$11476 + attribute \src "libresoc.v:180190.3-180229.6" + wire width 4 $6\src35__data_o$next[3:0]$11490 + attribute \src "libresoc.v:180006.17-180006.104" + wire $not$libresoc.v:180006$11443_Y + attribute \src "libresoc.v:180007.18-180007.105" + wire $not$libresoc.v:180007$11444_Y + attribute \src "libresoc.v:180008.17-180008.100" + wire $not$libresoc.v:180008$11445_Y + attribute \src "libresoc.v:180009.17-180009.103" + wire $not$libresoc.v:180009$11446_Y + attribute \src "libresoc.v:180010.17-180010.103" + wire $not$libresoc.v:180010$11447_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -368251,9 +371122,9 @@ module \reg_5 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest15__data_i @@ -368263,7 +371134,7 @@ module \reg_5 wire width 4 input 11 \dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest25__wen - attribute \src "libresoc.v:177834.7-177834.15" + attribute \src "libresoc.v:179930.7-179930.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r25__data_o @@ -368314,152 +371185,152 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177910$11392 + cell $not $not$libresoc.v:180006$11443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:177910$11392_Y + connect \Y $not$libresoc.v:180006$11443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177911$11393 + cell $not $not$libresoc.v:180007$11444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:177911$11393_Y + connect \Y $not$libresoc.v:180007$11444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177912$11394 + cell $not $not$libresoc.v:180008$11445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177912$11394_Y + connect \Y $not$libresoc.v:180008$11445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177913$11395 + cell $not $not$libresoc.v:180009$11446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177913$11395_Y + connect \Y $not$libresoc.v:180009$11446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177914$11396 + cell $not $not$libresoc.v:180010$11447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177914$11396_Y + connect \Y $not$libresoc.v:180010$11447_Y end - attribute \src "libresoc.v:177834.7-177834.20" - process $proc$libresoc.v:177834$11474 + attribute \src "libresoc.v:179930.7-179930.20" + process $proc$libresoc.v:179930$11525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177859.13-177859.31" - process $proc$libresoc.v:177859$11475 + attribute \src "libresoc.v:179955.13-179955.31" + process $proc$libresoc.v:179955$11526 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:177866.13-177866.30" - process $proc$libresoc.v:177866$11476 + attribute \src "libresoc.v:179962.13-179962.30" + process $proc$libresoc.v:179962$11527 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:177872.13-177872.25" - process $proc$libresoc.v:177872$11477 + attribute \src "libresoc.v:179968.13-179968.25" + process $proc$libresoc.v:179968$11528 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:177877.13-177877.33" - process $proc$libresoc.v:177877$11478 + attribute \src "libresoc.v:179973.13-179973.33" + process $proc$libresoc.v:179973$11529 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:177884.13-177884.33" - process $proc$libresoc.v:177884$11479 + attribute \src "libresoc.v:179980.13-179980.33" + process $proc$libresoc.v:179980$11530 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:177891.13-177891.33" - process $proc$libresoc.v:177891$11480 + attribute \src "libresoc.v:179987.13-179987.33" + process $proc$libresoc.v:179987$11531 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:177915.3-177916.25" - process $proc$libresoc.v:177915$11397 + attribute \src "libresoc.v:180011.3-180012.25" + process $proc$libresoc.v:180011$11448 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:177917.3-177918.39" - process $proc$libresoc.v:177917$11398 + attribute \src "libresoc.v:180013.3-180014.39" + process $proc$libresoc.v:180013$11449 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:177919.3-177920.37" - process $proc$libresoc.v:177919$11399 + attribute \src "libresoc.v:180015.3-180016.37" + process $proc$libresoc.v:180015$11450 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:177921.3-177922.43" - process $proc$libresoc.v:177921$11400 + attribute \src "libresoc.v:180017.3-180018.43" + process $proc$libresoc.v:180017$11451 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:177923.3-177924.43" - process $proc$libresoc.v:177923$11401 + attribute \src "libresoc.v:180019.3-180020.43" + process $proc$libresoc.v:180019$11452 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:177925.3-177926.43" - process $proc$libresoc.v:177925$11402 + attribute \src "libresoc.v:180021.3-180022.43" + process $proc$libresoc.v:180021$11453 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:177927.3-177966.6" - process $proc$libresoc.v:177927$11403 + attribute \src "libresoc.v:180023.3-180062.6" + process $proc$libresoc.v:180023$11454 assign { } { } assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11404 $6\src15__data_o$next[3:0]$11410 - attribute \src "libresoc.v:177928.5-177928.29" + assign $0\src15__data_o$next[3:0]$11455 $6\src15__data_o$next[3:0]$11461 + attribute \src "libresoc.v:180024.5-180024.29" switch \initial - attribute \src "libresoc.v:177928.9-177928.17" + attribute \src "libresoc.v:180024.9-180024.17" case 1'1 case end @@ -368471,66 +371342,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11405 $5\src15__data_o$next[3:0]$11409 + assign $1\src15__data_o$next[3:0]$11456 $5\src15__data_o$next[3:0]$11460 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11406 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11457 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11406 4'0000 + assign $2\src15__data_o$next[3:0]$11457 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11407 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11458 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11407 $2\src15__data_o$next[3:0]$11406 + assign $3\src15__data_o$next[3:0]$11458 $2\src15__data_o$next[3:0]$11457 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11408 \w5__data_i + assign $4\src15__data_o$next[3:0]$11459 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11408 $3\src15__data_o$next[3:0]$11407 + assign $4\src15__data_o$next[3:0]$11459 $3\src15__data_o$next[3:0]$11458 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11409 \reg + assign $5\src15__data_o$next[3:0]$11460 \reg case - assign $5\src15__data_o$next[3:0]$11409 $4\src15__data_o$next[3:0]$11408 + assign $5\src15__data_o$next[3:0]$11460 $4\src15__data_o$next[3:0]$11459 end case - assign $1\src15__data_o$next[3:0]$11405 4'0000 + assign $1\src15__data_o$next[3:0]$11456 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11410 4'0000 + assign $6\src15__data_o$next[3:0]$11461 4'0000 case - assign $6\src15__data_o$next[3:0]$11410 $1\src15__data_o$next[3:0]$11405 + assign $6\src15__data_o$next[3:0]$11461 $1\src15__data_o$next[3:0]$11456 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11404 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11455 end - attribute \src "libresoc.v:177967.3-177996.6" - process $proc$libresoc.v:177967$11411 + attribute \src "libresoc.v:180063.3-180092.6" + process $proc$libresoc.v:180063$11462 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177968.5-177968.29" + attribute \src "libresoc.v:180064.5-180064.29" switch \initial - attribute \src "libresoc.v:177968.9-177968.17" + attribute \src "libresoc.v:180064.9-180064.17" case 1'1 case end @@ -368576,17 +371447,17 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177997.3-178023.6" - process $proc$libresoc.v:177997$11412 + attribute \src "libresoc.v:180093.3-180119.6" + process $proc$libresoc.v:180093$11463 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11413 $4\reg$next[3:0]$11417 - attribute \src "libresoc.v:177998.5-177998.29" + assign $0\reg$next[3:0]$11464 $4\reg$next[3:0]$11468 + attribute \src "libresoc.v:180094.5-180094.29" switch \initial - attribute \src "libresoc.v:177998.9-177998.17" + attribute \src "libresoc.v:180094.9-180094.17" case 1'1 case end @@ -368595,49 +371466,49 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11414 \dest15__data_i + assign $1\reg$next[3:0]$11465 \dest15__data_i case - assign $1\reg$next[3:0]$11414 \reg + assign $1\reg$next[3:0]$11465 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11415 \dest25__data_i + assign $2\reg$next[3:0]$11466 \dest25__data_i case - assign $2\reg$next[3:0]$11415 $1\reg$next[3:0]$11414 + assign $2\reg$next[3:0]$11466 $1\reg$next[3:0]$11465 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11416 \w5__data_i + assign $3\reg$next[3:0]$11467 \w5__data_i case - assign $3\reg$next[3:0]$11416 $2\reg$next[3:0]$11415 + assign $3\reg$next[3:0]$11467 $2\reg$next[3:0]$11466 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11417 4'0000 + assign $4\reg$next[3:0]$11468 4'0000 case - assign $4\reg$next[3:0]$11417 $3\reg$next[3:0]$11416 + assign $4\reg$next[3:0]$11468 $3\reg$next[3:0]$11467 end sync always - update \reg$next $0\reg$next[3:0]$11413 + update \reg$next $0\reg$next[3:0]$11464 end - attribute \src "libresoc.v:178024.3-178063.6" - process $proc$libresoc.v:178024$11418 + attribute \src "libresoc.v:180120.3-180159.6" + process $proc$libresoc.v:180120$11469 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11419 $6\src25__data_o$next[3:0]$11425 - attribute \src "libresoc.v:178025.5-178025.29" + assign $0\src25__data_o$next[3:0]$11470 $6\src25__data_o$next[3:0]$11476 + attribute \src "libresoc.v:180121.5-180121.29" switch \initial - attribute \src "libresoc.v:178025.9-178025.17" + attribute \src "libresoc.v:180121.9-180121.17" case 1'1 case end @@ -368649,66 +371520,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11420 $5\src25__data_o$next[3:0]$11424 + assign $1\src25__data_o$next[3:0]$11471 $5\src25__data_o$next[3:0]$11475 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11421 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11472 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11421 4'0000 + assign $2\src25__data_o$next[3:0]$11472 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11422 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11473 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11422 $2\src25__data_o$next[3:0]$11421 + assign $3\src25__data_o$next[3:0]$11473 $2\src25__data_o$next[3:0]$11472 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11423 \w5__data_i + assign $4\src25__data_o$next[3:0]$11474 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11423 $3\src25__data_o$next[3:0]$11422 + assign $4\src25__data_o$next[3:0]$11474 $3\src25__data_o$next[3:0]$11473 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11424 \reg + assign $5\src25__data_o$next[3:0]$11475 \reg case - assign $5\src25__data_o$next[3:0]$11424 $4\src25__data_o$next[3:0]$11423 + assign $5\src25__data_o$next[3:0]$11475 $4\src25__data_o$next[3:0]$11474 end case - assign $1\src25__data_o$next[3:0]$11420 4'0000 + assign $1\src25__data_o$next[3:0]$11471 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11425 4'0000 + assign $6\src25__data_o$next[3:0]$11476 4'0000 case - assign $6\src25__data_o$next[3:0]$11425 $1\src25__data_o$next[3:0]$11420 + assign $6\src25__data_o$next[3:0]$11476 $1\src25__data_o$next[3:0]$11471 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11419 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11470 end - attribute \src "libresoc.v:178064.3-178093.6" - process $proc$libresoc.v:178064$11426 + attribute \src "libresoc.v:180160.3-180189.6" + process $proc$libresoc.v:180160$11477 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11427 $1\wr_detect$4[0:0]$11428 - attribute \src "libresoc.v:178065.5-178065.29" + assign $0\wr_detect$4[0:0]$11478 $1\wr_detect$4[0:0]$11479 + attribute \src "libresoc.v:180161.5-180161.29" switch \initial - attribute \src "libresoc.v:178065.9-178065.17" + attribute \src "libresoc.v:180161.9-180161.17" case 1'1 case end @@ -368720,49 +371591,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11428 $4\wr_detect$4[0:0]$11431 + assign $1\wr_detect$4[0:0]$11479 $4\wr_detect$4[0:0]$11482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11429 1'1 + assign $2\wr_detect$4[0:0]$11480 1'1 case - assign $2\wr_detect$4[0:0]$11429 1'0 + assign $2\wr_detect$4[0:0]$11480 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11430 1'1 + assign $3\wr_detect$4[0:0]$11481 1'1 case - assign $3\wr_detect$4[0:0]$11430 $2\wr_detect$4[0:0]$11429 + assign $3\wr_detect$4[0:0]$11481 $2\wr_detect$4[0:0]$11480 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11431 1'1 + assign $4\wr_detect$4[0:0]$11482 1'1 case - assign $4\wr_detect$4[0:0]$11431 $3\wr_detect$4[0:0]$11430 + assign $4\wr_detect$4[0:0]$11482 $3\wr_detect$4[0:0]$11481 end case - assign $1\wr_detect$4[0:0]$11428 1'0 + assign $1\wr_detect$4[0:0]$11479 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11427 + update \wr_detect$4 $0\wr_detect$4[0:0]$11478 end - attribute \src "libresoc.v:178094.3-178133.6" - process $proc$libresoc.v:178094$11432 + attribute \src "libresoc.v:180190.3-180229.6" + process $proc$libresoc.v:180190$11483 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11433 $6\src35__data_o$next[3:0]$11439 - attribute \src "libresoc.v:178095.5-178095.29" + assign $0\src35__data_o$next[3:0]$11484 $6\src35__data_o$next[3:0]$11490 + attribute \src "libresoc.v:180191.5-180191.29" switch \initial - attribute \src "libresoc.v:178095.9-178095.17" + attribute \src "libresoc.v:180191.9-180191.17" case 1'1 case end @@ -368774,66 +371645,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11434 $5\src35__data_o$next[3:0]$11438 + assign $1\src35__data_o$next[3:0]$11485 $5\src35__data_o$next[3:0]$11489 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11435 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11486 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11435 4'0000 + assign $2\src35__data_o$next[3:0]$11486 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11436 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11487 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11436 $2\src35__data_o$next[3:0]$11435 + assign $3\src35__data_o$next[3:0]$11487 $2\src35__data_o$next[3:0]$11486 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11437 \w5__data_i + assign $4\src35__data_o$next[3:0]$11488 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11437 $3\src35__data_o$next[3:0]$11436 + assign $4\src35__data_o$next[3:0]$11488 $3\src35__data_o$next[3:0]$11487 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11438 \reg + assign $5\src35__data_o$next[3:0]$11489 \reg case - assign $5\src35__data_o$next[3:0]$11438 $4\src35__data_o$next[3:0]$11437 + assign $5\src35__data_o$next[3:0]$11489 $4\src35__data_o$next[3:0]$11488 end case - assign $1\src35__data_o$next[3:0]$11434 4'0000 + assign $1\src35__data_o$next[3:0]$11485 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11439 4'0000 + assign $6\src35__data_o$next[3:0]$11490 4'0000 case - assign $6\src35__data_o$next[3:0]$11439 $1\src35__data_o$next[3:0]$11434 + assign $6\src35__data_o$next[3:0]$11490 $1\src35__data_o$next[3:0]$11485 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11433 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11484 end - attribute \src "libresoc.v:178134.3-178163.6" - process $proc$libresoc.v:178134$11440 + attribute \src "libresoc.v:180230.3-180259.6" + process $proc$libresoc.v:180230$11491 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11441 $1\wr_detect$7[0:0]$11442 - attribute \src "libresoc.v:178135.5-178135.29" + assign $0\wr_detect$7[0:0]$11492 $1\wr_detect$7[0:0]$11493 + attribute \src "libresoc.v:180231.5-180231.29" switch \initial - attribute \src "libresoc.v:178135.9-178135.17" + attribute \src "libresoc.v:180231.9-180231.17" case 1'1 case end @@ -368845,49 +371716,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11442 $4\wr_detect$7[0:0]$11445 + assign $1\wr_detect$7[0:0]$11493 $4\wr_detect$7[0:0]$11496 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11443 1'1 + assign $2\wr_detect$7[0:0]$11494 1'1 case - assign $2\wr_detect$7[0:0]$11443 1'0 + assign $2\wr_detect$7[0:0]$11494 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11444 1'1 + assign $3\wr_detect$7[0:0]$11495 1'1 case - assign $3\wr_detect$7[0:0]$11444 $2\wr_detect$7[0:0]$11443 + assign $3\wr_detect$7[0:0]$11495 $2\wr_detect$7[0:0]$11494 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11445 1'1 + assign $4\wr_detect$7[0:0]$11496 1'1 case - assign $4\wr_detect$7[0:0]$11445 $3\wr_detect$7[0:0]$11444 + assign $4\wr_detect$7[0:0]$11496 $3\wr_detect$7[0:0]$11495 end case - assign $1\wr_detect$7[0:0]$11442 1'0 + assign $1\wr_detect$7[0:0]$11493 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11441 + update \wr_detect$7 $0\wr_detect$7[0:0]$11492 end - attribute \src "libresoc.v:178164.3-178203.6" - process $proc$libresoc.v:178164$11446 + attribute \src "libresoc.v:180260.3-180299.6" + process $proc$libresoc.v:180260$11497 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11447 $6\r5__data_o$next[3:0]$11453 - attribute \src "libresoc.v:178165.5-178165.29" + assign $0\r5__data_o$next[3:0]$11498 $6\r5__data_o$next[3:0]$11504 + attribute \src "libresoc.v:180261.5-180261.29" switch \initial - attribute \src "libresoc.v:178165.9-178165.17" + attribute \src "libresoc.v:180261.9-180261.17" case 1'1 case end @@ -368899,66 +371770,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11448 $5\r5__data_o$next[3:0]$11452 + assign $1\r5__data_o$next[3:0]$11499 $5\r5__data_o$next[3:0]$11503 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11449 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11500 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11449 4'0000 + assign $2\r5__data_o$next[3:0]$11500 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11450 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11501 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11450 $2\r5__data_o$next[3:0]$11449 + assign $3\r5__data_o$next[3:0]$11501 $2\r5__data_o$next[3:0]$11500 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11451 \w5__data_i + assign $4\r5__data_o$next[3:0]$11502 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11451 $3\r5__data_o$next[3:0]$11450 + assign $4\r5__data_o$next[3:0]$11502 $3\r5__data_o$next[3:0]$11501 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11452 \reg + assign $5\r5__data_o$next[3:0]$11503 \reg case - assign $5\r5__data_o$next[3:0]$11452 $4\r5__data_o$next[3:0]$11451 + assign $5\r5__data_o$next[3:0]$11503 $4\r5__data_o$next[3:0]$11502 end case - assign $1\r5__data_o$next[3:0]$11448 4'0000 + assign $1\r5__data_o$next[3:0]$11499 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11453 4'0000 + assign $6\r5__data_o$next[3:0]$11504 4'0000 case - assign $6\r5__data_o$next[3:0]$11453 $1\r5__data_o$next[3:0]$11448 + assign $6\r5__data_o$next[3:0]$11504 $1\r5__data_o$next[3:0]$11499 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11447 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11498 end - attribute \src "libresoc.v:178204.3-178233.6" - process $proc$libresoc.v:178204$11454 + attribute \src "libresoc.v:180300.3-180329.6" + process $proc$libresoc.v:180300$11505 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11455 $1\wr_detect$10[0:0]$11456 - attribute \src "libresoc.v:178205.5-178205.29" + assign $0\wr_detect$10[0:0]$11506 $1\wr_detect$10[0:0]$11507 + attribute \src "libresoc.v:180301.5-180301.29" switch \initial - attribute \src "libresoc.v:178205.9-178205.17" + attribute \src "libresoc.v:180301.9-180301.17" case 1'1 case end @@ -368970,49 +371841,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11456 $4\wr_detect$10[0:0]$11459 + assign $1\wr_detect$10[0:0]$11507 $4\wr_detect$10[0:0]$11510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11457 1'1 + assign $2\wr_detect$10[0:0]$11508 1'1 case - assign $2\wr_detect$10[0:0]$11457 1'0 + assign $2\wr_detect$10[0:0]$11508 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11458 1'1 + assign $3\wr_detect$10[0:0]$11509 1'1 case - assign $3\wr_detect$10[0:0]$11458 $2\wr_detect$10[0:0]$11457 + assign $3\wr_detect$10[0:0]$11509 $2\wr_detect$10[0:0]$11508 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11459 1'1 + assign $4\wr_detect$10[0:0]$11510 1'1 case - assign $4\wr_detect$10[0:0]$11459 $3\wr_detect$10[0:0]$11458 + assign $4\wr_detect$10[0:0]$11510 $3\wr_detect$10[0:0]$11509 end case - assign $1\wr_detect$10[0:0]$11456 1'0 + assign $1\wr_detect$10[0:0]$11507 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11455 + update \wr_detect$10 $0\wr_detect$10[0:0]$11506 end - attribute \src "libresoc.v:178234.3-178273.6" - process $proc$libresoc.v:178234$11460 + attribute \src "libresoc.v:180330.3-180369.6" + process $proc$libresoc.v:180330$11511 assign { } { } assign { } { } assign { } { } - assign $0\r25__data_o$next[3:0]$11461 $6\r25__data_o$next[3:0]$11467 - attribute \src "libresoc.v:178235.5-178235.29" + assign $0\r25__data_o$next[3:0]$11512 $6\r25__data_o$next[3:0]$11518 + attribute \src "libresoc.v:180331.5-180331.29" switch \initial - attribute \src "libresoc.v:178235.9-178235.17" + attribute \src "libresoc.v:180331.9-180331.17" case 1'1 case end @@ -369024,66 +371895,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r25__data_o$next[3:0]$11462 $5\r25__data_o$next[3:0]$11466 + assign $1\r25__data_o$next[3:0]$11513 $5\r25__data_o$next[3:0]$11517 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r25__data_o$next[3:0]$11463 \dest15__data_i + assign $2\r25__data_o$next[3:0]$11514 \dest15__data_i case - assign $2\r25__data_o$next[3:0]$11463 4'0000 + assign $2\r25__data_o$next[3:0]$11514 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r25__data_o$next[3:0]$11464 \dest25__data_i + assign $3\r25__data_o$next[3:0]$11515 \dest25__data_i case - assign $3\r25__data_o$next[3:0]$11464 $2\r25__data_o$next[3:0]$11463 + assign $3\r25__data_o$next[3:0]$11515 $2\r25__data_o$next[3:0]$11514 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r25__data_o$next[3:0]$11465 \w5__data_i + assign $4\r25__data_o$next[3:0]$11516 \w5__data_i case - assign $4\r25__data_o$next[3:0]$11465 $3\r25__data_o$next[3:0]$11464 + assign $4\r25__data_o$next[3:0]$11516 $3\r25__data_o$next[3:0]$11515 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r25__data_o$next[3:0]$11466 \reg + assign $5\r25__data_o$next[3:0]$11517 \reg case - assign $5\r25__data_o$next[3:0]$11466 $4\r25__data_o$next[3:0]$11465 + assign $5\r25__data_o$next[3:0]$11517 $4\r25__data_o$next[3:0]$11516 end case - assign $1\r25__data_o$next[3:0]$11462 4'0000 + assign $1\r25__data_o$next[3:0]$11513 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r25__data_o$next[3:0]$11467 4'0000 + assign $6\r25__data_o$next[3:0]$11518 4'0000 case - assign $6\r25__data_o$next[3:0]$11467 $1\r25__data_o$next[3:0]$11462 + assign $6\r25__data_o$next[3:0]$11518 $1\r25__data_o$next[3:0]$11513 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11461 + update \r25__data_o$next $0\r25__data_o$next[3:0]$11512 end - attribute \src "libresoc.v:178274.3-178303.6" - process $proc$libresoc.v:178274$11468 + attribute \src "libresoc.v:180370.3-180399.6" + process $proc$libresoc.v:180370$11519 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11469 $1\wr_detect$13[0:0]$11470 - attribute \src "libresoc.v:178275.5-178275.29" + assign $0\wr_detect$13[0:0]$11520 $1\wr_detect$13[0:0]$11521 + attribute \src "libresoc.v:180371.5-180371.29" switch \initial - attribute \src "libresoc.v:178275.9-178275.17" + attribute \src "libresoc.v:180371.9-180371.17" case 1'1 case end @@ -369095,217 +371966,217 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11470 $4\wr_detect$13[0:0]$11473 + assign $1\wr_detect$13[0:0]$11521 $4\wr_detect$13[0:0]$11524 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11471 1'1 + assign $2\wr_detect$13[0:0]$11522 1'1 case - assign $2\wr_detect$13[0:0]$11471 1'0 + assign $2\wr_detect$13[0:0]$11522 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11472 1'1 + assign $3\wr_detect$13[0:0]$11523 1'1 case - assign $3\wr_detect$13[0:0]$11472 $2\wr_detect$13[0:0]$11471 + assign $3\wr_detect$13[0:0]$11523 $2\wr_detect$13[0:0]$11522 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11473 1'1 + assign $4\wr_detect$13[0:0]$11524 1'1 case - assign $4\wr_detect$13[0:0]$11473 $3\wr_detect$13[0:0]$11472 + assign $4\wr_detect$13[0:0]$11524 $3\wr_detect$13[0:0]$11523 end case - assign $1\wr_detect$13[0:0]$11470 1'0 + assign $1\wr_detect$13[0:0]$11521 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11469 + update \wr_detect$13 $0\wr_detect$13[0:0]$11520 end - connect \$9 $not$libresoc.v:177910$11392_Y - connect \$12 $not$libresoc.v:177911$11393_Y - connect \$1 $not$libresoc.v:177912$11394_Y - connect \$3 $not$libresoc.v:177913$11395_Y - connect \$6 $not$libresoc.v:177914$11396_Y + connect \$9 $not$libresoc.v:180006$11443_Y + connect \$12 $not$libresoc.v:180007$11444_Y + connect \$1 $not$libresoc.v:180008$11445_Y + connect \$3 $not$libresoc.v:180009$11446_Y + connect \$6 $not$libresoc.v:180010$11447_Y end -attribute \src "libresoc.v:178308.1-178779.10" +attribute \src "libresoc.v:180404.1-180875.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:178309.7-178309.20" + attribute \src "libresoc.v:180405.7-180405.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178709.3-178748.6" - wire width 4 $0\r26__data_o$next[3:0]$11550 - attribute \src "libresoc.v:178392.3-178393.39" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $0\r26__data_o$next[3:0]$11601 + attribute \src "libresoc.v:180488.3-180489.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:178639.3-178678.6" - wire width 4 $0\r6__data_o$next[3:0]$11536 - attribute \src "libresoc.v:178394.3-178395.37" + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $0\r6__data_o$next[3:0]$11587 + attribute \src "libresoc.v:180490.3-180491.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:178472.3-178498.6" - wire width 4 $0\reg$next[3:0]$11502 - attribute \src "libresoc.v:178390.3-178391.25" + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $0\reg$next[3:0]$11553 + attribute \src "libresoc.v:180486.3-180487.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:178402.3-178441.6" - wire width 4 $0\src16__data_o$next[3:0]$11493 - attribute \src "libresoc.v:178400.3-178401.43" + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $0\src16__data_o$next[3:0]$11544 + attribute \src "libresoc.v:180496.3-180497.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:178499.3-178538.6" - wire width 4 $0\src26__data_o$next[3:0]$11508 - attribute \src "libresoc.v:178398.3-178399.43" + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $0\src26__data_o$next[3:0]$11559 + attribute \src "libresoc.v:180494.3-180495.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:178569.3-178608.6" - wire width 4 $0\src36__data_o$next[3:0]$11522 - attribute \src "libresoc.v:178396.3-178397.43" + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $0\src36__data_o$next[3:0]$11573 + attribute \src "libresoc.v:180492.3-180493.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:178679.3-178708.6" - wire $0\wr_detect$10[0:0]$11544 - attribute \src "libresoc.v:178749.3-178778.6" - wire $0\wr_detect$13[0:0]$11558 - attribute \src "libresoc.v:178539.3-178568.6" - wire $0\wr_detect$4[0:0]$11516 - attribute \src "libresoc.v:178609.3-178638.6" - wire $0\wr_detect$7[0:0]$11530 - attribute \src "libresoc.v:178442.3-178471.6" + attribute \src "libresoc.v:180775.3-180804.6" + wire $0\wr_detect$10[0:0]$11595 + attribute \src "libresoc.v:180845.3-180874.6" + wire $0\wr_detect$13[0:0]$11609 + attribute \src "libresoc.v:180635.3-180664.6" + wire $0\wr_detect$4[0:0]$11567 + attribute \src "libresoc.v:180705.3-180734.6" + wire $0\wr_detect$7[0:0]$11581 + attribute \src "libresoc.v:180538.3-180567.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178709.3-178748.6" - wire width 4 $1\r26__data_o$next[3:0]$11551 - attribute \src "libresoc.v:178334.13-178334.31" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $1\r26__data_o$next[3:0]$11602 + attribute \src "libresoc.v:180430.13-180430.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:178639.3-178678.6" - wire width 4 $1\r6__data_o$next[3:0]$11537 - attribute \src "libresoc.v:178341.13-178341.30" + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $1\r6__data_o$next[3:0]$11588 + attribute \src "libresoc.v:180437.13-180437.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:178472.3-178498.6" - wire width 4 $1\reg$next[3:0]$11503 - attribute \src "libresoc.v:178347.13-178347.25" + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $1\reg$next[3:0]$11554 + attribute \src "libresoc.v:180443.13-180443.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:178402.3-178441.6" - wire width 4 $1\src16__data_o$next[3:0]$11494 - attribute \src "libresoc.v:178352.13-178352.33" + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $1\src16__data_o$next[3:0]$11545 + attribute \src "libresoc.v:180448.13-180448.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:178499.3-178538.6" - wire width 4 $1\src26__data_o$next[3:0]$11509 - attribute \src "libresoc.v:178359.13-178359.33" + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $1\src26__data_o$next[3:0]$11560 + attribute \src "libresoc.v:180455.13-180455.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:178569.3-178608.6" - wire width 4 $1\src36__data_o$next[3:0]$11523 - attribute \src "libresoc.v:178366.13-178366.33" + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $1\src36__data_o$next[3:0]$11574 + attribute \src "libresoc.v:180462.13-180462.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:178679.3-178708.6" - wire $1\wr_detect$10[0:0]$11545 - attribute \src "libresoc.v:178749.3-178778.6" - wire $1\wr_detect$13[0:0]$11559 - attribute \src "libresoc.v:178539.3-178568.6" - wire $1\wr_detect$4[0:0]$11517 - attribute \src "libresoc.v:178609.3-178638.6" - wire $1\wr_detect$7[0:0]$11531 - attribute \src "libresoc.v:178442.3-178471.6" + attribute \src "libresoc.v:180775.3-180804.6" + wire $1\wr_detect$10[0:0]$11596 + attribute \src "libresoc.v:180845.3-180874.6" + wire $1\wr_detect$13[0:0]$11610 + attribute \src "libresoc.v:180635.3-180664.6" + wire $1\wr_detect$4[0:0]$11568 + attribute \src "libresoc.v:180705.3-180734.6" + wire $1\wr_detect$7[0:0]$11582 + attribute \src "libresoc.v:180538.3-180567.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178709.3-178748.6" - wire width 4 $2\r26__data_o$next[3:0]$11552 - attribute \src "libresoc.v:178639.3-178678.6" - wire width 4 $2\r6__data_o$next[3:0]$11538 - attribute \src "libresoc.v:178472.3-178498.6" - wire width 4 $2\reg$next[3:0]$11504 - attribute \src "libresoc.v:178402.3-178441.6" - wire width 4 $2\src16__data_o$next[3:0]$11495 - attribute \src "libresoc.v:178499.3-178538.6" - wire width 4 $2\src26__data_o$next[3:0]$11510 - attribute \src "libresoc.v:178569.3-178608.6" - wire width 4 $2\src36__data_o$next[3:0]$11524 - attribute \src "libresoc.v:178679.3-178708.6" - wire $2\wr_detect$10[0:0]$11546 - attribute \src "libresoc.v:178749.3-178778.6" - wire $2\wr_detect$13[0:0]$11560 - attribute \src "libresoc.v:178539.3-178568.6" - wire $2\wr_detect$4[0:0]$11518 - attribute \src "libresoc.v:178609.3-178638.6" - wire $2\wr_detect$7[0:0]$11532 - attribute \src "libresoc.v:178442.3-178471.6" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $2\r26__data_o$next[3:0]$11603 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $2\r6__data_o$next[3:0]$11589 + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $2\reg$next[3:0]$11555 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $2\src16__data_o$next[3:0]$11546 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $2\src26__data_o$next[3:0]$11561 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $2\src36__data_o$next[3:0]$11575 + attribute \src "libresoc.v:180775.3-180804.6" + wire $2\wr_detect$10[0:0]$11597 + attribute \src "libresoc.v:180845.3-180874.6" + wire $2\wr_detect$13[0:0]$11611 + attribute \src "libresoc.v:180635.3-180664.6" + wire $2\wr_detect$4[0:0]$11569 + attribute \src "libresoc.v:180705.3-180734.6" + wire $2\wr_detect$7[0:0]$11583 + attribute \src "libresoc.v:180538.3-180567.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178709.3-178748.6" - wire width 4 $3\r26__data_o$next[3:0]$11553 - attribute \src "libresoc.v:178639.3-178678.6" - wire width 4 $3\r6__data_o$next[3:0]$11539 - attribute \src "libresoc.v:178472.3-178498.6" - wire width 4 $3\reg$next[3:0]$11505 - attribute \src "libresoc.v:178402.3-178441.6" - wire width 4 $3\src16__data_o$next[3:0]$11496 - attribute \src "libresoc.v:178499.3-178538.6" - wire width 4 $3\src26__data_o$next[3:0]$11511 - attribute \src "libresoc.v:178569.3-178608.6" - wire width 4 $3\src36__data_o$next[3:0]$11525 - attribute \src "libresoc.v:178679.3-178708.6" - wire $3\wr_detect$10[0:0]$11547 - attribute \src "libresoc.v:178749.3-178778.6" - wire $3\wr_detect$13[0:0]$11561 - attribute \src "libresoc.v:178539.3-178568.6" - wire $3\wr_detect$4[0:0]$11519 - attribute \src "libresoc.v:178609.3-178638.6" - wire $3\wr_detect$7[0:0]$11533 - attribute \src "libresoc.v:178442.3-178471.6" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $3\r26__data_o$next[3:0]$11604 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $3\r6__data_o$next[3:0]$11590 + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $3\reg$next[3:0]$11556 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $3\src16__data_o$next[3:0]$11547 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $3\src26__data_o$next[3:0]$11562 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $3\src36__data_o$next[3:0]$11576 + attribute \src "libresoc.v:180775.3-180804.6" + wire $3\wr_detect$10[0:0]$11598 + attribute \src "libresoc.v:180845.3-180874.6" + wire $3\wr_detect$13[0:0]$11612 + attribute \src "libresoc.v:180635.3-180664.6" + wire $3\wr_detect$4[0:0]$11570 + attribute \src "libresoc.v:180705.3-180734.6" + wire $3\wr_detect$7[0:0]$11584 + attribute \src "libresoc.v:180538.3-180567.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178709.3-178748.6" - wire width 4 $4\r26__data_o$next[3:0]$11554 - attribute \src "libresoc.v:178639.3-178678.6" - wire width 4 $4\r6__data_o$next[3:0]$11540 - attribute \src "libresoc.v:178472.3-178498.6" - wire width 4 $4\reg$next[3:0]$11506 - attribute \src "libresoc.v:178402.3-178441.6" - wire width 4 $4\src16__data_o$next[3:0]$11497 - attribute \src "libresoc.v:178499.3-178538.6" - wire width 4 $4\src26__data_o$next[3:0]$11512 - attribute \src "libresoc.v:178569.3-178608.6" - wire width 4 $4\src36__data_o$next[3:0]$11526 - attribute \src "libresoc.v:178679.3-178708.6" - wire $4\wr_detect$10[0:0]$11548 - attribute \src "libresoc.v:178749.3-178778.6" - wire $4\wr_detect$13[0:0]$11562 - attribute \src "libresoc.v:178539.3-178568.6" - wire $4\wr_detect$4[0:0]$11520 - attribute \src "libresoc.v:178609.3-178638.6" - wire $4\wr_detect$7[0:0]$11534 - attribute \src "libresoc.v:178442.3-178471.6" + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $4\r26__data_o$next[3:0]$11605 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $4\r6__data_o$next[3:0]$11591 + attribute \src "libresoc.v:180568.3-180594.6" + wire width 4 $4\reg$next[3:0]$11557 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $4\src16__data_o$next[3:0]$11548 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $4\src26__data_o$next[3:0]$11563 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $4\src36__data_o$next[3:0]$11577 + attribute \src "libresoc.v:180775.3-180804.6" + wire $4\wr_detect$10[0:0]$11599 + attribute \src "libresoc.v:180845.3-180874.6" + wire $4\wr_detect$13[0:0]$11613 + attribute \src "libresoc.v:180635.3-180664.6" + wire $4\wr_detect$4[0:0]$11571 + attribute \src "libresoc.v:180705.3-180734.6" + wire $4\wr_detect$7[0:0]$11585 + attribute \src "libresoc.v:180538.3-180567.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178709.3-178748.6" - wire width 4 $5\r26__data_o$next[3:0]$11555 - attribute \src "libresoc.v:178639.3-178678.6" - wire width 4 $5\r6__data_o$next[3:0]$11541 - attribute \src "libresoc.v:178402.3-178441.6" - wire width 4 $5\src16__data_o$next[3:0]$11498 - attribute \src "libresoc.v:178499.3-178538.6" - wire width 4 $5\src26__data_o$next[3:0]$11513 - attribute \src "libresoc.v:178569.3-178608.6" - wire width 4 $5\src36__data_o$next[3:0]$11527 - attribute \src "libresoc.v:178709.3-178748.6" - wire width 4 $6\r26__data_o$next[3:0]$11556 - attribute \src "libresoc.v:178639.3-178678.6" - wire width 4 $6\r6__data_o$next[3:0]$11542 - attribute \src "libresoc.v:178402.3-178441.6" - wire width 4 $6\src16__data_o$next[3:0]$11499 - attribute \src "libresoc.v:178499.3-178538.6" - wire width 4 $6\src26__data_o$next[3:0]$11514 - attribute \src "libresoc.v:178569.3-178608.6" - wire width 4 $6\src36__data_o$next[3:0]$11528 - attribute \src "libresoc.v:178385.17-178385.104" - wire $not$libresoc.v:178385$11481_Y - attribute \src "libresoc.v:178386.18-178386.105" - wire $not$libresoc.v:178386$11482_Y - attribute \src "libresoc.v:178387.17-178387.100" - wire $not$libresoc.v:178387$11483_Y - attribute \src "libresoc.v:178388.17-178388.103" - wire $not$libresoc.v:178388$11484_Y - attribute \src "libresoc.v:178389.17-178389.103" - wire $not$libresoc.v:178389$11485_Y + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $5\r26__data_o$next[3:0]$11606 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $5\r6__data_o$next[3:0]$11592 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $5\src16__data_o$next[3:0]$11549 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $5\src26__data_o$next[3:0]$11564 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $5\src36__data_o$next[3:0]$11578 + attribute \src "libresoc.v:180805.3-180844.6" + wire width 4 $6\r26__data_o$next[3:0]$11607 + attribute \src "libresoc.v:180735.3-180774.6" + wire width 4 $6\r6__data_o$next[3:0]$11593 + attribute \src "libresoc.v:180498.3-180537.6" + wire width 4 $6\src16__data_o$next[3:0]$11550 + attribute \src "libresoc.v:180595.3-180634.6" + wire width 4 $6\src26__data_o$next[3:0]$11565 + attribute \src "libresoc.v:180665.3-180704.6" + wire width 4 $6\src36__data_o$next[3:0]$11579 + attribute \src "libresoc.v:180481.17-180481.104" + wire $not$libresoc.v:180481$11532_Y + attribute \src "libresoc.v:180482.18-180482.105" + wire $not$libresoc.v:180482$11533_Y + attribute \src "libresoc.v:180483.17-180483.100" + wire $not$libresoc.v:180483$11534_Y + attribute \src "libresoc.v:180484.17-180484.103" + wire $not$libresoc.v:180484$11535_Y + attribute \src "libresoc.v:180485.17-180485.103" + wire $not$libresoc.v:180485$11536_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -369316,9 +372187,9 @@ module \reg_6 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest16__data_i @@ -369328,7 +372199,7 @@ module \reg_6 wire width 4 input 11 \dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest26__wen - attribute \src "libresoc.v:178309.7-178309.15" + attribute \src "libresoc.v:180405.7-180405.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r26__data_o @@ -369379,152 +372250,152 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178385$11481 + cell $not $not$libresoc.v:180481$11532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178385$11481_Y + connect \Y $not$libresoc.v:180481$11532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178386$11482 + cell $not $not$libresoc.v:180482$11533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:178386$11482_Y + connect \Y $not$libresoc.v:180482$11533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178387$11483 + cell $not $not$libresoc.v:180483$11534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178387$11483_Y + connect \Y $not$libresoc.v:180483$11534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178388$11484 + cell $not $not$libresoc.v:180484$11535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178388$11484_Y + connect \Y $not$libresoc.v:180484$11535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178389$11485 + cell $not $not$libresoc.v:180485$11536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178389$11485_Y + connect \Y $not$libresoc.v:180485$11536_Y end - attribute \src "libresoc.v:178309.7-178309.20" - process $proc$libresoc.v:178309$11563 + attribute \src "libresoc.v:180405.7-180405.20" + process $proc$libresoc.v:180405$11614 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178334.13-178334.31" - process $proc$libresoc.v:178334$11564 + attribute \src "libresoc.v:180430.13-180430.31" + process $proc$libresoc.v:180430$11615 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:178341.13-178341.30" - process $proc$libresoc.v:178341$11565 + attribute \src "libresoc.v:180437.13-180437.30" + process $proc$libresoc.v:180437$11616 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:178347.13-178347.25" - process $proc$libresoc.v:178347$11566 + attribute \src "libresoc.v:180443.13-180443.25" + process $proc$libresoc.v:180443$11617 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:178352.13-178352.33" - process $proc$libresoc.v:178352$11567 + attribute \src "libresoc.v:180448.13-180448.33" + process $proc$libresoc.v:180448$11618 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:178359.13-178359.33" - process $proc$libresoc.v:178359$11568 + attribute \src "libresoc.v:180455.13-180455.33" + process $proc$libresoc.v:180455$11619 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:178366.13-178366.33" - process $proc$libresoc.v:178366$11569 + attribute \src "libresoc.v:180462.13-180462.33" + process $proc$libresoc.v:180462$11620 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:178390.3-178391.25" - process $proc$libresoc.v:178390$11486 + attribute \src "libresoc.v:180486.3-180487.25" + process $proc$libresoc.v:180486$11537 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:178392.3-178393.39" - process $proc$libresoc.v:178392$11487 + attribute \src "libresoc.v:180488.3-180489.39" + process $proc$libresoc.v:180488$11538 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:178394.3-178395.37" - process $proc$libresoc.v:178394$11488 + attribute \src "libresoc.v:180490.3-180491.37" + process $proc$libresoc.v:180490$11539 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:178396.3-178397.43" - process $proc$libresoc.v:178396$11489 + attribute \src "libresoc.v:180492.3-180493.43" + process $proc$libresoc.v:180492$11540 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:178398.3-178399.43" - process $proc$libresoc.v:178398$11490 + attribute \src "libresoc.v:180494.3-180495.43" + process $proc$libresoc.v:180494$11541 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:178400.3-178401.43" - process $proc$libresoc.v:178400$11491 + attribute \src "libresoc.v:180496.3-180497.43" + process $proc$libresoc.v:180496$11542 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:178402.3-178441.6" - process $proc$libresoc.v:178402$11492 + attribute \src "libresoc.v:180498.3-180537.6" + process $proc$libresoc.v:180498$11543 assign { } { } assign { } { } assign { } { } - assign $0\src16__data_o$next[3:0]$11493 $6\src16__data_o$next[3:0]$11499 - attribute \src "libresoc.v:178403.5-178403.29" + assign $0\src16__data_o$next[3:0]$11544 $6\src16__data_o$next[3:0]$11550 + attribute \src "libresoc.v:180499.5-180499.29" switch \initial - attribute \src "libresoc.v:178403.9-178403.17" + attribute \src "libresoc.v:180499.9-180499.17" case 1'1 case end @@ -369536,66 +372407,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src16__data_o$next[3:0]$11494 $5\src16__data_o$next[3:0]$11498 + assign $1\src16__data_o$next[3:0]$11545 $5\src16__data_o$next[3:0]$11549 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src16__data_o$next[3:0]$11495 \dest16__data_i + assign $2\src16__data_o$next[3:0]$11546 \dest16__data_i case - assign $2\src16__data_o$next[3:0]$11495 4'0000 + assign $2\src16__data_o$next[3:0]$11546 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src16__data_o$next[3:0]$11496 \dest26__data_i + assign $3\src16__data_o$next[3:0]$11547 \dest26__data_i case - assign $3\src16__data_o$next[3:0]$11496 $2\src16__data_o$next[3:0]$11495 + assign $3\src16__data_o$next[3:0]$11547 $2\src16__data_o$next[3:0]$11546 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src16__data_o$next[3:0]$11497 \w6__data_i + assign $4\src16__data_o$next[3:0]$11548 \w6__data_i case - assign $4\src16__data_o$next[3:0]$11497 $3\src16__data_o$next[3:0]$11496 + assign $4\src16__data_o$next[3:0]$11548 $3\src16__data_o$next[3:0]$11547 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11498 \reg + assign $5\src16__data_o$next[3:0]$11549 \reg case - assign $5\src16__data_o$next[3:0]$11498 $4\src16__data_o$next[3:0]$11497 + assign $5\src16__data_o$next[3:0]$11549 $4\src16__data_o$next[3:0]$11548 end case - assign $1\src16__data_o$next[3:0]$11494 4'0000 + assign $1\src16__data_o$next[3:0]$11545 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11499 4'0000 + assign $6\src16__data_o$next[3:0]$11550 4'0000 case - assign $6\src16__data_o$next[3:0]$11499 $1\src16__data_o$next[3:0]$11494 + assign $6\src16__data_o$next[3:0]$11550 $1\src16__data_o$next[3:0]$11545 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11493 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11544 end - attribute \src "libresoc.v:178442.3-178471.6" - process $proc$libresoc.v:178442$11500 + attribute \src "libresoc.v:180538.3-180567.6" + process $proc$libresoc.v:180538$11551 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178443.5-178443.29" + attribute \src "libresoc.v:180539.5-180539.29" switch \initial - attribute \src "libresoc.v:178443.9-178443.17" + attribute \src "libresoc.v:180539.9-180539.17" case 1'1 case end @@ -369641,17 +372512,17 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178472.3-178498.6" - process $proc$libresoc.v:178472$11501 + attribute \src "libresoc.v:180568.3-180594.6" + process $proc$libresoc.v:180568$11552 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11502 $4\reg$next[3:0]$11506 - attribute \src "libresoc.v:178473.5-178473.29" + assign $0\reg$next[3:0]$11553 $4\reg$next[3:0]$11557 + attribute \src "libresoc.v:180569.5-180569.29" switch \initial - attribute \src "libresoc.v:178473.9-178473.17" + attribute \src "libresoc.v:180569.9-180569.17" case 1'1 case end @@ -369660,49 +372531,49 @@ module \reg_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11503 \dest16__data_i + assign $1\reg$next[3:0]$11554 \dest16__data_i case - assign $1\reg$next[3:0]$11503 \reg + assign $1\reg$next[3:0]$11554 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11504 \dest26__data_i + assign $2\reg$next[3:0]$11555 \dest26__data_i case - assign $2\reg$next[3:0]$11504 $1\reg$next[3:0]$11503 + assign $2\reg$next[3:0]$11555 $1\reg$next[3:0]$11554 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11505 \w6__data_i + assign $3\reg$next[3:0]$11556 \w6__data_i case - assign $3\reg$next[3:0]$11505 $2\reg$next[3:0]$11504 + assign $3\reg$next[3:0]$11556 $2\reg$next[3:0]$11555 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11506 4'0000 + assign $4\reg$next[3:0]$11557 4'0000 case - assign $4\reg$next[3:0]$11506 $3\reg$next[3:0]$11505 + assign $4\reg$next[3:0]$11557 $3\reg$next[3:0]$11556 end sync always - update \reg$next $0\reg$next[3:0]$11502 + update \reg$next $0\reg$next[3:0]$11553 end - attribute \src "libresoc.v:178499.3-178538.6" - process $proc$libresoc.v:178499$11507 + attribute \src "libresoc.v:180595.3-180634.6" + process $proc$libresoc.v:180595$11558 assign { } { } assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11508 $6\src26__data_o$next[3:0]$11514 - attribute \src "libresoc.v:178500.5-178500.29" + assign $0\src26__data_o$next[3:0]$11559 $6\src26__data_o$next[3:0]$11565 + attribute \src "libresoc.v:180596.5-180596.29" switch \initial - attribute \src "libresoc.v:178500.9-178500.17" + attribute \src "libresoc.v:180596.9-180596.17" case 1'1 case end @@ -369714,66 +372585,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11509 $5\src26__data_o$next[3:0]$11513 + assign $1\src26__data_o$next[3:0]$11560 $5\src26__data_o$next[3:0]$11564 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11510 \dest16__data_i + assign $2\src26__data_o$next[3:0]$11561 \dest16__data_i case - assign $2\src26__data_o$next[3:0]$11510 4'0000 + assign $2\src26__data_o$next[3:0]$11561 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11511 \dest26__data_i + assign $3\src26__data_o$next[3:0]$11562 \dest26__data_i case - assign $3\src26__data_o$next[3:0]$11511 $2\src26__data_o$next[3:0]$11510 + assign $3\src26__data_o$next[3:0]$11562 $2\src26__data_o$next[3:0]$11561 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11512 \w6__data_i + assign $4\src26__data_o$next[3:0]$11563 \w6__data_i case - assign $4\src26__data_o$next[3:0]$11512 $3\src26__data_o$next[3:0]$11511 + assign $4\src26__data_o$next[3:0]$11563 $3\src26__data_o$next[3:0]$11562 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11513 \reg + assign $5\src26__data_o$next[3:0]$11564 \reg case - assign $5\src26__data_o$next[3:0]$11513 $4\src26__data_o$next[3:0]$11512 + assign $5\src26__data_o$next[3:0]$11564 $4\src26__data_o$next[3:0]$11563 end case - assign $1\src26__data_o$next[3:0]$11509 4'0000 + assign $1\src26__data_o$next[3:0]$11560 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11514 4'0000 + assign $6\src26__data_o$next[3:0]$11565 4'0000 case - assign $6\src26__data_o$next[3:0]$11514 $1\src26__data_o$next[3:0]$11509 + assign $6\src26__data_o$next[3:0]$11565 $1\src26__data_o$next[3:0]$11560 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11508 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11559 end - attribute \src "libresoc.v:178539.3-178568.6" - process $proc$libresoc.v:178539$11515 + attribute \src "libresoc.v:180635.3-180664.6" + process $proc$libresoc.v:180635$11566 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11516 $1\wr_detect$4[0:0]$11517 - attribute \src "libresoc.v:178540.5-178540.29" + assign $0\wr_detect$4[0:0]$11567 $1\wr_detect$4[0:0]$11568 + attribute \src "libresoc.v:180636.5-180636.29" switch \initial - attribute \src "libresoc.v:178540.9-178540.17" + attribute \src "libresoc.v:180636.9-180636.17" case 1'1 case end @@ -369785,49 +372656,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11517 $4\wr_detect$4[0:0]$11520 + assign $1\wr_detect$4[0:0]$11568 $4\wr_detect$4[0:0]$11571 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11518 1'1 + assign $2\wr_detect$4[0:0]$11569 1'1 case - assign $2\wr_detect$4[0:0]$11518 1'0 + assign $2\wr_detect$4[0:0]$11569 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11519 1'1 + assign $3\wr_detect$4[0:0]$11570 1'1 case - assign $3\wr_detect$4[0:0]$11519 $2\wr_detect$4[0:0]$11518 + assign $3\wr_detect$4[0:0]$11570 $2\wr_detect$4[0:0]$11569 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11520 1'1 + assign $4\wr_detect$4[0:0]$11571 1'1 case - assign $4\wr_detect$4[0:0]$11520 $3\wr_detect$4[0:0]$11519 + assign $4\wr_detect$4[0:0]$11571 $3\wr_detect$4[0:0]$11570 end case - assign $1\wr_detect$4[0:0]$11517 1'0 + assign $1\wr_detect$4[0:0]$11568 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11516 + update \wr_detect$4 $0\wr_detect$4[0:0]$11567 end - attribute \src "libresoc.v:178569.3-178608.6" - process $proc$libresoc.v:178569$11521 + attribute \src "libresoc.v:180665.3-180704.6" + process $proc$libresoc.v:180665$11572 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11522 $6\src36__data_o$next[3:0]$11528 - attribute \src "libresoc.v:178570.5-178570.29" + assign $0\src36__data_o$next[3:0]$11573 $6\src36__data_o$next[3:0]$11579 + attribute \src "libresoc.v:180666.5-180666.29" switch \initial - attribute \src "libresoc.v:178570.9-178570.17" + attribute \src "libresoc.v:180666.9-180666.17" case 1'1 case end @@ -369839,66 +372710,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11523 $5\src36__data_o$next[3:0]$11527 + assign $1\src36__data_o$next[3:0]$11574 $5\src36__data_o$next[3:0]$11578 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11524 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11575 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11524 4'0000 + assign $2\src36__data_o$next[3:0]$11575 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11525 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11576 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11525 $2\src36__data_o$next[3:0]$11524 + assign $3\src36__data_o$next[3:0]$11576 $2\src36__data_o$next[3:0]$11575 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11526 \w6__data_i + assign $4\src36__data_o$next[3:0]$11577 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11526 $3\src36__data_o$next[3:0]$11525 + assign $4\src36__data_o$next[3:0]$11577 $3\src36__data_o$next[3:0]$11576 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11527 \reg + assign $5\src36__data_o$next[3:0]$11578 \reg case - assign $5\src36__data_o$next[3:0]$11527 $4\src36__data_o$next[3:0]$11526 + assign $5\src36__data_o$next[3:0]$11578 $4\src36__data_o$next[3:0]$11577 end case - assign $1\src36__data_o$next[3:0]$11523 4'0000 + assign $1\src36__data_o$next[3:0]$11574 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11528 4'0000 + assign $6\src36__data_o$next[3:0]$11579 4'0000 case - assign $6\src36__data_o$next[3:0]$11528 $1\src36__data_o$next[3:0]$11523 + assign $6\src36__data_o$next[3:0]$11579 $1\src36__data_o$next[3:0]$11574 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11522 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11573 end - attribute \src "libresoc.v:178609.3-178638.6" - process $proc$libresoc.v:178609$11529 + attribute \src "libresoc.v:180705.3-180734.6" + process $proc$libresoc.v:180705$11580 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11530 $1\wr_detect$7[0:0]$11531 - attribute \src "libresoc.v:178610.5-178610.29" + assign $0\wr_detect$7[0:0]$11581 $1\wr_detect$7[0:0]$11582 + attribute \src "libresoc.v:180706.5-180706.29" switch \initial - attribute \src "libresoc.v:178610.9-178610.17" + attribute \src "libresoc.v:180706.9-180706.17" case 1'1 case end @@ -369910,49 +372781,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11531 $4\wr_detect$7[0:0]$11534 + assign $1\wr_detect$7[0:0]$11582 $4\wr_detect$7[0:0]$11585 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11532 1'1 + assign $2\wr_detect$7[0:0]$11583 1'1 case - assign $2\wr_detect$7[0:0]$11532 1'0 + assign $2\wr_detect$7[0:0]$11583 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11533 1'1 + assign $3\wr_detect$7[0:0]$11584 1'1 case - assign $3\wr_detect$7[0:0]$11533 $2\wr_detect$7[0:0]$11532 + assign $3\wr_detect$7[0:0]$11584 $2\wr_detect$7[0:0]$11583 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11534 1'1 + assign $4\wr_detect$7[0:0]$11585 1'1 case - assign $4\wr_detect$7[0:0]$11534 $3\wr_detect$7[0:0]$11533 + assign $4\wr_detect$7[0:0]$11585 $3\wr_detect$7[0:0]$11584 end case - assign $1\wr_detect$7[0:0]$11531 1'0 + assign $1\wr_detect$7[0:0]$11582 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11530 + update \wr_detect$7 $0\wr_detect$7[0:0]$11581 end - attribute \src "libresoc.v:178639.3-178678.6" - process $proc$libresoc.v:178639$11535 + attribute \src "libresoc.v:180735.3-180774.6" + process $proc$libresoc.v:180735$11586 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11536 $6\r6__data_o$next[3:0]$11542 - attribute \src "libresoc.v:178640.5-178640.29" + assign $0\r6__data_o$next[3:0]$11587 $6\r6__data_o$next[3:0]$11593 + attribute \src "libresoc.v:180736.5-180736.29" switch \initial - attribute \src "libresoc.v:178640.9-178640.17" + attribute \src "libresoc.v:180736.9-180736.17" case 1'1 case end @@ -369964,66 +372835,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11537 $5\r6__data_o$next[3:0]$11541 + assign $1\r6__data_o$next[3:0]$11588 $5\r6__data_o$next[3:0]$11592 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11538 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11589 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11538 4'0000 + assign $2\r6__data_o$next[3:0]$11589 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11539 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11590 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11539 $2\r6__data_o$next[3:0]$11538 + assign $3\r6__data_o$next[3:0]$11590 $2\r6__data_o$next[3:0]$11589 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11540 \w6__data_i + assign $4\r6__data_o$next[3:0]$11591 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11540 $3\r6__data_o$next[3:0]$11539 + assign $4\r6__data_o$next[3:0]$11591 $3\r6__data_o$next[3:0]$11590 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11541 \reg + assign $5\r6__data_o$next[3:0]$11592 \reg case - assign $5\r6__data_o$next[3:0]$11541 $4\r6__data_o$next[3:0]$11540 + assign $5\r6__data_o$next[3:0]$11592 $4\r6__data_o$next[3:0]$11591 end case - assign $1\r6__data_o$next[3:0]$11537 4'0000 + assign $1\r6__data_o$next[3:0]$11588 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11542 4'0000 + assign $6\r6__data_o$next[3:0]$11593 4'0000 case - assign $6\r6__data_o$next[3:0]$11542 $1\r6__data_o$next[3:0]$11537 + assign $6\r6__data_o$next[3:0]$11593 $1\r6__data_o$next[3:0]$11588 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11536 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11587 end - attribute \src "libresoc.v:178679.3-178708.6" - process $proc$libresoc.v:178679$11543 + attribute \src "libresoc.v:180775.3-180804.6" + process $proc$libresoc.v:180775$11594 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11544 $1\wr_detect$10[0:0]$11545 - attribute \src "libresoc.v:178680.5-178680.29" + assign $0\wr_detect$10[0:0]$11595 $1\wr_detect$10[0:0]$11596 + attribute \src "libresoc.v:180776.5-180776.29" switch \initial - attribute \src "libresoc.v:178680.9-178680.17" + attribute \src "libresoc.v:180776.9-180776.17" case 1'1 case end @@ -370035,49 +372906,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11545 $4\wr_detect$10[0:0]$11548 + assign $1\wr_detect$10[0:0]$11596 $4\wr_detect$10[0:0]$11599 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11546 1'1 + assign $2\wr_detect$10[0:0]$11597 1'1 case - assign $2\wr_detect$10[0:0]$11546 1'0 + assign $2\wr_detect$10[0:0]$11597 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11547 1'1 + assign $3\wr_detect$10[0:0]$11598 1'1 case - assign $3\wr_detect$10[0:0]$11547 $2\wr_detect$10[0:0]$11546 + assign $3\wr_detect$10[0:0]$11598 $2\wr_detect$10[0:0]$11597 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11548 1'1 + assign $4\wr_detect$10[0:0]$11599 1'1 case - assign $4\wr_detect$10[0:0]$11548 $3\wr_detect$10[0:0]$11547 + assign $4\wr_detect$10[0:0]$11599 $3\wr_detect$10[0:0]$11598 end case - assign $1\wr_detect$10[0:0]$11545 1'0 + assign $1\wr_detect$10[0:0]$11596 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11544 + update \wr_detect$10 $0\wr_detect$10[0:0]$11595 end - attribute \src "libresoc.v:178709.3-178748.6" - process $proc$libresoc.v:178709$11549 + attribute \src "libresoc.v:180805.3-180844.6" + process $proc$libresoc.v:180805$11600 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11550 $6\r26__data_o$next[3:0]$11556 - attribute \src "libresoc.v:178710.5-178710.29" + assign $0\r26__data_o$next[3:0]$11601 $6\r26__data_o$next[3:0]$11607 + attribute \src "libresoc.v:180806.5-180806.29" switch \initial - attribute \src "libresoc.v:178710.9-178710.17" + attribute \src "libresoc.v:180806.9-180806.17" case 1'1 case end @@ -370089,66 +372960,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r26__data_o$next[3:0]$11551 $5\r26__data_o$next[3:0]$11555 + assign $1\r26__data_o$next[3:0]$11602 $5\r26__data_o$next[3:0]$11606 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r26__data_o$next[3:0]$11552 \dest16__data_i + assign $2\r26__data_o$next[3:0]$11603 \dest16__data_i case - assign $2\r26__data_o$next[3:0]$11552 4'0000 + assign $2\r26__data_o$next[3:0]$11603 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r26__data_o$next[3:0]$11553 \dest26__data_i + assign $3\r26__data_o$next[3:0]$11604 \dest26__data_i case - assign $3\r26__data_o$next[3:0]$11553 $2\r26__data_o$next[3:0]$11552 + assign $3\r26__data_o$next[3:0]$11604 $2\r26__data_o$next[3:0]$11603 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r26__data_o$next[3:0]$11554 \w6__data_i + assign $4\r26__data_o$next[3:0]$11605 \w6__data_i case - assign $4\r26__data_o$next[3:0]$11554 $3\r26__data_o$next[3:0]$11553 + assign $4\r26__data_o$next[3:0]$11605 $3\r26__data_o$next[3:0]$11604 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r26__data_o$next[3:0]$11555 \reg + assign $5\r26__data_o$next[3:0]$11606 \reg case - assign $5\r26__data_o$next[3:0]$11555 $4\r26__data_o$next[3:0]$11554 + assign $5\r26__data_o$next[3:0]$11606 $4\r26__data_o$next[3:0]$11605 end case - assign $1\r26__data_o$next[3:0]$11551 4'0000 + assign $1\r26__data_o$next[3:0]$11602 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11556 4'0000 + assign $6\r26__data_o$next[3:0]$11607 4'0000 case - assign $6\r26__data_o$next[3:0]$11556 $1\r26__data_o$next[3:0]$11551 + assign $6\r26__data_o$next[3:0]$11607 $1\r26__data_o$next[3:0]$11602 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11550 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11601 end - attribute \src "libresoc.v:178749.3-178778.6" - process $proc$libresoc.v:178749$11557 + attribute \src "libresoc.v:180845.3-180874.6" + process $proc$libresoc.v:180845$11608 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11558 $1\wr_detect$13[0:0]$11559 - attribute \src "libresoc.v:178750.5-178750.29" + assign $0\wr_detect$13[0:0]$11609 $1\wr_detect$13[0:0]$11610 + attribute \src "libresoc.v:180846.5-180846.29" switch \initial - attribute \src "libresoc.v:178750.9-178750.17" + attribute \src "libresoc.v:180846.9-180846.17" case 1'1 case end @@ -370160,217 +373031,217 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11559 $4\wr_detect$13[0:0]$11562 + assign $1\wr_detect$13[0:0]$11610 $4\wr_detect$13[0:0]$11613 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11560 1'1 + assign $2\wr_detect$13[0:0]$11611 1'1 case - assign $2\wr_detect$13[0:0]$11560 1'0 + assign $2\wr_detect$13[0:0]$11611 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11561 1'1 + assign $3\wr_detect$13[0:0]$11612 1'1 case - assign $3\wr_detect$13[0:0]$11561 $2\wr_detect$13[0:0]$11560 + assign $3\wr_detect$13[0:0]$11612 $2\wr_detect$13[0:0]$11611 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11562 1'1 + assign $4\wr_detect$13[0:0]$11613 1'1 case - assign $4\wr_detect$13[0:0]$11562 $3\wr_detect$13[0:0]$11561 + assign $4\wr_detect$13[0:0]$11613 $3\wr_detect$13[0:0]$11612 end case - assign $1\wr_detect$13[0:0]$11559 1'0 + assign $1\wr_detect$13[0:0]$11610 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11558 + update \wr_detect$13 $0\wr_detect$13[0:0]$11609 end - connect \$9 $not$libresoc.v:178385$11481_Y - connect \$12 $not$libresoc.v:178386$11482_Y - connect \$1 $not$libresoc.v:178387$11483_Y - connect \$3 $not$libresoc.v:178388$11484_Y - connect \$6 $not$libresoc.v:178389$11485_Y + connect \$9 $not$libresoc.v:180481$11532_Y + connect \$12 $not$libresoc.v:180482$11533_Y + connect \$1 $not$libresoc.v:180483$11534_Y + connect \$3 $not$libresoc.v:180484$11535_Y + connect \$6 $not$libresoc.v:180485$11536_Y end -attribute \src "libresoc.v:178783.1-179254.10" +attribute \src "libresoc.v:180879.1-181350.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:178784.7-178784.20" + attribute \src "libresoc.v:180880.7-180880.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179184.3-179223.6" - wire width 4 $0\r27__data_o$next[3:0]$11639 - attribute \src "libresoc.v:178867.3-178868.39" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $0\r27__data_o$next[3:0]$11690 + attribute \src "libresoc.v:180963.3-180964.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:179114.3-179153.6" - wire width 4 $0\r7__data_o$next[3:0]$11625 - attribute \src "libresoc.v:178869.3-178870.37" + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $0\r7__data_o$next[3:0]$11676 + attribute \src "libresoc.v:180965.3-180966.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:178947.3-178973.6" - wire width 4 $0\reg$next[3:0]$11591 - attribute \src "libresoc.v:178865.3-178866.25" + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $0\reg$next[3:0]$11642 + attribute \src "libresoc.v:180961.3-180962.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:178877.3-178916.6" - wire width 4 $0\src17__data_o$next[3:0]$11582 - attribute \src "libresoc.v:178875.3-178876.43" + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $0\src17__data_o$next[3:0]$11633 + attribute \src "libresoc.v:180971.3-180972.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:178974.3-179013.6" - wire width 4 $0\src27__data_o$next[3:0]$11597 - attribute \src "libresoc.v:178873.3-178874.43" + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $0\src27__data_o$next[3:0]$11648 + attribute \src "libresoc.v:180969.3-180970.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:179044.3-179083.6" - wire width 4 $0\src37__data_o$next[3:0]$11611 - attribute \src "libresoc.v:178871.3-178872.43" + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $0\src37__data_o$next[3:0]$11662 + attribute \src "libresoc.v:180967.3-180968.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:179154.3-179183.6" - wire $0\wr_detect$10[0:0]$11633 - attribute \src "libresoc.v:179224.3-179253.6" - wire $0\wr_detect$13[0:0]$11647 - attribute \src "libresoc.v:179014.3-179043.6" - wire $0\wr_detect$4[0:0]$11605 - attribute \src "libresoc.v:179084.3-179113.6" - wire $0\wr_detect$7[0:0]$11619 - attribute \src "libresoc.v:178917.3-178946.6" + attribute \src "libresoc.v:181250.3-181279.6" + wire $0\wr_detect$10[0:0]$11684 + attribute \src "libresoc.v:181320.3-181349.6" + wire $0\wr_detect$13[0:0]$11698 + attribute \src "libresoc.v:181110.3-181139.6" + wire $0\wr_detect$4[0:0]$11656 + attribute \src "libresoc.v:181180.3-181209.6" + wire $0\wr_detect$7[0:0]$11670 + attribute \src "libresoc.v:181013.3-181042.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179184.3-179223.6" - wire width 4 $1\r27__data_o$next[3:0]$11640 - attribute \src "libresoc.v:178809.13-178809.31" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $1\r27__data_o$next[3:0]$11691 + attribute \src "libresoc.v:180905.13-180905.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:179114.3-179153.6" - wire width 4 $1\r7__data_o$next[3:0]$11626 - attribute \src "libresoc.v:178816.13-178816.30" + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $1\r7__data_o$next[3:0]$11677 + attribute \src "libresoc.v:180912.13-180912.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:178947.3-178973.6" - wire width 4 $1\reg$next[3:0]$11592 - attribute \src "libresoc.v:178822.13-178822.25" + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $1\reg$next[3:0]$11643 + attribute \src "libresoc.v:180918.13-180918.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:178877.3-178916.6" - wire width 4 $1\src17__data_o$next[3:0]$11583 - attribute \src "libresoc.v:178827.13-178827.33" + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $1\src17__data_o$next[3:0]$11634 + attribute \src "libresoc.v:180923.13-180923.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:178974.3-179013.6" - wire width 4 $1\src27__data_o$next[3:0]$11598 - attribute \src "libresoc.v:178834.13-178834.33" + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $1\src27__data_o$next[3:0]$11649 + attribute \src "libresoc.v:180930.13-180930.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:179044.3-179083.6" - wire width 4 $1\src37__data_o$next[3:0]$11612 - attribute \src "libresoc.v:178841.13-178841.33" + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $1\src37__data_o$next[3:0]$11663 + attribute \src "libresoc.v:180937.13-180937.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:179154.3-179183.6" - wire $1\wr_detect$10[0:0]$11634 - attribute \src "libresoc.v:179224.3-179253.6" - wire $1\wr_detect$13[0:0]$11648 - attribute \src "libresoc.v:179014.3-179043.6" - wire $1\wr_detect$4[0:0]$11606 - attribute \src "libresoc.v:179084.3-179113.6" - wire $1\wr_detect$7[0:0]$11620 - attribute \src "libresoc.v:178917.3-178946.6" + attribute \src "libresoc.v:181250.3-181279.6" + wire $1\wr_detect$10[0:0]$11685 + attribute \src "libresoc.v:181320.3-181349.6" + wire $1\wr_detect$13[0:0]$11699 + attribute \src "libresoc.v:181110.3-181139.6" + wire $1\wr_detect$4[0:0]$11657 + attribute \src "libresoc.v:181180.3-181209.6" + wire $1\wr_detect$7[0:0]$11671 + attribute \src "libresoc.v:181013.3-181042.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179184.3-179223.6" - wire width 4 $2\r27__data_o$next[3:0]$11641 - attribute \src "libresoc.v:179114.3-179153.6" - wire width 4 $2\r7__data_o$next[3:0]$11627 - attribute \src "libresoc.v:178947.3-178973.6" - wire width 4 $2\reg$next[3:0]$11593 - attribute \src "libresoc.v:178877.3-178916.6" - wire width 4 $2\src17__data_o$next[3:0]$11584 - attribute \src "libresoc.v:178974.3-179013.6" - wire width 4 $2\src27__data_o$next[3:0]$11599 - attribute \src "libresoc.v:179044.3-179083.6" - wire width 4 $2\src37__data_o$next[3:0]$11613 - attribute \src "libresoc.v:179154.3-179183.6" - wire $2\wr_detect$10[0:0]$11635 - attribute \src "libresoc.v:179224.3-179253.6" - wire $2\wr_detect$13[0:0]$11649 - attribute \src "libresoc.v:179014.3-179043.6" - wire $2\wr_detect$4[0:0]$11607 - attribute \src "libresoc.v:179084.3-179113.6" - wire $2\wr_detect$7[0:0]$11621 - attribute \src "libresoc.v:178917.3-178946.6" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $2\r27__data_o$next[3:0]$11692 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $2\r7__data_o$next[3:0]$11678 + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $2\reg$next[3:0]$11644 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $2\src17__data_o$next[3:0]$11635 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $2\src27__data_o$next[3:0]$11650 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $2\src37__data_o$next[3:0]$11664 + attribute \src "libresoc.v:181250.3-181279.6" + wire $2\wr_detect$10[0:0]$11686 + attribute \src "libresoc.v:181320.3-181349.6" + wire $2\wr_detect$13[0:0]$11700 + attribute \src "libresoc.v:181110.3-181139.6" + wire $2\wr_detect$4[0:0]$11658 + attribute \src "libresoc.v:181180.3-181209.6" + wire $2\wr_detect$7[0:0]$11672 + attribute \src "libresoc.v:181013.3-181042.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179184.3-179223.6" - wire width 4 $3\r27__data_o$next[3:0]$11642 - attribute \src "libresoc.v:179114.3-179153.6" - wire width 4 $3\r7__data_o$next[3:0]$11628 - attribute \src "libresoc.v:178947.3-178973.6" - wire width 4 $3\reg$next[3:0]$11594 - attribute \src "libresoc.v:178877.3-178916.6" - wire width 4 $3\src17__data_o$next[3:0]$11585 - attribute \src "libresoc.v:178974.3-179013.6" - wire width 4 $3\src27__data_o$next[3:0]$11600 - attribute \src "libresoc.v:179044.3-179083.6" - wire width 4 $3\src37__data_o$next[3:0]$11614 - attribute \src "libresoc.v:179154.3-179183.6" - wire $3\wr_detect$10[0:0]$11636 - attribute \src "libresoc.v:179224.3-179253.6" - wire $3\wr_detect$13[0:0]$11650 - attribute \src "libresoc.v:179014.3-179043.6" - wire $3\wr_detect$4[0:0]$11608 - attribute \src "libresoc.v:179084.3-179113.6" - wire $3\wr_detect$7[0:0]$11622 - attribute \src "libresoc.v:178917.3-178946.6" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $3\r27__data_o$next[3:0]$11693 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $3\r7__data_o$next[3:0]$11679 + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $3\reg$next[3:0]$11645 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $3\src17__data_o$next[3:0]$11636 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $3\src27__data_o$next[3:0]$11651 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $3\src37__data_o$next[3:0]$11665 + attribute \src "libresoc.v:181250.3-181279.6" + wire $3\wr_detect$10[0:0]$11687 + attribute \src "libresoc.v:181320.3-181349.6" + wire $3\wr_detect$13[0:0]$11701 + attribute \src "libresoc.v:181110.3-181139.6" + wire $3\wr_detect$4[0:0]$11659 + attribute \src "libresoc.v:181180.3-181209.6" + wire $3\wr_detect$7[0:0]$11673 + attribute \src "libresoc.v:181013.3-181042.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179184.3-179223.6" - wire width 4 $4\r27__data_o$next[3:0]$11643 - attribute \src "libresoc.v:179114.3-179153.6" - wire width 4 $4\r7__data_o$next[3:0]$11629 - attribute \src "libresoc.v:178947.3-178973.6" - wire width 4 $4\reg$next[3:0]$11595 - attribute \src "libresoc.v:178877.3-178916.6" - wire width 4 $4\src17__data_o$next[3:0]$11586 - attribute \src "libresoc.v:178974.3-179013.6" - wire width 4 $4\src27__data_o$next[3:0]$11601 - attribute \src "libresoc.v:179044.3-179083.6" - wire width 4 $4\src37__data_o$next[3:0]$11615 - attribute \src "libresoc.v:179154.3-179183.6" - wire $4\wr_detect$10[0:0]$11637 - attribute \src "libresoc.v:179224.3-179253.6" - wire $4\wr_detect$13[0:0]$11651 - attribute \src "libresoc.v:179014.3-179043.6" - wire $4\wr_detect$4[0:0]$11609 - attribute \src "libresoc.v:179084.3-179113.6" - wire $4\wr_detect$7[0:0]$11623 - attribute \src "libresoc.v:178917.3-178946.6" + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $4\r27__data_o$next[3:0]$11694 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $4\r7__data_o$next[3:0]$11680 + attribute \src "libresoc.v:181043.3-181069.6" + wire width 4 $4\reg$next[3:0]$11646 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $4\src17__data_o$next[3:0]$11637 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $4\src27__data_o$next[3:0]$11652 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $4\src37__data_o$next[3:0]$11666 + attribute \src "libresoc.v:181250.3-181279.6" + wire $4\wr_detect$10[0:0]$11688 + attribute \src "libresoc.v:181320.3-181349.6" + wire $4\wr_detect$13[0:0]$11702 + attribute \src "libresoc.v:181110.3-181139.6" + wire $4\wr_detect$4[0:0]$11660 + attribute \src "libresoc.v:181180.3-181209.6" + wire $4\wr_detect$7[0:0]$11674 + attribute \src "libresoc.v:181013.3-181042.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179184.3-179223.6" - wire width 4 $5\r27__data_o$next[3:0]$11644 - attribute \src "libresoc.v:179114.3-179153.6" - wire width 4 $5\r7__data_o$next[3:0]$11630 - attribute \src "libresoc.v:178877.3-178916.6" - wire width 4 $5\src17__data_o$next[3:0]$11587 - attribute \src "libresoc.v:178974.3-179013.6" - wire width 4 $5\src27__data_o$next[3:0]$11602 - attribute \src "libresoc.v:179044.3-179083.6" - wire width 4 $5\src37__data_o$next[3:0]$11616 - attribute \src "libresoc.v:179184.3-179223.6" - wire width 4 $6\r27__data_o$next[3:0]$11645 - attribute \src "libresoc.v:179114.3-179153.6" - wire width 4 $6\r7__data_o$next[3:0]$11631 - attribute \src "libresoc.v:178877.3-178916.6" - wire width 4 $6\src17__data_o$next[3:0]$11588 - attribute \src "libresoc.v:178974.3-179013.6" - wire width 4 $6\src27__data_o$next[3:0]$11603 - attribute \src "libresoc.v:179044.3-179083.6" - wire width 4 $6\src37__data_o$next[3:0]$11617 - attribute \src "libresoc.v:178860.17-178860.104" - wire $not$libresoc.v:178860$11570_Y - attribute \src "libresoc.v:178861.18-178861.105" - wire $not$libresoc.v:178861$11571_Y - attribute \src "libresoc.v:178862.17-178862.100" - wire $not$libresoc.v:178862$11572_Y - attribute \src "libresoc.v:178863.17-178863.103" - wire $not$libresoc.v:178863$11573_Y - attribute \src "libresoc.v:178864.17-178864.103" - wire $not$libresoc.v:178864$11574_Y + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $5\r27__data_o$next[3:0]$11695 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $5\r7__data_o$next[3:0]$11681 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $5\src17__data_o$next[3:0]$11638 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $5\src27__data_o$next[3:0]$11653 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $5\src37__data_o$next[3:0]$11667 + attribute \src "libresoc.v:181280.3-181319.6" + wire width 4 $6\r27__data_o$next[3:0]$11696 + attribute \src "libresoc.v:181210.3-181249.6" + wire width 4 $6\r7__data_o$next[3:0]$11682 + attribute \src "libresoc.v:180973.3-181012.6" + wire width 4 $6\src17__data_o$next[3:0]$11639 + attribute \src "libresoc.v:181070.3-181109.6" + wire width 4 $6\src27__data_o$next[3:0]$11654 + attribute \src "libresoc.v:181140.3-181179.6" + wire width 4 $6\src37__data_o$next[3:0]$11668 + attribute \src "libresoc.v:180956.17-180956.104" + wire $not$libresoc.v:180956$11621_Y + attribute \src "libresoc.v:180957.18-180957.105" + wire $not$libresoc.v:180957$11622_Y + attribute \src "libresoc.v:180958.17-180958.100" + wire $not$libresoc.v:180958$11623_Y + attribute \src "libresoc.v:180959.17-180959.103" + wire $not$libresoc.v:180959$11624_Y + attribute \src "libresoc.v:180960.17-180960.103" + wire $not$libresoc.v:180960$11625_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -370381,9 +373252,9 @@ module \reg_7 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest17__data_i @@ -370393,7 +373264,7 @@ module \reg_7 wire width 4 input 11 \dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest27__wen - attribute \src "libresoc.v:178784.7-178784.15" + attribute \src "libresoc.v:180880.7-180880.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r27__data_o @@ -370444,152 +373315,152 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178860$11570 + cell $not $not$libresoc.v:180956$11621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178860$11570_Y + connect \Y $not$libresoc.v:180956$11621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178861$11571 + cell $not $not$libresoc.v:180957$11622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:178861$11571_Y + connect \Y $not$libresoc.v:180957$11622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178862$11572 + cell $not $not$libresoc.v:180958$11623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178862$11572_Y + connect \Y $not$libresoc.v:180958$11623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178863$11573 + cell $not $not$libresoc.v:180959$11624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178863$11573_Y + connect \Y $not$libresoc.v:180959$11624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178864$11574 + cell $not $not$libresoc.v:180960$11625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178864$11574_Y + connect \Y $not$libresoc.v:180960$11625_Y end - attribute \src "libresoc.v:178784.7-178784.20" - process $proc$libresoc.v:178784$11652 + attribute \src "libresoc.v:180880.7-180880.20" + process $proc$libresoc.v:180880$11703 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178809.13-178809.31" - process $proc$libresoc.v:178809$11653 + attribute \src "libresoc.v:180905.13-180905.31" + process $proc$libresoc.v:180905$11704 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:178816.13-178816.30" - process $proc$libresoc.v:178816$11654 + attribute \src "libresoc.v:180912.13-180912.30" + process $proc$libresoc.v:180912$11705 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:178822.13-178822.25" - process $proc$libresoc.v:178822$11655 + attribute \src "libresoc.v:180918.13-180918.25" + process $proc$libresoc.v:180918$11706 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:178827.13-178827.33" - process $proc$libresoc.v:178827$11656 + attribute \src "libresoc.v:180923.13-180923.33" + process $proc$libresoc.v:180923$11707 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:178834.13-178834.33" - process $proc$libresoc.v:178834$11657 + attribute \src "libresoc.v:180930.13-180930.33" + process $proc$libresoc.v:180930$11708 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:178841.13-178841.33" - process $proc$libresoc.v:178841$11658 + attribute \src "libresoc.v:180937.13-180937.33" + process $proc$libresoc.v:180937$11709 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:178865.3-178866.25" - process $proc$libresoc.v:178865$11575 + attribute \src "libresoc.v:180961.3-180962.25" + process $proc$libresoc.v:180961$11626 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:178867.3-178868.39" - process $proc$libresoc.v:178867$11576 + attribute \src "libresoc.v:180963.3-180964.39" + process $proc$libresoc.v:180963$11627 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:178869.3-178870.37" - process $proc$libresoc.v:178869$11577 + attribute \src "libresoc.v:180965.3-180966.37" + process $proc$libresoc.v:180965$11628 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:178871.3-178872.43" - process $proc$libresoc.v:178871$11578 + attribute \src "libresoc.v:180967.3-180968.43" + process $proc$libresoc.v:180967$11629 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:178873.3-178874.43" - process $proc$libresoc.v:178873$11579 + attribute \src "libresoc.v:180969.3-180970.43" + process $proc$libresoc.v:180969$11630 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:178875.3-178876.43" - process $proc$libresoc.v:178875$11580 + attribute \src "libresoc.v:180971.3-180972.43" + process $proc$libresoc.v:180971$11631 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:178877.3-178916.6" - process $proc$libresoc.v:178877$11581 + attribute \src "libresoc.v:180973.3-181012.6" + process $proc$libresoc.v:180973$11632 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11582 $6\src17__data_o$next[3:0]$11588 - attribute \src "libresoc.v:178878.5-178878.29" + assign $0\src17__data_o$next[3:0]$11633 $6\src17__data_o$next[3:0]$11639 + attribute \src "libresoc.v:180974.5-180974.29" switch \initial - attribute \src "libresoc.v:178878.9-178878.17" + attribute \src "libresoc.v:180974.9-180974.17" case 1'1 case end @@ -370601,66 +373472,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11583 $5\src17__data_o$next[3:0]$11587 + assign $1\src17__data_o$next[3:0]$11634 $5\src17__data_o$next[3:0]$11638 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11584 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11635 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11584 4'0000 + assign $2\src17__data_o$next[3:0]$11635 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11585 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11636 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11585 $2\src17__data_o$next[3:0]$11584 + assign $3\src17__data_o$next[3:0]$11636 $2\src17__data_o$next[3:0]$11635 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11586 \w7__data_i + assign $4\src17__data_o$next[3:0]$11637 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11586 $3\src17__data_o$next[3:0]$11585 + assign $4\src17__data_o$next[3:0]$11637 $3\src17__data_o$next[3:0]$11636 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11587 \reg + assign $5\src17__data_o$next[3:0]$11638 \reg case - assign $5\src17__data_o$next[3:0]$11587 $4\src17__data_o$next[3:0]$11586 + assign $5\src17__data_o$next[3:0]$11638 $4\src17__data_o$next[3:0]$11637 end case - assign $1\src17__data_o$next[3:0]$11583 4'0000 + assign $1\src17__data_o$next[3:0]$11634 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11588 4'0000 + assign $6\src17__data_o$next[3:0]$11639 4'0000 case - assign $6\src17__data_o$next[3:0]$11588 $1\src17__data_o$next[3:0]$11583 + assign $6\src17__data_o$next[3:0]$11639 $1\src17__data_o$next[3:0]$11634 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11582 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11633 end - attribute \src "libresoc.v:178917.3-178946.6" - process $proc$libresoc.v:178917$11589 + attribute \src "libresoc.v:181013.3-181042.6" + process $proc$libresoc.v:181013$11640 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178918.5-178918.29" + attribute \src "libresoc.v:181014.5-181014.29" switch \initial - attribute \src "libresoc.v:178918.9-178918.17" + attribute \src "libresoc.v:181014.9-181014.17" case 1'1 case end @@ -370706,17 +373577,17 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178947.3-178973.6" - process $proc$libresoc.v:178947$11590 + attribute \src "libresoc.v:181043.3-181069.6" + process $proc$libresoc.v:181043$11641 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11591 $4\reg$next[3:0]$11595 - attribute \src "libresoc.v:178948.5-178948.29" + assign $0\reg$next[3:0]$11642 $4\reg$next[3:0]$11646 + attribute \src "libresoc.v:181044.5-181044.29" switch \initial - attribute \src "libresoc.v:178948.9-178948.17" + attribute \src "libresoc.v:181044.9-181044.17" case 1'1 case end @@ -370725,49 +373596,49 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11592 \dest17__data_i + assign $1\reg$next[3:0]$11643 \dest17__data_i case - assign $1\reg$next[3:0]$11592 \reg + assign $1\reg$next[3:0]$11643 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11593 \dest27__data_i + assign $2\reg$next[3:0]$11644 \dest27__data_i case - assign $2\reg$next[3:0]$11593 $1\reg$next[3:0]$11592 + assign $2\reg$next[3:0]$11644 $1\reg$next[3:0]$11643 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11594 \w7__data_i + assign $3\reg$next[3:0]$11645 \w7__data_i case - assign $3\reg$next[3:0]$11594 $2\reg$next[3:0]$11593 + assign $3\reg$next[3:0]$11645 $2\reg$next[3:0]$11644 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11595 4'0000 + assign $4\reg$next[3:0]$11646 4'0000 case - assign $4\reg$next[3:0]$11595 $3\reg$next[3:0]$11594 + assign $4\reg$next[3:0]$11646 $3\reg$next[3:0]$11645 end sync always - update \reg$next $0\reg$next[3:0]$11591 + update \reg$next $0\reg$next[3:0]$11642 end - attribute \src "libresoc.v:178974.3-179013.6" - process $proc$libresoc.v:178974$11596 + attribute \src "libresoc.v:181070.3-181109.6" + process $proc$libresoc.v:181070$11647 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11597 $6\src27__data_o$next[3:0]$11603 - attribute \src "libresoc.v:178975.5-178975.29" + assign $0\src27__data_o$next[3:0]$11648 $6\src27__data_o$next[3:0]$11654 + attribute \src "libresoc.v:181071.5-181071.29" switch \initial - attribute \src "libresoc.v:178975.9-178975.17" + attribute \src "libresoc.v:181071.9-181071.17" case 1'1 case end @@ -370779,66 +373650,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11598 $5\src27__data_o$next[3:0]$11602 + assign $1\src27__data_o$next[3:0]$11649 $5\src27__data_o$next[3:0]$11653 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11599 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11650 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11599 4'0000 + assign $2\src27__data_o$next[3:0]$11650 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11600 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11651 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11600 $2\src27__data_o$next[3:0]$11599 + assign $3\src27__data_o$next[3:0]$11651 $2\src27__data_o$next[3:0]$11650 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11601 \w7__data_i + assign $4\src27__data_o$next[3:0]$11652 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11601 $3\src27__data_o$next[3:0]$11600 + assign $4\src27__data_o$next[3:0]$11652 $3\src27__data_o$next[3:0]$11651 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11602 \reg + assign $5\src27__data_o$next[3:0]$11653 \reg case - assign $5\src27__data_o$next[3:0]$11602 $4\src27__data_o$next[3:0]$11601 + assign $5\src27__data_o$next[3:0]$11653 $4\src27__data_o$next[3:0]$11652 end case - assign $1\src27__data_o$next[3:0]$11598 4'0000 + assign $1\src27__data_o$next[3:0]$11649 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11603 4'0000 + assign $6\src27__data_o$next[3:0]$11654 4'0000 case - assign $6\src27__data_o$next[3:0]$11603 $1\src27__data_o$next[3:0]$11598 + assign $6\src27__data_o$next[3:0]$11654 $1\src27__data_o$next[3:0]$11649 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11597 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11648 end - attribute \src "libresoc.v:179014.3-179043.6" - process $proc$libresoc.v:179014$11604 + attribute \src "libresoc.v:181110.3-181139.6" + process $proc$libresoc.v:181110$11655 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11605 $1\wr_detect$4[0:0]$11606 - attribute \src "libresoc.v:179015.5-179015.29" + assign $0\wr_detect$4[0:0]$11656 $1\wr_detect$4[0:0]$11657 + attribute \src "libresoc.v:181111.5-181111.29" switch \initial - attribute \src "libresoc.v:179015.9-179015.17" + attribute \src "libresoc.v:181111.9-181111.17" case 1'1 case end @@ -370850,49 +373721,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11606 $4\wr_detect$4[0:0]$11609 + assign $1\wr_detect$4[0:0]$11657 $4\wr_detect$4[0:0]$11660 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11607 1'1 + assign $2\wr_detect$4[0:0]$11658 1'1 case - assign $2\wr_detect$4[0:0]$11607 1'0 + assign $2\wr_detect$4[0:0]$11658 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11608 1'1 + assign $3\wr_detect$4[0:0]$11659 1'1 case - assign $3\wr_detect$4[0:0]$11608 $2\wr_detect$4[0:0]$11607 + assign $3\wr_detect$4[0:0]$11659 $2\wr_detect$4[0:0]$11658 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11609 1'1 + assign $4\wr_detect$4[0:0]$11660 1'1 case - assign $4\wr_detect$4[0:0]$11609 $3\wr_detect$4[0:0]$11608 + assign $4\wr_detect$4[0:0]$11660 $3\wr_detect$4[0:0]$11659 end case - assign $1\wr_detect$4[0:0]$11606 1'0 + assign $1\wr_detect$4[0:0]$11657 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11605 + update \wr_detect$4 $0\wr_detect$4[0:0]$11656 end - attribute \src "libresoc.v:179044.3-179083.6" - process $proc$libresoc.v:179044$11610 + attribute \src "libresoc.v:181140.3-181179.6" + process $proc$libresoc.v:181140$11661 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11611 $6\src37__data_o$next[3:0]$11617 - attribute \src "libresoc.v:179045.5-179045.29" + assign $0\src37__data_o$next[3:0]$11662 $6\src37__data_o$next[3:0]$11668 + attribute \src "libresoc.v:181141.5-181141.29" switch \initial - attribute \src "libresoc.v:179045.9-179045.17" + attribute \src "libresoc.v:181141.9-181141.17" case 1'1 case end @@ -370904,66 +373775,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$11612 $5\src37__data_o$next[3:0]$11616 + assign $1\src37__data_o$next[3:0]$11663 $5\src37__data_o$next[3:0]$11667 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$11613 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11664 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$11613 4'0000 + assign $2\src37__data_o$next[3:0]$11664 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$11614 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11665 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$11614 $2\src37__data_o$next[3:0]$11613 + assign $3\src37__data_o$next[3:0]$11665 $2\src37__data_o$next[3:0]$11664 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$11615 \w7__data_i + assign $4\src37__data_o$next[3:0]$11666 \w7__data_i case - assign $4\src37__data_o$next[3:0]$11615 $3\src37__data_o$next[3:0]$11614 + assign $4\src37__data_o$next[3:0]$11666 $3\src37__data_o$next[3:0]$11665 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$11616 \reg + assign $5\src37__data_o$next[3:0]$11667 \reg case - assign $5\src37__data_o$next[3:0]$11616 $4\src37__data_o$next[3:0]$11615 + assign $5\src37__data_o$next[3:0]$11667 $4\src37__data_o$next[3:0]$11666 end case - assign $1\src37__data_o$next[3:0]$11612 4'0000 + assign $1\src37__data_o$next[3:0]$11663 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$11617 4'0000 + assign $6\src37__data_o$next[3:0]$11668 4'0000 case - assign $6\src37__data_o$next[3:0]$11617 $1\src37__data_o$next[3:0]$11612 + assign $6\src37__data_o$next[3:0]$11668 $1\src37__data_o$next[3:0]$11663 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11611 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11662 end - attribute \src "libresoc.v:179084.3-179113.6" - process $proc$libresoc.v:179084$11618 + attribute \src "libresoc.v:181180.3-181209.6" + process $proc$libresoc.v:181180$11669 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11619 $1\wr_detect$7[0:0]$11620 - attribute \src "libresoc.v:179085.5-179085.29" + assign $0\wr_detect$7[0:0]$11670 $1\wr_detect$7[0:0]$11671 + attribute \src "libresoc.v:181181.5-181181.29" switch \initial - attribute \src "libresoc.v:179085.9-179085.17" + attribute \src "libresoc.v:181181.9-181181.17" case 1'1 case end @@ -370975,49 +373846,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11620 $4\wr_detect$7[0:0]$11623 + assign $1\wr_detect$7[0:0]$11671 $4\wr_detect$7[0:0]$11674 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11621 1'1 + assign $2\wr_detect$7[0:0]$11672 1'1 case - assign $2\wr_detect$7[0:0]$11621 1'0 + assign $2\wr_detect$7[0:0]$11672 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11622 1'1 + assign $3\wr_detect$7[0:0]$11673 1'1 case - assign $3\wr_detect$7[0:0]$11622 $2\wr_detect$7[0:0]$11621 + assign $3\wr_detect$7[0:0]$11673 $2\wr_detect$7[0:0]$11672 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11623 1'1 + assign $4\wr_detect$7[0:0]$11674 1'1 case - assign $4\wr_detect$7[0:0]$11623 $3\wr_detect$7[0:0]$11622 + assign $4\wr_detect$7[0:0]$11674 $3\wr_detect$7[0:0]$11673 end case - assign $1\wr_detect$7[0:0]$11620 1'0 + assign $1\wr_detect$7[0:0]$11671 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11619 + update \wr_detect$7 $0\wr_detect$7[0:0]$11670 end - attribute \src "libresoc.v:179114.3-179153.6" - process $proc$libresoc.v:179114$11624 + attribute \src "libresoc.v:181210.3-181249.6" + process $proc$libresoc.v:181210$11675 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$11625 $6\r7__data_o$next[3:0]$11631 - attribute \src "libresoc.v:179115.5-179115.29" + assign $0\r7__data_o$next[3:0]$11676 $6\r7__data_o$next[3:0]$11682 + attribute \src "libresoc.v:181211.5-181211.29" switch \initial - attribute \src "libresoc.v:179115.9-179115.17" + attribute \src "libresoc.v:181211.9-181211.17" case 1'1 case end @@ -371029,66 +373900,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$11626 $5\r7__data_o$next[3:0]$11630 + assign $1\r7__data_o$next[3:0]$11677 $5\r7__data_o$next[3:0]$11681 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$11627 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11678 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$11627 4'0000 + assign $2\r7__data_o$next[3:0]$11678 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$11628 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11679 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$11628 $2\r7__data_o$next[3:0]$11627 + assign $3\r7__data_o$next[3:0]$11679 $2\r7__data_o$next[3:0]$11678 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$11629 \w7__data_i + assign $4\r7__data_o$next[3:0]$11680 \w7__data_i case - assign $4\r7__data_o$next[3:0]$11629 $3\r7__data_o$next[3:0]$11628 + assign $4\r7__data_o$next[3:0]$11680 $3\r7__data_o$next[3:0]$11679 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$11630 \reg + assign $5\r7__data_o$next[3:0]$11681 \reg case - assign $5\r7__data_o$next[3:0]$11630 $4\r7__data_o$next[3:0]$11629 + assign $5\r7__data_o$next[3:0]$11681 $4\r7__data_o$next[3:0]$11680 end case - assign $1\r7__data_o$next[3:0]$11626 4'0000 + assign $1\r7__data_o$next[3:0]$11677 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$11631 4'0000 + assign $6\r7__data_o$next[3:0]$11682 4'0000 case - assign $6\r7__data_o$next[3:0]$11631 $1\r7__data_o$next[3:0]$11626 + assign $6\r7__data_o$next[3:0]$11682 $1\r7__data_o$next[3:0]$11677 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11625 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11676 end - attribute \src "libresoc.v:179154.3-179183.6" - process $proc$libresoc.v:179154$11632 + attribute \src "libresoc.v:181250.3-181279.6" + process $proc$libresoc.v:181250$11683 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11633 $1\wr_detect$10[0:0]$11634 - attribute \src "libresoc.v:179155.5-179155.29" + assign $0\wr_detect$10[0:0]$11684 $1\wr_detect$10[0:0]$11685 + attribute \src "libresoc.v:181251.5-181251.29" switch \initial - attribute \src "libresoc.v:179155.9-179155.17" + attribute \src "libresoc.v:181251.9-181251.17" case 1'1 case end @@ -371100,49 +373971,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11634 $4\wr_detect$10[0:0]$11637 + assign $1\wr_detect$10[0:0]$11685 $4\wr_detect$10[0:0]$11688 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11635 1'1 + assign $2\wr_detect$10[0:0]$11686 1'1 case - assign $2\wr_detect$10[0:0]$11635 1'0 + assign $2\wr_detect$10[0:0]$11686 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11636 1'1 + assign $3\wr_detect$10[0:0]$11687 1'1 case - assign $3\wr_detect$10[0:0]$11636 $2\wr_detect$10[0:0]$11635 + assign $3\wr_detect$10[0:0]$11687 $2\wr_detect$10[0:0]$11686 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11637 1'1 + assign $4\wr_detect$10[0:0]$11688 1'1 case - assign $4\wr_detect$10[0:0]$11637 $3\wr_detect$10[0:0]$11636 + assign $4\wr_detect$10[0:0]$11688 $3\wr_detect$10[0:0]$11687 end case - assign $1\wr_detect$10[0:0]$11634 1'0 + assign $1\wr_detect$10[0:0]$11685 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11633 + update \wr_detect$10 $0\wr_detect$10[0:0]$11684 end - attribute \src "libresoc.v:179184.3-179223.6" - process $proc$libresoc.v:179184$11638 + attribute \src "libresoc.v:181280.3-181319.6" + process $proc$libresoc.v:181280$11689 assign { } { } assign { } { } assign { } { } - assign $0\r27__data_o$next[3:0]$11639 $6\r27__data_o$next[3:0]$11645 - attribute \src "libresoc.v:179185.5-179185.29" + assign $0\r27__data_o$next[3:0]$11690 $6\r27__data_o$next[3:0]$11696 + attribute \src "libresoc.v:181281.5-181281.29" switch \initial - attribute \src "libresoc.v:179185.9-179185.17" + attribute \src "libresoc.v:181281.9-181281.17" case 1'1 case end @@ -371154,66 +374025,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r27__data_o$next[3:0]$11640 $5\r27__data_o$next[3:0]$11644 + assign $1\r27__data_o$next[3:0]$11691 $5\r27__data_o$next[3:0]$11695 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r27__data_o$next[3:0]$11641 \dest17__data_i + assign $2\r27__data_o$next[3:0]$11692 \dest17__data_i case - assign $2\r27__data_o$next[3:0]$11641 4'0000 + assign $2\r27__data_o$next[3:0]$11692 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r27__data_o$next[3:0]$11642 \dest27__data_i + assign $3\r27__data_o$next[3:0]$11693 \dest27__data_i case - assign $3\r27__data_o$next[3:0]$11642 $2\r27__data_o$next[3:0]$11641 + assign $3\r27__data_o$next[3:0]$11693 $2\r27__data_o$next[3:0]$11692 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r27__data_o$next[3:0]$11643 \w7__data_i + assign $4\r27__data_o$next[3:0]$11694 \w7__data_i case - assign $4\r27__data_o$next[3:0]$11643 $3\r27__data_o$next[3:0]$11642 + assign $4\r27__data_o$next[3:0]$11694 $3\r27__data_o$next[3:0]$11693 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r27__data_o$next[3:0]$11644 \reg + assign $5\r27__data_o$next[3:0]$11695 \reg case - assign $5\r27__data_o$next[3:0]$11644 $4\r27__data_o$next[3:0]$11643 + assign $5\r27__data_o$next[3:0]$11695 $4\r27__data_o$next[3:0]$11694 end case - assign $1\r27__data_o$next[3:0]$11640 4'0000 + assign $1\r27__data_o$next[3:0]$11691 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r27__data_o$next[3:0]$11645 4'0000 + assign $6\r27__data_o$next[3:0]$11696 4'0000 case - assign $6\r27__data_o$next[3:0]$11645 $1\r27__data_o$next[3:0]$11640 + assign $6\r27__data_o$next[3:0]$11696 $1\r27__data_o$next[3:0]$11691 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11639 + update \r27__data_o$next $0\r27__data_o$next[3:0]$11690 end - attribute \src "libresoc.v:179224.3-179253.6" - process $proc$libresoc.v:179224$11646 + attribute \src "libresoc.v:181320.3-181349.6" + process $proc$libresoc.v:181320$11697 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11647 $1\wr_detect$13[0:0]$11648 - attribute \src "libresoc.v:179225.5-179225.29" + assign $0\wr_detect$13[0:0]$11698 $1\wr_detect$13[0:0]$11699 + attribute \src "libresoc.v:181321.5-181321.29" switch \initial - attribute \src "libresoc.v:179225.9-179225.17" + attribute \src "libresoc.v:181321.9-181321.17" case 1'1 case end @@ -371225,77 +374096,77 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11648 $4\wr_detect$13[0:0]$11651 + assign $1\wr_detect$13[0:0]$11699 $4\wr_detect$13[0:0]$11702 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11649 1'1 + assign $2\wr_detect$13[0:0]$11700 1'1 case - assign $2\wr_detect$13[0:0]$11649 1'0 + assign $2\wr_detect$13[0:0]$11700 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11650 1'1 + assign $3\wr_detect$13[0:0]$11701 1'1 case - assign $3\wr_detect$13[0:0]$11650 $2\wr_detect$13[0:0]$11649 + assign $3\wr_detect$13[0:0]$11701 $2\wr_detect$13[0:0]$11700 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11651 1'1 + assign $4\wr_detect$13[0:0]$11702 1'1 case - assign $4\wr_detect$13[0:0]$11651 $3\wr_detect$13[0:0]$11650 + assign $4\wr_detect$13[0:0]$11702 $3\wr_detect$13[0:0]$11701 end case - assign $1\wr_detect$13[0:0]$11648 1'0 + assign $1\wr_detect$13[0:0]$11699 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11647 + update \wr_detect$13 $0\wr_detect$13[0:0]$11698 end - connect \$9 $not$libresoc.v:178860$11570_Y - connect \$12 $not$libresoc.v:178861$11571_Y - connect \$1 $not$libresoc.v:178862$11572_Y - connect \$3 $not$libresoc.v:178863$11573_Y - connect \$6 $not$libresoc.v:178864$11574_Y + connect \$9 $not$libresoc.v:180956$11621_Y + connect \$12 $not$libresoc.v:180957$11622_Y + connect \$1 $not$libresoc.v:180958$11623_Y + connect \$3 $not$libresoc.v:180959$11624_Y + connect \$6 $not$libresoc.v:180960$11625_Y end -attribute \src "libresoc.v:179258.1-179316.10" +attribute \src "libresoc.v:181354.1-181412.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:179259.7-179259.20" + attribute \src "libresoc.v:181355.7-181355.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179304.3-179312.6" - wire width 5 $0\q_int$next[4:0]$11669 - attribute \src "libresoc.v:179302.3-179303.27" + attribute \src "libresoc.v:181400.3-181408.6" + wire width 5 $0\q_int$next[4:0]$11720 + attribute \src "libresoc.v:181398.3-181399.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:179304.3-179312.6" - wire width 5 $1\q_int$next[4:0]$11670 - attribute \src "libresoc.v:179281.13-179281.26" + attribute \src "libresoc.v:181400.3-181408.6" + wire width 5 $1\q_int$next[4:0]$11721 + attribute \src "libresoc.v:181377.13-181377.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:179294.17-179294.96" - wire width 5 $and$libresoc.v:179294$11659_Y - attribute \src "libresoc.v:179299.17-179299.96" - wire width 5 $and$libresoc.v:179299$11664_Y - attribute \src "libresoc.v:179296.18-179296.93" - wire width 5 $not$libresoc.v:179296$11661_Y - attribute \src "libresoc.v:179298.17-179298.92" - wire width 5 $not$libresoc.v:179298$11663_Y - attribute \src "libresoc.v:179301.17-179301.92" - wire width 5 $not$libresoc.v:179301$11666_Y - attribute \src "libresoc.v:179295.18-179295.98" - wire width 5 $or$libresoc.v:179295$11660_Y - attribute \src "libresoc.v:179297.18-179297.99" - wire width 5 $or$libresoc.v:179297$11662_Y - attribute \src "libresoc.v:179300.17-179300.97" - wire width 5 $or$libresoc.v:179300$11665_Y + attribute \src "libresoc.v:181390.17-181390.96" + wire width 5 $and$libresoc.v:181390$11710_Y + attribute \src "libresoc.v:181395.17-181395.96" + wire width 5 $and$libresoc.v:181395$11715_Y + attribute \src "libresoc.v:181392.18-181392.93" + wire width 5 $not$libresoc.v:181392$11712_Y + attribute \src "libresoc.v:181394.17-181394.92" + wire width 5 $not$libresoc.v:181394$11714_Y + attribute \src "libresoc.v:181397.17-181397.92" + wire width 5 $not$libresoc.v:181397$11717_Y + attribute \src "libresoc.v:181391.18-181391.98" + wire width 5 $or$libresoc.v:181391$11711_Y + attribute \src "libresoc.v:181393.18-181393.99" + wire width 5 $or$libresoc.v:181393$11713_Y + attribute \src "libresoc.v:181396.17-181396.97" + wire width 5 $or$libresoc.v:181396$11716_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -371312,11 +374183,11 @@ module \req_l wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179259.7-179259.15" + attribute \src "libresoc.v:181355.7-181355.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -371333,7 +374204,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179294$11659 + cell $and $and$libresoc.v:181390$11710 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371341,10 +374212,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179294$11659_Y + connect \Y $and$libresoc.v:181390$11710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179299$11664 + cell $and $and$libresoc.v:181395$11715 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371352,34 +374223,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179299$11664_Y + connect \Y $and$libresoc.v:181395$11715_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179296$11661 + cell $not $not$libresoc.v:181392$11712 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:179296$11661_Y + connect \Y $not$libresoc.v:181392$11712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179298$11663 + cell $not $not$libresoc.v:181394$11714 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:179298$11663_Y + connect \Y $not$libresoc.v:181394$11714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179301$11666 + cell $not $not$libresoc.v:181397$11717 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:179301$11666_Y + connect \Y $not$libresoc.v:181397$11717_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179295$11660 + cell $or $or$libresoc.v:181391$11711 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371387,10 +374258,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179295$11660_Y + connect \Y $or$libresoc.v:181391$11711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179297$11662 + cell $or $or$libresoc.v:181393$11713 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371398,10 +374269,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179297$11662_Y + connect \Y $or$libresoc.v:181393$11713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179300$11665 + cell $or $or$libresoc.v:181396$11716 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371409,39 +374280,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179300$11665_Y + connect \Y $or$libresoc.v:181396$11716_Y end - attribute \src "libresoc.v:179259.7-179259.20" - process $proc$libresoc.v:179259$11671 + attribute \src "libresoc.v:181355.7-181355.20" + process $proc$libresoc.v:181355$11722 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179281.13-179281.26" - process $proc$libresoc.v:179281$11672 + attribute \src "libresoc.v:181377.13-181377.26" + process $proc$libresoc.v:181377$11723 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:179302.3-179303.27" - process $proc$libresoc.v:179302$11667 + attribute \src "libresoc.v:181398.3-181399.27" + process $proc$libresoc.v:181398$11718 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:179304.3-179312.6" - process $proc$libresoc.v:179304$11668 + attribute \src "libresoc.v:181400.3-181408.6" + process $proc$libresoc.v:181400$11719 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11669 $1\q_int$next[4:0]$11670 - attribute \src "libresoc.v:179305.5-179305.29" + assign $0\q_int$next[4:0]$11720 $1\q_int$next[4:0]$11721 + attribute \src "libresoc.v:181401.5-181401.29" switch \initial - attribute \src "libresoc.v:179305.9-179305.17" + attribute \src "libresoc.v:181401.9-181401.17" case 1'1 case end @@ -371450,56 +374321,56 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11670 5'00000 + assign $1\q_int$next[4:0]$11721 5'00000 case - assign $1\q_int$next[4:0]$11670 \$5 + assign $1\q_int$next[4:0]$11721 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11669 + update \q_int$next $0\q_int$next[4:0]$11720 end - connect \$9 $and$libresoc.v:179294$11659_Y - connect \$11 $or$libresoc.v:179295$11660_Y - connect \$13 $not$libresoc.v:179296$11661_Y - connect \$15 $or$libresoc.v:179297$11662_Y - connect \$1 $not$libresoc.v:179298$11663_Y - connect \$3 $and$libresoc.v:179299$11664_Y - connect \$5 $or$libresoc.v:179300$11665_Y - connect \$7 $not$libresoc.v:179301$11666_Y + connect \$9 $and$libresoc.v:181390$11710_Y + connect \$11 $or$libresoc.v:181391$11711_Y + connect \$13 $not$libresoc.v:181392$11712_Y + connect \$15 $or$libresoc.v:181393$11713_Y + connect \$1 $not$libresoc.v:181394$11714_Y + connect \$3 $and$libresoc.v:181395$11715_Y + connect \$5 $or$libresoc.v:181396$11716_Y + connect \$7 $not$libresoc.v:181397$11717_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179320.1-179378.10" +attribute \src "libresoc.v:181416.1-181474.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:179321.7-179321.20" + attribute \src "libresoc.v:181417.7-181417.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179366.3-179374.6" - wire width 4 $0\q_int$next[3:0]$11683 - attribute \src "libresoc.v:179364.3-179365.27" + attribute \src "libresoc.v:181462.3-181470.6" + wire width 4 $0\q_int$next[3:0]$11734 + attribute \src "libresoc.v:181460.3-181461.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:179366.3-179374.6" - wire width 4 $1\q_int$next[3:0]$11684 - attribute \src "libresoc.v:179343.13-179343.25" + attribute \src "libresoc.v:181462.3-181470.6" + wire width 4 $1\q_int$next[3:0]$11735 + attribute \src "libresoc.v:181439.13-181439.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:179356.17-179356.96" - wire width 4 $and$libresoc.v:179356$11673_Y - attribute \src "libresoc.v:179361.17-179361.96" - wire width 4 $and$libresoc.v:179361$11678_Y - attribute \src "libresoc.v:179358.18-179358.93" - wire width 4 $not$libresoc.v:179358$11675_Y - attribute \src "libresoc.v:179360.17-179360.92" - wire width 4 $not$libresoc.v:179360$11677_Y - attribute \src "libresoc.v:179363.17-179363.92" - wire width 4 $not$libresoc.v:179363$11680_Y - attribute \src "libresoc.v:179357.18-179357.98" - wire width 4 $or$libresoc.v:179357$11674_Y - attribute \src "libresoc.v:179359.18-179359.99" - wire width 4 $or$libresoc.v:179359$11676_Y - attribute \src "libresoc.v:179362.17-179362.97" - wire width 4 $or$libresoc.v:179362$11679_Y + attribute \src "libresoc.v:181452.17-181452.96" + wire width 4 $and$libresoc.v:181452$11724_Y + attribute \src "libresoc.v:181457.17-181457.96" + wire width 4 $and$libresoc.v:181457$11729_Y + attribute \src "libresoc.v:181454.18-181454.93" + wire width 4 $not$libresoc.v:181454$11726_Y + attribute \src "libresoc.v:181456.17-181456.92" + wire width 4 $not$libresoc.v:181456$11728_Y + attribute \src "libresoc.v:181459.17-181459.92" + wire width 4 $not$libresoc.v:181459$11731_Y + attribute \src "libresoc.v:181453.18-181453.98" + wire width 4 $or$libresoc.v:181453$11725_Y + attribute \src "libresoc.v:181455.18-181455.99" + wire width 4 $or$libresoc.v:181455$11727_Y + attribute \src "libresoc.v:181458.17-181458.97" + wire width 4 $or$libresoc.v:181458$11730_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -371516,11 +374387,11 @@ module \req_l$103 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179321.7-179321.15" + attribute \src "libresoc.v:181417.7-181417.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -371537,7 +374408,7 @@ module \req_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179356$11673 + cell $and $and$libresoc.v:181452$11724 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371545,10 +374416,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179356$11673_Y + connect \Y $and$libresoc.v:181452$11724_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179361$11678 + cell $and $and$libresoc.v:181457$11729 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371556,34 +374427,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179361$11678_Y + connect \Y $and$libresoc.v:181457$11729_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179358$11675 + cell $not $not$libresoc.v:181454$11726 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:179358$11675_Y + connect \Y $not$libresoc.v:181454$11726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179360$11677 + cell $not $not$libresoc.v:181456$11728 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:179360$11677_Y + connect \Y $not$libresoc.v:181456$11728_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179363$11680 + cell $not $not$libresoc.v:181459$11731 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:179363$11680_Y + connect \Y $not$libresoc.v:181459$11731_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179357$11674 + cell $or $or$libresoc.v:181453$11725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371591,10 +374462,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179357$11674_Y + connect \Y $or$libresoc.v:181453$11725_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179359$11676 + cell $or $or$libresoc.v:181455$11727 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371602,10 +374473,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179359$11676_Y + connect \Y $or$libresoc.v:181455$11727_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179362$11679 + cell $or $or$libresoc.v:181458$11730 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371613,39 +374484,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179362$11679_Y + connect \Y $or$libresoc.v:181458$11730_Y end - attribute \src "libresoc.v:179321.7-179321.20" - process $proc$libresoc.v:179321$11685 + attribute \src "libresoc.v:181417.7-181417.20" + process $proc$libresoc.v:181417$11736 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179343.13-179343.25" - process $proc$libresoc.v:179343$11686 + attribute \src "libresoc.v:181439.13-181439.25" + process $proc$libresoc.v:181439$11737 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:179364.3-179365.27" - process $proc$libresoc.v:179364$11681 + attribute \src "libresoc.v:181460.3-181461.27" + process $proc$libresoc.v:181460$11732 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:179366.3-179374.6" - process $proc$libresoc.v:179366$11682 + attribute \src "libresoc.v:181462.3-181470.6" + process $proc$libresoc.v:181462$11733 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11683 $1\q_int$next[3:0]$11684 - attribute \src "libresoc.v:179367.5-179367.29" + assign $0\q_int$next[3:0]$11734 $1\q_int$next[3:0]$11735 + attribute \src "libresoc.v:181463.5-181463.29" switch \initial - attribute \src "libresoc.v:179367.9-179367.17" + attribute \src "libresoc.v:181463.9-181463.17" case 1'1 case end @@ -371654,56 +374525,56 @@ module \req_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11684 4'0000 + assign $1\q_int$next[3:0]$11735 4'0000 case - assign $1\q_int$next[3:0]$11684 \$5 + assign $1\q_int$next[3:0]$11735 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11683 + update \q_int$next $0\q_int$next[3:0]$11734 end - connect \$9 $and$libresoc.v:179356$11673_Y - connect \$11 $or$libresoc.v:179357$11674_Y - connect \$13 $not$libresoc.v:179358$11675_Y - connect \$15 $or$libresoc.v:179359$11676_Y - connect \$1 $not$libresoc.v:179360$11677_Y - connect \$3 $and$libresoc.v:179361$11678_Y - connect \$5 $or$libresoc.v:179362$11679_Y - connect \$7 $not$libresoc.v:179363$11680_Y + connect \$9 $and$libresoc.v:181452$11724_Y + connect \$11 $or$libresoc.v:181453$11725_Y + connect \$13 $not$libresoc.v:181454$11726_Y + connect \$15 $or$libresoc.v:181455$11727_Y + connect \$1 $not$libresoc.v:181456$11728_Y + connect \$3 $and$libresoc.v:181457$11729_Y + connect \$5 $or$libresoc.v:181458$11730_Y + connect \$7 $not$libresoc.v:181459$11731_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179382.1-179440.10" +attribute \src "libresoc.v:181478.1-181536.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:179383.7-179383.20" + attribute \src "libresoc.v:181479.7-181479.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179428.3-179436.6" - wire width 3 $0\q_int$next[2:0]$11697 - attribute \src "libresoc.v:179426.3-179427.27" + attribute \src "libresoc.v:181524.3-181532.6" + wire width 3 $0\q_int$next[2:0]$11748 + attribute \src "libresoc.v:181522.3-181523.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:179428.3-179436.6" - wire width 3 $1\q_int$next[2:0]$11698 - attribute \src "libresoc.v:179405.13-179405.25" + attribute \src "libresoc.v:181524.3-181532.6" + wire width 3 $1\q_int$next[2:0]$11749 + attribute \src "libresoc.v:181501.13-181501.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:179418.17-179418.96" - wire width 3 $and$libresoc.v:179418$11687_Y - attribute \src "libresoc.v:179423.17-179423.96" - wire width 3 $and$libresoc.v:179423$11692_Y - attribute \src "libresoc.v:179420.18-179420.93" - wire width 3 $not$libresoc.v:179420$11689_Y - attribute \src "libresoc.v:179422.17-179422.92" - wire width 3 $not$libresoc.v:179422$11691_Y - attribute \src "libresoc.v:179425.17-179425.92" - wire width 3 $not$libresoc.v:179425$11694_Y - attribute \src "libresoc.v:179419.18-179419.98" - wire width 3 $or$libresoc.v:179419$11688_Y - attribute \src "libresoc.v:179421.18-179421.99" - wire width 3 $or$libresoc.v:179421$11690_Y - attribute \src "libresoc.v:179424.17-179424.97" - wire width 3 $or$libresoc.v:179424$11693_Y + attribute \src "libresoc.v:181514.17-181514.96" + wire width 3 $and$libresoc.v:181514$11738_Y + attribute \src "libresoc.v:181519.17-181519.96" + wire width 3 $and$libresoc.v:181519$11743_Y + attribute \src "libresoc.v:181516.18-181516.93" + wire width 3 $not$libresoc.v:181516$11740_Y + attribute \src "libresoc.v:181518.17-181518.92" + wire width 3 $not$libresoc.v:181518$11742_Y + attribute \src "libresoc.v:181521.17-181521.92" + wire width 3 $not$libresoc.v:181521$11745_Y + attribute \src "libresoc.v:181515.18-181515.98" + wire width 3 $or$libresoc.v:181515$11739_Y + attribute \src "libresoc.v:181517.18-181517.99" + wire width 3 $or$libresoc.v:181517$11741_Y + attribute \src "libresoc.v:181520.17-181520.97" + wire width 3 $or$libresoc.v:181520$11744_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -371720,11 +374591,11 @@ module \req_l$12 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179383.7-179383.15" + attribute \src "libresoc.v:181479.7-181479.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -371741,7 +374612,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179418$11687 + cell $and $and$libresoc.v:181514$11738 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371749,10 +374620,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179418$11687_Y + connect \Y $and$libresoc.v:181514$11738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179423$11692 + cell $and $and$libresoc.v:181519$11743 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371760,34 +374631,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179423$11692_Y + connect \Y $and$libresoc.v:181519$11743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179420$11689 + cell $not $not$libresoc.v:181516$11740 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:179420$11689_Y + connect \Y $not$libresoc.v:181516$11740_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179422$11691 + cell $not $not$libresoc.v:181518$11742 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:179422$11691_Y + connect \Y $not$libresoc.v:181518$11742_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179425$11694 + cell $not $not$libresoc.v:181521$11745 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:179425$11694_Y + connect \Y $not$libresoc.v:181521$11745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179419$11688 + cell $or $or$libresoc.v:181515$11739 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371795,10 +374666,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179419$11688_Y + connect \Y $or$libresoc.v:181515$11739_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179421$11690 + cell $or $or$libresoc.v:181517$11741 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371806,10 +374677,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179421$11690_Y + connect \Y $or$libresoc.v:181517$11741_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179424$11693 + cell $or $or$libresoc.v:181520$11744 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371817,39 +374688,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179424$11693_Y + connect \Y $or$libresoc.v:181520$11744_Y end - attribute \src "libresoc.v:179383.7-179383.20" - process $proc$libresoc.v:179383$11699 + attribute \src "libresoc.v:181479.7-181479.20" + process $proc$libresoc.v:181479$11750 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179405.13-179405.25" - process $proc$libresoc.v:179405$11700 + attribute \src "libresoc.v:181501.13-181501.25" + process $proc$libresoc.v:181501$11751 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:179426.3-179427.27" - process $proc$libresoc.v:179426$11695 + attribute \src "libresoc.v:181522.3-181523.27" + process $proc$libresoc.v:181522$11746 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:179428.3-179436.6" - process $proc$libresoc.v:179428$11696 + attribute \src "libresoc.v:181524.3-181532.6" + process $proc$libresoc.v:181524$11747 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11697 $1\q_int$next[2:0]$11698 - attribute \src "libresoc.v:179429.5-179429.29" + assign $0\q_int$next[2:0]$11748 $1\q_int$next[2:0]$11749 + attribute \src "libresoc.v:181525.5-181525.29" switch \initial - attribute \src "libresoc.v:179429.9-179429.17" + attribute \src "libresoc.v:181525.9-181525.17" case 1'1 case end @@ -371858,56 +374729,56 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11698 3'000 + assign $1\q_int$next[2:0]$11749 3'000 case - assign $1\q_int$next[2:0]$11698 \$5 + assign $1\q_int$next[2:0]$11749 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11697 + update \q_int$next $0\q_int$next[2:0]$11748 end - connect \$9 $and$libresoc.v:179418$11687_Y - connect \$11 $or$libresoc.v:179419$11688_Y - connect \$13 $not$libresoc.v:179420$11689_Y - connect \$15 $or$libresoc.v:179421$11690_Y - connect \$1 $not$libresoc.v:179422$11691_Y - connect \$3 $and$libresoc.v:179423$11692_Y - connect \$5 $or$libresoc.v:179424$11693_Y - connect \$7 $not$libresoc.v:179425$11694_Y + connect \$9 $and$libresoc.v:181514$11738_Y + connect \$11 $or$libresoc.v:181515$11739_Y + connect \$13 $not$libresoc.v:181516$11740_Y + connect \$15 $or$libresoc.v:181517$11741_Y + connect \$1 $not$libresoc.v:181518$11742_Y + connect \$3 $and$libresoc.v:181519$11743_Y + connect \$5 $or$libresoc.v:181520$11744_Y + connect \$7 $not$libresoc.v:181521$11745_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179444.1-179502.10" +attribute \src "libresoc.v:181540.1-181598.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:179445.7-179445.20" + attribute \src "libresoc.v:181541.7-181541.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179490.3-179498.6" - wire width 3 $0\q_int$next[2:0]$11711 - attribute \src "libresoc.v:179488.3-179489.27" + attribute \src "libresoc.v:181586.3-181594.6" + wire width 3 $0\q_int$next[2:0]$11762 + attribute \src "libresoc.v:181584.3-181585.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:179490.3-179498.6" - wire width 3 $1\q_int$next[2:0]$11712 - attribute \src "libresoc.v:179467.13-179467.25" + attribute \src "libresoc.v:181586.3-181594.6" + wire width 3 $1\q_int$next[2:0]$11763 + attribute \src "libresoc.v:181563.13-181563.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:179480.17-179480.96" - wire width 3 $and$libresoc.v:179480$11701_Y - attribute \src "libresoc.v:179485.17-179485.96" - wire width 3 $and$libresoc.v:179485$11706_Y - attribute \src "libresoc.v:179482.18-179482.93" - wire width 3 $not$libresoc.v:179482$11703_Y - attribute \src "libresoc.v:179484.17-179484.92" - wire width 3 $not$libresoc.v:179484$11705_Y - attribute \src "libresoc.v:179487.17-179487.92" - wire width 3 $not$libresoc.v:179487$11708_Y - attribute \src "libresoc.v:179481.18-179481.98" - wire width 3 $or$libresoc.v:179481$11702_Y - attribute \src "libresoc.v:179483.18-179483.99" - wire width 3 $or$libresoc.v:179483$11704_Y - attribute \src "libresoc.v:179486.17-179486.97" - wire width 3 $or$libresoc.v:179486$11707_Y + attribute \src "libresoc.v:181576.17-181576.96" + wire width 3 $and$libresoc.v:181576$11752_Y + attribute \src "libresoc.v:181581.17-181581.96" + wire width 3 $and$libresoc.v:181581$11757_Y + attribute \src "libresoc.v:181578.18-181578.93" + wire width 3 $not$libresoc.v:181578$11754_Y + attribute \src "libresoc.v:181580.17-181580.92" + wire width 3 $not$libresoc.v:181580$11756_Y + attribute \src "libresoc.v:181583.17-181583.92" + wire width 3 $not$libresoc.v:181583$11759_Y + attribute \src "libresoc.v:181577.18-181577.98" + wire width 3 $or$libresoc.v:181577$11753_Y + attribute \src "libresoc.v:181579.18-181579.99" + wire width 3 $or$libresoc.v:181579$11755_Y + attribute \src "libresoc.v:181582.17-181582.97" + wire width 3 $or$libresoc.v:181582$11758_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -371924,11 +374795,11 @@ module \req_l$121 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179445.7-179445.15" + attribute \src "libresoc.v:181541.7-181541.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -371945,7 +374816,7 @@ module \req_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179480$11701 + cell $and $and$libresoc.v:181576$11752 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371953,10 +374824,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179480$11701_Y + connect \Y $and$libresoc.v:181576$11752_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179485$11706 + cell $and $and$libresoc.v:181581$11757 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371964,34 +374835,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179485$11706_Y + connect \Y $and$libresoc.v:181581$11757_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179482$11703 + cell $not $not$libresoc.v:181578$11754 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:179482$11703_Y + connect \Y $not$libresoc.v:181578$11754_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179484$11705 + cell $not $not$libresoc.v:181580$11756 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:179484$11705_Y + connect \Y $not$libresoc.v:181580$11756_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179487$11708 + cell $not $not$libresoc.v:181583$11759 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:179487$11708_Y + connect \Y $not$libresoc.v:181583$11759_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179481$11702 + cell $or $or$libresoc.v:181577$11753 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371999,10 +374870,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179481$11702_Y + connect \Y $or$libresoc.v:181577$11753_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179483$11704 + cell $or $or$libresoc.v:181579$11755 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372010,10 +374881,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179483$11704_Y + connect \Y $or$libresoc.v:181579$11755_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179486$11707 + cell $or $or$libresoc.v:181582$11758 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372021,39 +374892,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179486$11707_Y + connect \Y $or$libresoc.v:181582$11758_Y end - attribute \src "libresoc.v:179445.7-179445.20" - process $proc$libresoc.v:179445$11713 + attribute \src "libresoc.v:181541.7-181541.20" + process $proc$libresoc.v:181541$11764 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179467.13-179467.25" - process $proc$libresoc.v:179467$11714 + attribute \src "libresoc.v:181563.13-181563.25" + process $proc$libresoc.v:181563$11765 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:179488.3-179489.27" - process $proc$libresoc.v:179488$11709 + attribute \src "libresoc.v:181584.3-181585.27" + process $proc$libresoc.v:181584$11760 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:179490.3-179498.6" - process $proc$libresoc.v:179490$11710 + attribute \src "libresoc.v:181586.3-181594.6" + process $proc$libresoc.v:181586$11761 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11711 $1\q_int$next[2:0]$11712 - attribute \src "libresoc.v:179491.5-179491.29" + assign $0\q_int$next[2:0]$11762 $1\q_int$next[2:0]$11763 + attribute \src "libresoc.v:181587.5-181587.29" switch \initial - attribute \src "libresoc.v:179491.9-179491.17" + attribute \src "libresoc.v:181587.9-181587.17" case 1'1 case end @@ -372062,56 +374933,56 @@ module \req_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11712 3'000 + assign $1\q_int$next[2:0]$11763 3'000 case - assign $1\q_int$next[2:0]$11712 \$5 + assign $1\q_int$next[2:0]$11763 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11711 + update \q_int$next $0\q_int$next[2:0]$11762 end - connect \$9 $and$libresoc.v:179480$11701_Y - connect \$11 $or$libresoc.v:179481$11702_Y - connect \$13 $not$libresoc.v:179482$11703_Y - connect \$15 $or$libresoc.v:179483$11704_Y - connect \$1 $not$libresoc.v:179484$11705_Y - connect \$3 $and$libresoc.v:179485$11706_Y - connect \$5 $or$libresoc.v:179486$11707_Y - connect \$7 $not$libresoc.v:179487$11708_Y + connect \$9 $and$libresoc.v:181576$11752_Y + connect \$11 $or$libresoc.v:181577$11753_Y + connect \$13 $not$libresoc.v:181578$11754_Y + connect \$15 $or$libresoc.v:181579$11755_Y + connect \$1 $not$libresoc.v:181580$11756_Y + connect \$3 $and$libresoc.v:181581$11757_Y + connect \$5 $or$libresoc.v:181582$11758_Y + connect \$7 $not$libresoc.v:181583$11759_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179506.1-179564.10" +attribute \src "libresoc.v:181602.1-181660.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:179507.7-179507.20" + attribute \src "libresoc.v:181603.7-181603.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179552.3-179560.6" - wire width 3 $0\q_int$next[2:0]$11725 - attribute \src "libresoc.v:179550.3-179551.27" + attribute \src "libresoc.v:181648.3-181656.6" + wire width 3 $0\q_int$next[2:0]$11776 + attribute \src "libresoc.v:181646.3-181647.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:179552.3-179560.6" - wire width 3 $1\q_int$next[2:0]$11726 - attribute \src "libresoc.v:179529.13-179529.25" + attribute \src "libresoc.v:181648.3-181656.6" + wire width 3 $1\q_int$next[2:0]$11777 + attribute \src "libresoc.v:181625.13-181625.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:179542.17-179542.96" - wire width 3 $and$libresoc.v:179542$11715_Y - attribute \src "libresoc.v:179547.17-179547.96" - wire width 3 $and$libresoc.v:179547$11720_Y - attribute \src "libresoc.v:179544.18-179544.93" - wire width 3 $not$libresoc.v:179544$11717_Y - attribute \src "libresoc.v:179546.17-179546.92" - wire width 3 $not$libresoc.v:179546$11719_Y - attribute \src "libresoc.v:179549.17-179549.92" - wire width 3 $not$libresoc.v:179549$11722_Y - attribute \src "libresoc.v:179543.18-179543.98" - wire width 3 $or$libresoc.v:179543$11716_Y - attribute \src "libresoc.v:179545.18-179545.99" - wire width 3 $or$libresoc.v:179545$11718_Y - attribute \src "libresoc.v:179548.17-179548.97" - wire width 3 $or$libresoc.v:179548$11721_Y + attribute \src "libresoc.v:181638.17-181638.96" + wire width 3 $and$libresoc.v:181638$11766_Y + attribute \src "libresoc.v:181643.17-181643.96" + wire width 3 $and$libresoc.v:181643$11771_Y + attribute \src "libresoc.v:181640.18-181640.93" + wire width 3 $not$libresoc.v:181640$11768_Y + attribute \src "libresoc.v:181642.17-181642.92" + wire width 3 $not$libresoc.v:181642$11770_Y + attribute \src "libresoc.v:181645.17-181645.92" + wire width 3 $not$libresoc.v:181645$11773_Y + attribute \src "libresoc.v:181639.18-181639.98" + wire width 3 $or$libresoc.v:181639$11767_Y + attribute \src "libresoc.v:181641.18-181641.99" + wire width 3 $or$libresoc.v:181641$11769_Y + attribute \src "libresoc.v:181644.17-181644.97" + wire width 3 $or$libresoc.v:181644$11772_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -372128,11 +374999,11 @@ module \req_l$25 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179507.7-179507.15" + attribute \src "libresoc.v:181603.7-181603.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -372149,7 +375020,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179542$11715 + cell $and $and$libresoc.v:181638$11766 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372157,10 +375028,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179542$11715_Y + connect \Y $and$libresoc.v:181638$11766_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179547$11720 + cell $and $and$libresoc.v:181643$11771 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372168,34 +375039,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179547$11720_Y + connect \Y $and$libresoc.v:181643$11771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179544$11717 + cell $not $not$libresoc.v:181640$11768 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:179544$11717_Y + connect \Y $not$libresoc.v:181640$11768_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179546$11719 + cell $not $not$libresoc.v:181642$11770 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:179546$11719_Y + connect \Y $not$libresoc.v:181642$11770_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179549$11722 + cell $not $not$libresoc.v:181645$11773 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:179549$11722_Y + connect \Y $not$libresoc.v:181645$11773_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179543$11716 + cell $or $or$libresoc.v:181639$11767 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372203,10 +375074,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179543$11716_Y + connect \Y $or$libresoc.v:181639$11767_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179545$11718 + cell $or $or$libresoc.v:181641$11769 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372214,10 +375085,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179545$11718_Y + connect \Y $or$libresoc.v:181641$11769_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179548$11721 + cell $or $or$libresoc.v:181644$11772 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372225,39 +375096,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179548$11721_Y + connect \Y $or$libresoc.v:181644$11772_Y end - attribute \src "libresoc.v:179507.7-179507.20" - process $proc$libresoc.v:179507$11727 + attribute \src "libresoc.v:181603.7-181603.20" + process $proc$libresoc.v:181603$11778 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179529.13-179529.25" - process $proc$libresoc.v:179529$11728 + attribute \src "libresoc.v:181625.13-181625.25" + process $proc$libresoc.v:181625$11779 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:179550.3-179551.27" - process $proc$libresoc.v:179550$11723 + attribute \src "libresoc.v:181646.3-181647.27" + process $proc$libresoc.v:181646$11774 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:179552.3-179560.6" - process $proc$libresoc.v:179552$11724 + attribute \src "libresoc.v:181648.3-181656.6" + process $proc$libresoc.v:181648$11775 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11725 $1\q_int$next[2:0]$11726 - attribute \src "libresoc.v:179553.5-179553.29" + assign $0\q_int$next[2:0]$11776 $1\q_int$next[2:0]$11777 + attribute \src "libresoc.v:181649.5-181649.29" switch \initial - attribute \src "libresoc.v:179553.9-179553.17" + attribute \src "libresoc.v:181649.9-181649.17" case 1'1 case end @@ -372266,56 +375137,56 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11726 3'000 + assign $1\q_int$next[2:0]$11777 3'000 case - assign $1\q_int$next[2:0]$11726 \$5 + assign $1\q_int$next[2:0]$11777 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11725 + update \q_int$next $0\q_int$next[2:0]$11776 end - connect \$9 $and$libresoc.v:179542$11715_Y - connect \$11 $or$libresoc.v:179543$11716_Y - connect \$13 $not$libresoc.v:179544$11717_Y - connect \$15 $or$libresoc.v:179545$11718_Y - connect \$1 $not$libresoc.v:179546$11719_Y - connect \$3 $and$libresoc.v:179547$11720_Y - connect \$5 $or$libresoc.v:179548$11721_Y - connect \$7 $not$libresoc.v:179549$11722_Y + connect \$9 $and$libresoc.v:181638$11766_Y + connect \$11 $or$libresoc.v:181639$11767_Y + connect \$13 $not$libresoc.v:181640$11768_Y + connect \$15 $or$libresoc.v:181641$11769_Y + connect \$1 $not$libresoc.v:181642$11770_Y + connect \$3 $and$libresoc.v:181643$11771_Y + connect \$5 $or$libresoc.v:181644$11772_Y + connect \$7 $not$libresoc.v:181645$11773_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179568.1-179626.10" +attribute \src "libresoc.v:181664.1-181722.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:179569.7-179569.20" + attribute \src "libresoc.v:181665.7-181665.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179614.3-179622.6" - wire width 5 $0\q_int$next[4:0]$11739 - attribute \src "libresoc.v:179612.3-179613.27" + attribute \src "libresoc.v:181710.3-181718.6" + wire width 5 $0\q_int$next[4:0]$11790 + attribute \src "libresoc.v:181708.3-181709.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:179614.3-179622.6" - wire width 5 $1\q_int$next[4:0]$11740 - attribute \src "libresoc.v:179591.13-179591.26" + attribute \src "libresoc.v:181710.3-181718.6" + wire width 5 $1\q_int$next[4:0]$11791 + attribute \src "libresoc.v:181687.13-181687.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:179604.17-179604.96" - wire width 5 $and$libresoc.v:179604$11729_Y - attribute \src "libresoc.v:179609.17-179609.96" - wire width 5 $and$libresoc.v:179609$11734_Y - attribute \src "libresoc.v:179606.18-179606.93" - wire width 5 $not$libresoc.v:179606$11731_Y - attribute \src "libresoc.v:179608.17-179608.92" - wire width 5 $not$libresoc.v:179608$11733_Y - attribute \src "libresoc.v:179611.17-179611.92" - wire width 5 $not$libresoc.v:179611$11736_Y - attribute \src "libresoc.v:179605.18-179605.98" - wire width 5 $or$libresoc.v:179605$11730_Y - attribute \src "libresoc.v:179607.18-179607.99" - wire width 5 $or$libresoc.v:179607$11732_Y - attribute \src "libresoc.v:179610.17-179610.97" - wire width 5 $or$libresoc.v:179610$11735_Y + attribute \src "libresoc.v:181700.17-181700.96" + wire width 5 $and$libresoc.v:181700$11780_Y + attribute \src "libresoc.v:181705.17-181705.96" + wire width 5 $and$libresoc.v:181705$11785_Y + attribute \src "libresoc.v:181702.18-181702.93" + wire width 5 $not$libresoc.v:181702$11782_Y + attribute \src "libresoc.v:181704.17-181704.92" + wire width 5 $not$libresoc.v:181704$11784_Y + attribute \src "libresoc.v:181707.17-181707.92" + wire width 5 $not$libresoc.v:181707$11787_Y + attribute \src "libresoc.v:181701.18-181701.98" + wire width 5 $or$libresoc.v:181701$11781_Y + attribute \src "libresoc.v:181703.18-181703.99" + wire width 5 $or$libresoc.v:181703$11783_Y + attribute \src "libresoc.v:181706.17-181706.97" + wire width 5 $or$libresoc.v:181706$11786_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -372332,11 +375203,11 @@ module \req_l$41 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179569.7-179569.15" + attribute \src "libresoc.v:181665.7-181665.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -372353,7 +375224,7 @@ module \req_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179604$11729 + cell $and $and$libresoc.v:181700$11780 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -372361,10 +375232,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179604$11729_Y + connect \Y $and$libresoc.v:181700$11780_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179609$11734 + cell $and $and$libresoc.v:181705$11785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -372372,34 +375243,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179609$11734_Y + connect \Y $and$libresoc.v:181705$11785_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179606$11731 + cell $not $not$libresoc.v:181702$11782 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:179606$11731_Y + connect \Y $not$libresoc.v:181702$11782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179608$11733 + cell $not $not$libresoc.v:181704$11784 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:179608$11733_Y + connect \Y $not$libresoc.v:181704$11784_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179611$11736 + cell $not $not$libresoc.v:181707$11787 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:179611$11736_Y + connect \Y $not$libresoc.v:181707$11787_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179605$11730 + cell $or $or$libresoc.v:181701$11781 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -372407,10 +375278,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179605$11730_Y + connect \Y $or$libresoc.v:181701$11781_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179607$11732 + cell $or $or$libresoc.v:181703$11783 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -372418,10 +375289,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179607$11732_Y + connect \Y $or$libresoc.v:181703$11783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179610$11735 + cell $or $or$libresoc.v:181706$11786 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -372429,39 +375300,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179610$11735_Y + connect \Y $or$libresoc.v:181706$11786_Y end - attribute \src "libresoc.v:179569.7-179569.20" - process $proc$libresoc.v:179569$11741 + attribute \src "libresoc.v:181665.7-181665.20" + process $proc$libresoc.v:181665$11792 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179591.13-179591.26" - process $proc$libresoc.v:179591$11742 + attribute \src "libresoc.v:181687.13-181687.26" + process $proc$libresoc.v:181687$11793 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:179612.3-179613.27" - process $proc$libresoc.v:179612$11737 + attribute \src "libresoc.v:181708.3-181709.27" + process $proc$libresoc.v:181708$11788 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:179614.3-179622.6" - process $proc$libresoc.v:179614$11738 + attribute \src "libresoc.v:181710.3-181718.6" + process $proc$libresoc.v:181710$11789 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11739 $1\q_int$next[4:0]$11740 - attribute \src "libresoc.v:179615.5-179615.29" + assign $0\q_int$next[4:0]$11790 $1\q_int$next[4:0]$11791 + attribute \src "libresoc.v:181711.5-181711.29" switch \initial - attribute \src "libresoc.v:179615.9-179615.17" + attribute \src "libresoc.v:181711.9-181711.17" case 1'1 case end @@ -372470,56 +375341,56 @@ module \req_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11740 5'00000 + assign $1\q_int$next[4:0]$11791 5'00000 case - assign $1\q_int$next[4:0]$11740 \$5 + assign $1\q_int$next[4:0]$11791 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11739 + update \q_int$next $0\q_int$next[4:0]$11790 end - connect \$9 $and$libresoc.v:179604$11729_Y - connect \$11 $or$libresoc.v:179605$11730_Y - connect \$13 $not$libresoc.v:179606$11731_Y - connect \$15 $or$libresoc.v:179607$11732_Y - connect \$1 $not$libresoc.v:179608$11733_Y - connect \$3 $and$libresoc.v:179609$11734_Y - connect \$5 $or$libresoc.v:179610$11735_Y - connect \$7 $not$libresoc.v:179611$11736_Y + connect \$9 $and$libresoc.v:181700$11780_Y + connect \$11 $or$libresoc.v:181701$11781_Y + connect \$13 $not$libresoc.v:181702$11782_Y + connect \$15 $or$libresoc.v:181703$11783_Y + connect \$1 $not$libresoc.v:181704$11784_Y + connect \$3 $and$libresoc.v:181705$11785_Y + connect \$5 $or$libresoc.v:181706$11786_Y + connect \$7 $not$libresoc.v:181707$11787_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179630.1-179688.10" +attribute \src "libresoc.v:181726.1-181784.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:179631.7-179631.20" + attribute \src "libresoc.v:181727.7-181727.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179676.3-179684.6" - wire width 2 $0\q_int$next[1:0]$11753 - attribute \src "libresoc.v:179674.3-179675.27" + attribute \src "libresoc.v:181772.3-181780.6" + wire width 2 $0\q_int$next[1:0]$11804 + attribute \src "libresoc.v:181770.3-181771.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:179676.3-179684.6" - wire width 2 $1\q_int$next[1:0]$11754 - attribute \src "libresoc.v:179653.13-179653.25" + attribute \src "libresoc.v:181772.3-181780.6" + wire width 2 $1\q_int$next[1:0]$11805 + attribute \src "libresoc.v:181749.13-181749.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:179666.17-179666.96" - wire width 2 $and$libresoc.v:179666$11743_Y - attribute \src "libresoc.v:179671.17-179671.96" - wire width 2 $and$libresoc.v:179671$11748_Y - attribute \src "libresoc.v:179668.18-179668.93" - wire width 2 $not$libresoc.v:179668$11745_Y - attribute \src "libresoc.v:179670.17-179670.92" - wire width 2 $not$libresoc.v:179670$11747_Y - attribute \src "libresoc.v:179673.17-179673.92" - wire width 2 $not$libresoc.v:179673$11750_Y - attribute \src "libresoc.v:179667.18-179667.98" - wire width 2 $or$libresoc.v:179667$11744_Y - attribute \src "libresoc.v:179669.18-179669.99" - wire width 2 $or$libresoc.v:179669$11746_Y - attribute \src "libresoc.v:179672.17-179672.97" - wire width 2 $or$libresoc.v:179672$11749_Y + attribute \src "libresoc.v:181762.17-181762.96" + wire width 2 $and$libresoc.v:181762$11794_Y + attribute \src "libresoc.v:181767.17-181767.96" + wire width 2 $and$libresoc.v:181767$11799_Y + attribute \src "libresoc.v:181764.18-181764.93" + wire width 2 $not$libresoc.v:181764$11796_Y + attribute \src "libresoc.v:181766.17-181766.92" + wire width 2 $not$libresoc.v:181766$11798_Y + attribute \src "libresoc.v:181769.17-181769.92" + wire width 2 $not$libresoc.v:181769$11801_Y + attribute \src "libresoc.v:181763.18-181763.98" + wire width 2 $or$libresoc.v:181763$11795_Y + attribute \src "libresoc.v:181765.18-181765.99" + wire width 2 $or$libresoc.v:181765$11797_Y + attribute \src "libresoc.v:181768.17-181768.97" + wire width 2 $or$libresoc.v:181768$11800_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -372536,11 +375407,11 @@ module \req_l$57 wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179631.7-179631.15" + attribute \src "libresoc.v:181727.7-181727.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int @@ -372557,7 +375428,7 @@ module \req_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179666$11743 + cell $and $and$libresoc.v:181762$11794 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -372565,10 +375436,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179666$11743_Y + connect \Y $and$libresoc.v:181762$11794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179671$11748 + cell $and $and$libresoc.v:181767$11799 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -372576,34 +375447,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179671$11748_Y + connect \Y $and$libresoc.v:181767$11799_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179668$11745 + cell $not $not$libresoc.v:181764$11796 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:179668$11745_Y + connect \Y $not$libresoc.v:181764$11796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179670$11747 + cell $not $not$libresoc.v:181766$11798 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:179670$11747_Y + connect \Y $not$libresoc.v:181766$11798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179673$11750 + cell $not $not$libresoc.v:181769$11801 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:179673$11750_Y + connect \Y $not$libresoc.v:181769$11801_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179667$11744 + cell $or $or$libresoc.v:181763$11795 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -372611,10 +375482,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179667$11744_Y + connect \Y $or$libresoc.v:181763$11795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179669$11746 + cell $or $or$libresoc.v:181765$11797 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -372622,10 +375493,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179669$11746_Y + connect \Y $or$libresoc.v:181765$11797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179672$11749 + cell $or $or$libresoc.v:181768$11800 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -372633,39 +375504,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179672$11749_Y + connect \Y $or$libresoc.v:181768$11800_Y end - attribute \src "libresoc.v:179631.7-179631.20" - process $proc$libresoc.v:179631$11755 + attribute \src "libresoc.v:181727.7-181727.20" + process $proc$libresoc.v:181727$11806 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179653.13-179653.25" - process $proc$libresoc.v:179653$11756 + attribute \src "libresoc.v:181749.13-181749.25" + process $proc$libresoc.v:181749$11807 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:179674.3-179675.27" - process $proc$libresoc.v:179674$11751 + attribute \src "libresoc.v:181770.3-181771.27" + process $proc$libresoc.v:181770$11802 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:179676.3-179684.6" - process $proc$libresoc.v:179676$11752 + attribute \src "libresoc.v:181772.3-181780.6" + process $proc$libresoc.v:181772$11803 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11753 $1\q_int$next[1:0]$11754 - attribute \src "libresoc.v:179677.5-179677.29" + assign $0\q_int$next[1:0]$11804 $1\q_int$next[1:0]$11805 + attribute \src "libresoc.v:181773.5-181773.29" switch \initial - attribute \src "libresoc.v:179677.9-179677.17" + attribute \src "libresoc.v:181773.9-181773.17" case 1'1 case end @@ -372674,56 +375545,56 @@ module \req_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$11754 2'00 + assign $1\q_int$next[1:0]$11805 2'00 case - assign $1\q_int$next[1:0]$11754 \$5 + assign $1\q_int$next[1:0]$11805 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$11753 + update \q_int$next $0\q_int$next[1:0]$11804 end - connect \$9 $and$libresoc.v:179666$11743_Y - connect \$11 $or$libresoc.v:179667$11744_Y - connect \$13 $not$libresoc.v:179668$11745_Y - connect \$15 $or$libresoc.v:179669$11746_Y - connect \$1 $not$libresoc.v:179670$11747_Y - connect \$3 $and$libresoc.v:179671$11748_Y - connect \$5 $or$libresoc.v:179672$11749_Y - connect \$7 $not$libresoc.v:179673$11750_Y + connect \$9 $and$libresoc.v:181762$11794_Y + connect \$11 $or$libresoc.v:181763$11795_Y + connect \$13 $not$libresoc.v:181764$11796_Y + connect \$15 $or$libresoc.v:181765$11797_Y + connect \$1 $not$libresoc.v:181766$11798_Y + connect \$3 $and$libresoc.v:181767$11799_Y + connect \$5 $or$libresoc.v:181768$11800_Y + connect \$7 $not$libresoc.v:181769$11801_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179692.1-179750.10" +attribute \src "libresoc.v:181788.1-181846.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:179693.7-179693.20" + attribute \src "libresoc.v:181789.7-181789.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179738.3-179746.6" - wire width 6 $0\q_int$next[5:0]$11767 - attribute \src "libresoc.v:179736.3-179737.27" + attribute \src "libresoc.v:181834.3-181842.6" + wire width 6 $0\q_int$next[5:0]$11818 + attribute \src "libresoc.v:181832.3-181833.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:179738.3-179746.6" - wire width 6 $1\q_int$next[5:0]$11768 - attribute \src "libresoc.v:179715.13-179715.26" + attribute \src "libresoc.v:181834.3-181842.6" + wire width 6 $1\q_int$next[5:0]$11819 + attribute \src "libresoc.v:181811.13-181811.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:179728.17-179728.96" - wire width 6 $and$libresoc.v:179728$11757_Y - attribute \src "libresoc.v:179733.17-179733.96" - wire width 6 $and$libresoc.v:179733$11762_Y - attribute \src "libresoc.v:179730.18-179730.93" - wire width 6 $not$libresoc.v:179730$11759_Y - attribute \src "libresoc.v:179732.17-179732.92" - wire width 6 $not$libresoc.v:179732$11761_Y - attribute \src "libresoc.v:179735.17-179735.92" - wire width 6 $not$libresoc.v:179735$11764_Y - attribute \src "libresoc.v:179729.18-179729.98" - wire width 6 $or$libresoc.v:179729$11758_Y - attribute \src "libresoc.v:179731.18-179731.99" - wire width 6 $or$libresoc.v:179731$11760_Y - attribute \src "libresoc.v:179734.17-179734.97" - wire width 6 $or$libresoc.v:179734$11763_Y + attribute \src "libresoc.v:181824.17-181824.96" + wire width 6 $and$libresoc.v:181824$11808_Y + attribute \src "libresoc.v:181829.17-181829.96" + wire width 6 $and$libresoc.v:181829$11813_Y + attribute \src "libresoc.v:181826.18-181826.93" + wire width 6 $not$libresoc.v:181826$11810_Y + attribute \src "libresoc.v:181828.17-181828.92" + wire width 6 $not$libresoc.v:181828$11812_Y + attribute \src "libresoc.v:181831.17-181831.92" + wire width 6 $not$libresoc.v:181831$11815_Y + attribute \src "libresoc.v:181825.18-181825.98" + wire width 6 $or$libresoc.v:181825$11809_Y + attribute \src "libresoc.v:181827.18-181827.99" + wire width 6 $or$libresoc.v:181827$11811_Y + attribute \src "libresoc.v:181830.17-181830.97" + wire width 6 $or$libresoc.v:181830$11814_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -372740,11 +375611,11 @@ module \req_l$69 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179693.7-179693.15" + attribute \src "libresoc.v:181789.7-181789.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -372761,7 +375632,7 @@ module \req_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179728$11757 + cell $and $and$libresoc.v:181824$11808 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -372769,10 +375640,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179728$11757_Y + connect \Y $and$libresoc.v:181824$11808_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179733$11762 + cell $and $and$libresoc.v:181829$11813 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -372780,34 +375651,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179733$11762_Y + connect \Y $and$libresoc.v:181829$11813_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179730$11759 + cell $not $not$libresoc.v:181826$11810 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:179730$11759_Y + connect \Y $not$libresoc.v:181826$11810_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179732$11761 + cell $not $not$libresoc.v:181828$11812 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:179732$11761_Y + connect \Y $not$libresoc.v:181828$11812_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179735$11764 + cell $not $not$libresoc.v:181831$11815 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:179735$11764_Y + connect \Y $not$libresoc.v:181831$11815_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179729$11758 + cell $or $or$libresoc.v:181825$11809 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -372815,10 +375686,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179729$11758_Y + connect \Y $or$libresoc.v:181825$11809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179731$11760 + cell $or $or$libresoc.v:181827$11811 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -372826,10 +375697,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179731$11760_Y + connect \Y $or$libresoc.v:181827$11811_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179734$11763 + cell $or $or$libresoc.v:181830$11814 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -372837,39 +375708,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179734$11763_Y + connect \Y $or$libresoc.v:181830$11814_Y end - attribute \src "libresoc.v:179693.7-179693.20" - process $proc$libresoc.v:179693$11769 + attribute \src "libresoc.v:181789.7-181789.20" + process $proc$libresoc.v:181789$11820 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179715.13-179715.26" - process $proc$libresoc.v:179715$11770 + attribute \src "libresoc.v:181811.13-181811.26" + process $proc$libresoc.v:181811$11821 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:179736.3-179737.27" - process $proc$libresoc.v:179736$11765 + attribute \src "libresoc.v:181832.3-181833.27" + process $proc$libresoc.v:181832$11816 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:179738.3-179746.6" - process $proc$libresoc.v:179738$11766 + attribute \src "libresoc.v:181834.3-181842.6" + process $proc$libresoc.v:181834$11817 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$11767 $1\q_int$next[5:0]$11768 - attribute \src "libresoc.v:179739.5-179739.29" + assign $0\q_int$next[5:0]$11818 $1\q_int$next[5:0]$11819 + attribute \src "libresoc.v:181835.5-181835.29" switch \initial - attribute \src "libresoc.v:179739.9-179739.17" + attribute \src "libresoc.v:181835.9-181835.17" case 1'1 case end @@ -372878,56 +375749,56 @@ module \req_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$11768 6'000000 + assign $1\q_int$next[5:0]$11819 6'000000 case - assign $1\q_int$next[5:0]$11768 \$5 + assign $1\q_int$next[5:0]$11819 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$11767 + update \q_int$next $0\q_int$next[5:0]$11818 end - connect \$9 $and$libresoc.v:179728$11757_Y - connect \$11 $or$libresoc.v:179729$11758_Y - connect \$13 $not$libresoc.v:179730$11759_Y - connect \$15 $or$libresoc.v:179731$11760_Y - connect \$1 $not$libresoc.v:179732$11761_Y - connect \$3 $and$libresoc.v:179733$11762_Y - connect \$5 $or$libresoc.v:179734$11763_Y - connect \$7 $not$libresoc.v:179735$11764_Y + connect \$9 $and$libresoc.v:181824$11808_Y + connect \$11 $or$libresoc.v:181825$11809_Y + connect \$13 $not$libresoc.v:181826$11810_Y + connect \$15 $or$libresoc.v:181827$11811_Y + connect \$1 $not$libresoc.v:181828$11812_Y + connect \$3 $and$libresoc.v:181829$11813_Y + connect \$5 $or$libresoc.v:181830$11814_Y + connect \$7 $not$libresoc.v:181831$11815_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179754.1-179812.10" +attribute \src "libresoc.v:181850.1-181908.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:179755.7-179755.20" + attribute \src "libresoc.v:181851.7-181851.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179800.3-179808.6" - wire width 4 $0\q_int$next[3:0]$11781 - attribute \src "libresoc.v:179798.3-179799.27" + attribute \src "libresoc.v:181896.3-181904.6" + wire width 4 $0\q_int$next[3:0]$11832 + attribute \src "libresoc.v:181894.3-181895.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:179800.3-179808.6" - wire width 4 $1\q_int$next[3:0]$11782 - attribute \src "libresoc.v:179777.13-179777.25" + attribute \src "libresoc.v:181896.3-181904.6" + wire width 4 $1\q_int$next[3:0]$11833 + attribute \src "libresoc.v:181873.13-181873.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:179790.17-179790.96" - wire width 4 $and$libresoc.v:179790$11771_Y - attribute \src "libresoc.v:179795.17-179795.96" - wire width 4 $and$libresoc.v:179795$11776_Y - attribute \src "libresoc.v:179792.18-179792.93" - wire width 4 $not$libresoc.v:179792$11773_Y - attribute \src "libresoc.v:179794.17-179794.92" - wire width 4 $not$libresoc.v:179794$11775_Y - attribute \src "libresoc.v:179797.17-179797.92" - wire width 4 $not$libresoc.v:179797$11778_Y - attribute \src "libresoc.v:179791.18-179791.98" - wire width 4 $or$libresoc.v:179791$11772_Y - attribute \src "libresoc.v:179793.18-179793.99" - wire width 4 $or$libresoc.v:179793$11774_Y - attribute \src "libresoc.v:179796.17-179796.97" - wire width 4 $or$libresoc.v:179796$11777_Y + attribute \src "libresoc.v:181886.17-181886.96" + wire width 4 $and$libresoc.v:181886$11822_Y + attribute \src "libresoc.v:181891.17-181891.96" + wire width 4 $and$libresoc.v:181891$11827_Y + attribute \src "libresoc.v:181888.18-181888.93" + wire width 4 $not$libresoc.v:181888$11824_Y + attribute \src "libresoc.v:181890.17-181890.92" + wire width 4 $not$libresoc.v:181890$11826_Y + attribute \src "libresoc.v:181893.17-181893.92" + wire width 4 $not$libresoc.v:181893$11829_Y + attribute \src "libresoc.v:181887.18-181887.98" + wire width 4 $or$libresoc.v:181887$11823_Y + attribute \src "libresoc.v:181889.18-181889.99" + wire width 4 $or$libresoc.v:181889$11825_Y + attribute \src "libresoc.v:181892.17-181892.97" + wire width 4 $or$libresoc.v:181892$11828_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -372944,11 +375815,11 @@ module \req_l$86 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179755.7-179755.15" + attribute \src "libresoc.v:181851.7-181851.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -372965,7 +375836,7 @@ module \req_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:179790$11771 + cell $and $and$libresoc.v:181886$11822 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -372973,10 +375844,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:179790$11771_Y + connect \Y $and$libresoc.v:181886$11822_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179795$11776 + cell $and $and$libresoc.v:181891$11827 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -372984,34 +375855,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179795$11776_Y + connect \Y $and$libresoc.v:181891$11827_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179792$11773 + cell $not $not$libresoc.v:181888$11824 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:179792$11773_Y + connect \Y $not$libresoc.v:181888$11824_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179794$11775 + cell $not $not$libresoc.v:181890$11826 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:179794$11775_Y + connect \Y $not$libresoc.v:181890$11826_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:179797$11778 + cell $not $not$libresoc.v:181893$11829 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:179797$11778_Y + connect \Y $not$libresoc.v:181893$11829_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:179791$11772 + cell $or $or$libresoc.v:181887$11823 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -373019,10 +375890,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:179791$11772_Y + connect \Y $or$libresoc.v:181887$11823_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179793$11774 + cell $or $or$libresoc.v:181889$11825 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -373030,10 +375901,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:179793$11774_Y + connect \Y $or$libresoc.v:181889$11825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179796$11777 + cell $or $or$libresoc.v:181892$11828 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -373041,39 +375912,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:179796$11777_Y + connect \Y $or$libresoc.v:181892$11828_Y end - attribute \src "libresoc.v:179755.7-179755.20" - process $proc$libresoc.v:179755$11783 + attribute \src "libresoc.v:181851.7-181851.20" + process $proc$libresoc.v:181851$11834 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179777.13-179777.25" - process $proc$libresoc.v:179777$11784 + attribute \src "libresoc.v:181873.13-181873.25" + process $proc$libresoc.v:181873$11835 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:179798.3-179799.27" - process $proc$libresoc.v:179798$11779 + attribute \src "libresoc.v:181894.3-181895.27" + process $proc$libresoc.v:181894$11830 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:179800.3-179808.6" - process $proc$libresoc.v:179800$11780 + attribute \src "libresoc.v:181896.3-181904.6" + process $proc$libresoc.v:181896$11831 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11781 $1\q_int$next[3:0]$11782 - attribute \src "libresoc.v:179801.5-179801.29" + assign $0\q_int$next[3:0]$11832 $1\q_int$next[3:0]$11833 + attribute \src "libresoc.v:181897.5-181897.29" switch \initial - attribute \src "libresoc.v:179801.9-179801.17" + attribute \src "libresoc.v:181897.9-181897.17" case 1'1 case end @@ -373082,50 +375953,50 @@ module \req_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11782 4'0000 + assign $1\q_int$next[3:0]$11833 4'0000 case - assign $1\q_int$next[3:0]$11782 \$5 + assign $1\q_int$next[3:0]$11833 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11781 + update \q_int$next $0\q_int$next[3:0]$11832 end - connect \$9 $and$libresoc.v:179790$11771_Y - connect \$11 $or$libresoc.v:179791$11772_Y - connect \$13 $not$libresoc.v:179792$11773_Y - connect \$15 $or$libresoc.v:179793$11774_Y - connect \$1 $not$libresoc.v:179794$11775_Y - connect \$3 $and$libresoc.v:179795$11776_Y - connect \$5 $or$libresoc.v:179796$11777_Y - connect \$7 $not$libresoc.v:179797$11778_Y + connect \$9 $and$libresoc.v:181886$11822_Y + connect \$11 $or$libresoc.v:181887$11823_Y + connect \$13 $not$libresoc.v:181888$11824_Y + connect \$15 $or$libresoc.v:181889$11825_Y + connect \$1 $not$libresoc.v:181890$11826_Y + connect \$3 $and$libresoc.v:181891$11827_Y + connect \$5 $or$libresoc.v:181892$11828_Y + connect \$7 $not$libresoc.v:181893$11829_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:179816.1-179865.10" +attribute \src "libresoc.v:181912.1-181961.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:179817.7-179817.20" + attribute \src "libresoc.v:181913.7-181913.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179853.3-179861.6" - wire $0\q_int$next[0:0]$11792 - attribute \src "libresoc.v:179851.3-179852.27" + attribute \src "libresoc.v:181949.3-181957.6" + wire $0\q_int$next[0:0]$11843 + attribute \src "libresoc.v:181947.3-181948.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:179853.3-179861.6" - wire $1\q_int$next[0:0]$11793 - attribute \src "libresoc.v:179833.7-179833.19" + attribute \src "libresoc.v:181949.3-181957.6" + wire $1\q_int$next[0:0]$11844 + attribute \src "libresoc.v:181929.7-181929.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:179848.17-179848.96" - wire $and$libresoc.v:179848$11787_Y - attribute \src "libresoc.v:179847.17-179847.94" - wire $not$libresoc.v:179847$11786_Y - attribute \src "libresoc.v:179850.17-179850.94" - wire $not$libresoc.v:179850$11789_Y - attribute \src "libresoc.v:179846.17-179846.100" - wire $or$libresoc.v:179846$11785_Y - attribute \src "libresoc.v:179849.17-179849.99" - wire $or$libresoc.v:179849$11788_Y + attribute \src "libresoc.v:181944.17-181944.96" + wire $and$libresoc.v:181944$11838_Y + attribute \src "libresoc.v:181943.17-181943.94" + wire $not$libresoc.v:181943$11837_Y + attribute \src "libresoc.v:181946.17-181946.94" + wire $not$libresoc.v:181946$11840_Y + attribute \src "libresoc.v:181942.17-181942.100" + wire $or$libresoc.v:181942$11836_Y + attribute \src "libresoc.v:181945.17-181945.99" + wire $or$libresoc.v:181945$11839_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -373136,11 +376007,11 @@ module \reset_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179817.7-179817.15" + attribute \src "libresoc.v:181913.7-181913.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -373157,7 +376028,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179848$11787 + cell $and $and$libresoc.v:181944$11838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373165,26 +376036,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179848$11787_Y + connect \Y $and$libresoc.v:181944$11838_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179847$11786 + cell $not $not$libresoc.v:181943$11837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:179847$11786_Y + connect \Y $not$libresoc.v:181943$11837_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179850$11789 + cell $not $not$libresoc.v:181946$11840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:179850$11789_Y + connect \Y $not$libresoc.v:181946$11840_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179846$11785 + cell $or $or$libresoc.v:181942$11836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373192,10 +376063,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:179846$11785_Y + connect \Y $or$libresoc.v:181942$11836_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179849$11788 + cell $or $or$libresoc.v:181945$11839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373203,39 +376074,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:179849$11788_Y + connect \Y $or$libresoc.v:181945$11839_Y end - attribute \src "libresoc.v:179817.7-179817.20" - process $proc$libresoc.v:179817$11794 + attribute \src "libresoc.v:181913.7-181913.20" + process $proc$libresoc.v:181913$11845 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179833.7-179833.19" - process $proc$libresoc.v:179833$11795 + attribute \src "libresoc.v:181929.7-181929.19" + process $proc$libresoc.v:181929$11846 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:179851.3-179852.27" - process $proc$libresoc.v:179851$11790 + attribute \src "libresoc.v:181947.3-181948.27" + process $proc$libresoc.v:181947$11841 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:179853.3-179861.6" - process $proc$libresoc.v:179853$11791 + attribute \src "libresoc.v:181949.3-181957.6" + process $proc$libresoc.v:181949$11842 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11792 $1\q_int$next[0:0]$11793 - attribute \src "libresoc.v:179854.5-179854.29" + assign $0\q_int$next[0:0]$11843 $1\q_int$next[0:0]$11844 + attribute \src "libresoc.v:181950.5-181950.29" switch \initial - attribute \src "libresoc.v:179854.9-179854.17" + attribute \src "libresoc.v:181950.9-181950.17" case 1'1 case end @@ -373244,47 +376115,47 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11793 1'0 + assign $1\q_int$next[0:0]$11844 1'0 case - assign $1\q_int$next[0:0]$11793 \$5 + assign $1\q_int$next[0:0]$11844 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11792 + update \q_int$next $0\q_int$next[0:0]$11843 end - connect \$9 $or$libresoc.v:179846$11785_Y - connect \$1 $not$libresoc.v:179847$11786_Y - connect \$3 $and$libresoc.v:179848$11787_Y - connect \$5 $or$libresoc.v:179849$11788_Y - connect \$7 $not$libresoc.v:179850$11789_Y + connect \$9 $or$libresoc.v:181942$11836_Y + connect \$1 $not$libresoc.v:181943$11837_Y + connect \$3 $and$libresoc.v:181944$11838_Y + connect \$5 $or$libresoc.v:181945$11839_Y + connect \$7 $not$libresoc.v:181946$11840_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:179869.1-179918.10" +attribute \src "libresoc.v:181965.1-182014.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:179870.7-179870.20" + attribute \src "libresoc.v:181966.7-181966.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179906.3-179914.6" - wire $0\q_int$next[0:0]$11803 - attribute \src "libresoc.v:179904.3-179905.27" + attribute \src "libresoc.v:182002.3-182010.6" + wire $0\q_int$next[0:0]$11854 + attribute \src "libresoc.v:182000.3-182001.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:179906.3-179914.6" - wire $1\q_int$next[0:0]$11804 - attribute \src "libresoc.v:179886.7-179886.19" + attribute \src "libresoc.v:182002.3-182010.6" + wire $1\q_int$next[0:0]$11855 + attribute \src "libresoc.v:181982.7-181982.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:179901.17-179901.96" - wire $and$libresoc.v:179901$11798_Y - attribute \src "libresoc.v:179900.17-179900.94" - wire $not$libresoc.v:179900$11797_Y - attribute \src "libresoc.v:179903.17-179903.94" - wire $not$libresoc.v:179903$11800_Y - attribute \src "libresoc.v:179899.17-179899.100" - wire $or$libresoc.v:179899$11796_Y - attribute \src "libresoc.v:179902.17-179902.99" - wire $or$libresoc.v:179902$11799_Y + attribute \src "libresoc.v:181997.17-181997.96" + wire $and$libresoc.v:181997$11849_Y + attribute \src "libresoc.v:181996.17-181996.94" + wire $not$libresoc.v:181996$11848_Y + attribute \src "libresoc.v:181999.17-181999.94" + wire $not$libresoc.v:181999$11851_Y + attribute \src "libresoc.v:181995.17-181995.100" + wire $or$libresoc.v:181995$11847_Y + attribute \src "libresoc.v:181998.17-181998.99" + wire $or$libresoc.v:181998$11850_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -373295,11 +376166,11 @@ module \reset_l$131 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:179870.7-179870.15" + attribute \src "libresoc.v:181966.7-181966.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -373316,7 +376187,7 @@ module \reset_l$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:179901$11798 + cell $and $and$libresoc.v:181997$11849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373324,26 +376195,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:179901$11798_Y + connect \Y $and$libresoc.v:181997$11849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:179900$11797 + cell $not $not$libresoc.v:181996$11848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:179900$11797_Y + connect \Y $not$libresoc.v:181996$11848_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:179903$11800 + cell $not $not$libresoc.v:181999$11851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:179903$11800_Y + connect \Y $not$libresoc.v:181999$11851_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:179899$11796 + cell $or $or$libresoc.v:181995$11847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373351,10 +376222,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:179899$11796_Y + connect \Y $or$libresoc.v:181995$11847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:179902$11799 + cell $or $or$libresoc.v:181998$11850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373362,39 +376233,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:179902$11799_Y + connect \Y $or$libresoc.v:181998$11850_Y end - attribute \src "libresoc.v:179870.7-179870.20" - process $proc$libresoc.v:179870$11805 + attribute \src "libresoc.v:181966.7-181966.20" + process $proc$libresoc.v:181966$11856 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179886.7-179886.19" - process $proc$libresoc.v:179886$11806 + attribute \src "libresoc.v:181982.7-181982.19" + process $proc$libresoc.v:181982$11857 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:179904.3-179905.27" - process $proc$libresoc.v:179904$11801 + attribute \src "libresoc.v:182000.3-182001.27" + process $proc$libresoc.v:182000$11852 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:179906.3-179914.6" - process $proc$libresoc.v:179906$11802 + attribute \src "libresoc.v:182002.3-182010.6" + process $proc$libresoc.v:182002$11853 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11803 $1\q_int$next[0:0]$11804 - attribute \src "libresoc.v:179907.5-179907.29" + assign $0\q_int$next[0:0]$11854 $1\q_int$next[0:0]$11855 + attribute \src "libresoc.v:182003.5-182003.29" switch \initial - attribute \src "libresoc.v:179907.9-179907.17" + attribute \src "libresoc.v:182003.9-182003.17" case 1'1 case end @@ -373403,287 +376274,287 @@ module \reset_l$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11804 1'0 + assign $1\q_int$next[0:0]$11855 1'0 case - assign $1\q_int$next[0:0]$11804 \$5 + assign $1\q_int$next[0:0]$11855 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11803 + update \q_int$next $0\q_int$next[0:0]$11854 end - connect \$9 $or$libresoc.v:179899$11796_Y - connect \$1 $not$libresoc.v:179900$11797_Y - connect \$3 $and$libresoc.v:179901$11798_Y - connect \$5 $or$libresoc.v:179902$11799_Y - connect \$7 $not$libresoc.v:179903$11800_Y + connect \$9 $or$libresoc.v:181995$11847_Y + connect \$1 $not$libresoc.v:181996$11848_Y + connect \$3 $and$libresoc.v:181997$11849_Y + connect \$5 $or$libresoc.v:181998$11850_Y + connect \$7 $not$libresoc.v:181999$11851_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:179922.1-180509.10" +attribute \src "libresoc.v:182018.1-182605.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:179923.7-179923.20" + attribute \src "libresoc.v:182019.7-182019.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $10\mask[9:9] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $11\mask[10:10] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $12\mask[11:11] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $13\mask[12:12] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $14\mask[13:13] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $15\mask[14:14] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $16\mask[15:15] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $17\mask[16:16] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $18\mask[17:17] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $19\mask[18:18] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $1\mask[0:0] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $20\mask[19:19] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $21\mask[20:20] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $22\mask[21:21] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $23\mask[22:22] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $24\mask[23:23] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $25\mask[24:24] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $26\mask[25:25] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $27\mask[26:26] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $28\mask[27:27] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $29\mask[28:28] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $2\mask[1:1] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $30\mask[29:29] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $31\mask[30:30] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $32\mask[31:31] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $33\mask[32:32] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $34\mask[33:33] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $35\mask[34:34] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $36\mask[35:35] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $37\mask[36:36] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $38\mask[37:37] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $39\mask[38:38] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $3\mask[2:2] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $40\mask[39:39] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $41\mask[40:40] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $42\mask[41:41] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $43\mask[42:42] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $44\mask[43:43] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $45\mask[44:44] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $46\mask[45:45] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $47\mask[46:46] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $48\mask[47:47] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $49\mask[48:48] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $4\mask[3:3] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $50\mask[49:49] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $51\mask[50:50] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $52\mask[51:51] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $53\mask[52:52] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $54\mask[53:53] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $55\mask[54:54] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $56\mask[55:55] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $57\mask[56:56] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $58\mask[57:57] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $59\mask[58:58] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $5\mask[4:4] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $60\mask[59:59] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $61\mask[60:60] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $62\mask[61:61] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $63\mask[62:62] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $64\mask[63:63] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $6\mask[5:5] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $7\mask[6:6] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $8\mask[7:7] - attribute \src "libresoc.v:180121.3-180508.6" + attribute \src "libresoc.v:182217.3-182604.6" wire $9\mask[8:8] - attribute \src "libresoc.v:180057.17-180057.96" - wire $gt$libresoc.v:180057$11807_Y - attribute \src "libresoc.v:180058.18-180058.98" - wire $gt$libresoc.v:180058$11808_Y - attribute \src "libresoc.v:180059.19-180059.99" - wire $gt$libresoc.v:180059$11809_Y - attribute \src "libresoc.v:180060.19-180060.99" - wire $gt$libresoc.v:180060$11810_Y - attribute \src "libresoc.v:180061.19-180061.99" - wire $gt$libresoc.v:180061$11811_Y - attribute \src "libresoc.v:180062.19-180062.99" - wire $gt$libresoc.v:180062$11812_Y - attribute \src "libresoc.v:180063.19-180063.99" - wire $gt$libresoc.v:180063$11813_Y - attribute \src "libresoc.v:180064.19-180064.99" - wire $gt$libresoc.v:180064$11814_Y - attribute \src "libresoc.v:180065.19-180065.99" - wire $gt$libresoc.v:180065$11815_Y - attribute \src "libresoc.v:180066.19-180066.99" - wire $gt$libresoc.v:180066$11816_Y - attribute \src "libresoc.v:180067.19-180067.99" - wire $gt$libresoc.v:180067$11817_Y - attribute \src "libresoc.v:180068.18-180068.97" - wire $gt$libresoc.v:180068$11818_Y - attribute \src "libresoc.v:180069.19-180069.99" - wire $gt$libresoc.v:180069$11819_Y - attribute \src "libresoc.v:180070.19-180070.99" - wire $gt$libresoc.v:180070$11820_Y - attribute \src "libresoc.v:180071.19-180071.99" - wire $gt$libresoc.v:180071$11821_Y - attribute \src "libresoc.v:180072.19-180072.99" - wire $gt$libresoc.v:180072$11822_Y - attribute \src "libresoc.v:180073.19-180073.99" - wire $gt$libresoc.v:180073$11823_Y - attribute \src "libresoc.v:180074.18-180074.97" - wire $gt$libresoc.v:180074$11824_Y - attribute \src "libresoc.v:180075.18-180075.97" - wire $gt$libresoc.v:180075$11825_Y - attribute \src "libresoc.v:180076.18-180076.97" - wire $gt$libresoc.v:180076$11826_Y - attribute \src "libresoc.v:180077.17-180077.96" - wire $gt$libresoc.v:180077$11827_Y - attribute \src "libresoc.v:180078.18-180078.97" - wire $gt$libresoc.v:180078$11828_Y - attribute \src "libresoc.v:180079.18-180079.97" - wire $gt$libresoc.v:180079$11829_Y - attribute \src "libresoc.v:180080.18-180080.97" - wire $gt$libresoc.v:180080$11830_Y - attribute \src "libresoc.v:180081.18-180081.97" - wire $gt$libresoc.v:180081$11831_Y - attribute \src "libresoc.v:180082.18-180082.97" - wire $gt$libresoc.v:180082$11832_Y - attribute \src "libresoc.v:180083.18-180083.97" - wire $gt$libresoc.v:180083$11833_Y - attribute \src "libresoc.v:180084.18-180084.97" - wire $gt$libresoc.v:180084$11834_Y - attribute \src "libresoc.v:180085.18-180085.98" - wire $gt$libresoc.v:180085$11835_Y - attribute \src "libresoc.v:180086.18-180086.98" - wire $gt$libresoc.v:180086$11836_Y - attribute \src "libresoc.v:180087.18-180087.98" - wire $gt$libresoc.v:180087$11837_Y - attribute \src "libresoc.v:180088.17-180088.96" - wire $gt$libresoc.v:180088$11838_Y - attribute \src "libresoc.v:180089.18-180089.98" - wire $gt$libresoc.v:180089$11839_Y - attribute \src "libresoc.v:180090.18-180090.98" - wire $gt$libresoc.v:180090$11840_Y - attribute \src "libresoc.v:180091.18-180091.98" - wire $gt$libresoc.v:180091$11841_Y - attribute \src "libresoc.v:180092.18-180092.98" - wire $gt$libresoc.v:180092$11842_Y - attribute \src "libresoc.v:180093.18-180093.98" - wire $gt$libresoc.v:180093$11843_Y - attribute \src "libresoc.v:180094.18-180094.98" - wire $gt$libresoc.v:180094$11844_Y - attribute \src "libresoc.v:180095.18-180095.98" - wire $gt$libresoc.v:180095$11845_Y - attribute \src "libresoc.v:180096.18-180096.98" - wire $gt$libresoc.v:180096$11846_Y - attribute \src "libresoc.v:180097.18-180097.98" - wire $gt$libresoc.v:180097$11847_Y - attribute \src "libresoc.v:180098.18-180098.98" - wire $gt$libresoc.v:180098$11848_Y - attribute \src "libresoc.v:180099.17-180099.96" - wire $gt$libresoc.v:180099$11849_Y - attribute \src "libresoc.v:180100.18-180100.98" - wire $gt$libresoc.v:180100$11850_Y - attribute \src "libresoc.v:180101.18-180101.98" - wire $gt$libresoc.v:180101$11851_Y - attribute \src "libresoc.v:180102.18-180102.98" - wire $gt$libresoc.v:180102$11852_Y - attribute \src "libresoc.v:180103.18-180103.98" - wire $gt$libresoc.v:180103$11853_Y - attribute \src "libresoc.v:180104.18-180104.98" - wire $gt$libresoc.v:180104$11854_Y - attribute \src "libresoc.v:180105.18-180105.98" - wire $gt$libresoc.v:180105$11855_Y - attribute \src "libresoc.v:180106.18-180106.98" - wire $gt$libresoc.v:180106$11856_Y - attribute \src "libresoc.v:180107.18-180107.98" - wire $gt$libresoc.v:180107$11857_Y - attribute \src "libresoc.v:180108.18-180108.98" - wire $gt$libresoc.v:180108$11858_Y - attribute \src "libresoc.v:180109.18-180109.98" - wire $gt$libresoc.v:180109$11859_Y - attribute \src "libresoc.v:180110.17-180110.96" - wire $gt$libresoc.v:180110$11860_Y - attribute \src "libresoc.v:180111.18-180111.98" - wire $gt$libresoc.v:180111$11861_Y - attribute \src "libresoc.v:180112.18-180112.98" - wire $gt$libresoc.v:180112$11862_Y - attribute \src "libresoc.v:180113.18-180113.98" - wire $gt$libresoc.v:180113$11863_Y - attribute \src "libresoc.v:180114.18-180114.98" - wire $gt$libresoc.v:180114$11864_Y - attribute \src "libresoc.v:180115.18-180115.98" - wire $gt$libresoc.v:180115$11865_Y - attribute \src "libresoc.v:180116.18-180116.98" - wire $gt$libresoc.v:180116$11866_Y - attribute \src "libresoc.v:180117.18-180117.98" - wire $gt$libresoc.v:180117$11867_Y - attribute \src "libresoc.v:180118.18-180118.98" - wire $gt$libresoc.v:180118$11868_Y - attribute \src "libresoc.v:180119.18-180119.98" - wire $gt$libresoc.v:180119$11869_Y - attribute \src "libresoc.v:180120.18-180120.98" - wire $gt$libresoc.v:180120$11870_Y + attribute \src "libresoc.v:182153.17-182153.96" + wire $gt$libresoc.v:182153$11858_Y + attribute \src "libresoc.v:182154.18-182154.98" + wire $gt$libresoc.v:182154$11859_Y + attribute \src "libresoc.v:182155.19-182155.99" + wire $gt$libresoc.v:182155$11860_Y + attribute \src "libresoc.v:182156.19-182156.99" + wire $gt$libresoc.v:182156$11861_Y + attribute \src "libresoc.v:182157.19-182157.99" + wire $gt$libresoc.v:182157$11862_Y + attribute \src "libresoc.v:182158.19-182158.99" + wire $gt$libresoc.v:182158$11863_Y + attribute \src "libresoc.v:182159.19-182159.99" + wire $gt$libresoc.v:182159$11864_Y + attribute \src "libresoc.v:182160.19-182160.99" + wire $gt$libresoc.v:182160$11865_Y + attribute \src "libresoc.v:182161.19-182161.99" + wire $gt$libresoc.v:182161$11866_Y + attribute \src "libresoc.v:182162.19-182162.99" + wire $gt$libresoc.v:182162$11867_Y + attribute \src "libresoc.v:182163.19-182163.99" + wire $gt$libresoc.v:182163$11868_Y + attribute \src "libresoc.v:182164.18-182164.97" + wire $gt$libresoc.v:182164$11869_Y + attribute \src "libresoc.v:182165.19-182165.99" + wire $gt$libresoc.v:182165$11870_Y + attribute \src "libresoc.v:182166.19-182166.99" + wire $gt$libresoc.v:182166$11871_Y + attribute \src "libresoc.v:182167.19-182167.99" + wire $gt$libresoc.v:182167$11872_Y + attribute \src "libresoc.v:182168.19-182168.99" + wire $gt$libresoc.v:182168$11873_Y + attribute \src "libresoc.v:182169.19-182169.99" + wire $gt$libresoc.v:182169$11874_Y + attribute \src "libresoc.v:182170.18-182170.97" + wire $gt$libresoc.v:182170$11875_Y + attribute \src "libresoc.v:182171.18-182171.97" + wire $gt$libresoc.v:182171$11876_Y + attribute \src "libresoc.v:182172.18-182172.97" + wire $gt$libresoc.v:182172$11877_Y + attribute \src "libresoc.v:182173.17-182173.96" + wire $gt$libresoc.v:182173$11878_Y + attribute \src "libresoc.v:182174.18-182174.97" + wire $gt$libresoc.v:182174$11879_Y + attribute \src "libresoc.v:182175.18-182175.97" + wire $gt$libresoc.v:182175$11880_Y + attribute \src "libresoc.v:182176.18-182176.97" + wire $gt$libresoc.v:182176$11881_Y + attribute \src "libresoc.v:182177.18-182177.97" + wire $gt$libresoc.v:182177$11882_Y + attribute \src "libresoc.v:182178.18-182178.97" + wire $gt$libresoc.v:182178$11883_Y + attribute \src "libresoc.v:182179.18-182179.97" + wire $gt$libresoc.v:182179$11884_Y + attribute \src "libresoc.v:182180.18-182180.97" + wire $gt$libresoc.v:182180$11885_Y + attribute \src "libresoc.v:182181.18-182181.98" + wire $gt$libresoc.v:182181$11886_Y + attribute \src "libresoc.v:182182.18-182182.98" + wire $gt$libresoc.v:182182$11887_Y + attribute \src "libresoc.v:182183.18-182183.98" + wire $gt$libresoc.v:182183$11888_Y + attribute \src "libresoc.v:182184.17-182184.96" + wire $gt$libresoc.v:182184$11889_Y + attribute \src "libresoc.v:182185.18-182185.98" + wire $gt$libresoc.v:182185$11890_Y + attribute \src "libresoc.v:182186.18-182186.98" + wire $gt$libresoc.v:182186$11891_Y + attribute \src "libresoc.v:182187.18-182187.98" + wire $gt$libresoc.v:182187$11892_Y + attribute \src "libresoc.v:182188.18-182188.98" + wire $gt$libresoc.v:182188$11893_Y + attribute \src "libresoc.v:182189.18-182189.98" + wire $gt$libresoc.v:182189$11894_Y + attribute \src "libresoc.v:182190.18-182190.98" + wire $gt$libresoc.v:182190$11895_Y + attribute \src "libresoc.v:182191.18-182191.98" + wire $gt$libresoc.v:182191$11896_Y + attribute \src "libresoc.v:182192.18-182192.98" + wire $gt$libresoc.v:182192$11897_Y + attribute \src "libresoc.v:182193.18-182193.98" + wire $gt$libresoc.v:182193$11898_Y + attribute \src "libresoc.v:182194.18-182194.98" + wire $gt$libresoc.v:182194$11899_Y + attribute \src "libresoc.v:182195.17-182195.96" + wire $gt$libresoc.v:182195$11900_Y + attribute \src "libresoc.v:182196.18-182196.98" + wire $gt$libresoc.v:182196$11901_Y + attribute \src "libresoc.v:182197.18-182197.98" + wire $gt$libresoc.v:182197$11902_Y + attribute \src "libresoc.v:182198.18-182198.98" + wire $gt$libresoc.v:182198$11903_Y + attribute \src "libresoc.v:182199.18-182199.98" + wire $gt$libresoc.v:182199$11904_Y + attribute \src "libresoc.v:182200.18-182200.98" + wire $gt$libresoc.v:182200$11905_Y + attribute \src "libresoc.v:182201.18-182201.98" + wire $gt$libresoc.v:182201$11906_Y + attribute \src "libresoc.v:182202.18-182202.98" + wire $gt$libresoc.v:182202$11907_Y + attribute \src "libresoc.v:182203.18-182203.98" + wire $gt$libresoc.v:182203$11908_Y + attribute \src "libresoc.v:182204.18-182204.98" + wire $gt$libresoc.v:182204$11909_Y + attribute \src "libresoc.v:182205.18-182205.98" + wire $gt$libresoc.v:182205$11910_Y + attribute \src "libresoc.v:182206.17-182206.96" + wire $gt$libresoc.v:182206$11911_Y + attribute \src "libresoc.v:182207.18-182207.98" + wire $gt$libresoc.v:182207$11912_Y + attribute \src "libresoc.v:182208.18-182208.98" + wire $gt$libresoc.v:182208$11913_Y + attribute \src "libresoc.v:182209.18-182209.98" + wire $gt$libresoc.v:182209$11914_Y + attribute \src "libresoc.v:182210.18-182210.98" + wire $gt$libresoc.v:182210$11915_Y + attribute \src "libresoc.v:182211.18-182211.98" + wire $gt$libresoc.v:182211$11916_Y + attribute \src "libresoc.v:182212.18-182212.98" + wire $gt$libresoc.v:182212$11917_Y + attribute \src "libresoc.v:182213.18-182213.98" + wire $gt$libresoc.v:182213$11918_Y + attribute \src "libresoc.v:182214.18-182214.98" + wire $gt$libresoc.v:182214$11919_Y + attribute \src "libresoc.v:182215.18-182215.98" + wire $gt$libresoc.v:182215$11920_Y + attribute \src "libresoc.v:182216.18-182216.98" + wire $gt$libresoc.v:182216$11921_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -373812,14 +376683,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:179923.7-179923.15" + attribute \src "libresoc.v:182019.7-182019.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180057$11807 + cell $gt $gt$libresoc.v:182153$11858 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373827,10 +376698,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:180057$11807_Y + connect \Y $gt$libresoc.v:182153$11858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180058$11808 + cell $gt $gt$libresoc.v:182154$11859 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373838,10 +376709,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:180058$11808_Y + connect \Y $gt$libresoc.v:182154$11859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180059$11809 + cell $gt $gt$libresoc.v:182155$11860 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373849,10 +376720,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:180059$11809_Y + connect \Y $gt$libresoc.v:182155$11860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180060$11810 + cell $gt $gt$libresoc.v:182156$11861 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373860,10 +376731,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:180060$11810_Y + connect \Y $gt$libresoc.v:182156$11861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180061$11811 + cell $gt $gt$libresoc.v:182157$11862 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373871,10 +376742,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:180061$11811_Y + connect \Y $gt$libresoc.v:182157$11862_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180062$11812 + cell $gt $gt$libresoc.v:182158$11863 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373882,10 +376753,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:180062$11812_Y + connect \Y $gt$libresoc.v:182158$11863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180063$11813 + cell $gt $gt$libresoc.v:182159$11864 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373893,10 +376764,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:180063$11813_Y + connect \Y $gt$libresoc.v:182159$11864_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180064$11814 + cell $gt $gt$libresoc.v:182160$11865 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373904,10 +376775,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:180064$11814_Y + connect \Y $gt$libresoc.v:182160$11865_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180065$11815 + cell $gt $gt$libresoc.v:182161$11866 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373915,10 +376786,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:180065$11815_Y + connect \Y $gt$libresoc.v:182161$11866_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180066$11816 + cell $gt $gt$libresoc.v:182162$11867 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373926,10 +376797,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:180066$11816_Y + connect \Y $gt$libresoc.v:182162$11867_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180067$11817 + cell $gt $gt$libresoc.v:182163$11868 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373937,10 +376808,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:180067$11817_Y + connect \Y $gt$libresoc.v:182163$11868_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180068$11818 + cell $gt $gt$libresoc.v:182164$11869 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373948,10 +376819,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:180068$11818_Y + connect \Y $gt$libresoc.v:182164$11869_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180069$11819 + cell $gt $gt$libresoc.v:182165$11870 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373959,10 +376830,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:180069$11819_Y + connect \Y $gt$libresoc.v:182165$11870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180070$11820 + cell $gt $gt$libresoc.v:182166$11871 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373970,10 +376841,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:180070$11820_Y + connect \Y $gt$libresoc.v:182166$11871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180071$11821 + cell $gt $gt$libresoc.v:182167$11872 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373981,10 +376852,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:180071$11821_Y + connect \Y $gt$libresoc.v:182167$11872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180072$11822 + cell $gt $gt$libresoc.v:182168$11873 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -373992,10 +376863,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:180072$11822_Y + connect \Y $gt$libresoc.v:182168$11873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180073$11823 + cell $gt $gt$libresoc.v:182169$11874 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374003,10 +376874,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:180073$11823_Y + connect \Y $gt$libresoc.v:182169$11874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180074$11824 + cell $gt $gt$libresoc.v:182170$11875 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374014,10 +376885,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:180074$11824_Y + connect \Y $gt$libresoc.v:182170$11875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180075$11825 + cell $gt $gt$libresoc.v:182171$11876 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374025,10 +376896,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:180075$11825_Y + connect \Y $gt$libresoc.v:182171$11876_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180076$11826 + cell $gt $gt$libresoc.v:182172$11877 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374036,10 +376907,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:180076$11826_Y + connect \Y $gt$libresoc.v:182172$11877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180077$11827 + cell $gt $gt$libresoc.v:182173$11878 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374047,10 +376918,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:180077$11827_Y + connect \Y $gt$libresoc.v:182173$11878_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180078$11828 + cell $gt $gt$libresoc.v:182174$11879 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374058,10 +376929,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:180078$11828_Y + connect \Y $gt$libresoc.v:182174$11879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180079$11829 + cell $gt $gt$libresoc.v:182175$11880 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374069,10 +376940,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:180079$11829_Y + connect \Y $gt$libresoc.v:182175$11880_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180080$11830 + cell $gt $gt$libresoc.v:182176$11881 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374080,10 +376951,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:180080$11830_Y + connect \Y $gt$libresoc.v:182176$11881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180081$11831 + cell $gt $gt$libresoc.v:182177$11882 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374091,10 +376962,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:180081$11831_Y + connect \Y $gt$libresoc.v:182177$11882_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180082$11832 + cell $gt $gt$libresoc.v:182178$11883 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374102,10 +376973,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:180082$11832_Y + connect \Y $gt$libresoc.v:182178$11883_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180083$11833 + cell $gt $gt$libresoc.v:182179$11884 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374113,10 +376984,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:180083$11833_Y + connect \Y $gt$libresoc.v:182179$11884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180084$11834 + cell $gt $gt$libresoc.v:182180$11885 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374124,10 +376995,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:180084$11834_Y + connect \Y $gt$libresoc.v:182180$11885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180085$11835 + cell $gt $gt$libresoc.v:182181$11886 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374135,10 +377006,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:180085$11835_Y + connect \Y $gt$libresoc.v:182181$11886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180086$11836 + cell $gt $gt$libresoc.v:182182$11887 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374146,10 +377017,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:180086$11836_Y + connect \Y $gt$libresoc.v:182182$11887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180087$11837 + cell $gt $gt$libresoc.v:182183$11888 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374157,10 +377028,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:180087$11837_Y + connect \Y $gt$libresoc.v:182183$11888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180088$11838 + cell $gt $gt$libresoc.v:182184$11889 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374168,10 +377039,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:180088$11838_Y + connect \Y $gt$libresoc.v:182184$11889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180089$11839 + cell $gt $gt$libresoc.v:182185$11890 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374179,10 +377050,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:180089$11839_Y + connect \Y $gt$libresoc.v:182185$11890_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180090$11840 + cell $gt $gt$libresoc.v:182186$11891 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374190,10 +377061,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:180090$11840_Y + connect \Y $gt$libresoc.v:182186$11891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180091$11841 + cell $gt $gt$libresoc.v:182187$11892 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374201,10 +377072,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:180091$11841_Y + connect \Y $gt$libresoc.v:182187$11892_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180092$11842 + cell $gt $gt$libresoc.v:182188$11893 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374212,10 +377083,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:180092$11842_Y + connect \Y $gt$libresoc.v:182188$11893_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180093$11843 + cell $gt $gt$libresoc.v:182189$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374223,10 +377094,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:180093$11843_Y + connect \Y $gt$libresoc.v:182189$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180094$11844 + cell $gt $gt$libresoc.v:182190$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374234,10 +377105,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:180094$11844_Y + connect \Y $gt$libresoc.v:182190$11895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180095$11845 + cell $gt $gt$libresoc.v:182191$11896 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374245,10 +377116,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:180095$11845_Y + connect \Y $gt$libresoc.v:182191$11896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180096$11846 + cell $gt $gt$libresoc.v:182192$11897 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374256,10 +377127,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:180096$11846_Y + connect \Y $gt$libresoc.v:182192$11897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180097$11847 + cell $gt $gt$libresoc.v:182193$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374267,10 +377138,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:180097$11847_Y + connect \Y $gt$libresoc.v:182193$11898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180098$11848 + cell $gt $gt$libresoc.v:182194$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374278,10 +377149,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:180098$11848_Y + connect \Y $gt$libresoc.v:182194$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180099$11849 + cell $gt $gt$libresoc.v:182195$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374289,10 +377160,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:180099$11849_Y + connect \Y $gt$libresoc.v:182195$11900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180100$11850 + cell $gt $gt$libresoc.v:182196$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374300,10 +377171,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:180100$11850_Y + connect \Y $gt$libresoc.v:182196$11901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180101$11851 + cell $gt $gt$libresoc.v:182197$11902 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374311,10 +377182,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:180101$11851_Y + connect \Y $gt$libresoc.v:182197$11902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180102$11852 + cell $gt $gt$libresoc.v:182198$11903 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374322,10 +377193,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:180102$11852_Y + connect \Y $gt$libresoc.v:182198$11903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180103$11853 + cell $gt $gt$libresoc.v:182199$11904 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374333,10 +377204,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:180103$11853_Y + connect \Y $gt$libresoc.v:182199$11904_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180104$11854 + cell $gt $gt$libresoc.v:182200$11905 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374344,10 +377215,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:180104$11854_Y + connect \Y $gt$libresoc.v:182200$11905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180105$11855 + cell $gt $gt$libresoc.v:182201$11906 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374355,10 +377226,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:180105$11855_Y + connect \Y $gt$libresoc.v:182201$11906_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180106$11856 + cell $gt $gt$libresoc.v:182202$11907 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374366,10 +377237,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:180106$11856_Y + connect \Y $gt$libresoc.v:182202$11907_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180107$11857 + cell $gt $gt$libresoc.v:182203$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374377,10 +377248,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:180107$11857_Y + connect \Y $gt$libresoc.v:182203$11908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180108$11858 + cell $gt $gt$libresoc.v:182204$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374388,10 +377259,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:180108$11858_Y + connect \Y $gt$libresoc.v:182204$11909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180109$11859 + cell $gt $gt$libresoc.v:182205$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374399,10 +377270,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:180109$11859_Y + connect \Y $gt$libresoc.v:182205$11910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180110$11860 + cell $gt $gt$libresoc.v:182206$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374410,10 +377281,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:180110$11860_Y + connect \Y $gt$libresoc.v:182206$11911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180111$11861 + cell $gt $gt$libresoc.v:182207$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374421,10 +377292,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:180111$11861_Y + connect \Y $gt$libresoc.v:182207$11912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180112$11862 + cell $gt $gt$libresoc.v:182208$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374432,10 +377303,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:180112$11862_Y + connect \Y $gt$libresoc.v:182208$11913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180113$11863 + cell $gt $gt$libresoc.v:182209$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374443,10 +377314,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:180113$11863_Y + connect \Y $gt$libresoc.v:182209$11914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180114$11864 + cell $gt $gt$libresoc.v:182210$11915 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374454,10 +377325,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:180114$11864_Y + connect \Y $gt$libresoc.v:182210$11915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180115$11865 + cell $gt $gt$libresoc.v:182211$11916 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374465,10 +377336,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:180115$11865_Y + connect \Y $gt$libresoc.v:182211$11916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180116$11866 + cell $gt $gt$libresoc.v:182212$11917 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374476,10 +377347,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:180116$11866_Y + connect \Y $gt$libresoc.v:182212$11917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180117$11867 + cell $gt $gt$libresoc.v:182213$11918 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374487,10 +377358,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:180117$11867_Y + connect \Y $gt$libresoc.v:182213$11918_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180118$11868 + cell $gt $gt$libresoc.v:182214$11919 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374498,10 +377369,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:180118$11868_Y + connect \Y $gt$libresoc.v:182214$11919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180119$11869 + cell $gt $gt$libresoc.v:182215$11920 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374509,10 +377380,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:180119$11869_Y + connect \Y $gt$libresoc.v:182215$11920_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:180120$11870 + cell $gt $gt$libresoc.v:182216$11921 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -374520,18 +377391,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:180120$11870_Y + connect \Y $gt$libresoc.v:182216$11921_Y end - attribute \src "libresoc.v:179923.7-179923.20" - process $proc$libresoc.v:179923$11872 + attribute \src "libresoc.v:182019.7-182019.20" + process $proc$libresoc.v:182019$11923 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180121.3-180508.6" - process $proc$libresoc.v:180121$11871 + attribute \src "libresoc.v:182217.3-182604.6" + process $proc$libresoc.v:182217$11922 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -374598,9 +377469,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:180122.5-180122.29" + attribute \src "libresoc.v:182218.5-182218.29" switch \initial - attribute \src "libresoc.v:180122.9-180122.17" + attribute \src "libresoc.v:182218.9-182218.17" case 1'1 case end @@ -375183,102 +378054,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:180057$11807_Y - connect \$99 $gt$libresoc.v:180058$11808_Y - connect \$101 $gt$libresoc.v:180059$11809_Y - connect \$103 $gt$libresoc.v:180060$11810_Y - connect \$105 $gt$libresoc.v:180061$11811_Y - connect \$107 $gt$libresoc.v:180062$11812_Y - connect \$109 $gt$libresoc.v:180063$11813_Y - connect \$111 $gt$libresoc.v:180064$11814_Y - connect \$113 $gt$libresoc.v:180065$11815_Y - connect \$115 $gt$libresoc.v:180066$11816_Y - connect \$117 $gt$libresoc.v:180067$11817_Y - connect \$11 $gt$libresoc.v:180068$11818_Y - connect \$119 $gt$libresoc.v:180069$11819_Y - connect \$121 $gt$libresoc.v:180070$11820_Y - connect \$123 $gt$libresoc.v:180071$11821_Y - connect \$125 $gt$libresoc.v:180072$11822_Y - connect \$127 $gt$libresoc.v:180073$11823_Y - connect \$13 $gt$libresoc.v:180074$11824_Y - connect \$15 $gt$libresoc.v:180075$11825_Y - connect \$17 $gt$libresoc.v:180076$11826_Y - connect \$1 $gt$libresoc.v:180077$11827_Y - connect \$19 $gt$libresoc.v:180078$11828_Y - connect \$21 $gt$libresoc.v:180079$11829_Y - connect \$23 $gt$libresoc.v:180080$11830_Y - connect \$25 $gt$libresoc.v:180081$11831_Y - connect \$27 $gt$libresoc.v:180082$11832_Y - connect \$29 $gt$libresoc.v:180083$11833_Y - connect \$31 $gt$libresoc.v:180084$11834_Y - connect \$33 $gt$libresoc.v:180085$11835_Y - connect \$35 $gt$libresoc.v:180086$11836_Y - connect \$37 $gt$libresoc.v:180087$11837_Y - connect \$3 $gt$libresoc.v:180088$11838_Y - connect \$39 $gt$libresoc.v:180089$11839_Y - connect \$41 $gt$libresoc.v:180090$11840_Y - connect \$43 $gt$libresoc.v:180091$11841_Y - connect \$45 $gt$libresoc.v:180092$11842_Y - connect \$47 $gt$libresoc.v:180093$11843_Y - connect \$49 $gt$libresoc.v:180094$11844_Y - connect \$51 $gt$libresoc.v:180095$11845_Y - connect \$53 $gt$libresoc.v:180096$11846_Y - connect \$55 $gt$libresoc.v:180097$11847_Y - connect \$57 $gt$libresoc.v:180098$11848_Y - connect \$5 $gt$libresoc.v:180099$11849_Y - connect \$59 $gt$libresoc.v:180100$11850_Y - connect \$61 $gt$libresoc.v:180101$11851_Y - connect \$63 $gt$libresoc.v:180102$11852_Y - connect \$65 $gt$libresoc.v:180103$11853_Y - connect \$67 $gt$libresoc.v:180104$11854_Y - connect \$69 $gt$libresoc.v:180105$11855_Y - connect \$71 $gt$libresoc.v:180106$11856_Y - connect \$73 $gt$libresoc.v:180107$11857_Y - connect \$75 $gt$libresoc.v:180108$11858_Y - connect \$77 $gt$libresoc.v:180109$11859_Y - connect \$7 $gt$libresoc.v:180110$11860_Y - connect \$79 $gt$libresoc.v:180111$11861_Y - connect \$81 $gt$libresoc.v:180112$11862_Y - connect \$83 $gt$libresoc.v:180113$11863_Y - connect \$85 $gt$libresoc.v:180114$11864_Y - connect \$87 $gt$libresoc.v:180115$11865_Y - connect \$89 $gt$libresoc.v:180116$11866_Y - connect \$91 $gt$libresoc.v:180117$11867_Y - connect \$93 $gt$libresoc.v:180118$11868_Y - connect \$95 $gt$libresoc.v:180119$11869_Y - connect \$97 $gt$libresoc.v:180120$11870_Y + connect \$9 $gt$libresoc.v:182153$11858_Y + connect \$99 $gt$libresoc.v:182154$11859_Y + connect \$101 $gt$libresoc.v:182155$11860_Y + connect \$103 $gt$libresoc.v:182156$11861_Y + connect \$105 $gt$libresoc.v:182157$11862_Y + connect \$107 $gt$libresoc.v:182158$11863_Y + connect \$109 $gt$libresoc.v:182159$11864_Y + connect \$111 $gt$libresoc.v:182160$11865_Y + connect \$113 $gt$libresoc.v:182161$11866_Y + connect \$115 $gt$libresoc.v:182162$11867_Y + connect \$117 $gt$libresoc.v:182163$11868_Y + connect \$11 $gt$libresoc.v:182164$11869_Y + connect \$119 $gt$libresoc.v:182165$11870_Y + connect \$121 $gt$libresoc.v:182166$11871_Y + connect \$123 $gt$libresoc.v:182167$11872_Y + connect \$125 $gt$libresoc.v:182168$11873_Y + connect \$127 $gt$libresoc.v:182169$11874_Y + connect \$13 $gt$libresoc.v:182170$11875_Y + connect \$15 $gt$libresoc.v:182171$11876_Y + connect \$17 $gt$libresoc.v:182172$11877_Y + connect \$1 $gt$libresoc.v:182173$11878_Y + connect \$19 $gt$libresoc.v:182174$11879_Y + connect \$21 $gt$libresoc.v:182175$11880_Y + connect \$23 $gt$libresoc.v:182176$11881_Y + connect \$25 $gt$libresoc.v:182177$11882_Y + connect \$27 $gt$libresoc.v:182178$11883_Y + connect \$29 $gt$libresoc.v:182179$11884_Y + connect \$31 $gt$libresoc.v:182180$11885_Y + connect \$33 $gt$libresoc.v:182181$11886_Y + connect \$35 $gt$libresoc.v:182182$11887_Y + connect \$37 $gt$libresoc.v:182183$11888_Y + connect \$3 $gt$libresoc.v:182184$11889_Y + connect \$39 $gt$libresoc.v:182185$11890_Y + connect \$41 $gt$libresoc.v:182186$11891_Y + connect \$43 $gt$libresoc.v:182187$11892_Y + connect \$45 $gt$libresoc.v:182188$11893_Y + connect \$47 $gt$libresoc.v:182189$11894_Y + connect \$49 $gt$libresoc.v:182190$11895_Y + connect \$51 $gt$libresoc.v:182191$11896_Y + connect \$53 $gt$libresoc.v:182192$11897_Y + connect \$55 $gt$libresoc.v:182193$11898_Y + connect \$57 $gt$libresoc.v:182194$11899_Y + connect \$5 $gt$libresoc.v:182195$11900_Y + connect \$59 $gt$libresoc.v:182196$11901_Y + connect \$61 $gt$libresoc.v:182197$11902_Y + connect \$63 $gt$libresoc.v:182198$11903_Y + connect \$65 $gt$libresoc.v:182199$11904_Y + connect \$67 $gt$libresoc.v:182200$11905_Y + connect \$69 $gt$libresoc.v:182201$11906_Y + connect \$71 $gt$libresoc.v:182202$11907_Y + connect \$73 $gt$libresoc.v:182203$11908_Y + connect \$75 $gt$libresoc.v:182204$11909_Y + connect \$77 $gt$libresoc.v:182205$11910_Y + connect \$7 $gt$libresoc.v:182206$11911_Y + connect \$79 $gt$libresoc.v:182207$11912_Y + connect \$81 $gt$libresoc.v:182208$11913_Y + connect \$83 $gt$libresoc.v:182209$11914_Y + connect \$85 $gt$libresoc.v:182210$11915_Y + connect \$87 $gt$libresoc.v:182211$11916_Y + connect \$89 $gt$libresoc.v:182212$11917_Y + connect \$91 $gt$libresoc.v:182213$11918_Y + connect \$93 $gt$libresoc.v:182214$11919_Y + connect \$95 $gt$libresoc.v:182215$11920_Y + connect \$97 $gt$libresoc.v:182216$11921_Y end -attribute \src "libresoc.v:180513.1-180571.10" +attribute \src "libresoc.v:182609.1-182667.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:180514.7-180514.20" + attribute \src "libresoc.v:182610.7-182610.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180559.3-180567.6" - wire $0\q_int$next[0:0]$11883 - attribute \src "libresoc.v:180557.3-180558.27" + attribute \src "libresoc.v:182655.3-182663.6" + wire $0\q_int$next[0:0]$11934 + attribute \src "libresoc.v:182653.3-182654.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:180559.3-180567.6" - wire $1\q_int$next[0:0]$11884 - attribute \src "libresoc.v:180536.7-180536.19" + attribute \src "libresoc.v:182655.3-182663.6" + wire $1\q_int$next[0:0]$11935 + attribute \src "libresoc.v:182632.7-182632.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:180549.17-180549.96" - wire $and$libresoc.v:180549$11873_Y - attribute \src "libresoc.v:180554.17-180554.96" - wire $and$libresoc.v:180554$11878_Y - attribute \src "libresoc.v:180551.18-180551.94" - wire $not$libresoc.v:180551$11875_Y - attribute \src "libresoc.v:180553.17-180553.93" - wire $not$libresoc.v:180553$11877_Y - attribute \src "libresoc.v:180556.17-180556.93" - wire $not$libresoc.v:180556$11880_Y - attribute \src "libresoc.v:180550.18-180550.99" - wire $or$libresoc.v:180550$11874_Y - attribute \src "libresoc.v:180552.18-180552.100" - wire $or$libresoc.v:180552$11876_Y - attribute \src "libresoc.v:180555.17-180555.98" - wire $or$libresoc.v:180555$11879_Y + attribute \src "libresoc.v:182645.17-182645.96" + wire $and$libresoc.v:182645$11924_Y + attribute \src "libresoc.v:182650.17-182650.96" + wire $and$libresoc.v:182650$11929_Y + attribute \src "libresoc.v:182647.18-182647.94" + wire $not$libresoc.v:182647$11926_Y + attribute \src "libresoc.v:182649.17-182649.93" + wire $not$libresoc.v:182649$11928_Y + attribute \src "libresoc.v:182652.17-182652.93" + wire $not$libresoc.v:182652$11931_Y + attribute \src "libresoc.v:182646.18-182646.99" + wire $or$libresoc.v:182646$11925_Y + attribute \src "libresoc.v:182648.18-182648.100" + wire $or$libresoc.v:182648$11927_Y + attribute \src "libresoc.v:182651.17-182651.98" + wire $or$libresoc.v:182651$11930_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375295,11 +378166,11 @@ module \rok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180514.7-180514.15" + attribute \src "libresoc.v:182610.7-182610.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -375316,7 +378187,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:180549$11873 + cell $and $and$libresoc.v:182645$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375324,10 +378195,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180549$11873_Y + connect \Y $and$libresoc.v:182645$11924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:180554$11878 + cell $and $and$libresoc.v:182650$11929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375335,34 +378206,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180554$11878_Y + connect \Y $and$libresoc.v:182650$11929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:180551$11875 + cell $not $not$libresoc.v:182647$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:180551$11875_Y + connect \Y $not$libresoc.v:182647$11926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:180553$11877 + cell $not $not$libresoc.v:182649$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180553$11877_Y + connect \Y $not$libresoc.v:182649$11928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:180556$11880 + cell $not $not$libresoc.v:182652$11931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180556$11880_Y + connect \Y $not$libresoc.v:182652$11931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:180550$11874 + cell $or $or$libresoc.v:182646$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375370,10 +378241,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:180550$11874_Y + connect \Y $or$libresoc.v:182646$11925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:180552$11876 + cell $or $or$libresoc.v:182648$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375381,10 +378252,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:180552$11876_Y + connect \Y $or$libresoc.v:182648$11927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:180555$11879 + cell $or $or$libresoc.v:182651$11930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375392,39 +378263,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:180555$11879_Y + connect \Y $or$libresoc.v:182651$11930_Y end - attribute \src "libresoc.v:180514.7-180514.20" - process $proc$libresoc.v:180514$11885 + attribute \src "libresoc.v:182610.7-182610.20" + process $proc$libresoc.v:182610$11936 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180536.7-180536.19" - process $proc$libresoc.v:180536$11886 + attribute \src "libresoc.v:182632.7-182632.19" + process $proc$libresoc.v:182632$11937 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:180557.3-180558.27" - process $proc$libresoc.v:180557$11881 + attribute \src "libresoc.v:182653.3-182654.27" + process $proc$libresoc.v:182653$11932 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:180559.3-180567.6" - process $proc$libresoc.v:180559$11882 + attribute \src "libresoc.v:182655.3-182663.6" + process $proc$libresoc.v:182655$11933 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11883 $1\q_int$next[0:0]$11884 - attribute \src "libresoc.v:180560.5-180560.29" + assign $0\q_int$next[0:0]$11934 $1\q_int$next[0:0]$11935 + attribute \src "libresoc.v:182656.5-182656.29" switch \initial - attribute \src "libresoc.v:180560.9-180560.17" + attribute \src "libresoc.v:182656.9-182656.17" case 1'1 case end @@ -375433,56 +378304,56 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11884 1'0 + assign $1\q_int$next[0:0]$11935 1'0 case - assign $1\q_int$next[0:0]$11884 \$5 + assign $1\q_int$next[0:0]$11935 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11883 + update \q_int$next $0\q_int$next[0:0]$11934 end - connect \$9 $and$libresoc.v:180549$11873_Y - connect \$11 $or$libresoc.v:180550$11874_Y - connect \$13 $not$libresoc.v:180551$11875_Y - connect \$15 $or$libresoc.v:180552$11876_Y - connect \$1 $not$libresoc.v:180553$11877_Y - connect \$3 $and$libresoc.v:180554$11878_Y - connect \$5 $or$libresoc.v:180555$11879_Y - connect \$7 $not$libresoc.v:180556$11880_Y + connect \$9 $and$libresoc.v:182645$11924_Y + connect \$11 $or$libresoc.v:182646$11925_Y + connect \$13 $not$libresoc.v:182647$11926_Y + connect \$15 $or$libresoc.v:182648$11927_Y + connect \$1 $not$libresoc.v:182649$11928_Y + connect \$3 $and$libresoc.v:182650$11929_Y + connect \$5 $or$libresoc.v:182651$11930_Y + connect \$7 $not$libresoc.v:182652$11931_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:180575.1-180633.10" +attribute \src "libresoc.v:182671.1-182729.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:180576.7-180576.20" + attribute \src "libresoc.v:182672.7-182672.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180621.3-180629.6" - wire $0\q_int$next[0:0]$11897 - attribute \src "libresoc.v:180619.3-180620.27" + attribute \src "libresoc.v:182717.3-182725.6" + wire $0\q_int$next[0:0]$11948 + attribute \src "libresoc.v:182715.3-182716.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:180621.3-180629.6" - wire $1\q_int$next[0:0]$11898 - attribute \src "libresoc.v:180598.7-180598.19" + attribute \src "libresoc.v:182717.3-182725.6" + wire $1\q_int$next[0:0]$11949 + attribute \src "libresoc.v:182694.7-182694.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:180611.17-180611.96" - wire $and$libresoc.v:180611$11887_Y - attribute \src "libresoc.v:180616.17-180616.96" - wire $and$libresoc.v:180616$11892_Y - attribute \src "libresoc.v:180613.18-180613.94" - wire $not$libresoc.v:180613$11889_Y - attribute \src "libresoc.v:180615.17-180615.93" - wire $not$libresoc.v:180615$11891_Y - attribute \src "libresoc.v:180618.17-180618.93" - wire $not$libresoc.v:180618$11894_Y - attribute \src "libresoc.v:180612.18-180612.99" - wire $or$libresoc.v:180612$11888_Y - attribute \src "libresoc.v:180614.18-180614.100" - wire $or$libresoc.v:180614$11890_Y - attribute \src "libresoc.v:180617.17-180617.98" - wire $or$libresoc.v:180617$11893_Y + attribute \src "libresoc.v:182707.17-182707.96" + wire $and$libresoc.v:182707$11938_Y + attribute \src "libresoc.v:182712.17-182712.96" + wire $and$libresoc.v:182712$11943_Y + attribute \src "libresoc.v:182709.18-182709.94" + wire $not$libresoc.v:182709$11940_Y + attribute \src "libresoc.v:182711.17-182711.93" + wire $not$libresoc.v:182711$11942_Y + attribute \src "libresoc.v:182714.17-182714.93" + wire $not$libresoc.v:182714$11945_Y + attribute \src "libresoc.v:182708.18-182708.99" + wire $or$libresoc.v:182708$11939_Y + attribute \src "libresoc.v:182710.18-182710.100" + wire $or$libresoc.v:182710$11941_Y + attribute \src "libresoc.v:182713.17-182713.98" + wire $or$libresoc.v:182713$11944_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375499,11 +378370,11 @@ module \rok_l$105 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180576.7-180576.15" + attribute \src "libresoc.v:182672.7-182672.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -375520,7 +378391,7 @@ module \rok_l$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:180611$11887 + cell $and $and$libresoc.v:182707$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375528,10 +378399,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180611$11887_Y + connect \Y $and$libresoc.v:182707$11938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:180616$11892 + cell $and $and$libresoc.v:182712$11943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375539,34 +378410,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180616$11892_Y + connect \Y $and$libresoc.v:182712$11943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:180613$11889 + cell $not $not$libresoc.v:182709$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:180613$11889_Y + connect \Y $not$libresoc.v:182709$11940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:180615$11891 + cell $not $not$libresoc.v:182711$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180615$11891_Y + connect \Y $not$libresoc.v:182711$11942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:180618$11894 + cell $not $not$libresoc.v:182714$11945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180618$11894_Y + connect \Y $not$libresoc.v:182714$11945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:180612$11888 + cell $or $or$libresoc.v:182708$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375574,10 +378445,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:180612$11888_Y + connect \Y $or$libresoc.v:182708$11939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:180614$11890 + cell $or $or$libresoc.v:182710$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375585,10 +378456,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:180614$11890_Y + connect \Y $or$libresoc.v:182710$11941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:180617$11893 + cell $or $or$libresoc.v:182713$11944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375596,39 +378467,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:180617$11893_Y + connect \Y $or$libresoc.v:182713$11944_Y end - attribute \src "libresoc.v:180576.7-180576.20" - process $proc$libresoc.v:180576$11899 + attribute \src "libresoc.v:182672.7-182672.20" + process $proc$libresoc.v:182672$11950 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180598.7-180598.19" - process $proc$libresoc.v:180598$11900 + attribute \src "libresoc.v:182694.7-182694.19" + process $proc$libresoc.v:182694$11951 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:180619.3-180620.27" - process $proc$libresoc.v:180619$11895 + attribute \src "libresoc.v:182715.3-182716.27" + process $proc$libresoc.v:182715$11946 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:180621.3-180629.6" - process $proc$libresoc.v:180621$11896 + attribute \src "libresoc.v:182717.3-182725.6" + process $proc$libresoc.v:182717$11947 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11897 $1\q_int$next[0:0]$11898 - attribute \src "libresoc.v:180622.5-180622.29" + assign $0\q_int$next[0:0]$11948 $1\q_int$next[0:0]$11949 + attribute \src "libresoc.v:182718.5-182718.29" switch \initial - attribute \src "libresoc.v:180622.9-180622.17" + attribute \src "libresoc.v:182718.9-182718.17" case 1'1 case end @@ -375637,56 +378508,56 @@ module \rok_l$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11898 1'0 + assign $1\q_int$next[0:0]$11949 1'0 case - assign $1\q_int$next[0:0]$11898 \$5 + assign $1\q_int$next[0:0]$11949 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11897 + update \q_int$next $0\q_int$next[0:0]$11948 end - connect \$9 $and$libresoc.v:180611$11887_Y - connect \$11 $or$libresoc.v:180612$11888_Y - connect \$13 $not$libresoc.v:180613$11889_Y - connect \$15 $or$libresoc.v:180614$11890_Y - connect \$1 $not$libresoc.v:180615$11891_Y - connect \$3 $and$libresoc.v:180616$11892_Y - connect \$5 $or$libresoc.v:180617$11893_Y - connect \$7 $not$libresoc.v:180618$11894_Y + connect \$9 $and$libresoc.v:182707$11938_Y + connect \$11 $or$libresoc.v:182708$11939_Y + connect \$13 $not$libresoc.v:182709$11940_Y + connect \$15 $or$libresoc.v:182710$11941_Y + connect \$1 $not$libresoc.v:182711$11942_Y + connect \$3 $and$libresoc.v:182712$11943_Y + connect \$5 $or$libresoc.v:182713$11944_Y + connect \$7 $not$libresoc.v:182714$11945_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:180637.1-180695.10" +attribute \src "libresoc.v:182733.1-182791.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:180638.7-180638.20" + attribute \src "libresoc.v:182734.7-182734.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180683.3-180691.6" - wire $0\q_int$next[0:0]$11911 - attribute \src "libresoc.v:180681.3-180682.27" + attribute \src "libresoc.v:182779.3-182787.6" + wire $0\q_int$next[0:0]$11962 + attribute \src "libresoc.v:182777.3-182778.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:180683.3-180691.6" - wire $1\q_int$next[0:0]$11912 - attribute \src "libresoc.v:180660.7-180660.19" + attribute \src "libresoc.v:182779.3-182787.6" + wire $1\q_int$next[0:0]$11963 + attribute \src "libresoc.v:182756.7-182756.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:180673.17-180673.96" - wire $and$libresoc.v:180673$11901_Y - attribute \src "libresoc.v:180678.17-180678.96" - wire $and$libresoc.v:180678$11906_Y - attribute \src "libresoc.v:180675.18-180675.94" - wire $not$libresoc.v:180675$11903_Y - attribute \src "libresoc.v:180677.17-180677.93" - wire $not$libresoc.v:180677$11905_Y - attribute \src "libresoc.v:180680.17-180680.93" - wire $not$libresoc.v:180680$11908_Y - attribute \src "libresoc.v:180674.18-180674.99" - wire $or$libresoc.v:180674$11902_Y - attribute \src "libresoc.v:180676.18-180676.100" - wire $or$libresoc.v:180676$11904_Y - attribute \src "libresoc.v:180679.17-180679.98" - wire $or$libresoc.v:180679$11907_Y + attribute \src "libresoc.v:182769.17-182769.96" + wire $and$libresoc.v:182769$11952_Y + attribute \src "libresoc.v:182774.17-182774.96" + wire $and$libresoc.v:182774$11957_Y + attribute \src "libresoc.v:182771.18-182771.94" + wire $not$libresoc.v:182771$11954_Y + attribute \src "libresoc.v:182773.17-182773.93" + wire $not$libresoc.v:182773$11956_Y + attribute \src "libresoc.v:182776.17-182776.93" + wire $not$libresoc.v:182776$11959_Y + attribute \src "libresoc.v:182770.18-182770.99" + wire $or$libresoc.v:182770$11953_Y + attribute \src "libresoc.v:182772.18-182772.100" + wire $or$libresoc.v:182772$11955_Y + attribute \src "libresoc.v:182775.17-182775.98" + wire $or$libresoc.v:182775$11958_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375703,11 +378574,11 @@ module \rok_l$123 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180638.7-180638.15" + attribute \src "libresoc.v:182734.7-182734.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -375724,7 +378595,7 @@ module \rok_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:180673$11901 + cell $and $and$libresoc.v:182769$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375732,10 +378603,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180673$11901_Y + connect \Y $and$libresoc.v:182769$11952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:180678$11906 + cell $and $and$libresoc.v:182774$11957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375743,34 +378614,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180678$11906_Y + connect \Y $and$libresoc.v:182774$11957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:180675$11903 + cell $not $not$libresoc.v:182771$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:180675$11903_Y + connect \Y $not$libresoc.v:182771$11954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:180677$11905 + cell $not $not$libresoc.v:182773$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180677$11905_Y + connect \Y $not$libresoc.v:182773$11956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:180680$11908 + cell $not $not$libresoc.v:182776$11959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180680$11908_Y + connect \Y $not$libresoc.v:182776$11959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:180674$11902 + cell $or $or$libresoc.v:182770$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375778,10 +378649,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:180674$11902_Y + connect \Y $or$libresoc.v:182770$11953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:180676$11904 + cell $or $or$libresoc.v:182772$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375789,10 +378660,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:180676$11904_Y + connect \Y $or$libresoc.v:182772$11955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:180679$11907 + cell $or $or$libresoc.v:182775$11958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375800,39 +378671,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:180679$11907_Y + connect \Y $or$libresoc.v:182775$11958_Y end - attribute \src "libresoc.v:180638.7-180638.20" - process $proc$libresoc.v:180638$11913 + attribute \src "libresoc.v:182734.7-182734.20" + process $proc$libresoc.v:182734$11964 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180660.7-180660.19" - process $proc$libresoc.v:180660$11914 + attribute \src "libresoc.v:182756.7-182756.19" + process $proc$libresoc.v:182756$11965 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:180681.3-180682.27" - process $proc$libresoc.v:180681$11909 + attribute \src "libresoc.v:182777.3-182778.27" + process $proc$libresoc.v:182777$11960 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:180683.3-180691.6" - process $proc$libresoc.v:180683$11910 + attribute \src "libresoc.v:182779.3-182787.6" + process $proc$libresoc.v:182779$11961 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11911 $1\q_int$next[0:0]$11912 - attribute \src "libresoc.v:180684.5-180684.29" + assign $0\q_int$next[0:0]$11962 $1\q_int$next[0:0]$11963 + attribute \src "libresoc.v:182780.5-182780.29" switch \initial - attribute \src "libresoc.v:180684.9-180684.17" + attribute \src "libresoc.v:182780.9-182780.17" case 1'1 case end @@ -375841,56 +378712,56 @@ module \rok_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11912 1'0 + assign $1\q_int$next[0:0]$11963 1'0 case - assign $1\q_int$next[0:0]$11912 \$5 + assign $1\q_int$next[0:0]$11963 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11911 + update \q_int$next $0\q_int$next[0:0]$11962 end - connect \$9 $and$libresoc.v:180673$11901_Y - connect \$11 $or$libresoc.v:180674$11902_Y - connect \$13 $not$libresoc.v:180675$11903_Y - connect \$15 $or$libresoc.v:180676$11904_Y - connect \$1 $not$libresoc.v:180677$11905_Y - connect \$3 $and$libresoc.v:180678$11906_Y - connect \$5 $or$libresoc.v:180679$11907_Y - connect \$7 $not$libresoc.v:180680$11908_Y + connect \$9 $and$libresoc.v:182769$11952_Y + connect \$11 $or$libresoc.v:182770$11953_Y + connect \$13 $not$libresoc.v:182771$11954_Y + connect \$15 $or$libresoc.v:182772$11955_Y + connect \$1 $not$libresoc.v:182773$11956_Y + connect \$3 $and$libresoc.v:182774$11957_Y + connect \$5 $or$libresoc.v:182775$11958_Y + connect \$7 $not$libresoc.v:182776$11959_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:180699.1-180757.10" +attribute \src "libresoc.v:182795.1-182853.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:180700.7-180700.20" + attribute \src "libresoc.v:182796.7-182796.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180745.3-180753.6" - wire $0\q_int$next[0:0]$11925 - attribute \src "libresoc.v:180743.3-180744.27" + attribute \src "libresoc.v:182841.3-182849.6" + wire $0\q_int$next[0:0]$11976 + attribute \src "libresoc.v:182839.3-182840.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:180745.3-180753.6" - wire $1\q_int$next[0:0]$11926 - attribute \src "libresoc.v:180722.7-180722.19" + attribute \src "libresoc.v:182841.3-182849.6" + wire $1\q_int$next[0:0]$11977 + attribute \src "libresoc.v:182818.7-182818.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:180735.17-180735.96" - wire $and$libresoc.v:180735$11915_Y - attribute \src "libresoc.v:180740.17-180740.96" - wire $and$libresoc.v:180740$11920_Y - attribute \src "libresoc.v:180737.18-180737.94" - wire $not$libresoc.v:180737$11917_Y - attribute \src "libresoc.v:180739.17-180739.93" - wire $not$libresoc.v:180739$11919_Y - attribute \src "libresoc.v:180742.17-180742.93" - wire $not$libresoc.v:180742$11922_Y - attribute \src "libresoc.v:180736.18-180736.99" - wire $or$libresoc.v:180736$11916_Y - attribute \src "libresoc.v:180738.18-180738.100" - wire $or$libresoc.v:180738$11918_Y - attribute \src "libresoc.v:180741.17-180741.98" - wire $or$libresoc.v:180741$11921_Y + attribute \src "libresoc.v:182831.17-182831.96" + wire $and$libresoc.v:182831$11966_Y + attribute \src "libresoc.v:182836.17-182836.96" + wire $and$libresoc.v:182836$11971_Y + attribute \src "libresoc.v:182833.18-182833.94" + wire $not$libresoc.v:182833$11968_Y + attribute \src "libresoc.v:182835.17-182835.93" + wire $not$libresoc.v:182835$11970_Y + attribute \src "libresoc.v:182838.17-182838.93" + wire $not$libresoc.v:182838$11973_Y + attribute \src "libresoc.v:182832.18-182832.99" + wire $or$libresoc.v:182832$11967_Y + attribute \src "libresoc.v:182834.18-182834.100" + wire $or$libresoc.v:182834$11969_Y + attribute \src "libresoc.v:182837.17-182837.98" + wire $or$libresoc.v:182837$11972_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375907,11 +378778,11 @@ module \rok_l$14 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180700.7-180700.15" + attribute \src "libresoc.v:182796.7-182796.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -375928,7 +378799,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:180735$11915 + cell $and $and$libresoc.v:182831$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375936,10 +378807,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180735$11915_Y + connect \Y $and$libresoc.v:182831$11966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:180740$11920 + cell $and $and$libresoc.v:182836$11971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375947,34 +378818,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180740$11920_Y + connect \Y $and$libresoc.v:182836$11971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:180737$11917 + cell $not $not$libresoc.v:182833$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:180737$11917_Y + connect \Y $not$libresoc.v:182833$11968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:180739$11919 + cell $not $not$libresoc.v:182835$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180739$11919_Y + connect \Y $not$libresoc.v:182835$11970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:180742$11922 + cell $not $not$libresoc.v:182838$11973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180742$11922_Y + connect \Y $not$libresoc.v:182838$11973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:180736$11916 + cell $or $or$libresoc.v:182832$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375982,10 +378853,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:180736$11916_Y + connect \Y $or$libresoc.v:182832$11967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:180738$11918 + cell $or $or$libresoc.v:182834$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -375993,10 +378864,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:180738$11918_Y + connect \Y $or$libresoc.v:182834$11969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:180741$11921 + cell $or $or$libresoc.v:182837$11972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376004,39 +378875,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:180741$11921_Y + connect \Y $or$libresoc.v:182837$11972_Y end - attribute \src "libresoc.v:180700.7-180700.20" - process $proc$libresoc.v:180700$11927 + attribute \src "libresoc.v:182796.7-182796.20" + process $proc$libresoc.v:182796$11978 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180722.7-180722.19" - process $proc$libresoc.v:180722$11928 + attribute \src "libresoc.v:182818.7-182818.19" + process $proc$libresoc.v:182818$11979 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:180743.3-180744.27" - process $proc$libresoc.v:180743$11923 + attribute \src "libresoc.v:182839.3-182840.27" + process $proc$libresoc.v:182839$11974 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:180745.3-180753.6" - process $proc$libresoc.v:180745$11924 + attribute \src "libresoc.v:182841.3-182849.6" + process $proc$libresoc.v:182841$11975 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11925 $1\q_int$next[0:0]$11926 - attribute \src "libresoc.v:180746.5-180746.29" + assign $0\q_int$next[0:0]$11976 $1\q_int$next[0:0]$11977 + attribute \src "libresoc.v:182842.5-182842.29" switch \initial - attribute \src "libresoc.v:180746.9-180746.17" + attribute \src "libresoc.v:182842.9-182842.17" case 1'1 case end @@ -376045,56 +378916,56 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11926 1'0 + assign $1\q_int$next[0:0]$11977 1'0 case - assign $1\q_int$next[0:0]$11926 \$5 + assign $1\q_int$next[0:0]$11977 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11925 + update \q_int$next $0\q_int$next[0:0]$11976 end - connect \$9 $and$libresoc.v:180735$11915_Y - connect \$11 $or$libresoc.v:180736$11916_Y - connect \$13 $not$libresoc.v:180737$11917_Y - connect \$15 $or$libresoc.v:180738$11918_Y - connect \$1 $not$libresoc.v:180739$11919_Y - connect \$3 $and$libresoc.v:180740$11920_Y - connect \$5 $or$libresoc.v:180741$11921_Y - connect \$7 $not$libresoc.v:180742$11922_Y + connect \$9 $and$libresoc.v:182831$11966_Y + connect \$11 $or$libresoc.v:182832$11967_Y + connect \$13 $not$libresoc.v:182833$11968_Y + connect \$15 $or$libresoc.v:182834$11969_Y + connect \$1 $not$libresoc.v:182835$11970_Y + connect \$3 $and$libresoc.v:182836$11971_Y + connect \$5 $or$libresoc.v:182837$11972_Y + connect \$7 $not$libresoc.v:182838$11973_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:180761.1-180819.10" +attribute \src "libresoc.v:182857.1-182915.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:180762.7-180762.20" + attribute \src "libresoc.v:182858.7-182858.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180807.3-180815.6" - wire $0\q_int$next[0:0]$11939 - attribute \src "libresoc.v:180805.3-180806.27" + attribute \src "libresoc.v:182903.3-182911.6" + wire $0\q_int$next[0:0]$11990 + attribute \src "libresoc.v:182901.3-182902.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:180807.3-180815.6" - wire $1\q_int$next[0:0]$11940 - attribute \src "libresoc.v:180784.7-180784.19" + attribute \src "libresoc.v:182903.3-182911.6" + wire $1\q_int$next[0:0]$11991 + attribute \src "libresoc.v:182880.7-182880.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:180797.17-180797.96" - wire $and$libresoc.v:180797$11929_Y - attribute \src "libresoc.v:180802.17-180802.96" - wire $and$libresoc.v:180802$11934_Y - attribute \src "libresoc.v:180799.18-180799.94" - wire $not$libresoc.v:180799$11931_Y - attribute \src "libresoc.v:180801.17-180801.93" - wire $not$libresoc.v:180801$11933_Y - attribute \src "libresoc.v:180804.17-180804.93" - wire $not$libresoc.v:180804$11936_Y - attribute \src "libresoc.v:180798.18-180798.99" - wire $or$libresoc.v:180798$11930_Y - attribute \src "libresoc.v:180800.18-180800.100" - wire $or$libresoc.v:180800$11932_Y - attribute \src "libresoc.v:180803.17-180803.98" - wire $or$libresoc.v:180803$11935_Y + attribute \src "libresoc.v:182893.17-182893.96" + wire $and$libresoc.v:182893$11980_Y + attribute \src "libresoc.v:182898.17-182898.96" + wire $and$libresoc.v:182898$11985_Y + attribute \src "libresoc.v:182895.18-182895.94" + wire $not$libresoc.v:182895$11982_Y + attribute \src "libresoc.v:182897.17-182897.93" + wire $not$libresoc.v:182897$11984_Y + attribute \src "libresoc.v:182900.17-182900.93" + wire $not$libresoc.v:182900$11987_Y + attribute \src "libresoc.v:182894.18-182894.99" + wire $or$libresoc.v:182894$11981_Y + attribute \src "libresoc.v:182896.18-182896.100" + wire $or$libresoc.v:182896$11983_Y + attribute \src "libresoc.v:182899.17-182899.98" + wire $or$libresoc.v:182899$11986_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376111,11 +378982,11 @@ module \rok_l$27 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180762.7-180762.15" + attribute \src "libresoc.v:182858.7-182858.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376132,7 +379003,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:180797$11929 + cell $and $and$libresoc.v:182893$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376140,10 +379011,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180797$11929_Y + connect \Y $and$libresoc.v:182893$11980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:180802$11934 + cell $and $and$libresoc.v:182898$11985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376151,34 +379022,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180802$11934_Y + connect \Y $and$libresoc.v:182898$11985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:180799$11931 + cell $not $not$libresoc.v:182895$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:180799$11931_Y + connect \Y $not$libresoc.v:182895$11982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:180801$11933 + cell $not $not$libresoc.v:182897$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180801$11933_Y + connect \Y $not$libresoc.v:182897$11984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:180804$11936 + cell $not $not$libresoc.v:182900$11987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180804$11936_Y + connect \Y $not$libresoc.v:182900$11987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:180798$11930 + cell $or $or$libresoc.v:182894$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376186,10 +379057,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:180798$11930_Y + connect \Y $or$libresoc.v:182894$11981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:180800$11932 + cell $or $or$libresoc.v:182896$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376197,10 +379068,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:180800$11932_Y + connect \Y $or$libresoc.v:182896$11983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:180803$11935 + cell $or $or$libresoc.v:182899$11986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376208,39 +379079,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:180803$11935_Y + connect \Y $or$libresoc.v:182899$11986_Y end - attribute \src "libresoc.v:180762.7-180762.20" - process $proc$libresoc.v:180762$11941 + attribute \src "libresoc.v:182858.7-182858.20" + process $proc$libresoc.v:182858$11992 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180784.7-180784.19" - process $proc$libresoc.v:180784$11942 + attribute \src "libresoc.v:182880.7-182880.19" + process $proc$libresoc.v:182880$11993 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:180805.3-180806.27" - process $proc$libresoc.v:180805$11937 + attribute \src "libresoc.v:182901.3-182902.27" + process $proc$libresoc.v:182901$11988 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:180807.3-180815.6" - process $proc$libresoc.v:180807$11938 + attribute \src "libresoc.v:182903.3-182911.6" + process $proc$libresoc.v:182903$11989 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11939 $1\q_int$next[0:0]$11940 - attribute \src "libresoc.v:180808.5-180808.29" + assign $0\q_int$next[0:0]$11990 $1\q_int$next[0:0]$11991 + attribute \src "libresoc.v:182904.5-182904.29" switch \initial - attribute \src "libresoc.v:180808.9-180808.17" + attribute \src "libresoc.v:182904.9-182904.17" case 1'1 case end @@ -376249,56 +379120,56 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11940 1'0 + assign $1\q_int$next[0:0]$11991 1'0 case - assign $1\q_int$next[0:0]$11940 \$5 + assign $1\q_int$next[0:0]$11991 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11939 + update \q_int$next $0\q_int$next[0:0]$11990 end - connect \$9 $and$libresoc.v:180797$11929_Y - connect \$11 $or$libresoc.v:180798$11930_Y - connect \$13 $not$libresoc.v:180799$11931_Y - connect \$15 $or$libresoc.v:180800$11932_Y - connect \$1 $not$libresoc.v:180801$11933_Y - connect \$3 $and$libresoc.v:180802$11934_Y - connect \$5 $or$libresoc.v:180803$11935_Y - connect \$7 $not$libresoc.v:180804$11936_Y + connect \$9 $and$libresoc.v:182893$11980_Y + connect \$11 $or$libresoc.v:182894$11981_Y + connect \$13 $not$libresoc.v:182895$11982_Y + connect \$15 $or$libresoc.v:182896$11983_Y + connect \$1 $not$libresoc.v:182897$11984_Y + connect \$3 $and$libresoc.v:182898$11985_Y + connect \$5 $or$libresoc.v:182899$11986_Y + connect \$7 $not$libresoc.v:182900$11987_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:180823.1-180881.10" +attribute \src "libresoc.v:182919.1-182977.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:180824.7-180824.20" + attribute \src "libresoc.v:182920.7-182920.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180869.3-180877.6" - wire $0\q_int$next[0:0]$11953 - attribute \src "libresoc.v:180867.3-180868.27" + attribute \src "libresoc.v:182965.3-182973.6" + wire $0\q_int$next[0:0]$12004 + attribute \src "libresoc.v:182963.3-182964.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:180869.3-180877.6" - wire $1\q_int$next[0:0]$11954 - attribute \src "libresoc.v:180846.7-180846.19" + attribute \src "libresoc.v:182965.3-182973.6" + wire $1\q_int$next[0:0]$12005 + attribute \src "libresoc.v:182942.7-182942.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:180859.17-180859.96" - wire $and$libresoc.v:180859$11943_Y - attribute \src "libresoc.v:180864.17-180864.96" - wire $and$libresoc.v:180864$11948_Y - attribute \src "libresoc.v:180861.18-180861.94" - wire $not$libresoc.v:180861$11945_Y - attribute \src "libresoc.v:180863.17-180863.93" - wire $not$libresoc.v:180863$11947_Y - attribute \src "libresoc.v:180866.17-180866.93" - wire $not$libresoc.v:180866$11950_Y - attribute \src "libresoc.v:180860.18-180860.99" - wire $or$libresoc.v:180860$11944_Y - attribute \src "libresoc.v:180862.18-180862.100" - wire $or$libresoc.v:180862$11946_Y - attribute \src "libresoc.v:180865.17-180865.98" - wire $or$libresoc.v:180865$11949_Y + attribute \src "libresoc.v:182955.17-182955.96" + wire $and$libresoc.v:182955$11994_Y + attribute \src "libresoc.v:182960.17-182960.96" + wire $and$libresoc.v:182960$11999_Y + attribute \src "libresoc.v:182957.18-182957.94" + wire $not$libresoc.v:182957$11996_Y + attribute \src "libresoc.v:182959.17-182959.93" + wire $not$libresoc.v:182959$11998_Y + attribute \src "libresoc.v:182962.17-182962.93" + wire $not$libresoc.v:182962$12001_Y + attribute \src "libresoc.v:182956.18-182956.99" + wire $or$libresoc.v:182956$11995_Y + attribute \src "libresoc.v:182958.18-182958.100" + wire $or$libresoc.v:182958$11997_Y + attribute \src "libresoc.v:182961.17-182961.98" + wire $or$libresoc.v:182961$12000_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376315,11 +379186,11 @@ module \rok_l$43 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180824.7-180824.15" + attribute \src "libresoc.v:182920.7-182920.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376336,7 +379207,7 @@ module \rok_l$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:180859$11943 + cell $and $and$libresoc.v:182955$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376344,10 +379215,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180859$11943_Y + connect \Y $and$libresoc.v:182955$11994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:180864$11948 + cell $and $and$libresoc.v:182960$11999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376355,34 +379226,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180864$11948_Y + connect \Y $and$libresoc.v:182960$11999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:180861$11945 + cell $not $not$libresoc.v:182957$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:180861$11945_Y + connect \Y $not$libresoc.v:182957$11996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:180863$11947 + cell $not $not$libresoc.v:182959$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180863$11947_Y + connect \Y $not$libresoc.v:182959$11998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:180866$11950 + cell $not $not$libresoc.v:182962$12001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180866$11950_Y + connect \Y $not$libresoc.v:182962$12001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:180860$11944 + cell $or $or$libresoc.v:182956$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376390,10 +379261,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:180860$11944_Y + connect \Y $or$libresoc.v:182956$11995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:180862$11946 + cell $or $or$libresoc.v:182958$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376401,10 +379272,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:180862$11946_Y + connect \Y $or$libresoc.v:182958$11997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:180865$11949 + cell $or $or$libresoc.v:182961$12000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376412,39 +379283,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:180865$11949_Y + connect \Y $or$libresoc.v:182961$12000_Y end - attribute \src "libresoc.v:180824.7-180824.20" - process $proc$libresoc.v:180824$11955 + attribute \src "libresoc.v:182920.7-182920.20" + process $proc$libresoc.v:182920$12006 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180846.7-180846.19" - process $proc$libresoc.v:180846$11956 + attribute \src "libresoc.v:182942.7-182942.19" + process $proc$libresoc.v:182942$12007 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:180867.3-180868.27" - process $proc$libresoc.v:180867$11951 + attribute \src "libresoc.v:182963.3-182964.27" + process $proc$libresoc.v:182963$12002 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:180869.3-180877.6" - process $proc$libresoc.v:180869$11952 + attribute \src "libresoc.v:182965.3-182973.6" + process $proc$libresoc.v:182965$12003 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11953 $1\q_int$next[0:0]$11954 - attribute \src "libresoc.v:180870.5-180870.29" + assign $0\q_int$next[0:0]$12004 $1\q_int$next[0:0]$12005 + attribute \src "libresoc.v:182966.5-182966.29" switch \initial - attribute \src "libresoc.v:180870.9-180870.17" + attribute \src "libresoc.v:182966.9-182966.17" case 1'1 case end @@ -376453,56 +379324,56 @@ module \rok_l$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11954 1'0 + assign $1\q_int$next[0:0]$12005 1'0 case - assign $1\q_int$next[0:0]$11954 \$5 + assign $1\q_int$next[0:0]$12005 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11953 + update \q_int$next $0\q_int$next[0:0]$12004 end - connect \$9 $and$libresoc.v:180859$11943_Y - connect \$11 $or$libresoc.v:180860$11944_Y - connect \$13 $not$libresoc.v:180861$11945_Y - connect \$15 $or$libresoc.v:180862$11946_Y - connect \$1 $not$libresoc.v:180863$11947_Y - connect \$3 $and$libresoc.v:180864$11948_Y - connect \$5 $or$libresoc.v:180865$11949_Y - connect \$7 $not$libresoc.v:180866$11950_Y + connect \$9 $and$libresoc.v:182955$11994_Y + connect \$11 $or$libresoc.v:182956$11995_Y + connect \$13 $not$libresoc.v:182957$11996_Y + connect \$15 $or$libresoc.v:182958$11997_Y + connect \$1 $not$libresoc.v:182959$11998_Y + connect \$3 $and$libresoc.v:182960$11999_Y + connect \$5 $or$libresoc.v:182961$12000_Y + connect \$7 $not$libresoc.v:182962$12001_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:180885.1-180943.10" +attribute \src "libresoc.v:182981.1-183039.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:180886.7-180886.20" + attribute \src "libresoc.v:182982.7-182982.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180931.3-180939.6" - wire $0\q_int$next[0:0]$11967 - attribute \src "libresoc.v:180929.3-180930.27" + attribute \src "libresoc.v:183027.3-183035.6" + wire $0\q_int$next[0:0]$12018 + attribute \src "libresoc.v:183025.3-183026.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:180931.3-180939.6" - wire $1\q_int$next[0:0]$11968 - attribute \src "libresoc.v:180908.7-180908.19" + attribute \src "libresoc.v:183027.3-183035.6" + wire $1\q_int$next[0:0]$12019 + attribute \src "libresoc.v:183004.7-183004.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:180921.17-180921.96" - wire $and$libresoc.v:180921$11957_Y - attribute \src "libresoc.v:180926.17-180926.96" - wire $and$libresoc.v:180926$11962_Y - attribute \src "libresoc.v:180923.18-180923.94" - wire $not$libresoc.v:180923$11959_Y - attribute \src "libresoc.v:180925.17-180925.93" - wire $not$libresoc.v:180925$11961_Y - attribute \src "libresoc.v:180928.17-180928.93" - wire $not$libresoc.v:180928$11964_Y - attribute \src "libresoc.v:180922.18-180922.99" - wire $or$libresoc.v:180922$11958_Y - attribute \src "libresoc.v:180924.18-180924.100" - wire $or$libresoc.v:180924$11960_Y - attribute \src "libresoc.v:180927.17-180927.98" - wire $or$libresoc.v:180927$11963_Y + attribute \src "libresoc.v:183017.17-183017.96" + wire $and$libresoc.v:183017$12008_Y + attribute \src "libresoc.v:183022.17-183022.96" + wire $and$libresoc.v:183022$12013_Y + attribute \src "libresoc.v:183019.18-183019.94" + wire $not$libresoc.v:183019$12010_Y + attribute \src "libresoc.v:183021.17-183021.93" + wire $not$libresoc.v:183021$12012_Y + attribute \src "libresoc.v:183024.17-183024.93" + wire $not$libresoc.v:183024$12015_Y + attribute \src "libresoc.v:183018.18-183018.99" + wire $or$libresoc.v:183018$12009_Y + attribute \src "libresoc.v:183020.18-183020.100" + wire $or$libresoc.v:183020$12011_Y + attribute \src "libresoc.v:183023.17-183023.98" + wire $or$libresoc.v:183023$12014_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376519,11 +379390,11 @@ module \rok_l$59 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180886.7-180886.15" + attribute \src "libresoc.v:182982.7-182982.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376540,7 +379411,7 @@ module \rok_l$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:180921$11957 + cell $and $and$libresoc.v:183017$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376548,10 +379419,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180921$11957_Y + connect \Y $and$libresoc.v:183017$12008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:180926$11962 + cell $and $and$libresoc.v:183022$12013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376559,34 +379430,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180926$11962_Y + connect \Y $and$libresoc.v:183022$12013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:180923$11959 + cell $not $not$libresoc.v:183019$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:180923$11959_Y + connect \Y $not$libresoc.v:183019$12010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:180925$11961 + cell $not $not$libresoc.v:183021$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180925$11961_Y + connect \Y $not$libresoc.v:183021$12012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:180928$11964 + cell $not $not$libresoc.v:183024$12015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180928$11964_Y + connect \Y $not$libresoc.v:183024$12015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:180922$11958 + cell $or $or$libresoc.v:183018$12009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376594,10 +379465,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:180922$11958_Y + connect \Y $or$libresoc.v:183018$12009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:180924$11960 + cell $or $or$libresoc.v:183020$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376605,10 +379476,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:180924$11960_Y + connect \Y $or$libresoc.v:183020$12011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:180927$11963 + cell $or $or$libresoc.v:183023$12014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376616,39 +379487,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:180927$11963_Y + connect \Y $or$libresoc.v:183023$12014_Y end - attribute \src "libresoc.v:180886.7-180886.20" - process $proc$libresoc.v:180886$11969 + attribute \src "libresoc.v:182982.7-182982.20" + process $proc$libresoc.v:182982$12020 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180908.7-180908.19" - process $proc$libresoc.v:180908$11970 + attribute \src "libresoc.v:183004.7-183004.19" + process $proc$libresoc.v:183004$12021 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:180929.3-180930.27" - process $proc$libresoc.v:180929$11965 + attribute \src "libresoc.v:183025.3-183026.27" + process $proc$libresoc.v:183025$12016 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:180931.3-180939.6" - process $proc$libresoc.v:180931$11966 + attribute \src "libresoc.v:183027.3-183035.6" + process $proc$libresoc.v:183027$12017 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11967 $1\q_int$next[0:0]$11968 - attribute \src "libresoc.v:180932.5-180932.29" + assign $0\q_int$next[0:0]$12018 $1\q_int$next[0:0]$12019 + attribute \src "libresoc.v:183028.5-183028.29" switch \initial - attribute \src "libresoc.v:180932.9-180932.17" + attribute \src "libresoc.v:183028.9-183028.17" case 1'1 case end @@ -376657,56 +379528,56 @@ module \rok_l$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11968 1'0 + assign $1\q_int$next[0:0]$12019 1'0 case - assign $1\q_int$next[0:0]$11968 \$5 + assign $1\q_int$next[0:0]$12019 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11967 + update \q_int$next $0\q_int$next[0:0]$12018 end - connect \$9 $and$libresoc.v:180921$11957_Y - connect \$11 $or$libresoc.v:180922$11958_Y - connect \$13 $not$libresoc.v:180923$11959_Y - connect \$15 $or$libresoc.v:180924$11960_Y - connect \$1 $not$libresoc.v:180925$11961_Y - connect \$3 $and$libresoc.v:180926$11962_Y - connect \$5 $or$libresoc.v:180927$11963_Y - connect \$7 $not$libresoc.v:180928$11964_Y + connect \$9 $and$libresoc.v:183017$12008_Y + connect \$11 $or$libresoc.v:183018$12009_Y + connect \$13 $not$libresoc.v:183019$12010_Y + connect \$15 $or$libresoc.v:183020$12011_Y + connect \$1 $not$libresoc.v:183021$12012_Y + connect \$3 $and$libresoc.v:183022$12013_Y + connect \$5 $or$libresoc.v:183023$12014_Y + connect \$7 $not$libresoc.v:183024$12015_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:180947.1-181005.10" +attribute \src "libresoc.v:183043.1-183101.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:180948.7-180948.20" + attribute \src "libresoc.v:183044.7-183044.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180993.3-181001.6" - wire $0\q_int$next[0:0]$11981 - attribute \src "libresoc.v:180991.3-180992.27" + attribute \src "libresoc.v:183089.3-183097.6" + wire $0\q_int$next[0:0]$12032 + attribute \src "libresoc.v:183087.3-183088.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:180993.3-181001.6" - wire $1\q_int$next[0:0]$11982 - attribute \src "libresoc.v:180970.7-180970.19" + attribute \src "libresoc.v:183089.3-183097.6" + wire $1\q_int$next[0:0]$12033 + attribute \src "libresoc.v:183066.7-183066.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:180983.17-180983.96" - wire $and$libresoc.v:180983$11971_Y - attribute \src "libresoc.v:180988.17-180988.96" - wire $and$libresoc.v:180988$11976_Y - attribute \src "libresoc.v:180985.18-180985.94" - wire $not$libresoc.v:180985$11973_Y - attribute \src "libresoc.v:180987.17-180987.93" - wire $not$libresoc.v:180987$11975_Y - attribute \src "libresoc.v:180990.17-180990.93" - wire $not$libresoc.v:180990$11978_Y - attribute \src "libresoc.v:180984.18-180984.99" - wire $or$libresoc.v:180984$11972_Y - attribute \src "libresoc.v:180986.18-180986.100" - wire $or$libresoc.v:180986$11974_Y - attribute \src "libresoc.v:180989.17-180989.98" - wire $or$libresoc.v:180989$11977_Y + attribute \src "libresoc.v:183079.17-183079.96" + wire $and$libresoc.v:183079$12022_Y + attribute \src "libresoc.v:183084.17-183084.96" + wire $and$libresoc.v:183084$12027_Y + attribute \src "libresoc.v:183081.18-183081.94" + wire $not$libresoc.v:183081$12024_Y + attribute \src "libresoc.v:183083.17-183083.93" + wire $not$libresoc.v:183083$12026_Y + attribute \src "libresoc.v:183086.17-183086.93" + wire $not$libresoc.v:183086$12029_Y + attribute \src "libresoc.v:183080.18-183080.99" + wire $or$libresoc.v:183080$12023_Y + attribute \src "libresoc.v:183082.18-183082.100" + wire $or$libresoc.v:183082$12025_Y + attribute \src "libresoc.v:183085.17-183085.98" + wire $or$libresoc.v:183085$12028_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376723,11 +379594,11 @@ module \rok_l$71 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:180948.7-180948.15" + attribute \src "libresoc.v:183044.7-183044.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376744,7 +379615,7 @@ module \rok_l$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:180983$11971 + cell $and $and$libresoc.v:183079$12022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376752,10 +379623,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:180983$11971_Y + connect \Y $and$libresoc.v:183079$12022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:180988$11976 + cell $and $and$libresoc.v:183084$12027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376763,34 +379634,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:180988$11976_Y + connect \Y $and$libresoc.v:183084$12027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:180985$11973 + cell $not $not$libresoc.v:183081$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:180985$11973_Y + connect \Y $not$libresoc.v:183081$12024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:180987$11975 + cell $not $not$libresoc.v:183083$12026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180987$11975_Y + connect \Y $not$libresoc.v:183083$12026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:180990$11978 + cell $not $not$libresoc.v:183086$12029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:180990$11978_Y + connect \Y $not$libresoc.v:183086$12029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:180984$11972 + cell $or $or$libresoc.v:183080$12023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376798,10 +379669,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:180984$11972_Y + connect \Y $or$libresoc.v:183080$12023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:180986$11974 + cell $or $or$libresoc.v:183082$12025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376809,10 +379680,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:180986$11974_Y + connect \Y $or$libresoc.v:183082$12025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:180989$11977 + cell $or $or$libresoc.v:183085$12028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376820,39 +379691,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:180989$11977_Y + connect \Y $or$libresoc.v:183085$12028_Y end - attribute \src "libresoc.v:180948.7-180948.20" - process $proc$libresoc.v:180948$11983 + attribute \src "libresoc.v:183044.7-183044.20" + process $proc$libresoc.v:183044$12034 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180970.7-180970.19" - process $proc$libresoc.v:180970$11984 + attribute \src "libresoc.v:183066.7-183066.19" + process $proc$libresoc.v:183066$12035 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:180991.3-180992.27" - process $proc$libresoc.v:180991$11979 + attribute \src "libresoc.v:183087.3-183088.27" + process $proc$libresoc.v:183087$12030 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:180993.3-181001.6" - process $proc$libresoc.v:180993$11980 + attribute \src "libresoc.v:183089.3-183097.6" + process $proc$libresoc.v:183089$12031 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11981 $1\q_int$next[0:0]$11982 - attribute \src "libresoc.v:180994.5-180994.29" + assign $0\q_int$next[0:0]$12032 $1\q_int$next[0:0]$12033 + attribute \src "libresoc.v:183090.5-183090.29" switch \initial - attribute \src "libresoc.v:180994.9-180994.17" + attribute \src "libresoc.v:183090.9-183090.17" case 1'1 case end @@ -376861,56 +379732,56 @@ module \rok_l$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11982 1'0 + assign $1\q_int$next[0:0]$12033 1'0 case - assign $1\q_int$next[0:0]$11982 \$5 + assign $1\q_int$next[0:0]$12033 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11981 + update \q_int$next $0\q_int$next[0:0]$12032 end - connect \$9 $and$libresoc.v:180983$11971_Y - connect \$11 $or$libresoc.v:180984$11972_Y - connect \$13 $not$libresoc.v:180985$11973_Y - connect \$15 $or$libresoc.v:180986$11974_Y - connect \$1 $not$libresoc.v:180987$11975_Y - connect \$3 $and$libresoc.v:180988$11976_Y - connect \$5 $or$libresoc.v:180989$11977_Y - connect \$7 $not$libresoc.v:180990$11978_Y + connect \$9 $and$libresoc.v:183079$12022_Y + connect \$11 $or$libresoc.v:183080$12023_Y + connect \$13 $not$libresoc.v:183081$12024_Y + connect \$15 $or$libresoc.v:183082$12025_Y + connect \$1 $not$libresoc.v:183083$12026_Y + connect \$3 $and$libresoc.v:183084$12027_Y + connect \$5 $or$libresoc.v:183085$12028_Y + connect \$7 $not$libresoc.v:183086$12029_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:181009.1-181067.10" +attribute \src "libresoc.v:183105.1-183163.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:181010.7-181010.20" + attribute \src "libresoc.v:183106.7-183106.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181055.3-181063.6" - wire $0\q_int$next[0:0]$11995 - attribute \src "libresoc.v:181053.3-181054.27" + attribute \src "libresoc.v:183151.3-183159.6" + wire $0\q_int$next[0:0]$12046 + attribute \src "libresoc.v:183149.3-183150.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181055.3-181063.6" - wire $1\q_int$next[0:0]$11996 - attribute \src "libresoc.v:181032.7-181032.19" + attribute \src "libresoc.v:183151.3-183159.6" + wire $1\q_int$next[0:0]$12047 + attribute \src "libresoc.v:183128.7-183128.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181045.17-181045.96" - wire $and$libresoc.v:181045$11985_Y - attribute \src "libresoc.v:181050.17-181050.96" - wire $and$libresoc.v:181050$11990_Y - attribute \src "libresoc.v:181047.18-181047.94" - wire $not$libresoc.v:181047$11987_Y - attribute \src "libresoc.v:181049.17-181049.93" - wire $not$libresoc.v:181049$11989_Y - attribute \src "libresoc.v:181052.17-181052.93" - wire $not$libresoc.v:181052$11992_Y - attribute \src "libresoc.v:181046.18-181046.99" - wire $or$libresoc.v:181046$11986_Y - attribute \src "libresoc.v:181048.18-181048.100" - wire $or$libresoc.v:181048$11988_Y - attribute \src "libresoc.v:181051.17-181051.98" - wire $or$libresoc.v:181051$11991_Y + attribute \src "libresoc.v:183141.17-183141.96" + wire $and$libresoc.v:183141$12036_Y + attribute \src "libresoc.v:183146.17-183146.96" + wire $and$libresoc.v:183146$12041_Y + attribute \src "libresoc.v:183143.18-183143.94" + wire $not$libresoc.v:183143$12038_Y + attribute \src "libresoc.v:183145.17-183145.93" + wire $not$libresoc.v:183145$12040_Y + attribute \src "libresoc.v:183148.17-183148.93" + wire $not$libresoc.v:183148$12043_Y + attribute \src "libresoc.v:183142.18-183142.99" + wire $or$libresoc.v:183142$12037_Y + attribute \src "libresoc.v:183144.18-183144.100" + wire $or$libresoc.v:183144$12039_Y + attribute \src "libresoc.v:183147.17-183147.98" + wire $or$libresoc.v:183147$12042_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376927,11 +379798,11 @@ module \rok_l$88 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181010.7-181010.15" + attribute \src "libresoc.v:183106.7-183106.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376948,7 +379819,7 @@ module \rok_l$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181045$11985 + cell $and $and$libresoc.v:183141$12036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376956,10 +379827,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181045$11985_Y + connect \Y $and$libresoc.v:183141$12036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181050$11990 + cell $and $and$libresoc.v:183146$12041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376967,34 +379838,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181050$11990_Y + connect \Y $and$libresoc.v:183146$12041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181047$11987 + cell $not $not$libresoc.v:183143$12038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:181047$11987_Y + connect \Y $not$libresoc.v:183143$12038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181049$11989 + cell $not $not$libresoc.v:183145$12040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:181049$11989_Y + connect \Y $not$libresoc.v:183145$12040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181052$11992 + cell $not $not$libresoc.v:183148$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:181052$11992_Y + connect \Y $not$libresoc.v:183148$12043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181046$11986 + cell $or $or$libresoc.v:183142$12037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377002,10 +379873,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:181046$11986_Y + connect \Y $or$libresoc.v:183142$12037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181048$11988 + cell $or $or$libresoc.v:183144$12039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377013,10 +379884,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:181048$11988_Y + connect \Y $or$libresoc.v:183144$12039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181051$11991 + cell $or $or$libresoc.v:183147$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377024,39 +379895,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:181051$11991_Y + connect \Y $or$libresoc.v:183147$12042_Y end - attribute \src "libresoc.v:181010.7-181010.20" - process $proc$libresoc.v:181010$11997 + attribute \src "libresoc.v:183106.7-183106.20" + process $proc$libresoc.v:183106$12048 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181032.7-181032.19" - process $proc$libresoc.v:181032$11998 + attribute \src "libresoc.v:183128.7-183128.19" + process $proc$libresoc.v:183128$12049 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181053.3-181054.27" - process $proc$libresoc.v:181053$11993 + attribute \src "libresoc.v:183149.3-183150.27" + process $proc$libresoc.v:183149$12044 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181055.3-181063.6" - process $proc$libresoc.v:181055$11994 + attribute \src "libresoc.v:183151.3-183159.6" + process $proc$libresoc.v:183151$12045 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11995 $1\q_int$next[0:0]$11996 - attribute \src "libresoc.v:181056.5-181056.29" + assign $0\q_int$next[0:0]$12046 $1\q_int$next[0:0]$12047 + attribute \src "libresoc.v:183152.5-183152.29" switch \initial - attribute \src "libresoc.v:181056.9-181056.17" + attribute \src "libresoc.v:183152.9-183152.17" case 1'1 case end @@ -377065,150 +379936,150 @@ module \rok_l$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11996 1'0 + assign $1\q_int$next[0:0]$12047 1'0 case - assign $1\q_int$next[0:0]$11996 \$5 + assign $1\q_int$next[0:0]$12047 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11995 + update \q_int$next $0\q_int$next[0:0]$12046 end - connect \$9 $and$libresoc.v:181045$11985_Y - connect \$11 $or$libresoc.v:181046$11986_Y - connect \$13 $not$libresoc.v:181047$11987_Y - connect \$15 $or$libresoc.v:181048$11988_Y - connect \$1 $not$libresoc.v:181049$11989_Y - connect \$3 $and$libresoc.v:181050$11990_Y - connect \$5 $or$libresoc.v:181051$11991_Y - connect \$7 $not$libresoc.v:181052$11992_Y + connect \$9 $and$libresoc.v:183141$12036_Y + connect \$11 $or$libresoc.v:183142$12037_Y + connect \$13 $not$libresoc.v:183143$12038_Y + connect \$15 $or$libresoc.v:183144$12039_Y + connect \$1 $not$libresoc.v:183145$12040_Y + connect \$3 $and$libresoc.v:183146$12041_Y + connect \$5 $or$libresoc.v:183147$12042_Y + connect \$7 $not$libresoc.v:183148$12043_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:181071.1-181422.10" +attribute \src "libresoc.v:183167.1-183518.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:181340.3-181349.6" + attribute \src "libresoc.v:183436.3-183445.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:181272.3-181286.6" + attribute \src "libresoc.v:183368.3-183382.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:181072.7-181072.20" + attribute \src "libresoc.v:183168.7-183168.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181362.3-181395.6" - wire width 7 $0\mb$8[6:0]$12046 - attribute \src "libresoc.v:181396.3-181410.6" - wire width 7 $0\me$13[6:0]$12051 - attribute \src "libresoc.v:181297.3-181308.6" + attribute \src "libresoc.v:183458.3-183491.6" + wire width 7 $0\mb$8[6:0]$12097 + attribute \src "libresoc.v:183492.3-183506.6" + wire width 7 $0\me$13[6:0]$12102 + attribute \src "libresoc.v:183393.3-183404.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:181309.3-181320.6" + attribute \src "libresoc.v:183405.3-183416.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:181321.3-181339.6" + attribute \src "libresoc.v:183417.3-183435.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:181287.3-181296.6" + attribute \src "libresoc.v:183383.3-183392.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:181350.3-181361.6" + attribute \src "libresoc.v:183446.3-183457.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:181340.3-181349.6" + attribute \src "libresoc.v:183436.3-183445.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:181272.3-181286.6" + attribute \src "libresoc.v:183368.3-183382.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:181362.3-181395.6" - wire width 7 $1\mb$8[6:0]$12047 - attribute \src "libresoc.v:181396.3-181410.6" - wire width 7 $1\me$13[6:0]$12052 - attribute \src "libresoc.v:181297.3-181308.6" + attribute \src "libresoc.v:183458.3-183491.6" + wire width 7 $1\mb$8[6:0]$12098 + attribute \src "libresoc.v:183492.3-183506.6" + wire width 7 $1\me$13[6:0]$12103 + attribute \src "libresoc.v:183393.3-183404.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:181309.3-181320.6" + attribute \src "libresoc.v:183405.3-183416.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:181321.3-181339.6" + attribute \src "libresoc.v:183417.3-183435.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:181287.3-181296.6" + attribute \src "libresoc.v:183383.3-183392.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:181350.3-181361.6" + attribute \src "libresoc.v:183446.3-183457.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:181362.3-181395.6" - wire width 2 $2\mb$8[6:5]$12048 - attribute \src "libresoc.v:181362.3-181395.6" - wire width 2 $3\mb$8[6:5]$12049 - attribute \src "libresoc.v:181223.18-181223.118" - wire $and$libresoc.v:181223$12002_Y - attribute \src "libresoc.v:181225.18-181225.114" - wire $and$libresoc.v:181225$12004_Y - attribute \src "libresoc.v:181234.18-181234.113" - wire $and$libresoc.v:181234$12013_Y - attribute \src "libresoc.v:181236.18-181236.114" - wire $and$libresoc.v:181236$12015_Y - attribute \src "libresoc.v:181238.18-181238.114" - wire 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$pos$libresoc.v:181221$12000_Y - attribute \src "libresoc.v:181258.18-181258.102" - wire $reduce_or$libresoc.v:181258$12037_Y - attribute \src "libresoc.v:181228.18-181228.109" - wire width 8 $sub$libresoc.v:181228$12007_Y - attribute \src "libresoc.v:181231.18-181231.110" - wire width 8 $sub$libresoc.v:181231$12010_Y + attribute \src "libresoc.v:183458.3-183491.6" + wire width 2 $2\mb$8[6:5]$12099 + attribute \src "libresoc.v:183458.3-183491.6" + wire width 2 $3\mb$8[6:5]$12100 + attribute \src "libresoc.v:183319.18-183319.118" + wire $and$libresoc.v:183319$12053_Y + attribute \src "libresoc.v:183321.18-183321.114" + wire $and$libresoc.v:183321$12055_Y + attribute \src "libresoc.v:183330.18-183330.113" + wire $and$libresoc.v:183330$12064_Y + attribute \src "libresoc.v:183332.18-183332.114" + wire $and$libresoc.v:183332$12066_Y + attribute \src "libresoc.v:183334.18-183334.114" + wire $and$libresoc.v:183334$12068_Y + attribute \src "libresoc.v:183335.18-183335.103" + wire width 64 $and$libresoc.v:183335$12069_Y + attribute \src "libresoc.v:183336.18-183336.106" + wire width 64 $and$libresoc.v:183336$12070_Y + attribute \src "libresoc.v:183338.18-183338.103" + wire width 64 $and$libresoc.v:183338$12072_Y + attribute \src "libresoc.v:183340.18-183340.105" + wire width 64 $and$libresoc.v:183340$12074_Y + attribute \src "libresoc.v:183343.18-183343.106" + wire width 64 $and$libresoc.v:183343$12077_Y + attribute \src "libresoc.v:183346.18-183346.105" + wire width 64 $and$libresoc.v:183346$12080_Y + attribute \src "libresoc.v:183348.17-183348.109" + wire $and$libresoc.v:183348$12082_Y + attribute \src "libresoc.v:183349.18-183349.104" + wire width 64 $and$libresoc.v:183349$12083_Y + attribute \src "libresoc.v:183353.18-183353.105" + wire width 64 $and$libresoc.v:183353$12087_Y + attribute \src "libresoc.v:183317.17-183317.98" + wire width 7 $extend$libresoc.v:183317$12050_Y + attribute \src "libresoc.v:183333.18-183333.122" + wire $gt$libresoc.v:183333$12067_Y + attribute \src "libresoc.v:183323.18-183323.111" + wire $le$libresoc.v:183323$12057_Y + attribute \src "libresoc.v:183325.18-183325.111" + wire $le$libresoc.v:183325$12059_Y + attribute \src "libresoc.v:183326.17-183326.117" + wire width 7 $neg$libresoc.v:183326$12060_Y + attribute \src "libresoc.v:183318.18-183318.103" + wire $not$libresoc.v:183318$12052_Y + attribute \src "libresoc.v:183320.18-183320.108" + wire $not$libresoc.v:183320$12054_Y + attribute \src "libresoc.v:183322.18-183322.105" + wire width 6 $not$libresoc.v:183322$12056_Y + attribute \src "libresoc.v:183328.18-183328.112" + wire width 64 $not$libresoc.v:183328$12062_Y + attribute \src "libresoc.v:183329.18-183329.109" + wire $not$libresoc.v:183329$12063_Y + attribute \src "libresoc.v:183337.17-183337.105" + wire $not$libresoc.v:183337$12071_Y + attribute \src "libresoc.v:183339.18-183339.102" + wire width 64 $not$libresoc.v:183339$12073_Y + attribute \src "libresoc.v:183345.18-183345.102" + wire width 64 $not$libresoc.v:183345$12079_Y + attribute \src "libresoc.v:183350.18-183350.100" + wire width 64 $not$libresoc.v:183350$12084_Y + attribute \src "libresoc.v:183352.18-183352.100" + wire width 64 $not$libresoc.v:183352$12086_Y + attribute \src "libresoc.v:183331.18-183331.115" + wire $or$libresoc.v:183331$12065_Y + attribute \src "libresoc.v:183341.18-183341.108" + wire width 64 $or$libresoc.v:183341$12075_Y + attribute \src "libresoc.v:183342.18-183342.103" + wire width 64 $or$libresoc.v:183342$12076_Y + attribute \src "libresoc.v:183344.18-183344.103" + wire width 64 $or$libresoc.v:183344$12078_Y + attribute \src "libresoc.v:183347.18-183347.108" + wire width 64 $or$libresoc.v:183347$12081_Y + attribute \src "libresoc.v:183351.18-183351.106" + wire width 64 $or$libresoc.v:183351$12085_Y + attribute \src "libresoc.v:183317.17-183317.98" + wire width 7 $pos$libresoc.v:183317$12051_Y + attribute \src "libresoc.v:183354.18-183354.102" + wire $reduce_or$libresoc.v:183354$12088_Y + attribute \src "libresoc.v:183324.18-183324.109" + wire width 8 $sub$libresoc.v:183324$12058_Y + attribute \src "libresoc.v:183327.18-183327.110" + wire width 8 $sub$libresoc.v:183327$12061_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -377301,7 +380172,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:181072.7-181072.15" + attribute \src "libresoc.v:183168.7-183168.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -377358,7 +380229,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:181223$12002 + cell $and $and$libresoc.v:183319$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377366,10 +380237,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:181223$12002_Y + connect \Y $and$libresoc.v:183319$12053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:181225$12004 + cell $and $and$libresoc.v:183321$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377377,10 +380248,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:181225$12004_Y + connect \Y $and$libresoc.v:183321$12055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:181234$12013 + cell $and $and$libresoc.v:183330$12064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377388,10 +380259,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:181234$12013_Y + connect \Y $and$libresoc.v:183330$12064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:181236$12015 + cell $and $and$libresoc.v:183332$12066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377399,10 +380270,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:181236$12015_Y + connect \Y $and$libresoc.v:183332$12066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:181238$12017 + cell $and $and$libresoc.v:183334$12068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377410,10 +380281,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:181238$12017_Y + connect \Y $and$libresoc.v:183334$12068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:181239$12018 + cell $and $and$libresoc.v:183335$12069 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377421,10 +380292,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:181239$12018_Y + connect \Y $and$libresoc.v:183335$12069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:181240$12019 + cell $and $and$libresoc.v:183336$12070 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377432,10 +380303,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:181240$12019_Y + connect \Y $and$libresoc.v:183336$12070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:181242$12021 + cell $and $and$libresoc.v:183338$12072 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377443,10 +380314,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:181242$12021_Y + connect \Y $and$libresoc.v:183338$12072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:181244$12023 + cell $and $and$libresoc.v:183340$12074 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377454,10 +380325,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:181244$12023_Y + connect \Y $and$libresoc.v:183340$12074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:181247$12026 + cell $and $and$libresoc.v:183343$12077 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377465,10 +380336,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:181247$12026_Y + connect \Y $and$libresoc.v:183343$12077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:181250$12029 + cell $and $and$libresoc.v:183346$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377476,10 +380347,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:181250$12029_Y + connect \Y $and$libresoc.v:183346$12080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:181252$12031 + cell $and $and$libresoc.v:183348$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377487,10 +380358,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:181252$12031_Y + connect \Y $and$libresoc.v:183348$12082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:181253$12032 + cell $and $and$libresoc.v:183349$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377498,10 +380369,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:181253$12032_Y + connect \Y $and$libresoc.v:183349$12083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:181257$12036 + cell $and $and$libresoc.v:183353$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377509,18 +380380,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:181257$12036_Y + connect \Y $and$libresoc.v:183353$12087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:181221$11999 + cell $pos $extend$libresoc.v:183317$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:181221$11999_Y + connect \Y $extend$libresoc.v:183317$12050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:181237$12016 + cell $gt $gt$libresoc.v:183333$12067 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -377528,10 +380399,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:181237$12016_Y + connect \Y $gt$libresoc.v:183333$12067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:181227$12006 + cell $le $le$libresoc.v:183323$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377539,10 +380410,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:181227$12006_Y + connect \Y $le$libresoc.v:183323$12057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:181229$12008 + cell $le $le$libresoc.v:183325$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377550,98 +380421,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:181229$12008_Y + connect \Y $le$libresoc.v:183325$12059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:181230$12009 + cell $neg $neg$libresoc.v:183326$12060 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:181230$12009_Y + connect \Y $neg$libresoc.v:183326$12060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:181222$12001 + cell $not $not$libresoc.v:183318$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:181222$12001_Y + connect \Y $not$libresoc.v:183318$12052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:181224$12003 + cell $not $not$libresoc.v:183320$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:181224$12003_Y + connect \Y $not$libresoc.v:183320$12054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:181226$12005 + cell $not $not$libresoc.v:183322$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:181226$12005_Y + connect \Y $not$libresoc.v:183322$12056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:181232$12011 + cell $not $not$libresoc.v:183328$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:181232$12011_Y + connect \Y $not$libresoc.v:183328$12062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:181233$12012 + cell $not $not$libresoc.v:183329$12063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:181233$12012_Y + connect \Y $not$libresoc.v:183329$12063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:181241$12020 + cell $not $not$libresoc.v:183337$12071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:181241$12020_Y + connect \Y $not$libresoc.v:183337$12071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:181243$12022 + cell $not $not$libresoc.v:183339$12073 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:181243$12022_Y + connect \Y $not$libresoc.v:183339$12073_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:181249$12028 + cell $not $not$libresoc.v:183345$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:181249$12028_Y + connect \Y $not$libresoc.v:183345$12079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:181254$12033 + cell $not $not$libresoc.v:183350$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:181254$12033_Y + connect \Y $not$libresoc.v:183350$12084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:181256$12035 + cell $not $not$libresoc.v:183352$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:181256$12035_Y + connect \Y $not$libresoc.v:183352$12086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:181235$12014 + cell $or $or$libresoc.v:183331$12065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377649,10 +380520,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:181235$12014_Y + connect \Y $or$libresoc.v:183331$12065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:181245$12024 + cell $or $or$libresoc.v:183341$12075 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377660,10 +380531,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:181245$12024_Y + connect \Y $or$libresoc.v:183341$12075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:181246$12025 + cell $or $or$libresoc.v:183342$12076 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377671,10 +380542,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:181246$12025_Y + connect \Y $or$libresoc.v:183342$12076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:181248$12027 + cell $or $or$libresoc.v:183344$12078 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377682,10 +380553,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:181248$12027_Y + connect \Y $or$libresoc.v:183344$12078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:181251$12030 + cell $or $or$libresoc.v:183347$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377693,10 +380564,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:181251$12030_Y + connect \Y $or$libresoc.v:183347$12081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:181255$12034 + cell $or $or$libresoc.v:183351$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -377704,26 +380575,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:181255$12034_Y + connect \Y $or$libresoc.v:183351$12085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:181221$12000 + cell $pos $pos$libresoc.v:183317$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:181221$11999_Y - connect \Y $pos$libresoc.v:181221$12000_Y + connect \A $extend$libresoc.v:183317$12050_Y + connect \Y $pos$libresoc.v:183317$12051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:181258$12037 + cell $reduce_or $reduce_or$libresoc.v:183354$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:181258$12037_Y + connect \Y $reduce_or$libresoc.v:183354$12088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:181228$12007 + cell $sub $sub$libresoc.v:183324$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377731,10 +380602,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:181228$12007_Y + connect \Y $sub$libresoc.v:183324$12058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:181231$12010 + cell $sub $sub$libresoc.v:183327$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -377742,42 +380613,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:181231$12010_Y + connect \Y $sub$libresoc.v:183327$12061_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:181259.13-181262.4" + attribute \src "libresoc.v:183355.13-183358.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:181263.14-181266.4" + attribute \src "libresoc.v:183359.14-183362.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:181267.8-181271.4" + attribute \src "libresoc.v:183363.8-183367.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:181072.7-181072.20" - process $proc$libresoc.v:181072$12053 + attribute \src "libresoc.v:183168.7-183168.20" + process $proc$libresoc.v:183168$12104 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181272.3-181286.6" - process $proc$libresoc.v:181272$12038 + attribute \src "libresoc.v:183368.3-183382.6" + process $proc$libresoc.v:183368$12089 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:181273.5-181273.29" + attribute \src "libresoc.v:183369.5-183369.29" switch \initial - attribute \src "libresoc.v:181273.9-181273.17" + attribute \src "libresoc.v:183369.9-183369.17" case 1'1 case end @@ -377799,14 +380670,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:181287.3-181296.6" - process $proc$libresoc.v:181287$12039 + attribute \src "libresoc.v:183383.3-183392.6" + process $proc$libresoc.v:183383$12090 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:181288.5-181288.29" + attribute \src "libresoc.v:183384.5-183384.29" switch \initial - attribute \src "libresoc.v:181288.9-181288.17" + attribute \src "libresoc.v:183384.9-183384.17" case 1'1 case end @@ -377822,13 +380693,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:181297.3-181308.6" - process $proc$libresoc.v:181297$12040 + attribute \src "libresoc.v:183393.3-183404.6" + process $proc$libresoc.v:183393$12091 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:181298.5-181298.29" + attribute \src "libresoc.v:183394.5-183394.29" switch \initial - attribute \src "libresoc.v:181298.9-181298.17" + attribute \src "libresoc.v:183394.9-183394.17" case 1'1 case end @@ -377846,13 +380717,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:181309.3-181320.6" - process $proc$libresoc.v:181309$12041 + attribute \src "libresoc.v:183405.3-183416.6" + process $proc$libresoc.v:183405$12092 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:181310.5-181310.29" + attribute \src "libresoc.v:183406.5-183406.29" switch \initial - attribute \src "libresoc.v:181310.9-181310.17" + attribute \src "libresoc.v:183406.9-183406.17" case 1'1 case end @@ -377870,14 +380741,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:181321.3-181339.6" - process $proc$libresoc.v:181321$12042 + attribute \src "libresoc.v:183417.3-183435.6" + process $proc$libresoc.v:183417$12093 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:181322.5-181322.29" + attribute \src "libresoc.v:183418.5-183418.29" switch \initial - attribute \src "libresoc.v:181322.9-181322.17" + attribute \src "libresoc.v:183418.9-183418.17" case 1'1 case end @@ -377905,14 +380776,14 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:181340.3-181349.6" - process $proc$libresoc.v:181340$12043 + attribute \src "libresoc.v:183436.3-183445.6" + process $proc$libresoc.v:183436$12094 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:181341.5-181341.29" + attribute \src "libresoc.v:183437.5-183437.29" switch \initial - attribute \src "libresoc.v:181341.9-181341.17" + attribute \src "libresoc.v:183437.9-183437.17" case 1'1 case end @@ -377928,13 +380799,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:181350.3-181361.6" - process $proc$libresoc.v:181350$12044 + attribute \src "libresoc.v:183446.3-183457.6" + process $proc$libresoc.v:183446$12095 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:181351.5-181351.29" + attribute \src "libresoc.v:183447.5-183447.29" switch \initial - attribute \src "libresoc.v:181351.9-181351.17" + attribute \src "libresoc.v:183447.9-183447.17" case 1'1 case end @@ -377952,13 +380823,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:181362.3-181395.6" - process $proc$libresoc.v:181362$12045 + attribute \src "libresoc.v:183458.3-183491.6" + process $proc$libresoc.v:183458$12096 assign { } { } - assign $0\mb$8[6:0]$12046 $1\mb$8[6:0]$12047 - attribute \src "libresoc.v:181363.5-181363.29" + assign $0\mb$8[6:0]$12097 $1\mb$8[6:0]$12098 + attribute \src "libresoc.v:183459.5-183459.29" switch \initial - attribute \src "libresoc.v:181363.9-181363.17" + attribute \src "libresoc.v:183459.9-183459.17" case 1'1 case end @@ -377967,48 +380838,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$12047 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12047 [6:5] $2\mb$8[6:5]$12048 + assign $1\mb$8[6:0]$12098 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12098 [6:5] $2\mb$8[6:5]$12099 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$12048 2'01 + assign $2\mb$8[6:5]$12099 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$12048 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12099 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$12047 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12047 [6:5] $3\mb$8[6:5]$12049 + assign $1\mb$8[6:0]$12098 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12098 [6:5] $3\mb$8[6:5]$12100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$12049 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12100 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$12049 \sh [6:5] + assign $3\mb$8[6:5]$12100 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$12047 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12098 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$12046 + update \mb$8 $0\mb$8[6:0]$12097 end - attribute \src "libresoc.v:181396.3-181410.6" - process $proc$libresoc.v:181396$12050 + attribute \src "libresoc.v:183492.3-183506.6" + process $proc$libresoc.v:183492$12101 assign { } { } - assign $0\me$13[6:0]$12051 $1\me$13[6:0]$12052 - attribute \src "libresoc.v:181397.5-181397.29" + assign $0\me$13[6:0]$12102 $1\me$13[6:0]$12103 + attribute \src "libresoc.v:183493.5-183493.29" switch \initial - attribute \src "libresoc.v:181397.9-181397.17" + attribute \src "libresoc.v:183493.9-183493.17" case 1'1 case end @@ -378017,57 +380888,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$12052 { 2'01 \me } + assign $1\me$13[6:0]$12103 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$12052 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12052 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12051 - end - connect \$9 $pos$libresoc.v:181221$12000_Y - connect \$11 $not$libresoc.v:181222$12001_Y - connect \$14 $and$libresoc.v:181223$12002_Y - connect \$16 $not$libresoc.v:181224$12003_Y - connect \$18 $and$libresoc.v:181225$12004_Y - connect \$20 $not$libresoc.v:181226$12005_Y - connect \$22 $le$libresoc.v:181227$12006_Y - connect \$25 $sub$libresoc.v:181228$12007_Y - connect \$27 $le$libresoc.v:181229$12008_Y - connect \$2 $neg$libresoc.v:181230$12009_Y - connect \$30 $sub$libresoc.v:181231$12010_Y - connect \$32 $not$libresoc.v:181232$12011_Y - connect \$34 $not$libresoc.v:181233$12012_Y - connect \$36 $and$libresoc.v:181234$12013_Y - connect \$38 $or$libresoc.v:181235$12014_Y - connect \$40 $and$libresoc.v:181236$12015_Y - connect \$42 $gt$libresoc.v:181237$12016_Y - connect \$44 $and$libresoc.v:181238$12017_Y - connect \$46 $and$libresoc.v:181239$12018_Y - connect \$48 $and$libresoc.v:181240$12019_Y - connect \$4 $not$libresoc.v:181241$12020_Y - connect \$51 $and$libresoc.v:181242$12021_Y - connect \$50 $not$libresoc.v:181243$12022_Y - connect \$54 $and$libresoc.v:181244$12023_Y - connect \$56 $or$libresoc.v:181245$12024_Y - connect \$58 $or$libresoc.v:181246$12025_Y - connect \$60 $and$libresoc.v:181247$12026_Y - connect \$63 $or$libresoc.v:181248$12027_Y - connect \$62 $not$libresoc.v:181249$12028_Y - connect \$66 $and$libresoc.v:181250$12029_Y - connect \$68 $or$libresoc.v:181251$12030_Y - connect \$6 $and$libresoc.v:181252$12031_Y - connect \$70 $and$libresoc.v:181253$12032_Y - connect \$72 $not$libresoc.v:181254$12033_Y - connect \$74 $or$libresoc.v:181255$12034_Y - connect \$77 $not$libresoc.v:181256$12035_Y - connect \$79 $and$libresoc.v:181257$12036_Y - connect \$76 $reduce_or$libresoc.v:181258$12037_Y + assign $1\me$13[6:0]$12103 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12103 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12102 + end + connect \$9 $pos$libresoc.v:183317$12051_Y + connect \$11 $not$libresoc.v:183318$12052_Y + connect \$14 $and$libresoc.v:183319$12053_Y + connect \$16 $not$libresoc.v:183320$12054_Y + connect \$18 $and$libresoc.v:183321$12055_Y + connect \$20 $not$libresoc.v:183322$12056_Y + connect \$22 $le$libresoc.v:183323$12057_Y + connect \$25 $sub$libresoc.v:183324$12058_Y + connect \$27 $le$libresoc.v:183325$12059_Y + connect \$2 $neg$libresoc.v:183326$12060_Y + connect \$30 $sub$libresoc.v:183327$12061_Y + connect \$32 $not$libresoc.v:183328$12062_Y + connect \$34 $not$libresoc.v:183329$12063_Y + connect \$36 $and$libresoc.v:183330$12064_Y + connect \$38 $or$libresoc.v:183331$12065_Y + connect \$40 $and$libresoc.v:183332$12066_Y + connect \$42 $gt$libresoc.v:183333$12067_Y + connect \$44 $and$libresoc.v:183334$12068_Y + connect \$46 $and$libresoc.v:183335$12069_Y + connect \$48 $and$libresoc.v:183336$12070_Y + connect \$4 $not$libresoc.v:183337$12071_Y + connect \$51 $and$libresoc.v:183338$12072_Y + connect \$50 $not$libresoc.v:183339$12073_Y + connect \$54 $and$libresoc.v:183340$12074_Y + connect \$56 $or$libresoc.v:183341$12075_Y + connect \$58 $or$libresoc.v:183342$12076_Y + connect \$60 $and$libresoc.v:183343$12077_Y + connect \$63 $or$libresoc.v:183344$12078_Y + connect \$62 $not$libresoc.v:183345$12079_Y + connect \$66 $and$libresoc.v:183346$12080_Y + connect \$68 $or$libresoc.v:183347$12081_Y + connect \$6 $and$libresoc.v:183348$12082_Y + connect \$70 $and$libresoc.v:183349$12083_Y + connect \$72 $not$libresoc.v:183350$12084_Y + connect \$74 $or$libresoc.v:183351$12085_Y + connect \$77 $not$libresoc.v:183352$12086_Y + connect \$79 $and$libresoc.v:183353$12087_Y + connect \$76 $reduce_or$libresoc.v:183354$12088_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -378080,15 +380951,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:181426.1-181440.10" +attribute \src "libresoc.v:183522.1-183536.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:181438.17-181438.32" - wire width 128 $shr$libresoc.v:181438$12055_Y - attribute \src "libresoc.v:181437.17-181437.100" - wire width 8 $sub$libresoc.v:181437$12054_Y + attribute \src "libresoc.v:183534.17-183534.32" + wire width 128 $shr$libresoc.v:183534$12106_Y + attribute \src "libresoc.v:183533.17-183533.100" + wire width 8 $sub$libresoc.v:183533$12105_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -378099,8 +380970,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:181438.17-181438.32" - cell $shr $shr$libresoc.v:181438$12055 + attribute \src "libresoc.v:183534.17-183534.32" + cell $shr $shr$libresoc.v:183534$12106 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -378108,10 +380979,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:181438$12055_Y + connect \Y $shr$libresoc.v:183534$12106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:181437$12054 + cell $sub $sub$libresoc.v:183533$12105 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378119,43 +380990,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:181437$12054_Y + connect \Y $sub$libresoc.v:183533$12105_Y end - connect \$2 $sub$libresoc.v:181437$12054_Y - connect \$1 $shr$libresoc.v:181438$12055_Y [63:0] + connect \$2 $sub$libresoc.v:183533$12105_Y + connect \$1 $shr$libresoc.v:183534$12106_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:181444.1-181502.10" +attribute \src "libresoc.v:183540.1-183598.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:181445.7-181445.20" + attribute \src "libresoc.v:183541.7-183541.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181490.3-181498.6" - wire $0\q_int$next[0:0]$12066 - attribute \src "libresoc.v:181488.3-181489.27" + attribute \src "libresoc.v:183586.3-183594.6" + wire $0\q_int$next[0:0]$12117 + attribute \src "libresoc.v:183584.3-183585.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181490.3-181498.6" - wire $1\q_int$next[0:0]$12067 - attribute \src "libresoc.v:181467.7-181467.19" + attribute \src "libresoc.v:183586.3-183594.6" + wire $1\q_int$next[0:0]$12118 + attribute \src "libresoc.v:183563.7-183563.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181480.17-181480.96" - wire $and$libresoc.v:181480$12056_Y - attribute \src "libresoc.v:181485.17-181485.96" - wire $and$libresoc.v:181485$12061_Y - attribute \src "libresoc.v:181482.18-181482.93" - wire $not$libresoc.v:181482$12058_Y - attribute \src "libresoc.v:181484.17-181484.92" - wire $not$libresoc.v:181484$12060_Y - attribute \src "libresoc.v:181487.17-181487.92" - wire $not$libresoc.v:181487$12063_Y - attribute \src "libresoc.v:181481.18-181481.98" - wire $or$libresoc.v:181481$12057_Y - attribute \src "libresoc.v:181483.18-181483.99" - wire $or$libresoc.v:181483$12059_Y - attribute \src "libresoc.v:181486.17-181486.97" - wire $or$libresoc.v:181486$12062_Y + attribute \src "libresoc.v:183576.17-183576.96" + wire $and$libresoc.v:183576$12107_Y + attribute \src "libresoc.v:183581.17-183581.96" + wire $and$libresoc.v:183581$12112_Y + attribute \src "libresoc.v:183578.18-183578.93" + wire $not$libresoc.v:183578$12109_Y + attribute \src "libresoc.v:183580.17-183580.92" + wire $not$libresoc.v:183580$12111_Y + attribute \src "libresoc.v:183583.17-183583.92" + wire $not$libresoc.v:183583$12114_Y + attribute \src "libresoc.v:183577.18-183577.98" + wire $or$libresoc.v:183577$12108_Y + attribute \src "libresoc.v:183579.18-183579.99" + wire $or$libresoc.v:183579$12110_Y + attribute \src "libresoc.v:183582.17-183582.97" + wire $or$libresoc.v:183582$12113_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378172,11 +381043,11 @@ module \rst_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181445.7-181445.15" + attribute \src "libresoc.v:183541.7-183541.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378193,7 +381064,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181480$12056 + cell $and $and$libresoc.v:183576$12107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378201,10 +381072,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181480$12056_Y + connect \Y $and$libresoc.v:183576$12107_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181485$12061 + cell $and $and$libresoc.v:183581$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378212,34 +381083,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181485$12061_Y + connect \Y $and$libresoc.v:183581$12112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181482$12058 + cell $not $not$libresoc.v:183578$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181482$12058_Y + connect \Y $not$libresoc.v:183578$12109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181484$12060 + cell $not $not$libresoc.v:183580$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181484$12060_Y + connect \Y $not$libresoc.v:183580$12111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181487$12063 + cell $not $not$libresoc.v:183583$12114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181487$12063_Y + connect \Y $not$libresoc.v:183583$12114_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181481$12057 + cell $or $or$libresoc.v:183577$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378247,10 +381118,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181481$12057_Y + connect \Y $or$libresoc.v:183577$12108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181483$12059 + cell $or $or$libresoc.v:183579$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378258,10 +381129,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181483$12059_Y + connect \Y $or$libresoc.v:183579$12110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181486$12062 + cell $or $or$libresoc.v:183582$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378269,39 +381140,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181486$12062_Y + connect \Y $or$libresoc.v:183582$12113_Y end - attribute \src "libresoc.v:181445.7-181445.20" - process $proc$libresoc.v:181445$12068 + attribute \src "libresoc.v:183541.7-183541.20" + process $proc$libresoc.v:183541$12119 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181467.7-181467.19" - process $proc$libresoc.v:181467$12069 + attribute \src "libresoc.v:183563.7-183563.19" + process $proc$libresoc.v:183563$12120 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181488.3-181489.27" - process $proc$libresoc.v:181488$12064 + attribute \src "libresoc.v:183584.3-183585.27" + process $proc$libresoc.v:183584$12115 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181490.3-181498.6" - process $proc$libresoc.v:181490$12065 + attribute \src "libresoc.v:183586.3-183594.6" + process $proc$libresoc.v:183586$12116 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12066 $1\q_int$next[0:0]$12067 - attribute \src "libresoc.v:181491.5-181491.29" + assign $0\q_int$next[0:0]$12117 $1\q_int$next[0:0]$12118 + attribute \src "libresoc.v:183587.5-183587.29" switch \initial - attribute \src "libresoc.v:181491.9-181491.17" + attribute \src "libresoc.v:183587.9-183587.17" case 1'1 case end @@ -378310,56 +381181,56 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12067 1'0 + assign $1\q_int$next[0:0]$12118 1'0 case - assign $1\q_int$next[0:0]$12067 \$5 + assign $1\q_int$next[0:0]$12118 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12066 + update \q_int$next $0\q_int$next[0:0]$12117 end - connect \$9 $and$libresoc.v:181480$12056_Y - connect \$11 $or$libresoc.v:181481$12057_Y - connect \$13 $not$libresoc.v:181482$12058_Y - connect \$15 $or$libresoc.v:181483$12059_Y - connect \$1 $not$libresoc.v:181484$12060_Y - connect \$3 $and$libresoc.v:181485$12061_Y - connect \$5 $or$libresoc.v:181486$12062_Y - connect \$7 $not$libresoc.v:181487$12063_Y + connect \$9 $and$libresoc.v:183576$12107_Y + connect \$11 $or$libresoc.v:183577$12108_Y + connect \$13 $not$libresoc.v:183578$12109_Y + connect \$15 $or$libresoc.v:183579$12110_Y + connect \$1 $not$libresoc.v:183580$12111_Y + connect \$3 $and$libresoc.v:183581$12112_Y + connect \$5 $or$libresoc.v:183582$12113_Y + connect \$7 $not$libresoc.v:183583$12114_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:181506.1-181564.10" +attribute \src "libresoc.v:183602.1-183660.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:181507.7-181507.20" + attribute \src "libresoc.v:183603.7-183603.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181552.3-181560.6" - wire $0\q_int$next[0:0]$12080 - attribute \src "libresoc.v:181550.3-181551.27" + attribute \src "libresoc.v:183648.3-183656.6" + wire $0\q_int$next[0:0]$12131 + attribute \src "libresoc.v:183646.3-183647.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181552.3-181560.6" - wire $1\q_int$next[0:0]$12081 - attribute \src "libresoc.v:181529.7-181529.19" + attribute \src "libresoc.v:183648.3-183656.6" + wire $1\q_int$next[0:0]$12132 + attribute \src "libresoc.v:183625.7-183625.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181542.17-181542.96" - wire $and$libresoc.v:181542$12070_Y - attribute \src "libresoc.v:181547.17-181547.96" - wire $and$libresoc.v:181547$12075_Y - attribute \src "libresoc.v:181544.18-181544.93" - wire $not$libresoc.v:181544$12072_Y - attribute \src "libresoc.v:181546.17-181546.92" - wire $not$libresoc.v:181546$12074_Y - attribute \src "libresoc.v:181549.17-181549.92" - wire $not$libresoc.v:181549$12077_Y - attribute \src "libresoc.v:181543.18-181543.98" - wire $or$libresoc.v:181543$12071_Y - attribute \src "libresoc.v:181545.18-181545.99" - wire $or$libresoc.v:181545$12073_Y - attribute \src "libresoc.v:181548.17-181548.97" - wire $or$libresoc.v:181548$12076_Y + attribute \src "libresoc.v:183638.17-183638.96" + wire $and$libresoc.v:183638$12121_Y + attribute \src "libresoc.v:183643.17-183643.96" + wire $and$libresoc.v:183643$12126_Y + attribute \src "libresoc.v:183640.18-183640.93" + wire $not$libresoc.v:183640$12123_Y + attribute \src "libresoc.v:183642.17-183642.92" + wire $not$libresoc.v:183642$12125_Y + attribute \src "libresoc.v:183645.17-183645.92" + wire $not$libresoc.v:183645$12128_Y + attribute \src "libresoc.v:183639.18-183639.98" + wire $or$libresoc.v:183639$12122_Y + attribute \src "libresoc.v:183641.18-183641.99" + wire $or$libresoc.v:183641$12124_Y + attribute \src "libresoc.v:183644.17-183644.97" + wire $or$libresoc.v:183644$12127_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378376,11 +381247,11 @@ module \rst_l$104 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181507.7-181507.15" + attribute \src "libresoc.v:183603.7-183603.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378397,7 +381268,7 @@ module \rst_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181542$12070 + cell $and $and$libresoc.v:183638$12121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378405,10 +381276,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181542$12070_Y + connect \Y $and$libresoc.v:183638$12121_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181547$12075 + cell $and $and$libresoc.v:183643$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378416,34 +381287,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181547$12075_Y + connect \Y $and$libresoc.v:183643$12126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181544$12072 + cell $not $not$libresoc.v:183640$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181544$12072_Y + connect \Y $not$libresoc.v:183640$12123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181546$12074 + cell $not $not$libresoc.v:183642$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181546$12074_Y + connect \Y $not$libresoc.v:183642$12125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181549$12077 + cell $not $not$libresoc.v:183645$12128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181549$12077_Y + connect \Y $not$libresoc.v:183645$12128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181543$12071 + cell $or $or$libresoc.v:183639$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378451,10 +381322,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181543$12071_Y + connect \Y $or$libresoc.v:183639$12122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181545$12073 + cell $or $or$libresoc.v:183641$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378462,10 +381333,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181545$12073_Y + connect \Y $or$libresoc.v:183641$12124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181548$12076 + cell $or $or$libresoc.v:183644$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378473,39 +381344,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181548$12076_Y + connect \Y $or$libresoc.v:183644$12127_Y end - attribute \src "libresoc.v:181507.7-181507.20" - process $proc$libresoc.v:181507$12082 + attribute \src "libresoc.v:183603.7-183603.20" + process $proc$libresoc.v:183603$12133 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181529.7-181529.19" - process $proc$libresoc.v:181529$12083 + attribute \src "libresoc.v:183625.7-183625.19" + process $proc$libresoc.v:183625$12134 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181550.3-181551.27" - process $proc$libresoc.v:181550$12078 + attribute \src "libresoc.v:183646.3-183647.27" + process $proc$libresoc.v:183646$12129 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181552.3-181560.6" - process $proc$libresoc.v:181552$12079 + attribute \src "libresoc.v:183648.3-183656.6" + process $proc$libresoc.v:183648$12130 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12080 $1\q_int$next[0:0]$12081 - attribute \src "libresoc.v:181553.5-181553.29" + assign $0\q_int$next[0:0]$12131 $1\q_int$next[0:0]$12132 + attribute \src "libresoc.v:183649.5-183649.29" switch \initial - attribute \src "libresoc.v:181553.9-181553.17" + attribute \src "libresoc.v:183649.9-183649.17" case 1'1 case end @@ -378514,56 +381385,56 @@ module \rst_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12081 1'0 + assign $1\q_int$next[0:0]$12132 1'0 case - assign $1\q_int$next[0:0]$12081 \$5 + assign $1\q_int$next[0:0]$12132 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12080 + update \q_int$next $0\q_int$next[0:0]$12131 end - connect \$9 $and$libresoc.v:181542$12070_Y - connect \$11 $or$libresoc.v:181543$12071_Y - connect \$13 $not$libresoc.v:181544$12072_Y - connect \$15 $or$libresoc.v:181545$12073_Y - connect \$1 $not$libresoc.v:181546$12074_Y - connect \$3 $and$libresoc.v:181547$12075_Y - connect \$5 $or$libresoc.v:181548$12076_Y - connect \$7 $not$libresoc.v:181549$12077_Y + connect \$9 $and$libresoc.v:183638$12121_Y + connect \$11 $or$libresoc.v:183639$12122_Y + connect \$13 $not$libresoc.v:183640$12123_Y + connect \$15 $or$libresoc.v:183641$12124_Y + connect \$1 $not$libresoc.v:183642$12125_Y + connect \$3 $and$libresoc.v:183643$12126_Y + connect \$5 $or$libresoc.v:183644$12127_Y + connect \$7 $not$libresoc.v:183645$12128_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:181568.1-181626.10" +attribute \src "libresoc.v:183664.1-183722.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:181569.7-181569.20" + attribute \src "libresoc.v:183665.7-183665.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181614.3-181622.6" - wire $0\q_int$next[0:0]$12094 - attribute \src "libresoc.v:181612.3-181613.27" + attribute \src "libresoc.v:183710.3-183718.6" + wire $0\q_int$next[0:0]$12145 + attribute \src "libresoc.v:183708.3-183709.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181614.3-181622.6" - wire $1\q_int$next[0:0]$12095 - attribute \src "libresoc.v:181591.7-181591.19" + attribute \src "libresoc.v:183710.3-183718.6" + wire $1\q_int$next[0:0]$12146 + attribute \src "libresoc.v:183687.7-183687.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181604.17-181604.96" - wire $and$libresoc.v:181604$12084_Y - attribute \src "libresoc.v:181609.17-181609.96" - wire $and$libresoc.v:181609$12089_Y - attribute \src "libresoc.v:181606.18-181606.93" - wire $not$libresoc.v:181606$12086_Y - attribute \src "libresoc.v:181608.17-181608.92" - wire $not$libresoc.v:181608$12088_Y - attribute \src "libresoc.v:181611.17-181611.92" - wire $not$libresoc.v:181611$12091_Y - attribute \src "libresoc.v:181605.18-181605.98" - wire $or$libresoc.v:181605$12085_Y - attribute \src "libresoc.v:181607.18-181607.99" - wire $or$libresoc.v:181607$12087_Y - attribute \src "libresoc.v:181610.17-181610.97" - wire $or$libresoc.v:181610$12090_Y + attribute \src "libresoc.v:183700.17-183700.96" + wire $and$libresoc.v:183700$12135_Y + attribute \src "libresoc.v:183705.17-183705.96" + wire $and$libresoc.v:183705$12140_Y + attribute \src "libresoc.v:183702.18-183702.93" + wire $not$libresoc.v:183702$12137_Y + attribute \src "libresoc.v:183704.17-183704.92" + wire $not$libresoc.v:183704$12139_Y + attribute \src "libresoc.v:183707.17-183707.92" + wire $not$libresoc.v:183707$12142_Y + attribute \src "libresoc.v:183701.18-183701.98" + wire $or$libresoc.v:183701$12136_Y + attribute \src "libresoc.v:183703.18-183703.99" + wire $or$libresoc.v:183703$12138_Y + attribute \src "libresoc.v:183706.17-183706.97" + wire $or$libresoc.v:183706$12141_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378580,11 +381451,11 @@ module \rst_l$122 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181569.7-181569.15" + attribute \src "libresoc.v:183665.7-183665.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378601,7 +381472,7 @@ module \rst_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181604$12084 + cell $and $and$libresoc.v:183700$12135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378609,10 +381480,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181604$12084_Y + connect \Y $and$libresoc.v:183700$12135_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181609$12089 + cell $and $and$libresoc.v:183705$12140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378620,34 +381491,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181609$12089_Y + connect \Y $and$libresoc.v:183705$12140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181606$12086 + cell $not $not$libresoc.v:183702$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181606$12086_Y + connect \Y $not$libresoc.v:183702$12137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181608$12088 + cell $not $not$libresoc.v:183704$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181608$12088_Y + connect \Y $not$libresoc.v:183704$12139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181611$12091 + cell $not $not$libresoc.v:183707$12142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181611$12091_Y + connect \Y $not$libresoc.v:183707$12142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181605$12085 + cell $or $or$libresoc.v:183701$12136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378655,10 +381526,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181605$12085_Y + connect \Y $or$libresoc.v:183701$12136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181607$12087 + cell $or $or$libresoc.v:183703$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378666,10 +381537,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181607$12087_Y + connect \Y $or$libresoc.v:183703$12138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181610$12090 + cell $or $or$libresoc.v:183706$12141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378677,39 +381548,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181610$12090_Y + connect \Y $or$libresoc.v:183706$12141_Y end - attribute \src "libresoc.v:181569.7-181569.20" - process $proc$libresoc.v:181569$12096 + attribute \src "libresoc.v:183665.7-183665.20" + process $proc$libresoc.v:183665$12147 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181591.7-181591.19" - process $proc$libresoc.v:181591$12097 + attribute \src "libresoc.v:183687.7-183687.19" + process $proc$libresoc.v:183687$12148 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181612.3-181613.27" - process $proc$libresoc.v:181612$12092 + attribute \src "libresoc.v:183708.3-183709.27" + process $proc$libresoc.v:183708$12143 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181614.3-181622.6" - process $proc$libresoc.v:181614$12093 + attribute \src "libresoc.v:183710.3-183718.6" + process $proc$libresoc.v:183710$12144 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12094 $1\q_int$next[0:0]$12095 - attribute \src "libresoc.v:181615.5-181615.29" + assign $0\q_int$next[0:0]$12145 $1\q_int$next[0:0]$12146 + attribute \src "libresoc.v:183711.5-183711.29" switch \initial - attribute \src "libresoc.v:181615.9-181615.17" + attribute \src "libresoc.v:183711.9-183711.17" case 1'1 case end @@ -378718,56 +381589,56 @@ module \rst_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12095 1'0 + assign $1\q_int$next[0:0]$12146 1'0 case - assign $1\q_int$next[0:0]$12095 \$5 + assign $1\q_int$next[0:0]$12146 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12094 + update \q_int$next $0\q_int$next[0:0]$12145 end - connect \$9 $and$libresoc.v:181604$12084_Y - connect \$11 $or$libresoc.v:181605$12085_Y - connect \$13 $not$libresoc.v:181606$12086_Y - connect \$15 $or$libresoc.v:181607$12087_Y - connect \$1 $not$libresoc.v:181608$12088_Y - connect \$3 $and$libresoc.v:181609$12089_Y - connect \$5 $or$libresoc.v:181610$12090_Y - connect \$7 $not$libresoc.v:181611$12091_Y + connect \$9 $and$libresoc.v:183700$12135_Y + connect \$11 $or$libresoc.v:183701$12136_Y + connect \$13 $not$libresoc.v:183702$12137_Y + connect \$15 $or$libresoc.v:183703$12138_Y + connect \$1 $not$libresoc.v:183704$12139_Y + connect \$3 $and$libresoc.v:183705$12140_Y + connect \$5 $or$libresoc.v:183706$12141_Y + connect \$7 $not$libresoc.v:183707$12142_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:181630.1-181688.10" +attribute \src "libresoc.v:183726.1-183784.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:181631.7-181631.20" + attribute \src "libresoc.v:183727.7-183727.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181676.3-181684.6" - wire $0\q_int$next[0:0]$12108 - attribute \src "libresoc.v:181674.3-181675.27" + attribute \src "libresoc.v:183772.3-183780.6" + wire $0\q_int$next[0:0]$12159 + attribute \src "libresoc.v:183770.3-183771.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181676.3-181684.6" - wire $1\q_int$next[0:0]$12109 - attribute \src "libresoc.v:181653.7-181653.19" + attribute \src "libresoc.v:183772.3-183780.6" + wire $1\q_int$next[0:0]$12160 + attribute \src "libresoc.v:183749.7-183749.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181666.17-181666.96" - wire $and$libresoc.v:181666$12098_Y - attribute \src "libresoc.v:181671.17-181671.96" - wire $and$libresoc.v:181671$12103_Y - attribute \src "libresoc.v:181668.18-181668.93" - wire $not$libresoc.v:181668$12100_Y - attribute \src "libresoc.v:181670.17-181670.92" - wire $not$libresoc.v:181670$12102_Y - attribute \src "libresoc.v:181673.17-181673.92" - wire $not$libresoc.v:181673$12105_Y - attribute \src "libresoc.v:181667.18-181667.98" - wire $or$libresoc.v:181667$12099_Y - attribute \src "libresoc.v:181669.18-181669.99" - wire $or$libresoc.v:181669$12101_Y - attribute \src "libresoc.v:181672.17-181672.97" - wire $or$libresoc.v:181672$12104_Y + attribute \src "libresoc.v:183762.17-183762.96" + wire $and$libresoc.v:183762$12149_Y + attribute \src "libresoc.v:183767.17-183767.96" + wire $and$libresoc.v:183767$12154_Y + attribute \src "libresoc.v:183764.18-183764.93" + wire $not$libresoc.v:183764$12151_Y + attribute \src "libresoc.v:183766.17-183766.92" + wire $not$libresoc.v:183766$12153_Y + attribute \src "libresoc.v:183769.17-183769.92" + wire $not$libresoc.v:183769$12156_Y + attribute \src "libresoc.v:183763.18-183763.98" + wire $or$libresoc.v:183763$12150_Y + attribute \src "libresoc.v:183765.18-183765.99" + wire $or$libresoc.v:183765$12152_Y + attribute \src "libresoc.v:183768.17-183768.97" + wire $or$libresoc.v:183768$12155_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378784,11 +381655,11 @@ module \rst_l$129 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181631.7-181631.15" + attribute \src "libresoc.v:183727.7-183727.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378805,7 +381676,7 @@ module \rst_l$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181666$12098 + cell $and $and$libresoc.v:183762$12149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378813,10 +381684,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181666$12098_Y + connect \Y $and$libresoc.v:183762$12149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181671$12103 + cell $and $and$libresoc.v:183767$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378824,34 +381695,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181671$12103_Y + connect \Y $and$libresoc.v:183767$12154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181668$12100 + cell $not $not$libresoc.v:183764$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181668$12100_Y + connect \Y $not$libresoc.v:183764$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181670$12102 + cell $not $not$libresoc.v:183766$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181670$12102_Y + connect \Y $not$libresoc.v:183766$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181673$12105 + cell $not $not$libresoc.v:183769$12156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181673$12105_Y + connect \Y $not$libresoc.v:183769$12156_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181667$12099 + cell $or $or$libresoc.v:183763$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378859,10 +381730,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181667$12099_Y + connect \Y $or$libresoc.v:183763$12150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181669$12101 + cell $or $or$libresoc.v:183765$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378870,10 +381741,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181669$12101_Y + connect \Y $or$libresoc.v:183765$12152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181672$12104 + cell $or $or$libresoc.v:183768$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378881,39 +381752,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181672$12104_Y + connect \Y $or$libresoc.v:183768$12155_Y end - attribute \src "libresoc.v:181631.7-181631.20" - process $proc$libresoc.v:181631$12110 + attribute \src "libresoc.v:183727.7-183727.20" + process $proc$libresoc.v:183727$12161 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181653.7-181653.19" - process $proc$libresoc.v:181653$12111 + attribute \src "libresoc.v:183749.7-183749.19" + process $proc$libresoc.v:183749$12162 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181674.3-181675.27" - process $proc$libresoc.v:181674$12106 + attribute \src "libresoc.v:183770.3-183771.27" + process $proc$libresoc.v:183770$12157 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181676.3-181684.6" - process $proc$libresoc.v:181676$12107 + attribute \src "libresoc.v:183772.3-183780.6" + process $proc$libresoc.v:183772$12158 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12108 $1\q_int$next[0:0]$12109 - attribute \src "libresoc.v:181677.5-181677.29" + assign $0\q_int$next[0:0]$12159 $1\q_int$next[0:0]$12160 + attribute \src "libresoc.v:183773.5-183773.29" switch \initial - attribute \src "libresoc.v:181677.9-181677.17" + attribute \src "libresoc.v:183773.9-183773.17" case 1'1 case end @@ -378922,56 +381793,56 @@ module \rst_l$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12109 1'0 + assign $1\q_int$next[0:0]$12160 1'0 case - assign $1\q_int$next[0:0]$12109 \$5 + assign $1\q_int$next[0:0]$12160 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12108 + update \q_int$next $0\q_int$next[0:0]$12159 end - connect \$9 $and$libresoc.v:181666$12098_Y - connect \$11 $or$libresoc.v:181667$12099_Y - connect \$13 $not$libresoc.v:181668$12100_Y - connect \$15 $or$libresoc.v:181669$12101_Y - connect \$1 $not$libresoc.v:181670$12102_Y - connect \$3 $and$libresoc.v:181671$12103_Y - connect \$5 $or$libresoc.v:181672$12104_Y - connect \$7 $not$libresoc.v:181673$12105_Y + connect \$9 $and$libresoc.v:183762$12149_Y + connect \$11 $or$libresoc.v:183763$12150_Y + connect \$13 $not$libresoc.v:183764$12151_Y + connect \$15 $or$libresoc.v:183765$12152_Y + connect \$1 $not$libresoc.v:183766$12153_Y + connect \$3 $and$libresoc.v:183767$12154_Y + connect \$5 $or$libresoc.v:183768$12155_Y + connect \$7 $not$libresoc.v:183769$12156_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:181692.1-181750.10" +attribute \src "libresoc.v:183788.1-183846.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:181693.7-181693.20" + attribute \src "libresoc.v:183789.7-183789.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181738.3-181746.6" - wire $0\q_int$next[0:0]$12122 - attribute \src "libresoc.v:181736.3-181737.27" + attribute \src "libresoc.v:183834.3-183842.6" + wire $0\q_int$next[0:0]$12173 + attribute \src "libresoc.v:183832.3-183833.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181738.3-181746.6" - wire $1\q_int$next[0:0]$12123 - attribute \src "libresoc.v:181715.7-181715.19" + attribute \src "libresoc.v:183834.3-183842.6" + wire $1\q_int$next[0:0]$12174 + attribute \src "libresoc.v:183811.7-183811.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181728.17-181728.96" - wire $and$libresoc.v:181728$12112_Y - attribute \src "libresoc.v:181733.17-181733.96" - wire $and$libresoc.v:181733$12117_Y - attribute \src "libresoc.v:181730.18-181730.93" - wire $not$libresoc.v:181730$12114_Y - attribute \src "libresoc.v:181732.17-181732.92" - wire $not$libresoc.v:181732$12116_Y - attribute \src "libresoc.v:181735.17-181735.92" - wire $not$libresoc.v:181735$12119_Y - attribute \src "libresoc.v:181729.18-181729.98" - wire $or$libresoc.v:181729$12113_Y - attribute \src "libresoc.v:181731.18-181731.99" - wire $or$libresoc.v:181731$12115_Y - attribute \src "libresoc.v:181734.17-181734.97" - wire $or$libresoc.v:181734$12118_Y + attribute \src "libresoc.v:183824.17-183824.96" + wire $and$libresoc.v:183824$12163_Y + attribute \src "libresoc.v:183829.17-183829.96" + wire $and$libresoc.v:183829$12168_Y + attribute \src "libresoc.v:183826.18-183826.93" + wire $not$libresoc.v:183826$12165_Y + attribute \src "libresoc.v:183828.17-183828.92" + wire $not$libresoc.v:183828$12167_Y + attribute \src "libresoc.v:183831.17-183831.92" + wire $not$libresoc.v:183831$12170_Y + attribute \src "libresoc.v:183825.18-183825.98" + wire $or$libresoc.v:183825$12164_Y + attribute \src "libresoc.v:183827.18-183827.99" + wire $or$libresoc.v:183827$12166_Y + attribute \src "libresoc.v:183830.17-183830.97" + wire $or$libresoc.v:183830$12169_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378988,11 +381859,11 @@ module \rst_l$13 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181693.7-181693.15" + attribute \src "libresoc.v:183789.7-183789.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379009,7 +381880,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181728$12112 + cell $and $and$libresoc.v:183824$12163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379017,10 +381888,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181728$12112_Y + connect \Y $and$libresoc.v:183824$12163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181733$12117 + cell $and $and$libresoc.v:183829$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379028,34 +381899,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181733$12117_Y + connect \Y $and$libresoc.v:183829$12168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181730$12114 + cell $not $not$libresoc.v:183826$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181730$12114_Y + connect \Y $not$libresoc.v:183826$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181732$12116 + cell $not $not$libresoc.v:183828$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181732$12116_Y + connect \Y $not$libresoc.v:183828$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181735$12119 + cell $not $not$libresoc.v:183831$12170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181735$12119_Y + connect \Y $not$libresoc.v:183831$12170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181729$12113 + cell $or $or$libresoc.v:183825$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379063,10 +381934,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181729$12113_Y + connect \Y $or$libresoc.v:183825$12164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181731$12115 + cell $or $or$libresoc.v:183827$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379074,10 +381945,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181731$12115_Y + connect \Y $or$libresoc.v:183827$12166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181734$12118 + cell $or $or$libresoc.v:183830$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379085,39 +381956,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181734$12118_Y + connect \Y $or$libresoc.v:183830$12169_Y end - attribute \src "libresoc.v:181693.7-181693.20" - process $proc$libresoc.v:181693$12124 + attribute \src "libresoc.v:183789.7-183789.20" + process $proc$libresoc.v:183789$12175 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181715.7-181715.19" - process $proc$libresoc.v:181715$12125 + attribute \src "libresoc.v:183811.7-183811.19" + process $proc$libresoc.v:183811$12176 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181736.3-181737.27" - process $proc$libresoc.v:181736$12120 + attribute \src "libresoc.v:183832.3-183833.27" + process $proc$libresoc.v:183832$12171 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181738.3-181746.6" - process $proc$libresoc.v:181738$12121 + attribute \src "libresoc.v:183834.3-183842.6" + process $proc$libresoc.v:183834$12172 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12122 $1\q_int$next[0:0]$12123 - attribute \src "libresoc.v:181739.5-181739.29" + assign $0\q_int$next[0:0]$12173 $1\q_int$next[0:0]$12174 + attribute \src "libresoc.v:183835.5-183835.29" switch \initial - attribute \src "libresoc.v:181739.9-181739.17" + attribute \src "libresoc.v:183835.9-183835.17" case 1'1 case end @@ -379126,56 +381997,56 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12123 1'0 + assign $1\q_int$next[0:0]$12174 1'0 case - assign $1\q_int$next[0:0]$12123 \$5 + assign $1\q_int$next[0:0]$12174 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12122 + update \q_int$next $0\q_int$next[0:0]$12173 end - connect \$9 $and$libresoc.v:181728$12112_Y - connect \$11 $or$libresoc.v:181729$12113_Y - connect \$13 $not$libresoc.v:181730$12114_Y - connect \$15 $or$libresoc.v:181731$12115_Y - connect \$1 $not$libresoc.v:181732$12116_Y - connect \$3 $and$libresoc.v:181733$12117_Y - connect \$5 $or$libresoc.v:181734$12118_Y - connect \$7 $not$libresoc.v:181735$12119_Y + connect \$9 $and$libresoc.v:183824$12163_Y + connect \$11 $or$libresoc.v:183825$12164_Y + connect \$13 $not$libresoc.v:183826$12165_Y + connect \$15 $or$libresoc.v:183827$12166_Y + connect \$1 $not$libresoc.v:183828$12167_Y + connect \$3 $and$libresoc.v:183829$12168_Y + connect \$5 $or$libresoc.v:183830$12169_Y + connect \$7 $not$libresoc.v:183831$12170_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:181754.1-181812.10" +attribute \src "libresoc.v:183850.1-183908.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:181755.7-181755.20" + attribute \src "libresoc.v:183851.7-183851.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181800.3-181808.6" - wire $0\q_int$next[0:0]$12136 - attribute \src "libresoc.v:181798.3-181799.27" + attribute \src "libresoc.v:183896.3-183904.6" + wire $0\q_int$next[0:0]$12187 + attribute \src "libresoc.v:183894.3-183895.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181800.3-181808.6" - wire $1\q_int$next[0:0]$12137 - attribute \src "libresoc.v:181777.7-181777.19" + attribute \src "libresoc.v:183896.3-183904.6" + wire $1\q_int$next[0:0]$12188 + attribute \src "libresoc.v:183873.7-183873.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181790.17-181790.96" - wire $and$libresoc.v:181790$12126_Y - attribute \src "libresoc.v:181795.17-181795.96" - wire $and$libresoc.v:181795$12131_Y - attribute \src "libresoc.v:181792.18-181792.93" - wire $not$libresoc.v:181792$12128_Y - attribute \src "libresoc.v:181794.17-181794.92" - wire $not$libresoc.v:181794$12130_Y - attribute \src "libresoc.v:181797.17-181797.92" - wire $not$libresoc.v:181797$12133_Y - attribute \src "libresoc.v:181791.18-181791.98" - wire $or$libresoc.v:181791$12127_Y - attribute \src "libresoc.v:181793.18-181793.99" - wire $or$libresoc.v:181793$12129_Y - attribute \src "libresoc.v:181796.17-181796.97" - wire $or$libresoc.v:181796$12132_Y + attribute \src "libresoc.v:183886.17-183886.96" + wire $and$libresoc.v:183886$12177_Y + attribute \src "libresoc.v:183891.17-183891.96" + wire $and$libresoc.v:183891$12182_Y + attribute \src "libresoc.v:183888.18-183888.93" + wire $not$libresoc.v:183888$12179_Y + attribute \src "libresoc.v:183890.17-183890.92" + wire $not$libresoc.v:183890$12181_Y + attribute \src "libresoc.v:183893.17-183893.92" + wire $not$libresoc.v:183893$12184_Y + attribute \src "libresoc.v:183887.18-183887.98" + wire $or$libresoc.v:183887$12178_Y + attribute \src "libresoc.v:183889.18-183889.99" + wire $or$libresoc.v:183889$12180_Y + attribute \src "libresoc.v:183892.17-183892.97" + wire $or$libresoc.v:183892$12183_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379192,11 +382063,11 @@ module \rst_l$26 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181755.7-181755.15" + attribute \src "libresoc.v:183851.7-183851.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379213,7 +382084,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181790$12126 + cell $and $and$libresoc.v:183886$12177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379221,10 +382092,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181790$12126_Y + connect \Y $and$libresoc.v:183886$12177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181795$12131 + cell $and $and$libresoc.v:183891$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379232,34 +382103,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181795$12131_Y + connect \Y $and$libresoc.v:183891$12182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181792$12128 + cell $not $not$libresoc.v:183888$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181792$12128_Y + connect \Y $not$libresoc.v:183888$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181794$12130 + cell $not $not$libresoc.v:183890$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181794$12130_Y + connect \Y $not$libresoc.v:183890$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181797$12133 + cell $not $not$libresoc.v:183893$12184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181797$12133_Y + connect \Y $not$libresoc.v:183893$12184_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181791$12127 + cell $or $or$libresoc.v:183887$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379267,10 +382138,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181791$12127_Y + connect \Y $or$libresoc.v:183887$12178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181793$12129 + cell $or $or$libresoc.v:183889$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379278,10 +382149,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181793$12129_Y + connect \Y $or$libresoc.v:183889$12180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181796$12132 + cell $or $or$libresoc.v:183892$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379289,39 +382160,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181796$12132_Y + connect \Y $or$libresoc.v:183892$12183_Y end - attribute \src "libresoc.v:181755.7-181755.20" - process $proc$libresoc.v:181755$12138 + attribute \src "libresoc.v:183851.7-183851.20" + process $proc$libresoc.v:183851$12189 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181777.7-181777.19" - process $proc$libresoc.v:181777$12139 + attribute \src "libresoc.v:183873.7-183873.19" + process $proc$libresoc.v:183873$12190 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181798.3-181799.27" - process $proc$libresoc.v:181798$12134 + attribute \src "libresoc.v:183894.3-183895.27" + process $proc$libresoc.v:183894$12185 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181800.3-181808.6" - process $proc$libresoc.v:181800$12135 + attribute \src "libresoc.v:183896.3-183904.6" + process $proc$libresoc.v:183896$12186 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12136 $1\q_int$next[0:0]$12137 - attribute \src "libresoc.v:181801.5-181801.29" + assign $0\q_int$next[0:0]$12187 $1\q_int$next[0:0]$12188 + attribute \src "libresoc.v:183897.5-183897.29" switch \initial - attribute \src "libresoc.v:181801.9-181801.17" + attribute \src "libresoc.v:183897.9-183897.17" case 1'1 case end @@ -379330,56 +382201,56 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12137 1'0 + assign $1\q_int$next[0:0]$12188 1'0 case - assign $1\q_int$next[0:0]$12137 \$5 + assign $1\q_int$next[0:0]$12188 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12136 + update \q_int$next $0\q_int$next[0:0]$12187 end - connect \$9 $and$libresoc.v:181790$12126_Y - connect \$11 $or$libresoc.v:181791$12127_Y - connect \$13 $not$libresoc.v:181792$12128_Y - connect \$15 $or$libresoc.v:181793$12129_Y - connect \$1 $not$libresoc.v:181794$12130_Y - connect \$3 $and$libresoc.v:181795$12131_Y - connect \$5 $or$libresoc.v:181796$12132_Y - connect \$7 $not$libresoc.v:181797$12133_Y + connect \$9 $and$libresoc.v:183886$12177_Y + connect \$11 $or$libresoc.v:183887$12178_Y + connect \$13 $not$libresoc.v:183888$12179_Y + connect \$15 $or$libresoc.v:183889$12180_Y + connect \$1 $not$libresoc.v:183890$12181_Y + connect \$3 $and$libresoc.v:183891$12182_Y + connect \$5 $or$libresoc.v:183892$12183_Y + connect \$7 $not$libresoc.v:183893$12184_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:181816.1-181874.10" +attribute \src "libresoc.v:183912.1-183970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:181817.7-181817.20" + attribute \src "libresoc.v:183913.7-183913.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181862.3-181870.6" - wire $0\q_int$next[0:0]$12150 - attribute \src "libresoc.v:181860.3-181861.27" + attribute \src "libresoc.v:183958.3-183966.6" + wire $0\q_int$next[0:0]$12201 + attribute \src "libresoc.v:183956.3-183957.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181862.3-181870.6" - wire $1\q_int$next[0:0]$12151 - attribute \src "libresoc.v:181839.7-181839.19" + attribute \src "libresoc.v:183958.3-183966.6" + wire $1\q_int$next[0:0]$12202 + attribute \src "libresoc.v:183935.7-183935.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181852.17-181852.96" - wire $and$libresoc.v:181852$12140_Y - attribute \src "libresoc.v:181857.17-181857.96" - wire $and$libresoc.v:181857$12145_Y - attribute \src "libresoc.v:181854.18-181854.93" - wire $not$libresoc.v:181854$12142_Y - attribute \src "libresoc.v:181856.17-181856.92" - wire $not$libresoc.v:181856$12144_Y - attribute \src "libresoc.v:181859.17-181859.92" - wire $not$libresoc.v:181859$12147_Y - attribute \src "libresoc.v:181853.18-181853.98" - wire $or$libresoc.v:181853$12141_Y - attribute \src "libresoc.v:181855.18-181855.99" - wire $or$libresoc.v:181855$12143_Y - attribute \src "libresoc.v:181858.17-181858.97" - wire $or$libresoc.v:181858$12146_Y + attribute \src "libresoc.v:183948.17-183948.96" + wire $and$libresoc.v:183948$12191_Y + attribute \src "libresoc.v:183953.17-183953.96" + wire $and$libresoc.v:183953$12196_Y + attribute \src "libresoc.v:183950.18-183950.93" + wire $not$libresoc.v:183950$12193_Y + attribute \src "libresoc.v:183952.17-183952.92" + wire $not$libresoc.v:183952$12195_Y + attribute \src "libresoc.v:183955.17-183955.92" + wire $not$libresoc.v:183955$12198_Y + attribute \src "libresoc.v:183949.18-183949.98" + wire $or$libresoc.v:183949$12192_Y + attribute \src "libresoc.v:183951.18-183951.99" + wire $or$libresoc.v:183951$12194_Y + attribute \src "libresoc.v:183954.17-183954.97" + wire $or$libresoc.v:183954$12197_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379396,11 +382267,11 @@ module \rst_l$42 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181817.7-181817.15" + attribute \src "libresoc.v:183913.7-183913.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379417,7 +382288,7 @@ module \rst_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181852$12140 + cell $and $and$libresoc.v:183948$12191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379425,10 +382296,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181852$12140_Y + connect \Y $and$libresoc.v:183948$12191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181857$12145 + cell $and $and$libresoc.v:183953$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379436,34 +382307,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181857$12145_Y + connect \Y $and$libresoc.v:183953$12196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181854$12142 + cell $not $not$libresoc.v:183950$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181854$12142_Y + connect \Y $not$libresoc.v:183950$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181856$12144 + cell $not $not$libresoc.v:183952$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181856$12144_Y + connect \Y $not$libresoc.v:183952$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181859$12147 + cell $not $not$libresoc.v:183955$12198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181859$12147_Y + connect \Y $not$libresoc.v:183955$12198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181853$12141 + cell $or $or$libresoc.v:183949$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379471,10 +382342,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181853$12141_Y + connect \Y $or$libresoc.v:183949$12192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181855$12143 + cell $or $or$libresoc.v:183951$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379482,10 +382353,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181855$12143_Y + connect \Y $or$libresoc.v:183951$12194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181858$12146 + cell $or $or$libresoc.v:183954$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379493,39 +382364,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181858$12146_Y + connect \Y $or$libresoc.v:183954$12197_Y end - attribute \src "libresoc.v:181817.7-181817.20" - process $proc$libresoc.v:181817$12152 + attribute \src "libresoc.v:183913.7-183913.20" + process $proc$libresoc.v:183913$12203 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181839.7-181839.19" - process $proc$libresoc.v:181839$12153 + attribute \src "libresoc.v:183935.7-183935.19" + process $proc$libresoc.v:183935$12204 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181860.3-181861.27" - process $proc$libresoc.v:181860$12148 + attribute \src "libresoc.v:183956.3-183957.27" + process $proc$libresoc.v:183956$12199 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181862.3-181870.6" - process $proc$libresoc.v:181862$12149 + attribute \src "libresoc.v:183958.3-183966.6" + process $proc$libresoc.v:183958$12200 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12150 $1\q_int$next[0:0]$12151 - attribute \src "libresoc.v:181863.5-181863.29" + assign $0\q_int$next[0:0]$12201 $1\q_int$next[0:0]$12202 + attribute \src "libresoc.v:183959.5-183959.29" switch \initial - attribute \src "libresoc.v:181863.9-181863.17" + attribute \src "libresoc.v:183959.9-183959.17" case 1'1 case end @@ -379534,56 +382405,56 @@ module \rst_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12151 1'0 + assign $1\q_int$next[0:0]$12202 1'0 case - assign $1\q_int$next[0:0]$12151 \$5 + assign $1\q_int$next[0:0]$12202 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12150 + update \q_int$next $0\q_int$next[0:0]$12201 end - connect \$9 $and$libresoc.v:181852$12140_Y - connect \$11 $or$libresoc.v:181853$12141_Y - connect \$13 $not$libresoc.v:181854$12142_Y - connect \$15 $or$libresoc.v:181855$12143_Y - connect \$1 $not$libresoc.v:181856$12144_Y - connect \$3 $and$libresoc.v:181857$12145_Y - connect \$5 $or$libresoc.v:181858$12146_Y - connect \$7 $not$libresoc.v:181859$12147_Y + connect \$9 $and$libresoc.v:183948$12191_Y + connect \$11 $or$libresoc.v:183949$12192_Y + connect \$13 $not$libresoc.v:183950$12193_Y + connect \$15 $or$libresoc.v:183951$12194_Y + connect \$1 $not$libresoc.v:183952$12195_Y + connect \$3 $and$libresoc.v:183953$12196_Y + connect \$5 $or$libresoc.v:183954$12197_Y + connect \$7 $not$libresoc.v:183955$12198_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:181878.1-181936.10" +attribute \src "libresoc.v:183974.1-184032.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:181879.7-181879.20" + attribute \src "libresoc.v:183975.7-183975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181924.3-181932.6" - wire $0\q_int$next[0:0]$12164 - attribute \src "libresoc.v:181922.3-181923.27" + attribute \src "libresoc.v:184020.3-184028.6" + wire $0\q_int$next[0:0]$12215 + attribute \src "libresoc.v:184018.3-184019.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181924.3-181932.6" - wire $1\q_int$next[0:0]$12165 - attribute \src "libresoc.v:181901.7-181901.19" + attribute \src "libresoc.v:184020.3-184028.6" + wire $1\q_int$next[0:0]$12216 + attribute \src "libresoc.v:183997.7-183997.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181914.17-181914.96" - wire $and$libresoc.v:181914$12154_Y - attribute \src "libresoc.v:181919.17-181919.96" - wire $and$libresoc.v:181919$12159_Y - attribute \src "libresoc.v:181916.18-181916.93" - wire $not$libresoc.v:181916$12156_Y - attribute \src "libresoc.v:181918.17-181918.92" - wire $not$libresoc.v:181918$12158_Y - attribute \src "libresoc.v:181921.17-181921.92" - wire $not$libresoc.v:181921$12161_Y - attribute \src "libresoc.v:181915.18-181915.98" - wire $or$libresoc.v:181915$12155_Y - attribute \src "libresoc.v:181917.18-181917.99" - wire $or$libresoc.v:181917$12157_Y - attribute \src "libresoc.v:181920.17-181920.97" - wire $or$libresoc.v:181920$12160_Y + attribute \src "libresoc.v:184010.17-184010.96" + wire $and$libresoc.v:184010$12205_Y + attribute \src "libresoc.v:184015.17-184015.96" + wire $and$libresoc.v:184015$12210_Y + attribute \src "libresoc.v:184012.18-184012.93" + wire $not$libresoc.v:184012$12207_Y + attribute \src "libresoc.v:184014.17-184014.92" + wire $not$libresoc.v:184014$12209_Y + attribute \src "libresoc.v:184017.17-184017.92" + wire $not$libresoc.v:184017$12212_Y + attribute \src "libresoc.v:184011.18-184011.98" + wire $or$libresoc.v:184011$12206_Y + attribute \src "libresoc.v:184013.18-184013.99" + wire $or$libresoc.v:184013$12208_Y + attribute \src "libresoc.v:184016.17-184016.97" + wire $or$libresoc.v:184016$12211_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379600,11 +382471,11 @@ module \rst_l$58 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181879.7-181879.15" + attribute \src "libresoc.v:183975.7-183975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379621,7 +382492,7 @@ module \rst_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181914$12154 + cell $and $and$libresoc.v:184010$12205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379629,10 +382500,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181914$12154_Y + connect \Y $and$libresoc.v:184010$12205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181919$12159 + cell $and $and$libresoc.v:184015$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379640,34 +382511,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181919$12159_Y + connect \Y $and$libresoc.v:184015$12210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181916$12156 + cell $not $not$libresoc.v:184012$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181916$12156_Y + connect \Y $not$libresoc.v:184012$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181918$12158 + cell $not $not$libresoc.v:184014$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181918$12158_Y + connect \Y $not$libresoc.v:184014$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181921$12161 + cell $not $not$libresoc.v:184017$12212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181921$12161_Y + connect \Y $not$libresoc.v:184017$12212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181915$12155 + cell $or $or$libresoc.v:184011$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379675,10 +382546,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181915$12155_Y + connect \Y $or$libresoc.v:184011$12206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181917$12157 + cell $or $or$libresoc.v:184013$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379686,10 +382557,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181917$12157_Y + connect \Y $or$libresoc.v:184013$12208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181920$12160 + cell $or $or$libresoc.v:184016$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379697,39 +382568,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181920$12160_Y + connect \Y $or$libresoc.v:184016$12211_Y end - attribute \src "libresoc.v:181879.7-181879.20" - process $proc$libresoc.v:181879$12166 + attribute \src "libresoc.v:183975.7-183975.20" + process $proc$libresoc.v:183975$12217 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181901.7-181901.19" - process $proc$libresoc.v:181901$12167 + attribute \src "libresoc.v:183997.7-183997.19" + process $proc$libresoc.v:183997$12218 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181922.3-181923.27" - process $proc$libresoc.v:181922$12162 + attribute \src "libresoc.v:184018.3-184019.27" + process $proc$libresoc.v:184018$12213 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181924.3-181932.6" - process $proc$libresoc.v:181924$12163 + attribute \src "libresoc.v:184020.3-184028.6" + process $proc$libresoc.v:184020$12214 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12164 $1\q_int$next[0:0]$12165 - attribute \src "libresoc.v:181925.5-181925.29" + assign $0\q_int$next[0:0]$12215 $1\q_int$next[0:0]$12216 + attribute \src "libresoc.v:184021.5-184021.29" switch \initial - attribute \src "libresoc.v:181925.9-181925.17" + attribute \src "libresoc.v:184021.9-184021.17" case 1'1 case end @@ -379738,56 +382609,56 @@ module \rst_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12165 1'0 + assign $1\q_int$next[0:0]$12216 1'0 case - assign $1\q_int$next[0:0]$12165 \$5 + assign $1\q_int$next[0:0]$12216 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12164 + update \q_int$next $0\q_int$next[0:0]$12215 end - connect \$9 $and$libresoc.v:181914$12154_Y - connect \$11 $or$libresoc.v:181915$12155_Y - connect \$13 $not$libresoc.v:181916$12156_Y - connect \$15 $or$libresoc.v:181917$12157_Y - connect \$1 $not$libresoc.v:181918$12158_Y - connect \$3 $and$libresoc.v:181919$12159_Y - connect \$5 $or$libresoc.v:181920$12160_Y - connect \$7 $not$libresoc.v:181921$12161_Y + connect \$9 $and$libresoc.v:184010$12205_Y + connect \$11 $or$libresoc.v:184011$12206_Y + connect \$13 $not$libresoc.v:184012$12207_Y + connect \$15 $or$libresoc.v:184013$12208_Y + connect \$1 $not$libresoc.v:184014$12209_Y + connect \$3 $and$libresoc.v:184015$12210_Y + connect \$5 $or$libresoc.v:184016$12211_Y + connect \$7 $not$libresoc.v:184017$12212_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:181940.1-181998.10" +attribute \src "libresoc.v:184036.1-184094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:181941.7-181941.20" + attribute \src "libresoc.v:184037.7-184037.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181986.3-181994.6" - wire $0\q_int$next[0:0]$12178 - attribute \src "libresoc.v:181984.3-181985.27" + attribute \src "libresoc.v:184082.3-184090.6" + wire $0\q_int$next[0:0]$12229 + attribute \src "libresoc.v:184080.3-184081.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181986.3-181994.6" - wire $1\q_int$next[0:0]$12179 - attribute \src "libresoc.v:181963.7-181963.19" + attribute \src "libresoc.v:184082.3-184090.6" + wire $1\q_int$next[0:0]$12230 + attribute \src "libresoc.v:184059.7-184059.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181976.17-181976.96" - wire $and$libresoc.v:181976$12168_Y - attribute \src "libresoc.v:181981.17-181981.96" - wire $and$libresoc.v:181981$12173_Y - attribute \src "libresoc.v:181978.18-181978.93" - wire $not$libresoc.v:181978$12170_Y - attribute \src "libresoc.v:181980.17-181980.92" - wire $not$libresoc.v:181980$12172_Y - attribute \src "libresoc.v:181983.17-181983.92" - wire $not$libresoc.v:181983$12175_Y - attribute \src "libresoc.v:181977.18-181977.98" - wire $or$libresoc.v:181977$12169_Y - attribute \src "libresoc.v:181979.18-181979.99" - wire $or$libresoc.v:181979$12171_Y - attribute \src "libresoc.v:181982.17-181982.97" - wire $or$libresoc.v:181982$12174_Y + attribute \src "libresoc.v:184072.17-184072.96" + wire $and$libresoc.v:184072$12219_Y + attribute \src "libresoc.v:184077.17-184077.96" + wire $and$libresoc.v:184077$12224_Y + attribute \src "libresoc.v:184074.18-184074.93" + wire $not$libresoc.v:184074$12221_Y + attribute \src "libresoc.v:184076.17-184076.92" + wire $not$libresoc.v:184076$12223_Y + attribute \src "libresoc.v:184079.17-184079.92" + wire $not$libresoc.v:184079$12226_Y + attribute \src "libresoc.v:184073.18-184073.98" + wire $or$libresoc.v:184073$12220_Y + attribute \src "libresoc.v:184075.18-184075.99" + wire $or$libresoc.v:184075$12222_Y + attribute \src "libresoc.v:184078.17-184078.97" + wire $or$libresoc.v:184078$12225_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379804,11 +382675,11 @@ module \rst_l$70 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:181941.7-181941.15" + attribute \src "libresoc.v:184037.7-184037.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379825,7 +382696,7 @@ module \rst_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181976$12168 + cell $and $and$libresoc.v:184072$12219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379833,10 +382704,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181976$12168_Y + connect \Y $and$libresoc.v:184072$12219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181981$12173 + cell $and $and$libresoc.v:184077$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379844,34 +382715,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181981$12173_Y + connect \Y $and$libresoc.v:184077$12224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181978$12170 + cell $not $not$libresoc.v:184074$12221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:181978$12170_Y + connect \Y $not$libresoc.v:184074$12221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181980$12172 + cell $not $not$libresoc.v:184076$12223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181980$12172_Y + connect \Y $not$libresoc.v:184076$12223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181983$12175 + cell $not $not$libresoc.v:184079$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:181983$12175_Y + connect \Y $not$libresoc.v:184079$12226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181977$12169 + cell $or $or$libresoc.v:184073$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379879,10 +382750,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:181977$12169_Y + connect \Y $or$libresoc.v:184073$12220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181979$12171 + cell $or $or$libresoc.v:184075$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379890,10 +382761,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:181979$12171_Y + connect \Y $or$libresoc.v:184075$12222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181982$12174 + cell $or $or$libresoc.v:184078$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379901,39 +382772,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:181982$12174_Y + connect \Y $or$libresoc.v:184078$12225_Y end - attribute \src "libresoc.v:181941.7-181941.20" - process $proc$libresoc.v:181941$12180 + attribute \src "libresoc.v:184037.7-184037.20" + process $proc$libresoc.v:184037$12231 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181963.7-181963.19" - process $proc$libresoc.v:181963$12181 + attribute \src "libresoc.v:184059.7-184059.19" + process $proc$libresoc.v:184059$12232 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181984.3-181985.27" - process $proc$libresoc.v:181984$12176 + attribute \src "libresoc.v:184080.3-184081.27" + process $proc$libresoc.v:184080$12227 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181986.3-181994.6" - process $proc$libresoc.v:181986$12177 + attribute \src "libresoc.v:184082.3-184090.6" + process $proc$libresoc.v:184082$12228 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12178 $1\q_int$next[0:0]$12179 - attribute \src "libresoc.v:181987.5-181987.29" + assign $0\q_int$next[0:0]$12229 $1\q_int$next[0:0]$12230 + attribute \src "libresoc.v:184083.5-184083.29" switch \initial - attribute \src "libresoc.v:181987.9-181987.17" + attribute \src "libresoc.v:184083.9-184083.17" case 1'1 case end @@ -379942,56 +382813,56 @@ module \rst_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12179 1'0 + assign $1\q_int$next[0:0]$12230 1'0 case - assign $1\q_int$next[0:0]$12179 \$5 + assign $1\q_int$next[0:0]$12230 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12178 + update \q_int$next $0\q_int$next[0:0]$12229 end - connect \$9 $and$libresoc.v:181976$12168_Y - connect \$11 $or$libresoc.v:181977$12169_Y - connect \$13 $not$libresoc.v:181978$12170_Y - connect \$15 $or$libresoc.v:181979$12171_Y - connect \$1 $not$libresoc.v:181980$12172_Y - connect \$3 $and$libresoc.v:181981$12173_Y - connect \$5 $or$libresoc.v:181982$12174_Y - connect \$7 $not$libresoc.v:181983$12175_Y + connect \$9 $and$libresoc.v:184072$12219_Y + connect \$11 $or$libresoc.v:184073$12220_Y + connect \$13 $not$libresoc.v:184074$12221_Y + connect \$15 $or$libresoc.v:184075$12222_Y + connect \$1 $not$libresoc.v:184076$12223_Y + connect \$3 $and$libresoc.v:184077$12224_Y + connect \$5 $or$libresoc.v:184078$12225_Y + connect \$7 $not$libresoc.v:184079$12226_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:182002.1-182060.10" +attribute \src "libresoc.v:184098.1-184156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:182003.7-182003.20" + attribute \src "libresoc.v:184099.7-184099.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182048.3-182056.6" - wire $0\q_int$next[0:0]$12192 - attribute \src "libresoc.v:182046.3-182047.27" + attribute \src "libresoc.v:184144.3-184152.6" + wire $0\q_int$next[0:0]$12243 + attribute \src "libresoc.v:184142.3-184143.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182048.3-182056.6" - wire $1\q_int$next[0:0]$12193 - attribute \src "libresoc.v:182025.7-182025.19" + attribute \src "libresoc.v:184144.3-184152.6" + wire $1\q_int$next[0:0]$12244 + attribute \src "libresoc.v:184121.7-184121.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182038.17-182038.96" - wire $and$libresoc.v:182038$12182_Y - attribute \src "libresoc.v:182043.17-182043.96" - wire $and$libresoc.v:182043$12187_Y - attribute \src "libresoc.v:182040.18-182040.93" - wire $not$libresoc.v:182040$12184_Y - attribute \src "libresoc.v:182042.17-182042.92" - wire $not$libresoc.v:182042$12186_Y - attribute \src "libresoc.v:182045.17-182045.92" - wire $not$libresoc.v:182045$12189_Y - attribute \src "libresoc.v:182039.18-182039.98" - wire $or$libresoc.v:182039$12183_Y - attribute \src "libresoc.v:182041.18-182041.99" - wire $or$libresoc.v:182041$12185_Y - attribute \src "libresoc.v:182044.17-182044.97" - wire $or$libresoc.v:182044$12188_Y + attribute \src "libresoc.v:184134.17-184134.96" + wire $and$libresoc.v:184134$12233_Y + attribute \src "libresoc.v:184139.17-184139.96" + wire $and$libresoc.v:184139$12238_Y + attribute \src "libresoc.v:184136.18-184136.93" + wire $not$libresoc.v:184136$12235_Y + attribute \src "libresoc.v:184138.17-184138.92" + wire $not$libresoc.v:184138$12237_Y + attribute \src "libresoc.v:184141.17-184141.92" + wire $not$libresoc.v:184141$12240_Y + attribute \src "libresoc.v:184135.18-184135.98" + wire $or$libresoc.v:184135$12234_Y + attribute \src "libresoc.v:184137.18-184137.99" + wire $or$libresoc.v:184137$12236_Y + attribute \src "libresoc.v:184140.17-184140.97" + wire $or$libresoc.v:184140$12239_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -380008,11 +382879,11 @@ module \rst_l$87 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:182003.7-182003.15" + attribute \src "libresoc.v:184099.7-184099.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380029,7 +382900,7 @@ module \rst_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182038$12182 + cell $and $and$libresoc.v:184134$12233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380037,10 +382908,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182038$12182_Y + connect \Y $and$libresoc.v:184134$12233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182043$12187 + cell $and $and$libresoc.v:184139$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380048,34 +382919,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182043$12187_Y + connect \Y $and$libresoc.v:184139$12238_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182040$12184 + cell $not $not$libresoc.v:184136$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:182040$12184_Y + connect \Y $not$libresoc.v:184136$12235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182042$12186 + cell $not $not$libresoc.v:184138$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:182042$12186_Y + connect \Y $not$libresoc.v:184138$12237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182045$12189 + cell $not $not$libresoc.v:184141$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:182045$12189_Y + connect \Y $not$libresoc.v:184141$12240_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182039$12183 + cell $or $or$libresoc.v:184135$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380083,10 +382954,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:182039$12183_Y + connect \Y $or$libresoc.v:184135$12234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182041$12185 + cell $or $or$libresoc.v:184137$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380094,10 +382965,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:182041$12185_Y + connect \Y $or$libresoc.v:184137$12236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182044$12188 + cell $or $or$libresoc.v:184140$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380105,39 +382976,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:182044$12188_Y + connect \Y $or$libresoc.v:184140$12239_Y end - attribute \src "libresoc.v:182003.7-182003.20" - process $proc$libresoc.v:182003$12194 + attribute \src "libresoc.v:184099.7-184099.20" + process $proc$libresoc.v:184099$12245 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182025.7-182025.19" - process $proc$libresoc.v:182025$12195 + attribute \src "libresoc.v:184121.7-184121.19" + process $proc$libresoc.v:184121$12246 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182046.3-182047.27" - process $proc$libresoc.v:182046$12190 + attribute \src "libresoc.v:184142.3-184143.27" + process $proc$libresoc.v:184142$12241 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182048.3-182056.6" - process $proc$libresoc.v:182048$12191 + attribute \src "libresoc.v:184144.3-184152.6" + process $proc$libresoc.v:184144$12242 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12192 $1\q_int$next[0:0]$12193 - attribute \src "libresoc.v:182049.5-182049.29" + assign $0\q_int$next[0:0]$12243 $1\q_int$next[0:0]$12244 + attribute \src "libresoc.v:184145.5-184145.29" switch \initial - attribute \src "libresoc.v:182049.9-182049.17" + attribute \src "libresoc.v:184145.9-184145.17" case 1'1 case end @@ -380146,92 +383017,92 @@ module \rst_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12193 1'0 + assign $1\q_int$next[0:0]$12244 1'0 case - assign $1\q_int$next[0:0]$12193 \$5 + assign $1\q_int$next[0:0]$12244 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12192 + update \q_int$next $0\q_int$next[0:0]$12243 end - connect \$9 $and$libresoc.v:182038$12182_Y - connect \$11 $or$libresoc.v:182039$12183_Y - connect \$13 $not$libresoc.v:182040$12184_Y - connect \$15 $or$libresoc.v:182041$12185_Y - connect \$1 $not$libresoc.v:182042$12186_Y - connect \$3 $and$libresoc.v:182043$12187_Y - connect \$5 $or$libresoc.v:182044$12188_Y - connect \$7 $not$libresoc.v:182045$12189_Y + connect \$9 $and$libresoc.v:184134$12233_Y + connect \$11 $or$libresoc.v:184135$12234_Y + connect \$13 $not$libresoc.v:184136$12235_Y + connect \$15 $or$libresoc.v:184137$12236_Y + connect \$1 $not$libresoc.v:184138$12237_Y + connect \$3 $and$libresoc.v:184139$12238_Y + connect \$5 $or$libresoc.v:184140$12239_Y + connect \$7 $not$libresoc.v:184141$12240_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:182064.1-182469.10" +attribute \src "libresoc.v:184160.1-184569.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:182427.3-182452.6" + attribute \src "libresoc.v:184527.3-184552.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:182065.7-182065.20" + attribute \src "libresoc.v:184161.7-184161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182427.3-182452.6" + attribute \src "libresoc.v:184527.3-184552.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:182427.3-182452.6" + attribute \src "libresoc.v:184527.3-184552.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:182406.18-182406.122" - wire $and$libresoc.v:182406$12197_Y - attribute \src "libresoc.v:182408.18-182408.122" - wire $and$libresoc.v:182408$12199_Y - attribute \src "libresoc.v:182417.18-182417.105" - wire $and$libresoc.v:182417$12212_Y - attribute \src "libresoc.v:182420.18-182420.105" - wire $and$libresoc.v:182420$12215_Y - attribute \src "libresoc.v:182416.18-182416.123" - wire $eq$libresoc.v:182416$12211_Y - attribute \src "libresoc.v:182419.18-182419.123" - wire $eq$libresoc.v:182419$12214_Y - attribute \src "libresoc.v:182422.18-182422.117" - wire $eq$libresoc.v:182422$12217_Y - attribute \src "libresoc.v:182409.18-182409.97" - wire width 65 $extend$libresoc.v:182409$12200_Y - attribute \src "libresoc.v:182410.18-182410.91" - wire width 65 $extend$libresoc.v:182410$12202_Y - attribute \src "libresoc.v:182412.18-182412.97" - wire width 65 $extend$libresoc.v:182412$12205_Y - attribute \src "libresoc.v:182413.18-182413.91" - wire width 65 $extend$libresoc.v:182413$12207_Y - attribute \src "libresoc.v:182425.18-182425.99" - wire width 128 $extend$libresoc.v:182425$12220_Y - attribute \src "libresoc.v:182415.18-182415.112" - wire $ge$libresoc.v:182415$12210_Y - attribute \src "libresoc.v:182418.18-182418.124" - wire $ge$libresoc.v:182418$12213_Y - attribute \src "libresoc.v:182409.18-182409.97" - wire width 65 $neg$libresoc.v:182409$12201_Y - attribute \src "libresoc.v:182412.18-182412.97" - wire width 65 $neg$libresoc.v:182412$12206_Y - attribute \src "libresoc.v:182410.18-182410.91" - wire width 65 $pos$libresoc.v:182410$12203_Y - attribute \src "libresoc.v:182413.18-182413.91" - wire width 65 $pos$libresoc.v:182413$12208_Y - attribute \src "libresoc.v:182425.18-182425.99" - wire width 128 $pos$libresoc.v:182425$12221_Y - attribute \src "libresoc.v:182424.18-182424.117" - wire width 95 $sshl$libresoc.v:182424$12219_Y - attribute \src "libresoc.v:182426.18-182426.111" - wire width 191 $sshl$libresoc.v:182426$12222_Y - attribute \src "libresoc.v:182405.18-182405.131" - wire $ternary$libresoc.v:182405$12196_Y - attribute \src "libresoc.v:182407.18-182407.131" - wire $ternary$libresoc.v:182407$12198_Y - attribute \src "libresoc.v:182411.18-182411.119" - wire width 65 $ternary$libresoc.v:182411$12204_Y - attribute \src "libresoc.v:182414.18-182414.120" - wire width 65 $ternary$libresoc.v:182414$12209_Y - attribute \src "libresoc.v:182421.18-182421.130" - wire width 32 $ternary$libresoc.v:182421$12216_Y - attribute \src "libresoc.v:182423.18-182423.131" - wire width 32 $ternary$libresoc.v:182423$12218_Y + attribute \src "libresoc.v:184506.18-184506.122" + wire $and$libresoc.v:184506$12248_Y + attribute \src "libresoc.v:184508.18-184508.122" + wire $and$libresoc.v:184508$12250_Y + attribute \src "libresoc.v:184517.18-184517.105" + wire $and$libresoc.v:184517$12263_Y + attribute \src "libresoc.v:184520.18-184520.105" + wire $and$libresoc.v:184520$12266_Y + attribute \src "libresoc.v:184516.18-184516.123" + wire $eq$libresoc.v:184516$12262_Y + attribute \src "libresoc.v:184519.18-184519.123" + wire $eq$libresoc.v:184519$12265_Y + attribute \src "libresoc.v:184522.18-184522.117" + wire $eq$libresoc.v:184522$12268_Y + attribute \src "libresoc.v:184509.18-184509.97" + wire width 65 $extend$libresoc.v:184509$12251_Y + attribute \src "libresoc.v:184510.18-184510.91" + wire width 65 $extend$libresoc.v:184510$12253_Y + attribute \src "libresoc.v:184512.18-184512.97" + wire width 65 $extend$libresoc.v:184512$12256_Y + attribute \src "libresoc.v:184513.18-184513.91" + wire width 65 $extend$libresoc.v:184513$12258_Y + attribute \src "libresoc.v:184525.18-184525.99" + wire width 128 $extend$libresoc.v:184525$12271_Y + attribute \src "libresoc.v:184515.18-184515.112" + wire $ge$libresoc.v:184515$12261_Y + attribute \src "libresoc.v:184518.18-184518.124" + wire $ge$libresoc.v:184518$12264_Y + attribute \src "libresoc.v:184509.18-184509.97" + wire width 65 $neg$libresoc.v:184509$12252_Y + attribute \src "libresoc.v:184512.18-184512.97" + wire width 65 $neg$libresoc.v:184512$12257_Y + attribute \src "libresoc.v:184510.18-184510.91" + wire width 65 $pos$libresoc.v:184510$12254_Y + attribute \src "libresoc.v:184513.18-184513.91" + wire width 65 $pos$libresoc.v:184513$12259_Y + attribute \src "libresoc.v:184525.18-184525.99" + wire width 128 $pos$libresoc.v:184525$12272_Y + attribute \src "libresoc.v:184524.18-184524.117" + wire width 95 $sshl$libresoc.v:184524$12270_Y + attribute \src "libresoc.v:184526.18-184526.111" + wire width 191 $sshl$libresoc.v:184526$12273_Y + attribute \src "libresoc.v:184505.18-184505.131" + wire $ternary$libresoc.v:184505$12247_Y + attribute \src "libresoc.v:184507.18-184507.131" + wire $ternary$libresoc.v:184507$12249_Y + attribute \src "libresoc.v:184511.18-184511.119" + wire width 65 $ternary$libresoc.v:184511$12255_Y + attribute \src "libresoc.v:184514.18-184514.120" + wire width 65 $ternary$libresoc.v:184514$12260_Y + attribute \src "libresoc.v:184521.18-184521.130" + wire width 32 $ternary$libresoc.v:184521$12267_Y + attribute \src "libresoc.v:184523.18-184523.131" + wire width 32 $ternary$libresoc.v:184523$12269_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -380300,44 +383171,46 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:182065.7-182065.15" + attribute \src "libresoc.v:184161.7-184161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 24 \logical_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -380436,6 +383309,7 @@ module \setup_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" @@ -380512,6 +383386,7 @@ module \setup_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -380573,7 +383448,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:182406$12197 + cell $and $and$libresoc.v:184506$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380581,10 +383456,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:182406$12197_Y + connect \Y $and$libresoc.v:184506$12248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:182408$12199 + cell $and $and$libresoc.v:184508$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380592,10 +383467,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:182408$12199_Y + connect \Y $and$libresoc.v:184508$12250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:182417$12212 + cell $and $and$libresoc.v:184517$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380603,10 +383478,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:182417$12212_Y + connect \Y $and$libresoc.v:184517$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:182420$12215 + cell $and $and$libresoc.v:184520$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380614,10 +383489,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:182420$12215_Y + connect \Y $and$libresoc.v:184520$12266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:182416$12211 + cell $eq $eq$libresoc.v:184516$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380625,10 +383500,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:182416$12211_Y + connect \Y $eq$libresoc.v:184516$12262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:182419$12214 + cell $eq $eq$libresoc.v:184519$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380636,10 +383511,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:182419$12214_Y + connect \Y $eq$libresoc.v:184519$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:182422$12217 + cell $eq $eq$libresoc.v:184522$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380647,50 +383522,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:182422$12217_Y + connect \Y $eq$libresoc.v:184522$12268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:182409$12200 + cell $pos $extend$libresoc.v:184509$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:182409$12200_Y + connect \Y $extend$libresoc.v:184509$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:182410$12202 + cell $pos $extend$libresoc.v:184510$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:182410$12202_Y + connect \Y $extend$libresoc.v:184510$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:182412$12205 + cell $pos $extend$libresoc.v:184512$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:182412$12205_Y + connect \Y $extend$libresoc.v:184512$12256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:182413$12207 + cell $pos $extend$libresoc.v:184513$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:182413$12207_Y + connect \Y $extend$libresoc.v:184513$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:182425$12220 + cell $pos $extend$libresoc.v:184525$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:182425$12220_Y + connect \Y $extend$libresoc.v:184525$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:182415$12210 + cell $ge $ge$libresoc.v:184515$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380698,10 +383573,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:182415$12210_Y + connect \Y $ge$libresoc.v:184515$12261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:182418$12213 + cell $ge $ge$libresoc.v:184518$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -380709,50 +383584,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:182418$12213_Y + connect \Y $ge$libresoc.v:184518$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:182409$12201 + cell $neg $neg$libresoc.v:184509$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:182409$12200_Y - connect \Y $neg$libresoc.v:182409$12201_Y + connect \A $extend$libresoc.v:184509$12251_Y + connect \Y $neg$libresoc.v:184509$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:182412$12206 + cell $neg $neg$libresoc.v:184512$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:182412$12205_Y - connect \Y $neg$libresoc.v:182412$12206_Y + connect \A $extend$libresoc.v:184512$12256_Y + connect \Y $neg$libresoc.v:184512$12257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:182410$12203 + cell $pos $pos$libresoc.v:184510$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:182410$12202_Y - connect \Y $pos$libresoc.v:182410$12203_Y + connect \A $extend$libresoc.v:184510$12253_Y + connect \Y $pos$libresoc.v:184510$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:182413$12208 + cell $pos $pos$libresoc.v:184513$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:182413$12207_Y - connect \Y $pos$libresoc.v:182413$12208_Y + connect \A $extend$libresoc.v:184513$12258_Y + connect \Y $pos$libresoc.v:184513$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:182425$12221 + cell $pos $pos$libresoc.v:184525$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:182425$12220_Y - connect \Y $pos$libresoc.v:182425$12221_Y + connect \A $extend$libresoc.v:184525$12271_Y + connect \Y $pos$libresoc.v:184525$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:182424$12219 + cell $sshl $sshl$libresoc.v:184524$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -380760,10 +383635,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:182424$12219_Y + connect \Y $sshl$libresoc.v:184524$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:182426$12222 + cell $sshl $sshl$libresoc.v:184526$12273 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380771,72 +383646,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:182426$12222_Y + connect \Y $sshl$libresoc.v:184526$12273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:182405$12196 + cell $mux $ternary$libresoc.v:184505$12247 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:182405$12196_Y + connect \Y $ternary$libresoc.v:184505$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:182407$12198 + cell $mux $ternary$libresoc.v:184507$12249 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:182407$12198_Y + connect \Y $ternary$libresoc.v:184507$12249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:182411$12204 + cell $mux $ternary$libresoc.v:184511$12255 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:182411$12204_Y + connect \Y $ternary$libresoc.v:184511$12255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:182414$12209 + cell $mux $ternary$libresoc.v:184514$12260 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:182414$12209_Y + connect \Y $ternary$libresoc.v:184514$12260_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:182421$12216 + cell $mux $ternary$libresoc.v:184521$12267 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:182421$12216_Y + connect \Y $ternary$libresoc.v:184521$12267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:182423$12218 + cell $mux $ternary$libresoc.v:184523$12269 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:182423$12218_Y + connect \Y $ternary$libresoc.v:184523$12269_Y end - attribute \src "libresoc.v:182065.7-182065.20" - process $proc$libresoc.v:182065$12224 + attribute \src "libresoc.v:184161.7-184161.20" + process $proc$libresoc.v:184161$12275 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182427.3-182452.6" - process $proc$libresoc.v:182427$12223 + attribute \src "libresoc.v:184527.3-184552.6" + process $proc$libresoc.v:184527$12274 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:182428.5-182428.29" + attribute \src "libresoc.v:184528.5-184528.29" switch \initial - attribute \src "libresoc.v:182428.9-182428.17" + attribute \src "libresoc.v:184528.9-184528.17" case 1'1 case end @@ -380868,28 +383743,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:182405$12196_Y - connect \$23 $and$libresoc.v:182406$12197_Y - connect \$25 $ternary$libresoc.v:182407$12198_Y - connect \$27 $and$libresoc.v:182408$12199_Y - connect \$30 $neg$libresoc.v:182409$12201_Y - connect \$32 $pos$libresoc.v:182410$12203_Y - connect \$34 $ternary$libresoc.v:182411$12204_Y - connect \$37 $neg$libresoc.v:182412$12206_Y - connect \$39 $pos$libresoc.v:182413$12208_Y - connect \$41 $ternary$libresoc.v:182414$12209_Y - connect \$43 $ge$libresoc.v:182415$12210_Y - connect \$45 $eq$libresoc.v:182416$12211_Y - connect \$47 $and$libresoc.v:182417$12212_Y - connect \$49 $ge$libresoc.v:182418$12213_Y - connect \$51 $eq$libresoc.v:182419$12214_Y - connect \$53 $and$libresoc.v:182420$12215_Y - connect \$55 $ternary$libresoc.v:182421$12216_Y - connect \$57 $eq$libresoc.v:182422$12217_Y - connect \$59 $ternary$libresoc.v:182423$12218_Y - connect \$62 $sshl$libresoc.v:182424$12219_Y - connect \$61 $pos$libresoc.v:182425$12221_Y - connect \$66 $sshl$libresoc.v:182426$12222_Y + connect \$21 $ternary$libresoc.v:184505$12247_Y + connect \$23 $and$libresoc.v:184506$12248_Y + connect \$25 $ternary$libresoc.v:184507$12249_Y + connect \$27 $and$libresoc.v:184508$12250_Y + connect \$30 $neg$libresoc.v:184509$12252_Y + connect \$32 $pos$libresoc.v:184510$12254_Y + connect \$34 $ternary$libresoc.v:184511$12255_Y + connect \$37 $neg$libresoc.v:184512$12257_Y + connect \$39 $pos$libresoc.v:184513$12259_Y + connect \$41 $ternary$libresoc.v:184514$12260_Y + connect \$43 $ge$libresoc.v:184515$12261_Y + connect \$45 $eq$libresoc.v:184516$12262_Y + connect \$47 $and$libresoc.v:184517$12263_Y + connect \$49 $ge$libresoc.v:184518$12264_Y + connect \$51 $eq$libresoc.v:184519$12265_Y + connect \$53 $and$libresoc.v:184520$12266_Y + connect \$55 $ternary$libresoc.v:184521$12267_Y + connect \$57 $eq$libresoc.v:184522$12268_Y + connect \$59 $ternary$libresoc.v:184523$12269_Y + connect \$62 $sshl$libresoc.v:184524$12270_Y + connect \$61 $pos$libresoc.v:184525$12272_Y + connect \$66 $sshl$libresoc.v:184526$12273_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -380907,513 +383782,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:182473.1-183676.10" +attribute \src "libresoc.v:184573.1-185780.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:183247.3-183248.25" + attribute \src "libresoc.v:185351.3-185352.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:183245.3-183246.46" + attribute \src "libresoc.v:185349.3-185350.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:183596.3-183604.6" - wire $0\alu_l_r_alu$next[0:0]$12442 - attribute \src "libresoc.v:183163.3-183164.39" + attribute \src "libresoc.v:185700.3-185708.6" + wire $0\alu_l_r_alu$next[0:0]$12493 + attribute \src "libresoc.v:185267.3-185268.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 13 $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12359 - attribute \src "libresoc.v:183191.3-183192.75" - wire width 13 $0\alu_shift_rot0_sr_op__fn_unit[12:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12360 - attribute \src "libresoc.v:183193.3-183194.89" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 + attribute \src "libresoc.v:185295.3-185296.75" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] + attribute \src "libresoc.v:185537.3-185574.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 + attribute \src "libresoc.v:185297.3-185298.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12361 - attribute \src "libresoc.v:183195.3-183196.85" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 + attribute \src "libresoc.v:185299.3-185300.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12362 - attribute \src "libresoc.v:183209.3-183210.83" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 + attribute \src "libresoc.v:185313.3-185314.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12363 - attribute \src "libresoc.v:183213.3-183214.77" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 + attribute \src "libresoc.v:185317.3-185318.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12364 - attribute \src "libresoc.v:183221.3-183222.69" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 + attribute \src "libresoc.v:185325.3-185326.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12365 - attribute \src "libresoc.v:183189.3-183190.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 + attribute \src "libresoc.v:185293.3-185294.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12366 - attribute \src "libresoc.v:183207.3-183208.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 + attribute \src "libresoc.v:185311.3-185312.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12367 - attribute \src "libresoc.v:183217.3-183218.77" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 + attribute \src "libresoc.v:185321.3-185322.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12368 - attribute \src "libresoc.v:183219.3-183220.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 + attribute \src "libresoc.v:185323.3-185324.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12369 - attribute \src "libresoc.v:183201.3-183202.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 + attribute \src "libresoc.v:185305.3-185306.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12370 - attribute \src "libresoc.v:183203.3-183204.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 + attribute \src "libresoc.v:185307.3-185308.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12371 - attribute \src "libresoc.v:183211.3-183212.85" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 + attribute \src "libresoc.v:185315.3-185316.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12372 - attribute \src "libresoc.v:183215.3-183216.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 + attribute \src "libresoc.v:185319.3-185320.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12373 - attribute \src "libresoc.v:183199.3-183200.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 + attribute \src "libresoc.v:185303.3-185304.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12374 - attribute \src "libresoc.v:183197.3-183198.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 + attribute \src "libresoc.v:185301.3-185302.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12375 - attribute \src "libresoc.v:183205.3-183206.79" + attribute \src "libresoc.v:185537.3-185574.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 + attribute \src "libresoc.v:185309.3-185310.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:183587.3-183595.6" - wire $0\alui_l_r_alui$next[0:0]$12439 - attribute \src "libresoc.v:183165.3-183166.43" + attribute \src "libresoc.v:185691.3-185699.6" + wire $0\alui_l_r_alui$next[0:0]$12490 + attribute \src "libresoc.v:185269.3-185270.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:183471.3-183492.6" - wire width 64 $0\data_r0__o$next[63:0]$12400 - attribute \src "libresoc.v:183185.3-183186.37" + attribute \src "libresoc.v:185575.3-185596.6" + wire width 64 $0\data_r0__o$next[63:0]$12451 + attribute \src "libresoc.v:185289.3-185290.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:183471.3-183492.6" - wire $0\data_r0__o_ok$next[0:0]$12401 - attribute \src "libresoc.v:183187.3-183188.43" + attribute \src "libresoc.v:185575.3-185596.6" + wire $0\data_r0__o_ok$next[0:0]$12452 + attribute \src "libresoc.v:185291.3-185292.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:183493.3-183514.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12408 - attribute \src "libresoc.v:183181.3-183182.43" + attribute \src "libresoc.v:185597.3-185618.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12459 + attribute \src "libresoc.v:185285.3-185286.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:183493.3-183514.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12409 - attribute \src "libresoc.v:183183.3-183184.49" + attribute \src "libresoc.v:185597.3-185618.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12460 + attribute \src "libresoc.v:185287.3-185288.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:183515.3-183536.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12416 - attribute \src "libresoc.v:183177.3-183178.47" + attribute \src "libresoc.v:185619.3-185640.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12467 + attribute \src "libresoc.v:185281.3-185282.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:183515.3-183536.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12417 - attribute \src "libresoc.v:183179.3-183180.53" + attribute \src "libresoc.v:185619.3-185640.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12468 + attribute \src "libresoc.v:185283.3-185284.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:183605.3-183614.6" + attribute \src "libresoc.v:185709.3-185718.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:183615.3-183624.6" + attribute \src "libresoc.v:185719.3-185728.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:183625.3-183634.6" + attribute \src "libresoc.v:185729.3-185738.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:182474.7-182474.20" + attribute \src "libresoc.v:184574.7-184574.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183388.3-183396.6" - wire $0\opc_l_r_opc$next[0:0]$12344 - attribute \src "libresoc.v:183231.3-183232.39" + attribute \src "libresoc.v:185492.3-185500.6" + wire $0\opc_l_r_opc$next[0:0]$12395 + attribute \src "libresoc.v:185335.3-185336.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:183379.3-183387.6" - wire $0\opc_l_s_opc$next[0:0]$12341 - attribute \src "libresoc.v:183233.3-183234.39" + attribute \src "libresoc.v:185483.3-185491.6" + wire $0\opc_l_s_opc$next[0:0]$12392 + attribute \src "libresoc.v:185337.3-185338.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:183635.3-183643.6" - wire width 3 $0\prev_wr_go$next[2:0]$12448 - attribute \src "libresoc.v:183243.3-183244.37" + attribute \src "libresoc.v:185739.3-185747.6" + wire width 3 $0\prev_wr_go$next[2:0]$12499 + attribute \src "libresoc.v:185347.3-185348.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:183333.3-183342.6" + attribute \src "libresoc.v:185437.3-185446.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:183424.3-183432.6" - wire width 3 $0\req_l_r_req$next[2:0]$12356 - attribute \src "libresoc.v:183223.3-183224.39" + attribute \src "libresoc.v:185528.3-185536.6" + wire width 3 $0\req_l_r_req$next[2:0]$12407 + attribute \src "libresoc.v:185327.3-185328.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:183415.3-183423.6" - wire width 3 $0\req_l_s_req$next[2:0]$12353 - attribute \src "libresoc.v:183225.3-183226.39" + attribute \src "libresoc.v:185519.3-185527.6" + wire width 3 $0\req_l_s_req$next[2:0]$12404 + attribute \src "libresoc.v:185329.3-185330.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:183352.3-183360.6" - wire $0\rok_l_r_rdok$next[0:0]$12332 - attribute \src "libresoc.v:183239.3-183240.41" + attribute \src "libresoc.v:185456.3-185464.6" + wire $0\rok_l_r_rdok$next[0:0]$12383 + attribute \src "libresoc.v:185343.3-185344.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:183343.3-183351.6" - wire $0\rok_l_s_rdok$next[0:0]$12329 - attribute \src "libresoc.v:183241.3-183242.41" + attribute \src "libresoc.v:185447.3-185455.6" + wire $0\rok_l_s_rdok$next[0:0]$12380 + attribute \src "libresoc.v:185345.3-185346.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:183370.3-183378.6" - wire $0\rst_l_r_rst$next[0:0]$12338 - attribute \src "libresoc.v:183235.3-183236.39" + attribute \src "libresoc.v:185474.3-185482.6" + wire $0\rst_l_r_rst$next[0:0]$12389 + attribute \src "libresoc.v:185339.3-185340.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:183361.3-183369.6" - wire $0\rst_l_s_rst$next[0:0]$12335 - attribute \src "libresoc.v:183237.3-183238.39" + attribute \src "libresoc.v:185465.3-185473.6" + wire $0\rst_l_s_rst$next[0:0]$12386 + attribute \src "libresoc.v:185341.3-185342.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:183406.3-183414.6" - wire width 5 $0\src_l_r_src$next[4:0]$12350 - attribute \src "libresoc.v:183227.3-183228.39" + attribute \src "libresoc.v:185510.3-185518.6" + wire width 5 $0\src_l_r_src$next[4:0]$12401 + attribute \src "libresoc.v:185331.3-185332.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:183397.3-183405.6" - wire width 5 $0\src_l_s_src$next[4:0]$12347 - attribute \src "libresoc.v:183229.3-183230.39" + attribute \src "libresoc.v:185501.3-185509.6" + wire width 5 $0\src_l_s_src$next[4:0]$12398 + attribute \src "libresoc.v:185333.3-185334.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:183537.3-183546.6" - wire width 64 $0\src_r0$next[63:0]$12424 - attribute \src "libresoc.v:183175.3-183176.29" + attribute \src "libresoc.v:185641.3-185650.6" + wire width 64 $0\src_r0$next[63:0]$12475 + attribute \src "libresoc.v:185279.3-185280.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:183547.3-183556.6" - wire width 64 $0\src_r1$next[63:0]$12427 - attribute \src "libresoc.v:183173.3-183174.29" + attribute \src "libresoc.v:185651.3-185660.6" + wire width 64 $0\src_r1$next[63:0]$12478 + attribute \src "libresoc.v:185277.3-185278.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:183557.3-183566.6" - wire width 64 $0\src_r2$next[63:0]$12430 - attribute \src "libresoc.v:183171.3-183172.29" + attribute \src "libresoc.v:185661.3-185670.6" + wire width 64 $0\src_r2$next[63:0]$12481 + attribute \src "libresoc.v:185275.3-185276.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:183567.3-183576.6" - wire $0\src_r3$next[0:0]$12433 - attribute \src "libresoc.v:183169.3-183170.29" + attribute \src "libresoc.v:185671.3-185680.6" + wire $0\src_r3$next[0:0]$12484 + attribute \src "libresoc.v:185273.3-185274.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:183577.3-183586.6" - wire width 2 $0\src_r4$next[1:0]$12436 - attribute \src "libresoc.v:183167.3-183168.29" + attribute \src "libresoc.v:185681.3-185690.6" + wire width 2 $0\src_r4$next[1:0]$12487 + attribute \src "libresoc.v:185271.3-185272.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:182596.7-182596.24" + attribute \src "libresoc.v:184696.7-184696.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:182606.7-182606.26" + attribute \src "libresoc.v:184706.7-184706.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:183596.3-183604.6" - wire $1\alu_l_r_alu$next[0:0]$12443 - attribute \src "libresoc.v:182614.7-182614.25" + attribute \src "libresoc.v:185700.3-185708.6" + wire $1\alu_l_r_alu$next[0:0]$12494 + attribute \src "libresoc.v:184714.7-184714.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 13 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12376 - attribute \src "libresoc.v:182656.14-182656.54" - wire width 13 $1\alu_shift_rot0_sr_op__fn_unit[12:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12377 - attribute \src "libresoc.v:182660.14-182660.73" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 + attribute \src "libresoc.v:184757.14-184757.54" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] + attribute \src "libresoc.v:185537.3-185574.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 + attribute \src "libresoc.v:184761.14-184761.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12378 - attribute \src "libresoc.v:182664.7-182664.48" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 + attribute \src "libresoc.v:184765.7-184765.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12379 - attribute \src "libresoc.v:182672.13-182672.53" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 + attribute \src "libresoc.v:184773.13-184773.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12380 - attribute \src "libresoc.v:182676.7-182676.44" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 + attribute \src "libresoc.v:184777.7-184777.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12381 - attribute \src "libresoc.v:182680.14-182680.48" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 + attribute \src "libresoc.v:184781.14-184781.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12382 - attribute \src "libresoc.v:182758.13-182758.52" + attribute \src "libresoc.v:185537.3-185574.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 + attribute \src "libresoc.v:184860.13-184860.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12383 - attribute \src "libresoc.v:182762.7-182762.45" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 + attribute \src "libresoc.v:184864.7-184864.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12384 - attribute \src "libresoc.v:182766.7-182766.44" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 + attribute \src "libresoc.v:184868.7-184868.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12385 - attribute \src "libresoc.v:182770.7-182770.45" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 + attribute \src "libresoc.v:184872.7-184872.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12386 - attribute \src "libresoc.v:182774.7-182774.42" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 + attribute \src "libresoc.v:184876.7-184876.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12387 - attribute \src "libresoc.v:182778.7-182778.42" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 + attribute \src "libresoc.v:184880.7-184880.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12388 - attribute \src "libresoc.v:182782.7-182782.48" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 + attribute \src "libresoc.v:184884.7-184884.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12389 - attribute \src "libresoc.v:182786.7-182786.45" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 + attribute \src "libresoc.v:184888.7-184888.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12390 - attribute \src "libresoc.v:182790.7-182790.42" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 + attribute \src "libresoc.v:184892.7-184892.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12391 - attribute \src "libresoc.v:182794.7-182794.42" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 + attribute \src "libresoc.v:184896.7-184896.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12392 - attribute \src "libresoc.v:182798.7-182798.45" + attribute \src "libresoc.v:185537.3-185574.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 + attribute \src "libresoc.v:184900.7-184900.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:183587.3-183595.6" - wire $1\alui_l_r_alui$next[0:0]$12440 - attribute \src "libresoc.v:182810.7-182810.27" + attribute \src "libresoc.v:185691.3-185699.6" + wire $1\alui_l_r_alui$next[0:0]$12491 + attribute \src "libresoc.v:184912.7-184912.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:183471.3-183492.6" - wire width 64 $1\data_r0__o$next[63:0]$12402 - attribute \src "libresoc.v:182844.14-182844.47" + attribute \src "libresoc.v:185575.3-185596.6" + wire width 64 $1\data_r0__o$next[63:0]$12453 + attribute \src "libresoc.v:184946.14-184946.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:183471.3-183492.6" - wire $1\data_r0__o_ok$next[0:0]$12403 - attribute \src "libresoc.v:182848.7-182848.27" + attribute \src "libresoc.v:185575.3-185596.6" + wire $1\data_r0__o_ok$next[0:0]$12454 + attribute \src "libresoc.v:184950.7-184950.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:183493.3-183514.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12410 - attribute \src "libresoc.v:182852.13-182852.33" + attribute \src "libresoc.v:185597.3-185618.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12461 + attribute \src "libresoc.v:184954.13-184954.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:183493.3-183514.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12411 - attribute \src "libresoc.v:182856.7-182856.30" + attribute \src "libresoc.v:185597.3-185618.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12462 + attribute \src "libresoc.v:184958.7-184958.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:183515.3-183536.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12418 - attribute \src "libresoc.v:182860.13-182860.35" + attribute \src "libresoc.v:185619.3-185640.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12469 + attribute \src "libresoc.v:184962.13-184962.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:183515.3-183536.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12419 - attribute \src "libresoc.v:182864.7-182864.32" + attribute \src "libresoc.v:185619.3-185640.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12470 + attribute \src "libresoc.v:184966.7-184966.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:183605.3-183614.6" + attribute \src "libresoc.v:185709.3-185718.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:183615.3-183624.6" + attribute \src "libresoc.v:185719.3-185728.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:183625.3-183634.6" + attribute \src "libresoc.v:185729.3-185738.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:183388.3-183396.6" - wire $1\opc_l_r_opc$next[0:0]$12345 - attribute \src "libresoc.v:182881.7-182881.25" + attribute \src "libresoc.v:185492.3-185500.6" + wire $1\opc_l_r_opc$next[0:0]$12396 + attribute \src "libresoc.v:184983.7-184983.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:183379.3-183387.6" - wire $1\opc_l_s_opc$next[0:0]$12342 - attribute \src "libresoc.v:182885.7-182885.25" + attribute \src "libresoc.v:185483.3-185491.6" + wire $1\opc_l_s_opc$next[0:0]$12393 + attribute \src "libresoc.v:184987.7-184987.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:183635.3-183643.6" - wire width 3 $1\prev_wr_go$next[2:0]$12449 - attribute \src "libresoc.v:183015.13-183015.30" + attribute \src "libresoc.v:185739.3-185747.6" + wire width 3 $1\prev_wr_go$next[2:0]$12500 + attribute \src "libresoc.v:185119.13-185119.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:183333.3-183342.6" + attribute \src "libresoc.v:185437.3-185446.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:183424.3-183432.6" - wire width 3 $1\req_l_r_req$next[2:0]$12357 - attribute \src "libresoc.v:183023.13-183023.31" + attribute \src "libresoc.v:185528.3-185536.6" + wire width 3 $1\req_l_r_req$next[2:0]$12408 + attribute \src "libresoc.v:185127.13-185127.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:183415.3-183423.6" - wire width 3 $1\req_l_s_req$next[2:0]$12354 - attribute \src "libresoc.v:183027.13-183027.31" + attribute \src "libresoc.v:185519.3-185527.6" + wire width 3 $1\req_l_s_req$next[2:0]$12405 + attribute \src "libresoc.v:185131.13-185131.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:183352.3-183360.6" - wire $1\rok_l_r_rdok$next[0:0]$12333 - attribute \src "libresoc.v:183039.7-183039.26" + attribute \src "libresoc.v:185456.3-185464.6" + wire $1\rok_l_r_rdok$next[0:0]$12384 + attribute \src "libresoc.v:185143.7-185143.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:183343.3-183351.6" - wire $1\rok_l_s_rdok$next[0:0]$12330 - attribute \src "libresoc.v:183043.7-183043.26" + attribute \src "libresoc.v:185447.3-185455.6" + wire $1\rok_l_s_rdok$next[0:0]$12381 + attribute \src "libresoc.v:185147.7-185147.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:183370.3-183378.6" - wire $1\rst_l_r_rst$next[0:0]$12339 - attribute \src "libresoc.v:183047.7-183047.25" + attribute \src "libresoc.v:185474.3-185482.6" + wire $1\rst_l_r_rst$next[0:0]$12390 + attribute \src "libresoc.v:185151.7-185151.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:183361.3-183369.6" - wire $1\rst_l_s_rst$next[0:0]$12336 - attribute \src "libresoc.v:183051.7-183051.25" + attribute \src "libresoc.v:185465.3-185473.6" + wire $1\rst_l_s_rst$next[0:0]$12387 + attribute \src "libresoc.v:185155.7-185155.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:183406.3-183414.6" - wire width 5 $1\src_l_r_src$next[4:0]$12351 - attribute \src "libresoc.v:183069.13-183069.32" + attribute \src "libresoc.v:185510.3-185518.6" + wire width 5 $1\src_l_r_src$next[4:0]$12402 + attribute \src "libresoc.v:185173.13-185173.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:183397.3-183405.6" - wire width 5 $1\src_l_s_src$next[4:0]$12348 - attribute \src "libresoc.v:183073.13-183073.32" + attribute \src "libresoc.v:185501.3-185509.6" + wire width 5 $1\src_l_s_src$next[4:0]$12399 + attribute \src "libresoc.v:185177.13-185177.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:183537.3-183546.6" - wire width 64 $1\src_r0$next[63:0]$12425 - attribute \src "libresoc.v:183079.14-183079.43" + attribute \src "libresoc.v:185641.3-185650.6" + wire width 64 $1\src_r0$next[63:0]$12476 + attribute \src "libresoc.v:185183.14-185183.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:183547.3-183556.6" - wire width 64 $1\src_r1$next[63:0]$12428 - attribute \src "libresoc.v:183083.14-183083.43" + attribute \src "libresoc.v:185651.3-185660.6" + wire width 64 $1\src_r1$next[63:0]$12479 + attribute \src "libresoc.v:185187.14-185187.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:183557.3-183566.6" - wire width 64 $1\src_r2$next[63:0]$12431 - attribute \src "libresoc.v:183087.14-183087.43" + attribute \src "libresoc.v:185661.3-185670.6" + wire width 64 $1\src_r2$next[63:0]$12482 + attribute \src "libresoc.v:185191.14-185191.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:183567.3-183576.6" - wire $1\src_r3$next[0:0]$12434 - attribute \src "libresoc.v:183091.7-183091.20" + attribute \src "libresoc.v:185671.3-185680.6" + wire $1\src_r3$next[0:0]$12485 + attribute \src "libresoc.v:185195.7-185195.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:183577.3-183586.6" - wire width 2 $1\src_r4$next[1:0]$12437 - attribute \src "libresoc.v:183095.13-183095.26" + attribute \src "libresoc.v:185681.3-185690.6" + wire width 2 $1\src_r4$next[1:0]$12488 + attribute \src "libresoc.v:185199.13-185199.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:183433.3-183470.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12393 - attribute \src "libresoc.v:183433.3-183470.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12394 - attribute \src "libresoc.v:183433.3-183470.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12395 - attribute \src "libresoc.v:183433.3-183470.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12396 - attribute \src "libresoc.v:183433.3-183470.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12397 - attribute \src "libresoc.v:183433.3-183470.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12398 - attribute \src "libresoc.v:183471.3-183492.6" - wire width 64 $2\data_r0__o$next[63:0]$12404 - attribute \src "libresoc.v:183471.3-183492.6" - wire $2\data_r0__o_ok$next[0:0]$12405 - attribute \src "libresoc.v:183493.3-183514.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12412 - attribute \src "libresoc.v:183493.3-183514.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12413 - attribute \src "libresoc.v:183515.3-183536.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12420 - attribute \src "libresoc.v:183515.3-183536.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12421 - attribute \src "libresoc.v:183471.3-183492.6" - wire $3\data_r0__o_ok$next[0:0]$12406 - attribute \src "libresoc.v:183493.3-183514.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12414 - attribute \src "libresoc.v:183515.3-183536.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12422 - attribute \src "libresoc.v:183105.19-183105.114" - wire width 5 $and$libresoc.v:183105$12226_Y - attribute \src "libresoc.v:183106.19-183106.125" - wire $and$libresoc.v:183106$12227_Y - attribute \src "libresoc.v:183107.19-183107.125" - wire $and$libresoc.v:183107$12228_Y - attribute \src "libresoc.v:183108.19-183108.125" - wire $and$libresoc.v:183108$12229_Y - attribute \src "libresoc.v:183109.18-183109.110" - wire $and$libresoc.v:183109$12230_Y - attribute \src "libresoc.v:183110.19-183110.141" - wire width 3 $and$libresoc.v:183110$12231_Y - attribute \src "libresoc.v:183111.19-183111.121" - wire width 3 $and$libresoc.v:183111$12232_Y - attribute \src "libresoc.v:183112.19-183112.127" - wire $and$libresoc.v:183112$12233_Y - attribute \src "libresoc.v:183113.19-183113.127" - wire $and$libresoc.v:183113$12234_Y - attribute \src "libresoc.v:183114.19-183114.127" - wire $and$libresoc.v:183114$12235_Y - attribute \src "libresoc.v:183116.18-183116.98" - wire $and$libresoc.v:183116$12237_Y - attribute \src "libresoc.v:183118.18-183118.100" - wire $and$libresoc.v:183118$12239_Y - attribute \src "libresoc.v:183119.18-183119.149" - wire width 3 $and$libresoc.v:183119$12240_Y - attribute \src "libresoc.v:183121.18-183121.119" - wire width 3 $and$libresoc.v:183121$12242_Y - attribute \src "libresoc.v:183124.17-183124.123" - wire $and$libresoc.v:183124$12245_Y - attribute \src "libresoc.v:183125.18-183125.116" - wire $and$libresoc.v:183125$12246_Y - attribute \src "libresoc.v:183130.18-183130.113" - wire $and$libresoc.v:183130$12251_Y - attribute \src "libresoc.v:183131.18-183131.125" - wire width 3 $and$libresoc.v:183131$12252_Y - attribute \src "libresoc.v:183133.18-183133.112" - wire $and$libresoc.v:183133$12254_Y - attribute \src "libresoc.v:183135.18-183135.132" - wire $and$libresoc.v:183135$12256_Y - attribute \src "libresoc.v:183136.18-183136.132" - wire $and$libresoc.v:183136$12257_Y - attribute \src "libresoc.v:183137.18-183137.117" - wire $and$libresoc.v:183137$12258_Y - attribute \src "libresoc.v:183143.18-183143.136" - wire $and$libresoc.v:183143$12264_Y - attribute \src "libresoc.v:183144.18-183144.124" - wire width 3 $and$libresoc.v:183144$12265_Y - attribute \src "libresoc.v:183146.18-183146.116" - wire $and$libresoc.v:183146$12267_Y - attribute \src "libresoc.v:183147.18-183147.119" - wire $and$libresoc.v:183147$12268_Y - attribute \src "libresoc.v:183148.18-183148.121" - wire $and$libresoc.v:183148$12269_Y - attribute \src "libresoc.v:183158.18-183158.140" - wire $and$libresoc.v:183158$12279_Y - attribute \src "libresoc.v:183159.18-183159.138" - wire $and$libresoc.v:183159$12280_Y - attribute \src "libresoc.v:183160.18-183160.171" - wire width 5 $and$libresoc.v:183160$12281_Y - attribute \src "libresoc.v:183162.18-183162.129" - wire width 5 $and$libresoc.v:183162$12283_Y - attribute \src "libresoc.v:183132.18-183132.113" - wire $eq$libresoc.v:183132$12253_Y - attribute \src "libresoc.v:183134.18-183134.119" - wire $eq$libresoc.v:183134$12255_Y - attribute \src "libresoc.v:183104.19-183104.115" - wire width 5 $not$libresoc.v:183104$12225_Y - attribute \src "libresoc.v:183115.18-183115.97" - wire $not$libresoc.v:183115$12236_Y - attribute \src "libresoc.v:183117.18-183117.99" - wire $not$libresoc.v:183117$12238_Y - attribute \src "libresoc.v:183120.18-183120.113" - wire width 3 $not$libresoc.v:183120$12241_Y - attribute \src "libresoc.v:183123.18-183123.106" - wire $not$libresoc.v:183123$12244_Y - attribute \src "libresoc.v:183129.18-183129.126" - wire $not$libresoc.v:183129$12250_Y - attribute \src "libresoc.v:183140.17-183140.113" - wire width 5 $not$libresoc.v:183140$12261_Y - attribute \src "libresoc.v:183161.18-183161.136" - wire $not$libresoc.v:183161$12282_Y - attribute \src "libresoc.v:183128.18-183128.112" - wire $or$libresoc.v:183128$12249_Y - attribute \src "libresoc.v:183138.18-183138.122" - wire $or$libresoc.v:183138$12259_Y - attribute \src "libresoc.v:183139.18-183139.124" - wire $or$libresoc.v:183139$12260_Y - attribute \src "libresoc.v:183141.18-183141.155" - wire width 3 $or$libresoc.v:183141$12262_Y - attribute \src "libresoc.v:183142.18-183142.181" - wire width 5 $or$libresoc.v:183142$12263_Y - attribute \src "libresoc.v:183145.18-183145.120" - wire width 3 $or$libresoc.v:183145$12266_Y - attribute \src "libresoc.v:183151.17-183151.117" - wire width 5 $or$libresoc.v:183151$12272_Y - attribute \src "libresoc.v:183157.17-183157.104" - wire $reduce_and$libresoc.v:183157$12278_Y - attribute \src "libresoc.v:183122.18-183122.106" - wire $reduce_or$libresoc.v:183122$12243_Y - attribute \src "libresoc.v:183126.18-183126.113" - wire $reduce_or$libresoc.v:183126$12247_Y - attribute \src "libresoc.v:183127.18-183127.112" - wire $reduce_or$libresoc.v:183127$12248_Y - attribute \src "libresoc.v:183149.18-183149.165" - wire $ternary$libresoc.v:183149$12270_Y - attribute \src "libresoc.v:183150.18-183150.182" - wire width 64 $ternary$libresoc.v:183150$12271_Y - attribute \src "libresoc.v:183152.18-183152.118" - wire width 64 $ternary$libresoc.v:183152$12273_Y - attribute \src "libresoc.v:183153.18-183153.115" - wire width 64 $ternary$libresoc.v:183153$12274_Y - attribute \src "libresoc.v:183154.18-183154.118" - wire width 64 $ternary$libresoc.v:183154$12275_Y - attribute \src "libresoc.v:183155.18-183155.118" - wire $ternary$libresoc.v:183155$12276_Y - attribute \src "libresoc.v:183156.18-183156.118" - wire width 2 $ternary$libresoc.v:183156$12277_Y + attribute \src "libresoc.v:185537.3-185574.6" + wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 + attribute \src "libresoc.v:185537.3-185574.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 + attribute \src "libresoc.v:185575.3-185596.6" + wire width 64 $2\data_r0__o$next[63:0]$12455 + attribute \src "libresoc.v:185575.3-185596.6" + wire $2\data_r0__o_ok$next[0:0]$12456 + attribute \src "libresoc.v:185597.3-185618.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12463 + attribute \src "libresoc.v:185597.3-185618.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12464 + attribute \src "libresoc.v:185619.3-185640.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12471 + attribute \src "libresoc.v:185619.3-185640.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12472 + attribute \src "libresoc.v:185575.3-185596.6" + wire $3\data_r0__o_ok$next[0:0]$12457 + attribute \src "libresoc.v:185597.3-185618.6" + wire $3\data_r1__cr_a_ok$next[0:0]$12465 + attribute \src "libresoc.v:185619.3-185640.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$12473 + attribute \src "libresoc.v:185209.19-185209.114" + wire width 5 $and$libresoc.v:185209$12277_Y + attribute \src "libresoc.v:185210.19-185210.125" + wire $and$libresoc.v:185210$12278_Y + attribute \src "libresoc.v:185211.19-185211.125" + wire $and$libresoc.v:185211$12279_Y + attribute \src "libresoc.v:185212.19-185212.125" + wire $and$libresoc.v:185212$12280_Y + attribute \src "libresoc.v:185213.18-185213.110" + wire $and$libresoc.v:185213$12281_Y + attribute \src "libresoc.v:185214.19-185214.141" + wire width 3 $and$libresoc.v:185214$12282_Y + attribute \src "libresoc.v:185215.19-185215.121" + wire width 3 $and$libresoc.v:185215$12283_Y + attribute \src "libresoc.v:185216.19-185216.127" + wire $and$libresoc.v:185216$12284_Y + attribute \src "libresoc.v:185217.19-185217.127" + wire $and$libresoc.v:185217$12285_Y + attribute \src "libresoc.v:185218.19-185218.127" + wire $and$libresoc.v:185218$12286_Y + attribute \src "libresoc.v:185220.18-185220.98" + wire $and$libresoc.v:185220$12288_Y + attribute \src "libresoc.v:185222.18-185222.100" + wire $and$libresoc.v:185222$12290_Y + attribute \src "libresoc.v:185223.18-185223.149" + wire width 3 $and$libresoc.v:185223$12291_Y + attribute \src "libresoc.v:185225.18-185225.119" + wire width 3 $and$libresoc.v:185225$12293_Y + attribute \src "libresoc.v:185228.17-185228.123" + wire $and$libresoc.v:185228$12296_Y + attribute \src "libresoc.v:185229.18-185229.116" + wire $and$libresoc.v:185229$12297_Y + attribute \src "libresoc.v:185234.18-185234.113" + wire $and$libresoc.v:185234$12302_Y + attribute \src "libresoc.v:185235.18-185235.125" + wire width 3 $and$libresoc.v:185235$12303_Y + attribute \src "libresoc.v:185237.18-185237.112" + wire $and$libresoc.v:185237$12305_Y + attribute \src "libresoc.v:185239.18-185239.132" + wire $and$libresoc.v:185239$12307_Y + attribute \src "libresoc.v:185240.18-185240.132" + wire $and$libresoc.v:185240$12308_Y + attribute \src "libresoc.v:185241.18-185241.117" + wire $and$libresoc.v:185241$12309_Y + attribute \src "libresoc.v:185247.18-185247.136" + wire $and$libresoc.v:185247$12315_Y + attribute \src "libresoc.v:185248.18-185248.124" + wire width 3 $and$libresoc.v:185248$12316_Y + attribute \src "libresoc.v:185250.18-185250.116" + wire $and$libresoc.v:185250$12318_Y + attribute \src "libresoc.v:185251.18-185251.119" + wire $and$libresoc.v:185251$12319_Y + attribute \src "libresoc.v:185252.18-185252.121" + wire $and$libresoc.v:185252$12320_Y + attribute \src "libresoc.v:185262.18-185262.140" + wire $and$libresoc.v:185262$12330_Y + attribute \src "libresoc.v:185263.18-185263.138" + wire $and$libresoc.v:185263$12331_Y + attribute \src "libresoc.v:185264.18-185264.171" + wire width 5 $and$libresoc.v:185264$12332_Y + attribute \src "libresoc.v:185266.18-185266.129" + wire width 5 $and$libresoc.v:185266$12334_Y + attribute \src "libresoc.v:185236.18-185236.113" + wire $eq$libresoc.v:185236$12304_Y + attribute \src "libresoc.v:185238.18-185238.119" + wire $eq$libresoc.v:185238$12306_Y + attribute \src "libresoc.v:185208.19-185208.115" + wire width 5 $not$libresoc.v:185208$12276_Y + attribute \src "libresoc.v:185219.18-185219.97" + wire $not$libresoc.v:185219$12287_Y + attribute \src "libresoc.v:185221.18-185221.99" + wire $not$libresoc.v:185221$12289_Y + attribute \src "libresoc.v:185224.18-185224.113" + wire width 3 $not$libresoc.v:185224$12292_Y + attribute \src "libresoc.v:185227.18-185227.106" + wire $not$libresoc.v:185227$12295_Y + attribute \src "libresoc.v:185233.18-185233.126" + wire $not$libresoc.v:185233$12301_Y + attribute \src "libresoc.v:185244.17-185244.113" + wire width 5 $not$libresoc.v:185244$12312_Y + attribute \src "libresoc.v:185265.18-185265.136" + wire $not$libresoc.v:185265$12333_Y + attribute \src "libresoc.v:185232.18-185232.112" + wire $or$libresoc.v:185232$12300_Y + attribute \src "libresoc.v:185242.18-185242.122" + wire $or$libresoc.v:185242$12310_Y + attribute \src "libresoc.v:185243.18-185243.124" + wire $or$libresoc.v:185243$12311_Y + attribute \src "libresoc.v:185245.18-185245.155" + wire width 3 $or$libresoc.v:185245$12313_Y + attribute \src "libresoc.v:185246.18-185246.181" + wire width 5 $or$libresoc.v:185246$12314_Y + attribute \src "libresoc.v:185249.18-185249.120" + wire width 3 $or$libresoc.v:185249$12317_Y + attribute \src "libresoc.v:185255.17-185255.117" + wire width 5 $or$libresoc.v:185255$12323_Y + attribute \src "libresoc.v:185261.17-185261.104" + wire $reduce_and$libresoc.v:185261$12329_Y + attribute \src "libresoc.v:185226.18-185226.106" + wire $reduce_or$libresoc.v:185226$12294_Y + attribute \src "libresoc.v:185230.18-185230.113" + wire $reduce_or$libresoc.v:185230$12298_Y + attribute \src "libresoc.v:185231.18-185231.112" + wire $reduce_or$libresoc.v:185231$12299_Y + attribute \src "libresoc.v:185253.18-185253.165" + wire $ternary$libresoc.v:185253$12321_Y + attribute \src "libresoc.v:185254.18-185254.182" + wire width 64 $ternary$libresoc.v:185254$12322_Y + attribute \src "libresoc.v:185256.18-185256.118" + wire width 64 $ternary$libresoc.v:185256$12324_Y + attribute \src "libresoc.v:185257.18-185257.115" + wire width 64 $ternary$libresoc.v:185257$12325_Y + attribute \src "libresoc.v:185258.18-185258.118" + wire width 64 $ternary$libresoc.v:185258$12326_Y + attribute \src "libresoc.v:185259.18-185259.118" + wire $ternary$libresoc.v:185259$12327_Y + attribute \src "libresoc.v:185260.18-185260.118" + wire width 2 $ternary$libresoc.v:185260$12328_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -381581,23 +384456,24 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_shift_rot0_rc attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_shift_rot0_sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_shift_rot0_sr_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_shift_rot0_sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_shift_rot0_sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_shift_rot0_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -381696,6 +384572,7 @@ module \shiftrot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_shift_rot0_sr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -381754,9 +384631,9 @@ module \shiftrot0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -381812,7 +384689,7 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:182474.7-182474.15" + attribute \src "libresoc.v:184574.7-184574.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok @@ -381827,21 +384704,22 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_shift_rot0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -381930,6 +384808,7 @@ module \shiftrot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -382043,7 +384922,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:183105$12226 + cell $and $and$libresoc.v:185209$12277 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382051,10 +384930,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:183105$12226_Y + connect \Y $and$libresoc.v:185209$12277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:183106$12227 + cell $and $and$libresoc.v:185210$12278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382062,10 +384941,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:183106$12227_Y + connect \Y $and$libresoc.v:185210$12278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:183107$12228 + cell $and $and$libresoc.v:185211$12279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382073,10 +384952,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:183107$12228_Y + connect \Y $and$libresoc.v:185211$12279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:183108$12229 + cell $and $and$libresoc.v:185212$12280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382084,10 +384963,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:183108$12229_Y + connect \Y $and$libresoc.v:185212$12280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:183109$12230 + cell $and $and$libresoc.v:185213$12281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382095,10 +384974,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:183109$12230_Y + connect \Y $and$libresoc.v:185213$12281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:183110$12231 + cell $and $and$libresoc.v:185214$12282 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382106,10 +384985,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:183110$12231_Y + connect \Y $and$libresoc.v:185214$12282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:183111$12232 + cell $and $and$libresoc.v:185215$12283 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382117,10 +384996,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:183111$12232_Y + connect \Y $and$libresoc.v:185215$12283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:183112$12233 + cell $and $and$libresoc.v:185216$12284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382128,10 +385007,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:183112$12233_Y + connect \Y $and$libresoc.v:185216$12284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:183113$12234 + cell $and $and$libresoc.v:185217$12285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382139,10 +385018,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:183113$12234_Y + connect \Y $and$libresoc.v:185217$12285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:183114$12235 + cell $and $and$libresoc.v:185218$12286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382150,10 +385029,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:183114$12235_Y + connect \Y $and$libresoc.v:185218$12286_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:183116$12237 + cell $and $and$libresoc.v:185220$12288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382161,10 +385040,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:183116$12237_Y + connect \Y $and$libresoc.v:185220$12288_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:183118$12239 + cell $and $and$libresoc.v:185222$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382172,10 +385051,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:183118$12239_Y + connect \Y $and$libresoc.v:185222$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:183119$12240 + cell $and $and$libresoc.v:185223$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382183,10 +385062,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:183119$12240_Y + connect \Y $and$libresoc.v:185223$12291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:183121$12242 + cell $and $and$libresoc.v:185225$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382194,10 +385073,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:183121$12242_Y + connect \Y $and$libresoc.v:185225$12293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:183124$12245 + cell $and $and$libresoc.v:185228$12296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382205,10 +385084,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:183124$12245_Y + connect \Y $and$libresoc.v:185228$12296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:183125$12246 + cell $and $and$libresoc.v:185229$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382216,10 +385095,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:183125$12246_Y + connect \Y $and$libresoc.v:185229$12297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:183130$12251 + cell $and $and$libresoc.v:185234$12302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382227,10 +385106,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:183130$12251_Y + connect \Y $and$libresoc.v:185234$12302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:183131$12252 + cell $and $and$libresoc.v:185235$12303 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382238,10 +385117,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:183131$12252_Y + connect \Y $and$libresoc.v:185235$12303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:183133$12254 + cell $and $and$libresoc.v:185237$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382249,10 +385128,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:183133$12254_Y + connect \Y $and$libresoc.v:185237$12305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:183135$12256 + cell $and $and$libresoc.v:185239$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382260,10 +385139,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:183135$12256_Y + connect \Y $and$libresoc.v:185239$12307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:183136$12257 + cell $and $and$libresoc.v:185240$12308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382271,10 +385150,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:183136$12257_Y + connect \Y $and$libresoc.v:185240$12308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:183137$12258 + cell $and $and$libresoc.v:185241$12309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382282,10 +385161,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:183137$12258_Y + connect \Y $and$libresoc.v:185241$12309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:183143$12264 + cell $and $and$libresoc.v:185247$12315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382293,10 +385172,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:183143$12264_Y + connect \Y $and$libresoc.v:185247$12315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:183144$12265 + cell $and $and$libresoc.v:185248$12316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382304,10 +385183,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:183144$12265_Y + connect \Y $and$libresoc.v:185248$12316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:183146$12267 + cell $and $and$libresoc.v:185250$12318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382315,10 +385194,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:183146$12267_Y + connect \Y $and$libresoc.v:185250$12318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:183147$12268 + cell $and $and$libresoc.v:185251$12319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382326,10 +385205,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:183147$12268_Y + connect \Y $and$libresoc.v:185251$12319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:183148$12269 + cell $and $and$libresoc.v:185252$12320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382337,10 +385216,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:183148$12269_Y + connect \Y $and$libresoc.v:185252$12320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:183158$12279 + cell $and $and$libresoc.v:185262$12330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382348,10 +385227,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:183158$12279_Y + connect \Y $and$libresoc.v:185262$12330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:183159$12280 + cell $and $and$libresoc.v:185263$12331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382359,10 +385238,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:183159$12280_Y + connect \Y $and$libresoc.v:185263$12331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:183160$12281 + cell $and $and$libresoc.v:185264$12332 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382370,10 +385249,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:183160$12281_Y + connect \Y $and$libresoc.v:185264$12332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:183162$12283 + cell $and $and$libresoc.v:185266$12334 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382381,10 +385260,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:183162$12283_Y + connect \Y $and$libresoc.v:185266$12334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:183132$12253 + cell $eq $eq$libresoc.v:185236$12304 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382392,10 +385271,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:183132$12253_Y + connect \Y $eq$libresoc.v:185236$12304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:183134$12255 + cell $eq $eq$libresoc.v:185238$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382403,74 +385282,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:183134$12255_Y + connect \Y $eq$libresoc.v:185238$12306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:183104$12225 + cell $not $not$libresoc.v:185208$12276 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:183104$12225_Y + connect \Y $not$libresoc.v:185208$12276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:183115$12236 + cell $not $not$libresoc.v:185219$12287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:183115$12236_Y + connect \Y $not$libresoc.v:185219$12287_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:183117$12238 + cell $not $not$libresoc.v:185221$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:183117$12238_Y + connect \Y $not$libresoc.v:185221$12289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:183120$12241 + cell $not $not$libresoc.v:185224$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:183120$12241_Y + connect \Y $not$libresoc.v:185224$12292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:183123$12244 + cell $not $not$libresoc.v:185227$12295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:183123$12244_Y + connect \Y $not$libresoc.v:185227$12295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:183129$12250 + cell $not $not$libresoc.v:185233$12301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:183129$12250_Y + connect \Y $not$libresoc.v:185233$12301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:183140$12261 + cell $not $not$libresoc.v:185244$12312 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:183140$12261_Y + connect \Y $not$libresoc.v:185244$12312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:183161$12282 + cell $not $not$libresoc.v:185265$12333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:183161$12282_Y + connect \Y $not$libresoc.v:185265$12333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:183128$12249 + cell $or $or$libresoc.v:185232$12300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382478,10 +385357,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:183128$12249_Y + connect \Y $or$libresoc.v:185232$12300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:183138$12259 + cell $or $or$libresoc.v:185242$12310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382489,10 +385368,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:183138$12259_Y + connect \Y $or$libresoc.v:185242$12310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:183139$12260 + cell $or $or$libresoc.v:185243$12311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382500,10 +385379,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:183139$12260_Y + connect \Y $or$libresoc.v:185243$12311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:183141$12262 + cell $or $or$libresoc.v:185245$12313 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382511,10 +385390,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:183141$12262_Y + connect \Y $or$libresoc.v:185245$12313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:183142$12263 + cell $or $or$libresoc.v:185246$12314 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382522,10 +385401,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:183142$12263_Y + connect \Y $or$libresoc.v:185246$12314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:183145$12266 + cell $or $or$libresoc.v:185249$12317 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -382533,10 +385412,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:183145$12266_Y + connect \Y $or$libresoc.v:185249$12317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:183151$12272 + cell $or $or$libresoc.v:185255$12323 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382544,98 +385423,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:183151$12272_Y + connect \Y $or$libresoc.v:185255$12323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:183157$12278 + cell $reduce_and $reduce_and$libresoc.v:185261$12329 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:183157$12278_Y + connect \Y $reduce_and$libresoc.v:185261$12329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:183122$12243 + cell $reduce_or $reduce_or$libresoc.v:185226$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:183122$12243_Y + connect \Y $reduce_or$libresoc.v:185226$12294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:183126$12247 + cell $reduce_or $reduce_or$libresoc.v:185230$12298 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:183126$12247_Y + connect \Y $reduce_or$libresoc.v:185230$12298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:183127$12248 + cell $reduce_or $reduce_or$libresoc.v:185231$12299 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:183127$12248_Y + connect \Y $reduce_or$libresoc.v:185231$12299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:183149$12270 + cell $mux $ternary$libresoc.v:185253$12321 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:183149$12270_Y + connect \Y $ternary$libresoc.v:185253$12321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:183150$12271 + cell $mux $ternary$libresoc.v:185254$12322 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:183150$12271_Y + connect \Y $ternary$libresoc.v:185254$12322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:183152$12273 + cell $mux $ternary$libresoc.v:185256$12324 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:183152$12273_Y + connect \Y $ternary$libresoc.v:185256$12324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:183153$12274 + cell $mux $ternary$libresoc.v:185257$12325 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:183153$12274_Y + connect \Y $ternary$libresoc.v:185257$12325_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:183154$12275 + cell $mux $ternary$libresoc.v:185258$12326 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:183154$12275_Y + connect \Y $ternary$libresoc.v:185258$12326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:183155$12276 + cell $mux $ternary$libresoc.v:185259$12327 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:183155$12276_Y + connect \Y $ternary$libresoc.v:185259$12327_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:183156$12277 + cell $mux $ternary$libresoc.v:185260$12328 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:183156$12277_Y + connect \Y $ternary$libresoc.v:185260$12328_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:183249.15-183255.4" + attribute \src "libresoc.v:185353.15-185359.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382644,7 +385523,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:183256.18-183291.4" + attribute \src "libresoc.v:185360.18-185395.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382682,7 +385561,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:183292.16-183298.4" + attribute \src "libresoc.v:185396.16-185402.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382691,7 +385570,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:183299.15-183305.4" + attribute \src "libresoc.v:185403.15-185409.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382700,7 +385579,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:183306.15-183312.4" + attribute \src "libresoc.v:185410.15-185416.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382709,7 +385588,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:183313.15-183319.4" + attribute \src "libresoc.v:185417.15-185423.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382718,7 +385597,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:183320.15-183325.4" + attribute \src "libresoc.v:185424.15-185429.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382726,7 +385605,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:183326.15-183332.4" + attribute \src "libresoc.v:185430.15-185436.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -382734,667 +385613,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:182474.7-182474.20" - process $proc$libresoc.v:182474$12450 + attribute \src "libresoc.v:184574.7-184574.20" + process $proc$libresoc.v:184574$12501 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182596.7-182596.24" - process $proc$libresoc.v:182596$12451 + attribute \src "libresoc.v:184696.7-184696.24" + process $proc$libresoc.v:184696$12502 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:182606.7-182606.26" - process $proc$libresoc.v:182606$12452 + attribute \src "libresoc.v:184706.7-184706.26" + process $proc$libresoc.v:184706$12503 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:182614.7-182614.25" - process $proc$libresoc.v:182614$12453 + attribute \src "libresoc.v:184714.7-184714.25" + process $proc$libresoc.v:184714$12504 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:182656.14-182656.54" - process $proc$libresoc.v:182656$12454 + attribute \src "libresoc.v:184757.14-184757.54" + process $proc$libresoc.v:184757$12505 assign { } { } - assign $1\alu_shift_rot0_sr_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[12:0] + update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:182660.14-182660.73" - process $proc$libresoc.v:182660$12455 + attribute \src "libresoc.v:184761.14-184761.73" + process $proc$libresoc.v:184761$12506 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:182664.7-182664.48" - process $proc$libresoc.v:182664$12456 + attribute \src "libresoc.v:184765.7-184765.48" + process $proc$libresoc.v:184765$12507 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:182672.13-182672.53" - process $proc$libresoc.v:182672$12457 + attribute \src "libresoc.v:184773.13-184773.53" + process $proc$libresoc.v:184773$12508 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:182676.7-182676.44" - process $proc$libresoc.v:182676$12458 + attribute \src "libresoc.v:184777.7-184777.44" + process $proc$libresoc.v:184777$12509 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:182680.14-182680.48" - process $proc$libresoc.v:182680$12459 + attribute \src "libresoc.v:184781.14-184781.48" + process $proc$libresoc.v:184781$12510 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:182758.13-182758.52" - process $proc$libresoc.v:182758$12460 + attribute \src "libresoc.v:184860.13-184860.52" + process $proc$libresoc.v:184860$12511 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:182762.7-182762.45" - process $proc$libresoc.v:182762$12461 + attribute \src "libresoc.v:184864.7-184864.45" + process $proc$libresoc.v:184864$12512 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:182766.7-182766.44" - process $proc$libresoc.v:182766$12462 + attribute \src "libresoc.v:184868.7-184868.44" + process $proc$libresoc.v:184868$12513 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:182770.7-182770.45" - process $proc$libresoc.v:182770$12463 + attribute \src "libresoc.v:184872.7-184872.45" + process $proc$libresoc.v:184872$12514 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:182774.7-182774.42" - process $proc$libresoc.v:182774$12464 + attribute \src "libresoc.v:184876.7-184876.42" + process $proc$libresoc.v:184876$12515 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:182778.7-182778.42" - process $proc$libresoc.v:182778$12465 + attribute \src "libresoc.v:184880.7-184880.42" + process $proc$libresoc.v:184880$12516 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:182782.7-182782.48" - process $proc$libresoc.v:182782$12466 + attribute \src "libresoc.v:184884.7-184884.48" + process $proc$libresoc.v:184884$12517 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:182786.7-182786.45" - process $proc$libresoc.v:182786$12467 + attribute \src "libresoc.v:184888.7-184888.45" + process $proc$libresoc.v:184888$12518 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:182790.7-182790.42" - process $proc$libresoc.v:182790$12468 + attribute \src "libresoc.v:184892.7-184892.42" + process $proc$libresoc.v:184892$12519 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:182794.7-182794.42" - process $proc$libresoc.v:182794$12469 + attribute \src "libresoc.v:184896.7-184896.42" + process $proc$libresoc.v:184896$12520 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:182798.7-182798.45" - process $proc$libresoc.v:182798$12470 + attribute \src "libresoc.v:184900.7-184900.45" + process $proc$libresoc.v:184900$12521 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:182810.7-182810.27" - process $proc$libresoc.v:182810$12471 + attribute \src "libresoc.v:184912.7-184912.27" + process $proc$libresoc.v:184912$12522 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:182844.14-182844.47" - process $proc$libresoc.v:182844$12472 + attribute \src "libresoc.v:184946.14-184946.47" + process $proc$libresoc.v:184946$12523 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:182848.7-182848.27" - process $proc$libresoc.v:182848$12473 + attribute \src "libresoc.v:184950.7-184950.27" + process $proc$libresoc.v:184950$12524 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:182852.13-182852.33" - process $proc$libresoc.v:182852$12474 + attribute \src "libresoc.v:184954.13-184954.33" + process $proc$libresoc.v:184954$12525 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:182856.7-182856.30" - process $proc$libresoc.v:182856$12475 + attribute \src "libresoc.v:184958.7-184958.30" + process $proc$libresoc.v:184958$12526 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:182860.13-182860.35" - process $proc$libresoc.v:182860$12476 + attribute \src "libresoc.v:184962.13-184962.35" + process $proc$libresoc.v:184962$12527 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:182864.7-182864.32" - process $proc$libresoc.v:182864$12477 + attribute \src "libresoc.v:184966.7-184966.32" + process $proc$libresoc.v:184966$12528 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:182881.7-182881.25" - process $proc$libresoc.v:182881$12478 + attribute \src "libresoc.v:184983.7-184983.25" + process $proc$libresoc.v:184983$12529 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:182885.7-182885.25" - process $proc$libresoc.v:182885$12479 + attribute \src "libresoc.v:184987.7-184987.25" + process $proc$libresoc.v:184987$12530 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:183015.13-183015.30" - process $proc$libresoc.v:183015$12480 + attribute \src "libresoc.v:185119.13-185119.30" + process $proc$libresoc.v:185119$12531 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:183023.13-183023.31" - process $proc$libresoc.v:183023$12481 + attribute \src "libresoc.v:185127.13-185127.31" + process $proc$libresoc.v:185127$12532 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:183027.13-183027.31" - process $proc$libresoc.v:183027$12482 + attribute \src "libresoc.v:185131.13-185131.31" + process $proc$libresoc.v:185131$12533 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:183039.7-183039.26" - process $proc$libresoc.v:183039$12483 + attribute \src "libresoc.v:185143.7-185143.26" + process $proc$libresoc.v:185143$12534 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:183043.7-183043.26" - process $proc$libresoc.v:183043$12484 + attribute \src "libresoc.v:185147.7-185147.26" + process $proc$libresoc.v:185147$12535 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:183047.7-183047.25" - process $proc$libresoc.v:183047$12485 + attribute \src "libresoc.v:185151.7-185151.25" + process $proc$libresoc.v:185151$12536 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:183051.7-183051.25" - process $proc$libresoc.v:183051$12486 + attribute \src "libresoc.v:185155.7-185155.25" + process $proc$libresoc.v:185155$12537 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:183069.13-183069.32" - process $proc$libresoc.v:183069$12487 + attribute \src "libresoc.v:185173.13-185173.32" + process $proc$libresoc.v:185173$12538 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:183073.13-183073.32" - process $proc$libresoc.v:183073$12488 + attribute \src "libresoc.v:185177.13-185177.32" + process $proc$libresoc.v:185177$12539 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:183079.14-183079.43" - process $proc$libresoc.v:183079$12489 + attribute \src "libresoc.v:185183.14-185183.43" + process $proc$libresoc.v:185183$12540 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:183083.14-183083.43" - process $proc$libresoc.v:183083$12490 + attribute \src "libresoc.v:185187.14-185187.43" + process $proc$libresoc.v:185187$12541 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:183087.14-183087.43" - process $proc$libresoc.v:183087$12491 + attribute \src "libresoc.v:185191.14-185191.43" + process $proc$libresoc.v:185191$12542 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:183091.7-183091.20" - process $proc$libresoc.v:183091$12492 + attribute \src "libresoc.v:185195.7-185195.20" + process $proc$libresoc.v:185195$12543 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:183095.13-183095.26" - process $proc$libresoc.v:183095$12493 + attribute \src "libresoc.v:185199.13-185199.26" + process $proc$libresoc.v:185199$12544 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:183163.3-183164.39" - process $proc$libresoc.v:183163$12284 + attribute \src "libresoc.v:185267.3-185268.39" + process $proc$libresoc.v:185267$12335 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:183165.3-183166.43" - process $proc$libresoc.v:183165$12285 + attribute \src "libresoc.v:185269.3-185270.43" + process $proc$libresoc.v:185269$12336 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:183167.3-183168.29" - process $proc$libresoc.v:183167$12286 + attribute \src "libresoc.v:185271.3-185272.29" + process $proc$libresoc.v:185271$12337 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:183169.3-183170.29" - process $proc$libresoc.v:183169$12287 + attribute \src "libresoc.v:185273.3-185274.29" + process $proc$libresoc.v:185273$12338 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:183171.3-183172.29" - process $proc$libresoc.v:183171$12288 + attribute \src "libresoc.v:185275.3-185276.29" + process $proc$libresoc.v:185275$12339 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:183173.3-183174.29" - process $proc$libresoc.v:183173$12289 + attribute \src "libresoc.v:185277.3-185278.29" + process $proc$libresoc.v:185277$12340 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:183175.3-183176.29" - process $proc$libresoc.v:183175$12290 + attribute \src "libresoc.v:185279.3-185280.29" + process $proc$libresoc.v:185279$12341 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:183177.3-183178.47" - process $proc$libresoc.v:183177$12291 + attribute \src "libresoc.v:185281.3-185282.47" + process $proc$libresoc.v:185281$12342 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:183179.3-183180.53" - process $proc$libresoc.v:183179$12292 + attribute \src "libresoc.v:185283.3-185284.53" + process $proc$libresoc.v:185283$12343 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:183181.3-183182.43" - process $proc$libresoc.v:183181$12293 + attribute \src "libresoc.v:185285.3-185286.43" + process $proc$libresoc.v:185285$12344 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:183183.3-183184.49" - process $proc$libresoc.v:183183$12294 + attribute \src "libresoc.v:185287.3-185288.49" + process $proc$libresoc.v:185287$12345 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:183185.3-183186.37" - process $proc$libresoc.v:183185$12295 + attribute \src "libresoc.v:185289.3-185290.37" + process $proc$libresoc.v:185289$12346 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:183187.3-183188.43" - process $proc$libresoc.v:183187$12296 + attribute \src "libresoc.v:185291.3-185292.43" + process $proc$libresoc.v:185291$12347 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:183189.3-183190.79" - process $proc$libresoc.v:183189$12297 + attribute \src "libresoc.v:185293.3-185294.79" + process $proc$libresoc.v:185293$12348 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:183191.3-183192.75" - process $proc$libresoc.v:183191$12298 + attribute \src "libresoc.v:185295.3-185296.75" + process $proc$libresoc.v:185295$12349 assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit[12:0] \alu_shift_rot0_sr_op__fn_unit$next + assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[12:0] + update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:183193.3-183194.89" - process $proc$libresoc.v:183193$12299 + attribute \src "libresoc.v:185297.3-185298.89" + process $proc$libresoc.v:185297$12350 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:183195.3-183196.85" - process $proc$libresoc.v:183195$12300 + attribute \src "libresoc.v:185299.3-185300.85" + process $proc$libresoc.v:185299$12351 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:183197.3-183198.73" - process $proc$libresoc.v:183197$12301 + attribute \src "libresoc.v:185301.3-185302.73" + process $proc$libresoc.v:185301$12352 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:183199.3-183200.73" - process $proc$libresoc.v:183199$12302 + attribute \src "libresoc.v:185303.3-185304.73" + process $proc$libresoc.v:185303$12353 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:183201.3-183202.73" - process $proc$libresoc.v:183201$12303 + attribute \src "libresoc.v:185305.3-185306.73" + process $proc$libresoc.v:185305$12354 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:183203.3-183204.73" - process $proc$libresoc.v:183203$12304 + attribute \src "libresoc.v:185307.3-185308.73" + process $proc$libresoc.v:185307$12355 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:183205.3-183206.79" - process $proc$libresoc.v:183205$12305 + attribute \src "libresoc.v:185309.3-185310.79" + process $proc$libresoc.v:185309$12356 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:183207.3-183208.79" - process $proc$libresoc.v:183207$12306 + attribute \src "libresoc.v:185311.3-185312.79" + process $proc$libresoc.v:185311$12357 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:183209.3-183210.83" - process $proc$libresoc.v:183209$12307 + attribute \src "libresoc.v:185313.3-185314.83" + process $proc$libresoc.v:185313$12358 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:183211.3-183212.85" - process $proc$libresoc.v:183211$12308 + attribute \src "libresoc.v:185315.3-185316.85" + process $proc$libresoc.v:185315$12359 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:183213.3-183214.77" - process $proc$libresoc.v:183213$12309 + attribute \src "libresoc.v:185317.3-185318.77" + process $proc$libresoc.v:185317$12360 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:183215.3-183216.79" - process $proc$libresoc.v:183215$12310 + attribute \src "libresoc.v:185319.3-185320.79" + process $proc$libresoc.v:185319$12361 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:183217.3-183218.77" - process $proc$libresoc.v:183217$12311 + attribute \src "libresoc.v:185321.3-185322.77" + process $proc$libresoc.v:185321$12362 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:183219.3-183220.79" - process $proc$libresoc.v:183219$12312 + attribute \src "libresoc.v:185323.3-185324.79" + process $proc$libresoc.v:185323$12363 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:183221.3-183222.69" - process $proc$libresoc.v:183221$12313 + attribute \src "libresoc.v:185325.3-185326.69" + process $proc$libresoc.v:185325$12364 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:183223.3-183224.39" - process $proc$libresoc.v:183223$12314 + attribute \src "libresoc.v:185327.3-185328.39" + process $proc$libresoc.v:185327$12365 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:183225.3-183226.39" - process $proc$libresoc.v:183225$12315 + attribute \src "libresoc.v:185329.3-185330.39" + process $proc$libresoc.v:185329$12366 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:183227.3-183228.39" - process $proc$libresoc.v:183227$12316 + attribute \src "libresoc.v:185331.3-185332.39" + process $proc$libresoc.v:185331$12367 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:183229.3-183230.39" - process $proc$libresoc.v:183229$12317 + attribute \src "libresoc.v:185333.3-185334.39" + process $proc$libresoc.v:185333$12368 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:183231.3-183232.39" - process $proc$libresoc.v:183231$12318 + attribute \src "libresoc.v:185335.3-185336.39" + process $proc$libresoc.v:185335$12369 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:183233.3-183234.39" - process $proc$libresoc.v:183233$12319 + attribute \src "libresoc.v:185337.3-185338.39" + process $proc$libresoc.v:185337$12370 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:183235.3-183236.39" - process $proc$libresoc.v:183235$12320 + attribute \src "libresoc.v:185339.3-185340.39" + process $proc$libresoc.v:185339$12371 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:183237.3-183238.39" - process $proc$libresoc.v:183237$12321 + attribute \src "libresoc.v:185341.3-185342.39" + process $proc$libresoc.v:185341$12372 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:183239.3-183240.41" - process $proc$libresoc.v:183239$12322 + attribute \src "libresoc.v:185343.3-185344.41" + process $proc$libresoc.v:185343$12373 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:183241.3-183242.41" - process $proc$libresoc.v:183241$12323 + attribute \src "libresoc.v:185345.3-185346.41" + process $proc$libresoc.v:185345$12374 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:183243.3-183244.37" - process $proc$libresoc.v:183243$12324 + attribute \src "libresoc.v:185347.3-185348.37" + process $proc$libresoc.v:185347$12375 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:183245.3-183246.46" - process $proc$libresoc.v:183245$12325 + attribute \src "libresoc.v:185349.3-185350.46" + process $proc$libresoc.v:185349$12376 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:183247.3-183248.25" - process $proc$libresoc.v:183247$12326 + attribute \src "libresoc.v:185351.3-185352.25" + process $proc$libresoc.v:185351$12377 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:183333.3-183342.6" - process $proc$libresoc.v:183333$12327 + attribute \src "libresoc.v:185437.3-185446.6" + process $proc$libresoc.v:185437$12378 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:183334.5-183334.29" + attribute \src "libresoc.v:185438.5-185438.29" switch \initial - attribute \src "libresoc.v:183334.9-183334.17" + attribute \src "libresoc.v:185438.9-185438.17" case 1'1 case end @@ -383410,14 +386289,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:183343.3-183351.6" - process $proc$libresoc.v:183343$12328 + attribute \src "libresoc.v:185447.3-185455.6" + process $proc$libresoc.v:185447$12379 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12329 $1\rok_l_s_rdok$next[0:0]$12330 - attribute \src "libresoc.v:183344.5-183344.29" + assign $0\rok_l_s_rdok$next[0:0]$12380 $1\rok_l_s_rdok$next[0:0]$12381 + attribute \src "libresoc.v:185448.5-185448.29" switch \initial - attribute \src "libresoc.v:183344.9-183344.17" + attribute \src "libresoc.v:185448.9-185448.17" case 1'1 case end @@ -383426,21 +386305,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12330 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12381 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12330 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12381 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12329 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12380 end - attribute \src "libresoc.v:183352.3-183360.6" - process $proc$libresoc.v:183352$12331 + attribute \src "libresoc.v:185456.3-185464.6" + process $proc$libresoc.v:185456$12382 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12332 $1\rok_l_r_rdok$next[0:0]$12333 - attribute \src "libresoc.v:183353.5-183353.29" + assign $0\rok_l_r_rdok$next[0:0]$12383 $1\rok_l_r_rdok$next[0:0]$12384 + attribute \src "libresoc.v:185457.5-185457.29" switch \initial - attribute \src "libresoc.v:183353.9-183353.17" + attribute \src "libresoc.v:185457.9-185457.17" case 1'1 case end @@ -383449,21 +386328,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12333 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12384 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12333 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12384 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12332 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12383 end - attribute \src "libresoc.v:183361.3-183369.6" - process $proc$libresoc.v:183361$12334 + attribute \src "libresoc.v:185465.3-185473.6" + process $proc$libresoc.v:185465$12385 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12335 $1\rst_l_s_rst$next[0:0]$12336 - attribute \src "libresoc.v:183362.5-183362.29" + assign $0\rst_l_s_rst$next[0:0]$12386 $1\rst_l_s_rst$next[0:0]$12387 + attribute \src "libresoc.v:185466.5-185466.29" switch \initial - attribute \src "libresoc.v:183362.9-183362.17" + attribute \src "libresoc.v:185466.9-185466.17" case 1'1 case end @@ -383472,21 +386351,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12336 1'0 + assign $1\rst_l_s_rst$next[0:0]$12387 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12336 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12387 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12335 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12386 end - attribute \src "libresoc.v:183370.3-183378.6" - process $proc$libresoc.v:183370$12337 + attribute \src "libresoc.v:185474.3-185482.6" + process $proc$libresoc.v:185474$12388 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12338 $1\rst_l_r_rst$next[0:0]$12339 - attribute \src "libresoc.v:183371.5-183371.29" + assign $0\rst_l_r_rst$next[0:0]$12389 $1\rst_l_r_rst$next[0:0]$12390 + attribute \src "libresoc.v:185475.5-185475.29" switch \initial - attribute \src "libresoc.v:183371.9-183371.17" + attribute \src "libresoc.v:185475.9-185475.17" case 1'1 case end @@ -383495,21 +386374,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12339 1'1 + assign $1\rst_l_r_rst$next[0:0]$12390 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12339 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12390 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12338 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12389 end - attribute \src "libresoc.v:183379.3-183387.6" - process $proc$libresoc.v:183379$12340 + attribute \src "libresoc.v:185483.3-185491.6" + process $proc$libresoc.v:185483$12391 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12341 $1\opc_l_s_opc$next[0:0]$12342 - attribute \src "libresoc.v:183380.5-183380.29" + assign $0\opc_l_s_opc$next[0:0]$12392 $1\opc_l_s_opc$next[0:0]$12393 + attribute \src "libresoc.v:185484.5-185484.29" switch \initial - attribute \src "libresoc.v:183380.9-183380.17" + attribute \src "libresoc.v:185484.9-185484.17" case 1'1 case end @@ -383518,21 +386397,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12342 1'0 + assign $1\opc_l_s_opc$next[0:0]$12393 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12342 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12393 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12341 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12392 end - attribute \src "libresoc.v:183388.3-183396.6" - process $proc$libresoc.v:183388$12343 + attribute \src "libresoc.v:185492.3-185500.6" + process $proc$libresoc.v:185492$12394 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12344 $1\opc_l_r_opc$next[0:0]$12345 - attribute \src "libresoc.v:183389.5-183389.29" + assign $0\opc_l_r_opc$next[0:0]$12395 $1\opc_l_r_opc$next[0:0]$12396 + attribute \src "libresoc.v:185493.5-185493.29" switch \initial - attribute \src "libresoc.v:183389.9-183389.17" + attribute \src "libresoc.v:185493.9-185493.17" case 1'1 case end @@ -383541,21 +386420,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12345 1'1 + assign $1\opc_l_r_opc$next[0:0]$12396 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12345 \req_done + assign $1\opc_l_r_opc$next[0:0]$12396 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12344 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12395 end - attribute \src "libresoc.v:183397.3-183405.6" - process $proc$libresoc.v:183397$12346 + attribute \src "libresoc.v:185501.3-185509.6" + process $proc$libresoc.v:185501$12397 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12347 $1\src_l_s_src$next[4:0]$12348 - attribute \src "libresoc.v:183398.5-183398.29" + assign $0\src_l_s_src$next[4:0]$12398 $1\src_l_s_src$next[4:0]$12399 + attribute \src "libresoc.v:185502.5-185502.29" switch \initial - attribute \src "libresoc.v:183398.9-183398.17" + attribute \src "libresoc.v:185502.9-185502.17" case 1'1 case end @@ -383564,21 +386443,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$12348 5'00000 + assign $1\src_l_s_src$next[4:0]$12399 5'00000 case - assign $1\src_l_s_src$next[4:0]$12348 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12399 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12347 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12398 end - attribute \src "libresoc.v:183406.3-183414.6" - process $proc$libresoc.v:183406$12349 + attribute \src "libresoc.v:185510.3-185518.6" + process $proc$libresoc.v:185510$12400 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12350 $1\src_l_r_src$next[4:0]$12351 - attribute \src "libresoc.v:183407.5-183407.29" + assign $0\src_l_r_src$next[4:0]$12401 $1\src_l_r_src$next[4:0]$12402 + attribute \src "libresoc.v:185511.5-185511.29" switch \initial - attribute \src "libresoc.v:183407.9-183407.17" + attribute \src "libresoc.v:185511.9-185511.17" case 1'1 case end @@ -383587,21 +386466,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$12351 5'11111 + assign $1\src_l_r_src$next[4:0]$12402 5'11111 case - assign $1\src_l_r_src$next[4:0]$12351 \reset_r + assign $1\src_l_r_src$next[4:0]$12402 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12350 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12401 end - attribute \src "libresoc.v:183415.3-183423.6" - process $proc$libresoc.v:183415$12352 + attribute \src "libresoc.v:185519.3-185527.6" + process $proc$libresoc.v:185519$12403 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12353 $1\req_l_s_req$next[2:0]$12354 - attribute \src "libresoc.v:183416.5-183416.29" + assign $0\req_l_s_req$next[2:0]$12404 $1\req_l_s_req$next[2:0]$12405 + attribute \src "libresoc.v:185520.5-185520.29" switch \initial - attribute \src "libresoc.v:183416.9-183416.17" + attribute \src "libresoc.v:185520.9-185520.17" case 1'1 case end @@ -383610,21 +386489,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$12354 3'000 + assign $1\req_l_s_req$next[2:0]$12405 3'000 case - assign $1\req_l_s_req$next[2:0]$12354 \$66 + assign $1\req_l_s_req$next[2:0]$12405 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12353 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12404 end - attribute \src "libresoc.v:183424.3-183432.6" - process $proc$libresoc.v:183424$12355 + attribute \src "libresoc.v:185528.3-185536.6" + process $proc$libresoc.v:185528$12406 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12356 $1\req_l_r_req$next[2:0]$12357 - attribute \src "libresoc.v:183425.5-183425.29" + assign $0\req_l_r_req$next[2:0]$12407 $1\req_l_r_req$next[2:0]$12408 + attribute \src "libresoc.v:185529.5-185529.29" switch \initial - attribute \src "libresoc.v:183425.9-183425.17" + attribute \src "libresoc.v:185529.9-185529.17" case 1'1 case end @@ -383633,15 +386512,15 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$12357 3'111 + assign $1\req_l_r_req$next[2:0]$12408 3'111 case - assign $1\req_l_r_req$next[2:0]$12357 \$68 + assign $1\req_l_r_req$next[2:0]$12408 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12356 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12407 end - attribute \src "libresoc.v:183433.3-183470.6" - process $proc$libresoc.v:183433$12358 + attribute \src "libresoc.v:185537.3-185574.6" + process $proc$libresoc.v:185537$12409 assign { } { } assign { } { } assign { } { } @@ -383676,32 +386555,32 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12359 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12376 + assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12362 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12379 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12363 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12380 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12364 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12381 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12365 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12382 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12366 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12383 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12367 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12384 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12368 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12385 + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12371 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12388 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12372 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12389 + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12375 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12392 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12360 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12393 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12361 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12394 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12369 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12395 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12370 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12396 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12373 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12397 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12374 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12398 - attribute \src "libresoc.v:183434.5-183434.29" + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 + attribute \src "libresoc.v:185538.5-185538.29" switch \initial - attribute \src "libresoc.v:183434.9-183434.17" + attribute \src "libresoc.v:185538.9-185538.17" case 1'1 case end @@ -383726,25 +386605,25 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12381 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12385 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12384 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12389 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12380 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12388 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12379 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12383 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12392 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12387 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12386 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12390 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12391 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12378 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12377 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12376 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12382 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12376 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12377 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12378 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12379 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12380 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12381 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12382 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12383 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12384 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12385 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12386 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12387 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12388 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12389 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12390 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12391 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12392 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -383756,53 +386635,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12393 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12394 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12398 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12397 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12395 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12396 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12393 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12377 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12394 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12378 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12395 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12386 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12396 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12387 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12397 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12390 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12398 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12391 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12359 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12360 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12361 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12362 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12363 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12364 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12365 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12366 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12367 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12368 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12369 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12370 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12371 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12372 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12373 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12374 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12375 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 end - attribute \src "libresoc.v:183471.3-183492.6" - process $proc$libresoc.v:183471$12399 + attribute \src "libresoc.v:185575.3-185596.6" + process $proc$libresoc.v:185575$12450 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12400 $2\data_r0__o$next[63:0]$12404 + assign $0\data_r0__o$next[63:0]$12451 $2\data_r0__o$next[63:0]$12455 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12401 $3\data_r0__o_ok$next[0:0]$12406 - attribute \src "libresoc.v:183472.5-183472.29" + assign $0\data_r0__o_ok$next[0:0]$12452 $3\data_r0__o_ok$next[0:0]$12457 + attribute \src "libresoc.v:185576.5-185576.29" switch \initial - attribute \src "libresoc.v:183472.9-183472.17" + attribute \src "libresoc.v:185576.9-185576.17" case 1'1 case end @@ -383812,10 +386691,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12403 $1\data_r0__o$next[63:0]$12402 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12454 $1\data_r0__o$next[63:0]$12453 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12402 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12403 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12453 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12454 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -383823,38 +386702,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12405 $2\data_r0__o$next[63:0]$12404 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12456 $2\data_r0__o$next[63:0]$12455 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12404 $1\data_r0__o$next[63:0]$12402 - assign $2\data_r0__o_ok$next[0:0]$12405 $1\data_r0__o_ok$next[0:0]$12403 + assign $2\data_r0__o$next[63:0]$12455 $1\data_r0__o$next[63:0]$12453 + assign $2\data_r0__o_ok$next[0:0]$12456 $1\data_r0__o_ok$next[0:0]$12454 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12406 1'0 + assign $3\data_r0__o_ok$next[0:0]$12457 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12406 $2\data_r0__o_ok$next[0:0]$12405 + assign $3\data_r0__o_ok$next[0:0]$12457 $2\data_r0__o_ok$next[0:0]$12456 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12400 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12401 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12451 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12452 end - attribute \src "libresoc.v:183493.3-183514.6" - process $proc$libresoc.v:183493$12407 + attribute \src "libresoc.v:185597.3-185618.6" + process $proc$libresoc.v:185597$12458 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12408 $2\data_r1__cr_a$next[3:0]$12412 + assign $0\data_r1__cr_a$next[3:0]$12459 $2\data_r1__cr_a$next[3:0]$12463 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12409 $3\data_r1__cr_a_ok$next[0:0]$12414 - attribute \src "libresoc.v:183494.5-183494.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12460 $3\data_r1__cr_a_ok$next[0:0]$12465 + attribute \src "libresoc.v:185598.5-185598.29" switch \initial - attribute \src "libresoc.v:183494.9-183494.17" + attribute \src "libresoc.v:185598.9-185598.17" case 1'1 case end @@ -383864,10 +386743,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12411 $1\data_r1__cr_a$next[3:0]$12410 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12462 $1\data_r1__cr_a$next[3:0]$12461 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12410 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12411 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12461 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12462 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -383875,38 +386754,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12413 $2\data_r1__cr_a$next[3:0]$12412 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12464 $2\data_r1__cr_a$next[3:0]$12463 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12412 $1\data_r1__cr_a$next[3:0]$12410 - assign $2\data_r1__cr_a_ok$next[0:0]$12413 $1\data_r1__cr_a_ok$next[0:0]$12411 + assign $2\data_r1__cr_a$next[3:0]$12463 $1\data_r1__cr_a$next[3:0]$12461 + assign $2\data_r1__cr_a_ok$next[0:0]$12464 $1\data_r1__cr_a_ok$next[0:0]$12462 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12414 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12465 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12414 $2\data_r1__cr_a_ok$next[0:0]$12413 + assign $3\data_r1__cr_a_ok$next[0:0]$12465 $2\data_r1__cr_a_ok$next[0:0]$12464 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12408 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12409 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12459 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12460 end - attribute \src "libresoc.v:183515.3-183536.6" - process $proc$libresoc.v:183515$12415 + attribute \src "libresoc.v:185619.3-185640.6" + process $proc$libresoc.v:185619$12466 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12416 $2\data_r2__xer_ca$next[1:0]$12420 + assign $0\data_r2__xer_ca$next[1:0]$12467 $2\data_r2__xer_ca$next[1:0]$12471 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12417 $3\data_r2__xer_ca_ok$next[0:0]$12422 - attribute \src "libresoc.v:183516.5-183516.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12468 $3\data_r2__xer_ca_ok$next[0:0]$12473 + attribute \src "libresoc.v:185620.5-185620.29" switch \initial - attribute \src "libresoc.v:183516.9-183516.17" + attribute \src "libresoc.v:185620.9-185620.17" case 1'1 case end @@ -383916,10 +386795,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12419 $1\data_r2__xer_ca$next[1:0]$12418 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12470 $1\data_r2__xer_ca$next[1:0]$12469 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12418 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12419 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12469 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12470 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -383927,32 +386806,32 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12421 $2\data_r2__xer_ca$next[1:0]$12420 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12472 $2\data_r2__xer_ca$next[1:0]$12471 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12420 $1\data_r2__xer_ca$next[1:0]$12418 - assign $2\data_r2__xer_ca_ok$next[0:0]$12421 $1\data_r2__xer_ca_ok$next[0:0]$12419 + assign $2\data_r2__xer_ca$next[1:0]$12471 $1\data_r2__xer_ca$next[1:0]$12469 + assign $2\data_r2__xer_ca_ok$next[0:0]$12472 $1\data_r2__xer_ca_ok$next[0:0]$12470 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12422 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12473 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12422 $2\data_r2__xer_ca_ok$next[0:0]$12421 + assign $3\data_r2__xer_ca_ok$next[0:0]$12473 $2\data_r2__xer_ca_ok$next[0:0]$12472 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12416 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12417 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12467 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12468 end - attribute \src "libresoc.v:183537.3-183546.6" - process $proc$libresoc.v:183537$12423 + attribute \src "libresoc.v:185641.3-185650.6" + process $proc$libresoc.v:185641$12474 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12424 $1\src_r0$next[63:0]$12425 - attribute \src "libresoc.v:183538.5-183538.29" + assign $0\src_r0$next[63:0]$12475 $1\src_r0$next[63:0]$12476 + attribute \src "libresoc.v:185642.5-185642.29" switch \initial - attribute \src "libresoc.v:183538.9-183538.17" + attribute \src "libresoc.v:185642.9-185642.17" case 1'1 case end @@ -383961,21 +386840,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12425 \src1_i + assign $1\src_r0$next[63:0]$12476 \src1_i case - assign $1\src_r0$next[63:0]$12425 \src_r0 + assign $1\src_r0$next[63:0]$12476 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12424 + update \src_r0$next $0\src_r0$next[63:0]$12475 end - attribute \src "libresoc.v:183547.3-183556.6" - process $proc$libresoc.v:183547$12426 + attribute \src "libresoc.v:185651.3-185660.6" + process $proc$libresoc.v:185651$12477 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12427 $1\src_r1$next[63:0]$12428 - attribute \src "libresoc.v:183548.5-183548.29" + assign $0\src_r1$next[63:0]$12478 $1\src_r1$next[63:0]$12479 + attribute \src "libresoc.v:185652.5-185652.29" switch \initial - attribute \src "libresoc.v:183548.9-183548.17" + attribute \src "libresoc.v:185652.9-185652.17" case 1'1 case end @@ -383984,21 +386863,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12428 \src_or_imm + assign $1\src_r1$next[63:0]$12479 \src_or_imm case - assign $1\src_r1$next[63:0]$12428 \src_r1 + assign $1\src_r1$next[63:0]$12479 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12427 + update \src_r1$next $0\src_r1$next[63:0]$12478 end - attribute \src "libresoc.v:183557.3-183566.6" - process $proc$libresoc.v:183557$12429 + attribute \src "libresoc.v:185661.3-185670.6" + process $proc$libresoc.v:185661$12480 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12430 $1\src_r2$next[63:0]$12431 - attribute \src "libresoc.v:183558.5-183558.29" + assign $0\src_r2$next[63:0]$12481 $1\src_r2$next[63:0]$12482 + attribute \src "libresoc.v:185662.5-185662.29" switch \initial - attribute \src "libresoc.v:183558.9-183558.17" + attribute \src "libresoc.v:185662.9-185662.17" case 1'1 case end @@ -384007,21 +386886,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12431 \src3_i + assign $1\src_r2$next[63:0]$12482 \src3_i case - assign $1\src_r2$next[63:0]$12431 \src_r2 + assign $1\src_r2$next[63:0]$12482 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12430 + update \src_r2$next $0\src_r2$next[63:0]$12481 end - attribute \src "libresoc.v:183567.3-183576.6" - process $proc$libresoc.v:183567$12432 + attribute \src "libresoc.v:185671.3-185680.6" + process $proc$libresoc.v:185671$12483 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12433 $1\src_r3$next[0:0]$12434 - attribute \src "libresoc.v:183568.5-183568.29" + assign $0\src_r3$next[0:0]$12484 $1\src_r3$next[0:0]$12485 + attribute \src "libresoc.v:185672.5-185672.29" switch \initial - attribute \src "libresoc.v:183568.9-183568.17" + attribute \src "libresoc.v:185672.9-185672.17" case 1'1 case end @@ -384030,21 +386909,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12434 \src4_i + assign $1\src_r3$next[0:0]$12485 \src4_i case - assign $1\src_r3$next[0:0]$12434 \src_r3 + assign $1\src_r3$next[0:0]$12485 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12433 + update \src_r3$next $0\src_r3$next[0:0]$12484 end - attribute \src "libresoc.v:183577.3-183586.6" - process $proc$libresoc.v:183577$12435 + attribute \src "libresoc.v:185681.3-185690.6" + process $proc$libresoc.v:185681$12486 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12436 $1\src_r4$next[1:0]$12437 - attribute \src "libresoc.v:183578.5-183578.29" + assign $0\src_r4$next[1:0]$12487 $1\src_r4$next[1:0]$12488 + attribute \src "libresoc.v:185682.5-185682.29" switch \initial - attribute \src "libresoc.v:183578.9-183578.17" + attribute \src "libresoc.v:185682.9-185682.17" case 1'1 case end @@ -384053,21 +386932,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12437 \src5_i + assign $1\src_r4$next[1:0]$12488 \src5_i case - assign $1\src_r4$next[1:0]$12437 \src_r4 + assign $1\src_r4$next[1:0]$12488 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12436 + update \src_r4$next $0\src_r4$next[1:0]$12487 end - attribute \src "libresoc.v:183587.3-183595.6" - process $proc$libresoc.v:183587$12438 + attribute \src "libresoc.v:185691.3-185699.6" + process $proc$libresoc.v:185691$12489 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12439 $1\alui_l_r_alui$next[0:0]$12440 - attribute \src "libresoc.v:183588.5-183588.29" + assign $0\alui_l_r_alui$next[0:0]$12490 $1\alui_l_r_alui$next[0:0]$12491 + attribute \src "libresoc.v:185692.5-185692.29" switch \initial - attribute \src "libresoc.v:183588.9-183588.17" + attribute \src "libresoc.v:185692.9-185692.17" case 1'1 case end @@ -384076,21 +386955,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12440 1'1 + assign $1\alui_l_r_alui$next[0:0]$12491 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12440 \$90 + assign $1\alui_l_r_alui$next[0:0]$12491 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12439 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12490 end - attribute \src "libresoc.v:183596.3-183604.6" - process $proc$libresoc.v:183596$12441 + attribute \src "libresoc.v:185700.3-185708.6" + process $proc$libresoc.v:185700$12492 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12442 $1\alu_l_r_alu$next[0:0]$12443 - attribute \src "libresoc.v:183597.5-183597.29" + assign $0\alu_l_r_alu$next[0:0]$12493 $1\alu_l_r_alu$next[0:0]$12494 + attribute \src "libresoc.v:185701.5-185701.29" switch \initial - attribute \src "libresoc.v:183597.9-183597.17" + attribute \src "libresoc.v:185701.9-185701.17" case 1'1 case end @@ -384099,21 +386978,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12443 1'1 + assign $1\alu_l_r_alu$next[0:0]$12494 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12443 \$92 + assign $1\alu_l_r_alu$next[0:0]$12494 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12442 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12493 end - attribute \src "libresoc.v:183605.3-183614.6" - process $proc$libresoc.v:183605$12444 + attribute \src "libresoc.v:185709.3-185718.6" + process $proc$libresoc.v:185709$12495 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:183606.5-183606.29" + attribute \src "libresoc.v:185710.5-185710.29" switch \initial - attribute \src "libresoc.v:183606.9-183606.17" + attribute \src "libresoc.v:185710.9-185710.17" case 1'1 case end @@ -384129,14 +387008,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:183615.3-183624.6" - process $proc$libresoc.v:183615$12445 + attribute \src "libresoc.v:185719.3-185728.6" + process $proc$libresoc.v:185719$12496 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:183616.5-183616.29" + attribute \src "libresoc.v:185720.5-185720.29" switch \initial - attribute \src "libresoc.v:183616.9-183616.17" + attribute \src "libresoc.v:185720.9-185720.17" case 1'1 case end @@ -384152,14 +387031,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:183625.3-183634.6" - process $proc$libresoc.v:183625$12446 + attribute \src "libresoc.v:185729.3-185738.6" + process $proc$libresoc.v:185729$12497 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:183626.5-183626.29" + attribute \src "libresoc.v:185730.5-185730.29" switch \initial - attribute \src "libresoc.v:183626.9-183626.17" + attribute \src "libresoc.v:185730.9-185730.17" case 1'1 case end @@ -384175,14 +387054,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:183635.3-183643.6" - process $proc$libresoc.v:183635$12447 + attribute \src "libresoc.v:185739.3-185747.6" + process $proc$libresoc.v:185739$12498 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12448 $1\prev_wr_go$next[2:0]$12449 - attribute \src "libresoc.v:183636.5-183636.29" + assign $0\prev_wr_go$next[2:0]$12499 $1\prev_wr_go$next[2:0]$12500 + attribute \src "libresoc.v:185740.5-185740.29" switch \initial - attribute \src "libresoc.v:183636.9-183636.17" + attribute \src "libresoc.v:185740.9-185740.17" case 1'1 case end @@ -384191,72 +387070,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12449 3'000 - case - assign $1\prev_wr_go$next[2:0]$12449 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12448 - end - connect \$100 $not$libresoc.v:183104$12225_Y - connect \$102 $and$libresoc.v:183105$12226_Y - connect \$104 $and$libresoc.v:183106$12227_Y - connect \$106 $and$libresoc.v:183107$12228_Y - connect \$108 $and$libresoc.v:183108$12229_Y - connect \$10 $and$libresoc.v:183109$12230_Y - connect \$110 $and$libresoc.v:183110$12231_Y - connect \$112 $and$libresoc.v:183111$12232_Y - connect \$114 $and$libresoc.v:183112$12233_Y - connect \$116 $and$libresoc.v:183113$12234_Y - connect \$118 $and$libresoc.v:183114$12235_Y - connect \$12 $not$libresoc.v:183115$12236_Y - connect \$14 $and$libresoc.v:183116$12237_Y - connect \$16 $not$libresoc.v:183117$12238_Y - connect \$18 $and$libresoc.v:183118$12239_Y - connect \$20 $and$libresoc.v:183119$12240_Y - connect \$24 $not$libresoc.v:183120$12241_Y - connect \$26 $and$libresoc.v:183121$12242_Y - connect \$23 $reduce_or$libresoc.v:183122$12243_Y - connect \$22 $not$libresoc.v:183123$12244_Y - connect \$2 $and$libresoc.v:183124$12245_Y - connect \$30 $and$libresoc.v:183125$12246_Y - connect \$32 $reduce_or$libresoc.v:183126$12247_Y - connect \$34 $reduce_or$libresoc.v:183127$12248_Y - connect \$36 $or$libresoc.v:183128$12249_Y - connect \$38 $not$libresoc.v:183129$12250_Y - connect \$40 $and$libresoc.v:183130$12251_Y - connect \$42 $and$libresoc.v:183131$12252_Y - connect \$44 $eq$libresoc.v:183132$12253_Y - connect \$46 $and$libresoc.v:183133$12254_Y - connect \$48 $eq$libresoc.v:183134$12255_Y - connect \$50 $and$libresoc.v:183135$12256_Y - connect \$52 $and$libresoc.v:183136$12257_Y - connect \$54 $and$libresoc.v:183137$12258_Y - connect \$56 $or$libresoc.v:183138$12259_Y - connect \$58 $or$libresoc.v:183139$12260_Y - connect \$5 $not$libresoc.v:183140$12261_Y - connect \$60 $or$libresoc.v:183141$12262_Y - connect \$62 $or$libresoc.v:183142$12263_Y - connect \$64 $and$libresoc.v:183143$12264_Y - connect \$66 $and$libresoc.v:183144$12265_Y - connect \$68 $or$libresoc.v:183145$12266_Y - connect \$70 $and$libresoc.v:183146$12267_Y - connect \$72 $and$libresoc.v:183147$12268_Y - connect \$74 $and$libresoc.v:183148$12269_Y - connect \$76 $ternary$libresoc.v:183149$12270_Y - connect \$78 $ternary$libresoc.v:183150$12271_Y - connect \$7 $or$libresoc.v:183151$12272_Y - connect \$80 $ternary$libresoc.v:183152$12273_Y - connect \$82 $ternary$libresoc.v:183153$12274_Y - connect \$84 $ternary$libresoc.v:183154$12275_Y - connect \$86 $ternary$libresoc.v:183155$12276_Y - connect \$88 $ternary$libresoc.v:183156$12277_Y - connect \$4 $reduce_and$libresoc.v:183157$12278_Y - connect \$90 $and$libresoc.v:183158$12279_Y - connect \$92 $and$libresoc.v:183159$12280_Y - connect \$94 $and$libresoc.v:183160$12281_Y - connect \$96 $not$libresoc.v:183161$12282_Y - connect \$98 $and$libresoc.v:183162$12283_Y + assign $1\prev_wr_go$next[2:0]$12500 3'000 + case + assign $1\prev_wr_go$next[2:0]$12500 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12499 + end + connect \$100 $not$libresoc.v:185208$12276_Y + connect \$102 $and$libresoc.v:185209$12277_Y + connect \$104 $and$libresoc.v:185210$12278_Y + connect \$106 $and$libresoc.v:185211$12279_Y + connect \$108 $and$libresoc.v:185212$12280_Y + connect \$10 $and$libresoc.v:185213$12281_Y + connect \$110 $and$libresoc.v:185214$12282_Y + connect \$112 $and$libresoc.v:185215$12283_Y + connect \$114 $and$libresoc.v:185216$12284_Y + connect \$116 $and$libresoc.v:185217$12285_Y + connect \$118 $and$libresoc.v:185218$12286_Y + connect \$12 $not$libresoc.v:185219$12287_Y + connect \$14 $and$libresoc.v:185220$12288_Y + connect \$16 $not$libresoc.v:185221$12289_Y + connect \$18 $and$libresoc.v:185222$12290_Y + connect \$20 $and$libresoc.v:185223$12291_Y + connect \$24 $not$libresoc.v:185224$12292_Y + connect \$26 $and$libresoc.v:185225$12293_Y + connect \$23 $reduce_or$libresoc.v:185226$12294_Y + connect \$22 $not$libresoc.v:185227$12295_Y + connect \$2 $and$libresoc.v:185228$12296_Y + connect \$30 $and$libresoc.v:185229$12297_Y + connect \$32 $reduce_or$libresoc.v:185230$12298_Y + connect \$34 $reduce_or$libresoc.v:185231$12299_Y + connect \$36 $or$libresoc.v:185232$12300_Y + connect \$38 $not$libresoc.v:185233$12301_Y + connect \$40 $and$libresoc.v:185234$12302_Y + connect \$42 $and$libresoc.v:185235$12303_Y + connect \$44 $eq$libresoc.v:185236$12304_Y + connect \$46 $and$libresoc.v:185237$12305_Y + connect \$48 $eq$libresoc.v:185238$12306_Y + connect \$50 $and$libresoc.v:185239$12307_Y + connect \$52 $and$libresoc.v:185240$12308_Y + connect \$54 $and$libresoc.v:185241$12309_Y + connect \$56 $or$libresoc.v:185242$12310_Y + connect \$58 $or$libresoc.v:185243$12311_Y + connect \$5 $not$libresoc.v:185244$12312_Y + connect \$60 $or$libresoc.v:185245$12313_Y + connect \$62 $or$libresoc.v:185246$12314_Y + connect \$64 $and$libresoc.v:185247$12315_Y + connect \$66 $and$libresoc.v:185248$12316_Y + connect \$68 $or$libresoc.v:185249$12317_Y + connect \$70 $and$libresoc.v:185250$12318_Y + connect \$72 $and$libresoc.v:185251$12319_Y + connect \$74 $and$libresoc.v:185252$12320_Y + connect \$76 $ternary$libresoc.v:185253$12321_Y + connect \$78 $ternary$libresoc.v:185254$12322_Y + connect \$7 $or$libresoc.v:185255$12323_Y + connect \$80 $ternary$libresoc.v:185256$12324_Y + connect \$82 $ternary$libresoc.v:185257$12325_Y + connect \$84 $ternary$libresoc.v:185258$12326_Y + connect \$86 $ternary$libresoc.v:185259$12327_Y + connect \$88 $ternary$libresoc.v:185260$12328_Y + connect \$4 $reduce_and$libresoc.v:185261$12329_Y + connect \$90 $and$libresoc.v:185262$12330_Y + connect \$92 $and$libresoc.v:185263$12331_Y + connect \$94 $and$libresoc.v:185264$12332_Y + connect \$96 $not$libresoc.v:185265$12333_Y + connect \$98 $and$libresoc.v:185266$12334_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -384290,48 +387169,48 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:183680.1-183860.10" +attribute \src "libresoc.v:185784.1-185964.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:183832.3-183835.6" - wire width 7 $0$memwr$\memory$libresoc.v:183834$12607_ADDR[6:0]$12610 - attribute \src "libresoc.v:183832.3-183835.6" - wire width 64 $0$memwr$\memory$libresoc.v:183834$12607_DATA[63:0]$12611 - attribute \src "libresoc.v:183832.3-183835.6" - wire width 64 $0$memwr$\memory$libresoc.v:183834$12607_EN[63:0]$12612 - attribute \src "libresoc.v:183832.3-183835.6" + attribute \src "libresoc.v:185936.3-185939.6" + wire width 7 $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 + attribute \src "libresoc.v:185936.3-185939.6" + wire width 64 $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 + attribute \src "libresoc.v:185936.3-185939.6" + wire width 64 $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 + attribute \src "libresoc.v:185936.3-185939.6" wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:183681.7-183681.20" + attribute \src "libresoc.v:185785.7-185785.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183837.3-183845.6" - wire $0\ren_delay$next[0:0]$12615 - attribute \src "libresoc.v:183713.3-183714.35" + attribute \src "libresoc.v:185941.3-185949.6" + wire $0\ren_delay$next[0:0]$12666 + attribute \src "libresoc.v:185817.3-185818.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:183846.3-183855.6" + attribute \src "libresoc.v:185950.3-185959.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:183837.3-183845.6" - wire $1\ren_delay$next[0:0]$12616 - attribute \src "libresoc.v:183697.7-183697.23" + attribute \src "libresoc.v:185941.3-185949.6" + wire $1\ren_delay$next[0:0]$12667 + attribute \src "libresoc.v:185801.7-185801.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:183846.3-183855.6" + attribute \src "libresoc.v:185950.3-185959.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:183836.26-183836.32" - wire width 64 $memrd$\memory$libresoc.v:183836$12613_DATA + attribute \src "libresoc.v:185940.26-185940.32" + wire width 64 $memrd$\memory$libresoc.v:185940$12664_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:183834$12607_ADDR + wire width 7 $memwr$\memory$libresoc.v:185938$12658_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:183834$12607_DATA + wire width 64 $memwr$\memory$libresoc.v:185938$12658_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:183834$12607_EN - attribute \src "libresoc.v:183831.13-183831.16" + wire width 64 $memwr$\memory$libresoc.v:185938$12658_EN + attribute \src "libresoc.v:185935.13-185935.16" wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:183681.7-183681.15" + attribute \src "libresoc.v:185785.7-185785.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr @@ -384359,1140 +387238,1140 @@ module \spr wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:183715.14-183715.20" + attribute \src "libresoc.v:185819.14-185819.20" memory width 64 size 113 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12618 + cell $meminit $meminit$\memory$libresoc.v:0$12669 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12618 + parameter \PRIORITY 12669 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12619 + cell $meminit $meminit$\memory$libresoc.v:0$12670 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12619 + parameter \PRIORITY 12670 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12620 + cell $meminit $meminit$\memory$libresoc.v:0$12671 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12620 + parameter \PRIORITY 12671 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12621 + cell $meminit $meminit$\memory$libresoc.v:0$12672 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12621 + parameter \PRIORITY 12672 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12622 + cell $meminit $meminit$\memory$libresoc.v:0$12673 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12622 + parameter \PRIORITY 12673 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12623 + cell $meminit $meminit$\memory$libresoc.v:0$12674 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12623 + parameter \PRIORITY 12674 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12624 + cell $meminit $meminit$\memory$libresoc.v:0$12675 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12624 + parameter \PRIORITY 12675 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12625 + cell $meminit $meminit$\memory$libresoc.v:0$12676 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12625 + parameter \PRIORITY 12676 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12626 + cell $meminit $meminit$\memory$libresoc.v:0$12677 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12626 + parameter \PRIORITY 12677 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12627 + cell $meminit $meminit$\memory$libresoc.v:0$12678 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12627 + parameter \PRIORITY 12678 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12628 + cell $meminit $meminit$\memory$libresoc.v:0$12679 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12628 + parameter \PRIORITY 12679 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12629 + cell $meminit $meminit$\memory$libresoc.v:0$12680 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12629 + parameter \PRIORITY 12680 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12630 + cell $meminit $meminit$\memory$libresoc.v:0$12681 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12630 + parameter \PRIORITY 12681 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12631 + cell $meminit $meminit$\memory$libresoc.v:0$12682 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12631 + parameter \PRIORITY 12682 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12632 + cell $meminit $meminit$\memory$libresoc.v:0$12683 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12632 + parameter \PRIORITY 12683 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12633 + cell $meminit $meminit$\memory$libresoc.v:0$12684 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12633 + parameter \PRIORITY 12684 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12634 + cell $meminit $meminit$\memory$libresoc.v:0$12685 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12634 + parameter \PRIORITY 12685 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12635 + cell $meminit $meminit$\memory$libresoc.v:0$12686 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12635 + parameter \PRIORITY 12686 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12636 + cell $meminit $meminit$\memory$libresoc.v:0$12687 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12636 + parameter \PRIORITY 12687 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12637 + cell $meminit $meminit$\memory$libresoc.v:0$12688 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12637 + parameter \PRIORITY 12688 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12638 + cell $meminit $meminit$\memory$libresoc.v:0$12689 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12638 + parameter \PRIORITY 12689 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12639 + cell $meminit $meminit$\memory$libresoc.v:0$12690 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12639 + parameter \PRIORITY 12690 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12640 + cell $meminit $meminit$\memory$libresoc.v:0$12691 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12640 + parameter \PRIORITY 12691 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12641 + cell $meminit $meminit$\memory$libresoc.v:0$12692 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12641 + parameter \PRIORITY 12692 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12642 + cell $meminit $meminit$\memory$libresoc.v:0$12693 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12642 + parameter \PRIORITY 12693 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12643 + cell $meminit $meminit$\memory$libresoc.v:0$12694 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12643 + parameter \PRIORITY 12694 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12644 + cell $meminit $meminit$\memory$libresoc.v:0$12695 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12644 + parameter \PRIORITY 12695 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12645 + cell $meminit $meminit$\memory$libresoc.v:0$12696 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12645 + parameter \PRIORITY 12696 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12646 + cell $meminit $meminit$\memory$libresoc.v:0$12697 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12646 + parameter \PRIORITY 12697 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12647 + cell $meminit $meminit$\memory$libresoc.v:0$12698 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12647 + parameter \PRIORITY 12698 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12648 + cell $meminit $meminit$\memory$libresoc.v:0$12699 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12648 + parameter \PRIORITY 12699 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12649 + cell $meminit $meminit$\memory$libresoc.v:0$12700 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12649 + parameter \PRIORITY 12700 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12650 + cell $meminit $meminit$\memory$libresoc.v:0$12701 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12650 + parameter \PRIORITY 12701 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 32 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12651 + cell $meminit $meminit$\memory$libresoc.v:0$12702 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12651 + parameter \PRIORITY 12702 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 33 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12652 + cell $meminit $meminit$\memory$libresoc.v:0$12703 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12652 + parameter \PRIORITY 12703 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 34 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12653 + cell $meminit $meminit$\memory$libresoc.v:0$12704 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12653 + parameter \PRIORITY 12704 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 35 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12654 + cell $meminit $meminit$\memory$libresoc.v:0$12705 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12654 + parameter \PRIORITY 12705 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 36 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12655 + cell $meminit $meminit$\memory$libresoc.v:0$12706 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12655 + parameter \PRIORITY 12706 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 37 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12656 + cell $meminit $meminit$\memory$libresoc.v:0$12707 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12656 + parameter \PRIORITY 12707 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 38 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12657 + cell $meminit $meminit$\memory$libresoc.v:0$12708 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12657 + parameter \PRIORITY 12708 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 39 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12658 + cell $meminit $meminit$\memory$libresoc.v:0$12709 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12658 + parameter \PRIORITY 12709 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 40 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12659 + cell $meminit $meminit$\memory$libresoc.v:0$12710 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12659 + parameter \PRIORITY 12710 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 41 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12660 + cell $meminit $meminit$\memory$libresoc.v:0$12711 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12660 + parameter \PRIORITY 12711 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 42 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12661 + cell $meminit $meminit$\memory$libresoc.v:0$12712 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12661 + parameter \PRIORITY 12712 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 43 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12662 + cell $meminit $meminit$\memory$libresoc.v:0$12713 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12662 + parameter \PRIORITY 12713 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 44 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12663 + cell $meminit $meminit$\memory$libresoc.v:0$12714 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12663 + parameter \PRIORITY 12714 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 45 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12664 + cell $meminit $meminit$\memory$libresoc.v:0$12715 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12664 + parameter \PRIORITY 12715 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 46 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12665 + cell $meminit $meminit$\memory$libresoc.v:0$12716 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12665 + parameter \PRIORITY 12716 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 47 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12666 + cell $meminit $meminit$\memory$libresoc.v:0$12717 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12666 + parameter \PRIORITY 12717 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 48 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12667 + cell $meminit $meminit$\memory$libresoc.v:0$12718 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12667 + parameter \PRIORITY 12718 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 49 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12668 + cell $meminit $meminit$\memory$libresoc.v:0$12719 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12668 + parameter \PRIORITY 12719 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 50 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12669 + cell $meminit $meminit$\memory$libresoc.v:0$12720 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12669 + parameter \PRIORITY 12720 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 51 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12670 + cell $meminit $meminit$\memory$libresoc.v:0$12721 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12670 + parameter \PRIORITY 12721 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 52 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12671 + cell $meminit $meminit$\memory$libresoc.v:0$12722 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12671 + parameter \PRIORITY 12722 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 53 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12672 + cell $meminit $meminit$\memory$libresoc.v:0$12723 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12672 + parameter \PRIORITY 12723 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 54 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12673 + cell $meminit $meminit$\memory$libresoc.v:0$12724 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12673 + parameter \PRIORITY 12724 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 55 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12674 + cell $meminit $meminit$\memory$libresoc.v:0$12725 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12674 + parameter \PRIORITY 12725 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 56 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12675 + cell $meminit $meminit$\memory$libresoc.v:0$12726 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12675 + parameter \PRIORITY 12726 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 57 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12676 + cell $meminit $meminit$\memory$libresoc.v:0$12727 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12676 + parameter \PRIORITY 12727 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 58 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12677 + cell $meminit $meminit$\memory$libresoc.v:0$12728 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12677 + parameter \PRIORITY 12728 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 59 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12678 + cell $meminit $meminit$\memory$libresoc.v:0$12729 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12678 + parameter \PRIORITY 12729 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 60 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12679 + cell $meminit $meminit$\memory$libresoc.v:0$12730 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12679 + parameter \PRIORITY 12730 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 61 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12680 + cell $meminit $meminit$\memory$libresoc.v:0$12731 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12680 + parameter \PRIORITY 12731 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 62 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12681 + cell $meminit $meminit$\memory$libresoc.v:0$12732 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12681 + parameter \PRIORITY 12732 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 63 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12682 + cell $meminit $meminit$\memory$libresoc.v:0$12733 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12682 + parameter \PRIORITY 12733 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 64 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12683 + cell $meminit $meminit$\memory$libresoc.v:0$12734 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12683 + parameter \PRIORITY 12734 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 65 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12684 + cell $meminit $meminit$\memory$libresoc.v:0$12735 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12684 + parameter \PRIORITY 12735 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 66 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12685 + cell $meminit $meminit$\memory$libresoc.v:0$12736 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12685 + parameter \PRIORITY 12736 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 67 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12686 + cell $meminit $meminit$\memory$libresoc.v:0$12737 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12686 + parameter \PRIORITY 12737 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 68 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12687 + cell $meminit $meminit$\memory$libresoc.v:0$12738 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12687 + parameter \PRIORITY 12738 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 69 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12688 + cell $meminit $meminit$\memory$libresoc.v:0$12739 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12688 + parameter \PRIORITY 12739 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 70 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12689 + cell $meminit $meminit$\memory$libresoc.v:0$12740 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12689 + parameter \PRIORITY 12740 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 71 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12690 + cell $meminit $meminit$\memory$libresoc.v:0$12741 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12690 + parameter \PRIORITY 12741 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 72 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12691 + cell $meminit $meminit$\memory$libresoc.v:0$12742 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12691 + parameter \PRIORITY 12742 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 73 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12692 + cell $meminit $meminit$\memory$libresoc.v:0$12743 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12692 + parameter \PRIORITY 12743 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 74 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12693 + cell $meminit $meminit$\memory$libresoc.v:0$12744 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12693 + parameter \PRIORITY 12744 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 75 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12694 + cell $meminit $meminit$\memory$libresoc.v:0$12745 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12694 + parameter \PRIORITY 12745 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 76 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12695 + cell $meminit $meminit$\memory$libresoc.v:0$12746 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12695 + parameter \PRIORITY 12746 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 77 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12696 + cell $meminit $meminit$\memory$libresoc.v:0$12747 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12696 + parameter \PRIORITY 12747 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 78 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12697 + cell $meminit $meminit$\memory$libresoc.v:0$12748 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12697 + parameter \PRIORITY 12748 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 79 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12698 + cell $meminit $meminit$\memory$libresoc.v:0$12749 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12698 + parameter \PRIORITY 12749 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 80 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12699 + cell $meminit $meminit$\memory$libresoc.v:0$12750 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12699 + parameter \PRIORITY 12750 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 81 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12700 + cell $meminit $meminit$\memory$libresoc.v:0$12751 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12700 + parameter \PRIORITY 12751 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 82 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12701 + cell $meminit $meminit$\memory$libresoc.v:0$12752 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12701 + parameter \PRIORITY 12752 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 83 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12702 + cell $meminit $meminit$\memory$libresoc.v:0$12753 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12702 + parameter \PRIORITY 12753 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 84 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12703 + cell $meminit $meminit$\memory$libresoc.v:0$12754 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12703 + parameter \PRIORITY 12754 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 85 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12704 + cell $meminit $meminit$\memory$libresoc.v:0$12755 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12704 + parameter \PRIORITY 12755 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 86 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12705 + cell $meminit $meminit$\memory$libresoc.v:0$12756 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12705 + parameter \PRIORITY 12756 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 87 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12706 + cell $meminit $meminit$\memory$libresoc.v:0$12757 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12706 + parameter \PRIORITY 12757 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 88 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12707 + cell $meminit $meminit$\memory$libresoc.v:0$12758 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12707 + parameter \PRIORITY 12758 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 89 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12708 + cell $meminit $meminit$\memory$libresoc.v:0$12759 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12708 + parameter \PRIORITY 12759 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 90 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12709 + cell $meminit $meminit$\memory$libresoc.v:0$12760 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12709 + parameter \PRIORITY 12760 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 91 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12710 + cell $meminit $meminit$\memory$libresoc.v:0$12761 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12710 + parameter \PRIORITY 12761 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 92 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12711 + cell $meminit $meminit$\memory$libresoc.v:0$12762 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12711 + parameter \PRIORITY 12762 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 93 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12712 + cell $meminit $meminit$\memory$libresoc.v:0$12763 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12712 + parameter \PRIORITY 12763 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 94 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12713 + cell $meminit $meminit$\memory$libresoc.v:0$12764 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12713 + parameter \PRIORITY 12764 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 95 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12714 + cell $meminit $meminit$\memory$libresoc.v:0$12765 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12714 + parameter \PRIORITY 12765 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 96 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12715 + cell $meminit $meminit$\memory$libresoc.v:0$12766 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12715 + parameter \PRIORITY 12766 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 97 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12716 + cell $meminit $meminit$\memory$libresoc.v:0$12767 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12716 + parameter \PRIORITY 12767 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 98 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12717 + cell $meminit $meminit$\memory$libresoc.v:0$12768 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12717 + parameter \PRIORITY 12768 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 99 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12718 + cell $meminit $meminit$\memory$libresoc.v:0$12769 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12718 + parameter \PRIORITY 12769 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 100 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12719 + cell $meminit $meminit$\memory$libresoc.v:0$12770 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12719 + parameter \PRIORITY 12770 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 101 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12720 + cell $meminit $meminit$\memory$libresoc.v:0$12771 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12720 + parameter \PRIORITY 12771 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 102 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12721 + cell $meminit $meminit$\memory$libresoc.v:0$12772 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12721 + parameter \PRIORITY 12772 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 103 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12722 + cell $meminit $meminit$\memory$libresoc.v:0$12773 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12722 + parameter \PRIORITY 12773 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 104 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12723 + cell $meminit $meminit$\memory$libresoc.v:0$12774 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12723 + parameter \PRIORITY 12774 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 105 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12724 + cell $meminit $meminit$\memory$libresoc.v:0$12775 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12724 + parameter \PRIORITY 12775 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 106 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12725 + cell $meminit $meminit$\memory$libresoc.v:0$12776 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12725 + parameter \PRIORITY 12776 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 107 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12726 + cell $meminit $meminit$\memory$libresoc.v:0$12777 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12726 + parameter \PRIORITY 12777 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 108 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12727 + cell $meminit $meminit$\memory$libresoc.v:0$12778 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12727 + parameter \PRIORITY 12778 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 109 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12728 + cell $meminit $meminit$\memory$libresoc.v:0$12779 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12728 + parameter \PRIORITY 12779 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 110 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12729 + cell $meminit $meminit$\memory$libresoc.v:0$12780 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12729 + parameter \PRIORITY 12780 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 111 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12730 + cell $meminit $meminit$\memory$libresoc.v:0$12781 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12730 + parameter \PRIORITY 12781 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 112 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:183836.26-183836.32" - cell $memrd $memrd$\memory$libresoc.v:183836$12613 + attribute \src "libresoc.v:185940.26-185940.32" + cell $memrd $memrd$\memory$libresoc.v:185940$12664 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -385501,83 +388380,83 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:183836$12613_DATA + connect \DATA $memrd$\memory$libresoc.v:185940$12664_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$12731 + cell $memwr $memwr$\memory$libresoc.v:0$12782 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 12731 + parameter \PRIORITY 12782 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:183834$12607_ADDR + connect \ADDR $memwr$\memory$libresoc.v:185938$12658_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:183834$12607_DATA - connect \EN $memwr$\memory$libresoc.v:183834$12607_EN + connect \DATA $memwr$\memory$libresoc.v:185938$12658_DATA + connect \EN $memwr$\memory$libresoc.v:185938$12658_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12734 + process $proc$libresoc.v:0$12785 sync always sync init end - attribute \src "libresoc.v:183681.7-183681.20" - process $proc$libresoc.v:183681$12732 + attribute \src "libresoc.v:185785.7-185785.20" + process $proc$libresoc.v:185785$12783 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183697.7-183697.23" - process $proc$libresoc.v:183697$12733 + attribute \src "libresoc.v:185801.7-185801.23" + process $proc$libresoc.v:185801$12784 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:183713.3-183714.35" - process $proc$libresoc.v:183713$12608 + attribute \src "libresoc.v:185817.3-185818.35" + process $proc$libresoc.v:185817$12659 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:183832.3-183835.6" - process $proc$libresoc.v:183832$12609 + attribute \src "libresoc.v:185936.3-185939.6" + process $proc$libresoc.v:185936$12660 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:183834$12607_ADDR[6:0]$12610 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:183834$12607_DATA[63:0]$12611 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:183834$12607_EN[63:0]$12612 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:183834.5-183834.59" + attribute \src "libresoc.v:185938.5-185938.59" switch \spr1__wen - attribute \src "libresoc.v:183834.9-183834.18" + attribute \src "libresoc.v:185938.9-185938.18" case 1'1 - assign $0$memwr$\memory$libresoc.v:183834$12607_ADDR[6:0]$12610 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:183834$12607_DATA[63:0]$12611 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:183834$12607_EN[63:0]$12612 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:183834$12607_ADDR $0$memwr$\memory$libresoc.v:183834$12607_ADDR[6:0]$12610 - update $memwr$\memory$libresoc.v:183834$12607_DATA $0$memwr$\memory$libresoc.v:183834$12607_DATA[63:0]$12611 - update $memwr$\memory$libresoc.v:183834$12607_EN $0$memwr$\memory$libresoc.v:183834$12607_EN[63:0]$12612 + update $memwr$\memory$libresoc.v:185938$12658_ADDR $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 + update $memwr$\memory$libresoc.v:185938$12658_DATA $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 + update $memwr$\memory$libresoc.v:185938$12658_EN $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 end - attribute \src "libresoc.v:183837.3-183845.6" - process $proc$libresoc.v:183837$12614 + attribute \src "libresoc.v:185941.3-185949.6" + process $proc$libresoc.v:185941$12665 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$12615 $1\ren_delay$next[0:0]$12616 - attribute \src "libresoc.v:183838.5-183838.29" + assign $0\ren_delay$next[0:0]$12666 $1\ren_delay$next[0:0]$12667 + attribute \src "libresoc.v:185942.5-185942.29" switch \initial - attribute \src "libresoc.v:183838.9-183838.17" + attribute \src "libresoc.v:185942.9-185942.17" case 1'1 case end @@ -385586,21 +388465,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$12616 1'0 + assign $1\ren_delay$next[0:0]$12667 1'0 case - assign $1\ren_delay$next[0:0]$12616 \spr1__ren + assign $1\ren_delay$next[0:0]$12667 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12615 + update \ren_delay$next $0\ren_delay$next[0:0]$12666 end - attribute \src "libresoc.v:183846.3-183855.6" - process $proc$libresoc.v:183846$12617 + attribute \src "libresoc.v:185950.3-185959.6" + process $proc$libresoc.v:185950$12668 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:183847.5-183847.29" + attribute \src "libresoc.v:185951.5-185951.29" switch \initial - attribute \src "libresoc.v:183847.9-183847.17" + attribute \src "libresoc.v:185951.9-185951.17" case 1'1 case end @@ -385616,503 +388495,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:183836$12613_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:185940$12664_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:183864.1-185113.10" +attribute \src "libresoc.v:185968.1-187221.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:184610.3-184611.25" + attribute \src "libresoc.v:186718.3-186719.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:184608.3-184609.40" + attribute \src "libresoc.v:186716.3-186717.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:185004.3-185012.6" - wire $0\alu_l_r_alu$next[0:0]$12948 - attribute \src "libresoc.v:184538.3-184539.39" + attribute \src "libresoc.v:187112.3-187120.6" + wire $0\alu_l_r_alu$next[0:0]$12999 + attribute \src "libresoc.v:186646.3-186647.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:184790.3-184802.6" - wire width 13 $0\alu_spr0_spr_op__fn_unit$next[12:0]$12870 - attribute \src "libresoc.v:184580.3-184581.65" - wire width 13 $0\alu_spr0_spr_op__fn_unit[12:0] - attribute \src "libresoc.v:184790.3-184802.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12871 - attribute \src "libresoc.v:184582.3-184583.59" + attribute \src "libresoc.v:186898.3-186910.6" + wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 + attribute \src "libresoc.v:186688.3-186689.65" + wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] + attribute \src "libresoc.v:186898.3-186910.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12922 + attribute \src "libresoc.v:186690.3-186691.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:184790.3-184802.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12872 - attribute \src "libresoc.v:184578.3-184579.69" + attribute \src "libresoc.v:186898.3-186910.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 + attribute \src "libresoc.v:186686.3-186687.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:184790.3-184802.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12873 - attribute \src "libresoc.v:184584.3-184585.67" + attribute \src "libresoc.v:186898.3-186910.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 + attribute \src "libresoc.v:186692.3-186693.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:184995.3-185003.6" - wire $0\alui_l_r_alui$next[0:0]$12945 - attribute \src "libresoc.v:184540.3-184541.43" + attribute \src "libresoc.v:187103.3-187111.6" + wire $0\alui_l_r_alui$next[0:0]$12996 + attribute \src "libresoc.v:186648.3-186649.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:184803.3-184824.6" - wire width 64 $0\data_r0__o$next[63:0]$12879 - attribute \src "libresoc.v:184574.3-184575.37" + attribute \src "libresoc.v:186911.3-186932.6" + wire width 64 $0\data_r0__o$next[63:0]$12930 + attribute \src "libresoc.v:186682.3-186683.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:184803.3-184824.6" - wire $0\data_r0__o_ok$next[0:0]$12880 - attribute \src "libresoc.v:184576.3-184577.43" + attribute \src "libresoc.v:186911.3-186932.6" + wire $0\data_r0__o_ok$next[0:0]$12931 + attribute \src "libresoc.v:186684.3-186685.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:184825.3-184846.6" - wire width 64 $0\data_r1__spr1$next[63:0]$12887 - attribute \src "libresoc.v:184570.3-184571.43" + attribute \src "libresoc.v:186933.3-186954.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12938 + attribute \src "libresoc.v:186678.3-186679.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:184825.3-184846.6" - wire $0\data_r1__spr1_ok$next[0:0]$12888 - attribute \src "libresoc.v:184572.3-184573.49" + attribute \src "libresoc.v:186933.3-186954.6" + wire $0\data_r1__spr1_ok$next[0:0]$12939 + attribute \src "libresoc.v:186680.3-186681.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:184847.3-184868.6" - wire width 64 $0\data_r2__fast1$next[63:0]$12895 - attribute \src "libresoc.v:184566.3-184567.45" + attribute \src "libresoc.v:186955.3-186976.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12946 + attribute \src "libresoc.v:186674.3-186675.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:184847.3-184868.6" - wire $0\data_r2__fast1_ok$next[0:0]$12896 - attribute \src "libresoc.v:184568.3-184569.51" + attribute \src "libresoc.v:186955.3-186976.6" + wire $0\data_r2__fast1_ok$next[0:0]$12947 + attribute \src "libresoc.v:186676.3-186677.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:184869.3-184890.6" - wire $0\data_r3__xer_so$next[0:0]$12903 - attribute \src "libresoc.v:184562.3-184563.47" + attribute \src "libresoc.v:186977.3-186998.6" + wire $0\data_r3__xer_so$next[0:0]$12954 + attribute \src "libresoc.v:186670.3-186671.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:184869.3-184890.6" - wire $0\data_r3__xer_so_ok$next[0:0]$12904 - attribute \src "libresoc.v:184564.3-184565.53" + attribute \src "libresoc.v:186977.3-186998.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12955 + attribute \src "libresoc.v:186672.3-186673.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:184891.3-184912.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$12911 - attribute \src "libresoc.v:184558.3-184559.47" + attribute \src "libresoc.v:186999.3-187020.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$12962 + attribute \src "libresoc.v:186666.3-186667.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:184891.3-184912.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$12912 - attribute \src "libresoc.v:184560.3-184561.53" + attribute \src "libresoc.v:186999.3-187020.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$12963 + attribute \src "libresoc.v:186668.3-186669.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:184913.3-184934.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$12919 - attribute \src "libresoc.v:184554.3-184555.47" + attribute \src "libresoc.v:187021.3-187042.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$12970 + attribute \src "libresoc.v:186662.3-186663.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:184913.3-184934.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$12920 - attribute \src "libresoc.v:184556.3-184557.53" + attribute \src "libresoc.v:187021.3-187042.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$12971 + attribute \src "libresoc.v:186664.3-186665.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:185013.3-185022.6" + attribute \src "libresoc.v:187121.3-187130.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:185023.3-185032.6" + attribute \src "libresoc.v:187131.3-187140.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:185033.3-185042.6" + attribute \src "libresoc.v:187141.3-187150.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:185043.3-185052.6" + attribute \src "libresoc.v:187151.3-187160.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:185053.3-185062.6" + attribute \src "libresoc.v:187161.3-187170.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:185063.3-185072.6" + attribute \src "libresoc.v:187171.3-187180.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:183865.7-183865.20" + attribute \src "libresoc.v:185969.7-185969.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184745.3-184753.6" - wire $0\opc_l_r_opc$next[0:0]$12855 - attribute \src "libresoc.v:184594.3-184595.39" + attribute \src "libresoc.v:186853.3-186861.6" + wire $0\opc_l_r_opc$next[0:0]$12906 + attribute \src "libresoc.v:186702.3-186703.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:184736.3-184744.6" - wire $0\opc_l_s_opc$next[0:0]$12852 - attribute \src "libresoc.v:184596.3-184597.39" + attribute \src "libresoc.v:186844.3-186852.6" + wire $0\opc_l_s_opc$next[0:0]$12903 + attribute \src "libresoc.v:186704.3-186705.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:185073.3-185081.6" - wire width 6 $0\prev_wr_go$next[5:0]$12957 - attribute \src "libresoc.v:184606.3-184607.37" + attribute \src "libresoc.v:187181.3-187189.6" + wire width 6 $0\prev_wr_go$next[5:0]$13008 + attribute \src "libresoc.v:186714.3-186715.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:184690.3-184699.6" + attribute \src "libresoc.v:186798.3-186807.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:184781.3-184789.6" - wire width 6 $0\req_l_r_req$next[5:0]$12867 - attribute \src "libresoc.v:184586.3-184587.39" + attribute \src "libresoc.v:186889.3-186897.6" + wire width 6 $0\req_l_r_req$next[5:0]$12918 + attribute \src "libresoc.v:186694.3-186695.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:184772.3-184780.6" - wire width 6 $0\req_l_s_req$next[5:0]$12864 - attribute \src "libresoc.v:184588.3-184589.39" + attribute \src "libresoc.v:186880.3-186888.6" + wire width 6 $0\req_l_s_req$next[5:0]$12915 + attribute \src "libresoc.v:186696.3-186697.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:184709.3-184717.6" - wire $0\rok_l_r_rdok$next[0:0]$12843 - attribute \src "libresoc.v:184602.3-184603.41" + attribute \src "libresoc.v:186817.3-186825.6" + wire $0\rok_l_r_rdok$next[0:0]$12894 + attribute \src "libresoc.v:186710.3-186711.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:184700.3-184708.6" - wire $0\rok_l_s_rdok$next[0:0]$12840 - attribute \src "libresoc.v:184604.3-184605.41" + attribute \src "libresoc.v:186808.3-186816.6" + wire $0\rok_l_s_rdok$next[0:0]$12891 + attribute \src "libresoc.v:186712.3-186713.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:184727.3-184735.6" - wire $0\rst_l_r_rst$next[0:0]$12849 - attribute \src "libresoc.v:184598.3-184599.39" + attribute \src "libresoc.v:186835.3-186843.6" + wire $0\rst_l_r_rst$next[0:0]$12900 + attribute \src "libresoc.v:186706.3-186707.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:184718.3-184726.6" - wire $0\rst_l_s_rst$next[0:0]$12846 - attribute \src "libresoc.v:184600.3-184601.39" + attribute \src "libresoc.v:186826.3-186834.6" + wire $0\rst_l_s_rst$next[0:0]$12897 + attribute \src "libresoc.v:186708.3-186709.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:184763.3-184771.6" - wire width 6 $0\src_l_r_src$next[5:0]$12861 - attribute \src "libresoc.v:184590.3-184591.39" + attribute \src "libresoc.v:186871.3-186879.6" + wire width 6 $0\src_l_r_src$next[5:0]$12912 + attribute \src "libresoc.v:186698.3-186699.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:184754.3-184762.6" - wire width 6 $0\src_l_s_src$next[5:0]$12858 - attribute \src "libresoc.v:184592.3-184593.39" + attribute \src "libresoc.v:186862.3-186870.6" + wire width 6 $0\src_l_s_src$next[5:0]$12909 + attribute \src "libresoc.v:186700.3-186701.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:184935.3-184944.6" - wire width 64 $0\src_r0$next[63:0]$12927 - attribute \src "libresoc.v:184552.3-184553.29" + attribute \src "libresoc.v:187043.3-187052.6" + wire width 64 $0\src_r0$next[63:0]$12978 + attribute \src "libresoc.v:186660.3-186661.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:184945.3-184954.6" - wire width 64 $0\src_r1$next[63:0]$12930 - attribute \src "libresoc.v:184550.3-184551.29" + attribute \src "libresoc.v:187053.3-187062.6" + wire width 64 $0\src_r1$next[63:0]$12981 + attribute \src "libresoc.v:186658.3-186659.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:184955.3-184964.6" - wire width 64 $0\src_r2$next[63:0]$12933 - attribute \src "libresoc.v:184548.3-184549.29" + attribute \src "libresoc.v:187063.3-187072.6" + wire width 64 $0\src_r2$next[63:0]$12984 + attribute \src "libresoc.v:186656.3-186657.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:184965.3-184974.6" - wire $0\src_r3$next[0:0]$12936 - attribute \src "libresoc.v:184546.3-184547.29" + attribute \src "libresoc.v:187073.3-187082.6" + wire $0\src_r3$next[0:0]$12987 + attribute \src "libresoc.v:186654.3-186655.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:184975.3-184984.6" - wire width 2 $0\src_r4$next[1:0]$12939 - attribute \src "libresoc.v:184544.3-184545.29" + attribute \src "libresoc.v:187083.3-187092.6" + wire width 2 $0\src_r4$next[1:0]$12990 + attribute \src "libresoc.v:186652.3-186653.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:184985.3-184994.6" - wire width 2 $0\src_r5$next[1:0]$12942 - attribute \src "libresoc.v:184542.3-184543.29" + attribute \src "libresoc.v:187093.3-187102.6" + wire width 2 $0\src_r5$next[1:0]$12993 + attribute \src "libresoc.v:186650.3-186651.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:184001.7-184001.24" + attribute \src "libresoc.v:186105.7-186105.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:184011.7-184011.26" + attribute \src "libresoc.v:186115.7-186115.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:185004.3-185012.6" - wire $1\alu_l_r_alu$next[0:0]$12949 - attribute \src "libresoc.v:184019.7-184019.25" + attribute \src "libresoc.v:187112.3-187120.6" + wire $1\alu_l_r_alu$next[0:0]$13000 + attribute \src "libresoc.v:186123.7-186123.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:184790.3-184802.6" - wire width 13 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12874 - attribute \src "libresoc.v:184063.14-184063.49" - wire width 13 $1\alu_spr0_spr_op__fn_unit[12:0] - attribute \src "libresoc.v:184790.3-184802.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12875 - attribute \src "libresoc.v:184067.14-184067.43" + attribute \src "libresoc.v:186898.3-186910.6" + wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 + attribute \src "libresoc.v:186168.14-186168.49" + wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] + attribute \src "libresoc.v:186898.3-186910.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12926 + attribute \src "libresoc.v:186172.14-186172.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:184790.3-184802.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12876 - attribute \src "libresoc.v:184145.13-184145.47" + attribute \src "libresoc.v:186898.3-186910.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 + attribute \src "libresoc.v:186251.13-186251.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:184790.3-184802.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12877 - attribute \src "libresoc.v:184149.7-184149.39" + attribute \src "libresoc.v:186898.3-186910.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 + attribute \src "libresoc.v:186255.7-186255.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:184995.3-185003.6" - wire $1\alui_l_r_alui$next[0:0]$12946 - attribute \src "libresoc.v:184167.7-184167.27" + attribute \src "libresoc.v:187103.3-187111.6" + wire $1\alui_l_r_alui$next[0:0]$12997 + attribute \src "libresoc.v:186273.7-186273.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:184803.3-184824.6" - wire width 64 $1\data_r0__o$next[63:0]$12881 - attribute \src "libresoc.v:184199.14-184199.47" + attribute \src "libresoc.v:186911.3-186932.6" + wire width 64 $1\data_r0__o$next[63:0]$12932 + attribute \src "libresoc.v:186305.14-186305.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:184803.3-184824.6" - wire $1\data_r0__o_ok$next[0:0]$12882 - attribute \src "libresoc.v:184203.7-184203.27" + attribute \src "libresoc.v:186911.3-186932.6" + wire $1\data_r0__o_ok$next[0:0]$12933 + attribute \src "libresoc.v:186309.7-186309.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:184825.3-184846.6" - wire width 64 $1\data_r1__spr1$next[63:0]$12889 - attribute \src "libresoc.v:184207.14-184207.50" + attribute \src "libresoc.v:186933.3-186954.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12940 + attribute \src "libresoc.v:186313.14-186313.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:184825.3-184846.6" - wire $1\data_r1__spr1_ok$next[0:0]$12890 - attribute \src "libresoc.v:184211.7-184211.30" + attribute \src "libresoc.v:186933.3-186954.6" + wire $1\data_r1__spr1_ok$next[0:0]$12941 + attribute \src "libresoc.v:186317.7-186317.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:184847.3-184868.6" - wire width 64 $1\data_r2__fast1$next[63:0]$12897 - attribute \src "libresoc.v:184215.14-184215.51" + attribute \src "libresoc.v:186955.3-186976.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12948 + attribute \src "libresoc.v:186321.14-186321.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:184847.3-184868.6" - wire $1\data_r2__fast1_ok$next[0:0]$12898 - attribute \src "libresoc.v:184219.7-184219.31" + attribute \src "libresoc.v:186955.3-186976.6" + wire $1\data_r2__fast1_ok$next[0:0]$12949 + attribute \src "libresoc.v:186325.7-186325.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:184869.3-184890.6" - wire $1\data_r3__xer_so$next[0:0]$12905 - attribute \src "libresoc.v:184223.7-184223.29" + attribute \src "libresoc.v:186977.3-186998.6" + wire $1\data_r3__xer_so$next[0:0]$12956 + attribute \src "libresoc.v:186329.7-186329.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:184869.3-184890.6" - wire $1\data_r3__xer_so_ok$next[0:0]$12906 - attribute \src "libresoc.v:184227.7-184227.32" + attribute \src "libresoc.v:186977.3-186998.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12957 + attribute \src "libresoc.v:186333.7-186333.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:184891.3-184912.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$12913 - attribute \src "libresoc.v:184231.13-184231.35" + attribute \src "libresoc.v:186999.3-187020.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$12964 + attribute \src "libresoc.v:186337.13-186337.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:184891.3-184912.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$12914 - attribute \src "libresoc.v:184235.7-184235.32" + attribute \src "libresoc.v:186999.3-187020.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$12965 + attribute \src "libresoc.v:186341.7-186341.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:184913.3-184934.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$12921 - attribute \src "libresoc.v:184239.13-184239.35" + attribute \src "libresoc.v:187021.3-187042.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$12972 + attribute \src "libresoc.v:186345.13-186345.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:184913.3-184934.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$12922 - attribute \src "libresoc.v:184243.7-184243.32" + attribute \src "libresoc.v:187021.3-187042.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$12973 + attribute \src "libresoc.v:186349.7-186349.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:185013.3-185022.6" + attribute \src "libresoc.v:187121.3-187130.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:185023.3-185032.6" + attribute \src "libresoc.v:187131.3-187140.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:185033.3-185042.6" + attribute \src "libresoc.v:187141.3-187150.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:185043.3-185052.6" + attribute \src "libresoc.v:187151.3-187160.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:185053.3-185062.6" + attribute \src "libresoc.v:187161.3-187170.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:185063.3-185072.6" + attribute \src "libresoc.v:187171.3-187180.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:184745.3-184753.6" - wire $1\opc_l_r_opc$next[0:0]$12856 - attribute \src "libresoc.v:184271.7-184271.25" + attribute \src "libresoc.v:186853.3-186861.6" + wire $1\opc_l_r_opc$next[0:0]$12907 + attribute \src "libresoc.v:186377.7-186377.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:184736.3-184744.6" - wire $1\opc_l_s_opc$next[0:0]$12853 - attribute \src "libresoc.v:184275.7-184275.25" + attribute \src "libresoc.v:186844.3-186852.6" + wire $1\opc_l_s_opc$next[0:0]$12904 + attribute \src "libresoc.v:186381.7-186381.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:185073.3-185081.6" - wire width 6 $1\prev_wr_go$next[5:0]$12958 - attribute \src "libresoc.v:184375.13-184375.31" + attribute \src "libresoc.v:187181.3-187189.6" + wire width 6 $1\prev_wr_go$next[5:0]$13009 + attribute \src "libresoc.v:186483.13-186483.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:184690.3-184699.6" + attribute \src "libresoc.v:186798.3-186807.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:184781.3-184789.6" - wire width 6 $1\req_l_r_req$next[5:0]$12868 - attribute \src "libresoc.v:184383.13-184383.32" + attribute \src "libresoc.v:186889.3-186897.6" + wire width 6 $1\req_l_r_req$next[5:0]$12919 + attribute \src "libresoc.v:186491.13-186491.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:184772.3-184780.6" - wire width 6 $1\req_l_s_req$next[5:0]$12865 - attribute \src "libresoc.v:184387.13-184387.32" + attribute \src "libresoc.v:186880.3-186888.6" + wire width 6 $1\req_l_s_req$next[5:0]$12916 + attribute \src "libresoc.v:186495.13-186495.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:184709.3-184717.6" - wire $1\rok_l_r_rdok$next[0:0]$12844 - attribute \src "libresoc.v:184399.7-184399.26" + attribute \src "libresoc.v:186817.3-186825.6" + wire $1\rok_l_r_rdok$next[0:0]$12895 + attribute \src "libresoc.v:186507.7-186507.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:184700.3-184708.6" - wire $1\rok_l_s_rdok$next[0:0]$12841 - attribute \src "libresoc.v:184403.7-184403.26" + attribute \src "libresoc.v:186808.3-186816.6" + wire $1\rok_l_s_rdok$next[0:0]$12892 + attribute \src "libresoc.v:186511.7-186511.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:184727.3-184735.6" - wire $1\rst_l_r_rst$next[0:0]$12850 - attribute \src "libresoc.v:184407.7-184407.25" + attribute \src "libresoc.v:186835.3-186843.6" + wire $1\rst_l_r_rst$next[0:0]$12901 + attribute \src "libresoc.v:186515.7-186515.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:184718.3-184726.6" - wire $1\rst_l_s_rst$next[0:0]$12847 - attribute \src "libresoc.v:184411.7-184411.25" + attribute \src "libresoc.v:186826.3-186834.6" + wire $1\rst_l_s_rst$next[0:0]$12898 + attribute \src "libresoc.v:186519.7-186519.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:184763.3-184771.6" - wire width 6 $1\src_l_r_src$next[5:0]$12862 - attribute \src "libresoc.v:184433.13-184433.32" + attribute \src "libresoc.v:186871.3-186879.6" + wire width 6 $1\src_l_r_src$next[5:0]$12913 + attribute \src "libresoc.v:186541.13-186541.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:184754.3-184762.6" - wire width 6 $1\src_l_s_src$next[5:0]$12859 - attribute \src "libresoc.v:184437.13-184437.32" + attribute \src "libresoc.v:186862.3-186870.6" + wire width 6 $1\src_l_s_src$next[5:0]$12910 + attribute \src "libresoc.v:186545.13-186545.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:184935.3-184944.6" - wire width 64 $1\src_r0$next[63:0]$12928 - attribute \src "libresoc.v:184441.14-184441.43" + attribute \src "libresoc.v:187043.3-187052.6" + wire width 64 $1\src_r0$next[63:0]$12979 + attribute \src "libresoc.v:186549.14-186549.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:184945.3-184954.6" - wire width 64 $1\src_r1$next[63:0]$12931 - attribute \src "libresoc.v:184445.14-184445.43" + attribute \src "libresoc.v:187053.3-187062.6" + wire width 64 $1\src_r1$next[63:0]$12982 + attribute \src "libresoc.v:186553.14-186553.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:184955.3-184964.6" - wire width 64 $1\src_r2$next[63:0]$12934 - attribute \src "libresoc.v:184449.14-184449.43" + attribute \src "libresoc.v:187063.3-187072.6" + wire width 64 $1\src_r2$next[63:0]$12985 + attribute \src "libresoc.v:186557.14-186557.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:184965.3-184974.6" - wire $1\src_r3$next[0:0]$12937 - attribute \src "libresoc.v:184453.7-184453.20" + attribute \src "libresoc.v:187073.3-187082.6" + wire $1\src_r3$next[0:0]$12988 + attribute \src "libresoc.v:186561.7-186561.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:184975.3-184984.6" - wire width 2 $1\src_r4$next[1:0]$12940 - attribute \src "libresoc.v:184457.13-184457.26" + attribute \src "libresoc.v:187083.3-187092.6" + wire width 2 $1\src_r4$next[1:0]$12991 + attribute \src "libresoc.v:186565.13-186565.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:184985.3-184994.6" - wire width 2 $1\src_r5$next[1:0]$12943 - attribute \src "libresoc.v:184461.13-184461.26" + attribute \src "libresoc.v:187093.3-187102.6" + wire width 2 $1\src_r5$next[1:0]$12994 + attribute \src "libresoc.v:186569.13-186569.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:184803.3-184824.6" - wire width 64 $2\data_r0__o$next[63:0]$12883 - attribute \src "libresoc.v:184803.3-184824.6" - wire $2\data_r0__o_ok$next[0:0]$12884 - attribute \src "libresoc.v:184825.3-184846.6" - wire width 64 $2\data_r1__spr1$next[63:0]$12891 - attribute \src "libresoc.v:184825.3-184846.6" - wire $2\data_r1__spr1_ok$next[0:0]$12892 - attribute \src "libresoc.v:184847.3-184868.6" - wire width 64 $2\data_r2__fast1$next[63:0]$12899 - attribute \src "libresoc.v:184847.3-184868.6" - wire $2\data_r2__fast1_ok$next[0:0]$12900 - attribute \src "libresoc.v:184869.3-184890.6" - wire $2\data_r3__xer_so$next[0:0]$12907 - attribute \src "libresoc.v:184869.3-184890.6" - wire $2\data_r3__xer_so_ok$next[0:0]$12908 - attribute \src "libresoc.v:184891.3-184912.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$12915 - attribute \src "libresoc.v:184891.3-184912.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$12916 - attribute \src "libresoc.v:184913.3-184934.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$12923 - attribute \src "libresoc.v:184913.3-184934.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$12924 - attribute \src "libresoc.v:184803.3-184824.6" - wire $3\data_r0__o_ok$next[0:0]$12885 - attribute \src "libresoc.v:184825.3-184846.6" - wire $3\data_r1__spr1_ok$next[0:0]$12893 - attribute \src "libresoc.v:184847.3-184868.6" - wire $3\data_r2__fast1_ok$next[0:0]$12901 - attribute \src "libresoc.v:184869.3-184890.6" - wire $3\data_r3__xer_so_ok$next[0:0]$12909 - attribute \src "libresoc.v:184891.3-184912.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$12917 - attribute \src "libresoc.v:184913.3-184934.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$12925 - attribute \src "libresoc.v:184473.19-184473.133" - wire $and$libresoc.v:184473$12736_Y - attribute \src "libresoc.v:184474.19-184474.183" - wire width 6 $and$libresoc.v:184474$12737_Y - attribute \src "libresoc.v:184475.19-184475.115" - wire width 6 $and$libresoc.v:184475$12738_Y - attribute \src "libresoc.v:184477.19-184477.115" - wire width 6 $and$libresoc.v:184477$12740_Y - attribute \src "libresoc.v:184478.19-184478.125" - wire $and$libresoc.v:184478$12741_Y - attribute \src "libresoc.v:184479.19-184479.125" - wire $and$libresoc.v:184479$12742_Y - attribute \src "libresoc.v:184480.19-184480.125" - wire $and$libresoc.v:184480$12743_Y - attribute \src "libresoc.v:184481.19-184481.125" - wire $and$libresoc.v:184481$12744_Y - attribute \src "libresoc.v:184482.19-184482.125" - wire $and$libresoc.v:184482$12745_Y - attribute \src "libresoc.v:184484.19-184484.125" - wire $and$libresoc.v:184484$12747_Y - attribute \src "libresoc.v:184485.19-184485.165" - wire width 6 $and$libresoc.v:184485$12748_Y - attribute \src "libresoc.v:184486.19-184486.121" - wire width 6 $and$libresoc.v:184486$12749_Y - attribute \src "libresoc.v:184487.19-184487.127" - wire $and$libresoc.v:184487$12750_Y - attribute \src "libresoc.v:184488.19-184488.127" - wire $and$libresoc.v:184488$12751_Y - attribute \src "libresoc.v:184490.19-184490.127" - wire $and$libresoc.v:184490$12753_Y - attribute \src "libresoc.v:184491.19-184491.127" - wire $and$libresoc.v:184491$12754_Y - attribute \src "libresoc.v:184492.19-184492.127" - wire $and$libresoc.v:184492$12755_Y - attribute \src "libresoc.v:184493.19-184493.127" - wire $and$libresoc.v:184493$12756_Y - attribute \src "libresoc.v:184494.18-184494.110" - wire $and$libresoc.v:184494$12757_Y - attribute \src "libresoc.v:184496.18-184496.98" - wire $and$libresoc.v:184496$12759_Y - attribute \src "libresoc.v:184498.18-184498.100" - wire $and$libresoc.v:184498$12761_Y - attribute \src "libresoc.v:184499.18-184499.182" - wire width 6 $and$libresoc.v:184499$12762_Y - attribute \src "libresoc.v:184501.18-184501.119" - wire width 6 $and$libresoc.v:184501$12764_Y - attribute \src "libresoc.v:184504.18-184504.116" - wire $and$libresoc.v:184504$12767_Y - attribute \src "libresoc.v:184509.18-184509.113" - wire $and$libresoc.v:184509$12772_Y - attribute \src "libresoc.v:184510.18-184510.125" - wire width 6 $and$libresoc.v:184510$12773_Y - attribute \src "libresoc.v:184512.18-184512.112" - wire $and$libresoc.v:184512$12775_Y - attribute \src "libresoc.v:184514.18-184514.126" - wire $and$libresoc.v:184514$12777_Y - attribute \src "libresoc.v:184515.18-184515.126" - wire $and$libresoc.v:184515$12778_Y - attribute \src "libresoc.v:184516.18-184516.117" - wire $and$libresoc.v:184516$12779_Y - attribute \src "libresoc.v:184521.18-184521.130" - wire $and$libresoc.v:184521$12784_Y - attribute \src "libresoc.v:184522.17-184522.123" - wire $and$libresoc.v:184522$12785_Y - attribute \src "libresoc.v:184523.18-184523.124" - wire width 6 $and$libresoc.v:184523$12786_Y - attribute \src "libresoc.v:184525.18-184525.116" - wire $and$libresoc.v:184525$12788_Y - attribute \src "libresoc.v:184526.18-184526.119" - wire $and$libresoc.v:184526$12789_Y - attribute \src "libresoc.v:184527.18-184527.120" - wire $and$libresoc.v:184527$12790_Y - attribute \src "libresoc.v:184528.18-184528.121" - wire $and$libresoc.v:184528$12791_Y - attribute \src "libresoc.v:184529.18-184529.121" - wire $and$libresoc.v:184529$12792_Y - attribute \src "libresoc.v:184530.18-184530.121" - wire $and$libresoc.v:184530$12793_Y - attribute \src "libresoc.v:184537.18-184537.134" - wire $and$libresoc.v:184537$12800_Y - attribute \src "libresoc.v:184511.18-184511.113" - wire $eq$libresoc.v:184511$12774_Y - attribute \src "libresoc.v:184513.18-184513.119" - wire $eq$libresoc.v:184513$12776_Y - attribute \src "libresoc.v:184472.17-184472.113" - wire width 6 $not$libresoc.v:184472$12735_Y - attribute \src "libresoc.v:184476.19-184476.115" - wire width 6 $not$libresoc.v:184476$12739_Y - attribute \src "libresoc.v:184495.18-184495.97" - wire $not$libresoc.v:184495$12758_Y - attribute \src "libresoc.v:184497.18-184497.99" - wire $not$libresoc.v:184497$12760_Y - attribute \src "libresoc.v:184500.18-184500.113" - wire width 6 $not$libresoc.v:184500$12763_Y - attribute \src "libresoc.v:184503.18-184503.106" - wire $not$libresoc.v:184503$12766_Y - attribute \src "libresoc.v:184508.18-184508.120" - wire $not$libresoc.v:184508$12771_Y - attribute \src "libresoc.v:184483.18-184483.118" - wire width 6 $or$libresoc.v:184483$12746_Y - attribute \src "libresoc.v:184507.18-184507.112" - wire $or$libresoc.v:184507$12770_Y - attribute \src "libresoc.v:184517.18-184517.122" - wire $or$libresoc.v:184517$12780_Y - attribute \src "libresoc.v:184518.18-184518.124" - wire $or$libresoc.v:184518$12781_Y - attribute \src "libresoc.v:184519.18-184519.194" - wire width 6 $or$libresoc.v:184519$12782_Y - attribute \src "libresoc.v:184520.18-184520.194" - wire width 6 $or$libresoc.v:184520$12783_Y - attribute \src "libresoc.v:184524.18-184524.120" - wire width 6 $or$libresoc.v:184524$12787_Y - attribute \src "libresoc.v:184489.17-184489.105" - wire $reduce_and$libresoc.v:184489$12752_Y - attribute \src "libresoc.v:184502.18-184502.106" - wire $reduce_or$libresoc.v:184502$12765_Y - attribute \src "libresoc.v:184505.18-184505.113" - wire $reduce_or$libresoc.v:184505$12768_Y - attribute \src "libresoc.v:184506.18-184506.112" - wire $reduce_or$libresoc.v:184506$12769_Y - attribute \src "libresoc.v:184531.18-184531.118" - wire width 64 $ternary$libresoc.v:184531$12794_Y - attribute \src "libresoc.v:184532.18-184532.118" - wire width 64 $ternary$libresoc.v:184532$12795_Y - attribute \src "libresoc.v:184533.18-184533.118" - wire width 64 $ternary$libresoc.v:184533$12796_Y - attribute \src "libresoc.v:184534.18-184534.118" - wire $ternary$libresoc.v:184534$12797_Y - attribute \src "libresoc.v:184535.18-184535.118" - wire width 2 $ternary$libresoc.v:184535$12798_Y - attribute \src "libresoc.v:184536.18-184536.118" - wire width 2 $ternary$libresoc.v:184536$12799_Y + attribute \src "libresoc.v:186911.3-186932.6" + wire width 64 $2\data_r0__o$next[63:0]$12934 + attribute \src "libresoc.v:186911.3-186932.6" + wire $2\data_r0__o_ok$next[0:0]$12935 + attribute \src "libresoc.v:186933.3-186954.6" + wire width 64 $2\data_r1__spr1$next[63:0]$12942 + attribute \src "libresoc.v:186933.3-186954.6" + wire $2\data_r1__spr1_ok$next[0:0]$12943 + attribute \src "libresoc.v:186955.3-186976.6" + wire width 64 $2\data_r2__fast1$next[63:0]$12950 + attribute \src "libresoc.v:186955.3-186976.6" + wire $2\data_r2__fast1_ok$next[0:0]$12951 + attribute \src "libresoc.v:186977.3-186998.6" + wire $2\data_r3__xer_so$next[0:0]$12958 + attribute \src "libresoc.v:186977.3-186998.6" + wire $2\data_r3__xer_so_ok$next[0:0]$12959 + attribute \src "libresoc.v:186999.3-187020.6" + wire width 2 $2\data_r4__xer_ov$next[1:0]$12966 + attribute \src "libresoc.v:186999.3-187020.6" + wire $2\data_r4__xer_ov_ok$next[0:0]$12967 + attribute \src "libresoc.v:187021.3-187042.6" + wire width 2 $2\data_r5__xer_ca$next[1:0]$12974 + attribute \src "libresoc.v:187021.3-187042.6" + wire $2\data_r5__xer_ca_ok$next[0:0]$12975 + attribute \src "libresoc.v:186911.3-186932.6" + wire $3\data_r0__o_ok$next[0:0]$12936 + attribute \src "libresoc.v:186933.3-186954.6" + wire $3\data_r1__spr1_ok$next[0:0]$12944 + attribute \src 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\src "libresoc.v:186619.18-186619.113" + wire $eq$libresoc.v:186619$12825_Y + attribute \src "libresoc.v:186621.18-186621.119" + wire $eq$libresoc.v:186621$12827_Y + attribute \src "libresoc.v:186580.17-186580.113" + wire width 6 $not$libresoc.v:186580$12786_Y + attribute \src "libresoc.v:186584.19-186584.115" + wire width 6 $not$libresoc.v:186584$12790_Y + attribute \src "libresoc.v:186603.18-186603.97" + wire $not$libresoc.v:186603$12809_Y + attribute \src "libresoc.v:186605.18-186605.99" + wire $not$libresoc.v:186605$12811_Y + attribute \src "libresoc.v:186608.18-186608.113" + wire width 6 $not$libresoc.v:186608$12814_Y + attribute \src "libresoc.v:186611.18-186611.106" + wire $not$libresoc.v:186611$12817_Y + attribute \src "libresoc.v:186616.18-186616.120" + wire $not$libresoc.v:186616$12822_Y + attribute \src "libresoc.v:186591.18-186591.118" + wire width 6 $or$libresoc.v:186591$12797_Y + attribute \src "libresoc.v:186615.18-186615.112" + wire $or$libresoc.v:186615$12821_Y + attribute \src "libresoc.v:186625.18-186625.122" + wire $or$libresoc.v:186625$12831_Y + attribute \src "libresoc.v:186626.18-186626.124" + wire $or$libresoc.v:186626$12832_Y + attribute \src "libresoc.v:186627.18-186627.194" + wire width 6 $or$libresoc.v:186627$12833_Y + attribute \src "libresoc.v:186628.18-186628.194" + wire width 6 $or$libresoc.v:186628$12834_Y + attribute \src "libresoc.v:186632.18-186632.120" + wire width 6 $or$libresoc.v:186632$12838_Y + attribute \src "libresoc.v:186597.17-186597.105" + wire $reduce_and$libresoc.v:186597$12803_Y + attribute \src "libresoc.v:186610.18-186610.106" + wire $reduce_or$libresoc.v:186610$12816_Y + attribute \src "libresoc.v:186613.18-186613.113" + wire $reduce_or$libresoc.v:186613$12819_Y + attribute \src "libresoc.v:186614.18-186614.112" + wire $reduce_or$libresoc.v:186614$12820_Y + attribute \src "libresoc.v:186639.18-186639.118" + wire width 64 $ternary$libresoc.v:186639$12845_Y + attribute \src "libresoc.v:186640.18-186640.118" + wire width 64 $ternary$libresoc.v:186640$12846_Y + attribute \src "libresoc.v:186641.18-186641.118" + wire width 64 $ternary$libresoc.v:186641$12847_Y + attribute \src "libresoc.v:186642.18-186642.118" + wire $ternary$libresoc.v:186642$12848_Y + attribute \src "libresoc.v:186643.18-186643.118" + wire width 2 $ternary$libresoc.v:186643$12849_Y + attribute \src "libresoc.v:186644.18-186644.118" + wire width 2 $ternary$libresoc.v:186644$12850_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -386296,23 +389175,24 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_spr1$1 attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_spr0_spr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_spr0_spr_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_spr0_spr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_spr0_spr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_spr0_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -386391,6 +389271,7 @@ module \spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_spr0_spr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -386419,9 +389300,9 @@ module \spr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o @@ -386507,7 +389388,7 @@ module \spr0 wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \fast1_ok - attribute \src "libresoc.v:183865.7-183865.15" + attribute \src "libresoc.v:185969.7-185969.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \o_ok @@ -386522,21 +389403,22 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_spr0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" @@ -386613,6 +389495,7 @@ module \spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -386716,7 +389599,7 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:184473$12736 + cell $and $and$libresoc.v:186581$12787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386724,10 +389607,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:184473$12736_Y + connect \Y $and$libresoc.v:186581$12787_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:184474$12737 + cell $and $and$libresoc.v:186582$12788 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -386735,10 +389618,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:184474$12737_Y + connect \Y $and$libresoc.v:186582$12788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:184475$12738 + cell $and $and$libresoc.v:186583$12789 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -386746,10 +389629,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:184475$12738_Y + connect \Y $and$libresoc.v:186583$12789_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:184477$12740 + cell $and $and$libresoc.v:186585$12791 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -386757,10 +389640,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:184477$12740_Y + connect \Y $and$libresoc.v:186585$12791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:184478$12741 + cell $and $and$libresoc.v:186586$12792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386768,10 +389651,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:184478$12741_Y + connect \Y $and$libresoc.v:186586$12792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:184479$12742 + cell $and $and$libresoc.v:186587$12793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386779,10 +389662,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:184479$12742_Y + connect \Y $and$libresoc.v:186587$12793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:184480$12743 + cell $and $and$libresoc.v:186588$12794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386790,10 +389673,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:184480$12743_Y + connect \Y $and$libresoc.v:186588$12794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:184481$12744 + cell $and $and$libresoc.v:186589$12795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386801,10 +389684,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:184481$12744_Y + connect \Y $and$libresoc.v:186589$12795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:184482$12745 + cell $and $and$libresoc.v:186590$12796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386812,10 +389695,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:184482$12745_Y + connect \Y $and$libresoc.v:186590$12796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:184484$12747 + cell $and $and$libresoc.v:186592$12798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386823,10 +389706,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:184484$12747_Y + connect \Y $and$libresoc.v:186592$12798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:184485$12748 + cell $and $and$libresoc.v:186593$12799 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -386834,10 +389717,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:184485$12748_Y + connect \Y $and$libresoc.v:186593$12799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:184486$12749 + cell $and $and$libresoc.v:186594$12800 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -386845,10 +389728,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:184486$12749_Y + connect \Y $and$libresoc.v:186594$12800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:184487$12750 + cell $and $and$libresoc.v:186595$12801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386856,10 +389739,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:184487$12750_Y + connect \Y $and$libresoc.v:186595$12801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:184488$12751 + cell $and $and$libresoc.v:186596$12802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386867,10 +389750,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:184488$12751_Y + connect \Y $and$libresoc.v:186596$12802_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:184490$12753 + cell $and $and$libresoc.v:186598$12804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386878,10 +389761,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:184490$12753_Y + connect \Y $and$libresoc.v:186598$12804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:184491$12754 + cell $and $and$libresoc.v:186599$12805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386889,10 +389772,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:184491$12754_Y + connect \Y $and$libresoc.v:186599$12805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:184492$12755 + cell $and $and$libresoc.v:186600$12806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386900,10 +389783,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:184492$12755_Y + connect \Y $and$libresoc.v:186600$12806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:184493$12756 + cell $and $and$libresoc.v:186601$12807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386911,10 +389794,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:184493$12756_Y + connect \Y $and$libresoc.v:186601$12807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:184494$12757 + cell $and $and$libresoc.v:186602$12808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386922,10 +389805,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:184494$12757_Y + connect \Y $and$libresoc.v:186602$12808_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:184496$12759 + cell $and $and$libresoc.v:186604$12810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386933,10 +389816,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:184496$12759_Y + connect \Y $and$libresoc.v:186604$12810_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:184498$12761 + cell $and $and$libresoc.v:186606$12812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386944,10 +389827,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:184498$12761_Y + connect \Y $and$libresoc.v:186606$12812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:184499$12762 + cell $and $and$libresoc.v:186607$12813 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -386955,10 +389838,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:184499$12762_Y + connect \Y $and$libresoc.v:186607$12813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:184501$12764 + cell $and $and$libresoc.v:186609$12815 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -386966,10 +389849,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:184501$12764_Y + connect \Y $and$libresoc.v:186609$12815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:184504$12767 + cell $and $and$libresoc.v:186612$12818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386977,10 +389860,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:184504$12767_Y + connect \Y $and$libresoc.v:186612$12818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:184509$12772 + cell $and $and$libresoc.v:186617$12823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386988,10 +389871,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:184509$12772_Y + connect \Y $and$libresoc.v:186617$12823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:184510$12773 + cell $and $and$libresoc.v:186618$12824 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -386999,10 +389882,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:184510$12773_Y + connect \Y $and$libresoc.v:186618$12824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:184512$12775 + cell $and $and$libresoc.v:186620$12826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387010,10 +389893,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:184512$12775_Y + connect \Y $and$libresoc.v:186620$12826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:184514$12777 + cell $and $and$libresoc.v:186622$12828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387021,10 +389904,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:184514$12777_Y + connect \Y $and$libresoc.v:186622$12828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:184515$12778 + cell $and $and$libresoc.v:186623$12829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387032,10 +389915,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:184515$12778_Y + connect \Y $and$libresoc.v:186623$12829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:184516$12779 + cell $and $and$libresoc.v:186624$12830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387043,10 +389926,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:184516$12779_Y + connect \Y $and$libresoc.v:186624$12830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:184521$12784 + cell $and $and$libresoc.v:186629$12835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387054,10 +389937,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:184521$12784_Y + connect \Y $and$libresoc.v:186629$12835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:184522$12785 + cell $and $and$libresoc.v:186630$12836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387065,10 +389948,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:184522$12785_Y + connect \Y $and$libresoc.v:186630$12836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:184523$12786 + cell $and $and$libresoc.v:186631$12837 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -387076,10 +389959,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:184523$12786_Y + connect \Y $and$libresoc.v:186631$12837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:184525$12788 + cell $and $and$libresoc.v:186633$12839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387087,10 +389970,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:184525$12788_Y + connect \Y $and$libresoc.v:186633$12839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:184526$12789 + cell $and $and$libresoc.v:186634$12840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387098,10 +389981,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:184526$12789_Y + connect \Y $and$libresoc.v:186634$12840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:184527$12790 + cell $and $and$libresoc.v:186635$12841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387109,10 +389992,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:184527$12790_Y + connect \Y $and$libresoc.v:186635$12841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:184528$12791 + cell $and $and$libresoc.v:186636$12842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387120,10 +390003,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:184528$12791_Y + connect \Y $and$libresoc.v:186636$12842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:184529$12792 + cell $and $and$libresoc.v:186637$12843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387131,10 +390014,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:184529$12792_Y + connect \Y $and$libresoc.v:186637$12843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:184530$12793 + cell $and $and$libresoc.v:186638$12844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387142,10 +390025,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:184530$12793_Y + connect \Y $and$libresoc.v:186638$12844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:184537$12800 + cell $and $and$libresoc.v:186645$12851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387153,10 +390036,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:184537$12800_Y + connect \Y $and$libresoc.v:186645$12851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:184511$12774 + cell $eq $eq$libresoc.v:186619$12825 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -387164,10 +390047,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:184511$12774_Y + connect \Y $eq$libresoc.v:186619$12825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:184513$12776 + cell $eq $eq$libresoc.v:186621$12827 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -387175,66 +390058,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:184513$12776_Y + connect \Y $eq$libresoc.v:186621$12827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:184472$12735 + cell $not $not$libresoc.v:186580$12786 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:184472$12735_Y + connect \Y $not$libresoc.v:186580$12786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:184476$12739 + cell $not $not$libresoc.v:186584$12790 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:184476$12739_Y + connect \Y $not$libresoc.v:186584$12790_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:184495$12758 + cell $not $not$libresoc.v:186603$12809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:184495$12758_Y + connect \Y $not$libresoc.v:186603$12809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:184497$12760 + cell $not $not$libresoc.v:186605$12811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:184497$12760_Y + connect \Y $not$libresoc.v:186605$12811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:184500$12763 + cell $not $not$libresoc.v:186608$12814 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:184500$12763_Y + connect \Y $not$libresoc.v:186608$12814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:184503$12766 + cell $not $not$libresoc.v:186611$12817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:184503$12766_Y + connect \Y $not$libresoc.v:186611$12817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:184508$12771 + cell $not $not$libresoc.v:186616$12822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:184508$12771_Y + connect \Y $not$libresoc.v:186616$12822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:184483$12746 + cell $or $or$libresoc.v:186591$12797 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -387242,10 +390125,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:184483$12746_Y + connect \Y $or$libresoc.v:186591$12797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:184507$12770 + cell $or $or$libresoc.v:186615$12821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387253,10 +390136,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:184507$12770_Y + connect \Y $or$libresoc.v:186615$12821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:184517$12780 + cell $or $or$libresoc.v:186625$12831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387264,10 +390147,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:184517$12780_Y + connect \Y $or$libresoc.v:186625$12831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:184518$12781 + cell $or $or$libresoc.v:186626$12832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387275,10 +390158,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:184518$12781_Y + connect \Y $or$libresoc.v:186626$12832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:184519$12782 + cell $or $or$libresoc.v:186627$12833 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -387286,10 +390169,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:184519$12782_Y + connect \Y $or$libresoc.v:186627$12833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:184520$12783 + cell $or $or$libresoc.v:186628$12834 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -387297,10 +390180,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:184520$12783_Y + connect \Y $or$libresoc.v:186628$12834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:184524$12787 + cell $or $or$libresoc.v:186632$12838 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -387308,90 +390191,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:184524$12787_Y + connect \Y $or$libresoc.v:186632$12838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:184489$12752 + cell $reduce_and $reduce_and$libresoc.v:186597$12803 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:184489$12752_Y + connect \Y $reduce_and$libresoc.v:186597$12803_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:184502$12765 + cell $reduce_or $reduce_or$libresoc.v:186610$12816 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:184502$12765_Y + connect \Y $reduce_or$libresoc.v:186610$12816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:184505$12768 + cell $reduce_or $reduce_or$libresoc.v:186613$12819 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:184505$12768_Y + connect \Y $reduce_or$libresoc.v:186613$12819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:184506$12769 + cell $reduce_or $reduce_or$libresoc.v:186614$12820 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:184506$12769_Y + connect \Y $reduce_or$libresoc.v:186614$12820_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:184531$12794 + cell $mux $ternary$libresoc.v:186639$12845 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:184531$12794_Y + connect \Y $ternary$libresoc.v:186639$12845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:184532$12795 + cell $mux $ternary$libresoc.v:186640$12846 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:184532$12795_Y + connect \Y $ternary$libresoc.v:186640$12846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:184533$12796 + cell $mux $ternary$libresoc.v:186641$12847 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:184533$12796_Y + connect \Y $ternary$libresoc.v:186641$12847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:184534$12797 + cell $mux $ternary$libresoc.v:186642$12848 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:184534$12797_Y + connect \Y $ternary$libresoc.v:186642$12848_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:184535$12798 + cell $mux $ternary$libresoc.v:186643$12849 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:184535$12798_Y + connect \Y $ternary$libresoc.v:186643$12849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:184536$12799 + cell $mux $ternary$libresoc.v:186644$12850 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:184536$12799_Y + connect \Y $ternary$libresoc.v:186644$12850_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:184612.14-184618.4" + attribute \src "libresoc.v:186720.14-186726.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -387400,7 +390283,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:184619.12-184648.4" + attribute \src "libresoc.v:186727.12-186756.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -387432,7 +390315,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:184649.15-184655.4" + attribute \src "libresoc.v:186757.15-186763.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -387441,7 +390324,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:184656.14-184662.4" + attribute \src "libresoc.v:186764.14-186770.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -387450,7 +390333,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:184663.14-184669.4" + attribute \src "libresoc.v:186771.14-186777.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -387459,7 +390342,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:184670.14-184676.4" + attribute \src "libresoc.v:186778.14-186784.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -387468,7 +390351,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:184677.14-184682.4" + attribute \src "libresoc.v:186785.14-186790.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -387476,7 +390359,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:184683.14-184689.4" + attribute \src "libresoc.v:186791.14-186797.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -387484,577 +390367,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:183865.7-183865.20" - process $proc$libresoc.v:183865$12959 + attribute \src "libresoc.v:185969.7-185969.20" + process $proc$libresoc.v:185969$13010 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184001.7-184001.24" - process $proc$libresoc.v:184001$12960 + attribute \src "libresoc.v:186105.7-186105.24" + process $proc$libresoc.v:186105$13011 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:184011.7-184011.26" - process $proc$libresoc.v:184011$12961 + attribute \src "libresoc.v:186115.7-186115.26" + process $proc$libresoc.v:186115$13012 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:184019.7-184019.25" - process $proc$libresoc.v:184019$12962 + attribute \src "libresoc.v:186123.7-186123.25" + process $proc$libresoc.v:186123$13013 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:184063.14-184063.49" - process $proc$libresoc.v:184063$12963 + attribute \src "libresoc.v:186168.14-186168.49" + process $proc$libresoc.v:186168$13014 assign { } { } - assign $1\alu_spr0_spr_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[12:0] + update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:184067.14-184067.43" - process $proc$libresoc.v:184067$12964 + attribute \src "libresoc.v:186172.14-186172.43" + process $proc$libresoc.v:186172$13015 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:184145.13-184145.47" - process $proc$libresoc.v:184145$12965 + attribute \src "libresoc.v:186251.13-186251.47" + process $proc$libresoc.v:186251$13016 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:184149.7-184149.39" - process $proc$libresoc.v:184149$12966 + attribute \src "libresoc.v:186255.7-186255.39" + process $proc$libresoc.v:186255$13017 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:184167.7-184167.27" - process $proc$libresoc.v:184167$12967 + attribute \src "libresoc.v:186273.7-186273.27" + process $proc$libresoc.v:186273$13018 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:184199.14-184199.47" - process $proc$libresoc.v:184199$12968 + attribute \src "libresoc.v:186305.14-186305.47" + process $proc$libresoc.v:186305$13019 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:184203.7-184203.27" - process $proc$libresoc.v:184203$12969 + attribute \src "libresoc.v:186309.7-186309.27" + process $proc$libresoc.v:186309$13020 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:184207.14-184207.50" - process $proc$libresoc.v:184207$12970 + attribute \src "libresoc.v:186313.14-186313.50" + process $proc$libresoc.v:186313$13021 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:184211.7-184211.30" - process $proc$libresoc.v:184211$12971 + attribute \src "libresoc.v:186317.7-186317.30" + process $proc$libresoc.v:186317$13022 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:184215.14-184215.51" - process $proc$libresoc.v:184215$12972 + attribute \src "libresoc.v:186321.14-186321.51" + process $proc$libresoc.v:186321$13023 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:184219.7-184219.31" - process $proc$libresoc.v:184219$12973 + attribute \src "libresoc.v:186325.7-186325.31" + process $proc$libresoc.v:186325$13024 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:184223.7-184223.29" - process $proc$libresoc.v:184223$12974 + attribute \src "libresoc.v:186329.7-186329.29" + process $proc$libresoc.v:186329$13025 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:184227.7-184227.32" - process $proc$libresoc.v:184227$12975 + attribute \src "libresoc.v:186333.7-186333.32" + process $proc$libresoc.v:186333$13026 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:184231.13-184231.35" - process $proc$libresoc.v:184231$12976 + attribute \src "libresoc.v:186337.13-186337.35" + process $proc$libresoc.v:186337$13027 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:184235.7-184235.32" - process $proc$libresoc.v:184235$12977 + attribute \src "libresoc.v:186341.7-186341.32" + process $proc$libresoc.v:186341$13028 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:184239.13-184239.35" - process $proc$libresoc.v:184239$12978 + attribute \src "libresoc.v:186345.13-186345.35" + process $proc$libresoc.v:186345$13029 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:184243.7-184243.32" - process $proc$libresoc.v:184243$12979 + attribute \src "libresoc.v:186349.7-186349.32" + process $proc$libresoc.v:186349$13030 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:184271.7-184271.25" - process $proc$libresoc.v:184271$12980 + attribute \src "libresoc.v:186377.7-186377.25" + process $proc$libresoc.v:186377$13031 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:184275.7-184275.25" - process $proc$libresoc.v:184275$12981 + attribute \src "libresoc.v:186381.7-186381.25" + process $proc$libresoc.v:186381$13032 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:184375.13-184375.31" - process $proc$libresoc.v:184375$12982 + attribute \src "libresoc.v:186483.13-186483.31" + process $proc$libresoc.v:186483$13033 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:184383.13-184383.32" - process $proc$libresoc.v:184383$12983 + attribute \src "libresoc.v:186491.13-186491.32" + process $proc$libresoc.v:186491$13034 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:184387.13-184387.32" - process $proc$libresoc.v:184387$12984 + attribute \src "libresoc.v:186495.13-186495.32" + process $proc$libresoc.v:186495$13035 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:184399.7-184399.26" - process $proc$libresoc.v:184399$12985 + attribute \src "libresoc.v:186507.7-186507.26" + process $proc$libresoc.v:186507$13036 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:184403.7-184403.26" - process $proc$libresoc.v:184403$12986 + attribute \src "libresoc.v:186511.7-186511.26" + process $proc$libresoc.v:186511$13037 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:184407.7-184407.25" - process $proc$libresoc.v:184407$12987 + attribute \src "libresoc.v:186515.7-186515.25" + process $proc$libresoc.v:186515$13038 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:184411.7-184411.25" - process $proc$libresoc.v:184411$12988 + attribute \src "libresoc.v:186519.7-186519.25" + process $proc$libresoc.v:186519$13039 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:184433.13-184433.32" - process $proc$libresoc.v:184433$12989 + attribute \src "libresoc.v:186541.13-186541.32" + process $proc$libresoc.v:186541$13040 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:184437.13-184437.32" - process $proc$libresoc.v:184437$12990 + attribute \src "libresoc.v:186545.13-186545.32" + process $proc$libresoc.v:186545$13041 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:184441.14-184441.43" - process $proc$libresoc.v:184441$12991 + attribute \src "libresoc.v:186549.14-186549.43" + process $proc$libresoc.v:186549$13042 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:184445.14-184445.43" - process $proc$libresoc.v:184445$12992 + attribute \src "libresoc.v:186553.14-186553.43" + process $proc$libresoc.v:186553$13043 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:184449.14-184449.43" - process $proc$libresoc.v:184449$12993 + attribute \src "libresoc.v:186557.14-186557.43" + process $proc$libresoc.v:186557$13044 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:184453.7-184453.20" - process $proc$libresoc.v:184453$12994 + attribute \src "libresoc.v:186561.7-186561.20" + process $proc$libresoc.v:186561$13045 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:184457.13-184457.26" - process $proc$libresoc.v:184457$12995 + attribute \src "libresoc.v:186565.13-186565.26" + process $proc$libresoc.v:186565$13046 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:184461.13-184461.26" - process $proc$libresoc.v:184461$12996 + attribute \src "libresoc.v:186569.13-186569.26" + process $proc$libresoc.v:186569$13047 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:184538.3-184539.39" - process $proc$libresoc.v:184538$12801 + attribute \src "libresoc.v:186646.3-186647.39" + process $proc$libresoc.v:186646$12852 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:184540.3-184541.43" - process $proc$libresoc.v:184540$12802 + attribute \src "libresoc.v:186648.3-186649.43" + process $proc$libresoc.v:186648$12853 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:184542.3-184543.29" - process $proc$libresoc.v:184542$12803 + attribute \src "libresoc.v:186650.3-186651.29" + process $proc$libresoc.v:186650$12854 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:184544.3-184545.29" - process $proc$libresoc.v:184544$12804 + attribute \src "libresoc.v:186652.3-186653.29" + process $proc$libresoc.v:186652$12855 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:184546.3-184547.29" - process $proc$libresoc.v:184546$12805 + attribute \src "libresoc.v:186654.3-186655.29" + process $proc$libresoc.v:186654$12856 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:184548.3-184549.29" - process $proc$libresoc.v:184548$12806 + attribute \src "libresoc.v:186656.3-186657.29" + process $proc$libresoc.v:186656$12857 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:184550.3-184551.29" - process $proc$libresoc.v:184550$12807 + attribute \src "libresoc.v:186658.3-186659.29" + process $proc$libresoc.v:186658$12858 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:184552.3-184553.29" - process $proc$libresoc.v:184552$12808 + attribute \src "libresoc.v:186660.3-186661.29" + process $proc$libresoc.v:186660$12859 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:184554.3-184555.47" - process $proc$libresoc.v:184554$12809 + attribute \src "libresoc.v:186662.3-186663.47" + process $proc$libresoc.v:186662$12860 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:184556.3-184557.53" - process $proc$libresoc.v:184556$12810 + attribute \src "libresoc.v:186664.3-186665.53" + process $proc$libresoc.v:186664$12861 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:184558.3-184559.47" - process $proc$libresoc.v:184558$12811 + attribute \src "libresoc.v:186666.3-186667.47" + process $proc$libresoc.v:186666$12862 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:184560.3-184561.53" - process $proc$libresoc.v:184560$12812 + attribute \src "libresoc.v:186668.3-186669.53" + process $proc$libresoc.v:186668$12863 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:184562.3-184563.47" - process $proc$libresoc.v:184562$12813 + attribute \src "libresoc.v:186670.3-186671.47" + process $proc$libresoc.v:186670$12864 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:184564.3-184565.53" - process $proc$libresoc.v:184564$12814 + attribute \src "libresoc.v:186672.3-186673.53" + process $proc$libresoc.v:186672$12865 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:184566.3-184567.45" - process $proc$libresoc.v:184566$12815 + attribute \src "libresoc.v:186674.3-186675.45" + process $proc$libresoc.v:186674$12866 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:184568.3-184569.51" - process $proc$libresoc.v:184568$12816 + attribute \src "libresoc.v:186676.3-186677.51" + process $proc$libresoc.v:186676$12867 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:184570.3-184571.43" - process $proc$libresoc.v:184570$12817 + attribute \src "libresoc.v:186678.3-186679.43" + process $proc$libresoc.v:186678$12868 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:184572.3-184573.49" - process $proc$libresoc.v:184572$12818 + attribute \src "libresoc.v:186680.3-186681.49" + process $proc$libresoc.v:186680$12869 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:184574.3-184575.37" - process $proc$libresoc.v:184574$12819 + attribute \src "libresoc.v:186682.3-186683.37" + process $proc$libresoc.v:186682$12870 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:184576.3-184577.43" - process $proc$libresoc.v:184576$12820 + attribute \src "libresoc.v:186684.3-186685.43" + process $proc$libresoc.v:186684$12871 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:184578.3-184579.69" - process $proc$libresoc.v:184578$12821 + attribute \src "libresoc.v:186686.3-186687.69" + process $proc$libresoc.v:186686$12872 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:184580.3-184581.65" - process $proc$libresoc.v:184580$12822 + attribute \src "libresoc.v:186688.3-186689.65" + process $proc$libresoc.v:186688$12873 assign { } { } - assign $0\alu_spr0_spr_op__fn_unit[12:0] \alu_spr0_spr_op__fn_unit$next + assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk - update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[12:0] + update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:184582.3-184583.59" - process $proc$libresoc.v:184582$12823 + attribute \src "libresoc.v:186690.3-186691.59" + process $proc$libresoc.v:186690$12874 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:184584.3-184585.67" - process $proc$libresoc.v:184584$12824 + attribute \src "libresoc.v:186692.3-186693.67" + process $proc$libresoc.v:186692$12875 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:184586.3-184587.39" - process $proc$libresoc.v:184586$12825 + attribute \src "libresoc.v:186694.3-186695.39" + process $proc$libresoc.v:186694$12876 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:184588.3-184589.39" - process $proc$libresoc.v:184588$12826 + attribute \src "libresoc.v:186696.3-186697.39" + process $proc$libresoc.v:186696$12877 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:184590.3-184591.39" - process $proc$libresoc.v:184590$12827 + attribute \src "libresoc.v:186698.3-186699.39" + process $proc$libresoc.v:186698$12878 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:184592.3-184593.39" - process $proc$libresoc.v:184592$12828 + attribute \src "libresoc.v:186700.3-186701.39" + process $proc$libresoc.v:186700$12879 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:184594.3-184595.39" - process $proc$libresoc.v:184594$12829 + attribute \src "libresoc.v:186702.3-186703.39" + process $proc$libresoc.v:186702$12880 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:184596.3-184597.39" - process $proc$libresoc.v:184596$12830 + attribute \src "libresoc.v:186704.3-186705.39" + process $proc$libresoc.v:186704$12881 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:184598.3-184599.39" - process $proc$libresoc.v:184598$12831 + attribute \src "libresoc.v:186706.3-186707.39" + process $proc$libresoc.v:186706$12882 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:184600.3-184601.39" - process $proc$libresoc.v:184600$12832 + attribute \src "libresoc.v:186708.3-186709.39" + process $proc$libresoc.v:186708$12883 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:184602.3-184603.41" - process $proc$libresoc.v:184602$12833 + attribute \src "libresoc.v:186710.3-186711.41" + process $proc$libresoc.v:186710$12884 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:184604.3-184605.41" - process $proc$libresoc.v:184604$12834 + attribute \src "libresoc.v:186712.3-186713.41" + process $proc$libresoc.v:186712$12885 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:184606.3-184607.37" - process $proc$libresoc.v:184606$12835 + attribute \src "libresoc.v:186714.3-186715.37" + process $proc$libresoc.v:186714$12886 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:184608.3-184609.40" - process $proc$libresoc.v:184608$12836 + attribute \src "libresoc.v:186716.3-186717.40" + process $proc$libresoc.v:186716$12887 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:184610.3-184611.25" - process $proc$libresoc.v:184610$12837 + attribute \src "libresoc.v:186718.3-186719.25" + process $proc$libresoc.v:186718$12888 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:184690.3-184699.6" - process $proc$libresoc.v:184690$12838 + attribute \src "libresoc.v:186798.3-186807.6" + process $proc$libresoc.v:186798$12889 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:184691.5-184691.29" + attribute \src "libresoc.v:186799.5-186799.29" switch \initial - attribute \src "libresoc.v:184691.9-184691.17" + attribute \src "libresoc.v:186799.9-186799.17" case 1'1 case end @@ -388070,14 +390953,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:184700.3-184708.6" - process $proc$libresoc.v:184700$12839 + attribute \src "libresoc.v:186808.3-186816.6" + process $proc$libresoc.v:186808$12890 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12840 $1\rok_l_s_rdok$next[0:0]$12841 - attribute \src "libresoc.v:184701.5-184701.29" + assign $0\rok_l_s_rdok$next[0:0]$12891 $1\rok_l_s_rdok$next[0:0]$12892 + attribute \src "libresoc.v:186809.5-186809.29" switch \initial - attribute \src "libresoc.v:184701.9-184701.17" + attribute \src "libresoc.v:186809.9-186809.17" case 1'1 case end @@ -388086,21 +390969,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12841 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12892 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12841 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12892 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12840 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12891 end - attribute \src "libresoc.v:184709.3-184717.6" - process $proc$libresoc.v:184709$12842 + attribute \src "libresoc.v:186817.3-186825.6" + process $proc$libresoc.v:186817$12893 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12843 $1\rok_l_r_rdok$next[0:0]$12844 - attribute \src "libresoc.v:184710.5-184710.29" + assign $0\rok_l_r_rdok$next[0:0]$12894 $1\rok_l_r_rdok$next[0:0]$12895 + attribute \src "libresoc.v:186818.5-186818.29" switch \initial - attribute \src "libresoc.v:184710.9-184710.17" + attribute \src "libresoc.v:186818.9-186818.17" case 1'1 case end @@ -388109,21 +390992,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12844 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12895 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12844 \$68 + assign $1\rok_l_r_rdok$next[0:0]$12895 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12843 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12894 end - attribute \src "libresoc.v:184718.3-184726.6" - process $proc$libresoc.v:184718$12845 + attribute \src "libresoc.v:186826.3-186834.6" + process $proc$libresoc.v:186826$12896 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12846 $1\rst_l_s_rst$next[0:0]$12847 - attribute \src "libresoc.v:184719.5-184719.29" + assign $0\rst_l_s_rst$next[0:0]$12897 $1\rst_l_s_rst$next[0:0]$12898 + attribute \src "libresoc.v:186827.5-186827.29" switch \initial - attribute \src "libresoc.v:184719.9-184719.17" + attribute \src "libresoc.v:186827.9-186827.17" case 1'1 case end @@ -388132,21 +391015,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12847 1'0 + assign $1\rst_l_s_rst$next[0:0]$12898 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12847 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12898 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12846 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12897 end - attribute \src "libresoc.v:184727.3-184735.6" - process $proc$libresoc.v:184727$12848 + attribute \src "libresoc.v:186835.3-186843.6" + process $proc$libresoc.v:186835$12899 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12849 $1\rst_l_r_rst$next[0:0]$12850 - attribute \src "libresoc.v:184728.5-184728.29" + assign $0\rst_l_r_rst$next[0:0]$12900 $1\rst_l_r_rst$next[0:0]$12901 + attribute \src "libresoc.v:186836.5-186836.29" switch \initial - attribute \src "libresoc.v:184728.9-184728.17" + attribute \src "libresoc.v:186836.9-186836.17" case 1'1 case end @@ -388155,21 +391038,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12850 1'1 + assign $1\rst_l_r_rst$next[0:0]$12901 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12850 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12901 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12849 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12900 end - attribute \src "libresoc.v:184736.3-184744.6" - process $proc$libresoc.v:184736$12851 + attribute \src "libresoc.v:186844.3-186852.6" + process $proc$libresoc.v:186844$12902 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12852 $1\opc_l_s_opc$next[0:0]$12853 - attribute \src "libresoc.v:184737.5-184737.29" + assign $0\opc_l_s_opc$next[0:0]$12903 $1\opc_l_s_opc$next[0:0]$12904 + attribute \src "libresoc.v:186845.5-186845.29" switch \initial - attribute \src "libresoc.v:184737.9-184737.17" + attribute \src "libresoc.v:186845.9-186845.17" case 1'1 case end @@ -388178,21 +391061,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12853 1'0 + assign $1\opc_l_s_opc$next[0:0]$12904 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12853 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12904 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12852 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12903 end - attribute \src "libresoc.v:184745.3-184753.6" - process $proc$libresoc.v:184745$12854 + attribute \src "libresoc.v:186853.3-186861.6" + process $proc$libresoc.v:186853$12905 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12855 $1\opc_l_r_opc$next[0:0]$12856 - attribute \src "libresoc.v:184746.5-184746.29" + assign $0\opc_l_r_opc$next[0:0]$12906 $1\opc_l_r_opc$next[0:0]$12907 + attribute \src "libresoc.v:186854.5-186854.29" switch \initial - attribute \src "libresoc.v:184746.9-184746.17" + attribute \src "libresoc.v:186854.9-186854.17" case 1'1 case end @@ -388201,21 +391084,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12856 1'1 + assign $1\opc_l_r_opc$next[0:0]$12907 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12856 \req_done + assign $1\opc_l_r_opc$next[0:0]$12907 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12855 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12906 end - attribute \src "libresoc.v:184754.3-184762.6" - process $proc$libresoc.v:184754$12857 + attribute \src "libresoc.v:186862.3-186870.6" + process $proc$libresoc.v:186862$12908 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$12858 $1\src_l_s_src$next[5:0]$12859 - attribute \src "libresoc.v:184755.5-184755.29" + assign $0\src_l_s_src$next[5:0]$12909 $1\src_l_s_src$next[5:0]$12910 + attribute \src "libresoc.v:186863.5-186863.29" switch \initial - attribute \src "libresoc.v:184755.9-184755.17" + attribute \src "libresoc.v:186863.9-186863.17" case 1'1 case end @@ -388224,21 +391107,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$12859 6'000000 + assign $1\src_l_s_src$next[5:0]$12910 6'000000 case - assign $1\src_l_s_src$next[5:0]$12859 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$12910 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12858 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12909 end - attribute \src "libresoc.v:184763.3-184771.6" - process $proc$libresoc.v:184763$12860 + attribute \src "libresoc.v:186871.3-186879.6" + process $proc$libresoc.v:186871$12911 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$12861 $1\src_l_r_src$next[5:0]$12862 - attribute \src "libresoc.v:184764.5-184764.29" + assign $0\src_l_r_src$next[5:0]$12912 $1\src_l_r_src$next[5:0]$12913 + attribute \src "libresoc.v:186872.5-186872.29" switch \initial - attribute \src "libresoc.v:184764.9-184764.17" + attribute \src "libresoc.v:186872.9-186872.17" case 1'1 case end @@ -388247,21 +391130,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$12862 6'111111 + assign $1\src_l_r_src$next[5:0]$12913 6'111111 case - assign $1\src_l_r_src$next[5:0]$12862 \reset_r + assign $1\src_l_r_src$next[5:0]$12913 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12861 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12912 end - attribute \src "libresoc.v:184772.3-184780.6" - process $proc$libresoc.v:184772$12863 + attribute \src "libresoc.v:186880.3-186888.6" + process $proc$libresoc.v:186880$12914 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$12864 $1\req_l_s_req$next[5:0]$12865 - attribute \src "libresoc.v:184773.5-184773.29" + assign $0\req_l_s_req$next[5:0]$12915 $1\req_l_s_req$next[5:0]$12916 + attribute \src "libresoc.v:186881.5-186881.29" switch \initial - attribute \src "libresoc.v:184773.9-184773.17" + attribute \src "libresoc.v:186881.9-186881.17" case 1'1 case end @@ -388270,21 +391153,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$12865 6'000000 + assign $1\req_l_s_req$next[5:0]$12916 6'000000 case - assign $1\req_l_s_req$next[5:0]$12865 \$70 + assign $1\req_l_s_req$next[5:0]$12916 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12864 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12915 end - attribute \src "libresoc.v:184781.3-184789.6" - process $proc$libresoc.v:184781$12866 + attribute \src "libresoc.v:186889.3-186897.6" + process $proc$libresoc.v:186889$12917 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$12867 $1\req_l_r_req$next[5:0]$12868 - attribute \src "libresoc.v:184782.5-184782.29" + assign $0\req_l_r_req$next[5:0]$12918 $1\req_l_r_req$next[5:0]$12919 + attribute \src "libresoc.v:186890.5-186890.29" switch \initial - attribute \src "libresoc.v:184782.9-184782.17" + attribute \src "libresoc.v:186890.9-186890.17" case 1'1 case end @@ -388293,15 +391176,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$12868 6'111111 + assign $1\req_l_r_req$next[5:0]$12919 6'111111 case - assign $1\req_l_r_req$next[5:0]$12868 \$72 + assign $1\req_l_r_req$next[5:0]$12919 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12867 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12918 end - attribute \src "libresoc.v:184790.3-184802.6" - process $proc$libresoc.v:184790$12869 + attribute \src "libresoc.v:186898.3-186910.6" + process $proc$libresoc.v:186898$12920 assign { } { } assign { } { } assign { } { } @@ -388310,13 +391193,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[12:0]$12870 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12874 - assign $0\alu_spr0_spr_op__insn$next[31:0]$12871 $1\alu_spr0_spr_op__insn$next[31:0]$12875 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12872 $1\alu_spr0_spr_op__insn_type$next[6:0]$12876 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12873 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12877 - attribute \src "libresoc.v:184791.5-184791.29" + assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12922 $1\alu_spr0_spr_op__insn$next[31:0]$12926 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 + attribute \src "libresoc.v:186899.5-186899.29" switch \initial - attribute \src "libresoc.v:184791.9-184791.17" + attribute \src "libresoc.v:186899.9-186899.17" case 1'1 case end @@ -388328,33 +391211,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12877 $1\alu_spr0_spr_op__insn$next[31:0]$12875 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12874 $1\alu_spr0_spr_op__insn_type$next[6:0]$12876 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 $1\alu_spr0_spr_op__insn$next[31:0]$12926 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[12:0]$12874 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$12875 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12876 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12877 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12926 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[12:0]$12870 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12871 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12872 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12873 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12922 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 end - attribute \src "libresoc.v:184803.3-184824.6" - process $proc$libresoc.v:184803$12878 + attribute \src "libresoc.v:186911.3-186932.6" + process $proc$libresoc.v:186911$12929 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12879 $2\data_r0__o$next[63:0]$12883 + assign $0\data_r0__o$next[63:0]$12930 $2\data_r0__o$next[63:0]$12934 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12880 $3\data_r0__o_ok$next[0:0]$12885 - attribute \src "libresoc.v:184804.5-184804.29" + assign $0\data_r0__o_ok$next[0:0]$12931 $3\data_r0__o_ok$next[0:0]$12936 + attribute \src "libresoc.v:186912.5-186912.29" switch \initial - attribute \src "libresoc.v:184804.9-184804.17" + attribute \src "libresoc.v:186912.9-186912.17" case 1'1 case end @@ -388364,10 +391247,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12882 $1\data_r0__o$next[63:0]$12881 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$12933 $1\data_r0__o$next[63:0]$12932 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$12881 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12882 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12932 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12933 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -388375,38 +391258,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12884 $2\data_r0__o$next[63:0]$12883 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12935 $2\data_r0__o$next[63:0]$12934 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12883 $1\data_r0__o$next[63:0]$12881 - assign $2\data_r0__o_ok$next[0:0]$12884 $1\data_r0__o_ok$next[0:0]$12882 + assign $2\data_r0__o$next[63:0]$12934 $1\data_r0__o$next[63:0]$12932 + assign $2\data_r0__o_ok$next[0:0]$12935 $1\data_r0__o_ok$next[0:0]$12933 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12885 1'0 + assign $3\data_r0__o_ok$next[0:0]$12936 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12885 $2\data_r0__o_ok$next[0:0]$12884 + assign $3\data_r0__o_ok$next[0:0]$12936 $2\data_r0__o_ok$next[0:0]$12935 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12879 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12880 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12930 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12931 end - attribute \src "libresoc.v:184825.3-184846.6" - process $proc$libresoc.v:184825$12886 + attribute \src "libresoc.v:186933.3-186954.6" + process $proc$libresoc.v:186933$12937 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$12887 $2\data_r1__spr1$next[63:0]$12891 + assign $0\data_r1__spr1$next[63:0]$12938 $2\data_r1__spr1$next[63:0]$12942 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$12888 $3\data_r1__spr1_ok$next[0:0]$12893 - attribute \src "libresoc.v:184826.5-184826.29" + assign $0\data_r1__spr1_ok$next[0:0]$12939 $3\data_r1__spr1_ok$next[0:0]$12944 + attribute \src "libresoc.v:186934.5-186934.29" switch \initial - attribute \src "libresoc.v:184826.9-184826.17" + attribute \src "libresoc.v:186934.9-186934.17" case 1'1 case end @@ -388416,10 +391299,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$12890 $1\data_r1__spr1$next[63:0]$12889 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$12941 $1\data_r1__spr1$next[63:0]$12940 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$12889 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$12890 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$12940 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12941 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -388427,38 +391310,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$12892 $2\data_r1__spr1$next[63:0]$12891 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$12943 $2\data_r1__spr1$next[63:0]$12942 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$12891 $1\data_r1__spr1$next[63:0]$12889 - assign $2\data_r1__spr1_ok$next[0:0]$12892 $1\data_r1__spr1_ok$next[0:0]$12890 + assign $2\data_r1__spr1$next[63:0]$12942 $1\data_r1__spr1$next[63:0]$12940 + assign $2\data_r1__spr1_ok$next[0:0]$12943 $1\data_r1__spr1_ok$next[0:0]$12941 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$12893 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$12944 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$12893 $2\data_r1__spr1_ok$next[0:0]$12892 + assign $3\data_r1__spr1_ok$next[0:0]$12944 $2\data_r1__spr1_ok$next[0:0]$12943 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12887 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12888 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12938 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12939 end - attribute \src "libresoc.v:184847.3-184868.6" - process $proc$libresoc.v:184847$12894 + attribute \src "libresoc.v:186955.3-186976.6" + process $proc$libresoc.v:186955$12945 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$12895 $2\data_r2__fast1$next[63:0]$12899 + assign $0\data_r2__fast1$next[63:0]$12946 $2\data_r2__fast1$next[63:0]$12950 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$12896 $3\data_r2__fast1_ok$next[0:0]$12901 - attribute \src "libresoc.v:184848.5-184848.29" + assign $0\data_r2__fast1_ok$next[0:0]$12947 $3\data_r2__fast1_ok$next[0:0]$12952 + attribute \src "libresoc.v:186956.5-186956.29" switch \initial - attribute \src "libresoc.v:184848.9-184848.17" + attribute \src "libresoc.v:186956.9-186956.17" case 1'1 case end @@ -388468,10 +391351,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$12898 $1\data_r2__fast1$next[63:0]$12897 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$12949 $1\data_r2__fast1$next[63:0]$12948 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$12897 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$12898 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$12948 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12949 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -388479,38 +391362,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$12900 $2\data_r2__fast1$next[63:0]$12899 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$12951 $2\data_r2__fast1$next[63:0]$12950 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$12899 $1\data_r2__fast1$next[63:0]$12897 - assign $2\data_r2__fast1_ok$next[0:0]$12900 $1\data_r2__fast1_ok$next[0:0]$12898 + assign $2\data_r2__fast1$next[63:0]$12950 $1\data_r2__fast1$next[63:0]$12948 + assign $2\data_r2__fast1_ok$next[0:0]$12951 $1\data_r2__fast1_ok$next[0:0]$12949 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$12901 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$12952 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$12901 $2\data_r2__fast1_ok$next[0:0]$12900 + assign $3\data_r2__fast1_ok$next[0:0]$12952 $2\data_r2__fast1_ok$next[0:0]$12951 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12895 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12896 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12946 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12947 end - attribute \src "libresoc.v:184869.3-184890.6" - process $proc$libresoc.v:184869$12902 + attribute \src "libresoc.v:186977.3-186998.6" + process $proc$libresoc.v:186977$12953 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$12903 $2\data_r3__xer_so$next[0:0]$12907 + assign $0\data_r3__xer_so$next[0:0]$12954 $2\data_r3__xer_so$next[0:0]$12958 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$12904 $3\data_r3__xer_so_ok$next[0:0]$12909 - attribute \src "libresoc.v:184870.5-184870.29" + assign $0\data_r3__xer_so_ok$next[0:0]$12955 $3\data_r3__xer_so_ok$next[0:0]$12960 + attribute \src "libresoc.v:186978.5-186978.29" switch \initial - attribute \src "libresoc.v:184870.9-184870.17" + attribute \src "libresoc.v:186978.9-186978.17" case 1'1 case end @@ -388520,10 +391403,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$12906 $1\data_r3__xer_so$next[0:0]$12905 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$12957 $1\data_r3__xer_so$next[0:0]$12956 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$12905 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$12906 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$12956 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12957 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -388531,38 +391414,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$12908 $2\data_r3__xer_so$next[0:0]$12907 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$12959 $2\data_r3__xer_so$next[0:0]$12958 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$12907 $1\data_r3__xer_so$next[0:0]$12905 - assign $2\data_r3__xer_so_ok$next[0:0]$12908 $1\data_r3__xer_so_ok$next[0:0]$12906 + assign $2\data_r3__xer_so$next[0:0]$12958 $1\data_r3__xer_so$next[0:0]$12956 + assign $2\data_r3__xer_so_ok$next[0:0]$12959 $1\data_r3__xer_so_ok$next[0:0]$12957 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$12909 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$12960 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$12909 $2\data_r3__xer_so_ok$next[0:0]$12908 + assign $3\data_r3__xer_so_ok$next[0:0]$12960 $2\data_r3__xer_so_ok$next[0:0]$12959 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12903 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12904 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12954 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12955 end - attribute \src "libresoc.v:184891.3-184912.6" - process $proc$libresoc.v:184891$12910 + attribute \src "libresoc.v:186999.3-187020.6" + process $proc$libresoc.v:186999$12961 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$12911 $2\data_r4__xer_ov$next[1:0]$12915 + assign $0\data_r4__xer_ov$next[1:0]$12962 $2\data_r4__xer_ov$next[1:0]$12966 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$12912 $3\data_r4__xer_ov_ok$next[0:0]$12917 - attribute \src "libresoc.v:184892.5-184892.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$12963 $3\data_r4__xer_ov_ok$next[0:0]$12968 + attribute \src "libresoc.v:187000.5-187000.29" switch \initial - attribute \src "libresoc.v:184892.9-184892.17" + attribute \src "libresoc.v:187000.9-187000.17" case 1'1 case end @@ -388572,10 +391455,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$12914 $1\data_r4__xer_ov$next[1:0]$12913 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$12965 $1\data_r4__xer_ov$next[1:0]$12964 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$12913 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$12914 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$12964 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$12965 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -388583,38 +391466,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$12916 $2\data_r4__xer_ov$next[1:0]$12915 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$12967 $2\data_r4__xer_ov$next[1:0]$12966 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$12915 $1\data_r4__xer_ov$next[1:0]$12913 - assign $2\data_r4__xer_ov_ok$next[0:0]$12916 $1\data_r4__xer_ov_ok$next[0:0]$12914 + assign $2\data_r4__xer_ov$next[1:0]$12966 $1\data_r4__xer_ov$next[1:0]$12964 + assign $2\data_r4__xer_ov_ok$next[0:0]$12967 $1\data_r4__xer_ov_ok$next[0:0]$12965 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$12917 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$12968 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$12917 $2\data_r4__xer_ov_ok$next[0:0]$12916 + assign $3\data_r4__xer_ov_ok$next[0:0]$12968 $2\data_r4__xer_ov_ok$next[0:0]$12967 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12911 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12912 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12962 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12963 end - attribute \src "libresoc.v:184913.3-184934.6" - process $proc$libresoc.v:184913$12918 + attribute \src "libresoc.v:187021.3-187042.6" + process $proc$libresoc.v:187021$12969 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$12919 $2\data_r5__xer_ca$next[1:0]$12923 + assign $0\data_r5__xer_ca$next[1:0]$12970 $2\data_r5__xer_ca$next[1:0]$12974 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$12920 $3\data_r5__xer_ca_ok$next[0:0]$12925 - attribute \src "libresoc.v:184914.5-184914.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$12971 $3\data_r5__xer_ca_ok$next[0:0]$12976 + attribute \src "libresoc.v:187022.5-187022.29" switch \initial - attribute \src "libresoc.v:184914.9-184914.17" + attribute \src "libresoc.v:187022.9-187022.17" case 1'1 case end @@ -388624,10 +391507,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$12922 $1\data_r5__xer_ca$next[1:0]$12921 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$12973 $1\data_r5__xer_ca$next[1:0]$12972 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$12921 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$12922 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$12972 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$12973 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -388635,32 +391518,32 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$12924 $2\data_r5__xer_ca$next[1:0]$12923 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$12975 $2\data_r5__xer_ca$next[1:0]$12974 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$12923 $1\data_r5__xer_ca$next[1:0]$12921 - assign $2\data_r5__xer_ca_ok$next[0:0]$12924 $1\data_r5__xer_ca_ok$next[0:0]$12922 + assign $2\data_r5__xer_ca$next[1:0]$12974 $1\data_r5__xer_ca$next[1:0]$12972 + assign $2\data_r5__xer_ca_ok$next[0:0]$12975 $1\data_r5__xer_ca_ok$next[0:0]$12973 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$12925 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$12976 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$12925 $2\data_r5__xer_ca_ok$next[0:0]$12924 + assign $3\data_r5__xer_ca_ok$next[0:0]$12976 $2\data_r5__xer_ca_ok$next[0:0]$12975 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12919 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12920 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12970 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12971 end - attribute \src "libresoc.v:184935.3-184944.6" - process $proc$libresoc.v:184935$12926 + attribute \src "libresoc.v:187043.3-187052.6" + process $proc$libresoc.v:187043$12977 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12927 $1\src_r0$next[63:0]$12928 - attribute \src "libresoc.v:184936.5-184936.29" + assign $0\src_r0$next[63:0]$12978 $1\src_r0$next[63:0]$12979 + attribute \src "libresoc.v:187044.5-187044.29" switch \initial - attribute \src "libresoc.v:184936.9-184936.17" + attribute \src "libresoc.v:187044.9-187044.17" case 1'1 case end @@ -388669,21 +391552,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12928 \src1_i + assign $1\src_r0$next[63:0]$12979 \src1_i case - assign $1\src_r0$next[63:0]$12928 \src_r0 + assign $1\src_r0$next[63:0]$12979 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12927 + update \src_r0$next $0\src_r0$next[63:0]$12978 end - attribute \src "libresoc.v:184945.3-184954.6" - process $proc$libresoc.v:184945$12929 + attribute \src "libresoc.v:187053.3-187062.6" + process $proc$libresoc.v:187053$12980 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12930 $1\src_r1$next[63:0]$12931 - attribute \src "libresoc.v:184946.5-184946.29" + assign $0\src_r1$next[63:0]$12981 $1\src_r1$next[63:0]$12982 + attribute \src "libresoc.v:187054.5-187054.29" switch \initial - attribute \src "libresoc.v:184946.9-184946.17" + attribute \src "libresoc.v:187054.9-187054.17" case 1'1 case end @@ -388692,21 +391575,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12931 \src2_i + assign $1\src_r1$next[63:0]$12982 \src2_i case - assign $1\src_r1$next[63:0]$12931 \src_r1 + assign $1\src_r1$next[63:0]$12982 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12930 + update \src_r1$next $0\src_r1$next[63:0]$12981 end - attribute \src "libresoc.v:184955.3-184964.6" - process $proc$libresoc.v:184955$12932 + attribute \src "libresoc.v:187063.3-187072.6" + process $proc$libresoc.v:187063$12983 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12933 $1\src_r2$next[63:0]$12934 - attribute \src "libresoc.v:184956.5-184956.29" + assign $0\src_r2$next[63:0]$12984 $1\src_r2$next[63:0]$12985 + attribute \src "libresoc.v:187064.5-187064.29" switch \initial - attribute \src "libresoc.v:184956.9-184956.17" + attribute \src "libresoc.v:187064.9-187064.17" case 1'1 case end @@ -388715,21 +391598,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12934 \src3_i + assign $1\src_r2$next[63:0]$12985 \src3_i case - assign $1\src_r2$next[63:0]$12934 \src_r2 + assign $1\src_r2$next[63:0]$12985 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12933 + update \src_r2$next $0\src_r2$next[63:0]$12984 end - attribute \src "libresoc.v:184965.3-184974.6" - process $proc$libresoc.v:184965$12935 + attribute \src "libresoc.v:187073.3-187082.6" + process $proc$libresoc.v:187073$12986 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12936 $1\src_r3$next[0:0]$12937 - attribute \src "libresoc.v:184966.5-184966.29" + assign $0\src_r3$next[0:0]$12987 $1\src_r3$next[0:0]$12988 + attribute \src "libresoc.v:187074.5-187074.29" switch \initial - attribute \src "libresoc.v:184966.9-184966.17" + attribute \src "libresoc.v:187074.9-187074.17" case 1'1 case end @@ -388738,21 +391621,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12937 \src4_i + assign $1\src_r3$next[0:0]$12988 \src4_i case - assign $1\src_r3$next[0:0]$12937 \src_r3 + assign $1\src_r3$next[0:0]$12988 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12936 + update \src_r3$next $0\src_r3$next[0:0]$12987 end - attribute \src "libresoc.v:184975.3-184984.6" - process $proc$libresoc.v:184975$12938 + attribute \src "libresoc.v:187083.3-187092.6" + process $proc$libresoc.v:187083$12989 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12939 $1\src_r4$next[1:0]$12940 - attribute \src "libresoc.v:184976.5-184976.29" + assign $0\src_r4$next[1:0]$12990 $1\src_r4$next[1:0]$12991 + attribute \src "libresoc.v:187084.5-187084.29" switch \initial - attribute \src "libresoc.v:184976.9-184976.17" + attribute \src "libresoc.v:187084.9-187084.17" case 1'1 case end @@ -388761,21 +391644,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12940 \src5_i + assign $1\src_r4$next[1:0]$12991 \src5_i case - assign $1\src_r4$next[1:0]$12940 \src_r4 + assign $1\src_r4$next[1:0]$12991 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12939 + update \src_r4$next $0\src_r4$next[1:0]$12990 end - attribute \src "libresoc.v:184985.3-184994.6" - process $proc$libresoc.v:184985$12941 + attribute \src "libresoc.v:187093.3-187102.6" + process $proc$libresoc.v:187093$12992 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$12942 $1\src_r5$next[1:0]$12943 - attribute \src "libresoc.v:184986.5-184986.29" + assign $0\src_r5$next[1:0]$12993 $1\src_r5$next[1:0]$12994 + attribute \src "libresoc.v:187094.5-187094.29" switch \initial - attribute \src "libresoc.v:184986.9-184986.17" + attribute \src "libresoc.v:187094.9-187094.17" case 1'1 case end @@ -388784,21 +391667,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$12943 \src6_i + assign $1\src_r5$next[1:0]$12994 \src6_i case - assign $1\src_r5$next[1:0]$12943 \src_r5 + assign $1\src_r5$next[1:0]$12994 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$12942 + update \src_r5$next $0\src_r5$next[1:0]$12993 end - attribute \src "libresoc.v:184995.3-185003.6" - process $proc$libresoc.v:184995$12944 + attribute \src "libresoc.v:187103.3-187111.6" + process $proc$libresoc.v:187103$12995 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12945 $1\alui_l_r_alui$next[0:0]$12946 - attribute \src "libresoc.v:184996.5-184996.29" + assign $0\alui_l_r_alui$next[0:0]$12996 $1\alui_l_r_alui$next[0:0]$12997 + attribute \src "libresoc.v:187104.5-187104.29" switch \initial - attribute \src "libresoc.v:184996.9-184996.17" + attribute \src "libresoc.v:187104.9-187104.17" case 1'1 case end @@ -388807,21 +391690,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12946 1'1 + assign $1\alui_l_r_alui$next[0:0]$12997 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12946 \$98 + assign $1\alui_l_r_alui$next[0:0]$12997 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12945 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12996 end - attribute \src "libresoc.v:185004.3-185012.6" - process $proc$libresoc.v:185004$12947 + attribute \src "libresoc.v:187112.3-187120.6" + process $proc$libresoc.v:187112$12998 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12948 $1\alu_l_r_alu$next[0:0]$12949 - attribute \src "libresoc.v:185005.5-185005.29" + assign $0\alu_l_r_alu$next[0:0]$12999 $1\alu_l_r_alu$next[0:0]$13000 + attribute \src "libresoc.v:187113.5-187113.29" switch \initial - attribute \src "libresoc.v:185005.9-185005.17" + attribute \src "libresoc.v:187113.9-187113.17" case 1'1 case end @@ -388830,21 +391713,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12949 1'1 + assign $1\alu_l_r_alu$next[0:0]$13000 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12949 \$100 + assign $1\alu_l_r_alu$next[0:0]$13000 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12948 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12999 end - attribute \src "libresoc.v:185013.3-185022.6" - process $proc$libresoc.v:185013$12950 + attribute \src "libresoc.v:187121.3-187130.6" + process $proc$libresoc.v:187121$13001 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:185014.5-185014.29" + attribute \src "libresoc.v:187122.5-187122.29" switch \initial - attribute \src "libresoc.v:185014.9-185014.17" + attribute \src "libresoc.v:187122.9-187122.17" case 1'1 case end @@ -388860,14 +391743,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:185023.3-185032.6" - process $proc$libresoc.v:185023$12951 + attribute \src "libresoc.v:187131.3-187140.6" + process $proc$libresoc.v:187131$13002 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:185024.5-185024.29" + attribute \src "libresoc.v:187132.5-187132.29" switch \initial - attribute \src "libresoc.v:185024.9-185024.17" + attribute \src "libresoc.v:187132.9-187132.17" case 1'1 case end @@ -388883,14 +391766,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:185033.3-185042.6" - process $proc$libresoc.v:185033$12952 + attribute \src "libresoc.v:187141.3-187150.6" + process $proc$libresoc.v:187141$13003 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:185034.5-185034.29" + attribute \src "libresoc.v:187142.5-187142.29" switch \initial - attribute \src "libresoc.v:185034.9-185034.17" + attribute \src "libresoc.v:187142.9-187142.17" case 1'1 case end @@ -388906,14 +391789,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:185043.3-185052.6" - process $proc$libresoc.v:185043$12953 + attribute \src "libresoc.v:187151.3-187160.6" + process $proc$libresoc.v:187151$13004 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:185044.5-185044.29" + attribute \src "libresoc.v:187152.5-187152.29" switch \initial - attribute \src "libresoc.v:185044.9-185044.17" + attribute \src "libresoc.v:187152.9-187152.17" case 1'1 case end @@ -388929,14 +391812,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:185053.3-185062.6" - process $proc$libresoc.v:185053$12954 + attribute \src "libresoc.v:187161.3-187170.6" + process $proc$libresoc.v:187161$13005 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:185054.5-185054.29" + attribute \src "libresoc.v:187162.5-187162.29" switch \initial - attribute \src "libresoc.v:185054.9-185054.17" + attribute \src "libresoc.v:187162.9-187162.17" case 1'1 case end @@ -388952,14 +391835,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:185063.3-185072.6" - process $proc$libresoc.v:185063$12955 + attribute \src "libresoc.v:187171.3-187180.6" + process $proc$libresoc.v:187171$13006 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:185064.5-185064.29" + attribute \src "libresoc.v:187172.5-187172.29" switch \initial - attribute \src "libresoc.v:185064.9-185064.17" + attribute \src "libresoc.v:187172.9-187172.17" case 1'1 case end @@ -388975,14 +391858,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:185073.3-185081.6" - process $proc$libresoc.v:185073$12956 + attribute \src "libresoc.v:187181.3-187189.6" + process $proc$libresoc.v:187181$13007 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$12957 $1\prev_wr_go$next[5:0]$12958 - attribute \src "libresoc.v:185074.5-185074.29" + assign $0\prev_wr_go$next[5:0]$13008 $1\prev_wr_go$next[5:0]$13009 + attribute \src "libresoc.v:187182.5-187182.29" switch \initial - attribute \src "libresoc.v:185074.9-185074.17" + attribute \src "libresoc.v:187182.9-187182.17" case 1'1 case end @@ -388991,79 +391874,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$12958 6'000000 - case - assign $1\prev_wr_go$next[5:0]$12958 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12957 - end - connect \$9 $not$libresoc.v:184472$12735_Y - connect \$100 $and$libresoc.v:184473$12736_Y - connect \$102 $and$libresoc.v:184474$12737_Y - connect \$104 $and$libresoc.v:184475$12738_Y - connect \$106 $not$libresoc.v:184476$12739_Y - connect \$108 $and$libresoc.v:184477$12740_Y - connect \$110 $and$libresoc.v:184478$12741_Y - connect \$112 $and$libresoc.v:184479$12742_Y - connect \$114 $and$libresoc.v:184480$12743_Y - connect \$116 $and$libresoc.v:184481$12744_Y - connect \$118 $and$libresoc.v:184482$12745_Y - connect \$11 $or$libresoc.v:184483$12746_Y - connect \$120 $and$libresoc.v:184484$12747_Y - connect \$122 $and$libresoc.v:184485$12748_Y - connect \$124 $and$libresoc.v:184486$12749_Y - connect \$126 $and$libresoc.v:184487$12750_Y - connect \$128 $and$libresoc.v:184488$12751_Y - connect \$8 $reduce_and$libresoc.v:184489$12752_Y - connect \$130 $and$libresoc.v:184490$12753_Y - connect \$132 $and$libresoc.v:184491$12754_Y - connect \$134 $and$libresoc.v:184492$12755_Y - connect \$136 $and$libresoc.v:184493$12756_Y - connect \$14 $and$libresoc.v:184494$12757_Y - connect \$16 $not$libresoc.v:184495$12758_Y - connect \$18 $and$libresoc.v:184496$12759_Y - connect \$20 $not$libresoc.v:184497$12760_Y - connect \$22 $and$libresoc.v:184498$12761_Y - connect \$24 $and$libresoc.v:184499$12762_Y - connect \$28 $not$libresoc.v:184500$12763_Y - connect \$30 $and$libresoc.v:184501$12764_Y - connect \$27 $reduce_or$libresoc.v:184502$12765_Y - connect \$26 $not$libresoc.v:184503$12766_Y - connect \$34 $and$libresoc.v:184504$12767_Y - connect \$36 $reduce_or$libresoc.v:184505$12768_Y - connect \$38 $reduce_or$libresoc.v:184506$12769_Y - connect \$40 $or$libresoc.v:184507$12770_Y - connect \$42 $not$libresoc.v:184508$12771_Y - connect \$44 $and$libresoc.v:184509$12772_Y - connect \$46 $and$libresoc.v:184510$12773_Y - connect \$48 $eq$libresoc.v:184511$12774_Y - connect \$50 $and$libresoc.v:184512$12775_Y - connect \$52 $eq$libresoc.v:184513$12776_Y - connect \$54 $and$libresoc.v:184514$12777_Y - connect \$56 $and$libresoc.v:184515$12778_Y - connect \$58 $and$libresoc.v:184516$12779_Y - connect \$60 $or$libresoc.v:184517$12780_Y - connect \$62 $or$libresoc.v:184518$12781_Y - connect \$64 $or$libresoc.v:184519$12782_Y - connect \$66 $or$libresoc.v:184520$12783_Y - connect \$68 $and$libresoc.v:184521$12784_Y - connect \$6 $and$libresoc.v:184522$12785_Y - connect \$70 $and$libresoc.v:184523$12786_Y - connect \$72 $or$libresoc.v:184524$12787_Y - connect \$74 $and$libresoc.v:184525$12788_Y - connect \$76 $and$libresoc.v:184526$12789_Y - connect \$78 $and$libresoc.v:184527$12790_Y - connect \$80 $and$libresoc.v:184528$12791_Y - connect \$82 $and$libresoc.v:184529$12792_Y - connect \$84 $and$libresoc.v:184530$12793_Y - connect \$86 $ternary$libresoc.v:184531$12794_Y - connect \$88 $ternary$libresoc.v:184532$12795_Y - connect \$90 $ternary$libresoc.v:184533$12796_Y - connect \$92 $ternary$libresoc.v:184534$12797_Y - connect \$94 $ternary$libresoc.v:184535$12798_Y - connect \$96 $ternary$libresoc.v:184536$12799_Y - connect \$98 $and$libresoc.v:184537$12800_Y + assign $1\prev_wr_go$next[5:0]$13009 6'000000 + case + assign $1\prev_wr_go$next[5:0]$13009 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13008 + end + connect \$9 $not$libresoc.v:186580$12786_Y + connect \$100 $and$libresoc.v:186581$12787_Y + connect \$102 $and$libresoc.v:186582$12788_Y + connect \$104 $and$libresoc.v:186583$12789_Y + connect \$106 $not$libresoc.v:186584$12790_Y + connect \$108 $and$libresoc.v:186585$12791_Y + connect \$110 $and$libresoc.v:186586$12792_Y + connect \$112 $and$libresoc.v:186587$12793_Y + connect \$114 $and$libresoc.v:186588$12794_Y + connect \$116 $and$libresoc.v:186589$12795_Y + connect \$118 $and$libresoc.v:186590$12796_Y + connect \$11 $or$libresoc.v:186591$12797_Y + connect \$120 $and$libresoc.v:186592$12798_Y + connect \$122 $and$libresoc.v:186593$12799_Y + connect \$124 $and$libresoc.v:186594$12800_Y + connect \$126 $and$libresoc.v:186595$12801_Y + connect \$128 $and$libresoc.v:186596$12802_Y + connect \$8 $reduce_and$libresoc.v:186597$12803_Y + connect \$130 $and$libresoc.v:186598$12804_Y + connect \$132 $and$libresoc.v:186599$12805_Y + connect \$134 $and$libresoc.v:186600$12806_Y + connect \$136 $and$libresoc.v:186601$12807_Y + connect \$14 $and$libresoc.v:186602$12808_Y + connect \$16 $not$libresoc.v:186603$12809_Y + connect \$18 $and$libresoc.v:186604$12810_Y + connect \$20 $not$libresoc.v:186605$12811_Y + connect \$22 $and$libresoc.v:186606$12812_Y + connect \$24 $and$libresoc.v:186607$12813_Y + connect \$28 $not$libresoc.v:186608$12814_Y + connect \$30 $and$libresoc.v:186609$12815_Y + connect \$27 $reduce_or$libresoc.v:186610$12816_Y + connect \$26 $not$libresoc.v:186611$12817_Y + connect \$34 $and$libresoc.v:186612$12818_Y + connect \$36 $reduce_or$libresoc.v:186613$12819_Y + connect \$38 $reduce_or$libresoc.v:186614$12820_Y + connect \$40 $or$libresoc.v:186615$12821_Y + connect \$42 $not$libresoc.v:186616$12822_Y + connect \$44 $and$libresoc.v:186617$12823_Y + connect \$46 $and$libresoc.v:186618$12824_Y + connect \$48 $eq$libresoc.v:186619$12825_Y + connect \$50 $and$libresoc.v:186620$12826_Y + connect \$52 $eq$libresoc.v:186621$12827_Y + connect \$54 $and$libresoc.v:186622$12828_Y + connect \$56 $and$libresoc.v:186623$12829_Y + connect \$58 $and$libresoc.v:186624$12830_Y + connect \$60 $or$libresoc.v:186625$12831_Y + connect \$62 $or$libresoc.v:186626$12832_Y + connect \$64 $or$libresoc.v:186627$12833_Y + connect \$66 $or$libresoc.v:186628$12834_Y + connect \$68 $and$libresoc.v:186629$12835_Y + connect \$6 $and$libresoc.v:186630$12836_Y + connect \$70 $and$libresoc.v:186631$12837_Y + connect \$72 $or$libresoc.v:186632$12838_Y + connect \$74 $and$libresoc.v:186633$12839_Y + connect \$76 $and$libresoc.v:186634$12840_Y + connect \$78 $and$libresoc.v:186635$12841_Y + connect \$80 $and$libresoc.v:186636$12842_Y + connect \$82 $and$libresoc.v:186637$12843_Y + connect \$84 $and$libresoc.v:186638$12844_Y + connect \$86 $ternary$libresoc.v:186639$12845_Y + connect \$88 $ternary$libresoc.v:186640$12846_Y + connect \$90 $ternary$libresoc.v:186641$12847_Y + connect \$92 $ternary$libresoc.v:186642$12848_Y + connect \$94 $ternary$libresoc.v:186643$12849_Y + connect \$96 $ternary$libresoc.v:186644$12850_Y + connect \$98 $and$libresoc.v:186645$12851_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -389096,111 +391979,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:185117.1-185633.10" +attribute \src "libresoc.v:187225.1-187745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:185386.3-185401.6" - wire width 64 $0\fast1$7[63:0]$13005 - attribute \src "libresoc.v:185463.3-185478.6" + attribute \src "libresoc.v:187498.3-187513.6" + wire width 64 $0\fast1$7[63:0]$13056 + attribute \src "libresoc.v:187575.3-187590.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:185118.7-185118.20" + attribute \src "libresoc.v:187226.7-187226.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185421.3-185462.6" + attribute \src "libresoc.v:187533.3-187574.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:185421.3-185462.6" + attribute \src "libresoc.v:187533.3-187574.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:185611.3-185629.6" - wire width 64 $0\spr1$6[63:0]$13030 - attribute \src "libresoc.v:185402.3-185420.6" + attribute \src "libresoc.v:187723.3-187741.6" + wire width 64 $0\spr1$6[63:0]$13081 + attribute \src "libresoc.v:187514.3-187532.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:185566.3-185589.6" - wire width 2 $0\xer_ca$10[1:0]$13024 - attribute \src "libresoc.v:185590.3-185610.6" + attribute \src "libresoc.v:187678.3-187701.6" + wire width 2 $0\xer_ca$10[1:0]$13075 + attribute \src "libresoc.v:187702.3-187722.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:185521.3-185544.6" - wire width 2 $0\xer_ov$9[1:0]$13018 - attribute \src "libresoc.v:185545.3-185565.6" + attribute \src "libresoc.v:187633.3-187656.6" + wire width 2 $0\xer_ov$9[1:0]$13069 + attribute \src "libresoc.v:187657.3-187677.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:185479.3-185499.6" - wire $0\xer_so$8[0:0]$13012 - attribute \src "libresoc.v:185500.3-185520.6" + attribute \src "libresoc.v:187591.3-187611.6" + wire $0\xer_so$8[0:0]$13063 + attribute \src "libresoc.v:187612.3-187632.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:185386.3-185401.6" - wire width 64 $1\fast1$7[63:0]$13006 - attribute \src "libresoc.v:185463.3-185478.6" + attribute \src "libresoc.v:187498.3-187513.6" + wire width 64 $1\fast1$7[63:0]$13057 + attribute \src "libresoc.v:187575.3-187590.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:185421.3-185462.6" + attribute \src "libresoc.v:187533.3-187574.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:185421.3-185462.6" + attribute \src "libresoc.v:187533.3-187574.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:185611.3-185629.6" - wire width 64 $1\spr1$6[63:0]$13031 - attribute \src "libresoc.v:185402.3-185420.6" + attribute \src "libresoc.v:187723.3-187741.6" + wire width 64 $1\spr1$6[63:0]$13082 + attribute \src "libresoc.v:187514.3-187532.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:185566.3-185589.6" - wire width 2 $1\xer_ca$10[1:0]$13025 - attribute \src "libresoc.v:185590.3-185610.6" + attribute \src "libresoc.v:187678.3-187701.6" + wire width 2 $1\xer_ca$10[1:0]$13076 + attribute \src "libresoc.v:187702.3-187722.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:185521.3-185544.6" - wire width 2 $1\xer_ov$9[1:0]$13019 - attribute \src "libresoc.v:185545.3-185565.6" + attribute \src "libresoc.v:187633.3-187656.6" + wire width 2 $1\xer_ov$9[1:0]$13070 + attribute \src "libresoc.v:187657.3-187677.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:185479.3-185499.6" - wire $1\xer_so$8[0:0]$13013 - attribute \src "libresoc.v:185500.3-185520.6" + attribute \src "libresoc.v:187591.3-187611.6" + wire $1\xer_so$8[0:0]$13064 + attribute \src "libresoc.v:187612.3-187632.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:185386.3-185401.6" - wire width 64 $2\fast1$7[63:0]$13007 - attribute \src "libresoc.v:185463.3-185478.6" + attribute \src "libresoc.v:187498.3-187513.6" + wire width 64 $2\fast1$7[63:0]$13058 + attribute \src "libresoc.v:187575.3-187590.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:185421.3-185462.6" + attribute \src "libresoc.v:187533.3-187574.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:185611.3-185629.6" - wire width 64 $2\spr1$6[63:0]$13032 - attribute \src "libresoc.v:185402.3-185420.6" + attribute \src "libresoc.v:187723.3-187741.6" + wire width 64 $2\spr1$6[63:0]$13083 + attribute \src "libresoc.v:187514.3-187532.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:185566.3-185589.6" - wire width 2 $2\xer_ca$10[1:0]$13026 - attribute \src "libresoc.v:185590.3-185610.6" + attribute \src "libresoc.v:187678.3-187701.6" + wire width 2 $2\xer_ca$10[1:0]$13077 + attribute \src "libresoc.v:187702.3-187722.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:185521.3-185544.6" - wire width 2 $2\xer_ov$9[1:0]$13020 - attribute \src "libresoc.v:185545.3-185565.6" + attribute \src "libresoc.v:187633.3-187656.6" + wire width 2 $2\xer_ov$9[1:0]$13071 + attribute \src "libresoc.v:187657.3-187677.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:185479.3-185499.6" - wire $2\xer_so$8[0:0]$13014 - attribute \src "libresoc.v:185500.3-185520.6" + attribute \src "libresoc.v:187591.3-187611.6" + wire $2\xer_so$8[0:0]$13065 + attribute \src "libresoc.v:187612.3-187632.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:185421.3-185462.6" + attribute \src "libresoc.v:187533.3-187574.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:185566.3-185589.6" - wire width 2 $3\xer_ca$10[1:0]$13027 - attribute \src "libresoc.v:185590.3-185610.6" + attribute \src "libresoc.v:187678.3-187701.6" + wire width 2 $3\xer_ca$10[1:0]$13078 + attribute \src "libresoc.v:187702.3-187722.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:185521.3-185544.6" - wire width 2 $3\xer_ov$9[1:0]$13021 - attribute \src "libresoc.v:185545.3-185565.6" + attribute \src "libresoc.v:187633.3-187656.6" + wire width 2 $3\xer_ov$9[1:0]$13072 + attribute \src "libresoc.v:187657.3-187677.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:185479.3-185499.6" - wire $3\xer_so$8[0:0]$13015 - attribute \src "libresoc.v:185500.3-185520.6" + attribute \src "libresoc.v:187591.3-187611.6" + wire $3\xer_so$8[0:0]$13066 + attribute \src "libresoc.v:187612.3-187632.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:185379.18-185379.106" - wire $eq$libresoc.v:185379$12997_Y - attribute \src "libresoc.v:185380.18-185380.106" - wire $eq$libresoc.v:185380$12998_Y - attribute \src "libresoc.v:185381.18-185381.106" - wire $eq$libresoc.v:185381$12999_Y - attribute \src "libresoc.v:185382.18-185382.106" - wire $eq$libresoc.v:185382$13000_Y - attribute \src "libresoc.v:185383.18-185383.106" - wire $eq$libresoc.v:185383$13001_Y - attribute \src "libresoc.v:185384.18-185384.106" - wire $eq$libresoc.v:185384$13002_Y - attribute \src "libresoc.v:185385.18-185385.106" - wire $eq$libresoc.v:185385$13003_Y + attribute \src "libresoc.v:187491.18-187491.106" + wire $eq$libresoc.v:187491$13048_Y + attribute \src "libresoc.v:187492.18-187492.106" + wire $eq$libresoc.v:187492$13049_Y + attribute \src "libresoc.v:187493.18-187493.106" + wire $eq$libresoc.v:187493$13050_Y + attribute \src "libresoc.v:187494.18-187494.106" + wire $eq$libresoc.v:187494$13051_Y + attribute \src "libresoc.v:187495.18-187495.106" + wire $eq$libresoc.v:187495$13052_Y + attribute \src "libresoc.v:187496.18-187496.106" + wire $eq$libresoc.v:187496$13053_Y + attribute \src "libresoc.v:187497.18-187497.106" + wire $eq$libresoc.v:187497$13054_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" @@ -389221,7 +392104,7 @@ module \spr_main wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast1_ok - attribute \src "libresoc.v:185118.7-185118.15" + attribute \src "libresoc.v:187226.7-187226.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid @@ -389242,37 +392125,39 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 19 \spr1_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \spr_op__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 2 \spr_op__fn_unit attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 13 \spr_op__fn_unit$3 + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 output 13 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -389351,6 +392236,7 @@ module \spr_main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \spr_op__insn_type attribute \enum_base_type "MicrOp" @@ -389427,6 +392313,7 @@ module \spr_main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 12 \spr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -389452,7 +392339,7 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:185379$12997 + cell $eq $eq$libresoc.v:187491$13048 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389460,10 +392347,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:185379$12997_Y + connect \Y $eq$libresoc.v:187491$13048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:185380$12998 + cell $eq $eq$libresoc.v:187492$13049 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389471,10 +392358,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:185380$12998_Y + connect \Y $eq$libresoc.v:187492$13049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:185381$12999 + cell $eq $eq$libresoc.v:187493$13050 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389482,10 +392369,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:185381$12999_Y + connect \Y $eq$libresoc.v:187493$13050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:185382$13000 + cell $eq $eq$libresoc.v:187494$13051 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389493,10 +392380,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:185382$13000_Y + connect \Y $eq$libresoc.v:187494$13051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:185383$13001 + cell $eq $eq$libresoc.v:187495$13052 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389504,10 +392391,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:185383$13001_Y + connect \Y $eq$libresoc.v:187495$13052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:185384$13002 + cell $eq $eq$libresoc.v:187496$13053 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389515,10 +392402,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:185384$13002_Y + connect \Y $eq$libresoc.v:187496$13053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:185385$13003 + cell $eq $eq$libresoc.v:187497$13054 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389526,24 +392413,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:185385$13003_Y + connect \Y $eq$libresoc.v:187497$13054_Y end - attribute \src "libresoc.v:185118.7-185118.20" - process $proc$libresoc.v:185118$13033 + attribute \src "libresoc.v:187226.7-187226.20" + process $proc$libresoc.v:187226$13084 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185386.3-185401.6" - process $proc$libresoc.v:185386$13004 + attribute \src "libresoc.v:187498.3-187513.6" + process $proc$libresoc.v:187498$13055 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$13005 $1\fast1$7[63:0]$13006 - attribute \src "libresoc.v:185387.5-185387.29" + assign $0\fast1$7[63:0]$13056 $1\fast1$7[63:0]$13057 + attribute \src "libresoc.v:187499.5-187499.29" switch \initial - attribute \src "libresoc.v:185387.9-185387.17" + attribute \src "libresoc.v:187499.9-187499.17" case 1'1 case end @@ -389552,30 +392439,30 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$13006 $2\fast1$7[63:0]$13007 + assign $1\fast1$7[63:0]$13057 $2\fast1$7[63:0]$13058 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$13007 \ra + assign $2\fast1$7[63:0]$13058 \ra case - assign $2\fast1$7[63:0]$13007 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$13058 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$13006 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$13057 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$13005 + update \fast1$7 $0\fast1$7[63:0]$13056 end - attribute \src "libresoc.v:185402.3-185420.6" - process $proc$libresoc.v:185402$13008 + attribute \src "libresoc.v:187514.3-187532.6" + process $proc$libresoc.v:187514$13059 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:185403.5-185403.29" + attribute \src "libresoc.v:187515.5-187515.29" switch \initial - attribute \src "libresoc.v:185403.9-185403.17" + attribute \src "libresoc.v:187515.9-187515.17" case 1'1 case end @@ -389601,17 +392488,17 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:185421.3-185462.6" - process $proc$libresoc.v:185421$13009 + attribute \src "libresoc.v:187533.3-187574.6" + process $proc$libresoc.v:187533$13060 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:185422.5-185422.29" + attribute \src "libresoc.v:187534.5-187534.29" switch \initial - attribute \src "libresoc.v:185422.9-185422.17" + attribute \src "libresoc.v:187534.9-187534.17" case 1'1 case end @@ -389662,14 +392549,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:185463.3-185478.6" - process $proc$libresoc.v:185463$13010 + attribute \src "libresoc.v:187575.3-187590.6" + process $proc$libresoc.v:187575$13061 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:185464.5-185464.29" + attribute \src "libresoc.v:187576.5-187576.29" switch \initial - attribute \src "libresoc.v:185464.9-185464.17" + attribute \src "libresoc.v:187576.9-187576.17" case 1'1 case end @@ -389694,14 +392581,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:185479.3-185499.6" - process $proc$libresoc.v:185479$13011 + attribute \src "libresoc.v:187591.3-187611.6" + process $proc$libresoc.v:187591$13062 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$13012 $1\xer_so$8[0:0]$13013 - attribute \src "libresoc.v:185480.5-185480.29" + assign $0\xer_so$8[0:0]$13063 $1\xer_so$8[0:0]$13064 + attribute \src "libresoc.v:187592.5-187592.29" switch \initial - attribute \src "libresoc.v:185480.9-185480.17" + attribute \src "libresoc.v:187592.9-187592.17" case 1'1 case end @@ -389710,39 +392597,39 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$13013 $2\xer_so$8[0:0]$13014 + assign $1\xer_so$8[0:0]$13064 $2\xer_so$8[0:0]$13065 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$13014 $3\xer_so$8[0:0]$13015 + assign $2\xer_so$8[0:0]$13065 $3\xer_so$8[0:0]$13066 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$13015 \ra [31] + assign $3\xer_so$8[0:0]$13066 \ra [31] case - assign $3\xer_so$8[0:0]$13015 1'0 + assign $3\xer_so$8[0:0]$13066 1'0 end case - assign $2\xer_so$8[0:0]$13014 1'0 + assign $2\xer_so$8[0:0]$13065 1'0 end case - assign $1\xer_so$8[0:0]$13013 1'0 + assign $1\xer_so$8[0:0]$13064 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$13012 + update \xer_so$8 $0\xer_so$8[0:0]$13063 end - attribute \src "libresoc.v:185500.3-185520.6" - process $proc$libresoc.v:185500$13016 + attribute \src "libresoc.v:187612.3-187632.6" + process $proc$libresoc.v:187612$13067 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:185501.5-185501.29" + attribute \src "libresoc.v:187613.5-187613.29" switch \initial - attribute \src "libresoc.v:185501.9-185501.17" + attribute \src "libresoc.v:187613.9-187613.17" case 1'1 case end @@ -389776,14 +392663,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:185521.3-185544.6" - process $proc$libresoc.v:185521$13017 + attribute \src "libresoc.v:187633.3-187656.6" + process $proc$libresoc.v:187633$13068 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$13018 $1\xer_ov$9[1:0]$13019 - attribute \src "libresoc.v:185522.5-185522.29" + assign $0\xer_ov$9[1:0]$13069 $1\xer_ov$9[1:0]$13070 + attribute \src "libresoc.v:187634.5-187634.29" switch \initial - attribute \src "libresoc.v:185522.9-185522.17" + attribute \src "libresoc.v:187634.9-187634.17" case 1'1 case end @@ -389792,40 +392679,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$13019 $2\xer_ov$9[1:0]$13020 + assign $1\xer_ov$9[1:0]$13070 $2\xer_ov$9[1:0]$13071 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$13020 $3\xer_ov$9[1:0]$13021 + assign $2\xer_ov$9[1:0]$13071 $3\xer_ov$9[1:0]$13072 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$13021 [0] \ra [30] - assign $3\xer_ov$9[1:0]$13021 [1] \ra [19] + assign $3\xer_ov$9[1:0]$13072 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13072 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$13021 2'00 + assign $3\xer_ov$9[1:0]$13072 2'00 end case - assign $2\xer_ov$9[1:0]$13020 2'00 + assign $2\xer_ov$9[1:0]$13071 2'00 end case - assign $1\xer_ov$9[1:0]$13019 2'00 + assign $1\xer_ov$9[1:0]$13070 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$13018 + update \xer_ov$9 $0\xer_ov$9[1:0]$13069 end - attribute \src "libresoc.v:185545.3-185565.6" - process $proc$libresoc.v:185545$13022 + attribute \src "libresoc.v:187657.3-187677.6" + process $proc$libresoc.v:187657$13073 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:185546.5-185546.29" + attribute \src "libresoc.v:187658.5-187658.29" switch \initial - attribute \src "libresoc.v:185546.9-185546.17" + attribute \src "libresoc.v:187658.9-187658.17" case 1'1 case end @@ -389859,14 +392746,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:185566.3-185589.6" - process $proc$libresoc.v:185566$13023 + attribute \src "libresoc.v:187678.3-187701.6" + process $proc$libresoc.v:187678$13074 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$13024 $1\xer_ca$10[1:0]$13025 - attribute \src "libresoc.v:185567.5-185567.29" + assign $0\xer_ca$10[1:0]$13075 $1\xer_ca$10[1:0]$13076 + attribute \src "libresoc.v:187679.5-187679.29" switch \initial - attribute \src "libresoc.v:185567.9-185567.17" + attribute \src "libresoc.v:187679.9-187679.17" case 1'1 case end @@ -389875,40 +392762,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$13025 $2\xer_ca$10[1:0]$13026 + assign $1\xer_ca$10[1:0]$13076 $2\xer_ca$10[1:0]$13077 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$13026 $3\xer_ca$10[1:0]$13027 + assign $2\xer_ca$10[1:0]$13077 $3\xer_ca$10[1:0]$13078 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$13027 [0] \ra [29] - assign $3\xer_ca$10[1:0]$13027 [1] \ra [18] + assign $3\xer_ca$10[1:0]$13078 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13078 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$13027 2'00 + assign $3\xer_ca$10[1:0]$13078 2'00 end case - assign $2\xer_ca$10[1:0]$13026 2'00 + assign $2\xer_ca$10[1:0]$13077 2'00 end case - assign $1\xer_ca$10[1:0]$13025 2'00 + assign $1\xer_ca$10[1:0]$13076 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$13024 + update \xer_ca$10 $0\xer_ca$10[1:0]$13075 end - attribute \src "libresoc.v:185590.3-185610.6" - process $proc$libresoc.v:185590$13028 + attribute \src "libresoc.v:187702.3-187722.6" + process $proc$libresoc.v:187702$13079 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:185591.5-185591.29" + attribute \src "libresoc.v:187703.5-187703.29" switch \initial - attribute \src "libresoc.v:185591.9-185591.17" + attribute \src "libresoc.v:187703.9-187703.17" case 1'1 case end @@ -389942,14 +392829,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:185611.3-185629.6" - process $proc$libresoc.v:185611$13029 + attribute \src "libresoc.v:187723.3-187741.6" + process $proc$libresoc.v:187723$13080 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$13030 $1\spr1$6[63:0]$13031 - attribute \src "libresoc.v:185612.5-185612.29" + assign $0\spr1$6[63:0]$13081 $1\spr1$6[63:0]$13082 + attribute \src "libresoc.v:187724.5-187724.29" switch \initial - attribute \src "libresoc.v:185612.9-185612.17" + attribute \src "libresoc.v:187724.9-187724.17" case 1'1 case end @@ -389958,62 +392845,62 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$13031 $2\spr1$6[63:0]$13032 + assign $1\spr1$6[63:0]$13082 $2\spr1$6[63:0]$13083 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$13032 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$13083 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$13032 \ra + assign $2\spr1$6[63:0]$13083 \ra end case - assign $1\spr1$6[63:0]$13031 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$13082 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$13030 + update \spr1$6 $0\spr1$6[63:0]$13081 end - connect \$11 $eq$libresoc.v:185379$12997_Y - connect \$13 $eq$libresoc.v:185380$12998_Y - connect \$15 $eq$libresoc.v:185381$12999_Y - connect \$17 $eq$libresoc.v:185382$13000_Y - connect \$19 $eq$libresoc.v:185383$13001_Y - connect \$21 $eq$libresoc.v:185384$13002_Y - connect \$23 $eq$libresoc.v:185385$13003_Y + connect \$11 $eq$libresoc.v:187491$13048_Y + connect \$13 $eq$libresoc.v:187492$13049_Y + connect \$15 $eq$libresoc.v:187493$13050_Y + connect \$17 $eq$libresoc.v:187494$13051_Y + connect \$19 $eq$libresoc.v:187495$13052_Y + connect \$21 $eq$libresoc.v:187496$13053_Y + connect \$23 $eq$libresoc.v:187497$13054_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:185637.1-186473.10" +attribute \src "libresoc.v:187749.1-188585.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:185767.3-185797.6" + attribute \src "libresoc.v:187879.3-187909.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:185798.3-185828.6" + attribute \src "libresoc.v:187910.3-187940.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:185638.7-185638.20" + attribute \src "libresoc.v:187750.7-187750.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185829.3-186150.6" + attribute \src "libresoc.v:187941.3-188262.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:186151.3-186472.6" + attribute \src "libresoc.v:188263.3-188584.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:185767.3-185797.6" + attribute \src "libresoc.v:187879.3-187909.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:185798.3-185828.6" + attribute \src "libresoc.v:187910.3-187940.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:185829.3-186150.6" + attribute \src "libresoc.v:187941.3-188262.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:186151.3-186472.6" + attribute \src "libresoc.v:188263.3-188584.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:185638.7-185638.15" + attribute \src "libresoc.v:187750.7-187750.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" wire width 10 input 5 \spr_i @@ -390135,22 +393022,22 @@ module \sprmap wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:185638.7-185638.20" - process $proc$libresoc.v:185638$13038 + attribute \src "libresoc.v:187750.7-187750.20" + process $proc$libresoc.v:187750$13089 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185767.3-185797.6" - process $proc$libresoc.v:185767$13034 + attribute \src "libresoc.v:187879.3-187909.6" + process $proc$libresoc.v:187879$13085 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:185768.5-185768.29" + attribute \src "libresoc.v:187880.5-187880.29" switch \initial - attribute \src "libresoc.v:185768.9-185768.17" + attribute \src "libresoc.v:187880.9-187880.17" case 1'1 case end @@ -390194,14 +393081,14 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:185798.3-185828.6" - process $proc$libresoc.v:185798$13035 + attribute \src "libresoc.v:187910.3-187940.6" + process $proc$libresoc.v:187910$13086 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:185799.5-185799.29" + attribute \src "libresoc.v:187911.5-187911.29" switch \initial - attribute \src "libresoc.v:185799.9-185799.17" + attribute \src "libresoc.v:187911.9-187911.17" case 1'1 case end @@ -390245,14 +393132,14 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:185829.3-186150.6" - process $proc$libresoc.v:185829$13036 + attribute \src "libresoc.v:187941.3-188262.6" + process $proc$libresoc.v:187941$13087 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:185830.5-185830.29" + attribute \src "libresoc.v:187942.5-187942.29" switch \initial - attribute \src "libresoc.v:185830.9-185830.17" + attribute \src "libresoc.v:187942.9-187942.17" case 1'1 case end @@ -390684,14 +393571,14 @@ module \sprmap sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:186151.3-186472.6" - process $proc$libresoc.v:186151$13037 + attribute \src "libresoc.v:188263.3-188584.6" + process $proc$libresoc.v:188263$13088 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:186152.5-186152.29" + attribute \src "libresoc.v:188264.5-188264.29" switch \initial - attribute \src "libresoc.v:186152.9-186152.17" + attribute \src "libresoc.v:188264.9-188264.17" case 1'1 case end @@ -391124,34 +394011,34 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:186477.1-187313.10" +attribute \src "libresoc.v:188589.1-189425.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" module \sprmap$174 - attribute \src "libresoc.v:186607.3-186637.6" + attribute \src "libresoc.v:188719.3-188749.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:186638.3-186668.6" + attribute \src "libresoc.v:188750.3-188780.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:186478.7-186478.20" + attribute \src "libresoc.v:188590.7-188590.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186669.3-186990.6" + attribute \src "libresoc.v:188781.3-189102.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:186991.3-187312.6" + attribute \src "libresoc.v:189103.3-189424.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:186607.3-186637.6" + attribute \src "libresoc.v:188719.3-188749.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:186638.3-186668.6" + attribute \src "libresoc.v:188750.3-188780.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:186669.3-186990.6" + attribute \src "libresoc.v:188781.3-189102.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:186991.3-187312.6" + attribute \src "libresoc.v:189103.3-189424.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:186478.7-186478.15" + attribute \src "libresoc.v:188590.7-188590.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" wire width 10 input 5 \spr_i @@ -391273,22 +394160,22 @@ module \sprmap$174 wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:186478.7-186478.20" - process $proc$libresoc.v:186478$13043 + attribute \src "libresoc.v:188590.7-188590.20" + process $proc$libresoc.v:188590$13094 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186607.3-186637.6" - process $proc$libresoc.v:186607$13039 + attribute \src "libresoc.v:188719.3-188749.6" + process $proc$libresoc.v:188719$13090 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:186608.5-186608.29" + attribute \src "libresoc.v:188720.5-188720.29" switch \initial - attribute \src "libresoc.v:186608.9-186608.17" + attribute \src "libresoc.v:188720.9-188720.17" case 1'1 case end @@ -391332,14 +394219,14 @@ module \sprmap$174 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:186638.3-186668.6" - process $proc$libresoc.v:186638$13040 + attribute \src "libresoc.v:188750.3-188780.6" + process $proc$libresoc.v:188750$13091 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:186639.5-186639.29" + attribute \src "libresoc.v:188751.5-188751.29" switch \initial - attribute \src "libresoc.v:186639.9-186639.17" + attribute \src "libresoc.v:188751.9-188751.17" case 1'1 case end @@ -391383,14 +394270,14 @@ module \sprmap$174 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:186669.3-186990.6" - process $proc$libresoc.v:186669$13041 + attribute \src "libresoc.v:188781.3-189102.6" + process $proc$libresoc.v:188781$13092 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:186670.5-186670.29" + attribute \src "libresoc.v:188782.5-188782.29" switch \initial - attribute \src "libresoc.v:186670.9-186670.17" + attribute \src "libresoc.v:188782.9-188782.17" case 1'1 case end @@ -391822,14 +394709,14 @@ module \sprmap$174 sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:186991.3-187312.6" - process $proc$libresoc.v:186991$13042 + attribute \src "libresoc.v:189103.3-189424.6" + process $proc$libresoc.v:189103$13093 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:186992.5-186992.29" + attribute \src "libresoc.v:189104.5-189104.29" switch \initial - attribute \src "libresoc.v:186992.9-186992.17" + attribute \src "libresoc.v:189104.9-189104.17" case 1'1 case end @@ -392262,37 +395149,1337 @@ module \sprmap$174 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:187317.1-187375.10" +attribute \src "libresoc.v:189429.1-189569.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" +attribute \generator "nMigen" +module \sram4k_0 + attribute \src "libresoc.v:189504.3-189518.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:189534.3-189548.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:189430.7-189430.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189489.3-189503.6" + wire $0\sram4k_0_wb__ack$next[0:0]$13099 + attribute \src "libresoc.v:189470.3-189471.49" + wire $0\sram4k_0_wb__ack[0:0] + attribute \src "libresoc.v:189519.3-189533.6" + wire width 64 $0\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189479.3-189488.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189549.3-189568.6" + wire $0\we[0:0] + attribute \src "libresoc.v:189504.3-189518.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:189534.3-189548.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:189489.3-189503.6" + wire $1\sram4k_0_wb__ack$next[0:0]$13100 + attribute \src "libresoc.v:189447.7-189447.30" + wire $1\sram4k_0_wb__ack[0:0] + attribute \src "libresoc.v:189519.3-189533.6" + wire width 64 $1\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189479.3-189488.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189549.3-189568.6" + wire $1\we[0:0] + attribute \src "libresoc.v:189504.3-189518.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189534.3-189548.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189489.3-189503.6" + wire $2\sram4k_0_wb__ack$next[0:0]$13101 + attribute \src "libresoc.v:189519.3-189533.6" + wire width 64 $2\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189549.3-189568.6" + wire $2\we[0:0] + attribute \src "libresoc.v:189549.3-189568.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189469.17-189469.129" + wire $and$libresoc.v:189469$13095_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189430.7-189430.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_0_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:189469$13095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_0_wb__cyc + connect \B \sram4k_0_wb__stb + connect \Y $and$libresoc.v:189469$13095_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189472.21-189478.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:189430.7-189430.20" + process $proc$libresoc.v:189430$13106 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189447.7-189447.30" + process $proc$libresoc.v:189447$13107 + assign { } { } + assign $1\sram4k_0_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0] + end + attribute \src "libresoc.v:189470.3-189471.49" + process $proc$libresoc.v:189470$13096 + assign { } { } + assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next + sync posedge \clk + update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0] + end + attribute \src "libresoc.v:189479.3-189488.6" + process $proc$libresoc.v:189479$13097 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189480.5-189480.29" + switch \initial + attribute \src "libresoc.v:189480.9-189480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:189489.3-189503.6" + process $proc$libresoc.v:189489$13098 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_0_wb__ack$next[0:0]$13099 $2\sram4k_0_wb__ack$next[0:0]$13101 + attribute \src "libresoc.v:189490.5-189490.29" + switch \initial + attribute \src "libresoc.v:189490.9-189490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_0_wb__ack$next[0:0]$13100 \wb_active + case + assign $1\sram4k_0_wb__ack$next[0:0]$13100 \sram4k_0_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_0_wb__ack$next[0:0]$13101 1'0 + case + assign $2\sram4k_0_wb__ack$next[0:0]$13101 $1\sram4k_0_wb__ack$next[0:0]$13100 + end + sync always + update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13099 + end + attribute \src "libresoc.v:189504.3-189518.6" + process $proc$libresoc.v:189504$13102 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189505.5-189505.29" + switch \initial + attribute \src "libresoc.v:189505.9-189505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_0_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:189519.3-189533.6" + process $proc$libresoc.v:189519$13103 + assign { } { } + assign { } { } + assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189520.5-189520.29" + switch \initial + attribute \src "libresoc.v:189520.9-189520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_0_wb__dat_r[63:0] $2\sram4k_0_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_0_wb__dat_r[63:0] \q + case + assign $2\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0] + end + attribute \src "libresoc.v:189534.3-189548.6" + process $proc$libresoc.v:189534$13104 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189535.5-189535.29" + switch \initial + attribute \src "libresoc.v:189535.9-189535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_0_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189549.3-189568.6" + process $proc$libresoc.v:189549$13105 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189550.5-189550.29" + switch \initial + attribute \src "libresoc.v:189550.9-189550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_0_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_0_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:189469$13095_Y +end +attribute \src "libresoc.v:189573.1-189713.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" +attribute \generator "nMigen" +module \sram4k_1 + attribute \src "libresoc.v:189648.3-189662.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:189678.3-189692.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:189574.7-189574.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189633.3-189647.6" + wire $0\sram4k_1_wb__ack$next[0:0]$13112 + attribute \src "libresoc.v:189614.3-189615.49" + wire $0\sram4k_1_wb__ack[0:0] + attribute \src "libresoc.v:189663.3-189677.6" + wire width 64 $0\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189623.3-189632.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189693.3-189712.6" + wire $0\we[0:0] + attribute \src "libresoc.v:189648.3-189662.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:189678.3-189692.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:189633.3-189647.6" + wire $1\sram4k_1_wb__ack$next[0:0]$13113 + attribute \src "libresoc.v:189591.7-189591.30" + wire $1\sram4k_1_wb__ack[0:0] + attribute \src "libresoc.v:189663.3-189677.6" + wire width 64 $1\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189623.3-189632.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189693.3-189712.6" + wire $1\we[0:0] + attribute \src "libresoc.v:189648.3-189662.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189678.3-189692.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189633.3-189647.6" + wire $2\sram4k_1_wb__ack$next[0:0]$13114 + attribute \src "libresoc.v:189663.3-189677.6" + wire width 64 $2\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189693.3-189712.6" + wire $2\we[0:0] + attribute \src "libresoc.v:189693.3-189712.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189613.17-189613.129" + wire $and$libresoc.v:189613$13108_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189574.7-189574.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_1_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:189613$13108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_1_wb__cyc + connect \B \sram4k_1_wb__stb + connect \Y $and$libresoc.v:189613$13108_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189616.21-189622.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:189574.7-189574.20" + process $proc$libresoc.v:189574$13119 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189591.7-189591.30" + process $proc$libresoc.v:189591$13120 + assign { } { } + assign $1\sram4k_1_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0] + end + attribute \src "libresoc.v:189614.3-189615.49" + process $proc$libresoc.v:189614$13109 + assign { } { } + assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next + sync posedge \clk + update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0] + end + attribute \src "libresoc.v:189623.3-189632.6" + process $proc$libresoc.v:189623$13110 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189624.5-189624.29" + switch \initial + attribute \src "libresoc.v:189624.9-189624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:189633.3-189647.6" + process $proc$libresoc.v:189633$13111 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_1_wb__ack$next[0:0]$13112 $2\sram4k_1_wb__ack$next[0:0]$13114 + attribute \src "libresoc.v:189634.5-189634.29" + switch \initial + attribute \src "libresoc.v:189634.9-189634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_1_wb__ack$next[0:0]$13113 \wb_active + case + assign $1\sram4k_1_wb__ack$next[0:0]$13113 \sram4k_1_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_1_wb__ack$next[0:0]$13114 1'0 + case + assign $2\sram4k_1_wb__ack$next[0:0]$13114 $1\sram4k_1_wb__ack$next[0:0]$13113 + end + sync always + update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13112 + end + attribute \src "libresoc.v:189648.3-189662.6" + process $proc$libresoc.v:189648$13115 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189649.5-189649.29" + switch \initial + attribute \src "libresoc.v:189649.9-189649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_1_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:189663.3-189677.6" + process $proc$libresoc.v:189663$13116 + assign { } { } + assign { } { } + assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189664.5-189664.29" + switch \initial + attribute \src "libresoc.v:189664.9-189664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_1_wb__dat_r[63:0] $2\sram4k_1_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_1_wb__dat_r[63:0] \q + case + assign $2\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0] + end + attribute \src "libresoc.v:189678.3-189692.6" + process $proc$libresoc.v:189678$13117 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189679.5-189679.29" + switch \initial + attribute \src "libresoc.v:189679.9-189679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_1_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189693.3-189712.6" + process $proc$libresoc.v:189693$13118 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189694.5-189694.29" + switch \initial + attribute \src "libresoc.v:189694.9-189694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_1_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_1_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:189613$13108_Y +end +attribute \src "libresoc.v:189717.1-189857.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" +attribute \generator "nMigen" +module \sram4k_2 + attribute \src "libresoc.v:189792.3-189806.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:189822.3-189836.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:189718.7-189718.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189777.3-189791.6" + wire $0\sram4k_2_wb__ack$next[0:0]$13125 + attribute \src "libresoc.v:189758.3-189759.49" + wire $0\sram4k_2_wb__ack[0:0] + attribute \src "libresoc.v:189807.3-189821.6" + wire width 64 $0\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189767.3-189776.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189837.3-189856.6" + wire $0\we[0:0] + attribute \src "libresoc.v:189792.3-189806.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:189822.3-189836.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:189777.3-189791.6" + wire $1\sram4k_2_wb__ack$next[0:0]$13126 + attribute \src "libresoc.v:189735.7-189735.30" + wire $1\sram4k_2_wb__ack[0:0] + attribute \src "libresoc.v:189807.3-189821.6" + wire width 64 $1\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189767.3-189776.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189837.3-189856.6" + wire $1\we[0:0] + attribute \src "libresoc.v:189792.3-189806.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189822.3-189836.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189777.3-189791.6" + wire $2\sram4k_2_wb__ack$next[0:0]$13127 + attribute \src "libresoc.v:189807.3-189821.6" + wire width 64 $2\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189837.3-189856.6" + wire $2\we[0:0] + attribute \src "libresoc.v:189837.3-189856.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189757.17-189757.129" + wire $and$libresoc.v:189757$13121_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189718.7-189718.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_2_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:189757$13121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_2_wb__cyc + connect \B \sram4k_2_wb__stb + connect \Y $and$libresoc.v:189757$13121_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189760.21-189766.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:189718.7-189718.20" + process $proc$libresoc.v:189718$13132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189735.7-189735.30" + process $proc$libresoc.v:189735$13133 + assign { } { } + assign $1\sram4k_2_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0] + end + attribute \src "libresoc.v:189758.3-189759.49" + process $proc$libresoc.v:189758$13122 + assign { } { } + assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next + sync posedge \clk + update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0] + end + attribute \src "libresoc.v:189767.3-189776.6" + process $proc$libresoc.v:189767$13123 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189768.5-189768.29" + switch \initial + attribute \src "libresoc.v:189768.9-189768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:189777.3-189791.6" + process $proc$libresoc.v:189777$13124 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_2_wb__ack$next[0:0]$13125 $2\sram4k_2_wb__ack$next[0:0]$13127 + attribute \src "libresoc.v:189778.5-189778.29" + switch \initial + attribute \src "libresoc.v:189778.9-189778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_2_wb__ack$next[0:0]$13126 \wb_active + case + assign $1\sram4k_2_wb__ack$next[0:0]$13126 \sram4k_2_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_2_wb__ack$next[0:0]$13127 1'0 + case + assign $2\sram4k_2_wb__ack$next[0:0]$13127 $1\sram4k_2_wb__ack$next[0:0]$13126 + end + sync always + update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13125 + end + attribute \src "libresoc.v:189792.3-189806.6" + process $proc$libresoc.v:189792$13128 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189793.5-189793.29" + switch \initial + attribute \src "libresoc.v:189793.9-189793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_2_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:189807.3-189821.6" + process $proc$libresoc.v:189807$13129 + assign { } { } + assign { } { } + assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189808.5-189808.29" + switch \initial + attribute \src "libresoc.v:189808.9-189808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_2_wb__dat_r[63:0] $2\sram4k_2_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_2_wb__dat_r[63:0] \q + case + assign $2\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0] + end + attribute \src "libresoc.v:189822.3-189836.6" + process $proc$libresoc.v:189822$13130 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189823.5-189823.29" + switch \initial + attribute \src "libresoc.v:189823.9-189823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_2_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189837.3-189856.6" + process $proc$libresoc.v:189837$13131 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189838.5-189838.29" + switch \initial + attribute \src "libresoc.v:189838.9-189838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_2_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_2_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:189757$13121_Y +end +attribute \src "libresoc.v:189861.1-190001.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" +attribute \generator "nMigen" +module \sram4k_3 + attribute \src "libresoc.v:189936.3-189950.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:189966.3-189980.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:189862.7-189862.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189921.3-189935.6" + wire $0\sram4k_3_wb__ack$next[0:0]$13138 + attribute \src "libresoc.v:189902.3-189903.49" + wire $0\sram4k_3_wb__ack[0:0] + attribute \src "libresoc.v:189951.3-189965.6" + wire width 64 $0\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:189911.3-189920.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189981.3-190000.6" + wire $0\we[0:0] + attribute \src "libresoc.v:189936.3-189950.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:189966.3-189980.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:189921.3-189935.6" + wire $1\sram4k_3_wb__ack$next[0:0]$13139 + attribute \src "libresoc.v:189879.7-189879.30" + wire $1\sram4k_3_wb__ack[0:0] + attribute \src "libresoc.v:189951.3-189965.6" + wire width 64 $1\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:189911.3-189920.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189981.3-190000.6" + wire $1\we[0:0] + attribute \src "libresoc.v:189936.3-189950.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189966.3-189980.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189921.3-189935.6" + wire $2\sram4k_3_wb__ack$next[0:0]$13140 + attribute \src "libresoc.v:189951.3-189965.6" + wire width 64 $2\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:189981.3-190000.6" + wire $2\we[0:0] + attribute \src "libresoc.v:189981.3-190000.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189901.17-189901.129" + wire $and$libresoc.v:189901$13134_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" + wire width 64 \d + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189862.7-189862.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_3_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" + cell $and $and$libresoc.v:189901$13134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_3_wb__cyc + connect \B \sram4k_3_wb__stb + connect \Y $and$libresoc.v:189901$13134_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189904.21-189910.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:189862.7-189862.20" + process $proc$libresoc.v:189862$13145 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189879.7-189879.30" + process $proc$libresoc.v:189879$13146 + assign { } { } + assign $1\sram4k_3_wb__ack[0:0] 1'0 + sync always + sync init + update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0] + end + attribute \src "libresoc.v:189902.3-189903.49" + process $proc$libresoc.v:189902$13135 + assign { } { } + assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next + sync posedge \clk + update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0] + end + attribute \src "libresoc.v:189911.3-189920.6" + process $proc$libresoc.v:189911$13136 + assign { } { } + assign { } { } + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189912.5-189912.29" + switch \initial + attribute \src "libresoc.v:189912.9-189912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wb_active[0:0] \$1 + case + assign $1\wb_active[0:0] 1'0 + end + sync always + update \wb_active $0\wb_active[0:0] + end + attribute \src "libresoc.v:189921.3-189935.6" + process $proc$libresoc.v:189921$13137 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_3_wb__ack$next[0:0]$13138 $2\sram4k_3_wb__ack$next[0:0]$13140 + attribute \src "libresoc.v:189922.5-189922.29" + switch \initial + attribute \src "libresoc.v:189922.9-189922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_3_wb__ack$next[0:0]$13139 \wb_active + case + assign $1\sram4k_3_wb__ack$next[0:0]$13139 \sram4k_3_wb__ack + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_3_wb__ack$next[0:0]$13140 1'0 + case + assign $2\sram4k_3_wb__ack$next[0:0]$13140 $1\sram4k_3_wb__ack$next[0:0]$13139 + end + sync always + update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13138 + end + attribute \src "libresoc.v:189936.3-189950.6" + process $proc$libresoc.v:189936$13141 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189937.5-189937.29" + switch \initial + attribute \src "libresoc.v:189937.9-189937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_3_wb__adr + case + assign $2\a[8:0] 9'000000000 + end + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:189951.3-189965.6" + process $proc$libresoc.v:189951$13142 + assign { } { } + assign { } { } + assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:189952.5-189952.29" + switch \initial + attribute \src "libresoc.v:189952.9-189952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_3_wb__dat_r[63:0] $2\sram4k_3_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_3_wb__dat_r[63:0] \q + case + assign $2\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0] + end + attribute \src "libresoc.v:189966.3-189980.6" + process $proc$libresoc.v:189966$13143 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189967.5-189967.29" + switch \initial + attribute \src "libresoc.v:189967.9-189967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_3_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189981.3-190000.6" + process $proc$libresoc.v:189981$13144 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189982.5-189982.29" + switch \initial + attribute \src "libresoc.v:189982.9-189982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" + switch \enable + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" + switch \sram4k_3_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_3_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + connect \$1 $and$libresoc.v:189901$13134_Y +end +attribute \src "libresoc.v:190005.1-190063.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:187318.7-187318.20" + attribute \src "libresoc.v:190006.7-190006.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187363.3-187371.6" - wire width 4 $0\q_int$next[3:0]$13054 - attribute \src "libresoc.v:187361.3-187362.27" + attribute \src "libresoc.v:190051.3-190059.6" + wire width 4 $0\q_int$next[3:0]$13157 + attribute \src "libresoc.v:190049.3-190050.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:187363.3-187371.6" - wire width 4 $1\q_int$next[3:0]$13055 - attribute \src "libresoc.v:187340.13-187340.25" + attribute \src "libresoc.v:190051.3-190059.6" + wire width 4 $1\q_int$next[3:0]$13158 + attribute \src "libresoc.v:190028.13-190028.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:187353.17-187353.96" - wire width 4 $and$libresoc.v:187353$13044_Y - attribute \src "libresoc.v:187358.17-187358.96" - wire width 4 $and$libresoc.v:187358$13049_Y - attribute \src "libresoc.v:187355.18-187355.93" - wire width 4 $not$libresoc.v:187355$13046_Y - attribute \src "libresoc.v:187357.17-187357.92" - wire width 4 $not$libresoc.v:187357$13048_Y - attribute \src "libresoc.v:187360.17-187360.92" - wire width 4 $not$libresoc.v:187360$13051_Y - attribute \src "libresoc.v:187354.18-187354.98" - wire width 4 $or$libresoc.v:187354$13045_Y - attribute \src "libresoc.v:187356.18-187356.99" - wire width 4 $or$libresoc.v:187356$13047_Y - attribute \src "libresoc.v:187359.17-187359.97" - wire width 4 $or$libresoc.v:187359$13050_Y + attribute \src "libresoc.v:190041.17-190041.96" + wire width 4 $and$libresoc.v:190041$13147_Y + attribute \src "libresoc.v:190046.17-190046.96" + wire width 4 $and$libresoc.v:190046$13152_Y + attribute \src "libresoc.v:190043.18-190043.93" + wire width 4 $not$libresoc.v:190043$13149_Y + attribute \src "libresoc.v:190045.17-190045.92" + wire width 4 $not$libresoc.v:190045$13151_Y + attribute \src "libresoc.v:190048.17-190048.92" + wire width 4 $not$libresoc.v:190048$13154_Y + attribute \src "libresoc.v:190042.18-190042.98" + wire width 4 $or$libresoc.v:190042$13148_Y + attribute \src "libresoc.v:190044.18-190044.99" + wire width 4 $or$libresoc.v:190044$13150_Y + attribute \src "libresoc.v:190047.17-190047.97" + wire width 4 $or$libresoc.v:190047$13153_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392309,11 +396496,11 @@ module \src_l wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187318.7-187318.15" + attribute \src "libresoc.v:190006.7-190006.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -392330,7 +396517,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187353$13044 + cell $and $and$libresoc.v:190041$13147 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -392338,10 +396525,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187353$13044_Y + connect \Y $and$libresoc.v:190041$13147_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187358$13049 + cell $and $and$libresoc.v:190046$13152 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -392349,34 +396536,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187358$13049_Y + connect \Y $and$libresoc.v:190046$13152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187355$13046 + cell $not $not$libresoc.v:190043$13149 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:187355$13046_Y + connect \Y $not$libresoc.v:190043$13149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187357$13048 + cell $not $not$libresoc.v:190045$13151 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:187357$13048_Y + connect \Y $not$libresoc.v:190045$13151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187360$13051 + cell $not $not$libresoc.v:190048$13154 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:187360$13051_Y + connect \Y $not$libresoc.v:190048$13154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187354$13045 + cell $or $or$libresoc.v:190042$13148 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -392384,10 +396571,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187354$13045_Y + connect \Y $or$libresoc.v:190042$13148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187356$13047 + cell $or $or$libresoc.v:190044$13150 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -392395,10 +396582,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187356$13047_Y + connect \Y $or$libresoc.v:190044$13150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187359$13050 + cell $or $or$libresoc.v:190047$13153 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -392406,39 +396593,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187359$13050_Y + connect \Y $or$libresoc.v:190047$13153_Y end - attribute \src "libresoc.v:187318.7-187318.20" - process $proc$libresoc.v:187318$13056 + attribute \src "libresoc.v:190006.7-190006.20" + process $proc$libresoc.v:190006$13159 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187340.13-187340.25" - process $proc$libresoc.v:187340$13057 + attribute \src "libresoc.v:190028.13-190028.25" + process $proc$libresoc.v:190028$13160 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:187361.3-187362.27" - process $proc$libresoc.v:187361$13052 + attribute \src "libresoc.v:190049.3-190050.27" + process $proc$libresoc.v:190049$13155 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:187363.3-187371.6" - process $proc$libresoc.v:187363$13053 + attribute \src "libresoc.v:190051.3-190059.6" + process $proc$libresoc.v:190051$13156 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13054 $1\q_int$next[3:0]$13055 - attribute \src "libresoc.v:187364.5-187364.29" + assign $0\q_int$next[3:0]$13157 $1\q_int$next[3:0]$13158 + attribute \src "libresoc.v:190052.5-190052.29" switch \initial - attribute \src "libresoc.v:187364.9-187364.17" + attribute \src "libresoc.v:190052.9-190052.17" case 1'1 case end @@ -392447,56 +396634,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13055 4'0000 + assign $1\q_int$next[3:0]$13158 4'0000 case - assign $1\q_int$next[3:0]$13055 \$5 + assign $1\q_int$next[3:0]$13158 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13054 + update \q_int$next $0\q_int$next[3:0]$13157 end - connect \$9 $and$libresoc.v:187353$13044_Y - connect \$11 $or$libresoc.v:187354$13045_Y - connect \$13 $not$libresoc.v:187355$13046_Y - connect \$15 $or$libresoc.v:187356$13047_Y - connect \$1 $not$libresoc.v:187357$13048_Y - connect \$3 $and$libresoc.v:187358$13049_Y - connect \$5 $or$libresoc.v:187359$13050_Y - connect \$7 $not$libresoc.v:187360$13051_Y + connect \$9 $and$libresoc.v:190041$13147_Y + connect \$11 $or$libresoc.v:190042$13148_Y + connect \$13 $not$libresoc.v:190043$13149_Y + connect \$15 $or$libresoc.v:190044$13150_Y + connect \$1 $not$libresoc.v:190045$13151_Y + connect \$3 $and$libresoc.v:190046$13152_Y + connect \$5 $or$libresoc.v:190047$13153_Y + connect \$7 $not$libresoc.v:190048$13154_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187379.1-187437.10" +attribute \src "libresoc.v:190067.1-190125.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:187380.7-187380.20" + attribute \src "libresoc.v:190068.7-190068.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187425.3-187433.6" - wire width 6 $0\q_int$next[5:0]$13068 - attribute \src "libresoc.v:187423.3-187424.27" + attribute \src "libresoc.v:190113.3-190121.6" + wire width 6 $0\q_int$next[5:0]$13171 + attribute \src "libresoc.v:190111.3-190112.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:187425.3-187433.6" - wire width 6 $1\q_int$next[5:0]$13069 - attribute \src "libresoc.v:187402.13-187402.26" + attribute \src "libresoc.v:190113.3-190121.6" + wire width 6 $1\q_int$next[5:0]$13172 + attribute \src "libresoc.v:190090.13-190090.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:187415.17-187415.96" - wire width 6 $and$libresoc.v:187415$13058_Y - attribute \src "libresoc.v:187420.17-187420.96" - wire width 6 $and$libresoc.v:187420$13063_Y - attribute \src "libresoc.v:187417.18-187417.93" - wire width 6 $not$libresoc.v:187417$13060_Y - attribute \src "libresoc.v:187419.17-187419.92" - wire width 6 $not$libresoc.v:187419$13062_Y - attribute \src "libresoc.v:187422.17-187422.92" - wire width 6 $not$libresoc.v:187422$13065_Y - attribute \src "libresoc.v:187416.18-187416.98" - wire width 6 $or$libresoc.v:187416$13059_Y - attribute \src "libresoc.v:187418.18-187418.99" - wire width 6 $or$libresoc.v:187418$13061_Y - attribute \src "libresoc.v:187421.17-187421.97" - wire width 6 $or$libresoc.v:187421$13064_Y + attribute \src "libresoc.v:190103.17-190103.96" + wire width 6 $and$libresoc.v:190103$13161_Y + attribute \src "libresoc.v:190108.17-190108.96" + wire width 6 $and$libresoc.v:190108$13166_Y + attribute \src "libresoc.v:190105.18-190105.93" + wire width 6 $not$libresoc.v:190105$13163_Y + attribute \src "libresoc.v:190107.17-190107.92" + wire width 6 $not$libresoc.v:190107$13165_Y + attribute \src "libresoc.v:190110.17-190110.92" + wire width 6 $not$libresoc.v:190110$13168_Y + attribute \src "libresoc.v:190104.18-190104.98" + wire width 6 $or$libresoc.v:190104$13162_Y + attribute \src "libresoc.v:190106.18-190106.99" + wire width 6 $or$libresoc.v:190106$13164_Y + attribute \src "libresoc.v:190109.17-190109.97" + wire width 6 $or$libresoc.v:190109$13167_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392513,11 +396700,11 @@ module \src_l$10 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187380.7-187380.15" + attribute \src "libresoc.v:190068.7-190068.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -392534,7 +396721,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187415$13058 + cell $and $and$libresoc.v:190103$13161 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -392542,10 +396729,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187415$13058_Y + connect \Y $and$libresoc.v:190103$13161_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187420$13063 + cell $and $and$libresoc.v:190108$13166 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -392553,34 +396740,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187420$13063_Y + connect \Y $and$libresoc.v:190108$13166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187417$13060 + cell $not $not$libresoc.v:190105$13163 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:187417$13060_Y + connect \Y $not$libresoc.v:190105$13163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187419$13062 + cell $not $not$libresoc.v:190107$13165 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:187419$13062_Y + connect \Y $not$libresoc.v:190107$13165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187422$13065 + cell $not $not$libresoc.v:190110$13168 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:187422$13065_Y + connect \Y $not$libresoc.v:190110$13168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187416$13059 + cell $or $or$libresoc.v:190104$13162 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -392588,10 +396775,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187416$13059_Y + connect \Y $or$libresoc.v:190104$13162_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187418$13061 + cell $or $or$libresoc.v:190106$13164 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -392599,10 +396786,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187418$13061_Y + connect \Y $or$libresoc.v:190106$13164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187421$13064 + cell $or $or$libresoc.v:190109$13167 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -392610,39 +396797,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187421$13064_Y + connect \Y $or$libresoc.v:190109$13167_Y end - attribute \src "libresoc.v:187380.7-187380.20" - process $proc$libresoc.v:187380$13070 + attribute \src "libresoc.v:190068.7-190068.20" + process $proc$libresoc.v:190068$13173 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187402.13-187402.26" - process $proc$libresoc.v:187402$13071 + attribute \src "libresoc.v:190090.13-190090.26" + process $proc$libresoc.v:190090$13174 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:187423.3-187424.27" - process $proc$libresoc.v:187423$13066 + attribute \src "libresoc.v:190111.3-190112.27" + process $proc$libresoc.v:190111$13169 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:187425.3-187433.6" - process $proc$libresoc.v:187425$13067 + attribute \src "libresoc.v:190113.3-190121.6" + process $proc$libresoc.v:190113$13170 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13068 $1\q_int$next[5:0]$13069 - attribute \src "libresoc.v:187426.5-187426.29" + assign $0\q_int$next[5:0]$13171 $1\q_int$next[5:0]$13172 + attribute \src "libresoc.v:190114.5-190114.29" switch \initial - attribute \src "libresoc.v:187426.9-187426.17" + attribute \src "libresoc.v:190114.9-190114.17" case 1'1 case end @@ -392651,56 +396838,56 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13069 6'000000 + assign $1\q_int$next[5:0]$13172 6'000000 case - assign $1\q_int$next[5:0]$13069 \$5 + assign $1\q_int$next[5:0]$13172 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13068 + update \q_int$next $0\q_int$next[5:0]$13171 end - connect \$9 $and$libresoc.v:187415$13058_Y - connect \$11 $or$libresoc.v:187416$13059_Y - connect \$13 $not$libresoc.v:187417$13060_Y - connect \$15 $or$libresoc.v:187418$13061_Y - connect \$1 $not$libresoc.v:187419$13062_Y - connect \$3 $and$libresoc.v:187420$13063_Y - connect \$5 $or$libresoc.v:187421$13064_Y - connect \$7 $not$libresoc.v:187422$13065_Y + connect \$9 $and$libresoc.v:190103$13161_Y + connect \$11 $or$libresoc.v:190104$13162_Y + connect \$13 $not$libresoc.v:190105$13163_Y + connect \$15 $or$libresoc.v:190106$13164_Y + connect \$1 $not$libresoc.v:190107$13165_Y + connect \$3 $and$libresoc.v:190108$13166_Y + connect \$5 $or$libresoc.v:190109$13167_Y + connect \$7 $not$libresoc.v:190110$13168_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187441.1-187499.10" +attribute \src "libresoc.v:190129.1-190187.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:187442.7-187442.20" + attribute \src "libresoc.v:190130.7-190130.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187487.3-187495.6" - wire width 3 $0\q_int$next[2:0]$13082 - attribute \src "libresoc.v:187485.3-187486.27" + attribute \src "libresoc.v:190175.3-190183.6" + wire width 3 $0\q_int$next[2:0]$13185 + attribute \src "libresoc.v:190173.3-190174.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:187487.3-187495.6" - wire width 3 $1\q_int$next[2:0]$13083 - attribute \src "libresoc.v:187464.13-187464.25" + attribute \src "libresoc.v:190175.3-190183.6" + wire width 3 $1\q_int$next[2:0]$13186 + attribute \src "libresoc.v:190152.13-190152.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:187477.17-187477.96" - wire width 3 $and$libresoc.v:187477$13072_Y - attribute \src "libresoc.v:187482.17-187482.96" - wire width 3 $and$libresoc.v:187482$13077_Y - attribute \src "libresoc.v:187479.18-187479.93" - wire width 3 $not$libresoc.v:187479$13074_Y - attribute \src "libresoc.v:187481.17-187481.92" - wire width 3 $not$libresoc.v:187481$13076_Y - attribute \src "libresoc.v:187484.17-187484.92" - wire width 3 $not$libresoc.v:187484$13079_Y - attribute \src "libresoc.v:187478.18-187478.98" - wire width 3 $or$libresoc.v:187478$13073_Y - attribute \src "libresoc.v:187480.18-187480.99" - wire width 3 $or$libresoc.v:187480$13075_Y - attribute \src "libresoc.v:187483.17-187483.97" - wire width 3 $or$libresoc.v:187483$13078_Y + attribute \src "libresoc.v:190165.17-190165.96" + wire width 3 $and$libresoc.v:190165$13175_Y + attribute \src "libresoc.v:190170.17-190170.96" + wire width 3 $and$libresoc.v:190170$13180_Y + attribute \src "libresoc.v:190167.18-190167.93" + wire width 3 $not$libresoc.v:190167$13177_Y + attribute \src "libresoc.v:190169.17-190169.92" + wire width 3 $not$libresoc.v:190169$13179_Y + attribute \src "libresoc.v:190172.17-190172.92" + wire width 3 $not$libresoc.v:190172$13182_Y + attribute \src "libresoc.v:190166.18-190166.98" + wire width 3 $or$libresoc.v:190166$13176_Y + attribute \src "libresoc.v:190168.18-190168.99" + wire width 3 $or$libresoc.v:190168$13178_Y + attribute \src "libresoc.v:190171.17-190171.97" + wire width 3 $or$libresoc.v:190171$13181_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392717,11 +396904,11 @@ module \src_l$101 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187442.7-187442.15" + attribute \src "libresoc.v:190130.7-190130.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -392738,7 +396925,7 @@ module \src_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187477$13072 + cell $and $and$libresoc.v:190165$13175 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -392746,10 +396933,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187477$13072_Y + connect \Y $and$libresoc.v:190165$13175_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187482$13077 + cell $and $and$libresoc.v:190170$13180 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -392757,34 +396944,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187482$13077_Y + connect \Y $and$libresoc.v:190170$13180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187479$13074 + cell $not $not$libresoc.v:190167$13177 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:187479$13074_Y + connect \Y $not$libresoc.v:190167$13177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187481$13076 + cell $not $not$libresoc.v:190169$13179 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187481$13076_Y + connect \Y $not$libresoc.v:190169$13179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187484$13079 + cell $not $not$libresoc.v:190172$13182 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187484$13079_Y + connect \Y $not$libresoc.v:190172$13182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187478$13073 + cell $or $or$libresoc.v:190166$13176 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -392792,10 +396979,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187478$13073_Y + connect \Y $or$libresoc.v:190166$13176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187480$13075 + cell $or $or$libresoc.v:190168$13178 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -392803,10 +396990,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187480$13075_Y + connect \Y $or$libresoc.v:190168$13178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187483$13078 + cell $or $or$libresoc.v:190171$13181 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -392814,39 +397001,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187483$13078_Y + connect \Y $or$libresoc.v:190171$13181_Y end - attribute \src "libresoc.v:187442.7-187442.20" - process $proc$libresoc.v:187442$13084 + attribute \src "libresoc.v:190130.7-190130.20" + process $proc$libresoc.v:190130$13187 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187464.13-187464.25" - process $proc$libresoc.v:187464$13085 + attribute \src "libresoc.v:190152.13-190152.25" + process $proc$libresoc.v:190152$13188 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:187485.3-187486.27" - process $proc$libresoc.v:187485$13080 + attribute \src "libresoc.v:190173.3-190174.27" + process $proc$libresoc.v:190173$13183 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:187487.3-187495.6" - process $proc$libresoc.v:187487$13081 + attribute \src "libresoc.v:190175.3-190183.6" + process $proc$libresoc.v:190175$13184 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13082 $1\q_int$next[2:0]$13083 - attribute \src "libresoc.v:187488.5-187488.29" + assign $0\q_int$next[2:0]$13185 $1\q_int$next[2:0]$13186 + attribute \src "libresoc.v:190176.5-190176.29" switch \initial - attribute \src "libresoc.v:187488.9-187488.17" + attribute \src "libresoc.v:190176.9-190176.17" case 1'1 case end @@ -392855,56 +397042,56 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13083 3'000 + assign $1\q_int$next[2:0]$13186 3'000 case - assign $1\q_int$next[2:0]$13083 \$5 + assign $1\q_int$next[2:0]$13186 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13082 + update \q_int$next $0\q_int$next[2:0]$13185 end - connect \$9 $and$libresoc.v:187477$13072_Y - connect \$11 $or$libresoc.v:187478$13073_Y - connect \$13 $not$libresoc.v:187479$13074_Y - connect \$15 $or$libresoc.v:187480$13075_Y - connect \$1 $not$libresoc.v:187481$13076_Y - connect \$3 $and$libresoc.v:187482$13077_Y - connect \$5 $or$libresoc.v:187483$13078_Y - connect \$7 $not$libresoc.v:187484$13079_Y + connect \$9 $and$libresoc.v:190165$13175_Y + connect \$11 $or$libresoc.v:190166$13176_Y + connect \$13 $not$libresoc.v:190167$13177_Y + connect \$15 $or$libresoc.v:190168$13178_Y + connect \$1 $not$libresoc.v:190169$13179_Y + connect \$3 $and$libresoc.v:190170$13180_Y + connect \$5 $or$libresoc.v:190171$13181_Y + connect \$7 $not$libresoc.v:190172$13182_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187503.1-187561.10" +attribute \src "libresoc.v:190191.1-190249.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:187504.7-187504.20" + attribute \src "libresoc.v:190192.7-190192.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187549.3-187557.6" - wire width 5 $0\q_int$next[4:0]$13096 - attribute \src "libresoc.v:187547.3-187548.27" + attribute \src "libresoc.v:190237.3-190245.6" + wire width 5 $0\q_int$next[4:0]$13199 + attribute \src "libresoc.v:190235.3-190236.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:187549.3-187557.6" - wire width 5 $1\q_int$next[4:0]$13097 - attribute \src "libresoc.v:187526.13-187526.26" + attribute \src "libresoc.v:190237.3-190245.6" + wire width 5 $1\q_int$next[4:0]$13200 + attribute \src "libresoc.v:190214.13-190214.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:187539.17-187539.96" - wire width 5 $and$libresoc.v:187539$13086_Y - attribute \src "libresoc.v:187544.17-187544.96" - wire width 5 $and$libresoc.v:187544$13091_Y - attribute \src "libresoc.v:187541.18-187541.93" - wire width 5 $not$libresoc.v:187541$13088_Y - attribute \src "libresoc.v:187543.17-187543.92" - wire width 5 $not$libresoc.v:187543$13090_Y - attribute \src "libresoc.v:187546.17-187546.92" - wire width 5 $not$libresoc.v:187546$13093_Y - attribute \src "libresoc.v:187540.18-187540.98" - wire width 5 $or$libresoc.v:187540$13087_Y - attribute \src "libresoc.v:187542.18-187542.99" - wire width 5 $or$libresoc.v:187542$13089_Y - attribute \src "libresoc.v:187545.17-187545.97" - wire width 5 $or$libresoc.v:187545$13092_Y + attribute \src "libresoc.v:190227.17-190227.96" + wire width 5 $and$libresoc.v:190227$13189_Y + attribute \src "libresoc.v:190232.17-190232.96" + wire width 5 $and$libresoc.v:190232$13194_Y + attribute \src "libresoc.v:190229.18-190229.93" + wire width 5 $not$libresoc.v:190229$13191_Y + attribute \src "libresoc.v:190231.17-190231.92" + wire width 5 $not$libresoc.v:190231$13193_Y + attribute \src "libresoc.v:190234.17-190234.92" + wire width 5 $not$libresoc.v:190234$13196_Y + attribute \src "libresoc.v:190228.18-190228.98" + wire width 5 $or$libresoc.v:190228$13190_Y + attribute \src "libresoc.v:190230.18-190230.99" + wire width 5 $or$libresoc.v:190230$13192_Y + attribute \src "libresoc.v:190233.17-190233.97" + wire width 5 $or$libresoc.v:190233$13195_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392921,11 +397108,11 @@ module \src_l$119 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187504.7-187504.15" + attribute \src "libresoc.v:190192.7-190192.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -392942,7 +397129,7 @@ module \src_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187539$13086 + cell $and $and$libresoc.v:190227$13189 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -392950,10 +397137,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187539$13086_Y + connect \Y $and$libresoc.v:190227$13189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187544$13091 + cell $and $and$libresoc.v:190232$13194 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -392961,34 +397148,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187544$13091_Y + connect \Y $and$libresoc.v:190232$13194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187541$13088 + cell $not $not$libresoc.v:190229$13191 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:187541$13088_Y + connect \Y $not$libresoc.v:190229$13191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187543$13090 + cell $not $not$libresoc.v:190231$13193 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:187543$13090_Y + connect \Y $not$libresoc.v:190231$13193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187546$13093 + cell $not $not$libresoc.v:190234$13196 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:187546$13093_Y + connect \Y $not$libresoc.v:190234$13196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187540$13087 + cell $or $or$libresoc.v:190228$13190 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -392996,10 +397183,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187540$13087_Y + connect \Y $or$libresoc.v:190228$13190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187542$13089 + cell $or $or$libresoc.v:190230$13192 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -393007,10 +397194,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187542$13089_Y + connect \Y $or$libresoc.v:190230$13192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187545$13092 + cell $or $or$libresoc.v:190233$13195 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -393018,39 +397205,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187545$13092_Y + connect \Y $or$libresoc.v:190233$13195_Y end - attribute \src "libresoc.v:187504.7-187504.20" - process $proc$libresoc.v:187504$13098 + attribute \src "libresoc.v:190192.7-190192.20" + process $proc$libresoc.v:190192$13201 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187526.13-187526.26" - process $proc$libresoc.v:187526$13099 + attribute \src "libresoc.v:190214.13-190214.26" + process $proc$libresoc.v:190214$13202 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:187547.3-187548.27" - process $proc$libresoc.v:187547$13094 + attribute \src "libresoc.v:190235.3-190236.27" + process $proc$libresoc.v:190235$13197 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:187549.3-187557.6" - process $proc$libresoc.v:187549$13095 + attribute \src "libresoc.v:190237.3-190245.6" + process $proc$libresoc.v:190237$13198 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13096 $1\q_int$next[4:0]$13097 - attribute \src "libresoc.v:187550.5-187550.29" + assign $0\q_int$next[4:0]$13199 $1\q_int$next[4:0]$13200 + attribute \src "libresoc.v:190238.5-190238.29" switch \initial - attribute \src "libresoc.v:187550.9-187550.17" + attribute \src "libresoc.v:190238.9-190238.17" case 1'1 case end @@ -393059,56 +397246,56 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$13097 5'00000 + assign $1\q_int$next[4:0]$13200 5'00000 case - assign $1\q_int$next[4:0]$13097 \$5 + assign $1\q_int$next[4:0]$13200 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$13096 + update \q_int$next $0\q_int$next[4:0]$13199 end - connect \$9 $and$libresoc.v:187539$13086_Y - connect \$11 $or$libresoc.v:187540$13087_Y - connect \$13 $not$libresoc.v:187541$13088_Y - connect \$15 $or$libresoc.v:187542$13089_Y - connect \$1 $not$libresoc.v:187543$13090_Y - connect \$3 $and$libresoc.v:187544$13091_Y - connect \$5 $or$libresoc.v:187545$13092_Y - connect \$7 $not$libresoc.v:187546$13093_Y + connect \$9 $and$libresoc.v:190227$13189_Y + connect \$11 $or$libresoc.v:190228$13190_Y + connect \$13 $not$libresoc.v:190229$13191_Y + connect \$15 $or$libresoc.v:190230$13192_Y + connect \$1 $not$libresoc.v:190231$13193_Y + connect \$3 $and$libresoc.v:190232$13194_Y + connect \$5 $or$libresoc.v:190233$13195_Y + connect \$7 $not$libresoc.v:190234$13196_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187565.1-187623.10" +attribute \src "libresoc.v:190253.1-190311.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:187566.7-187566.20" + attribute \src "libresoc.v:190254.7-190254.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187611.3-187619.6" - wire width 3 $0\q_int$next[2:0]$13110 - attribute \src "libresoc.v:187609.3-187610.27" + attribute \src "libresoc.v:190299.3-190307.6" + wire width 3 $0\q_int$next[2:0]$13213 + attribute \src "libresoc.v:190297.3-190298.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:187611.3-187619.6" - wire width 3 $1\q_int$next[2:0]$13111 - attribute \src "libresoc.v:187588.13-187588.25" + attribute \src "libresoc.v:190299.3-190307.6" + wire width 3 $1\q_int$next[2:0]$13214 + attribute \src "libresoc.v:190276.13-190276.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:187601.17-187601.96" - wire width 3 $and$libresoc.v:187601$13100_Y - attribute \src "libresoc.v:187606.17-187606.96" - wire width 3 $and$libresoc.v:187606$13105_Y - attribute \src "libresoc.v:187603.18-187603.93" - wire width 3 $not$libresoc.v:187603$13102_Y - attribute \src "libresoc.v:187605.17-187605.92" - wire width 3 $not$libresoc.v:187605$13104_Y - attribute \src "libresoc.v:187608.17-187608.92" - wire width 3 $not$libresoc.v:187608$13107_Y - attribute \src "libresoc.v:187602.18-187602.98" - wire width 3 $or$libresoc.v:187602$13101_Y - attribute \src "libresoc.v:187604.18-187604.99" - wire width 3 $or$libresoc.v:187604$13103_Y - attribute \src "libresoc.v:187607.17-187607.97" - wire width 3 $or$libresoc.v:187607$13106_Y + attribute \src "libresoc.v:190289.17-190289.96" + wire width 3 $and$libresoc.v:190289$13203_Y + attribute \src "libresoc.v:190294.17-190294.96" + wire width 3 $and$libresoc.v:190294$13208_Y + attribute \src "libresoc.v:190291.18-190291.93" + wire width 3 $not$libresoc.v:190291$13205_Y + attribute \src "libresoc.v:190293.17-190293.92" + wire width 3 $not$libresoc.v:190293$13207_Y + attribute \src "libresoc.v:190296.17-190296.92" + wire width 3 $not$libresoc.v:190296$13210_Y + attribute \src "libresoc.v:190290.18-190290.98" + wire width 3 $or$libresoc.v:190290$13204_Y + attribute \src "libresoc.v:190292.18-190292.99" + wire width 3 $or$libresoc.v:190292$13206_Y + attribute \src "libresoc.v:190295.17-190295.97" + wire width 3 $or$libresoc.v:190295$13209_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -393125,11 +397312,11 @@ module \src_l$127 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187566.7-187566.15" + attribute \src "libresoc.v:190254.7-190254.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -393146,7 +397333,7 @@ module \src_l$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187601$13100 + cell $and $and$libresoc.v:190289$13203 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393154,10 +397341,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187601$13100_Y + connect \Y $and$libresoc.v:190289$13203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187606$13105 + cell $and $and$libresoc.v:190294$13208 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393165,34 +397352,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187606$13105_Y + connect \Y $and$libresoc.v:190294$13208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187603$13102 + cell $not $not$libresoc.v:190291$13205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:187603$13102_Y + connect \Y $not$libresoc.v:190291$13205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187605$13104 + cell $not $not$libresoc.v:190293$13207 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187605$13104_Y + connect \Y $not$libresoc.v:190293$13207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187608$13107 + cell $not $not$libresoc.v:190296$13210 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187608$13107_Y + connect \Y $not$libresoc.v:190296$13210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187602$13101 + cell $or $or$libresoc.v:190290$13204 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393200,10 +397387,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187602$13101_Y + connect \Y $or$libresoc.v:190290$13204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187604$13103 + cell $or $or$libresoc.v:190292$13206 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393211,10 +397398,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187604$13103_Y + connect \Y $or$libresoc.v:190292$13206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187607$13106 + cell $or $or$libresoc.v:190295$13209 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393222,39 +397409,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187607$13106_Y + connect \Y $or$libresoc.v:190295$13209_Y end - attribute \src "libresoc.v:187566.7-187566.20" - process $proc$libresoc.v:187566$13112 + attribute \src "libresoc.v:190254.7-190254.20" + process $proc$libresoc.v:190254$13215 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187588.13-187588.25" - process $proc$libresoc.v:187588$13113 + attribute \src "libresoc.v:190276.13-190276.25" + process $proc$libresoc.v:190276$13216 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:187609.3-187610.27" - process $proc$libresoc.v:187609$13108 + attribute \src "libresoc.v:190297.3-190298.27" + process $proc$libresoc.v:190297$13211 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:187611.3-187619.6" - process $proc$libresoc.v:187611$13109 + attribute \src "libresoc.v:190299.3-190307.6" + process $proc$libresoc.v:190299$13212 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13110 $1\q_int$next[2:0]$13111 - attribute \src "libresoc.v:187612.5-187612.29" + assign $0\q_int$next[2:0]$13213 $1\q_int$next[2:0]$13214 + attribute \src "libresoc.v:190300.5-190300.29" switch \initial - attribute \src "libresoc.v:187612.9-187612.17" + attribute \src "libresoc.v:190300.9-190300.17" case 1'1 case end @@ -393263,56 +397450,56 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13111 3'000 + assign $1\q_int$next[2:0]$13214 3'000 case - assign $1\q_int$next[2:0]$13111 \$5 + assign $1\q_int$next[2:0]$13214 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13110 + update \q_int$next $0\q_int$next[2:0]$13213 end - connect \$9 $and$libresoc.v:187601$13100_Y - connect \$11 $or$libresoc.v:187602$13101_Y - connect \$13 $not$libresoc.v:187603$13102_Y - connect \$15 $or$libresoc.v:187604$13103_Y - connect \$1 $not$libresoc.v:187605$13104_Y - connect \$3 $and$libresoc.v:187606$13105_Y - connect \$5 $or$libresoc.v:187607$13106_Y - connect \$7 $not$libresoc.v:187608$13107_Y + connect \$9 $and$libresoc.v:190289$13203_Y + connect \$11 $or$libresoc.v:190290$13204_Y + connect \$13 $not$libresoc.v:190291$13205_Y + connect \$15 $or$libresoc.v:190292$13206_Y + connect \$1 $not$libresoc.v:190293$13207_Y + connect \$3 $and$libresoc.v:190294$13208_Y + connect \$5 $or$libresoc.v:190295$13209_Y + connect \$7 $not$libresoc.v:190296$13210_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187627.1-187685.10" +attribute \src "libresoc.v:190315.1-190373.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:187628.7-187628.20" + attribute \src "libresoc.v:190316.7-190316.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187673.3-187681.6" - wire width 3 $0\q_int$next[2:0]$13124 - attribute \src "libresoc.v:187671.3-187672.27" + attribute \src "libresoc.v:190361.3-190369.6" + wire width 3 $0\q_int$next[2:0]$13227 + attribute \src "libresoc.v:190359.3-190360.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:187673.3-187681.6" - wire width 3 $1\q_int$next[2:0]$13125 - attribute \src "libresoc.v:187650.13-187650.25" + attribute \src "libresoc.v:190361.3-190369.6" + wire width 3 $1\q_int$next[2:0]$13228 + attribute \src "libresoc.v:190338.13-190338.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:187663.17-187663.96" - wire width 3 $and$libresoc.v:187663$13114_Y - attribute \src "libresoc.v:187668.17-187668.96" - wire width 3 $and$libresoc.v:187668$13119_Y - attribute \src "libresoc.v:187665.18-187665.93" - wire width 3 $not$libresoc.v:187665$13116_Y - attribute \src "libresoc.v:187667.17-187667.92" - wire width 3 $not$libresoc.v:187667$13118_Y - attribute \src "libresoc.v:187670.17-187670.92" - wire width 3 $not$libresoc.v:187670$13121_Y - attribute \src "libresoc.v:187664.18-187664.98" - wire width 3 $or$libresoc.v:187664$13115_Y - attribute \src "libresoc.v:187666.18-187666.99" - wire width 3 $or$libresoc.v:187666$13117_Y - attribute \src "libresoc.v:187669.17-187669.97" - wire width 3 $or$libresoc.v:187669$13120_Y + attribute \src "libresoc.v:190351.17-190351.96" + wire width 3 $and$libresoc.v:190351$13217_Y + attribute \src "libresoc.v:190356.17-190356.96" + wire width 3 $and$libresoc.v:190356$13222_Y + attribute \src "libresoc.v:190353.18-190353.93" + wire width 3 $not$libresoc.v:190353$13219_Y + attribute \src "libresoc.v:190355.17-190355.92" + wire width 3 $not$libresoc.v:190355$13221_Y + attribute \src "libresoc.v:190358.17-190358.92" + wire width 3 $not$libresoc.v:190358$13224_Y + attribute \src "libresoc.v:190352.18-190352.98" + wire width 3 $or$libresoc.v:190352$13218_Y + attribute \src "libresoc.v:190354.18-190354.99" + wire width 3 $or$libresoc.v:190354$13220_Y + attribute \src "libresoc.v:190357.17-190357.97" + wire width 3 $or$libresoc.v:190357$13223_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -393329,11 +397516,11 @@ module \src_l$23 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187628.7-187628.15" + attribute \src "libresoc.v:190316.7-190316.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -393350,7 +397537,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187663$13114 + cell $and $and$libresoc.v:190351$13217 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393358,10 +397545,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187663$13114_Y + connect \Y $and$libresoc.v:190351$13217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187668$13119 + cell $and $and$libresoc.v:190356$13222 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393369,34 +397556,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187668$13119_Y + connect \Y $and$libresoc.v:190356$13222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187665$13116 + cell $not $not$libresoc.v:190353$13219 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:187665$13116_Y + connect \Y $not$libresoc.v:190353$13219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187667$13118 + cell $not $not$libresoc.v:190355$13221 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187667$13118_Y + connect \Y $not$libresoc.v:190355$13221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187670$13121 + cell $not $not$libresoc.v:190358$13224 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187670$13121_Y + connect \Y $not$libresoc.v:190358$13224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187664$13115 + cell $or $or$libresoc.v:190352$13218 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393404,10 +397591,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187664$13115_Y + connect \Y $or$libresoc.v:190352$13218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187666$13117 + cell $or $or$libresoc.v:190354$13220 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393415,10 +397602,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187666$13117_Y + connect \Y $or$libresoc.v:190354$13220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187669$13120 + cell $or $or$libresoc.v:190357$13223 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393426,39 +397613,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187669$13120_Y + connect \Y $or$libresoc.v:190357$13223_Y end - attribute \src "libresoc.v:187628.7-187628.20" - process $proc$libresoc.v:187628$13126 + attribute \src "libresoc.v:190316.7-190316.20" + process $proc$libresoc.v:190316$13229 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187650.13-187650.25" - process $proc$libresoc.v:187650$13127 + attribute \src "libresoc.v:190338.13-190338.25" + process $proc$libresoc.v:190338$13230 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:187671.3-187672.27" - process $proc$libresoc.v:187671$13122 + attribute \src "libresoc.v:190359.3-190360.27" + process $proc$libresoc.v:190359$13225 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:187673.3-187681.6" - process $proc$libresoc.v:187673$13123 + attribute \src "libresoc.v:190361.3-190369.6" + process $proc$libresoc.v:190361$13226 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13124 $1\q_int$next[2:0]$13125 - attribute \src "libresoc.v:187674.5-187674.29" + assign $0\q_int$next[2:0]$13227 $1\q_int$next[2:0]$13228 + attribute \src "libresoc.v:190362.5-190362.29" switch \initial - attribute \src "libresoc.v:187674.9-187674.17" + attribute \src "libresoc.v:190362.9-190362.17" case 1'1 case end @@ -393467,56 +397654,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13125 3'000 + assign $1\q_int$next[2:0]$13228 3'000 case - assign $1\q_int$next[2:0]$13125 \$5 + assign $1\q_int$next[2:0]$13228 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13124 + update \q_int$next $0\q_int$next[2:0]$13227 end - connect \$9 $and$libresoc.v:187663$13114_Y - connect \$11 $or$libresoc.v:187664$13115_Y - connect \$13 $not$libresoc.v:187665$13116_Y - connect \$15 $or$libresoc.v:187666$13117_Y - connect \$1 $not$libresoc.v:187667$13118_Y - connect \$3 $and$libresoc.v:187668$13119_Y - connect \$5 $or$libresoc.v:187669$13120_Y - connect \$7 $not$libresoc.v:187670$13121_Y + connect \$9 $and$libresoc.v:190351$13217_Y + connect \$11 $or$libresoc.v:190352$13218_Y + connect \$13 $not$libresoc.v:190353$13219_Y + connect \$15 $or$libresoc.v:190354$13220_Y + connect \$1 $not$libresoc.v:190355$13221_Y + connect \$3 $and$libresoc.v:190356$13222_Y + connect \$5 $or$libresoc.v:190357$13223_Y + connect \$7 $not$libresoc.v:190358$13224_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187689.1-187747.10" +attribute \src "libresoc.v:190377.1-190435.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:187690.7-187690.20" + attribute \src "libresoc.v:190378.7-190378.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187735.3-187743.6" - wire width 4 $0\q_int$next[3:0]$13138 - attribute \src "libresoc.v:187733.3-187734.27" + attribute \src "libresoc.v:190423.3-190431.6" + wire width 4 $0\q_int$next[3:0]$13241 + attribute \src "libresoc.v:190421.3-190422.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:187735.3-187743.6" - wire width 4 $1\q_int$next[3:0]$13139 - attribute \src "libresoc.v:187712.13-187712.25" + attribute \src "libresoc.v:190423.3-190431.6" + wire width 4 $1\q_int$next[3:0]$13242 + attribute \src "libresoc.v:190400.13-190400.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:187725.17-187725.96" - wire width 4 $and$libresoc.v:187725$13128_Y - attribute \src "libresoc.v:187730.17-187730.96" - wire width 4 $and$libresoc.v:187730$13133_Y - attribute \src "libresoc.v:187727.18-187727.93" - wire width 4 $not$libresoc.v:187727$13130_Y - attribute \src "libresoc.v:187729.17-187729.92" - wire width 4 $not$libresoc.v:187729$13132_Y - attribute \src "libresoc.v:187732.17-187732.92" - wire width 4 $not$libresoc.v:187732$13135_Y - attribute \src "libresoc.v:187726.18-187726.98" - wire width 4 $or$libresoc.v:187726$13129_Y - attribute \src "libresoc.v:187728.18-187728.99" - wire width 4 $or$libresoc.v:187728$13131_Y - attribute \src "libresoc.v:187731.17-187731.97" - wire width 4 $or$libresoc.v:187731$13134_Y + attribute \src "libresoc.v:190413.17-190413.96" + wire width 4 $and$libresoc.v:190413$13231_Y + attribute \src "libresoc.v:190418.17-190418.96" + wire width 4 $and$libresoc.v:190418$13236_Y + attribute \src "libresoc.v:190415.18-190415.93" + wire width 4 $not$libresoc.v:190415$13233_Y + attribute \src "libresoc.v:190417.17-190417.92" + wire width 4 $not$libresoc.v:190417$13235_Y + attribute \src "libresoc.v:190420.17-190420.92" + wire width 4 $not$libresoc.v:190420$13238_Y + attribute \src "libresoc.v:190414.18-190414.98" + wire width 4 $or$libresoc.v:190414$13232_Y + attribute \src "libresoc.v:190416.18-190416.99" + wire width 4 $or$libresoc.v:190416$13234_Y + attribute \src "libresoc.v:190419.17-190419.97" + wire width 4 $or$libresoc.v:190419$13237_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -393533,11 +397720,11 @@ module \src_l$39 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187690.7-187690.15" + attribute \src "libresoc.v:190378.7-190378.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -393554,7 +397741,7 @@ module \src_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187725$13128 + cell $and $and$libresoc.v:190413$13231 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -393562,10 +397749,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187725$13128_Y + connect \Y $and$libresoc.v:190413$13231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187730$13133 + cell $and $and$libresoc.v:190418$13236 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -393573,34 +397760,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187730$13133_Y + connect \Y $and$libresoc.v:190418$13236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187727$13130 + cell $not $not$libresoc.v:190415$13233 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:187727$13130_Y + connect \Y $not$libresoc.v:190415$13233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187729$13132 + cell $not $not$libresoc.v:190417$13235 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:187729$13132_Y + connect \Y $not$libresoc.v:190417$13235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187732$13135 + cell $not $not$libresoc.v:190420$13238 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:187732$13135_Y + connect \Y $not$libresoc.v:190420$13238_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187726$13129 + cell $or $or$libresoc.v:190414$13232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -393608,10 +397795,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187726$13129_Y + connect \Y $or$libresoc.v:190414$13232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187728$13131 + cell $or $or$libresoc.v:190416$13234 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -393619,10 +397806,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187728$13131_Y + connect \Y $or$libresoc.v:190416$13234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187731$13134 + cell $or $or$libresoc.v:190419$13237 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -393630,39 +397817,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187731$13134_Y + connect \Y $or$libresoc.v:190419$13237_Y end - attribute \src "libresoc.v:187690.7-187690.20" - process $proc$libresoc.v:187690$13140 + attribute \src "libresoc.v:190378.7-190378.20" + process $proc$libresoc.v:190378$13243 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187712.13-187712.25" - process $proc$libresoc.v:187712$13141 + attribute \src "libresoc.v:190400.13-190400.25" + process $proc$libresoc.v:190400$13244 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:187733.3-187734.27" - process $proc$libresoc.v:187733$13136 + attribute \src "libresoc.v:190421.3-190422.27" + process $proc$libresoc.v:190421$13239 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:187735.3-187743.6" - process $proc$libresoc.v:187735$13137 + attribute \src "libresoc.v:190423.3-190431.6" + process $proc$libresoc.v:190423$13240 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13138 $1\q_int$next[3:0]$13139 - attribute \src "libresoc.v:187736.5-187736.29" + assign $0\q_int$next[3:0]$13241 $1\q_int$next[3:0]$13242 + attribute \src "libresoc.v:190424.5-190424.29" switch \initial - attribute \src "libresoc.v:187736.9-187736.17" + attribute \src "libresoc.v:190424.9-190424.17" case 1'1 case end @@ -393671,56 +397858,56 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13139 4'0000 + assign $1\q_int$next[3:0]$13242 4'0000 case - assign $1\q_int$next[3:0]$13139 \$5 + assign $1\q_int$next[3:0]$13242 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13138 + update \q_int$next $0\q_int$next[3:0]$13241 end - connect \$9 $and$libresoc.v:187725$13128_Y - connect \$11 $or$libresoc.v:187726$13129_Y - connect \$13 $not$libresoc.v:187727$13130_Y - connect \$15 $or$libresoc.v:187728$13131_Y - connect \$1 $not$libresoc.v:187729$13132_Y - connect \$3 $and$libresoc.v:187730$13133_Y - connect \$5 $or$libresoc.v:187731$13134_Y - connect \$7 $not$libresoc.v:187732$13135_Y + connect \$9 $and$libresoc.v:190413$13231_Y + connect \$11 $or$libresoc.v:190414$13232_Y + connect \$13 $not$libresoc.v:190415$13233_Y + connect \$15 $or$libresoc.v:190416$13234_Y + connect \$1 $not$libresoc.v:190417$13235_Y + connect \$3 $and$libresoc.v:190418$13236_Y + connect \$5 $or$libresoc.v:190419$13237_Y + connect \$7 $not$libresoc.v:190420$13238_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187751.1-187809.10" +attribute \src "libresoc.v:190439.1-190497.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:187752.7-187752.20" + attribute \src "libresoc.v:190440.7-190440.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187797.3-187805.6" - wire width 3 $0\q_int$next[2:0]$13152 - attribute \src "libresoc.v:187795.3-187796.27" + attribute \src "libresoc.v:190485.3-190493.6" + wire width 3 $0\q_int$next[2:0]$13255 + attribute \src "libresoc.v:190483.3-190484.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:187797.3-187805.6" - wire width 3 $1\q_int$next[2:0]$13153 - attribute \src "libresoc.v:187774.13-187774.25" + attribute \src "libresoc.v:190485.3-190493.6" + wire width 3 $1\q_int$next[2:0]$13256 + attribute \src "libresoc.v:190462.13-190462.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:187787.17-187787.96" - wire width 3 $and$libresoc.v:187787$13142_Y - attribute \src "libresoc.v:187792.17-187792.96" - wire width 3 $and$libresoc.v:187792$13147_Y - attribute \src "libresoc.v:187789.18-187789.93" - wire width 3 $not$libresoc.v:187789$13144_Y - attribute \src "libresoc.v:187791.17-187791.92" - wire width 3 $not$libresoc.v:187791$13146_Y - attribute \src "libresoc.v:187794.17-187794.92" - wire width 3 $not$libresoc.v:187794$13149_Y - attribute \src "libresoc.v:187788.18-187788.98" - wire width 3 $or$libresoc.v:187788$13143_Y - attribute \src "libresoc.v:187790.18-187790.99" - wire width 3 $or$libresoc.v:187790$13145_Y - attribute \src "libresoc.v:187793.17-187793.97" - wire width 3 $or$libresoc.v:187793$13148_Y + attribute \src "libresoc.v:190475.17-190475.96" + wire width 3 $and$libresoc.v:190475$13245_Y + attribute \src "libresoc.v:190480.17-190480.96" + wire width 3 $and$libresoc.v:190480$13250_Y + attribute \src "libresoc.v:190477.18-190477.93" + wire width 3 $not$libresoc.v:190477$13247_Y + attribute \src "libresoc.v:190479.17-190479.92" + wire width 3 $not$libresoc.v:190479$13249_Y + attribute \src "libresoc.v:190482.17-190482.92" + wire width 3 $not$libresoc.v:190482$13252_Y + attribute \src "libresoc.v:190476.18-190476.98" + wire width 3 $or$libresoc.v:190476$13246_Y + attribute \src "libresoc.v:190478.18-190478.99" + wire width 3 $or$libresoc.v:190478$13248_Y + attribute \src "libresoc.v:190481.17-190481.97" + wire width 3 $or$libresoc.v:190481$13251_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -393737,11 +397924,11 @@ module \src_l$55 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187752.7-187752.15" + attribute \src "libresoc.v:190440.7-190440.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -393758,7 +397945,7 @@ module \src_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187787$13142 + cell $and $and$libresoc.v:190475$13245 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393766,10 +397953,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187787$13142_Y + connect \Y $and$libresoc.v:190475$13245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187792$13147 + cell $and $and$libresoc.v:190480$13250 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393777,34 +397964,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187792$13147_Y + connect \Y $and$libresoc.v:190480$13250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187789$13144 + cell $not $not$libresoc.v:190477$13247 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:187789$13144_Y + connect \Y $not$libresoc.v:190477$13247_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187791$13146 + cell $not $not$libresoc.v:190479$13249 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187791$13146_Y + connect \Y $not$libresoc.v:190479$13249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187794$13149 + cell $not $not$libresoc.v:190482$13252 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187794$13149_Y + connect \Y $not$libresoc.v:190482$13252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187788$13143 + cell $or $or$libresoc.v:190476$13246 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393812,10 +397999,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187788$13143_Y + connect \Y $or$libresoc.v:190476$13246_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187790$13145 + cell $or $or$libresoc.v:190478$13248 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393823,10 +398010,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187790$13145_Y + connect \Y $or$libresoc.v:190478$13248_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187793$13148 + cell $or $or$libresoc.v:190481$13251 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -393834,39 +398021,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187793$13148_Y + connect \Y $or$libresoc.v:190481$13251_Y end - attribute \src "libresoc.v:187752.7-187752.20" - process $proc$libresoc.v:187752$13154 + attribute \src "libresoc.v:190440.7-190440.20" + process $proc$libresoc.v:190440$13257 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187774.13-187774.25" - process $proc$libresoc.v:187774$13155 + attribute \src "libresoc.v:190462.13-190462.25" + process $proc$libresoc.v:190462$13258 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:187795.3-187796.27" - process $proc$libresoc.v:187795$13150 + attribute \src "libresoc.v:190483.3-190484.27" + process $proc$libresoc.v:190483$13253 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:187797.3-187805.6" - process $proc$libresoc.v:187797$13151 + attribute \src "libresoc.v:190485.3-190493.6" + process $proc$libresoc.v:190485$13254 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13152 $1\q_int$next[2:0]$13153 - attribute \src "libresoc.v:187798.5-187798.29" + assign $0\q_int$next[2:0]$13255 $1\q_int$next[2:0]$13256 + attribute \src "libresoc.v:190486.5-190486.29" switch \initial - attribute \src "libresoc.v:187798.9-187798.17" + attribute \src "libresoc.v:190486.9-190486.17" case 1'1 case end @@ -393875,56 +398062,56 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13153 3'000 + assign $1\q_int$next[2:0]$13256 3'000 case - assign $1\q_int$next[2:0]$13153 \$5 + assign $1\q_int$next[2:0]$13256 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13152 + update \q_int$next $0\q_int$next[2:0]$13255 end - connect \$9 $and$libresoc.v:187787$13142_Y - connect \$11 $or$libresoc.v:187788$13143_Y - connect \$13 $not$libresoc.v:187789$13144_Y - connect \$15 $or$libresoc.v:187790$13145_Y - connect \$1 $not$libresoc.v:187791$13146_Y - connect \$3 $and$libresoc.v:187792$13147_Y - connect \$5 $or$libresoc.v:187793$13148_Y - connect \$7 $not$libresoc.v:187794$13149_Y + connect \$9 $and$libresoc.v:190475$13245_Y + connect \$11 $or$libresoc.v:190476$13246_Y + connect \$13 $not$libresoc.v:190477$13247_Y + connect \$15 $or$libresoc.v:190478$13248_Y + connect \$1 $not$libresoc.v:190479$13249_Y + connect \$3 $and$libresoc.v:190480$13250_Y + connect \$5 $or$libresoc.v:190481$13251_Y + connect \$7 $not$libresoc.v:190482$13252_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187813.1-187871.10" +attribute \src "libresoc.v:190501.1-190559.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:187814.7-187814.20" + attribute \src "libresoc.v:190502.7-190502.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187859.3-187867.6" - wire width 6 $0\q_int$next[5:0]$13166 - attribute \src "libresoc.v:187857.3-187858.27" + attribute \src "libresoc.v:190547.3-190555.6" + wire width 6 $0\q_int$next[5:0]$13269 + attribute \src "libresoc.v:190545.3-190546.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:187859.3-187867.6" - wire width 6 $1\q_int$next[5:0]$13167 - attribute \src "libresoc.v:187836.13-187836.26" + attribute \src "libresoc.v:190547.3-190555.6" + wire width 6 $1\q_int$next[5:0]$13270 + attribute \src "libresoc.v:190524.13-190524.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:187849.17-187849.96" - wire width 6 $and$libresoc.v:187849$13156_Y - attribute \src "libresoc.v:187854.17-187854.96" - wire width 6 $and$libresoc.v:187854$13161_Y - attribute \src "libresoc.v:187851.18-187851.93" - wire width 6 $not$libresoc.v:187851$13158_Y - attribute \src "libresoc.v:187853.17-187853.92" - wire width 6 $not$libresoc.v:187853$13160_Y - attribute \src "libresoc.v:187856.17-187856.92" - wire width 6 $not$libresoc.v:187856$13163_Y - attribute \src "libresoc.v:187850.18-187850.98" - wire width 6 $or$libresoc.v:187850$13157_Y - attribute \src "libresoc.v:187852.18-187852.99" - wire width 6 $or$libresoc.v:187852$13159_Y - attribute \src "libresoc.v:187855.17-187855.97" - wire width 6 $or$libresoc.v:187855$13162_Y + attribute \src "libresoc.v:190537.17-190537.96" + wire width 6 $and$libresoc.v:190537$13259_Y + attribute \src "libresoc.v:190542.17-190542.96" + wire width 6 $and$libresoc.v:190542$13264_Y + attribute \src "libresoc.v:190539.18-190539.93" + wire width 6 $not$libresoc.v:190539$13261_Y + attribute \src "libresoc.v:190541.17-190541.92" + wire width 6 $not$libresoc.v:190541$13263_Y + attribute \src "libresoc.v:190544.17-190544.92" + wire width 6 $not$libresoc.v:190544$13266_Y + attribute \src "libresoc.v:190538.18-190538.98" + wire width 6 $or$libresoc.v:190538$13260_Y + attribute \src "libresoc.v:190540.18-190540.99" + wire width 6 $or$libresoc.v:190540$13262_Y + attribute \src "libresoc.v:190543.17-190543.97" + wire width 6 $or$libresoc.v:190543$13265_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -393941,11 +398128,11 @@ module \src_l$67 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187814.7-187814.15" + attribute \src "libresoc.v:190502.7-190502.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -393962,7 +398149,7 @@ module \src_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187849$13156 + cell $and $and$libresoc.v:190537$13259 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393970,10 +398157,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187849$13156_Y + connect \Y $and$libresoc.v:190537$13259_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187854$13161 + cell $and $and$libresoc.v:190542$13264 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393981,34 +398168,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187854$13161_Y + connect \Y $and$libresoc.v:190542$13264_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187851$13158 + cell $not $not$libresoc.v:190539$13261 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:187851$13158_Y + connect \Y $not$libresoc.v:190539$13261_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187853$13160 + cell $not $not$libresoc.v:190541$13263 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:187853$13160_Y + connect \Y $not$libresoc.v:190541$13263_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187856$13163 + cell $not $not$libresoc.v:190544$13266 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:187856$13163_Y + connect \Y $not$libresoc.v:190544$13266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187850$13157 + cell $or $or$libresoc.v:190538$13260 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394016,10 +398203,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187850$13157_Y + connect \Y $or$libresoc.v:190538$13260_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187852$13159 + cell $or $or$libresoc.v:190540$13262 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394027,10 +398214,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187852$13159_Y + connect \Y $or$libresoc.v:190540$13262_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187855$13162 + cell $or $or$libresoc.v:190543$13265 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394038,39 +398225,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187855$13162_Y + connect \Y $or$libresoc.v:190543$13265_Y end - attribute \src "libresoc.v:187814.7-187814.20" - process $proc$libresoc.v:187814$13168 + attribute \src "libresoc.v:190502.7-190502.20" + process $proc$libresoc.v:190502$13271 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187836.13-187836.26" - process $proc$libresoc.v:187836$13169 + attribute \src "libresoc.v:190524.13-190524.26" + process $proc$libresoc.v:190524$13272 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:187857.3-187858.27" - process $proc$libresoc.v:187857$13164 + attribute \src "libresoc.v:190545.3-190546.27" + process $proc$libresoc.v:190545$13267 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:187859.3-187867.6" - process $proc$libresoc.v:187859$13165 + attribute \src "libresoc.v:190547.3-190555.6" + process $proc$libresoc.v:190547$13268 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13166 $1\q_int$next[5:0]$13167 - attribute \src "libresoc.v:187860.5-187860.29" + assign $0\q_int$next[5:0]$13269 $1\q_int$next[5:0]$13270 + attribute \src "libresoc.v:190548.5-190548.29" switch \initial - attribute \src "libresoc.v:187860.9-187860.17" + attribute \src "libresoc.v:190548.9-190548.17" case 1'1 case end @@ -394079,56 +398266,56 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13167 6'000000 + assign $1\q_int$next[5:0]$13270 6'000000 case - assign $1\q_int$next[5:0]$13167 \$5 + assign $1\q_int$next[5:0]$13270 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13166 + update \q_int$next $0\q_int$next[5:0]$13269 end - connect \$9 $and$libresoc.v:187849$13156_Y - connect \$11 $or$libresoc.v:187850$13157_Y - connect \$13 $not$libresoc.v:187851$13158_Y - connect \$15 $or$libresoc.v:187852$13159_Y - connect \$1 $not$libresoc.v:187853$13160_Y - connect \$3 $and$libresoc.v:187854$13161_Y - connect \$5 $or$libresoc.v:187855$13162_Y - connect \$7 $not$libresoc.v:187856$13163_Y + connect \$9 $and$libresoc.v:190537$13259_Y + connect \$11 $or$libresoc.v:190538$13260_Y + connect \$13 $not$libresoc.v:190539$13261_Y + connect \$15 $or$libresoc.v:190540$13262_Y + connect \$1 $not$libresoc.v:190541$13263_Y + connect \$3 $and$libresoc.v:190542$13264_Y + connect \$5 $or$libresoc.v:190543$13265_Y + connect \$7 $not$libresoc.v:190544$13266_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187875.1-187933.10" +attribute \src "libresoc.v:190563.1-190621.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:187876.7-187876.20" + attribute \src "libresoc.v:190564.7-190564.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187921.3-187929.6" - wire width 3 $0\q_int$next[2:0]$13180 - attribute \src "libresoc.v:187919.3-187920.27" + attribute \src "libresoc.v:190609.3-190617.6" + wire width 3 $0\q_int$next[2:0]$13283 + attribute \src "libresoc.v:190607.3-190608.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:187921.3-187929.6" - wire width 3 $1\q_int$next[2:0]$13181 - attribute \src "libresoc.v:187898.13-187898.25" + attribute \src "libresoc.v:190609.3-190617.6" + wire width 3 $1\q_int$next[2:0]$13284 + attribute \src "libresoc.v:190586.13-190586.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:187911.17-187911.96" - wire width 3 $and$libresoc.v:187911$13170_Y - attribute \src "libresoc.v:187916.17-187916.96" - wire width 3 $and$libresoc.v:187916$13175_Y - attribute \src "libresoc.v:187913.18-187913.93" - wire width 3 $not$libresoc.v:187913$13172_Y - attribute \src "libresoc.v:187915.17-187915.92" - wire width 3 $not$libresoc.v:187915$13174_Y - attribute \src "libresoc.v:187918.17-187918.92" - wire width 3 $not$libresoc.v:187918$13177_Y - attribute \src "libresoc.v:187912.18-187912.98" - wire width 3 $or$libresoc.v:187912$13171_Y - attribute \src "libresoc.v:187914.18-187914.99" - wire width 3 $or$libresoc.v:187914$13173_Y - attribute \src "libresoc.v:187917.17-187917.97" - wire width 3 $or$libresoc.v:187917$13176_Y + attribute \src "libresoc.v:190599.17-190599.96" + wire width 3 $and$libresoc.v:190599$13273_Y + attribute \src "libresoc.v:190604.17-190604.96" + wire width 3 $and$libresoc.v:190604$13278_Y + attribute \src "libresoc.v:190601.18-190601.93" + wire width 3 $not$libresoc.v:190601$13275_Y + attribute \src "libresoc.v:190603.17-190603.92" + wire width 3 $not$libresoc.v:190603$13277_Y + attribute \src "libresoc.v:190606.17-190606.92" + wire width 3 $not$libresoc.v:190606$13280_Y + attribute \src "libresoc.v:190600.18-190600.98" + wire width 3 $or$libresoc.v:190600$13274_Y + attribute \src "libresoc.v:190602.18-190602.99" + wire width 3 $or$libresoc.v:190602$13276_Y + attribute \src "libresoc.v:190605.17-190605.97" + wire width 3 $or$libresoc.v:190605$13279_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -394145,11 +398332,11 @@ module \src_l$84 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187876.7-187876.15" + attribute \src "libresoc.v:190564.7-190564.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -394166,7 +398353,7 @@ module \src_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187911$13170 + cell $and $and$libresoc.v:190599$13273 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -394174,10 +398361,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187911$13170_Y + connect \Y $and$libresoc.v:190599$13273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187916$13175 + cell $and $and$libresoc.v:190604$13278 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -394185,34 +398372,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187916$13175_Y + connect \Y $and$libresoc.v:190604$13278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187913$13172 + cell $not $not$libresoc.v:190601$13275 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:187913$13172_Y + connect \Y $not$libresoc.v:190601$13275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187915$13174 + cell $not $not$libresoc.v:190603$13277 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187915$13174_Y + connect \Y $not$libresoc.v:190603$13277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187918$13177 + cell $not $not$libresoc.v:190606$13280 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:187918$13177_Y + connect \Y $not$libresoc.v:190606$13280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187912$13171 + cell $or $or$libresoc.v:190600$13274 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -394220,10 +398407,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:187912$13171_Y + connect \Y $or$libresoc.v:190600$13274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187914$13173 + cell $or $or$libresoc.v:190602$13276 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -394231,10 +398418,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:187914$13173_Y + connect \Y $or$libresoc.v:190602$13276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187917$13176 + cell $or $or$libresoc.v:190605$13279 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -394242,39 +398429,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:187917$13176_Y + connect \Y $or$libresoc.v:190605$13279_Y end - attribute \src "libresoc.v:187876.7-187876.20" - process $proc$libresoc.v:187876$13182 + attribute \src "libresoc.v:190564.7-190564.20" + process $proc$libresoc.v:190564$13285 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187898.13-187898.25" - process $proc$libresoc.v:187898$13183 + attribute \src "libresoc.v:190586.13-190586.25" + process $proc$libresoc.v:190586$13286 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:187919.3-187920.27" - process $proc$libresoc.v:187919$13178 + attribute \src "libresoc.v:190607.3-190608.27" + process $proc$libresoc.v:190607$13281 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:187921.3-187929.6" - process $proc$libresoc.v:187921$13179 + attribute \src "libresoc.v:190609.3-190617.6" + process $proc$libresoc.v:190609$13282 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13180 $1\q_int$next[2:0]$13181 - attribute \src "libresoc.v:187922.5-187922.29" + assign $0\q_int$next[2:0]$13283 $1\q_int$next[2:0]$13284 + attribute \src "libresoc.v:190610.5-190610.29" switch \initial - attribute \src "libresoc.v:187922.9-187922.17" + attribute \src "libresoc.v:190610.9-190610.17" case 1'1 case end @@ -394283,56 +398470,56 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13181 3'000 + assign $1\q_int$next[2:0]$13284 3'000 case - assign $1\q_int$next[2:0]$13181 \$5 + assign $1\q_int$next[2:0]$13284 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13180 + update \q_int$next $0\q_int$next[2:0]$13283 end - connect \$9 $and$libresoc.v:187911$13170_Y - connect \$11 $or$libresoc.v:187912$13171_Y - connect \$13 $not$libresoc.v:187913$13172_Y - connect \$15 $or$libresoc.v:187914$13173_Y - connect \$1 $not$libresoc.v:187915$13174_Y - connect \$3 $and$libresoc.v:187916$13175_Y - connect \$5 $or$libresoc.v:187917$13176_Y - connect \$7 $not$libresoc.v:187918$13177_Y + connect \$9 $and$libresoc.v:190599$13273_Y + connect \$11 $or$libresoc.v:190600$13274_Y + connect \$13 $not$libresoc.v:190601$13275_Y + connect \$15 $or$libresoc.v:190602$13276_Y + connect \$1 $not$libresoc.v:190603$13277_Y + connect \$3 $and$libresoc.v:190604$13278_Y + connect \$5 $or$libresoc.v:190605$13279_Y + connect \$7 $not$libresoc.v:190606$13280_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:187937.1-187995.10" +attribute \src "libresoc.v:190625.1-190683.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:187938.7-187938.20" + attribute \src "libresoc.v:190626.7-190626.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187983.3-187991.6" - wire $0\q_int$next[0:0]$13194 - attribute \src "libresoc.v:187981.3-187982.27" + attribute \src "libresoc.v:190671.3-190679.6" + wire $0\q_int$next[0:0]$13297 + attribute \src "libresoc.v:190669.3-190670.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:187983.3-187991.6" - wire $1\q_int$next[0:0]$13195 - attribute \src "libresoc.v:187960.7-187960.19" + attribute \src "libresoc.v:190671.3-190679.6" + wire $1\q_int$next[0:0]$13298 + attribute \src "libresoc.v:190648.7-190648.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:187973.17-187973.96" - wire $and$libresoc.v:187973$13184_Y - attribute \src "libresoc.v:187978.17-187978.96" - wire $and$libresoc.v:187978$13189_Y - attribute \src "libresoc.v:187975.18-187975.99" - wire $not$libresoc.v:187975$13186_Y - attribute \src "libresoc.v:187977.17-187977.98" - wire $not$libresoc.v:187977$13188_Y - attribute \src "libresoc.v:187980.17-187980.98" - wire $not$libresoc.v:187980$13191_Y - attribute \src "libresoc.v:187974.18-187974.104" - wire $or$libresoc.v:187974$13185_Y - attribute \src "libresoc.v:187976.18-187976.105" - wire $or$libresoc.v:187976$13187_Y - attribute \src "libresoc.v:187979.17-187979.103" - wire $or$libresoc.v:187979$13190_Y + attribute \src "libresoc.v:190661.17-190661.96" + wire $and$libresoc.v:190661$13287_Y + attribute \src "libresoc.v:190666.17-190666.96" + wire $and$libresoc.v:190666$13292_Y + attribute \src "libresoc.v:190663.18-190663.99" + wire $not$libresoc.v:190663$13289_Y + attribute \src "libresoc.v:190665.17-190665.98" + wire $not$libresoc.v:190665$13291_Y + attribute \src "libresoc.v:190668.17-190668.98" + wire $not$libresoc.v:190668$13294_Y + attribute \src "libresoc.v:190662.18-190662.104" + wire $or$libresoc.v:190662$13288_Y + attribute \src "libresoc.v:190664.18-190664.105" + wire $or$libresoc.v:190664$13290_Y + attribute \src "libresoc.v:190667.17-190667.103" + wire $or$libresoc.v:190667$13293_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -394349,11 +398536,11 @@ module \st_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:187938.7-187938.15" + attribute \src "libresoc.v:190626.7-190626.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -394370,7 +398557,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187973$13184 + cell $and $and$libresoc.v:190661$13287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394378,10 +398565,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187973$13184_Y + connect \Y $and$libresoc.v:190661$13287_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187978$13189 + cell $and $and$libresoc.v:190666$13292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394389,34 +398576,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187978$13189_Y + connect \Y $and$libresoc.v:190666$13292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187975$13186 + cell $not $not$libresoc.v:190663$13289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:187975$13186_Y + connect \Y $not$libresoc.v:190663$13289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187977$13188 + cell $not $not$libresoc.v:190665$13291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:187977$13188_Y + connect \Y $not$libresoc.v:190665$13291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187980$13191 + cell $not $not$libresoc.v:190668$13294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:187980$13191_Y + connect \Y $not$libresoc.v:190668$13294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187974$13185 + cell $or $or$libresoc.v:190662$13288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394424,10 +398611,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:187974$13185_Y + connect \Y $or$libresoc.v:190662$13288_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187976$13187 + cell $or $or$libresoc.v:190664$13290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394435,10 +398622,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:187976$13187_Y + connect \Y $or$libresoc.v:190664$13290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187979$13190 + cell $or $or$libresoc.v:190667$13293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394446,39 +398633,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:187979$13190_Y + connect \Y $or$libresoc.v:190667$13293_Y end - attribute \src "libresoc.v:187938.7-187938.20" - process $proc$libresoc.v:187938$13196 + attribute \src "libresoc.v:190626.7-190626.20" + process $proc$libresoc.v:190626$13299 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187960.7-187960.19" - process $proc$libresoc.v:187960$13197 + attribute \src "libresoc.v:190648.7-190648.19" + process $proc$libresoc.v:190648$13300 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:187981.3-187982.27" - process $proc$libresoc.v:187981$13192 + attribute \src "libresoc.v:190669.3-190670.27" + process $proc$libresoc.v:190669$13295 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:187983.3-187991.6" - process $proc$libresoc.v:187983$13193 + attribute \src "libresoc.v:190671.3-190679.6" + process $proc$libresoc.v:190671$13296 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13194 $1\q_int$next[0:0]$13195 - attribute \src "libresoc.v:187984.5-187984.29" + assign $0\q_int$next[0:0]$13297 $1\q_int$next[0:0]$13298 + attribute \src "libresoc.v:190672.5-190672.29" switch \initial - attribute \src "libresoc.v:187984.9-187984.17" + attribute \src "libresoc.v:190672.9-190672.17" case 1'1 case end @@ -394487,56 +398674,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13195 1'0 + assign $1\q_int$next[0:0]$13298 1'0 case - assign $1\q_int$next[0:0]$13195 \$5 + assign $1\q_int$next[0:0]$13298 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13194 + update \q_int$next $0\q_int$next[0:0]$13297 end - connect \$9 $and$libresoc.v:187973$13184_Y - connect \$11 $or$libresoc.v:187974$13185_Y - connect \$13 $not$libresoc.v:187975$13186_Y - connect \$15 $or$libresoc.v:187976$13187_Y - connect \$1 $not$libresoc.v:187977$13188_Y - connect \$3 $and$libresoc.v:187978$13189_Y - connect \$5 $or$libresoc.v:187979$13190_Y - connect \$7 $not$libresoc.v:187980$13191_Y + connect \$9 $and$libresoc.v:190661$13287_Y + connect \$11 $or$libresoc.v:190662$13288_Y + connect \$13 $not$libresoc.v:190663$13289_Y + connect \$15 $or$libresoc.v:190664$13290_Y + connect \$1 $not$libresoc.v:190665$13291_Y + connect \$3 $and$libresoc.v:190666$13292_Y + connect \$5 $or$libresoc.v:190667$13293_Y + connect \$7 $not$libresoc.v:190668$13294_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:187999.1-188057.10" +attribute \src "libresoc.v:190687.1-190745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:188000.7-188000.20" + attribute \src "libresoc.v:190688.7-190688.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188045.3-188053.6" - wire $0\q_int$next[0:0]$13208 - attribute \src "libresoc.v:188043.3-188044.27" + attribute \src "libresoc.v:190733.3-190741.6" + wire $0\q_int$next[0:0]$13311 + attribute \src "libresoc.v:190731.3-190732.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188045.3-188053.6" - wire $1\q_int$next[0:0]$13209 - attribute \src "libresoc.v:188022.7-188022.19" + attribute \src "libresoc.v:190733.3-190741.6" + wire $1\q_int$next[0:0]$13312 + attribute \src "libresoc.v:190710.7-190710.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188035.17-188035.96" - wire $and$libresoc.v:188035$13198_Y - attribute \src "libresoc.v:188040.17-188040.96" - wire $and$libresoc.v:188040$13203_Y - attribute \src "libresoc.v:188037.18-188037.97" - wire $not$libresoc.v:188037$13200_Y - attribute \src "libresoc.v:188039.17-188039.96" - wire $not$libresoc.v:188039$13202_Y - attribute \src "libresoc.v:188042.17-188042.96" - wire $not$libresoc.v:188042$13205_Y - attribute \src "libresoc.v:188036.18-188036.102" - wire $or$libresoc.v:188036$13199_Y - attribute \src "libresoc.v:188038.18-188038.103" - wire $or$libresoc.v:188038$13201_Y - attribute \src "libresoc.v:188041.17-188041.101" - wire $or$libresoc.v:188041$13204_Y + attribute \src "libresoc.v:190723.17-190723.96" + wire $and$libresoc.v:190723$13301_Y + attribute \src "libresoc.v:190728.17-190728.96" + wire $and$libresoc.v:190728$13306_Y + attribute \src "libresoc.v:190725.18-190725.97" + wire $not$libresoc.v:190725$13303_Y + attribute \src "libresoc.v:190727.17-190727.96" + wire $not$libresoc.v:190727$13305_Y + attribute \src "libresoc.v:190730.17-190730.96" + wire $not$libresoc.v:190730$13308_Y + attribute \src "libresoc.v:190724.18-190724.102" + wire $or$libresoc.v:190724$13302_Y + attribute \src "libresoc.v:190726.18-190726.103" + wire $or$libresoc.v:190726$13304_Y + attribute \src "libresoc.v:190729.17-190729.101" + wire $or$libresoc.v:190729$13307_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -394553,11 +398740,11 @@ module \st_done wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:188000.7-188000.15" + attribute \src "libresoc.v:190688.7-190688.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -394574,7 +398761,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188035$13198 + cell $and $and$libresoc.v:190723$13301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394582,10 +398769,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188035$13198_Y + connect \Y $and$libresoc.v:190723$13301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188040$13203 + cell $and $and$libresoc.v:190728$13306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394593,34 +398780,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188040$13203_Y + connect \Y $and$libresoc.v:190728$13306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188037$13200 + cell $not $not$libresoc.v:190725$13303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:188037$13200_Y + connect \Y $not$libresoc.v:190725$13303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188039$13202 + cell $not $not$libresoc.v:190727$13305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:188039$13202_Y + connect \Y $not$libresoc.v:190727$13305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188042$13205 + cell $not $not$libresoc.v:190730$13308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:188042$13205_Y + connect \Y $not$libresoc.v:190730$13308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188036$13199 + cell $or $or$libresoc.v:190724$13302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394628,10 +398815,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:188036$13199_Y + connect \Y $or$libresoc.v:190724$13302_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188038$13201 + cell $or $or$libresoc.v:190726$13304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394639,10 +398826,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:188038$13201_Y + connect \Y $or$libresoc.v:190726$13304_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188041$13204 + cell $or $or$libresoc.v:190729$13307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394650,39 +398837,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:188041$13204_Y + connect \Y $or$libresoc.v:190729$13307_Y end - attribute \src "libresoc.v:188000.7-188000.20" - process $proc$libresoc.v:188000$13210 + attribute \src "libresoc.v:190688.7-190688.20" + process $proc$libresoc.v:190688$13313 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188022.7-188022.19" - process $proc$libresoc.v:188022$13211 + attribute \src "libresoc.v:190710.7-190710.19" + process $proc$libresoc.v:190710$13314 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188043.3-188044.27" - process $proc$libresoc.v:188043$13206 + attribute \src "libresoc.v:190731.3-190732.27" + process $proc$libresoc.v:190731$13309 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188045.3-188053.6" - process $proc$libresoc.v:188045$13207 + attribute \src "libresoc.v:190733.3-190741.6" + process $proc$libresoc.v:190733$13310 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13208 $1\q_int$next[0:0]$13209 - attribute \src "libresoc.v:188046.5-188046.29" + assign $0\q_int$next[0:0]$13311 $1\q_int$next[0:0]$13312 + attribute \src "libresoc.v:190734.5-190734.29" switch \initial - attribute \src "libresoc.v:188046.9-188046.17" + attribute \src "libresoc.v:190734.9-190734.17" case 1'1 case end @@ -394691,86 +398878,86 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13209 1'0 + assign $1\q_int$next[0:0]$13312 1'0 case - assign $1\q_int$next[0:0]$13209 \$5 + assign $1\q_int$next[0:0]$13312 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13208 + update \q_int$next $0\q_int$next[0:0]$13311 end - connect \$9 $and$libresoc.v:188035$13198_Y - connect \$11 $or$libresoc.v:188036$13199_Y - connect \$13 $not$libresoc.v:188037$13200_Y - connect \$15 $or$libresoc.v:188038$13201_Y - connect \$1 $not$libresoc.v:188039$13202_Y - connect \$3 $and$libresoc.v:188040$13203_Y - connect \$5 $or$libresoc.v:188041$13204_Y - connect \$7 $not$libresoc.v:188042$13205_Y + connect \$9 $and$libresoc.v:190723$13301_Y + connect \$11 $or$libresoc.v:190724$13302_Y + connect \$13 $not$libresoc.v:190725$13303_Y + connect \$15 $or$libresoc.v:190726$13304_Y + connect \$1 $not$libresoc.v:190727$13305_Y + connect \$3 $and$libresoc.v:190728$13306_Y + connect \$5 $or$libresoc.v:190729$13307_Y + connect \$7 $not$libresoc.v:190730$13308_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:188061.1-188357.10" +attribute \src "libresoc.v:190749.1-191045.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:188309.3-188318.6" + attribute \src "libresoc.v:190997.3-191006.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:188062.7-188062.20" + attribute \src "libresoc.v:190750.7-190750.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188328.3-188337.6" + attribute \src "libresoc.v:191016.3-191025.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:188319.3-188327.6" - wire width 3 $0\ren_delay$12$next[2:0]$13235 - attribute \src "libresoc.v:188223.3-188224.43" - wire width 3 $0\ren_delay$12[2:0]$13224 - attribute \src "libresoc.v:188190.13-188190.34" - wire width 3 $0\ren_delay$12[2:0]$13241 - attribute \src "libresoc.v:188281.3-188289.6" - wire width 3 $0\ren_delay$19$next[2:0]$13227 - attribute \src "libresoc.v:188221.3-188222.43" - wire width 3 $0\ren_delay$19[2:0]$13222 - attribute \src "libresoc.v:188194.13-188194.34" - wire width 3 $0\ren_delay$19[2:0]$13243 - attribute \src "libresoc.v:188300.3-188308.6" - wire width 3 $0\ren_delay$next[2:0]$13231 - attribute \src "libresoc.v:188225.3-188226.35" + attribute \src "libresoc.v:191007.3-191015.6" + wire width 3 $0\ren_delay$12$next[2:0]$13338 + attribute \src "libresoc.v:190911.3-190912.43" + wire width 3 $0\ren_delay$12[2:0]$13327 + attribute \src "libresoc.v:190878.13-190878.34" + wire width 3 $0\ren_delay$12[2:0]$13344 + attribute \src "libresoc.v:190969.3-190977.6" + wire width 3 $0\ren_delay$19$next[2:0]$13330 + attribute \src "libresoc.v:190909.3-190910.43" + wire width 3 $0\ren_delay$19[2:0]$13325 + attribute \src "libresoc.v:190882.13-190882.34" + wire width 3 $0\ren_delay$19[2:0]$13346 + attribute \src "libresoc.v:190988.3-190996.6" + wire width 3 $0\ren_delay$next[2:0]$13334 + attribute \src "libresoc.v:190913.3-190914.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:188290.3-188299.6" + attribute \src "libresoc.v:190978.3-190987.6" wire width 64 $0\sv__data_o[63:0] - attribute \src "libresoc.v:188309.3-188318.6" + attribute \src "libresoc.v:190997.3-191006.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:188328.3-188337.6" + attribute \src "libresoc.v:191016.3-191025.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:188319.3-188327.6" - wire width 3 $1\ren_delay$12$next[2:0]$13236 - attribute \src "libresoc.v:188281.3-188289.6" - wire width 3 $1\ren_delay$19$next[2:0]$13228 - attribute \src "libresoc.v:188300.3-188308.6" - wire width 3 $1\ren_delay$next[2:0]$13232 - attribute \src "libresoc.v:188188.13-188188.29" + attribute \src "libresoc.v:191007.3-191015.6" + wire width 3 $1\ren_delay$12$next[2:0]$13339 + attribute \src "libresoc.v:190969.3-190977.6" + wire width 3 $1\ren_delay$19$next[2:0]$13331 + attribute \src "libresoc.v:190988.3-190996.6" + wire width 3 $1\ren_delay$next[2:0]$13335 + attribute \src "libresoc.v:190876.13-190876.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:188290.3-188299.6" + attribute \src "libresoc.v:190978.3-190987.6" wire width 64 $1\sv__data_o[63:0] - attribute \src "libresoc.v:188212.18-188212.109" - wire width 64 $or$libresoc.v:188212$13212_Y - attribute \src "libresoc.v:188214.18-188214.124" - wire width 64 $or$libresoc.v:188214$13214_Y - attribute \src "libresoc.v:188215.18-188215.110" - wire width 64 $or$libresoc.v:188215$13215_Y - attribute \src "libresoc.v:188217.18-188217.122" - wire width 64 $or$libresoc.v:188217$13217_Y - attribute \src "libresoc.v:188218.18-188218.109" - wire width 64 $or$libresoc.v:188218$13218_Y - attribute \src "libresoc.v:188220.17-188220.123" - wire width 64 $or$libresoc.v:188220$13220_Y - attribute \src "libresoc.v:188213.18-188213.100" - wire $reduce_or$libresoc.v:188213$13213_Y - attribute \src "libresoc.v:188216.18-188216.100" - wire $reduce_or$libresoc.v:188216$13216_Y - attribute \src "libresoc.v:188219.17-188219.95" - wire $reduce_or$libresoc.v:188219$13219_Y + attribute \src "libresoc.v:190900.18-190900.109" + wire width 64 $or$libresoc.v:190900$13315_Y + attribute \src "libresoc.v:190902.18-190902.124" + wire width 64 $or$libresoc.v:190902$13317_Y + attribute \src "libresoc.v:190903.18-190903.110" + wire width 64 $or$libresoc.v:190903$13318_Y + attribute \src "libresoc.v:190905.18-190905.122" + wire width 64 $or$libresoc.v:190905$13320_Y + attribute \src "libresoc.v:190906.18-190906.109" + wire width 64 $or$libresoc.v:190906$13321_Y + attribute \src "libresoc.v:190908.17-190908.123" + wire width 64 $or$libresoc.v:190908$13323_Y + attribute \src "libresoc.v:190901.18-190901.100" + wire $reduce_or$libresoc.v:190901$13316_Y + attribute \src "libresoc.v:190904.18-190904.100" + wire $reduce_or$libresoc.v:190904$13319_Y + attribute \src "libresoc.v:190907.17-190907.95" + wire $reduce_or$libresoc.v:190907$13322_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -394793,9 +398980,9 @@ module \state wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \data_i @@ -394805,7 +398992,7 @@ module \state wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 - attribute \src "libresoc.v:188062.7-188062.15" + attribute \src "libresoc.v:190750.7-190750.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 9 \msr__data_o @@ -394920,7 +399107,7 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:188212$13212 + cell $or $or$libresoc.v:190900$13315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -394928,10 +399115,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:188212$13212_Y + connect \Y $or$libresoc.v:190900$13315_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:188214$13214 + cell $or $or$libresoc.v:190902$13317 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -394939,10 +399126,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o - connect \Y $or$libresoc.v:188214$13214_Y + connect \Y $or$libresoc.v:190902$13317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:188215$13215 + cell $or $or$libresoc.v:190903$13318 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -394950,10 +399137,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 - connect \Y $or$libresoc.v:188215$13215_Y + connect \Y $or$libresoc.v:190903$13318_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:188217$13217 + cell $or $or$libresoc.v:190905$13320 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -394961,10 +399148,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o - connect \Y $or$libresoc.v:188217$13217_Y + connect \Y $or$libresoc.v:190905$13320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:188218$13218 + cell $or $or$libresoc.v:190906$13321 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -394972,10 +399159,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 - connect \Y $or$libresoc.v:188218$13218_Y + connect \Y $or$libresoc.v:190906$13321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:188220$13220 + cell $or $or$libresoc.v:190908$13323 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -394983,34 +399170,34 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o - connect \Y $or$libresoc.v:188220$13220_Y + connect \Y $or$libresoc.v:190908$13323_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188213$13213 + cell $reduce_or $reduce_or$libresoc.v:190901$13316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:188213$13213_Y + connect \Y $reduce_or$libresoc.v:190901$13316_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188216$13216 + cell $reduce_or $reduce_or$libresoc.v:190904$13319 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 - connect \Y $reduce_or$libresoc.v:188216$13216_Y + connect \Y $reduce_or$libresoc.v:190904$13319_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188219$13219 + cell $reduce_or $reduce_or$libresoc.v:190907$13322 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:188219$13219_Y + connect \Y $reduce_or$libresoc.v:190907$13322_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:188227.15-188244.4" + attribute \src "libresoc.v:190915.15-190932.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -395030,7 +399217,7 @@ module \state connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:188245.15-188262.4" + attribute \src "libresoc.v:190933.15-190950.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -395050,7 +399237,7 @@ module \state connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:188263.15-188280.4" + attribute \src "libresoc.v:190951.15-190968.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -395069,67 +399256,67 @@ module \state connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end - attribute \src "libresoc.v:188062.7-188062.20" - process $proc$libresoc.v:188062$13238 + attribute \src "libresoc.v:190750.7-190750.20" + process $proc$libresoc.v:190750$13341 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188188.13-188188.29" - process $proc$libresoc.v:188188$13239 + attribute \src "libresoc.v:190876.13-190876.29" + process $proc$libresoc.v:190876$13342 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:188190.13-188190.34" - process $proc$libresoc.v:188190$13240 + attribute \src "libresoc.v:190878.13-190878.34" + process $proc$libresoc.v:190878$13343 assign { } { } - assign $0\ren_delay$12[2:0]$13241 3'000 + assign $0\ren_delay$12[2:0]$13344 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[2:0]$13241 + update \ren_delay$12 $0\ren_delay$12[2:0]$13344 end - attribute \src "libresoc.v:188194.13-188194.34" - process $proc$libresoc.v:188194$13242 + attribute \src "libresoc.v:190882.13-190882.34" + process $proc$libresoc.v:190882$13345 assign { } { } - assign $0\ren_delay$19[2:0]$13243 3'000 + assign $0\ren_delay$19[2:0]$13346 3'000 sync always sync init - update \ren_delay$19 $0\ren_delay$19[2:0]$13243 + update \ren_delay$19 $0\ren_delay$19[2:0]$13346 end - attribute \src "libresoc.v:188221.3-188222.43" - process $proc$libresoc.v:188221$13221 + attribute \src "libresoc.v:190909.3-190910.43" + process $proc$libresoc.v:190909$13324 assign { } { } - assign $0\ren_delay$19[2:0]$13222 \ren_delay$19$next + assign $0\ren_delay$19[2:0]$13325 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$19 $0\ren_delay$19[2:0]$13222 + update \ren_delay$19 $0\ren_delay$19[2:0]$13325 end - attribute \src "libresoc.v:188223.3-188224.43" - process $proc$libresoc.v:188223$13223 + attribute \src "libresoc.v:190911.3-190912.43" + process $proc$libresoc.v:190911$13326 assign { } { } - assign $0\ren_delay$12[2:0]$13224 \ren_delay$12$next + assign $0\ren_delay$12[2:0]$13327 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[2:0]$13224 + update \ren_delay$12 $0\ren_delay$12[2:0]$13327 end - attribute \src "libresoc.v:188225.3-188226.35" - process $proc$libresoc.v:188225$13225 + attribute \src "libresoc.v:190913.3-190914.35" + process $proc$libresoc.v:190913$13328 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:188281.3-188289.6" - process $proc$libresoc.v:188281$13226 + attribute \src "libresoc.v:190969.3-190977.6" + process $proc$libresoc.v:190969$13329 assign { } { } assign { } { } - assign $0\ren_delay$19$next[2:0]$13227 $1\ren_delay$19$next[2:0]$13228 - attribute \src "libresoc.v:188282.5-188282.29" + assign $0\ren_delay$19$next[2:0]$13330 $1\ren_delay$19$next[2:0]$13331 + attribute \src "libresoc.v:190970.5-190970.29" switch \initial - attribute \src "libresoc.v:188282.9-188282.17" + attribute \src "libresoc.v:190970.9-190970.17" case 1'1 case end @@ -395138,21 +399325,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$19$next[2:0]$13228 3'000 + assign $1\ren_delay$19$next[2:0]$13331 3'000 case - assign $1\ren_delay$19$next[2:0]$13228 \sv__ren + assign $1\ren_delay$19$next[2:0]$13331 \sv__ren end sync always - update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13227 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13330 end - attribute \src "libresoc.v:188290.3-188299.6" - process $proc$libresoc.v:188290$13229 + attribute \src "libresoc.v:190978.3-190987.6" + process $proc$libresoc.v:190978$13332 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] - attribute \src "libresoc.v:188291.5-188291.29" + attribute \src "libresoc.v:190979.5-190979.29" switch \initial - attribute \src "libresoc.v:188291.9-188291.17" + attribute \src "libresoc.v:190979.9-190979.17" case 1'1 case end @@ -395168,14 +399355,14 @@ module \state sync always update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:188300.3-188308.6" - process $proc$libresoc.v:188300$13230 + attribute \src "libresoc.v:190988.3-190996.6" + process $proc$libresoc.v:190988$13333 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13231 $1\ren_delay$next[2:0]$13232 - attribute \src "libresoc.v:188301.5-188301.29" + assign $0\ren_delay$next[2:0]$13334 $1\ren_delay$next[2:0]$13335 + attribute \src "libresoc.v:190989.5-190989.29" switch \initial - attribute \src "libresoc.v:188301.9-188301.17" + attribute \src "libresoc.v:190989.9-190989.17" case 1'1 case end @@ -395184,21 +399371,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13232 3'000 + assign $1\ren_delay$next[2:0]$13335 3'000 case - assign $1\ren_delay$next[2:0]$13232 \cia__ren + assign $1\ren_delay$next[2:0]$13335 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13231 + update \ren_delay$next $0\ren_delay$next[2:0]$13334 end - attribute \src "libresoc.v:188309.3-188318.6" - process $proc$libresoc.v:188309$13233 + attribute \src "libresoc.v:190997.3-191006.6" + process $proc$libresoc.v:190997$13336 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:188310.5-188310.29" + attribute \src "libresoc.v:190998.5-190998.29" switch \initial - attribute \src "libresoc.v:188310.9-188310.17" + attribute \src "libresoc.v:190998.9-190998.17" case 1'1 case end @@ -395214,14 +399401,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - attribute \src "libresoc.v:188319.3-188327.6" - process $proc$libresoc.v:188319$13234 + attribute \src "libresoc.v:191007.3-191015.6" + process $proc$libresoc.v:191007$13337 assign { } { } assign { } { } - assign $0\ren_delay$12$next[2:0]$13235 $1\ren_delay$12$next[2:0]$13236 - attribute \src "libresoc.v:188320.5-188320.29" + assign $0\ren_delay$12$next[2:0]$13338 $1\ren_delay$12$next[2:0]$13339 + attribute \src "libresoc.v:191008.5-191008.29" switch \initial - attribute \src "libresoc.v:188320.9-188320.17" + attribute \src "libresoc.v:191008.9-191008.17" case 1'1 case end @@ -395230,21 +399417,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[2:0]$13236 3'000 + assign $1\ren_delay$12$next[2:0]$13339 3'000 case - assign $1\ren_delay$12$next[2:0]$13236 \msr__ren + assign $1\ren_delay$12$next[2:0]$13339 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13235 + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13338 end - attribute \src "libresoc.v:188328.3-188337.6" - process $proc$libresoc.v:188328$13237 + attribute \src "libresoc.v:191016.3-191025.6" + process $proc$libresoc.v:191016$13340 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:188329.5-188329.29" + attribute \src "libresoc.v:191017.5-191017.29" switch \initial - attribute \src "libresoc.v:188329.9-188329.17" + attribute \src "libresoc.v:191017.9-191017.17" case 1'1 case end @@ -395260,15 +399447,15 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - connect \$10 $or$libresoc.v:188212$13212_Y - connect \$13 $reduce_or$libresoc.v:188213$13213_Y - connect \$15 $or$libresoc.v:188214$13214_Y - connect \$17 $or$libresoc.v:188215$13215_Y - connect \$20 $reduce_or$libresoc.v:188216$13216_Y - connect \$22 $or$libresoc.v:188217$13217_Y - connect \$24 $or$libresoc.v:188218$13218_Y - connect \$6 $reduce_or$libresoc.v:188219$13219_Y - connect \$8 $or$libresoc.v:188220$13220_Y + connect \$10 $or$libresoc.v:190900$13315_Y + connect \$13 $reduce_or$libresoc.v:190901$13316_Y + connect \$15 $or$libresoc.v:190902$13317_Y + connect \$17 $or$libresoc.v:190903$13318_Y + connect \$20 $reduce_or$libresoc.v:190904$13319_Y + connect \$22 $or$libresoc.v:190905$13320_Y + connect \$24 $or$libresoc.v:190906$13321_Y + connect \$6 $reduce_or$libresoc.v:190907$13322_Y + connect \$8 $or$libresoc.v:190908$13323_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i @@ -395289,37 +399476,37 @@ module \state connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:188361.1-188419.10" +attribute \src "libresoc.v:191049.1-191107.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:188362.7-188362.20" + attribute \src "libresoc.v:191050.7-191050.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188407.3-188415.6" - wire $0\q_int$next[0:0]$13254 - attribute \src "libresoc.v:188405.3-188406.27" + attribute \src "libresoc.v:191095.3-191103.6" + wire $0\q_int$next[0:0]$13357 + attribute \src "libresoc.v:191093.3-191094.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188407.3-188415.6" - wire $1\q_int$next[0:0]$13255 - attribute \src "libresoc.v:188384.7-188384.19" + attribute \src "libresoc.v:191095.3-191103.6" + wire $1\q_int$next[0:0]$13358 + attribute \src "libresoc.v:191072.7-191072.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188397.17-188397.96" - wire $and$libresoc.v:188397$13244_Y - attribute \src "libresoc.v:188402.17-188402.96" - wire $and$libresoc.v:188402$13249_Y - attribute \src "libresoc.v:188399.18-188399.93" - wire $not$libresoc.v:188399$13246_Y - attribute \src "libresoc.v:188401.17-188401.92" - wire $not$libresoc.v:188401$13248_Y - attribute \src "libresoc.v:188404.17-188404.92" - wire $not$libresoc.v:188404$13251_Y - attribute \src "libresoc.v:188398.18-188398.98" - wire $or$libresoc.v:188398$13245_Y - attribute \src "libresoc.v:188400.18-188400.99" - wire $or$libresoc.v:188400$13247_Y - attribute \src "libresoc.v:188403.17-188403.97" - wire $or$libresoc.v:188403$13250_Y + attribute \src "libresoc.v:191085.17-191085.96" + wire $and$libresoc.v:191085$13347_Y + attribute \src "libresoc.v:191090.17-191090.96" + wire $and$libresoc.v:191090$13352_Y + attribute \src "libresoc.v:191087.18-191087.93" + wire $not$libresoc.v:191087$13349_Y + attribute \src "libresoc.v:191089.17-191089.92" + wire $not$libresoc.v:191089$13351_Y + attribute \src "libresoc.v:191092.17-191092.92" + wire $not$libresoc.v:191092$13354_Y + attribute \src "libresoc.v:191086.18-191086.98" + wire $or$libresoc.v:191086$13348_Y + attribute \src "libresoc.v:191088.18-191088.99" + wire $or$libresoc.v:191088$13350_Y + attribute \src "libresoc.v:191091.17-191091.97" + wire $or$libresoc.v:191091$13353_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -395336,11 +399523,11 @@ module \sto_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:188362.7-188362.15" + attribute \src "libresoc.v:191050.7-191050.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -395357,7 +399544,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188397$13244 + cell $and $and$libresoc.v:191085$13347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395365,10 +399552,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188397$13244_Y + connect \Y $and$libresoc.v:191085$13347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188402$13249 + cell $and $and$libresoc.v:191090$13352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395376,34 +399563,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188402$13249_Y + connect \Y $and$libresoc.v:191090$13352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188399$13246 + cell $not $not$libresoc.v:191087$13349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:188399$13246_Y + connect \Y $not$libresoc.v:191087$13349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188401$13248 + cell $not $not$libresoc.v:191089$13351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:188401$13248_Y + connect \Y $not$libresoc.v:191089$13351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188404$13251 + cell $not $not$libresoc.v:191092$13354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:188404$13251_Y + connect \Y $not$libresoc.v:191092$13354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188398$13245 + cell $or $or$libresoc.v:191086$13348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395411,10 +399598,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:188398$13245_Y + connect \Y $or$libresoc.v:191086$13348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188400$13247 + cell $or $or$libresoc.v:191088$13350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395422,10 +399609,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:188400$13247_Y + connect \Y $or$libresoc.v:191088$13350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188403$13250 + cell $or $or$libresoc.v:191091$13353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395433,39 +399620,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:188403$13250_Y + connect \Y $or$libresoc.v:191091$13353_Y end - attribute \src "libresoc.v:188362.7-188362.20" - process $proc$libresoc.v:188362$13256 + attribute \src "libresoc.v:191050.7-191050.20" + process $proc$libresoc.v:191050$13359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188384.7-188384.19" - process $proc$libresoc.v:188384$13257 + attribute \src "libresoc.v:191072.7-191072.19" + process $proc$libresoc.v:191072$13360 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188405.3-188406.27" - process $proc$libresoc.v:188405$13252 + attribute \src "libresoc.v:191093.3-191094.27" + process $proc$libresoc.v:191093$13355 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188407.3-188415.6" - process $proc$libresoc.v:188407$13253 + attribute \src "libresoc.v:191095.3-191103.6" + process $proc$libresoc.v:191095$13356 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13254 $1\q_int$next[0:0]$13255 - attribute \src "libresoc.v:188408.5-188408.29" + assign $0\q_int$next[0:0]$13357 $1\q_int$next[0:0]$13358 + attribute \src "libresoc.v:191096.5-191096.29" switch \initial - attribute \src "libresoc.v:188408.9-188408.17" + attribute \src "libresoc.v:191096.9-191096.17" case 1'1 case end @@ -395474,26 +399661,26 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13255 1'0 + assign $1\q_int$next[0:0]$13358 1'0 case - assign $1\q_int$next[0:0]$13255 \$5 + assign $1\q_int$next[0:0]$13358 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13254 + update \q_int$next $0\q_int$next[0:0]$13357 end - connect \$9 $and$libresoc.v:188397$13244_Y - connect \$11 $or$libresoc.v:188398$13245_Y - connect \$13 $not$libresoc.v:188399$13246_Y - connect \$15 $or$libresoc.v:188400$13247_Y - connect \$1 $not$libresoc.v:188401$13248_Y - connect \$3 $and$libresoc.v:188402$13249_Y - connect \$5 $or$libresoc.v:188403$13250_Y - connect \$7 $not$libresoc.v:188404$13251_Y + connect \$9 $and$libresoc.v:191085$13347_Y + connect \$11 $or$libresoc.v:191086$13348_Y + connect \$13 $not$libresoc.v:191087$13349_Y + connect \$15 $or$libresoc.v:191088$13350_Y + connect \$1 $not$libresoc.v:191089$13351_Y + connect \$3 $and$libresoc.v:191090$13352_Y + connect \$5 $or$libresoc.v:191091$13353_Y + connect \$7 $not$libresoc.v:191092$13354_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:188424.1-189530.10" +attribute \src "libresoc.v:191112.1-192349.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -395509,8 +399696,10 @@ module \test_issuer wire input 8 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133" wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 368 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 404 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 406 \clk_sel_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" @@ -395762,43 +399951,43 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 334 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 355 \icp_wb__ack + wire output 391 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 349 \icp_wb__adr + wire width 28 input 385 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 353 \icp_wb__cyc + wire input 389 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 351 \icp_wb__dat_r + wire width 32 output 387 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 350 \icp_wb__dat_w + wire width 32 input 386 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 357 \icp_wb__err + wire input 393 \icp_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 352 \icp_wb__sel + wire width 4 input 388 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 354 \icp_wb__stb + wire input 390 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 356 \icp_wb__we + wire input 392 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 364 \ics_wb__ack + wire output 400 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 358 \ics_wb__adr + wire width 28 input 394 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 362 \ics_wb__cyc + wire input 398 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 360 \ics_wb__dat_r + wire width 32 output 396 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 359 \ics_wb__dat_w + wire width 32 input 395 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 366 \ics_wb__err + wire input 402 \ics_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 361 \ics_wb__sel + wire width 4 input 397 \ics_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 363 \ics_wb__stb + wire input 399 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 365 \ics_wb__we + wire input 401 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 367 \int_level_i + wire width 16 input 403 \int_level_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 17 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" @@ -395868,11 +400057,25 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 142 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 370 \pc_i + wire width 64 input 409 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 1 \pc_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129" wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" + wire output 407 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire \pll_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 408 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire \pll_pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:810" + wire \pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:810" + wire \pllclk_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 145 \pwm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -395881,8 +400084,8 @@ module \test_issuer wire input 147 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 369 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 405 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 155 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -396239,10 +400442,91 @@ module \test_issuer wire input 263 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 356 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 349 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 353 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 351 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 350 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 357 \sram4k_0_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 352 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 354 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 355 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 365 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 358 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 362 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 360 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 359 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 366 \sram4k_1_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 361 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 363 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 364 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 374 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 367 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 371 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 369 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 368 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 375 \sram4k_2_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 370 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 372 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 373 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 383 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 376 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 380 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 378 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 377 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 384 \sram4k_3_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 379 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 381 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 382 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:189167.6-189528.4" + attribute \src "libresoc.v:191943.7-191949.4" + cell \pll \pll + connect \clk_24_i \pll_clk_24_i + connect \clk_pll_o \pll_clk_pll_o + connect \clk_sel_i \clk_sel_i + connect \pll_18_o \pll_pll_18_o + connect \pll_lck_o \pll_lck_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191950.6-192343.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -396604,2009 +400888,2079 @@ module \test_issuer connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o connect \sdr_we_n__core__o \sdr_we_n__core__o connect \sdr_we_n__pad__o \sdr_we_n__pad__o - end - connect \ti_coresync_clk \clk + connect \sram4k_0_wb__ack \sram4k_0_wb__ack + connect \sram4k_0_wb__adr \sram4k_0_wb__adr + connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc + connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r + connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w + connect \sram4k_0_wb__sel \sram4k_0_wb__sel + connect \sram4k_0_wb__stb \sram4k_0_wb__stb + connect \sram4k_0_wb__we \sram4k_0_wb__we + connect \sram4k_1_wb__ack \sram4k_1_wb__ack + connect \sram4k_1_wb__adr \sram4k_1_wb__adr + connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc + connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r + connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w + connect \sram4k_1_wb__sel \sram4k_1_wb__sel + connect \sram4k_1_wb__stb \sram4k_1_wb__stb + connect \sram4k_1_wb__we \sram4k_1_wb__we + connect \sram4k_2_wb__ack \sram4k_2_wb__ack + connect \sram4k_2_wb__adr \sram4k_2_wb__adr + connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc + connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r + connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w + connect \sram4k_2_wb__sel \sram4k_2_wb__sel + connect \sram4k_2_wb__stb \sram4k_2_wb__stb + connect \sram4k_2_wb__we \sram4k_2_wb__we + connect \sram4k_3_wb__ack \sram4k_3_wb__ack + connect \sram4k_3_wb__adr \sram4k_3_wb__adr + connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc + connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r + connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w + connect \sram4k_3_wb__sel \sram4k_3_wb__sel + connect \sram4k_3_wb__stb \sram4k_3_wb__stb + connect \sram4k_3_wb__we \sram4k_3_wb__we + end + connect \ti_coresync_clk \pll_clk_pll_o + connect \pllclk_rst \rst + connect \pll_18_o \pll_pll_18_o + connect \pll_clk_24_i \clk + connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:189534.1-194513.10" +attribute \src "libresoc.v:192353.1-197545.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $0\core_asmcode$next[7:0]$13738 - attribute \src "libresoc.v:192025.3-192026.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $0\core_asmcode$next[7:0]$13857 + attribute \src "libresoc.v:194947.3-194948.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:192862.3-192886.6" - wire $0\core_bigendian_i$10$next[0:0]$13542 - attribute \src "libresoc.v:192137.3-192138.57" - wire $0\core_bigendian_i$10[0:0]$13454 - attribute \src "libresoc.v:189805.7-189805.35" - wire $0\core_bigendian_i$10[0:0]$13951 - attribute \src "libresoc.v:193381.3-193393.6" + attribute \src "libresoc.v:195854.3-195878.6" + wire $0\core_bigendian_i$10$next[0:0]$13655 + attribute \src "libresoc.v:195077.3-195078.57" + wire $0\core_bigendian_i$10[0:0]$13574 + attribute \src "libresoc.v:192630.7-192630.35" + wire $0\core_bigendian_i$10[0:0]$14064 + attribute \src "libresoc.v:196436.3-196448.6" wire width 3 $0\core_cia__ren[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 64 $0\core_core_core_cia$next[63:0]$13739 - attribute \src "libresoc.v:192101.3-192102.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13858 + attribute \src "libresoc.v:195021.3-195022.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$13740 - attribute \src "libresoc.v:192145.3-192146.57" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13859 + attribute \src "libresoc.v:195065.3-195066.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$13741 - attribute \src "libresoc.v:192147.3-192148.63" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13860 + attribute \src "libresoc.v:195067.3-195068.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$13742 - attribute \src "libresoc.v:192149.3-192150.57" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13861 + attribute \src "libresoc.v:195069.3-195070.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$13743 - attribute \src "libresoc.v:192127.3-192128.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13444 - attribute \src "libresoc.v:189831.7-189831.44" - wire $0\core_core_core_exc_$signal$3[0:0]$13959 - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$13744 - attribute \src "libresoc.v:192129.3-192130.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13446 - attribute \src "libresoc.v:189835.7-189835.44" - wire $0\core_core_core_exc_$signal$4[0:0]$13961 - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$13745 - attribute \src "libresoc.v:192131.3-192132.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13448 - attribute \src "libresoc.v:189839.7-189839.44" - wire $0\core_core_core_exc_$signal$5[0:0]$13963 - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$13746 - attribute \src "libresoc.v:192133.3-192134.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13450 - attribute \src "libresoc.v:189843.7-189843.44" - wire $0\core_core_core_exc_$signal$6[0:0]$13965 - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$13747 - attribute \src "libresoc.v:192135.3-192136.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13452 - attribute \src "libresoc.v:189847.7-189847.44" - wire $0\core_core_core_exc_$signal$7[0:0]$13967 - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$13748 - attribute \src "libresoc.v:192139.3-192140.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13456 - attribute \src "libresoc.v:189851.7-189851.44" - wire $0\core_core_core_exc_$signal$8[0:0]$13969 - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$13749 - attribute \src "libresoc.v:192141.3-192142.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13458 - attribute \src "libresoc.v:189855.7-189855.44" - wire $0\core_core_core_exc_$signal$9[0:0]$13971 - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_exc_$signal$next[0:0]$13750 - attribute \src "libresoc.v:192125.3-192126.71" - wire $0\core_core_core_exc_$signal[0:0]$13442 - attribute \src "libresoc.v:189829.7-189829.42" - wire $0\core_core_core_exc_$signal[0:0]$13957 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 13 $0\core_core_core_fn_unit$next[12:0]$13751 - attribute \src "libresoc.v:192107.3-192108.61" - wire width 13 $0\core_core_core_fn_unit[12:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$13752 - attribute \src "libresoc.v:192121.3-192122.69" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13862 + attribute \src "libresoc.v:195047.3-195048.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13552 + attribute \src "libresoc.v:192656.7-192656.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14072 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13863 + attribute \src "libresoc.v:195049.3-195050.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13554 + attribute \src "libresoc.v:192660.7-192660.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14074 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13864 + attribute \src "libresoc.v:195051.3-195052.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13556 + attribute \src "libresoc.v:192664.7-192664.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14076 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13865 + attribute \src "libresoc.v:195053.3-195054.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13558 + attribute \src "libresoc.v:192668.7-192668.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14078 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13866 + attribute \src "libresoc.v:195057.3-195058.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13561 + attribute \src "libresoc.v:192672.7-192672.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14080 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13867 + attribute \src "libresoc.v:195059.3-195060.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13563 + attribute \src "libresoc.v:192676.7-192676.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14082 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13868 + attribute \src "libresoc.v:195061.3-195062.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13565 + attribute \src "libresoc.v:192680.7-192680.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14084 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13869 + attribute \src "libresoc.v:195045.3-195046.71" + wire $0\core_core_core_exc_$signal[0:0]$13550 + attribute \src "libresoc.v:192654.7-192654.42" + wire $0\core_core_core_exc_$signal[0:0]$14070 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$13870 + attribute \src "libresoc.v:195027.3-195028.61" + wire width 14 $0\core_core_core_fn_unit[13:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13871 + attribute \src "libresoc.v:195041.3-195042.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 32 $0\core_core_core_insn$next[31:0]$13753 - attribute \src "libresoc.v:192103.3-192104.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13872 + attribute \src "libresoc.v:195023.3-195024.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$13754 - attribute \src "libresoc.v:192105.3-192106.65" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13873 + attribute \src "libresoc.v:195025.3-195026.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_is_32bit$next[0:0]$13755 - attribute \src "libresoc.v:192153.3-192154.63" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_is_32bit$next[0:0]$13874 + attribute \src "libresoc.v:195073.3-195074.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 64 $0\core_core_core_msr$next[63:0]$13756 - attribute \src "libresoc.v:192099.3-192100.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13875 + attribute \src "libresoc.v:195019.3-195020.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_oe$next[0:0]$13757 - attribute \src "libresoc.v:192117.3-192118.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_oe$next[0:0]$13876 + attribute \src "libresoc.v:195037.3-195038.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_oe_ok$next[0:0]$13758 - attribute \src "libresoc.v:192119.3-192120.57" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_oe_ok$next[0:0]$13877 + attribute \src "libresoc.v:195039.3-195040.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_rc$next[0:0]$13759 - attribute \src "libresoc.v:192111.3-192112.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_rc$next[0:0]$13878 + attribute \src "libresoc.v:195031.3-195032.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_core_rc_ok$next[0:0]$13760 - attribute \src "libresoc.v:192113.3-192114.57" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_core_rc_ok$next[0:0]$13879 + attribute \src "libresoc.v:195035.3-195036.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$13761 - attribute \src "libresoc.v:192143.3-192144.63" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13880 + attribute \src "libresoc.v:195063.3-195064.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$13762 - attribute \src "libresoc.v:192123.3-192124.63" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$13881 + attribute \src "libresoc.v:195043.3-195044.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_cr_in1$next[6:0]$13763 - attribute \src "libresoc.v:192081.3-192082.49" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$13882 + attribute \src "libresoc.v:195001.3-195002.49" wire width 7 $0\core_core_cr_in1[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_cr_in1_ok$next[0:0]$13764 - attribute \src "libresoc.v:192083.3-192084.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13883 + attribute \src "libresoc.v:195003.3-195004.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_cr_in2$1$next[6:0]$13765 - attribute \src "libresoc.v:192089.3-192090.55" - wire width 7 $0\core_core_cr_in2$1[6:0]$13422 - attribute \src "libresoc.v:190011.13-190011.41" - wire width 7 $0\core_core_cr_in2$1[6:0]$13988 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_cr_in2$next[6:0]$13766 - attribute \src "libresoc.v:192085.3-192086.49" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$13884 + attribute \src "libresoc.v:195009.3-195010.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13530 + attribute \src "libresoc.v:192838.13-192838.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14101 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$13885 + attribute \src "libresoc.v:195005.3-195006.49" wire width 7 $0\core_core_cr_in2[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$13767 - attribute \src "libresoc.v:192091.3-192092.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13424 - attribute \src "libresoc.v:190019.7-190019.37" - wire $0\core_core_cr_in2_ok$2[0:0]$13991 - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_cr_in2_ok$next[0:0]$13768 - attribute \src "libresoc.v:192087.3-192088.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13886 + attribute \src "libresoc.v:195013.3-195014.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13533 + attribute \src "libresoc.v:192846.7-192846.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14104 + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_cr_in2_ok$next[0:0]$13887 + attribute \src "libresoc.v:195007.3-195008.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_cr_out$next[6:0]$13769 - attribute \src "libresoc.v:192095.3-192096.49" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_cr_out$next[6:0]$13888 + attribute \src "libresoc.v:195015.3-195016.49" wire width 7 $0\core_core_cr_out[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_cr_wr_ok$next[0:0]$13770 - attribute \src "libresoc.v:192151.3-192152.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_cr_wr_ok$next[0:0]$13889 + attribute \src "libresoc.v:195071.3-195072.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $0\core_core_dststep$next[6:0]$13496 - attribute \src "libresoc.v:192017.3-192018.51" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $0\core_core_dststep$next[6:0]$13609 + attribute \src "libresoc.v:194937.3-194938.51" wire width 7 $0\core_core_dststep[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_ea$next[6:0]$13771 - attribute \src "libresoc.v:192033.3-192034.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_ea$next[6:0]$13890 + attribute \src "libresoc.v:194953.3-194954.41" wire width 7 $0\core_core_ea[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $0\core_core_fast1$next[2:0]$13772 - attribute \src "libresoc.v:192063.3-192064.47" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_fast1$next[2:0]$13891 + attribute \src "libresoc.v:194983.3-194984.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_fast1_ok$next[0:0]$13773 - attribute \src "libresoc.v:192065.3-192066.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_fast1_ok$next[0:0]$13892 + attribute \src "libresoc.v:194985.3-194986.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $0\core_core_fast2$next[2:0]$13774 - attribute \src "libresoc.v:192067.3-192068.47" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_fast2$next[2:0]$13893 + attribute \src "libresoc.v:194987.3-194988.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_fast2_ok$next[0:0]$13775 - attribute \src "libresoc.v:192069.3-192070.53" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_fast2_ok$next[0:0]$13894 + attribute \src "libresoc.v:194991.3-194992.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $0\core_core_fasto1$next[2:0]$13776 - attribute \src "libresoc.v:192073.3-192074.49" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_fasto1$next[2:0]$13895 + attribute \src "libresoc.v:194993.3-194994.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $0\core_core_fasto2$next[2:0]$13777 - attribute \src "libresoc.v:192077.3-192078.49" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_fasto2$next[2:0]$13896 + attribute \src "libresoc.v:194997.3-194998.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_lk$next[0:0]$13778 - attribute \src "libresoc.v:192109.3-192110.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_lk$next[0:0]$13897 + attribute \src "libresoc.v:195029.3-195030.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $0\core_core_maxvl$next[6:0]$13497 - attribute \src "libresoc.v:192023.3-192024.47" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13610 + attribute \src "libresoc.v:194943.3-194944.47" wire width 7 $0\core_core_maxvl[6:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $0\core_core_pc$next[63:0]$13498 - attribute \src "libresoc.v:192181.3-192182.41" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $0\core_core_pc$next[63:0]$13611 + attribute \src "libresoc.v:194915.3-194916.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_reg1$next[6:0]$13779 - attribute \src "libresoc.v:192037.3-192038.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_reg1$next[6:0]$13898 + attribute \src "libresoc.v:194957.3-194958.45" wire width 7 $0\core_core_reg1[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_reg1_ok$next[0:0]$13780 - attribute \src "libresoc.v:192039.3-192040.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_reg1_ok$next[0:0]$13899 + attribute \src "libresoc.v:194959.3-194960.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_reg2$next[6:0]$13781 - attribute \src "libresoc.v:192041.3-192042.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_reg2$next[6:0]$13900 + attribute \src "libresoc.v:194961.3-194962.45" wire width 7 $0\core_core_reg2[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_reg2_ok$next[0:0]$13782 - attribute \src "libresoc.v:192043.3-192044.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_reg2_ok$next[0:0]$13901 + attribute \src "libresoc.v:194963.3-194964.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_reg3$next[6:0]$13783 - attribute \src "libresoc.v:192045.3-192046.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_reg3$next[6:0]$13902 + attribute \src "libresoc.v:194965.3-194966.45" wire width 7 $0\core_core_reg3[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_reg3_ok$next[0:0]$13784 - attribute \src "libresoc.v:192047.3-192048.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_reg3_ok$next[0:0]$13903 + attribute \src "libresoc.v:194969.3-194970.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $0\core_core_rego$next[6:0]$13785 - attribute \src "libresoc.v:192029.3-192030.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $0\core_core_rego$next[6:0]$13904 + attribute \src "libresoc.v:194949.3-194950.45" wire width 7 $0\core_core_rego[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 10 $0\core_core_spr1$next[9:0]$13786 - attribute \src "libresoc.v:192055.3-192056.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $0\core_core_spr1$next[9:0]$13905 + attribute \src "libresoc.v:194975.3-194976.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_core_spr1_ok$next[0:0]$13787 - attribute \src "libresoc.v:192057.3-192058.51" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_core_spr1_ok$next[0:0]$13906 + attribute \src "libresoc.v:194977.3-194978.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 10 $0\core_core_spro$next[9:0]$13788 - attribute \src "libresoc.v:192051.3-192052.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $0\core_core_spro$next[9:0]$13907 + attribute \src "libresoc.v:194971.3-194972.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $0\core_core_srcstep$next[6:0]$13499 - attribute \src "libresoc.v:192019.3-192020.51" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13612 + attribute \src "libresoc.v:194939.3-194940.51" wire width 7 $0\core_core_srcstep[6:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 2 $0\core_core_subvl$next[1:0]$13500 - attribute \src "libresoc.v:192015.3-192016.47" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $0\core_core_subvl$next[1:0]$13613 + attribute \src "libresoc.v:194935.3-194936.47" wire width 2 $0\core_core_subvl[1:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 2 $0\core_core_svstep$next[1:0]$13501 - attribute \src "libresoc.v:192013.3-192014.49" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $0\core_core_svstep$next[1:0]$13614 + attribute \src "libresoc.v:194933.3-194934.49" wire width 2 $0\core_core_svstep[1:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $0\core_core_vl$next[6:0]$13502 - attribute \src "libresoc.v:192021.3-192022.41" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $0\core_core_vl$next[6:0]$13615 + attribute \src "libresoc.v:194941.3-194942.41" wire width 7 $0\core_core_vl[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $0\core_core_xer_in$next[2:0]$13789 - attribute \src "libresoc.v:192059.3-192060.49" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $0\core_core_xer_in$next[2:0]$13908 + attribute \src "libresoc.v:194979.3-194980.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_cr_out_ok$next[0:0]$13790 - attribute \src "libresoc.v:192097.3-192098.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_cr_out_ok$next[0:0]$13909 + attribute \src "libresoc.v:195017.3-195018.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:192966.3-192975.6" - wire width 64 $0\core_data_i$12[63:0]$13554 - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:196021.3-196030.6" + wire width 64 $0\core_data_i$12[63:0]$13673 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $0\core_dec$next[63:0]$13503 - attribute \src "libresoc.v:192011.3-192012.33" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $0\core_dec$next[63:0]$13616 + attribute \src "libresoc.v:194931.3-194932.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:193079.3-193088.6" + attribute \src "libresoc.v:196134.3-196143.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:193089.3-193098.6" + attribute \src "libresoc.v:196144.3-196153.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_ea_ok$next[0:0]$13791 - attribute \src "libresoc.v:192035.3-192036.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_ea_ok$next[0:0]$13910 + attribute \src "libresoc.v:194955.3-194956.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire $0\core_eint$next[0:0]$13504 - attribute \src "libresoc.v:192009.3-192010.35" + attribute \src "libresoc.v:195788.3-195832.6" + wire $0\core_eint$next[0:0]$13617 + attribute \src "libresoc.v:194929.3-194930.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_fasto1_ok$next[0:0]$13792 - attribute \src "libresoc.v:192075.3-192076.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_fasto1_ok$next[0:0]$13911 + attribute \src "libresoc.v:194995.3-194996.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_fasto2_ok$next[0:0]$13793 - attribute \src "libresoc.v:192079.3-192080.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_fasto2_ok$next[0:0]$13912 + attribute \src "libresoc.v:194999.3-195000.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:193128.3-193137.6" + attribute \src "libresoc.v:196183.3-196192.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:193167.3-193176.6" + attribute \src "libresoc.v:196222.3-196231.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:193275.3-193289.6" - wire width 3 $0\core_issue__addr$13[2:0]$13594 - attribute \src "libresoc.v:193206.3-193220.6" + attribute \src "libresoc.v:196330.3-196344.6" + wire width 3 $0\core_issue__addr$13[2:0]$13713 + attribute \src "libresoc.v:196261.3-196275.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:193305.3-193319.6" + attribute \src "libresoc.v:196360.3-196374.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:193221.3-193235.6" + attribute \src "libresoc.v:196276.3-196290.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:193290.3-193304.6" + attribute \src "libresoc.v:196345.3-196359.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:193012.3-193027.6" + attribute \src "libresoc.v:196067.3-196082.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:192987.3-193011.6" + attribute \src "libresoc.v:196042.3-196066.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $0\core_msr$next[63:0]$13505 - attribute \src "libresoc.v:191999.3-192000.33" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $0\core_msr$next[63:0]$13618 + attribute \src "libresoc.v:194927.3-194928.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:193568.3-193583.6" + attribute \src "libresoc.v:196632.3-196647.6" wire width 3 $0\core_msr__ren[2:0] - attribute \src "libresoc.v:192841.3-192861.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13537 - attribute \src "libresoc.v:192159.3-192160.47" + attribute \src "libresoc.v:195833.3-195853.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13650 + attribute \src "libresoc.v:195099.3-195100.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_rego_ok$next[0:0]$13794 - attribute \src "libresoc.v:192031.3-192032.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_rego_ok$next[0:0]$13913 + attribute \src "libresoc.v:194951.3-194952.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_spro_ok$next[0:0]$13795 - attribute \src "libresoc.v:192053.3-192054.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_spro_ok$next[0:0]$13914 + attribute \src "libresoc.v:194973.3-194974.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:194091.3-194121.6" + attribute \src "libresoc.v:197141.3-197171.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:193419.3-193431.6" + attribute \src "libresoc.v:196474.3-196486.6" wire width 3 $0\core_sv__ren[2:0] - attribute \src "libresoc.v:192956.3-192965.6" - wire width 3 $0\core_wen$11[2:0]$13551 - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:195879.3-195903.6" + wire $0\core_sv_a_nz$next[0:0]$13660 + attribute \src "libresoc.v:195055.3-195056.41" + wire $0\core_sv_a_nz[0:0] + attribute \src "libresoc.v:196011.3-196020.6" + wire width 3 $0\core_wen$11[2:0]$13670 + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $0\core_wen[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $0\core_xer_out$next[0:0]$13796 - attribute \src "libresoc.v:192061.3-192062.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire $0\core_xer_out$next[0:0]$13915 + attribute \src "libresoc.v:194981.3-194982.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:192193.3-192194.43" + attribute \src "libresoc.v:195113.3-195114.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $0\cur_cur_dststep$next[6:0]$13635 - attribute \src "libresoc.v:192177.3-192178.47" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13754 + attribute \src "libresoc.v:195097.3-195098.47" wire width 7 $0\cur_cur_dststep[6:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $0\cur_cur_maxvl$next[6:0]$13636 - attribute \src "libresoc.v:192185.3-192186.43" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13755 + attribute \src "libresoc.v:195105.3-195106.43" wire width 7 $0\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $0\cur_cur_srcstep$next[6:0]$13637 - attribute \src "libresoc.v:192179.3-192180.47" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13756 + attribute \src "libresoc.v:195101.3-195102.47" wire width 7 $0\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $0\cur_cur_subvl$next[1:0]$13638 - attribute \src "libresoc.v:192175.3-192176.43" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13757 + attribute \src "libresoc.v:195095.3-195096.43" wire width 2 $0\cur_cur_subvl[1:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $0\cur_cur_svstep$next[1:0]$13639 - attribute \src "libresoc.v:192173.3-192174.45" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13758 + attribute \src "libresoc.v:195093.3-195094.45" wire width 2 $0\cur_cur_svstep[1:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $0\cur_cur_vl$next[6:0]$13640 - attribute \src "libresoc.v:192183.3-192184.37" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13759 + attribute \src "libresoc.v:195103.3-195104.37" wire width 7 $0\cur_cur_vl[6:0] - attribute \src "libresoc.v:193138.3-193146.6" - wire $0\d_cr_delay$next[0:0]$13576 - attribute \src "libresoc.v:192071.3-192072.37" + attribute \src "libresoc.v:196193.3-196201.6" + wire $0\d_cr_delay$next[0:0]$13695 + attribute \src "libresoc.v:194989.3-194990.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:193099.3-193107.6" - wire $0\d_reg_delay$next[0:0]$13570 - attribute \src "libresoc.v:192093.3-192094.39" + attribute \src "libresoc.v:196154.3-196162.6" + wire $0\d_reg_delay$next[0:0]$13689 + attribute \src "libresoc.v:195011.3-195012.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:193177.3-193185.6" - wire $0\d_xer_delay$next[0:0]$13582 - attribute \src "libresoc.v:192049.3-192050.39" + attribute \src "libresoc.v:196232.3-196240.6" + wire $0\d_xer_delay$next[0:0]$13701 + attribute \src "libresoc.v:194967.3-194968.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:194122.3-194152.6" + attribute \src "libresoc.v:197172.3-197202.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:193157.3-193166.6" + attribute \src "libresoc.v:196212.3-196221.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:193147.3-193156.6" + attribute \src "libresoc.v:196202.3-196211.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:193118.3-193127.6" + attribute \src "libresoc.v:196173.3-196182.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:193108.3-193117.6" + attribute \src "libresoc.v:196163.3-196172.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:193196.3-193205.6" + attribute \src "libresoc.v:196251.3-196260.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:193186.3-193195.6" + attribute \src "libresoc.v:196241.3-196250.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:192778.3-192786.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13490 - attribute \src "libresoc.v:192007.3-192008.45" + attribute \src "libresoc.v:195751.3-195759.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13597 + attribute \src "libresoc.v:194925.3-194926.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:193584.3-193592.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13620 - attribute \src "libresoc.v:192001.3-192002.39" + attribute \src "libresoc.v:196487.3-196495.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13736 + attribute \src "libresoc.v:194919.3-194920.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:192787.3-192795.6" - wire $0\dbg_dmi_req_i$next[0:0]$13493 - attribute \src "libresoc.v:192005.3-192006.43" + attribute \src "libresoc.v:195760.3-195768.6" + wire $0\dbg_dmi_req_i$next[0:0]$13600 + attribute \src "libresoc.v:194923.3-194924.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:193347.3-193355.6" - wire $0\dbg_dmi_we_i$next[0:0]$13604 - attribute \src "libresoc.v:192003.3-192004.41" + attribute \src "libresoc.v:196402.3-196410.6" + wire $0\dbg_dmi_we_i$next[0:0]$13723 + attribute \src "libresoc.v:194921.3-194922.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:193320.3-193335.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13599 - attribute \src "libresoc.v:191997.3-191998.41" + attribute \src "libresoc.v:196375.3-196390.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13718 + attribute \src "libresoc.v:194913.3-194914.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:194471.3-194479.6" - wire $0\dec2_cur_eint$next[0:0]$13943 - attribute \src "libresoc.v:192197.3-192198.43" + attribute \src "libresoc.v:195769.3-195777.6" + wire $0\dec2_cur_eint$next[0:0]$13603 + attribute \src "libresoc.v:195117.3-195118.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:193850.3-193870.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13683 - attribute \src "libresoc.v:192167.3-192168.41" + attribute \src "libresoc.v:196905.3-196925.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13802 + attribute \src "libresoc.v:195087.3-195088.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:193697.3-193717.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13630 - attribute \src "libresoc.v:192187.3-192188.39" + attribute \src "libresoc.v:196752.3-196772.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13749 + attribute \src "libresoc.v:195107.3-195108.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:193890.3-193920.6" - wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13692 - attribute \src "libresoc.v:192163.3-192164.53" + attribute \src "libresoc.v:196945.3-196975.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13811 + attribute \src "libresoc.v:195083.3-195084.53" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:194480.3-194489.6" - wire width 2 $0\delay$next[1:0]$13946 - attribute \src "libresoc.v:192195.3-192196.27" + attribute \src "libresoc.v:195778.3-195787.6" + wire width 2 $0\delay$next[1:0]$13606 + attribute \src "libresoc.v:195115.3-195116.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:193028.3-193062.6" - wire $0\exec_fsm_state$next[0:0]$13560 - attribute \src "libresoc.v:192115.3-192116.45" + attribute \src "libresoc.v:196083.3-196117.6" + wire $0\exec_fsm_state$next[0:0]$13679 + attribute \src "libresoc.v:195033.3-195034.45" wire $0\exec_fsm_state[0:0] - attribute \src "libresoc.v:192976.3-192986.6" + attribute \src "libresoc.v:196031.3-196041.6" wire $0\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:192887.3-192897.6" + attribute \src "libresoc.v:195942.3-195952.6" wire $0\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:192898.3-192913.6" + attribute \src "libresoc.v:195953.3-195968.6" wire $0\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:193063.3-193078.6" + attribute \src "libresoc.v:196118.3-196133.6" wire $0\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:193796.3-193849.6" - wire width 2 $0\fetch_fsm_state$next[1:0]$13675 - attribute \src "libresoc.v:192169.3-192170.47" + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13794 + attribute \src "libresoc.v:195089.3-195090.47" wire width 2 $0\fetch_fsm_state[1:0] - attribute \src "libresoc.v:194349.3-194359.6" + attribute \src "libresoc.v:197394.3-197404.6" wire $0\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:193921.3-193931.6" + attribute \src "libresoc.v:196976.3-196986.6" wire $0\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:193593.3-193603.6" + attribute \src "libresoc.v:196657.3-196667.6" wire $0\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:193994.3-194009.6" + attribute \src "libresoc.v:197044.3-197059.6" wire $0\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:193236.3-193263.6" - wire width 2 $0\fsm_state$next[1:0]$13589 - attribute \src "libresoc.v:192027.3-192028.35" + attribute \src "libresoc.v:196291.3-196318.6" + wire width 2 $0\fsm_state$next[1:0]$13708 + attribute \src "libresoc.v:194945.3-194946.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:193604.3-193619.6" + attribute \src "libresoc.v:196668.3-196683.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:193629.3-193662.6" + attribute \src "libresoc.v:196684.3-196717.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:193663.3-193696.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:189535.7-189535.20" + attribute \src "libresoc.v:192354.7-192354.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192935.3-192955.6" + attribute \src "libresoc.v:195904.3-195941.6" + wire $0\insn_done[0:0] + attribute \src "libresoc.v:195990.3-196010.6" wire $0\is_last[0:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $0\issue_fsm_state$next[2:0]$13700 - attribute \src "libresoc.v:192161.3-192162.47" + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $0\issue_fsm_state$next[2:0]$13819 + attribute \src "libresoc.v:195081.3-195082.47" wire width 3 $0\issue_fsm_state[2:0] - attribute \src "libresoc.v:193620.3-193628.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$13625 - attribute \src "libresoc.v:192201.3-192202.49" + attribute \src "libresoc.v:196648.3-196656.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13742 + attribute \src "libresoc.v:194917.3-194918.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:193787.3-193795.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13672 - attribute \src "libresoc.v:192199.3-192200.47" + attribute \src "libresoc.v:196812.3-196820.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13785 + attribute \src "libresoc.v:195119.3-195120.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:193757.3-193786.6" - wire $0\msr_read$next[0:0]$13666 - attribute \src "libresoc.v:192171.3-192172.33" + attribute \src "libresoc.v:196821.3-196850.6" + wire $0\msr_read$next[0:0]$13788 + attribute \src "libresoc.v:195091.3-195092.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:193264.3-193274.6" + attribute \src "libresoc.v:196319.3-196329.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $0\new_svstate_dststep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $0\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $0\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $0\new_svstate_subvl[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $0\new_svstate_svstep[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $0\new_svstate_vl[6:0] - attribute \src "libresoc.v:193336.3-193346.6" + attribute \src "libresoc.v:196391.3-196401.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:192914.3-192934.6" + attribute \src "libresoc.v:195969.3-195989.6" wire width 7 $0\next_srcstep[6:0] - attribute \src "libresoc.v:193871.3-193889.6" - wire width 64 $0\nia$next[63:0]$13688 - attribute \src "libresoc.v:192165.3-192166.23" + attribute \src "libresoc.v:196926.3-196944.6" + wire width 64 $0\nia$next[63:0]$13807 + attribute \src "libresoc.v:195085.3-195086.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:193365.3-193380.6" + attribute \src "libresoc.v:196420.3-196435.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $0\pc_changed$next[0:0]$13714 - attribute \src "libresoc.v:192157.3-192158.37" + attribute \src "libresoc.v:197203.3-197269.6" + wire $0\pc_changed$next[0:0]$13833 + attribute \src "libresoc.v:195079.3-195080.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:193356.3-193364.6" - wire $0\pc_ok_delay$next[0:0]$13607 - attribute \src "libresoc.v:192191.3-192192.39" + attribute \src "libresoc.v:196411.3-196419.6" + wire $0\pc_ok_delay$next[0:0]$13726 + attribute \src "libresoc.v:195111.3-195112.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:194282.3-194348.6" - wire $0\sv_changed$next[0:0]$13726 - attribute \src "libresoc.v:192155.3-192156.37" + attribute \src "libresoc.v:197327.3-197393.6" + wire $0\sv_changed$next[0:0]$13845 + attribute \src "libresoc.v:195075.3-195076.37" wire $0\sv_changed[0:0] - attribute \src "libresoc.v:193403.3-193418.6" + attribute \src "libresoc.v:196458.3-196473.6" wire width 64 $0\svstate[63:0] - attribute \src "libresoc.v:193394.3-193402.6" - wire $0\svstate_ok_delay$next[0:0]$13612 - attribute \src "libresoc.v:192189.3-192190.49" + attribute \src "libresoc.v:196449.3-196457.6" + wire $0\svstate_ok_delay$next[0:0]$13731 + attribute \src "libresoc.v:195109.3-195110.49" wire $0\svstate_ok_delay[0:0] - attribute \src "libresoc.v:194220.3-194281.6" + attribute \src "libresoc.v:197270.3-197326.6" wire $0\update_svstate[0:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $10\issue_fsm_state$next[2:0]$13710 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $1\core_asmcode$next[7:0]$13797 - attribute \src "libresoc.v:189799.13-189799.33" + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $10\issue_fsm_state$next[2:0]$13829 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $1\core_asmcode$next[7:0]$13916 + attribute \src "libresoc.v:192624.13-192624.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:192862.3-192886.6" - wire $1\core_bigendian_i$10$next[0:0]$13543 - attribute \src "libresoc.v:193381.3-193393.6" + attribute \src "libresoc.v:195854.3-195878.6" + wire $1\core_bigendian_i$10$next[0:0]$13656 + attribute \src "libresoc.v:196436.3-196448.6" wire width 3 $1\core_cia__ren[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 64 $1\core_core_core_cia$next[63:0]$13798 - attribute \src "libresoc.v:189813.14-189813.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $1\core_core_core_cia$next[63:0]$13917 + attribute \src "libresoc.v:192638.14-192638.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$13799 - attribute \src "libresoc.v:189817.13-189817.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$13918 + attribute \src "libresoc.v:192642.13-192642.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$13800 - attribute \src "libresoc.v:189821.7-189821.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$13919 + attribute \src "libresoc.v:192646.7-192646.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$13801 - attribute \src "libresoc.v:189825.13-189825.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$13920 + attribute \src "libresoc.v:192650.13-192650.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$13802 - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$13803 - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$13804 - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$13805 - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$13806 - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$13807 - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$13808 - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_exc_$signal$next[0:0]$13809 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 13 $1\core_core_core_fn_unit$next[12:0]$13810 - attribute \src "libresoc.v:189875.14-189875.47" - wire width 13 $1\core_core_core_fn_unit[12:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$13811 - attribute \src "libresoc.v:189883.13-189883.46" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$13921 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$13922 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$13923 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$13924 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$13925 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$13926 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$13927 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_exc_$signal$next[0:0]$13928 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$13929 + attribute \src "libresoc.v:192701.14-192701.47" + wire width 14 $1\core_core_core_fn_unit[13:0] + attribute \src "libresoc.v:197405.3-197515.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$13930 + attribute \src "libresoc.v:192709.13-192709.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 32 $1\core_core_core_insn$next[31:0]$13812 - attribute \src "libresoc.v:189887.14-189887.41" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 32 $1\core_core_core_insn$next[31:0]$13931 + attribute \src "libresoc.v:192713.14-192713.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$13813 - attribute \src "libresoc.v:189965.13-189965.45" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$13932 + attribute \src "libresoc.v:192792.13-192792.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_is_32bit$next[0:0]$13814 - attribute \src "libresoc.v:189969.7-189969.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_is_32bit$next[0:0]$13933 + attribute \src "libresoc.v:192796.7-192796.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 64 $1\core_core_core_msr$next[63:0]$13815 - attribute \src "libresoc.v:189973.14-189973.55" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $1\core_core_core_msr$next[63:0]$13934 + attribute \src "libresoc.v:192800.14-192800.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_oe$next[0:0]$13816 - attribute \src "libresoc.v:189977.7-189977.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_oe$next[0:0]$13935 + attribute \src "libresoc.v:192804.7-192804.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_oe_ok$next[0:0]$13817 - attribute \src "libresoc.v:189981.7-189981.34" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_oe_ok$next[0:0]$13936 + attribute \src "libresoc.v:192808.7-192808.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_rc$next[0:0]$13818 - attribute \src "libresoc.v:189985.7-189985.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_rc$next[0:0]$13937 + attribute \src "libresoc.v:192812.7-192812.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_core_rc_ok$next[0:0]$13819 - attribute \src "libresoc.v:189989.7-189989.34" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_core_rc_ok$next[0:0]$13938 + attribute \src "libresoc.v:192816.7-192816.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$13820 - attribute \src "libresoc.v:189993.14-189993.48" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$13939 + attribute \src "libresoc.v:192820.14-192820.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$13821 - attribute \src "libresoc.v:189997.13-189997.44" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$13940 + attribute \src "libresoc.v:192824.13-192824.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_cr_in1$next[6:0]$13822 - attribute \src "libresoc.v:190001.13-190001.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$13941 + attribute \src "libresoc.v:192828.13-192828.37" wire width 7 $1\core_core_cr_in1[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_cr_in1_ok$next[0:0]$13823 - attribute \src "libresoc.v:190005.7-190005.33" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_cr_in1_ok$next[0:0]$13942 + attribute \src "libresoc.v:192832.7-192832.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_cr_in2$1$next[6:0]$13824 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_cr_in2$next[6:0]$13825 - attribute \src "libresoc.v:190009.13-190009.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$13943 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$13944 + attribute \src "libresoc.v:192836.13-192836.37" wire width 7 $1\core_core_cr_in2[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$13826 - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_cr_in2_ok$next[0:0]$13827 - attribute \src "libresoc.v:190017.7-190017.33" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$13945 + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_cr_in2_ok$next[0:0]$13946 + attribute \src "libresoc.v:192844.7-192844.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_cr_out$next[6:0]$13828 - attribute \src "libresoc.v:190025.13-190025.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_cr_out$next[6:0]$13947 + attribute \src "libresoc.v:192852.13-192852.37" wire width 7 $1\core_core_cr_out[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_cr_wr_ok$next[0:0]$13829 - attribute \src "libresoc.v:190029.7-190029.32" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_cr_wr_ok$next[0:0]$13948 + attribute \src "libresoc.v:192856.7-192856.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $1\core_core_dststep$next[6:0]$13506 - attribute \src "libresoc.v:190033.13-190033.38" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $1\core_core_dststep$next[6:0]$13619 + attribute \src "libresoc.v:192860.13-192860.38" wire width 7 $1\core_core_dststep[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_ea$next[6:0]$13830 - attribute \src "libresoc.v:190037.13-190037.33" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_ea$next[6:0]$13949 + attribute \src "libresoc.v:192864.13-192864.33" wire width 7 $1\core_core_ea[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $1\core_core_fast1$next[2:0]$13831 - attribute \src "libresoc.v:190041.13-190041.35" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_fast1$next[2:0]$13950 + attribute \src "libresoc.v:192868.13-192868.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_fast1_ok$next[0:0]$13832 - attribute \src "libresoc.v:190045.7-190045.32" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_fast1_ok$next[0:0]$13951 + attribute \src "libresoc.v:192872.7-192872.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $1\core_core_fast2$next[2:0]$13833 - attribute \src "libresoc.v:190049.13-190049.35" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_fast2$next[2:0]$13952 + attribute \src "libresoc.v:192876.13-192876.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_fast2_ok$next[0:0]$13834 - attribute \src "libresoc.v:190053.7-190053.32" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_fast2_ok$next[0:0]$13953 + attribute \src "libresoc.v:192880.7-192880.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $1\core_core_fasto1$next[2:0]$13835 - attribute \src "libresoc.v:190057.13-190057.36" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_fasto1$next[2:0]$13954 + attribute \src "libresoc.v:192884.13-192884.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $1\core_core_fasto2$next[2:0]$13836 - attribute \src "libresoc.v:190061.13-190061.36" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_fasto2$next[2:0]$13955 + attribute \src "libresoc.v:192888.13-192888.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_lk$next[0:0]$13837 - attribute \src "libresoc.v:190065.7-190065.26" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_lk$next[0:0]$13956 + attribute \src "libresoc.v:192892.7-192892.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $1\core_core_maxvl$next[6:0]$13507 - attribute \src "libresoc.v:190069.13-190069.36" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13620 + attribute \src "libresoc.v:192896.13-192896.36" wire width 7 $1\core_core_maxvl[6:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $1\core_core_pc$next[63:0]$13508 - attribute \src "libresoc.v:190073.14-190073.49" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $1\core_core_pc$next[63:0]$13621 + attribute \src "libresoc.v:192900.14-192900.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_reg1$next[6:0]$13838 - attribute \src "libresoc.v:190077.13-190077.35" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_reg1$next[6:0]$13957 + attribute \src "libresoc.v:192904.13-192904.35" wire width 7 $1\core_core_reg1[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_reg1_ok$next[0:0]$13839 - attribute \src "libresoc.v:190081.7-190081.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_reg1_ok$next[0:0]$13958 + attribute \src "libresoc.v:192908.7-192908.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_reg2$next[6:0]$13840 - attribute \src "libresoc.v:190085.13-190085.35" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_reg2$next[6:0]$13959 + attribute \src "libresoc.v:192912.13-192912.35" wire width 7 $1\core_core_reg2[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_reg2_ok$next[0:0]$13841 - attribute \src "libresoc.v:190089.7-190089.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_reg2_ok$next[0:0]$13960 + attribute \src "libresoc.v:192916.7-192916.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_reg3$next[6:0]$13842 - attribute \src "libresoc.v:190093.13-190093.35" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_reg3$next[6:0]$13961 + attribute \src "libresoc.v:192920.13-192920.35" wire width 7 $1\core_core_reg3[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_reg3_ok$next[0:0]$13843 - attribute \src "libresoc.v:190097.7-190097.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_reg3_ok$next[0:0]$13962 + attribute \src "libresoc.v:192924.7-192924.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $1\core_core_rego$next[6:0]$13844 - attribute \src "libresoc.v:190101.13-190101.35" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $1\core_core_rego$next[6:0]$13963 + attribute \src "libresoc.v:192928.13-192928.35" wire width 7 $1\core_core_rego[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 10 $1\core_core_spr1$next[9:0]$13845 - attribute \src "libresoc.v:190219.13-190219.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $1\core_core_spr1$next[9:0]$13964 + attribute \src "libresoc.v:193046.13-193046.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_core_spr1_ok$next[0:0]$13846 - attribute \src "libresoc.v:190223.7-190223.31" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_core_spr1_ok$next[0:0]$13965 + attribute \src "libresoc.v:193050.7-193050.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 10 $1\core_core_spro$next[9:0]$13847 - attribute \src "libresoc.v:190341.13-190341.37" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $1\core_core_spro$next[9:0]$13966 + attribute \src "libresoc.v:193168.13-193168.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $1\core_core_srcstep$next[6:0]$13509 - attribute \src "libresoc.v:190345.13-190345.38" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13622 + attribute \src "libresoc.v:193172.13-193172.38" wire width 7 $1\core_core_srcstep[6:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 2 $1\core_core_subvl$next[1:0]$13510 - attribute \src "libresoc.v:190349.13-190349.35" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $1\core_core_subvl$next[1:0]$13623 + attribute \src "libresoc.v:193176.13-193176.35" wire width 2 $1\core_core_subvl[1:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 2 $1\core_core_svstep$next[1:0]$13511 - attribute \src "libresoc.v:190353.13-190353.36" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $1\core_core_svstep$next[1:0]$13624 + attribute \src "libresoc.v:193180.13-193180.36" wire width 2 $1\core_core_svstep[1:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $1\core_core_vl$next[6:0]$13512 - attribute \src "libresoc.v:190359.13-190359.33" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $1\core_core_vl$next[6:0]$13625 + attribute \src "libresoc.v:193186.13-193186.33" wire width 7 $1\core_core_vl[6:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $1\core_core_xer_in$next[2:0]$13848 - attribute \src "libresoc.v:190363.13-190363.36" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $1\core_core_xer_in$next[2:0]$13967 + attribute \src "libresoc.v:193190.13-193190.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_cr_out_ok$next[0:0]$13849 - attribute \src "libresoc.v:190371.7-190371.28" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_cr_out_ok$next[0:0]$13968 + attribute \src "libresoc.v:193198.7-193198.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:192966.3-192975.6" - wire width 64 $1\core_data_i$12[63:0]$13555 - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:196021.3-196030.6" + wire width 64 $1\core_data_i$12[63:0]$13674 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $1\core_dec$next[63:0]$13513 - attribute \src "libresoc.v:190387.14-190387.45" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $1\core_dec$next[63:0]$13626 + attribute \src "libresoc.v:193214.14-193214.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:193079.3-193088.6" + attribute \src "libresoc.v:196134.3-196143.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:193089.3-193098.6" + attribute \src "libresoc.v:196144.3-196153.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_ea_ok$next[0:0]$13850 - attribute \src "libresoc.v:190397.7-190397.24" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_ea_ok$next[0:0]$13969 + attribute \src "libresoc.v:193224.7-193224.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire $1\core_eint$next[0:0]$13514 - attribute \src "libresoc.v:190401.7-190401.23" + attribute \src "libresoc.v:195788.3-195832.6" + wire $1\core_eint$next[0:0]$13627 + attribute \src "libresoc.v:193228.7-193228.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_fasto1_ok$next[0:0]$13851 - attribute \src "libresoc.v:190405.7-190405.28" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_fasto1_ok$next[0:0]$13970 + attribute \src "libresoc.v:193232.7-193232.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_fasto2_ok$next[0:0]$13852 - attribute \src "libresoc.v:190409.7-190409.28" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_fasto2_ok$next[0:0]$13971 + attribute \src "libresoc.v:193236.7-193236.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:193128.3-193137.6" + attribute \src "libresoc.v:196183.3-196192.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:193167.3-193176.6" + attribute \src "libresoc.v:196222.3-196231.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:193275.3-193289.6" - wire width 3 $1\core_issue__addr$13[2:0]$13595 - attribute \src "libresoc.v:193206.3-193220.6" + attribute \src "libresoc.v:196330.3-196344.6" + wire width 3 $1\core_issue__addr$13[2:0]$13714 + attribute \src "libresoc.v:196261.3-196275.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:193305.3-193319.6" + attribute \src "libresoc.v:196360.3-196374.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:193221.3-193235.6" + attribute \src "libresoc.v:196276.3-196290.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:193290.3-193304.6" + attribute \src "libresoc.v:196345.3-196359.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:193012.3-193027.6" + attribute \src "libresoc.v:196067.3-196082.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:192987.3-193011.6" + attribute \src "libresoc.v:196042.3-196066.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $1\core_msr$next[63:0]$13515 - attribute \src "libresoc.v:190437.14-190437.45" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $1\core_msr$next[63:0]$13628 + attribute \src "libresoc.v:193264.14-193264.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:193568.3-193583.6" + attribute \src "libresoc.v:196632.3-196647.6" wire width 3 $1\core_msr__ren[2:0] - attribute \src "libresoc.v:192841.3-192861.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13538 - attribute \src "libresoc.v:190445.14-190445.37" + attribute \src "libresoc.v:195833.3-195853.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13651 + attribute \src "libresoc.v:193272.14-193272.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_rego_ok$next[0:0]$13853 - attribute \src "libresoc.v:190449.7-190449.26" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_rego_ok$next[0:0]$13972 + attribute \src "libresoc.v:193276.7-193276.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_spro_ok$next[0:0]$13854 - attribute \src "libresoc.v:190453.7-190453.26" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_spro_ok$next[0:0]$13973 + attribute \src "libresoc.v:193280.7-193280.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:194091.3-194121.6" + attribute \src "libresoc.v:197141.3-197171.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:193419.3-193431.6" + attribute \src "libresoc.v:196474.3-196486.6" wire width 3 $1\core_sv__ren[2:0] - attribute \src "libresoc.v:192956.3-192965.6" - wire width 3 $1\core_wen$11[2:0]$13552 - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:195879.3-195903.6" + wire $1\core_sv_a_nz$next[0:0]$13661 + attribute \src "libresoc.v:193292.7-193292.26" + wire $1\core_sv_a_nz[0:0] + attribute \src "libresoc.v:196011.3-196020.6" + wire width 3 $1\core_wen$11[2:0]$13671 + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $1\core_wen[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $1\core_xer_out$next[0:0]$13855 - attribute \src "libresoc.v:190471.7-190471.26" + attribute \src "libresoc.v:197405.3-197515.6" + wire $1\core_xer_out$next[0:0]$13974 + attribute \src "libresoc.v:193302.7-193302.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:190477.7-190477.30" + attribute \src "libresoc.v:193308.7-193308.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $1\cur_cur_dststep$next[6:0]$13641 - attribute \src "libresoc.v:190483.13-190483.36" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13760 + attribute \src "libresoc.v:193314.13-193314.36" wire width 7 $1\cur_cur_dststep[6:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $1\cur_cur_maxvl$next[6:0]$13642 - attribute \src "libresoc.v:190487.13-190487.34" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13761 + attribute \src "libresoc.v:193318.13-193318.34" wire width 7 $1\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $1\cur_cur_srcstep$next[6:0]$13643 - attribute \src "libresoc.v:190491.13-190491.36" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13762 + attribute \src "libresoc.v:193322.13-193322.36" wire width 7 $1\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $1\cur_cur_subvl$next[1:0]$13644 - attribute \src "libresoc.v:190495.13-190495.33" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13763 + attribute \src "libresoc.v:193326.13-193326.33" wire width 2 $1\cur_cur_subvl[1:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $1\cur_cur_svstep$next[1:0]$13645 - attribute \src "libresoc.v:190499.13-190499.34" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13764 + attribute \src "libresoc.v:193330.13-193330.34" wire width 2 $1\cur_cur_svstep[1:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $1\cur_cur_vl$next[6:0]$13646 - attribute \src "libresoc.v:190503.13-190503.31" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13765 + attribute \src "libresoc.v:193334.13-193334.31" wire width 7 $1\cur_cur_vl[6:0] - attribute \src "libresoc.v:193138.3-193146.6" - wire $1\d_cr_delay$next[0:0]$13577 - attribute \src "libresoc.v:190507.7-190507.24" + attribute \src "libresoc.v:196193.3-196201.6" + wire $1\d_cr_delay$next[0:0]$13696 + attribute \src "libresoc.v:193338.7-193338.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:193099.3-193107.6" - wire $1\d_reg_delay$next[0:0]$13571 - attribute \src "libresoc.v:190511.7-190511.25" + attribute \src "libresoc.v:196154.3-196162.6" + wire $1\d_reg_delay$next[0:0]$13690 + attribute \src "libresoc.v:193342.7-193342.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:193177.3-193185.6" - wire $1\d_xer_delay$next[0:0]$13583 - attribute \src "libresoc.v:190515.7-190515.25" + attribute \src "libresoc.v:196232.3-196240.6" + wire $1\d_xer_delay$next[0:0]$13702 + attribute \src "libresoc.v:193346.7-193346.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:194122.3-194152.6" + attribute \src "libresoc.v:197172.3-197202.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:193157.3-193166.6" + attribute \src "libresoc.v:196212.3-196221.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:193147.3-193156.6" + attribute \src "libresoc.v:196202.3-196211.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:193118.3-193127.6" + attribute \src "libresoc.v:196173.3-196182.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:193108.3-193117.6" + attribute \src "libresoc.v:196163.3-196172.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:193196.3-193205.6" + attribute \src "libresoc.v:196251.3-196260.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:193186.3-193195.6" + attribute \src "libresoc.v:196241.3-196250.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:192778.3-192786.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13491 - attribute \src "libresoc.v:190563.13-190563.34" + attribute \src "libresoc.v:195751.3-195759.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13598 + attribute \src "libresoc.v:193394.13-193394.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:193584.3-193592.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13621 - attribute \src "libresoc.v:190567.14-190567.48" + attribute \src "libresoc.v:196487.3-196495.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13737 + attribute \src "libresoc.v:193398.14-193398.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:192787.3-192795.6" - wire $1\dbg_dmi_req_i$next[0:0]$13494 - attribute \src "libresoc.v:190573.7-190573.27" + attribute \src "libresoc.v:195760.3-195768.6" + wire $1\dbg_dmi_req_i$next[0:0]$13601 + attribute \src "libresoc.v:193404.7-193404.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:193347.3-193355.6" - wire $1\dbg_dmi_we_i$next[0:0]$13605 - attribute \src "libresoc.v:190577.7-190577.26" + attribute \src "libresoc.v:196402.3-196410.6" + wire $1\dbg_dmi_we_i$next[0:0]$13724 + attribute \src "libresoc.v:193408.7-193408.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:193320.3-193335.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13600 - attribute \src "libresoc.v:190631.14-190631.49" + attribute \src "libresoc.v:196375.3-196390.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13719 + attribute \src "libresoc.v:193462.14-193462.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:194471.3-194479.6" - wire $1\dec2_cur_eint$next[0:0]$13944 - attribute \src "libresoc.v:190635.7-190635.27" + attribute \src "libresoc.v:195769.3-195777.6" + wire $1\dec2_cur_eint$next[0:0]$13604 + attribute \src "libresoc.v:193466.7-193466.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:193850.3-193870.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13684 - attribute \src "libresoc.v:190639.14-190639.49" + attribute \src "libresoc.v:196905.3-196925.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13803 + attribute \src "libresoc.v:193470.14-193470.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:193697.3-193717.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13631 - attribute \src "libresoc.v:190643.14-190643.48" + attribute \src "libresoc.v:196752.3-196772.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13750 + attribute \src "libresoc.v:193474.14-193474.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:193890.3-193920.6" - wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13693 - attribute \src "libresoc.v:190793.14-190793.40" + attribute \src "libresoc.v:196945.3-196975.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13812 + attribute \src "libresoc.v:193626.14-193626.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:194480.3-194489.6" - wire width 2 $1\delay$next[1:0]$13947 - attribute \src "libresoc.v:191061.13-191061.25" + attribute \src "libresoc.v:195778.3-195787.6" + wire width 2 $1\delay$next[1:0]$13607 + attribute \src "libresoc.v:193896.13-193896.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:193028.3-193062.6" - wire $1\exec_fsm_state$next[0:0]$13561 - attribute \src "libresoc.v:191077.7-191077.28" + attribute \src "libresoc.v:196083.3-196117.6" + wire $1\exec_fsm_state$next[0:0]$13680 + attribute \src "libresoc.v:193912.7-193912.28" wire $1\exec_fsm_state[0:0] - attribute \src "libresoc.v:192976.3-192986.6" + attribute \src "libresoc.v:196031.3-196041.6" wire $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:192887.3-192897.6" + attribute \src "libresoc.v:195942.3-195952.6" wire $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:192898.3-192913.6" + attribute \src "libresoc.v:195953.3-195968.6" wire $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:193063.3-193078.6" + attribute \src "libresoc.v:196118.3-196133.6" wire $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:193796.3-193849.6" - wire width 2 $1\fetch_fsm_state$next[1:0]$13676 - attribute \src "libresoc.v:191089.13-191089.35" + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13795 + attribute \src "libresoc.v:193924.13-193924.35" wire width 2 $1\fetch_fsm_state[1:0] - attribute \src "libresoc.v:194349.3-194359.6" + attribute \src "libresoc.v:197394.3-197404.6" wire $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:193921.3-193931.6" + attribute \src "libresoc.v:196976.3-196986.6" wire $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:193593.3-193603.6" + attribute \src "libresoc.v:196657.3-196667.6" wire $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:193994.3-194009.6" + attribute \src "libresoc.v:197044.3-197059.6" wire $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:193236.3-193263.6" - wire width 2 $1\fsm_state$next[1:0]$13590 - attribute \src "libresoc.v:191101.13-191101.29" + attribute \src "libresoc.v:196291.3-196318.6" + wire width 2 $1\fsm_state$next[1:0]$13709 + attribute \src "libresoc.v:193936.13-193936.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:193604.3-193619.6" + attribute \src "libresoc.v:196668.3-196683.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:193629.3-193662.6" + attribute \src "libresoc.v:196684.3-196717.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:193663.3-193696.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:192935.3-192955.6" + attribute \src "libresoc.v:195904.3-195941.6" + wire $1\insn_done[0:0] + attribute \src "libresoc.v:195990.3-196010.6" wire $1\is_last[0:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $1\issue_fsm_state$next[2:0]$13701 - attribute \src "libresoc.v:191357.13-191357.35" + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $1\issue_fsm_state$next[2:0]$13820 + attribute \src "libresoc.v:194196.13-194196.35" wire width 3 $1\issue_fsm_state[2:0] - attribute \src "libresoc.v:193620.3-193628.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$13626 - attribute \src "libresoc.v:191361.7-191361.30" + attribute \src "libresoc.v:196648.3-196656.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13743 + attribute \src "libresoc.v:194200.7-194200.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:193787.3-193795.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13673 - attribute \src "libresoc.v:191369.14-191369.52" + attribute \src "libresoc.v:196812.3-196820.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13786 + attribute \src "libresoc.v:194208.14-194208.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:193757.3-193786.6" - wire $1\msr_read$next[0:0]$13667 - attribute \src "libresoc.v:191425.7-191425.22" + attribute \src "libresoc.v:196821.3-196850.6" + wire $1\msr_read$next[0:0]$13789 + attribute \src "libresoc.v:194266.7-194266.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:193264.3-193274.6" + attribute \src "libresoc.v:196319.3-196329.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $1\new_svstate_dststep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $1\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $1\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $1\new_svstate_subvl[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $1\new_svstate_svstep[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:193336.3-193346.6" + attribute \src "libresoc.v:196391.3-196401.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:192914.3-192934.6" + attribute \src "libresoc.v:195969.3-195989.6" wire width 7 $1\next_srcstep[6:0] - attribute \src "libresoc.v:193871.3-193889.6" - wire width 64 $1\nia$next[63:0]$13689 - attribute \src "libresoc.v:191463.14-191463.40" + attribute \src "libresoc.v:196926.3-196944.6" + wire width 64 $1\nia$next[63:0]$13808 + attribute \src "libresoc.v:194304.14-194304.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:193365.3-193380.6" + attribute \src "libresoc.v:196420.3-196435.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $1\pc_changed$next[0:0]$13715 - attribute \src "libresoc.v:191469.7-191469.24" + attribute \src "libresoc.v:197203.3-197269.6" + wire $1\pc_changed$next[0:0]$13834 + attribute \src "libresoc.v:194310.7-194310.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:193356.3-193364.6" - wire $1\pc_ok_delay$next[0:0]$13608 - attribute \src "libresoc.v:191479.7-191479.25" + attribute \src "libresoc.v:196411.3-196419.6" + wire $1\pc_ok_delay$next[0:0]$13727 + attribute \src "libresoc.v:194320.7-194320.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:194282.3-194348.6" - wire $1\sv_changed$next[0:0]$13727 - attribute \src "libresoc.v:191851.7-191851.24" + attribute \src "libresoc.v:197327.3-197393.6" + wire $1\sv_changed$next[0:0]$13846 + attribute \src "libresoc.v:194764.7-194764.24" wire $1\sv_changed[0:0] - attribute \src "libresoc.v:193403.3-193418.6" + attribute \src "libresoc.v:196458.3-196473.6" wire width 64 $1\svstate[63:0] - attribute \src "libresoc.v:193394.3-193402.6" - wire $1\svstate_ok_delay$next[0:0]$13613 - attribute \src "libresoc.v:191861.7-191861.30" + attribute \src "libresoc.v:196449.3-196457.6" + wire $1\svstate_ok_delay$next[0:0]$13732 + attribute \src "libresoc.v:194774.7-194774.30" wire $1\svstate_ok_delay[0:0] - attribute \src "libresoc.v:194220.3-194281.6" + attribute \src "libresoc.v:197270.3-197326.6" wire $1\update_svstate[0:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $2\core_asmcode$next[7:0]$13856 - attribute \src "libresoc.v:192862.3-192886.6" - wire $2\core_bigendian_i$10$next[0:0]$13544 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 64 $2\core_core_core_cia$next[63:0]$13857 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$13858 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$13859 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$13860 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$13861 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$13862 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$13863 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$13864 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$13865 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$13866 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$13867 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_exc_$signal$next[0:0]$13868 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 13 $2\core_core_core_fn_unit$next[12:0]$13869 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$13870 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 32 $2\core_core_core_insn$next[31:0]$13871 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$13872 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_is_32bit$next[0:0]$13873 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 64 $2\core_core_core_msr$next[63:0]$13874 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_oe$next[0:0]$13875 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_oe_ok$next[0:0]$13876 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_rc$next[0:0]$13877 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_core_rc_ok$next[0:0]$13878 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$13879 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$13880 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_cr_in1$next[6:0]$13881 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_cr_in1_ok$next[0:0]$13882 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_cr_in2$1$next[6:0]$13883 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_cr_in2$next[6:0]$13884 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$13885 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_cr_in2_ok$next[0:0]$13886 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_cr_out$next[6:0]$13887 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_cr_wr_ok$next[0:0]$13888 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $2\core_core_dststep$next[6:0]$13516 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_ea$next[6:0]$13889 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $2\core_core_fast1$next[2:0]$13890 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_fast1_ok$next[0:0]$13891 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $2\core_core_fast2$next[2:0]$13892 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_fast2_ok$next[0:0]$13893 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $2\core_core_fasto1$next[2:0]$13894 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $2\core_core_fasto2$next[2:0]$13895 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_lk$next[0:0]$13896 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $2\core_core_maxvl$next[6:0]$13517 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $2\core_core_pc$next[63:0]$13518 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_reg1$next[6:0]$13897 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_reg1_ok$next[0:0]$13898 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_reg2$next[6:0]$13899 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_reg2_ok$next[0:0]$13900 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_reg3$next[6:0]$13901 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_reg3_ok$next[0:0]$13902 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 7 $2\core_core_rego$next[6:0]$13903 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 10 $2\core_core_spr1$next[9:0]$13904 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_core_spr1_ok$next[0:0]$13905 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 10 $2\core_core_spro$next[9:0]$13906 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $2\core_core_srcstep$next[6:0]$13519 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 2 $2\core_core_subvl$next[1:0]$13520 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 2 $2\core_core_svstep$next[1:0]$13521 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $2\core_core_vl$next[6:0]$13522 - attribute \src "libresoc.v:194360.3-194470.6" - wire width 3 $2\core_core_xer_in$next[2:0]$13907 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_cr_out_ok$next[0:0]$13908 - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $2\core_asmcode$next[7:0]$13975 + attribute \src "libresoc.v:195854.3-195878.6" + wire $2\core_bigendian_i$10$next[0:0]$13657 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $2\core_core_core_cia$next[63:0]$13976 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$13977 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$13978 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$13979 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$13980 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$13981 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$13982 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$13983 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$13984 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$13985 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$13986 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_exc_$signal$next[0:0]$13987 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 14 $2\core_core_core_fn_unit$next[13:0]$13988 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$13989 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 32 $2\core_core_core_insn$next[31:0]$13990 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$13991 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_is_32bit$next[0:0]$13992 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 64 $2\core_core_core_msr$next[63:0]$13993 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_oe$next[0:0]$13994 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_oe_ok$next[0:0]$13995 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_rc$next[0:0]$13996 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_core_rc_ok$next[0:0]$13997 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$13998 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$13999 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14000 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14001 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14002 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14003 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14004 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14005 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14006 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14007 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $2\core_core_dststep$next[6:0]$13629 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_ea$next[6:0]$14008 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_fast1$next[2:0]$14009 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_fast1_ok$next[0:0]$14010 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_fast2$next[2:0]$14011 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_fast2_ok$next[0:0]$14012 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14013 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14014 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_lk$next[0:0]$14015 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13630 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $2\core_core_pc$next[63:0]$13631 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_reg1$next[6:0]$14016 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_reg1_ok$next[0:0]$14017 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_reg2$next[6:0]$14018 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_reg2_ok$next[0:0]$14019 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_reg3$next[6:0]$14020 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_reg3_ok$next[0:0]$14021 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 7 $2\core_core_rego$next[6:0]$14022 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $2\core_core_spr1$next[9:0]$14023 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_core_spr1_ok$next[0:0]$14024 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 10 $2\core_core_spro$next[9:0]$14025 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13632 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $2\core_core_subvl$next[1:0]$13633 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $2\core_core_svstep$next[1:0]$13634 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $2\core_core_vl$next[6:0]$13635 + attribute \src "libresoc.v:197405.3-197515.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14026 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_cr_out_ok$next[0:0]$14027 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $2\core_dec$next[63:0]$13523 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_ea_ok$next[0:0]$13909 - attribute \src "libresoc.v:192796.3-192840.6" - wire $2\core_eint$next[0:0]$13524 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_fasto1_ok$next[0:0]$13910 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_fasto2_ok$next[0:0]$13911 - attribute \src "libresoc.v:193012.3-193027.6" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $2\core_dec$next[63:0]$13636 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_ea_ok$next[0:0]$14028 + attribute \src "libresoc.v:195788.3-195832.6" + wire $2\core_eint$next[0:0]$13637 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_fasto1_ok$next[0:0]$14029 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_fasto2_ok$next[0:0]$14030 + attribute \src "libresoc.v:196067.3-196082.6" wire $2\core_issue_i[0:0] - attribute \src "libresoc.v:192987.3-193011.6" + attribute \src "libresoc.v:196042.3-196066.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $2\core_msr$next[63:0]$13525 - attribute \src "libresoc.v:193568.3-193583.6" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $2\core_msr$next[63:0]$13638 + attribute \src "libresoc.v:196632.3-196647.6" wire width 3 $2\core_msr__ren[2:0] - attribute \src "libresoc.v:192841.3-192861.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13539 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_rego_ok$next[0:0]$13912 - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_spro_ok$next[0:0]$13913 - attribute \src "libresoc.v:194091.3-194121.6" + attribute \src "libresoc.v:195833.3-195853.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13652 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_rego_ok$next[0:0]$14031 + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_spro_ok$next[0:0]$14032 + attribute \src "libresoc.v:197141.3-197171.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:195879.3-195903.6" + wire $2\core_sv_a_nz$next[0:0]$13662 + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $2\core_wen[2:0] - attribute \src "libresoc.v:194360.3-194470.6" - wire $2\core_xer_out$next[0:0]$13914 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $2\cur_cur_dststep$next[6:0]$13647 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $2\cur_cur_maxvl$next[6:0]$13648 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $2\cur_cur_srcstep$next[6:0]$13649 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $2\cur_cur_subvl$next[1:0]$13650 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $2\cur_cur_svstep$next[1:0]$13651 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $2\cur_cur_vl$next[6:0]$13652 - attribute \src "libresoc.v:194122.3-194152.6" + attribute \src "libresoc.v:197405.3-197515.6" + wire $2\core_xer_out$next[0:0]$14033 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13766 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13767 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13768 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13769 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13770 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13771 + attribute \src "libresoc.v:197172.3-197202.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:193320.3-193335.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13601 - attribute \src "libresoc.v:193850.3-193870.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13685 - attribute \src "libresoc.v:193697.3-193717.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13632 - attribute \src "libresoc.v:193890.3-193920.6" - wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13694 - attribute \src "libresoc.v:193028.3-193062.6" - wire $2\exec_fsm_state$next[0:0]$13562 - attribute \src "libresoc.v:192898.3-192913.6" + attribute \src "libresoc.v:196375.3-196390.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13720 + attribute \src "libresoc.v:196905.3-196925.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13804 + attribute \src "libresoc.v:196752.3-196772.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13751 + attribute \src "libresoc.v:196945.3-196975.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13813 + attribute \src "libresoc.v:196083.3-196117.6" + wire $2\exec_fsm_state$next[0:0]$13681 + attribute \src "libresoc.v:195953.3-195968.6" wire $2\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:193063.3-193078.6" + attribute \src "libresoc.v:196118.3-196133.6" wire $2\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:193796.3-193849.6" - wire width 2 $2\fetch_fsm_state$next[1:0]$13677 - attribute \src "libresoc.v:193994.3-194009.6" + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13796 + attribute \src "libresoc.v:197044.3-197059.6" wire $2\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:193236.3-193263.6" - wire width 2 $2\fsm_state$next[1:0]$13591 - attribute \src "libresoc.v:193604.3-193619.6" + attribute \src "libresoc.v:196291.3-196318.6" + wire width 2 $2\fsm_state$next[1:0]$13710 + attribute \src "libresoc.v:196668.3-196683.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:193629.3-193662.6" + attribute \src "libresoc.v:196684.3-196717.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:193663.3-193696.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:192935.3-192955.6" + attribute \src "libresoc.v:195904.3-195941.6" + wire $2\insn_done[0:0] + attribute \src "libresoc.v:195990.3-196010.6" wire $2\is_last[0:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $2\issue_fsm_state$next[2:0]$13702 - attribute \src "libresoc.v:193757.3-193786.6" - wire $2\msr_read$next[0:0]$13668 - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $2\issue_fsm_state$next[2:0]$13821 + attribute \src "libresoc.v:196821.3-196850.6" + wire $2\msr_read$next[0:0]$13790 + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $2\new_svstate_dststep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $2\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $2\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $2\new_svstate_subvl[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $2\new_svstate_svstep[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $2\new_svstate_vl[6:0] - attribute \src "libresoc.v:192914.3-192934.6" + attribute \src "libresoc.v:195969.3-195989.6" wire width 7 $2\next_srcstep[6:0] - attribute \src "libresoc.v:193871.3-193889.6" - wire width 64 $2\nia$next[63:0]$13690 - attribute \src "libresoc.v:193365.3-193380.6" + attribute \src "libresoc.v:196926.3-196944.6" + wire width 64 $2\nia$next[63:0]$13809 + attribute \src "libresoc.v:196420.3-196435.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $2\pc_changed$next[0:0]$13716 - attribute \src "libresoc.v:194282.3-194348.6" - wire $2\sv_changed$next[0:0]$13728 - attribute \src "libresoc.v:193403.3-193418.6" + attribute \src "libresoc.v:197203.3-197269.6" + wire $2\pc_changed$next[0:0]$13835 + attribute \src "libresoc.v:197327.3-197393.6" + wire $2\sv_changed$next[0:0]$13847 + attribute \src "libresoc.v:196458.3-196473.6" wire width 64 $2\svstate[63:0] - attribute \src "libresoc.v:194220.3-194281.6" + attribute \src "libresoc.v:197270.3-197326.6" wire $2\update_svstate[0:0] - attribute \src "libresoc.v:192862.3-192886.6" - wire $3\core_bigendian_i$10$next[0:0]$13545 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$13915 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$13916 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$13917 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$13918 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$13919 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$13920 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$13921 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$13922 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_exc_$signal$next[0:0]$13923 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_oe_ok$next[0:0]$13924 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_core_rc_ok$next[0:0]$13925 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_cr_in1_ok$next[0:0]$13926 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$13927 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_cr_in2_ok$next[0:0]$13928 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_cr_wr_ok$next[0:0]$13929 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $3\core_core_dststep$next[6:0]$13526 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_fast1_ok$next[0:0]$13930 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_fast2_ok$next[0:0]$13931 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $3\core_core_maxvl$next[6:0]$13527 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $3\core_core_pc$next[63:0]$13528 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_reg1_ok$next[0:0]$13932 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_reg2_ok$next[0:0]$13933 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_reg3_ok$next[0:0]$13934 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_core_spr1_ok$next[0:0]$13935 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $3\core_core_srcstep$next[6:0]$13529 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 2 $3\core_core_subvl$next[1:0]$13530 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 2 $3\core_core_svstep$next[1:0]$13531 - attribute \src "libresoc.v:192796.3-192840.6" - wire width 7 $3\core_core_vl$next[6:0]$13532 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_cr_out_ok$next[0:0]$13936 - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:195854.3-195878.6" + wire $3\core_bigendian_i$10$next[0:0]$13658 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14034 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14035 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14036 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14037 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14038 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14039 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14040 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14041 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14042 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_oe_ok$next[0:0]$14043 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_core_rc_ok$next[0:0]$14044 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14045 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14046 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14047 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14048 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $3\core_core_dststep$next[6:0]$13639 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_fast1_ok$next[0:0]$14049 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_fast2_ok$next[0:0]$14050 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13640 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $3\core_core_pc$next[63:0]$13641 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_reg1_ok$next[0:0]$14051 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_reg2_ok$next[0:0]$14052 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_reg3_ok$next[0:0]$14053 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_core_spr1_ok$next[0:0]$14054 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13642 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $3\core_core_subvl$next[1:0]$13643 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 2 $3\core_core_svstep$next[1:0]$13644 + attribute \src "libresoc.v:195788.3-195832.6" + wire width 7 $3\core_core_vl$next[6:0]$13645 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_cr_out_ok$next[0:0]$14055 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $3\core_dec$next[63:0]$13533 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_ea_ok$next[0:0]$13937 - attribute \src "libresoc.v:192796.3-192840.6" - wire $3\core_eint$next[0:0]$13534 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_fasto1_ok$next[0:0]$13938 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_fasto2_ok$next[0:0]$13939 - attribute \src "libresoc.v:192987.3-193011.6" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $3\core_dec$next[63:0]$13646 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_ea_ok$next[0:0]$14056 + attribute \src "libresoc.v:195788.3-195832.6" + wire $3\core_eint$next[0:0]$13647 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_fasto1_ok$next[0:0]$14057 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_fasto2_ok$next[0:0]$14058 + attribute \src "libresoc.v:196042.3-196066.6" wire $3\core_ivalid_i[0:0] - attribute \src "libresoc.v:192796.3-192840.6" - wire width 64 $3\core_msr$next[63:0]$13535 - attribute \src "libresoc.v:192841.3-192861.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13540 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_rego_ok$next[0:0]$13940 - attribute \src "libresoc.v:194360.3-194470.6" - wire $3\core_spro_ok$next[0:0]$13941 - attribute \src "libresoc.v:194091.3-194121.6" + attribute \src "libresoc.v:195788.3-195832.6" + wire width 64 $3\core_msr$next[63:0]$13648 + attribute \src "libresoc.v:195833.3-195853.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13653 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_rego_ok$next[0:0]$14059 + attribute \src "libresoc.v:197405.3-197515.6" + wire $3\core_spro_ok$next[0:0]$14060 + attribute \src "libresoc.v:197141.3-197171.6" wire $3\core_stopped_i[0:0] - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:195879.3-195903.6" + wire $3\core_sv_a_nz$next[0:0]$13663 + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $3\core_wen[2:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $3\cur_cur_dststep$next[6:0]$13653 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $3\cur_cur_maxvl$next[6:0]$13654 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $3\cur_cur_srcstep$next[6:0]$13655 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $3\cur_cur_subvl$next[1:0]$13656 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $3\cur_cur_svstep$next[1:0]$13657 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $3\cur_cur_vl$next[6:0]$13658 - attribute \src "libresoc.v:194122.3-194152.6" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13772 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13773 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13774 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13775 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13776 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13777 + attribute \src "libresoc.v:197172.3-197202.6" wire $3\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:193850.3-193870.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13686 - attribute \src "libresoc.v:193697.3-193717.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13633 - attribute \src "libresoc.v:193890.3-193920.6" - wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13695 - attribute \src "libresoc.v:193028.3-193062.6" - wire $3\exec_fsm_state$next[0:0]$13563 - attribute \src "libresoc.v:193796.3-193849.6" - wire width 2 $3\fetch_fsm_state$next[1:0]$13678 - attribute \src "libresoc.v:193629.3-193662.6" + attribute \src "libresoc.v:196905.3-196925.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13805 + attribute \src "libresoc.v:196752.3-196772.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13752 + attribute \src "libresoc.v:196945.3-196975.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13814 + attribute \src "libresoc.v:196083.3-196117.6" + wire $3\exec_fsm_state$next[0:0]$13682 + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13797 + attribute \src "libresoc.v:196684.3-196717.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:193663.3-193696.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:192935.3-192955.6" + attribute \src "libresoc.v:195904.3-195941.6" + wire $3\insn_done[0:0] + attribute \src "libresoc.v:195990.3-196010.6" wire $3\is_last[0:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $3\issue_fsm_state$next[2:0]$13703 - attribute \src "libresoc.v:193757.3-193786.6" - wire $3\msr_read$next[0:0]$13669 - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $3\issue_fsm_state$next[2:0]$13822 + attribute \src "libresoc.v:196821.3-196850.6" + wire $3\msr_read$next[0:0]$13791 + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $3\new_svstate_dststep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $3\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $3\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $3\new_svstate_subvl[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $3\new_svstate_svstep[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $3\new_svstate_vl[6:0] - attribute \src "libresoc.v:192914.3-192934.6" + attribute \src "libresoc.v:195969.3-195989.6" wire width 7 $3\next_srcstep[6:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $3\pc_changed$next[0:0]$13717 - attribute \src "libresoc.v:194282.3-194348.6" - wire $3\sv_changed$next[0:0]$13729 - attribute \src "libresoc.v:194220.3-194281.6" + attribute \src "libresoc.v:197203.3-197269.6" + wire $3\pc_changed$next[0:0]$13836 + attribute \src "libresoc.v:197327.3-197393.6" + wire $3\sv_changed$next[0:0]$13848 + attribute \src "libresoc.v:197270.3-197326.6" wire $3\update_svstate[0:0] - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $4\core_data_i[63:0] - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $4\core_wen[2:0] - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $4\cur_cur_dststep$next[6:0]$13659 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $4\cur_cur_maxvl$next[6:0]$13660 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $4\cur_cur_srcstep$next[6:0]$13661 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $4\cur_cur_subvl$next[1:0]$13662 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 2 $4\cur_cur_svstep$next[1:0]$13663 - attribute \src "libresoc.v:193718.3-193756.6" - wire width 7 $4\cur_cur_vl$next[6:0]$13664 - attribute \src "libresoc.v:193028.3-193062.6" - wire $4\exec_fsm_state$next[0:0]$13564 - attribute \src "libresoc.v:193796.3-193849.6" - wire width 2 $4\fetch_fsm_state$next[1:0]$13679 - attribute \src "libresoc.v:193629.3-193662.6" + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13778 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13779 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13780 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13781 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13782 + attribute \src "libresoc.v:196773.3-196811.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13783 + attribute \src "libresoc.v:196083.3-196117.6" + wire $4\exec_fsm_state$next[0:0]$13683 + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13798 + attribute \src "libresoc.v:196684.3-196717.6" wire $4\imem_a_valid_i[0:0] - attribute \src "libresoc.v:193663.3-193696.6" + attribute \src "libresoc.v:196718.3-196751.6" wire $4\imem_f_valid_i[0:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $4\issue_fsm_state$next[2:0]$13704 - attribute \src "libresoc.v:193757.3-193786.6" - wire $4\msr_read$next[0:0]$13670 - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:195904.3-195941.6" + wire $4\insn_done[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $4\issue_fsm_state$next[2:0]$13823 + attribute \src "libresoc.v:196821.3-196850.6" + wire $4\msr_read$next[0:0]$13792 + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $4\new_svstate_dststep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $4\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $4\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $4\new_svstate_subvl[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $4\new_svstate_svstep[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $4\new_svstate_vl[6:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $4\pc_changed$next[0:0]$13718 - attribute \src "libresoc.v:194282.3-194348.6" - wire $4\sv_changed$next[0:0]$13730 - attribute \src "libresoc.v:194220.3-194281.6" + attribute \src "libresoc.v:197203.3-197269.6" + wire $4\pc_changed$next[0:0]$13837 + attribute \src "libresoc.v:197327.3-197393.6" + wire $4\sv_changed$next[0:0]$13849 + attribute \src "libresoc.v:197270.3-197326.6" wire $4\update_svstate[0:0] - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $5\core_data_i[63:0] - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $5\core_wen[2:0] - attribute \src "libresoc.v:193028.3-193062.6" - wire $5\exec_fsm_state$next[0:0]$13565 - attribute \src "libresoc.v:193796.3-193849.6" - wire width 2 $5\fetch_fsm_state$next[1:0]$13680 - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $5\issue_fsm_state$next[2:0]$13705 - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196083.3-196117.6" + wire $5\exec_fsm_state$next[0:0]$13684 + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13799 + attribute \src "libresoc.v:195904.3-195941.6" + wire $5\insn_done[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $5\issue_fsm_state$next[2:0]$13824 + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $5\new_svstate_dststep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $5\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $5\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $5\new_svstate_subvl[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 2 $5\new_svstate_svstep[1:0] - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $5\new_svstate_vl[6:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $5\pc_changed$next[0:0]$13719 - attribute \src "libresoc.v:194282.3-194348.6" - wire $5\sv_changed$next[0:0]$13731 - attribute \src "libresoc.v:194220.3-194281.6" + attribute \src "libresoc.v:197203.3-197269.6" + wire $5\pc_changed$next[0:0]$13838 + attribute \src "libresoc.v:197327.3-197393.6" + wire $5\sv_changed$next[0:0]$13850 + attribute \src "libresoc.v:197270.3-197326.6" wire $5\update_svstate[0:0] - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $6\core_data_i[63:0] - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $6\core_wen[2:0] - attribute \src "libresoc.v:193796.3-193849.6" - wire width 2 $6\fetch_fsm_state$next[1:0]$13681 - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $6\issue_fsm_state$next[2:0]$13706 - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:196851.3-196904.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13800 + attribute \src "libresoc.v:195904.3-195941.6" + wire $6\insn_done[0:0] + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $6\issue_fsm_state$next[2:0]$13825 + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $6\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $6\pc_changed$next[0:0]$13720 - attribute \src "libresoc.v:194282.3-194348.6" - wire $6\sv_changed$next[0:0]$13732 - attribute \src "libresoc.v:194220.3-194281.6" + attribute \src "libresoc.v:197203.3-197269.6" + wire $6\pc_changed$next[0:0]$13839 + attribute \src "libresoc.v:197327.3-197393.6" + wire $6\sv_changed$next[0:0]$13851 + attribute \src "libresoc.v:197270.3-197326.6" wire $6\update_svstate[0:0] - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $7\core_data_i[63:0] - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $7\core_wen[2:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $7\issue_fsm_state$next[2:0]$13707 - attribute \src "libresoc.v:193932.3-193993.6" + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $7\issue_fsm_state$next[2:0]$13826 + attribute \src "libresoc.v:196987.3-197043.6" wire width 7 $7\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $7\pc_changed$next[0:0]$13721 - attribute \src "libresoc.v:194282.3-194348.6" - wire $7\sv_changed$next[0:0]$13733 - attribute \src "libresoc.v:194220.3-194281.6" + attribute \src "libresoc.v:197203.3-197269.6" + wire $7\pc_changed$next[0:0]$13840 + attribute \src "libresoc.v:197327.3-197393.6" + wire $7\sv_changed$next[0:0]$13852 + attribute \src "libresoc.v:197270.3-197326.6" wire $7\update_svstate[0:0] - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $8\core_data_i[63:0] - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $8\core_wen[2:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $8\issue_fsm_state$next[2:0]$13708 - attribute \src "libresoc.v:193932.3-193993.6" - wire width 7 $8\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:194153.3-194219.6" - wire $8\pc_changed$next[0:0]$13722 - attribute \src "libresoc.v:194282.3-194348.6" - wire $8\sv_changed$next[0:0]$13734 - attribute \src "libresoc.v:194220.3-194281.6" - wire $8\update_svstate[0:0] - attribute \src "libresoc.v:193500.3-193567.6" + attribute \src "libresoc.v:197060.3-197140.6" + wire width 3 $8\issue_fsm_state$next[2:0]$13827 + attribute \src "libresoc.v:197203.3-197269.6" + wire $8\pc_changed$next[0:0]$13841 + attribute \src "libresoc.v:197327.3-197393.6" + wire $8\sv_changed$next[0:0]$13853 + attribute \src "libresoc.v:196564.3-196631.6" wire width 64 $9\core_data_i[63:0] - attribute \src "libresoc.v:193432.3-193499.6" + attribute \src "libresoc.v:196496.3-196563.6" wire width 3 $9\core_wen[2:0] - attribute \src "libresoc.v:194010.3-194090.6" - wire width 3 $9\issue_fsm_state$next[2:0]$13709 - attribute \src "libresoc.v:194153.3-194219.6" - wire $9\pc_changed$next[0:0]$13723 - attribute \src "libresoc.v:194282.3-194348.6" - wire $9\sv_changed$next[0:0]$13735 - attribute \src "libresoc.v:191878.19-191878.108" - wire width 65 $add$libresoc.v:191878$13258_Y - attribute \src "libresoc.v:191948.19-191948.112" - wire width 8 $add$libresoc.v:191948$13325_Y - attribute \src "libresoc.v:191960.19-191960.115" - wire width 65 $add$libresoc.v:191960$13339_Y - attribute \src "libresoc.v:191994.18-191994.107" - wire width 65 $add$libresoc.v:191994$13372_Y - attribute \src "libresoc.v:191883.19-191883.104" - wire $and$libresoc.v:191883$13263_Y - attribute \src "libresoc.v:191886.19-191886.104" - wire $and$libresoc.v:191886$13266_Y - attribute \src "libresoc.v:191892.19-191892.104" - wire $and$libresoc.v:191892$13271_Y - attribute \src "libresoc.v:191895.19-191895.104" - wire $and$libresoc.v:191895$13274_Y - attribute \src "libresoc.v:191898.19-191898.104" - wire $and$libresoc.v:191898$13276_Y - attribute \src "libresoc.v:191901.19-191901.104" - wire $and$libresoc.v:191901$13279_Y - attribute \src "libresoc.v:191906.19-191906.104" - wire $and$libresoc.v:191906$13284_Y - attribute \src "libresoc.v:191909.19-191909.104" - wire $and$libresoc.v:191909$13287_Y - attribute \src "libresoc.v:191912.19-191912.104" - wire $and$libresoc.v:191912$13290_Y - attribute \src "libresoc.v:191915.19-191915.104" - wire $and$libresoc.v:191915$13293_Y - attribute \src "libresoc.v:191918.19-191918.104" - wire $and$libresoc.v:191918$13296_Y - attribute \src "libresoc.v:191921.19-191921.104" - wire $and$libresoc.v:191921$13299_Y - attribute \src "libresoc.v:191922.19-191922.115" - wire width 3 $and$libresoc.v:191922$13300_Y - attribute \src "libresoc.v:191926.19-191926.104" - wire $and$libresoc.v:191926$13304_Y - attribute \src "libresoc.v:191929.19-191929.104" - wire $and$libresoc.v:191929$13307_Y - attribute \src "libresoc.v:191935.19-191935.104" - wire $and$libresoc.v:191935$13312_Y - attribute \src "libresoc.v:191938.19-191938.104" - wire $and$libresoc.v:191938$13315_Y - attribute \src "libresoc.v:191939.19-191939.115" - wire width 3 $and$libresoc.v:191939$13316_Y - attribute \src "libresoc.v:191943.19-191943.104" - wire $and$libresoc.v:191943$13320_Y - attribute \src "libresoc.v:191946.19-191946.104" - wire $and$libresoc.v:191946$13323_Y - attribute \src "libresoc.v:191951.19-191951.104" - wire $and$libresoc.v:191951$13328_Y - attribute \src "libresoc.v:191966.18-191966.109" - wire $and$libresoc.v:191966$13345_Y - attribute \src "libresoc.v:191972.18-191972.101" - wire $and$libresoc.v:191972$13352_Y - attribute \src "libresoc.v:191975.18-191975.101" - wire $and$libresoc.v:191975$13354_Y - attribute \src "libresoc.v:191978.18-191978.101" - wire $and$libresoc.v:191978$13357_Y - attribute \src "libresoc.v:191983.18-191983.101" - wire $and$libresoc.v:191983$13362_Y - attribute \src "libresoc.v:191986.18-191986.101" - wire $and$libresoc.v:191986$13364_Y - attribute \src "libresoc.v:191989.18-191989.101" - wire $and$libresoc.v:191989$13367_Y - attribute \src "libresoc.v:191897.19-191897.108" - wire $eq$libresoc.v:191897$13275_Y - attribute \src "libresoc.v:191952.19-191952.116" - wire $eq$libresoc.v:191952$13329_Y - attribute \src "libresoc.v:191974.18-191974.107" - wire $eq$libresoc.v:191974$13353_Y - attribute \src "libresoc.v:191985.18-191985.107" - wire $eq$libresoc.v:191985$13363_Y - attribute \src "libresoc.v:191957.19-191957.114" - wire width 64 $extend$libresoc.v:191957$13334_Y - attribute \src "libresoc.v:191958.19-191958.113" - wire width 64 $extend$libresoc.v:191958$13336_Y - attribute \src "libresoc.v:191969.18-191969.109" - wire width 64 $extend$libresoc.v:191969$13348_Y - attribute \src "libresoc.v:191879.19-191879.106" - wire width 7 $mul$libresoc.v:191879$13259_Y - attribute \src "libresoc.v:191995.18-191995.110" - wire width 7 $mul$libresoc.v:191995$13373_Y - attribute \src "libresoc.v:191947.18-191947.102" - wire $ne$libresoc.v:191947$13324_Y - attribute \src "libresoc.v:191954.19-191954.123" - wire $ne$libresoc.v:191954$13331_Y - attribute \src "libresoc.v:191964.18-191964.102" - wire $ne$libresoc.v:191964$13343_Y - attribute \src "libresoc.v:191881.19-191881.107" - wire $not$libresoc.v:191881$13261_Y - attribute \src "libresoc.v:191882.19-191882.109" - wire $not$libresoc.v:191882$13262_Y - attribute \src "libresoc.v:191884.19-191884.107" - wire $not$libresoc.v:191884$13264_Y - attribute \src "libresoc.v:191885.19-191885.109" - wire $not$libresoc.v:191885$13265_Y - attribute \src "libresoc.v:191890.19-191890.107" - wire $not$libresoc.v:191890$13269_Y - attribute \src "libresoc.v:191891.19-191891.109" - wire $not$libresoc.v:191891$13270_Y - attribute \src "libresoc.v:191893.19-191893.107" - wire $not$libresoc.v:191893$13272_Y - attribute \src "libresoc.v:191894.19-191894.109" - wire $not$libresoc.v:191894$13273_Y - attribute \src "libresoc.v:191899.19-191899.107" - wire $not$libresoc.v:191899$13277_Y - attribute \src "libresoc.v:191900.19-191900.109" - wire $not$libresoc.v:191900$13278_Y - attribute \src "libresoc.v:191904.19-191904.107" - wire $not$libresoc.v:191904$13282_Y - attribute \src "libresoc.v:191905.19-191905.109" - wire $not$libresoc.v:191905$13283_Y - attribute \src "libresoc.v:191907.19-191907.107" - wire $not$libresoc.v:191907$13285_Y - attribute \src "libresoc.v:191908.19-191908.109" - wire $not$libresoc.v:191908$13286_Y - attribute \src "libresoc.v:191910.19-191910.107" - wire $not$libresoc.v:191910$13288_Y - attribute \src "libresoc.v:191911.19-191911.109" - wire $not$libresoc.v:191911$13289_Y - attribute \src "libresoc.v:191913.19-191913.107" - wire $not$libresoc.v:191913$13291_Y - attribute \src "libresoc.v:191914.19-191914.109" - wire $not$libresoc.v:191914$13292_Y - attribute \src "libresoc.v:191916.19-191916.107" - wire $not$libresoc.v:191916$13294_Y - attribute \src "libresoc.v:191917.19-191917.109" - wire $not$libresoc.v:191917$13295_Y - attribute \src "libresoc.v:191919.19-191919.107" - wire $not$libresoc.v:191919$13297_Y - attribute \src "libresoc.v:191920.19-191920.109" - wire $not$libresoc.v:191920$13298_Y - attribute \src "libresoc.v:191924.19-191924.107" - wire $not$libresoc.v:191924$13302_Y - attribute \src "libresoc.v:191925.19-191925.109" - wire $not$libresoc.v:191925$13303_Y - attribute \src "libresoc.v:191927.19-191927.107" - wire $not$libresoc.v:191927$13305_Y - attribute \src "libresoc.v:191928.19-191928.109" - wire $not$libresoc.v:191928$13306_Y - attribute \src "libresoc.v:191933.19-191933.107" - wire $not$libresoc.v:191933$13310_Y - attribute \src "libresoc.v:191934.19-191934.109" - wire $not$libresoc.v:191934$13311_Y - attribute \src "libresoc.v:191936.19-191936.107" - wire $not$libresoc.v:191936$13313_Y - attribute \src "libresoc.v:191937.19-191937.109" - wire $not$libresoc.v:191937$13314_Y - attribute \src "libresoc.v:191941.19-191941.107" - wire $not$libresoc.v:191941$13318_Y - attribute \src "libresoc.v:191942.19-191942.109" - wire $not$libresoc.v:191942$13319_Y - attribute \src "libresoc.v:191944.19-191944.107" - wire $not$libresoc.v:191944$13321_Y - attribute \src "libresoc.v:191945.19-191945.109" - wire $not$libresoc.v:191945$13322_Y - attribute \src "libresoc.v:191949.19-191949.107" - wire $not$libresoc.v:191949$13326_Y - attribute \src "libresoc.v:191950.19-191950.109" - wire $not$libresoc.v:191950$13327_Y - attribute \src "libresoc.v:191955.19-191955.107" - wire $not$libresoc.v:191955$13332_Y - attribute \src "libresoc.v:191956.19-191956.107" - wire $not$libresoc.v:191956$13333_Y - attribute \src "libresoc.v:191965.18-191965.103" - wire $not$libresoc.v:191965$13344_Y - attribute \src "libresoc.v:191967.18-191967.98" - wire $not$libresoc.v:191967$13346_Y - attribute \src "libresoc.v:191968.18-191968.103" - wire $not$libresoc.v:191968$13347_Y - attribute \src "libresoc.v:191970.18-191970.106" - wire $not$libresoc.v:191970$13350_Y - attribute \src "libresoc.v:191971.18-191971.108" - wire $not$libresoc.v:191971$13351_Y - attribute \src "libresoc.v:191976.18-191976.106" - wire $not$libresoc.v:191976$13355_Y - attribute \src "libresoc.v:191977.18-191977.108" - wire $not$libresoc.v:191977$13356_Y - attribute \src "libresoc.v:191981.18-191981.106" - wire $not$libresoc.v:191981$13360_Y - attribute \src "libresoc.v:191982.18-191982.108" - wire $not$libresoc.v:191982$13361_Y - attribute \src "libresoc.v:191987.18-191987.106" - wire $not$libresoc.v:191987$13365_Y - attribute \src "libresoc.v:191988.18-191988.108" - wire $not$libresoc.v:191988$13366_Y - attribute \src "libresoc.v:191992.18-191992.99" - wire $not$libresoc.v:191992$13370_Y - attribute \src "libresoc.v:191993.18-191993.99" - wire $not$libresoc.v:191993$13371_Y - attribute \src "libresoc.v:191887.19-191887.113" - wire $or$libresoc.v:191887$13267_Y - attribute \src "libresoc.v:191888.19-191888.104" - wire $or$libresoc.v:191888$13268_Y - attribute \src "libresoc.v:191902.19-191902.113" - wire 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$sub$libresoc.v:194875$13444_Y + attribute \src "libresoc.v:194876.18-194876.101" + wire width 3 $sub$libresoc.v:194876$13445_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" wire width 65 \$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" wire width 65 \$101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" wire \$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" wire \$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" wire \$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$186 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" wire width 3 \$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" wire \$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$206 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$220 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:444" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" wire width 3 \$223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" wire \$226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" wire \$228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:509" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" wire \$230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$232 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342" - wire width 8 \$238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342" - wire width 8 \$239 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - wire \$241 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - wire \$243 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - wire \$245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + wire width 8 \$244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + wire width 8 \$245 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$247 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + wire \$249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" wire width 3 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" wire \$253 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448" - wire \$255 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$257 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$259 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + wire width 64 \$255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" + wire \$257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + wire \$259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" wire width 3 \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:702" - wire width 65 \$261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:702" - wire width 65 \$262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" - wire width 65 \$264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" - wire width 65 \$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \$263 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \$265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + wire width 65 \$267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + wire width 65 \$268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" + wire width 65 \$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" + wire width 65 \$271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:562" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" wire \$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" wire \$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" wire \$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" wire \$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" wire \$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" wire \$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" wire \$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" wire width 65 \$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" wire width 65 \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" wire width 32 \$95 @@ -398624,17 +402978,17 @@ module \ti wire input 343 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133" wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 1 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 392 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132" wire input 4 \core_bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire \core_bigendian_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire \core_bigendian_i$10$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_cia__data_o @@ -398689,23 +403043,24 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 13 \core_core_core_fn_unit + wire width 14 \core_core_core_fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 13 \core_core_core_fn_unit$next + wire width 14 \core_core_core_fn_unit$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -398792,6 +403147,7 @@ module \ti attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \core_core_core_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" @@ -399184,7 +403540,7 @@ module \ti wire width 2 \core_core_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \core_core_svstep$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire \core_core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \core_core_vl @@ -399194,9 +403550,9 @@ module \ti wire width 3 \core_core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 \core_core_xer_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:95" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire \core_coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_cr_out_ok @@ -399260,9 +403616,9 @@ module \ti wire \core_issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" wire \core_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \core_ivalid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr @@ -399272,9 +403628,9 @@ module \ti wire width 64 \core_msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 32 \core_raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 32 \core_raw_insn_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_rego_ok @@ -399286,12 +403642,16 @@ module \ti wire \core_spro_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_state_nia_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_stopped_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_sv__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire \core_sv_a_nz + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire \core_sv_a_nz$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \core_wb_dcache_en attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -399302,8 +403662,8 @@ module \ti wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" - wire input 360 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 2 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" @@ -399334,17 +403694,17 @@ module \ti wire width 7 \cur_cur_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:657" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:672" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:657" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:672" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:647" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:647" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:682" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:682" wire \d_xer_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \dbg_core_dbg_core_dbg_dststep @@ -399511,21 +403871,22 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_fasto2_ok attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 13 \dec2_fn_unit + wire width 14 \dec2_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -399608,6 +403969,7 @@ module \ti attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \dec2_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" @@ -399880,6 +404242,8 @@ module \ti wire width 10 \dec2_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + wire \dec2_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 13 \dec2_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" @@ -399888,9 +404252,9 @@ module \ti wire width 3 \dec2_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 179 \eint_0__core__i @@ -399904,33 +404268,33 @@ module \ti wire output 181 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" wire \exec_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" wire \exec_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:608" wire \exec_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" wire \exec_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" wire \exec_pc_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" wire \exec_pc_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" wire width 2 \fetch_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" wire width 2 \fetch_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" wire \fetch_insn_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:588" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" wire \fetch_insn_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" wire \fetch_pc_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" wire \fetch_pc_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 188 \gpio_e10__core__i @@ -400139,35 +404503,35 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 344 \icp_wb__ack + wire output 376 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 350 \icp_wb__adr + wire width 28 input 382 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 345 \icp_wb__cyc + wire input 377 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 346 \icp_wb__dat_r + wire width 32 output 378 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 347 \icp_wb__dat_w + wire width 32 input 379 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 351 \icp_wb__sel + wire width 4 input 383 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 348 \icp_wb__stb + wire input 380 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 349 \icp_wb__we + wire input 381 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 357 \ics_wb__ack + wire output 389 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 352 \ics_wb__adr + wire width 28 input 384 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 354 \ics_wb__cyc + wire input 386 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 356 \ics_wb__dat_r + wire width 32 output 388 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 358 \ics_wb__dat_w + wire width 32 input 390 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 355 \ics_wb__stb + wire input 387 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 359 \ics_wb__we + wire input 391 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" @@ -400180,15 +404544,19 @@ module \ti wire \imem_f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:189535.7-189535.15" + attribute \src "libresoc.v:192354.7-192354.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 353 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" + wire width 16 input 385 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" wire \is_last - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" + wire \is_svp64_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" wire width 3 \issue_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" wire width 3 \issue_fsm_state$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o @@ -400222,6 +404590,8 @@ module \ti wire output 337 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 338 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire \jtag_wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400254,9 +404624,9 @@ module \ti wire input 81 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 236 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \mtwi_scl__core__o @@ -400274,7 +404644,7 @@ module \ti wire output 239 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 240 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" wire width 64 \new_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \new_svstate_dststep @@ -400288,19 +404658,19 @@ module \ti wire width 2 \new_svstate_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \new_svstate_vl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" wire width 7 \next_srcstep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542" wire \pc_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 7 \pc_i @@ -400308,11 +404678,11 @@ module \ti wire input 6 \pc_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129" wire width 64 output 5 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:502" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513" wire \por_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \pwm_0__core__o @@ -400322,8 +404692,8 @@ module \ti wire input 88 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 243 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 2 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400680,23 +405050,95 @@ module \ti wire input 146 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 301 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:532" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_0_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 346 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 347 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 344 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 348 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 349 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 351 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 345 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 350 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_1_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 354 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 355 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 352 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 356 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 357 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 359 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 353 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 358 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_2_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 362 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 363 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 360 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 364 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 365 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 367 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 361 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 366 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_3_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 370 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 371 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 368 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 372 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 373 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 375 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 369 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 374 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" wire \sv_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:532" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" wire \sv_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire width 64 \svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 \svstate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \svstate_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" wire \svstate_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" wire \svstate_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \ti_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" wire \update_svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o @@ -400708,8 +405150,8 @@ module \ti wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" - cell $add $add$libresoc.v:191878$13258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + cell $add $add$libresoc.v:194791$13361 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -400717,10 +405159,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:191878$13258_Y + connect \Y $add$libresoc.v:194791$13361_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342" - cell $add $add$libresoc.v:191948$13325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + cell $add $add$libresoc.v:194864$13431 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -400728,10 +405170,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_srcstep connect \B 1'1 - connect \Y $add$libresoc.v:191948$13325_Y + connect \Y $add$libresoc.v:194864$13431_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718" - cell $add $add$libresoc.v:191960$13339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" + cell $add $add$libresoc.v:194877$13446 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -400739,10 +405181,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:191960$13339_Y + connect \Y $add$libresoc.v:194877$13446_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" - cell $add $add$libresoc.v:191994$13372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" + cell $add $add$libresoc.v:194910$13478 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -400750,10 +405192,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:191994$13372_Y + connect \Y $add$libresoc.v:194910$13478_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191883$13263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194796$13366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400761,10 +405203,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$106 connect \B \$108 - connect \Y $and$libresoc.v:191883$13263_Y + connect \Y $and$libresoc.v:194796$13366_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191886$13266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194799$13369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400772,10 +405214,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$112 connect \B \$114 - connect \Y $and$libresoc.v:191886$13266_Y + connect \Y $and$libresoc.v:194799$13369_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191892$13271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194805$13374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400783,10 +405225,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:191892$13271_Y + connect \Y $and$libresoc.v:194805$13374_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191895$13274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194808$13377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400794,32 +405236,32 @@ module \ti parameter \Y_WIDTH 1 connect \A \$130 connect \B \$132 - connect \Y $and$libresoc.v:191895$13274_Y + connect \Y $and$libresoc.v:194808$13377_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - cell $and $and$libresoc.v:191898$13276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $and $and$libresoc.v:194810$13379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$136 - connect \B \$138 - connect \Y $and$libresoc.v:191898$13276_Y + connect \A \is_svp64_mode + connect \B \$136 + connect \Y $and$libresoc.v:194810$13379_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191901$13279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194813$13382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$142 - connect \B \$144 - connect \Y $and$libresoc.v:191901$13279_Y + connect \A \$140 + connect \B \$142 + connect \Y $and$libresoc.v:194813$13382_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191906$13284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194819$13387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400827,10 +405269,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$152 connect \B \$154 - connect \Y $and$libresoc.v:191906$13284_Y + connect \Y $and$libresoc.v:194819$13387_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191909$13287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194822$13390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400838,10 +405280,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$158 connect \B \$160 - connect \Y $and$libresoc.v:191909$13287_Y + connect \Y $and$libresoc.v:194822$13390_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191912$13290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194825$13393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400849,10 +405291,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$164 connect \B \$166 - connect \Y $and$libresoc.v:191912$13290_Y + connect \Y $and$libresoc.v:194825$13393_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191915$13293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194828$13396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400860,10 +405302,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$170 connect \B \$172 - connect \Y $and$libresoc.v:191915$13293_Y + connect \Y $and$libresoc.v:194828$13396_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191918$13296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194831$13399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400871,10 +405313,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$176 connect \B \$178 - connect \Y $and$libresoc.v:191918$13296_Y + connect \Y $and$libresoc.v:194831$13399_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191921$13299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194834$13402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400882,10 +405324,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$182 connect \B \$184 - connect \Y $and$libresoc.v:191921$13299_Y + connect \Y $and$libresoc.v:194834$13402_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" - cell $and $and$libresoc.v:191922$13300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" + cell $and $and$libresoc.v:194835$13403 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -400893,10 +405335,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 - connect \Y $and$libresoc.v:191922$13300_Y + connect \Y $and$libresoc.v:194835$13403_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191926$13304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194839$13407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400904,10 +405346,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$192 connect \B \$194 - connect \Y $and$libresoc.v:191926$13304_Y + connect \Y $and$libresoc.v:194839$13407_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191929$13307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194842$13410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400915,10 +405357,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$198 connect \B \$200 - connect \Y $and$libresoc.v:191929$13307_Y + connect \Y $and$libresoc.v:194842$13410_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191935$13312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194848$13415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400926,10 +405368,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$210 connect \B \$212 - connect \Y $and$libresoc.v:191935$13312_Y + connect \Y $and$libresoc.v:194848$13415_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191938$13315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194851$13418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400937,10 +405379,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$216 connect \B \$218 - connect \Y $and$libresoc.v:191938$13315_Y + connect \Y $and$libresoc.v:194851$13418_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:444" - cell $and $and$libresoc.v:191939$13316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" + cell $and $and$libresoc.v:194852$13419 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -400948,21 +405390,21 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 3'100 - connect \Y $and$libresoc.v:191939$13316_Y + connect \Y $and$libresoc.v:194852$13419_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191943$13320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $and $and$libresoc.v:194855$13422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$226 - connect \B \$228 - connect \Y $and$libresoc.v:191943$13320_Y + connect \A \is_svp64_mode + connect \B \$226 + connect \Y $and$libresoc.v:194855$13422_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191946$13323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194859$13426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400970,21 +405412,32 @@ module \ti parameter \Y_WIDTH 1 connect \A \$232 connect \B \$234 - connect \Y $and$libresoc.v:191946$13323_Y + connect \Y $and$libresoc.v:194859$13426_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191951$13328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194863$13430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$241 - connect \B \$243 - connect \Y $and$libresoc.v:191951$13328_Y + connect \A \$238 + connect \B \$240 + connect \Y $and$libresoc.v:194863$13430_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194867$13434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$247 + connect \B \$249 + connect \Y $and$libresoc.v:194867$13434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:191966$13345 + cell $and $and$libresoc.v:194882$13451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400992,10 +405445,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o connect \B \$34 - connect \Y $and$libresoc.v:191966$13345_Y + connect \Y $and$libresoc.v:194882$13451_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191972$13352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194888$13458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401003,32 +405456,32 @@ module \ti parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:191972$13352_Y + connect \Y $and$libresoc.v:194888$13458_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - cell $and $and$libresoc.v:191975$13354 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $and $and$libresoc.v:194890$13460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$50 - connect \B \$52 - connect \Y $and$libresoc.v:191975$13354_Y + connect \A \is_svp64_mode + connect \B \$50 + connect \Y $and$libresoc.v:194890$13460_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191978$13357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194893$13463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$56 - connect \B \$58 - connect \Y $and$libresoc.v:191978$13357_Y + connect \A \$54 + connect \B \$56 + connect \Y $and$libresoc.v:194893$13463_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:191983$13362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $and $and$libresoc.v:194899$13468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401036,32 +405489,32 @@ module \ti parameter \Y_WIDTH 1 connect \A \$66 connect \B \$68 - connect \Y $and$libresoc.v:191983$13362_Y + connect \Y $and$libresoc.v:194899$13468_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - cell $and $and$libresoc.v:191986$13364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $and $and$libresoc.v:194901$13470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$72 - connect \B \$74 - connect \Y $and$libresoc.v:191986$13364_Y + connect \A \is_svp64_mode + connect \B \$72 + connect \Y $and$libresoc.v:194901$13470_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $and $and$libresoc.v:191989$13367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $and $and$libresoc.v:194904$13473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$78 - connect \B \$80 - connect \Y $and$libresoc.v:191989$13367_Y + connect \A \$76 + connect \B \$78 + connect \Y $and$libresoc.v:194904$13473_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - cell $eq $eq$libresoc.v:191897$13275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $eq $eq$libresoc.v:194809$13378 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -401069,10 +405522,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:191897$13275_Y + connect \Y $eq$libresoc.v:194809$13378_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $eq $eq$libresoc.v:191952$13329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $eq $eq$libresoc.v:194854$13421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_cur_vl + connect \B 1'0 + connect \Y $eq$libresoc.v:194854$13421_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + cell $eq $eq$libresoc.v:194868$13435 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -401080,10 +405544,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \next_srcstep connect \B \cur_cur_vl - connect \Y $eq$libresoc.v:191952$13329_Y + connect \Y $eq$libresoc.v:194868$13435_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - cell $eq $eq$libresoc.v:191974$13353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $eq $eq$libresoc.v:194889$13459 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -401091,10 +405555,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:191974$13353_Y + connect \Y $eq$libresoc.v:194889$13459_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - cell $eq $eq$libresoc.v:191985$13363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + cell $eq $eq$libresoc.v:194900$13469 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -401102,34 +405566,34 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:191985$13363_Y + connect \Y $eq$libresoc.v:194900$13469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:191957$13334 + cell $pos $extend$libresoc.v:194873$13440 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:191957$13334_Y + connect \Y $extend$libresoc.v:194873$13440_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:191958$13336 + cell $pos $extend$libresoc.v:194874$13442 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:191958$13336_Y + connect \Y $extend$libresoc.v:194874$13442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:191969$13348 + cell $pos $extend$libresoc.v:194885$13454 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \svstate_i - connect \Y $extend$libresoc.v:191969$13348_Y + connect \Y $extend$libresoc.v:194885$13454_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:191879$13259 + cell $mul $mul$libresoc.v:194792$13362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401137,10 +405601,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \$100 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:191879$13259_Y + connect \Y $mul$libresoc.v:194792$13362_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:191995$13373 + cell $mul $mul$libresoc.v:194911$13479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401148,10 +405612,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:191995$13373_Y + connect \Y $mul$libresoc.v:194911$13479_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:509" - cell $ne $ne$libresoc.v:191947$13324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + cell $ne $ne$libresoc.v:194861$13428 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -401159,10 +405623,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $ne$libresoc.v:191947$13324_Y + connect \Y $ne$libresoc.v:194861$13428_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:441" - cell $ne $ne$libresoc.v:191954$13331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" + cell $ne $ne$libresoc.v:194870$13437 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -401170,10 +405634,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:191954$13331_Y + connect \Y $ne$libresoc.v:194870$13437_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - cell $ne $ne$libresoc.v:191964$13343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $ne $ne$libresoc.v:194880$13449 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -401181,418 +405645,426 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 - connect \Y $ne$libresoc.v:191964$13343_Y + connect \Y $ne$libresoc.v:194880$13449_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191881$13261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194794$13364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191881$13261_Y + connect \Y $not$libresoc.v:194794$13364_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191882$13262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194795$13365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191882$13262_Y + connect \Y $not$libresoc.v:194795$13365_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191884$13264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194797$13367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191884$13264_Y + connect \Y $not$libresoc.v:194797$13367_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191885$13265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194798$13368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191885$13265_Y + connect \Y $not$libresoc.v:194798$13368_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191890$13269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194803$13372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191890$13269_Y + connect \Y $not$libresoc.v:194803$13372_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191891$13270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194804$13373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191891$13270_Y + connect \Y $not$libresoc.v:194804$13373_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191893$13272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194806$13375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191893$13272_Y + connect \Y $not$libresoc.v:194806$13375_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191894$13273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194807$13376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191894$13273_Y + connect \Y $not$libresoc.v:194807$13376_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191899$13277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194811$13380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191899$13277_Y + connect \Y $not$libresoc.v:194811$13380_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191900$13278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194812$13381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191900$13278_Y + connect \Y $not$libresoc.v:194812$13381_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191904$13282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194817$13385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191904$13282_Y + connect \Y $not$libresoc.v:194817$13385_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191905$13283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194818$13386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191905$13283_Y + connect \Y $not$libresoc.v:194818$13386_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191907$13285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194820$13388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191907$13285_Y + connect \Y $not$libresoc.v:194820$13388_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191908$13286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194821$13389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191908$13286_Y + connect \Y $not$libresoc.v:194821$13389_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191910$13288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194823$13391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191910$13288_Y + connect \Y $not$libresoc.v:194823$13391_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191911$13289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194824$13392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191911$13289_Y + connect \Y $not$libresoc.v:194824$13392_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191913$13291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194826$13394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191913$13291_Y + connect \Y $not$libresoc.v:194826$13394_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191914$13292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194827$13395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191914$13292_Y + connect \Y $not$libresoc.v:194827$13395_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191916$13294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194829$13397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191916$13294_Y + connect \Y $not$libresoc.v:194829$13397_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191917$13295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194830$13398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191917$13295_Y + connect \Y $not$libresoc.v:194830$13398_Y end - attribute \src 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1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191927$13305_Y + connect \Y $not$libresoc.v:194840$13408_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191928$13306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194841$13409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191928$13306_Y + connect \Y $not$libresoc.v:194841$13409_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191933$13310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194846$13413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191933$13310_Y + connect \Y $not$libresoc.v:194846$13413_Y end - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194850$13417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191937$13314_Y + connect \Y $not$libresoc.v:194850$13417_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191941$13318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $not $not$libresoc.v:194856$13423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:194856$13423_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194857$13424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191941$13318_Y + connect \Y $not$libresoc.v:194857$13424_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191942$13319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194858$13425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191942$13319_Y + connect \Y $not$libresoc.v:194858$13425_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191944$13321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194860$13427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191944$13321_Y + connect \Y $not$libresoc.v:194860$13427_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191945$13322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194862$13429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191945$13322_Y + connect \Y $not$libresoc.v:194862$13429_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191949$13326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194865$13432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191949$13326_Y + connect \Y $not$libresoc.v:194865$13432_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191950$13327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194866$13433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191950$13327_Y + connect \Y $not$libresoc.v:194866$13433_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448" - cell $not $not$libresoc.v:191955$13332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $not $not$libresoc.v:194871$13438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:191955$13332_Y + connect \Y $not$libresoc.v:194871$13438_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448" - cell $not $not$libresoc.v:191956$13333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $not $not$libresoc.v:194872$13439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:191956$13333_Y + connect \Y $not$libresoc.v:194872$13439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:191965$13344 + cell $not $not$libresoc.v:194881$13450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:191965$13344_Y + connect \Y $not$libresoc.v:194881$13450_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" - cell $not $not$libresoc.v:191967$13346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" + cell $not $not$libresoc.v:194883$13452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok - connect \Y $not$libresoc.v:191967$13346_Y + connect \Y $not$libresoc.v:194883$13452_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $not $not$libresoc.v:191968$13347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:562" + cell $not $not$libresoc.v:194884$13453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svstate_i_ok - connect \Y $not$libresoc.v:191968$13347_Y + connect \Y $not$libresoc.v:194884$13453_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191970$13350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194886$13456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191970$13350_Y + connect \Y $not$libresoc.v:194886$13456_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191971$13351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194887$13457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191971$13351_Y + connect \Y $not$libresoc.v:194887$13457_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191976$13355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194891$13461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191976$13355_Y + connect \Y $not$libresoc.v:194891$13461_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191977$13356 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194892$13462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191977$13356_Y + connect \Y $not$libresoc.v:194892$13462_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191981$13360 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194897$13466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191981$13360_Y + connect \Y $not$libresoc.v:194897$13466_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $not $not$libresoc.v:191982$13361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:194898$13467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191982$13361_Y + connect \Y $not$libresoc.v:194898$13467_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191987$13365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194902$13471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:191987$13365_Y + connect \Y $not$libresoc.v:194902$13471_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - cell $not $not$libresoc.v:191988$13366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + cell $not $not$libresoc.v:194903$13472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:191988$13366_Y + connect \Y $not$libresoc.v:194903$13472_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" - cell $not $not$libresoc.v:191992$13370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + cell $not $not$libresoc.v:194908$13476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:191992$13370_Y + connect \Y $not$libresoc.v:194908$13476_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" - cell $not $not$libresoc.v:191993$13371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + cell $not $not$libresoc.v:194909$13477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:191993$13371_Y + connect \Y $not$libresoc.v:194909$13477_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - cell $or $or$libresoc.v:191887$13267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194800$13370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401600,21 +406072,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:191887$13267_Y + connect \Y $or$libresoc.v:194800$13370_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" - cell $or $or$libresoc.v:191888$13268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194802$13371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A 1'1 + connect \A \$120 connect \B \is_last - connect \Y $or$libresoc.v:191888$13268_Y + connect \Y $or$libresoc.v:194802$13371_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - cell $or $or$libresoc.v:191902$13280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194814$13383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401622,21 +406094,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:191902$13280_Y + connect \Y $or$libresoc.v:194814$13383_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" - cell $or $or$libresoc.v:191903$13281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194816$13384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A 1'1 + connect \A \$148 connect \B \is_last - connect \Y $or$libresoc.v:191903$13281_Y + connect \Y $or$libresoc.v:194816$13384_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - cell $or $or$libresoc.v:191930$13308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194843$13411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401644,21 +406116,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:191930$13308_Y + connect \Y $or$libresoc.v:194843$13411_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" - cell $or $or$libresoc.v:191931$13309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194845$13412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A 1'1 + connect \A \$206 connect \B \is_last - connect \Y $or$libresoc.v:191931$13309_Y + connect \Y $or$libresoc.v:194845$13412_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - cell $or $or$libresoc.v:191962$13341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $or $or$libresoc.v:194878$13447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401666,10 +406138,10 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:191962$13341_Y + connect \Y $or$libresoc.v:194878$13447_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - cell $or $or$libresoc.v:191963$13342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + cell $or $or$libresoc.v:194879$13448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401677,10 +406149,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:191963$13342_Y + connect \Y $or$libresoc.v:194879$13448_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - cell $or $or$libresoc.v:191979$13358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194894$13464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401688,21 +406160,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:191979$13358_Y + connect \Y $or$libresoc.v:194894$13464_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" - cell $or $or$libresoc.v:191980$13359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194896$13465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A 1'1 + connect \A \$62 connect \B \is_last - connect \Y $or$libresoc.v:191980$13359_Y + connect \Y $or$libresoc.v:194896$13465_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - cell $or $or$libresoc.v:191990$13368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $or $or$libresoc.v:194905$13474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -401710,69 +406182,69 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:191990$13368_Y + connect \Y $or$libresoc.v:194905$13474_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" - cell $or $or$libresoc.v:191991$13369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + cell $or $or$libresoc.v:194907$13475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A 1'1 + connect \A \$84 connect \B \is_last - connect \Y $or$libresoc.v:191991$13369_Y + connect \Y $or$libresoc.v:194907$13475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:191953$13330 + cell $pos $pos$libresoc.v:194869$13436 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } - connect \Y $pos$libresoc.v:191953$13330_Y + connect \Y $pos$libresoc.v:194869$13436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:191957$13335 + cell $pos $pos$libresoc.v:194873$13441 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:191957$13334_Y - connect \Y $pos$libresoc.v:191957$13335_Y + connect \A $extend$libresoc.v:194873$13440_Y + connect \Y $pos$libresoc.v:194873$13441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:191958$13337 + cell $pos $pos$libresoc.v:194874$13443 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:191958$13336_Y - connect \Y $pos$libresoc.v:191958$13337_Y + connect \A $extend$libresoc.v:194874$13442_Y + connect \Y $pos$libresoc.v:194874$13443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:191969$13349 + cell $pos $pos$libresoc.v:194885$13455 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:191969$13348_Y - connect \Y $pos$libresoc.v:191969$13349_Y + connect \A $extend$libresoc.v:194885$13454_Y + connect \Y $pos$libresoc.v:194885$13455_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:191923$13301 + cell $reduce_or $reduce_or$libresoc.v:194836$13404 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$189 - connect \Y $reduce_or$libresoc.v:191923$13301_Y + connect \Y $reduce_or$libresoc.v:194836$13404_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:191940$13317 + cell $reduce_or $reduce_or$libresoc.v:194853$13420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$223 - connect \Y $reduce_or$libresoc.v:191940$13317_Y + connect \Y $reduce_or$libresoc.v:194853$13420_Y end - attribute \src "libresoc.v:191880.18-191880.41" - cell $shr $shr$libresoc.v:191880$13260 + attribute \src "libresoc.v:194793.18-194793.41" + cell $shr $shr$libresoc.v:194793$13363 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -401780,10 +406252,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$103 - connect \Y $shr$libresoc.v:191880$13260_Y + connect \Y $shr$libresoc.v:194793$13363_Y end - attribute \src "libresoc.v:191996.18-191996.40" - cell $shr $shr$libresoc.v:191996$13374 + attribute \src "libresoc.v:194912.18-194912.40" + cell $shr $shr$libresoc.v:194912$13480 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -401791,10 +406263,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$96 - connect \Y $shr$libresoc.v:191996$13374_Y + connect \Y $shr$libresoc.v:194912$13480_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:702" - cell $sub $sub$libresoc.v:191959$13338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + cell $sub $sub$libresoc.v:194875$13444 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -401802,10 +406274,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:191959$13338_Y + connect \Y $sub$libresoc.v:194875$13444_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" - cell $sub $sub$libresoc.v:191961$13340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" + cell $sub $sub$libresoc.v:194876$13445 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -401813,10 +406285,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:191961$13340_Y + connect \Y $sub$libresoc.v:194876$13445_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:192203.8-192300.4" + attribute \src "libresoc.v:195121.8-195219.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -401911,12 +406383,13 @@ module \ti connect \state_nia_wen \core_state_nia_wen connect \sv__data_o \core_sv__data_o connect \sv__ren \core_sv__ren + connect \sv_a_nz \core_sv_a_nz connect \wb_dcache_en \core_wb_dcache_en connect \wen \core_wen connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:192301.7-192332.4" + attribute \src "libresoc.v:195220.7-195251.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep @@ -401950,7 +406423,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:192333.8-192399.4" + attribute \src "libresoc.v:195252.8-195319.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -402013,13 +406486,14 @@ module \ti connect \spr1_ok \dec2_spr1_ok connect \spro \dec2_spro connect \spro_ok \dec2_spro_ok + connect \sv_a_nz \dec2_sv_a_nz connect \trapaddr \dec2_trapaddr connect \traptype \dec2_traptype connect \xer_in \dec2_xer_in connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:192400.8-192416.4" + attribute \src "libresoc.v:195320.8-195336.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -402038,7 +406512,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:192417.8-192748.4" + attribute \src "libresoc.v:195337.8-195669.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -402370,9 +406844,70 @@ module \ti connect \sdr_we_n__pad__o \sdr_we_n__pad__o connect \wb_dcache_en \core_wb_dcache_en connect \wb_icache_en \imem_wb_icache_en + connect \wb_sram_en \jtag_wb_sram_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195670.12-195682.4" + cell \sram4k_0 \sram4k_0 + connect \clk \clk + connect \enable \sram4k_0_enable + connect \rst \rst + connect \sram4k_0_wb__ack \sram4k_0_wb__ack + connect \sram4k_0_wb__adr \sram4k_0_wb__adr + connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc + connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r + connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w + connect \sram4k_0_wb__sel \sram4k_0_wb__sel + connect \sram4k_0_wb__stb \sram4k_0_wb__stb + connect \sram4k_0_wb__we \sram4k_0_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195683.12-195695.4" + cell \sram4k_1 \sram4k_1 + connect \clk \clk + connect \enable \sram4k_1_enable + connect \rst \rst + connect \sram4k_1_wb__ack \sram4k_1_wb__ack + connect \sram4k_1_wb__adr \sram4k_1_wb__adr + connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc + connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r + connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w + connect \sram4k_1_wb__sel \sram4k_1_wb__sel + connect \sram4k_1_wb__stb \sram4k_1_wb__stb + connect \sram4k_1_wb__we \sram4k_1_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195696.12-195708.4" + cell \sram4k_2 \sram4k_2 + connect \clk \clk + connect \enable \sram4k_2_enable + connect \rst \rst + connect \sram4k_2_wb__ack \sram4k_2_wb__ack + connect \sram4k_2_wb__adr \sram4k_2_wb__adr + connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc + connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r + connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w + connect \sram4k_2_wb__sel \sram4k_2_wb__sel + connect \sram4k_2_wb__stb \sram4k_2_wb__stb + connect \sram4k_2_wb__we \sram4k_2_wb__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195709.12-195721.4" + cell \sram4k_3 \sram4k_3 + connect \clk \clk + connect \enable \sram4k_3_enable + connect \rst \rst + connect \sram4k_3_wb__ack \sram4k_3_wb__ack + connect \sram4k_3_wb__adr \sram4k_3_wb__adr + connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc + connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r + connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w + connect \sram4k_3_wb__sel \sram4k_3_wb__sel + connect \sram4k_3_wb__stb \sram4k_3_wb__stb + connect \sram4k_3_wb__we \sram4k_3_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:192749.12-192763.4" + attribute \src "libresoc.v:195722.12-195736.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -402389,7 +406924,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:192764.12-192777.4" + attribute \src "libresoc.v:195737.12-195750.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -402404,1567 +406939,1605 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:189535.7-189535.20" - process $proc$libresoc.v:189535$13948 + attribute \src "libresoc.v:192354.7-192354.20" + process $proc$libresoc.v:192354$14061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189799.13-189799.33" - process $proc$libresoc.v:189799$13949 + attribute \src "libresoc.v:192624.13-192624.33" + process $proc$libresoc.v:192624$14062 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:189805.7-189805.35" - process $proc$libresoc.v:189805$13950 + attribute \src "libresoc.v:192630.7-192630.35" + process $proc$libresoc.v:192630$14063 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13951 1'0 + assign $0\core_bigendian_i$10[0:0]$14064 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13951 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14064 end - attribute \src "libresoc.v:189813.14-189813.55" - process $proc$libresoc.v:189813$13952 + attribute \src "libresoc.v:192638.14-192638.55" + process $proc$libresoc.v:192638$14065 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:189817.13-189817.41" - process $proc$libresoc.v:189817$13953 + attribute \src "libresoc.v:192642.13-192642.41" + process $proc$libresoc.v:192642$14066 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:189821.7-189821.37" - process $proc$libresoc.v:189821$13954 + attribute \src "libresoc.v:192646.7-192646.37" + process $proc$libresoc.v:192646$14067 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:189825.13-189825.41" - process $proc$libresoc.v:189825$13955 + attribute \src "libresoc.v:192650.13-192650.41" + process $proc$libresoc.v:192650$14068 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:189829.7-189829.42" - process $proc$libresoc.v:189829$13956 + attribute \src "libresoc.v:192654.7-192654.42" + process $proc$libresoc.v:192654$14069 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13957 1'0 + assign $0\core_core_core_exc_$signal[0:0]$14070 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13957 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14070 end - attribute \src "libresoc.v:189831.7-189831.44" - process $proc$libresoc.v:189831$13958 + attribute \src "libresoc.v:192656.7-192656.44" + process $proc$libresoc.v:192656$14071 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13959 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$14072 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13959 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14072 end - attribute \src "libresoc.v:189835.7-189835.44" - process $proc$libresoc.v:189835$13960 + attribute \src "libresoc.v:192660.7-192660.44" + process $proc$libresoc.v:192660$14073 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13961 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$14074 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13961 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14074 end - attribute \src "libresoc.v:189839.7-189839.44" - process $proc$libresoc.v:189839$13962 + attribute \src "libresoc.v:192664.7-192664.44" + process $proc$libresoc.v:192664$14075 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13963 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$14076 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13963 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14076 end - attribute \src "libresoc.v:189843.7-189843.44" - process $proc$libresoc.v:189843$13964 + attribute \src "libresoc.v:192668.7-192668.44" + process $proc$libresoc.v:192668$14077 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13965 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$14078 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13965 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14078 end - attribute \src "libresoc.v:189847.7-189847.44" - process $proc$libresoc.v:189847$13966 + attribute \src "libresoc.v:192672.7-192672.44" + process $proc$libresoc.v:192672$14079 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13967 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$14080 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13967 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14080 end - attribute \src "libresoc.v:189851.7-189851.44" - process $proc$libresoc.v:189851$13968 + attribute \src "libresoc.v:192676.7-192676.44" + process $proc$libresoc.v:192676$14081 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13969 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$14082 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13969 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14082 end - attribute \src "libresoc.v:189855.7-189855.44" - process $proc$libresoc.v:189855$13970 + attribute \src "libresoc.v:192680.7-192680.44" + process $proc$libresoc.v:192680$14083 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13971 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$14084 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13971 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14084 end - attribute \src "libresoc.v:189875.14-189875.47" - process $proc$libresoc.v:189875$13972 + attribute \src "libresoc.v:192701.14-192701.47" + process $proc$libresoc.v:192701$14085 assign { } { } - assign $1\core_core_core_fn_unit[12:0] 13'0000000000000 + assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init - update \core_core_core_fn_unit $1\core_core_core_fn_unit[12:0] + update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:189883.13-189883.46" - process $proc$libresoc.v:189883$13973 + attribute \src "libresoc.v:192709.13-192709.46" + process $proc$libresoc.v:192709$14086 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:189887.14-189887.41" - process $proc$libresoc.v:189887$13974 + attribute \src "libresoc.v:192713.14-192713.41" + process $proc$libresoc.v:192713$14087 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:189965.13-189965.45" - process $proc$libresoc.v:189965$13975 + attribute \src "libresoc.v:192792.13-192792.45" + process $proc$libresoc.v:192792$14088 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:189969.7-189969.37" - process $proc$libresoc.v:189969$13976 + attribute \src "libresoc.v:192796.7-192796.37" + process $proc$libresoc.v:192796$14089 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:189973.14-189973.55" - process $proc$libresoc.v:189973$13977 + attribute \src "libresoc.v:192800.14-192800.55" + process $proc$libresoc.v:192800$14090 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:189977.7-189977.31" - process $proc$libresoc.v:189977$13978 + attribute \src "libresoc.v:192804.7-192804.31" + process $proc$libresoc.v:192804$14091 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:189981.7-189981.34" - process $proc$libresoc.v:189981$13979 + attribute \src "libresoc.v:192808.7-192808.34" + process $proc$libresoc.v:192808$14092 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:189985.7-189985.31" - process $proc$libresoc.v:189985$13980 + attribute \src "libresoc.v:192812.7-192812.31" + process $proc$libresoc.v:192812$14093 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:189989.7-189989.34" - process $proc$libresoc.v:189989$13981 + attribute \src "libresoc.v:192816.7-192816.34" + process $proc$libresoc.v:192816$14094 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:189993.14-189993.48" - process $proc$libresoc.v:189993$13982 + attribute \src "libresoc.v:192820.14-192820.48" + process $proc$libresoc.v:192820$14095 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:189997.13-189997.44" - process $proc$libresoc.v:189997$13983 + attribute \src "libresoc.v:192824.13-192824.44" + process $proc$libresoc.v:192824$14096 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:190001.13-190001.37" - process $proc$libresoc.v:190001$13984 + attribute \src "libresoc.v:192828.13-192828.37" + process $proc$libresoc.v:192828$14097 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:190005.7-190005.33" - process $proc$libresoc.v:190005$13985 + attribute \src "libresoc.v:192832.7-192832.33" + process $proc$libresoc.v:192832$14098 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:190009.13-190009.37" - process $proc$libresoc.v:190009$13986 + attribute \src "libresoc.v:192836.13-192836.37" + process $proc$libresoc.v:192836$14099 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:190011.13-190011.41" - process $proc$libresoc.v:190011$13987 + attribute \src "libresoc.v:192838.13-192838.41" + process $proc$libresoc.v:192838$14100 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13988 7'0000000 + assign $0\core_core_cr_in2$1[6:0]$14101 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13988 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14101 end - attribute \src "libresoc.v:190017.7-190017.33" - process $proc$libresoc.v:190017$13989 + attribute \src "libresoc.v:192844.7-192844.33" + process $proc$libresoc.v:192844$14102 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:190019.7-190019.37" - process $proc$libresoc.v:190019$13990 + attribute \src "libresoc.v:192846.7-192846.37" + process $proc$libresoc.v:192846$14103 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13991 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$14104 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13991 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14104 end - attribute \src "libresoc.v:190025.13-190025.37" - process $proc$libresoc.v:190025$13992 + attribute \src "libresoc.v:192852.13-192852.37" + process $proc$libresoc.v:192852$14105 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:190029.7-190029.32" - process $proc$libresoc.v:190029$13993 + attribute \src "libresoc.v:192856.7-192856.32" + process $proc$libresoc.v:192856$14106 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:190033.13-190033.38" - process $proc$libresoc.v:190033$13994 + attribute \src "libresoc.v:192860.13-192860.38" + process $proc$libresoc.v:192860$14107 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end - attribute \src "libresoc.v:190037.13-190037.33" - process $proc$libresoc.v:190037$13995 + attribute \src "libresoc.v:192864.13-192864.33" + process $proc$libresoc.v:192864$14108 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:190041.13-190041.35" - process $proc$libresoc.v:190041$13996 + attribute \src "libresoc.v:192868.13-192868.35" + process $proc$libresoc.v:192868$14109 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:190045.7-190045.32" - process $proc$libresoc.v:190045$13997 + attribute \src "libresoc.v:192872.7-192872.32" + process $proc$libresoc.v:192872$14110 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:190049.13-190049.35" - process $proc$libresoc.v:190049$13998 + attribute \src "libresoc.v:192876.13-192876.35" + process $proc$libresoc.v:192876$14111 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:190053.7-190053.32" - process $proc$libresoc.v:190053$13999 + attribute \src "libresoc.v:192880.7-192880.32" + process $proc$libresoc.v:192880$14112 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:190057.13-190057.36" - process $proc$libresoc.v:190057$14000 + attribute \src "libresoc.v:192884.13-192884.36" + process $proc$libresoc.v:192884$14113 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:190061.13-190061.36" - process $proc$libresoc.v:190061$14001 + attribute \src "libresoc.v:192888.13-192888.36" + process $proc$libresoc.v:192888$14114 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:190065.7-190065.26" - process $proc$libresoc.v:190065$14002 + attribute \src "libresoc.v:192892.7-192892.26" + process $proc$libresoc.v:192892$14115 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:190069.13-190069.36" - process $proc$libresoc.v:190069$14003 + attribute \src "libresoc.v:192896.13-192896.36" + process $proc$libresoc.v:192896$14116 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end - attribute \src "libresoc.v:190073.14-190073.49" - process $proc$libresoc.v:190073$14004 + attribute \src "libresoc.v:192900.14-192900.49" + process $proc$libresoc.v:192900$14117 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:190077.13-190077.35" - process $proc$libresoc.v:190077$14005 + attribute \src "libresoc.v:192904.13-192904.35" + process $proc$libresoc.v:192904$14118 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:190081.7-190081.31" - process $proc$libresoc.v:190081$14006 + attribute \src "libresoc.v:192908.7-192908.31" + process $proc$libresoc.v:192908$14119 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:190085.13-190085.35" - process $proc$libresoc.v:190085$14007 + attribute \src "libresoc.v:192912.13-192912.35" + process $proc$libresoc.v:192912$14120 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:190089.7-190089.31" - process $proc$libresoc.v:190089$14008 + attribute \src "libresoc.v:192916.7-192916.31" + process $proc$libresoc.v:192916$14121 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:190093.13-190093.35" - process $proc$libresoc.v:190093$14009 + attribute \src "libresoc.v:192920.13-192920.35" + process $proc$libresoc.v:192920$14122 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:190097.7-190097.31" - process $proc$libresoc.v:190097$14010 + attribute \src "libresoc.v:192924.7-192924.31" + process $proc$libresoc.v:192924$14123 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:190101.13-190101.35" - process $proc$libresoc.v:190101$14011 + attribute \src "libresoc.v:192928.13-192928.35" + process $proc$libresoc.v:192928$14124 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:190219.13-190219.37" - process $proc$libresoc.v:190219$14012 + attribute \src "libresoc.v:193046.13-193046.37" + process $proc$libresoc.v:193046$14125 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:190223.7-190223.31" - process $proc$libresoc.v:190223$14013 + attribute \src "libresoc.v:193050.7-193050.31" + process $proc$libresoc.v:193050$14126 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:190341.13-190341.37" - process $proc$libresoc.v:190341$14014 + attribute \src "libresoc.v:193168.13-193168.37" + process $proc$libresoc.v:193168$14127 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:190345.13-190345.38" - process $proc$libresoc.v:190345$14015 + attribute \src "libresoc.v:193172.13-193172.38" + process $proc$libresoc.v:193172$14128 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end - attribute \src "libresoc.v:190349.13-190349.35" - process $proc$libresoc.v:190349$14016 + attribute \src "libresoc.v:193176.13-193176.35" + process $proc$libresoc.v:193176$14129 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end - attribute \src "libresoc.v:190353.13-190353.36" - process $proc$libresoc.v:190353$14017 + attribute \src "libresoc.v:193180.13-193180.36" + process $proc$libresoc.v:193180$14130 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end - attribute \src "libresoc.v:190359.13-190359.33" - process $proc$libresoc.v:190359$14018 + attribute \src "libresoc.v:193186.13-193186.33" + process $proc$libresoc.v:193186$14131 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end - attribute \src "libresoc.v:190363.13-190363.36" - process $proc$libresoc.v:190363$14019 + attribute \src "libresoc.v:193190.13-193190.36" + process $proc$libresoc.v:193190$14132 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:190371.7-190371.28" - process $proc$libresoc.v:190371$14020 + attribute \src "libresoc.v:193198.7-193198.28" + process $proc$libresoc.v:193198$14133 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:190387.14-190387.45" - process $proc$libresoc.v:190387$14021 + attribute \src "libresoc.v:193214.14-193214.45" + process $proc$libresoc.v:193214$14134 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:190397.7-190397.24" - process $proc$libresoc.v:190397$14022 + attribute \src "libresoc.v:193224.7-193224.24" + process $proc$libresoc.v:193224$14135 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:190401.7-190401.23" - process $proc$libresoc.v:190401$14023 + attribute \src "libresoc.v:193228.7-193228.23" + process $proc$libresoc.v:193228$14136 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:190405.7-190405.28" - process $proc$libresoc.v:190405$14024 + attribute \src "libresoc.v:193232.7-193232.28" + process $proc$libresoc.v:193232$14137 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:190409.7-190409.28" - process $proc$libresoc.v:190409$14025 + attribute \src "libresoc.v:193236.7-193236.28" + process $proc$libresoc.v:193236$14138 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:190437.14-190437.45" - process $proc$libresoc.v:190437$14026 + attribute \src "libresoc.v:193264.14-193264.45" + process $proc$libresoc.v:193264$14139 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:190445.14-190445.37" - process $proc$libresoc.v:190445$14027 + attribute \src "libresoc.v:193272.14-193272.37" + process $proc$libresoc.v:193272$14140 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:190449.7-190449.26" - process $proc$libresoc.v:190449$14028 + attribute \src "libresoc.v:193276.7-193276.26" + process $proc$libresoc.v:193276$14141 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:190453.7-190453.26" - process $proc$libresoc.v:190453$14029 + attribute \src "libresoc.v:193280.7-193280.26" + process $proc$libresoc.v:193280$14142 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:190471.7-190471.26" - process $proc$libresoc.v:190471$14030 + attribute \src "libresoc.v:193292.7-193292.26" + process $proc$libresoc.v:193292$14143 + assign { } { } + assign $1\core_sv_a_nz[0:0] 1'0 + sync always + sync init + update \core_sv_a_nz $1\core_sv_a_nz[0:0] + end + attribute \src "libresoc.v:193302.7-193302.26" + process $proc$libresoc.v:193302$14144 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:190477.7-190477.30" - process $proc$libresoc.v:190477$14031 + attribute \src "libresoc.v:193308.7-193308.30" + process $proc$libresoc.v:193308$14145 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:190483.13-190483.36" - process $proc$libresoc.v:190483$14032 + attribute \src "libresoc.v:193314.13-193314.36" + process $proc$libresoc.v:193314$14146 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:190487.13-190487.34" - process $proc$libresoc.v:190487$14033 + attribute \src "libresoc.v:193318.13-193318.34" + process $proc$libresoc.v:193318$14147 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:190491.13-190491.36" - process $proc$libresoc.v:190491$14034 + attribute \src "libresoc.v:193322.13-193322.36" + process $proc$libresoc.v:193322$14148 assign { } { } assign $1\cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:190495.13-190495.33" - process $proc$libresoc.v:190495$14035 + attribute \src "libresoc.v:193326.13-193326.33" + process $proc$libresoc.v:193326$14149 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:190499.13-190499.34" - process $proc$libresoc.v:190499$14036 + attribute \src "libresoc.v:193330.13-193330.34" + process $proc$libresoc.v:193330$14150 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:190503.13-190503.31" - process $proc$libresoc.v:190503$14037 + attribute \src "libresoc.v:193334.13-193334.31" + process $proc$libresoc.v:193334$14151 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end - attribute \src "libresoc.v:190507.7-190507.24" - process $proc$libresoc.v:190507$14038 + attribute \src "libresoc.v:193338.7-193338.24" + process $proc$libresoc.v:193338$14152 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:190511.7-190511.25" - process $proc$libresoc.v:190511$14039 + attribute \src "libresoc.v:193342.7-193342.25" + process $proc$libresoc.v:193342$14153 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:190515.7-190515.25" - process $proc$libresoc.v:190515$14040 + attribute \src "libresoc.v:193346.7-193346.25" + process $proc$libresoc.v:193346$14154 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:190563.13-190563.34" - process $proc$libresoc.v:190563$14041 + attribute \src "libresoc.v:193394.13-193394.34" + process $proc$libresoc.v:193394$14155 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:190567.14-190567.48" - process $proc$libresoc.v:190567$14042 + attribute \src "libresoc.v:193398.14-193398.48" + process $proc$libresoc.v:193398$14156 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:190573.7-190573.27" - process $proc$libresoc.v:190573$14043 + attribute \src "libresoc.v:193404.7-193404.27" + process $proc$libresoc.v:193404$14157 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:190577.7-190577.26" - process $proc$libresoc.v:190577$14044 + attribute \src "libresoc.v:193408.7-193408.26" + process $proc$libresoc.v:193408$14158 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:190631.14-190631.49" - process $proc$libresoc.v:190631$14045 + attribute \src "libresoc.v:193462.14-193462.49" + process $proc$libresoc.v:193462$14159 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:190635.7-190635.27" - process $proc$libresoc.v:190635$14046 + attribute \src "libresoc.v:193466.7-193466.27" + process $proc$libresoc.v:193466$14160 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:190639.14-190639.49" - process $proc$libresoc.v:190639$14047 + attribute \src "libresoc.v:193470.14-193470.49" + process $proc$libresoc.v:193470$14161 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:190643.14-190643.48" - process $proc$libresoc.v:190643$14048 + attribute \src "libresoc.v:193474.14-193474.48" + process $proc$libresoc.v:193474$14162 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:190793.14-190793.40" - process $proc$libresoc.v:190793$14049 + attribute \src "libresoc.v:193626.14-193626.40" + process $proc$libresoc.v:193626$14163 assign { } { } assign $1\dec2_raw_opcode_in[31:0] 0 sync always sync init update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:191061.13-191061.25" - process $proc$libresoc.v:191061$14050 + attribute \src "libresoc.v:193896.13-193896.25" + process $proc$libresoc.v:193896$14164 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:191077.7-191077.28" - process $proc$libresoc.v:191077$14051 + attribute \src "libresoc.v:193912.7-193912.28" + process $proc$libresoc.v:193912$14165 assign { } { } assign $1\exec_fsm_state[0:0] 1'0 sync always sync init update \exec_fsm_state $1\exec_fsm_state[0:0] end - attribute \src "libresoc.v:191089.13-191089.35" - process $proc$libresoc.v:191089$14052 + attribute \src "libresoc.v:193924.13-193924.35" + process $proc$libresoc.v:193924$14166 assign { } { } assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:191101.13-191101.29" - process $proc$libresoc.v:191101$14053 + attribute \src "libresoc.v:193936.13-193936.29" + process $proc$libresoc.v:193936$14167 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:191357.13-191357.35" - process $proc$libresoc.v:191357$14054 + attribute \src "libresoc.v:194196.13-194196.35" + process $proc$libresoc.v:194196$14168 assign { } { } assign $1\issue_fsm_state[2:0] 3'000 sync always sync init update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:191361.7-191361.30" - process $proc$libresoc.v:191361$14055 + attribute \src "libresoc.v:194200.7-194200.30" + process $proc$libresoc.v:194200$14169 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:191369.14-191369.52" - process $proc$libresoc.v:191369$14056 + attribute \src "libresoc.v:194208.14-194208.52" + process $proc$libresoc.v:194208$14170 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:191425.7-191425.22" - process $proc$libresoc.v:191425$14057 + attribute \src "libresoc.v:194266.7-194266.22" + process $proc$libresoc.v:194266$14171 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:191463.14-191463.40" - process $proc$libresoc.v:191463$14058 + attribute \src "libresoc.v:194304.14-194304.40" + process $proc$libresoc.v:194304$14172 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:191469.7-191469.24" - process $proc$libresoc.v:191469$14059 + attribute \src "libresoc.v:194310.7-194310.24" + process $proc$libresoc.v:194310$14173 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:191479.7-191479.25" - process $proc$libresoc.v:191479$14060 + attribute \src "libresoc.v:194320.7-194320.25" + process $proc$libresoc.v:194320$14174 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:191851.7-191851.24" - process $proc$libresoc.v:191851$14061 + attribute \src "libresoc.v:194764.7-194764.24" + process $proc$libresoc.v:194764$14175 assign { } { } assign $1\sv_changed[0:0] 1'0 sync always sync init update \sv_changed $1\sv_changed[0:0] end - attribute \src "libresoc.v:191861.7-191861.30" - process $proc$libresoc.v:191861$14062 + attribute \src "libresoc.v:194774.7-194774.30" + process $proc$libresoc.v:194774$14176 assign { } { } assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init update \svstate_ok_delay $1\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:191997.3-191998.41" - process $proc$libresoc.v:191997$13375 + attribute \src "libresoc.v:194913.3-194914.41" + process $proc$libresoc.v:194913$13481 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:191999.3-192000.33" - process $proc$libresoc.v:191999$13376 + attribute \src "libresoc.v:194915.3-194916.41" + process $proc$libresoc.v:194915$13482 assign { } { } - assign $0\core_msr[63:0] \core_msr$next + assign $0\core_core_pc[63:0] \core_core_pc$next sync posedge \clk - update \core_msr $0\core_msr[63:0] + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "libresoc.v:194917.3-194918.49" + process $proc$libresoc.v:194917$13483 + assign { } { } + assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next + sync posedge \clk + update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:192001.3-192002.39" - process $proc$libresoc.v:192001$13377 + attribute \src "libresoc.v:194919.3-194920.39" + process $proc$libresoc.v:194919$13484 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:192003.3-192004.41" - process $proc$libresoc.v:192003$13378 + attribute \src "libresoc.v:194921.3-194922.41" + process $proc$libresoc.v:194921$13485 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:192005.3-192006.43" - process $proc$libresoc.v:192005$13379 + attribute \src "libresoc.v:194923.3-194924.43" + process $proc$libresoc.v:194923$13486 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:192007.3-192008.45" - process $proc$libresoc.v:192007$13380 + attribute \src "libresoc.v:194925.3-194926.45" + process $proc$libresoc.v:194925$13487 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:192009.3-192010.35" - process $proc$libresoc.v:192009$13381 + attribute \src "libresoc.v:194927.3-194928.33" + process $proc$libresoc.v:194927$13488 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:194929.3-194930.35" + process $proc$libresoc.v:194929$13489 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:192011.3-192012.33" - process $proc$libresoc.v:192011$13382 + attribute \src "libresoc.v:194931.3-194932.33" + process $proc$libresoc.v:194931$13490 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:192013.3-192014.49" - process $proc$libresoc.v:192013$13383 + attribute \src "libresoc.v:194933.3-194934.49" + process $proc$libresoc.v:194933$13491 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:192015.3-192016.47" - process $proc$libresoc.v:192015$13384 + attribute \src "libresoc.v:194935.3-194936.47" + process $proc$libresoc.v:194935$13492 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:192017.3-192018.51" - process $proc$libresoc.v:192017$13385 + attribute \src "libresoc.v:194937.3-194938.51" + process $proc$libresoc.v:194937$13493 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:192019.3-192020.51" - process $proc$libresoc.v:192019$13386 + attribute \src "libresoc.v:194939.3-194940.51" + process $proc$libresoc.v:194939$13494 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:192021.3-192022.41" - process $proc$libresoc.v:192021$13387 + attribute \src "libresoc.v:194941.3-194942.41" + process $proc$libresoc.v:194941$13495 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:192023.3-192024.47" - process $proc$libresoc.v:192023$13388 + attribute \src "libresoc.v:194943.3-194944.47" + process $proc$libresoc.v:194943$13496 assign { } { } assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:192025.3-192026.41" - process $proc$libresoc.v:192025$13389 + attribute \src "libresoc.v:194945.3-194946.35" + process $proc$libresoc.v:194945$13497 assign { } { } - assign $0\core_asmcode[7:0] \core_asmcode$next + assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk - update \core_asmcode $0\core_asmcode[7:0] + update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:192027.3-192028.35" - process $proc$libresoc.v:192027$13390 + attribute \src "libresoc.v:194947.3-194948.41" + process $proc$libresoc.v:194947$13498 assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next + assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk - update \fsm_state $0\fsm_state[1:0] + update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:192029.3-192030.45" - process $proc$libresoc.v:192029$13391 + attribute \src "libresoc.v:194949.3-194950.45" + process $proc$libresoc.v:194949$13499 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:192031.3-192032.41" - process $proc$libresoc.v:192031$13392 + attribute \src "libresoc.v:194951.3-194952.41" + process $proc$libresoc.v:194951$13500 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:192033.3-192034.41" - process $proc$libresoc.v:192033$13393 + attribute \src "libresoc.v:194953.3-194954.41" + process $proc$libresoc.v:194953$13501 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:192035.3-192036.37" - process $proc$libresoc.v:192035$13394 + attribute \src "libresoc.v:194955.3-194956.37" + process $proc$libresoc.v:194955$13502 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:192037.3-192038.45" - process $proc$libresoc.v:192037$13395 + attribute \src "libresoc.v:194957.3-194958.45" + process $proc$libresoc.v:194957$13503 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:192039.3-192040.51" - process $proc$libresoc.v:192039$13396 + attribute \src "libresoc.v:194959.3-194960.51" + process $proc$libresoc.v:194959$13504 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:192041.3-192042.45" - process $proc$libresoc.v:192041$13397 + attribute \src "libresoc.v:194961.3-194962.45" + process $proc$libresoc.v:194961$13505 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:192043.3-192044.51" - process $proc$libresoc.v:192043$13398 + attribute \src "libresoc.v:194963.3-194964.51" + process $proc$libresoc.v:194963$13506 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:192045.3-192046.45" - process $proc$libresoc.v:192045$13399 + attribute \src "libresoc.v:194965.3-194966.45" + process $proc$libresoc.v:194965$13507 assign { } { } assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:192047.3-192048.51" - process $proc$libresoc.v:192047$13400 + attribute \src "libresoc.v:194967.3-194968.39" + process $proc$libresoc.v:194967$13508 assign { } { } - assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next + assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk - update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] + update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:192049.3-192050.39" - process $proc$libresoc.v:192049$13401 + attribute \src "libresoc.v:194969.3-194970.51" + process $proc$libresoc.v:194969$13509 assign { } { } - assign $0\d_xer_delay[0:0] \d_xer_delay$next + assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk - update \d_xer_delay $0\d_xer_delay[0:0] + update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:192051.3-192052.45" - process $proc$libresoc.v:192051$13402 + attribute \src "libresoc.v:194971.3-194972.45" + process $proc$libresoc.v:194971$13510 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:192053.3-192054.41" - process $proc$libresoc.v:192053$13403 + attribute \src "libresoc.v:194973.3-194974.41" + process $proc$libresoc.v:194973$13511 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:192055.3-192056.45" - process $proc$libresoc.v:192055$13404 + attribute \src "libresoc.v:194975.3-194976.45" + process $proc$libresoc.v:194975$13512 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:192057.3-192058.51" - process $proc$libresoc.v:192057$13405 + attribute \src "libresoc.v:194977.3-194978.51" + process $proc$libresoc.v:194977$13513 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:192059.3-192060.49" - process $proc$libresoc.v:192059$13406 + attribute \src "libresoc.v:194979.3-194980.49" + process $proc$libresoc.v:194979$13514 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:192061.3-192062.41" - process $proc$libresoc.v:192061$13407 + attribute \src "libresoc.v:194981.3-194982.41" + process $proc$libresoc.v:194981$13515 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:192063.3-192064.47" - process $proc$libresoc.v:192063$13408 + attribute \src "libresoc.v:194983.3-194984.47" + process $proc$libresoc.v:194983$13516 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:192065.3-192066.53" - process $proc$libresoc.v:192065$13409 + attribute \src "libresoc.v:194985.3-194986.53" + process $proc$libresoc.v:194985$13517 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:192067.3-192068.47" - process $proc$libresoc.v:192067$13410 + attribute \src "libresoc.v:194987.3-194988.47" + process $proc$libresoc.v:194987$13518 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:192069.3-192070.53" - process $proc$libresoc.v:192069$13411 + attribute \src "libresoc.v:194989.3-194990.37" + process $proc$libresoc.v:194989$13519 assign { } { } - assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next + assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk - update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] + update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:192071.3-192072.37" - process $proc$libresoc.v:192071$13412 + attribute \src "libresoc.v:194991.3-194992.53" + process $proc$libresoc.v:194991$13520 assign { } { } - assign $0\d_cr_delay[0:0] \d_cr_delay$next + assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk - update \d_cr_delay $0\d_cr_delay[0:0] + update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:192073.3-192074.49" - process $proc$libresoc.v:192073$13413 + attribute \src "libresoc.v:194993.3-194994.49" + process $proc$libresoc.v:194993$13521 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:192075.3-192076.45" - process $proc$libresoc.v:192075$13414 + attribute \src "libresoc.v:194995.3-194996.45" + process $proc$libresoc.v:194995$13522 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:192077.3-192078.49" - process $proc$libresoc.v:192077$13415 + attribute \src "libresoc.v:194997.3-194998.49" + process $proc$libresoc.v:194997$13523 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:192079.3-192080.45" - process $proc$libresoc.v:192079$13416 + attribute \src "libresoc.v:194999.3-195000.45" + process $proc$libresoc.v:194999$13524 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:192081.3-192082.49" - process $proc$libresoc.v:192081$13417 + attribute \src "libresoc.v:195001.3-195002.49" + process $proc$libresoc.v:195001$13525 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:192083.3-192084.55" - process $proc$libresoc.v:192083$13418 + attribute \src "libresoc.v:195003.3-195004.55" + process $proc$libresoc.v:195003$13526 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:192085.3-192086.49" - process $proc$libresoc.v:192085$13419 + attribute \src "libresoc.v:195005.3-195006.49" + process $proc$libresoc.v:195005$13527 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:192087.3-192088.55" - process $proc$libresoc.v:192087$13420 + attribute \src "libresoc.v:195007.3-195008.55" + process $proc$libresoc.v:195007$13528 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:192089.3-192090.55" - process $proc$libresoc.v:192089$13421 + attribute \src "libresoc.v:195009.3-195010.55" + process $proc$libresoc.v:195009$13529 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13422 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[6:0]$13530 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13422 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13530 end - attribute \src "libresoc.v:192091.3-192092.61" - process $proc$libresoc.v:192091$13423 + attribute \src "libresoc.v:195011.3-195012.39" + process $proc$libresoc.v:195011$13531 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13424 \core_core_cr_in2_ok$2$next + assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13424 + update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:192093.3-192094.39" - process $proc$libresoc.v:192093$13425 + attribute \src "libresoc.v:195013.3-195014.61" + process $proc$libresoc.v:195013$13532 assign { } { } - assign $0\d_reg_delay[0:0] \d_reg_delay$next + assign $0\core_core_cr_in2_ok$2[0:0]$13533 \core_core_cr_in2_ok$2$next sync posedge \clk - update \d_reg_delay $0\d_reg_delay[0:0] + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13533 end - attribute \src "libresoc.v:192095.3-192096.49" - process $proc$libresoc.v:192095$13426 + attribute \src "libresoc.v:195015.3-195016.49" + process $proc$libresoc.v:195015$13534 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:192097.3-192098.45" - process $proc$libresoc.v:192097$13427 + attribute \src "libresoc.v:195017.3-195018.45" + process $proc$libresoc.v:195017$13535 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:192099.3-192100.53" - process $proc$libresoc.v:192099$13428 + attribute \src "libresoc.v:195019.3-195020.53" + process $proc$libresoc.v:195019$13536 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:192101.3-192102.53" - process $proc$libresoc.v:192101$13429 + attribute \src "libresoc.v:195021.3-195022.53" + process $proc$libresoc.v:195021$13537 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:192103.3-192104.55" - process $proc$libresoc.v:192103$13430 + attribute \src "libresoc.v:195023.3-195024.55" + process $proc$libresoc.v:195023$13538 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:192105.3-192106.65" - process $proc$libresoc.v:192105$13431 + attribute \src "libresoc.v:195025.3-195026.65" + process $proc$libresoc.v:195025$13539 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:192107.3-192108.61" - process $proc$libresoc.v:192107$13432 + attribute \src "libresoc.v:195027.3-195028.61" + process $proc$libresoc.v:195027$13540 assign { } { } - assign $0\core_core_core_fn_unit[12:0] \core_core_core_fn_unit$next + assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk - update \core_core_core_fn_unit $0\core_core_core_fn_unit[12:0] + update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:192109.3-192110.41" - process $proc$libresoc.v:192109$13433 + attribute \src "libresoc.v:195029.3-195030.41" + process $proc$libresoc.v:195029$13541 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:192111.3-192112.51" - process $proc$libresoc.v:192111$13434 + attribute \src "libresoc.v:195031.3-195032.51" + process $proc$libresoc.v:195031$13542 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:192113.3-192114.57" - process $proc$libresoc.v:192113$13435 + attribute \src "libresoc.v:195033.3-195034.45" + process $proc$libresoc.v:195033$13543 assign { } { } - assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next + assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk - update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] + update \exec_fsm_state $0\exec_fsm_state[0:0] end - attribute \src "libresoc.v:192115.3-192116.45" - process $proc$libresoc.v:192115$13436 + attribute \src "libresoc.v:195035.3-195036.57" + process $proc$libresoc.v:195035$13544 assign { } { } - assign $0\exec_fsm_state[0:0] \exec_fsm_state$next + assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk - update \exec_fsm_state $0\exec_fsm_state[0:0] + update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:192117.3-192118.51" - process $proc$libresoc.v:192117$13437 + attribute \src "libresoc.v:195037.3-195038.51" + process $proc$libresoc.v:195037$13545 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:192119.3-192120.57" - process $proc$libresoc.v:192119$13438 + attribute \src "libresoc.v:195039.3-195040.57" + process $proc$libresoc.v:195039$13546 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:192121.3-192122.69" - process $proc$libresoc.v:192121$13439 + attribute \src "libresoc.v:195041.3-195042.69" + process $proc$libresoc.v:195041$13547 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:192123.3-192124.63" - process $proc$libresoc.v:192123$13440 + attribute \src "libresoc.v:195043.3-195044.63" + process $proc$libresoc.v:195043$13548 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:192125.3-192126.71" - process $proc$libresoc.v:192125$13441 + attribute \src "libresoc.v:195045.3-195046.71" + process $proc$libresoc.v:195045$13549 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13442 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13550 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13442 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13550 end - attribute \src "libresoc.v:192127.3-192128.75" - process $proc$libresoc.v:192127$13443 + attribute \src "libresoc.v:195047.3-195048.75" + process $proc$libresoc.v:195047$13551 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13444 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13552 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13444 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13552 end - attribute \src "libresoc.v:192129.3-192130.75" - process $proc$libresoc.v:192129$13445 + attribute \src "libresoc.v:195049.3-195050.75" + process $proc$libresoc.v:195049$13553 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13446 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13554 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13446 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13554 end - attribute \src "libresoc.v:192131.3-192132.75" - process $proc$libresoc.v:192131$13447 + attribute \src "libresoc.v:195051.3-195052.75" + process $proc$libresoc.v:195051$13555 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13448 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13556 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13448 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13556 end - attribute \src "libresoc.v:192133.3-192134.75" - process $proc$libresoc.v:192133$13449 + attribute \src "libresoc.v:195053.3-195054.75" + process $proc$libresoc.v:195053$13557 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13450 \core_core_core_exc_$signal$6$next + assign $0\core_core_core_exc_$signal$6[0:0]$13558 \core_core_core_exc_$signal$6$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13450 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13558 end - attribute \src "libresoc.v:192135.3-192136.75" - process $proc$libresoc.v:192135$13451 + attribute \src "libresoc.v:195055.3-195056.41" + process $proc$libresoc.v:195055$13559 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13452 \core_core_core_exc_$signal$7$next + assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13452 + update \core_sv_a_nz $0\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:192137.3-192138.57" - process $proc$libresoc.v:192137$13453 + attribute \src "libresoc.v:195057.3-195058.75" + process $proc$libresoc.v:195057$13560 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13454 \core_bigendian_i$10$next + assign $0\core_core_core_exc_$signal$7[0:0]$13561 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13454 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13561 end - attribute \src "libresoc.v:192139.3-192140.75" - process $proc$libresoc.v:192139$13455 + attribute \src "libresoc.v:195059.3-195060.75" + process $proc$libresoc.v:195059$13562 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13456 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$8[0:0]$13563 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13456 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13563 end - attribute \src "libresoc.v:192141.3-192142.75" - process $proc$libresoc.v:192141$13457 + attribute \src "libresoc.v:195061.3-195062.75" + process $proc$libresoc.v:195061$13564 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13458 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$9[0:0]$13565 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13458 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13565 end - attribute \src "libresoc.v:192143.3-192144.63" - process $proc$libresoc.v:192143$13459 + attribute \src "libresoc.v:195063.3-195064.63" + process $proc$libresoc.v:195063$13566 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:192145.3-192146.57" - process $proc$libresoc.v:192145$13460 + attribute \src "libresoc.v:195065.3-195066.57" + process $proc$libresoc.v:195065$13567 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:192147.3-192148.63" - process $proc$libresoc.v:192147$13461 + attribute \src "libresoc.v:195067.3-195068.63" + process $proc$libresoc.v:195067$13568 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:192149.3-192150.57" - process $proc$libresoc.v:192149$13462 + attribute \src "libresoc.v:195069.3-195070.57" + process $proc$libresoc.v:195069$13569 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:192151.3-192152.53" - process $proc$libresoc.v:192151$13463 + attribute \src "libresoc.v:195071.3-195072.53" + process $proc$libresoc.v:195071$13570 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:192153.3-192154.63" - process $proc$libresoc.v:192153$13464 + attribute \src "libresoc.v:195073.3-195074.63" + process $proc$libresoc.v:195073$13571 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:192155.3-192156.37" - process $proc$libresoc.v:192155$13465 + attribute \src "libresoc.v:195075.3-195076.37" + process $proc$libresoc.v:195075$13572 assign { } { } assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk update \sv_changed $0\sv_changed[0:0] end - attribute \src "libresoc.v:192157.3-192158.37" - process $proc$libresoc.v:192157$13466 + attribute \src "libresoc.v:195077.3-195078.57" + process $proc$libresoc.v:195077$13573 assign { } { } - assign $0\pc_changed[0:0] \pc_changed$next + assign $0\core_bigendian_i$10[0:0]$13574 \core_bigendian_i$10$next sync posedge \clk - update \pc_changed $0\pc_changed[0:0] + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13574 end - attribute \src "libresoc.v:192159.3-192160.47" - process $proc$libresoc.v:192159$13467 + attribute \src "libresoc.v:195079.3-195080.37" + process $proc$libresoc.v:195079$13575 assign { } { } - assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next + assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk - update \core_raw_insn_i $0\core_raw_insn_i[31:0] + update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:192161.3-192162.47" - process $proc$libresoc.v:192161$13468 + attribute \src "libresoc.v:195081.3-195082.47" + process $proc$libresoc.v:195081$13576 assign { } { } assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:192163.3-192164.53" - process $proc$libresoc.v:192163$13469 + attribute \src "libresoc.v:195083.3-195084.53" + process $proc$libresoc.v:195083$13577 assign { } { } assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:192165.3-192166.23" - process $proc$libresoc.v:192165$13470 + attribute \src "libresoc.v:195085.3-195086.23" + process $proc$libresoc.v:195085$13578 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:192167.3-192168.41" - process $proc$libresoc.v:192167$13471 + attribute \src "libresoc.v:195087.3-195088.41" + process $proc$libresoc.v:195087$13579 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:192169.3-192170.47" - process $proc$libresoc.v:192169$13472 + attribute \src "libresoc.v:195089.3-195090.47" + process $proc$libresoc.v:195089$13580 assign { } { } assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk update \fetch_fsm_state $0\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:192171.3-192172.33" - process $proc$libresoc.v:192171$13473 + attribute \src "libresoc.v:195091.3-195092.33" + process $proc$libresoc.v:195091$13581 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:192173.3-192174.45" - process $proc$libresoc.v:192173$13474 + attribute \src "libresoc.v:195093.3-195094.45" + process $proc$libresoc.v:195093$13582 assign { } { } assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:192175.3-192176.43" - process $proc$libresoc.v:192175$13475 + attribute \src "libresoc.v:195095.3-195096.43" + process $proc$libresoc.v:195095$13583 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:192177.3-192178.47" - process $proc$libresoc.v:192177$13476 + attribute \src "libresoc.v:195097.3-195098.47" + process $proc$libresoc.v:195097$13584 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:192179.3-192180.47" - process $proc$libresoc.v:192179$13477 + attribute \src "libresoc.v:195099.3-195100.47" + process $proc$libresoc.v:195099$13585 assign { } { } - assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next + assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk - update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] + update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:192181.3-192182.41" - process $proc$libresoc.v:192181$13478 + attribute \src "libresoc.v:195101.3-195102.47" + process $proc$libresoc.v:195101$13586 assign { } { } - assign $0\core_core_pc[63:0] \core_core_pc$next + assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk - update \core_core_pc $0\core_core_pc[63:0] + update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:192183.3-192184.37" - process $proc$libresoc.v:192183$13479 + attribute \src "libresoc.v:195103.3-195104.37" + process $proc$libresoc.v:195103$13587 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end - attribute \src "libresoc.v:192185.3-192186.43" - process $proc$libresoc.v:192185$13480 + attribute \src "libresoc.v:195105.3-195106.43" + process $proc$libresoc.v:195105$13588 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:192187.3-192188.39" - process $proc$libresoc.v:192187$13481 + attribute \src "libresoc.v:195107.3-195108.39" + process $proc$libresoc.v:195107$13589 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:192189.3-192190.49" - process $proc$libresoc.v:192189$13482 + attribute \src "libresoc.v:195109.3-195110.49" + process $proc$libresoc.v:195109$13590 assign { } { } assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next sync posedge \clk update \svstate_ok_delay $0\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:192191.3-192192.39" - process $proc$libresoc.v:192191$13483 + attribute \src "libresoc.v:195111.3-195112.39" + process $proc$libresoc.v:195111$13591 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:192193.3-192194.43" - process $proc$libresoc.v:192193$13484 + attribute \src "libresoc.v:195113.3-195114.43" + process $proc$libresoc.v:195113$13592 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:192195.3-192196.27" - process $proc$libresoc.v:192195$13485 + attribute \src "libresoc.v:195115.3-195116.27" + process $proc$libresoc.v:195115$13593 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:192197.3-192198.43" - process $proc$libresoc.v:192197$13486 + attribute \src "libresoc.v:195117.3-195118.43" + process $proc$libresoc.v:195117$13594 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:192199.3-192200.47" - process $proc$libresoc.v:192199$13487 + attribute \src "libresoc.v:195119.3-195120.47" + process $proc$libresoc.v:195119$13595 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:192201.3-192202.49" - process $proc$libresoc.v:192201$13488 + attribute \src "libresoc.v:195751.3-195759.6" + process $proc$libresoc.v:195751$13596 assign { } { } - assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next - sync posedge \clk - update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + assign { } { } + assign $0\dbg_dmi_addr_i$next[3:0]$13597 $1\dbg_dmi_addr_i$next[3:0]$13598 + attribute \src "libresoc.v:195752.5-195752.29" + switch \initial + attribute \src "libresoc.v:195752.9-195752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_addr_i$next[3:0]$13598 4'0000 + case + assign $1\dbg_dmi_addr_i$next[3:0]$13598 \jtag_dmi0__addr_i + end + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13597 end - attribute \src "libresoc.v:192778.3-192786.6" - process $proc$libresoc.v:192778$13489 + attribute \src "libresoc.v:195760.3-195768.6" + process $proc$libresoc.v:195760$13599 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13490 $1\dbg_dmi_addr_i$next[3:0]$13491 - attribute \src "libresoc.v:192779.5-192779.29" + assign $0\dbg_dmi_req_i$next[0:0]$13600 $1\dbg_dmi_req_i$next[0:0]$13601 + attribute \src "libresoc.v:195761.5-195761.29" switch \initial - attribute \src "libresoc.v:192779.9-192779.17" + attribute \src "libresoc.v:195761.9-195761.17" case 1'1 case end @@ -403973,21 +408546,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13491 4'0000 + assign $1\dbg_dmi_req_i$next[0:0]$13601 1'0 case - assign $1\dbg_dmi_addr_i$next[3:0]$13491 \jtag_dmi0__addr_i + assign $1\dbg_dmi_req_i$next[0:0]$13601 \jtag_dmi0__req_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13490 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13600 end - attribute \src "libresoc.v:192787.3-192795.6" - process $proc$libresoc.v:192787$13492 + attribute \src "libresoc.v:195769.3-195777.6" + process $proc$libresoc.v:195769$13602 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13493 $1\dbg_dmi_req_i$next[0:0]$13494 - attribute \src "libresoc.v:192788.5-192788.29" + assign $0\dec2_cur_eint$next[0:0]$13603 $1\dec2_cur_eint$next[0:0]$13604 + attribute \src "libresoc.v:195770.5-195770.29" switch \initial - attribute \src "libresoc.v:192788.9-192788.17" + attribute \src "libresoc.v:195770.9-195770.17" case 1'1 case end @@ -403996,17 +408569,38 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13494 1'0 + assign $1\dec2_cur_eint$next[0:0]$13604 1'0 case - assign $1\dbg_dmi_req_i$next[0:0]$13494 \jtag_dmi0__req_i + assign $1\dec2_cur_eint$next[0:0]$13604 \xics_icp_core_irq_o end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13493 + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13603 end - attribute \src "libresoc.v:192796.3-192840.6" - process $proc$libresoc.v:192796$13495 + attribute \src "libresoc.v:195778.3-195787.6" + process $proc$libresoc.v:195778$13605 assign { } { } assign { } { } + assign $0\delay$next[1:0]$13606 $1\delay$next[1:0]$13607 + attribute \src "libresoc.v:195779.5-195779.29" + switch \initial + attribute \src "libresoc.v:195779.9-195779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$13607 \$25 [1:0] + case + assign $1\delay$next[1:0]$13607 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$13606 + end + attribute \src "libresoc.v:195788.3-195832.6" + process $proc$libresoc.v:195788$13608 assign { } { } assign { } { } assign { } { } @@ -404035,23 +408629,25 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_dststep$next[6:0]$13496 $3\core_core_dststep$next[6:0]$13526 - assign $0\core_core_maxvl$next[6:0]$13497 $3\core_core_maxvl$next[6:0]$13527 - assign $0\core_core_pc$next[63:0]$13498 $3\core_core_pc$next[63:0]$13528 - assign $0\core_core_srcstep$next[6:0]$13499 $3\core_core_srcstep$next[6:0]$13529 - assign $0\core_core_subvl$next[1:0]$13500 $3\core_core_subvl$next[1:0]$13530 - assign $0\core_core_svstep$next[1:0]$13501 $3\core_core_svstep$next[1:0]$13531 - assign $0\core_core_vl$next[6:0]$13502 $3\core_core_vl$next[6:0]$13532 - assign $0\core_dec$next[63:0]$13503 $3\core_dec$next[63:0]$13533 - assign $0\core_eint$next[0:0]$13504 $3\core_eint$next[0:0]$13534 - assign $0\core_msr$next[63:0]$13505 $3\core_msr$next[63:0]$13535 - attribute \src "libresoc.v:192797.5-192797.29" + assign { } { } + assign { } { } + assign $0\core_core_dststep$next[6:0]$13609 $3\core_core_dststep$next[6:0]$13639 + assign $0\core_core_maxvl$next[6:0]$13610 $3\core_core_maxvl$next[6:0]$13640 + assign $0\core_core_pc$next[63:0]$13611 $3\core_core_pc$next[63:0]$13641 + assign $0\core_core_srcstep$next[6:0]$13612 $3\core_core_srcstep$next[6:0]$13642 + assign $0\core_core_subvl$next[1:0]$13613 $3\core_core_subvl$next[1:0]$13643 + assign $0\core_core_svstep$next[1:0]$13614 $3\core_core_svstep$next[1:0]$13644 + assign $0\core_core_vl$next[6:0]$13615 $3\core_core_vl$next[6:0]$13645 + assign $0\core_dec$next[63:0]$13616 $3\core_dec$next[63:0]$13646 + assign $0\core_eint$next[0:0]$13617 $3\core_eint$next[0:0]$13647 + assign $0\core_msr$next[63:0]$13618 $3\core_msr$next[63:0]$13648 + attribute \src "libresoc.v:195789.5-195789.29" switch \initial - attribute \src "libresoc.v:192797.9-192797.17" + attribute \src "libresoc.v:195789.9-195789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -404065,17 +408661,17 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_core_dststep$next[6:0]$13506 $2\core_core_dststep$next[6:0]$13516 - assign $1\core_core_maxvl$next[6:0]$13507 $2\core_core_maxvl$next[6:0]$13517 - assign $1\core_core_pc$next[63:0]$13508 $2\core_core_pc$next[63:0]$13518 - assign $1\core_core_srcstep$next[6:0]$13509 $2\core_core_srcstep$next[6:0]$13519 - assign $1\core_core_subvl$next[1:0]$13510 $2\core_core_subvl$next[1:0]$13520 - assign $1\core_core_svstep$next[1:0]$13511 $2\core_core_svstep$next[1:0]$13521 - assign $1\core_core_vl$next[6:0]$13512 $2\core_core_vl$next[6:0]$13522 - assign $1\core_dec$next[63:0]$13513 $2\core_dec$next[63:0]$13523 - assign $1\core_eint$next[0:0]$13514 $2\core_eint$next[0:0]$13524 - assign $1\core_msr$next[63:0]$13515 $2\core_msr$next[63:0]$13525 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + assign $1\core_core_dststep$next[6:0]$13619 $2\core_core_dststep$next[6:0]$13629 + assign $1\core_core_maxvl$next[6:0]$13620 $2\core_core_maxvl$next[6:0]$13630 + assign $1\core_core_pc$next[63:0]$13621 $2\core_core_pc$next[63:0]$13631 + assign $1\core_core_srcstep$next[6:0]$13622 $2\core_core_srcstep$next[6:0]$13632 + assign $1\core_core_subvl$next[1:0]$13623 $2\core_core_subvl$next[1:0]$13633 + assign $1\core_core_svstep$next[1:0]$13624 $2\core_core_svstep$next[1:0]$13634 + assign $1\core_core_vl$next[6:0]$13625 $2\core_core_vl$next[6:0]$13635 + assign $1\core_dec$next[63:0]$13626 $2\core_dec$next[63:0]$13636 + assign $1\core_eint$next[0:0]$13627 $2\core_eint$next[0:0]$13637 + assign $1\core_msr$next[63:0]$13628 $2\core_msr$next[63:0]$13638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404089,18 +408685,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_maxvl$next[6:0]$13517 $2\core_core_vl$next[6:0]$13522 $2\core_core_srcstep$next[6:0]$13519 $2\core_core_dststep$next[6:0]$13516 $2\core_core_subvl$next[1:0]$13520 $2\core_core_svstep$next[1:0]$13521 $2\core_dec$next[63:0]$13523 $2\core_eint$next[0:0]$13524 $2\core_msr$next[63:0]$13525 $2\core_core_pc$next[63:0]$13518 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $2\core_core_maxvl$next[6:0]$13630 $2\core_core_vl$next[6:0]$13635 $2\core_core_srcstep$next[6:0]$13632 $2\core_core_dststep$next[6:0]$13629 $2\core_core_subvl$next[1:0]$13633 $2\core_core_svstep$next[1:0]$13634 $2\core_dec$next[63:0]$13636 $2\core_eint$next[0:0]$13637 $2\core_msr$next[63:0]$13638 $2\core_core_pc$next[63:0]$13631 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $2\core_core_dststep$next[6:0]$13516 \core_core_dststep - assign $2\core_core_maxvl$next[6:0]$13517 \core_core_maxvl - assign $2\core_core_pc$next[63:0]$13518 \core_core_pc - assign $2\core_core_srcstep$next[6:0]$13519 \core_core_srcstep - assign $2\core_core_subvl$next[1:0]$13520 \core_core_subvl - assign $2\core_core_svstep$next[1:0]$13521 \core_core_svstep - assign $2\core_core_vl$next[6:0]$13522 \core_core_vl - assign $2\core_dec$next[63:0]$13523 \core_dec - assign $2\core_eint$next[0:0]$13524 \core_eint - assign $2\core_msr$next[63:0]$13525 \core_msr + assign $2\core_core_dststep$next[6:0]$13629 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13630 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13631 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13632 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13633 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13634 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13635 \core_core_vl + assign $2\core_dec$next[63:0]$13636 \core_dec + assign $2\core_eint$next[0:0]$13637 \core_eint + assign $2\core_msr$next[63:0]$13638 \core_msr end attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -404114,18 +408710,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_maxvl$next[6:0]$13507 $1\core_core_vl$next[6:0]$13512 $1\core_core_srcstep$next[6:0]$13509 $1\core_core_dststep$next[6:0]$13506 $1\core_core_subvl$next[1:0]$13510 $1\core_core_svstep$next[1:0]$13511 $1\core_dec$next[63:0]$13513 $1\core_eint$next[0:0]$13514 $1\core_msr$next[63:0]$13515 $1\core_core_pc$next[63:0]$13508 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $1\core_core_maxvl$next[6:0]$13620 $1\core_core_vl$next[6:0]$13625 $1\core_core_srcstep$next[6:0]$13622 $1\core_core_dststep$next[6:0]$13619 $1\core_core_subvl$next[1:0]$13623 $1\core_core_svstep$next[1:0]$13624 $1\core_dec$next[63:0]$13626 $1\core_eint$next[0:0]$13627 $1\core_msr$next[63:0]$13628 $1\core_core_pc$next[63:0]$13621 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $1\core_core_dststep$next[6:0]$13506 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13507 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13508 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13509 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13510 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13511 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13512 \core_core_vl - assign $1\core_dec$next[63:0]$13513 \core_dec - assign $1\core_eint$next[0:0]$13514 \core_eint - assign $1\core_msr$next[63:0]$13515 \core_msr + assign $1\core_core_dststep$next[6:0]$13619 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13620 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13621 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13622 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13623 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13624 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13625 \core_core_vl + assign $1\core_dec$next[63:0]$13626 \core_dec + assign $1\core_eint$next[0:0]$13627 \core_eint + assign $1\core_msr$next[63:0]$13628 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -404141,140 +408737,255 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_core_pc$next[63:0]$13528 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13535 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13534 1'0 - assign $3\core_dec$next[63:0]$13533 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_core_svstep$next[1:0]$13531 2'00 - assign $3\core_core_subvl$next[1:0]$13530 2'00 - assign $3\core_core_dststep$next[6:0]$13526 7'0000000 - assign $3\core_core_srcstep$next[6:0]$13529 7'0000000 - assign $3\core_core_vl$next[6:0]$13532 7'0000000 - assign $3\core_core_maxvl$next[6:0]$13527 7'0000000 + assign $3\core_core_pc$next[63:0]$13641 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13648 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13647 1'0 + assign $3\core_dec$next[63:0]$13646 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13644 2'00 + assign $3\core_core_subvl$next[1:0]$13643 2'00 + assign $3\core_core_dststep$next[6:0]$13639 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13642 7'0000000 + assign $3\core_core_vl$next[6:0]$13645 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13640 7'0000000 + case + assign $3\core_core_dststep$next[6:0]$13639 $1\core_core_dststep$next[6:0]$13619 + assign $3\core_core_maxvl$next[6:0]$13640 $1\core_core_maxvl$next[6:0]$13620 + assign $3\core_core_pc$next[63:0]$13641 $1\core_core_pc$next[63:0]$13621 + assign $3\core_core_srcstep$next[6:0]$13642 $1\core_core_srcstep$next[6:0]$13622 + assign $3\core_core_subvl$next[1:0]$13643 $1\core_core_subvl$next[1:0]$13623 + assign $3\core_core_svstep$next[1:0]$13644 $1\core_core_svstep$next[1:0]$13624 + assign $3\core_core_vl$next[6:0]$13645 $1\core_core_vl$next[6:0]$13625 + assign $3\core_dec$next[63:0]$13646 $1\core_dec$next[63:0]$13626 + assign $3\core_eint$next[0:0]$13647 $1\core_eint$next[0:0]$13627 + assign $3\core_msr$next[63:0]$13648 $1\core_msr$next[63:0]$13628 + end + sync always + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13609 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13610 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13611 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13612 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13613 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13614 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13615 + update \core_dec$next $0\core_dec$next[63:0]$13616 + update \core_eint$next $0\core_eint$next[0:0]$13617 + update \core_msr$next $0\core_msr$next[63:0]$13618 + end + attribute \src "libresoc.v:195833.3-195853.6" + process $proc$libresoc.v:195833$13649 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_raw_insn_i$next[31:0]$13650 $3\core_raw_insn_i$next[31:0]$13653 + attribute \src "libresoc.v:195834.5-195834.29" + switch \initial + attribute \src "libresoc.v:195834.9-195834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13651 $2\core_raw_insn_i$next[31:0]$13652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_raw_insn_i$next[31:0]$13652 \dec2_raw_opcode_in + case + assign $2\core_raw_insn_i$next[31:0]$13652 \core_raw_insn_i + end + case + assign $1\core_raw_insn_i$next[31:0]$13651 \core_raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_raw_insn_i$next[31:0]$13653 0 case - assign $3\core_core_dststep$next[6:0]$13526 $1\core_core_dststep$next[6:0]$13506 - assign $3\core_core_maxvl$next[6:0]$13527 $1\core_core_maxvl$next[6:0]$13507 - assign $3\core_core_pc$next[63:0]$13528 $1\core_core_pc$next[63:0]$13508 - assign $3\core_core_srcstep$next[6:0]$13529 $1\core_core_srcstep$next[6:0]$13509 - assign $3\core_core_subvl$next[1:0]$13530 $1\core_core_subvl$next[1:0]$13510 - assign $3\core_core_svstep$next[1:0]$13531 $1\core_core_svstep$next[1:0]$13511 - assign $3\core_core_vl$next[6:0]$13532 $1\core_core_vl$next[6:0]$13512 - assign $3\core_dec$next[63:0]$13533 $1\core_dec$next[63:0]$13513 - assign $3\core_eint$next[0:0]$13534 $1\core_eint$next[0:0]$13514 - assign $3\core_msr$next[63:0]$13535 $1\core_msr$next[63:0]$13515 + assign $3\core_raw_insn_i$next[31:0]$13653 $1\core_raw_insn_i$next[31:0]$13651 end sync always - update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13496 - update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13497 - update \core_core_pc$next $0\core_core_pc$next[63:0]$13498 - update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13499 - update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13500 - update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13501 - update \core_core_vl$next $0\core_core_vl$next[6:0]$13502 - update \core_dec$next $0\core_dec$next[63:0]$13503 - update \core_eint$next $0\core_eint$next[0:0]$13504 - update \core_msr$next $0\core_msr$next[63:0]$13505 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13650 end - attribute \src "libresoc.v:192841.3-192861.6" - process $proc$libresoc.v:192841$13536 + attribute \src "libresoc.v:195854.3-195878.6" + process $proc$libresoc.v:195854$13654 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13537 $3\core_raw_insn_i$next[31:0]$13540 - attribute \src "libresoc.v:192842.5-192842.29" + assign $0\core_bigendian_i$10$next[0:0]$13655 $3\core_bigendian_i$10$next[0:0]$13658 + attribute \src "libresoc.v:195855.5-195855.29" switch \initial - attribute \src "libresoc.v:192842.9-192842.17" + attribute \src "libresoc.v:195855.9-195855.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13538 $2\core_raw_insn_i$next[31:0]$13539 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + assign $1\core_bigendian_i$10$next[0:0]$13656 $2\core_bigendian_i$10$next[0:0]$13657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13539 \dec2_raw_opcode_in + assign $2\core_bigendian_i$10$next[0:0]$13657 \core_bigendian_i case - assign $2\core_raw_insn_i$next[31:0]$13539 \core_raw_insn_i + assign $2\core_bigendian_i$10$next[0:0]$13657 \core_bigendian_i$10 end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13656 \core_bigendian_i case - assign $1\core_raw_insn_i$next[31:0]$13538 \core_raw_insn_i + assign $1\core_bigendian_i$10$next[0:0]$13656 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13540 0 + assign $3\core_bigendian_i$10$next[0:0]$13658 1'0 case - assign $3\core_raw_insn_i$next[31:0]$13540 $1\core_raw_insn_i$next[31:0]$13538 + assign $3\core_bigendian_i$10$next[0:0]$13658 $1\core_bigendian_i$10$next[0:0]$13656 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13537 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13655 end - attribute \src "libresoc.v:192862.3-192886.6" - process $proc$libresoc.v:192862$13541 + attribute \src "libresoc.v:195879.3-195903.6" + process $proc$libresoc.v:195879$13659 assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13542 $3\core_bigendian_i$10$next[0:0]$13545 - attribute \src "libresoc.v:192863.5-192863.29" + assign $0\core_sv_a_nz$next[0:0]$13660 $3\core_sv_a_nz$next[0:0]$13663 + attribute \src "libresoc.v:195880.5-195880.29" switch \initial - attribute \src "libresoc.v:192863.9-192863.17" + attribute \src "libresoc.v:195880.9-195880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13543 $2\core_bigendian_i$10$next[0:0]$13544 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + assign $1\core_sv_a_nz$next[0:0]$13661 $2\core_sv_a_nz$next[0:0]$13662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13544 \core_bigendian_i + assign $2\core_sv_a_nz$next[0:0]$13662 \dec2_sv_a_nz case - assign $2\core_bigendian_i$10$next[0:0]$13544 \core_bigendian_i$10 + assign $2\core_sv_a_nz$next[0:0]$13662 \core_sv_a_nz end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13543 \core_bigendian_i + assign $1\core_sv_a_nz$next[0:0]$13661 \dec2_sv_a_nz case - assign $1\core_bigendian_i$10$next[0:0]$13543 \core_bigendian_i$10 + assign $1\core_sv_a_nz$next[0:0]$13661 \core_sv_a_nz end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13545 1'0 + assign $3\core_sv_a_nz$next[0:0]$13663 1'0 + case + assign $3\core_sv_a_nz$next[0:0]$13663 $1\core_sv_a_nz$next[0:0]$13661 + end + sync always + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13660 + end + attribute \src "libresoc.v:195904.3-195941.6" + process $proc$libresoc.v:195904$13664 + assign { } { } + assign { } { } + assign { } { } + assign $0\insn_done[0:0] $4\insn_done[0:0] + attribute \src "libresoc.v:195905.5-195905.29" + switch \initial + attribute \src "libresoc.v:195905.9-195905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\insn_done[0:0] $2\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\insn_done[0:0] $3\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \$228 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\insn_done[0:0] 1'1 + case + assign $3\insn_done[0:0] 1'0 + end + case + assign $2\insn_done[0:0] 1'0 + end + case + assign $1\insn_done[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\insn_done[0:0] $5\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + switch \$230 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\insn_done[0:0] $6\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:460" + switch \exec_pc_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\insn_done[0:0] 1'1 + case + assign $6\insn_done[0:0] $1\insn_done[0:0] + end + case + assign $5\insn_done[0:0] $1\insn_done[0:0] + end case - assign $3\core_bigendian_i$10$next[0:0]$13545 $1\core_bigendian_i$10$next[0:0]$13543 + assign $4\insn_done[0:0] $1\insn_done[0:0] end sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13542 + update \insn_done $0\insn_done[0:0] end - attribute \src "libresoc.v:192887.3-192897.6" - process $proc$libresoc.v:192887$13546 + attribute \src "libresoc.v:195942.3-195952.6" + process $proc$libresoc.v:195942$13665 assign { } { } assign { } { } assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:192888.5-192888.29" + attribute \src "libresoc.v:195943.5-195943.29" switch \initial - attribute \src "libresoc.v:192888.9-192888.17" + attribute \src "libresoc.v:195943.9-195943.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'010 @@ -404286,25 +408997,25 @@ module \ti sync always update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] end - attribute \src "libresoc.v:192898.3-192913.6" - process $proc$libresoc.v:192898$13547 + attribute \src "libresoc.v:195953.3-195968.6" + process $proc$libresoc.v:195953$13666 assign { } { } assign { } { } assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:192899.5-192899.29" + attribute \src "libresoc.v:195954.5-195954.29" switch \initial - attribute \src "libresoc.v:192899.9-192899.17" + attribute \src "libresoc.v:195954.9-195954.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - switch \$230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$236 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -404318,35 +409029,35 @@ module \ti sync always update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end - attribute \src "libresoc.v:192914.3-192934.6" - process $proc$libresoc.v:192914$13548 + attribute \src "libresoc.v:195969.3-195989.6" + process $proc$libresoc.v:195969$13667 assign { } { } assign { } { } assign $0\next_srcstep[6:0] $1\next_srcstep[6:0] - attribute \src "libresoc.v:192915.5-192915.29" + attribute \src "libresoc.v:195970.5-195970.29" switch \initial - attribute \src "libresoc.v:192915.9-192915.17" + attribute \src "libresoc.v:195970.9-195970.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\next_srcstep[6:0] $2\next_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - switch \$236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$242 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\next_srcstep[6:0] $3\next_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\next_srcstep[6:0] \$238 [6:0] + assign $3\next_srcstep[6:0] \$244 [6:0] case assign $3\next_srcstep[6:0] 7'0000000 end @@ -404359,35 +409070,35 @@ module \ti sync always update \next_srcstep $0\next_srcstep[6:0] end - attribute \src "libresoc.v:192935.3-192955.6" - process $proc$libresoc.v:192935$13549 + attribute \src "libresoc.v:195990.3-196010.6" + process $proc$libresoc.v:195990$13668 assign { } { } assign { } { } assign $0\is_last[0:0] $1\is_last[0:0] - attribute \src "libresoc.v:192936.5-192936.29" + attribute \src "libresoc.v:195991.5-195991.29" switch \initial - attribute \src "libresoc.v:192936.9-192936.17" + attribute \src "libresoc.v:195991.9-195991.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\is_last[0:0] $2\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - switch \$245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$251 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\is_last[0:0] $3\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\is_last[0:0] \$247 + assign $3\is_last[0:0] \$253 case assign $3\is_last[0:0] 1'0 end @@ -404400,64 +409111,64 @@ module \ti sync always update \is_last $0\is_last[0:0] end - attribute \src "libresoc.v:192956.3-192965.6" - process $proc$libresoc.v:192956$13550 + attribute \src "libresoc.v:196011.3-196020.6" + process $proc$libresoc.v:196011$13669 assign { } { } assign { } { } - assign $0\core_wen$11[2:0]$13551 $1\core_wen$11[2:0]$13552 - attribute \src "libresoc.v:192957.5-192957.29" + assign $0\core_wen$11[2:0]$13670 $1\core_wen$11[2:0]$13671 + attribute \src "libresoc.v:196012.5-196012.29" switch \initial - attribute \src "libresoc.v:192957.9-192957.17" + attribute \src "libresoc.v:196012.9-196012.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:401" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_wen$11[2:0]$13552 3'100 + assign $1\core_wen$11[2:0]$13671 3'100 case - assign $1\core_wen$11[2:0]$13552 3'000 + assign $1\core_wen$11[2:0]$13671 3'000 end sync always - update \core_wen$11 $0\core_wen$11[2:0]$13551 + update \core_wen$11 $0\core_wen$11[2:0]$13670 end - attribute \src "libresoc.v:192966.3-192975.6" - process $proc$libresoc.v:192966$13553 + attribute \src "libresoc.v:196021.3-196030.6" + process $proc$libresoc.v:196021$13672 assign { } { } assign { } { } - assign $0\core_data_i$12[63:0]$13554 $1\core_data_i$12[63:0]$13555 - attribute \src "libresoc.v:192967.5-192967.29" + assign $0\core_data_i$12[63:0]$13673 $1\core_data_i$12[63:0]$13674 + attribute \src "libresoc.v:196022.5-196022.29" switch \initial - attribute \src "libresoc.v:192967.9-192967.17" + attribute \src "libresoc.v:196022.9-196022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:401" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_data_i$12[63:0]$13555 \$249 + assign $1\core_data_i$12[63:0]$13674 \$255 case - assign $1\core_data_i$12[63:0]$13555 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_data_i$12[63:0]$13674 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \core_data_i$12 $0\core_data_i$12[63:0]$13554 + update \core_data_i$12 $0\core_data_i$12[63:0]$13673 end - attribute \src "libresoc.v:192976.3-192986.6" - process $proc$libresoc.v:192976$13556 + attribute \src "libresoc.v:196031.3-196041.6" + process $proc$libresoc.v:196031$13675 assign { } { } assign { } { } assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:192977.5-192977.29" + attribute \src "libresoc.v:196032.5-196032.29" switch \initial - attribute \src "libresoc.v:192977.9-192977.17" + attribute \src "libresoc.v:196032.9-196032.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 @@ -404469,24 +409180,24 @@ module \ti sync always update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] end - attribute \src "libresoc.v:192987.3-193011.6" - process $proc$libresoc.v:192987$13557 + attribute \src "libresoc.v:196042.3-196066.6" + process $proc$libresoc.v:196042$13676 assign { } { } assign { } { } assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:192988.5-192988.29" + attribute \src "libresoc.v:196043.5-196043.29" switch \initial - attribute \src "libresoc.v:192988.9-192988.17" + attribute \src "libresoc.v:196043.9-196043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404499,8 +409210,8 @@ module \ti case 1'1 assign { } { } assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:441" - switch \$251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" + switch \$257 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -404514,24 +409225,24 @@ module \ti sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:193012.3-193027.6" - process $proc$libresoc.v:193012$13558 + attribute \src "libresoc.v:196067.3-196082.6" + process $proc$libresoc.v:196067$13677 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:193013.5-193013.29" + attribute \src "libresoc.v:196068.5-196068.29" switch \initial - attribute \src "libresoc.v:193013.9-193013.17" + attribute \src "libresoc.v:196068.9-196068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404546,89 +409257,89 @@ module \ti sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:193028.3-193062.6" - process $proc$libresoc.v:193028$13559 + attribute \src "libresoc.v:196083.3-196117.6" + process $proc$libresoc.v:196083$13678 assign { } { } assign { } { } assign { } { } - assign $0\exec_fsm_state$next[0:0]$13560 $5\exec_fsm_state$next[0:0]$13565 - attribute \src "libresoc.v:193029.5-193029.29" + assign $0\exec_fsm_state$next[0:0]$13679 $5\exec_fsm_state$next[0:0]$13684 + attribute \src "libresoc.v:196084.5-196084.29" switch \initial - attribute \src "libresoc.v:193029.9-193029.17" + attribute \src "libresoc.v:196084.9-196084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13561 $2\exec_fsm_state$next[0:0]$13562 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432" + assign $1\exec_fsm_state$next[0:0]$13680 $2\exec_fsm_state$next[0:0]$13681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\exec_fsm_state$next[0:0]$13562 1'1 + assign $2\exec_fsm_state$next[0:0]$13681 1'1 case - assign $2\exec_fsm_state$next[0:0]$13562 \exec_fsm_state + assign $2\exec_fsm_state$next[0:0]$13681 \exec_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13561 $3\exec_fsm_state$next[0:0]$13563 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448" - switch \$253 + assign $1\exec_fsm_state$next[0:0]$13680 $3\exec_fsm_state$next[0:0]$13682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + switch \$259 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\exec_fsm_state$next[0:0]$13563 $4\exec_fsm_state$next[0:0]$13564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:450" + assign $3\exec_fsm_state$next[0:0]$13682 $4\exec_fsm_state$next[0:0]$13683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:460" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\exec_fsm_state$next[0:0]$13564 1'0 + assign $4\exec_fsm_state$next[0:0]$13683 1'0 case - assign $4\exec_fsm_state$next[0:0]$13564 \exec_fsm_state + assign $4\exec_fsm_state$next[0:0]$13683 \exec_fsm_state end case - assign $3\exec_fsm_state$next[0:0]$13563 \exec_fsm_state + assign $3\exec_fsm_state$next[0:0]$13682 \exec_fsm_state end case - assign $1\exec_fsm_state$next[0:0]$13561 \exec_fsm_state + assign $1\exec_fsm_state$next[0:0]$13680 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\exec_fsm_state$next[0:0]$13565 1'0 + assign $5\exec_fsm_state$next[0:0]$13684 1'0 case - assign $5\exec_fsm_state$next[0:0]$13565 $1\exec_fsm_state$next[0:0]$13561 + assign $5\exec_fsm_state$next[0:0]$13684 $1\exec_fsm_state$next[0:0]$13680 end sync always - update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13560 + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13679 end - attribute \src "libresoc.v:193063.3-193078.6" - process $proc$libresoc.v:193063$13566 + attribute \src "libresoc.v:196118.3-196133.6" + process $proc$libresoc.v:196118$13685 assign { } { } assign { } { } assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:193064.5-193064.29" + attribute \src "libresoc.v:196119.5-196119.29" switch \initial - attribute \src "libresoc.v:193064.9-193064.17" + attribute \src "libresoc.v:196119.9-196119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448" - switch \$255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + switch \$261 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -404642,18 +409353,18 @@ module \ti sync always update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] end - attribute \src "libresoc.v:193079.3-193088.6" - process $proc$libresoc.v:193079$13567 + attribute \src "libresoc.v:196134.3-196143.6" + process $proc$libresoc.v:196134$13686 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:193080.5-193080.29" + attribute \src "libresoc.v:196135.5-196135.29" switch \initial - attribute \src "libresoc.v:193080.9-193080.17" + attribute \src "libresoc.v:196135.9-196135.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404665,18 +409376,18 @@ module \ti sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:193089.3-193098.6" - process $proc$libresoc.v:193089$13568 + attribute \src "libresoc.v:196144.3-196153.6" + process $proc$libresoc.v:196144$13687 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:193090.5-193090.29" + attribute \src "libresoc.v:196145.5-196145.29" switch \initial - attribute \src "libresoc.v:193090.9-193090.17" + attribute \src "libresoc.v:196145.9-196145.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404688,14 +409399,14 @@ module \ti sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:193099.3-193107.6" - process $proc$libresoc.v:193099$13569 + attribute \src "libresoc.v:196154.3-196162.6" + process $proc$libresoc.v:196154$13688 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13570 $1\d_reg_delay$next[0:0]$13571 - attribute \src "libresoc.v:193100.5-193100.29" + assign $0\d_reg_delay$next[0:0]$13689 $1\d_reg_delay$next[0:0]$13690 + attribute \src "libresoc.v:196155.5-196155.29" switch \initial - attribute \src "libresoc.v:193100.9-193100.17" + attribute \src "libresoc.v:196155.9-196155.17" case 1'1 case end @@ -404704,25 +409415,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13571 1'0 + assign $1\d_reg_delay$next[0:0]$13690 1'0 case - assign $1\d_reg_delay$next[0:0]$13571 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13690 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13570 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13689 end - attribute \src "libresoc.v:193108.3-193117.6" - process $proc$libresoc.v:193108$13572 + attribute \src "libresoc.v:196163.3-196172.6" + process $proc$libresoc.v:196163$13691 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:193109.5-193109.29" + attribute \src "libresoc.v:196164.5-196164.29" switch \initial - attribute \src "libresoc.v:193109.9-193109.17" + attribute \src "libresoc.v:196164.9-196164.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404734,18 +409445,18 @@ module \ti sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:193118.3-193127.6" - process $proc$libresoc.v:193118$13573 + attribute \src "libresoc.v:196173.3-196182.6" + process $proc$libresoc.v:196173$13692 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:193119.5-193119.29" + attribute \src "libresoc.v:196174.5-196174.29" switch \initial - attribute \src "libresoc.v:193119.9-193119.17" + attribute \src "libresoc.v:196174.9-196174.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:649" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404757,18 +409468,18 @@ module \ti sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:193128.3-193137.6" - process $proc$libresoc.v:193128$13574 + attribute \src "libresoc.v:196183.3-196192.6" + process $proc$libresoc.v:196183$13693 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:193129.5-193129.29" + attribute \src "libresoc.v:196184.5-196184.29" switch \initial - attribute \src "libresoc.v:193129.9-193129.17" + attribute \src "libresoc.v:196184.9-196184.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404780,14 +409491,14 @@ module \ti sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:193138.3-193146.6" - process $proc$libresoc.v:193138$13575 + attribute \src "libresoc.v:196193.3-196201.6" + process $proc$libresoc.v:196193$13694 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13576 $1\d_cr_delay$next[0:0]$13577 - attribute \src "libresoc.v:193139.5-193139.29" + assign $0\d_cr_delay$next[0:0]$13695 $1\d_cr_delay$next[0:0]$13696 + attribute \src "libresoc.v:196194.5-196194.29" switch \initial - attribute \src "libresoc.v:193139.9-193139.17" + attribute \src "libresoc.v:196194.9-196194.17" case 1'1 case end @@ -404796,48 +409507,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13577 1'0 + assign $1\d_cr_delay$next[0:0]$13696 1'0 case - assign $1\d_cr_delay$next[0:0]$13577 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13696 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13576 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13695 end - attribute \src "libresoc.v:193147.3-193156.6" - process $proc$libresoc.v:193147$13578 + attribute \src "libresoc.v:196202.3-196211.6" + process $proc$libresoc.v:196202$13697 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:193148.5-193148.29" + attribute \src "libresoc.v:196203.5-196203.29" switch \initial - attribute \src "libresoc.v:193148.9-193148.17" + attribute \src "libresoc.v:196203.9-196203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$257 + assign $1\dbg_d_cr_data[63:0] \$263 case assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:193157.3-193166.6" - process $proc$libresoc.v:193157$13579 + attribute \src "libresoc.v:196212.3-196221.6" + process $proc$libresoc.v:196212$13698 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:193158.5-193158.29" + attribute \src "libresoc.v:196213.5-196213.29" switch \initial - attribute \src "libresoc.v:193158.9-193158.17" + attribute \src "libresoc.v:196213.9-196213.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404849,18 +409560,18 @@ module \ti sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:193167.3-193176.6" - process $proc$libresoc.v:193167$13580 + attribute \src "libresoc.v:196222.3-196231.6" + process $proc$libresoc.v:196222$13699 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:193168.5-193168.29" + attribute \src "libresoc.v:196223.5-196223.29" switch \initial - attribute \src "libresoc.v:193168.9-193168.17" + attribute \src "libresoc.v:196223.9-196223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404872,14 +409583,14 @@ module \ti sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:193177.3-193185.6" - process $proc$libresoc.v:193177$13581 + attribute \src "libresoc.v:196232.3-196240.6" + process $proc$libresoc.v:196232$13700 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13582 $1\d_xer_delay$next[0:0]$13583 - attribute \src "libresoc.v:193178.5-193178.29" + assign $0\d_xer_delay$next[0:0]$13701 $1\d_xer_delay$next[0:0]$13702 + attribute \src "libresoc.v:196233.5-196233.29" switch \initial - attribute \src "libresoc.v:193178.9-193178.17" + attribute \src "libresoc.v:196233.9-196233.17" case 1'1 case end @@ -404888,48 +409599,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13583 1'0 + assign $1\d_xer_delay$next[0:0]$13702 1'0 case - assign $1\d_xer_delay$next[0:0]$13583 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13702 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13582 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13701 end - attribute \src "libresoc.v:193186.3-193195.6" - process $proc$libresoc.v:193186$13584 + attribute \src "libresoc.v:196241.3-196250.6" + process $proc$libresoc.v:196241$13703 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:193187.5-193187.29" + attribute \src "libresoc.v:196242.5-196242.29" switch \initial - attribute \src "libresoc.v:193187.9-193187.17" + attribute \src "libresoc.v:196242.9-196242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$259 + assign $1\dbg_d_xer_data[63:0] \$265 case assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:193196.3-193205.6" - process $proc$libresoc.v:193196$13585 + attribute \src "libresoc.v:196251.3-196260.6" + process $proc$libresoc.v:196251$13704 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:193197.5-193197.29" + attribute \src "libresoc.v:196252.5-196252.29" switch \initial - attribute \src "libresoc.v:193197.9-193197.17" + attribute \src "libresoc.v:196252.9-196252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -404941,18 +409652,18 @@ module \ti sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:193206.3-193220.6" - process $proc$libresoc.v:193206$13586 + attribute \src "libresoc.v:196261.3-196275.6" + process $proc$libresoc.v:196261$13705 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:193207.5-193207.29" + attribute \src "libresoc.v:196262.5-196262.29" switch \initial - attribute \src "libresoc.v:193207.9-193207.17" + attribute \src "libresoc.v:196262.9-196262.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -404968,18 +409679,18 @@ module \ti sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:193221.3-193235.6" - process $proc$libresoc.v:193221$13587 + attribute \src "libresoc.v:196276.3-196290.6" + process $proc$libresoc.v:196276$13706 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:193222.5-193222.29" + attribute \src "libresoc.v:196277.5-196277.29" switch \initial - attribute \src "libresoc.v:193222.9-193222.17" + attribute \src "libresoc.v:196277.9-196277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -404995,113 +409706,113 @@ module \ti sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:193236.3-193263.6" - process $proc$libresoc.v:193236$13588 + attribute \src "libresoc.v:196291.3-196318.6" + process $proc$libresoc.v:196291$13707 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$13589 $2\fsm_state$next[1:0]$13591 - attribute \src "libresoc.v:193237.5-193237.29" + assign $0\fsm_state$next[1:0]$13708 $2\fsm_state$next[1:0]$13710 + attribute \src "libresoc.v:196292.5-196292.29" switch \initial - attribute \src "libresoc.v:193237.9-193237.17" + attribute \src "libresoc.v:196292.9-196292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13590 2'01 + assign $1\fsm_state$next[1:0]$13709 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13590 2'10 + assign $1\fsm_state$next[1:0]$13709 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13590 2'11 + assign $1\fsm_state$next[1:0]$13709 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13590 2'00 + assign $1\fsm_state$next[1:0]$13709 2'00 case - assign $1\fsm_state$next[1:0]$13590 \fsm_state + assign $1\fsm_state$next[1:0]$13709 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$13591 2'00 + assign $2\fsm_state$next[1:0]$13710 2'00 case - assign $2\fsm_state$next[1:0]$13591 $1\fsm_state$next[1:0]$13590 + assign $2\fsm_state$next[1:0]$13710 $1\fsm_state$next[1:0]$13709 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13589 + update \fsm_state$next $0\fsm_state$next[1:0]$13708 end - attribute \src "libresoc.v:193264.3-193274.6" - process $proc$libresoc.v:193264$13592 + attribute \src "libresoc.v:196319.3-196329.6" + process $proc$libresoc.v:196319$13711 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:193265.5-193265.29" + attribute \src "libresoc.v:196320.5-196320.29" switch \initial - attribute \src "libresoc.v:193265.9-193265.17" + attribute \src "libresoc.v:196320.9-196320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\new_dec[63:0] \$261 [63:0] + assign $1\new_dec[63:0] \$267 [63:0] case assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:193275.3-193289.6" - process $proc$libresoc.v:193275$13593 + attribute \src "libresoc.v:196330.3-196344.6" + process $proc$libresoc.v:196330$13712 assign { } { } assign { } { } - assign $0\core_issue__addr$13[2:0]$13594 $1\core_issue__addr$13[2:0]$13595 - attribute \src "libresoc.v:193276.5-193276.29" + assign $0\core_issue__addr$13[2:0]$13713 $1\core_issue__addr$13[2:0]$13714 + attribute \src "libresoc.v:196331.5-196331.29" switch \initial - attribute \src "libresoc.v:193276.9-193276.17" + attribute \src "libresoc.v:196331.9-196331.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$13[2:0]$13595 3'110 + assign $1\core_issue__addr$13[2:0]$13714 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$13[2:0]$13595 3'111 + assign $1\core_issue__addr$13[2:0]$13714 3'111 case - assign $1\core_issue__addr$13[2:0]$13595 3'000 + assign $1\core_issue__addr$13[2:0]$13714 3'000 end sync always - update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13594 + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13713 end - attribute \src "libresoc.v:193290.3-193304.6" - process $proc$libresoc.v:193290$13596 + attribute \src "libresoc.v:196345.3-196359.6" + process $proc$libresoc.v:196345$13715 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:193291.5-193291.29" + attribute \src "libresoc.v:196346.5-196346.29" switch \initial - attribute \src "libresoc.v:193291.9-193291.17" + attribute \src "libresoc.v:196346.9-196346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -405117,18 +409828,18 @@ module \ti sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:193305.3-193319.6" - process $proc$libresoc.v:193305$13597 + attribute \src "libresoc.v:196360.3-196374.6" + process $proc$libresoc.v:196360$13716 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:193306.5-193306.29" + attribute \src "libresoc.v:196361.5-196361.29" switch \initial - attribute \src "libresoc.v:193306.9-193306.17" + attribute \src "libresoc.v:196361.9-196361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -405144,70 +409855,70 @@ module \ti sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:193320.3-193335.6" - process $proc$libresoc.v:193320$13598 + attribute \src "libresoc.v:196375.3-196390.6" + process $proc$libresoc.v:196375$13717 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13599 $2\dec2_cur_dec$next[63:0]$13601 - attribute \src "libresoc.v:193321.5-193321.29" + assign $0\dec2_cur_dec$next[63:0]$13718 $2\dec2_cur_dec$next[63:0]$13720 + attribute \src "libresoc.v:196376.5-196376.29" switch \initial - attribute \src "libresoc.v:193321.9-193321.17" + attribute \src "libresoc.v:196376.9-196376.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13600 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13719 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$13600 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13719 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13601 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13720 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13601 $1\dec2_cur_dec$next[63:0]$13600 + assign $2\dec2_cur_dec$next[63:0]$13720 $1\dec2_cur_dec$next[63:0]$13719 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13599 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13718 end - attribute \src "libresoc.v:193336.3-193346.6" - process $proc$libresoc.v:193336$13602 + attribute \src "libresoc.v:196391.3-196401.6" + process $proc$libresoc.v:196391$13721 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:193337.5-193337.29" + attribute \src "libresoc.v:196392.5-196392.29" switch \initial - attribute \src "libresoc.v:193337.9-193337.17" + attribute \src "libresoc.v:196392.9-196392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\new_tb[63:0] \$264 [63:0] + assign $1\new_tb[63:0] \$270 [63:0] case assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:193347.3-193355.6" - process $proc$libresoc.v:193347$13603 + attribute \src "libresoc.v:196402.3-196410.6" + process $proc$libresoc.v:196402$13722 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13604 $1\dbg_dmi_we_i$next[0:0]$13605 - attribute \src "libresoc.v:193348.5-193348.29" + assign $0\dbg_dmi_we_i$next[0:0]$13723 $1\dbg_dmi_we_i$next[0:0]$13724 + attribute \src "libresoc.v:196403.5-196403.29" switch \initial - attribute \src "libresoc.v:193348.9-193348.17" + attribute \src "libresoc.v:196403.9-196403.17" case 1'1 case end @@ -405216,21 +409927,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13605 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13724 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$13605 \jtag_dmi0__we_i + assign $1\dbg_dmi_we_i$next[0:0]$13724 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13604 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13723 end - attribute \src "libresoc.v:193356.3-193364.6" - process $proc$libresoc.v:193356$13606 + attribute \src "libresoc.v:196411.3-196419.6" + process $proc$libresoc.v:196411$13725 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13607 $1\pc_ok_delay$next[0:0]$13608 - attribute \src "libresoc.v:193357.5-193357.29" + assign $0\pc_ok_delay$next[0:0]$13726 $1\pc_ok_delay$next[0:0]$13727 + attribute \src "libresoc.v:196412.5-196412.29" switch \initial - attribute \src "libresoc.v:193357.9-193357.17" + attribute \src "libresoc.v:196412.9-196412.17" case 1'1 case end @@ -405239,26 +409950,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13608 1'0 + assign $1\pc_ok_delay$next[0:0]$13727 1'0 case - assign $1\pc_ok_delay$next[0:0]$13608 \$38 + assign $1\pc_ok_delay$next[0:0]$13727 \$38 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13607 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13726 end - attribute \src "libresoc.v:193365.3-193380.6" - process $proc$libresoc.v:193365$13609 + attribute \src "libresoc.v:196420.3-196435.6" + process $proc$libresoc.v:196420$13728 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:193366.5-193366.29" + attribute \src "libresoc.v:196421.5-196421.29" switch \initial - attribute \src "libresoc.v:193366.9-193366.17" + attribute \src "libresoc.v:196421.9-196421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:538" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405267,7 +409978,7 @@ module \ti case assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:545" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405279,18 +409990,18 @@ module \ti sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:193381.3-193393.6" - process $proc$libresoc.v:193381$13610 + attribute \src "libresoc.v:196436.3-196448.6" + process $proc$libresoc.v:196436$13729 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] - attribute \src "libresoc.v:193382.5-193382.29" + attribute \src "libresoc.v:196437.5-196437.29" switch \initial - attribute \src "libresoc.v:193382.9-193382.17" + attribute \src "libresoc.v:196437.9-196437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:538" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405303,14 +410014,14 @@ module \ti sync always update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:193394.3-193402.6" - process $proc$libresoc.v:193394$13611 + attribute \src "libresoc.v:196449.3-196457.6" + process $proc$libresoc.v:196449$13730 assign { } { } assign { } { } - assign $0\svstate_ok_delay$next[0:0]$13612 $1\svstate_ok_delay$next[0:0]$13613 - attribute \src "libresoc.v:193395.5-193395.29" + assign $0\svstate_ok_delay$next[0:0]$13731 $1\svstate_ok_delay$next[0:0]$13732 + attribute \src "libresoc.v:196450.5-196450.29" switch \initial - attribute \src "libresoc.v:193395.9-193395.17" + attribute \src "libresoc.v:196450.9-196450.17" case 1'1 case end @@ -405319,26 +410030,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\svstate_ok_delay$next[0:0]$13613 1'0 + assign $1\svstate_ok_delay$next[0:0]$13732 1'0 case - assign $1\svstate_ok_delay$next[0:0]$13613 \$40 + assign $1\svstate_ok_delay$next[0:0]$13732 \$40 end sync always - update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13612 + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13731 end - attribute \src "libresoc.v:193403.3-193418.6" - process $proc$libresoc.v:193403$13614 + attribute \src "libresoc.v:196458.3-196473.6" + process $proc$libresoc.v:196458$13733 assign { } { } assign { } { } assign { } { } assign $0\svstate[63:0] $2\svstate[63:0] - attribute \src "libresoc.v:193404.5-193404.29" + attribute \src "libresoc.v:196459.5-196459.29" switch \initial - attribute \src "libresoc.v:193404.9-193404.17" + attribute \src "libresoc.v:196459.9-196459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405347,7 +410058,7 @@ module \ti case assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570" switch \svstate_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405359,18 +410070,18 @@ module \ti sync always update \svstate $0\svstate[63:0] end - attribute \src "libresoc.v:193419.3-193431.6" - process $proc$libresoc.v:193419$13615 + attribute \src "libresoc.v:196474.3-196486.6" + process $proc$libresoc.v:196474$13734 assign { } { } assign { } { } assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] - attribute \src "libresoc.v:193420.5-193420.29" + attribute \src "libresoc.v:196475.5-196475.29" switch \initial - attribute \src "libresoc.v:193420.9-193420.17" + attribute \src "libresoc.v:196475.9-196475.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:552" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405383,24 +410094,47 @@ module \ti sync always update \core_sv__ren $0\core_sv__ren[2:0] end - attribute \src "libresoc.v:193432.3-193499.6" - process $proc$libresoc.v:193432$13616 + attribute \src "libresoc.v:196487.3-196495.6" + process $proc$libresoc.v:196487$13735 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$13736 $1\dbg_dmi_din$next[63:0]$13737 + attribute \src "libresoc.v:196488.5-196488.29" + switch \initial + attribute \src "libresoc.v:196488.9-196488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$13737 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$13737 \jtag_dmi0__din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13736 + end + attribute \src "libresoc.v:196496.3-196563.6" + process $proc$libresoc.v:196496$13738 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] - attribute \src "libresoc.v:193433.5-193433.29" + attribute \src "libresoc.v:196497.5-196497.29" switch \initial - attribute \src "libresoc.v:193433.9-193433.17" + attribute \src "libresoc.v:196497.9-196497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_wen[2:0] $2\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405409,7 +410143,7 @@ module \ti case assign { } { } assign $2\core_wen[2:0] $3\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405423,14 +410157,14 @@ module \ti case 3'001 assign { } { } assign $1\core_wen[2:0] $4\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_wen[2:0] $5\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - switch \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -405445,20 +410179,20 @@ module \ti case 3'011 assign { } { } assign $1\core_wen[2:0] $6\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - switch \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_wen[2:0] $7\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_wen[2:0] $8\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - switch { \$64 \$62 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$64 \$60 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $8\core_wen[2:0] 3'000 @@ -405476,7 +410210,7 @@ module \ti case assign { } { } assign $6\core_wen[2:0] $9\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405492,24 +410226,24 @@ module \ti sync always update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:193500.3-193567.6" - process $proc$libresoc.v:193500$13617 + attribute \src "libresoc.v:196564.3-196631.6" + process $proc$libresoc.v:196564$13739 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:193501.5-193501.29" + attribute \src "libresoc.v:196565.5-196565.29" switch \initial - attribute \src "libresoc.v:193501.9-193501.17" + attribute \src "libresoc.v:196565.9-196565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405518,7 +410252,7 @@ module \ti case assign { } { } assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405532,14 +410266,14 @@ module \ti case 3'001 assign { } { } assign $1\core_data_i[63:0] $4\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_data_i[63:0] $5\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - switch \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \$74 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -405554,20 +410288,20 @@ module \ti case 3'011 assign { } { } assign $1\core_data_i[63:0] $6\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - switch \$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_data_i[63:0] $7\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_data_i[63:0] $8\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - switch { \$86 \$84 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$86 \$82 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -405585,7 +410319,7 @@ module \ti case assign { } { } assign $6\core_data_i[63:0] $9\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405601,24 +410335,24 @@ module \ti sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:193568.3-193583.6" - process $proc$libresoc.v:193568$13618 + attribute \src "libresoc.v:196632.3-196647.6" + process $proc$libresoc.v:196632$13740 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] - attribute \src "libresoc.v:193569.5-193569.29" + attribute \src "libresoc.v:196633.5-196633.29" switch \initial - attribute \src "libresoc.v:193569.9-193569.17" + attribute \src "libresoc.v:196633.9-196633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405633,14 +410367,14 @@ module \ti sync always update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:193584.3-193592.6" - process $proc$libresoc.v:193584$13619 + attribute \src "libresoc.v:196648.3-196656.6" + process $proc$libresoc.v:196648$13741 assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13620 $1\dbg_dmi_din$next[63:0]$13621 - attribute \src "libresoc.v:193585.5-193585.29" + assign $0\jtag_dmi0__ack_o$next[0:0]$13742 $1\jtag_dmi0__ack_o$next[0:0]$13743 + attribute \src "libresoc.v:196649.5-196649.29" switch \initial - attribute \src "libresoc.v:193585.9-193585.17" + attribute \src "libresoc.v:196649.9-196649.17" case 1'1 case end @@ -405649,25 +410383,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13621 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__ack_o$next[0:0]$13743 1'0 case - assign $1\dbg_dmi_din$next[63:0]$13621 \jtag_dmi0__din + assign $1\jtag_dmi0__ack_o$next[0:0]$13743 \dbg_dmi_ack_o end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13620 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13742 end - attribute \src "libresoc.v:193593.3-193603.6" - process $proc$libresoc.v:193593$13622 + attribute \src "libresoc.v:196657.3-196667.6" + process $proc$libresoc.v:196657$13744 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:193594.5-193594.29" + attribute \src "libresoc.v:196658.5-196658.29" switch \initial - attribute \src "libresoc.v:193594.9-193594.17" + attribute \src "libresoc.v:196658.9-196658.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -405679,24 +410413,24 @@ module \ti sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:193604.3-193619.6" - process $proc$libresoc.v:193604$13623 + attribute \src "libresoc.v:196668.3-196683.6" + process $proc$libresoc.v:196668$13745 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:193605.5-193605.29" + attribute \src "libresoc.v:196669.5-196669.29" switch \initial - attribute \src "libresoc.v:193605.9-193605.17" + attribute \src "libresoc.v:196669.9-196669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405711,47 +410445,24 @@ module \ti sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:193620.3-193628.6" - process $proc$libresoc.v:193620$13624 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13625 $1\jtag_dmi0__ack_o$next[0:0]$13626 - attribute \src "libresoc.v:193621.5-193621.29" - switch \initial - attribute \src "libresoc.v:193621.9-193621.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13626 1'0 - case - assign $1\jtag_dmi0__ack_o$next[0:0]$13626 \dbg_dmi_ack_o - end - sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13625 - end - attribute \src "libresoc.v:193629.3-193662.6" - process $proc$libresoc.v:193629$13627 + attribute \src "libresoc.v:196684.3-196717.6" + process $proc$libresoc.v:196684$13746 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:193630.5-193630.29" + attribute \src "libresoc.v:196685.5-196685.29" switch \initial - attribute \src "libresoc.v:193630.9-193630.17" + attribute \src "libresoc.v:196685.9-196685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405764,7 +410475,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405777,7 +410488,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405792,24 +410503,24 @@ module \ti sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:193663.3-193696.6" - process $proc$libresoc.v:193663$13628 + attribute \src "libresoc.v:196718.3-196751.6" + process $proc$libresoc.v:196718$13747 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:193664.5-193664.29" + attribute \src "libresoc.v:196719.5-196719.29" switch \initial - attribute \src "libresoc.v:193664.9-193664.17" + attribute \src "libresoc.v:196719.9-196719.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405822,7 +410533,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405835,7 +410546,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405850,50 +410561,50 @@ module \ti sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:193697.3-193717.6" - process $proc$libresoc.v:193697$13629 + attribute \src "libresoc.v:196752.3-196772.6" + process $proc$libresoc.v:196752$13748 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13630 $3\dec2_cur_pc$next[63:0]$13633 - attribute \src "libresoc.v:193698.5-193698.29" + assign $0\dec2_cur_pc$next[63:0]$13749 $3\dec2_cur_pc$next[63:0]$13752 + attribute \src "libresoc.v:196753.5-196753.29" switch \initial - attribute \src "libresoc.v:193698.9-193698.17" + attribute \src "libresoc.v:196753.9-196753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13631 $2\dec2_cur_pc$next[63:0]$13632 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + assign $1\dec2_cur_pc$next[63:0]$13750 $2\dec2_cur_pc$next[63:0]$13751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13632 \pc + assign $2\dec2_cur_pc$next[63:0]$13751 \pc case - assign $2\dec2_cur_pc$next[63:0]$13632 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13751 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$13631 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13750 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13633 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13752 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_pc$next[63:0]$13633 $1\dec2_cur_pc$next[63:0]$13631 + assign $3\dec2_cur_pc$next[63:0]$13752 $1\dec2_cur_pc$next[63:0]$13750 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13630 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13749 end - attribute \src "libresoc.v:193718.3-193756.6" - process $proc$libresoc.v:193718$13634 + attribute \src "libresoc.v:196773.3-196811.6" + process $proc$libresoc.v:196773$13753 assign { } { } assign { } { } assign { } { } @@ -405918,19 +410629,19 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\cur_cur_dststep$next[6:0]$13635 $4\cur_cur_dststep$next[6:0]$13659 - assign $0\cur_cur_maxvl$next[6:0]$13636 $4\cur_cur_maxvl$next[6:0]$13660 - assign $0\cur_cur_srcstep$next[6:0]$13637 $4\cur_cur_srcstep$next[6:0]$13661 - assign $0\cur_cur_subvl$next[1:0]$13638 $4\cur_cur_subvl$next[1:0]$13662 - assign $0\cur_cur_svstep$next[1:0]$13639 $4\cur_cur_svstep$next[1:0]$13663 - assign $0\cur_cur_vl$next[6:0]$13640 $4\cur_cur_vl$next[6:0]$13664 - attribute \src "libresoc.v:193719.5-193719.29" + assign $0\cur_cur_dststep$next[6:0]$13754 $4\cur_cur_dststep$next[6:0]$13778 + assign $0\cur_cur_maxvl$next[6:0]$13755 $4\cur_cur_maxvl$next[6:0]$13779 + assign $0\cur_cur_srcstep$next[6:0]$13756 $4\cur_cur_srcstep$next[6:0]$13780 + assign $0\cur_cur_subvl$next[1:0]$13757 $4\cur_cur_subvl$next[1:0]$13781 + assign $0\cur_cur_svstep$next[1:0]$13758 $4\cur_cur_svstep$next[1:0]$13782 + assign $0\cur_cur_vl$next[6:0]$13759 $4\cur_cur_vl$next[6:0]$13783 + attribute \src "libresoc.v:196774.5-196774.29" switch \initial - attribute \src "libresoc.v:193719.9-193719.17" + attribute \src "libresoc.v:196774.9-196774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -405940,13 +410651,13 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\cur_cur_dststep$next[6:0]$13641 $2\cur_cur_dststep$next[6:0]$13647 - assign $1\cur_cur_maxvl$next[6:0]$13642 $2\cur_cur_maxvl$next[6:0]$13648 - assign $1\cur_cur_srcstep$next[6:0]$13643 $2\cur_cur_srcstep$next[6:0]$13649 - assign $1\cur_cur_subvl$next[1:0]$13644 $2\cur_cur_subvl$next[1:0]$13650 - assign $1\cur_cur_svstep$next[1:0]$13645 $2\cur_cur_svstep$next[1:0]$13651 - assign $1\cur_cur_vl$next[6:0]$13646 $2\cur_cur_vl$next[6:0]$13652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + assign $1\cur_cur_dststep$next[6:0]$13760 $2\cur_cur_dststep$next[6:0]$13766 + assign $1\cur_cur_maxvl$next[6:0]$13761 $2\cur_cur_maxvl$next[6:0]$13767 + assign $1\cur_cur_srcstep$next[6:0]$13762 $2\cur_cur_srcstep$next[6:0]$13768 + assign $1\cur_cur_subvl$next[1:0]$13763 $2\cur_cur_subvl$next[1:0]$13769 + assign $1\cur_cur_svstep$next[1:0]$13764 $2\cur_cur_svstep$next[1:0]$13770 + assign $1\cur_cur_vl$next[6:0]$13765 $2\cur_cur_vl$next[6:0]$13771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405956,24 +410667,24 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\cur_cur_maxvl$next[6:0]$13648 $2\cur_cur_vl$next[6:0]$13652 $2\cur_cur_srcstep$next[6:0]$13649 $2\cur_cur_dststep$next[6:0]$13647 $2\cur_cur_subvl$next[1:0]$13650 $2\cur_cur_svstep$next[1:0]$13651 } \svstate [31:0] + assign { $2\cur_cur_maxvl$next[6:0]$13767 $2\cur_cur_vl$next[6:0]$13771 $2\cur_cur_srcstep$next[6:0]$13768 $2\cur_cur_dststep$next[6:0]$13766 $2\cur_cur_subvl$next[1:0]$13769 $2\cur_cur_svstep$next[1:0]$13770 } \svstate [31:0] case - assign $2\cur_cur_dststep$next[6:0]$13647 \cur_cur_dststep - assign $2\cur_cur_maxvl$next[6:0]$13648 \cur_cur_maxvl - assign $2\cur_cur_srcstep$next[6:0]$13649 \cur_cur_srcstep - assign $2\cur_cur_subvl$next[1:0]$13650 \cur_cur_subvl - assign $2\cur_cur_svstep$next[1:0]$13651 \cur_cur_svstep - assign $2\cur_cur_vl$next[6:0]$13652 \cur_cur_vl + assign $2\cur_cur_dststep$next[6:0]$13766 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13767 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13768 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13769 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13770 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13771 \cur_cur_vl end case - assign $1\cur_cur_dststep$next[6:0]$13641 \cur_cur_dststep - assign $1\cur_cur_maxvl$next[6:0]$13642 \cur_cur_maxvl - assign $1\cur_cur_srcstep$next[6:0]$13643 \cur_cur_srcstep - assign $1\cur_cur_subvl$next[1:0]$13644 \cur_cur_subvl - assign $1\cur_cur_svstep$next[1:0]$13645 \cur_cur_svstep - assign $1\cur_cur_vl$next[6:0]$13646 \cur_cur_vl + assign $1\cur_cur_dststep$next[6:0]$13760 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13761 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13762 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13763 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13764 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13765 \cur_cur_vl end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:401" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -405983,14 +410694,14 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $3\cur_cur_maxvl$next[6:0]$13654 $3\cur_cur_vl$next[6:0]$13658 $3\cur_cur_srcstep$next[6:0]$13655 $3\cur_cur_dststep$next[6:0]$13653 $3\cur_cur_subvl$next[1:0]$13656 $3\cur_cur_svstep$next[1:0]$13657 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + assign { $3\cur_cur_maxvl$next[6:0]$13773 $3\cur_cur_vl$next[6:0]$13777 $3\cur_cur_srcstep$next[6:0]$13774 $3\cur_cur_dststep$next[6:0]$13772 $3\cur_cur_subvl$next[1:0]$13775 $3\cur_cur_svstep$next[1:0]$13776 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $3\cur_cur_dststep$next[6:0]$13653 $1\cur_cur_dststep$next[6:0]$13641 - assign $3\cur_cur_maxvl$next[6:0]$13654 $1\cur_cur_maxvl$next[6:0]$13642 - assign $3\cur_cur_srcstep$next[6:0]$13655 $1\cur_cur_srcstep$next[6:0]$13643 - assign $3\cur_cur_subvl$next[1:0]$13656 $1\cur_cur_subvl$next[1:0]$13644 - assign $3\cur_cur_svstep$next[1:0]$13657 $1\cur_cur_svstep$next[1:0]$13645 - assign $3\cur_cur_vl$next[6:0]$13658 $1\cur_cur_vl$next[6:0]$13646 + assign $3\cur_cur_dststep$next[6:0]$13772 $1\cur_cur_dststep$next[6:0]$13760 + assign $3\cur_cur_maxvl$next[6:0]$13773 $1\cur_cur_maxvl$next[6:0]$13761 + assign $3\cur_cur_srcstep$next[6:0]$13774 $1\cur_cur_srcstep$next[6:0]$13762 + assign $3\cur_cur_subvl$next[1:0]$13775 $1\cur_cur_subvl$next[1:0]$13763 + assign $3\cur_cur_svstep$next[1:0]$13776 $1\cur_cur_svstep$next[1:0]$13764 + assign $3\cur_cur_vl$next[6:0]$13777 $1\cur_cur_vl$next[6:0]$13765 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -406002,323 +410713,323 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\cur_cur_svstep$next[1:0]$13663 2'00 - assign $4\cur_cur_subvl$next[1:0]$13662 2'00 - assign $4\cur_cur_dststep$next[6:0]$13659 7'0000000 - assign $4\cur_cur_srcstep$next[6:0]$13661 7'0000000 - assign $4\cur_cur_vl$next[6:0]$13664 7'0000000 - assign $4\cur_cur_maxvl$next[6:0]$13660 7'0000000 + assign $4\cur_cur_svstep$next[1:0]$13782 2'00 + assign $4\cur_cur_subvl$next[1:0]$13781 2'00 + assign $4\cur_cur_dststep$next[6:0]$13778 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13780 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13783 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13779 7'0000000 case - assign $4\cur_cur_dststep$next[6:0]$13659 $3\cur_cur_dststep$next[6:0]$13653 - assign $4\cur_cur_maxvl$next[6:0]$13660 $3\cur_cur_maxvl$next[6:0]$13654 - assign $4\cur_cur_srcstep$next[6:0]$13661 $3\cur_cur_srcstep$next[6:0]$13655 - assign $4\cur_cur_subvl$next[1:0]$13662 $3\cur_cur_subvl$next[1:0]$13656 - assign $4\cur_cur_svstep$next[1:0]$13663 $3\cur_cur_svstep$next[1:0]$13657 - assign $4\cur_cur_vl$next[6:0]$13664 $3\cur_cur_vl$next[6:0]$13658 + assign $4\cur_cur_dststep$next[6:0]$13778 $3\cur_cur_dststep$next[6:0]$13772 + assign $4\cur_cur_maxvl$next[6:0]$13779 $3\cur_cur_maxvl$next[6:0]$13773 + assign $4\cur_cur_srcstep$next[6:0]$13780 $3\cur_cur_srcstep$next[6:0]$13774 + assign $4\cur_cur_subvl$next[1:0]$13781 $3\cur_cur_subvl$next[1:0]$13775 + assign $4\cur_cur_svstep$next[1:0]$13782 $3\cur_cur_svstep$next[1:0]$13776 + assign $4\cur_cur_vl$next[6:0]$13783 $3\cur_cur_vl$next[6:0]$13777 end sync always - update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13635 - update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13636 - update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13637 - update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13638 - update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13639 - update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13640 + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13754 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13755 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13756 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13757 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13758 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13759 end - attribute \src "libresoc.v:193757.3-193786.6" - process $proc$libresoc.v:193757$13665 + attribute \src "libresoc.v:196812.3-196820.6" + process $proc$libresoc.v:196812$13784 assign { } { } + assign { } { } + assign $0\jtag_dmi0__dout$next[63:0]$13785 $1\jtag_dmi0__dout$next[63:0]$13786 + attribute \src "libresoc.v:196813.5-196813.29" + switch \initial + attribute \src "libresoc.v:196813.9-196813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__dout$next[63:0]$13786 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0__dout$next[63:0]$13786 \dbg_dmi_dout + end + sync always + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13785 + end + attribute \src "libresoc.v:196821.3-196850.6" + process $proc$libresoc.v:196821$13787 assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$13666 $4\msr_read$next[0:0]$13670 - attribute \src "libresoc.v:193758.5-193758.29" + assign { } { } + assign $0\msr_read$next[0:0]$13788 $4\msr_read$next[0:0]$13792 + attribute \src "libresoc.v:196822.5-196822.29" switch \initial - attribute \src "libresoc.v:193758.9-193758.17" + attribute \src "libresoc.v:196822.9-196822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13667 $2\msr_read$next[0:0]$13668 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + assign $1\msr_read$next[0:0]$13789 $2\msr_read$next[0:0]$13790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_read$next[0:0]$13668 1'0 + assign $2\msr_read$next[0:0]$13790 1'0 case - assign $2\msr_read$next[0:0]$13668 \msr_read + assign $2\msr_read$next[0:0]$13790 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13667 $3\msr_read$next[0:0]$13669 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + assign $1\msr_read$next[0:0]$13789 $3\msr_read$next[0:0]$13791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" switch \$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr_read$next[0:0]$13669 1'1 + assign $3\msr_read$next[0:0]$13791 1'1 case - assign $3\msr_read$next[0:0]$13669 \msr_read + assign $3\msr_read$next[0:0]$13791 \msr_read end case - assign $1\msr_read$next[0:0]$13667 \msr_read + assign $1\msr_read$next[0:0]$13789 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13670 1'1 + assign $4\msr_read$next[0:0]$13792 1'1 case - assign $4\msr_read$next[0:0]$13670 $1\msr_read$next[0:0]$13667 + assign $4\msr_read$next[0:0]$13792 $1\msr_read$next[0:0]$13789 end sync always - update \msr_read$next $0\msr_read$next[0:0]$13666 + update \msr_read$next $0\msr_read$next[0:0]$13788 end - attribute \src "libresoc.v:193787.3-193795.6" - process $proc$libresoc.v:193787$13671 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13672 $1\jtag_dmi0__dout$next[63:0]$13673 - attribute \src "libresoc.v:193788.5-193788.29" - switch \initial - attribute \src "libresoc.v:193788.9-193788.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13673 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\jtag_dmi0__dout$next[63:0]$13673 \dbg_dmi_dout - end - sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13672 - end - attribute \src "libresoc.v:193796.3-193849.6" - process $proc$libresoc.v:193796$13674 + attribute \src "libresoc.v:196851.3-196904.6" + process $proc$libresoc.v:196851$13793 assign { } { } assign { } { } assign { } { } - assign $0\fetch_fsm_state$next[1:0]$13675 $6\fetch_fsm_state$next[1:0]$13681 - attribute \src "libresoc.v:193797.5-193797.29" + assign $0\fetch_fsm_state$next[1:0]$13794 $6\fetch_fsm_state$next[1:0]$13800 + attribute \src "libresoc.v:196852.5-196852.29" switch \initial - attribute \src "libresoc.v:193797.9-193797.17" + attribute \src "libresoc.v:196852.9-196852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13676 $2\fetch_fsm_state$next[1:0]$13677 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + assign $1\fetch_fsm_state$next[1:0]$13795 $2\fetch_fsm_state$next[1:0]$13796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fetch_fsm_state$next[1:0]$13677 2'01 + assign $2\fetch_fsm_state$next[1:0]$13796 2'01 case - assign $2\fetch_fsm_state$next[1:0]$13677 \fetch_fsm_state + assign $2\fetch_fsm_state$next[1:0]$13796 \fetch_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13676 $3\fetch_fsm_state$next[1:0]$13678 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + assign $1\fetch_fsm_state$next[1:0]$13795 $3\fetch_fsm_state$next[1:0]$13797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\fetch_fsm_state$next[1:0]$13678 \fetch_fsm_state + assign $3\fetch_fsm_state$next[1:0]$13797 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\fetch_fsm_state$next[1:0]$13678 2'10 + assign $3\fetch_fsm_state$next[1:0]$13797 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13676 $4\fetch_fsm_state$next[1:0]$13679 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + assign $1\fetch_fsm_state$next[1:0]$13795 $4\fetch_fsm_state$next[1:0]$13798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\fetch_fsm_state$next[1:0]$13679 \fetch_fsm_state + assign $4\fetch_fsm_state$next[1:0]$13798 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fetch_fsm_state$next[1:0]$13679 2'10 + assign $4\fetch_fsm_state$next[1:0]$13798 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13676 $5\fetch_fsm_state$next[1:0]$13680 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:248" + assign $1\fetch_fsm_state$next[1:0]$13795 $5\fetch_fsm_state$next[1:0]$13799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:254" switch \fetch_insn_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fetch_fsm_state$next[1:0]$13680 2'00 + assign $5\fetch_fsm_state$next[1:0]$13799 2'00 case - assign $5\fetch_fsm_state$next[1:0]$13680 \fetch_fsm_state + assign $5\fetch_fsm_state$next[1:0]$13799 \fetch_fsm_state end case - assign $1\fetch_fsm_state$next[1:0]$13676 \fetch_fsm_state + assign $1\fetch_fsm_state$next[1:0]$13795 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fetch_fsm_state$next[1:0]$13681 2'00 + assign $6\fetch_fsm_state$next[1:0]$13800 2'00 case - assign $6\fetch_fsm_state$next[1:0]$13681 $1\fetch_fsm_state$next[1:0]$13676 + assign $6\fetch_fsm_state$next[1:0]$13800 $1\fetch_fsm_state$next[1:0]$13795 end sync always - update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13675 + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13794 end - attribute \src "libresoc.v:193850.3-193870.6" - process $proc$libresoc.v:193850$13682 + attribute \src "libresoc.v:196905.3-196925.6" + process $proc$libresoc.v:196905$13801 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13683 $3\dec2_cur_msr$next[63:0]$13686 - attribute \src "libresoc.v:193851.5-193851.29" + assign $0\dec2_cur_msr$next[63:0]$13802 $3\dec2_cur_msr$next[63:0]$13805 + attribute \src "libresoc.v:196906.5-196906.29" switch \initial - attribute \src "libresoc.v:193851.9-193851.17" + attribute \src "libresoc.v:196906.9-196906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13684 $2\dec2_cur_msr$next[63:0]$13685 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + assign $1\dec2_cur_msr$next[63:0]$13803 $2\dec2_cur_msr$next[63:0]$13804 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13685 \core_msr__data_o + assign $2\dec2_cur_msr$next[63:0]$13804 \core_msr__data_o case - assign $2\dec2_cur_msr$next[63:0]$13685 \dec2_cur_msr + assign $2\dec2_cur_msr$next[63:0]$13804 \dec2_cur_msr end case - assign $1\dec2_cur_msr$next[63:0]$13684 \dec2_cur_msr + assign $1\dec2_cur_msr$next[63:0]$13803 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13686 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_msr$next[63:0]$13805 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_msr$next[63:0]$13686 $1\dec2_cur_msr$next[63:0]$13684 + assign $3\dec2_cur_msr$next[63:0]$13805 $1\dec2_cur_msr$next[63:0]$13803 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13683 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13802 end - attribute \src "libresoc.v:193871.3-193889.6" - process $proc$libresoc.v:193871$13687 + attribute \src "libresoc.v:196926.3-196944.6" + process $proc$libresoc.v:196926$13806 assign { } { } assign { } { } - assign $0\nia$next[63:0]$13688 $1\nia$next[63:0]$13689 - attribute \src "libresoc.v:193872.5-193872.29" + assign $0\nia$next[63:0]$13807 $1\nia$next[63:0]$13808 + attribute \src "libresoc.v:196927.5-196927.29" switch \initial - attribute \src "libresoc.v:193872.9-193872.17" + attribute \src "libresoc.v:196927.9-196927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\nia$next[63:0]$13689 $2\nia$next[63:0]$13690 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + assign $1\nia$next[63:0]$13808 $2\nia$next[63:0]$13809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\nia$next[63:0]$13690 \nia + assign $2\nia$next[63:0]$13809 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\nia$next[63:0]$13690 \$92 [63:0] + assign $2\nia$next[63:0]$13809 \$92 [63:0] end case - assign $1\nia$next[63:0]$13689 \nia + assign $1\nia$next[63:0]$13808 \nia end sync always - update \nia$next $0\nia$next[63:0]$13688 + update \nia$next $0\nia$next[63:0]$13807 end - attribute \src "libresoc.v:193890.3-193920.6" - process $proc$libresoc.v:193890$13691 + attribute \src "libresoc.v:196945.3-196975.6" + process $proc$libresoc.v:196945$13810 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in$next[31:0]$13692 $1\dec2_raw_opcode_in$next[31:0]$13693 - attribute \src "libresoc.v:193891.5-193891.29" + assign $0\dec2_raw_opcode_in$next[31:0]$13811 $1\dec2_raw_opcode_in$next[31:0]$13812 + attribute \src "libresoc.v:196946.5-196946.29" switch \initial - attribute \src "libresoc.v:193891.9-193891.17" + attribute \src "libresoc.v:196946.9-196946.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13693 $2\dec2_raw_opcode_in$next[31:0]$13694 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + assign $1\dec2_raw_opcode_in$next[31:0]$13812 $2\dec2_raw_opcode_in$next[31:0]$13813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_raw_opcode_in$next[31:0]$13694 \dec2_raw_opcode_in + assign $2\dec2_raw_opcode_in$next[31:0]$13813 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dec2_raw_opcode_in$next[31:0]$13694 \$95 + assign $2\dec2_raw_opcode_in$next[31:0]$13813 \$95 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13693 $3\dec2_raw_opcode_in$next[31:0]$13695 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + assign $1\dec2_raw_opcode_in$next[31:0]$13812 $3\dec2_raw_opcode_in$next[31:0]$13814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\dec2_raw_opcode_in$next[31:0]$13695 \dec2_raw_opcode_in + assign $3\dec2_raw_opcode_in$next[31:0]$13814 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\dec2_raw_opcode_in$next[31:0]$13695 \$99 + assign $3\dec2_raw_opcode_in$next[31:0]$13814 \$99 end case - assign $1\dec2_raw_opcode_in$next[31:0]$13693 \dec2_raw_opcode_in + assign $1\dec2_raw_opcode_in$next[31:0]$13812 \dec2_raw_opcode_in end sync always - update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13692 + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13811 end - attribute \src "libresoc.v:193921.3-193931.6" - process $proc$libresoc.v:193921$13696 + attribute \src "libresoc.v:196976.3-196986.6" + process $proc$libresoc.v:196976$13815 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:193922.5-193922.29" + attribute \src "libresoc.v:196977.5-196977.29" switch \initial - attribute \src "libresoc.v:193922.9-193922.17" + attribute \src "libresoc.v:196977.9-196977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -406330,8 +411041,8 @@ module \ti sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:193932.3-193993.6" - process $proc$libresoc.v:193932$13697 + attribute \src "libresoc.v:196987.3-197043.6" + process $proc$libresoc.v:196987$13816 assign { } { } assign { } { } assign { } { } @@ -406345,13 +411056,13 @@ module \ti assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:193933.5-193933.29" + attribute \src "libresoc.v:196988.5-196988.29" switch \initial - attribute \src "libresoc.v:193933.9-193933.17" + attribute \src "libresoc.v:196988.9-196988.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -406367,7 +411078,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406391,7 +411102,7 @@ module \ti assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0] assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0] assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406425,7 +411136,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406436,30 +411147,20 @@ module \ti assign $4\new_svstate_svstep[1:0] \cur_cur_svstep assign $4\new_svstate_vl[6:0] \cur_cur_vl assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - switch { \$120 \$118 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$122 \$118 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign { } { } - assign $6\new_svstate_srcstep[6:0] $7\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - switch \$122 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\new_svstate_srcstep[6:0] 7'0000000 - case - assign $7\new_svstate_srcstep[6:0] \cur_cur_srcstep - end + assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -406478,11 +411179,11 @@ module \ti assign { } { } assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] assign $4\new_svstate_maxvl[6:0] $5\new_svstate_maxvl[6:0] - assign $4\new_svstate_srcstep[6:0] $8\new_svstate_srcstep[6:0] + assign $4\new_svstate_srcstep[6:0] $7\new_svstate_srcstep[6:0] assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406492,11 +411193,11 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $8\new_svstate_srcstep[6:0] $5\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i + assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $7\new_svstate_srcstep[6:0] $5\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i case assign $5\new_svstate_dststep[6:0] \cur_cur_dststep assign $5\new_svstate_maxvl[6:0] \cur_cur_maxvl - assign $8\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $7\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $5\new_svstate_subvl[1:0] \cur_cur_subvl assign $5\new_svstate_svstep[1:0] \cur_cur_svstep assign $5\new_svstate_vl[6:0] \cur_cur_vl @@ -406518,24 +411219,24 @@ module \ti update \new_svstate_svstep $0\new_svstate_svstep[1:0] update \new_svstate_vl $0\new_svstate_vl[6:0] end - attribute \src "libresoc.v:193994.3-194009.6" - process $proc$libresoc.v:193994$13698 + attribute \src "libresoc.v:197044.3-197059.6" + process $proc$libresoc.v:197044$13817 assign { } { } assign { } { } assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:193995.5-193995.29" + attribute \src "libresoc.v:197045.5-197045.29" switch \initial - attribute \src "libresoc.v:193995.9-193995.17" + attribute \src "libresoc.v:197045.9-197045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$128 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406550,153 +411251,153 @@ module \ti sync always update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end - attribute \src "libresoc.v:194010.3-194090.6" - process $proc$libresoc.v:194010$13699 + attribute \src "libresoc.v:197060.3-197140.6" + process $proc$libresoc.v:197060$13818 assign { } { } assign { } { } assign { } { } - assign $0\issue_fsm_state$next[2:0]$13700 $10\issue_fsm_state$next[2:0]$13710 - attribute \src "libresoc.v:194011.5-194011.29" + assign $0\issue_fsm_state$next[2:0]$13819 $10\issue_fsm_state$next[2:0]$13829 + attribute \src "libresoc.v:197061.5-197061.29" switch \initial - attribute \src "libresoc.v:194011.9-194011.17" + attribute \src "libresoc.v:197061.9-197061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13701 $2\issue_fsm_state$next[2:0]$13702 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + assign $1\issue_fsm_state$next[2:0]$13820 $2\issue_fsm_state$next[2:0]$13821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\issue_fsm_state$next[2:0]$13702 $3\issue_fsm_state$next[2:0]$13703 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + assign $2\issue_fsm_state$next[2:0]$13821 $3\issue_fsm_state$next[2:0]$13822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\issue_fsm_state$next[2:0]$13703 3'001 + assign $3\issue_fsm_state$next[2:0]$13822 3'001 case - assign $3\issue_fsm_state$next[2:0]$13703 \issue_fsm_state + assign $3\issue_fsm_state$next[2:0]$13822 \issue_fsm_state end case - assign $2\issue_fsm_state$next[2:0]$13702 \issue_fsm_state + assign $2\issue_fsm_state$next[2:0]$13821 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13701 $4\issue_fsm_state$next[2:0]$13704 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + assign $1\issue_fsm_state$next[2:0]$13820 $4\issue_fsm_state$next[2:0]$13823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\issue_fsm_state$next[2:0]$13704 $5\issue_fsm_state$next[2:0]$13705 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" - switch \$140 + assign $4\issue_fsm_state$next[2:0]$13823 $5\issue_fsm_state$next[2:0]$13824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \$138 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\issue_fsm_state$next[2:0]$13705 3'000 + assign $5\issue_fsm_state$next[2:0]$13824 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\issue_fsm_state$next[2:0]$13705 3'010 + assign $5\issue_fsm_state$next[2:0]$13824 3'010 end case - assign $4\issue_fsm_state$next[2:0]$13704 \issue_fsm_state + assign $4\issue_fsm_state$next[2:0]$13823 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13701 $6\issue_fsm_state$next[2:0]$13706 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:331" + assign $1\issue_fsm_state$next[2:0]$13820 $6\issue_fsm_state$next[2:0]$13825 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" switch \exec_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\issue_fsm_state$next[2:0]$13706 3'011 + assign $6\issue_fsm_state$next[2:0]$13825 3'011 case - assign $6\issue_fsm_state$next[2:0]$13706 \issue_fsm_state + assign $6\issue_fsm_state$next[2:0]$13825 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13701 $7\issue_fsm_state$next[2:0]$13707 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - switch \$146 + assign $1\issue_fsm_state$next[2:0]$13820 $7\issue_fsm_state$next[2:0]$13826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\issue_fsm_state$next[2:0]$13707 $8\issue_fsm_state$next[2:0]$13708 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" + assign $7\issue_fsm_state$next[2:0]$13826 $8\issue_fsm_state$next[2:0]$13827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\issue_fsm_state$next[2:0]$13708 $9\issue_fsm_state$next[2:0]$13709 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - switch { \$150 \$148 } + assign $8\issue_fsm_state$next[2:0]$13827 $9\issue_fsm_state$next[2:0]$13828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$150 \$146 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $9\issue_fsm_state$next[2:0]$13709 3'000 + assign $9\issue_fsm_state$next[2:0]$13828 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $9\issue_fsm_state$next[2:0]$13709 3'000 + assign $9\issue_fsm_state$next[2:0]$13828 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $9\issue_fsm_state$next[2:0]$13709 3'100 + assign $9\issue_fsm_state$next[2:0]$13828 3'100 end case - assign $8\issue_fsm_state$next[2:0]$13708 \issue_fsm_state + assign $8\issue_fsm_state$next[2:0]$13827 \issue_fsm_state end case - assign $7\issue_fsm_state$next[2:0]$13707 \issue_fsm_state + assign $7\issue_fsm_state$next[2:0]$13826 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13701 3'010 + assign $1\issue_fsm_state$next[2:0]$13820 3'010 case - assign $1\issue_fsm_state$next[2:0]$13701 \issue_fsm_state + assign $1\issue_fsm_state$next[2:0]$13820 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\issue_fsm_state$next[2:0]$13710 3'000 + assign $10\issue_fsm_state$next[2:0]$13829 3'000 case - assign $10\issue_fsm_state$next[2:0]$13710 $1\issue_fsm_state$next[2:0]$13701 + assign $10\issue_fsm_state$next[2:0]$13829 $1\issue_fsm_state$next[2:0]$13820 end sync always - update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13700 + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13819 end - attribute \src "libresoc.v:194091.3-194121.6" - process $proc$libresoc.v:194091$13711 + attribute \src "libresoc.v:197141.3-197171.6" + process $proc$libresoc.v:197141$13830 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:194092.5-194092.29" + attribute \src "libresoc.v:197142.5-197142.29" switch \initial - attribute \src "libresoc.v:194092.9-194092.17" + attribute \src "libresoc.v:197142.9-197142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$156 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406710,7 +411411,7 @@ module \ti case 3'011 assign { } { } assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" switch \$162 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406726,24 +411427,24 @@ module \ti sync always update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:194122.3-194152.6" - process $proc$libresoc.v:194122$13712 + attribute \src "libresoc.v:197172.3-197202.6" + process $proc$libresoc.v:197172$13831 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:194123.5-194123.29" + attribute \src "libresoc.v:197173.5-197173.29" switch \initial - attribute \src "libresoc.v:194123.9-194123.17" + attribute \src "libresoc.v:197173.9-197173.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$168 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406757,7 +411458,7 @@ module \ti case 3'011 assign { } { } assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" switch \$174 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406773,131 +411474,131 @@ module \ti sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:194153.3-194219.6" - process $proc$libresoc.v:194153$13713 + attribute \src "libresoc.v:197203.3-197269.6" + process $proc$libresoc.v:197203$13832 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$13714 $9\pc_changed$next[0:0]$13723 - attribute \src "libresoc.v:194154.5-194154.29" + assign $0\pc_changed$next[0:0]$13833 $9\pc_changed$next[0:0]$13842 + attribute \src "libresoc.v:197204.5-197204.29" switch \initial - attribute \src "libresoc.v:194154.9-194154.17" + attribute \src "libresoc.v:197204.9-197204.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\pc_changed$next[0:0]$13715 $2\pc_changed$next[0:0]$13716 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + assign $1\pc_changed$next[0:0]$13834 $2\pc_changed$next[0:0]$13835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$180 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\pc_changed$next[0:0]$13716 \pc_changed + assign $2\pc_changed$next[0:0]$13835 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\pc_changed$next[0:0]$13716 $3\pc_changed$next[0:0]$13717 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + assign $2\pc_changed$next[0:0]$13835 $3\pc_changed$next[0:0]$13836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$13717 1'1 + assign $3\pc_changed$next[0:0]$13836 1'1 case - assign $3\pc_changed$next[0:0]$13717 \pc_changed + assign $3\pc_changed$next[0:0]$13836 \pc_changed end end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\pc_changed$next[0:0]$13715 $4\pc_changed$next[0:0]$13718 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + assign $1\pc_changed$next[0:0]$13834 $4\pc_changed$next[0:0]$13837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" switch \$186 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\pc_changed$next[0:0]$13718 \pc_changed + assign $4\pc_changed$next[0:0]$13837 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\pc_changed$next[0:0]$13718 $5\pc_changed$next[0:0]$13719 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + assign $4\pc_changed$next[0:0]$13837 $5\pc_changed$next[0:0]$13838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\pc_changed$next[0:0]$13719 1'1 + assign $5\pc_changed$next[0:0]$13838 1'1 case - assign $5\pc_changed$next[0:0]$13719 \pc_changed + assign $5\pc_changed$next[0:0]$13838 \pc_changed end end case - assign $1\pc_changed$next[0:0]$13715 \pc_changed + assign $1\pc_changed$next[0:0]$13834 \pc_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\pc_changed$next[0:0]$13720 $7\pc_changed$next[0:0]$13721 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432" + assign $6\pc_changed$next[0:0]$13839 $7\pc_changed$next[0:0]$13840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\pc_changed$next[0:0]$13721 1'0 + assign $7\pc_changed$next[0:0]$13840 1'0 case - assign $7\pc_changed$next[0:0]$13721 $1\pc_changed$next[0:0]$13715 + assign $7\pc_changed$next[0:0]$13840 $1\pc_changed$next[0:0]$13834 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\pc_changed$next[0:0]$13720 $8\pc_changed$next[0:0]$13722 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + assign $6\pc_changed$next[0:0]$13839 $8\pc_changed$next[0:0]$13841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" switch \$188 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\pc_changed$next[0:0]$13722 1'1 + assign $8\pc_changed$next[0:0]$13841 1'1 case - assign $8\pc_changed$next[0:0]$13722 $1\pc_changed$next[0:0]$13715 + assign $8\pc_changed$next[0:0]$13841 $1\pc_changed$next[0:0]$13834 end case - assign $6\pc_changed$next[0:0]$13720 $1\pc_changed$next[0:0]$13715 + assign $6\pc_changed$next[0:0]$13839 $1\pc_changed$next[0:0]$13834 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\pc_changed$next[0:0]$13723 1'0 + assign $9\pc_changed$next[0:0]$13842 1'0 case - assign $9\pc_changed$next[0:0]$13723 $6\pc_changed$next[0:0]$13720 + assign $9\pc_changed$next[0:0]$13842 $6\pc_changed$next[0:0]$13839 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13714 + update \pc_changed$next $0\pc_changed$next[0:0]$13833 end - attribute \src "libresoc.v:194220.3-194281.6" - process $proc$libresoc.v:194220$13724 + attribute \src "libresoc.v:197270.3-197326.6" + process $proc$libresoc.v:197270$13843 assign { } { } assign { } { } assign $0\update_svstate[0:0] $1\update_svstate[0:0] - attribute \src "libresoc.v:194221.5-194221.29" + attribute \src "libresoc.v:197271.5-197271.29" switch \initial - attribute \src "libresoc.v:194221.9-194221.17" + attribute \src "libresoc.v:197271.9-197271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\update_svstate[0:0] $2\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$196 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406906,7 +411607,7 @@ module \ti case assign { } { } assign $2\update_svstate[0:0] $3\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -406920,36 +411621,26 @@ module \ti case 3'011 assign { } { } assign $1\update_svstate[0:0] $4\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" switch \$202 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\update_svstate[0:0] $5\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\update_svstate[0:0] $6\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - switch { \$206 \$204 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + switch { \$208 \$204 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $6\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign { } { } - assign $6\update_svstate[0:0] $7\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - switch \$208 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\update_svstate[0:0] 1'1 - case - assign $7\update_svstate[0:0] 1'0 - end + assign $6\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -406961,15 +411652,15 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\update_svstate[0:0] $8\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" + assign $4\update_svstate[0:0] $7\update_svstate[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\update_svstate[0:0] 1'1 + assign $7\update_svstate[0:0] 1'1 case - assign $8\update_svstate[0:0] 1'0 + assign $7\update_svstate[0:0] 1'0 end end case @@ -406978,125 +411669,125 @@ module \ti sync always update \update_svstate $0\update_svstate[0:0] end - attribute \src "libresoc.v:194282.3-194348.6" - process $proc$libresoc.v:194282$13725 + attribute \src "libresoc.v:197327.3-197393.6" + process $proc$libresoc.v:197327$13844 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sv_changed$next[0:0]$13726 $9\sv_changed$next[0:0]$13735 - attribute \src "libresoc.v:194283.5-194283.29" + assign $0\sv_changed$next[0:0]$13845 $9\sv_changed$next[0:0]$13854 + attribute \src "libresoc.v:197328.5-197328.29" switch \initial - attribute \src "libresoc.v:194283.9-194283.17" + attribute \src "libresoc.v:197328.9-197328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\sv_changed$next[0:0]$13727 $2\sv_changed$next[0:0]$13728 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + assign $1\sv_changed$next[0:0]$13846 $2\sv_changed$next[0:0]$13847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \$214 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\sv_changed$next[0:0]$13728 \sv_changed + assign $2\sv_changed$next[0:0]$13847 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\sv_changed$next[0:0]$13728 $3\sv_changed$next[0:0]$13729 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" + assign $2\sv_changed$next[0:0]$13847 $3\sv_changed$next[0:0]$13848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv_changed$next[0:0]$13729 1'1 + assign $3\sv_changed$next[0:0]$13848 1'1 case - assign $3\sv_changed$next[0:0]$13729 \sv_changed + assign $3\sv_changed$next[0:0]$13848 \sv_changed end end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\sv_changed$next[0:0]$13727 $4\sv_changed$next[0:0]$13730 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + assign $1\sv_changed$next[0:0]$13846 $4\sv_changed$next[0:0]$13849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" switch \$220 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\sv_changed$next[0:0]$13730 \sv_changed + assign $4\sv_changed$next[0:0]$13849 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\sv_changed$next[0:0]$13730 $5\sv_changed$next[0:0]$13731 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" + assign $4\sv_changed$next[0:0]$13849 $5\sv_changed$next[0:0]$13850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv_changed$next[0:0]$13731 1'1 + assign $5\sv_changed$next[0:0]$13850 1'1 case - assign $5\sv_changed$next[0:0]$13731 \sv_changed + assign $5\sv_changed$next[0:0]$13850 \sv_changed end end case - assign $1\sv_changed$next[0:0]$13727 \sv_changed + assign $1\sv_changed$next[0:0]$13846 \sv_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:427" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\sv_changed$next[0:0]$13732 $7\sv_changed$next[0:0]$13733 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:432" + assign $6\sv_changed$next[0:0]$13851 $7\sv_changed$next[0:0]$13852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv_changed$next[0:0]$13733 1'0 + assign $7\sv_changed$next[0:0]$13852 1'0 case - assign $7\sv_changed$next[0:0]$13733 $1\sv_changed$next[0:0]$13727 + assign $7\sv_changed$next[0:0]$13852 $1\sv_changed$next[0:0]$13846 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv_changed$next[0:0]$13732 $8\sv_changed$next[0:0]$13734 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:444" + assign $6\sv_changed$next[0:0]$13851 $8\sv_changed$next[0:0]$13853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" switch \$222 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\sv_changed$next[0:0]$13734 1'1 + assign $8\sv_changed$next[0:0]$13853 1'1 case - assign $8\sv_changed$next[0:0]$13734 $1\sv_changed$next[0:0]$13727 + assign $8\sv_changed$next[0:0]$13853 $1\sv_changed$next[0:0]$13846 end case - assign $6\sv_changed$next[0:0]$13732 $1\sv_changed$next[0:0]$13727 + assign $6\sv_changed$next[0:0]$13851 $1\sv_changed$next[0:0]$13846 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\sv_changed$next[0:0]$13735 1'0 + assign $9\sv_changed$next[0:0]$13854 1'0 case - assign $9\sv_changed$next[0:0]$13735 $6\sv_changed$next[0:0]$13732 + assign $9\sv_changed$next[0:0]$13854 $6\sv_changed$next[0:0]$13851 end sync always - update \sv_changed$next $0\sv_changed$next[0:0]$13726 + update \sv_changed$next $0\sv_changed$next[0:0]$13845 end - attribute \src "libresoc.v:194349.3-194359.6" - process $proc$libresoc.v:194349$13736 + attribute \src "libresoc.v:197394.3-197404.6" + process $proc$libresoc.v:197394$13855 assign { } { } assign { } { } assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:194350.5-194350.29" + attribute \src "libresoc.v:197395.5-197395.29" switch \initial - attribute \src "libresoc.v:194350.9-194350.17" + attribute \src "libresoc.v:197395.9-197395.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -407108,8 +411799,8 @@ module \ti sync always update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end - attribute \src "libresoc.v:194360.3-194470.6" - process $proc$libresoc.v:194360$13737 + attribute \src "libresoc.v:197405.3-197515.6" + process $proc$libresoc.v:197405$13856 assign { } { } assign { } { } assign { } { } @@ -407228,11 +411919,11 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$13738 $1\core_asmcode$next[7:0]$13797 - assign $0\core_core_core_cia$next[63:0]$13739 $1\core_core_core_cia$next[63:0]$13798 - assign $0\core_core_core_cr_rd$next[7:0]$13740 $1\core_core_core_cr_rd$next[7:0]$13799 + assign $0\core_asmcode$next[7:0]$13857 $1\core_asmcode$next[7:0]$13916 + assign $0\core_core_core_cia$next[63:0]$13858 $1\core_core_core_cia$next[63:0]$13917 + assign $0\core_core_core_cr_rd$next[7:0]$13859 $1\core_core_core_cr_rd$next[7:0]$13918 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$13742 $1\core_core_core_cr_wr$next[7:0]$13801 + assign $0\core_core_core_cr_wr$next[7:0]$13861 $1\core_core_core_cr_wr$next[7:0]$13920 assign { } { } assign { } { } assign { } { } @@ -407241,86 +411932,86 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[12:0]$13751 $1\core_core_core_fn_unit$next[12:0]$13810 - assign $0\core_core_core_input_carry$next[1:0]$13752 $1\core_core_core_input_carry$next[1:0]$13811 - assign $0\core_core_core_insn$next[31:0]$13753 $1\core_core_core_insn$next[31:0]$13812 - assign $0\core_core_core_insn_type$next[6:0]$13754 $1\core_core_core_insn_type$next[6:0]$13813 - assign $0\core_core_core_is_32bit$next[0:0]$13755 $1\core_core_core_is_32bit$next[0:0]$13814 - assign $0\core_core_core_msr$next[63:0]$13756 $1\core_core_core_msr$next[63:0]$13815 - assign $0\core_core_core_oe$next[0:0]$13757 $1\core_core_core_oe$next[0:0]$13816 + assign $0\core_core_core_fn_unit$next[13:0]$13870 $1\core_core_core_fn_unit$next[13:0]$13929 + assign $0\core_core_core_input_carry$next[1:0]$13871 $1\core_core_core_input_carry$next[1:0]$13930 + assign $0\core_core_core_insn$next[31:0]$13872 $1\core_core_core_insn$next[31:0]$13931 + assign $0\core_core_core_insn_type$next[6:0]$13873 $1\core_core_core_insn_type$next[6:0]$13932 + assign $0\core_core_core_is_32bit$next[0:0]$13874 $1\core_core_core_is_32bit$next[0:0]$13933 + assign $0\core_core_core_msr$next[63:0]$13875 $1\core_core_core_msr$next[63:0]$13934 + assign $0\core_core_core_oe$next[0:0]$13876 $1\core_core_core_oe$next[0:0]$13935 assign { } { } - assign $0\core_core_core_rc$next[0:0]$13759 $1\core_core_core_rc$next[0:0]$13818 + assign $0\core_core_core_rc$next[0:0]$13878 $1\core_core_core_rc$next[0:0]$13937 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$13761 $1\core_core_core_trapaddr$next[12:0]$13820 - assign $0\core_core_core_traptype$next[7:0]$13762 $1\core_core_core_traptype$next[7:0]$13821 - assign $0\core_core_cr_in1$next[6:0]$13763 $1\core_core_cr_in1$next[6:0]$13822 + assign $0\core_core_core_trapaddr$next[12:0]$13880 $1\core_core_core_trapaddr$next[12:0]$13939 + assign $0\core_core_core_traptype$next[7:0]$13881 $1\core_core_core_traptype$next[7:0]$13940 + assign $0\core_core_cr_in1$next[6:0]$13882 $1\core_core_cr_in1$next[6:0]$13941 assign { } { } - assign $0\core_core_cr_in2$1$next[6:0]$13765 $1\core_core_cr_in2$1$next[6:0]$13824 - assign $0\core_core_cr_in2$next[6:0]$13766 $1\core_core_cr_in2$next[6:0]$13825 + assign $0\core_core_cr_in2$1$next[6:0]$13884 $1\core_core_cr_in2$1$next[6:0]$13943 + assign $0\core_core_cr_in2$next[6:0]$13885 $1\core_core_cr_in2$next[6:0]$13944 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[6:0]$13769 $1\core_core_cr_out$next[6:0]$13828 + assign $0\core_core_cr_out$next[6:0]$13888 $1\core_core_cr_out$next[6:0]$13947 assign { } { } - assign $0\core_core_ea$next[6:0]$13771 $1\core_core_ea$next[6:0]$13830 - assign $0\core_core_fast1$next[2:0]$13772 $1\core_core_fast1$next[2:0]$13831 + assign $0\core_core_ea$next[6:0]$13890 $1\core_core_ea$next[6:0]$13949 + assign $0\core_core_fast1$next[2:0]$13891 $1\core_core_fast1$next[2:0]$13950 assign { } { } - assign $0\core_core_fast2$next[2:0]$13774 $1\core_core_fast2$next[2:0]$13833 + assign $0\core_core_fast2$next[2:0]$13893 $1\core_core_fast2$next[2:0]$13952 assign { } { } - assign $0\core_core_fasto1$next[2:0]$13776 $1\core_core_fasto1$next[2:0]$13835 - assign $0\core_core_fasto2$next[2:0]$13777 $1\core_core_fasto2$next[2:0]$13836 - assign $0\core_core_lk$next[0:0]$13778 $1\core_core_lk$next[0:0]$13837 - assign $0\core_core_reg1$next[6:0]$13779 $1\core_core_reg1$next[6:0]$13838 + assign $0\core_core_fasto1$next[2:0]$13895 $1\core_core_fasto1$next[2:0]$13954 + assign $0\core_core_fasto2$next[2:0]$13896 $1\core_core_fasto2$next[2:0]$13955 + assign $0\core_core_lk$next[0:0]$13897 $1\core_core_lk$next[0:0]$13956 + assign $0\core_core_reg1$next[6:0]$13898 $1\core_core_reg1$next[6:0]$13957 assign { } { } - assign $0\core_core_reg2$next[6:0]$13781 $1\core_core_reg2$next[6:0]$13840 + assign $0\core_core_reg2$next[6:0]$13900 $1\core_core_reg2$next[6:0]$13959 assign { } { } - assign $0\core_core_reg3$next[6:0]$13783 $1\core_core_reg3$next[6:0]$13842 + assign $0\core_core_reg3$next[6:0]$13902 $1\core_core_reg3$next[6:0]$13961 assign { } { } - assign $0\core_core_rego$next[6:0]$13785 $1\core_core_rego$next[6:0]$13844 - assign $0\core_core_spr1$next[9:0]$13786 $1\core_core_spr1$next[9:0]$13845 + assign $0\core_core_rego$next[6:0]$13904 $1\core_core_rego$next[6:0]$13963 + assign $0\core_core_spr1$next[9:0]$13905 $1\core_core_spr1$next[9:0]$13964 assign { } { } - assign $0\core_core_spro$next[9:0]$13788 $1\core_core_spro$next[9:0]$13847 - assign $0\core_core_xer_in$next[2:0]$13789 $1\core_core_xer_in$next[2:0]$13848 + assign $0\core_core_spro$next[9:0]$13907 $1\core_core_spro$next[9:0]$13966 + assign $0\core_core_xer_in$next[2:0]$13908 $1\core_core_xer_in$next[2:0]$13967 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$13796 $1\core_xer_out$next[0:0]$13855 - assign $0\core_core_core_cr_rd_ok$next[0:0]$13741 $3\core_core_core_cr_rd_ok$next[0:0]$13915 - assign $0\core_core_core_exc_$signal$3$next[0:0]$13743 $3\core_core_core_exc_$signal$3$next[0:0]$13916 - assign $0\core_core_core_exc_$signal$4$next[0:0]$13744 $3\core_core_core_exc_$signal$4$next[0:0]$13917 - assign $0\core_core_core_exc_$signal$5$next[0:0]$13745 $3\core_core_core_exc_$signal$5$next[0:0]$13918 - assign $0\core_core_core_exc_$signal$6$next[0:0]$13746 $3\core_core_core_exc_$signal$6$next[0:0]$13919 - assign $0\core_core_core_exc_$signal$7$next[0:0]$13747 $3\core_core_core_exc_$signal$7$next[0:0]$13920 - assign $0\core_core_core_exc_$signal$8$next[0:0]$13748 $3\core_core_core_exc_$signal$8$next[0:0]$13921 - assign $0\core_core_core_exc_$signal$9$next[0:0]$13749 $3\core_core_core_exc_$signal$9$next[0:0]$13922 - assign $0\core_core_core_exc_$signal$next[0:0]$13750 $3\core_core_core_exc_$signal$next[0:0]$13923 - assign $0\core_core_core_oe_ok$next[0:0]$13758 $3\core_core_core_oe_ok$next[0:0]$13924 - assign $0\core_core_core_rc_ok$next[0:0]$13760 $3\core_core_core_rc_ok$next[0:0]$13925 - assign $0\core_core_cr_in1_ok$next[0:0]$13764 $3\core_core_cr_in1_ok$next[0:0]$13926 - assign $0\core_core_cr_in2_ok$2$next[0:0]$13767 $3\core_core_cr_in2_ok$2$next[0:0]$13927 - assign $0\core_core_cr_in2_ok$next[0:0]$13768 $3\core_core_cr_in2_ok$next[0:0]$13928 - assign $0\core_core_cr_wr_ok$next[0:0]$13770 $3\core_core_cr_wr_ok$next[0:0]$13929 - assign $0\core_core_fast1_ok$next[0:0]$13773 $3\core_core_fast1_ok$next[0:0]$13930 - assign $0\core_core_fast2_ok$next[0:0]$13775 $3\core_core_fast2_ok$next[0:0]$13931 - assign $0\core_core_reg1_ok$next[0:0]$13780 $3\core_core_reg1_ok$next[0:0]$13932 - assign $0\core_core_reg2_ok$next[0:0]$13782 $3\core_core_reg2_ok$next[0:0]$13933 - assign $0\core_core_reg3_ok$next[0:0]$13784 $3\core_core_reg3_ok$next[0:0]$13934 - assign $0\core_core_spr1_ok$next[0:0]$13787 $3\core_core_spr1_ok$next[0:0]$13935 - assign $0\core_cr_out_ok$next[0:0]$13790 $3\core_cr_out_ok$next[0:0]$13936 - assign $0\core_ea_ok$next[0:0]$13791 $3\core_ea_ok$next[0:0]$13937 - assign $0\core_fasto1_ok$next[0:0]$13792 $3\core_fasto1_ok$next[0:0]$13938 - assign $0\core_fasto2_ok$next[0:0]$13793 $3\core_fasto2_ok$next[0:0]$13939 - assign $0\core_rego_ok$next[0:0]$13794 $3\core_rego_ok$next[0:0]$13940 - assign $0\core_spro_ok$next[0:0]$13795 $3\core_spro_ok$next[0:0]$13941 - attribute \src "libresoc.v:194361.5-194361.29" + assign $0\core_xer_out$next[0:0]$13915 $1\core_xer_out$next[0:0]$13974 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13860 $3\core_core_core_cr_rd_ok$next[0:0]$14034 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13862 $3\core_core_core_exc_$signal$3$next[0:0]$14035 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13863 $3\core_core_core_exc_$signal$4$next[0:0]$14036 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13864 $3\core_core_core_exc_$signal$5$next[0:0]$14037 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13865 $3\core_core_core_exc_$signal$6$next[0:0]$14038 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13866 $3\core_core_core_exc_$signal$7$next[0:0]$14039 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13867 $3\core_core_core_exc_$signal$8$next[0:0]$14040 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13868 $3\core_core_core_exc_$signal$9$next[0:0]$14041 + assign $0\core_core_core_exc_$signal$next[0:0]$13869 $3\core_core_core_exc_$signal$next[0:0]$14042 + assign $0\core_core_core_oe_ok$next[0:0]$13877 $3\core_core_core_oe_ok$next[0:0]$14043 + assign $0\core_core_core_rc_ok$next[0:0]$13879 $3\core_core_core_rc_ok$next[0:0]$14044 + assign $0\core_core_cr_in1_ok$next[0:0]$13883 $3\core_core_cr_in1_ok$next[0:0]$14045 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13886 $3\core_core_cr_in2_ok$2$next[0:0]$14046 + assign $0\core_core_cr_in2_ok$next[0:0]$13887 $3\core_core_cr_in2_ok$next[0:0]$14047 + assign $0\core_core_cr_wr_ok$next[0:0]$13889 $3\core_core_cr_wr_ok$next[0:0]$14048 + assign $0\core_core_fast1_ok$next[0:0]$13892 $3\core_core_fast1_ok$next[0:0]$14049 + assign $0\core_core_fast2_ok$next[0:0]$13894 $3\core_core_fast2_ok$next[0:0]$14050 + assign $0\core_core_reg1_ok$next[0:0]$13899 $3\core_core_reg1_ok$next[0:0]$14051 + assign $0\core_core_reg2_ok$next[0:0]$13901 $3\core_core_reg2_ok$next[0:0]$14052 + assign $0\core_core_reg3_ok$next[0:0]$13903 $3\core_core_reg3_ok$next[0:0]$14053 + assign $0\core_core_spr1_ok$next[0:0]$13906 $3\core_core_spr1_ok$next[0:0]$14054 + assign $0\core_cr_out_ok$next[0:0]$13909 $3\core_cr_out_ok$next[0:0]$14055 + assign $0\core_ea_ok$next[0:0]$13910 $3\core_ea_ok$next[0:0]$14056 + assign $0\core_fasto1_ok$next[0:0]$13911 $3\core_fasto1_ok$next[0:0]$14057 + assign $0\core_fasto2_ok$next[0:0]$13912 $3\core_fasto2_ok$next[0:0]$14058 + assign $0\core_rego_ok$next[0:0]$13913 $3\core_rego_ok$next[0:0]$14059 + assign $0\core_spro_ok$next[0:0]$13914 $3\core_spro_ok$next[0:0]$14060 + attribute \src "libresoc.v:197406.5-197406.29" switch \initial - attribute \src "libresoc.v:194361.9-194361.17" + attribute \src "libresoc.v:197406.9-197406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -407383,66 +412074,66 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$13797 $2\core_asmcode$next[7:0]$13856 - assign $1\core_core_core_cia$next[63:0]$13798 $2\core_core_core_cia$next[63:0]$13857 - assign $1\core_core_core_cr_rd$next[7:0]$13799 $2\core_core_core_cr_rd$next[7:0]$13858 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13800 $2\core_core_core_cr_rd_ok$next[0:0]$13859 - assign $1\core_core_core_cr_wr$next[7:0]$13801 $2\core_core_core_cr_wr$next[7:0]$13860 - assign $1\core_core_core_exc_$signal$3$next[0:0]$13802 $2\core_core_core_exc_$signal$3$next[0:0]$13861 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13803 $2\core_core_core_exc_$signal$4$next[0:0]$13862 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13804 $2\core_core_core_exc_$signal$5$next[0:0]$13863 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13805 $2\core_core_core_exc_$signal$6$next[0:0]$13864 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13806 $2\core_core_core_exc_$signal$7$next[0:0]$13865 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13807 $2\core_core_core_exc_$signal$8$next[0:0]$13866 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13808 $2\core_core_core_exc_$signal$9$next[0:0]$13867 - assign $1\core_core_core_exc_$signal$next[0:0]$13809 $2\core_core_core_exc_$signal$next[0:0]$13868 - assign $1\core_core_core_fn_unit$next[12:0]$13810 $2\core_core_core_fn_unit$next[12:0]$13869 - assign $1\core_core_core_input_carry$next[1:0]$13811 $2\core_core_core_input_carry$next[1:0]$13870 - assign $1\core_core_core_insn$next[31:0]$13812 $2\core_core_core_insn$next[31:0]$13871 - assign $1\core_core_core_insn_type$next[6:0]$13813 $2\core_core_core_insn_type$next[6:0]$13872 - assign $1\core_core_core_is_32bit$next[0:0]$13814 $2\core_core_core_is_32bit$next[0:0]$13873 - assign $1\core_core_core_msr$next[63:0]$13815 $2\core_core_core_msr$next[63:0]$13874 - assign $1\core_core_core_oe$next[0:0]$13816 $2\core_core_core_oe$next[0:0]$13875 - assign $1\core_core_core_oe_ok$next[0:0]$13817 $2\core_core_core_oe_ok$next[0:0]$13876 - assign $1\core_core_core_rc$next[0:0]$13818 $2\core_core_core_rc$next[0:0]$13877 - assign $1\core_core_core_rc_ok$next[0:0]$13819 $2\core_core_core_rc_ok$next[0:0]$13878 - assign $1\core_core_core_trapaddr$next[12:0]$13820 $2\core_core_core_trapaddr$next[12:0]$13879 - assign $1\core_core_core_traptype$next[7:0]$13821 $2\core_core_core_traptype$next[7:0]$13880 - assign $1\core_core_cr_in1$next[6:0]$13822 $2\core_core_cr_in1$next[6:0]$13881 - assign $1\core_core_cr_in1_ok$next[0:0]$13823 $2\core_core_cr_in1_ok$next[0:0]$13882 - assign $1\core_core_cr_in2$1$next[6:0]$13824 $2\core_core_cr_in2$1$next[6:0]$13883 - assign $1\core_core_cr_in2$next[6:0]$13825 $2\core_core_cr_in2$next[6:0]$13884 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13826 $2\core_core_cr_in2_ok$2$next[0:0]$13885 - assign $1\core_core_cr_in2_ok$next[0:0]$13827 $2\core_core_cr_in2_ok$next[0:0]$13886 - assign $1\core_core_cr_out$next[6:0]$13828 $2\core_core_cr_out$next[6:0]$13887 - assign $1\core_core_cr_wr_ok$next[0:0]$13829 $2\core_core_cr_wr_ok$next[0:0]$13888 - assign $1\core_core_ea$next[6:0]$13830 $2\core_core_ea$next[6:0]$13889 - assign $1\core_core_fast1$next[2:0]$13831 $2\core_core_fast1$next[2:0]$13890 - assign $1\core_core_fast1_ok$next[0:0]$13832 $2\core_core_fast1_ok$next[0:0]$13891 - assign $1\core_core_fast2$next[2:0]$13833 $2\core_core_fast2$next[2:0]$13892 - assign $1\core_core_fast2_ok$next[0:0]$13834 $2\core_core_fast2_ok$next[0:0]$13893 - assign $1\core_core_fasto1$next[2:0]$13835 $2\core_core_fasto1$next[2:0]$13894 - assign $1\core_core_fasto2$next[2:0]$13836 $2\core_core_fasto2$next[2:0]$13895 - assign $1\core_core_lk$next[0:0]$13837 $2\core_core_lk$next[0:0]$13896 - assign $1\core_core_reg1$next[6:0]$13838 $2\core_core_reg1$next[6:0]$13897 - assign $1\core_core_reg1_ok$next[0:0]$13839 $2\core_core_reg1_ok$next[0:0]$13898 - assign $1\core_core_reg2$next[6:0]$13840 $2\core_core_reg2$next[6:0]$13899 - assign $1\core_core_reg2_ok$next[0:0]$13841 $2\core_core_reg2_ok$next[0:0]$13900 - assign $1\core_core_reg3$next[6:0]$13842 $2\core_core_reg3$next[6:0]$13901 - assign $1\core_core_reg3_ok$next[0:0]$13843 $2\core_core_reg3_ok$next[0:0]$13902 - assign $1\core_core_rego$next[6:0]$13844 $2\core_core_rego$next[6:0]$13903 - assign $1\core_core_spr1$next[9:0]$13845 $2\core_core_spr1$next[9:0]$13904 - assign $1\core_core_spr1_ok$next[0:0]$13846 $2\core_core_spr1_ok$next[0:0]$13905 - assign $1\core_core_spro$next[9:0]$13847 $2\core_core_spro$next[9:0]$13906 - assign $1\core_core_xer_in$next[2:0]$13848 $2\core_core_xer_in$next[2:0]$13907 - assign $1\core_cr_out_ok$next[0:0]$13849 $2\core_cr_out_ok$next[0:0]$13908 - assign $1\core_ea_ok$next[0:0]$13850 $2\core_ea_ok$next[0:0]$13909 - assign $1\core_fasto1_ok$next[0:0]$13851 $2\core_fasto1_ok$next[0:0]$13910 - assign $1\core_fasto2_ok$next[0:0]$13852 $2\core_fasto2_ok$next[0:0]$13911 - assign $1\core_rego_ok$next[0:0]$13853 $2\core_rego_ok$next[0:0]$13912 - assign $1\core_spro_ok$next[0:0]$13854 $2\core_spro_ok$next[0:0]$13913 - assign $1\core_xer_out$next[0:0]$13855 $2\core_xer_out$next[0:0]$13914 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + assign $1\core_asmcode$next[7:0]$13916 $2\core_asmcode$next[7:0]$13975 + assign $1\core_core_core_cia$next[63:0]$13917 $2\core_core_core_cia$next[63:0]$13976 + assign $1\core_core_core_cr_rd$next[7:0]$13918 $2\core_core_core_cr_rd$next[7:0]$13977 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13919 $2\core_core_core_cr_rd_ok$next[0:0]$13978 + assign $1\core_core_core_cr_wr$next[7:0]$13920 $2\core_core_core_cr_wr$next[7:0]$13979 + assign $1\core_core_core_exc_$signal$3$next[0:0]$13921 $2\core_core_core_exc_$signal$3$next[0:0]$13980 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13922 $2\core_core_core_exc_$signal$4$next[0:0]$13981 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13923 $2\core_core_core_exc_$signal$5$next[0:0]$13982 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13924 $2\core_core_core_exc_$signal$6$next[0:0]$13983 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13925 $2\core_core_core_exc_$signal$7$next[0:0]$13984 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13926 $2\core_core_core_exc_$signal$8$next[0:0]$13985 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13927 $2\core_core_core_exc_$signal$9$next[0:0]$13986 + assign $1\core_core_core_exc_$signal$next[0:0]$13928 $2\core_core_core_exc_$signal$next[0:0]$13987 + assign $1\core_core_core_fn_unit$next[13:0]$13929 $2\core_core_core_fn_unit$next[13:0]$13988 + assign $1\core_core_core_input_carry$next[1:0]$13930 $2\core_core_core_input_carry$next[1:0]$13989 + assign $1\core_core_core_insn$next[31:0]$13931 $2\core_core_core_insn$next[31:0]$13990 + assign $1\core_core_core_insn_type$next[6:0]$13932 $2\core_core_core_insn_type$next[6:0]$13991 + assign $1\core_core_core_is_32bit$next[0:0]$13933 $2\core_core_core_is_32bit$next[0:0]$13992 + assign $1\core_core_core_msr$next[63:0]$13934 $2\core_core_core_msr$next[63:0]$13993 + assign $1\core_core_core_oe$next[0:0]$13935 $2\core_core_core_oe$next[0:0]$13994 + assign $1\core_core_core_oe_ok$next[0:0]$13936 $2\core_core_core_oe_ok$next[0:0]$13995 + assign $1\core_core_core_rc$next[0:0]$13937 $2\core_core_core_rc$next[0:0]$13996 + assign $1\core_core_core_rc_ok$next[0:0]$13938 $2\core_core_core_rc_ok$next[0:0]$13997 + assign $1\core_core_core_trapaddr$next[12:0]$13939 $2\core_core_core_trapaddr$next[12:0]$13998 + assign $1\core_core_core_traptype$next[7:0]$13940 $2\core_core_core_traptype$next[7:0]$13999 + assign $1\core_core_cr_in1$next[6:0]$13941 $2\core_core_cr_in1$next[6:0]$14000 + assign $1\core_core_cr_in1_ok$next[0:0]$13942 $2\core_core_cr_in1_ok$next[0:0]$14001 + assign $1\core_core_cr_in2$1$next[6:0]$13943 $2\core_core_cr_in2$1$next[6:0]$14002 + assign $1\core_core_cr_in2$next[6:0]$13944 $2\core_core_cr_in2$next[6:0]$14003 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13945 $2\core_core_cr_in2_ok$2$next[0:0]$14004 + assign $1\core_core_cr_in2_ok$next[0:0]$13946 $2\core_core_cr_in2_ok$next[0:0]$14005 + assign $1\core_core_cr_out$next[6:0]$13947 $2\core_core_cr_out$next[6:0]$14006 + assign $1\core_core_cr_wr_ok$next[0:0]$13948 $2\core_core_cr_wr_ok$next[0:0]$14007 + assign $1\core_core_ea$next[6:0]$13949 $2\core_core_ea$next[6:0]$14008 + assign $1\core_core_fast1$next[2:0]$13950 $2\core_core_fast1$next[2:0]$14009 + assign $1\core_core_fast1_ok$next[0:0]$13951 $2\core_core_fast1_ok$next[0:0]$14010 + assign $1\core_core_fast2$next[2:0]$13952 $2\core_core_fast2$next[2:0]$14011 + assign $1\core_core_fast2_ok$next[0:0]$13953 $2\core_core_fast2_ok$next[0:0]$14012 + assign $1\core_core_fasto1$next[2:0]$13954 $2\core_core_fasto1$next[2:0]$14013 + assign $1\core_core_fasto2$next[2:0]$13955 $2\core_core_fasto2$next[2:0]$14014 + assign $1\core_core_lk$next[0:0]$13956 $2\core_core_lk$next[0:0]$14015 + assign $1\core_core_reg1$next[6:0]$13957 $2\core_core_reg1$next[6:0]$14016 + assign $1\core_core_reg1_ok$next[0:0]$13958 $2\core_core_reg1_ok$next[0:0]$14017 + assign $1\core_core_reg2$next[6:0]$13959 $2\core_core_reg2$next[6:0]$14018 + assign $1\core_core_reg2_ok$next[0:0]$13960 $2\core_core_reg2_ok$next[0:0]$14019 + assign $1\core_core_reg3$next[6:0]$13961 $2\core_core_reg3$next[6:0]$14020 + assign $1\core_core_reg3_ok$next[0:0]$13962 $2\core_core_reg3_ok$next[0:0]$14021 + assign $1\core_core_rego$next[6:0]$13963 $2\core_core_rego$next[6:0]$14022 + assign $1\core_core_spr1$next[9:0]$13964 $2\core_core_spr1$next[9:0]$14023 + assign $1\core_core_spr1_ok$next[0:0]$13965 $2\core_core_spr1_ok$next[0:0]$14024 + assign $1\core_core_spro$next[9:0]$13966 $2\core_core_spro$next[9:0]$14025 + assign $1\core_core_xer_in$next[2:0]$13967 $2\core_core_xer_in$next[2:0]$14026 + assign $1\core_cr_out_ok$next[0:0]$13968 $2\core_cr_out_ok$next[0:0]$14027 + assign $1\core_ea_ok$next[0:0]$13969 $2\core_ea_ok$next[0:0]$14028 + assign $1\core_fasto1_ok$next[0:0]$13970 $2\core_fasto1_ok$next[0:0]$14029 + assign $1\core_fasto2_ok$next[0:0]$13971 $2\core_fasto2_ok$next[0:0]$14030 + assign $1\core_rego_ok$next[0:0]$13972 $2\core_rego_ok$next[0:0]$14031 + assign $1\core_spro_ok$next[0:0]$13973 $2\core_spro_ok$next[0:0]$14032 + assign $1\core_xer_out$next[0:0]$13974 $2\core_xer_out$next[0:0]$14033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -407505,67 +412196,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$13873 $2\core_core_cr_wr_ok$next[0:0]$13888 $2\core_core_core_cr_wr$next[7:0]$13860 $2\core_core_core_cr_rd_ok$next[0:0]$13859 $2\core_core_core_cr_rd$next[7:0]$13858 $2\core_core_core_trapaddr$next[12:0]$13879 $2\core_core_core_exc_$signal$9$next[0:0]$13867 $2\core_core_core_exc_$signal$8$next[0:0]$13866 $2\core_core_core_exc_$signal$7$next[0:0]$13865 $2\core_core_core_exc_$signal$6$next[0:0]$13864 $2\core_core_core_exc_$signal$5$next[0:0]$13863 $2\core_core_core_exc_$signal$4$next[0:0]$13862 $2\core_core_core_exc_$signal$3$next[0:0]$13861 $2\core_core_core_exc_$signal$next[0:0]$13868 $2\core_core_core_traptype$next[7:0]$13880 $2\core_core_core_input_carry$next[1:0]$13870 $2\core_core_core_oe_ok$next[0:0]$13876 $2\core_core_core_oe$next[0:0]$13875 $2\core_core_core_rc_ok$next[0:0]$13878 $2\core_core_core_rc$next[0:0]$13877 $2\core_core_lk$next[0:0]$13896 $2\core_core_core_fn_unit$next[12:0]$13869 $2\core_core_core_insn_type$next[6:0]$13872 $2\core_core_core_insn$next[31:0]$13871 $2\core_core_core_cia$next[63:0]$13857 $2\core_core_core_msr$next[63:0]$13874 $2\core_cr_out_ok$next[0:0]$13908 $2\core_core_cr_out$next[6:0]$13887 $2\core_core_cr_in2_ok$2$next[0:0]$13885 $2\core_core_cr_in2$1$next[6:0]$13883 $2\core_core_cr_in2_ok$next[0:0]$13886 $2\core_core_cr_in2$next[6:0]$13884 $2\core_core_cr_in1_ok$next[0:0]$13882 $2\core_core_cr_in1$next[6:0]$13881 $2\core_fasto2_ok$next[0:0]$13911 $2\core_core_fasto2$next[2:0]$13895 $2\core_fasto1_ok$next[0:0]$13910 $2\core_core_fasto1$next[2:0]$13894 $2\core_core_fast2_ok$next[0:0]$13893 $2\core_core_fast2$next[2:0]$13892 $2\core_core_fast1_ok$next[0:0]$13891 $2\core_core_fast1$next[2:0]$13890 $2\core_xer_out$next[0:0]$13914 $2\core_core_xer_in$next[2:0]$13907 $2\core_core_spr1_ok$next[0:0]$13905 $2\core_core_spr1$next[9:0]$13904 $2\core_spro_ok$next[0:0]$13913 $2\core_core_spro$next[9:0]$13906 $2\core_core_reg3_ok$next[0:0]$13902 $2\core_core_reg3$next[6:0]$13901 $2\core_core_reg2_ok$next[0:0]$13900 $2\core_core_reg2$next[6:0]$13899 $2\core_core_reg1_ok$next[0:0]$13898 $2\core_core_reg1$next[6:0]$13897 $2\core_ea_ok$next[0:0]$13909 $2\core_core_ea$next[6:0]$13889 $2\core_rego_ok$next[0:0]$13912 $2\core_core_rego$next[6:0]$13903 $2\core_asmcode$next[7:0]$13856 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $2\core_core_core_is_32bit$next[0:0]$13992 $2\core_core_cr_wr_ok$next[0:0]$14007 $2\core_core_core_cr_wr$next[7:0]$13979 $2\core_core_core_cr_rd_ok$next[0:0]$13978 $2\core_core_core_cr_rd$next[7:0]$13977 $2\core_core_core_trapaddr$next[12:0]$13998 $2\core_core_core_exc_$signal$9$next[0:0]$13986 $2\core_core_core_exc_$signal$8$next[0:0]$13985 $2\core_core_core_exc_$signal$7$next[0:0]$13984 $2\core_core_core_exc_$signal$6$next[0:0]$13983 $2\core_core_core_exc_$signal$5$next[0:0]$13982 $2\core_core_core_exc_$signal$4$next[0:0]$13981 $2\core_core_core_exc_$signal$3$next[0:0]$13980 $2\core_core_core_exc_$signal$next[0:0]$13987 $2\core_core_core_traptype$next[7:0]$13999 $2\core_core_core_input_carry$next[1:0]$13989 $2\core_core_core_oe_ok$next[0:0]$13995 $2\core_core_core_oe$next[0:0]$13994 $2\core_core_core_rc_ok$next[0:0]$13997 $2\core_core_core_rc$next[0:0]$13996 $2\core_core_lk$next[0:0]$14015 $2\core_core_core_fn_unit$next[13:0]$13988 $2\core_core_core_insn_type$next[6:0]$13991 $2\core_core_core_insn$next[31:0]$13990 $2\core_core_core_cia$next[63:0]$13976 $2\core_core_core_msr$next[63:0]$13993 $2\core_cr_out_ok$next[0:0]$14027 $2\core_core_cr_out$next[6:0]$14006 $2\core_core_cr_in2_ok$2$next[0:0]$14004 $2\core_core_cr_in2$1$next[6:0]$14002 $2\core_core_cr_in2_ok$next[0:0]$14005 $2\core_core_cr_in2$next[6:0]$14003 $2\core_core_cr_in1_ok$next[0:0]$14001 $2\core_core_cr_in1$next[6:0]$14000 $2\core_fasto2_ok$next[0:0]$14030 $2\core_core_fasto2$next[2:0]$14014 $2\core_fasto1_ok$next[0:0]$14029 $2\core_core_fasto1$next[2:0]$14013 $2\core_core_fast2_ok$next[0:0]$14012 $2\core_core_fast2$next[2:0]$14011 $2\core_core_fast1_ok$next[0:0]$14010 $2\core_core_fast1$next[2:0]$14009 $2\core_xer_out$next[0:0]$14033 $2\core_core_xer_in$next[2:0]$14026 $2\core_core_spr1_ok$next[0:0]$14024 $2\core_core_spr1$next[9:0]$14023 $2\core_spro_ok$next[0:0]$14032 $2\core_core_spro$next[9:0]$14025 $2\core_core_reg3_ok$next[0:0]$14021 $2\core_core_reg3$next[6:0]$14020 $2\core_core_reg2_ok$next[0:0]$14019 $2\core_core_reg2$next[6:0]$14018 $2\core_core_reg1_ok$next[0:0]$14017 $2\core_core_reg1$next[6:0]$14016 $2\core_ea_ok$next[0:0]$14028 $2\core_core_ea$next[6:0]$14008 $2\core_rego_ok$next[0:0]$14031 $2\core_core_rego$next[6:0]$14022 $2\core_asmcode$next[7:0]$13975 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $2\core_asmcode$next[7:0]$13856 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$13857 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$13858 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$13859 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$13860 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$13861 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$13862 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$13863 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$13864 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$13865 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$13866 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$13867 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$13868 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[12:0]$13869 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$13870 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$13871 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$13872 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$13873 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$13874 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$13875 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$13876 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$13877 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$13878 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$13879 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$13880 \core_core_core_traptype - assign $2\core_core_cr_in1$next[6:0]$13881 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$13882 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[6:0]$13883 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[6:0]$13884 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$13885 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$13886 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[6:0]$13887 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$13888 \core_core_cr_wr_ok - assign $2\core_core_ea$next[6:0]$13889 \core_core_ea - assign $2\core_core_fast1$next[2:0]$13890 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$13891 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$13892 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$13893 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$13894 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$13895 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$13896 \core_core_lk - assign $2\core_core_reg1$next[6:0]$13897 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$13898 \core_core_reg1_ok - assign $2\core_core_reg2$next[6:0]$13899 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$13900 \core_core_reg2_ok - assign $2\core_core_reg3$next[6:0]$13901 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$13902 \core_core_reg3_ok - assign $2\core_core_rego$next[6:0]$13903 \core_core_rego - assign $2\core_core_spr1$next[9:0]$13904 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$13905 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$13906 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$13907 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$13908 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$13909 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$13910 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$13911 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$13912 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$13913 \core_spro_ok - assign $2\core_xer_out$next[0:0]$13914 \core_xer_out + assign $2\core_asmcode$next[7:0]$13975 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$13976 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$13977 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$13978 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$13979 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$13980 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$13981 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$13982 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$13983 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$13984 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$13985 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$13986 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$13987 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[13:0]$13988 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$13989 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$13990 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$13991 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$13992 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$13993 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$13994 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$13995 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$13996 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$13997 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$13998 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$13999 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14000 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14001 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14002 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14003 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14004 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14005 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14006 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14007 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14008 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14009 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14010 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14011 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14012 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14013 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14014 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14015 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14016 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14017 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14018 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14019 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14020 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14021 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14022 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14023 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14024 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14025 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14026 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14027 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14028 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14029 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14030 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14031 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14032 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14033 \core_xer_out end attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -407628,67 +412319,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$13814 $1\core_core_cr_wr_ok$next[0:0]$13829 $1\core_core_core_cr_wr$next[7:0]$13801 $1\core_core_core_cr_rd_ok$next[0:0]$13800 $1\core_core_core_cr_rd$next[7:0]$13799 $1\core_core_core_trapaddr$next[12:0]$13820 $1\core_core_core_exc_$signal$9$next[0:0]$13808 $1\core_core_core_exc_$signal$8$next[0:0]$13807 $1\core_core_core_exc_$signal$7$next[0:0]$13806 $1\core_core_core_exc_$signal$6$next[0:0]$13805 $1\core_core_core_exc_$signal$5$next[0:0]$13804 $1\core_core_core_exc_$signal$4$next[0:0]$13803 $1\core_core_core_exc_$signal$3$next[0:0]$13802 $1\core_core_core_exc_$signal$next[0:0]$13809 $1\core_core_core_traptype$next[7:0]$13821 $1\core_core_core_input_carry$next[1:0]$13811 $1\core_core_core_oe_ok$next[0:0]$13817 $1\core_core_core_oe$next[0:0]$13816 $1\core_core_core_rc_ok$next[0:0]$13819 $1\core_core_core_rc$next[0:0]$13818 $1\core_core_lk$next[0:0]$13837 $1\core_core_core_fn_unit$next[12:0]$13810 $1\core_core_core_insn_type$next[6:0]$13813 $1\core_core_core_insn$next[31:0]$13812 $1\core_core_core_cia$next[63:0]$13798 $1\core_core_core_msr$next[63:0]$13815 $1\core_cr_out_ok$next[0:0]$13849 $1\core_core_cr_out$next[6:0]$13828 $1\core_core_cr_in2_ok$2$next[0:0]$13826 $1\core_core_cr_in2$1$next[6:0]$13824 $1\core_core_cr_in2_ok$next[0:0]$13827 $1\core_core_cr_in2$next[6:0]$13825 $1\core_core_cr_in1_ok$next[0:0]$13823 $1\core_core_cr_in1$next[6:0]$13822 $1\core_fasto2_ok$next[0:0]$13852 $1\core_core_fasto2$next[2:0]$13836 $1\core_fasto1_ok$next[0:0]$13851 $1\core_core_fasto1$next[2:0]$13835 $1\core_core_fast2_ok$next[0:0]$13834 $1\core_core_fast2$next[2:0]$13833 $1\core_core_fast1_ok$next[0:0]$13832 $1\core_core_fast1$next[2:0]$13831 $1\core_xer_out$next[0:0]$13855 $1\core_core_xer_in$next[2:0]$13848 $1\core_core_spr1_ok$next[0:0]$13846 $1\core_core_spr1$next[9:0]$13845 $1\core_spro_ok$next[0:0]$13854 $1\core_core_spro$next[9:0]$13847 $1\core_core_reg3_ok$next[0:0]$13843 $1\core_core_reg3$next[6:0]$13842 $1\core_core_reg2_ok$next[0:0]$13841 $1\core_core_reg2$next[6:0]$13840 $1\core_core_reg1_ok$next[0:0]$13839 $1\core_core_reg1$next[6:0]$13838 $1\core_ea_ok$next[0:0]$13850 $1\core_core_ea$next[6:0]$13830 $1\core_rego_ok$next[0:0]$13853 $1\core_core_rego$next[6:0]$13844 $1\core_asmcode$next[7:0]$13797 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $1\core_core_core_is_32bit$next[0:0]$13933 $1\core_core_cr_wr_ok$next[0:0]$13948 $1\core_core_core_cr_wr$next[7:0]$13920 $1\core_core_core_cr_rd_ok$next[0:0]$13919 $1\core_core_core_cr_rd$next[7:0]$13918 $1\core_core_core_trapaddr$next[12:0]$13939 $1\core_core_core_exc_$signal$9$next[0:0]$13927 $1\core_core_core_exc_$signal$8$next[0:0]$13926 $1\core_core_core_exc_$signal$7$next[0:0]$13925 $1\core_core_core_exc_$signal$6$next[0:0]$13924 $1\core_core_core_exc_$signal$5$next[0:0]$13923 $1\core_core_core_exc_$signal$4$next[0:0]$13922 $1\core_core_core_exc_$signal$3$next[0:0]$13921 $1\core_core_core_exc_$signal$next[0:0]$13928 $1\core_core_core_traptype$next[7:0]$13940 $1\core_core_core_input_carry$next[1:0]$13930 $1\core_core_core_oe_ok$next[0:0]$13936 $1\core_core_core_oe$next[0:0]$13935 $1\core_core_core_rc_ok$next[0:0]$13938 $1\core_core_core_rc$next[0:0]$13937 $1\core_core_lk$next[0:0]$13956 $1\core_core_core_fn_unit$next[13:0]$13929 $1\core_core_core_insn_type$next[6:0]$13932 $1\core_core_core_insn$next[31:0]$13931 $1\core_core_core_cia$next[63:0]$13917 $1\core_core_core_msr$next[63:0]$13934 $1\core_cr_out_ok$next[0:0]$13968 $1\core_core_cr_out$next[6:0]$13947 $1\core_core_cr_in2_ok$2$next[0:0]$13945 $1\core_core_cr_in2$1$next[6:0]$13943 $1\core_core_cr_in2_ok$next[0:0]$13946 $1\core_core_cr_in2$next[6:0]$13944 $1\core_core_cr_in1_ok$next[0:0]$13942 $1\core_core_cr_in1$next[6:0]$13941 $1\core_fasto2_ok$next[0:0]$13971 $1\core_core_fasto2$next[2:0]$13955 $1\core_fasto1_ok$next[0:0]$13970 $1\core_core_fasto1$next[2:0]$13954 $1\core_core_fast2_ok$next[0:0]$13953 $1\core_core_fast2$next[2:0]$13952 $1\core_core_fast1_ok$next[0:0]$13951 $1\core_core_fast1$next[2:0]$13950 $1\core_xer_out$next[0:0]$13974 $1\core_core_xer_in$next[2:0]$13967 $1\core_core_spr1_ok$next[0:0]$13965 $1\core_core_spr1$next[9:0]$13964 $1\core_spro_ok$next[0:0]$13973 $1\core_core_spro$next[9:0]$13966 $1\core_core_reg3_ok$next[0:0]$13962 $1\core_core_reg3$next[6:0]$13961 $1\core_core_reg2_ok$next[0:0]$13960 $1\core_core_reg2$next[6:0]$13959 $1\core_core_reg1_ok$next[0:0]$13958 $1\core_core_reg1$next[6:0]$13957 $1\core_ea_ok$next[0:0]$13969 $1\core_core_ea$next[6:0]$13949 $1\core_rego_ok$next[0:0]$13972 $1\core_core_rego$next[6:0]$13963 $1\core_asmcode$next[7:0]$13916 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $1\core_asmcode$next[7:0]$13797 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13798 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13799 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13800 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13801 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13802 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13803 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13804 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13805 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13806 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13807 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13808 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13809 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[12:0]$13810 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13811 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13812 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13813 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13814 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13815 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13816 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13817 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13818 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13819 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13820 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13821 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13822 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13823 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13824 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13825 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13826 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13827 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13828 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13829 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13830 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13831 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13832 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13833 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13834 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13835 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13836 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13837 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13838 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13839 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13840 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13841 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13842 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13843 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13844 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13845 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13846 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13847 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13848 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13849 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13850 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13851 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13852 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13853 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13854 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13855 \core_xer_out + assign $1\core_asmcode$next[7:0]$13916 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13917 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13918 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13919 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13920 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13921 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13922 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13923 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13924 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13925 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13926 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13927 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13928 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$13929 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13930 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13931 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13932 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13933 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13934 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13935 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13936 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13937 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13938 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13939 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13940 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13941 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13942 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13943 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13944 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13945 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13946 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13947 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13948 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13949 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13950 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13951 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13952 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13953 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13954 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13955 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13956 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13957 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13958 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13959 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13960 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13961 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13962 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13963 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13964 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13965 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13966 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13967 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13968 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13969 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13970 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13971 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13972 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13973 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13974 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -407721,296 +412412,255 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_rego_ok$next[0:0]$13940 1'0 - assign $3\core_ea_ok$next[0:0]$13937 1'0 - assign $3\core_core_reg1_ok$next[0:0]$13932 1'0 - assign $3\core_core_reg2_ok$next[0:0]$13933 1'0 - assign $3\core_core_reg3_ok$next[0:0]$13934 1'0 - assign $3\core_spro_ok$next[0:0]$13941 1'0 - assign $3\core_core_spr1_ok$next[0:0]$13935 1'0 - assign $3\core_core_fast1_ok$next[0:0]$13930 1'0 - assign $3\core_core_fast2_ok$next[0:0]$13931 1'0 - assign $3\core_fasto1_ok$next[0:0]$13938 1'0 - assign $3\core_fasto2_ok$next[0:0]$13939 1'0 - assign $3\core_core_cr_in1_ok$next[0:0]$13926 1'0 - assign $3\core_core_cr_in2_ok$next[0:0]$13928 1'0 - assign $3\core_core_cr_in2_ok$2$next[0:0]$13927 1'0 - assign $3\core_cr_out_ok$next[0:0]$13936 1'0 - assign $3\core_core_core_rc_ok$next[0:0]$13925 1'0 - assign $3\core_core_core_oe_ok$next[0:0]$13924 1'0 - assign $3\core_core_core_exc_$signal$next[0:0]$13923 1'0 - assign $3\core_core_core_exc_$signal$3$next[0:0]$13916 1'0 - assign $3\core_core_core_exc_$signal$4$next[0:0]$13917 1'0 - assign $3\core_core_core_exc_$signal$5$next[0:0]$13918 1'0 - assign $3\core_core_core_exc_$signal$6$next[0:0]$13919 1'0 - assign $3\core_core_core_exc_$signal$7$next[0:0]$13920 1'0 - assign $3\core_core_core_exc_$signal$8$next[0:0]$13921 1'0 - assign $3\core_core_core_exc_$signal$9$next[0:0]$13922 1'0 - assign $3\core_core_core_cr_rd_ok$next[0:0]$13915 1'0 - assign $3\core_core_cr_wr_ok$next[0:0]$13929 1'0 - case - assign $3\core_core_core_cr_rd_ok$next[0:0]$13915 $1\core_core_core_cr_rd_ok$next[0:0]$13800 - assign $3\core_core_core_exc_$signal$3$next[0:0]$13916 $1\core_core_core_exc_$signal$3$next[0:0]$13802 - assign $3\core_core_core_exc_$signal$4$next[0:0]$13917 $1\core_core_core_exc_$signal$4$next[0:0]$13803 - assign $3\core_core_core_exc_$signal$5$next[0:0]$13918 $1\core_core_core_exc_$signal$5$next[0:0]$13804 - assign $3\core_core_core_exc_$signal$6$next[0:0]$13919 $1\core_core_core_exc_$signal$6$next[0:0]$13805 - assign $3\core_core_core_exc_$signal$7$next[0:0]$13920 $1\core_core_core_exc_$signal$7$next[0:0]$13806 - assign $3\core_core_core_exc_$signal$8$next[0:0]$13921 $1\core_core_core_exc_$signal$8$next[0:0]$13807 - assign $3\core_core_core_exc_$signal$9$next[0:0]$13922 $1\core_core_core_exc_$signal$9$next[0:0]$13808 - assign $3\core_core_core_exc_$signal$next[0:0]$13923 $1\core_core_core_exc_$signal$next[0:0]$13809 - assign $3\core_core_core_oe_ok$next[0:0]$13924 $1\core_core_core_oe_ok$next[0:0]$13817 - assign $3\core_core_core_rc_ok$next[0:0]$13925 $1\core_core_core_rc_ok$next[0:0]$13819 - assign $3\core_core_cr_in1_ok$next[0:0]$13926 $1\core_core_cr_in1_ok$next[0:0]$13823 - assign $3\core_core_cr_in2_ok$2$next[0:0]$13927 $1\core_core_cr_in2_ok$2$next[0:0]$13826 - assign $3\core_core_cr_in2_ok$next[0:0]$13928 $1\core_core_cr_in2_ok$next[0:0]$13827 - assign $3\core_core_cr_wr_ok$next[0:0]$13929 $1\core_core_cr_wr_ok$next[0:0]$13829 - assign $3\core_core_fast1_ok$next[0:0]$13930 $1\core_core_fast1_ok$next[0:0]$13832 - assign $3\core_core_fast2_ok$next[0:0]$13931 $1\core_core_fast2_ok$next[0:0]$13834 - assign $3\core_core_reg1_ok$next[0:0]$13932 $1\core_core_reg1_ok$next[0:0]$13839 - assign $3\core_core_reg2_ok$next[0:0]$13933 $1\core_core_reg2_ok$next[0:0]$13841 - assign $3\core_core_reg3_ok$next[0:0]$13934 $1\core_core_reg3_ok$next[0:0]$13843 - assign $3\core_core_spr1_ok$next[0:0]$13935 $1\core_core_spr1_ok$next[0:0]$13846 - assign $3\core_cr_out_ok$next[0:0]$13936 $1\core_cr_out_ok$next[0:0]$13849 - assign $3\core_ea_ok$next[0:0]$13937 $1\core_ea_ok$next[0:0]$13850 - assign $3\core_fasto1_ok$next[0:0]$13938 $1\core_fasto1_ok$next[0:0]$13851 - assign $3\core_fasto2_ok$next[0:0]$13939 $1\core_fasto2_ok$next[0:0]$13852 - assign $3\core_rego_ok$next[0:0]$13940 $1\core_rego_ok$next[0:0]$13853 - assign $3\core_spro_ok$next[0:0]$13941 $1\core_spro_ok$next[0:0]$13854 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$13738 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13739 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13740 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13741 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13742 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13743 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13744 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13745 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13746 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13747 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13748 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13749 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13750 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[12:0]$13751 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13752 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13753 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13754 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13755 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13756 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13757 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13758 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13759 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13760 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13761 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13762 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13763 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13764 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13765 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13766 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13767 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13768 - update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13769 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13770 - update \core_core_ea$next $0\core_core_ea$next[6:0]$13771 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13772 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13773 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13774 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13775 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13776 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13777 - update \core_core_lk$next $0\core_core_lk$next[0:0]$13778 - update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13779 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13780 - update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13781 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13782 - update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13783 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13784 - update \core_core_rego$next $0\core_core_rego$next[6:0]$13785 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13786 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13787 - update \core_core_spro$next $0\core_core_spro$next[9:0]$13788 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13789 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13790 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13791 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13792 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13793 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13794 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13795 - update \core_xer_out$next $0\core_xer_out$next[0:0]$13796 - end - attribute \src "libresoc.v:194471.3-194479.6" - process $proc$libresoc.v:194471$13942 - assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13943 $1\dec2_cur_eint$next[0:0]$13944 - attribute \src "libresoc.v:194472.5-194472.29" - switch \initial - attribute \src "libresoc.v:194472.9-194472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13944 1'0 - case - assign $1\dec2_cur_eint$next[0:0]$13944 \xics_icp_core_irq_o - end - sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13943 - end - attribute \src "libresoc.v:194480.3-194489.6" - process $proc$libresoc.v:194480$13945 - assign { } { } - assign { } { } - assign $0\delay$next[1:0]$13946 $1\delay$next[1:0]$13947 - attribute \src "libresoc.v:194481.5-194481.29" - switch \initial - attribute \src "libresoc.v:194481.9-194481.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:509" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\delay$next[1:0]$13947 \$25 [1:0] - case - assign $1\delay$next[1:0]$13947 \delay - end - sync always - update \delay$next $0\delay$next[1:0]$13946 - end - connect \$101 $add$libresoc.v:191878$13258_Y - connect \$103 $mul$libresoc.v:191879$13259_Y - connect \$99 $shr$libresoc.v:191880$13260_Y [31:0] - connect \$106 $not$libresoc.v:191881$13261_Y - connect \$108 $not$libresoc.v:191882$13262_Y - connect \$110 $and$libresoc.v:191883$13263_Y - connect \$112 $not$libresoc.v:191884$13264_Y - connect \$114 $not$libresoc.v:191885$13265_Y - connect \$116 $and$libresoc.v:191886$13266_Y - connect \$118 $or$libresoc.v:191887$13267_Y - connect \$120 $or$libresoc.v:191888$13268_Y - connect \$122 1'0 - connect \$124 $not$libresoc.v:191890$13269_Y - connect \$126 $not$libresoc.v:191891$13270_Y - connect \$128 $and$libresoc.v:191892$13271_Y - connect \$130 $not$libresoc.v:191893$13272_Y - connect \$132 $not$libresoc.v:191894$13273_Y - connect \$134 $and$libresoc.v:191895$13274_Y - connect \$136 1'0 - connect \$138 $eq$libresoc.v:191897$13275_Y - connect \$140 $and$libresoc.v:191898$13276_Y - connect \$142 $not$libresoc.v:191899$13277_Y - connect \$144 $not$libresoc.v:191900$13278_Y - connect \$146 $and$libresoc.v:191901$13279_Y - connect \$148 $or$libresoc.v:191902$13280_Y - connect \$150 $or$libresoc.v:191903$13281_Y - connect \$152 $not$libresoc.v:191904$13282_Y - connect \$154 $not$libresoc.v:191905$13283_Y - connect \$156 $and$libresoc.v:191906$13284_Y - connect \$158 $not$libresoc.v:191907$13285_Y - connect \$160 $not$libresoc.v:191908$13286_Y - connect \$162 $and$libresoc.v:191909$13287_Y - connect \$164 $not$libresoc.v:191910$13288_Y - connect \$166 $not$libresoc.v:191911$13289_Y - connect \$168 $and$libresoc.v:191912$13290_Y - connect \$170 $not$libresoc.v:191913$13291_Y - connect \$172 $not$libresoc.v:191914$13292_Y - connect \$174 $and$libresoc.v:191915$13293_Y - connect \$176 $not$libresoc.v:191916$13294_Y - connect \$178 $not$libresoc.v:191917$13295_Y - connect \$180 $and$libresoc.v:191918$13296_Y - connect \$182 $not$libresoc.v:191919$13297_Y - connect \$184 $not$libresoc.v:191920$13298_Y - connect \$186 $and$libresoc.v:191921$13299_Y - connect \$189 $and$libresoc.v:191922$13300_Y - connect \$188 $reduce_or$libresoc.v:191923$13301_Y - connect \$192 $not$libresoc.v:191924$13302_Y - connect \$194 $not$libresoc.v:191925$13303_Y - connect \$196 $and$libresoc.v:191926$13304_Y - connect \$198 $not$libresoc.v:191927$13305_Y - connect \$200 $not$libresoc.v:191928$13306_Y - connect \$202 $and$libresoc.v:191929$13307_Y - connect \$204 $or$libresoc.v:191930$13308_Y - connect \$206 $or$libresoc.v:191931$13309_Y - connect \$208 1'0 - connect \$210 $not$libresoc.v:191933$13310_Y - connect \$212 $not$libresoc.v:191934$13311_Y - connect \$214 $and$libresoc.v:191935$13312_Y - connect \$216 $not$libresoc.v:191936$13313_Y - connect \$218 $not$libresoc.v:191937$13314_Y - connect \$220 $and$libresoc.v:191938$13315_Y - connect \$223 $and$libresoc.v:191939$13316_Y - connect \$222 $reduce_or$libresoc.v:191940$13317_Y - connect \$226 $not$libresoc.v:191941$13318_Y - connect \$228 $not$libresoc.v:191942$13319_Y - connect \$230 $and$libresoc.v:191943$13320_Y - connect \$232 $not$libresoc.v:191944$13321_Y - connect \$234 $not$libresoc.v:191945$13322_Y - connect \$236 $and$libresoc.v:191946$13323_Y - connect \$23 $ne$libresoc.v:191947$13324_Y - connect \$239 $add$libresoc.v:191948$13325_Y - connect \$241 $not$libresoc.v:191949$13326_Y - connect \$243 $not$libresoc.v:191950$13327_Y - connect \$245 $and$libresoc.v:191951$13328_Y - connect \$247 $eq$libresoc.v:191952$13329_Y - connect \$249 $pos$libresoc.v:191953$13330_Y - connect \$251 $ne$libresoc.v:191954$13331_Y - connect \$253 $not$libresoc.v:191955$13332_Y - connect \$255 $not$libresoc.v:191956$13333_Y - connect \$257 $pos$libresoc.v:191957$13335_Y - connect \$259 $pos$libresoc.v:191958$13337_Y - connect \$262 $sub$libresoc.v:191959$13338_Y - connect \$265 $add$libresoc.v:191960$13339_Y - connect \$26 $sub$libresoc.v:191961$13340_Y - connect \$28 $or$libresoc.v:191962$13341_Y - connect \$30 $or$libresoc.v:191963$13342_Y - connect \$32 $ne$libresoc.v:191964$13343_Y - connect \$34 $not$libresoc.v:191965$13344_Y - connect \$36 $and$libresoc.v:191966$13345_Y - connect \$38 $not$libresoc.v:191967$13346_Y - connect \$40 $not$libresoc.v:191968$13347_Y - connect \$42 $pos$libresoc.v:191969$13349_Y - connect \$44 $not$libresoc.v:191970$13350_Y - connect \$46 $not$libresoc.v:191971$13351_Y - connect \$48 $and$libresoc.v:191972$13352_Y - connect \$50 1'0 - connect \$52 $eq$libresoc.v:191974$13353_Y - connect \$54 $and$libresoc.v:191975$13354_Y - connect \$56 $not$libresoc.v:191976$13355_Y - connect \$58 $not$libresoc.v:191977$13356_Y - connect \$60 $and$libresoc.v:191978$13357_Y - connect \$62 $or$libresoc.v:191979$13358_Y - connect \$64 $or$libresoc.v:191980$13359_Y - connect \$66 $not$libresoc.v:191981$13360_Y - connect \$68 $not$libresoc.v:191982$13361_Y - connect \$70 $and$libresoc.v:191983$13362_Y - connect \$72 1'0 - connect \$74 $eq$libresoc.v:191985$13363_Y - connect \$76 $and$libresoc.v:191986$13364_Y - connect \$78 $not$libresoc.v:191987$13365_Y - connect \$80 $not$libresoc.v:191988$13366_Y - connect \$82 $and$libresoc.v:191989$13367_Y - connect \$84 $or$libresoc.v:191990$13368_Y - connect \$86 $or$libresoc.v:191991$13369_Y - connect \$88 $not$libresoc.v:191992$13370_Y - connect \$90 $not$libresoc.v:191993$13371_Y - connect \$93 $add$libresoc.v:191994$13372_Y - connect \$96 $mul$libresoc.v:191995$13373_Y - connect \$95 $shr$libresoc.v:191996$13374_Y [31:0] + assign $3\core_rego_ok$next[0:0]$14059 1'0 + assign $3\core_ea_ok$next[0:0]$14056 1'0 + assign $3\core_core_reg1_ok$next[0:0]$14051 1'0 + assign $3\core_core_reg2_ok$next[0:0]$14052 1'0 + assign $3\core_core_reg3_ok$next[0:0]$14053 1'0 + assign $3\core_spro_ok$next[0:0]$14060 1'0 + assign $3\core_core_spr1_ok$next[0:0]$14054 1'0 + assign $3\core_core_fast1_ok$next[0:0]$14049 1'0 + assign $3\core_core_fast2_ok$next[0:0]$14050 1'0 + assign $3\core_fasto1_ok$next[0:0]$14057 1'0 + assign $3\core_fasto2_ok$next[0:0]$14058 1'0 + assign $3\core_core_cr_in1_ok$next[0:0]$14045 1'0 + assign $3\core_core_cr_in2_ok$next[0:0]$14047 1'0 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14046 1'0 + assign $3\core_cr_out_ok$next[0:0]$14055 1'0 + assign $3\core_core_core_rc_ok$next[0:0]$14044 1'0 + assign $3\core_core_core_oe_ok$next[0:0]$14043 1'0 + assign $3\core_core_core_exc_$signal$next[0:0]$14042 1'0 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14035 1'0 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14036 1'0 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14037 1'0 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14038 1'0 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14039 1'0 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14040 1'0 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14041 1'0 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14034 1'0 + assign $3\core_core_cr_wr_ok$next[0:0]$14048 1'0 + case + assign $3\core_core_core_cr_rd_ok$next[0:0]$14034 $1\core_core_core_cr_rd_ok$next[0:0]$13919 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14035 $1\core_core_core_exc_$signal$3$next[0:0]$13921 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14036 $1\core_core_core_exc_$signal$4$next[0:0]$13922 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14037 $1\core_core_core_exc_$signal$5$next[0:0]$13923 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14038 $1\core_core_core_exc_$signal$6$next[0:0]$13924 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14039 $1\core_core_core_exc_$signal$7$next[0:0]$13925 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14040 $1\core_core_core_exc_$signal$8$next[0:0]$13926 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14041 $1\core_core_core_exc_$signal$9$next[0:0]$13927 + assign $3\core_core_core_exc_$signal$next[0:0]$14042 $1\core_core_core_exc_$signal$next[0:0]$13928 + assign $3\core_core_core_oe_ok$next[0:0]$14043 $1\core_core_core_oe_ok$next[0:0]$13936 + assign $3\core_core_core_rc_ok$next[0:0]$14044 $1\core_core_core_rc_ok$next[0:0]$13938 + assign $3\core_core_cr_in1_ok$next[0:0]$14045 $1\core_core_cr_in1_ok$next[0:0]$13942 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14046 $1\core_core_cr_in2_ok$2$next[0:0]$13945 + assign $3\core_core_cr_in2_ok$next[0:0]$14047 $1\core_core_cr_in2_ok$next[0:0]$13946 + assign $3\core_core_cr_wr_ok$next[0:0]$14048 $1\core_core_cr_wr_ok$next[0:0]$13948 + assign $3\core_core_fast1_ok$next[0:0]$14049 $1\core_core_fast1_ok$next[0:0]$13951 + assign $3\core_core_fast2_ok$next[0:0]$14050 $1\core_core_fast2_ok$next[0:0]$13953 + assign $3\core_core_reg1_ok$next[0:0]$14051 $1\core_core_reg1_ok$next[0:0]$13958 + assign $3\core_core_reg2_ok$next[0:0]$14052 $1\core_core_reg2_ok$next[0:0]$13960 + assign $3\core_core_reg3_ok$next[0:0]$14053 $1\core_core_reg3_ok$next[0:0]$13962 + assign $3\core_core_spr1_ok$next[0:0]$14054 $1\core_core_spr1_ok$next[0:0]$13965 + assign $3\core_cr_out_ok$next[0:0]$14055 $1\core_cr_out_ok$next[0:0]$13968 + assign $3\core_ea_ok$next[0:0]$14056 $1\core_ea_ok$next[0:0]$13969 + assign $3\core_fasto1_ok$next[0:0]$14057 $1\core_fasto1_ok$next[0:0]$13970 + assign $3\core_fasto2_ok$next[0:0]$14058 $1\core_fasto2_ok$next[0:0]$13971 + assign $3\core_rego_ok$next[0:0]$14059 $1\core_rego_ok$next[0:0]$13972 + assign $3\core_spro_ok$next[0:0]$14060 $1\core_spro_ok$next[0:0]$13973 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$13857 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13858 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13859 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13860 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13861 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13862 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13863 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13864 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13865 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13866 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13867 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13868 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13869 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13870 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13871 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13872 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13873 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13874 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13875 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13876 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13877 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13878 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13879 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13880 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13881 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13882 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13883 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13884 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13885 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13886 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13887 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13888 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13889 + update \core_core_ea$next $0\core_core_ea$next[6:0]$13890 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13891 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13892 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13893 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13894 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13895 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13896 + update \core_core_lk$next $0\core_core_lk$next[0:0]$13897 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13898 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13899 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13900 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13901 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13902 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13903 + update \core_core_rego$next $0\core_core_rego$next[6:0]$13904 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13905 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13906 + update \core_core_spro$next $0\core_core_spro$next[9:0]$13907 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13908 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13909 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13910 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13911 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13912 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13913 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13914 + update \core_xer_out$next $0\core_xer_out$next[0:0]$13915 + end + connect \$101 $add$libresoc.v:194791$13361_Y + connect \$103 $mul$libresoc.v:194792$13362_Y + connect \$99 $shr$libresoc.v:194793$13363_Y [31:0] + connect \$106 $not$libresoc.v:194794$13364_Y + connect \$108 $not$libresoc.v:194795$13365_Y + connect \$110 $and$libresoc.v:194796$13366_Y + connect \$112 $not$libresoc.v:194797$13367_Y + connect \$114 $not$libresoc.v:194798$13368_Y + connect \$116 $and$libresoc.v:194799$13369_Y + connect \$118 $or$libresoc.v:194800$13370_Y + connect \$120 1'1 + connect \$122 $or$libresoc.v:194802$13371_Y + connect \$124 $not$libresoc.v:194803$13372_Y + connect \$126 $not$libresoc.v:194804$13373_Y + connect \$128 $and$libresoc.v:194805$13374_Y + connect \$130 $not$libresoc.v:194806$13375_Y + connect \$132 $not$libresoc.v:194807$13376_Y + connect \$134 $and$libresoc.v:194808$13377_Y + connect \$136 $eq$libresoc.v:194809$13378_Y + connect \$138 $and$libresoc.v:194810$13379_Y + connect \$140 $not$libresoc.v:194811$13380_Y + connect \$142 $not$libresoc.v:194812$13381_Y + connect \$144 $and$libresoc.v:194813$13382_Y + connect \$146 $or$libresoc.v:194814$13383_Y + connect \$148 1'1 + connect \$150 $or$libresoc.v:194816$13384_Y + connect \$152 $not$libresoc.v:194817$13385_Y + connect \$154 $not$libresoc.v:194818$13386_Y + connect \$156 $and$libresoc.v:194819$13387_Y + connect \$158 $not$libresoc.v:194820$13388_Y + connect \$160 $not$libresoc.v:194821$13389_Y + connect \$162 $and$libresoc.v:194822$13390_Y + connect \$164 $not$libresoc.v:194823$13391_Y + connect \$166 $not$libresoc.v:194824$13392_Y + connect \$168 $and$libresoc.v:194825$13393_Y + connect \$170 $not$libresoc.v:194826$13394_Y + connect \$172 $not$libresoc.v:194827$13395_Y + connect \$174 $and$libresoc.v:194828$13396_Y + connect \$176 $not$libresoc.v:194829$13397_Y + connect \$178 $not$libresoc.v:194830$13398_Y + connect \$180 $and$libresoc.v:194831$13399_Y + connect \$182 $not$libresoc.v:194832$13400_Y + connect \$184 $not$libresoc.v:194833$13401_Y + connect \$186 $and$libresoc.v:194834$13402_Y + connect \$189 $and$libresoc.v:194835$13403_Y + connect \$188 $reduce_or$libresoc.v:194836$13404_Y + connect \$192 $not$libresoc.v:194837$13405_Y + connect \$194 $not$libresoc.v:194838$13406_Y + connect \$196 $and$libresoc.v:194839$13407_Y + connect \$198 $not$libresoc.v:194840$13408_Y + connect \$200 $not$libresoc.v:194841$13409_Y + connect \$202 $and$libresoc.v:194842$13410_Y + connect \$204 $or$libresoc.v:194843$13411_Y + connect \$206 1'1 + connect \$208 $or$libresoc.v:194845$13412_Y + connect \$210 $not$libresoc.v:194846$13413_Y + connect \$212 $not$libresoc.v:194847$13414_Y + connect \$214 $and$libresoc.v:194848$13415_Y + connect \$216 $not$libresoc.v:194849$13416_Y + connect \$218 $not$libresoc.v:194850$13417_Y + connect \$220 $and$libresoc.v:194851$13418_Y + connect \$223 $and$libresoc.v:194852$13419_Y + connect \$222 $reduce_or$libresoc.v:194853$13420_Y + connect \$226 $eq$libresoc.v:194854$13421_Y + connect \$228 $and$libresoc.v:194855$13422_Y + connect \$230 $not$libresoc.v:194856$13423_Y + connect \$232 $not$libresoc.v:194857$13424_Y + connect \$234 $not$libresoc.v:194858$13425_Y + connect \$236 $and$libresoc.v:194859$13426_Y + connect \$238 $not$libresoc.v:194860$13427_Y + connect \$23 $ne$libresoc.v:194861$13428_Y + connect \$240 $not$libresoc.v:194862$13429_Y + connect \$242 $and$libresoc.v:194863$13430_Y + connect \$245 $add$libresoc.v:194864$13431_Y + connect \$247 $not$libresoc.v:194865$13432_Y + connect \$249 $not$libresoc.v:194866$13433_Y + connect \$251 $and$libresoc.v:194867$13434_Y + connect \$253 $eq$libresoc.v:194868$13435_Y + connect \$255 $pos$libresoc.v:194869$13436_Y + connect \$257 $ne$libresoc.v:194870$13437_Y + connect \$259 $not$libresoc.v:194871$13438_Y + connect \$261 $not$libresoc.v:194872$13439_Y + connect \$263 $pos$libresoc.v:194873$13441_Y + connect \$265 $pos$libresoc.v:194874$13443_Y + connect \$268 $sub$libresoc.v:194875$13444_Y + connect \$26 $sub$libresoc.v:194876$13445_Y + connect \$271 $add$libresoc.v:194877$13446_Y + connect \$28 $or$libresoc.v:194878$13447_Y + connect \$30 $or$libresoc.v:194879$13448_Y + connect \$32 $ne$libresoc.v:194880$13449_Y + connect \$34 $not$libresoc.v:194881$13450_Y + connect \$36 $and$libresoc.v:194882$13451_Y + connect \$38 $not$libresoc.v:194883$13452_Y + connect \$40 $not$libresoc.v:194884$13453_Y + connect \$42 $pos$libresoc.v:194885$13455_Y + connect \$44 $not$libresoc.v:194886$13456_Y + connect \$46 $not$libresoc.v:194887$13457_Y + connect \$48 $and$libresoc.v:194888$13458_Y + connect \$50 $eq$libresoc.v:194889$13459_Y + connect \$52 $and$libresoc.v:194890$13460_Y + connect \$54 $not$libresoc.v:194891$13461_Y + connect \$56 $not$libresoc.v:194892$13462_Y + connect \$58 $and$libresoc.v:194893$13463_Y + connect \$60 $or$libresoc.v:194894$13464_Y + connect \$62 1'1 + connect \$64 $or$libresoc.v:194896$13465_Y + connect \$66 $not$libresoc.v:194897$13466_Y + connect \$68 $not$libresoc.v:194898$13467_Y + connect \$70 $and$libresoc.v:194899$13468_Y + connect \$72 $eq$libresoc.v:194900$13469_Y + connect \$74 $and$libresoc.v:194901$13470_Y + connect \$76 $not$libresoc.v:194902$13471_Y + connect \$78 $not$libresoc.v:194903$13472_Y + connect \$80 $and$libresoc.v:194904$13473_Y + connect \$82 $or$libresoc.v:194905$13474_Y + connect \$84 1'1 + connect \$86 $or$libresoc.v:194907$13475_Y + connect \$88 $not$libresoc.v:194908$13476_Y + connect \$90 $not$libresoc.v:194909$13477_Y + connect \$93 $add$libresoc.v:194910$13478_Y + connect \$96 $mul$libresoc.v:194911$13479_Y + connect \$95 $shr$libresoc.v:194912$13480_Y [31:0] connect \$25 \$26 connect \$92 \$93 connect \$100 \$101 - connect \$238 \$239 - connect \$261 \$262 - connect \$264 \$265 + connect \$244 \$245 + connect \$267 \$268 + connect \$270 \$271 + connect \dec2_sv_a_nz 1'0 connect \svstate_i_ok 1'0 connect \svstate_i 0 + connect \is_svp64_mode 1'0 connect \dbg_core_dbg_msr \dec2_cur_msr connect { \dbg_core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_svstep } \svstate [31:0] connect \dbg_core_dbg_pc \pc @@ -408026,486 +412676,490 @@ module \ti connect \ti_rst \$32 connect \por_clk \clk connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } + connect \sram4k_3_enable \jtag_wb_sram_en + connect \sram4k_2_enable \jtag_wb_sram_en + connect \sram4k_1_enable \jtag_wb_sram_en + connect \sram4k_0_enable \jtag_wb_sram_en end -attribute \src "libresoc.v:194517.1-195704.10" +attribute \src "libresoc.v:197549.1-198740.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:195249.3-195250.25" + attribute \src "libresoc.v:198285.3-198286.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:195247.3-195248.41" + attribute \src "libresoc.v:198283.3-198284.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:195607.3-195615.6" - wire $0\alu_l_r_alu$next[0:0]$14268 - attribute \src "libresoc.v:195175.3-195176.39" + attribute \src "libresoc.v:198643.3-198651.6" + wire $0\alu_l_r_alu$next[0:0]$14382 + attribute \src "libresoc.v:198211.3-198212.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14194 - attribute \src "libresoc.v:195215.3-195216.61" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14308 + attribute \src "libresoc.v:198251.3-198252.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 13 $0\alu_trap0_trap_op__fn_unit$next[12:0]$14195 - attribute \src "libresoc.v:195209.3-195210.69" - wire width 13 $0\alu_trap0_trap_op__fn_unit[12:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14196 - attribute \src "libresoc.v:195211.3-195212.63" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 + attribute \src "libresoc.v:198245.3-198246.69" + wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] + attribute \src "libresoc.v:198466.3-198483.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14310 + attribute \src "libresoc.v:198247.3-198248.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14197 - attribute \src "libresoc.v:195207.3-195208.73" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 + attribute \src "libresoc.v:198243.3-198244.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14198 - attribute \src "libresoc.v:195217.3-195218.71" + attribute \src "libresoc.v:198466.3-198483.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 + attribute \src "libresoc.v:198253.3-198254.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14199 - attribute \src "libresoc.v:195223.3-195224.71" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 + attribute \src "libresoc.v:198259.3-198260.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14200 - attribute \src "libresoc.v:195213.3-195214.61" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14314 + attribute \src "libresoc.v:198249.3-198250.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14201 - attribute \src "libresoc.v:195221.3-195222.71" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 + attribute \src "libresoc.v:198257.3-198258.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14202 - attribute \src "libresoc.v:195219.3-195220.71" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14316 + attribute \src "libresoc.v:198255.3-198256.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:195598.3-195606.6" - wire $0\alui_l_r_alui$next[0:0]$14265 - attribute \src "libresoc.v:195177.3-195178.43" + attribute \src "libresoc.v:198634.3-198642.6" + wire $0\alui_l_r_alui$next[0:0]$14379 + attribute \src "libresoc.v:198213.3-198214.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:195448.3-195469.6" - wire width 64 $0\data_r0__o$next[63:0]$14213 - attribute \src "libresoc.v:195203.3-195204.37" + attribute \src "libresoc.v:198484.3-198505.6" + wire width 64 $0\data_r0__o$next[63:0]$14327 + attribute \src "libresoc.v:198239.3-198240.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:195448.3-195469.6" - wire $0\data_r0__o_ok$next[0:0]$14214 - attribute \src "libresoc.v:195205.3-195206.43" + attribute \src "libresoc.v:198484.3-198505.6" + wire $0\data_r0__o_ok$next[0:0]$14328 + attribute \src "libresoc.v:198241.3-198242.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:195470.3-195491.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14221 - attribute \src "libresoc.v:195199.3-195200.45" + attribute \src "libresoc.v:198506.3-198527.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14335 + attribute \src "libresoc.v:198235.3-198236.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:195470.3-195491.6" - wire $0\data_r1__fast1_ok$next[0:0]$14222 - attribute \src "libresoc.v:195201.3-195202.51" + attribute \src "libresoc.v:198506.3-198527.6" + wire $0\data_r1__fast1_ok$next[0:0]$14336 + attribute \src "libresoc.v:198237.3-198238.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:195492.3-195513.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14229 - attribute \src "libresoc.v:195195.3-195196.45" + attribute \src "libresoc.v:198528.3-198549.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14343 + attribute \src "libresoc.v:198231.3-198232.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:195492.3-195513.6" - wire $0\data_r2__fast2_ok$next[0:0]$14230 - attribute \src "libresoc.v:195197.3-195198.51" + attribute \src "libresoc.v:198528.3-198549.6" + wire $0\data_r2__fast2_ok$next[0:0]$14344 + attribute \src "libresoc.v:198233.3-198234.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:195514.3-195535.6" - wire width 64 $0\data_r3__nia$next[63:0]$14237 - attribute \src "libresoc.v:195191.3-195192.41" + attribute \src "libresoc.v:198550.3-198571.6" + wire width 64 $0\data_r3__nia$next[63:0]$14351 + attribute \src "libresoc.v:198227.3-198228.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:195514.3-195535.6" - wire $0\data_r3__nia_ok$next[0:0]$14238 - attribute \src "libresoc.v:195193.3-195194.47" + attribute \src "libresoc.v:198550.3-198571.6" + wire $0\data_r3__nia_ok$next[0:0]$14352 + attribute \src "libresoc.v:198229.3-198230.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:195536.3-195557.6" - wire width 64 $0\data_r4__msr$next[63:0]$14245 - attribute \src "libresoc.v:195187.3-195188.41" + attribute \src "libresoc.v:198572.3-198593.6" + wire width 64 $0\data_r4__msr$next[63:0]$14359 + attribute \src "libresoc.v:198223.3-198224.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:195536.3-195557.6" - wire $0\data_r4__msr_ok$next[0:0]$14246 - attribute \src "libresoc.v:195189.3-195190.47" + attribute \src "libresoc.v:198572.3-198593.6" + wire $0\data_r4__msr_ok$next[0:0]$14360 + attribute \src "libresoc.v:198225.3-198226.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:195616.3-195625.6" + attribute \src "libresoc.v:198652.3-198661.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:195626.3-195635.6" + attribute \src "libresoc.v:198662.3-198671.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:195636.3-195645.6" + attribute \src "libresoc.v:198672.3-198681.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:195646.3-195655.6" + attribute \src "libresoc.v:198682.3-198691.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:195656.3-195665.6" + attribute \src "libresoc.v:198692.3-198701.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:194518.7-194518.20" + attribute \src "libresoc.v:197550.7-197550.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195385.3-195393.6" - wire $0\opc_l_r_opc$next[0:0]$14179 - attribute \src "libresoc.v:195233.3-195234.39" + attribute \src "libresoc.v:198421.3-198429.6" + wire $0\opc_l_r_opc$next[0:0]$14293 + attribute \src "libresoc.v:198269.3-198270.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:195376.3-195384.6" - wire $0\opc_l_s_opc$next[0:0]$14176 - attribute \src "libresoc.v:195235.3-195236.39" + attribute \src "libresoc.v:198412.3-198420.6" + wire $0\opc_l_s_opc$next[0:0]$14290 + attribute \src "libresoc.v:198271.3-198272.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:195666.3-195674.6" - wire width 5 $0\prev_wr_go$next[4:0]$14276 - attribute \src "libresoc.v:195245.3-195246.37" + attribute \src "libresoc.v:198702.3-198710.6" + wire width 5 $0\prev_wr_go$next[4:0]$14390 + attribute \src "libresoc.v:198281.3-198282.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:195330.3-195339.6" + attribute \src "libresoc.v:198366.3-198375.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:195421.3-195429.6" - wire width 5 $0\req_l_r_req$next[4:0]$14191 - attribute \src "libresoc.v:195225.3-195226.39" + attribute \src "libresoc.v:198457.3-198465.6" + wire width 5 $0\req_l_r_req$next[4:0]$14305 + attribute \src "libresoc.v:198261.3-198262.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:195412.3-195420.6" - wire width 5 $0\req_l_s_req$next[4:0]$14188 - attribute \src "libresoc.v:195227.3-195228.39" + attribute \src "libresoc.v:198448.3-198456.6" + wire width 5 $0\req_l_s_req$next[4:0]$14302 + attribute \src "libresoc.v:198263.3-198264.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:195349.3-195357.6" - wire $0\rok_l_r_rdok$next[0:0]$14167 - attribute \src "libresoc.v:195241.3-195242.41" + attribute \src "libresoc.v:198385.3-198393.6" + wire $0\rok_l_r_rdok$next[0:0]$14281 + attribute \src "libresoc.v:198277.3-198278.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:195340.3-195348.6" - wire $0\rok_l_s_rdok$next[0:0]$14164 - attribute \src "libresoc.v:195243.3-195244.41" + attribute \src "libresoc.v:198376.3-198384.6" + wire $0\rok_l_s_rdok$next[0:0]$14278 + attribute \src "libresoc.v:198279.3-198280.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:195367.3-195375.6" - wire $0\rst_l_r_rst$next[0:0]$14173 - attribute \src "libresoc.v:195237.3-195238.39" + attribute \src "libresoc.v:198403.3-198411.6" + wire $0\rst_l_r_rst$next[0:0]$14287 + attribute \src "libresoc.v:198273.3-198274.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:195358.3-195366.6" - wire $0\rst_l_s_rst$next[0:0]$14170 - attribute \src "libresoc.v:195239.3-195240.39" + attribute \src "libresoc.v:198394.3-198402.6" + wire $0\rst_l_s_rst$next[0:0]$14284 + attribute \src "libresoc.v:198275.3-198276.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:195403.3-195411.6" - wire width 4 $0\src_l_r_src$next[3:0]$14185 - attribute \src "libresoc.v:195229.3-195230.39" + attribute \src "libresoc.v:198439.3-198447.6" + wire width 4 $0\src_l_r_src$next[3:0]$14299 + attribute \src "libresoc.v:198265.3-198266.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:195394.3-195402.6" - wire width 4 $0\src_l_s_src$next[3:0]$14182 - attribute \src "libresoc.v:195231.3-195232.39" + attribute \src "libresoc.v:198430.3-198438.6" + wire width 4 $0\src_l_s_src$next[3:0]$14296 + attribute \src "libresoc.v:198267.3-198268.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:195558.3-195567.6" - wire width 64 $0\src_r0$next[63:0]$14253 - attribute \src "libresoc.v:195185.3-195186.29" + attribute \src "libresoc.v:198594.3-198603.6" + wire width 64 $0\src_r0$next[63:0]$14367 + attribute \src "libresoc.v:198221.3-198222.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:195568.3-195577.6" - wire width 64 $0\src_r1$next[63:0]$14256 - attribute \src "libresoc.v:195183.3-195184.29" + attribute \src "libresoc.v:198604.3-198613.6" + wire width 64 $0\src_r1$next[63:0]$14370 + attribute \src "libresoc.v:198219.3-198220.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:195578.3-195587.6" - wire width 64 $0\src_r2$next[63:0]$14259 - attribute \src "libresoc.v:195181.3-195182.29" + attribute \src "libresoc.v:198614.3-198623.6" + wire width 64 $0\src_r2$next[63:0]$14373 + attribute \src "libresoc.v:198217.3-198218.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:195588.3-195597.6" - wire width 64 $0\src_r3$next[63:0]$14262 - attribute \src "libresoc.v:195179.3-195180.29" + attribute \src "libresoc.v:198624.3-198633.6" + wire width 64 $0\src_r3$next[63:0]$14376 + attribute \src "libresoc.v:198215.3-198216.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:194644.7-194644.24" + attribute \src "libresoc.v:197676.7-197676.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:194654.7-194654.26" + attribute \src "libresoc.v:197686.7-197686.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:195607.3-195615.6" - wire $1\alu_l_r_alu$next[0:0]$14269 - attribute \src "libresoc.v:194662.7-194662.25" + attribute \src "libresoc.v:198643.3-198651.6" + wire $1\alu_l_r_alu$next[0:0]$14383 + attribute \src "libresoc.v:197694.7-197694.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14203 - attribute \src "libresoc.v:194698.14-194698.59" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14317 + attribute \src "libresoc.v:197730.14-197730.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 13 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14204 - attribute \src "libresoc.v:194716.14-194716.51" - wire width 13 $1\alu_trap0_trap_op__fn_unit[12:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14205 - attribute \src "libresoc.v:194720.14-194720.45" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 + attribute \src "libresoc.v:197749.14-197749.51" + wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] + attribute \src "libresoc.v:198466.3-198483.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14319 + attribute \src "libresoc.v:197753.14-197753.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14206 - attribute \src "libresoc.v:194798.13-194798.49" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 + attribute \src "libresoc.v:197832.13-197832.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14207 - attribute \src "libresoc.v:194802.7-194802.41" + attribute \src "libresoc.v:198466.3-198483.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 + attribute \src "libresoc.v:197836.7-197836.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14208 - attribute \src "libresoc.v:194806.13-194806.48" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 + attribute \src "libresoc.v:197840.13-197840.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14209 - attribute \src "libresoc.v:194810.14-194810.59" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14323 + attribute \src "libresoc.v:197844.14-197844.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14210 - attribute \src "libresoc.v:194814.14-194814.52" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 + attribute \src "libresoc.v:197848.14-197848.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:195430.3-195447.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14211 - attribute \src "libresoc.v:194818.13-194818.48" + attribute \src "libresoc.v:198466.3-198483.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 + attribute \src "libresoc.v:197852.13-197852.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:195598.3-195606.6" - wire $1\alui_l_r_alui$next[0:0]$14266 - attribute \src "libresoc.v:194824.7-194824.27" + attribute \src "libresoc.v:198634.3-198642.6" + wire $1\alui_l_r_alui$next[0:0]$14380 + attribute \src "libresoc.v:197858.7-197858.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:195448.3-195469.6" - wire width 64 $1\data_r0__o$next[63:0]$14215 - attribute \src "libresoc.v:194856.14-194856.47" + attribute \src "libresoc.v:198484.3-198505.6" + wire width 64 $1\data_r0__o$next[63:0]$14329 + attribute \src "libresoc.v:197890.14-197890.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:195448.3-195469.6" - wire $1\data_r0__o_ok$next[0:0]$14216 - attribute \src "libresoc.v:194860.7-194860.27" + attribute \src "libresoc.v:198484.3-198505.6" + wire $1\data_r0__o_ok$next[0:0]$14330 + attribute \src "libresoc.v:197894.7-197894.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:195470.3-195491.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14223 - attribute \src "libresoc.v:194864.14-194864.51" + attribute \src "libresoc.v:198506.3-198527.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14337 + attribute \src "libresoc.v:197898.14-197898.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:195470.3-195491.6" - wire $1\data_r1__fast1_ok$next[0:0]$14224 - attribute \src "libresoc.v:194868.7-194868.31" + attribute \src "libresoc.v:198506.3-198527.6" + wire $1\data_r1__fast1_ok$next[0:0]$14338 + attribute \src "libresoc.v:197902.7-197902.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:195492.3-195513.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14231 - attribute \src "libresoc.v:194872.14-194872.51" + attribute \src "libresoc.v:198528.3-198549.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14345 + attribute \src "libresoc.v:197906.14-197906.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:195492.3-195513.6" - wire $1\data_r2__fast2_ok$next[0:0]$14232 - attribute \src "libresoc.v:194876.7-194876.31" + attribute \src "libresoc.v:198528.3-198549.6" + wire $1\data_r2__fast2_ok$next[0:0]$14346 + attribute \src "libresoc.v:197910.7-197910.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:195514.3-195535.6" - wire width 64 $1\data_r3__nia$next[63:0]$14239 - attribute \src "libresoc.v:194880.14-194880.49" + attribute \src "libresoc.v:198550.3-198571.6" + wire width 64 $1\data_r3__nia$next[63:0]$14353 + attribute \src "libresoc.v:197914.14-197914.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:195514.3-195535.6" - wire $1\data_r3__nia_ok$next[0:0]$14240 - attribute \src "libresoc.v:194884.7-194884.29" + attribute \src "libresoc.v:198550.3-198571.6" + wire $1\data_r3__nia_ok$next[0:0]$14354 + attribute \src "libresoc.v:197918.7-197918.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:195536.3-195557.6" - wire width 64 $1\data_r4__msr$next[63:0]$14247 - attribute \src "libresoc.v:194888.14-194888.49" + attribute \src "libresoc.v:198572.3-198593.6" + wire width 64 $1\data_r4__msr$next[63:0]$14361 + attribute \src "libresoc.v:197922.14-197922.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:195536.3-195557.6" - wire $1\data_r4__msr_ok$next[0:0]$14248 - attribute \src "libresoc.v:194892.7-194892.29" + attribute \src "libresoc.v:198572.3-198593.6" + wire $1\data_r4__msr_ok$next[0:0]$14362 + attribute \src "libresoc.v:197926.7-197926.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:195616.3-195625.6" + attribute \src "libresoc.v:198652.3-198661.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:195626.3-195635.6" + attribute \src "libresoc.v:198662.3-198671.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:195636.3-195645.6" + attribute \src "libresoc.v:198672.3-198681.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:195646.3-195655.6" + attribute \src "libresoc.v:198682.3-198691.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:195656.3-195665.6" + attribute \src "libresoc.v:198692.3-198701.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:195385.3-195393.6" - wire $1\opc_l_r_opc$next[0:0]$14180 - attribute \src "libresoc.v:194923.7-194923.25" + attribute \src "libresoc.v:198421.3-198429.6" + wire $1\opc_l_r_opc$next[0:0]$14294 + attribute \src "libresoc.v:197957.7-197957.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:195376.3-195384.6" - wire $1\opc_l_s_opc$next[0:0]$14177 - attribute \src "libresoc.v:194927.7-194927.25" + attribute \src "libresoc.v:198412.3-198420.6" + wire $1\opc_l_s_opc$next[0:0]$14291 + attribute \src "libresoc.v:197961.7-197961.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:195666.3-195674.6" - wire width 5 $1\prev_wr_go$next[4:0]$14277 - attribute \src "libresoc.v:195037.13-195037.31" + attribute \src "libresoc.v:198702.3-198710.6" + wire width 5 $1\prev_wr_go$next[4:0]$14391 + attribute \src "libresoc.v:198073.13-198073.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:195330.3-195339.6" + attribute \src "libresoc.v:198366.3-198375.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:195421.3-195429.6" - wire width 5 $1\req_l_r_req$next[4:0]$14192 - attribute \src "libresoc.v:195045.13-195045.32" + attribute \src "libresoc.v:198457.3-198465.6" + wire width 5 $1\req_l_r_req$next[4:0]$14306 + attribute \src "libresoc.v:198081.13-198081.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:195412.3-195420.6" - wire width 5 $1\req_l_s_req$next[4:0]$14189 - attribute \src "libresoc.v:195049.13-195049.32" + attribute \src "libresoc.v:198448.3-198456.6" + wire width 5 $1\req_l_s_req$next[4:0]$14303 + attribute \src "libresoc.v:198085.13-198085.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:195349.3-195357.6" - wire $1\rok_l_r_rdok$next[0:0]$14168 - attribute \src "libresoc.v:195061.7-195061.26" + attribute \src "libresoc.v:198385.3-198393.6" + wire $1\rok_l_r_rdok$next[0:0]$14282 + attribute \src "libresoc.v:198097.7-198097.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:195340.3-195348.6" - wire $1\rok_l_s_rdok$next[0:0]$14165 - attribute \src "libresoc.v:195065.7-195065.26" + attribute \src "libresoc.v:198376.3-198384.6" + wire $1\rok_l_s_rdok$next[0:0]$14279 + attribute \src "libresoc.v:198101.7-198101.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:195367.3-195375.6" - wire $1\rst_l_r_rst$next[0:0]$14174 - attribute \src "libresoc.v:195069.7-195069.25" + attribute \src "libresoc.v:198403.3-198411.6" + wire $1\rst_l_r_rst$next[0:0]$14288 + attribute \src "libresoc.v:198105.7-198105.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:195358.3-195366.6" - wire $1\rst_l_s_rst$next[0:0]$14171 - attribute \src "libresoc.v:195073.7-195073.25" + attribute \src "libresoc.v:198394.3-198402.6" + wire $1\rst_l_s_rst$next[0:0]$14285 + attribute \src "libresoc.v:198109.7-198109.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:195403.3-195411.6" - wire width 4 $1\src_l_r_src$next[3:0]$14186 - attribute \src "libresoc.v:195089.13-195089.31" + attribute \src "libresoc.v:198439.3-198447.6" + wire width 4 $1\src_l_r_src$next[3:0]$14300 + attribute \src "libresoc.v:198125.13-198125.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:195394.3-195402.6" - wire width 4 $1\src_l_s_src$next[3:0]$14183 - attribute \src "libresoc.v:195093.13-195093.31" + attribute \src "libresoc.v:198430.3-198438.6" + wire width 4 $1\src_l_s_src$next[3:0]$14297 + attribute \src "libresoc.v:198129.13-198129.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:195558.3-195567.6" - wire width 64 $1\src_r0$next[63:0]$14254 - attribute \src "libresoc.v:195097.14-195097.43" + attribute \src "libresoc.v:198594.3-198603.6" + wire width 64 $1\src_r0$next[63:0]$14368 + attribute \src "libresoc.v:198133.14-198133.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:195568.3-195577.6" - wire width 64 $1\src_r1$next[63:0]$14257 - attribute \src "libresoc.v:195101.14-195101.43" + attribute \src "libresoc.v:198604.3-198613.6" + wire width 64 $1\src_r1$next[63:0]$14371 + attribute \src "libresoc.v:198137.14-198137.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:195578.3-195587.6" - wire width 64 $1\src_r2$next[63:0]$14260 - attribute \src "libresoc.v:195105.14-195105.43" + attribute \src "libresoc.v:198614.3-198623.6" + wire width 64 $1\src_r2$next[63:0]$14374 + attribute \src "libresoc.v:198141.14-198141.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:195588.3-195597.6" - wire width 64 $1\src_r3$next[63:0]$14263 - attribute \src "libresoc.v:195109.14-195109.43" + attribute \src "libresoc.v:198624.3-198633.6" + wire width 64 $1\src_r3$next[63:0]$14377 + attribute \src "libresoc.v:198145.14-198145.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:195448.3-195469.6" - wire width 64 $2\data_r0__o$next[63:0]$14217 - attribute \src "libresoc.v:195448.3-195469.6" - wire $2\data_r0__o_ok$next[0:0]$14218 - attribute \src "libresoc.v:195470.3-195491.6" - wire width 64 $2\data_r1__fast1$next[63:0]$14225 - attribute \src "libresoc.v:195470.3-195491.6" - wire $2\data_r1__fast1_ok$next[0:0]$14226 - attribute \src "libresoc.v:195492.3-195513.6" - wire width 64 $2\data_r2__fast2$next[63:0]$14233 - attribute \src "libresoc.v:195492.3-195513.6" - wire $2\data_r2__fast2_ok$next[0:0]$14234 - attribute \src "libresoc.v:195514.3-195535.6" - wire width 64 $2\data_r3__nia$next[63:0]$14241 - attribute \src "libresoc.v:195514.3-195535.6" - wire $2\data_r3__nia_ok$next[0:0]$14242 - attribute \src "libresoc.v:195536.3-195557.6" - wire width 64 $2\data_r4__msr$next[63:0]$14249 - attribute \src "libresoc.v:195536.3-195557.6" - wire $2\data_r4__msr_ok$next[0:0]$14250 - attribute \src "libresoc.v:195448.3-195469.6" - wire $3\data_r0__o_ok$next[0:0]$14219 - attribute \src "libresoc.v:195470.3-195491.6" - wire $3\data_r1__fast1_ok$next[0:0]$14227 - attribute \src "libresoc.v:195492.3-195513.6" - wire $3\data_r2__fast2_ok$next[0:0]$14235 - attribute \src "libresoc.v:195514.3-195535.6" - wire $3\data_r3__nia_ok$next[0:0]$14243 - attribute \src "libresoc.v:195536.3-195557.6" - wire $3\data_r4__msr_ok$next[0:0]$14251 - attribute \src "libresoc.v:195115.18-195115.112" - wire width 4 $and$libresoc.v:195115$14064_Y - attribute \src "libresoc.v:195116.19-195116.125" - wire $and$libresoc.v:195116$14065_Y - attribute \src "libresoc.v:195117.19-195117.125" - wire $and$libresoc.v:195117$14066_Y - attribute \src "libresoc.v:195118.19-195118.125" - wire $and$libresoc.v:195118$14067_Y - attribute \src "libresoc.v:195119.19-195119.125" - wire $and$libresoc.v:195119$14068_Y - attribute \src "libresoc.v:195120.19-195120.125" - wire $and$libresoc.v:195120$14069_Y - attribute \src "libresoc.v:195121.19-195121.157" - wire width 5 $and$libresoc.v:195121$14070_Y - attribute \src "libresoc.v:195122.19-195122.121" - wire width 5 $and$libresoc.v:195122$14071_Y - attribute \src "libresoc.v:195123.19-195123.127" - wire $and$libresoc.v:195123$14072_Y - attribute \src "libresoc.v:195124.19-195124.127" - wire $and$libresoc.v:195124$14073_Y - attribute \src "libresoc.v:195125.18-195125.110" - wire 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$not$libresoc.v:198173$14200_Y + attribute \src "libresoc.v:198179.18-198179.121" + wire $not$libresoc.v:198179$14206_Y + attribute \src "libresoc.v:198194.17-198194.113" + wire width 4 $not$libresoc.v:198194$14221_Y + attribute \src "libresoc.v:198210.18-198210.114" + wire width 4 $not$libresoc.v:198210$14237_Y + attribute \src "libresoc.v:198177.18-198177.112" + wire $or$libresoc.v:198177$14204_Y + attribute \src "libresoc.v:198188.18-198188.122" + wire $or$libresoc.v:198188$14215_Y + attribute \src "libresoc.v:198189.18-198189.124" + wire $or$libresoc.v:198189$14216_Y + attribute \src "libresoc.v:198190.18-198190.181" + wire width 5 $or$libresoc.v:198190$14217_Y + attribute \src "libresoc.v:198191.18-198191.168" + wire width 4 $or$libresoc.v:198191$14218_Y + attribute \src "libresoc.v:198195.18-198195.120" + wire width 5 $or$libresoc.v:198195$14222_Y + attribute \src "libresoc.v:198205.17-198205.117" + wire width 4 $or$libresoc.v:198205$14232_Y + attribute \src "libresoc.v:198150.17-198150.104" + wire $reduce_and$libresoc.v:198150$14177_Y + attribute \src "libresoc.v:198172.18-198172.106" + wire $reduce_or$libresoc.v:198172$14199_Y + attribute \src "libresoc.v:198175.18-198175.113" + wire $reduce_or$libresoc.v:198175$14202_Y + attribute \src "libresoc.v:198176.18-198176.112" + wire $reduce_or$libresoc.v:198176$14203_Y + attribute \src "libresoc.v:198201.18-198201.118" + wire width 64 $ternary$libresoc.v:198201$14228_Y + attribute \src "libresoc.v:198202.18-198202.118" + wire width 64 $ternary$libresoc.v:198202$14229_Y + attribute \src "libresoc.v:198203.18-198203.118" + wire width 64 $ternary$libresoc.v:198203$14230_Y + attribute \src "libresoc.v:198204.18-198204.118" + wire width 64 $ternary$libresoc.v:198204$14231_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -408689,23 +413343,24 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_trap0_trap_op__cia$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__fn_unit$next + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_trap0_trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 \alu_trap0_trap_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_trap0_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -408784,6 +413439,7 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_trap0_trap_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -408816,9 +413472,9 @@ module \trap0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o @@ -408896,7 +413552,7 @@ module \trap0 wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \fast2_ok - attribute \src "libresoc.v:194518.7-194518.15" + attribute \src "libresoc.v:197550.7-197550.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \msr_ok @@ -408917,21 +413573,22 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 6 \oper_i_alu_trap0__cia attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_trap0__fn_unit + attribute \enum_value_00000000000000 "NONE" + attribute \enum_value_00000000000010 "ALU" + attribute \enum_value_00000000000100 "LDST" + attribute \enum_value_00000000001000 "SHIFT_ROT" + attribute \enum_value_00000000010000 "LOGICAL" + attribute \enum_value_00000000100000 "BRANCH" + attribute \enum_value_00000001000000 "CR" + attribute \enum_value_00000010000000 "TRAP" + attribute \enum_value_00000100000000 "MUL" + attribute \enum_value_00001000000000 "DIV" + attribute \enum_value_00010000000000 "SPR" + attribute \enum_value_00100000000000 "MMU" + attribute \enum_value_01000000000000 "SV" + attribute \enum_value_10000000000000 "VL" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 14 input 3 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" @@ -409008,6 +413665,7 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" + attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -409099,7 +413757,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:195115$14064 + cell $and $and$libresoc.v:198151$14178 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -409107,10 +413765,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:195115$14064_Y + connect \Y $and$libresoc.v:198151$14178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:195116$14065 + cell $and $and$libresoc.v:198152$14179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409118,10 +413776,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:195116$14065_Y + connect \Y $and$libresoc.v:198152$14179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:195117$14066 + cell $and $and$libresoc.v:198153$14180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409129,10 +413787,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:195117$14066_Y + connect \Y $and$libresoc.v:198153$14180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:195118$14067 + cell $and $and$libresoc.v:198154$14181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409140,10 +413798,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:195118$14067_Y + connect \Y $and$libresoc.v:198154$14181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:195119$14068 + cell $and $and$libresoc.v:198155$14182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409151,10 +413809,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:195119$14068_Y + connect \Y $and$libresoc.v:198155$14182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:195120$14069 + cell $and $and$libresoc.v:198156$14183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409162,10 +413820,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:195120$14069_Y + connect \Y $and$libresoc.v:198156$14183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:195121$14070 + cell $and $and$libresoc.v:198157$14184 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409173,10 +413831,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:195121$14070_Y + connect \Y $and$libresoc.v:198157$14184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:195122$14071 + cell $and $and$libresoc.v:198158$14185 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409184,10 +413842,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:195122$14071_Y + connect \Y $and$libresoc.v:198158$14185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:195123$14072 + cell $and $and$libresoc.v:198159$14186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409195,10 +413853,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:195123$14072_Y + connect \Y $and$libresoc.v:198159$14186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:195124$14073 + cell $and $and$libresoc.v:198160$14187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409206,10 +413864,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:195124$14073_Y + connect \Y $and$libresoc.v:198160$14187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:195125$14074 + cell $and $and$libresoc.v:198161$14188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409217,10 +413875,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:195125$14074_Y + connect \Y $and$libresoc.v:198161$14188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:195126$14075 + cell $and $and$libresoc.v:198162$14189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409228,10 +413886,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:195126$14075_Y + connect \Y $and$libresoc.v:198162$14189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:195127$14076 + cell $and $and$libresoc.v:198163$14190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409239,10 +413897,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:195127$14076_Y + connect \Y $and$libresoc.v:198163$14190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:195128$14077 + cell $and $and$libresoc.v:198164$14191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409250,10 +413908,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:195128$14077_Y + connect \Y $and$libresoc.v:198164$14191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:195130$14079 + cell $and $and$libresoc.v:198166$14193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409261,10 +413919,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:195130$14079_Y + connect \Y $and$libresoc.v:198166$14193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:195132$14081 + cell $and $and$libresoc.v:198168$14195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409272,10 +413930,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:195132$14081_Y + connect \Y $and$libresoc.v:198168$14195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:195133$14082 + cell $and $and$libresoc.v:198169$14196 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409283,10 +413941,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:195133$14082_Y + connect \Y $and$libresoc.v:198169$14196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:195135$14084 + cell $and $and$libresoc.v:198171$14198 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409294,10 +413952,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:195135$14084_Y + connect \Y $and$libresoc.v:198171$14198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:195138$14087 + cell $and $and$libresoc.v:198174$14201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409305,10 +413963,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:195138$14087_Y + connect \Y $and$libresoc.v:198174$14201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:195142$14091 + cell $and $and$libresoc.v:198178$14205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409316,10 +413974,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:195142$14091_Y + connect \Y $and$libresoc.v:198178$14205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:195144$14093 + cell $and $and$libresoc.v:198180$14207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409327,10 +413985,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:195144$14093_Y + connect \Y $and$libresoc.v:198180$14207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:195145$14094 + cell $and $and$libresoc.v:198181$14208 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409338,10 +413996,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:195145$14094_Y + connect \Y $and$libresoc.v:198181$14208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:195147$14096 + cell $and $and$libresoc.v:198183$14210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409349,10 +414007,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:195147$14096_Y + connect \Y $and$libresoc.v:198183$14210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:195149$14098 + cell $and $and$libresoc.v:198185$14212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409360,10 +414018,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:195149$14098_Y + connect \Y $and$libresoc.v:198185$14212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:195150$14099 + cell $and $and$libresoc.v:198186$14213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409371,10 +414029,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:195150$14099_Y + connect \Y $and$libresoc.v:198186$14213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:195151$14100 + cell $and $and$libresoc.v:198187$14214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409382,10 +414040,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:195151$14100_Y + connect \Y $and$libresoc.v:198187$14214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:195156$14105 + cell $and $and$libresoc.v:198192$14219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409393,10 +414051,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:195156$14105_Y + connect \Y $and$libresoc.v:198192$14219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:195157$14106 + cell $and $and$libresoc.v:198193$14220 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409404,10 +414062,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:195157$14106_Y + connect \Y $and$libresoc.v:198193$14220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:195160$14109 + cell $and $and$libresoc.v:198196$14223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409415,10 +414073,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:195160$14109_Y + connect \Y $and$libresoc.v:198196$14223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:195161$14110 + cell $and $and$libresoc.v:198197$14224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409426,10 +414084,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:195161$14110_Y + connect \Y $and$libresoc.v:198197$14224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:195162$14111 + cell $and $and$libresoc.v:198198$14225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409437,10 +414095,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:195162$14111_Y + connect \Y $and$libresoc.v:198198$14225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:195163$14112 + cell $and $and$libresoc.v:198199$14226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409448,10 +414106,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:195163$14112_Y + connect \Y $and$libresoc.v:198199$14226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:195164$14113 + cell $and $and$libresoc.v:198200$14227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409459,10 +414117,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:195164$14113_Y + connect \Y $and$libresoc.v:198200$14227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:195170$14119 + cell $and $and$libresoc.v:198206$14233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409470,10 +414128,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:195170$14119_Y + connect \Y $and$libresoc.v:198206$14233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:195171$14120 + cell $and $and$libresoc.v:198207$14234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409481,10 +414139,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:195171$14120_Y + connect \Y $and$libresoc.v:198207$14234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:195172$14121 + cell $and $and$libresoc.v:198208$14235 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -409492,10 +414150,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:195172$14121_Y + connect \Y $and$libresoc.v:198208$14235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:195173$14122 + cell $and $and$libresoc.v:198209$14236 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -409503,10 +414161,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:195173$14122_Y + connect \Y $and$libresoc.v:198209$14236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:195146$14095 + cell $eq $eq$libresoc.v:198182$14209 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409514,10 +414172,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:195146$14095_Y + connect \Y $eq$libresoc.v:198182$14209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:195148$14097 + cell $eq $eq$libresoc.v:198184$14211 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409525,66 +414183,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:195148$14097_Y + connect \Y $eq$libresoc.v:198184$14211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:195129$14078 + cell $not $not$libresoc.v:198165$14192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:195129$14078_Y + connect \Y $not$libresoc.v:198165$14192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:195131$14080 + cell $not $not$libresoc.v:198167$14194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:195131$14080_Y + connect \Y $not$libresoc.v:198167$14194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:195134$14083 + cell $not $not$libresoc.v:198170$14197 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:195134$14083_Y + connect \Y $not$libresoc.v:198170$14197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:195137$14086 + cell $not $not$libresoc.v:198173$14200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:195137$14086_Y + connect \Y $not$libresoc.v:198173$14200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:195143$14092 + cell $not $not$libresoc.v:198179$14206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:195143$14092_Y + connect \Y $not$libresoc.v:198179$14206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:195158$14107 + cell $not $not$libresoc.v:198194$14221 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:195158$14107_Y + connect \Y $not$libresoc.v:198194$14221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:195174$14123 + cell $not $not$libresoc.v:198210$14237 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:195174$14123_Y + connect \Y $not$libresoc.v:198210$14237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:195141$14090 + cell $or $or$libresoc.v:198177$14204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409592,10 +414250,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:195141$14090_Y + connect \Y $or$libresoc.v:198177$14204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:195152$14101 + cell $or $or$libresoc.v:198188$14215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409603,10 +414261,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:195152$14101_Y + connect \Y $or$libresoc.v:198188$14215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:195153$14102 + cell $or $or$libresoc.v:198189$14216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409614,10 +414272,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:195153$14102_Y + connect \Y $or$libresoc.v:198189$14216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:195154$14103 + cell $or $or$libresoc.v:198190$14217 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409625,10 +414283,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:195154$14103_Y + connect \Y $or$libresoc.v:198190$14217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:195155$14104 + cell $or $or$libresoc.v:198191$14218 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -409636,10 +414294,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:195155$14104_Y + connect \Y $or$libresoc.v:198191$14218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:195159$14108 + cell $or $or$libresoc.v:198195$14222 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -409647,10 +414305,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:195159$14108_Y + connect \Y $or$libresoc.v:198195$14222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:195169$14118 + cell $or $or$libresoc.v:198205$14232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -409658,74 +414316,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:195169$14118_Y + connect \Y $or$libresoc.v:198205$14232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:195114$14063 + cell $reduce_and $reduce_and$libresoc.v:198150$14177 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:195114$14063_Y + connect \Y $reduce_and$libresoc.v:198150$14177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:195136$14085 + cell $reduce_or $reduce_or$libresoc.v:198172$14199 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:195136$14085_Y + connect \Y $reduce_or$libresoc.v:198172$14199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:195139$14088 + cell $reduce_or $reduce_or$libresoc.v:198175$14202 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:195139$14088_Y + connect \Y $reduce_or$libresoc.v:198175$14202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:195140$14089 + cell $reduce_or $reduce_or$libresoc.v:198176$14203 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:195140$14089_Y + connect \Y $reduce_or$libresoc.v:198176$14203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:195165$14114 + cell $mux $ternary$libresoc.v:198201$14228 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:195165$14114_Y + connect \Y $ternary$libresoc.v:198201$14228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:195166$14115 + cell $mux $ternary$libresoc.v:198202$14229 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:195166$14115_Y + connect \Y $ternary$libresoc.v:198202$14229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:195167$14116 + cell $mux $ternary$libresoc.v:198203$14230 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:195167$14116_Y + connect \Y $ternary$libresoc.v:198203$14230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:195168$14117 + cell $mux $ternary$libresoc.v:198204$14231 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:195168$14117_Y + connect \Y $ternary$libresoc.v:198204$14231_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:195251.14-195257.4" + attribute \src "libresoc.v:198287.14-198293.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -409734,7 +414392,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:195258.13-195288.4" + attribute \src "libresoc.v:198294.13-198324.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -409767,7 +414425,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:195289.15-195295.4" + attribute \src "libresoc.v:198325.15-198331.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -409776,7 +414434,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:195296.14-195302.4" + attribute \src "libresoc.v:198332.14-198338.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -409785,7 +414443,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:195303.14-195309.4" + attribute \src "libresoc.v:198339.14-198345.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -409794,7 +414452,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:195310.14-195316.4" + attribute \src "libresoc.v:198346.14-198352.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -409803,7 +414461,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:195317.14-195322.4" + attribute \src "libresoc.v:198353.14-198358.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -409811,7 +414469,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:195323.14-195329.4" + attribute \src "libresoc.v:198359.14-198365.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -409819,592 +414477,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:194518.7-194518.20" - process $proc$libresoc.v:194518$14278 + attribute \src "libresoc.v:197550.7-197550.20" + process $proc$libresoc.v:197550$14392 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:194644.7-194644.24" - process $proc$libresoc.v:194644$14279 + attribute \src "libresoc.v:197676.7-197676.24" + process $proc$libresoc.v:197676$14393 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:194654.7-194654.26" - process $proc$libresoc.v:194654$14280 + attribute \src "libresoc.v:197686.7-197686.26" + process $proc$libresoc.v:197686$14394 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:194662.7-194662.25" - process $proc$libresoc.v:194662$14281 + attribute \src "libresoc.v:197694.7-197694.25" + process $proc$libresoc.v:197694$14395 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:194698.14-194698.59" - process $proc$libresoc.v:194698$14282 + attribute \src "libresoc.v:197730.14-197730.59" + process $proc$libresoc.v:197730$14396 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:194716.14-194716.51" - process $proc$libresoc.v:194716$14283 + attribute \src "libresoc.v:197749.14-197749.51" + process $proc$libresoc.v:197749$14397 assign { } { } - assign $1\alu_trap0_trap_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init - update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[12:0] + update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:194720.14-194720.45" - process $proc$libresoc.v:194720$14284 + attribute \src "libresoc.v:197753.14-197753.45" + process $proc$libresoc.v:197753$14398 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:194798.13-194798.49" - process $proc$libresoc.v:194798$14285 + attribute \src "libresoc.v:197832.13-197832.49" + process $proc$libresoc.v:197832$14399 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:194802.7-194802.41" - process $proc$libresoc.v:194802$14286 + attribute \src "libresoc.v:197836.7-197836.41" + process $proc$libresoc.v:197836$14400 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:194806.13-194806.48" - process $proc$libresoc.v:194806$14287 + attribute \src "libresoc.v:197840.13-197840.48" + process $proc$libresoc.v:197840$14401 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:194810.14-194810.59" - process $proc$libresoc.v:194810$14288 + attribute \src "libresoc.v:197844.14-197844.59" + process $proc$libresoc.v:197844$14402 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:194814.14-194814.52" - process $proc$libresoc.v:194814$14289 + attribute \src "libresoc.v:197848.14-197848.52" + process $proc$libresoc.v:197848$14403 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:194818.13-194818.48" - process $proc$libresoc.v:194818$14290 + attribute \src "libresoc.v:197852.13-197852.48" + process $proc$libresoc.v:197852$14404 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:194824.7-194824.27" - process $proc$libresoc.v:194824$14291 + attribute \src "libresoc.v:197858.7-197858.27" + process $proc$libresoc.v:197858$14405 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:194856.14-194856.47" - process $proc$libresoc.v:194856$14292 + attribute \src "libresoc.v:197890.14-197890.47" + process $proc$libresoc.v:197890$14406 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:194860.7-194860.27" - process $proc$libresoc.v:194860$14293 + attribute \src "libresoc.v:197894.7-197894.27" + process $proc$libresoc.v:197894$14407 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:194864.14-194864.51" - process $proc$libresoc.v:194864$14294 + attribute \src "libresoc.v:197898.14-197898.51" + process $proc$libresoc.v:197898$14408 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:194868.7-194868.31" - process $proc$libresoc.v:194868$14295 + attribute \src "libresoc.v:197902.7-197902.31" + process $proc$libresoc.v:197902$14409 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:194872.14-194872.51" - process $proc$libresoc.v:194872$14296 + attribute \src "libresoc.v:197906.14-197906.51" + process $proc$libresoc.v:197906$14410 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:194876.7-194876.31" - process $proc$libresoc.v:194876$14297 + attribute \src "libresoc.v:197910.7-197910.31" + process $proc$libresoc.v:197910$14411 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:194880.14-194880.49" - process $proc$libresoc.v:194880$14298 + attribute \src "libresoc.v:197914.14-197914.49" + process $proc$libresoc.v:197914$14412 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:194884.7-194884.29" - process $proc$libresoc.v:194884$14299 + attribute \src "libresoc.v:197918.7-197918.29" + process $proc$libresoc.v:197918$14413 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:194888.14-194888.49" - process $proc$libresoc.v:194888$14300 + attribute \src "libresoc.v:197922.14-197922.49" + process $proc$libresoc.v:197922$14414 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:194892.7-194892.29" - process $proc$libresoc.v:194892$14301 + attribute \src "libresoc.v:197926.7-197926.29" + process $proc$libresoc.v:197926$14415 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:194923.7-194923.25" - process $proc$libresoc.v:194923$14302 + attribute \src "libresoc.v:197957.7-197957.25" + process $proc$libresoc.v:197957$14416 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:194927.7-194927.25" - process $proc$libresoc.v:194927$14303 + attribute \src "libresoc.v:197961.7-197961.25" + process $proc$libresoc.v:197961$14417 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:195037.13-195037.31" - process $proc$libresoc.v:195037$14304 + attribute \src "libresoc.v:198073.13-198073.31" + process $proc$libresoc.v:198073$14418 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:195045.13-195045.32" - process $proc$libresoc.v:195045$14305 + attribute \src "libresoc.v:198081.13-198081.32" + process $proc$libresoc.v:198081$14419 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:195049.13-195049.32" - process $proc$libresoc.v:195049$14306 + attribute \src "libresoc.v:198085.13-198085.32" + process $proc$libresoc.v:198085$14420 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:195061.7-195061.26" - process $proc$libresoc.v:195061$14307 + attribute \src "libresoc.v:198097.7-198097.26" + process $proc$libresoc.v:198097$14421 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:195065.7-195065.26" - process $proc$libresoc.v:195065$14308 + attribute \src "libresoc.v:198101.7-198101.26" + process $proc$libresoc.v:198101$14422 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:195069.7-195069.25" - process $proc$libresoc.v:195069$14309 + attribute \src "libresoc.v:198105.7-198105.25" + process $proc$libresoc.v:198105$14423 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:195073.7-195073.25" - process $proc$libresoc.v:195073$14310 + attribute \src "libresoc.v:198109.7-198109.25" + process $proc$libresoc.v:198109$14424 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:195089.13-195089.31" - process $proc$libresoc.v:195089$14311 + attribute \src "libresoc.v:198125.13-198125.31" + process $proc$libresoc.v:198125$14425 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:195093.13-195093.31" - process $proc$libresoc.v:195093$14312 + attribute \src "libresoc.v:198129.13-198129.31" + process $proc$libresoc.v:198129$14426 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:195097.14-195097.43" - process $proc$libresoc.v:195097$14313 + attribute \src "libresoc.v:198133.14-198133.43" + process $proc$libresoc.v:198133$14427 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:195101.14-195101.43" - process $proc$libresoc.v:195101$14314 + attribute \src "libresoc.v:198137.14-198137.43" + process $proc$libresoc.v:198137$14428 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:195105.14-195105.43" - process $proc$libresoc.v:195105$14315 + attribute \src "libresoc.v:198141.14-198141.43" + process $proc$libresoc.v:198141$14429 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:195109.14-195109.43" - process $proc$libresoc.v:195109$14316 + attribute \src "libresoc.v:198145.14-198145.43" + process $proc$libresoc.v:198145$14430 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:195175.3-195176.39" - process $proc$libresoc.v:195175$14124 + attribute \src "libresoc.v:198211.3-198212.39" + process $proc$libresoc.v:198211$14238 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:195177.3-195178.43" - process $proc$libresoc.v:195177$14125 + attribute \src "libresoc.v:198213.3-198214.43" + process $proc$libresoc.v:198213$14239 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:195179.3-195180.29" - process $proc$libresoc.v:195179$14126 + attribute \src "libresoc.v:198215.3-198216.29" + process $proc$libresoc.v:198215$14240 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:195181.3-195182.29" - process $proc$libresoc.v:195181$14127 + attribute \src "libresoc.v:198217.3-198218.29" + process $proc$libresoc.v:198217$14241 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:195183.3-195184.29" - process $proc$libresoc.v:195183$14128 + attribute \src "libresoc.v:198219.3-198220.29" + process $proc$libresoc.v:198219$14242 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:195185.3-195186.29" - process $proc$libresoc.v:195185$14129 + attribute \src "libresoc.v:198221.3-198222.29" + process $proc$libresoc.v:198221$14243 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:195187.3-195188.41" - process $proc$libresoc.v:195187$14130 + attribute \src "libresoc.v:198223.3-198224.41" + process $proc$libresoc.v:198223$14244 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:195189.3-195190.47" - process $proc$libresoc.v:195189$14131 + attribute \src "libresoc.v:198225.3-198226.47" + process $proc$libresoc.v:198225$14245 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:195191.3-195192.41" - process $proc$libresoc.v:195191$14132 + attribute \src "libresoc.v:198227.3-198228.41" + process $proc$libresoc.v:198227$14246 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:195193.3-195194.47" - process $proc$libresoc.v:195193$14133 + attribute \src "libresoc.v:198229.3-198230.47" + process $proc$libresoc.v:198229$14247 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:195195.3-195196.45" - process $proc$libresoc.v:195195$14134 + attribute \src "libresoc.v:198231.3-198232.45" + process $proc$libresoc.v:198231$14248 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:195197.3-195198.51" - process $proc$libresoc.v:195197$14135 + attribute \src "libresoc.v:198233.3-198234.51" + process $proc$libresoc.v:198233$14249 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:195199.3-195200.45" - process $proc$libresoc.v:195199$14136 + attribute \src "libresoc.v:198235.3-198236.45" + process $proc$libresoc.v:198235$14250 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:195201.3-195202.51" - process $proc$libresoc.v:195201$14137 + attribute \src "libresoc.v:198237.3-198238.51" + process $proc$libresoc.v:198237$14251 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:195203.3-195204.37" - process $proc$libresoc.v:195203$14138 + attribute \src "libresoc.v:198239.3-198240.37" + process $proc$libresoc.v:198239$14252 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:195205.3-195206.43" - process $proc$libresoc.v:195205$14139 + attribute \src "libresoc.v:198241.3-198242.43" + process $proc$libresoc.v:198241$14253 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:195207.3-195208.73" - process $proc$libresoc.v:195207$14140 + attribute \src "libresoc.v:198243.3-198244.73" + process $proc$libresoc.v:198243$14254 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:195209.3-195210.69" - process $proc$libresoc.v:195209$14141 + attribute \src "libresoc.v:198245.3-198246.69" + process $proc$libresoc.v:198245$14255 assign { } { } - assign $0\alu_trap0_trap_op__fn_unit[12:0] \alu_trap0_trap_op__fn_unit$next + assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk - update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[12:0] + update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:195211.3-195212.63" - process $proc$libresoc.v:195211$14142 + attribute \src "libresoc.v:198247.3-198248.63" + process $proc$libresoc.v:198247$14256 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:195213.3-195214.61" - process $proc$libresoc.v:195213$14143 + attribute \src "libresoc.v:198249.3-198250.61" + process $proc$libresoc.v:198249$14257 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:195215.3-195216.61" - process $proc$libresoc.v:195215$14144 + attribute \src "libresoc.v:198251.3-198252.61" + process $proc$libresoc.v:198251$14258 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:195217.3-195218.71" - process $proc$libresoc.v:195217$14145 + attribute \src "libresoc.v:198253.3-198254.71" + process $proc$libresoc.v:198253$14259 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:195219.3-195220.71" - process $proc$libresoc.v:195219$14146 + attribute \src "libresoc.v:198255.3-198256.71" + process $proc$libresoc.v:198255$14260 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:195221.3-195222.71" - process $proc$libresoc.v:195221$14147 + attribute \src "libresoc.v:198257.3-198258.71" + process $proc$libresoc.v:198257$14261 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:195223.3-195224.71" - process $proc$libresoc.v:195223$14148 + attribute \src "libresoc.v:198259.3-198260.71" + process $proc$libresoc.v:198259$14262 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:195225.3-195226.39" - process $proc$libresoc.v:195225$14149 + attribute \src "libresoc.v:198261.3-198262.39" + process $proc$libresoc.v:198261$14263 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:195227.3-195228.39" - process $proc$libresoc.v:195227$14150 + attribute \src "libresoc.v:198263.3-198264.39" + process $proc$libresoc.v:198263$14264 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:195229.3-195230.39" - process $proc$libresoc.v:195229$14151 + attribute \src "libresoc.v:198265.3-198266.39" + process $proc$libresoc.v:198265$14265 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:195231.3-195232.39" - process $proc$libresoc.v:195231$14152 + attribute \src "libresoc.v:198267.3-198268.39" + process $proc$libresoc.v:198267$14266 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:195233.3-195234.39" - process $proc$libresoc.v:195233$14153 + attribute \src "libresoc.v:198269.3-198270.39" + process $proc$libresoc.v:198269$14267 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:195235.3-195236.39" - process $proc$libresoc.v:195235$14154 + attribute \src "libresoc.v:198271.3-198272.39" + process $proc$libresoc.v:198271$14268 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:195237.3-195238.39" - process $proc$libresoc.v:195237$14155 + attribute \src "libresoc.v:198273.3-198274.39" + process $proc$libresoc.v:198273$14269 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:195239.3-195240.39" - process $proc$libresoc.v:195239$14156 + attribute \src "libresoc.v:198275.3-198276.39" + process $proc$libresoc.v:198275$14270 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:195241.3-195242.41" - process $proc$libresoc.v:195241$14157 + attribute \src "libresoc.v:198277.3-198278.41" + process $proc$libresoc.v:198277$14271 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:195243.3-195244.41" - process $proc$libresoc.v:195243$14158 + attribute \src "libresoc.v:198279.3-198280.41" + process $proc$libresoc.v:198279$14272 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:195245.3-195246.37" - process $proc$libresoc.v:195245$14159 + attribute \src "libresoc.v:198281.3-198282.37" + process $proc$libresoc.v:198281$14273 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:195247.3-195248.41" - process $proc$libresoc.v:195247$14160 + attribute \src "libresoc.v:198283.3-198284.41" + process $proc$libresoc.v:198283$14274 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:195249.3-195250.25" - process $proc$libresoc.v:195249$14161 + attribute \src "libresoc.v:198285.3-198286.25" + process $proc$libresoc.v:198285$14275 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:195330.3-195339.6" - process $proc$libresoc.v:195330$14162 + attribute \src "libresoc.v:198366.3-198375.6" + process $proc$libresoc.v:198366$14276 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:195331.5-195331.29" + attribute \src "libresoc.v:198367.5-198367.29" switch \initial - attribute \src "libresoc.v:195331.9-195331.17" + attribute \src "libresoc.v:198367.9-198367.17" case 1'1 case end @@ -410420,14 +415078,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:195340.3-195348.6" - process $proc$libresoc.v:195340$14163 + attribute \src "libresoc.v:198376.3-198384.6" + process $proc$libresoc.v:198376$14277 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14164 $1\rok_l_s_rdok$next[0:0]$14165 - attribute \src "libresoc.v:195341.5-195341.29" + assign $0\rok_l_s_rdok$next[0:0]$14278 $1\rok_l_s_rdok$next[0:0]$14279 + attribute \src "libresoc.v:198377.5-198377.29" switch \initial - attribute \src "libresoc.v:195341.9-195341.17" + attribute \src "libresoc.v:198377.9-198377.17" case 1'1 case end @@ -410436,21 +415094,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14165 1'0 + assign $1\rok_l_s_rdok$next[0:0]$14279 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14165 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$14279 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14164 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14278 end - attribute \src "libresoc.v:195349.3-195357.6" - process $proc$libresoc.v:195349$14166 + attribute \src "libresoc.v:198385.3-198393.6" + process $proc$libresoc.v:198385$14280 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14167 $1\rok_l_r_rdok$next[0:0]$14168 - attribute \src "libresoc.v:195350.5-195350.29" + assign $0\rok_l_r_rdok$next[0:0]$14281 $1\rok_l_r_rdok$next[0:0]$14282 + attribute \src "libresoc.v:198386.5-198386.29" switch \initial - attribute \src "libresoc.v:195350.9-195350.17" + attribute \src "libresoc.v:198386.9-198386.17" case 1'1 case end @@ -410459,21 +415117,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14168 1'1 + assign $1\rok_l_r_rdok$next[0:0]$14282 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$14168 \$65 + assign $1\rok_l_r_rdok$next[0:0]$14282 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14167 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14281 end - attribute \src "libresoc.v:195358.3-195366.6" - process $proc$libresoc.v:195358$14169 + attribute \src "libresoc.v:198394.3-198402.6" + process $proc$libresoc.v:198394$14283 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14170 $1\rst_l_s_rst$next[0:0]$14171 - attribute \src "libresoc.v:195359.5-195359.29" + assign $0\rst_l_s_rst$next[0:0]$14284 $1\rst_l_s_rst$next[0:0]$14285 + attribute \src "libresoc.v:198395.5-198395.29" switch \initial - attribute \src "libresoc.v:195359.9-195359.17" + attribute \src "libresoc.v:198395.9-198395.17" case 1'1 case end @@ -410482,21 +415140,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14171 1'0 + assign $1\rst_l_s_rst$next[0:0]$14285 1'0 case - assign $1\rst_l_s_rst$next[0:0]$14171 \all_rd + assign $1\rst_l_s_rst$next[0:0]$14285 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14170 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14284 end - attribute \src "libresoc.v:195367.3-195375.6" - process $proc$libresoc.v:195367$14172 + attribute \src "libresoc.v:198403.3-198411.6" + process $proc$libresoc.v:198403$14286 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14173 $1\rst_l_r_rst$next[0:0]$14174 - attribute \src "libresoc.v:195368.5-195368.29" + assign $0\rst_l_r_rst$next[0:0]$14287 $1\rst_l_r_rst$next[0:0]$14288 + attribute \src "libresoc.v:198404.5-198404.29" switch \initial - attribute \src "libresoc.v:195368.9-195368.17" + attribute \src "libresoc.v:198404.9-198404.17" case 1'1 case end @@ -410505,21 +415163,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14174 1'1 + assign $1\rst_l_r_rst$next[0:0]$14288 1'1 case - assign $1\rst_l_r_rst$next[0:0]$14174 \rst_r + assign $1\rst_l_r_rst$next[0:0]$14288 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14173 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14287 end - attribute \src "libresoc.v:195376.3-195384.6" - process $proc$libresoc.v:195376$14175 + attribute \src "libresoc.v:198412.3-198420.6" + process $proc$libresoc.v:198412$14289 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14176 $1\opc_l_s_opc$next[0:0]$14177 - attribute \src "libresoc.v:195377.5-195377.29" + assign $0\opc_l_s_opc$next[0:0]$14290 $1\opc_l_s_opc$next[0:0]$14291 + attribute \src "libresoc.v:198413.5-198413.29" switch \initial - attribute \src "libresoc.v:195377.9-195377.17" + attribute \src "libresoc.v:198413.9-198413.17" case 1'1 case end @@ -410528,21 +415186,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14177 1'0 + assign $1\opc_l_s_opc$next[0:0]$14291 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14177 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$14291 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14176 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14290 end - attribute \src "libresoc.v:195385.3-195393.6" - process $proc$libresoc.v:195385$14178 + attribute \src "libresoc.v:198421.3-198429.6" + process $proc$libresoc.v:198421$14292 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14179 $1\opc_l_r_opc$next[0:0]$14180 - attribute \src "libresoc.v:195386.5-195386.29" + assign $0\opc_l_r_opc$next[0:0]$14293 $1\opc_l_r_opc$next[0:0]$14294 + attribute \src "libresoc.v:198422.5-198422.29" switch \initial - attribute \src "libresoc.v:195386.9-195386.17" + attribute \src "libresoc.v:198422.9-198422.17" case 1'1 case end @@ -410551,21 +415209,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14180 1'1 + assign $1\opc_l_r_opc$next[0:0]$14294 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14180 \req_done + assign $1\opc_l_r_opc$next[0:0]$14294 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14179 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14293 end - attribute \src "libresoc.v:195394.3-195402.6" - process $proc$libresoc.v:195394$14181 + attribute \src "libresoc.v:198430.3-198438.6" + process $proc$libresoc.v:198430$14295 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14182 $1\src_l_s_src$next[3:0]$14183 - attribute \src "libresoc.v:195395.5-195395.29" + assign $0\src_l_s_src$next[3:0]$14296 $1\src_l_s_src$next[3:0]$14297 + attribute \src "libresoc.v:198431.5-198431.29" switch \initial - attribute \src "libresoc.v:195395.9-195395.17" + attribute \src "libresoc.v:198431.9-198431.17" case 1'1 case end @@ -410574,21 +415232,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14183 4'0000 + assign $1\src_l_s_src$next[3:0]$14297 4'0000 case - assign $1\src_l_s_src$next[3:0]$14183 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14297 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14182 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14296 end - attribute \src "libresoc.v:195403.3-195411.6" - process $proc$libresoc.v:195403$14184 + attribute \src "libresoc.v:198439.3-198447.6" + process $proc$libresoc.v:198439$14298 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14185 $1\src_l_r_src$next[3:0]$14186 - attribute \src "libresoc.v:195404.5-195404.29" + assign $0\src_l_r_src$next[3:0]$14299 $1\src_l_r_src$next[3:0]$14300 + attribute \src "libresoc.v:198440.5-198440.29" switch \initial - attribute \src "libresoc.v:195404.9-195404.17" + attribute \src "libresoc.v:198440.9-198440.17" case 1'1 case end @@ -410597,21 +415255,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14186 4'1111 + assign $1\src_l_r_src$next[3:0]$14300 4'1111 case - assign $1\src_l_r_src$next[3:0]$14186 \reset_r + assign $1\src_l_r_src$next[3:0]$14300 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14185 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14299 end - attribute \src "libresoc.v:195412.3-195420.6" - process $proc$libresoc.v:195412$14187 + attribute \src "libresoc.v:198448.3-198456.6" + process $proc$libresoc.v:198448$14301 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14188 $1\req_l_s_req$next[4:0]$14189 - attribute \src "libresoc.v:195413.5-195413.29" + assign $0\req_l_s_req$next[4:0]$14302 $1\req_l_s_req$next[4:0]$14303 + attribute \src "libresoc.v:198449.5-198449.29" switch \initial - attribute \src "libresoc.v:195413.9-195413.17" + attribute \src "libresoc.v:198449.9-198449.17" case 1'1 case end @@ -410620,21 +415278,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14189 5'00000 + assign $1\req_l_s_req$next[4:0]$14303 5'00000 case - assign $1\req_l_s_req$next[4:0]$14189 \$67 + assign $1\req_l_s_req$next[4:0]$14303 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14188 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14302 end - attribute \src "libresoc.v:195421.3-195429.6" - process $proc$libresoc.v:195421$14190 + attribute \src "libresoc.v:198457.3-198465.6" + process $proc$libresoc.v:198457$14304 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14191 $1\req_l_r_req$next[4:0]$14192 - attribute \src "libresoc.v:195422.5-195422.29" + assign $0\req_l_r_req$next[4:0]$14305 $1\req_l_r_req$next[4:0]$14306 + attribute \src "libresoc.v:198458.5-198458.29" switch \initial - attribute \src "libresoc.v:195422.9-195422.17" + attribute \src "libresoc.v:198458.9-198458.17" case 1'1 case end @@ -410643,15 +415301,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14192 5'11111 + assign $1\req_l_r_req$next[4:0]$14306 5'11111 case - assign $1\req_l_r_req$next[4:0]$14192 \$69 + assign $1\req_l_r_req$next[4:0]$14306 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14191 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14305 end - attribute \src "libresoc.v:195430.3-195447.6" - process $proc$libresoc.v:195430$14193 + attribute \src "libresoc.v:198466.3-198483.6" + process $proc$libresoc.v:198466$14307 assign { } { } assign { } { } assign { } { } @@ -410670,18 +415328,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14194 $1\alu_trap0_trap_op__cia$next[63:0]$14203 - assign $0\alu_trap0_trap_op__fn_unit$next[12:0]$14195 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14204 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14196 $1\alu_trap0_trap_op__insn$next[31:0]$14205 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14197 $1\alu_trap0_trap_op__insn_type$next[6:0]$14206 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14198 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14207 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14199 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14208 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14200 $1\alu_trap0_trap_op__msr$next[63:0]$14209 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14201 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14210 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14202 $1\alu_trap0_trap_op__traptype$next[7:0]$14211 - attribute \src "libresoc.v:195431.5-195431.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$14308 $1\alu_trap0_trap_op__cia$next[63:0]$14317 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14310 $1\alu_trap0_trap_op__insn$next[31:0]$14319 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14314 $1\alu_trap0_trap_op__msr$next[63:0]$14323 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14316 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 + attribute \src "libresoc.v:198467.5-198467.29" switch \initial - attribute \src "libresoc.v:195431.9-195431.17" + attribute \src "libresoc.v:198467.9-198467.17" case 1'1 case end @@ -410698,43 +415356,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14208 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14210 $1\alu_trap0_trap_op__traptype$next[7:0]$14211 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14207 $1\alu_trap0_trap_op__cia$next[63:0]$14203 $1\alu_trap0_trap_op__msr$next[63:0]$14209 $1\alu_trap0_trap_op__insn$next[31:0]$14205 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14204 $1\alu_trap0_trap_op__insn_type$next[6:0]$14206 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 $1\alu_trap0_trap_op__cia$next[63:0]$14317 $1\alu_trap0_trap_op__msr$next[63:0]$14323 $1\alu_trap0_trap_op__insn$next[31:0]$14319 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14203 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[12:0]$14204 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14205 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14206 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14207 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14208 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14209 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14210 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14211 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14317 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14319 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14323 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14325 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14194 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[12:0]$14195 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14196 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14197 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14198 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14199 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14200 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14201 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14202 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14308 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14310 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14314 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14316 end - attribute \src "libresoc.v:195448.3-195469.6" - process $proc$libresoc.v:195448$14212 + attribute \src "libresoc.v:198484.3-198505.6" + process $proc$libresoc.v:198484$14326 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14213 $2\data_r0__o$next[63:0]$14217 + assign $0\data_r0__o$next[63:0]$14327 $2\data_r0__o$next[63:0]$14331 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14214 $3\data_r0__o_ok$next[0:0]$14219 - attribute \src "libresoc.v:195449.5-195449.29" + assign $0\data_r0__o_ok$next[0:0]$14328 $3\data_r0__o_ok$next[0:0]$14333 + attribute \src "libresoc.v:198485.5-198485.29" switch \initial - attribute \src "libresoc.v:195449.9-195449.17" + attribute \src "libresoc.v:198485.9-198485.17" case 1'1 case end @@ -410744,10 +415402,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14216 $1\data_r0__o$next[63:0]$14215 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14330 $1\data_r0__o$next[63:0]$14329 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14215 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14216 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14329 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14330 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -410755,38 +415413,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14218 $2\data_r0__o$next[63:0]$14217 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14332 $2\data_r0__o$next[63:0]$14331 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14217 $1\data_r0__o$next[63:0]$14215 - assign $2\data_r0__o_ok$next[0:0]$14218 $1\data_r0__o_ok$next[0:0]$14216 + assign $2\data_r0__o$next[63:0]$14331 $1\data_r0__o$next[63:0]$14329 + assign $2\data_r0__o_ok$next[0:0]$14332 $1\data_r0__o_ok$next[0:0]$14330 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14219 1'0 + assign $3\data_r0__o_ok$next[0:0]$14333 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14219 $2\data_r0__o_ok$next[0:0]$14218 + assign $3\data_r0__o_ok$next[0:0]$14333 $2\data_r0__o_ok$next[0:0]$14332 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14213 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14214 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14327 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14328 end - attribute \src "libresoc.v:195470.3-195491.6" - process $proc$libresoc.v:195470$14220 + attribute \src "libresoc.v:198506.3-198527.6" + process $proc$libresoc.v:198506$14334 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14221 $2\data_r1__fast1$next[63:0]$14225 + assign $0\data_r1__fast1$next[63:0]$14335 $2\data_r1__fast1$next[63:0]$14339 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14222 $3\data_r1__fast1_ok$next[0:0]$14227 - attribute \src "libresoc.v:195471.5-195471.29" + assign $0\data_r1__fast1_ok$next[0:0]$14336 $3\data_r1__fast1_ok$next[0:0]$14341 + attribute \src "libresoc.v:198507.5-198507.29" switch \initial - attribute \src "libresoc.v:195471.9-195471.17" + attribute \src "libresoc.v:198507.9-198507.17" case 1'1 case end @@ -410796,10 +415454,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14224 $1\data_r1__fast1$next[63:0]$14223 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14338 $1\data_r1__fast1$next[63:0]$14337 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14223 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14224 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14337 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14338 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -410807,38 +415465,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14226 $2\data_r1__fast1$next[63:0]$14225 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14340 $2\data_r1__fast1$next[63:0]$14339 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14225 $1\data_r1__fast1$next[63:0]$14223 - assign $2\data_r1__fast1_ok$next[0:0]$14226 $1\data_r1__fast1_ok$next[0:0]$14224 + assign $2\data_r1__fast1$next[63:0]$14339 $1\data_r1__fast1$next[63:0]$14337 + assign $2\data_r1__fast1_ok$next[0:0]$14340 $1\data_r1__fast1_ok$next[0:0]$14338 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14227 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14341 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14227 $2\data_r1__fast1_ok$next[0:0]$14226 + assign $3\data_r1__fast1_ok$next[0:0]$14341 $2\data_r1__fast1_ok$next[0:0]$14340 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14221 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14222 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14335 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14336 end - attribute \src "libresoc.v:195492.3-195513.6" - process $proc$libresoc.v:195492$14228 + attribute \src "libresoc.v:198528.3-198549.6" + process $proc$libresoc.v:198528$14342 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14229 $2\data_r2__fast2$next[63:0]$14233 + assign $0\data_r2__fast2$next[63:0]$14343 $2\data_r2__fast2$next[63:0]$14347 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14230 $3\data_r2__fast2_ok$next[0:0]$14235 - attribute \src "libresoc.v:195493.5-195493.29" + assign $0\data_r2__fast2_ok$next[0:0]$14344 $3\data_r2__fast2_ok$next[0:0]$14349 + attribute \src "libresoc.v:198529.5-198529.29" switch \initial - attribute \src "libresoc.v:195493.9-195493.17" + attribute \src "libresoc.v:198529.9-198529.17" case 1'1 case end @@ -410848,10 +415506,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14232 $1\data_r2__fast2$next[63:0]$14231 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14346 $1\data_r2__fast2$next[63:0]$14345 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14231 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14232 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14345 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14346 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -410859,38 +415517,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14234 $2\data_r2__fast2$next[63:0]$14233 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14348 $2\data_r2__fast2$next[63:0]$14347 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14233 $1\data_r2__fast2$next[63:0]$14231 - assign $2\data_r2__fast2_ok$next[0:0]$14234 $1\data_r2__fast2_ok$next[0:0]$14232 + assign $2\data_r2__fast2$next[63:0]$14347 $1\data_r2__fast2$next[63:0]$14345 + assign $2\data_r2__fast2_ok$next[0:0]$14348 $1\data_r2__fast2_ok$next[0:0]$14346 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14235 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14349 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14235 $2\data_r2__fast2_ok$next[0:0]$14234 + assign $3\data_r2__fast2_ok$next[0:0]$14349 $2\data_r2__fast2_ok$next[0:0]$14348 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14229 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14230 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14343 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14344 end - attribute \src "libresoc.v:195514.3-195535.6" - process $proc$libresoc.v:195514$14236 + attribute \src "libresoc.v:198550.3-198571.6" + process $proc$libresoc.v:198550$14350 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14237 $2\data_r3__nia$next[63:0]$14241 + assign $0\data_r3__nia$next[63:0]$14351 $2\data_r3__nia$next[63:0]$14355 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14238 $3\data_r3__nia_ok$next[0:0]$14243 - attribute \src "libresoc.v:195515.5-195515.29" + assign $0\data_r3__nia_ok$next[0:0]$14352 $3\data_r3__nia_ok$next[0:0]$14357 + attribute \src "libresoc.v:198551.5-198551.29" switch \initial - attribute \src "libresoc.v:195515.9-195515.17" + attribute \src "libresoc.v:198551.9-198551.17" case 1'1 case end @@ -410900,10 +415558,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14240 $1\data_r3__nia$next[63:0]$14239 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14354 $1\data_r3__nia$next[63:0]$14353 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14239 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14240 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14353 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14354 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -410911,38 +415569,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14242 $2\data_r3__nia$next[63:0]$14241 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14356 $2\data_r3__nia$next[63:0]$14355 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14241 $1\data_r3__nia$next[63:0]$14239 - assign $2\data_r3__nia_ok$next[0:0]$14242 $1\data_r3__nia_ok$next[0:0]$14240 + assign $2\data_r3__nia$next[63:0]$14355 $1\data_r3__nia$next[63:0]$14353 + assign $2\data_r3__nia_ok$next[0:0]$14356 $1\data_r3__nia_ok$next[0:0]$14354 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14243 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14357 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14243 $2\data_r3__nia_ok$next[0:0]$14242 + assign $3\data_r3__nia_ok$next[0:0]$14357 $2\data_r3__nia_ok$next[0:0]$14356 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14237 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14238 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14351 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14352 end - attribute \src "libresoc.v:195536.3-195557.6" - process $proc$libresoc.v:195536$14244 + attribute \src "libresoc.v:198572.3-198593.6" + process $proc$libresoc.v:198572$14358 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14245 $2\data_r4__msr$next[63:0]$14249 + assign $0\data_r4__msr$next[63:0]$14359 $2\data_r4__msr$next[63:0]$14363 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14246 $3\data_r4__msr_ok$next[0:0]$14251 - attribute \src "libresoc.v:195537.5-195537.29" + assign $0\data_r4__msr_ok$next[0:0]$14360 $3\data_r4__msr_ok$next[0:0]$14365 + attribute \src "libresoc.v:198573.5-198573.29" switch \initial - attribute \src "libresoc.v:195537.9-195537.17" + attribute \src "libresoc.v:198573.9-198573.17" case 1'1 case end @@ -410952,10 +415610,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14248 $1\data_r4__msr$next[63:0]$14247 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14362 $1\data_r4__msr$next[63:0]$14361 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14247 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14248 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14361 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14362 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -410963,32 +415621,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14250 $2\data_r4__msr$next[63:0]$14249 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14364 $2\data_r4__msr$next[63:0]$14363 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14249 $1\data_r4__msr$next[63:0]$14247 - assign $2\data_r4__msr_ok$next[0:0]$14250 $1\data_r4__msr_ok$next[0:0]$14248 + assign $2\data_r4__msr$next[63:0]$14363 $1\data_r4__msr$next[63:0]$14361 + assign $2\data_r4__msr_ok$next[0:0]$14364 $1\data_r4__msr_ok$next[0:0]$14362 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14251 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14365 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14251 $2\data_r4__msr_ok$next[0:0]$14250 + assign $3\data_r4__msr_ok$next[0:0]$14365 $2\data_r4__msr_ok$next[0:0]$14364 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14245 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14246 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14359 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14360 end - attribute \src "libresoc.v:195558.3-195567.6" - process $proc$libresoc.v:195558$14252 + attribute \src "libresoc.v:198594.3-198603.6" + process $proc$libresoc.v:198594$14366 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14253 $1\src_r0$next[63:0]$14254 - attribute \src "libresoc.v:195559.5-195559.29" + assign $0\src_r0$next[63:0]$14367 $1\src_r0$next[63:0]$14368 + attribute \src "libresoc.v:198595.5-198595.29" switch \initial - attribute \src "libresoc.v:195559.9-195559.17" + attribute \src "libresoc.v:198595.9-198595.17" case 1'1 case end @@ -410997,21 +415655,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14254 \src1_i + assign $1\src_r0$next[63:0]$14368 \src1_i case - assign $1\src_r0$next[63:0]$14254 \src_r0 + assign $1\src_r0$next[63:0]$14368 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14253 + update \src_r0$next $0\src_r0$next[63:0]$14367 end - attribute \src "libresoc.v:195568.3-195577.6" - process $proc$libresoc.v:195568$14255 + attribute \src "libresoc.v:198604.3-198613.6" + process $proc$libresoc.v:198604$14369 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14256 $1\src_r1$next[63:0]$14257 - attribute \src "libresoc.v:195569.5-195569.29" + assign $0\src_r1$next[63:0]$14370 $1\src_r1$next[63:0]$14371 + attribute \src "libresoc.v:198605.5-198605.29" switch \initial - attribute \src "libresoc.v:195569.9-195569.17" + attribute \src "libresoc.v:198605.9-198605.17" case 1'1 case end @@ -411020,21 +415678,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14257 \src2_i + assign $1\src_r1$next[63:0]$14371 \src2_i case - assign $1\src_r1$next[63:0]$14257 \src_r1 + assign $1\src_r1$next[63:0]$14371 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14256 + update \src_r1$next $0\src_r1$next[63:0]$14370 end - attribute \src "libresoc.v:195578.3-195587.6" - process $proc$libresoc.v:195578$14258 + attribute \src "libresoc.v:198614.3-198623.6" + process $proc$libresoc.v:198614$14372 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14259 $1\src_r2$next[63:0]$14260 - attribute \src "libresoc.v:195579.5-195579.29" + assign $0\src_r2$next[63:0]$14373 $1\src_r2$next[63:0]$14374 + attribute \src "libresoc.v:198615.5-198615.29" switch \initial - attribute \src "libresoc.v:195579.9-195579.17" + attribute \src "libresoc.v:198615.9-198615.17" case 1'1 case end @@ -411043,21 +415701,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14260 \src3_i + assign $1\src_r2$next[63:0]$14374 \src3_i case - assign $1\src_r2$next[63:0]$14260 \src_r2 + assign $1\src_r2$next[63:0]$14374 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14259 + update \src_r2$next $0\src_r2$next[63:0]$14373 end - attribute \src "libresoc.v:195588.3-195597.6" - process $proc$libresoc.v:195588$14261 + attribute \src "libresoc.v:198624.3-198633.6" + process $proc$libresoc.v:198624$14375 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14262 $1\src_r3$next[63:0]$14263 - attribute \src "libresoc.v:195589.5-195589.29" + assign $0\src_r3$next[63:0]$14376 $1\src_r3$next[63:0]$14377 + attribute \src "libresoc.v:198625.5-198625.29" switch \initial - attribute \src "libresoc.v:195589.9-195589.17" + attribute \src "libresoc.v:198625.9-198625.17" case 1'1 case end @@ -411066,21 +415724,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14263 \src4_i + assign $1\src_r3$next[63:0]$14377 \src4_i case - assign $1\src_r3$next[63:0]$14263 \src_r3 + assign $1\src_r3$next[63:0]$14377 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14262 + update \src_r3$next $0\src_r3$next[63:0]$14376 end - attribute \src "libresoc.v:195598.3-195606.6" - process $proc$libresoc.v:195598$14264 + attribute \src "libresoc.v:198634.3-198642.6" + process $proc$libresoc.v:198634$14378 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14265 $1\alui_l_r_alui$next[0:0]$14266 - attribute \src "libresoc.v:195599.5-195599.29" + assign $0\alui_l_r_alui$next[0:0]$14379 $1\alui_l_r_alui$next[0:0]$14380 + attribute \src "libresoc.v:198635.5-198635.29" switch \initial - attribute \src "libresoc.v:195599.9-195599.17" + attribute \src "libresoc.v:198635.9-198635.17" case 1'1 case end @@ -411089,21 +415747,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14266 1'1 + assign $1\alui_l_r_alui$next[0:0]$14380 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14266 \$89 + assign $1\alui_l_r_alui$next[0:0]$14380 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14265 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14379 end - attribute \src "libresoc.v:195607.3-195615.6" - process $proc$libresoc.v:195607$14267 + attribute \src "libresoc.v:198643.3-198651.6" + process $proc$libresoc.v:198643$14381 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14268 $1\alu_l_r_alu$next[0:0]$14269 - attribute \src "libresoc.v:195608.5-195608.29" + assign $0\alu_l_r_alu$next[0:0]$14382 $1\alu_l_r_alu$next[0:0]$14383 + attribute \src "libresoc.v:198644.5-198644.29" switch \initial - attribute \src "libresoc.v:195608.9-195608.17" + attribute \src "libresoc.v:198644.9-198644.17" case 1'1 case end @@ -411112,21 +415770,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14269 1'1 + assign $1\alu_l_r_alu$next[0:0]$14383 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14269 \$91 + assign $1\alu_l_r_alu$next[0:0]$14383 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14268 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14382 end - attribute \src "libresoc.v:195616.3-195625.6" - process $proc$libresoc.v:195616$14270 + attribute \src "libresoc.v:198652.3-198661.6" + process $proc$libresoc.v:198652$14384 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:195617.5-195617.29" + attribute \src "libresoc.v:198653.5-198653.29" switch \initial - attribute \src "libresoc.v:195617.9-195617.17" + attribute \src "libresoc.v:198653.9-198653.17" case 1'1 case end @@ -411142,14 +415800,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:195626.3-195635.6" - process $proc$libresoc.v:195626$14271 + attribute \src "libresoc.v:198662.3-198671.6" + process $proc$libresoc.v:198662$14385 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:195627.5-195627.29" + attribute \src "libresoc.v:198663.5-198663.29" switch \initial - attribute \src "libresoc.v:195627.9-195627.17" + attribute \src "libresoc.v:198663.9-198663.17" case 1'1 case end @@ -411165,14 +415823,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:195636.3-195645.6" - process $proc$libresoc.v:195636$14272 + attribute \src "libresoc.v:198672.3-198681.6" + process $proc$libresoc.v:198672$14386 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:195637.5-195637.29" + attribute \src "libresoc.v:198673.5-198673.29" switch \initial - attribute \src "libresoc.v:195637.9-195637.17" + attribute \src "libresoc.v:198673.9-198673.17" case 1'1 case end @@ -411188,14 +415846,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:195646.3-195655.6" - process $proc$libresoc.v:195646$14273 + attribute \src "libresoc.v:198682.3-198691.6" + process $proc$libresoc.v:198682$14387 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:195647.5-195647.29" + attribute \src "libresoc.v:198683.5-198683.29" switch \initial - attribute \src "libresoc.v:195647.9-195647.17" + attribute \src "libresoc.v:198683.9-198683.17" case 1'1 case end @@ -411211,14 +415869,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:195656.3-195665.6" - process $proc$libresoc.v:195656$14274 + attribute \src "libresoc.v:198692.3-198701.6" + process $proc$libresoc.v:198692$14388 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:195657.5-195657.29" + attribute \src "libresoc.v:198693.5-198693.29" switch \initial - attribute \src "libresoc.v:195657.9-195657.17" + attribute \src "libresoc.v:198693.9-198693.17" case 1'1 case end @@ -411234,14 +415892,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:195666.3-195674.6" - process $proc$libresoc.v:195666$14275 + attribute \src "libresoc.v:198702.3-198710.6" + process $proc$libresoc.v:198702$14389 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14276 $1\prev_wr_go$next[4:0]$14277 - attribute \src "libresoc.v:195667.5-195667.29" + assign $0\prev_wr_go$next[4:0]$14390 $1\prev_wr_go$next[4:0]$14391 + attribute \src "libresoc.v:198703.5-198703.29" switch \initial - attribute \src "libresoc.v:195667.9-195667.17" + attribute \src "libresoc.v:198703.9-198703.17" case 1'1 case end @@ -411250,74 +415908,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14277 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14277 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14276 - end - connect \$5 $reduce_and$libresoc.v:195114$14063_Y - connect \$99 $and$libresoc.v:195115$14064_Y - connect \$101 $and$libresoc.v:195116$14065_Y - connect \$103 $and$libresoc.v:195117$14066_Y - connect \$105 $and$libresoc.v:195118$14067_Y - connect \$107 $and$libresoc.v:195119$14068_Y - connect \$109 $and$libresoc.v:195120$14069_Y - connect \$111 $and$libresoc.v:195121$14070_Y - connect \$113 $and$libresoc.v:195122$14071_Y - connect \$115 $and$libresoc.v:195123$14072_Y - connect \$117 $and$libresoc.v:195124$14073_Y - connect \$11 $and$libresoc.v:195125$14074_Y - connect \$119 $and$libresoc.v:195126$14075_Y - connect \$121 $and$libresoc.v:195127$14076_Y - connect \$123 $and$libresoc.v:195128$14077_Y - connect \$13 $not$libresoc.v:195129$14078_Y - connect \$15 $and$libresoc.v:195130$14079_Y - connect \$17 $not$libresoc.v:195131$14080_Y - connect \$19 $and$libresoc.v:195132$14081_Y - connect \$21 $and$libresoc.v:195133$14082_Y - connect \$25 $not$libresoc.v:195134$14083_Y - connect \$27 $and$libresoc.v:195135$14084_Y - connect \$24 $reduce_or$libresoc.v:195136$14085_Y - connect \$23 $not$libresoc.v:195137$14086_Y - connect \$31 $and$libresoc.v:195138$14087_Y - connect \$33 $reduce_or$libresoc.v:195139$14088_Y - connect \$35 $reduce_or$libresoc.v:195140$14089_Y - connect \$37 $or$libresoc.v:195141$14090_Y - connect \$3 $and$libresoc.v:195142$14091_Y - connect \$39 $not$libresoc.v:195143$14092_Y - connect \$41 $and$libresoc.v:195144$14093_Y - connect \$43 $and$libresoc.v:195145$14094_Y - connect \$45 $eq$libresoc.v:195146$14095_Y - connect \$47 $and$libresoc.v:195147$14096_Y - connect \$49 $eq$libresoc.v:195148$14097_Y - connect \$51 $and$libresoc.v:195149$14098_Y - connect \$53 $and$libresoc.v:195150$14099_Y - connect \$55 $and$libresoc.v:195151$14100_Y - connect \$57 $or$libresoc.v:195152$14101_Y - connect \$59 $or$libresoc.v:195153$14102_Y - connect \$61 $or$libresoc.v:195154$14103_Y - connect \$63 $or$libresoc.v:195155$14104_Y - connect \$65 $and$libresoc.v:195156$14105_Y - connect \$67 $and$libresoc.v:195157$14106_Y - connect \$6 $not$libresoc.v:195158$14107_Y - connect \$69 $or$libresoc.v:195159$14108_Y - connect \$71 $and$libresoc.v:195160$14109_Y - connect \$73 $and$libresoc.v:195161$14110_Y - connect \$75 $and$libresoc.v:195162$14111_Y - connect \$77 $and$libresoc.v:195163$14112_Y - connect \$79 $and$libresoc.v:195164$14113_Y - connect \$81 $ternary$libresoc.v:195165$14114_Y - connect \$83 $ternary$libresoc.v:195166$14115_Y - connect \$85 $ternary$libresoc.v:195167$14116_Y - connect \$87 $ternary$libresoc.v:195168$14117_Y - connect \$8 $or$libresoc.v:195169$14118_Y - connect \$89 $and$libresoc.v:195170$14119_Y - connect \$91 $and$libresoc.v:195171$14120_Y - connect \$93 $and$libresoc.v:195172$14121_Y - connect \$95 $and$libresoc.v:195173$14122_Y - connect \$97 $not$libresoc.v:195174$14123_Y + assign $1\prev_wr_go$next[4:0]$14391 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14391 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14390 + end + connect \$5 $reduce_and$libresoc.v:198150$14177_Y + connect \$99 $and$libresoc.v:198151$14178_Y + connect \$101 $and$libresoc.v:198152$14179_Y + connect \$103 $and$libresoc.v:198153$14180_Y + connect \$105 $and$libresoc.v:198154$14181_Y + connect \$107 $and$libresoc.v:198155$14182_Y + connect \$109 $and$libresoc.v:198156$14183_Y + connect \$111 $and$libresoc.v:198157$14184_Y + connect \$113 $and$libresoc.v:198158$14185_Y + connect \$115 $and$libresoc.v:198159$14186_Y + connect \$117 $and$libresoc.v:198160$14187_Y + connect \$11 $and$libresoc.v:198161$14188_Y + connect \$119 $and$libresoc.v:198162$14189_Y + connect \$121 $and$libresoc.v:198163$14190_Y + connect \$123 $and$libresoc.v:198164$14191_Y + connect \$13 $not$libresoc.v:198165$14192_Y + connect \$15 $and$libresoc.v:198166$14193_Y + connect \$17 $not$libresoc.v:198167$14194_Y + connect \$19 $and$libresoc.v:198168$14195_Y + connect \$21 $and$libresoc.v:198169$14196_Y + connect \$25 $not$libresoc.v:198170$14197_Y + connect \$27 $and$libresoc.v:198171$14198_Y + connect \$24 $reduce_or$libresoc.v:198172$14199_Y + connect \$23 $not$libresoc.v:198173$14200_Y + connect \$31 $and$libresoc.v:198174$14201_Y + connect \$33 $reduce_or$libresoc.v:198175$14202_Y + connect \$35 $reduce_or$libresoc.v:198176$14203_Y + connect \$37 $or$libresoc.v:198177$14204_Y + connect \$3 $and$libresoc.v:198178$14205_Y + connect \$39 $not$libresoc.v:198179$14206_Y + connect \$41 $and$libresoc.v:198180$14207_Y + connect \$43 $and$libresoc.v:198181$14208_Y + connect \$45 $eq$libresoc.v:198182$14209_Y + connect \$47 $and$libresoc.v:198183$14210_Y + connect \$49 $eq$libresoc.v:198184$14211_Y + connect \$51 $and$libresoc.v:198185$14212_Y + connect \$53 $and$libresoc.v:198186$14213_Y + connect \$55 $and$libresoc.v:198187$14214_Y + connect \$57 $or$libresoc.v:198188$14215_Y + connect \$59 $or$libresoc.v:198189$14216_Y + connect \$61 $or$libresoc.v:198190$14217_Y + connect \$63 $or$libresoc.v:198191$14218_Y + connect \$65 $and$libresoc.v:198192$14219_Y + connect \$67 $and$libresoc.v:198193$14220_Y + connect \$6 $not$libresoc.v:198194$14221_Y + connect \$69 $or$libresoc.v:198195$14222_Y + connect \$71 $and$libresoc.v:198196$14223_Y + connect \$73 $and$libresoc.v:198197$14224_Y + connect \$75 $and$libresoc.v:198198$14225_Y + connect \$77 $and$libresoc.v:198199$14226_Y + connect \$79 $and$libresoc.v:198200$14227_Y + connect \$81 $ternary$libresoc.v:198201$14228_Y + connect \$83 $ternary$libresoc.v:198202$14229_Y + connect \$85 $ternary$libresoc.v:198203$14230_Y + connect \$87 $ternary$libresoc.v:198204$14231_Y + connect \$8 $or$libresoc.v:198205$14232_Y + connect \$89 $and$libresoc.v:198206$14233_Y + connect \$91 $and$libresoc.v:198207$14234_Y + connect \$93 $and$libresoc.v:198208$14235_Y + connect \$95 $and$libresoc.v:198209$14236_Y + connect \$97 $not$libresoc.v:198210$14237_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -411348,37 +416006,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:195708.1-195766.10" +attribute \src "libresoc.v:198744.1-198802.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:195709.7-195709.20" + attribute \src "libresoc.v:198745.7-198745.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195754.3-195762.6" - wire $0\q_int$next[0:0]$14327 - attribute \src "libresoc.v:195752.3-195753.27" + attribute \src "libresoc.v:198790.3-198798.6" + wire $0\q_int$next[0:0]$14441 + attribute \src "libresoc.v:198788.3-198789.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:195754.3-195762.6" - wire $1\q_int$next[0:0]$14328 - attribute \src "libresoc.v:195731.7-195731.19" + attribute \src "libresoc.v:198790.3-198798.6" + wire $1\q_int$next[0:0]$14442 + attribute \src "libresoc.v:198767.7-198767.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:195744.17-195744.96" - wire $and$libresoc.v:195744$14317_Y - attribute \src "libresoc.v:195749.17-195749.96" - wire $and$libresoc.v:195749$14322_Y - attribute \src "libresoc.v:195746.18-195746.93" - wire $not$libresoc.v:195746$14319_Y - attribute \src "libresoc.v:195748.17-195748.92" - wire $not$libresoc.v:195748$14321_Y - attribute \src "libresoc.v:195751.17-195751.92" - wire $not$libresoc.v:195751$14324_Y - attribute \src "libresoc.v:195745.18-195745.98" - wire $or$libresoc.v:195745$14318_Y - attribute \src "libresoc.v:195747.18-195747.99" - wire $or$libresoc.v:195747$14320_Y - attribute \src "libresoc.v:195750.17-195750.97" - wire $or$libresoc.v:195750$14323_Y + attribute \src "libresoc.v:198780.17-198780.96" + wire $and$libresoc.v:198780$14431_Y + attribute \src "libresoc.v:198785.17-198785.96" + wire $and$libresoc.v:198785$14436_Y + attribute \src "libresoc.v:198782.18-198782.93" + wire $not$libresoc.v:198782$14433_Y + attribute \src "libresoc.v:198784.17-198784.92" + wire $not$libresoc.v:198784$14435_Y + attribute \src "libresoc.v:198787.17-198787.92" + wire $not$libresoc.v:198787$14438_Y + attribute \src "libresoc.v:198781.18-198781.98" + wire $or$libresoc.v:198781$14432_Y + attribute \src "libresoc.v:198783.18-198783.99" + wire $or$libresoc.v:198783$14434_Y + attribute \src "libresoc.v:198786.17-198786.97" + wire $or$libresoc.v:198786$14437_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -411395,11 +416053,11 @@ module \upd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:195709.7-195709.15" + attribute \src "libresoc.v:198745.7-198745.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -411416,7 +416074,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:195744$14317 + cell $and $and$libresoc.v:198780$14431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411424,10 +416082,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:195744$14317_Y + connect \Y $and$libresoc.v:198780$14431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:195749$14322 + cell $and $and$libresoc.v:198785$14436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411435,34 +416093,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:195749$14322_Y + connect \Y $and$libresoc.v:198785$14436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:195746$14319 + cell $not $not$libresoc.v:198782$14433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:195746$14319_Y + connect \Y $not$libresoc.v:198782$14433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:195748$14321 + cell $not $not$libresoc.v:198784$14435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:195748$14321_Y + connect \Y $not$libresoc.v:198784$14435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:195751$14324 + cell $not $not$libresoc.v:198787$14438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:195751$14324_Y + connect \Y $not$libresoc.v:198787$14438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:195745$14318 + cell $or $or$libresoc.v:198781$14432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411470,10 +416128,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:195745$14318_Y + connect \Y $or$libresoc.v:198781$14432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:195747$14320 + cell $or $or$libresoc.v:198783$14434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411481,10 +416139,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:195747$14320_Y + connect \Y $or$libresoc.v:198783$14434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:195750$14323 + cell $or $or$libresoc.v:198786$14437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411492,39 +416150,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:195750$14323_Y + connect \Y $or$libresoc.v:198786$14437_Y end - attribute \src "libresoc.v:195709.7-195709.20" - process $proc$libresoc.v:195709$14329 + attribute \src "libresoc.v:198745.7-198745.20" + process $proc$libresoc.v:198745$14443 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195731.7-195731.19" - process $proc$libresoc.v:195731$14330 + attribute \src "libresoc.v:198767.7-198767.19" + process $proc$libresoc.v:198767$14444 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:195752.3-195753.27" - process $proc$libresoc.v:195752$14325 + attribute \src "libresoc.v:198788.3-198789.27" + process $proc$libresoc.v:198788$14439 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:195754.3-195762.6" - process $proc$libresoc.v:195754$14326 + attribute \src "libresoc.v:198790.3-198798.6" + process $proc$libresoc.v:198790$14440 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14327 $1\q_int$next[0:0]$14328 - attribute \src "libresoc.v:195755.5-195755.29" + assign $0\q_int$next[0:0]$14441 $1\q_int$next[0:0]$14442 + attribute \src "libresoc.v:198791.5-198791.29" switch \initial - attribute \src "libresoc.v:195755.9-195755.17" + attribute \src "libresoc.v:198791.9-198791.17" case 1'1 case end @@ -411533,56 +416191,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14328 1'0 + assign $1\q_int$next[0:0]$14442 1'0 case - assign $1\q_int$next[0:0]$14328 \$5 + assign $1\q_int$next[0:0]$14442 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14327 + update \q_int$next $0\q_int$next[0:0]$14441 end - connect \$9 $and$libresoc.v:195744$14317_Y - connect \$11 $or$libresoc.v:195745$14318_Y - connect \$13 $not$libresoc.v:195746$14319_Y - connect \$15 $or$libresoc.v:195747$14320_Y - connect \$1 $not$libresoc.v:195748$14321_Y - connect \$3 $and$libresoc.v:195749$14322_Y - connect \$5 $or$libresoc.v:195750$14323_Y - connect \$7 $not$libresoc.v:195751$14324_Y + connect \$9 $and$libresoc.v:198780$14431_Y + connect \$11 $or$libresoc.v:198781$14432_Y + connect \$13 $not$libresoc.v:198782$14433_Y + connect \$15 $or$libresoc.v:198783$14434_Y + connect \$1 $not$libresoc.v:198784$14435_Y + connect \$3 $and$libresoc.v:198785$14436_Y + connect \$5 $or$libresoc.v:198786$14437_Y + connect \$7 $not$libresoc.v:198787$14438_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:195770.1-195828.10" +attribute \src "libresoc.v:198806.1-198864.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:195771.7-195771.20" + attribute \src "libresoc.v:198807.7-198807.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195816.3-195824.6" - wire $0\q_int$next[0:0]$14341 - attribute \src "libresoc.v:195814.3-195815.27" + attribute \src "libresoc.v:198852.3-198860.6" + wire $0\q_int$next[0:0]$14455 + attribute \src "libresoc.v:198850.3-198851.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:195816.3-195824.6" - wire $1\q_int$next[0:0]$14342 - attribute \src "libresoc.v:195793.7-195793.19" + attribute \src "libresoc.v:198852.3-198860.6" + wire $1\q_int$next[0:0]$14456 + attribute \src "libresoc.v:198829.7-198829.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:195806.17-195806.96" - wire $and$libresoc.v:195806$14331_Y - attribute \src "libresoc.v:195811.17-195811.96" - wire $and$libresoc.v:195811$14336_Y - attribute \src "libresoc.v:195808.18-195808.95" - wire $not$libresoc.v:195808$14333_Y - attribute \src "libresoc.v:195810.17-195810.94" - wire $not$libresoc.v:195810$14335_Y - attribute \src "libresoc.v:195813.17-195813.94" - wire $not$libresoc.v:195813$14338_Y - attribute \src "libresoc.v:195807.18-195807.100" - wire $or$libresoc.v:195807$14332_Y - attribute \src "libresoc.v:195809.18-195809.101" - wire $or$libresoc.v:195809$14334_Y - attribute \src "libresoc.v:195812.17-195812.99" - wire $or$libresoc.v:195812$14337_Y + attribute \src "libresoc.v:198842.17-198842.96" + wire $and$libresoc.v:198842$14445_Y + attribute \src "libresoc.v:198847.17-198847.96" + wire $and$libresoc.v:198847$14450_Y + attribute \src "libresoc.v:198844.18-198844.95" + wire $not$libresoc.v:198844$14447_Y + attribute \src "libresoc.v:198846.17-198846.94" + wire $not$libresoc.v:198846$14449_Y + attribute \src "libresoc.v:198849.17-198849.94" + wire $not$libresoc.v:198849$14452_Y + attribute \src "libresoc.v:198843.18-198843.100" + wire $or$libresoc.v:198843$14446_Y + attribute \src "libresoc.v:198845.18-198845.101" + wire $or$libresoc.v:198845$14448_Y + attribute \src "libresoc.v:198848.17-198848.99" + wire $or$libresoc.v:198848$14451_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -411599,11 +416257,11 @@ module \valid_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:195771.7-195771.15" + attribute \src "libresoc.v:198807.7-198807.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -411620,7 +416278,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:195806$14331 + cell $and $and$libresoc.v:198842$14445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411628,10 +416286,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:195806$14331_Y + connect \Y $and$libresoc.v:198842$14445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:195811$14336 + cell $and $and$libresoc.v:198847$14450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411639,34 +416297,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:195811$14336_Y + connect \Y $and$libresoc.v:198847$14450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:195808$14333 + cell $not $not$libresoc.v:198844$14447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:195808$14333_Y + connect \Y $not$libresoc.v:198844$14447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:195810$14335 + cell $not $not$libresoc.v:198846$14449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:195810$14335_Y + connect \Y $not$libresoc.v:198846$14449_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:195813$14338 + cell $not $not$libresoc.v:198849$14452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:195813$14338_Y + connect \Y $not$libresoc.v:198849$14452_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:195807$14332 + cell $or $or$libresoc.v:198843$14446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411674,10 +416332,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:195807$14332_Y + connect \Y $or$libresoc.v:198843$14446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:195809$14334 + cell $or $or$libresoc.v:198845$14448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411685,10 +416343,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:195809$14334_Y + connect \Y $or$libresoc.v:198845$14448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:195812$14337 + cell $or $or$libresoc.v:198848$14451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411696,39 +416354,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:195812$14337_Y + connect \Y $or$libresoc.v:198848$14451_Y end - attribute \src "libresoc.v:195771.7-195771.20" - process $proc$libresoc.v:195771$14343 + attribute \src "libresoc.v:198807.7-198807.20" + process $proc$libresoc.v:198807$14457 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195793.7-195793.19" - process $proc$libresoc.v:195793$14344 + attribute \src "libresoc.v:198829.7-198829.19" + process $proc$libresoc.v:198829$14458 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:195814.3-195815.27" - process $proc$libresoc.v:195814$14339 + attribute \src "libresoc.v:198850.3-198851.27" + process $proc$libresoc.v:198850$14453 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:195816.3-195824.6" - process $proc$libresoc.v:195816$14340 + attribute \src "libresoc.v:198852.3-198860.6" + process $proc$libresoc.v:198852$14454 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14341 $1\q_int$next[0:0]$14342 - attribute \src "libresoc.v:195817.5-195817.29" + assign $0\q_int$next[0:0]$14455 $1\q_int$next[0:0]$14456 + attribute \src "libresoc.v:198853.5-198853.29" switch \initial - attribute \src "libresoc.v:195817.9-195817.17" + attribute \src "libresoc.v:198853.9-198853.17" case 1'1 case end @@ -411737,56 +416395,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14342 1'0 + assign $1\q_int$next[0:0]$14456 1'0 case - assign $1\q_int$next[0:0]$14342 \$5 + assign $1\q_int$next[0:0]$14456 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14341 + update \q_int$next $0\q_int$next[0:0]$14455 end - connect \$9 $and$libresoc.v:195806$14331_Y - connect \$11 $or$libresoc.v:195807$14332_Y - connect \$13 $not$libresoc.v:195808$14333_Y - connect \$15 $or$libresoc.v:195809$14334_Y - connect \$1 $not$libresoc.v:195810$14335_Y - connect \$3 $and$libresoc.v:195811$14336_Y - connect \$5 $or$libresoc.v:195812$14337_Y - connect \$7 $not$libresoc.v:195813$14338_Y + connect \$9 $and$libresoc.v:198842$14445_Y + connect \$11 $or$libresoc.v:198843$14446_Y + connect \$13 $not$libresoc.v:198844$14447_Y + connect \$15 $or$libresoc.v:198845$14448_Y + connect \$1 $not$libresoc.v:198846$14449_Y + connect \$3 $and$libresoc.v:198847$14450_Y + connect \$5 $or$libresoc.v:198848$14451_Y + connect \$7 $not$libresoc.v:198849$14452_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:195832.1-195890.10" +attribute \src "libresoc.v:198868.1-198926.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:195833.7-195833.20" + attribute \src "libresoc.v:198869.7-198869.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195878.3-195886.6" - wire $0\q_int$next[0:0]$14355 - attribute \src "libresoc.v:195876.3-195877.27" + attribute \src "libresoc.v:198914.3-198922.6" + wire $0\q_int$next[0:0]$14469 + attribute \src "libresoc.v:198912.3-198913.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:195878.3-195886.6" - wire $1\q_int$next[0:0]$14356 - attribute \src "libresoc.v:195855.7-195855.19" + attribute \src "libresoc.v:198914.3-198922.6" + wire $1\q_int$next[0:0]$14470 + attribute \src "libresoc.v:198891.7-198891.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:195868.17-195868.96" - wire $and$libresoc.v:195868$14345_Y - attribute \src "libresoc.v:195873.17-195873.96" - wire $and$libresoc.v:195873$14350_Y - attribute \src "libresoc.v:195870.18-195870.93" - wire $not$libresoc.v:195870$14347_Y - attribute \src "libresoc.v:195872.17-195872.92" - wire $not$libresoc.v:195872$14349_Y - attribute \src "libresoc.v:195875.17-195875.92" - wire $not$libresoc.v:195875$14352_Y - attribute \src "libresoc.v:195869.18-195869.98" - wire $or$libresoc.v:195869$14346_Y - attribute \src "libresoc.v:195871.18-195871.99" - wire $or$libresoc.v:195871$14348_Y - attribute \src "libresoc.v:195874.17-195874.97" - wire $or$libresoc.v:195874$14351_Y + attribute \src "libresoc.v:198904.17-198904.96" + wire $and$libresoc.v:198904$14459_Y + attribute \src "libresoc.v:198909.17-198909.96" + wire $and$libresoc.v:198909$14464_Y + attribute \src "libresoc.v:198906.18-198906.93" + wire $not$libresoc.v:198906$14461_Y + attribute \src "libresoc.v:198908.17-198908.92" + wire $not$libresoc.v:198908$14463_Y + attribute \src "libresoc.v:198911.17-198911.92" + wire $not$libresoc.v:198911$14466_Y + attribute \src "libresoc.v:198905.18-198905.98" + wire $or$libresoc.v:198905$14460_Y + attribute \src "libresoc.v:198907.18-198907.99" + wire $or$libresoc.v:198907$14462_Y + attribute \src "libresoc.v:198910.17-198910.97" + wire $or$libresoc.v:198910$14465_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -411803,11 +416461,11 @@ module \wri_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst - attribute \src "libresoc.v:195833.7-195833.15" + attribute \src "libresoc.v:198869.7-198869.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -411824,7 +416482,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:195868$14345 + cell $and $and$libresoc.v:198904$14459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411832,10 +416490,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:195868$14345_Y + connect \Y $and$libresoc.v:198904$14459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:195873$14350 + cell $and $and$libresoc.v:198909$14464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411843,34 +416501,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:195873$14350_Y + connect \Y $and$libresoc.v:198909$14464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:195870$14347 + cell $not $not$libresoc.v:198906$14461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:195870$14347_Y + connect \Y $not$libresoc.v:198906$14461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:195872$14349 + cell $not $not$libresoc.v:198908$14463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:195872$14349_Y + connect \Y $not$libresoc.v:198908$14463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:195875$14352 + cell $not $not$libresoc.v:198911$14466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:195875$14352_Y + connect \Y $not$libresoc.v:198911$14466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:195869$14346 + cell $or $or$libresoc.v:198905$14460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411878,10 +416536,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:195869$14346_Y + connect \Y $or$libresoc.v:198905$14460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:195871$14348 + cell $or $or$libresoc.v:198907$14462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411889,10 +416547,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:195871$14348_Y + connect \Y $or$libresoc.v:198907$14462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:195874$14351 + cell $or $or$libresoc.v:198910$14465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -411900,39 +416558,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:195874$14351_Y + connect \Y $or$libresoc.v:198910$14465_Y end - attribute \src "libresoc.v:195833.7-195833.20" - process $proc$libresoc.v:195833$14357 + attribute \src "libresoc.v:198869.7-198869.20" + process $proc$libresoc.v:198869$14471 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195855.7-195855.19" - process $proc$libresoc.v:195855$14358 + attribute \src "libresoc.v:198891.7-198891.19" + process $proc$libresoc.v:198891$14472 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:195876.3-195877.27" - process $proc$libresoc.v:195876$14353 + attribute \src "libresoc.v:198912.3-198913.27" + process $proc$libresoc.v:198912$14467 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:195878.3-195886.6" - process $proc$libresoc.v:195878$14354 + attribute \src "libresoc.v:198914.3-198922.6" + process $proc$libresoc.v:198914$14468 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14355 $1\q_int$next[0:0]$14356 - attribute \src "libresoc.v:195879.5-195879.29" + assign $0\q_int$next[0:0]$14469 $1\q_int$next[0:0]$14470 + attribute \src "libresoc.v:198915.5-198915.29" switch \initial - attribute \src "libresoc.v:195879.9-195879.17" + attribute \src "libresoc.v:198915.9-198915.17" case 1'1 case end @@ -411941,54 +416599,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14356 1'0 + assign $1\q_int$next[0:0]$14470 1'0 case - assign $1\q_int$next[0:0]$14356 \$5 + assign $1\q_int$next[0:0]$14470 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14355 + update \q_int$next $0\q_int$next[0:0]$14469 end - connect \$9 $and$libresoc.v:195868$14345_Y - connect \$11 $or$libresoc.v:195869$14346_Y - connect \$13 $not$libresoc.v:195870$14347_Y - connect \$15 $or$libresoc.v:195871$14348_Y - connect \$1 $not$libresoc.v:195872$14349_Y - connect \$3 $and$libresoc.v:195873$14350_Y - connect \$5 $or$libresoc.v:195874$14351_Y - connect \$7 $not$libresoc.v:195875$14352_Y + connect \$9 $and$libresoc.v:198904$14459_Y + connect \$11 $or$libresoc.v:198905$14460_Y + connect \$13 $not$libresoc.v:198906$14461_Y + connect \$15 $or$libresoc.v:198907$14462_Y + connect \$1 $not$libresoc.v:198908$14463_Y + connect \$3 $and$libresoc.v:198909$14464_Y + connect \$5 $or$libresoc.v:198910$14465_Y + connect \$7 $not$libresoc.v:198911$14466_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:195894.1-195960.10" +attribute \src "libresoc.v:198930.1-198996.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:195939.17-195939.91" - wire $not$libresoc.v:195939$14359_Y - attribute \src "libresoc.v:195941.18-195941.93" - wire $not$libresoc.v:195941$14361_Y - attribute \src "libresoc.v:195943.18-195943.93" - wire $not$libresoc.v:195943$14363_Y - attribute \src "libresoc.v:195944.17-195944.89" - wire width 6 $not$libresoc.v:195944$14364_Y - attribute \src "libresoc.v:195946.18-195946.93" - wire $not$libresoc.v:195946$14366_Y - attribute \src "libresoc.v:195949.17-195949.91" - wire $not$libresoc.v:195949$14369_Y - attribute \src "libresoc.v:195940.18-195940.106" - wire $reduce_or$libresoc.v:195940$14360_Y - attribute \src "libresoc.v:195942.18-195942.106" - wire $reduce_or$libresoc.v:195942$14362_Y - attribute \src "libresoc.v:195945.18-195945.106" - wire $reduce_or$libresoc.v:195945$14365_Y - attribute \src "libresoc.v:195947.18-195947.90" - wire $reduce_or$libresoc.v:195947$14367_Y - attribute \src "libresoc.v:195948.17-195948.103" - wire $reduce_or$libresoc.v:195948$14368_Y - attribute \src "libresoc.v:195950.17-195950.105" - wire $reduce_or$libresoc.v:195950$14370_Y + attribute \src "libresoc.v:198975.17-198975.91" + wire $not$libresoc.v:198975$14473_Y + attribute \src "libresoc.v:198977.18-198977.93" + wire $not$libresoc.v:198977$14475_Y + attribute \src "libresoc.v:198979.18-198979.93" + wire $not$libresoc.v:198979$14477_Y + attribute \src "libresoc.v:198980.17-198980.89" + wire width 6 $not$libresoc.v:198980$14478_Y + attribute \src "libresoc.v:198982.18-198982.93" + wire $not$libresoc.v:198982$14480_Y + attribute \src "libresoc.v:198985.17-198985.91" + wire $not$libresoc.v:198985$14483_Y + attribute \src "libresoc.v:198976.18-198976.106" + wire $reduce_or$libresoc.v:198976$14474_Y + attribute \src "libresoc.v:198978.18-198978.106" + wire $reduce_or$libresoc.v:198978$14476_Y + attribute \src "libresoc.v:198981.18-198981.106" + wire $reduce_or$libresoc.v:198981$14479_Y + attribute \src "libresoc.v:198983.18-198983.90" + wire $reduce_or$libresoc.v:198983$14481_Y + attribute \src "libresoc.v:198984.17-198984.103" + wire $reduce_or$libresoc.v:198984$14482_Y + attribute \src "libresoc.v:198986.17-198986.105" + wire $reduce_or$libresoc.v:198986$14484_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -412034,113 +416692,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:195939$14359 + cell $not $not$libresoc.v:198975$14473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:195939$14359_Y + connect \Y $not$libresoc.v:198975$14473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:195941$14361 + cell $not $not$libresoc.v:198977$14475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:195941$14361_Y + connect \Y $not$libresoc.v:198977$14475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:195943$14363 + cell $not $not$libresoc.v:198979$14477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:195943$14363_Y + connect \Y $not$libresoc.v:198979$14477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:195944$14364 + cell $not $not$libresoc.v:198980$14478 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:195944$14364_Y + connect \Y $not$libresoc.v:198980$14478_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:195946$14366 + cell $not $not$libresoc.v:198982$14480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:195946$14366_Y + connect \Y $not$libresoc.v:198982$14480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:195949$14369 + cell $not $not$libresoc.v:198985$14483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:195949$14369_Y + connect \Y $not$libresoc.v:198985$14483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:195940$14360 + cell $reduce_or $reduce_or$libresoc.v:198976$14474 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:195940$14360_Y + connect \Y $reduce_or$libresoc.v:198976$14474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:195942$14362 + cell $reduce_or $reduce_or$libresoc.v:198978$14476 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:195942$14362_Y + connect \Y $reduce_or$libresoc.v:198978$14476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:195945$14365 + cell $reduce_or $reduce_or$libresoc.v:198981$14479 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:195945$14365_Y + connect \Y $reduce_or$libresoc.v:198981$14479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:195947$14367 + cell $reduce_or $reduce_or$libresoc.v:198983$14481 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:195947$14367_Y + connect \Y $reduce_or$libresoc.v:198983$14481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:195948$14368 + cell $reduce_or $reduce_or$libresoc.v:198984$14482 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:195948$14368_Y + connect \Y $reduce_or$libresoc.v:198984$14482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:195950$14370 + cell $reduce_or $reduce_or$libresoc.v:198986$14484 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:195950$14370_Y - end - connect \$7 $not$libresoc.v:195939$14359_Y - connect \$12 $reduce_or$libresoc.v:195940$14360_Y - connect \$11 $not$libresoc.v:195941$14361_Y - connect \$16 $reduce_or$libresoc.v:195942$14362_Y - connect \$15 $not$libresoc.v:195943$14363_Y - connect \$1 $not$libresoc.v:195944$14364_Y - connect \$20 $reduce_or$libresoc.v:195945$14365_Y - connect \$19 $not$libresoc.v:195946$14366_Y - connect \$23 $reduce_or$libresoc.v:195947$14367_Y - connect \$4 $reduce_or$libresoc.v:195948$14368_Y - connect \$3 $not$libresoc.v:195949$14369_Y - connect \$8 $reduce_or$libresoc.v:195950$14370_Y + connect \Y $reduce_or$libresoc.v:198986$14484_Y + end + connect \$7 $not$libresoc.v:198975$14473_Y + connect \$12 $reduce_or$libresoc.v:198976$14474_Y + connect \$11 $not$libresoc.v:198977$14475_Y + connect \$16 $reduce_or$libresoc.v:198978$14476_Y + connect \$15 $not$libresoc.v:198979$14477_Y + connect \$1 $not$libresoc.v:198980$14478_Y + connect \$20 $reduce_or$libresoc.v:198981$14479_Y + connect \$19 $not$libresoc.v:198982$14480_Y + connect \$23 $reduce_or$libresoc.v:198983$14481_Y + connect \$4 $reduce_or$libresoc.v:198984$14482_Y + connect \$3 $not$libresoc.v:198985$14483_Y + connect \$8 $reduce_or$libresoc.v:198986$14484_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -412151,15 +416809,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:195964.1-195985.10" +attribute \src "libresoc.v:199000.1-199021.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:195979.17-195979.89" - wire $not$libresoc.v:195979$14371_Y - attribute \src "libresoc.v:195980.17-195980.89" - wire $reduce_or$libresoc.v:195980$14372_Y + attribute \src "libresoc.v:199015.17-199015.89" + wire $not$libresoc.v:199015$14485_Y + attribute \src "libresoc.v:199016.17-199016.89" + wire $reduce_or$libresoc.v:199016$14486_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -412175,53 +416833,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:195979$14371 + cell $not $not$libresoc.v:199015$14485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:195979$14371_Y + connect \Y $not$libresoc.v:199015$14485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:195980$14372 + cell $reduce_or $reduce_or$libresoc.v:199016$14486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:195980$14372_Y + connect \Y $reduce_or$libresoc.v:199016$14486_Y end - connect \$1 $not$libresoc.v:195979$14371_Y - connect \$3 $reduce_or$libresoc.v:195980$14372_Y + connect \$1 $not$libresoc.v:199015$14485_Y + connect \$3 $reduce_or$libresoc.v:199016$14486_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:195989.1-196046.10" +attribute \src "libresoc.v:199025.1-199082.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:196028.17-196028.91" - wire $not$libresoc.v:196028$14373_Y - attribute \src "libresoc.v:196030.18-196030.93" - wire $not$libresoc.v:196030$14375_Y - attribute \src "libresoc.v:196032.18-196032.93" - wire $not$libresoc.v:196032$14377_Y - attribute \src "libresoc.v:196033.17-196033.89" - wire width 5 $not$libresoc.v:196033$14378_Y - attribute \src "libresoc.v:196036.17-196036.91" - wire $not$libresoc.v:196036$14381_Y - attribute \src "libresoc.v:196029.18-196029.106" - wire $reduce_or$libresoc.v:196029$14374_Y - attribute \src "libresoc.v:196031.18-196031.106" - wire $reduce_or$libresoc.v:196031$14376_Y - attribute \src "libresoc.v:196034.18-196034.90" - wire $reduce_or$libresoc.v:196034$14379_Y - attribute \src "libresoc.v:196035.17-196035.103" - wire $reduce_or$libresoc.v:196035$14380_Y - attribute \src "libresoc.v:196037.17-196037.105" - wire $reduce_or$libresoc.v:196037$14382_Y + attribute \src "libresoc.v:199064.17-199064.91" + wire $not$libresoc.v:199064$14487_Y + attribute \src "libresoc.v:199066.18-199066.93" + wire $not$libresoc.v:199066$14489_Y + attribute \src "libresoc.v:199068.18-199068.93" + wire $not$libresoc.v:199068$14491_Y + attribute \src "libresoc.v:199069.17-199069.89" + wire width 5 $not$libresoc.v:199069$14492_Y + attribute \src "libresoc.v:199072.17-199072.91" + wire $not$libresoc.v:199072$14495_Y + attribute \src "libresoc.v:199065.18-199065.106" + wire $reduce_or$libresoc.v:199065$14488_Y + attribute \src "libresoc.v:199067.18-199067.106" + wire $reduce_or$libresoc.v:199067$14490_Y + attribute \src "libresoc.v:199070.18-199070.90" + wire $reduce_or$libresoc.v:199070$14493_Y + attribute \src "libresoc.v:199071.17-199071.103" + wire $reduce_or$libresoc.v:199071$14494_Y + attribute \src "libresoc.v:199073.17-199073.105" + wire $reduce_or$libresoc.v:199073$14496_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -412261,95 +416919,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196028$14373 + cell $not $not$libresoc.v:199064$14487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:196028$14373_Y + connect \Y $not$libresoc.v:199064$14487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196030$14375 + cell $not $not$libresoc.v:199066$14489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:196030$14375_Y + connect \Y $not$libresoc.v:199066$14489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196032$14377 + cell $not $not$libresoc.v:199068$14491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:196032$14377_Y + connect \Y $not$libresoc.v:199068$14491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:196033$14378 + cell $not $not$libresoc.v:199069$14492 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:196033$14378_Y + connect \Y $not$libresoc.v:199069$14492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196036$14381 + cell $not $not$libresoc.v:199072$14495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:196036$14381_Y + connect \Y $not$libresoc.v:199072$14495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196029$14374 + cell $reduce_or $reduce_or$libresoc.v:199065$14488 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:196029$14374_Y + connect \Y $reduce_or$libresoc.v:199065$14488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196031$14376 + cell $reduce_or $reduce_or$libresoc.v:199067$14490 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:196031$14376_Y + connect \Y $reduce_or$libresoc.v:199067$14490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:196034$14379 + cell $reduce_or $reduce_or$libresoc.v:199070$14493 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:196034$14379_Y + connect \Y $reduce_or$libresoc.v:199070$14493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196035$14380 + cell $reduce_or $reduce_or$libresoc.v:199071$14494 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:196035$14380_Y + connect \Y $reduce_or$libresoc.v:199071$14494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196037$14382 + cell $reduce_or $reduce_or$libresoc.v:199073$14496 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:196037$14382_Y - end - connect \$7 $not$libresoc.v:196028$14373_Y - connect \$12 $reduce_or$libresoc.v:196029$14374_Y - connect \$11 $not$libresoc.v:196030$14375_Y - connect \$16 $reduce_or$libresoc.v:196031$14376_Y - connect \$15 $not$libresoc.v:196032$14377_Y - connect \$1 $not$libresoc.v:196033$14378_Y - connect \$19 $reduce_or$libresoc.v:196034$14379_Y - connect \$4 $reduce_or$libresoc.v:196035$14380_Y - connect \$3 $not$libresoc.v:196036$14381_Y - connect \$8 $reduce_or$libresoc.v:196037$14382_Y + connect \Y $reduce_or$libresoc.v:199073$14496_Y + end + connect \$7 $not$libresoc.v:199064$14487_Y + connect \$12 $reduce_or$libresoc.v:199065$14488_Y + connect \$11 $not$libresoc.v:199066$14489_Y + connect \$16 $reduce_or$libresoc.v:199067$14490_Y + connect \$15 $not$libresoc.v:199068$14491_Y + connect \$1 $not$libresoc.v:199069$14492_Y + connect \$19 $reduce_or$libresoc.v:199070$14493_Y + connect \$4 $reduce_or$libresoc.v:199071$14494_Y + connect \$3 $not$libresoc.v:199072$14495_Y + connect \$8 $reduce_or$libresoc.v:199073$14496_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -412359,51 +417017,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:196050.1-196152.10" +attribute \src "libresoc.v:199086.1-199188.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:196119.17-196119.91" - wire $not$libresoc.v:196119$14383_Y - attribute \src "libresoc.v:196121.18-196121.93" - wire $not$libresoc.v:196121$14385_Y - attribute \src "libresoc.v:196123.18-196123.93" - wire $not$libresoc.v:196123$14387_Y - attribute \src "libresoc.v:196124.17-196124.89" - wire width 10 $not$libresoc.v:196124$14388_Y - attribute \src "libresoc.v:196126.18-196126.93" - wire $not$libresoc.v:196126$14390_Y - attribute \src "libresoc.v:196128.18-196128.93" - wire $not$libresoc.v:196128$14392_Y - attribute \src "libresoc.v:196130.18-196130.93" - wire $not$libresoc.v:196130$14394_Y - attribute \src "libresoc.v:196132.18-196132.93" - wire $not$libresoc.v:196132$14396_Y - attribute \src "libresoc.v:196134.18-196134.93" - wire $not$libresoc.v:196134$14398_Y - attribute \src "libresoc.v:196137.17-196137.91" - wire $not$libresoc.v:196137$14401_Y - attribute \src "libresoc.v:196120.18-196120.106" - wire $reduce_or$libresoc.v:196120$14384_Y - attribute \src "libresoc.v:196122.18-196122.106" - wire $reduce_or$libresoc.v:196122$14386_Y - attribute \src "libresoc.v:196125.18-196125.106" - wire $reduce_or$libresoc.v:196125$14389_Y - attribute \src "libresoc.v:196127.18-196127.106" - wire $reduce_or$libresoc.v:196127$14391_Y - attribute \src "libresoc.v:196129.18-196129.106" - wire $reduce_or$libresoc.v:196129$14393_Y - attribute \src "libresoc.v:196131.18-196131.106" - wire $reduce_or$libresoc.v:196131$14395_Y - attribute \src "libresoc.v:196133.18-196133.106" - wire $reduce_or$libresoc.v:196133$14397_Y - attribute \src "libresoc.v:196135.18-196135.90" - wire $reduce_or$libresoc.v:196135$14399_Y - attribute \src "libresoc.v:196136.17-196136.103" - wire $reduce_or$libresoc.v:196136$14400_Y - attribute \src "libresoc.v:196138.17-196138.105" - wire $reduce_or$libresoc.v:196138$14402_Y + attribute \src "libresoc.v:199155.17-199155.91" + wire $not$libresoc.v:199155$14497_Y + attribute \src "libresoc.v:199157.18-199157.93" + wire $not$libresoc.v:199157$14499_Y + attribute \src "libresoc.v:199159.18-199159.93" + wire $not$libresoc.v:199159$14501_Y + attribute \src "libresoc.v:199160.17-199160.89" + wire width 10 $not$libresoc.v:199160$14502_Y + attribute \src "libresoc.v:199162.18-199162.93" + wire $not$libresoc.v:199162$14504_Y + attribute \src "libresoc.v:199164.18-199164.93" + wire $not$libresoc.v:199164$14506_Y + attribute \src "libresoc.v:199166.18-199166.93" + wire $not$libresoc.v:199166$14508_Y + attribute \src "libresoc.v:199168.18-199168.93" + wire $not$libresoc.v:199168$14510_Y + attribute \src "libresoc.v:199170.18-199170.93" + wire $not$libresoc.v:199170$14512_Y + attribute \src "libresoc.v:199173.17-199173.91" + wire $not$libresoc.v:199173$14515_Y + attribute \src "libresoc.v:199156.18-199156.106" + wire $reduce_or$libresoc.v:199156$14498_Y + attribute \src "libresoc.v:199158.18-199158.106" + wire $reduce_or$libresoc.v:199158$14500_Y + attribute \src "libresoc.v:199161.18-199161.106" + wire $reduce_or$libresoc.v:199161$14503_Y + attribute \src "libresoc.v:199163.18-199163.106" + wire $reduce_or$libresoc.v:199163$14505_Y + attribute \src "libresoc.v:199165.18-199165.106" + wire $reduce_or$libresoc.v:199165$14507_Y + attribute \src "libresoc.v:199167.18-199167.106" + wire $reduce_or$libresoc.v:199167$14509_Y + attribute \src "libresoc.v:199169.18-199169.106" + wire $reduce_or$libresoc.v:199169$14511_Y + attribute \src "libresoc.v:199171.18-199171.90" + wire $reduce_or$libresoc.v:199171$14513_Y + attribute \src "libresoc.v:199172.17-199172.103" + wire $reduce_or$libresoc.v:199172$14514_Y + attribute \src "libresoc.v:199174.17-199174.105" + wire $reduce_or$libresoc.v:199174$14516_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -412473,185 +417131,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196119$14383 + cell $not $not$libresoc.v:199155$14497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:196119$14383_Y + connect \Y $not$libresoc.v:199155$14497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196121$14385 + cell $not $not$libresoc.v:199157$14499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:196121$14385_Y + connect \Y $not$libresoc.v:199157$14499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196123$14387 + cell $not $not$libresoc.v:199159$14501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:196123$14387_Y + connect \Y $not$libresoc.v:199159$14501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:196124$14388 + cell $not $not$libresoc.v:199160$14502 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:196124$14388_Y + connect \Y $not$libresoc.v:199160$14502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196126$14390 + cell $not $not$libresoc.v:199162$14504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:196126$14390_Y + connect \Y $not$libresoc.v:199162$14504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196128$14392 + cell $not $not$libresoc.v:199164$14506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:196128$14392_Y + connect \Y $not$libresoc.v:199164$14506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196130$14394 + cell $not $not$libresoc.v:199166$14508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:196130$14394_Y + connect \Y $not$libresoc.v:199166$14508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196132$14396 + cell $not $not$libresoc.v:199168$14510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:196132$14396_Y + connect \Y $not$libresoc.v:199168$14510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196134$14398 + cell $not $not$libresoc.v:199170$14512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:196134$14398_Y + connect \Y $not$libresoc.v:199170$14512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196137$14401 + cell $not $not$libresoc.v:199173$14515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:196137$14401_Y + connect \Y $not$libresoc.v:199173$14515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196120$14384 + cell $reduce_or $reduce_or$libresoc.v:199156$14498 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:196120$14384_Y + connect \Y $reduce_or$libresoc.v:199156$14498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196122$14386 + cell $reduce_or $reduce_or$libresoc.v:199158$14500 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:196122$14386_Y + connect \Y $reduce_or$libresoc.v:199158$14500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196125$14389 + cell $reduce_or $reduce_or$libresoc.v:199161$14503 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:196125$14389_Y + connect \Y $reduce_or$libresoc.v:199161$14503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196127$14391 + cell $reduce_or $reduce_or$libresoc.v:199163$14505 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:196127$14391_Y + connect \Y $reduce_or$libresoc.v:199163$14505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196129$14393 + cell $reduce_or $reduce_or$libresoc.v:199165$14507 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:196129$14393_Y + connect \Y $reduce_or$libresoc.v:199165$14507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196131$14395 + cell $reduce_or $reduce_or$libresoc.v:199167$14509 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:196131$14395_Y + connect \Y $reduce_or$libresoc.v:199167$14509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196133$14397 + cell $reduce_or $reduce_or$libresoc.v:199169$14511 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:196133$14397_Y + connect \Y $reduce_or$libresoc.v:199169$14511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:196135$14399 + cell $reduce_or $reduce_or$libresoc.v:199171$14513 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:196135$14399_Y + connect \Y $reduce_or$libresoc.v:199171$14513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196136$14400 + cell $reduce_or $reduce_or$libresoc.v:199172$14514 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:196136$14400_Y + connect \Y $reduce_or$libresoc.v:199172$14514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196138$14402 + cell $reduce_or $reduce_or$libresoc.v:199174$14516 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:196138$14402_Y - end - connect \$7 $not$libresoc.v:196119$14383_Y - connect \$12 $reduce_or$libresoc.v:196120$14384_Y - connect \$11 $not$libresoc.v:196121$14385_Y - connect \$16 $reduce_or$libresoc.v:196122$14386_Y - connect \$15 $not$libresoc.v:196123$14387_Y - connect \$1 $not$libresoc.v:196124$14388_Y - connect \$20 $reduce_or$libresoc.v:196125$14389_Y - connect \$19 $not$libresoc.v:196126$14390_Y - connect \$24 $reduce_or$libresoc.v:196127$14391_Y - connect \$23 $not$libresoc.v:196128$14392_Y - connect \$28 $reduce_or$libresoc.v:196129$14393_Y - connect \$27 $not$libresoc.v:196130$14394_Y - connect \$32 $reduce_or$libresoc.v:196131$14395_Y - connect \$31 $not$libresoc.v:196132$14396_Y - connect \$36 $reduce_or$libresoc.v:196133$14397_Y - connect \$35 $not$libresoc.v:196134$14398_Y - connect \$39 $reduce_or$libresoc.v:196135$14399_Y - connect \$4 $reduce_or$libresoc.v:196136$14400_Y - connect \$3 $not$libresoc.v:196137$14401_Y - connect \$8 $reduce_or$libresoc.v:196138$14402_Y + connect \Y $reduce_or$libresoc.v:199174$14516_Y + end + connect \$7 $not$libresoc.v:199155$14497_Y + connect \$12 $reduce_or$libresoc.v:199156$14498_Y + connect \$11 $not$libresoc.v:199157$14499_Y + connect \$16 $reduce_or$libresoc.v:199158$14500_Y + connect \$15 $not$libresoc.v:199159$14501_Y + connect \$1 $not$libresoc.v:199160$14502_Y + connect \$20 $reduce_or$libresoc.v:199161$14503_Y + connect \$19 $not$libresoc.v:199162$14504_Y + connect \$24 $reduce_or$libresoc.v:199163$14505_Y + connect \$23 $not$libresoc.v:199164$14506_Y + connect \$28 $reduce_or$libresoc.v:199165$14507_Y + connect \$27 $not$libresoc.v:199166$14508_Y + connect \$32 $reduce_or$libresoc.v:199167$14509_Y + connect \$31 $not$libresoc.v:199168$14510_Y + connect \$36 $reduce_or$libresoc.v:199169$14511_Y + connect \$35 $not$libresoc.v:199170$14512_Y + connect \$39 $reduce_or$libresoc.v:199171$14513_Y + connect \$4 $reduce_or$libresoc.v:199172$14514_Y + connect \$3 $not$libresoc.v:199173$14515_Y + connect \$8 $reduce_or$libresoc.v:199174$14516_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -412666,15 +417324,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:196156.1-196177.10" +attribute \src "libresoc.v:199192.1-199213.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:196171.17-196171.89" - wire $not$libresoc.v:196171$14403_Y - attribute \src "libresoc.v:196172.17-196172.89" - wire $reduce_or$libresoc.v:196172$14404_Y + attribute \src "libresoc.v:199207.17-199207.89" + wire $not$libresoc.v:199207$14517_Y + attribute \src "libresoc.v:199208.17-199208.89" + wire $reduce_or$libresoc.v:199208$14518_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -412690,37 +417348,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:196171$14403 + cell $not $not$libresoc.v:199207$14517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:196171$14403_Y + connect \Y $not$libresoc.v:199207$14517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:196172$14404 + cell $reduce_or $reduce_or$libresoc.v:199208$14518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:196172$14404_Y + connect \Y $reduce_or$libresoc.v:199208$14518_Y end - connect \$1 $not$libresoc.v:196171$14403_Y - connect \$3 $reduce_or$libresoc.v:196172$14404_Y + connect \$1 $not$libresoc.v:199207$14517_Y + connect \$3 $reduce_or$libresoc.v:199208$14518_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:196181.1-196202.10" +attribute \src "libresoc.v:199217.1-199238.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:196196.17-196196.89" - wire $not$libresoc.v:196196$14405_Y - attribute \src "libresoc.v:196197.17-196197.89" - wire $reduce_or$libresoc.v:196197$14406_Y + attribute \src "libresoc.v:199232.17-199232.89" + wire $not$libresoc.v:199232$14519_Y + attribute \src "libresoc.v:199233.17-199233.89" + wire $reduce_or$libresoc.v:199233$14520_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -412736,41 +417394,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:196196$14405 + cell $not $not$libresoc.v:199232$14519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:196196$14405_Y + connect \Y $not$libresoc.v:199232$14519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:196197$14406 + cell $reduce_or $reduce_or$libresoc.v:199233$14520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:196197$14406_Y + connect \Y $reduce_or$libresoc.v:199233$14520_Y end - connect \$1 $not$libresoc.v:196196$14405_Y - connect \$3 $reduce_or$libresoc.v:196197$14406_Y + connect \$1 $not$libresoc.v:199232$14519_Y + connect \$3 $reduce_or$libresoc.v:199233$14520_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:196206.1-196236.10" +attribute \src "libresoc.v:199242.1-199272.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:196227.17-196227.89" - wire width 2 $not$libresoc.v:196227$14407_Y - attribute \src "libresoc.v:196229.17-196229.91" - wire $not$libresoc.v:196229$14409_Y - attribute \src "libresoc.v:196228.17-196228.103" - wire $reduce_or$libresoc.v:196228$14408_Y - attribute \src "libresoc.v:196230.17-196230.89" - wire $reduce_or$libresoc.v:196230$14410_Y + attribute \src "libresoc.v:199263.17-199263.89" + wire width 2 $not$libresoc.v:199263$14521_Y + attribute \src "libresoc.v:199265.17-199265.91" + wire $not$libresoc.v:199265$14523_Y + attribute \src "libresoc.v:199264.17-199264.103" + wire $reduce_or$libresoc.v:199264$14522_Y + attribute \src "libresoc.v:199266.17-199266.89" + wire $reduce_or$libresoc.v:199266$14524_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -412792,64 +417450,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:196227$14407 + cell $not $not$libresoc.v:199263$14521 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:196227$14407_Y + connect \Y $not$libresoc.v:199263$14521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196229$14409 + cell $not $not$libresoc.v:199265$14523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:196229$14409_Y + connect \Y $not$libresoc.v:199265$14523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196228$14408 + cell $reduce_or $reduce_or$libresoc.v:199264$14522 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:196228$14408_Y + connect \Y $reduce_or$libresoc.v:199264$14522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:196230$14410 + cell $reduce_or $reduce_or$libresoc.v:199266$14524 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:196230$14410_Y + connect \Y $reduce_or$libresoc.v:199266$14524_Y end - connect \$1 $not$libresoc.v:196227$14407_Y - connect \$4 $reduce_or$libresoc.v:196228$14408_Y - connect \$3 $not$libresoc.v:196229$14409_Y - connect \$7 $reduce_or$libresoc.v:196230$14410_Y + connect \$1 $not$libresoc.v:199263$14521_Y + connect \$4 $reduce_or$libresoc.v:199264$14522_Y + connect \$3 $not$libresoc.v:199265$14523_Y + connect \$7 $reduce_or$libresoc.v:199266$14524_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:196240.1-196279.10" +attribute \src "libresoc.v:199276.1-199315.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:196267.17-196267.91" - wire $not$libresoc.v:196267$14411_Y - attribute \src "libresoc.v:196269.17-196269.89" - wire width 3 $not$libresoc.v:196269$14413_Y - attribute \src "libresoc.v:196271.17-196271.91" - wire $not$libresoc.v:196271$14415_Y - attribute \src "libresoc.v:196268.18-196268.90" - wire $reduce_or$libresoc.v:196268$14412_Y - attribute \src "libresoc.v:196270.17-196270.103" - wire $reduce_or$libresoc.v:196270$14414_Y - attribute \src "libresoc.v:196272.17-196272.105" - wire $reduce_or$libresoc.v:196272$14416_Y + attribute \src "libresoc.v:199303.17-199303.91" + wire $not$libresoc.v:199303$14525_Y + attribute \src "libresoc.v:199305.17-199305.89" + wire width 3 $not$libresoc.v:199305$14527_Y + attribute \src "libresoc.v:199307.17-199307.91" + wire $not$libresoc.v:199307$14529_Y + attribute \src "libresoc.v:199304.18-199304.90" + wire $reduce_or$libresoc.v:199304$14526_Y + attribute \src "libresoc.v:199306.17-199306.103" + wire $reduce_or$libresoc.v:199306$14528_Y + attribute \src "libresoc.v:199308.17-199308.105" + wire $reduce_or$libresoc.v:199308$14530_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -412877,59 +417535,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196267$14411 + cell $not $not$libresoc.v:199303$14525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:196267$14411_Y + connect \Y $not$libresoc.v:199303$14525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:196269$14413 + cell $not $not$libresoc.v:199305$14527 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:196269$14413_Y + connect \Y $not$libresoc.v:199305$14527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196271$14415 + cell $not $not$libresoc.v:199307$14529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:196271$14415_Y + connect \Y $not$libresoc.v:199307$14529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:196268$14412 + cell $reduce_or $reduce_or$libresoc.v:199304$14526 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:196268$14412_Y + connect \Y $reduce_or$libresoc.v:199304$14526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196270$14414 + cell $reduce_or $reduce_or$libresoc.v:199306$14528 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:196270$14414_Y + connect \Y $reduce_or$libresoc.v:199306$14528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196272$14416 + cell $reduce_or $reduce_or$libresoc.v:199308$14530 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:196272$14416_Y - end - connect \$7 $not$libresoc.v:196267$14411_Y - connect \$11 $reduce_or$libresoc.v:196268$14412_Y - connect \$1 $not$libresoc.v:196269$14413_Y - connect \$4 $reduce_or$libresoc.v:196270$14414_Y - connect \$3 $not$libresoc.v:196271$14415_Y - connect \$8 $reduce_or$libresoc.v:196272$14416_Y + connect \Y $reduce_or$libresoc.v:199308$14530_Y + end + connect \$7 $not$libresoc.v:199303$14525_Y + connect \$11 $reduce_or$libresoc.v:199304$14526_Y + connect \$1 $not$libresoc.v:199305$14527_Y + connect \$4 $reduce_or$libresoc.v:199306$14528_Y + connect \$3 $not$libresoc.v:199307$14529_Y + connect \$8 $reduce_or$libresoc.v:199308$14530_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -412937,27 +417595,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:196283.1-196331.10" +attribute \src "libresoc.v:199319.1-199367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:196316.17-196316.91" - wire $not$libresoc.v:196316$14417_Y - attribute \src "libresoc.v:196318.18-196318.93" - wire $not$libresoc.v:196318$14419_Y - attribute \src "libresoc.v:196320.17-196320.89" - wire width 4 $not$libresoc.v:196320$14421_Y - attribute \src "libresoc.v:196322.17-196322.91" - wire $not$libresoc.v:196322$14423_Y - attribute \src "libresoc.v:196317.18-196317.106" - wire $reduce_or$libresoc.v:196317$14418_Y - attribute \src "libresoc.v:196319.18-196319.90" - wire $reduce_or$libresoc.v:196319$14420_Y - attribute \src "libresoc.v:196321.17-196321.103" - wire $reduce_or$libresoc.v:196321$14422_Y - attribute \src "libresoc.v:196323.17-196323.105" - wire $reduce_or$libresoc.v:196323$14424_Y + attribute \src "libresoc.v:199352.17-199352.91" + wire $not$libresoc.v:199352$14531_Y + attribute \src "libresoc.v:199354.18-199354.93" + wire $not$libresoc.v:199354$14533_Y + attribute \src "libresoc.v:199356.17-199356.89" + wire width 4 $not$libresoc.v:199356$14535_Y + attribute \src "libresoc.v:199358.17-199358.91" + wire $not$libresoc.v:199358$14537_Y + attribute \src "libresoc.v:199353.18-199353.106" + wire $reduce_or$libresoc.v:199353$14532_Y + attribute \src "libresoc.v:199355.18-199355.90" + wire $reduce_or$libresoc.v:199355$14534_Y + attribute \src "libresoc.v:199357.17-199357.103" + wire $reduce_or$libresoc.v:199357$14536_Y + attribute \src "libresoc.v:199359.17-199359.105" + wire $reduce_or$libresoc.v:199359$14538_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -412991,77 +417649,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196316$14417 + cell $not $not$libresoc.v:199352$14531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:196316$14417_Y + connect \Y $not$libresoc.v:199352$14531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196318$14419 + cell $not $not$libresoc.v:199354$14533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:196318$14419_Y + connect \Y $not$libresoc.v:199354$14533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:196320$14421 + cell $not $not$libresoc.v:199356$14535 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:196320$14421_Y + connect \Y $not$libresoc.v:199356$14535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196322$14423 + cell $not $not$libresoc.v:199358$14537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:196322$14423_Y + connect \Y $not$libresoc.v:199358$14537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196317$14418 + cell $reduce_or $reduce_or$libresoc.v:199353$14532 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:196317$14418_Y + connect \Y $reduce_or$libresoc.v:199353$14532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:196319$14420 + cell $reduce_or $reduce_or$libresoc.v:199355$14534 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:196319$14420_Y + connect \Y $reduce_or$libresoc.v:199355$14534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196321$14422 + cell $reduce_or $reduce_or$libresoc.v:199357$14536 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:196321$14422_Y + connect \Y $reduce_or$libresoc.v:199357$14536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196323$14424 + cell $reduce_or $reduce_or$libresoc.v:199359$14538 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:196323$14424_Y - end - connect \$7 $not$libresoc.v:196316$14417_Y - connect \$12 $reduce_or$libresoc.v:196317$14418_Y - connect \$11 $not$libresoc.v:196318$14419_Y - connect \$15 $reduce_or$libresoc.v:196319$14420_Y - connect \$1 $not$libresoc.v:196320$14421_Y - connect \$4 $reduce_or$libresoc.v:196321$14422_Y - connect \$3 $not$libresoc.v:196322$14423_Y - connect \$8 $reduce_or$libresoc.v:196323$14424_Y + connect \Y $reduce_or$libresoc.v:199359$14538_Y + end + connect \$7 $not$libresoc.v:199352$14531_Y + connect \$12 $reduce_or$libresoc.v:199353$14532_Y + connect \$11 $not$libresoc.v:199354$14533_Y + connect \$15 $reduce_or$libresoc.v:199355$14534_Y + connect \$1 $not$libresoc.v:199356$14535_Y + connect \$4 $reduce_or$libresoc.v:199357$14536_Y + connect \$3 $not$libresoc.v:199358$14537_Y + connect \$8 $reduce_or$libresoc.v:199359$14538_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -413070,27 +417728,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:196335.1-196383.10" +attribute \src "libresoc.v:199371.1-199419.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:196368.17-196368.91" - wire $not$libresoc.v:196368$14425_Y - attribute \src "libresoc.v:196370.18-196370.93" - wire $not$libresoc.v:196370$14427_Y - attribute \src "libresoc.v:196372.17-196372.89" - wire width 4 $not$libresoc.v:196372$14429_Y - attribute \src "libresoc.v:196374.17-196374.91" - wire $not$libresoc.v:196374$14431_Y - attribute \src "libresoc.v:196369.18-196369.106" - wire $reduce_or$libresoc.v:196369$14426_Y - attribute \src "libresoc.v:196371.18-196371.90" - wire $reduce_or$libresoc.v:196371$14428_Y - attribute \src "libresoc.v:196373.17-196373.103" - wire $reduce_or$libresoc.v:196373$14430_Y - attribute \src "libresoc.v:196375.17-196375.105" - wire $reduce_or$libresoc.v:196375$14432_Y + attribute \src "libresoc.v:199404.17-199404.91" + wire $not$libresoc.v:199404$14539_Y + attribute \src "libresoc.v:199406.18-199406.93" + wire $not$libresoc.v:199406$14541_Y + attribute \src "libresoc.v:199408.17-199408.89" + wire width 4 $not$libresoc.v:199408$14543_Y + attribute \src "libresoc.v:199410.17-199410.91" + wire $not$libresoc.v:199410$14545_Y + attribute \src "libresoc.v:199405.18-199405.106" + wire $reduce_or$libresoc.v:199405$14540_Y + attribute \src "libresoc.v:199407.18-199407.90" + wire $reduce_or$libresoc.v:199407$14542_Y + attribute \src "libresoc.v:199409.17-199409.103" + wire $reduce_or$libresoc.v:199409$14544_Y + attribute \src "libresoc.v:199411.17-199411.105" + wire $reduce_or$libresoc.v:199411$14546_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -413124,77 +417782,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196368$14425 + cell $not $not$libresoc.v:199404$14539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:196368$14425_Y + connect \Y $not$libresoc.v:199404$14539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196370$14427 + cell $not $not$libresoc.v:199406$14541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:196370$14427_Y + connect \Y $not$libresoc.v:199406$14541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:196372$14429 + cell $not $not$libresoc.v:199408$14543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:196372$14429_Y + connect \Y $not$libresoc.v:199408$14543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:196374$14431 + cell $not $not$libresoc.v:199410$14545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:196374$14431_Y + connect \Y $not$libresoc.v:199410$14545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196369$14426 + cell $reduce_or $reduce_or$libresoc.v:199405$14540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:196369$14426_Y + connect \Y $reduce_or$libresoc.v:199405$14540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:196371$14428 + cell $reduce_or $reduce_or$libresoc.v:199407$14542 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:196371$14428_Y + connect \Y $reduce_or$libresoc.v:199407$14542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196373$14430 + cell $reduce_or $reduce_or$libresoc.v:199409$14544 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:196373$14430_Y + connect \Y $reduce_or$libresoc.v:199409$14544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:196375$14432 + cell $reduce_or $reduce_or$libresoc.v:199411$14546 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:196375$14432_Y - end - connect \$7 $not$libresoc.v:196368$14425_Y - connect \$12 $reduce_or$libresoc.v:196369$14426_Y - connect \$11 $not$libresoc.v:196370$14427_Y - connect \$15 $reduce_or$libresoc.v:196371$14428_Y - connect \$1 $not$libresoc.v:196372$14429_Y - connect \$4 $reduce_or$libresoc.v:196373$14430_Y - connect \$3 $not$libresoc.v:196374$14431_Y - connect \$8 $reduce_or$libresoc.v:196375$14432_Y + connect \Y $reduce_or$libresoc.v:199411$14546_Y + end + connect \$7 $not$libresoc.v:199404$14539_Y + connect \$12 $reduce_or$libresoc.v:199405$14540_Y + connect \$11 $not$libresoc.v:199406$14541_Y + connect \$15 $reduce_or$libresoc.v:199407$14542_Y + connect \$1 $not$libresoc.v:199408$14543_Y + connect \$4 $reduce_or$libresoc.v:199409$14544_Y + connect \$3 $not$libresoc.v:199410$14545_Y + connect \$8 $reduce_or$libresoc.v:199411$14546_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -413203,67 +417861,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:196387.1-196707.10" +attribute \src "libresoc.v:199423.1-199743.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:196388.7-196388.20" + attribute \src "libresoc.v:199424.7-199424.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196667.3-196675.6" - wire width 3 $0\ren_delay$11$next[2:0]$14456 - attribute \src "libresoc.v:196565.3-196566.43" - wire width 3 $0\ren_delay$11[2:0]$14445 - attribute \src "libresoc.v:196524.13-196524.34" - wire width 3 $0\ren_delay$11[2:0]$14462 - attribute \src "libresoc.v:196629.3-196637.6" - wire width 3 $0\ren_delay$18$next[2:0]$14448 - attribute \src "libresoc.v:196563.3-196564.43" - wire width 3 $0\ren_delay$18[2:0]$14443 - attribute \src "libresoc.v:196528.13-196528.34" - wire width 3 $0\ren_delay$18[2:0]$14464 - attribute \src "libresoc.v:196648.3-196656.6" - wire width 3 $0\ren_delay$next[2:0]$14452 - attribute \src "libresoc.v:196567.3-196568.35" + attribute \src "libresoc.v:199703.3-199711.6" + wire width 3 $0\ren_delay$11$next[2:0]$14570 + attribute \src "libresoc.v:199601.3-199602.43" + wire width 3 $0\ren_delay$11[2:0]$14559 + attribute \src "libresoc.v:199560.13-199560.34" + wire width 3 $0\ren_delay$11[2:0]$14576 + attribute \src "libresoc.v:199665.3-199673.6" + wire width 3 $0\ren_delay$18$next[2:0]$14562 + attribute \src "libresoc.v:199599.3-199600.43" + wire width 3 $0\ren_delay$18[2:0]$14557 + attribute \src "libresoc.v:199564.13-199564.34" + wire width 3 $0\ren_delay$18[2:0]$14578 + attribute \src "libresoc.v:199684.3-199692.6" + wire width 3 $0\ren_delay$next[2:0]$14566 + attribute \src "libresoc.v:199603.3-199604.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:196657.3-196666.6" + attribute \src "libresoc.v:199693.3-199702.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:196676.3-196685.6" + attribute \src "libresoc.v:199712.3-199721.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:196638.3-196647.6" + attribute \src "libresoc.v:199674.3-199683.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:196667.3-196675.6" - wire width 3 $1\ren_delay$11$next[2:0]$14457 - attribute \src "libresoc.v:196629.3-196637.6" - wire width 3 $1\ren_delay$18$next[2:0]$14449 - attribute \src "libresoc.v:196648.3-196656.6" - wire width 3 $1\ren_delay$next[2:0]$14453 - attribute \src "libresoc.v:196522.13-196522.29" + attribute \src "libresoc.v:199703.3-199711.6" + wire width 3 $1\ren_delay$11$next[2:0]$14571 + attribute \src "libresoc.v:199665.3-199673.6" + wire width 3 $1\ren_delay$18$next[2:0]$14563 + attribute \src "libresoc.v:199684.3-199692.6" + wire width 3 $1\ren_delay$next[2:0]$14567 + attribute \src "libresoc.v:199558.13-199558.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:196657.3-196666.6" + attribute \src "libresoc.v:199693.3-199702.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:196676.3-196685.6" + attribute \src "libresoc.v:199712.3-199721.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:196638.3-196647.6" + attribute \src "libresoc.v:199674.3-199683.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:196554.17-196554.109" - wire width 2 $or$libresoc.v:196554$14433_Y - attribute \src "libresoc.v:196556.18-196556.126" - wire width 2 $or$libresoc.v:196556$14435_Y - attribute \src "libresoc.v:196557.18-196557.111" - wire width 2 $or$libresoc.v:196557$14436_Y - attribute \src "libresoc.v:196559.18-196559.126" - wire width 2 $or$libresoc.v:196559$14438_Y - attribute \src "libresoc.v:196560.18-196560.111" - wire width 2 $or$libresoc.v:196560$14439_Y - attribute \src "libresoc.v:196562.17-196562.125" - wire width 2 $or$libresoc.v:196562$14441_Y - attribute \src "libresoc.v:196555.18-196555.100" - wire $reduce_or$libresoc.v:196555$14434_Y - attribute \src "libresoc.v:196558.18-196558.100" - wire $reduce_or$libresoc.v:196558$14437_Y - attribute \src "libresoc.v:196561.17-196561.95" - wire $reduce_or$libresoc.v:196561$14440_Y + attribute \src "libresoc.v:199590.17-199590.109" + wire width 2 $or$libresoc.v:199590$14547_Y + attribute \src "libresoc.v:199592.18-199592.126" + wire width 2 $or$libresoc.v:199592$14549_Y + attribute \src "libresoc.v:199593.18-199593.111" + wire width 2 $or$libresoc.v:199593$14550_Y + attribute \src "libresoc.v:199595.18-199595.126" + wire width 2 $or$libresoc.v:199595$14552_Y + attribute \src "libresoc.v:199596.18-199596.111" + wire width 2 $or$libresoc.v:199596$14553_Y + attribute \src "libresoc.v:199598.17-199598.125" + wire width 2 $or$libresoc.v:199598$14555_Y + attribute \src "libresoc.v:199591.18-199591.100" + wire $reduce_or$libresoc.v:199591$14548_Y + attribute \src "libresoc.v:199594.18-199594.100" + wire $reduce_or$libresoc.v:199594$14551_Y + attribute \src "libresoc.v:199597.17-199597.95" + wire $reduce_or$libresoc.v:199597$14554_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -413282,9 +417940,9 @@ module \xer wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i @@ -413300,7 +417958,7 @@ module \xer wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:196388.7-196388.15" + attribute \src "libresoc.v:199424.7-199424.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i @@ -413429,7 +418087,7 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:196554$14433 + cell $or $or$libresoc.v:199590$14547 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -413437,10 +418095,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:196554$14433_Y + connect \Y $or$libresoc.v:199590$14547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:196556$14435 + cell $or $or$libresoc.v:199592$14549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -413448,10 +418106,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:196556$14435_Y + connect \Y $or$libresoc.v:199592$14549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:196557$14436 + cell $or $or$libresoc.v:199593$14550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -413459,10 +418117,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:196557$14436_Y + connect \Y $or$libresoc.v:199593$14550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:196559$14438 + cell $or $or$libresoc.v:199595$14552 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -413470,10 +418128,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:196559$14438_Y + connect \Y $or$libresoc.v:199595$14552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:196560$14439 + cell $or $or$libresoc.v:199596$14553 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -413481,10 +418139,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:196560$14439_Y + connect \Y $or$libresoc.v:199596$14553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:196562$14441 + cell $or $or$libresoc.v:199598$14555 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -413492,34 +418150,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:196562$14441_Y + connect \Y $or$libresoc.v:199598$14555_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:196555$14434 + cell $reduce_or $reduce_or$libresoc.v:199591$14548 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:196555$14434_Y + connect \Y $reduce_or$libresoc.v:199591$14548_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:196558$14437 + cell $reduce_or $reduce_or$libresoc.v:199594$14551 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:196558$14437_Y + connect \Y $reduce_or$libresoc.v:199594$14551_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:196561$14440 + cell $reduce_or $reduce_or$libresoc.v:199597$14554 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:196561$14440_Y + connect \Y $reduce_or$libresoc.v:199597$14554_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:196569.15-196588.4" + attribute \src "libresoc.v:199605.15-199624.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413541,7 +418199,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:196589.15-196608.4" + attribute \src "libresoc.v:199625.15-199644.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413563,7 +418221,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:196609.15-196628.4" + attribute \src "libresoc.v:199645.15-199664.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413584,67 +418242,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:196388.7-196388.20" - process $proc$libresoc.v:196388$14459 + attribute \src "libresoc.v:199424.7-199424.20" + process $proc$libresoc.v:199424$14573 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196522.13-196522.29" - process $proc$libresoc.v:196522$14460 + attribute \src "libresoc.v:199558.13-199558.29" + process $proc$libresoc.v:199558$14574 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:196524.13-196524.34" - process $proc$libresoc.v:196524$14461 + attribute \src "libresoc.v:199560.13-199560.34" + process $proc$libresoc.v:199560$14575 assign { } { } - assign $0\ren_delay$11[2:0]$14462 3'000 + assign $0\ren_delay$11[2:0]$14576 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14462 + update \ren_delay$11 $0\ren_delay$11[2:0]$14576 end - attribute \src "libresoc.v:196528.13-196528.34" - process $proc$libresoc.v:196528$14463 + attribute \src "libresoc.v:199564.13-199564.34" + process $proc$libresoc.v:199564$14577 assign { } { } - assign $0\ren_delay$18[2:0]$14464 3'000 + assign $0\ren_delay$18[2:0]$14578 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14464 + update \ren_delay$18 $0\ren_delay$18[2:0]$14578 end - attribute \src "libresoc.v:196563.3-196564.43" - process $proc$libresoc.v:196563$14442 + attribute \src "libresoc.v:199599.3-199600.43" + process $proc$libresoc.v:199599$14556 assign { } { } - assign $0\ren_delay$18[2:0]$14443 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14557 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14443 + update \ren_delay$18 $0\ren_delay$18[2:0]$14557 end - attribute \src "libresoc.v:196565.3-196566.43" - process $proc$libresoc.v:196565$14444 + attribute \src "libresoc.v:199601.3-199602.43" + process $proc$libresoc.v:199601$14558 assign { } { } - assign $0\ren_delay$11[2:0]$14445 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14559 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14445 + update \ren_delay$11 $0\ren_delay$11[2:0]$14559 end - attribute \src "libresoc.v:196567.3-196568.35" - process $proc$libresoc.v:196567$14446 + attribute \src "libresoc.v:199603.3-199604.35" + process $proc$libresoc.v:199603$14560 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:196629.3-196637.6" - process $proc$libresoc.v:196629$14447 + attribute \src "libresoc.v:199665.3-199673.6" + process $proc$libresoc.v:199665$14561 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14448 $1\ren_delay$18$next[2:0]$14449 - attribute \src "libresoc.v:196630.5-196630.29" + assign $0\ren_delay$18$next[2:0]$14562 $1\ren_delay$18$next[2:0]$14563 + attribute \src "libresoc.v:199666.5-199666.29" switch \initial - attribute \src "libresoc.v:196630.9-196630.17" + attribute \src "libresoc.v:199666.9-199666.17" case 1'1 case end @@ -413653,21 +418311,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14449 3'000 + assign $1\ren_delay$18$next[2:0]$14563 3'000 case - assign $1\ren_delay$18$next[2:0]$14449 \src3__ren + assign $1\ren_delay$18$next[2:0]$14563 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14448 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14562 end - attribute \src "libresoc.v:196638.3-196647.6" - process $proc$libresoc.v:196638$14450 + attribute \src "libresoc.v:199674.3-199683.6" + process $proc$libresoc.v:199674$14564 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:196639.5-196639.29" + attribute \src "libresoc.v:199675.5-199675.29" switch \initial - attribute \src "libresoc.v:196639.9-196639.17" + attribute \src "libresoc.v:199675.9-199675.17" case 1'1 case end @@ -413683,14 +418341,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:196648.3-196656.6" - process $proc$libresoc.v:196648$14451 + attribute \src "libresoc.v:199684.3-199692.6" + process $proc$libresoc.v:199684$14565 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14452 $1\ren_delay$next[2:0]$14453 - attribute \src "libresoc.v:196649.5-196649.29" + assign $0\ren_delay$next[2:0]$14566 $1\ren_delay$next[2:0]$14567 + attribute \src "libresoc.v:199685.5-199685.29" switch \initial - attribute \src "libresoc.v:196649.9-196649.17" + attribute \src "libresoc.v:199685.9-199685.17" case 1'1 case end @@ -413699,21 +418357,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14453 3'000 + assign $1\ren_delay$next[2:0]$14567 3'000 case - assign $1\ren_delay$next[2:0]$14453 \src1__ren + assign $1\ren_delay$next[2:0]$14567 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14452 + update \ren_delay$next $0\ren_delay$next[2:0]$14566 end - attribute \src "libresoc.v:196657.3-196666.6" - process $proc$libresoc.v:196657$14454 + attribute \src "libresoc.v:199693.3-199702.6" + process $proc$libresoc.v:199693$14568 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:196658.5-196658.29" + attribute \src "libresoc.v:199694.5-199694.29" switch \initial - attribute \src "libresoc.v:196658.9-196658.17" + attribute \src "libresoc.v:199694.9-199694.17" case 1'1 case end @@ -413729,14 +418387,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:196667.3-196675.6" - process $proc$libresoc.v:196667$14455 + attribute \src "libresoc.v:199703.3-199711.6" + process $proc$libresoc.v:199703$14569 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14456 $1\ren_delay$11$next[2:0]$14457 - attribute \src "libresoc.v:196668.5-196668.29" + assign $0\ren_delay$11$next[2:0]$14570 $1\ren_delay$11$next[2:0]$14571 + attribute \src "libresoc.v:199704.5-199704.29" switch \initial - attribute \src "libresoc.v:196668.9-196668.17" + attribute \src "libresoc.v:199704.9-199704.17" case 1'1 case end @@ -413745,21 +418403,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14457 3'000 + assign $1\ren_delay$11$next[2:0]$14571 3'000 case - assign $1\ren_delay$11$next[2:0]$14457 \src2__ren + assign $1\ren_delay$11$next[2:0]$14571 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14456 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14570 end - attribute \src "libresoc.v:196676.3-196685.6" - process $proc$libresoc.v:196676$14458 + attribute \src "libresoc.v:199712.3-199721.6" + process $proc$libresoc.v:199712$14572 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:196677.5-196677.29" + attribute \src "libresoc.v:199713.5-199713.29" switch \initial - attribute \src "libresoc.v:196677.9-196677.17" + attribute \src "libresoc.v:199713.9-199713.17" case 1'1 case end @@ -413775,15 +418433,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:196554$14433_Y - connect \$12 $reduce_or$libresoc.v:196555$14434_Y - connect \$14 $or$libresoc.v:196556$14435_Y - connect \$16 $or$libresoc.v:196557$14436_Y - connect \$19 $reduce_or$libresoc.v:196558$14437_Y - connect \$21 $or$libresoc.v:196559$14438_Y - connect \$23 $or$libresoc.v:196560$14439_Y - connect \$5 $reduce_or$libresoc.v:196561$14440_Y - connect \$7 $or$libresoc.v:196562$14441_Y + connect \$9 $or$libresoc.v:199590$14547_Y + connect \$12 $reduce_or$libresoc.v:199591$14548_Y + connect \$14 $or$libresoc.v:199592$14549_Y + connect \$16 $or$libresoc.v:199593$14550_Y + connect \$19 $reduce_or$libresoc.v:199594$14551_Y + connect \$21 $or$libresoc.v:199595$14552_Y + connect \$23 $or$libresoc.v:199596$14553_Y + connect \$5 $reduce_or$libresoc.v:199597$14554_Y + connect \$7 $or$libresoc.v:199598$14555_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -413806,153 +418464,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:196711.1-197025.10" +attribute \src "libresoc.v:199747.1-200061.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:196889.3-196917.6" + attribute \src "libresoc.v:199925.3-199953.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:196940.3-196948.6" - wire $0\core_irq_o$next[0:0]$14500 - attribute \src "libresoc.v:196831.3-196832.37" + attribute \src "libresoc.v:199976.3-199984.6" + wire $0\core_irq_o$next[0:0]$14614 + attribute \src "libresoc.v:199867.3-199868.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $0\cppr$10[7:0]$14504 - attribute \src "libresoc.v:196845.3-196860.6" - wire width 8 $0\cppr$next[7:0]$14483 - attribute \src "libresoc.v:196835.3-196836.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $0\cppr$10[7:0]$14618 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 8 $0\cppr$next[7:0]$14597 + attribute \src "libresoc.v:199871.3-199872.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:196949.3-196958.6" + attribute \src "libresoc.v:199985.3-199994.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:196712.7-196712.20" + attribute \src "libresoc.v:199748.7-199748.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire $0\irq$12[0:0]$14505 - attribute \src "libresoc.v:196845.3-196860.6" - wire $0\irq$next[0:0]$14484 - attribute \src "libresoc.v:196839.3-196840.23" + attribute \src "libresoc.v:199995.3-200057.6" + wire $0\irq$12[0:0]$14619 + attribute \src "libresoc.v:199881.3-199896.6" + wire $0\irq$next[0:0]$14598 + attribute \src "libresoc.v:199875.3-199876.23" wire $0\irq[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $0\mfrr$11[7:0]$14506 - attribute \src "libresoc.v:196845.3-196860.6" - wire width 8 $0\mfrr$next[7:0]$14485 - attribute \src "libresoc.v:196837.3-196838.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $0\mfrr$11[7:0]$14620 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 8 $0\mfrr$next[7:0]$14599 + attribute \src "libresoc.v:199873.3-199874.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:196928.3-196939.6" + attribute \src "libresoc.v:199964.3-199975.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:196918.3-196927.6" + attribute \src "libresoc.v:199954.3-199963.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire $0\wb_ack$14[0:0]$14507 - attribute \src "libresoc.v:196845.3-196860.6" - wire $0\wb_ack$next[0:0]$14486 - attribute \src "libresoc.v:196843.3-196844.29" + attribute \src "libresoc.v:199995.3-200057.6" + wire $0\wb_ack$14[0:0]$14621 + attribute \src "libresoc.v:199881.3-199896.6" + wire $0\wb_ack$next[0:0]$14600 + attribute \src "libresoc.v:199879.3-199880.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 32 $0\wb_rd_data$13[31:0]$14508 - attribute \src "libresoc.v:196845.3-196860.6" - wire width 32 $0\wb_rd_data$next[31:0]$14487 - attribute \src "libresoc.v:196841.3-196842.37" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 32 $0\wb_rd_data$13[31:0]$14622 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 32 $0\wb_rd_data$next[31:0]$14601 + attribute \src "libresoc.v:199877.3-199878.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:196861.3-196888.6" + attribute \src "libresoc.v:199897.3-199924.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 24 $0\xisr$9[23:0]$14509 - attribute \src "libresoc.v:196845.3-196860.6" - wire width 24 $0\xisr$next[23:0]$14488 - attribute \src "libresoc.v:196833.3-196834.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 24 $0\xisr$9[23:0]$14623 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 24 $0\xisr$next[23:0]$14602 + attribute \src "libresoc.v:199869.3-199870.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:196889.3-196917.6" + attribute \src "libresoc.v:199925.3-199953.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:196940.3-196948.6" - wire $1\core_irq_o$next[0:0]$14501 - attribute \src "libresoc.v:196741.7-196741.24" + attribute \src "libresoc.v:199976.3-199984.6" + wire $1\core_irq_o$next[0:0]$14615 + attribute \src "libresoc.v:199777.7-199777.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $1\cppr$10[7:0]$14510 - attribute \src "libresoc.v:196845.3-196860.6" - wire width 8 $1\cppr$next[7:0]$14489 - attribute \src "libresoc.v:196745.13-196745.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $1\cppr$10[7:0]$14624 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 8 $1\cppr$next[7:0]$14603 + attribute \src "libresoc.v:199781.13-199781.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:196949.3-196958.6" + attribute \src "libresoc.v:199985.3-199994.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire $1\irq$12[0:0]$14520 - attribute \src "libresoc.v:196845.3-196860.6" - wire $1\irq$next[0:0]$14490 - attribute \src "libresoc.v:196774.7-196774.17" + attribute \src "libresoc.v:199995.3-200057.6" + wire $1\irq$12[0:0]$14634 + attribute \src "libresoc.v:199881.3-199896.6" + wire $1\irq$next[0:0]$14604 + attribute \src "libresoc.v:199810.7-199810.17" wire $1\irq[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $1\mfrr$11[7:0]$14511 - attribute \src "libresoc.v:196845.3-196860.6" - wire width 8 $1\mfrr$next[7:0]$14491 - attribute \src "libresoc.v:196782.13-196782.25" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $1\mfrr$11[7:0]$14625 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 8 $1\mfrr$next[7:0]$14605 + attribute \src "libresoc.v:199818.13-199818.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:196928.3-196939.6" + attribute \src "libresoc.v:199964.3-199975.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:196918.3-196927.6" + attribute \src "libresoc.v:199954.3-199963.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire $1\wb_ack$14[0:0]$14512 - attribute \src "libresoc.v:196845.3-196860.6" - wire $1\wb_ack$next[0:0]$14492 - attribute \src "libresoc.v:196796.7-196796.20" + attribute \src "libresoc.v:199995.3-200057.6" + wire $1\wb_ack$14[0:0]$14626 + attribute \src "libresoc.v:199881.3-199896.6" + wire $1\wb_ack$next[0:0]$14606 + attribute \src "libresoc.v:199832.7-199832.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:196845.3-196860.6" - wire width 32 $1\wb_rd_data$next[31:0]$14493 - attribute \src "libresoc.v:196804.14-196804.32" + attribute \src "libresoc.v:199881.3-199896.6" + wire width 32 $1\wb_rd_data$next[31:0]$14607 + attribute \src "libresoc.v:199840.14-199840.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:196861.3-196888.6" + attribute \src "libresoc.v:199897.3-199924.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 24 $1\xisr$9[23:0]$14517 - attribute \src "libresoc.v:196845.3-196860.6" - wire width 24 $1\xisr$next[23:0]$14494 - attribute \src "libresoc.v:196814.14-196814.31" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 24 $1\xisr$9[23:0]$14631 + attribute \src "libresoc.v:199881.3-199896.6" + wire width 24 $1\xisr$next[23:0]$14608 + attribute \src "libresoc.v:199850.14-199850.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:196889.3-196917.6" + attribute \src "libresoc.v:199925.3-199953.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $2\cppr$10[7:0]$14513 - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $2\mfrr$11[7:0]$14514 - attribute \src "libresoc.v:196861.3-196888.6" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $2\cppr$10[7:0]$14627 + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $2\mfrr$11[7:0]$14628 + attribute \src "libresoc.v:199897.3-199924.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 24 $2\xisr$9[23:0]$14518 - attribute \src "libresoc.v:196889.3-196917.6" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 24 $2\xisr$9[23:0]$14632 + attribute \src "libresoc.v:199925.3-199953.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $3\cppr$10[7:0]$14515 - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $3\mfrr$11[7:0]$14516 - attribute \src "libresoc.v:196861.3-196888.6" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $3\cppr$10[7:0]$14629 + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $3\mfrr$11[7:0]$14630 + attribute \src "libresoc.v:199897.3-199924.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:196959.3-197021.6" - wire width 8 $4\cppr$10[7:0]$14519 - attribute \src "libresoc.v:196861.3-196888.6" + attribute \src "libresoc.v:199995.3-200057.6" + wire width 8 $4\cppr$10[7:0]$14633 + attribute \src "libresoc.v:199897.3-199924.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:196821.18-196821.116" - wire $and$libresoc.v:196821$14465_Y - attribute \src "libresoc.v:196825.18-196825.116" - wire $and$libresoc.v:196825$14469_Y - attribute \src "libresoc.v:196827.18-196827.116" - wire $and$libresoc.v:196827$14471_Y - attribute \src "libresoc.v:196830.17-196830.109" - wire $and$libresoc.v:196830$14474_Y - attribute \src "libresoc.v:196826.18-196826.110" - wire $eq$libresoc.v:196826$14470_Y - attribute \src "libresoc.v:196823.18-196823.114" - wire $lt$libresoc.v:196823$14467_Y - attribute \src "libresoc.v:196824.18-196824.109" - wire $lt$libresoc.v:196824$14468_Y - attribute \src "libresoc.v:196829.18-196829.114" - wire $lt$libresoc.v:196829$14473_Y - attribute \src "libresoc.v:196822.18-196822.109" - wire $ne$libresoc.v:196822$14466_Y - attribute \src "libresoc.v:196828.18-196828.109" - wire $ne$libresoc.v:196828$14472_Y + attribute \src "libresoc.v:199857.18-199857.116" + wire $and$libresoc.v:199857$14579_Y + attribute \src "libresoc.v:199861.18-199861.116" + wire $and$libresoc.v:199861$14583_Y + attribute \src "libresoc.v:199863.18-199863.116" + wire $and$libresoc.v:199863$14585_Y + attribute \src "libresoc.v:199866.17-199866.109" + wire $and$libresoc.v:199866$14588_Y + attribute \src "libresoc.v:199862.18-199862.110" + wire $eq$libresoc.v:199862$14584_Y + attribute \src "libresoc.v:199859.18-199859.114" + wire $lt$libresoc.v:199859$14581_Y + attribute \src "libresoc.v:199860.18-199860.109" + wire $lt$libresoc.v:199860$14582_Y + attribute \src "libresoc.v:199865.18-199865.114" + wire $lt$libresoc.v:199865$14587_Y + attribute \src "libresoc.v:199858.18-199858.109" + wire $ne$libresoc.v:199858$14580_Y + attribute \src "libresoc.v:199864.18-199864.109" + wire $ne$libresoc.v:199864$14586_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -413977,10 +418635,10 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire output 3 \core_irq_o + wire output 4 \core_irq_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \core_irq_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" @@ -414008,10 +418666,10 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 10 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 input 2 \ics_i_pri + wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 input 1 \ics_i_src - attribute \src "libresoc.v:196712.7-196712.15" + wire width 4 input 2 \ics_i_src + attribute \src "libresoc.v:199748.7-199748.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -414033,8 +418691,8 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 4 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" @@ -414062,7 +418720,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:196821$14465 + cell $and $and$libresoc.v:199857$14579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414070,10 +418728,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:196821$14465_Y + connect \Y $and$libresoc.v:199857$14579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:196825$14469 + cell $and $and$libresoc.v:199861$14583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414081,10 +418739,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:196825$14469_Y + connect \Y $and$libresoc.v:199861$14583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:196827$14471 + cell $and $and$libresoc.v:199863$14585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414092,10 +418750,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:196827$14471_Y + connect \Y $and$libresoc.v:199863$14585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:196830$14474 + cell $and $and$libresoc.v:199866$14588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414103,10 +418761,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:196830$14474_Y + connect \Y $and$libresoc.v:199866$14588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:196826$14470 + cell $eq $eq$libresoc.v:199862$14584 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414114,10 +418772,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:196826$14470_Y + connect \Y $eq$libresoc.v:199862$14584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:196823$14467 + cell $lt $lt$libresoc.v:199859$14581 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -414125,10 +418783,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:196823$14467_Y + connect \Y $lt$libresoc.v:199859$14581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:196824$14468 + cell $lt $lt$libresoc.v:199860$14582 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -414136,10 +418794,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:196824$14468_Y + connect \Y $lt$libresoc.v:199860$14582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:196829$14473 + cell $lt $lt$libresoc.v:199865$14587 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -414147,10 +418805,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:196829$14473_Y + connect \Y $lt$libresoc.v:199865$14587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:196822$14466 + cell $ne $ne$libresoc.v:199858$14580 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -414158,10 +418816,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:196822$14466_Y + connect \Y $ne$libresoc.v:199858$14580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:196828$14472 + cell $ne $ne$libresoc.v:199864$14586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -414169,123 +418827,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:196828$14472_Y + connect \Y $ne$libresoc.v:199864$14586_Y end - attribute \src "libresoc.v:196712.7-196712.20" - process $proc$libresoc.v:196712$14521 + attribute \src "libresoc.v:199748.7-199748.20" + process $proc$libresoc.v:199748$14635 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196741.7-196741.24" - process $proc$libresoc.v:196741$14522 + attribute \src "libresoc.v:199777.7-199777.24" + process $proc$libresoc.v:199777$14636 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:196745.13-196745.25" - process $proc$libresoc.v:196745$14523 + attribute \src "libresoc.v:199781.13-199781.25" + process $proc$libresoc.v:199781$14637 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:196774.7-196774.17" - process $proc$libresoc.v:196774$14524 + attribute \src "libresoc.v:199810.7-199810.17" + process $proc$libresoc.v:199810$14638 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:196782.13-196782.25" - process $proc$libresoc.v:196782$14525 + attribute \src "libresoc.v:199818.13-199818.25" + process $proc$libresoc.v:199818$14639 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:196796.7-196796.20" - process $proc$libresoc.v:196796$14526 + attribute \src "libresoc.v:199832.7-199832.20" + process $proc$libresoc.v:199832$14640 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:196804.14-196804.32" - process $proc$libresoc.v:196804$14527 + attribute \src "libresoc.v:199840.14-199840.32" + process $proc$libresoc.v:199840$14641 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:196814.14-196814.31" - process $proc$libresoc.v:196814$14528 + attribute \src "libresoc.v:199850.14-199850.31" + process $proc$libresoc.v:199850$14642 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:196831.3-196832.37" - process $proc$libresoc.v:196831$14475 + attribute \src "libresoc.v:199867.3-199868.37" + process $proc$libresoc.v:199867$14589 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:196833.3-196834.25" - process $proc$libresoc.v:196833$14476 + attribute \src "libresoc.v:199869.3-199870.25" + process $proc$libresoc.v:199869$14590 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:196835.3-196836.25" - process $proc$libresoc.v:196835$14477 + attribute \src "libresoc.v:199871.3-199872.25" + process $proc$libresoc.v:199871$14591 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:196837.3-196838.25" - process $proc$libresoc.v:196837$14478 + attribute \src "libresoc.v:199873.3-199874.25" + process $proc$libresoc.v:199873$14592 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:196839.3-196840.23" - process $proc$libresoc.v:196839$14479 + attribute \src "libresoc.v:199875.3-199876.23" + process $proc$libresoc.v:199875$14593 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:196841.3-196842.37" - process $proc$libresoc.v:196841$14480 + attribute \src "libresoc.v:199877.3-199878.37" + process $proc$libresoc.v:199877$14594 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:196843.3-196844.29" - process $proc$libresoc.v:196843$14481 + attribute \src "libresoc.v:199879.3-199880.29" + process $proc$libresoc.v:199879$14595 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:196845.3-196860.6" - process $proc$libresoc.v:196845$14482 + attribute \src "libresoc.v:199881.3-199896.6" + process $proc$libresoc.v:199881$14596 assign { } { } assign { } { } assign { } { } @@ -414293,15 +418951,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14483 $1\cppr$next[7:0]$14489 - assign $0\irq$next[0:0]$14484 $1\irq$next[0:0]$14490 - assign $0\mfrr$next[7:0]$14485 $1\mfrr$next[7:0]$14491 - assign $0\wb_ack$next[0:0]$14486 $1\wb_ack$next[0:0]$14492 - assign $0\wb_rd_data$next[31:0]$14487 $1\wb_rd_data$next[31:0]$14493 - assign $0\xisr$next[23:0]$14488 $1\xisr$next[23:0]$14494 - attribute \src "libresoc.v:196846.5-196846.29" + assign $0\cppr$next[7:0]$14597 $1\cppr$next[7:0]$14603 + assign $0\irq$next[0:0]$14598 $1\irq$next[0:0]$14604 + assign $0\mfrr$next[7:0]$14599 $1\mfrr$next[7:0]$14605 + assign $0\wb_ack$next[0:0]$14600 $1\wb_ack$next[0:0]$14606 + assign $0\wb_rd_data$next[31:0]$14601 $1\wb_rd_data$next[31:0]$14607 + assign $0\xisr$next[23:0]$14602 $1\xisr$next[23:0]$14608 + attribute \src "libresoc.v:199882.5-199882.29" switch \initial - attribute \src "libresoc.v:196846.9-196846.17" + attribute \src "libresoc.v:199882.9-199882.17" case 1'1 case end @@ -414315,36 +418973,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14494 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14489 8'00000000 - assign $1\mfrr$next[7:0]$14491 8'11111111 - assign $1\irq$next[0:0]$14490 1'0 - assign $1\wb_rd_data$next[31:0]$14493 0 - assign $1\wb_ack$next[0:0]$14492 1'0 + assign $1\xisr$next[23:0]$14608 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14603 8'00000000 + assign $1\mfrr$next[7:0]$14605 8'11111111 + assign $1\irq$next[0:0]$14604 1'0 + assign $1\wb_rd_data$next[31:0]$14607 0 + assign $1\wb_ack$next[0:0]$14606 1'0 case - assign $1\cppr$next[7:0]$14489 \cppr$2 - assign $1\irq$next[0:0]$14490 \irq$4 - assign $1\mfrr$next[7:0]$14491 \mfrr$3 - assign $1\wb_ack$next[0:0]$14492 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14493 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14494 \xisr$1 + assign $1\cppr$next[7:0]$14603 \cppr$2 + assign $1\irq$next[0:0]$14604 \irq$4 + assign $1\mfrr$next[7:0]$14605 \mfrr$3 + assign $1\wb_ack$next[0:0]$14606 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14607 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14608 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14483 - update \irq$next $0\irq$next[0:0]$14484 - update \mfrr$next $0\mfrr$next[7:0]$14485 - update \wb_ack$next $0\wb_ack$next[0:0]$14486 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14487 - update \xisr$next $0\xisr$next[23:0]$14488 + update \cppr$next $0\cppr$next[7:0]$14597 + update \irq$next $0\irq$next[0:0]$14598 + update \mfrr$next $0\mfrr$next[7:0]$14599 + update \wb_ack$next $0\wb_ack$next[0:0]$14600 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14601 + update \xisr$next $0\xisr$next[23:0]$14602 end - attribute \src "libresoc.v:196861.3-196888.6" - process $proc$libresoc.v:196861$14495 + attribute \src "libresoc.v:199897.3-199924.6" + process $proc$libresoc.v:199897$14609 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:196862.5-196862.29" + attribute \src "libresoc.v:199898.5-199898.29" switch \initial - attribute \src "libresoc.v:196862.9-196862.17" + attribute \src "libresoc.v:199898.9-199898.17" case 1'1 case end @@ -414388,14 +419046,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:196889.3-196917.6" - process $proc$libresoc.v:196889$14496 + attribute \src "libresoc.v:199925.3-199953.6" + process $proc$libresoc.v:199925$14610 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:196890.5-196890.29" + attribute \src "libresoc.v:199926.5-199926.29" switch \initial - attribute \src "libresoc.v:196890.9-196890.17" + attribute \src "libresoc.v:199926.9-199926.17" case 1'1 case end @@ -414438,14 +419096,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:196918.3-196927.6" - process $proc$libresoc.v:196918$14497 + attribute \src "libresoc.v:199954.3-199963.6" + process $proc$libresoc.v:199954$14611 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:196919.5-196919.29" + attribute \src "libresoc.v:199955.5-199955.29" switch \initial - attribute \src "libresoc.v:196919.9-196919.17" + attribute \src "libresoc.v:199955.9-199955.17" case 1'1 case end @@ -414461,13 +419119,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:196928.3-196939.6" - process $proc$libresoc.v:196928$14498 + attribute \src "libresoc.v:199964.3-199975.6" + process $proc$libresoc.v:199964$14612 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:196929.5-196929.29" + attribute \src "libresoc.v:199965.5-199965.29" switch \initial - attribute \src "libresoc.v:196929.9-196929.17" + attribute \src "libresoc.v:199965.9-199965.17" case 1'1 case end @@ -414485,14 +419143,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:196940.3-196948.6" - process $proc$libresoc.v:196940$14499 + attribute \src "libresoc.v:199976.3-199984.6" + process $proc$libresoc.v:199976$14613 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14500 $1\core_irq_o$next[0:0]$14501 - attribute \src "libresoc.v:196941.5-196941.29" + assign $0\core_irq_o$next[0:0]$14614 $1\core_irq_o$next[0:0]$14615 + attribute \src "libresoc.v:199977.5-199977.29" switch \initial - attribute \src "libresoc.v:196941.9-196941.17" + attribute \src "libresoc.v:199977.9-199977.17" case 1'1 case end @@ -414501,21 +419159,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14501 1'0 + assign $1\core_irq_o$next[0:0]$14615 1'0 case - assign $1\core_irq_o$next[0:0]$14501 \irq + assign $1\core_irq_o$next[0:0]$14615 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14500 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14614 end - attribute \src "libresoc.v:196949.3-196958.6" - process $proc$libresoc.v:196949$14502 + attribute \src "libresoc.v:199985.3-199994.6" + process $proc$libresoc.v:199985$14616 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:196950.5-196950.29" + attribute \src "libresoc.v:199986.5-199986.29" switch \initial - attribute \src "libresoc.v:196950.9-196950.17" + attribute \src "libresoc.v:199986.9-199986.17" case 1'1 case end @@ -414531,8 +419189,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:196959.3-197021.6" - process $proc$libresoc.v:196959$14503 + attribute \src "libresoc.v:199995.3-200057.6" + process $proc$libresoc.v:199995$14617 assign { } { } assign { } { } assign { } { } @@ -414542,18 +419200,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14506 $1\mfrr$11[7:0]$14511 - assign $0\wb_ack$14[0:0]$14507 $1\wb_ack$14[0:0]$14512 + assign $0\mfrr$11[7:0]$14620 $1\mfrr$11[7:0]$14625 + assign $0\wb_ack$14[0:0]$14621 $1\wb_ack$14[0:0]$14626 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14509 $2\xisr$9[23:0]$14518 - assign $0\cppr$10[7:0]$14504 $4\cppr$10[7:0]$14519 - assign $0\wb_rd_data$13[31:0]$14508 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14505 $1\irq$12[0:0]$14520 - attribute \src "libresoc.v:196960.5-196960.29" + assign $0\xisr$9[23:0]$14623 $2\xisr$9[23:0]$14632 + assign $0\cppr$10[7:0]$14618 $4\cppr$10[7:0]$14633 + assign $0\wb_rd_data$13[31:0]$14622 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14619 $1\irq$12[0:0]$14634 + attribute \src "libresoc.v:199996.5-199996.29" switch \initial - attribute \src "libresoc.v:196960.9-196960.17" + attribute \src "libresoc.v:199996.9-199996.17" case 1'1 case end @@ -414564,712 +419222,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14512 1'1 - assign $1\cppr$10[7:0]$14510 $2\cppr$10[7:0]$14513 - assign $1\mfrr$11[7:0]$14511 $2\mfrr$11[7:0]$14514 + assign $1\wb_ack$14[0:0]$14626 1'1 + assign $1\cppr$10[7:0]$14624 $2\cppr$10[7:0]$14627 + assign $1\mfrr$11[7:0]$14625 $2\mfrr$11[7:0]$14628 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14513 $3\cppr$10[7:0]$14515 - assign $2\mfrr$11[7:0]$14514 $3\mfrr$11[7:0]$14516 + assign $2\cppr$10[7:0]$14627 $3\cppr$10[7:0]$14629 + assign $2\mfrr$11[7:0]$14628 $3\mfrr$11[7:0]$14630 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14516 \mfrr - assign $3\cppr$10[7:0]$14515 \be_in [31:24] + assign $3\mfrr$11[7:0]$14630 \mfrr + assign $3\cppr$10[7:0]$14629 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14516 \mfrr - assign $3\cppr$10[7:0]$14515 \be_in [31:24] + assign $3\mfrr$11[7:0]$14630 \mfrr + assign $3\cppr$10[7:0]$14629 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14515 \cppr + assign $3\cppr$10[7:0]$14629 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14516 \be_in [31:24] + assign $3\mfrr$11[7:0]$14630 \be_in [31:24] case - assign $3\cppr$10[7:0]$14515 \cppr - assign $3\mfrr$11[7:0]$14516 \mfrr + assign $3\cppr$10[7:0]$14629 \cppr + assign $3\mfrr$11[7:0]$14630 \mfrr end case - assign $2\cppr$10[7:0]$14513 \cppr - assign $2\mfrr$11[7:0]$14514 \mfrr + assign $2\cppr$10[7:0]$14627 \cppr + assign $2\mfrr$11[7:0]$14628 \mfrr end case - assign $1\cppr$10[7:0]$14510 \cppr - assign $1\mfrr$11[7:0]$14511 \mfrr - assign $1\wb_ack$14[0:0]$14512 1'0 + assign $1\cppr$10[7:0]$14624 \cppr + assign $1\mfrr$11[7:0]$14625 \mfrr + assign $1\wb_ack$14[0:0]$14626 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14517 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14631 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14517 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14631 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14518 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14632 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14518 $1\xisr$9[23:0]$14517 + assign $2\xisr$9[23:0]$14632 $1\xisr$9[23:0]$14631 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14519 \min_pri + assign $4\cppr$10[7:0]$14633 \min_pri case - assign $4\cppr$10[7:0]$14519 $1\cppr$10[7:0]$14510 + assign $4\cppr$10[7:0]$14633 $1\cppr$10[7:0]$14624 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14520 1'1 + assign $1\irq$12[0:0]$14634 1'1 case - assign $1\irq$12[0:0]$14520 1'0 + assign $1\irq$12[0:0]$14634 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14504 - update \irq$12 $0\irq$12[0:0]$14505 - update \mfrr$11 $0\mfrr$11[7:0]$14506 - update \wb_ack$14 $0\wb_ack$14[0:0]$14507 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14508 - update \xisr$9 $0\xisr$9[23:0]$14509 + update \cppr$10 $0\cppr$10[7:0]$14618 + update \irq$12 $0\irq$12[0:0]$14619 + update \mfrr$11 $0\mfrr$11[7:0]$14620 + update \wb_ack$14 $0\wb_ack$14[0:0]$14621 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14622 + update \xisr$9 $0\xisr$9[23:0]$14623 end - connect \$15 $and$libresoc.v:196821$14465_Y - connect \$17 $ne$libresoc.v:196822$14466_Y - connect \$19 $lt$libresoc.v:196823$14467_Y - connect \$21 $lt$libresoc.v:196824$14468_Y - connect \$23 $and$libresoc.v:196825$14469_Y - connect \$25 $eq$libresoc.v:196826$14470_Y - connect \$27 $and$libresoc.v:196827$14471_Y - connect \$29 $ne$libresoc.v:196828$14472_Y - connect \$31 $lt$libresoc.v:196829$14473_Y - connect \$7 $and$libresoc.v:196830$14474_Y + connect \$15 $and$libresoc.v:199857$14579_Y + connect \$17 $ne$libresoc.v:199858$14580_Y + connect \$19 $lt$libresoc.v:199859$14581_Y + connect \$21 $lt$libresoc.v:199860$14582_Y + connect \$23 $and$libresoc.v:199861$14583_Y + connect \$25 $eq$libresoc.v:199862$14584_Y + connect \$27 $and$libresoc.v:199863$14585_Y + connect \$29 $ne$libresoc.v:199864$14586_Y + connect \$31 $lt$libresoc.v:199865$14587_Y + connect \$7 $and$libresoc.v:199866$14588_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:197029.1-198078.10" +attribute \src "libresoc.v:200065.1-201114.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:197959.3-198008.6" + attribute \src "libresoc.v:200995.3-201044.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:197670.3-197679.6" + attribute \src "libresoc.v:200706.3-200715.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:197879.3-197888.6" + attribute \src "libresoc.v:200915.3-200924.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:197899.3-197908.6" + attribute \src "libresoc.v:200935.3-200944.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:197919.3-197928.6" + attribute \src "libresoc.v:200955.3-200964.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:197939.3-197948.6" + attribute \src "libresoc.v:200975.3-200984.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:198009.3-198018.6" + attribute \src "libresoc.v:201045.3-201054.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:198029.3-198038.6" + attribute \src "libresoc.v:201065.3-201074.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:197690.3-197699.6" + attribute \src "libresoc.v:200726.3-200735.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:197710.3-197719.6" + attribute \src "libresoc.v:200746.3-200755.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:197730.3-197739.6" + attribute \src "libresoc.v:200766.3-200775.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:197759.3-197768.6" + attribute \src "libresoc.v:200795.3-200804.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:197779.3-197788.6" + attribute \src "libresoc.v:200815.3-200824.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:197799.3-197808.6" + attribute \src "libresoc.v:200835.3-200844.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:197819.3-197828.6" + attribute \src "libresoc.v:200855.3-200864.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:197839.3-197848.6" + attribute \src "libresoc.v:200875.3-200884.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:197859.3-197868.6" + attribute \src "libresoc.v:200895.3-200904.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:197660.3-197669.6" + attribute \src "libresoc.v:200696.3-200705.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:197869.3-197878.6" + attribute \src "libresoc.v:200905.3-200914.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:197889.3-197898.6" + attribute \src "libresoc.v:200925.3-200934.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:197909.3-197918.6" + attribute \src "libresoc.v:200945.3-200954.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:197929.3-197938.6" + attribute \src "libresoc.v:200965.3-200974.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:197949.3-197958.6" + attribute \src "libresoc.v:200985.3-200994.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:198019.3-198028.6" + attribute \src "libresoc.v:201055.3-201064.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:197680.3-197689.6" + attribute \src "libresoc.v:200716.3-200725.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:197700.3-197709.6" + attribute \src "libresoc.v:200736.3-200745.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:197720.3-197729.6" + attribute \src "libresoc.v:200756.3-200765.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:197740.3-197749.6" + attribute \src "libresoc.v:200776.3-200785.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:197769.3-197778.6" + attribute \src "libresoc.v:200805.3-200814.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:197789.3-197798.6" + attribute \src "libresoc.v:200825.3-200834.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:197809.3-197818.6" + attribute \src "libresoc.v:200845.3-200854.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:197829.3-197838.6" + attribute \src "libresoc.v:200865.3-200874.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:197849.3-197858.6" + attribute \src "libresoc.v:200885.3-200894.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:198039.3-198048.6" + attribute \src "libresoc.v:201075.3-201084.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:197534.3-197535.25" + attribute \src "libresoc.v:200570.3-200571.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:197532.3-197533.28" + attribute \src "libresoc.v:200568.3-200569.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:198058.3-198066.6" - wire $0\ics_wb__ack$next[0:0]$14775 - attribute \src "libresoc.v:197568.3-197569.39" + attribute \src "libresoc.v:201094.3-201102.6" + wire $0\ics_wb__ack$next[0:0]$14889 + attribute \src "libresoc.v:200604.3-200605.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:198049.3-198057.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$14772 - attribute \src "libresoc.v:197570.3-197571.43" + attribute \src "libresoc.v:201085.3-201093.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$14886 + attribute \src "libresoc.v:200606.3-200607.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:197030.7-197030.20" + attribute \src "libresoc.v:200066.7-200066.20" wire $0\initial[0:0] - attribute \src "libresoc.v:197750.3-197758.6" - wire width 16 $0\int_level_l$next[15:0]$14744 - attribute \src "libresoc.v:197572.3-197573.39" + attribute \src "libresoc.v:200786.3-200794.6" + wire width 16 $0\int_level_l$next[15:0]$14858 + attribute \src "libresoc.v:200608.3-200609.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive0_pri$next[7:0]$14654 - attribute \src "libresoc.v:197536.3-197537.35" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive0_pri$next[7:0]$14768 + attribute \src "libresoc.v:200572.3-200573.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive10_pri$next[7:0]$14655 - attribute \src "libresoc.v:197556.3-197557.37" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive10_pri$next[7:0]$14769 + attribute \src "libresoc.v:200592.3-200593.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive11_pri$next[7:0]$14656 - attribute \src "libresoc.v:197558.3-197559.37" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive11_pri$next[7:0]$14770 + attribute \src "libresoc.v:200594.3-200595.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive12_pri$next[7:0]$14657 - attribute \src "libresoc.v:197560.3-197561.37" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive12_pri$next[7:0]$14771 + attribute \src "libresoc.v:200596.3-200597.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive13_pri$next[7:0]$14658 - attribute \src "libresoc.v:197562.3-197563.37" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive13_pri$next[7:0]$14772 + attribute \src "libresoc.v:200598.3-200599.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive14_pri$next[7:0]$14659 - attribute \src "libresoc.v:197564.3-197565.37" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive14_pri$next[7:0]$14773 + attribute \src "libresoc.v:200600.3-200601.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive15_pri$next[7:0]$14660 - attribute \src "libresoc.v:197566.3-197567.37" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive15_pri$next[7:0]$14774 + attribute \src "libresoc.v:200602.3-200603.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive1_pri$next[7:0]$14661 - attribute \src "libresoc.v:197538.3-197539.35" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive1_pri$next[7:0]$14775 + attribute \src "libresoc.v:200574.3-200575.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive2_pri$next[7:0]$14662 - attribute \src "libresoc.v:197540.3-197541.35" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive2_pri$next[7:0]$14776 + attribute \src "libresoc.v:200576.3-200577.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive3_pri$next[7:0]$14663 - attribute \src "libresoc.v:197542.3-197543.35" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive3_pri$next[7:0]$14777 + attribute \src "libresoc.v:200578.3-200579.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive4_pri$next[7:0]$14664 - attribute \src "libresoc.v:197544.3-197545.35" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive4_pri$next[7:0]$14778 + attribute \src "libresoc.v:200580.3-200581.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive5_pri$next[7:0]$14665 - attribute \src "libresoc.v:197546.3-197547.35" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive5_pri$next[7:0]$14779 + attribute \src "libresoc.v:200582.3-200583.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive6_pri$next[7:0]$14666 - attribute \src "libresoc.v:197548.3-197549.35" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive6_pri$next[7:0]$14780 + attribute \src "libresoc.v:200584.3-200585.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $0\xive7_pri$next[7:0]$14667 - attribute \src "libresoc.v:197550.3-197551.35" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $0\xive7_pri$next[7:0]$14781 + attribute \src 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attribute \src "libresoc.v:197869.3-197878.6" + attribute \src "libresoc.v:200905.3-200914.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:197889.3-197898.6" + attribute \src "libresoc.v:200925.3-200934.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:197909.3-197918.6" + attribute \src "libresoc.v:200945.3-200954.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:197929.3-197938.6" + attribute \src "libresoc.v:200965.3-200974.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:197949.3-197958.6" + attribute \src "libresoc.v:200985.3-200994.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:198019.3-198028.6" + attribute \src "libresoc.v:201055.3-201064.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:197680.3-197689.6" + attribute \src "libresoc.v:200716.3-200725.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:197700.3-197709.6" + attribute \src "libresoc.v:200736.3-200745.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:197720.3-197729.6" + attribute \src "libresoc.v:200756.3-200765.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:197740.3-197749.6" + attribute \src "libresoc.v:200776.3-200785.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:197769.3-197778.6" + attribute \src "libresoc.v:200805.3-200814.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:197789.3-197798.6" + attribute \src "libresoc.v:200825.3-200834.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:197809.3-197818.6" + attribute \src "libresoc.v:200845.3-200854.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:197829.3-197838.6" + attribute \src "libresoc.v:200865.3-200874.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:197849.3-197858.6" + attribute \src "libresoc.v:200885.3-200894.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:198039.3-198048.6" + attribute \src "libresoc.v:201075.3-201084.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:197311.13-197311.30" + attribute \src "libresoc.v:200347.13-200347.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:197316.13-197316.29" + attribute \src "libresoc.v:200352.13-200352.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:198058.3-198066.6" - wire $1\ics_wb__ack$next[0:0]$14776 - attribute \src "libresoc.v:197325.7-197325.25" + attribute \src "libresoc.v:201094.3-201102.6" + wire $1\ics_wb__ack$next[0:0]$14890 + attribute \src "libresoc.v:200361.7-200361.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:198049.3-198057.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$14773 - attribute \src "libresoc.v:197334.14-197334.35" + attribute \src "libresoc.v:201085.3-201093.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$14887 + attribute \src "libresoc.v:200370.14-200370.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:197750.3-197758.6" - wire width 16 $1\int_level_l$next[15:0]$14745 - attribute \src "libresoc.v:197346.14-197346.36" + attribute \src "libresoc.v:200786.3-200794.6" + wire width 16 $1\int_level_l$next[15:0]$14859 + attribute \src "libresoc.v:200382.14-200382.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive0_pri$next[7:0]$14670 - attribute \src "libresoc.v:197366.13-197366.30" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive0_pri$next[7:0]$14784 + attribute \src "libresoc.v:200402.13-200402.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive10_pri$next[7:0]$14671 - attribute \src "libresoc.v:197370.13-197370.31" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive10_pri$next[7:0]$14785 + attribute \src "libresoc.v:200406.13-200406.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive11_pri$next[7:0]$14672 - attribute \src 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\src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive14_pri$next[7:0]$14789 + attribute \src "libresoc.v:200422.13-200422.31" wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive15_pri$next[7:0]$14676 - attribute \src "libresoc.v:197390.13-197390.31" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive15_pri$next[7:0]$14790 + attribute \src "libresoc.v:200426.13-200426.31" wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive1_pri$next[7:0]$14677 - attribute \src "libresoc.v:197394.13-197394.30" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive1_pri$next[7:0]$14791 + attribute \src "libresoc.v:200430.13-200430.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive2_pri$next[7:0]$14678 - attribute \src "libresoc.v:197398.13-197398.30" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive2_pri$next[7:0]$14792 + attribute \src "libresoc.v:200434.13-200434.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive3_pri$next[7:0]$14679 - attribute \src "libresoc.v:197402.13-197402.30" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive3_pri$next[7:0]$14793 + attribute \src "libresoc.v:200438.13-200438.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive4_pri$next[7:0]$14680 - attribute \src "libresoc.v:197406.13-197406.30" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive4_pri$next[7:0]$14794 + attribute \src "libresoc.v:200442.13-200442.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive5_pri$next[7:0]$14681 - attribute \src "libresoc.v:197410.13-197410.30" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive5_pri$next[7:0]$14795 + attribute \src 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$1\xive8_pri[7:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $1\xive9_pri$next[7:0]$14685 - attribute \src "libresoc.v:197426.13-197426.30" + attribute \src "libresoc.v:200610.3-200695.6" + wire width 8 $1\xive9_pri$next[7:0]$14799 + attribute \src "libresoc.v:200462.13-200462.30" wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:197959.3-198008.6" + attribute \src "libresoc.v:200995.3-201044.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive0_pri$next[7:0]$14686 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive10_pri$next[7:0]$14687 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive11_pri$next[7:0]$14688 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive12_pri$next[7:0]$14689 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive13_pri$next[7:0]$14690 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive14_pri$next[7:0]$14691 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive15_pri$next[7:0]$14692 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive1_pri$next[7:0]$14693 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive2_pri$next[7:0]$14694 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive3_pri$next[7:0]$14695 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive4_pri$next[7:0]$14696 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive5_pri$next[7:0]$14697 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive6_pri$next[7:0]$14698 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive7_pri$next[7:0]$14699 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive8_pri$next[7:0]$14700 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $2\xive9_pri$next[7:0]$14701 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive0_pri$next[7:0]$14702 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive10_pri$next[7:0]$14703 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive11_pri$next[7:0]$14704 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive12_pri$next[7:0]$14705 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive13_pri$next[7:0]$14706 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive14_pri$next[7:0]$14707 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive15_pri$next[7:0]$14708 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive1_pri$next[7:0]$14709 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive2_pri$next[7:0]$14710 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive3_pri$next[7:0]$14711 - attribute \src "libresoc.v:197574.3-197659.6" - wire width 8 $3\xive4_pri$next[7:0]$14712 - attribute \src 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$and$libresoc.v:200515$14693_Y + attribute \src "libresoc.v:200517.19-200517.115" + wire $and$libresoc.v:200517$14695_Y + attribute \src "libresoc.v:200519.19-200519.115" + wire $and$libresoc.v:200519$14697_Y + attribute \src "libresoc.v:200522.19-200522.115" + wire $and$libresoc.v:200522$14700_Y + attribute \src "libresoc.v:200546.17-200546.115" + wire $and$libresoc.v:200546$14724_Y + attribute \src "libresoc.v:200554.18-200554.112" + wire $and$libresoc.v:200554$14732_Y + attribute \src "libresoc.v:200556.18-200556.112" + wire $and$libresoc.v:200556$14734_Y + attribute \src "libresoc.v:200558.18-200558.112" + wire $and$libresoc.v:200558$14736_Y + attribute \src "libresoc.v:200560.18-200560.112" + wire $and$libresoc.v:200560$14738_Y + attribute \src "libresoc.v:200563.18-200563.112" + wire $and$libresoc.v:200563$14741_Y + attribute \src "libresoc.v:200565.18-200565.112" + wire $and$libresoc.v:200565$14743_Y + attribute \src "libresoc.v:200567.18-200567.112" + wire $and$libresoc.v:200567$14745_Y + attribute \src "libresoc.v:200481.18-200481.109" + wire $eq$libresoc.v:200481$14659_Y + attribute \src "libresoc.v:200503.18-200503.109" + wire $eq$libresoc.v:200503$14681_Y + attribute \src "libresoc.v:200520.17-200520.114" + wire $eq$libresoc.v:200520$14698_Y + attribute \src "libresoc.v:200523.19-200523.110" + wire $eq$libresoc.v:200523$14701_Y + attribute \src "libresoc.v:200525.18-200525.109" + wire $eq$libresoc.v:200525$14703_Y + attribute \src "libresoc.v:200527.18-200527.109" + wire $eq$libresoc.v:200527$14705_Y + attribute \src "libresoc.v:200529.18-200529.109" + wire $eq$libresoc.v:200529$14707_Y + attribute \src "libresoc.v:200531.18-200531.109" + wire $eq$libresoc.v:200531$14709_Y + attribute \src "libresoc.v:200533.18-200533.109" + wire $eq$libresoc.v:200533$14711_Y + attribute \src "libresoc.v:200535.17-200535.114" + wire $eq$libresoc.v:200535$14713_Y + attribute \src "libresoc.v:200536.18-200536.109" + wire $eq$libresoc.v:200536$14714_Y + attribute \src "libresoc.v:200538.18-200538.109" + wire $eq$libresoc.v:200538$14716_Y + attribute \src "libresoc.v:200540.18-200540.110" + wire $eq$libresoc.v:200540$14718_Y + attribute \src "libresoc.v:200542.18-200542.110" + wire $eq$libresoc.v:200542$14720_Y + attribute \src "libresoc.v:200544.18-200544.110" + wire $eq$libresoc.v:200544$14722_Y + attribute \src "libresoc.v:200547.18-200547.110" + wire $eq$libresoc.v:200547$14725_Y + attribute \src "libresoc.v:200549.18-200549.110" + wire $eq$libresoc.v:200549$14727_Y + attribute \src "libresoc.v:200551.18-200551.110" + wire $eq$libresoc.v:200551$14729_Y + attribute \src "libresoc.v:200562.17-200562.108" + wire $eq$libresoc.v:200562$14740_Y + attribute \src "libresoc.v:200466.18-200466.111" + wire $lt$libresoc.v:200466$14644_Y + attribute \src "libresoc.v:200468.19-200468.112" + wire $lt$libresoc.v:200468$14646_Y + attribute \src "libresoc.v:200470.19-200470.112" + wire $lt$libresoc.v:200470$14648_Y + attribute \src "libresoc.v:200472.19-200472.112" + wire $lt$libresoc.v:200472$14650_Y + attribute \src "libresoc.v:200474.19-200474.112" + wire $lt$libresoc.v:200474$14652_Y + attribute \src "libresoc.v:200476.19-200476.112" + wire $lt$libresoc.v:200476$14654_Y + attribute \src "libresoc.v:200478.19-200478.112" + wire $lt$libresoc.v:200478$14656_Y + attribute \src "libresoc.v:200480.19-200480.112" + wire $lt$libresoc.v:200480$14658_Y + attribute \src "libresoc.v:200483.19-200483.112" + wire $lt$libresoc.v:200483$14661_Y + attribute \src "libresoc.v:200485.19-200485.112" + wire $lt$libresoc.v:200485$14663_Y + attribute \src "libresoc.v:200488.19-200488.112" + wire $lt$libresoc.v:200488$14666_Y + attribute \src "libresoc.v:200490.19-200490.112" + wire $lt$libresoc.v:200490$14668_Y + attribute \src "libresoc.v:200492.19-200492.112" + wire $lt$libresoc.v:200492$14670_Y + attribute \src "libresoc.v:200494.19-200494.112" + wire $lt$libresoc.v:200494$14672_Y + attribute \src "libresoc.v:200496.19-200496.113" + wire $lt$libresoc.v:200496$14674_Y + attribute \src "libresoc.v:200498.19-200498.113" + wire $lt$libresoc.v:200498$14676_Y + attribute \src "libresoc.v:200500.19-200500.114" + wire $lt$libresoc.v:200500$14678_Y + attribute \src "libresoc.v:200502.19-200502.114" + wire $lt$libresoc.v:200502$14680_Y + attribute \src "libresoc.v:200505.19-200505.114" + wire $lt$libresoc.v:200505$14683_Y + attribute \src "libresoc.v:200507.19-200507.114" + wire $lt$libresoc.v:200507$14685_Y + attribute \src "libresoc.v:200510.19-200510.114" + wire $lt$libresoc.v:200510$14688_Y + attribute \src "libresoc.v:200512.19-200512.114" + wire $lt$libresoc.v:200512$14690_Y + attribute \src "libresoc.v:200514.19-200514.114" + wire $lt$libresoc.v:200514$14692_Y + attribute \src "libresoc.v:200516.19-200516.114" + wire $lt$libresoc.v:200516$14694_Y + attribute \src "libresoc.v:200518.19-200518.114" + wire $lt$libresoc.v:200518$14696_Y + attribute \src "libresoc.v:200521.19-200521.114" + wire $lt$libresoc.v:200521$14699_Y + attribute \src "libresoc.v:200555.18-200555.110" + wire $lt$libresoc.v:200555$14733_Y + attribute \src "libresoc.v:200557.18-200557.110" + wire $lt$libresoc.v:200557$14735_Y + attribute \src "libresoc.v:200559.18-200559.111" + wire $lt$libresoc.v:200559$14737_Y + attribute \src "libresoc.v:200561.18-200561.111" + wire $lt$libresoc.v:200561$14739_Y + attribute \src "libresoc.v:200564.18-200564.111" + wire $lt$libresoc.v:200564$14742_Y + attribute \src "libresoc.v:200566.18-200566.111" + wire $lt$libresoc.v:200566$14744_Y + attribute \src "libresoc.v:200553.18-200553.40" + wire width 16 $shr$libresoc.v:200553$14731_Y + attribute \src "libresoc.v:200465.17-200465.114" + wire width 8 $ternary$libresoc.v:200465$14643_Y + attribute \src "libresoc.v:200487.18-200487.116" + wire width 8 $ternary$libresoc.v:200487$14665_Y + attribute \src "libresoc.v:200509.18-200509.116" + wire width 8 $ternary$libresoc.v:200509$14687_Y + attribute \src "libresoc.v:200524.19-200524.118" + wire width 8 $ternary$libresoc.v:200524$14702_Y + attribute \src "libresoc.v:200526.18-200526.116" + wire width 8 $ternary$libresoc.v:200526$14704_Y + attribute \src "libresoc.v:200528.18-200528.116" + wire width 8 $ternary$libresoc.v:200528$14706_Y + attribute \src "libresoc.v:200530.18-200530.116" + wire width 8 $ternary$libresoc.v:200530$14708_Y + attribute \src "libresoc.v:200532.18-200532.116" + wire width 8 $ternary$libresoc.v:200532$14710_Y + attribute \src "libresoc.v:200534.18-200534.116" + wire width 8 $ternary$libresoc.v:200534$14712_Y + attribute \src "libresoc.v:200537.18-200537.116" + wire width 8 $ternary$libresoc.v:200537$14715_Y + attribute \src "libresoc.v:200539.18-200539.116" + wire width 8 $ternary$libresoc.v:200539$14717_Y + attribute \src "libresoc.v:200541.18-200541.117" + wire width 8 $ternary$libresoc.v:200541$14719_Y + attribute \src "libresoc.v:200543.18-200543.117" + wire width 8 $ternary$libresoc.v:200543$14721_Y + attribute \src "libresoc.v:200545.18-200545.117" + wire width 8 $ternary$libresoc.v:200545$14723_Y + attribute \src "libresoc.v:200548.18-200548.117" + wire width 8 $ternary$libresoc.v:200548$14726_Y + attribute \src "libresoc.v:200550.18-200550.117" + wire width 8 $ternary$libresoc.v:200550$14728_Y + attribute \src "libresoc.v:200552.18-200552.117" + wire width 8 $ternary$libresoc.v:200552$14730_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -415480,7 +420138,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -415549,11 +420207,11 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" wire \ibit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 output 2 \icp_o_pri + wire width 8 output 3 \icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 \icp_o_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 output 1 \icp_o_src + wire width 4 output 2 \icp_o_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \icp_o_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" @@ -415578,7 +420236,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:197030.7-197030.15" + attribute \src "libresoc.v:200066.7-200066.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -415598,8 +420256,8 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" - wire input 3 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" @@ -415667,7 +420325,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197431$14531 + cell $and $and$libresoc.v:200467$14645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415675,10 +420333,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:197431$14531_Y + connect \Y $and$libresoc.v:200467$14645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197433$14533 + cell $and $and$libresoc.v:200469$14647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415686,10 +420344,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:197433$14533_Y + connect \Y $and$libresoc.v:200469$14647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197435$14535 + cell $and $and$libresoc.v:200471$14649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415697,10 +420355,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:197435$14535_Y + connect \Y $and$libresoc.v:200471$14649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197437$14537 + cell $and $and$libresoc.v:200473$14651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415708,10 +420366,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:197437$14537_Y + connect \Y $and$libresoc.v:200473$14651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197439$14539 + cell $and $and$libresoc.v:200475$14653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415719,10 +420377,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:197439$14539_Y + connect \Y $and$libresoc.v:200475$14653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197441$14541 + cell $and $and$libresoc.v:200477$14655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415730,10 +420388,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:197441$14541_Y + connect \Y $and$libresoc.v:200477$14655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197443$14543 + cell $and $and$libresoc.v:200479$14657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415741,10 +420399,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:197443$14543_Y + connect \Y $and$libresoc.v:200479$14657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197446$14546 + cell $and $and$libresoc.v:200482$14660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415752,10 +420410,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:197446$14546_Y + connect \Y $and$libresoc.v:200482$14660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197448$14548 + cell $and $and$libresoc.v:200484$14662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415763,10 +420421,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:197448$14548_Y + connect \Y $and$libresoc.v:200484$14662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197450$14550 + cell $and $and$libresoc.v:200486$14664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415774,10 +420432,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:197450$14550_Y + connect \Y $and$libresoc.v:200486$14664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197453$14553 + cell $and $and$libresoc.v:200489$14667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415785,10 +420443,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:197453$14553_Y + connect \Y $and$libresoc.v:200489$14667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197455$14555 + cell $and $and$libresoc.v:200491$14669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415796,10 +420454,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:197455$14555_Y + connect \Y $and$libresoc.v:200491$14669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197457$14557 + cell $and $and$libresoc.v:200493$14671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415807,10 +420465,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:197457$14557_Y + connect \Y $and$libresoc.v:200493$14671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197459$14559 + cell $and $and$libresoc.v:200495$14673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415818,10 +420476,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:197459$14559_Y + connect \Y $and$libresoc.v:200495$14673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197461$14561 + cell $and $and$libresoc.v:200497$14675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415829,10 +420487,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:197461$14561_Y + connect \Y $and$libresoc.v:200497$14675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197463$14563 + cell $and $and$libresoc.v:200499$14677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415840,10 +420498,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:197463$14563_Y + connect \Y $and$libresoc.v:200499$14677_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197465$14565 + cell $and $and$libresoc.v:200501$14679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415851,10 +420509,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:197465$14565_Y + connect \Y $and$libresoc.v:200501$14679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197468$14568 + cell $and $and$libresoc.v:200504$14682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415862,10 +420520,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:197468$14568_Y + connect \Y $and$libresoc.v:200504$14682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197470$14570 + cell $and $and$libresoc.v:200506$14684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415873,10 +420531,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:197470$14570_Y + connect \Y $and$libresoc.v:200506$14684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197472$14572 + cell $and $and$libresoc.v:200508$14686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415884,10 +420542,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:197472$14572_Y + connect \Y $and$libresoc.v:200508$14686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197475$14575 + cell $and $and$libresoc.v:200511$14689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415895,10 +420553,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:197475$14575_Y + connect \Y $and$libresoc.v:200511$14689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197477$14577 + cell $and $and$libresoc.v:200513$14691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415906,10 +420564,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:197477$14577_Y + connect \Y $and$libresoc.v:200513$14691_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197479$14579 + cell $and $and$libresoc.v:200515$14693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415917,10 +420575,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:197479$14579_Y + connect \Y $and$libresoc.v:200515$14693_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197481$14581 + cell $and $and$libresoc.v:200517$14695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415928,10 +420586,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:197481$14581_Y + connect \Y $and$libresoc.v:200517$14695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197483$14583 + cell $and $and$libresoc.v:200519$14697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415939,10 +420597,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:197483$14583_Y + connect \Y $and$libresoc.v:200519$14697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197486$14586 + cell $and $and$libresoc.v:200522$14700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415950,10 +420608,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:197486$14586_Y + connect \Y $and$libresoc.v:200522$14700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:197510$14610 + cell $and $and$libresoc.v:200546$14724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415961,10 +420619,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:197510$14610_Y + connect \Y $and$libresoc.v:200546$14724_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:197518$14618 + cell $and $and$libresoc.v:200554$14732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415972,10 +420630,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:197518$14618_Y + connect \Y $and$libresoc.v:200554$14732_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197520$14620 + cell $and $and$libresoc.v:200556$14734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415983,10 +420641,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:197520$14620_Y + connect \Y $and$libresoc.v:200556$14734_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197522$14622 + cell $and $and$libresoc.v:200558$14736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415994,10 +420652,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:197522$14622_Y + connect \Y $and$libresoc.v:200558$14736_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197524$14624 + cell $and $and$libresoc.v:200560$14738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416005,10 +420663,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:197524$14624_Y + connect \Y $and$libresoc.v:200560$14738_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197527$14627 + cell $and $and$libresoc.v:200563$14741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416016,10 +420674,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:197527$14627_Y + connect \Y $and$libresoc.v:200563$14741_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197529$14629 + cell $and $and$libresoc.v:200565$14743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416027,10 +420685,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:197529$14629_Y + connect \Y $and$libresoc.v:200565$14743_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:197531$14631 + cell $and $and$libresoc.v:200567$14745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416038,10 +420696,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:197531$14631_Y + connect \Y $and$libresoc.v:200567$14745_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197445$14545 + cell $eq $eq$libresoc.v:200481$14659 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416049,10 +420707,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197445$14545_Y + connect \Y $eq$libresoc.v:200481$14659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197467$14567 + cell $eq $eq$libresoc.v:200503$14681 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416060,10 +420718,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197467$14567_Y + connect \Y $eq$libresoc.v:200503$14681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:197484$14584 + cell $eq $eq$libresoc.v:200520$14698 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -416071,10 +420729,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:197484$14584_Y + connect \Y $eq$libresoc.v:200520$14698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197487$14587 + cell $eq $eq$libresoc.v:200523$14701 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416082,10 +420740,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:197487$14587_Y + connect \Y $eq$libresoc.v:200523$14701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197489$14589 + cell $eq $eq$libresoc.v:200525$14703 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416093,10 +420751,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197489$14589_Y + connect \Y $eq$libresoc.v:200525$14703_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197491$14591 + cell $eq $eq$libresoc.v:200527$14705 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416104,10 +420762,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197491$14591_Y + connect \Y $eq$libresoc.v:200527$14705_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197493$14593 + cell $eq $eq$libresoc.v:200529$14707 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416115,10 +420773,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197493$14593_Y + connect \Y $eq$libresoc.v:200529$14707_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197495$14595 + cell $eq $eq$libresoc.v:200531$14709 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416126,10 +420784,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197495$14595_Y + connect \Y $eq$libresoc.v:200531$14709_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197497$14597 + cell $eq $eq$libresoc.v:200533$14711 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416137,10 +420795,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197497$14597_Y + connect \Y $eq$libresoc.v:200533$14711_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:197499$14599 + cell $eq $eq$libresoc.v:200535$14713 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -416148,10 +420806,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:197499$14599_Y + connect \Y $eq$libresoc.v:200535$14713_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197500$14600 + cell $eq $eq$libresoc.v:200536$14714 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416159,10 +420817,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197500$14600_Y + connect \Y $eq$libresoc.v:200536$14714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197502$14602 + cell $eq $eq$libresoc.v:200538$14716 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416170,10 +420828,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197502$14602_Y + connect \Y $eq$libresoc.v:200538$14716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197504$14604 + cell $eq $eq$libresoc.v:200540$14718 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416181,10 +420839,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197504$14604_Y + connect \Y $eq$libresoc.v:200540$14718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197506$14606 + cell $eq $eq$libresoc.v:200542$14720 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416192,10 +420850,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197506$14606_Y + connect \Y $eq$libresoc.v:200542$14720_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197508$14608 + cell $eq $eq$libresoc.v:200544$14722 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416203,10 +420861,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197508$14608_Y + connect \Y $eq$libresoc.v:200544$14722_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197511$14611 + cell $eq $eq$libresoc.v:200547$14725 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416214,10 +420872,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197511$14611_Y + connect \Y $eq$libresoc.v:200547$14725_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197513$14613 + cell $eq $eq$libresoc.v:200549$14727 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416225,10 +420883,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197513$14613_Y + connect \Y $eq$libresoc.v:200549$14727_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197515$14615 + cell $eq $eq$libresoc.v:200551$14729 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416236,10 +420894,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197515$14615_Y + connect \Y $eq$libresoc.v:200551$14729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:197526$14626 + cell $eq $eq$libresoc.v:200562$14740 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416247,10 +420905,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:197526$14626_Y + connect \Y $eq$libresoc.v:200562$14740_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197430$14530 + cell $lt $lt$libresoc.v:200466$14644 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416258,10 +420916,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:197430$14530_Y + connect \Y $lt$libresoc.v:200466$14644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197432$14532 + cell $lt $lt$libresoc.v:200468$14646 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416269,10 +420927,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:197432$14532_Y + connect \Y $lt$libresoc.v:200468$14646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197434$14534 + cell $lt $lt$libresoc.v:200470$14648 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416280,10 +420938,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:197434$14534_Y + connect \Y $lt$libresoc.v:200470$14648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197436$14536 + cell $lt $lt$libresoc.v:200472$14650 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416291,10 +420949,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:197436$14536_Y + connect \Y $lt$libresoc.v:200472$14650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197438$14538 + cell $lt $lt$libresoc.v:200474$14652 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416302,10 +420960,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:197438$14538_Y + connect \Y $lt$libresoc.v:200474$14652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197440$14540 + cell $lt $lt$libresoc.v:200476$14654 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416313,10 +420971,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:197440$14540_Y + connect \Y $lt$libresoc.v:200476$14654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197442$14542 + cell $lt $lt$libresoc.v:200478$14656 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416324,10 +420982,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:197442$14542_Y + connect \Y $lt$libresoc.v:200478$14656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197444$14544 + cell $lt $lt$libresoc.v:200480$14658 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416335,10 +420993,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:197444$14544_Y + connect \Y $lt$libresoc.v:200480$14658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197447$14547 + cell $lt $lt$libresoc.v:200483$14661 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416346,10 +421004,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:197447$14547_Y + connect \Y $lt$libresoc.v:200483$14661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197449$14549 + cell $lt $lt$libresoc.v:200485$14663 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416357,10 +421015,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:197449$14549_Y + connect \Y $lt$libresoc.v:200485$14663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197452$14552 + cell $lt $lt$libresoc.v:200488$14666 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416368,10 +421026,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:197452$14552_Y + connect \Y $lt$libresoc.v:200488$14666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197454$14554 + cell $lt $lt$libresoc.v:200490$14668 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416379,10 +421037,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:197454$14554_Y + connect \Y $lt$libresoc.v:200490$14668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197456$14556 + cell $lt $lt$libresoc.v:200492$14670 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416390,10 +421048,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:197456$14556_Y + connect \Y $lt$libresoc.v:200492$14670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197458$14558 + cell $lt $lt$libresoc.v:200494$14672 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416401,10 +421059,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:197458$14558_Y + connect \Y $lt$libresoc.v:200494$14672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197460$14560 + cell $lt $lt$libresoc.v:200496$14674 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416412,10 +421070,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:197460$14560_Y + connect \Y $lt$libresoc.v:200496$14674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197462$14562 + cell $lt $lt$libresoc.v:200498$14676 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416423,10 +421081,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:197462$14562_Y + connect \Y $lt$libresoc.v:200498$14676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197464$14564 + cell $lt $lt$libresoc.v:200500$14678 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416434,10 +421092,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:197464$14564_Y + connect \Y $lt$libresoc.v:200500$14678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197466$14566 + cell $lt $lt$libresoc.v:200502$14680 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416445,10 +421103,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:197466$14566_Y + connect \Y $lt$libresoc.v:200502$14680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197469$14569 + cell $lt $lt$libresoc.v:200505$14683 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416456,10 +421114,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:197469$14569_Y + connect \Y $lt$libresoc.v:200505$14683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197471$14571 + cell $lt $lt$libresoc.v:200507$14685 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416467,10 +421125,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:197471$14571_Y + connect \Y $lt$libresoc.v:200507$14685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197474$14574 + cell $lt $lt$libresoc.v:200510$14688 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416478,10 +421136,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:197474$14574_Y + connect \Y $lt$libresoc.v:200510$14688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197476$14576 + cell $lt $lt$libresoc.v:200512$14690 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416489,10 +421147,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:197476$14576_Y + connect \Y $lt$libresoc.v:200512$14690_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197478$14578 + cell $lt $lt$libresoc.v:200514$14692 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416500,10 +421158,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:197478$14578_Y + connect \Y $lt$libresoc.v:200514$14692_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197480$14580 + cell $lt $lt$libresoc.v:200516$14694 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416511,10 +421169,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:197480$14580_Y + connect \Y $lt$libresoc.v:200516$14694_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197482$14582 + cell $lt $lt$libresoc.v:200518$14696 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416522,10 +421180,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:197482$14582_Y + connect \Y $lt$libresoc.v:200518$14696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197485$14585 + cell $lt $lt$libresoc.v:200521$14699 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416533,10 +421191,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:197485$14585_Y + connect \Y $lt$libresoc.v:200521$14699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197519$14619 + cell $lt $lt$libresoc.v:200555$14733 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416544,10 +421202,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:197519$14619_Y + connect \Y $lt$libresoc.v:200555$14733_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197521$14621 + cell $lt $lt$libresoc.v:200557$14735 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416555,10 +421213,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:197521$14621_Y + connect \Y $lt$libresoc.v:200557$14735_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197523$14623 + cell $lt $lt$libresoc.v:200559$14737 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416566,10 +421224,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:197523$14623_Y + connect \Y $lt$libresoc.v:200559$14737_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197525$14625 + cell $lt $lt$libresoc.v:200561$14739 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416577,10 +421235,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:197525$14625_Y + connect \Y $lt$libresoc.v:200561$14739_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197528$14628 + cell $lt $lt$libresoc.v:200564$14742 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416588,10 +421246,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:197528$14628_Y + connect \Y $lt$libresoc.v:200564$14742_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:197530$14630 + cell $lt $lt$libresoc.v:200566$14744 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -416599,10 +421257,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:197530$14630_Y + connect \Y $lt$libresoc.v:200566$14744_Y end - attribute \src "libresoc.v:197517.18-197517.40" - cell $shr $shr$libresoc.v:197517$14617 + attribute \src "libresoc.v:200553.18-200553.40" + cell $shr $shr$libresoc.v:200553$14731 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -416610,469 +421268,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:197517$14617_Y + connect \Y $shr$libresoc.v:200553$14731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197429$14529 + cell $mux $ternary$libresoc.v:200465$14643 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:197429$14529_Y + connect \Y $ternary$libresoc.v:200465$14643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197451$14551 + cell $mux $ternary$libresoc.v:200487$14665 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:197451$14551_Y + connect \Y $ternary$libresoc.v:200487$14665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197473$14573 + cell $mux $ternary$libresoc.v:200509$14687 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:197473$14573_Y + connect \Y $ternary$libresoc.v:200509$14687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197488$14588 + cell $mux $ternary$libresoc.v:200524$14702 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:197488$14588_Y + connect \Y $ternary$libresoc.v:200524$14702_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197490$14590 + cell $mux $ternary$libresoc.v:200526$14704 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:197490$14590_Y + connect \Y $ternary$libresoc.v:200526$14704_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197492$14592 + cell $mux $ternary$libresoc.v:200528$14706 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:197492$14592_Y + connect \Y $ternary$libresoc.v:200528$14706_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197494$14594 + cell $mux $ternary$libresoc.v:200530$14708 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:197494$14594_Y + connect \Y $ternary$libresoc.v:200530$14708_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197496$14596 + cell $mux $ternary$libresoc.v:200532$14710 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:197496$14596_Y + connect \Y $ternary$libresoc.v:200532$14710_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197498$14598 + cell $mux $ternary$libresoc.v:200534$14712 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:197498$14598_Y + connect \Y $ternary$libresoc.v:200534$14712_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197501$14601 + cell $mux $ternary$libresoc.v:200537$14715 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:197501$14601_Y + connect \Y $ternary$libresoc.v:200537$14715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197503$14603 + cell $mux $ternary$libresoc.v:200539$14717 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:197503$14603_Y + connect \Y $ternary$libresoc.v:200539$14717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197505$14605 + cell $mux $ternary$libresoc.v:200541$14719 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:197505$14605_Y + connect \Y $ternary$libresoc.v:200541$14719_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197507$14607 + cell $mux $ternary$libresoc.v:200543$14721 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:197507$14607_Y + connect \Y $ternary$libresoc.v:200543$14721_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197509$14609 + cell $mux $ternary$libresoc.v:200545$14723 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:197509$14609_Y + connect \Y $ternary$libresoc.v:200545$14723_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197512$14612 + cell $mux $ternary$libresoc.v:200548$14726 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:197512$14612_Y + connect \Y $ternary$libresoc.v:200548$14726_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197514$14614 + cell $mux $ternary$libresoc.v:200550$14728 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:197514$14614_Y + connect \Y $ternary$libresoc.v:200550$14728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:197516$14616 + cell $mux $ternary$libresoc.v:200552$14730 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:197516$14616_Y + connect \Y $ternary$libresoc.v:200552$14730_Y end - attribute \src "libresoc.v:197030.7-197030.20" - process $proc$libresoc.v:197030$14777 + attribute \src "libresoc.v:200066.7-200066.20" + process $proc$libresoc.v:200066$14891 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:197311.13-197311.30" - process $proc$libresoc.v:197311$14778 + attribute \src "libresoc.v:200347.13-200347.30" + process $proc$libresoc.v:200347$14892 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:197316.13-197316.29" - process $proc$libresoc.v:197316$14779 + attribute \src "libresoc.v:200352.13-200352.29" + process $proc$libresoc.v:200352$14893 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:197325.7-197325.25" - process $proc$libresoc.v:197325$14780 + attribute \src "libresoc.v:200361.7-200361.25" + process $proc$libresoc.v:200361$14894 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:197334.14-197334.35" - process $proc$libresoc.v:197334$14781 + attribute \src "libresoc.v:200370.14-200370.35" + process $proc$libresoc.v:200370$14895 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:197346.14-197346.36" - process $proc$libresoc.v:197346$14782 + attribute \src "libresoc.v:200382.14-200382.36" + process $proc$libresoc.v:200382$14896 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:197366.13-197366.30" - process $proc$libresoc.v:197366$14783 + attribute \src "libresoc.v:200402.13-200402.30" + process $proc$libresoc.v:200402$14897 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:197370.13-197370.31" - process $proc$libresoc.v:197370$14784 + attribute \src "libresoc.v:200406.13-200406.31" + process $proc$libresoc.v:200406$14898 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:197374.13-197374.31" - process $proc$libresoc.v:197374$14785 + attribute \src "libresoc.v:200410.13-200410.31" + process $proc$libresoc.v:200410$14899 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:197378.13-197378.31" - process $proc$libresoc.v:197378$14786 + attribute \src "libresoc.v:200414.13-200414.31" + process $proc$libresoc.v:200414$14900 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:197382.13-197382.31" - process $proc$libresoc.v:197382$14787 + attribute \src "libresoc.v:200418.13-200418.31" + process $proc$libresoc.v:200418$14901 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:197386.13-197386.31" - process $proc$libresoc.v:197386$14788 + attribute \src "libresoc.v:200422.13-200422.31" + process $proc$libresoc.v:200422$14902 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:197390.13-197390.31" - process $proc$libresoc.v:197390$14789 + attribute \src "libresoc.v:200426.13-200426.31" + process $proc$libresoc.v:200426$14903 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:197394.13-197394.30" - process $proc$libresoc.v:197394$14790 + attribute \src "libresoc.v:200430.13-200430.30" + process $proc$libresoc.v:200430$14904 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:197398.13-197398.30" - process $proc$libresoc.v:197398$14791 + attribute \src "libresoc.v:200434.13-200434.30" + process $proc$libresoc.v:200434$14905 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:197402.13-197402.30" - process $proc$libresoc.v:197402$14792 + attribute \src "libresoc.v:200438.13-200438.30" + process $proc$libresoc.v:200438$14906 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:197406.13-197406.30" - process $proc$libresoc.v:197406$14793 + attribute \src "libresoc.v:200442.13-200442.30" + process $proc$libresoc.v:200442$14907 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:197410.13-197410.30" - process $proc$libresoc.v:197410$14794 + attribute \src "libresoc.v:200446.13-200446.30" + process $proc$libresoc.v:200446$14908 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:197414.13-197414.30" - process $proc$libresoc.v:197414$14795 + attribute \src "libresoc.v:200450.13-200450.30" + process $proc$libresoc.v:200450$14909 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:197418.13-197418.30" - process $proc$libresoc.v:197418$14796 + attribute \src "libresoc.v:200454.13-200454.30" + process $proc$libresoc.v:200454$14910 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:197422.13-197422.30" - process $proc$libresoc.v:197422$14797 + attribute \src "libresoc.v:200458.13-200458.30" + process $proc$libresoc.v:200458$14911 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:197426.13-197426.30" - process $proc$libresoc.v:197426$14798 + attribute \src "libresoc.v:200462.13-200462.30" + process $proc$libresoc.v:200462$14912 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:197532.3-197533.28" - process $proc$libresoc.v:197532$14632 + attribute \src "libresoc.v:200568.3-200569.28" + process $proc$libresoc.v:200568$14746 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:197534.3-197535.25" - process $proc$libresoc.v:197534$14633 + attribute \src "libresoc.v:200570.3-200571.25" + process $proc$libresoc.v:200570$14747 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:197536.3-197537.35" - process $proc$libresoc.v:197536$14634 + attribute \src "libresoc.v:200572.3-200573.35" + process $proc$libresoc.v:200572$14748 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:197538.3-197539.35" - process $proc$libresoc.v:197538$14635 + attribute \src "libresoc.v:200574.3-200575.35" + process $proc$libresoc.v:200574$14749 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:197540.3-197541.35" - process $proc$libresoc.v:197540$14636 + attribute \src "libresoc.v:200576.3-200577.35" + process $proc$libresoc.v:200576$14750 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:197542.3-197543.35" - process $proc$libresoc.v:197542$14637 + attribute \src "libresoc.v:200578.3-200579.35" + process $proc$libresoc.v:200578$14751 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:197544.3-197545.35" - process $proc$libresoc.v:197544$14638 + attribute \src "libresoc.v:200580.3-200581.35" + process $proc$libresoc.v:200580$14752 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:197546.3-197547.35" - process $proc$libresoc.v:197546$14639 + attribute \src "libresoc.v:200582.3-200583.35" + process $proc$libresoc.v:200582$14753 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:197548.3-197549.35" - process $proc$libresoc.v:197548$14640 + attribute \src "libresoc.v:200584.3-200585.35" + process $proc$libresoc.v:200584$14754 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:197550.3-197551.35" - process $proc$libresoc.v:197550$14641 + attribute \src "libresoc.v:200586.3-200587.35" + process $proc$libresoc.v:200586$14755 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:197552.3-197553.35" - process $proc$libresoc.v:197552$14642 + attribute \src "libresoc.v:200588.3-200589.35" + process $proc$libresoc.v:200588$14756 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:197554.3-197555.35" - process $proc$libresoc.v:197554$14643 + attribute \src "libresoc.v:200590.3-200591.35" + process $proc$libresoc.v:200590$14757 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:197556.3-197557.37" - process $proc$libresoc.v:197556$14644 + attribute \src "libresoc.v:200592.3-200593.37" + process $proc$libresoc.v:200592$14758 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:197558.3-197559.37" - process $proc$libresoc.v:197558$14645 + attribute \src "libresoc.v:200594.3-200595.37" + process $proc$libresoc.v:200594$14759 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:197560.3-197561.37" - process $proc$libresoc.v:197560$14646 + attribute \src "libresoc.v:200596.3-200597.37" + process $proc$libresoc.v:200596$14760 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:197562.3-197563.37" - process $proc$libresoc.v:197562$14647 + attribute \src "libresoc.v:200598.3-200599.37" + process $proc$libresoc.v:200598$14761 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:197564.3-197565.37" - process $proc$libresoc.v:197564$14648 + attribute \src "libresoc.v:200600.3-200601.37" + process $proc$libresoc.v:200600$14762 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:197566.3-197567.37" - process $proc$libresoc.v:197566$14649 + attribute \src "libresoc.v:200602.3-200603.37" + process $proc$libresoc.v:200602$14763 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:197568.3-197569.39" - process $proc$libresoc.v:197568$14650 + attribute \src "libresoc.v:200604.3-200605.39" + process $proc$libresoc.v:200604$14764 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:197570.3-197571.43" - process $proc$libresoc.v:197570$14651 + attribute \src "libresoc.v:200606.3-200607.43" + process $proc$libresoc.v:200606$14765 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:197572.3-197573.39" - process $proc$libresoc.v:197572$14652 + attribute \src "libresoc.v:200608.3-200609.39" + process $proc$libresoc.v:200608$14766 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:197574.3-197659.6" - process $proc$libresoc.v:197574$14653 + attribute \src "libresoc.v:200610.3-200695.6" + process $proc$libresoc.v:200610$14767 assign { } { } assign { } { } assign { } { } @@ -417121,25 +421779,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14654 $4\xive0_pri$next[7:0]$14718 - assign $0\xive10_pri$next[7:0]$14655 $4\xive10_pri$next[7:0]$14719 - assign $0\xive11_pri$next[7:0]$14656 $4\xive11_pri$next[7:0]$14720 - assign $0\xive12_pri$next[7:0]$14657 $4\xive12_pri$next[7:0]$14721 - assign $0\xive13_pri$next[7:0]$14658 $4\xive13_pri$next[7:0]$14722 - assign $0\xive14_pri$next[7:0]$14659 $4\xive14_pri$next[7:0]$14723 - assign $0\xive15_pri$next[7:0]$14660 $4\xive15_pri$next[7:0]$14724 - assign $0\xive1_pri$next[7:0]$14661 $4\xive1_pri$next[7:0]$14725 - assign $0\xive2_pri$next[7:0]$14662 $4\xive2_pri$next[7:0]$14726 - assign $0\xive3_pri$next[7:0]$14663 $4\xive3_pri$next[7:0]$14727 - assign $0\xive4_pri$next[7:0]$14664 $4\xive4_pri$next[7:0]$14728 - assign $0\xive5_pri$next[7:0]$14665 $4\xive5_pri$next[7:0]$14729 - assign $0\xive6_pri$next[7:0]$14666 $4\xive6_pri$next[7:0]$14730 - assign $0\xive7_pri$next[7:0]$14667 $4\xive7_pri$next[7:0]$14731 - assign $0\xive8_pri$next[7:0]$14668 $4\xive8_pri$next[7:0]$14732 - assign $0\xive9_pri$next[7:0]$14669 $4\xive9_pri$next[7:0]$14733 - attribute \src "libresoc.v:197575.5-197575.29" + assign $0\xive0_pri$next[7:0]$14768 $4\xive0_pri$next[7:0]$14832 + assign $0\xive10_pri$next[7:0]$14769 $4\xive10_pri$next[7:0]$14833 + assign $0\xive11_pri$next[7:0]$14770 $4\xive11_pri$next[7:0]$14834 + assign $0\xive12_pri$next[7:0]$14771 $4\xive12_pri$next[7:0]$14835 + assign $0\xive13_pri$next[7:0]$14772 $4\xive13_pri$next[7:0]$14836 + assign $0\xive14_pri$next[7:0]$14773 $4\xive14_pri$next[7:0]$14837 + assign $0\xive15_pri$next[7:0]$14774 $4\xive15_pri$next[7:0]$14838 + assign $0\xive1_pri$next[7:0]$14775 $4\xive1_pri$next[7:0]$14839 + assign $0\xive2_pri$next[7:0]$14776 $4\xive2_pri$next[7:0]$14840 + assign $0\xive3_pri$next[7:0]$14777 $4\xive3_pri$next[7:0]$14841 + assign $0\xive4_pri$next[7:0]$14778 $4\xive4_pri$next[7:0]$14842 + assign $0\xive5_pri$next[7:0]$14779 $4\xive5_pri$next[7:0]$14843 + assign $0\xive6_pri$next[7:0]$14780 $4\xive6_pri$next[7:0]$14844 + assign $0\xive7_pri$next[7:0]$14781 $4\xive7_pri$next[7:0]$14845 + assign $0\xive8_pri$next[7:0]$14782 $4\xive8_pri$next[7:0]$14846 + assign $0\xive9_pri$next[7:0]$14783 $4\xive9_pri$next[7:0]$14847 + attribute \src "libresoc.v:200611.5-200611.29" switch \initial - attribute \src "libresoc.v:197575.9-197575.17" + attribute \src "libresoc.v:200611.9-200611.17" case 1'1 case end @@ -417163,22 +421821,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14670 $2\xive0_pri$next[7:0]$14686 - assign $1\xive10_pri$next[7:0]$14671 $2\xive10_pri$next[7:0]$14687 - assign $1\xive11_pri$next[7:0]$14672 $2\xive11_pri$next[7:0]$14688 - assign $1\xive12_pri$next[7:0]$14673 $2\xive12_pri$next[7:0]$14689 - assign $1\xive13_pri$next[7:0]$14674 $2\xive13_pri$next[7:0]$14690 - assign $1\xive14_pri$next[7:0]$14675 $2\xive14_pri$next[7:0]$14691 - assign $1\xive15_pri$next[7:0]$14676 $2\xive15_pri$next[7:0]$14692 - assign $1\xive1_pri$next[7:0]$14677 $2\xive1_pri$next[7:0]$14693 - assign $1\xive2_pri$next[7:0]$14678 $2\xive2_pri$next[7:0]$14694 - assign $1\xive3_pri$next[7:0]$14679 $2\xive3_pri$next[7:0]$14695 - assign $1\xive4_pri$next[7:0]$14680 $2\xive4_pri$next[7:0]$14696 - assign $1\xive5_pri$next[7:0]$14681 $2\xive5_pri$next[7:0]$14697 - assign $1\xive6_pri$next[7:0]$14682 $2\xive6_pri$next[7:0]$14698 - assign $1\xive7_pri$next[7:0]$14683 $2\xive7_pri$next[7:0]$14699 - assign $1\xive8_pri$next[7:0]$14684 $2\xive8_pri$next[7:0]$14700 - assign $1\xive9_pri$next[7:0]$14685 $2\xive9_pri$next[7:0]$14701 + assign $1\xive0_pri$next[7:0]$14784 $2\xive0_pri$next[7:0]$14800 + assign $1\xive10_pri$next[7:0]$14785 $2\xive10_pri$next[7:0]$14801 + assign $1\xive11_pri$next[7:0]$14786 $2\xive11_pri$next[7:0]$14802 + assign $1\xive12_pri$next[7:0]$14787 $2\xive12_pri$next[7:0]$14803 + assign $1\xive13_pri$next[7:0]$14788 $2\xive13_pri$next[7:0]$14804 + assign $1\xive14_pri$next[7:0]$14789 $2\xive14_pri$next[7:0]$14805 + assign $1\xive15_pri$next[7:0]$14790 $2\xive15_pri$next[7:0]$14806 + assign $1\xive1_pri$next[7:0]$14791 $2\xive1_pri$next[7:0]$14807 + assign $1\xive2_pri$next[7:0]$14792 $2\xive2_pri$next[7:0]$14808 + assign $1\xive3_pri$next[7:0]$14793 $2\xive3_pri$next[7:0]$14809 + assign $1\xive4_pri$next[7:0]$14794 $2\xive4_pri$next[7:0]$14810 + assign $1\xive5_pri$next[7:0]$14795 $2\xive5_pri$next[7:0]$14811 + assign $1\xive6_pri$next[7:0]$14796 $2\xive6_pri$next[7:0]$14812 + assign $1\xive7_pri$next[7:0]$14797 $2\xive7_pri$next[7:0]$14813 + assign $1\xive8_pri$next[7:0]$14798 $2\xive8_pri$next[7:0]$14814 + assign $1\xive9_pri$next[7:0]$14799 $2\xive9_pri$next[7:0]$14815 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -417199,381 +421857,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14686 $3\xive0_pri$next[7:0]$14702 - assign $2\xive10_pri$next[7:0]$14687 $3\xive10_pri$next[7:0]$14703 - assign $2\xive11_pri$next[7:0]$14688 $3\xive11_pri$next[7:0]$14704 - assign $2\xive12_pri$next[7:0]$14689 $3\xive12_pri$next[7:0]$14705 - assign $2\xive13_pri$next[7:0]$14690 $3\xive13_pri$next[7:0]$14706 - assign $2\xive14_pri$next[7:0]$14691 $3\xive14_pri$next[7:0]$14707 - assign $2\xive15_pri$next[7:0]$14692 $3\xive15_pri$next[7:0]$14708 - assign $2\xive1_pri$next[7:0]$14693 $3\xive1_pri$next[7:0]$14709 - assign $2\xive2_pri$next[7:0]$14694 $3\xive2_pri$next[7:0]$14710 - assign $2\xive3_pri$next[7:0]$14695 $3\xive3_pri$next[7:0]$14711 - assign $2\xive4_pri$next[7:0]$14696 $3\xive4_pri$next[7:0]$14712 - assign $2\xive5_pri$next[7:0]$14697 $3\xive5_pri$next[7:0]$14713 - assign $2\xive6_pri$next[7:0]$14698 $3\xive6_pri$next[7:0]$14714 - assign $2\xive7_pri$next[7:0]$14699 $3\xive7_pri$next[7:0]$14715 - assign $2\xive8_pri$next[7:0]$14700 $3\xive8_pri$next[7:0]$14716 - assign $2\xive9_pri$next[7:0]$14701 $3\xive9_pri$next[7:0]$14717 + assign $2\xive0_pri$next[7:0]$14800 $3\xive0_pri$next[7:0]$14816 + assign $2\xive10_pri$next[7:0]$14801 $3\xive10_pri$next[7:0]$14817 + assign $2\xive11_pri$next[7:0]$14802 $3\xive11_pri$next[7:0]$14818 + assign $2\xive12_pri$next[7:0]$14803 $3\xive12_pri$next[7:0]$14819 + assign $2\xive13_pri$next[7:0]$14804 $3\xive13_pri$next[7:0]$14820 + assign $2\xive14_pri$next[7:0]$14805 $3\xive14_pri$next[7:0]$14821 + assign $2\xive15_pri$next[7:0]$14806 $3\xive15_pri$next[7:0]$14822 + assign $2\xive1_pri$next[7:0]$14807 $3\xive1_pri$next[7:0]$14823 + assign $2\xive2_pri$next[7:0]$14808 $3\xive2_pri$next[7:0]$14824 + assign $2\xive3_pri$next[7:0]$14809 $3\xive3_pri$next[7:0]$14825 + assign $2\xive4_pri$next[7:0]$14810 $3\xive4_pri$next[7:0]$14826 + assign $2\xive5_pri$next[7:0]$14811 $3\xive5_pri$next[7:0]$14827 + assign $2\xive6_pri$next[7:0]$14812 $3\xive6_pri$next[7:0]$14828 + assign $2\xive7_pri$next[7:0]$14813 $3\xive7_pri$next[7:0]$14829 + assign $2\xive8_pri$next[7:0]$14814 $3\xive8_pri$next[7:0]$14830 + assign $2\xive9_pri$next[7:0]$14815 $3\xive9_pri$next[7:0]$14831 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive0_pri$next[7:0]$14702 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive0_pri$next[7:0]$14816 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive1_pri$next[7:0]$14709 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive1_pri$next[7:0]$14823 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive2_pri$next[7:0]$14710 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive2_pri$next[7:0]$14824 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive3_pri$next[7:0]$14711 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive3_pri$next[7:0]$14825 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive4_pri$next[7:0]$14712 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive4_pri$next[7:0]$14826 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive5_pri$next[7:0]$14713 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive5_pri$next[7:0]$14827 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive6_pri$next[7:0]$14714 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive6_pri$next[7:0]$14828 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive7_pri$next[7:0]$14715 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive7_pri$next[7:0]$14829 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive8_pri$next[7:0]$14716 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive8_pri$next[7:0]$14830 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14717 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14831 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive10_pri$next[7:0]$14703 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive10_pri$next[7:0]$14817 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive11_pri$next[7:0]$14704 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive11_pri$next[7:0]$14818 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive12_pri$next[7:0]$14705 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive12_pri$next[7:0]$14819 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive13_pri$next[7:0]$14706 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive13_pri$next[7:0]$14820 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive14_pri$next[7:0]$14707 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive14_pri$next[7:0]$14821 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri - assign $3\xive15_pri$next[7:0]$14708 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive15_pri$next[7:0]$14822 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$14702 \xive0_pri - assign $3\xive10_pri$next[7:0]$14703 \xive10_pri - assign $3\xive11_pri$next[7:0]$14704 \xive11_pri - assign $3\xive12_pri$next[7:0]$14705 \xive12_pri - assign $3\xive13_pri$next[7:0]$14706 \xive13_pri - assign $3\xive14_pri$next[7:0]$14707 \xive14_pri - assign $3\xive15_pri$next[7:0]$14708 \xive15_pri - assign $3\xive1_pri$next[7:0]$14709 \xive1_pri - assign $3\xive2_pri$next[7:0]$14710 \xive2_pri - assign $3\xive3_pri$next[7:0]$14711 \xive3_pri - assign $3\xive4_pri$next[7:0]$14712 \xive4_pri - assign $3\xive5_pri$next[7:0]$14713 \xive5_pri - assign $3\xive6_pri$next[7:0]$14714 \xive6_pri - assign $3\xive7_pri$next[7:0]$14715 \xive7_pri - assign $3\xive8_pri$next[7:0]$14716 \xive8_pri - assign $3\xive9_pri$next[7:0]$14717 \xive9_pri + assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive9_pri$next[7:0]$14831 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14686 \xive0_pri - assign $2\xive10_pri$next[7:0]$14687 \xive10_pri - assign $2\xive11_pri$next[7:0]$14688 \xive11_pri - assign $2\xive12_pri$next[7:0]$14689 \xive12_pri - assign $2\xive13_pri$next[7:0]$14690 \xive13_pri - assign $2\xive14_pri$next[7:0]$14691 \xive14_pri - assign $2\xive15_pri$next[7:0]$14692 \xive15_pri - assign $2\xive1_pri$next[7:0]$14693 \xive1_pri - assign $2\xive2_pri$next[7:0]$14694 \xive2_pri - assign $2\xive3_pri$next[7:0]$14695 \xive3_pri - assign $2\xive4_pri$next[7:0]$14696 \xive4_pri - assign $2\xive5_pri$next[7:0]$14697 \xive5_pri - assign $2\xive6_pri$next[7:0]$14698 \xive6_pri - assign $2\xive7_pri$next[7:0]$14699 \xive7_pri - assign $2\xive8_pri$next[7:0]$14700 \xive8_pri - assign $2\xive9_pri$next[7:0]$14701 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14670 \xive0_pri - assign $1\xive10_pri$next[7:0]$14671 \xive10_pri - assign $1\xive11_pri$next[7:0]$14672 \xive11_pri - assign $1\xive12_pri$next[7:0]$14673 \xive12_pri - assign $1\xive13_pri$next[7:0]$14674 \xive13_pri - assign $1\xive14_pri$next[7:0]$14675 \xive14_pri - assign $1\xive15_pri$next[7:0]$14676 \xive15_pri - assign $1\xive1_pri$next[7:0]$14677 \xive1_pri - assign $1\xive2_pri$next[7:0]$14678 \xive2_pri - assign $1\xive3_pri$next[7:0]$14679 \xive3_pri - assign $1\xive4_pri$next[7:0]$14680 \xive4_pri - assign $1\xive5_pri$next[7:0]$14681 \xive5_pri - assign $1\xive6_pri$next[7:0]$14682 \xive6_pri - assign $1\xive7_pri$next[7:0]$14683 \xive7_pri - assign $1\xive8_pri$next[7:0]$14684 \xive8_pri - assign $1\xive9_pri$next[7:0]$14685 \xive9_pri + assign $2\xive0_pri$next[7:0]$14800 \xive0_pri + assign $2\xive10_pri$next[7:0]$14801 \xive10_pri + assign $2\xive11_pri$next[7:0]$14802 \xive11_pri + assign $2\xive12_pri$next[7:0]$14803 \xive12_pri + assign $2\xive13_pri$next[7:0]$14804 \xive13_pri + assign $2\xive14_pri$next[7:0]$14805 \xive14_pri + assign $2\xive15_pri$next[7:0]$14806 \xive15_pri + assign $2\xive1_pri$next[7:0]$14807 \xive1_pri + assign $2\xive2_pri$next[7:0]$14808 \xive2_pri + assign $2\xive3_pri$next[7:0]$14809 \xive3_pri + assign $2\xive4_pri$next[7:0]$14810 \xive4_pri + assign $2\xive5_pri$next[7:0]$14811 \xive5_pri + assign $2\xive6_pri$next[7:0]$14812 \xive6_pri + assign $2\xive7_pri$next[7:0]$14813 \xive7_pri + assign $2\xive8_pri$next[7:0]$14814 \xive8_pri + assign $2\xive9_pri$next[7:0]$14815 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14784 \xive0_pri + assign $1\xive10_pri$next[7:0]$14785 \xive10_pri + assign $1\xive11_pri$next[7:0]$14786 \xive11_pri + assign $1\xive12_pri$next[7:0]$14787 \xive12_pri + assign $1\xive13_pri$next[7:0]$14788 \xive13_pri + assign $1\xive14_pri$next[7:0]$14789 \xive14_pri + assign $1\xive15_pri$next[7:0]$14790 \xive15_pri + assign $1\xive1_pri$next[7:0]$14791 \xive1_pri + assign $1\xive2_pri$next[7:0]$14792 \xive2_pri + assign $1\xive3_pri$next[7:0]$14793 \xive3_pri + assign $1\xive4_pri$next[7:0]$14794 \xive4_pri + assign $1\xive5_pri$next[7:0]$14795 \xive5_pri + assign $1\xive6_pri$next[7:0]$14796 \xive6_pri + assign $1\xive7_pri$next[7:0]$14797 \xive7_pri + assign $1\xive8_pri$next[7:0]$14798 \xive8_pri + assign $1\xive9_pri$next[7:0]$14799 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -417595,66 +422253,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$14718 8'11111111 - assign $4\xive1_pri$next[7:0]$14725 8'11111111 - assign $4\xive2_pri$next[7:0]$14726 8'11111111 - assign $4\xive3_pri$next[7:0]$14727 8'11111111 - assign $4\xive4_pri$next[7:0]$14728 8'11111111 - assign $4\xive5_pri$next[7:0]$14729 8'11111111 - assign $4\xive6_pri$next[7:0]$14730 8'11111111 - assign $4\xive7_pri$next[7:0]$14731 8'11111111 - assign $4\xive8_pri$next[7:0]$14732 8'11111111 - assign $4\xive9_pri$next[7:0]$14733 8'11111111 - assign $4\xive10_pri$next[7:0]$14719 8'11111111 - assign $4\xive11_pri$next[7:0]$14720 8'11111111 - assign $4\xive12_pri$next[7:0]$14721 8'11111111 - assign $4\xive13_pri$next[7:0]$14722 8'11111111 - assign $4\xive14_pri$next[7:0]$14723 8'11111111 - assign $4\xive15_pri$next[7:0]$14724 8'11111111 + assign $4\xive0_pri$next[7:0]$14832 8'11111111 + assign $4\xive1_pri$next[7:0]$14839 8'11111111 + assign $4\xive2_pri$next[7:0]$14840 8'11111111 + assign $4\xive3_pri$next[7:0]$14841 8'11111111 + assign $4\xive4_pri$next[7:0]$14842 8'11111111 + assign $4\xive5_pri$next[7:0]$14843 8'11111111 + assign $4\xive6_pri$next[7:0]$14844 8'11111111 + assign $4\xive7_pri$next[7:0]$14845 8'11111111 + assign $4\xive8_pri$next[7:0]$14846 8'11111111 + assign $4\xive9_pri$next[7:0]$14847 8'11111111 + assign $4\xive10_pri$next[7:0]$14833 8'11111111 + assign $4\xive11_pri$next[7:0]$14834 8'11111111 + assign $4\xive12_pri$next[7:0]$14835 8'11111111 + assign $4\xive13_pri$next[7:0]$14836 8'11111111 + assign $4\xive14_pri$next[7:0]$14837 8'11111111 + assign $4\xive15_pri$next[7:0]$14838 8'11111111 case - assign $4\xive0_pri$next[7:0]$14718 $1\xive0_pri$next[7:0]$14670 - assign $4\xive10_pri$next[7:0]$14719 $1\xive10_pri$next[7:0]$14671 - assign $4\xive11_pri$next[7:0]$14720 $1\xive11_pri$next[7:0]$14672 - assign $4\xive12_pri$next[7:0]$14721 $1\xive12_pri$next[7:0]$14673 - assign $4\xive13_pri$next[7:0]$14722 $1\xive13_pri$next[7:0]$14674 - assign $4\xive14_pri$next[7:0]$14723 $1\xive14_pri$next[7:0]$14675 - assign $4\xive15_pri$next[7:0]$14724 $1\xive15_pri$next[7:0]$14676 - assign $4\xive1_pri$next[7:0]$14725 $1\xive1_pri$next[7:0]$14677 - assign $4\xive2_pri$next[7:0]$14726 $1\xive2_pri$next[7:0]$14678 - assign $4\xive3_pri$next[7:0]$14727 $1\xive3_pri$next[7:0]$14679 - assign $4\xive4_pri$next[7:0]$14728 $1\xive4_pri$next[7:0]$14680 - assign $4\xive5_pri$next[7:0]$14729 $1\xive5_pri$next[7:0]$14681 - assign $4\xive6_pri$next[7:0]$14730 $1\xive6_pri$next[7:0]$14682 - assign $4\xive7_pri$next[7:0]$14731 $1\xive7_pri$next[7:0]$14683 - assign $4\xive8_pri$next[7:0]$14732 $1\xive8_pri$next[7:0]$14684 - assign $4\xive9_pri$next[7:0]$14733 $1\xive9_pri$next[7:0]$14685 + assign $4\xive0_pri$next[7:0]$14832 $1\xive0_pri$next[7:0]$14784 + assign $4\xive10_pri$next[7:0]$14833 $1\xive10_pri$next[7:0]$14785 + assign $4\xive11_pri$next[7:0]$14834 $1\xive11_pri$next[7:0]$14786 + assign $4\xive12_pri$next[7:0]$14835 $1\xive12_pri$next[7:0]$14787 + assign $4\xive13_pri$next[7:0]$14836 $1\xive13_pri$next[7:0]$14788 + assign $4\xive14_pri$next[7:0]$14837 $1\xive14_pri$next[7:0]$14789 + assign $4\xive15_pri$next[7:0]$14838 $1\xive15_pri$next[7:0]$14790 + assign $4\xive1_pri$next[7:0]$14839 $1\xive1_pri$next[7:0]$14791 + assign $4\xive2_pri$next[7:0]$14840 $1\xive2_pri$next[7:0]$14792 + assign $4\xive3_pri$next[7:0]$14841 $1\xive3_pri$next[7:0]$14793 + assign $4\xive4_pri$next[7:0]$14842 $1\xive4_pri$next[7:0]$14794 + assign $4\xive5_pri$next[7:0]$14843 $1\xive5_pri$next[7:0]$14795 + assign $4\xive6_pri$next[7:0]$14844 $1\xive6_pri$next[7:0]$14796 + assign $4\xive7_pri$next[7:0]$14845 $1\xive7_pri$next[7:0]$14797 + assign $4\xive8_pri$next[7:0]$14846 $1\xive8_pri$next[7:0]$14798 + assign $4\xive9_pri$next[7:0]$14847 $1\xive9_pri$next[7:0]$14799 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14654 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14655 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14656 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14657 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14658 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14659 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14660 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14661 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14662 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14663 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14664 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14665 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14666 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14667 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14668 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14669 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14768 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14769 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14770 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14771 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14772 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14773 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14774 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14775 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14776 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14777 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14778 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14779 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14780 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14781 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14782 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14783 end - attribute \src "libresoc.v:197660.3-197669.6" - process $proc$libresoc.v:197660$14734 + attribute \src "libresoc.v:200696.3-200705.6" + process $proc$libresoc.v:200696$14848 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:197661.5-197661.29" + attribute \src "libresoc.v:200697.5-200697.29" switch \initial - attribute \src "libresoc.v:197661.9-197661.17" + attribute \src "libresoc.v:200697.9-200697.17" case 1'1 case end @@ -417670,14 +422328,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:197670.3-197679.6" - process $proc$libresoc.v:197670$14735 + attribute \src "libresoc.v:200706.3-200715.6" + process $proc$libresoc.v:200706$14849 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:197671.5-197671.29" + attribute \src "libresoc.v:200707.5-200707.29" switch \initial - attribute \src "libresoc.v:197671.9-197671.17" + attribute \src "libresoc.v:200707.9-200707.17" case 1'1 case end @@ -417693,14 +422351,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:197680.3-197689.6" - process $proc$libresoc.v:197680$14736 + attribute \src "libresoc.v:200716.3-200725.6" + process $proc$libresoc.v:200716$14850 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:197681.5-197681.29" + attribute \src "libresoc.v:200717.5-200717.29" switch \initial - attribute \src "libresoc.v:197681.9-197681.17" + attribute \src "libresoc.v:200717.9-200717.17" case 1'1 case end @@ -417716,14 +422374,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:197690.3-197699.6" - process $proc$libresoc.v:197690$14737 + attribute \src "libresoc.v:200726.3-200735.6" + process $proc$libresoc.v:200726$14851 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:197691.5-197691.29" + attribute \src "libresoc.v:200727.5-200727.29" switch \initial - attribute \src "libresoc.v:197691.9-197691.17" + attribute \src "libresoc.v:200727.9-200727.17" case 1'1 case end @@ -417739,14 +422397,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:197700.3-197709.6" - process $proc$libresoc.v:197700$14738 + attribute \src "libresoc.v:200736.3-200745.6" + process $proc$libresoc.v:200736$14852 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:197701.5-197701.29" + attribute \src "libresoc.v:200737.5-200737.29" switch \initial - attribute \src "libresoc.v:197701.9-197701.17" + attribute \src "libresoc.v:200737.9-200737.17" case 1'1 case end @@ -417762,14 +422420,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:197710.3-197719.6" - process $proc$libresoc.v:197710$14739 + attribute \src "libresoc.v:200746.3-200755.6" + process $proc$libresoc.v:200746$14853 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:197711.5-197711.29" + attribute \src "libresoc.v:200747.5-200747.29" switch \initial - attribute \src "libresoc.v:197711.9-197711.17" + attribute \src "libresoc.v:200747.9-200747.17" case 1'1 case end @@ -417785,14 +422443,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:197720.3-197729.6" - process $proc$libresoc.v:197720$14740 + attribute \src "libresoc.v:200756.3-200765.6" + process $proc$libresoc.v:200756$14854 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:197721.5-197721.29" + attribute \src "libresoc.v:200757.5-200757.29" switch \initial - attribute \src "libresoc.v:197721.9-197721.17" + attribute \src "libresoc.v:200757.9-200757.17" case 1'1 case end @@ -417808,14 +422466,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:197730.3-197739.6" - process $proc$libresoc.v:197730$14741 + attribute \src "libresoc.v:200766.3-200775.6" + process $proc$libresoc.v:200766$14855 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:197731.5-197731.29" + attribute \src "libresoc.v:200767.5-200767.29" switch \initial - attribute \src "libresoc.v:197731.9-197731.17" + attribute \src "libresoc.v:200767.9-200767.17" case 1'1 case end @@ -417831,14 +422489,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:197740.3-197749.6" - process $proc$libresoc.v:197740$14742 + attribute \src "libresoc.v:200776.3-200785.6" + process $proc$libresoc.v:200776$14856 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:197741.5-197741.29" + attribute \src "libresoc.v:200777.5-200777.29" switch \initial - attribute \src "libresoc.v:197741.9-197741.17" + attribute \src "libresoc.v:200777.9-200777.17" case 1'1 case end @@ -417854,14 +422512,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:197750.3-197758.6" - process $proc$libresoc.v:197750$14743 + attribute \src "libresoc.v:200786.3-200794.6" + process $proc$libresoc.v:200786$14857 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$14744 $1\int_level_l$next[15:0]$14745 - attribute \src "libresoc.v:197751.5-197751.29" + assign $0\int_level_l$next[15:0]$14858 $1\int_level_l$next[15:0]$14859 + attribute \src "libresoc.v:200787.5-200787.29" switch \initial - attribute \src "libresoc.v:197751.9-197751.17" + attribute \src "libresoc.v:200787.9-200787.17" case 1'1 case end @@ -417870,21 +422528,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$14745 16'0000000000000000 + assign $1\int_level_l$next[15:0]$14859 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$14745 \int_level_i + assign $1\int_level_l$next[15:0]$14859 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$14744 + update \int_level_l$next $0\int_level_l$next[15:0]$14858 end - attribute \src "libresoc.v:197759.3-197768.6" - process $proc$libresoc.v:197759$14746 + attribute \src "libresoc.v:200795.3-200804.6" + process $proc$libresoc.v:200795$14860 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:197760.5-197760.29" + attribute \src "libresoc.v:200796.5-200796.29" switch \initial - attribute \src "libresoc.v:197760.9-197760.17" + attribute \src "libresoc.v:200796.9-200796.17" case 1'1 case end @@ -417900,14 +422558,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:197769.3-197778.6" - process $proc$libresoc.v:197769$14747 + attribute \src "libresoc.v:200805.3-200814.6" + process $proc$libresoc.v:200805$14861 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:197770.5-197770.29" + attribute \src "libresoc.v:200806.5-200806.29" switch \initial - attribute \src "libresoc.v:197770.9-197770.17" + attribute \src "libresoc.v:200806.9-200806.17" case 1'1 case end @@ -417923,14 +422581,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:197779.3-197788.6" - process $proc$libresoc.v:197779$14748 + attribute \src "libresoc.v:200815.3-200824.6" + process $proc$libresoc.v:200815$14862 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:197780.5-197780.29" + attribute \src "libresoc.v:200816.5-200816.29" switch \initial - attribute \src "libresoc.v:197780.9-197780.17" + attribute \src "libresoc.v:200816.9-200816.17" case 1'1 case end @@ -417946,14 +422604,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:197789.3-197798.6" - process $proc$libresoc.v:197789$14749 + attribute \src "libresoc.v:200825.3-200834.6" + process $proc$libresoc.v:200825$14863 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:197790.5-197790.29" + attribute \src "libresoc.v:200826.5-200826.29" switch \initial - attribute \src "libresoc.v:197790.9-197790.17" + attribute \src "libresoc.v:200826.9-200826.17" case 1'1 case end @@ -417969,14 +422627,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:197799.3-197808.6" - process $proc$libresoc.v:197799$14750 + attribute \src "libresoc.v:200835.3-200844.6" + process $proc$libresoc.v:200835$14864 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:197800.5-197800.29" + attribute \src "libresoc.v:200836.5-200836.29" switch \initial - attribute \src "libresoc.v:197800.9-197800.17" + attribute \src "libresoc.v:200836.9-200836.17" case 1'1 case end @@ -417992,14 +422650,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:197809.3-197818.6" - process $proc$libresoc.v:197809$14751 + attribute \src "libresoc.v:200845.3-200854.6" + process $proc$libresoc.v:200845$14865 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:197810.5-197810.29" + attribute \src "libresoc.v:200846.5-200846.29" switch \initial - attribute \src "libresoc.v:197810.9-197810.17" + attribute \src "libresoc.v:200846.9-200846.17" case 1'1 case end @@ -418015,14 +422673,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:197819.3-197828.6" - process $proc$libresoc.v:197819$14752 + attribute \src "libresoc.v:200855.3-200864.6" + process $proc$libresoc.v:200855$14866 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:197820.5-197820.29" + attribute \src "libresoc.v:200856.5-200856.29" switch \initial - attribute \src "libresoc.v:197820.9-197820.17" + attribute \src "libresoc.v:200856.9-200856.17" case 1'1 case end @@ -418038,14 +422696,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:197829.3-197838.6" - process $proc$libresoc.v:197829$14753 + attribute \src "libresoc.v:200865.3-200874.6" + process $proc$libresoc.v:200865$14867 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:197830.5-197830.29" + attribute \src "libresoc.v:200866.5-200866.29" switch \initial - attribute \src "libresoc.v:197830.9-197830.17" + attribute \src "libresoc.v:200866.9-200866.17" case 1'1 case end @@ -418061,14 +422719,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:197839.3-197848.6" - process $proc$libresoc.v:197839$14754 + attribute \src "libresoc.v:200875.3-200884.6" + process $proc$libresoc.v:200875$14868 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:197840.5-197840.29" + attribute \src "libresoc.v:200876.5-200876.29" switch \initial - attribute \src "libresoc.v:197840.9-197840.17" + attribute \src "libresoc.v:200876.9-200876.17" case 1'1 case end @@ -418084,14 +422742,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:197849.3-197858.6" - process $proc$libresoc.v:197849$14755 + attribute \src "libresoc.v:200885.3-200894.6" + process $proc$libresoc.v:200885$14869 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:197850.5-197850.29" + attribute \src "libresoc.v:200886.5-200886.29" switch \initial - attribute \src "libresoc.v:197850.9-197850.17" + attribute \src "libresoc.v:200886.9-200886.17" case 1'1 case end @@ -418107,14 +422765,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:197859.3-197868.6" - process $proc$libresoc.v:197859$14756 + attribute \src "libresoc.v:200895.3-200904.6" + process $proc$libresoc.v:200895$14870 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:197860.5-197860.29" + attribute \src "libresoc.v:200896.5-200896.29" switch \initial - attribute \src "libresoc.v:197860.9-197860.17" + attribute \src "libresoc.v:200896.9-200896.17" case 1'1 case end @@ -418130,14 +422788,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:197869.3-197878.6" - process $proc$libresoc.v:197869$14757 + attribute \src "libresoc.v:200905.3-200914.6" + process $proc$libresoc.v:200905$14871 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:197870.5-197870.29" + attribute \src "libresoc.v:200906.5-200906.29" switch \initial - attribute \src "libresoc.v:197870.9-197870.17" + attribute \src "libresoc.v:200906.9-200906.17" case 1'1 case end @@ -418153,14 +422811,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:197879.3-197888.6" - process $proc$libresoc.v:197879$14758 + attribute \src "libresoc.v:200915.3-200924.6" + process $proc$libresoc.v:200915$14872 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:197880.5-197880.29" + attribute \src "libresoc.v:200916.5-200916.29" switch \initial - attribute \src "libresoc.v:197880.9-197880.17" + attribute \src "libresoc.v:200916.9-200916.17" case 1'1 case end @@ -418176,14 +422834,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:197889.3-197898.6" - process $proc$libresoc.v:197889$14759 + attribute \src "libresoc.v:200925.3-200934.6" + process $proc$libresoc.v:200925$14873 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:197890.5-197890.29" + attribute \src "libresoc.v:200926.5-200926.29" switch \initial - attribute \src "libresoc.v:197890.9-197890.17" + attribute \src "libresoc.v:200926.9-200926.17" case 1'1 case end @@ -418199,14 +422857,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:197899.3-197908.6" - process $proc$libresoc.v:197899$14760 + attribute \src "libresoc.v:200935.3-200944.6" + process $proc$libresoc.v:200935$14874 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:197900.5-197900.29" + attribute \src "libresoc.v:200936.5-200936.29" switch \initial - attribute \src "libresoc.v:197900.9-197900.17" + attribute \src "libresoc.v:200936.9-200936.17" case 1'1 case end @@ -418222,14 +422880,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:197909.3-197918.6" - process $proc$libresoc.v:197909$14761 + attribute \src "libresoc.v:200945.3-200954.6" + process $proc$libresoc.v:200945$14875 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:197910.5-197910.29" + attribute \src "libresoc.v:200946.5-200946.29" switch \initial - attribute \src "libresoc.v:197910.9-197910.17" + attribute \src "libresoc.v:200946.9-200946.17" case 1'1 case end @@ -418245,14 +422903,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:197919.3-197928.6" - process $proc$libresoc.v:197919$14762 + attribute \src "libresoc.v:200955.3-200964.6" + process $proc$libresoc.v:200955$14876 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:197920.5-197920.29" + attribute \src "libresoc.v:200956.5-200956.29" switch \initial - attribute \src "libresoc.v:197920.9-197920.17" + attribute \src "libresoc.v:200956.9-200956.17" case 1'1 case end @@ -418268,14 +422926,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:197929.3-197938.6" - process $proc$libresoc.v:197929$14763 + attribute \src "libresoc.v:200965.3-200974.6" + process $proc$libresoc.v:200965$14877 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:197930.5-197930.29" + attribute \src "libresoc.v:200966.5-200966.29" switch \initial - attribute \src "libresoc.v:197930.9-197930.17" + attribute \src "libresoc.v:200966.9-200966.17" case 1'1 case end @@ -418291,14 +422949,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:197939.3-197948.6" - process $proc$libresoc.v:197939$14764 + attribute \src "libresoc.v:200975.3-200984.6" + process $proc$libresoc.v:200975$14878 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:197940.5-197940.29" + attribute \src "libresoc.v:200976.5-200976.29" switch \initial - attribute \src "libresoc.v:197940.9-197940.17" + attribute \src "libresoc.v:200976.9-200976.17" case 1'1 case end @@ -418314,14 +422972,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:197949.3-197958.6" - process $proc$libresoc.v:197949$14765 + attribute \src "libresoc.v:200985.3-200994.6" + process $proc$libresoc.v:200985$14879 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:197950.5-197950.29" + attribute \src "libresoc.v:200986.5-200986.29" switch \initial - attribute \src "libresoc.v:197950.9-197950.17" + attribute \src "libresoc.v:200986.9-200986.17" case 1'1 case end @@ -418337,14 +422995,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:197959.3-198008.6" - process $proc$libresoc.v:197959$14766 + attribute \src "libresoc.v:200995.3-201044.6" + process $proc$libresoc.v:200995$14880 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:197960.5-197960.29" + attribute \src "libresoc.v:200996.5-200996.29" switch \initial - attribute \src "libresoc.v:197960.9-197960.17" + attribute \src "libresoc.v:200996.9-200996.17" case 1'1 case end @@ -418437,14 +423095,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:198009.3-198018.6" - process $proc$libresoc.v:198009$14767 + attribute \src "libresoc.v:201045.3-201054.6" + process $proc$libresoc.v:201045$14881 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:198010.5-198010.29" + attribute \src "libresoc.v:201046.5-201046.29" switch \initial - attribute \src "libresoc.v:198010.9-198010.17" + attribute \src "libresoc.v:201046.9-201046.17" case 1'1 case end @@ -418460,14 +423118,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:198019.3-198028.6" - process $proc$libresoc.v:198019$14768 + attribute \src "libresoc.v:201055.3-201064.6" + process $proc$libresoc.v:201055$14882 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:198020.5-198020.29" + attribute \src "libresoc.v:201056.5-201056.29" switch \initial - attribute \src "libresoc.v:198020.9-198020.17" + attribute \src "libresoc.v:201056.9-201056.17" case 1'1 case end @@ -418483,14 +423141,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:198029.3-198038.6" - process $proc$libresoc.v:198029$14769 + attribute \src "libresoc.v:201065.3-201074.6" + process $proc$libresoc.v:201065$14883 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:198030.5-198030.29" + attribute \src "libresoc.v:201066.5-201066.29" switch \initial - attribute \src "libresoc.v:198030.9-198030.17" + attribute \src "libresoc.v:201066.9-201066.17" case 1'1 case end @@ -418506,14 +423164,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:198039.3-198048.6" - process $proc$libresoc.v:198039$14770 + attribute \src "libresoc.v:201075.3-201084.6" + process $proc$libresoc.v:201075$14884 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:198040.5-198040.29" + attribute \src "libresoc.v:201076.5-201076.29" switch \initial - attribute \src "libresoc.v:198040.9-198040.17" + attribute \src "libresoc.v:201076.9-201076.17" case 1'1 case end @@ -418529,14 +423187,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:198049.3-198057.6" - process $proc$libresoc.v:198049$14771 + attribute \src "libresoc.v:201085.3-201093.6" + process $proc$libresoc.v:201085$14885 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$14772 $1\ics_wb__dat_r$next[31:0]$14773 - attribute \src "libresoc.v:198050.5-198050.29" + assign $0\ics_wb__dat_r$next[31:0]$14886 $1\ics_wb__dat_r$next[31:0]$14887 + attribute \src "libresoc.v:201086.5-201086.29" switch \initial - attribute \src "libresoc.v:198050.9-198050.17" + attribute \src "libresoc.v:201086.9-201086.17" case 1'1 case end @@ -418545,21 +423203,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$14773 0 + assign $1\ics_wb__dat_r$next[31:0]$14887 0 case - assign $1\ics_wb__dat_r$next[31:0]$14773 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$14887 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14772 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14886 end - attribute \src "libresoc.v:198058.3-198066.6" - process $proc$libresoc.v:198058$14774 + attribute \src "libresoc.v:201094.3-201102.6" + process $proc$libresoc.v:201094$14888 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$14775 $1\ics_wb__ack$next[0:0]$14776 - attribute \src "libresoc.v:198059.5-198059.29" + assign $0\ics_wb__ack$next[0:0]$14889 $1\ics_wb__ack$next[0:0]$14890 + attribute \src "libresoc.v:201095.5-201095.29" switch \initial - attribute \src "libresoc.v:198059.9-198059.17" + attribute \src "libresoc.v:201095.9-201095.17" case 1'1 case end @@ -418568,116 +423226,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$14776 1'0 - case - assign $1\ics_wb__ack$next[0:0]$14776 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14775 - end - connect \$7 $ternary$libresoc.v:197429$14529_Y - connect \$99 $lt$libresoc.v:197430$14530_Y - connect \$101 $and$libresoc.v:197431$14531_Y - connect \$103 $lt$libresoc.v:197432$14532_Y - connect \$105 $and$libresoc.v:197433$14533_Y - connect \$107 $lt$libresoc.v:197434$14534_Y - connect \$109 $and$libresoc.v:197435$14535_Y - connect \$111 $lt$libresoc.v:197436$14536_Y - connect \$113 $and$libresoc.v:197437$14537_Y - connect \$115 $lt$libresoc.v:197438$14538_Y - connect \$117 $and$libresoc.v:197439$14539_Y - connect \$119 $lt$libresoc.v:197440$14540_Y - connect \$121 $and$libresoc.v:197441$14541_Y - connect \$123 $lt$libresoc.v:197442$14542_Y - connect \$125 $and$libresoc.v:197443$14543_Y - connect \$127 $lt$libresoc.v:197444$14544_Y - connect \$12 $eq$libresoc.v:197445$14545_Y - connect \$129 $and$libresoc.v:197446$14546_Y - connect \$131 $lt$libresoc.v:197447$14547_Y - connect \$133 $and$libresoc.v:197448$14548_Y - connect \$135 $lt$libresoc.v:197449$14549_Y - connect \$137 $and$libresoc.v:197450$14550_Y - connect \$11 $ternary$libresoc.v:197451$14551_Y - connect \$139 $lt$libresoc.v:197452$14552_Y - connect \$141 $and$libresoc.v:197453$14553_Y - connect \$143 $lt$libresoc.v:197454$14554_Y - connect \$145 $and$libresoc.v:197455$14555_Y - connect \$147 $lt$libresoc.v:197456$14556_Y - connect \$149 $and$libresoc.v:197457$14557_Y - connect \$151 $lt$libresoc.v:197458$14558_Y - connect \$153 $and$libresoc.v:197459$14559_Y - connect \$155 $lt$libresoc.v:197460$14560_Y - connect \$157 $and$libresoc.v:197461$14561_Y - connect \$159 $lt$libresoc.v:197462$14562_Y - connect \$161 $and$libresoc.v:197463$14563_Y - connect \$163 $lt$libresoc.v:197464$14564_Y - connect \$165 $and$libresoc.v:197465$14565_Y - connect \$167 $lt$libresoc.v:197466$14566_Y - connect \$16 $eq$libresoc.v:197467$14567_Y - connect \$169 $and$libresoc.v:197468$14568_Y - connect \$171 $lt$libresoc.v:197469$14569_Y - connect \$173 $and$libresoc.v:197470$14570_Y - connect \$175 $lt$libresoc.v:197471$14571_Y - connect \$177 $and$libresoc.v:197472$14572_Y - connect \$15 $ternary$libresoc.v:197473$14573_Y - connect \$179 $lt$libresoc.v:197474$14574_Y - connect \$181 $and$libresoc.v:197475$14575_Y - connect \$183 $lt$libresoc.v:197476$14576_Y - connect \$185 $and$libresoc.v:197477$14577_Y - connect \$187 $lt$libresoc.v:197478$14578_Y - connect \$189 $and$libresoc.v:197479$14579_Y - connect \$191 $lt$libresoc.v:197480$14580_Y - connect \$193 $and$libresoc.v:197481$14581_Y - connect \$195 $lt$libresoc.v:197482$14582_Y - connect \$197 $and$libresoc.v:197483$14583_Y - connect \$1 $eq$libresoc.v:197484$14584_Y - connect \$199 $lt$libresoc.v:197485$14585_Y - connect \$201 $and$libresoc.v:197486$14586_Y - connect \$204 $eq$libresoc.v:197487$14587_Y - connect \$203 $ternary$libresoc.v:197488$14588_Y - connect \$20 $eq$libresoc.v:197489$14589_Y - connect \$19 $ternary$libresoc.v:197490$14590_Y - connect \$24 $eq$libresoc.v:197491$14591_Y - connect \$23 $ternary$libresoc.v:197492$14592_Y - connect \$28 $eq$libresoc.v:197493$14593_Y - connect \$27 $ternary$libresoc.v:197494$14594_Y - connect \$32 $eq$libresoc.v:197495$14595_Y - connect \$31 $ternary$libresoc.v:197496$14596_Y - connect \$36 $eq$libresoc.v:197497$14597_Y - connect \$35 $ternary$libresoc.v:197498$14598_Y - connect \$3 $eq$libresoc.v:197499$14599_Y - connect \$40 $eq$libresoc.v:197500$14600_Y - connect \$39 $ternary$libresoc.v:197501$14601_Y - connect \$44 $eq$libresoc.v:197502$14602_Y - connect \$43 $ternary$libresoc.v:197503$14603_Y - connect \$48 $eq$libresoc.v:197504$14604_Y - connect \$47 $ternary$libresoc.v:197505$14605_Y - connect \$52 $eq$libresoc.v:197506$14606_Y - connect \$51 $ternary$libresoc.v:197507$14607_Y - connect \$56 $eq$libresoc.v:197508$14608_Y - connect \$55 $ternary$libresoc.v:197509$14609_Y - connect \$5 $and$libresoc.v:197510$14610_Y - connect \$60 $eq$libresoc.v:197511$14611_Y - connect \$59 $ternary$libresoc.v:197512$14612_Y - connect \$64 $eq$libresoc.v:197513$14613_Y - connect \$63 $ternary$libresoc.v:197514$14614_Y - connect \$68 $eq$libresoc.v:197515$14615_Y - connect \$67 $ternary$libresoc.v:197516$14616_Y - connect \$71 $shr$libresoc.v:197517$14617_Y [0] - connect \$73 $and$libresoc.v:197518$14618_Y - connect \$75 $lt$libresoc.v:197519$14619_Y - connect \$77 $and$libresoc.v:197520$14620_Y - connect \$79 $lt$libresoc.v:197521$14621_Y - connect \$81 $and$libresoc.v:197522$14622_Y - connect \$83 $lt$libresoc.v:197523$14623_Y - connect \$85 $and$libresoc.v:197524$14624_Y - connect \$87 $lt$libresoc.v:197525$14625_Y - connect \$8 $eq$libresoc.v:197526$14626_Y - connect \$89 $and$libresoc.v:197527$14627_Y - connect \$91 $lt$libresoc.v:197528$14628_Y - connect \$93 $and$libresoc.v:197529$14629_Y - connect \$95 $lt$libresoc.v:197530$14630_Y - connect \$97 $and$libresoc.v:197531$14631_Y + assign $1\ics_wb__ack$next[0:0]$14890 1'0 + case + assign $1\ics_wb__ack$next[0:0]$14890 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14889 + end + connect \$7 $ternary$libresoc.v:200465$14643_Y + connect \$99 $lt$libresoc.v:200466$14644_Y + connect \$101 $and$libresoc.v:200467$14645_Y + connect \$103 $lt$libresoc.v:200468$14646_Y + connect \$105 $and$libresoc.v:200469$14647_Y + connect \$107 $lt$libresoc.v:200470$14648_Y + connect \$109 $and$libresoc.v:200471$14649_Y + connect \$111 $lt$libresoc.v:200472$14650_Y + connect \$113 $and$libresoc.v:200473$14651_Y + connect \$115 $lt$libresoc.v:200474$14652_Y + connect \$117 $and$libresoc.v:200475$14653_Y + connect \$119 $lt$libresoc.v:200476$14654_Y + connect \$121 $and$libresoc.v:200477$14655_Y + connect \$123 $lt$libresoc.v:200478$14656_Y + connect \$125 $and$libresoc.v:200479$14657_Y + connect \$127 $lt$libresoc.v:200480$14658_Y + connect \$12 $eq$libresoc.v:200481$14659_Y + connect \$129 $and$libresoc.v:200482$14660_Y + connect \$131 $lt$libresoc.v:200483$14661_Y + connect \$133 $and$libresoc.v:200484$14662_Y + connect \$135 $lt$libresoc.v:200485$14663_Y + connect \$137 $and$libresoc.v:200486$14664_Y + connect \$11 $ternary$libresoc.v:200487$14665_Y + connect \$139 $lt$libresoc.v:200488$14666_Y + connect \$141 $and$libresoc.v:200489$14667_Y + connect \$143 $lt$libresoc.v:200490$14668_Y + connect \$145 $and$libresoc.v:200491$14669_Y + connect \$147 $lt$libresoc.v:200492$14670_Y + connect \$149 $and$libresoc.v:200493$14671_Y + connect \$151 $lt$libresoc.v:200494$14672_Y + connect \$153 $and$libresoc.v:200495$14673_Y + connect \$155 $lt$libresoc.v:200496$14674_Y + connect \$157 $and$libresoc.v:200497$14675_Y + connect \$159 $lt$libresoc.v:200498$14676_Y + connect \$161 $and$libresoc.v:200499$14677_Y + connect \$163 $lt$libresoc.v:200500$14678_Y + connect \$165 $and$libresoc.v:200501$14679_Y + connect \$167 $lt$libresoc.v:200502$14680_Y + connect \$16 $eq$libresoc.v:200503$14681_Y + connect \$169 $and$libresoc.v:200504$14682_Y + connect \$171 $lt$libresoc.v:200505$14683_Y + connect \$173 $and$libresoc.v:200506$14684_Y + connect \$175 $lt$libresoc.v:200507$14685_Y + connect \$177 $and$libresoc.v:200508$14686_Y + connect \$15 $ternary$libresoc.v:200509$14687_Y + connect \$179 $lt$libresoc.v:200510$14688_Y + connect \$181 $and$libresoc.v:200511$14689_Y + connect \$183 $lt$libresoc.v:200512$14690_Y + connect \$185 $and$libresoc.v:200513$14691_Y + connect \$187 $lt$libresoc.v:200514$14692_Y + connect \$189 $and$libresoc.v:200515$14693_Y + connect \$191 $lt$libresoc.v:200516$14694_Y + connect \$193 $and$libresoc.v:200517$14695_Y + connect \$195 $lt$libresoc.v:200518$14696_Y + connect \$197 $and$libresoc.v:200519$14697_Y + connect \$1 $eq$libresoc.v:200520$14698_Y + connect \$199 $lt$libresoc.v:200521$14699_Y + connect \$201 $and$libresoc.v:200522$14700_Y + connect \$204 $eq$libresoc.v:200523$14701_Y + connect \$203 $ternary$libresoc.v:200524$14702_Y + connect \$20 $eq$libresoc.v:200525$14703_Y + connect \$19 $ternary$libresoc.v:200526$14704_Y + connect \$24 $eq$libresoc.v:200527$14705_Y + connect \$23 $ternary$libresoc.v:200528$14706_Y + connect \$28 $eq$libresoc.v:200529$14707_Y + connect \$27 $ternary$libresoc.v:200530$14708_Y + connect \$32 $eq$libresoc.v:200531$14709_Y + connect \$31 $ternary$libresoc.v:200532$14710_Y + connect \$36 $eq$libresoc.v:200533$14711_Y + connect \$35 $ternary$libresoc.v:200534$14712_Y + connect \$3 $eq$libresoc.v:200535$14713_Y + connect \$40 $eq$libresoc.v:200536$14714_Y + connect \$39 $ternary$libresoc.v:200537$14715_Y + connect \$44 $eq$libresoc.v:200538$14716_Y + connect \$43 $ternary$libresoc.v:200539$14717_Y + connect \$48 $eq$libresoc.v:200540$14718_Y + connect \$47 $ternary$libresoc.v:200541$14719_Y + connect \$52 $eq$libresoc.v:200542$14720_Y + connect \$51 $ternary$libresoc.v:200543$14721_Y + connect \$56 $eq$libresoc.v:200544$14722_Y + connect \$55 $ternary$libresoc.v:200545$14723_Y + connect \$5 $and$libresoc.v:200546$14724_Y + connect \$60 $eq$libresoc.v:200547$14725_Y + connect \$59 $ternary$libresoc.v:200548$14726_Y + connect \$64 $eq$libresoc.v:200549$14727_Y + connect \$63 $ternary$libresoc.v:200550$14728_Y + connect \$68 $eq$libresoc.v:200551$14729_Y + connect \$67 $ternary$libresoc.v:200552$14730_Y + connect \$71 $shr$libresoc.v:200553$14731_Y [0] + connect \$73 $and$libresoc.v:200554$14732_Y + connect \$75 $lt$libresoc.v:200555$14733_Y + connect \$77 $and$libresoc.v:200556$14734_Y + connect \$79 $lt$libresoc.v:200557$14735_Y + connect \$81 $and$libresoc.v:200558$14736_Y + connect \$83 $lt$libresoc.v:200559$14737_Y + connect \$85 $and$libresoc.v:200560$14738_Y + connect \$87 $lt$libresoc.v:200561$14739_Y + connect \$8 $eq$libresoc.v:200562$14740_Y + connect \$89 $and$libresoc.v:200563$14741_Y + connect \$91 $lt$libresoc.v:200564$14742_Y + connect \$93 $and$libresoc.v:200565$14743_Y + connect \$95 $lt$libresoc.v:200566$14744_Y + connect \$97 $and$libresoc.v:200567$14745_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 -- 2.30.2